Word Pro - HM ISA-GPIB-PC2A.lwp
Contents
1. IR Interrupt clear bit Table 3 4 below is an example of the actual physical register addresses for a ISA GPIB PC2A board Base Address of 02E1 3 4 ISA GPIB PC2A NI PCIIA REGISTERS Table 3 4 Physical Register Addresses for Board Base Address 02E1 ADDRESS WRITE READ 02E1 Byte out register Byte In register O6EI Interrupt Mask 1 register Interrupt Status 1 register OAEI Interrupt Mask 2 register Interrupt Status 2 register OEE1 Serial Poll Mode register Serial Poll Status register 12E1 Address Mode register Address Status register 16E1 Auxiliary Mode register Command Pass through register IAE Address Register 0 1 Address 0 register 1EE1 End Of String register Address 1 register 10 3 5 CONVERTING PCI DRIVERS FOR THE ISA GPIB PC2A If you are working with your own PCII driver converting it for the ISA GPIB PC2A is an easy task The register functions of the PCII and ISA GPIB PC2A NI PCIIA are identical the addressing is very different Refer to the prior descriptions to learn how different If you have hard coded all the addresses into your driver converting your driver to work with both the PCII and ISA GPIB PC2A will require that you replace all the hard coded addresses with variables If you have referenced all other addresses as an offset from the base address such as IN Base 4 or OUT Base 7 you will have to replace each such reference with variable names Table 3 5 is a list of p2. 7 REGOFFSET 12 For your notes 13 For your notes 14 EC Declaration of Conformity We Measurement Computing Corporation declare under sole responsibility that the product ISA GPIB PC2A GPIB Interface board Part Number Description to which this declaration relates meets the essential requirements is in conformity with and CE marking has been applied according to the relevant EC Directives listed below using the relevant section of the following EC standards and other normative documents EU EMC Directive 89 336 EEC Essential requirements relating to electromagnetic compatibility EU 55022 Class B Limits and methods of measurements of radio interference characteristics of information technology equipment EN 50082 1 EC generic immunity requirements IEC 801 2 Electrostatic discharge requirements for industrial process measurement and control equipment IEC 801 3 Radiated electromagnetic field requirements for industrial process measurements and control equipment IEC 801 4 Electrically fast transients for industrial process measurement and control equipment Carl Haapaoja Director of Quality Assurance Measurement Computing Corporation 16 Commerce Boulevard Middleboro Massachusetts 02346 508 946 5100 Fax 508 946 9500 E mail info measurementcomputing com www measurementcomputing com
3. C Figure 1 2 GPIB Linear Connection Configuration Star Connection Configuration Instrument D Instrument A Instrument C Instrument E Figure 1 3 GPIB Star Connection Configuration 2 INSTALLATION 2 1 BOARDLAYOUT The ISA GPIB PC2A has one bank of switches and three jumper blocks which must be set before installing the board in your computer COMPUTERBOARDS INC L C Wait State Generator Selection Base Address Selection Interrupt Selection DMA Channel Selection ISA GPIB PC2A Switch positions and functions are identical to those on the NI PCIIA Figure 2 1 Board Switch and Jumper Locations 2 2 BASE ADDRESS The base address of the ISA GPIB PC2A is set with the two switches labeled 14 and 13 Only four possible base addresses are available In addition there is considerable rollover or addresses which are not deselected by the address enable circuitry of the ISA GPIB PC2A The default address chosen by National Instruments for the PCIIA was 02E1h so that 1s the default setting for the ISA GPIB PC2A Unlike most other I O boards the National Instrument PCIA uses nonconsecutive I O addresses and the ISA GPIB PC2A does the same to maintain compatibility 0 The ISA GPIB PC2A I O address is selected using only the two lowest switches on the 5 positio
4. A WAIT STATE amp DMA SELECT Figure 2 4 Wait State and DMA Select Jumpers On PC XT class machines the hard disk controller usually occupies DMA level 3 and the floppy disk controller usually occupies level 2 Neither level 2 nor 3 are a good choice of DMA level on a PC XT equipped with a floppy and hard disk On PC AT 386 class computers both DMA channels 1 and 3 are available 3 REGISTER MAPS 3 1 ADDRESS DECODING There are only four possible base addresses which can be selected using the switches on the ISA GPIB PC2A Those four base addresses are shown below in bold type For a given base address the ISA GPIB PC2A registers appear at eight additional addresses within the personal computer s I O address space Table 3 1 Board Base Addressing 02E1 06E1 OAEI OEEI 22E1 26El 2AEI 2EEI 12E1 16E1 IAEI 1EE1 32El 36El 3AEI 3EEl 42E146El1 4AEI 4EEl 62E1 66El 6AEI 6EEI S2El 56E1 S5SAEI SEEI 72El 76El TAEI 7EEl If the addressing scheme in the table above appears confusing and unconventional we agree it is The addressing of the ISA GPIB PC2A is easiest to understand in relation to National s PCH board NI PCIIA Here are the addresses of the PCII board 3 2 NI PCI REGISTERS NOT ISA GPIB PC2A Table 3 2 NI PCII Registers ADDRESS WRITE READ Base 0 Byte out register Byte In register Base 1 Interrupt Mask 1 register Interrupt Status 1 register Base 2 Interrupt Mask 2 register Interrupt Status 2 r
5. C AT Interrupt 4 Selected 234567 1 0 o 2 000 0 Interrupt 6 Selected Interrupt 7 Selected Factory Default for PC AT 234567 e e e ojojo 4 2 UH a tt B The six possible switch settings and jumper locations for each of the interrupts 2 to 7 Figure 2 3 Interrupt Switch and Jumper Settings National Instruments chose interrupt level 7 IRQ7 as the default for the PCIIA Your ISA GPIB PC2A is configured at the factory for IRQ7 Although IRQ7 is acceptable that interrupt is reserved for the LPT1 printer device A better choice is IRQ5 on most machines 2 4 WAIT STATE JUMPER amp DMA JUMPERS The ISA GPIB PC2A boards have a wait state jumper which enables an onboard wait state generator A wait state is an extra delay injected into the processor s clock via the bus This delay slows down the processor so that signals from slow devices chips will be valid You will probably not need a wait state since the I O bus is slowed down on even the fastest PCs The default is no wait state selected The ISA GPIB PC2A can use DMA levels 1 2 3 or none The factory default is level 1 e je e le eje Wait State Disabled Wait State Enabled 1 d 2 3 3 22 3 8 00090 009090 00090 00090 DMA Channel 1 DMA Channel 3 112 233 1122 33 e o oo 0000090 e o 090 0000090 DMA Channel 2 No DMA Channel Selected ISA GPIB PC2
6. ISA GPIB PC2A User s Manual A IMEASUREMENT COMPUTING Revision 5 November 2000 MEGA FIFO the CIO prefix to data acquisition board model numbers the PCM prefix to data acquisition board model numbers PCM DAS08 PCM D24C3 PCM DAC02 PCM COM422 PCM COM485 PCM DMM PCM DAS16D 12 PCM DAS16S 12 PCM DAS16D 16 PCM DAS16S 16 PCI DAS6402 16 Universal Library InstaCal Harsh Environment Warranty and Measurement Computing Corporation are registered trademarks of Measurement Computing Corporation IBM PC and PC AT are trademarks of International Business Machines Corp Windows is a trademark of Microsoft Corp All other trademarks are the property of their respective owners Information furnished by Measurement Computing Corp is believed to be accurate and reliable However no responsibility is assumed by Measurement Computing Corporation neither for its use nor for any infringements of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or copyrights of Measurement Computing Corporation All rights reserved No part of this publication may be reproduced stored in a retrieval system or transmitted in any form by any means electronic mechanical by photocopying recording or otherwise without the prior written permission of Measurement Computing Corporation Notice Measurement Computing Corporation does not authorize any Measureme
7. JUMPER amp DMA JUMPERS sees 8 3 REGISTER MAPS 0 ccc eee hh n 9 3 1 ADDRESS DECODING esee eee 9 3 2 NI PCI REGISTERS NOT ISA GPIB PC2A eese 9 3 3 ISA GPIB PC2A NI PCIA REGISTERS 0004 10 3 4 ISA GPIB PC2A NI PCIA REGISTERS ss eeeees s 10 3 5 CONVERTING PCII DRIVERS FOR THEISA GPIB PC2A 11 This is a blank page 1 INTRODUCTION The ISA GPIB PC2A is a 100 compatible replacement for the National Instruments PCH PCHA and all other GPIB interfaces which are register and functionally compatible with them To set up the ISA GPIB PC2A set the switches and jumpers on the board to match the configuration of the GPIB interface board and software you currently use 1 1 NATIONAL INSTRUMENTS PCI amp PCIA OWNERS The ISA GPIB PC2A is easy to use if you are familiar with the National Instruments Inc PCIIA GPIB interface board All of the ISA GPIB PC2A switches and jumpers are in the same location and have the same function as the PCIIA If you are using the National Instruments PCII board you will find that the switches and jumpers are in a different location although the functions of the switches and jumpers on the NI PCII and PCIIA are nearly identical Because the ISA GPIB PC2A is designed to be 100 compatible with the NI PCHA from the connector to the registers and to look similar as well references to the NI PCIIA board in thi
8. egister Base 3 Serial Poll Mode register Serial Poll Status register Base 4 Address Mode register Address Status register Base 5 Auxiliary Mode register Command Pass through register Base 6 Address Register 0 1 Address 0 register Base 7 End Of String register Address 1 register The addressing of the PCII is easy to understand A Base Address Switch selects the boards Base Address and the register functions on the board occupy consecutive I O addresses Eight of them in total Complete descriptions of each register and it s functions follow in a later section Back to the ISA GPIB PC2A NI PCIIA The registers on the ISA GPIB PC2A are the same as those of the NI PCIIA shown below The logic of the address decoding is very different The eight registers are not consecutive The registers are offset by 400h between each register 3 3 ISA GPIB PC2A NI PCIIA REGISTERS Table 3 3 ISA GPIB PC2A NI PCIIA Registers ADDRESS WRITE READ Base 40 Byte out register Byte In register Base 400 Interrupt Mask 1 register Interrupt Status 1 register Base 800 Interrupt Mask 2 register Interrupt Status 2 register Base C00 Serial Poll Mode register Serial Poll Status register Base 1000 Address Mode register Address Status register Base 1400 Auxiliary Mode register Command Pass through register Base 1800 Address Register 0 1 Address 0 register Base 1C00 End Of String register Address 1 register 2F0
9. ener accepts data from a Talker and a Controller manages the flow of information over the bus A GPIB Digital Voltmeter is acting as a Listener as its input configurations and ranges are set and then as a Talker when it actually sends its readings to the computer The Controller is in charge of all communications over the bus The Controller s job is to make sure only one device tries to talk at a time and make sure the correct Listeners are paying attention when the Talker talks Each GPIB system has a single system controller The system controller is ultimately in charge of the bus and is in control as the bus is powered up There can be more than one Controller on the bus and the System Controller can pass active control to another controller capable device though only one can be Controller In Charge at a given time The GPIB board is usually designated as the System Controller 1 3 2 GPIB Electrical Signal Configuration The GPIB is an 8 bit parallel data transfer bus In addition to the eight data bits the bus carries three handshaking lines and five GPIB specific management and control lines The remainder of the standard 24 pin GPIB cable is used for the cable shield signal grounds and returns The GPIB connector pin out is shown in Figure 1 1 below DIO1 1 13 DIO5 DIO2 2 14 DIO6 DIO3 3 15 DIO7 DIO4 4 16 DIO8 EOI 5 17 REN DA 6 18 GND Twisted Pair with DAV NRFD 7 19 GND Twisted Pair with NRFD NDAC 8 20 GND Twisted Pair wit
10. h NDAC IFC 9 21 GND Twisted Pair with IFC SRQ 10 22 GND Twisted Pair with SRQ ATN 11 23 GND Twisted Pair with ATN SHIELD 12 24 SIGNAL GROUND GPIB Pinout as viewed looking into connector on ISA GPIB PC2A Figure 1 1 ISA GPIB PC2A Connector Pin Out 2 1 3 3 Data Lines DIO1 through DIOS are the data transfer bits Most GPIB systems send 7 bit data and use the eight bit as a parity or disregard it entirely 1 3 4 Handshaking Lines There are three handshaking lines that control the data transfer between devices NRFD Not Ready For Data this bit is used to indicate the readiness or lack thereof of a device to accept data DAV Data Valid bit is used to indicate to receiving devices that data has been placed on the bus and is available to read e NDAC Not Data Accepted is asserted by the receiving device to indicate that data has been read and may now be removed from the bus 1 3 5 System Management Lines e ATN Attention is used by the controller to specify how data on the DIO lines is interpreted and which devices must respond to the data e IFC Interface Clear is used by the system controller to place the entire system in a known quiescent Cleared state and to assert itself as Controller In Charge CIC SRQ Service Request is used by a device on the bus to indicate the need for attention and requests an interrupt of the current event sequence REN Remote Enable is used by the controller i
11. n DIP switch 14 The upper three switches are interrupt select switched 13 BASE ADDRESS 02EI Both switches to the right M 52 Base Address 02E1 Base Address 22E1 Base Address 42E1 Base Address 62E1 ISA GPIB PC2A BASE ADDRESS SWITCH Figure 2 2 Base Address Switches Following are the tables of addresses also used for a given setting Be sure that any other I O boards installed in your computer do not use one of these addresses 02E1 06E1 OAEI OEEI 22E1 26El 2AEI 2EEI 12E1 16E1 IAEI IEEI 32E1 36El 3AEl 3EEl 42E1 46E1 AAEI AEBEI 62E1 66El 6AEI 6EEI S2El 56E1 S5SAEI SEEI 72El 76El TAEI 7EEl The ISA GPIB PC2A uses eight I O Addresses 2 3 INTERRUPT LEVEL SELECT The interrupt used by the ISA GPIB PC2A is set with three switches a jumper and your software All three must match or interrupts will not function properly The following table shows switch settings and jumper locations for each of the six possible interrupts 2 to 7 0 1 ISA GPIB PC2A Interrupt logic is controlled by a combination of 2 Switched O 1 amp 2 and the interrupt jumper 14 13 Switches 13 and 14 the lower two select the base address 23456 7 BENE 23456 7 Bez vty 0 2 Interrupt 2 Selected Interrupt 3 Selected E 0 23456 7 0 234567 1 ee o 1 e e e ej e e 2 Desa E ze 0 1 thy Interrupt 5 Selected Best for P
12. n conjunction with other messages to place a device on the bus into either remote or local mode EOI End or Identify Is used by Talkers to indicate the end of a message string or is used by the Controller to command a polling sequence 1 4 CONNECTION CONFIGURATIONS The GPIB specification is quite definitive regarding the number of devices and cable lengths allowed in a GPIB system There can be no more than 15 devices on a single contiguous GPIB bus Larger systems are possible by installing additional GPIB interface boards in your computer The maximum total length of all cables on a single GPIB system is 20 meters In addition cable length between consecutive devices must be no greater than four meters and average cable length must be two meters or less Stated another way the total cable length in meters in the system cannot be longer than two times the number of devices up to 20 meters Longer length systems are possible but only with the use of a GPIB extender card In addition to the above rules at least two thirds of all devices on the bus should be powered on for proper operation Keeping the above constraints in mind there is no limitation on the actual connection scheme used to connect the GPIB devices together Star Linear or any combination of both may be used These are shown in Figures 1 2 and 1 3 below Linear Connection Configuration Instrument D Instrument
13. nt Computing Corporation product for use in life support systems and or devices without the written approval of the President of Measurement Computing Corporation Life support devices systems are devices or systems which a are intended for surgical implantation into the body or b support or sustain life and whose failure to perform can be reasonably expected to result in injury Measurement Computing Corp products are not designed with the components required and are not subject to the testing required to ensure a level of reliability suitable for the treatment and diagnosis of people C Copyright 2000 Measurement Computing Corporation HM ISA GPIB PC2A lwp TABLE OF CONTENTS I INTRODUCTION zn ee reg a e RA pae es 1 1 1 NATIONAL INSTRUMENTS PCH amp PCIA OWNERS 1 1 2 GPIB HISTORY ente Pe EARS BO POOR OA ip ere E ER 1 1 3 GPIB SYSTEM DESCRIPTION 0 0 0 00 eee eee e 2 1 3 1 Talkers Listeners and Controllers 0 0 0c cece eee 2 1 3 2 GPIB Electrical Signal Configuration 00 2 1 3 3 Data Lines 4 24 re i a e i ded 3 1 3 4 Handshaking Lines 3 1 3 5 System Management Lines lesleeeeeee eee 3 1 4 CONNECTION CONFIGURATIONS 0 0 0 0 ee eee eee 3 ZINSTALLATION iii E nie Be Kain be os 5 2 BOARD LAYOUT 2 2 22er tee th Bae Bae 5 2 2 BASE ADDRESS eR Regem eere e ER ade A 5 2 3 INTERRUPT LEVEL SELECT eese 6 2 4 WAIT STATE
14. roposed variable names Table 3 5 Proposed ISA GPIB PC2A Registers Mnemonics ADDRESS WRITE READ Base 0 BOR Byte Out BIR Byte In Base 400 IRM1 Interrupt Mask 1 IRS1 Interrupt Status 1 Base 800 IRM2 Interrupt Mask 2 IRS2 Interrupt Status 2 Base C00 SPM Serial Poll Mode SPS Serial Poll Status Base 1000 ADM Address Mode ASR Address Status Base 1400 AMR Auxiliary Mode CPT Command Pass through Base 1800 A01 Address 0 1 AOR Address O Base 1C00 EOS End Of String AIR Address 1 2F0 IR Interrupt clear bit After all the register functions have unique variable names and all IN and OUT statements reference the variable names and not a hard address or merely an offset from the base address you can implement the following code to fix the addresses in the variable for PCI or ISA GPIB PC2A boards BASEADR 02E1 If PCII then REGOFFSET 1 If PC2A then REGOFFSET 400h REGOFFSET 400h Write registers BOR BASEADR 0 REGOFFSET IRM1 BASEADR 1 REGOFFSET IRM2 BASEADR 2 REGOFFSET SPM BASEADR 3 REGOFFSET ADM BASEADR 4 REGOFFSET AMR BASEADR 5 REGOFFSET A01 BASEADR 6 REGOFFSET EOS BASEADR 7 REGOFFSET 11 BIR IRS1 IRS2 SPS ASR CPT AOR AiR Read registers BASEADR 0 REGOFFSET BASEADR 1 REGOFFSET BASEADR 2 REGOFFSET BASEADR 3 REGOFFSET BASEADR 4 REGOFFSET BASEADR 5 REGOFFSET BASEADR 6 REGOFFSET BASEADR
15. s manual apply to the ISA GPIB PC2A also This manual supplies information on switch settings and jumper position for base address DMA channel interrupt level and wait state Information on programming is found in the manual for the software package you intend to use with the ISA GPIB PC2A 1 2 GPIB HISTORY The GPIB General Purpose Interface Bus has become the worldwide standard for connecting instruments to computers Invented in the 1960s by Hewlett Packard and originally designated as HPIB the bus specification was eventually adopted by a wide variety of both instrument and computer manufacturers The original specification was documented and sanctioned by the IEEE as IEEE 488 The advent of the inexpensive and powerful personal computer has driven the GPIB market through explosive growth As GPIB bus usage expanded there arose the need for some additional capability and standardization so in 1987 IEEE 488 2 was adopted IEEE 488 2 was revised ammended in 1992 and represents the current GPIB specification The new specification provides some standardization among compliant instruments This standardization greatly simplifies the job of the GPIB system designer since 488 2 compliant instruments share common programming conventions 1 3 GPIB SYSTEM DESCRIPTION 1 3 1 Talkers Listeners and Controllers A GPIB device can be a Talker Listener and or Controller As the name implies a Talker sends data to one or more Listeners A List
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