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XSA-200 Manual

1. VSYNC configuration of the FPGA via the parallel port In stand alone mode the CPLD also configures the FPGA with a bitstream from the Flash RAM XSA 351000 BOARD V1 0 USER MANUAL 21 100 MHz Fixed Freguency Oscillator An oscillator provides a fixed 100 MHz clock signal to a dedicated clock input of the CPLD From this clock the CPLD generates two clock signals CLKA and CLKB that go to dedicated clock inputs of the FPGA This allows the CPLD to control the FPGA clocks By default the CPLD outputs 100 MHz and 50 MHz clocks on CLKA and CLKB respectively The clock divider circuit in the CPLD can be reprogrammed to send lower frequency clocks to the FPGA if desired The CLKB signal also exits through a pin on the prototyping header so it can be used as a clock for an external system connected to the XSA 351000 Board Or the external system can send a clock directly to the FPGA through the dedicated CLKC pin of the prototyping header CLKA CPLD CLKB 100 Mhz MASTER CLK Oscillator CLKB Ek CLKC HI XSA 351000 BOARD V1 0 USER MANUAL 22 Synchronous DRAM The XSA 351000 Board incorporates a 16M x 16 SDRAM K4S561632ETC75 that connects solely to the FPGA as shown below Note that the clock signal is re routed back to a dedicated clock input of the FPGA to compensate for clock delays to the SDRAM thus allowing synchronization of the FPGA s internal operations with the SDRAM opera
2. R4 10 L10P 5 URN fu pa RS 10_L27N_5 WRESHE N13 R6 10 L29N 5 GND TL GNDeT1 FLASH D8 I 10 L10N 5 yRAdA pigo 15 10675 2 5u T6 UCCAUXeT6 SDRAM BA9 fZ I08AZ UGA GREEN 08 IO L32P AGA pacy AS 10669 SDRAM CAS A12 TO LIIN 1 UREF 42 eu fil UCCAUX A11 spRAM D5 A12 108A12 UGA HSyNc BZ IO L30P 8 spRAM CSH B8 IO L32N 8 GCLK7 GND B9 GNDEBS spRAM IEH 842 I0L34P 1 eppep p B11 10 L29N 1 spram po B12 10 L27N 1 SDRAM Ba1 EZ IO L30N D uga REpg LE I0 L31P 0 VREE Puro LS 10 L32N LARIE pam D 106010 SDRAM D6 ZL IO L29P 1 spRAM DIG 210 L27P 1 SDRAM CKE DZ_10_L29P_8 yga usync BE 10 L31N 8 spRAM UDQM 28 10 L32P 1 GGekfhm p7 DILO 10 L30N 1 sopam ns Dit 10 L28N 4 eppen pm 212 IO UREF_1 UGA BLUE1 EZ IO L29N O 43 3y E8_UCCO_9e E8 a au ES_UCCO_1 E9 sppaM cik EL2 10 L30P 1 suo Eli 10 L28P 1 1 24 12 UCCINT E12 43 3u EZ UCCO 8eF7 3 3u E8 UCCO 86F8 a au E8 UCCO_18F9 a au 18 UCCO 16F18 GND ELL GNDeF11 600 1014 12 10 L21N 2 END SZ GNDe67 END S8 40608 END 22 GNDe69 GND 812 GNDe618 3 34 BLL UCCO_28611 proro12 212 10_L23N_2 UREF_2 GND HZ GNDEH7 GND H8_GND H8 GND HS_GND amp HS GND HL2GNDEH18 3 3U H11 UCCO 28H11 3 30 42 UCCO_2 H12 GND Z GNDEJ7 END J8 GNDEJ8 END 19 GNDeJ9 GND 418 GNDEJ18 3 34 J44 UCCO_38J11 3 34 42 UCCO_38J12 GND Z ENDeK7 GND KE GNDEKB GND 9 04089 CND 12 GNDeK10 3 3U ELL UCCO 38K11 pi as 3 K12 IO L2
3. 213 IO L39P 3 prorog3 Sit IO L39N 3 GND 115 GND6J15 PROT084 46 10 L40N 3 VREF 3 CLKC RI IO L32N 4 6CLK1 FLesH a K13 I0 L24P 3 riasH ay Kit I0 L24N 3 proroge 15 108K15 PROTOS1 X16 TO L40P 3 CLKA 19 IO L32P 4 6CLKO FLASH A6 13 10 L21N 3 FLasy a4 44 10 L22P 3 pporozg L15 10 L22N 3 2 5U 116 UCCAUXeL16 FLASH NE TS 10 L21P 3 FLasH A17 M4 10_L19N_3 proroze JS 10 1L20P 3 rasH as HIS J0 L20N 3 11 24 NIS UCCINTENIS Fi asp ag M14 10 L19SP 3 pprorozz N15__10_L17P_3 URRAgR_a z N16 10 L17N 3 FLASH A12 P13 TO UREF_48P1 54 094 P24 IO L16P 3 Fiasm pg PLS IO LISN EI acy_peseTy PIS IO LOAN 3 URP 3 FLASH a15 R13 10 LOAN 4 URP 4 END BIS GNDERI5 pp asu 1g R16 IO LB1P 3 URN 3 PROTO78 J13 10_LO1P_4 URNefj A14 44 108714 GND D GND T16 3 34 3 34 3 34 3 3U 3 3V es les lero Tea qe e e qe NIN INN Onl nl ol telt GND GND GND GND EXT FPGA PROG 1 8 lz E E E e 316 470 ISTE LT ae E 2 54 25U _ 2 54 _ 2 54 o 36 115 CCLK 64 les les leo sees 2 BS PROG B 0 1 8 1uF 4uF 0 1 FPGA INIT GE ERA NS 10 L31N 4 INIT B T Eo E 014 gt BONE GND GND GND GND FPGA TMS BSY PS 10 L31P 4 DOUT BUSY FPGA TDI CS R3 IO L81P 5 CS B 4 20 1 2V 1 2U 1 2U FPGA TDO WR I IO L81N 5 RDHR B lex ez les tea FPGA TCK tE c14 TCK ZE Ti Ti Ti c13 TMS A2 TDI GND GND GND GND 615 TDO NA FPGA 2 54 4 M4_ MAGU E ER Document Number REU Date 6 23 2005 03 42 10p Sheet 1 10 FPGA DIN DO FPGA D1 ES
4. CPLD But when the FPGA lowers the Flash CE the CPLD will stop driving the LED decimal point to allow the FPGA access to data line D1 ofthe Flash For more details on how the CPLD manages the interface between the parallel port and the FPGA both before and after device configuration see this application note XSA 351000 BOARD V1 0 USER MANUAL 29 XILINX Parallel Cable IV Connector The XSA 351000 Board has a connector X4 for attaching a XILINX Parallel Cable IV The connections between the Parallel Cable IV and the XSA 351000 Board are shown below You will need to reprogram the CPLD on the XSA 351000 Board with the XSTOOLS XSA 3S 1000 p4jtag svf file before you can use the Parallel Cable IV Then disconnect the XESS downloading cable and connect the Parallel Cable IV to the X4 connector You should never simultaneously attach a Parallel Cable IV and the XESS parallel port downloading cable After connecting the Parallel Cable IV you can use IMPACT to download bitstreams to the FPGA in boundary scan mode A U2 TD ma keert O Prototyping Header The pins of the FPGA are accessible through the 84 pin prototyping header on the underside of the XSA 351000 Board Pin 1 of the header denoted by a square pad is located in the middle of the left hand edge of the board and the remaining 83 pins are arranged counter clockwise around the periphery The physical dimensions of the prototyping header and the pin arrangement are shown b
5. EI ESI E EI HET ASA SA 90 EA NOA E A O oyy ENE SI HVT E Ha dd toda 8 PN E SEA EN HE EE MEE A HE EE E E 1 T i EK asa IA PN BLV HSVI gt yo pp med KEETIS EEE EI EEE EET SVT ae aS yoo po EE OO eee ee OOO nn ea HST gt o pop Dnw po po ke EEE DSC EES i oN HST a ee E E ER SS ea asa OU Pld HST OW pp po o ee EEE EI WV BE 106 6V HSVIA gt yo pp Om po op NH RARA 0403 45 A HESSI EES E ET EA AE AS ARA DIN SSA AAA AA NEEN E AE AS BOV A A IS AE EI EEE SII Et TT EEEN WOW ST gt o po MM ksa mi ovsa ES OO O A A A A E E E EE EE EE EEE Mod B il NI ESSE LS e AS lt AI P ONE OAS CCN GGA OZ LE EH LH L OL 63633 LISA AEE AA HHL OL OLT 7913 134 1796700170 TS PA AA Se O EHE A OO EEE ELN YN cu aw EIA GAEL YO NS Lr yn suong Hod Is se S ul ul uid oo Sd von an 250 en useld uvas us sam eene EN Uld 0702 LN Uld VOda ween 01608 000LS VSX ey UO s UaUOdWOD 19470 pue 0149 WOd4 041 400 4189 54011004402 EE PI geolotdi EWEN E EA EA AS A E E E EA NE eeh RA CA 60108 A E A ee O RA ZOO A A O Ti s AAA MM ioga VAL ZOO AE AS A AS E AA A AA AA AAA A ole et POLO ES EN EE HE EI SS E E LOE BOLO eee Ee A EE EN A FOL ST SS SS SS ES SSS SS SS SS ESS ESSE OO OL A A A et Et VE A ee BOO U WO EE EA A AA EA E EA AAA O EA AO AAA PS OOd A VOL El eel 1 AMI o A PS l
6. O EEE 98S ES SE E E E SSS E E ESS EASI RARA 08 OVAS POW EE EE GE OBV El 00008 ROW 6 vvas RRA P SV A AAE CE a A A A SN E E A A A NAS RRA WS Lr vn suoyng Hod se maosa BSS VON naso en useid w e 031 pese EM uid TED Um ua voda mmm 01608 000LS VSX ey UO sJusuodwog 19470 pue 0149 WOd4 041 400 4189 540112004402 XSA 381000 Schematics The following pages show the detailed schematics for the XSA 351000 Board XSA 351000 BOARD V1 0 USER MANUAL 33 END AL 40661 SDRAM A9 A3 I0 UREF B6A2nRAM A1 A4 TO L01P 8 JARN Brey 05 10665 2 5U A6 VCCAUXEAS uGa RED2 BL IO LO1P 7 URN 7 nn B2GNDEB2 SDRAM A2 B4_10_L 1N_ URBpAM ag B5 10 L25P 8 spRAM A1g B 10 L28P 8 SDRAM A5 LL IO LAIN 7 URBrAm Ag C2 TO L16N 7 yga GREEN2 C3 10 L16P 7 UREF 7 SDRAM A14 C8 10 L25N D spRAM A12 C IO L28N 0 PROTO25 DL IO L17N 7 ppgto24 22 10 117P 7 spram az 23 10 L19P 7 11 20 D4 VCCINTED4 uge a ye D5 10 UREF GeD cA
7. to ground The pin is pulled high through a resistor when the switch is open OFF Two of the DIP switches also connect to the upper two bits of the Flash address bus These DIP switches are used to select the Flash quadrant holding a bitstream that will be loaded into the FPGA by the CPLD on power up XSA 351000 BOARD V1 0 USER MANUAL 25 The FPGA also connects to two pushbuttons Each pushbutton applies a low level to its FPGA pin when pressed and a resistor pulls the pin to a high level when the pushbutton is released Small resistors are placed in series between the FPGA and the switches and pushbuttons to prevent damage if the FPGA tries to drive a pin that is being pulled low 3 3V gt FLASH A19 A gt FLASH A18 E SW1 1 So MN o SW1 2 so MN o SW1 3 45 o MN SW1 4 66 ANA AN sw2 5003 PS 2 Port A PS 2 port provides the FPGA with an interface to either a keyboard or a mouse The FPGA receives two signals from the PS 2 interface a clock signal and a serial data stream that is synchronized with the falling edge of the clock For more details on using the PS 2 port and a simple circuit for receiving keystroke information from a keyboard see this application note 3 3V The FPGA can generate a video signal for display on a VGA monitor The FPGA outputs three bits each of red green and blue color information to a simpl
8. x You start GXSLOAD by clicking on the IE icon placed on the desktop during the XSTOOLS installation This brings up the window shown below Select the XSA 351000 Board and the parallel port to which it is connected as indicated below X gxsload E 191 xi Board Type x 4 351000 Load Port Ba FPG4 CPLO Flash EEPRORM High Address 0 Low Address Upload Format HEX E E Now you can download bitstream files to the FPGA or CPLD simply by dragging them from their folder and dropping them into the FPGA CPLD pane ofthe GXSLOAD window as shown below X gxsload E E E ioj x E Board Type mm 221000 Load File Edit View Favorites Tools Help El E Folders A Ba A X o Ed Part LPT1 E wit Ert Address CARSTOOLS1 581351000 sl FPGA CPLD Flash EEPROM aa FinitF bit JI High Address O 1FFFFF DEET FFFFF Low Address o Upload Format HEX E Type BIT File Si 1393 EB d My Computer Once you drop the file the highlighted file name appears in the FPGA CPLD pane and the Load button in the GXSLOAD window is enabled Clicking on the Load button will begin sending the bitstream in the file to the XSA 351000 Board through the parallel port connection BIT files contain configuration bitstreams that are loaded into the FPGA while SVF files will go to the CPLD GXSLOAD will reject any non downloadable files ones XSA 351000 BOARD V1 0 USER MANUAL 13 with a suffix oth
9. 0 folder into the FPGA CPLD pane of the GXSLOAD window Then click on the Load button and the CPLD will be reprogrammed in less than a minute Then move the shunt on jumper J9 from the XS to the XI position At this point you can start IMPACT and it will believe it is connected to the XSA 351000 Board through a Xilinx Parallel Cable III in boundary scan mode Follow the instructions for IMPACT to download bitstreams to the FPGA You can also use a Xilinx Parallel Cable IV with the XSA 351000 Board by downloading the XSTOOLS XSA 3S1000 p4jtag svf file into the CPLD Then disconnect the XESS downloading cable and connect the Xilinx Parallel Cable IV to the X4 connector Now start IMPACT to download bitstreams to the FPGA in boundary scan mode Note that the CPLD only needs to be reprogrammed once to support MPACT because it retains its configuration even when power is removed from the board If you want to go back to using the GXSLOAD programming utility just must move the shunt on J9 back to the XS position and download the X STOOLSIXSAldwnldpar svf file into the CPLD Storing Non Volatile Bitstreams in the Flash The FPGA on the XSA 351000 Board stores its configuration in an on chip SRAM which is erased whenever power is removed Once your design is finished you may want to store the bitstream in the 16 Mbit Flash device on the XSA 351000 Board from which the FPGA will be configured each time power is applied XSA 351000 BOARD V1 0 USER M
10. 00 Board circuitry Be careful The voltage regulator on the XSA 3S1000 Board can become hot To reduce the power dissipation in the regulator and keep it cool use a power supply with a voltage near 5V You can also attach a heat sink to the regulator if necessary Powering Through the PS 2 Connector You can use your XSA 351000 Board with a laptop PC by connecting a PS 2 male to male cable between the PS 2 ports of the laptop and the board The shunt on jumper J7 should be in the PS 2 position The on board voltage regulation circuitry will create the voltages required by the rest of the XSA 351000 Board circuitry Many PS 2 ports cannot supply more than 0 5A so large high frequency FPGA designs may not work when using this power source XSA 351000 BOARD V1 0 USER MANUAL 6 Solderless Protoboard Installation The two rows of pins from your XSA 351000 Board can be plugged into a solderless protoboard with holes spaced at 0 1 intervals One of the A C E protoboards from 3M is a good choice Once plugged in many of the pins of the FPGA are accessible to other circuits on the protoboard The labels printed next to the rows of pins on your XSA 351000 Board correspond to the pin numbers of the FPGA Power can still be supplied to your XSA 351000 Board though the 5V 9V DC jack or power can be applied directly through several pins on the underside of the board Just connect 5V 3 3V 2 5V and ground to the pins of your XSA 351000 Bo
11. 3N 3 43 3u LZ UCCO 5eL7 3 3u L8_UCCO_5BL8 43 3u L9 UCCO_4eL9 a au L18 UCCO_48L18 END Lit GNDeL11 EI guppy 12 IO L23P 3 UREF 3 FLASH D12 2 IO L30P 5 a au 8 UCCO 58M8 3 34 MS UCCO_48M9 proross 18 I0 L29N 4p a piN Do li 10 L27N 4 DIN DQ 2y M12 VCCINTEM12 FLASH D14 M 10 L30N 5 FLASH A16 NLG _10_L29P_4 ppga p4 ML 10 L27P 4 84 AsH A13 NL2 I0 UREF 48N12 FLASH D45 PZ 10602 FPG amp D2 212 I0 L38N 4 D2proTos IO L28N 4 proro 1 Pl2 IO L25N 4 FPGA D5 RZ 10 L341P 5 05 GND R8 GNDERB FpGA D3 4010 L30P 4 D3 pp cg RiL I0L28P 4 ppg ogg 212 10 L25P 4 FPGA D4 IZ IO L31N Bb ByTE4 I8 I0 UREF 5 pp s6 118 IO UREF 48718 45 5y TLL UCCAUX T11 pporogg 112108712 su3 ALS TO L10N 1 VREReM n2 fl4 TO LOAN 1 URP 1 GND ALS GNDEA16 SDRAM D3 B13 I0 L10P 4 spRAM D11 B14 IO_L 1P_1 URN_1 gnp Bi5 GNDEB15 ps2 cLk 246 10 LOAN 2 URP 2 SDRAM DO 15_10_L16N_2 spRAM D13 1610_LO1P_2 URN_2 Ut 1 24 D13 UCCINT D13 spRAM D12 D14 IO L16P 2 proro 1 245 10_L17N_2 pproro19 D16_10_L17P_2 UREF_2 XC351000 4F T256 092 06 6 13 10_L19N_2 pporozg Elf I0_L19P_2 proro18 E15 IO_L2 N_2 proro14 El 10 _ 200 2 SDRAM D15 EL2 10 L21P 2 proro13 ELL IO L22N 2 pRoTO19 25 10 L22P 2 2 5U 16 UCCAUXEF 16 protog 13 IO L23P 2 protog Sit IO L24N 2 PROTO7 815 IO L24P 2 PROTOS 216 108616 Soa ne a protos 13 TO L39N 2 PROTO4 Hit 10 L39P 2 PROTO3 DS IO L40N 2 PROTOL His 10 L40P 2 UREF 2 CLKB P8 10 L32N 5 6CLK3 PROTO82
12. 4 ESS Corporation XSA 3S1000 Board V1 0 User Manual How to install test and use your new XSA 351000 Board RELEASE DATE 6 23 2005 Copyright O 2001 2005 by X Engineering Software Systems Corporation All XS prefix product designations are trademarks of XESS Corp All XC prefix product designations are trademarks of XILINX All rights reserved No part of this publication may be reproduced stored in a retrieval system or transmitted in any form or by any means electronic mechanical photocopying recording or otherwise without the prior written permission of the publisher Printed in the United States of America XSA 351000 BOARD V1 0 USER MANUAL 1 Table of Contents XSA 351000 BOARD V1 0 USER MANUAL 2 XSA 351000 BOARD V1 0 USER MANUAL Preliminaries Getting Help Here are some places to get help if you encounter problems If you can t get the XSA 351000 Board hardware to work send an e mail message describing your problem to helo xess com or submit a problem report at htto www xess com help html Our web site also has m janswers to frequently asked questions m example designs application notes and tutorials for the XS Boards m ja place to sign up for our email forum where you can post questions to other XS Board users If you can t get your XILINX WebPACK software tools installed properly send an e mail message describing your problem to hotline XILINX com or check thei
13. ANUAL 15 The Flash is partitioned into four quadrants each of which can hold a bitstream for the FPGA Before a bitstream can be downloaded into a guadrant of the Flash the BIT file must be converted into an EXO or MCS format using one of the following commands uadran ress Range onversion Comman sms 5012 0x000000 0x07FFFF promgen u 0 file bit p exo w ON ON promgen u O file bit p mcs w 1 0x080000 0x0FFFFF promgen u 80000 file bit p exo w ON OFF promgen u 80000 file bit so mcs AN 2 0x100000 0x17FFFF promgen u 100000 file bit p exo w OFF ON promgen u 100000 file bit p mcs w 3 0x180000 0x1FFFFF promgen u 180000 file bit p exo w OFF OFF promgen u 180000 file bit so mcs w In the commands shown above the bitstream in file bit is transformed into an EXO or MCS formatted file starting at the first address in each quadrant and proceeding upward The EXO or MCS file is downloaded into the Flash device by dragging it into the Flash EEPROM pane and clicking on the Load button This activates the following sequence of steps 1 The FPGA and CPLD on the XSA 351000 Board are reprogrammed to create an interface between the Flash device and the PC parallel port 2 The entire Flash device is erased 3 The contents of the EXO or MCS file are downloaded into the Flash through the parallel port 4 The CPLD is reprogrammed with a circuit that configures the F
14. D V1 0 USER MANUAL 17 After the data is uploaded from the Flash the default parallel port interface remains in the CPLD You will need to reprogram the CPLD with the configuration loader bitstream in XSTOOLS XSA 3S 1000 fcnfg svf if you want the FPGA to be configured from Flash whenever power is applied Downloading and Uploading Data to the SDRAM The XSA 351000 Board contains a 256 Mbit synchronous DRAM 16M x 16 SDRAM whose contents can be downloaded and uploaded by GXSLOAD This is useful for initializing the SDRAM with data for use by the FPGA and then reading the SDRAM contents after the FPGA has operated upon it The SDRAM is loaded with data by dragging amp dropping one or more EXO MCS HEX and or XES files into the RAM pane of the GXSLOAD window and then clicking on the Load button This activates the following sequence of steps 1 The FPGA is reprogrammed to create an interface between the SDRAM and the PC parallel port This interface 16 stored in the XSTOOLSIXSAI3S1000lramintfc bit bitstream file The CPLD must have previously been loaded with the dwnldpar svf file found in the same folder 2 The contents of the EXO MCS HEX or XES files are downloaded into the SDRAM through the parallel port The data in the files will overwrite each other if their address ranges overlap 3 If any file is highlighted in the FPGA CPLD pane then this bitstream is loaded into the FPGA or CPLD on the XSA 351000 Board Otherwis
15. FLASH A9 DQ6 FPGA D6 FLASH AS DQ13 FLASH D13 FLASH A19 DAS FPGA D5 DQ12 FLASH D12 FLASH WE DQ4 FPGA D4 FLASH RESE TE UCC 13550 DQ11 FLASH D11 DQ3 FPGA D3 FLASH RDY DQ10 FLASH D10 FLASA ALS DQ2 FPGA D2 FLASH A17 DAS FLASH D9Y FLASH A7 DQ1 FPGA D1 FLASH A6 DQ8 FLASH D8 FLASA A9 DAB FPGA DIN DO FLASH A4 OEH FLASH OE FLASA AS 45561 GND FLASH A2 CE FLASH CE FEASA AL AD FLASH AQ FLASH RESE TE FLASH CE FLASH BYTE Sheet 3710 TA SDRAM DO 315 SDRAM D1 SDRAM D2 GND SDRAM D3 SDRAM D4 3 3U SDRAM D5 SDRAM D6 GND SDRAM D 3 3U SDRAM LDQM SDRAM WE SDRAM CAS SDRAM RAS SDRAM CS SDRAM BA SDRAM BA1 SDRAM A10 SDRAM AB SDRAM A1 SDRAM A2 SDRAM A3 pare fren U4 Samsung K45561632ETC79 Ba GND SDRAM D15 GND SDRAM D14 SDRAM D13 E Sed SDRAM D12 SDRAM D11 GND SDRAM D19 SDRAM DS FO SDRAM D8 GND SDRAM UDQM SDRAM CLK SDRAM CKE SDRAM A12 SDRAM A11 SDRAM A9 SDRAM A8 SDRAM AZ SDRAM A6 SDRAM A5 SDRAM A4 GND 10 SDRAM CKE R G 4 7K 9 SDRAM CS RZA 4 7K PSV 3 3V B LuF Pe Li Sheet 4 18 PS2 DATA PS2 CLK UGA RED2 UGA RED1 UGA REDO UGA GREEN2 UGA GREEN1 UGA GREENO UGA HSYNC UGA BLUE2 UGA USYNC UGA BLUE1 UGA BLUEO SO O1 LO A 00 td NI NN ON Jameco 71466 4 5 R2D 470 Tk PS 2 UGA Switches R1D 1 0K lt Wes se R4D 1 8K 672372000 SAIA Sheet 5 18 ECS 3993M 1808009 BN Sheet 6 10 3 3U 2 5U uz e
16. FPGA D2 FPGA D3 FPGA DONE FPGA D4 FPGA INITE FPGA D5 FPGA D6 FPGA D7 FLASH D15 FLASH A16 GND PP S5 PP D 3 3U ii CO OO IN AN O1 0 IN 1 061 1 076TSZ UCCINTB1 1 064 IZ0 6151 1 0B6 1 087 1 0 CCk2 Sao TuF G 0 GND 12 A i GND FPGA TMS BSY FPGA TDI CS FPGA PROG F PGA TDO WR 13450 F_LASH OE FLASH CE GND F_LASH A CLKB CLKA FPGA CCLK CPLD TDO FLASH AL FLASH A2 FLASH A3 1 0 6SR 1 0863 1 0862 170861 I 0860 1 0859 1 0858 1 0897 1 0806 UCCIOe2 GND 4 100 1 0852 1 0851 1 0850 1 0849 U2 XC9572XL 10U064 T O GCK3 1 0618 1 0619 1 0620 GNDe 3 1 0622 1 0823 1 0824 1 0825 UCCI081 1 0827 1 0831 1 0832 TDI LMS TCK 17 18 19 20 21 22 23 24 25 26 27 28 a 30 31 32 PP D6 PP D5 PP D1 GND PP D4 PP D3 PP S3 PP S4 3 2 PP DO PP C3 PP C2 PP C1 PP D2 FLASH A15 MASTER CLK 1 0848 1 0847 1 0846 1 0845 1 0844 1 0843 1 0842 GNDe1 1 0840 1 0839 1 0838 VCCINT 2 1 0836 1 0835 1 0834 1 0833 FSV C 0 GND LUF FLASA A FLASA A0 FLASA A6 FLASH AZ FLASH A17 FPGA TCK FLASH WE GND FLASH A8 FLASA A9 FELASA ALY 3 FLASH A11 FLASH A12 FLASASALS FLASH A14 age RE o TuF 14 a GND Sheet 2 10 U3 Spansion S29ALB16M10TA1020 FLASH A15 016 FLASH A16 FLASH A14 BYTE FLASH BYTE FLASH A13 USSe2 GND FLASH A12 DQ15 A 1 FLASH D15 FLASH A11 DQ7 FPGA D7 FLASH ALO DQ14 FLASH D14
17. GA This lets the PC pass data to the FPGA over the parallel port data lines while receiving data from the FPGA over the status lines The active connections between the FPGA CPLD and the parallel port after configuration are shown below XSA 351000 BOARD V1 0 USER MANUAL 28 BS The FPGA sends data to the PC by driving logic levels onto the AO A1 and A2 Flash address lines which pass through the CPLD and onto the parallel port status lines 53 54 and 55 respectively Conversely the PC sends data to the FPGA on parallel port data lines D7 DO and the data passes through the CPLD and ends up on the A15 A8 Flash address lines respectively The FPGA should never drive A15 A8 unless it is accessing the Flash otherwise the CPLD and or FPGA could be damaged The CPLD can sense when the FPGA lowers the Flash CE and it will release the Flash address lines so the FPGA can drive them without contention The CPLD also drives the decimal point of the LED display connected to Flash data line D1 to give a visual indication when the FPGA is configured with a valid bitstream Unless it is accessing the Flash RAM the FPGA should never drive Flash data line D1 to a low logic level or it may damage itself or the
18. L 19 Programmer s Models This section describes the various sections of the XSA 351000 Board and shows how the I O of the FPGA and CPLD are connected to the rest of the circuitry The schematics which follow are less detailed so as to simplify the descriptions For more information you can find a table of FPGA and CPLD pin connections and detailed schematics at the end of this manual XSA 3S1000 Board Organization The XSA 351000 Board contains the following components FPGA This is the main repository of programmable logic on the XSA 351000 Board CPLD This manages the interface between the PC parallel port and the rest of the XSA 351000 Board It can also configure the FPGA with a bitstream from Flash Oscillator A fixed frequency oscillator generates the master clock for the XSA 351000 Board SDRAM A 256 Mbit SDRAM provides volatile data storage accessible by the FPGA Flash A 16 Mbit Flash device provides non volatile storage for data and FPGA configuration bitstreams LED A seven segment LED allows visible feedback as the XSA 351000 Board operates DIP switch A four position DIP switch passes settings to the XSA 351000 Board and controls the upper address bits of the Flash device Pushbuttons Two pushbuttons send momentary contact information to the FPGA PS 2 Port A keyboard or mouse can interface to the XSA 351000 Board through this port VGA Port The XSA 351000 Board can send signals to display 512 col
19. NI i EE eloa 8S ts SOLO E EIEC Rm ED EEDI CT ESI AT ogg N90 L088 AAN AA A SS AA AA A A A AAA AM AT RR O IE O O E ISOLOUd MAA A IN OOA DPI BPO LOU SI S eN 8vOLOUd A O O VA LOLOL ae EEE eee EES EEE EA AAA NEON AA ee CCA SVOLOUd Es Ps Pa Pa EES KE EES EEE EAT AA O V POLO Es A AE A 5 ee 01088 AR EL WOLO d EE RARAS AA AA AO ESSES EH EO LON BE EKE E E EE EE SEI TESTE RRA 2601080 11 EE EE 1 EE E 11 11 TE EET A EI El AAA EENI E E NA A HIHI Lr vn suoyng Hod 01608 000LS VSX ey UO sjuauoduiod 19470 pue 0149 WOd4 041 400 4189 54011004402 RANA CA HONASANOA A AO EAT Ee ANNE eV SS aa ee Se SS A A a SSS E A E E IN EEE EAN AAA AAA AIT SEEN A O DN EE SSA O Ss ES O O PO PO O AA ESLORA MV A ee Sn SEEN OM VN ESS SS SSS SSS EEE A E OSS EMS MS A LE ZMS je e ole e TA ASE NE jh p lle GNS ARAS CAES EA E EI ESI AO EN E E AO AAA EEE Avas A O O SSA A II NES OBW Gy ES NES INT NOGUTAVEOS E EEE SS E SSS SS EES EE EEE SS eae aaa SAI Ell 2 2 NES EDS ES NES RRA CA ELONVHOS E HE E EEE HE AI A HE EEE ae ES RR AA DOLO NOS A OO pera gt gt gt gt gt lea ONO PBO Wa NES E E E EI E 0 EE HE EE anvas AAA WO anvas DEN NATA A anvas A ES ee O y wod EES era 6006 ARA OC ONO WPO tae A E NES ES EE E E E 609 EES CIO AMOS ARA AA AAA AAA A AAN SNS ES OWS EES EES EES EE EEE 20609 EI E Saas AR 49 VENAS ae e e E A
20. OUW DIT Sheet 18 18
21. PACK tools for programming their CPLDs and Spartan series FPGAs The XESS CDROM contains a version of WebPACK that will generate bitstream configuration files compatible with your XSA 351000 Board You can also the most current version of the WebPACK tools from the XILINX website In addition XESS Corp provides the XSTOOLS utilities for interfacing a PC to your XSA 351000 Board These utilities should be installed automatically when you insert the XSTOOLS CDROM into your CDROM drive If not then manually run the SETUP EXE installation program on the CDROM Applying Power to Your XSA 351000 Board You can use your XSA 351000 Board in three ways distinguished by the method you use to apply power to the board Only use one of these methods to power your XSA 351000 Board Supplying power from multiple sources can damage the board and or power supplies Using a 5V 9V DC wall mount power supply You can use your XSA 351000 Board all by itself to experiment with logic designs Just place the XSA 3S1000 Board on a non conducting surface as shown in Then apply power to the XSA 351000 Board from a DC wall mount power supply with a 2 1 mm female center positive plug and a voltage in the range 5V 9V See Figure 2 for the location of the 5V 9V DC power jack on your XSA 351000 Board The shunt on jumper J7 should be in the 9V position The on board voltage regulation circuitry will create the voltages required by the rest of the XSA 3510
22. PGA with the contents of the Flash whenever power is applied to the XSA 351000 Board This configuration loader is stored in the XSTOOLS KSA 3S 1000 fcnfg svf file Once the Flash download is complete you must set the DIP switches to select the Flash quadrant containing the FPGA bitstream see the switch settings in the table above The FPGA will be configured with the bitstream in that guadrant whenever power is applied to the board You can download multiple bitstreams to the Flash and use the switches to select the one to be loaded into the FPGA on power up Multiple files can be stored in the Flash device just by dragging them into the Flash EEPROM area highlighting the files to be downloaded and clicking the Load button Note that anything previously stored in the Flash will be erased by each new download This is useful if you need to store information in the Flash in addition to the FPGA bitstream Files are selected and de selected for downloading just by clicking on their names in the Flash EEPROM area The address ranges of the data in each file should not overlap or this will corrupt the data stored in the Flash device You can also examine the contents of the Flash device by uploading it to the PC To upload data from an address range in the Flash type the upper and lower bounds of the range into the High Address and Low Address fields located below the Flash EEPROM pane and select the format for the uploaded data from the Upload F
23. US LMS1585ACT 3 3 TPS73225DBU OO IN OUT 1 2 GND GND C23 C26 L 0 1uUF 4 7UF S7 ur LZ Y U8 FAN11125X GND HS 632 103 UE 47uF GND Power Supply TITLE xsa 35 Document Number REU Date 6 23 2005 03 42 10p Sheet 7 10 Uref Gnd TCK UCLK NL TDO DONE TDI DIN TMS PROG XI PCBL IU HDR 1 2 3 4 5 6 f 8 9 CPLD TDO PP S6 PP S7 PP S5 0625 SL 2 3 Sheet 8 18 CLKC PROTO66 PROT067 PROTO68 PROTO69 PROTO 0 PROTO 1 PROT077 PROTO 8 PROTO 9 PROTO8 PROT081 PROTO82 PROTO83 PROTO84 PROT01 PSU PROTOS PROT04 PROTOS PROTO6 PROTO PROTOS PROTOS PROTO10 CLKB PROTO12 PROTO62 PROTO61 PROTO6 PROT059 PROTOS8 PROTO57 PROTOS6 EXT FPGA PROG Poesy GND PROT051 PROTOS PROTO49 PROTO48 PROTO47 PROTO46 PROTO45 PROTO44 PROTO43 PROTO42 PROTO41 PROTO4 PROTO39 PROTO38 PROTO37 PROTO36 PROTO35 PROT034 PROT033 PROTO32 PROTO31 PROTO13 FPGA TDO WR PROTO14 PROTOZ9 FPGA TDI CS PROTO28 FPGA TCK PROTO27 FPGA TMS BSY PROTO26 PROTO18 PROTO19 PROTO20 PROTO21 PROTO25 PROTO24 PROTO23 they Molex 22284360 sheet 9 10 FLASH A19 FLASH A18 2 SW1 3 3 SW1 4 2 2 RSA 470 RIC 470 RSD 470 FPGA D3 FPGA D2 FPGA DIN DO FPGA D7 FPGA D6 FPGA D4 FPGA DS FPGA D1 efe KIN No J o gt oo fa for DUDO Vx VV ot Va V ETRE Te Te Te O a jw or JON UG TO CD UID Wax Wax Va V J O m K A1 DAD 000000
24. XSA 3S1000 Board connects it to a PC One end ofthe cable attaches to the parallel port on the PC and the other connects to the female DB 25 connector at the top of the XSA 3S1000 Board as shown in Connecting a VGA Monitor to Your XSA 351000 Board You can display images with up to 512 colors on a VGA monitor by connecting it to the VGA port at the bottom of your XSA 3S1000 Board see Figure 1 You will have to create a VGA display circuit for your XSA 3S1000 Board to actually display an image See for details on the VGA port circuitry and an example of a VGA display circuit XSA 351000 BOARD V1 0 USER MANUAL 8 Connecting a Mouse or Keyboard to Your XSA 351000 Board You can accept inputs from a keyboard or mouse by connecting it to the PS 2 port at the bottom of your XSA 351000 Board see Figure 1 You will have to create a keyboard or mouse interface circuit to actually receive information on keystrokes or mouse movements See for details on the PS 2 port circuitry and an example of a keyboard interface Inserting the XSA 351000 Board into an XStend Board Do not insert an XSA 3S1000 Board into an XST 1 or XST 2 x XStend Board The XSA 351000 Board is not compatible with the voltages on these versions of the XStend Board An XST 3 0 XStend Board will be available in 2005 Setting the Jumpers on Your XSA 351000 Board Jumper J2 J7 J9 J10 The default jumper settings shown in Table 2 configure your XSA 3S1000 Board
25. ard listed in Table 1 Remove the shunt on jumper J2 if you supply 2 5V from an external source e Table 1 Power supply pins for the XSA 351000 Board Voltage Pin Note 5V 2 This pin is labeled 5V 3 3V 54 This pin is labeled 3 3V 2 5V 22 This pin is labeled 2 5V GND 52 This pin is labeled GND Parallel Port e Figure 1 External connections to the XSA 351000 Board XSA 351000 BOARD V1 0 USER MANUAL 7 Parallel Port E O PE LO 76 a O 14 25 1 13 KC Tax IB 4000000800 E o e Te 411100 TK C28 Ri e a 9 09 Parallel Cable IV Connector 01555 ha UL 8 E 2004 af De eno Si e 5V 9V DC 11 Ki SEC me u B dl UI Perz su 100 MHz Oscillator Soe uF ki e 012 _ mmm a y7 u N20 eh O mes J8 e LED Digit o mmm U2 RS GNDO CPLD e nao ens us fuso fam NO 1115 E R3 140 els E E 12 exis 3 E me r 2 1 M NU rit DIP Switches 0114 0516 J1 8H16 R32 5u 0H15 0H14 0H13 0016 15 FPGA M ci ers SDRAM oo 1111111111111111111111111 1 e 65 ri4 Ke 00 oris Ut F30 STD oy J2 C TCK UHT 8 Eze 1157 PIS rm 50 359 Board 4 pushbuttons ens GEEN E 020 pl o f 2 Q9 2 OSS ch W Wed Geier R4 D R2 C33 J4 J3 5 1 PS 2 Port o as o VGA Port i TC read HDF15 CONEC e Figure 2 Arrangement of components on the XSA 351000 Board Connecting a PC to Your XSA 351000 Board The 6 DB25 male to male cable included with your
26. e resistor ladder DAC This provides a palette of 2 x 2 x 2 512 colors The outputs of the DAC are sent to the XSA 351000 BOARD V1 0 USER MANUAL 26 RGB inputs of a VGA monitor The FPGA also generates the horizontal and vertical sync pulses HSYNCH VSYNCH See this for more details on a simple circuit for generating VGA signals that displays an image stored in SDRAM VSYNC HSYNC REDO RED 1 RED2 GREENO GREEN we Wr w GREEN2 AAA AM MN w BLUEO BLUE BLUE2 Parallel Port The parallel port is the main interface for communicating between the XSA 351000 Board and a PC Control line CO and status line S6 connect directly to the FPGA and can be used for bidirectional communication between the FPGA and PC The CPLD handles the fifteen remaining active lines ofthe parallel port as follows Three of the parallel port control lines C1 C3 connect to the JTAG pins through which the CPLD is programmed The C1 control line clocks configuration data presented on the C3 line into the CPLD while the C2 signal steers the actions ofthe CPLD programming state machine Meanwhile information from the CPLD returns to the PC through status line 57 The eight data lines DO D7 and the remaining three status lines S3 S5 connect to general purpose pins ofthe CPLD The CPLD can be programmed to act as an interface between the FPGA and the parallel port The CPLD connects to t
27. e the FPGA remains configured as an interface between the PC and the SDRAM You can also examine the contents of the SDRAM device by uploading it to the PC To upload data from an address range in the SDRAM type the upper and lower bounds of the range into the High Address and Low Address fields below the RAM pane and select the format for the uploaded data from the Upload Format pulldown list Then click on the file icon and drag amp drop it into any folder This activates the following sequence of steps 1 The FPGA is reprogrammed to create an interface between the SDRAM device and the PC parallel port 2 The SDRAM data between the high and low addresses inclusive is uploaded through the parallel port 3 The uploaded data is stored in a file named RAMUPLD with an extension that reflects the file format XSA 351000 BOARD V1 0 USER MANUAL 18 X gxsload 3 E gt 10 x Board Type x 4 351000 Load Port Ba FPGASCPLD Flash EEPROM OTT High Address DEET FFFFF Low Address Upload Format HEX 3 The 16 bit data words in the SDRAM are mapped into the eight bit data format of the HEX MCS EXO and XES files using a Big Endian style That is the 16 bit word at location N in the SDRAM is stored in the eight bit file with the upper eight bits at address 2N and the lower eight bits at address 2N 1 This byte ordering applies for both RAM uploads and downloads XSA 351000 BOARD V1 0 USER MANUA
28. eedi SY 40108 EEN SE LO EE EI EE E E SSS E E E E EE EE PC EESTI SE EOLOHd AAA A E RH E ili Eli Old ASS VESES e pe oo CES 000 EXE 0099 960 EPSE 00000 9600 A AA O A A AO E O O AAA E E ES ES A A A A AAA A Ol A Ao O 9009 EECH O O O js A AA CF KEE EK dd A CE EA AS E 700 111 A A 11 1 1 BD DD acoeg A EA Edel AA E LE E E EEE EE EU A aaa ill joga OO Ordi AAA AA ill A E FE EAS E Edel j esi s E AE EE ssa joa LR 0009 AAA A a CESSA ASA Z ano 9 22 SSAI Z9 SSA cyan romano HELVIEVLO LAA gg og za o ved ON ANA Es Se ESA EL MEE E E EE EE EI HE IE E EH A NS EEE WS BSS EI E E EN EI ESA SS E HE AO ER SSE L 90 TAE AAA ooo ess A OOS Lr vn suoyng Hod 01609 0001S VSX ey UO s UaUOdWOD 19410 pue 0149 VOd 041 400 4189 SUOIJUUOJ TI 9080 oa 606 VS A ES OA O EES eee AAA VANOS EO OVAS AAA AA A AO EEDI EI EI EON RARA gig Oe EE AES EE EES SS IS SI ESI SS NE 8 O ESOO A de O O O AN SI A EE HE E AR HIN ICON A A A AAA AAA AAA AAA AA AA ME SN 6 EI El IE B OM M M M 1 0 Ke E E os SN LOL SS SSS SSS A M A AA AAA AAA AAA A sy 1 1 9 LOL ERRE E E SE SE A E EE EEE rss OO LOL Et AA AS SS A t erie eer es LOL UE 0LOLO d A EH L088 NNT AA A 49 bd E L088 EE HESSE IE ST ET EH EG U ITS 8 SOLO A E ESI EES EE EE EE WL WSS A A A 2go L088 E A O A EE 0 09008 Essas SEE WS FS
29. elow XSA 351000 BOARD V1 0 USER MANUAL 30 lt 1 19 gt 64 0 4 63 o 8 e e e 01 y gt 2 A e 8 e e 84 e 1 m 4 1 e e o 8 o o e e o e e 8 e 21 0 22 A subset of the FPGA pins connects to the prototyping header These pins are not connected to any of the other components on the XSA 351000 Board so they are completely free to use for I O operations with external systems without any restrictions The number of the FPGA pin connected to a given header pin is printed next to the header pin on the board This makes it easier to find a given FPGA pin when you want to connect it to an external system XSA 351000 BOARD V1 0 USER MANUAL 31 XSA 351000 Pin Connections The following tables list the pin numbers of the FPGA and CPLD along with the pin names of the other chips that they connect to on the XSA 351000 Board XSA 351000 BOARD V1 0 USER MANUAL 32 SAA AA e oe oe 05 oo e Oo eN A LH NOVO gt o pp 66003 po o Ni dvd MA STN 9 DEE OPA SEA El M HESSI EEE SEE EEE GES 6609 SAI SE EIA tOVOdA GEE AAA 0 FIN ONO VO A A AAA A eh A a DDDE jose AA EUN 30090 HS A A EEE EEES ISH TAHT gt ooo Ss 01 EES di ss SY SO aed HVT oo E ARA A E MS ea keris v te HVT E HE EE EE HA IEEE
30. er than BIT or SVF During the downloading process GXSLOAD will display the name ofthe file and the progress of the current download X gxsload E 0 x Board Type x 4 351000 Load Port Ba FPGA CPLD Flazh EEPROM High Address Low Address Upload Format HEX E E You can drag amp drop multiple files into the FPGA CPLD area Clicking your mouse on a filename will highlight the name and select it for downloading Only one file at a time can be selected for downloading X gxsload E JO x Board Type x5 4 351000 Load Port pm y FPGASCPLD Flash EEPROM High Address Low Address Upload Format HEX ramintfc bit test board bit XSA 351000 BOARD V1 0 USER MANUAL 14 Double clicking the highlighted file will deselect it so no file will be downloaded Doing this disables the Load button X grsload E O x Board Type esa 351000 S Load Port LPT1 FPGASCPLD Flash EEPROM rarnintfc bit diwrldpar svt test board bit High Address Low Address Upload Format HEX La HEX La Downloading Using Xilinx IMPACT You can use the Xilinx IMPACT software to download bitstreams to the XSA 351000 Board The IMPACT programming tool downloads bitstreams through the JTAG interface of the FPGA so we need to change the parallel port interface by reprogramming the CPLD Drag 8 drop the p3jtag svf file from the XSTOOLS XSA 3S 100
31. for use in a logic design environment You will need to change the jumper settings only if you are m downloading FPGA bitstreams to your XSA 351000 Board using the XILINX IMPACT software m changing the power sources for the XSA 351000 supply voltages Setting On default Off 1 2 9V 2 3 PS 2 1 2 XI 2 3 XS default N A e Table 2 Jumper settings for XSA 351000 Boards Purpose A shunt should be installed if the 2 5V supply voltage is derived from the 3 3V supply The shunt should be removed if the 2 5V supply voltage is applied from an external source through pin 22 of the XSA 351000 Board labeled 2 5V at the lower right hand corner of the board The shunt should be installed on pins 1 and 2 if the board supply voltages are derived from the an external 5V 9V DC supply The shunt should be installed on pins 2 and 3 if the board supply voltages are derived from the 5V supply applied through the PS 2 keyboard mouse connector J4 The shunt should be installed on pins 1 and 2 XI if the XSA 351000 Board is to be downloaded using the XILINX iMPACT software The shunt should be installed on pins 2 and 3 XS if the XSA 351000 Board is to be downloaded using the XESS GXSLOAD software This is a header that provides access to the 5V and GND references on the board No shunt should be placed on this header Testing Your XSA 351000 Board Once your XSA 351000 Board is installed and t
32. he FPGA configuration pins so it can pass bitstreams from the parallel port to the FPGA The actual configuration data is presented to the FPGA on the same 8 bit bus that also connects to the Flash and seven segment LED The CPLD also drives the configuration pins CCLK PROGRAMA CSF and WR that sequence the loading of a bitstream into the FPGA The CPLD can monitor the status of the bitstream download through the INIT DONE and BSY DOUT pins The CPLD also has access to the FPGA s JTAG pins TCK TMS TDI and TDO The TMS TDI and TDO pins share the connections with the BSY DOUT CSF and WR pins The CPLD can be programmed with an interface that allows configuration of the FPGA through the JTAG pins using the XILINX MPACT software see this for more details Jumper J9 allows the connection of status pin S7 to the general purpose CPLD pin that also drives status pin S5 This is required by the MPACT software so it can check for the presence of the downloading cable XSA 351000 BOARD V1 0 USER MANUAL 27 Parallel Port 2 PPDO 3 PPD 4 PPD2 5 6 PPD4 7 PPD5 8 PPD6 9 PPD7 PPC3 PPC2 PPC PPS7 4 PPS5 lt PPS4 lt PPS3 lt PPCO PPS6 lt PPD3 After the FPGA is configured with a bitstream and the DONE pin goes high the CPLD switches into a mode that connects the parallel port data and status pins to the FP
33. he jumpers are in their default configuration you can test the board using the GUl based GXSTEST utility as follows XSA 351000 BOARD V1 0 USER MANUAL 9 You start GXSTEST by clicking on the ESU icon placed on the desktop during the XSTOOLS installation This brings up the window shown below Board Type x58 351000 TEST Port LPT E xit Next you select the parallel port that your XSA 351000 Board is connected to from the Port pulldown list GXSTEST starts with parallel port LPT1 as the default but you can also select LPT2 or LPT3 depending upon the configuration of your PC After selecting the parallel port pick the XSA 351000 item in the Board Type pulldown list Then click on the TEST button to start the testing procedure GXSTEST will configure the FPGA to perform a test procedure on your XSA 351000 Board Within thirty seconds you will see a O displayed on the LED digit if the test completes successfully Otherwise an E will be displayed if the test fails A status window will also appear on your PC screen informing you of the success or failure of the test If your XSA 351000 Board fails the test you will be shown a checklist of common causes for failure If none of these causes applies to your situation then try some of the solutions listed in the XSTOOLS README TXT file If you cannot get your board to pass the test even after taking these steps then contact XESS Corp for further assistance As a result of testing
34. istors on the board and prevent it from functioning correctly Therefore you have to set the bitstream generation options to disable these internal resistors This is done by right clicking on the Generate Programming File item in the Processes pane and selecting Properties from the pop up menu Processes for Source and gate behavioral Add Existing Source EI Create New Source _ Gi Design Entry Utilities ns Gi User Constraints ns k Sunthesize ST re E Implement Desig WC Process Wet XSA 351000 BOARD V1 0 USER MANUAL Run Rerun Rerun All Shop Open without Updating 11 Then select the Configuration Options tab in the Process Properties window and change all the pin settings to float Then click on the OK button The internal pullup and pulldown resistors will now be disabled in the bitstream generated for this project Process Properties E E x Float JTAG Pin TMS Unused IOB Pins leek Cade 12 Tiet Havandarimali Cancel Default Help Float Downloading Bitstreams into the FPGA and CPLD Downloading Using GXSLOAD As you develop and test a logic design you will usually connect the XSA 351000 Board to the parallel port of a PC and download the configuration bitstream each time you make changes You can download a bitstream into your XSA 351000 Board using the GXSLOAD utility XSA 351000 BOARD V1 0 USER MANUAL 12
35. or graphics on a VGA monitor through this port Parallel Port This is the main interface for passing configuration bitstreams and data to and from the XSA 351000 Board XSA 351000 BOARD V1 0 USER MANUAL 20 Parallel Port 2 PPDO da PPD2 5 PPD3 6 PPD4 Te 8 9 gt o PPD6 PPD7 Te PPC2 PPC1 PPS7 lt PPS5 lt PPS4 4 PPS3 lt PPCO PPS6 lt Prototyping Header Many of the FPGA I O pins are connected to the 84 pins on the bottom of the XSA 351000 Board that are meant to mate with solderless breadboards or an XST 3 Board H PPD1 a A17 AO PPD5 D15 D8 D7 DO PPC3 e Figure 3 XSA 351000 Board programmer s model Programmable logic FPGA and CPLD VV The XSA 351000 Board contains two programmable logic chips A 1 000 000 gate XILINX Spartan3 FPGA in a 256 pin BGA package XC3S1000 41256 is the main repository of programmable logic on the XSA 3S1000 Board A XILINX XC9500XL CPLD XC9572XL 10VG64 is used to manage the 015 DO DAT BAO A12 AO RAS CAS CS WE DQMH DQML CKE CLK CLK PS 2 Port DATA VGA Connector RED2 REDO GREEN2 GREENO BLUE2 BLUEO HSYNC
36. or write the Flash To avoid contention the CPLD is programmed to release control of all Flash address data control lines whenever the FPGA lowers the Flash CE line When the Flash is disabled by raising CE the I O lines connected to the Flash are available for general purpose communication between the FPGA and the CPLD RESP NA oo To E SW1 2 SW1 1 XSA 351000 BOARD V1 0 USER MANUAL Seven Segment LED The XSA 351000 Board has a 7 segment LED digit for use by the FPGA or the CPLD Segments of the LED glow when a logic high level is applied to them The LED shares the same eight bit data bus that interconnects the CPLD the FPGA configuration port and the lower byte of the Flash RAM data bus The connections between the LED segments and the data bus are shown below We use two distinct labelings of the LED segments in our documentation and design examples so we show the connections for both FPGA DIN DO FPGA DIN DO FPGA D1 FPGA D1 FPGA D2 FPGA D2 FPGA D3 FPGA D3 FPGA D4 FPGA D4 FPGA D5 FPGA D5 FPGA D6 FPGA D6 FPGA D7 FPGA D7 DIP Switches and Pushbuttons Four DIP switches are attached to the FPGA When closed ON each switch pulls the connected pin ofthe FPGA
37. ormat pulldown list XSA 351000 BOARD V1 0 USER MANUAL 16 Then click on the file icon and drag 8 drop it into any folder This activates the following seguence of steps 1 The CPLD and FPGA on the XSA 351000 Board are reprogrammed to create an interface between the Flash device and the PC parallel port 2 The Flash data between the high and low addresses inclusive is uploaded through the parallel port 3 The uploaded data is stored in a file named FLSHUPLD with an extension that reflects the file format X gxsload E E Board Type esa 351000 5 Load Pott Ba FPGASCPLD Flash EEPROR L High Address 043FFFF Low Address en Upload Format HEX The uploaded data can be stored in the following formats MCS Intel hexadecimal file format This is the same format generated by the promgen utility with the p mcs option HEX Identical to MCS format EXO 16 Motorola S record format with 16 bit addresses suitable for 64 KByte uploads only EX0 24 Motorola S record format with 24 bit addresses This is the same format generated by the promgen utility with the p exo option EX0 32 Motorola S record format with 32 bit addresses XESS 16 XESS hexadecimal format with 16 bit addresses This is a simplified file format that does not use checksums XESS 24 XESS hexadecimal format with 24 bit addresses XESS 32 XESS hexadecimal format with 32 bit addresses XSA 351000 BOAR
38. pEn4 D6 I0 L27P 0 proTo2g EL IO L20N 7 ppgT027 E2 IO L2eP 7 spRAM A4 E3 IO L19N 7 URB Ra ag Ef 10 L21P 7 1 24 ES UCCINTEES spRAM A3 ES_I0_L27N_ 12 50 EL_UCCAUXBF1 pporoz2 2 IO L22N 7 pproro 9 3 10 L22P 7 pporozg Et 10_L21N_7 proro 3 E8 Io L23P 7 END ES GNDEFS PROTO36 8L IO L40P 7 proro3 S2 10862 PROTO34 83 I0 L24N 7 proro33 S4_I0_L24P_7 proro31 55 10 L23N 7 43 3 BE UCCO 7866 PROTO39 H4_I0_L4 N_7 UREF_7 gnp H2 GNDEH2 PROTO38 H3 IO L39N 7 proro37 Ho 10 L39P 7 3 3U HS UCCO 7eH5 a a H6 _UCCO_7eH6 PROTO4B IL IO L40P 6 UVRBRdg044 I2 IO L40N e ppoT042 J3__10_L39P_6 s 1 4 J4 IO L39N 6 3 3u J5_UCCO_6eJ5 3 3u J6_UCCO_6eJ6 PROTO43 KL IOBK1 eu K2 10 L24P 6 pi asu aig K3 10_124N_6 RE eua K4 10123P_6 prorosp KS 10 L23N 6 3 30 KE UCCO 68K6 42 54 LL UCCAUXBLA proros4 L2_I0_L22P_6 ppoto4g L3 I0 L22N 6 pporo4g L4_10_L21P_6 ppoT057 L5 10 L21N 6 END L GNDeL6 PROTO47 L_IO_L28P_6 proro4g 2 IO L20N 6 proros MS_IO_L19P_6 prorosg U IO L18N 6 4 24 MS UCCINTEMS epga_pz 6 10 L28P 5 07 PROTO59 NL IO L17P 6 VRERdrose N2_10_L17N_6 ppoToga NI 10 116P 6 1 0y N4 UCCINTEN4 pp As ag NS 10645 FPGA D6 N6 IO L28N 5 D6 prorosg PL IO L81P 6 UR g 7064 P2 IO L16N 6 FLASH OE P510_127P_5 pLas p44 P6 I0_L29P_5 UREF_5 PROTO42 RL IO LBIN 6 URP 6 gyp R2 GNDER2 FLASH CE
39. r web site at http Avww xilinx com support support htm If you need help using the WebPACK software to create designs for your XSA 351000 Board then check out this futorial The XSA 351000 is not 5V tolerant Do not connect 5V logic signals to the prototyping header Do not insert your XSA 351000 Board into an XST 1 or XST 2 x XStend Board These versions of the XStend Boards contain some 5V logic The XSA 351000 Board requires an external power supply to operate It does not draw power through the downloading cable from the PC parallel port If you are connecting a 5V 9V DC power supply to your XSA 351000 Board please make sure the center terminal of the plug is positive and the outer sleeve is negative Do not power your XSA 351000 Board with a battery This will not provide enough current to insure reliable operation of the XSA 351000 Board Even if vou have experience with the XILINX software tools please read this on setting the bitstream generation options for the XSA 3S1000 Board XSA 351000 BOARD V1 0 USER MANUAL 4 Packing List Here is what you should have received in your package m an XSA 3S1000 Board m a6 cable with a 25 pin male connector on each end m an XSTOOLS CDROM with software utilities and documentation for using the XSA 351000 Board XSA 351000 BOARD V1 0 USER MANUAL 5 Installation Installing the XSTOOLS Utilities and Documentation XILINX currently provides the Web
40. the XSA 351000 Board the CPLD is programmed with the standard parallel port interface found in the XSTOOLS XSA 3S1000 dwnidpar svf bitstream file This is the interface that should be loaded into the CPLD when you want to use it with the GXSLOAD utility Setting the XSA 351000 Board Clock Oscillator Frequency Unlike previous versions of the XSA Board your XSA 351000 Board has a fixed frequency oscillator of 100 MHz The GXSSETCLK utility cannot be used to change the frequency of the clock sent to the FPGA and CPLD You can lower the clock frequency b placing a clock divider circuit in the FPGA or CPLD See the section on the XSA 351000 Board clock circuitry for more details XSA 351000 BOARD V1 0 USER MANUAL 10 Programming This section will show you how to download logic designs into the FPGA and CPLD of your XSA 351000 Board and how to download and upload data to and from the SDRAM and Flash devices on the board Generating Bitstreams for the FPGA Before downloading a bitstream to the FPGA on your XSA 351000 Board you will use the XILINX development software to generate the BIT file Steps for doing this are given in the XILINX documentation but there is one detail that is specific to your board The Spartan3 FPGA has relatively low impedance internal pullup and pulldown resistors on its pins that become active after the FPGA is configured These resistors can overpower the 4 7KQ external pullup and pulldown res
41. tions This describes an SDRAM controller that makes the SDRAM appear like a simple static RAM to the rest of the circuitry in the FPGA FPGA D15 DO UDQM LDQM A12 AU BA1 BAO RAS CAS CS WE CKE GCLK The CPLD and FPGA connect to a 16 Mbit Flash RAM S29AL016M10TAI020 that operates in either byte mode 2M x 8 or word mode 1M x 16 The CPLD uses the byte mode as it only has access to the lower eight bits of the Flash data bus while the FPGA connects to the entire 16 bit data bus and can select either mode using the BYTE control line The FPGA has access to the entire Flash address bus so it can read or write any location For this reason the FPGA is used to pass data between the parallel port and the Flash when GXSLOAD downloads uploads files to from the Flash The CPLD however is not connected to the upper two address lines so it can only access a quadrant of the Flash The guadrant is selected by two DIP switches connected to the upper address lines On power up in stand alone mode the CPLD configures the FPGA with a bitstream retrieved XSA 351000 BOARD V1 0 USER MANUAL 23 from the selected guadrant so the DIP switches can be used to select between four separate bitstreams stored in the Flash See the on the XSA Board Flash configuration circuit for more details on this After power up any application circuit loaded into the FPGA can read and

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