Reed-Solomon Encoder IP User`s Guide
Contents
1. 505 161 504 457 24 149 reeds enco 1 0034 DVB 84 273 240 24 N A 155 reeds enco 1 004 Ipc ATSC 130 417 307 24 N A 157 1 Performance and utilization characteristics are generated using LFX125B 04F256C in Lattice ispLEVERE v 3 x software The evaluation version of this IP core only vvorks on this specific device density package and speed grade Table 7 Parameters for Typical Configurations Name CCSDS DVB ATSC OC192 n 225 204 207 255 k 223 188 187 239 s 8 8 8 8 f 391 285 285 285 rootspace 11 1 1 1 gstart 112 0 0 0 nreg 1 1 1 1 latency 3 3 3 3 algorithm 1 1 1 1 handshake 0 0 0 0 Supplied Netlist Configurations The Ordering Part Number OPN for all configurations of the Reed Solomon Encoder core targeting ispXPGA devices is REEDS ENCO XP N1 Table 6 lists the netlists that are available in the Evaluation Package which can be downloaded from the Lattice web site at www latticesemi com You can use the IPexpress software tool to help generate new configurations of this IP core IPexpress is the Lattice IP configuration utility and is included as a standard feature of the ispLEVER design tools Details regarding the usage of IPexpress can be found in the IPexpress and ispLEVER help system For more information on the ispLEVER design tools visit the Lattice web site at www latticesemi com software Lattice Semiconductor Appendix for LatticeECP and2. i Xi XO DN6 DNS d out iA D6 i D5 A D4 iA DBP A C3 A C2 i C1 status rdy dvalid Figure 8 explains the timing of an RS 7 3 double pipelined encoder with enab1e de asserted during the opera tion of the encoder The handshaking signal dvalid indicates the data on d out is invalid while the encoder maintains its state during the time enable is lovv Figure 8 Timing of an RS 7 3 Double Pipelined Encoder vvith enable De asserted enable J byp m 1 1 1 1 1 1 1 1 1 1 i din B De D5 D4 XX i Xa x XO Dne DNS j d out ih D6 j D5 ih D4 il D4 il C3 ih C2 iA C1 status rdy dvalid Lattice Semiconductor Reed Solomon Encoder User s Guide Figure 9 explains the timing of an RS 7 3 double pipelined encoder vvith start re asserted during the operation of the encoder The handshaking signal rdy indicates the encoder is ready to receive a new set of data when start S re asserted during encoding Figure 9 Timing of an RS 7 3 Double Pipelined Encoder with start Re asserted clk rstn start enable byp dun i DS l DA IC xa V pe i Ds D O d out i D6 il DS il 4 D5 il D4 status rdy dvalid Signal Definitions Table 1 shows the input and output signals for the Reed Solomo
3. illustrates the functional modules and internal bus structure used in the Reed Solomon Encoder core Figure 1 Reed Solomon Encoder Core Block Diagram Multiplier Array din o hz Adder Array a 9 9 pr o Remainder Array N d_out v rstn gt enable 4 Control yp gt status start gt gt dvalid clk gt gt rdy Multiplier Array The Multiplier Array does the Galois field multiplication between the generator coefficients and the addition of input data and feedback modulo 2 This multiplication is an optimized multiplication between the generator coefficients which are constants and the input of the Multiplier Array This optimization is done when processing the core Adder Array The Adder Array performs addition modulo 2 on the data from the previous element of the Remainder Array and the result of the corresponding Galois field multiplication from the Multiplier Array The outputs from the Adder Array are latched into the Remainder Array on each clock cycle Lattice Semiconductor Reed Solomon Encoder User s Guide Remainder Array The Remainder Array is a shift register array It stores the remainder polynomial after the polynomial division The remainder polynomial becomes the check symbols once all information symbols have been processed The Remainder Array shifts in t
4. 4 x94 x 4 1 285 9 xo x44 529 10 x 4 xP 1 1033 11 x 1 2053 12 x x x X 4179 Lattice Semiconductor Reed Solomon Encoder User s Guide Reed Solomon Encoder Core Design Flovv The Reed Solomon IP Core can be implemented using various methods The scope of this document covers only the push button Graphical User Interface GUI flow Figure 10 illustrates the software flow model used when designing with the Reed Solomon Encoder core Figure 10 Lattice IP Core Implementation Flow Install and launch ispLEVER software Obtain desired IP package download Core Evaluation package or purchase IP package Protected Simulation Model Install IP package x IP Core Netlist Perform functional simulation vvith the provided core model gt v Synthesize top level design vvith the IP black box declaration 4 v Place and route the design v Run static timing analysis v Done IPexpress M The Lattice IP configuration tool IPexpress is incorporated in the ispLEVERE software IPexpress includes a GUI for entering the required parameters to configure the core For more information on using IPexpress and the ispLEVER design software refer to the software help and tutorials included with ispLEVER For more information on ispLEVER see the Lattice web site at www latticesemi com software Functional RTL Simu
5. Lattice Semiconductor EELEE Corporation Reed Solomon Encoder User s Guide October 2005 ipug05_03 0 Lattice Semiconductor Reed Solomon Encoder User s Guide ntroduction Lattice s Reed Solomon Encoder core provides an ideal solution that meets the needs of today s Reed Solomon applications The Reed Solomon Encoder core provides a customizable solution allovving forvvard error correction in many design applications This core allovvs designers to focus on the application rather than the Reed Solomon Encoder resulting in faster time to market Reed Solomon codes are vvidely used in various applications for forvvard error correction and detection Lattice s Reed Solomon Encoder core is a fully synchronous core developed in conjunction with Lattice s Reed Solomon Decoder core to provide a complimentary pair For more information on Lattice products refer to the Lattice web site at www latticesemi com This user s guide illustrates the functionality and implementation of the Reed Solomon Encoder to provide encod ing on any data transmission It also describes a method for achieving the maximum level of performance The Reed Solomon Encoder Core This section describes the functionality of the Reed Solomon Encoder core It includes information on how to cus tomize the Reed Solomon Encoder core as well as the details necessary to design an application that will interface with the Reed Solomon Encoder core Figure 1
6. LatticeEC FPGAs Table 8 Performance and Resource Utilization Reed Solomon Encoder User s Guide sysMEM fmax Parameter File Mode SLICEs LUTs Registers I Os EBRs MHz reeds enco 2 1 001 lpc OC192 147 252 217 24 N A 206 reeds enco e2 1 002 lpc CCSDS 280 460 413 24 N A 194 reeds enco e2 1 003 Ipc DVB 149 253 220 24 N A 205 reeds enco e2 1 004 Ipc ATSC 196 320 279 24 N A 201 1 Performance and utilization characteristics are generated using LFEC20E 5F672C in Lattice s ispLEVER v 4 1 software When using this IP core in a different device density package or speed grade performance may vary Table 9 Parameters for Typical Configurations Name CCSDS DVB ATSC OC192 n 255 204 207 255 k 223 188 187 239 s 8 8 8 8 f 391 285 285 285 rootspace 11 1 1 1 gstart 112 0 0 0 nreg 1 1 1 1 latency 3 3 3 3 algorithm 1 1 1 1 handshake 0 0 0 0 Supplied Netlist Configurations The Ordering Part Number OPN for all configurations of the Reed Solomon Encoder core targeting LatticeECP EC devices is REEDS ENCO E2 N1 Table 8 lists the netlists that are available in the Evaluation Package which can be downloaded from the Lattice web site at www latticesemi com You can use the IPexpress software tool to help generate new configurations of this IP core IPexpress is the Lattice IP configuration utility and is included as a standard feature of the ispLEVE
7. R design tools Details regarding the usage of IPexpress be found in the IPexpress and ispLEVER help system For more information on the ispLEVER design tools visit the Lattice web site at www latticesemi com software
8. The handshaking signal rdy indicates the encoder is ready to receive a new set of data when start is re asserted during encoding Figure 5 Timing of an RS 7 3 Single Pipelined Encoder with start Re asserted rstn start PA A enable byp din N D6 j D5 Yy D4 X3 pe y ps na i xa xa Xi deli 1 D6 D5 y D4 C3 06 05 y D4 y C3 status rdy HEH m dvalid Figure 6 illustrates the timing of an RS 7 3 double pipelined encoder during normal operation The handshake signals status rdy and dvalid display how the encoder communicates with the source and destination devices Figure 6 Timing of an RS 7 3 Double Pipelined Encoder rsin start j Ji i enable yp 1 1 1 1 1 1 1 din 1 D6 D5 D4 xa x DNe DNS DNA status a rdy dvalid Lattice Semiconductor Reed Solomon Encoder User s Guide Figure 7 shovvs the timing of an RS 7 3 double pipelined encoder vvith byp asserted during the operation of the encoder The handshaking signals are identical to normal operation but the output is shifted due to the extra bypass data vvhich does not require check symbols Figure 7 Timing of an RS 7 3 Double Pipelined Encoder vvith byp Asserted start enable J byp N d n j De il Dsi D4 DBP X3 il
9. ce and utilization characteristics for OR4E02 2BA352 When using other devices performance may vary Table 5 Parameters for Typical Configurations Name CCSDS DVB ATSC OC192 n 255 204 207 255 k 223 188 187 239 5 8 f 391 285 285 285 rootspace 11 1 1 1 gstart 112 0 0 0 nreg 1 1 1 1 latency 3 3 3 3 algorithm 1 1 1 1 handshake 0 0 0 0 Supplied Netlist Configurations The Ordering Part Number OPN for all configurations of the Reed Solomon Encoder core targeting ORCA Series 4 devices is REEDS ENCO 04 N1 Table 4 lists the netlists that are available in the Evaluation Package which can be downloaded from the Lattice web site at www latticesemi com You can use the IPexpress software tool to help generate new configurations of this IP core IPexpress is the Lattice IP configuration utility and is included as a standard feature of the ispLEVER design tools Details regarding the usage of IPexpress be found in the IPexpress and ispLEVER help system For more information on the ispLEVER design tools visit the Lattice web site at www latticesemi com software Lattice Semiconductor Appendix for ispXPGA FPGAs Table 6 Performance and Resource Utilization Reed Solomon Encoder User s Guide ispXPGA sysMEM Parameter File Mode PFUs LUTs Registers I Os EBRs fmax MHz reeds_enco_xp_1_001 lpc OC192 86 273 248 24 N A 166 reeds enco 1 0021
10. describes how to run synthesis using Synplify outside the ispLEVER Project Navigator 1 Createanew working directory for synthesis 2 Launch the Synplify synthesis tool 3 Startanew project and add the specified files in the following order source reeds enco 04 1 00x params v source orca4_synplify v source pll_orca v source reeds_enco_04_1_00x v source lt top level RTL source gt v Lattice Semiconductor Reed Solomon Encoder User s Guide 8 Note lt top level RTL sources could be the user s top level design or the top level source top rsenc pll v file in the source directory of the downloaded package In the Implementation Options select a target device 4E02 speed grade 2 and package BA352 Specify an EDIF netlist filename and EDIF netlist output location in the Implementation Options This top level EDIF netlist will be used during place and route Be sure the IP core reeds enco 04 1 00x is instantiated inside top level RTL source file In the Implementation Options set the following Fanout guide 500 Enable FSM compiler Enable resource sharing e Set the global frequency constraint to 195MHZ Select Run Synthesis Using LeonardoSpectrum The step by step procedure provided below describes how to run synthesis using LeondardoSpectrum outside the ispLEVER Project Navigator 1 2 3 4 5 8 9 Create a new working directory for synthesis Launch the LeonardoSpectrum synth
11. ed in Table 2 Table 3 lists the default field polynomial for a given symbol width Table 2 Reed Solomon Encoder Parameter Descriptions Name Value Default Description n 3 4095 255 Number of symbols k 1 4093 239 Number of information symbols 5 3 12 8 Symbol vvidth f 11 8191 See Table 3 Decimal value of the field polynomial rootspace 1 65535 1 Root spacing of the generator polynomial The value of rootspace must satisfy the following equation GCD rootspace 28 1 1 GCD is Greatest Common Divisor gstart 0 65535 0 Offset value of the generator polynomial The starting value for the first root of the generator polynomial is calculated as rootspace gstart inreg 0 1 1 0 the inputs will not be registered 1 the inputs will be registered latency 2 3 3 2 the input on d_in will take 2 clock cycles to reach d_out 3 the input on d_in will take 3 clock cycles to reach d_out algorithm 0 1 1 Selects between two different multiplication algorithms Used to improve timing results handshake 0 1 0 1 the core will be a non continuous core configuration 0 the core will be a continuous core configuration rdy and dvalid vill be used in non continuous configuration only Table 3 Reed Solomon Encoder Default Field Polynomial Symbol VVidth Default Field Polynomial Decimal Value 3 x x 1 11 4 x x 1 19 5 xo x 1 37 6 xo4 x41 67 7 x x 1 137 8 x84 x4
12. esis tool Start a new project and select Lattice device technology ORCA 4E Set the source directory as the working directory Open the specified files in the following order source reeds enco 04 1 00x params v source lt top level RTL source gt v source pll_orca v source reeds_enco_04_1_00x v Note lt top level RTL source gt could be users top level design or the top level source top_rsenc_pll v file in the source directory of the downloaded package Set the synthesis directory created in step 1 as the path where you would like to save the output netlist Specify an EDIF netlist filename for the output file This top level EDIF netlist will be used during place and route Be sure the IP core reeds enco 04 1 00x is instantiated inside top level RTL source file Select Run Flow Place and Route Once the EDIF netlist is generated the next step is to import the EDIF into the Project Navigator The step by step procedure provided below describes how to perform place and route in ispLEVER for an ORCA device 1 2 3 Create a new working directory for place and route Start a new project assign a project name and select the project type as EDIF Select an ORCA target device with 2 speed grade and BA352 package Lattice Semiconductor Reed Solomon Encoder User s Guide 10 11 12 13 Copy the following files to the place and route working directory a par reeds_enco_04_1_00x ng
13. he data from the Adder Array until no information symbols remain When all the informa tion symbols have been received the polynomial multiplication stops and the contents of the Remainder Array are output to d out Control Block The control block generates all control signals and determines the state of the Reed Solomon Encoder The inputs control the state of the encoder The control signals from the control block are sent through the control bus to deter mine when data should be transmitted to the encoder Timing Diagrams The illustrated timing examples utilize a non continuous RS 7 3 code The timing remains the same whether the core is continuous or non continuous However when the core is continuous the rdy and dvalid signals are not used Figure 2 illustrates the timing of an RS 7 3 single pipelined encoder during normal operation The handshake sig nals status rdy and dvalid display how the encoder communicates with the source and destination devices Figure 2 Timing of an RS 7 3 Single Pipelined Encoder ek L L 4 xf L L X L L Xi rstn start 1 L T T enable byp din BB pe D5 D4 xs x XO X DN61 DNS DN4 dout i i Deo be b Ge e ek ne0 qi status rdy dvalid Lattice Semiconductor Reed Solomon Encoder User s Guide Figure 3 shovvs the timing of an RS 7 3 single pi
14. lation Under ModelSim PC Platform Note The following procedures are shown using the ORCA Series 4 version of the Reed Solomon Decoder core For other device versions refer to the Readme release notes included in that evaluation package Once the Reed Solomon Encoder core has been downloaded and unzipped to the designated directory the core is ready for evaluation The functional simulation of the RS Encoder core involved developing a verification environ ment that supports a very comprehensive test suite Lattice Semiconductor Reed Solomon Encoder User s Guide A simulation script file is provided in the eval directory for RTL simulation The script file eval sim rsenc do uses pre compiled models provided vvith this package The pre compiled library of models is located in the directory reeds 04 1 O0x orca4 ver1 3 lib modelsim vvork Simulation Procedures 1 Launch ModelSim 2 Using the main GUI change the directory location Select File gt Change Directory gt reeds enco 04 1 00x orca4 ver1 3 eval simulation 3 Execute lt Modelsim macro name gt do Select Macro gt Execute Macro gt scripts eval sim rsenc do The functional simulation for IP cores is currently not applicable with the OEM version of ModelSim embedded in the ispLEVER 3 0 software For more information on how to use ModelSim please refer to the ModelSim User s Manual Core Implementation Users can instantiate the IP co
15. n Encoder core Refer to the ispLEVER Software User s Manual for additional information Table 1 Reed Solomon Encoder Signals Active Signal Name I O Type State Signal Description d_in s 1 0 Input N A Input data rstn Input Low Asynchronous reset input enable Input High Enables the encoder to process data on d_in When low the input data is ignored and d_out holds its state byp Input High Indicates the data on d_in should pass directly through to d_out after the latency This signal is ignored if enable is low start Input High Indicates that the data on d_inis the first information symbol of a new code word This signal is ignored if byp is high or enable is low clk Input Rising Edge Master clock input d_out s 1 0 Output N A Output data status Output High Indicates the information symbols are present on d_out or byp is asserted dvalid Output High Indicates valid data on d_out Not available with continuous configuration rdy Output High Indicates the encoder is ready to receive data Active when rstn is asserted or when ready to receive data or start is asserted Inactive when sufficient data has been received and check symbols are being calculated Not available with continuous configuration Lattice Semiconductor Reed Solomon Encoder User s Guide Reed Solomon Encoder Parameters The Reed Solomon Encoder has several parameters that allovv the core to be configured in different modes list
16. o b 45 enco 04 1 00x prf c The top level EDIF netlist generated from running synthesis Rename the reeds enco 04 1 file in step 4 to match the project name For example if the project name is demo then the prf file must be renamed to demo prf The preference file name must match that of the project name mport the EDIF netlist into the project In the ispLEVER Project Navigator select Tools gt Timing Checkpoint Options The Timing Checkpoint Options window will pop up In both Checkpoint Options select Continue In the ispLEVER Project Navigator highlight Place amp Route Design with a right mouse click select Properties Set the following Properties Placement Iterations 1 Placement Save Best Run 1 e Placement Iteration Start Point 20 Routing Resource Optimization 5 e Routing Delay Reduction Passes 2 Routing Passes 15 Placement Effort Level 5 All other options remain at their default values The properties shown above are the settings for OC192 mode Each configuration has its own properties settings For the appropriate settings for specific configuration please refer to the readme htm that located in the downloaded package Select the Place amp Route Trace Report in the Project Navigator to execute Place and Route and generate a timing report for ORCA If the fmax for the core does not meet the required static timing then proceed to step 11 Otherwise j
17. pelined encoder vvith byp asserted during the operation of the encoder The handshaking signals are identical to normal operation but the output is shifted due to the extra bypass data vvhich does not require check symbols Figure 3 Timing of an RS 7 3 Single Pipelined Encoder vvith byp Asserted rmm r XY A A fx rus YA TO 1 1 j 1 J 1 1 j 1 clk j __ U 1 __ L __ f Of __ __ rstn start enable Ain bs iN D5 D4 ih DBP l ih 6 DNS dout iA D6 iA D5 iN D4 iN DBP iA C3 iA C2 iN C1 iN 0 status rdy dvalid Figure 4 explains the timing of an RS 7 3 single pipelined encoder vvith enable de asserted during the operation of the encoder The handshaking signal dvalid indicates the data on d out is invalid vvhile the encoder main tains its state during the time enable is lovv Figure 4 Timing of an RS 7 3 Single Pipelined Encoder vvith enable De asserted clk rstn start t j j j 1 enable byp d in B R pe os pa xx xa x x xo Dne DNS d out D6 i D5 j D4 A DA C3 A C2 i C1 A Co status rdy dvalid Lattice Semiconductor Reed Solomon Encoder User s Guide Figure 5 explains the timing of an RS 7 3 single pipelined encoder vvith start re asserted during the operation of the encoder
18. re to implement it into their system design The following Verilog source files for Reed Solomon Encoder core are provided reeds enco 04 1 00x v for the Reed Solomon Encoder core top RTL source e top rsenc pll v for top level source Users can use the core top RTL as a black box to the system designs All default signal names in the top level RTL source file must be replaced with real signal names from the system design Black Box Consideration Since the core is delivered as a gate level netlist the synthesis software will not re synthesize the internal nets of the core In the synthesis process the instantiated core must be declared as a black box The ispLEVER software automatically detects the provided netlist of the instantiated IP core in the design For more detailed information regarding Synplify s black box declaration please refer to the Instantiating Black Boxes in Verilog section of the Synplify reference manual The core implementation consists of synthesis and place and route sections Each of the sections is described below Two synthesis tools Synplicity Synplify and LeonardoSpectrum are included in the ispLEVER software for seamless processing of designs The current IP cores are being tested with ED F flow The following are the step by step procedure for each synthesis tool to generate an EDIF netlist containing the IP core as a black box Synthesis Using Synplicity Synplify The step by step procedure below
19. ump to step 13 Select the Cycle Stealing process in the Project Navigator Select the Place amp Route Trace Report process again to generate a new timing report The Timing Summary section should indicate no timing errors VVhen you open the timing report it is possible you might see some timing violations due to over constraint Do the follovving steps to obtain a correct timing report Copy the file post route trace prf that is located in directory reeds 04 1 00x orca4 ver1 0 par to the place and route working directory in step 1 Open a DOS shell and change its directory to the working directory in step 1 Type trce v 1 c o post route trace tvvr lt your project name gt ncd post route trace prf The new timing report is generated in post route trace twr Technical Support Assistance Hotline 1 800 LATTICE North America 1 503 268 8001 Outside North America e mail techsupport latticesemi com Internet www latticesemi com Lattice Semiconductor Reed Solomon Encoder User s Guide Appendix for ORCA Series 4 FPGAs Table 4 Performance and Utilization ORCA 4 sysMEM Parameter File Mode PFUs LUTs Registers I Os EBRs fmax MHz reeds enco 04 1 001 lpc OC192 58 210 194 24 N A 168 reeds 04 1 002 ipc CCSDS 88 327 323 24 N A 156 reeds enco 04 1 003 lpc DVB 58 201 194 24 N A 167 reeds 04 1 004 lpc ATSC 71 233 226 24 N A 166 1 Performan
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