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Xilinx UG201 Virtex-5 FPGA ML555 Development Kit for PCI and

1. poss Signal FPGA Pin m Mina Signal FPGA Pin bees 117 DDR2_VCC1V8 NC 118 DDR2_VCC1V8 NC 119 No connect NC 120 No connect NC 121 GND NC 122 GND NC 123 DO32 AB28 In Out 124 DO36 AK26 In Out 125 DQ33 AA28 In Out 126 DQ37 AF28 In Out 127 GND NC 128 GND NC 129 DOS4_B AK27 In Out 130 DM4 AF24 Out 131 DQS4 AK28 In Out 132 GND NC 133 GND NC 134 DQ38 AE28 In Out 135 DQ34 AG28 In Out 136 DQ39 AJ27 In Out 137 DQ35 AH28 In Out 138 GND NC 139 GND NC 140 DQ44 AC25 In Out 141 DQ40 AG25 In Out 142 DQ45 AC24 In Out 143 DO41 AG27 In Out 144 GND NC 145 GND NC 146 DQS5 B AJ26 In Out 147 DM5 AD24 Out 148 DOS5 AH27 In Out 149 GND NC 150 GND NC 151 DQ42 AE27 In Out 152 DQ46 AD26 In Out 153 DQ43 AE26 In Out 154 DQ47 AD25 In Out 155 GND NC 156 GND NC 157 DO48 AN14 In Out 158 DQ52 AN13 In Out 159 DQ49 AP14 In Out 160 DQ53 AM13 In Out 161 GND NC 162 GND NC 163 No connect NC 164 CK1 AG10 Out 165 GND NC 166 CK1_B AGI Out 167 DOQS6 B AD11 In Out 168 GND NC 169 DQS6 AD10 In Out 170 DM6 AP12 Out 171 GND NC 172 GND NC 173 DQ50 AB10 In Out 174 DQ54 AAS In Out 175 DO51 AA10 In Out 176 DQ55 AA9 In Out 177 GND NC 178 GND NC 179 DQ56 ACS In Out 180 DQ60 AC10 In Out 181 DQ57 AB8 In Out 182 DQ61 AC9 In Out Virtex 5 FPGA ML555 Development Kit www xilinx com 37 UG201 v1 4 March 10 2008 Chapter 3 Hardware Description Table 3 5 SDRAM Interface Signal Descriptions Continued XILINX
2. pons Signal FPGA Pin FI pas e Signal FPGA Pin 7 a 183 GND NC 184 GND NC 185 DM7 AJ9 Out 186 DQS7_B Aju In Out 187 GND NC 188 DQS7 AKI In Out 189 DQ58 AMI2 In Out 190 GND NC 191 DQ59 AMI1 In Out 192 DQ62 AK9 In Out 193 GND NC 194 DQ63 AF9 In Out 195 SDA AD9 In Out 196 GND NC 197 SCL AES Out 198 GND SA0 NC 199 DDR2 VCCIV8 NC 200 GND SA1 NC Notes 1 DDR2 memory interface signals are connected to FPGA banks 4 17 21 and 22 The FPGA reference voltage Vcco for these banks is 1 8V See the ML555 board schematics on the CD ROM for further information 2 NC no connect 3 Pin 115 S1 B is a no connect because the ML555 board does not support dual rank SODIMMs 38 Power consumption for the DDR2 memory interface is dependent upon the density and speed of DDR2 memory installed in the SODIMM socket Table 3 6 shows approximate 1 8V current consumption requirements by density and transfer rate for Micron Semiconductor SODIMMs supported by the ML555 board Memory data sheet specifications should be consulted to determine specific power requirements for the SODIMM memory devices Higher densities and higher performance SODIMMs are supported however the user must calculate total application power and stay within the PCI and or PCI Express add in card specifications Table 3 6 DDR2 SODIMM Current Consumption versus Data Transfer Rate Memory Density 400 MT s 533 MT s 667 MT s 128 MB 480 mA 720 mA 860
3. pai Signal FPGA Pin peg n Signal FPGA Pin ies 51 DOS2 AA29 In Out 52 DM2 AH29 Out 53 GND NC 54 GND NC 55 DO18 AJ31 In Out 56 DQ22 AJ30 In Out 57 DQ19 AK31 In Out 58 DQ23 AH30 In Out 59 GND NC 60 GND NC 61 DQ24 AA25 In Out 62 DQ28 Y24 In Out 63 DQ25 AA26 In Out 64 DQ29 AA24 In Out 65 GND NC 66 GND NC 67 DM3 AC28 Out 68 DQS3_B AJ29 In Out 69 No connect NC 70 DQS3 AK29 In Out 71 GND NC 72 GND NC 73 DQ26 AB27 In Out 74 DQ30 AB25 In Out 75 DQ27 AC27 In Out 76 DQ31 AB26 In Out 77 GND NC 78 GND NC 79 CKEO AG8 Out 80 No connect NC 81 DDR2_VCC1V8 NC 82 DDR2_VCC1V8 NC 83 No connect NC 84 No connect NC 85 BA2 NC5 AF11 Out 86 No connect NC 87 DDR2_VCC1V8 NC 88 DDR2_VCC1V8 NC 89 A12 AH19 Out 90 All AH20 Out 91 A9 AHI15 Out 92 A7 AG16 Out 93 A8 AG20 Out 94 A6 AH17 Out 95 DDR2_VCC1V8 NC 96 DDR2_VCC1V8 NC 97 A5 AH22 Out 98 A4 AG22 Out 99 A3 AG17 Out 100 A2 AH18 Out 101 A1 AF18 Out 102 AO AE18 Out 103 DDR2_VCC1V8 NC 104 DDR2_VCC1V8 NC 105 A10 AGI5 Out 106 BA1 AH13 Out 107 BAO AH14 Out 108 RAS_B AG13 Out 109 WE_B AF19 Out 110 S0 B AG18 Out 111 DDR2_VCC1V8 NC 112 DDR2_VCC1V8 NC 113 CAS B AH12 Out 114 ODTO AG30 Out 1156 No connect NC 116 No connect NC 36 www xilinx com Virtex 5 FPGA ML555 Development Kit UG201 v1 4 March 10 2008 2 XILINX Table 3 5 SDRAM Interface Signal Descriptions Continued DDR2 SDRAM SODIMM
4. Signal Name FPGA Pin FPGA Bank Bank Vcco Volts Function PCIBUSCLK1 L34 11 3 0 Regional PCI bus applications FPGA_CLK_30MHZ AD32 13 3 0 User defined GPIO2 I10 N V7 GP1O2 I10 P W7 GPIO2 I11 N AF5 GP1O2 H1 P AGS 18 25 User defined LVDS general purpose I O GPIO2_I12_N AF6 interface GP1O2 I12 P AE7 GPIO2 I13 N Y6 GP1O2 I13 P W6 70 www xilinx com Virtex 5 FPGA ML555 Development Kit UG201 v1 4 March 10 2008 XILINX Table 3 26 FPGA Clock Capable I O Connectivity Continued Clock Generation Signal Name FPGA Pin FPGA Bank Bank Vcco Volts Function GPIO1_I10_N E27 GP101_T10_P E26 GPIO1_I11_N F28 GP101_I11_P E28 19 25 User defined LVDS general purpose I O GPIO1_I12_N G28 interface GP101_I12_P H28 GPIO1_I13_N H27 GP101_I13_P G27 GPIO1_I00_N K22 GPIO1_I00_P K23 GPIO1_I01_N H23 GP101_I01_P G23 1 25 User defined LVDS general purpose I O GPIO1_I22_N K12 interface GP101_I22_P K13 GPIO1 I23 N H12 GPIO1 D3 P JA2 GPIO2 I00 N AE23 GPIO2 I00 P AE22 GPIO2 I01 N AG23 GP102_I01_P AF23 2 25 User defined LVDS general purpose I O GPIO2 22 N AE12 interface GP1O2 D2 P AE13 GPIO2 I23 N AG12 GPIO2 D3 P AF13 PO RXC RXCLK H7 Ethernet PHY clocks from daughtercard PU TXC GIXCLK TE 12 2 5 HW AFX BERG EPHY P1 TXC GTXCLK K8 20 2 5 Ethernet PHY clocks from daughtercard Pl RXC RXCLK jo HW A
5. 92 www xilinx com Virtex 5 FPGA ML555 Development Kit UG201 v1 4 March 10 2008 XILINX Table 4 3 FPGA Configuration Pin Listing Continued SelectMAP Interface Pin Number Net Name Direction Pin Type Description M15 FPGA DONE O DONE Active High signal indicating configuration is complete AD15 FPGA BUSY B O DOUT_BUSY Active Low Busy signal AD19 FLASH D0O I IO SelectMAP data bit 0 connected to Platform Flash P15 device AE19 FLASH D10 I IO SelectMAP data bit 1 connected to Platform Flash device AE17 FLASH D20 I IO SelectMAP data bit 2 connected to Platform Flash device AF16 FLASH D30 I IO SelectMAP data bit 3 connected to Platform Flash device AD20 FLASH D4O I IO SelectMAP data bit 4 connected to Platform Flash device AE21 FLASH D50 I IO SelectMAP data bit 5 connected to Platform Flash device AE16 FLASH_D6 I IO SelectMAP data bit 6 connected to Platform Flash device AF15 FLASH D7 I IO SelectMAP data bit 7 connected to Platform Flash device L11 FORCEG2A I IO Input connected from Pin 31 of Platform Flash device L10 WIDE 3A I IO Input connected from Pin 29 of CPLD C13 PCIW ENG O IO Output connected to Pin 33 of CPLD B13 RTR 3A oO IO Output connected to Pin 32 of CPLD B12 CPLD SPARE1C 9 I O IO Spare I O connected to CPLD pin 21 A13 CPLD_SPARE2 24 I O IO Spare I O connected to CPLD pin 22 H
6. For PCI Express applications the ML555 board uses the 12V power rail as the input power to a 12V to 5V DC to DC converter The output of this DC to DC converter then provides the input voltage to most of the voltage regulators on the board The GTP transceiver analog supplies and Vccmr are supplied by the 3 3V input from the system board For PCI and PCI X applications the ML555 board uses the 5V power rail as the input to all voltage regulators on the board The ML555 interface for PCI Express designs supports x1 x4 and x8 lane configurations A 1 lane to 16 lane converter board for PCI Express designs is required to plug an ML555 board into the x1 slots for PCI Express operation These interface connectors are available from Catalyst Enterprises ML555 Board DC Power Regulators 80 The ML555 board contains oncard voltage regulators that provide power for the Virtex 5 FPGA and onboard peripherals see Table 3 34 www xilinx com Virtex 5 FPGA ML555 Development Kit UG201 v1 4 March 10 2008 2 XILINX Table 3 34 ML555 Onboard DC to DC Voltage Converters Voltage Regulators Input Voltage Source ML555 Board Nominal Maximum Reference Output Output DC Power Sink Designator PCI or PCI X Mode2 PCI Express Voltage Current Mode mne a VR10 Not Used Connector 12V 5V 6A p regulators in PCI Input Express mode only DDR2 memory other 1 8V ML555 pe
7. usssuuusssses 86 Chapter 4 Configuration Configuration Modes siu nui ed a CR Ae RAO puted eked exe Gee Dea Ro E e 89 JEAG Chain nein E Ea e p ICA GIC A dac el gea 89 JTAG POft ool 20 ee ee BEA en I PEU RE ee EI a 90 SelectMAP Interface icici ccs bib Re bales 18 a REG ee a wR be ee 91 CPLD Programming Examples sssse en 97 Static Configuration 2s usa 3 cise ES bed DUE VEU ee E e 97 Generic Dynamic Reconfiguration csse nen 98 SelectMAP Clock Selection ussssssssssee ee 100 Platform Flash Image Generation and Programming 101 eun EC 101 Creating a PROM File in Command Line Mode 0 2 0 0 0c cee eee eee 101 iMPACT and PROMGEN Wizard GUI Mode leen 101 Specifying the Xilinx PROM Device 2 cece eee 103 Programming the PROM ccc II en 104 www xilinx com Virtex 5 FPGA ML555 Development Kit UG201 v1 4 March 10 2008 7 XILINX Preface About This Guide This user guide is a description of the Virtex 5 FPGA ML555 Development Kit for PCI and PCI Express designs Complete and up to date documentation of the Virtex 5 family of FPGAs is available on the Xilinx website at http www xilinx com virtex5 Guide Contents This manual contains the following chapters Chapter 1 Introduction e Chapter 2 Getting Started e Chapter 3 Hardware Description e Chapter 4 Configuration Additional Documentation The
8. P33 LVDS P1 Bus Connector for P13 Connector PCI PCI X for PCI Express Designs Designs P5 JTAG Configuration Global CLK SMA J1 USB B User Pushbuttons LEDS J3 SFP1 J4 SFP2 J5 Serial ATA UG201 c3 02 022708 Figure 3 2 Annotated ML555 Board The CD included in the kit contains ML555 board schematics and layout files 22 www xilinx com Virtex 5 FPGA ML555 Development Kit UG201 v1 4 March 10 2008 XILINX Edge Connector for PCI Express Operation Edge Connector for PCI Express Operation Caution PCI and PCI Express system units provide different DC voltages to the add in card connectors Before plugging the ML555 board into the system unit the power configuration header settings must be reviewed to verify that the board will be powered properly Failure to configure the power system properly could result in damage to the system unit or the ML555 board Refer to Figure 3 16 page 78 to see how the SW8 switch and the P18 connector are configured for PCI Express power Figure 3 3 shows the location of the edge connector and power management headers for PCI Express systems SW8 aii Slide Switch SW8 P13 8 Lane Connector for PCI Express Designs LOSXIASOX G X3LUlN XNIIX IZ P45 Configure for PCI Express Lane Width Presence Detect P18 Install Shunts for PCI Express Designs UG201 c3 03 022708 Figure 3 3 Connector and Power Management Headers for PCI Express Designs Virtex 5
9. U15 5 6 Generic Dynamic Reconfiguration It is possible to dynamically reconfigure the entire FPGA after power up With this method the CPLD loads a predetermined default bitstream from the Platform Flash upon power up After initial configuration the FPGA can signal to the CPLD that it wants to be reconfigured with a different bitstream using the CPLD_SPARE 1 10 pins The FPGA www xilinx com Virtex 5 FPGA ML555 Development Kit UG201 v1 4 March 10 2008 XILINX SelectMAP Interface simply specifies the bitstream revision along with a signal to indicate when to start the configuration process Logic within the CPLD then controls the configuration pins to the FPGA and Platform Flash to complete the configuration cycle This logic can be as simple as driving the REV_SEL pins to the Flash and the PROG_B pin on the FPGA to begin configuration The MAN_AUTO_B input to the CPLD can be incorporated into the design to override the dynamic reconfiguration and allow only static configuration as described in XAPP693 Ref 12 This application note provides details on using a CPLD and Platform Flash to dynamically reconfigure an FPGA Figure 4 7 illustrates this method The LogiCORE Getting Started Guide for PCI X provides information on using the FORCE WIDE PCIW_EN and RTR signals to support dynamic reconfiguration XAPP938 Ref 4 provides an example of dynamic FPGA reconfiguration U1 U10 Platform Flash D 0 7 D zo FPGA X
10. UG201 v1 4 March 10 2008 7 XILINX Chapter 3 Hardware Description A high level block diagram of the Virtex 5 FPGA ML555 board is shown in Figure 3 1 followed by a brief description of each board section Figure 3 2 is a photograph of the ML555 board with the key interfaces marked Serial ATA GTP SMA Connector J5 Connectors SFP Connectors DDR2 x2 SODIMM J2 J3 and J4 Xilinx Generic Interface XGI 125 and 200 MHz Header Oscillators Ethernet PHY Programmable Parallel Cable IV Clock JTAG Port P5 Synthesizer x2 Virtex 5 32 Mbit 30 MHz XCF32P LVCMOS FPGA Platform Flash x2 Oscillator XC5VLX50T FFG1136 Clock Generator pe Dp ER S USB 2 0 Port J1 3 0V for 24 Channel LVDS PCI Compliance I O Interfaces x2 P32 and P33 System 2 5V System 1 8V 64 bit 3 3V Vecint 1 0V Edge Connector for PCI PCI X P1 Var 0 9V GTP Analog Power X1 x4 or x8 Edge Connector for PCI Express 2 P13 Voltage Regulators UG201_c3_01_030508 Figure 3 1 ML555 Board Block Diagram Virtex 5 FPGA ML555 Development Kit www xilinx com 21 UG201 v1 4 March 10 2008 Chapter 3 Hardware Description XILINX J2 DDR2 lt SODIMM x mi ELT Wong Bf pet 3X3 FEEEEHEEEHEEE TEE Et Sides siens Xilinx Generic Interface Headers XC5VLX50T FPGA GTP SMA MGTREFCLK GTP SMA LOSX1ASOX G X31LU1N B s f P32 LVDS XNnIX TS S
11. 10 2008 XILINX Voltage Regulators Voltage Regulators The ML555 board is powered from either the PCI slot that it is plugged into utilizing the 5V and the 3 3V power rails see Table 3 4 for the specific power pins within the PCI edge connector pinout or the PCI Express slot that it is plugged into utilizing the 3 3V and 12V power rails ML555 DC Power System The ML555 board plugs into either a parallel PCI bus slot or a serial PCI Express slot in a system unit PCI and PCI Express designs use different connector systems for add in cards System units provide unique DC voltages to the add in cards through the connectors PCI system units provide 3 3V and 5V while PCI Express system units provide 3 3V and 12V to add in cards For PCI Express applications the ML555 board converts the 12V supply to 5V before powering the onboard voltage regulators For PCI applications most of the onboard regulators are powered by 5V provided by the system units The GTP transceiver analog supplies and the FPGA Vccmr voltage are sourced from either 3 3V from the PCI Express connector or a 5V to 3 0V DC converter on the ML555 board Two configuration headers are provided on the ML555 board to select between the 5V and 3 3V power sources as indicated in Table 3 30 and Table 3 31 Figure 3 14 is a block diagram of the ML555 voltage regulator topology Virtex 5 FPGA ML555 Development Kit www xilinx com 75 UG201 v1 4 March 10 2008 Chapter 3 Ha
12. 250 250 125 62 5 31 25 0 OB 275 275 137 5 68 75 34 375 0 0C 300 300 150 75 37 5 0 0D 325 325 162 5 81 25 40 625 0 OE 350 350 175 87 5 43 75 0 OF 375 375 187 5 93 75 46 875 0 10 400 400 200 100 50 0 11 425 425 212 5 106 25 53 125 0 12 450 450 225 112 5 56 25 0 13 475 475 237 5 118 75 59 375 0 14 500 500 250 125 62 5 0 15 525 525 262 5 131 25 65 625 0 16 550 550 275 137 5 68 75 0 17 575 575 287 5 143 75 71 875 0 18 600 600 300 150 75 0 19 625 625 312 5 156 25 78 125 0 1A 650 650 325 162 5 81 25 0 1B 675 675 337 5 168 75 84 375 0 1C 700 700 350 175 87 5 0 Ox1D OxFF Will not LOCK N A N A N A N A 1 0x00 OxFF 66 www xilinx com Virtex 5 FPGA ML555 Development Kit UG201 v1 4 March 10 2008 XILINX Clock Generation Table 3 24 shows the board DIP switch settings for the two clock synthesizer circuits and the switch positions assigned for the M and N constants When the switch is in the ON position a logic 1 is obtained and in the OFF position a logic 0 is obtained Figure 3 12 shows a graphic representation of the DIP switches and indicates which switch positions are used for the M and N input values to the clock synthesizers When the switch is in the OFF position a logic 0 is selected When the switch is not in the OFF position a logic 1 is selected ICS1 input N1 is located on SW12 position 8 Figure 3 12 shows two examples one with ICS1 generating a 330 MHz clock and the
13. 46 GND N A 47 GP1O2 I09 P AH5 48 GP1O2 I08 P Y11 49 GP1O2 I09 N AG6 50 GP1O2 I08 N W11 51 GND N A 52 GND N A 53 GP1O2 I07 P AH7 54 GP1O2 I06 P W10 55 GP1O2 I07 N AG7 56 GP102_I06_N w9 57 GND N A 58 GND N A 59 GP102_I05_P AJ7 60 GP1O2 I04 P V8 61 GP1O2 I05 N AJ6 62 GP1O2 I04 N U8 63 GND N A 64 GND N A 65 GP102_I03_P AK7 66 GP1O2 I02 P V10 67 GP1O2 I03 N AK6 68 GP102_I02_N v9 69 GND N A 70 GND N A 71 No Connect N A 72 No Connect N A 73 No Connect N A 74 No Connect N A 75 GND N A 76 GND N A 77 GP1O2 I01 PO AF23 78 GP1O2 I00 PO AE22 79 GP1O2 I01 NO AG23 80 GP10O2 I00 NO AE23 Notes DEY Bcc MESSE board schematics onthe EROM oradin naia S e 2 Bank 2 GPIO clock capable I O signals All others are in FPGA Bank 18 NC no connect 4 Bank 18 clock capable I O pins w 48 www xilinx com Virtex 5 FPGA ML555 Development Kit UG201 v1 4 March 10 2008 XILINX LVDS Interface SAMTEC QSE 028 DP SAMTEC QSE 028 DP P32 P33 V10 v9 NC NC AE22 AE23 LVDS Interface Cable Connectivity cable not provided in kit OREL Clock Capable I O in Bank 19 P32 and Bank 18 P33 Clock Capable I O in Bank 1 P32 and Bank 2 P33 Ground UG201_c3_06_092706 Notes T c channel 0 of P32 connects to GPIO channel 0 of P33 when LVDS interface cable connects P32 to 2 en channel 1 of P32 connects to GPIO channel 1 of P33 when LVDS interface cable connects P32 to 3 NC No connection Figure 3 6 LVDS Transmit an
14. And PROM Properties C Erase Before Programming Read Protect C PROM CoolRunnerll Usercode 8 Hex Digits CPLD Specific Properties Write Protect Functional Test On The Fly Program XPLA UES Enter up ta 13 characters PROM Specific Properties C Load FPGA ParallelMode Use D4 for CF Virtex ll Virtex 4 Programming Properties Pulse PROG Program Key Cs Cem Cm Cie UG201 c4 11 052307 Figure 4 13 Programming Properties Programming Properties Category amp Programming Properties Ad ced PROM Programming Properties Revision Properties During Configuration PROM is Configuration Master select clock source PROM is Slave clocked externally External Clock Internal Clack Clock Frequency 20 MHz Cancel Apply Help UG201_c4_12_022007 Figure 4 14 Advanced PROM Programming Properties 106 www xilinx com Virtex 5 FPGA ML555 Development Kit UG201 v1 4 March 10 2008 X XILINX Platform Flash Image Generation and Programming Programming Properties Category S Programming Properties Advanced PROM Programming Properties Revision Properties Design Revision and Customer Cade Select Design Revision and Enter Customer Code Max 64 Hex Digits Design Read Write Free Erase Verify Running Customer Code Revision Protect Protect
15. Chapter 3 Hardware Description XILINX XCF32PFS48C Platform Flash U1 and U15 Figure 4 5 page 92 and Table 4 5 page 95 summarize the Platform Flash connections to the XC5VLX50T FPGA U10 and the XC2C32 CPLD U6 The XCF32PFS48C Veco is 2 5V The Platform Flash holds up to four configuration images for the XC5VLX50T FPGA two images in each device As shown in Figure 4 5 the configuration image is selected by applying shorting blocks to header P3 When generating design images for the ML555 board the BITGEN compress option is not required to store four design images in the Platform Flash device Table 3 37 shows how to select each one of the four configuration image files depending upon how shunts are installed on header P3 Table 3 37 Platform Flash Image Selection MAN_AUTO FLASH_IMAGE1_SEL FLASH IMAGEO SEL 1 P3 5 to P3 6 P3 3 to P3 4 P3 1 to P3 2 FPGA Configuration Image Selected Configure FPGA with Platform Flash U1 Image SHUNT ON SHUNT ON SHUNT ON 0 4 lane Virtex 5 LogiCORE Endpoint block for PCI Express memory completer design Configure FPGA with Platform Flash U1 Image SHUNT ON SHUNT ON SHUNT OFF 1 8 lane Virtex 5 FPGA LogiCORE Endpoint block for PCI Express memory completer design Configure FPGA with Platform Flash U15 Image SHUNT ON SHUNT OFF SHUNT ON 0 32 bit 33 MHz memory reference design for PCI operation Configure FPGA with Platform Flash U15 Image S
16. Clock if the EPHY daughtercard is installed J19 P1 RCLK1O Port 1 Ethernet PHY Receive Clock if the EPHY daughtercard is installed J14 PCIBUSCLK2 P1 B16 active only when the ML555 board is installed in a PCI bus connector Not active when the ML555 board is installed in a PCI Express connector J16 PCIE_GCLK_P Global clock input available only if an ICS874003 02 PCI Express clock jitter attenuator circuit is installed on the ML555 board at location U16 not the default board configuration This clock is 100 125 or 250 MHz as selected by the CPLD controls The default is a 250 MHz spread spectrum clock generated from the add in card PCI Express input clock on connector P13 J17 PCIE_GCLK_N Global clock input available only if an ICS874003 02 PCI Express clock jitter attenuator circuit is installed on the ML555 board at location U16 this is not the default board configuration This clock is 100 125 or 250 MHz as selected by the CPLD controls The default is a 250 MHz spread spectrum clock generated from the add in card input clock for PCI Express operation on connector P13 H15 SATA_MGT_CLKSEL FPGA output used to select the fixed 125 MHz oscillator or the Clock Synthesizer 2 output to be routed to GTP_DUAL tile XOY5 MGTREFCLK and SMA_MGT_GCLK global clock inputs The ML555 board has a 4 7KQ pull up resistor to 2 5V to provide default selection of clock synthesizer 2 as the output of the Clock Mux block shown in Figure 3 8 an
17. Creating a PROM File in Command Line Mode The Xilinx PROMGEN application can be used to create a PROM file from configuration BIT files for use in programming XCF32P Platform Flash devices on the ML555 board PROMGEN is run in command line mode This design example assumes two ML555 design BIT files are copied to a directory where output files are to be stored and that the PROMGEN application is invoked from this same directory An example command line entry to take two XC5VLX50T FF1136 design BIT files design1 bit and design2 bit and create an MCS output file called ml1555xcf32p is as follows promgen w p mcs c FF o m1555xcf32p ver 0 designl bit ver 1 design2 bit x xcf32p Where w overwrites any existing output design files p is the PROM output file format Use MCS format for XCF32P devices c is fill data of OxFF 0 is the output file name created in the directory from which PROMGEN is called verx is either design revision 0 or design revision 1 X is the device type of XCF32P used on the ML555 board Enter promgen in the command window with no options to see the command syntax options PROMGEN creates four output files with file extensions of MCS CFI PRM and SIG The MCS and CFI files should always be used when programming the Platform Flash The CFI file contains configuration information that iMPACT uses for programming designs with multiple revisions iMPACT and PROMGEN Wizard GUI Mode Follow these steps
18. FPGA ML555 Development Kit www xilinx com 23 UG201 v1 4 March 10 2008 Chapter 3 Hardware Description 24 XILINX Table 3 1 shows the connector pin assignment for PCI Express designs The board supports x1 x4 and x8 endpoint designs The ML555 board is an endpoint add in card Port names are with respect to the system board host Table 3 1 P13 Edge Connector Socket Pinout for PCI Express Designs P13 A Side Signal P13 B Side Signal A1 PCIE_PRSNT1_B B1 12 VOLTS A2 12 VOLTS B2 12 VOLTS A3 12 VOLTS B3 12 VOLTS A4 GND B4 GND A5 JTAG_TCK B5 SMCLK A6 JTAG_TDI B6 SMDAT A7 JTAG_TDO B7 GND A8 JTAG_TMS B8 3 3 VOLTS A9 3 3 VOLTS B9 JTAG TRST B A10 43 3 VOLTS B10 43 3 VOLTSAUX All PCIE PERST B11 PCIE WAKE BO KEY KEY A12 GND B12 RESERVED A13 PCIE REFCLKP B13 GND A14 PCIE REFCLKNO B14 PETPO A15 GND B15 PETNO A16 PERPO B16 GND A17 PERNO B17 PCIE_PRSNT2_BM A18 GND B18 GND A19 RESERVED B19 PETP1 A20 GND B20 PETN1 A21 PERP1 B21 GND A22 PERN1 B22 GND A23 GND B23 PETP2 A24 GND B24 PETN2 A25 PERP2 B25 GND A26 PERN2 B26 GND A27 GND B27 PETP3 A28 GND B28 PETN3 A29 PERP3 B29 GND www xilinx com Virtex 5 FPGA ML555 Development Kit UG201 v1 4 March 10 2008 XILINX Edge Connector for PCI Express Operation Table 3 1 P13 Edge Connector Socket Pinout for PCI Express Desi
19. March 10 2008 XILINX Platform Flash Image Generation and Programming Specifying the Xilinx PROM Device Follow these steps to specify the PROM device 1 Under Specify Xilinx PROM Device shown in Figure 4 10 select the following From the Number of Revisions drop down box choose 2 The XCF32P supports a maximum of two XC5VLX50T design images From the Select a PROM drop down boxes choose xc p and xc 32p then click Add Click Next iMPACT Specify Xilinx PROM Auto Select PROM Enable Revisioning Number of Revisions _ Enable Compression Select a PROM bits xcfp xcf32p 33554432 Position 0 xcf32p UG201_c4_10_052307 Figure 4 10 Specify Xilinx PROM Device 2 Under File Generation Summary click Finish Click OK to start adding device files for Revision 0 3 Under Add Device browse for the bitfile you want for Configuration Address 0 and click Open 4 Under Add Device Would you like to add to Revision 0 click No 5 Browse for the bitfile you want for Configuration Address 1 and click Open 6 Under Add Device Would you like to add to Revision 1 click No 7 Under Add Device You have completed the device file entry Click OK to continue 8 Under Available Operations Are double click on Generate File Virtex 5 FPGA ML555 Development Kit www xilinx com 103 UG201 v1 4 March 10 2008 Chapter 4 Configuration XILINX 9 Unde
20. X 64 bits 100 MHz Global J14 v6 PCI X 64 bits 66 MHz Global J14 v6 PCI 64 bits 33 MHz Global J14 These Xilinx interface cores are pre implemented and fully tested modules for Xilinx FPGAs The v4 64 bit interface is compliant with the PCI Local Bus Specification revision 3 0 The v6 64 bit interface is compliant with the PCI Local Bus Specification revision 3 0 and the PCI X Addendum revision 2 0 The pinout for each Virtex 5 device and the relative placement of the internal logic are predefined Critical paths are controlled by constraints to ensure predictable timing significantly reducing the engineering time required to implement the bus interface portion of a user design When targeting an XC5VLX50T FFG1136 FPGA the Xilinx CORE Generator tool provides an example design and a constraints file utilizing the ML555 board pinout for PCI and PCI X designs Resources can instead be focused on unique user application logic in the FPGA and on the system level design As a result the Xilinx interface products for PCI and PCI X operation minimize product development time The following links provide more information e Xilinx LogiCORE products www xilinx com products design_resources conn_central index htm e PCI and PCI X specific applications www xilinx com products design resources conn central protocols pci pcix htm Included with the purchase of the ML555 development kit is a 90 day access to
21. are connected to FPGA bank 13 The reference voltage Vcco for this bank is 3 0V See the ML555 board schematics on the CD ROM for additional information The clock synthesizer clocks are not connected to FPGA bank 13 2 The LVDSCLKMOD 2 differential clock is connected to a differential clock multiplexer The output of the multiplexer goes to FPGA global clock inputs J20 P and J21 N and MGT X0Y5 MGTREFCLK inputs E4 and D4 Virtex 5 FPGA ML555 Development Kit www xilinx com UG201 v1 4 March 10 2008 69 Chapter 3 Hardware Description XILINX Figure 3 13 is a timing diagram showing the serial and parallel programming modes of operation The parallel mode has priority over serial mode SCLOCK SDATA 1X TO JQULLX NI XNOXMBEXMZXMEX X X X M2X Mi AMO STROBE 100 ns max M N XX SCLOCK E PLOAD 20 ns min j 3 20 ns min E soata KK STROBE N MN XX PLOAD N 7 l UG201_c3_12_092706 Figure 3 13 Serial Configuration Interface Timing Clock Capable I O Pins Associated with Clock Inputs Some clock capable input and output pins of the FPGA are connected to clocking sources on the ML555 board Table 3 26 summarizes these FPGA clock capable inputs and outputs along with their FPGA bank numbers and I O bank reference voltages Table 3 26 FPGA Clock Capable I O Connectivity
22. default 2 MHz CCLK used by the BitGen application Refer to Platform Flash Image Generation and Programming page 101 for a BitGen example Figure 4 8 shows the clock structure for SelectMAP mode along with Header P2 U1 U15 Flash U10 FPGA CLKIN j P2 Header CLKOUT CCLK GC Y2 30 MHz Oscillator U4 Clock Buffer U6 CPLD O GC1 Master SelectMAP default UG201_c4_08_022608 Figure 4 8 SelectMAP Clock Circuitry 100 www xilinx com Virtex 5 FPGA ML555 Development Kit UG201 v1 4 March 10 2008 XILINX Platform Flash Image Generation and Programming Platform Flash Image Generation and Programming This section provides general guidelines on how to create a PROM image file with two design revisions bitstreams using the Configuration File Wizard in the iMPACT FPGA programming tool Online documentation from the Configuration File Wizard and iMPACT is available through the Help gt Help Topics menu selection in iMPACT The Xilinx Development System Reference Guide provides details on how to create a PROM image file using PROMGen The Development System Reference Guide provides details on bitstream file options available with the BitGen application For example the FPGA CCLK frequency can be controlled using a BitGen option To select a 20 MHz configuration clock CCLK frequency versus the default 2 MHz the following command syntax is used bitgen g ConfigRate 20 lt input file gt Setup
23. description of the FPGA configuration circuitry and methods used on the Virtex 5 FPGA ML555 board The JTAG chain permits the CPLD and or the Platform Flash devices to be bypassed with onboard headers Figure 4 1 shows the location of configuration switches connectors and devices discussed in this chapter Virtex 5 FPGA ML555 Development Kit www xilinx com 87 UG201 v1 4 March 10 2008 Chapter 4 Configuration XILINX ALL 1 n a cS U10 FPGA SW7 RST U6 CPLD U1 Platform Flash SW5 Mode Switch P38 P5 JTAG Connector P39 SW6 PROG P3 P2 P20 UG201_c4_01_091806 Figure 4 1 Configurable Devices 88 www xilinx com Virtex 5 FPGA ML555 Development Kit UG201 v1 4 March 10 2008 XILINX Configuration Modes Configuration Modes JTAG Chain Table 4 1 shows the Virtex 5 FPGA configuration modes along with the correct settings for the Configuration Mode switch SW5 Table 4 1 Configuration Modes Mode SW5 2 Model JTAG P5 1 2 3 MO M1 M2 Master SelectMAPO N A 0 0 1 Slave SelectM APO N A 0 1 1 JTAG Yes 1 0 1 Master Serial N A 0 0 0 Slave Serial N A 1 1 1 Notes 1 Switch position 4 is used to select the DC voltage level applied to the HSWAPEN FPGA configuration input This switch controls whether the weak pull up resistors on the FPGA I Os are enabled or disabled prior to configuration 2 0 switch position
24. in Table 3 2 Table 3 2 Presence Detect Configuration Header for PCI Express Designs P45 Physical Connection at Number of Connector P13 Active Lanes in Shunt Position on Connector P45 Design PRSNT1 B PRSNT2 B 1 Install shunt on connector P45 pins 5 6 P13 A1 P13 B17 4 Install shunt on connector P45 pins 3 4 P13 A1 P13 B31 8 Install shunt on connector P45 pins 1 2 P13 A1 P13 B48 Notes 1 P45 pins 2 4 and 6 are all connected to PCIE PRSNTI B on connector P13 pin A1 2 See Figure 3 3 page 23 for the location of configuration header P45 Downshifting is defined as plugging an add in card into a connector that is not fully routed for all of the lanes In general downshifting is not allowed and is physically prevented An exception is the x8 connector in which the system designer can choose to route only the first four lanes a x8 lane card must function as a x4 lane card in this scenario The ML555 board can be used as either a x4 or a x8 lane card depending upon the user design loaded into the FPGA For development purposes several companies offer x16 to x1 adapters that permit plugging multilane add in cards into single lane PCI Express system unit connectors The adapter is not provided with the ML555 development kit Table 3 3 shows the correlation between PCI Express signals P13 add in card pin FPGA pins and GTP_DUAL tile location assignments 26 www xilinx com Virtex 5 FPGA ML555 Develo
25. is Closed or in the ON position 1 switch position is Open or in the OFF position See Figure 4 2 3 When using SelectMAP configuration mode see Table 4 7 for configuration of the CCLK source for master mode operation Slave SelectMAP clocking is not supported on the ML555 board Master SelectMAP with a minimum 20 MHz configuration clock CCLK frequency is the recommended configuration method for PCI PCI X and PCI Express applications utilizing the ML555 board Figure 4 2 shows the Configuration Mode switch SW5 position 4 is used to select the DC voltage level applied to the HSWAPEN input pin in the FPGA configuration bank If the switch is in the OFF position the weak preconfiguration I O pull up resistors are disabled If the switch is in the ON position the weak preconfiguration I O pull up resistors are enabled SW5 Logic Logic 234 O JO JO O OFF 1 MODE UG201 c4 02 091706 Figure 4 2 Configuration Mode Switch Figure 4 3 shows the JTAG chain on the ML555 board The chain can be driven by the following sources e Xilinx Parallel Cable IV or Platform Cable USB e OtherJTAG cables The JTAG chain supports bypassing of the CPLD or the Platform Flash devices The FPGA cannot be bypassed Board connector header P39 is used to enable or bypass the CPLD Virtex 5 FPGA ML555 Development Kit www xilinx com 89 UG201 v1 4 March 10 2008 Chapter 4 Configuration XILINX connec
26. is intended to plug in to a 3 3V keyed system board The ML555 board is not a Universal add in card nor is it intended to plug into a 5V keyed system board Figure 1 1 shows how to identify a 3 3V system board slot left side from a non supported 5V system board slot right side Dual Voltage Signalling 3 3V Add in Card Add in Card O Buffers Powered l O Buffers Powered on on 3 0V Rail Connector Dependent Rail 3 3V 64 bit Connector 5V 64 bit Connector UG201 c1 01 050106 Rear of Computer Chassis Rear of Computer Chassis Figure 1 1 Add in Card Connectors Virtex 5 FPGA ML555 Development Kit www xilinx com 13 UG201 v1 4 March 10 2008 Chapter 1 Introduction XILINX The ML555 board is supported by Xilinx LogiCORE IP versions 4 and 6 respectively Each core has a primary version number shown in Table 1 1 followed by a revision or build number More information about the current versions of these cores is available in the LogiCORE data sheets for the PCI and PCI X section of the PCI PCI X product lounge refer to http www xilinx com products logicore lounge lounge htm Table 1 1 lists the Xilinx cores for PCI and PCI X operation Table 1 1 Xilinx Cores Supporting PCI and PCI X Operation Version od Bus Width prequency FPGA Ping v4 PCI 32 bits 33 MHz Global J14 v4 PCI 32 bits 66 MHz Global J14 v4 PCI 64 bits 33 MHz Global J14 v6 PCI X 64 bits 133 MHz Global J14 v6 PCI
27. lane configurations e Two Small Form factor Pluggable SFP Transceiver module ports SFP modules are not included e Xilinx Generic Interface XGI headers support installation of Xilinx Ethernet PHY daughtercard sold separately for 10 100 1000 Mb Ethernet connectivity e TwoSAMTEC LVDS interface connectors with up to 24 high speed LVDS channels each cables sold separately e One Serial ATA SATA disk drive interface connector SATA cable not provided e One set of SMA ports for offboard GTP transceiver connectivity e User pushbutton switches and LEDs e Device configuration through on board Platform Flash or Xilinx Platform Cable USB e PCI clocking support for global and regional clocking applications e On board power regulators 3 0V PCI 2 5V 1 8V 1 0V 0 9V Vr e Two programmable clock synthesizer chips to support DDR2 memory interfaces 10 100 1000 Mb Ethernet protocols SATA Fibre Channel Aurora and other serial GTP baud rates Available Xilinx Accessories The ML555 board has one set of SMA connectors connected to one of the GTP transceiver ports of the XC5VLX50T FPGA Xilinx sells a number of SMA conversion module boards that permit the conversion of the on board SMA interface to other popular multi gigabit serial connector interfaces These accessories boards are available through your local Xilinx Sales office Xilinx also provides an Ethernet PHY daughtercard that can be used to provide dual Ethernet connectivity t
28. listing and physical FPGA pin locations LOC constraint to get started designing user applications with the Xilinx ISE software Signal names can be changed to match user preferences if the board schematic signal names are not identical to the top level user design file names Open the ReadMe txt file on the CD to review the list of contents Initial Board Checks Before Applying Power Note These steps MUST be performed before plugging in the ML555 board 1 Set up the Configuration Mode Switch SW5 for Master SelectMAP See Table 4 1 page 89 and Figure 4 2 page 89 2 Configure Jumper Block P2 to select configuration CCLK source FPGA See Table 4 7 page 100 and Figure 4 8 page 100 3 Configure Jumper Block P3 to select one of four Platform Flash configuration files or use JTAG programming cable to load user design See Table 3 37 page 86 4 Switch SW8 selects the FPGA Vccemr source PCI or PCI Express bus as described in ML555 DC Power System page 75 5 Jumper Block P18 enables the 12V to 5V enable for PCI Express operation as described in ML555 DC Power System page 75 The ML555 board now can be plugged into a powered down 3 3V only add in card slot for PCI Express or PCI PCI X operation See the cd_rom txt file on the CD Virtex 5 FPGA ML555 Development Kit www xilinx com 19 UG201 v1 4 March 10 2008 Chapter 2 Getting Started 20 www xilinx com 2 XILINX Virtex 5 FPGA ML555 Development Kit
29. mA 256 MB 620 mA 780 mA 940 mA 512 MB 720 mA 780 mA 1100 mA Current consumption can be higher than shown in Table 3 6 if the four memory banks are interleaved in the DDR2 memory Interleaving is accomplished by using the BA 2 0 bank address as the least significant column address bits to the DDR2 memory This increases power dissipation rather than memory performance and should be avoided for PCI Express and PCI bus applications where add in card power is limited by specification to 25W Virtex 5 FPGA ML555 Development Kit UG201 v1 4 March 10 2008 www xilinx com X XILINX Small Form factor Pluggable SFP Module Interface Small Form factor Pluggable SFP Module Interface The ML555 board has two SFP connectors that support user installed SFP modules to support Fibre Channel and Gigabit Ethernet interfaces The interface is compliant with the multi source agreement specification entitled Cooperation Agreement for Small Form Factor Pluggable Transceivers Table 3 7 lists the connector pins and any associated FPGA connectivity The ML555 board provides filtered 3 3V power to both SFP modules per the SFP specification Table 3 7 SFP Connectors SFP1 J3 Signal FPGA Pin 2 SFP2 J4 FPGA Pin 1 GND NC 1 NC 2 SFP 1 2 _TX_FAULT NC 2 NC 3 SFP 1 2 TX DISABLE NC 3 NC 4 IIC_SDA_SFP 1 2 ES 4 F8 5 II2 SCK SFP 1 2 E9
30. module is available from the Xilinx website at www xilinx com xlnx xebiz designResources ip_product_details jsp key HW AFX SMA RJ45 Conversion Module SMA to HSSDC2 HW AFX SMA HSSDC2 The SMA to HSSDC2 module can be used in conjunction with the ML555 SMA connectors to convert the SMA interface to a HSSDC2 interface The SMA to HSSDC2 conversion module can be ordered from Xilinx as part number HW AFX SMA HSSDC2 Contact your local sales office for pricing information Additional information on the conversion module is available from the Xilinx website at www xilinx com xlInx xebiz designResources ip product details jsp key HW AFX S5MA HSSDC2 PHY Daughtercard HW AFX BERG EPHY The PHY daughtercard plugs into the XGI headers on the ML555 board The PHY daughtercard provides Ethernet capability to the ML555 development platform by using two Marvel Alaska 88E1111 Gigabit over copper transceivers These PHY devices perform all physical layer PHY functions operate at 10 100 1000 Mb s and support many interfaces of the embedded tri mode Ethernet MAC in the Virtex 5 FPGA The PHY daughtercard can be ordered from Xilinx as part number HW AFX BERG EPHY Contact your local sales office for pricing information Additional information on the PHY daughtercard is available from the Xilinx website at www xilinx com xlInx xebiz designResources ip product details jsp key HW AFX BERG EPHY Virtex 5 FPGA ML555 Development Kit www xili
31. or bit image is included on the CD ROM to permit testing the FPGA to VCP interface The reference design utilizes the MicroBlaze soft processor and a UART core to communicate to the PC terminal window The ML555 board provides a USB Type B device port connector that is intended to be cabled to the host computer with a USB Type A port connector Table 3 17 describes the USB interface pin assignments Table 3 17 USB Connector Signal Names and Pin Assignments USB Connector Signal Name Description J1 Pin 1 VBUS 5V from HOST system not used 2 USB DATA N Bidirectional differential serial data n side 3 USB DATA P Bidirectional differential serial data p side 4 GROUND Signal ground Clock Generation 52 The clock generation section of the ML555 board provides three fixed two programmable and two pairs of differential SMA inputs for clock sources 1 Epson EG 2121C A 125 0000M LHPAB 2 5V LVDS differential oscillator 125 MHz FPGA oscillator for Gigabit Ethernet 2 Epson SG 8002C A 30 0000M PCC 3 3V LVCMOS single ended oscillator This clock is buffered via U9 It goes to the CPLD and one of the FPGA global clock inputs 3 Epson EG 2121CA 200 0000M PHPAB 2 5V LVPECL differential oscillator One pair of SMA clock inputs is connected to the global clock bank and the other pair of SMA clock inputs is connected to the GTP DUAL tile XOY3 MGTREFCLK inputs The global clock SMA ports can also be used
32. xilinx com 41 UG201 v1 4 March 10 2008 Chapter 3 Hardware Description Table 3 10 Ethernet PHY Daughtercard J15 Connection XILINX J15 EVEN Signal J15 ODD Signal FPGA Pin FPGA In Out 2 GND 1 P1_TD_TXD1 M8 Out 4 GND 3 P1_TXCTL_TXEN F11 Out 6 GND 5 P1 TXC GTXCLKO K8 Out 8 GND 7 P1 COL L9 In 10 GND 9 P1 TD TXD3 E12 Out 12 GND 11 p1 TD TXD2 N9 Out 14 GND 13 No connect NC 16 GND 15 P1 TD TXDO F13 Out 18 GND 17 P1 TXD7 G13 Out 20 GND 19 P1 TXD6 N10 Out 22 GND 21 P1 TXD5 E13 Out 24 GND 23 P1 TXDA4 L8 Out 26 GND 25 P1 MDC E7 Out 28 GND 27 P1 MDIO U10 In Out 30 GND 29 P1 TXER G7 Out 32 GND 31 P1 INT T11 In 34 GND 33 PO COL F6 In 36 GND 35 PO TXD7 p9 Out 38 GND 37 PO INT G5 In 40 GND 39 PO TXD6 P10 Out 42 GND 41 PO TXD5 M5 Out 44 GND 43 PO TXDA4 N7 Out 46 GND 45 PO TD TXD3 L6 Out 48 GND 47 PO TD TXD2 N5 Out 50 GND 49 PO TD TXD1 L4 Out 52 GND 51 PO TD TXDO p7 Out 54 GND 53 PO MDC K7 Out 56 GND 55 PO MDIO R6 In Out 58 GND 57 RESET B T6 Out 60 GND 59 PO_TXC_GTXCLK T8 Out 62 GND 61 PO_TXCTL_TXEN U7 Out 64 GND 63 PO_TXER J7 Out Notes 1 2 3 4 42 UG065 Ref 3 provides additional information on the HW AFX BERG EPHY Daughtercard These signals are connected to FPGA banks 12 and 20 The bank reference voltage Veco is 2 5V See the ML555 board schematics on the CD ROM for addit
33. 1 Using a DCM with the DCM CLKFX output The ML555 30 MHz clock input is used on GCLK pin L19 as the DCM clock input The 125 MHz clock input is used through the U2 clock multiplexer GCLK inputs G15 P and G16 N as the DCM clock input The 125 MHz clock input is used through the clock driver GCLK inputs J20 P and J21 N as the DCM clock input 2 Using an external signal generator and connecting the signal generator outputs either single ended or differential to the ML555 SMA clock inputs J10 GCLKP H17 and J11 GCLKN H18 The frequency generator output is set to the desired frequency A DCM is not required for this method of generating the IDELAYCTRL reference clock 72 www xilinx com Virtex 5 FPGA ML555 Development Kit UG201 v1 4 March 10 2008 2 XILINX User LEDs User LEDs 3 Using one of the clock synthesizer chips If using the parallel input mode SW9 and or SW11 must be pressed and released to obtain a known output frequency from the clock synthesizers after a power on cycle Typically CLOCK SYNTHI is reserved for the DDR2 memory clock generation If the DDR2 memory is not used or the clock frequency for the DDR2 memory is 200 MHz this clock can be used for 200 MHz clock generation The ML555 board supports DDR2 400 DDR2 533 and DDR2 667 rates CLOCK SYNTHZ2 routed through the U3 clock mux goes to GCLK P J20 and GCLK N J21 The SATA MGT CLKSEL output port on FPGA pin H15 must be set to either a log
34. 1 and U15 See Table 4 6 page 98 for additional information on P3 selection of stored FPGA bitstream images Pushbutton Reset Switch SW7 The ML555 board provides a pushbutton switch SW7 for a user assigned function This switch labelled RESET is wired to the CPLD U6 pin 18 general purpose I O pin The switch output is connected by a 4 7 KO pull up resistor to 2 5V This pushbutton generates a switch closure to GND when pressed Switch contact debounce logic must be implemented inside the CPLD There are multiple connections between the CPLD U6 and the FPGA U10 to transmit SW7 activity Power Consumption 74 The PCI specification outlines the power consumption limitations for PCI add in boards The maximum allowable power consumption across all power rails 5V 3 3V 12V 12V is 25W On the PCI connector two signals allow the power demand of a board to be specified The PRSNTT 1 2 signals are used by a system board to detect if an add in card is physically present in the slot and the total power requirements of the add in card The signals are required for the add in card but are optional for the system board The ML555 board uses the EDGE_PRSNT1 and EDGE_PRSNT2 signals to request the maximum 25W power limit by grounding PRSNT1 and leaving PRSNT2 open The SKT PRSNTT 1 2 f signals on the PCI X expansion socket J1 are routed to the FPGA for sensing www xilinx com Virtex 5 FPGA ML555 Development Kit UG201 v1 4 March
35. 31 In A39 VCC3V3 NC B39 unused NC A40 unused NC B40 EDGE_PERR_B K34 In Out A41 unused NC B41 VCC3V3 NC A42 GND NC B42 EDGE_SERR_B K33 In Out A43 EDGE_PAR G33 In Out B43 VCC3V3 NC A44 EDGE AD15 R26 In Out B44 EDGE CBE1 E32 In Out A45 VCC3V3 NC B45 EDGE AD14 R27 In Out A46 EDGE AD13 U26 In Out B46 GND NC A47 EDGE AD11 U25 In Out B47 EDGE AD12 T26 In Out A48 GND NC B48 EDGE_AD10 T25 In Out A49 EDGE_AD9 B32 In Out B49 EDGE_M66EN L29 In A50 GND NC B50 GND NC A51 GND NC B51 GND NC A52 EDGE CBEO E33 In Out B52 EDGE_AD8 A33 In Out A53 VCC3V3 NC B53 EDGE AD7 B33 In Out A54 EDGE AD6 C33 In Out B54 VCC3V3 NC A55 EDGE AD4 D32 In Out B55 EDGE AD5 C32 In Out A56 GND NC B56 EDGE AD3 C34 In Out A57 EDGE AD2 D34 In Out B57 GND NC A58 EDGE ADO H32 In Out B58 EDGE AD1 G32 In Out A59 VCC3V3 NC B59 VCC3V3 NC A60 EDGE REQ64 B N33 In Out B60 EDGE ACKo4 B K32 In Out A61 VCC5 NC B61 VCC5 NC A62 VCC5 NC B62 VCC5 NC 64 Bit Connector A63 GND NC B63 unused NC A64 EDGE CBE7 L33 In Out B64 GND NC Virtex 5 FPGA ML555 Development Kit www xilinx com 31 UG201 v1 4 March 10 2008 Chapter 3 Hardware Description XILINX Table 3 4 P1 PCI Edge Connector Pinout Continued Sido Signal FPGA Pin ij ie Signal FPGA Pin i A65 EDGE CBE5 P34 In Ou B 5 EDGE CBE6 M3 I Out A66 VCC3V3 NC B66 EDGE CBE4 N34 In Out A67 EDGE PAR6
36. 4 GND N A 25 GPIO1_106_N N28 26 GPIO1_I07_N K26 27 GPIO1_I06_P M28 28 GPIO1_107_P K27 29 GND N A 30 GND N A 31 GPIO1_108_N L28 82 GPIO1 I09 N M27 33 GPIOI1 108 P K28 34 GPIO1_109_P N27 35 GND N A 36 GND N A 37 GPIO1_I10_N E27 38 GPIO1_I11_N F28 39 GPIO1 H0 PO E26 40 GPIOI I11 P E28 41 GPIO1 H2 NO G28 42 GPIO1 H3 NO H27 43 GPIO1 I12 P0 H28 44 GPIO1 H3 PO G27 45 GND N A 46 GND N A 47 GPIO1_I14_N F26 48 GPIO1_I15_N H24 49 GPIOI I14 P F25 50 GPIOI I15 P H25 51 GND N A 52 GND N A 53 GPIO1_I16_N G26 54 GPIO1_I17_N J26 55 GPIO1_116_P G25 56 GPIO1_I17_P J27 57 GND N A 58 GND N A 59 GPIO1 H8 N M26 60 GPIO1_I19_N J25 61 GPIO1_I18_P M25 62 GPIO1_I19_P J24 63 GND N A 64 GND N A 65 GPIO1_I20_N L26 66 GPIO1_I21_N L24 67 GPIO1_I20_P L25 68 GPIO1_I21_P K24 69 GND N A 70 GND N A 71 No connect N A 72 No connect N A www xilinx com Virtex 5 FPGA ML555 Development Kit UG201 v1 4 March 10 2008 Table 3 12 SAMTEC Pin Connections P32 Continued LVDS Interface SAMTEC QSE SAMTEC QSE 028 DP P32 Signal FPGA 028 DP P32 Signal FPGA Pin Pin Odd Even 73 No connect N A 74 No connect N A 75 GND N A 76 GND N A 77 GPIO1 D2 NO K12 78 GPIO1 D3 NO H12 79 GPIO1 D2 PO K13 80 GPIO1 123 PO J12 Notes 1 These signals are connected to FPGA banks 1 and 19 The FPGA reference voltage for these banks is 2 5V See the ML555 board schematics on the CD ROM for addition
37. 4 M33 In Out B67 GND NC A68 EDGE AD62 N32 In Out B68 EDGE_AD63 P32 In Out A69 GND NC B69 EDGE_AD61 T33 In Out A70 EDGE AD60 R34 In Out B70 VCC3V3 NC A71 EDGE_AD58 R32 In Out B71 EDGE_AD59 R33 In Out A72 GND NC B72 EDGE_AD57 U33 In Out A73 EDGE AD56 T34 In Out B73 GND NC A74 EDGE AD54 U31 In Out B74 EDGE AD55 U32 In Out A75 VCC3V3 NC B75 EDGE AD53 V32 In Out A76 EDGE AD52 V33 In Out B76 GND NC A77 EDGE AD50 V34 In Out B77 EDGE ADb51 W34 In Out A78 GND NC B78 EDGE AD49 Y33 In Out A79 EDGE ADA48 AA33 In Out B79 VCC3V3 NC A80 EDGE AD46 Y34 In Out B80 EDGE_AD47 AA34 In Out A81 GND NC B81 EDGE_AD45 Y32 In Out A82 EDGE_AD44 W32 In Out B82 GND NC A83 EDGE_AD42 AD34 In Out B83 EDGE_AD43 AC34 In Out A84 VCC3V3 NC B84 EDGE ADA1 AC32 In Out A85 EDGE AD40 AB32 In Out B85 GND NC A86 EDGE AD38 AB33 In Out B86 EDGE AD39 AC33 In Out A87 GND NC B87 EDGE AD37 AF33 In Out A88 EDGE AD36 AE33 In Out B88 VCC3V3 NC A89 EDGE AD34 AE34 In Out B89 EDGE AD35 AF34 In Out A90 GND NC B90 EDGE AD33 AH34 In Out A91 EDGE AD32 AJ34 In Out B91 GND NC A92 unused NC B92 unused NC A93 GND NC B93 unused NC A94 unused NC B94 GND NC Notes 1 PCl interface signals are connected to FPGA banks 11 13 and 15 The reference voltage Vcco for these FPGA banks is 3 0V See the ML555 board schematics on the CD ROM for additional information 2 NC no connect 3 PCIBUSCLK1 is routed to FPGA global clock input pin J14 and PCIBUSCLK2 is routed to FPGA regional clock input pin L34
38. 5 F9 6 SFP 1 2 TCVR PRESENT B 9 NC 6 NC 7 SFP 1 2 RATE SEL NC 7 NC 8 SFP 1 2 LOS NC 8 NC 9 GND NC 9 NC 10 GND NC 10 NC 11 GND NC 11 NC 12 SFP 1 2 _RXN H1 12 n 13 SFP 1 2 _RXP G1 13 K1 14 GND NC 14 NC 15 SFP_RX_3 3V NC 15 NC 16 SFP_TX_3 3V NC 16 NC 17 GND NC 17 NC 18 SFP 1 2 _TXP F2 18 L2 19 SFP 1 2 _TXN G2 19 K2 20 GND NC 20 NC Notes 1 Transceiver port names do not include the 1 2 shown in this table Replace 1 2 with SFP1 or SFP2 as the prefix or suffix in the port name The SFP ports are connected to GTP DUAL tile X0Y4 NC no connect ak OQ M TX FAULT input from SFP goes to a board testpoint only TX DISABLE has an on board 4 7 KO pull down resistor By default the transceiver is enabled Some SFP modules require a The PC interface signals are connected to FPGA bank 20 The reference voltage Vcco for this bank is 2 5V stronger pull down resistor to enable the transmitter In this situation resistors R394 and R402 on the ML555 board should be replaced with a 1 KO or lower value resistor to force the transmitter to be enabled 6 TCVR PRESENT is not connected to the FPGA 7 RATE SEL is pulled up to 3 3V with a 4 7 KQ resistor P26 or P29 pin 1 or 2 is shorted to ground to select a different transmission rate 8 Loss of signal from the SFP interface is connected to light emitting diode LED D7 for SFP1 and D8 for SFP2 Virtex 5 FPGA ML555 Development Kit The ML555 kit
39. 8 Synthesizer 1 700 MHz U19 Clock Differential LVDS 3125 MHz to Refer to Figure 3 8 Synthesizer 20 700 MHz J10 Differential SMA User Specified SMA_GCLKP FPGA U10 Bank 3 Global Clock input Single Ended Input GCLK_P pin H17 P J11 Differential only SMA User Specified Must not be connected to a single ended clock Input GCLK N SMA_GCLKN FPGA U10 Bank 3 Global Clock differential input pin H18 N J126 Differential SMA User Specified GTP DUAL tile XOY3 MGTREFCLK P pin P4 Input J136 Differential SMA User Specified GTP DUAL tile X0Y3 MGTREFCLK_N pin P3 Input PCIE REFCLKP Differential LVDS 100 MHz FPGA U10 GTP_DUAL tile XOY2 MGTREFCLK_P system board Spread pin Y4 and FPGA U10 global clock input pin J16 as input Spectrum PCIE_GCLK_P Virtex 5 FPGA ML555 Development Kit www xilinx com 53 UG201 v1 4 March 10 2008 Chapter 3 Hardware Description XILINX Table 3 18 ML555 Board Clock Sources Continued Clock Designator Output Type Frequency Destination Pin PCIE_REFCLKN Differential LVDS 0 100 MHz FPGA U10 GTP_DUAL tile XOY2 MGTREFCLK_N system board Spread pin Y3 and FPGA U10 global clock input pin J17 input Spectrum Notes 1 Differential clock inputs to the FPGA should use the IBUFDS input buffer library primitive Setting the DIFF TERM attribute of the 2 IBUFDS to TRUE provides 100 Q on chip termination for the LVDS clock source driver The clock synthesiz
40. 8 N 1 0 00b N 1 0 01b i N 1 0 11b 0 35 530 530 265 132 5 66 25 0 36 540 540 270 135 67 5 0 37 550 550 275 137 5 68 75 0 38 560 560 280 140 70 0 39 570 570 285 142 5 71 25 0 3A 580 580 290 145 72 5 0 3B 590 590 295 147 5 73 75 0 3C 600 600 300 150 75 0 3D 610 610 305 152 5 76 25 0 3E 620 620 310 155 77 5 0 3F 630 630 315 157 5 78 75 0 40 640 640 320 160 80 0 41 650 650 325 162 5 81 25 0 42 660 660 330 165 82 5 0 43 670 670 335 167 5 83 75 0 44 680 680 340 170 85 0 45 690 690 345 172 5 86 25 0 46 700 700 350 175 87 5 0 0x47 OxFF Will not LOCK N A N A N A N A 1 0x00 OxFF Virtex 5 FPGA ML555 Development Kit UG201 v1 4 March 10 2008 www xilinx com 65 Chapter 3 Hardware Description XILINX Table 3 23 shows the clock synthesis ranges possible with different selections of multiplier M and divisor N inputs to the ICS8442 device with a 25 MHz reference clock input for Clock Synthesizer 2 Table 3 23 Clock Synthesizer 2 Frequency Output for Multiplier Divider Values with a 25 MHz Input Clock Multiplier Input Output Output Output Selection VCO Lock Output Frequency Frequency MHz Frequency Frequency hex Frequency Range MHz with Divisor with Divisor 2 MHz with MHz with MHz 1 N 1 0 00b Divisor 4 Divisor 8 M8 M 7 0 N 1 0 01b wr ol 105 N 1 0 11b 0 0x00 0x09 Will not LOCK N A N A N A N A 0 0A
41. 9 CPLD SPARE3C 9 I O IO Spare I O connected to CPLD pin 36 Notes 1 Configuration signals are connected to FPGA bank 0 The reference voltage Veco for this bank is 2 5V See the ML555 board schematics on the CD ROM for additional information 2 These signals are connected to FPGA bank 20 The FPGA reference voltage Vcco for this bank is 2 5V See the ML555 board schematics on the CD ROM for additional information 3 The Net Names and Directions for pins L11 L10 C13 and B13 were chosen to support a specific PCI PCI X design as described in CPLD Programming Examples The user can use these pins as spare bidirectional pins 4 Use LVCMOS 25 I O standard for general purpose I O connected to the CPLD 5 The Platform Flash data bus is connected to FPGA Bank 2 The FPGA reference voltage Veco for this bank is 2 5V Platform Flash data bit 0 is also connected to FPGA bank 0 to support the Serial SelectMAP configuration Virtex 5 FPGA ML555 Development Kit UG201 v1 4 March 10 2008 www xilinx com 93 Chapter 4 Configuration XILINX Table 4 4 CPLD Pin Listing LUN Net Name Direction Pin Type Description 1 CPLD CLK 30MHZ I IO GC1 30 MHz Global Clock Input 2 FLASH IMAGEO0 SELECT I IO1 Revision Select Pin 0 from Header P3 3 FLASH IMAGEI1 SELECT I IO2 Revision Select Pin 1 from Header P3 4 GND I GND1 Groun
42. AO ea Y gt MGT REFCLKP Ics p PCIE250M_N MGT_REFCLKN ai 874003 A1 PCIE GCLK P J16 GCLKP nn PCIE_GCLK_N 17 GCLKN GCLKP GCLKN MGT_REFCLKP MGT REFCLKN GTP X0Y1 MGT REFCLKP MGT REFCLKN GTP X0YO gt MGT REFCLKP GTP X0Y3 MGT REFCLKN GCLKP GCLKN MGT REFCLKP MGT_REFCLKN GTP XoY4 GCLKP GCLKN GTP X0Y5 Bank 3 I O gt GCLKP GCLKN gt GCLK UG201_c3_08_022608 Figure 3 9 Clock Synthesis Block Diagram Optional Customer Install Configuration 56 www xilinx com Virtex 5 FPGA ML555 Development Kit UG201 v1 4 March 10 2008 2 XILINX Global Clock Inputs Global clock inputs to the FPGA are summarized in Table 3 19 Global clocks are connected to FPGA bank 3 Table 3 19 FPGA Global Clock Inputs Clock Generation FPGA Pins Signal Name Clock Source L18 LVPECL_200M_N 200 MHz LVPECL oscillator Y3 K17 LVPECL_200M_P 200 MHz LVPECL oscillator Y3 H18 SMA_GCLKN gt 5 SMA Connector J11 H17 SMA_GCLKP 5 SMA Connector J10 H19 LVDSCLKMODI P Clock Synthesizer 1 H20 LVDSCLKMOD1_N Clock Synthesizer 1 J20 SATA_MGT_GCLKP Selectable 125 MHz Oscillator or Clock Synthesizer 2 J218 SATA_MGT_GCLKN Selectable 125 MHz Oscillator or Clock Synthesizer 2 G16 SFP_MGT_GCLKN 125 MHz LVDS Oscillator G15 SFP_MGT_GCLKP 125 MHz LVDS Oscillator L19 FPGA GCLK 30MHZO 30 MHz Oscillator H14 PO_RCLK1 Port 0 Ethernet PHY Receive
43. ATA MGT REFCLKN D4 MGT REFCLKN GTP X0Y5 SATA MGT CLKSEL H15 Bank 3 I O 200 MHz LVPECL_200M_P K17 LVPECL LVPECL_200M_N LiB cer Pi Bte x C LK J4 GCLK UG201 c3 18 022608 Figure 3 8 Clock Synthesis Block Diagram Default Configuration Virtex 5 FPGA ML555 Development Kit www xilinx com 55 UG201 v1 4 March 10 2008 Chapter 3 Hardware Description XILINX Figure 3 9 shows an optional clock synthesis configuration which uses an ICS874003 jitter attenuator circuit Contact your local Xilinx representative for more information on this option FPGA_GCLK_30MHZ SMA_GCLKP J10 T 9 SMA GCLKN P13 A13 x P13 A14 DX PCIE REFCLK H19 H20 10 MHz MGT_XOY1_RCLKP AFA MGT X0Y1 RCLKN AF37 Aa Mhig MGT_X0Y0_RCLKP ALS MGT_X0Y0_RCLKN AL4 SMA J12 Pa SMA J13 9 BS SFP_MGT_GCLKP Clock 125 MHz Driver G15 Clock 9 Driver SFP MGT GCLKN G16 SFP MGT REFCLKP H4 1 SFP MGT REFCLKN H3 SATA MGT GCLKP SATA MGT GCLKN J20 J21 Clock 99 SATA MGT REFCLKP Mux Q1 SATA MGT REFCLKN Select H15 gt MGT REFCLKP gt MGT REFCLKN 200 MHz h SATA MGT CLKSEL LVPECL 200M P K17 LVPECL LVPECL_200M_N L18 gt PCICLK J14 P1 B16 X U10 FPGA L9 GCLK HU GCLKP H18 GCLKN
44. CF32PF XC5VLX50T U6 CPLD FORCE XC2C32 WIDE PCIW_EN CE1 U15 CE U1 BUSY RTRC DONE DOUT_BUSY RDWR_B CS_B PROG_B OE RESET To P2 REV_SELO From P2 REV SEL1 State Machine INIT B and Logic CPLD SPARE 1 10 CCLK MO M1 M2 2 s 55m 3 8 9 9g 30 MHZ From To P2 13 CPLD iii 94 CLK 2 9 ai S Gi HRE t c m P3 SG j pes it i DIP Sw 3 4 5 6 UG201 c4 07 022608 Notes 1 FORCE WIDE PCIW EN and RTR are FPGA general purpose I Os Figure 4 7 CPLD Configuration for Dynamic Reconfiguration Virtex 5 FPGA ML555 Development Kit UG201 v1 4 March 10 2008 www xilinx com 99 Chapter 4 Configuration XILINX SelectMAP Clock Selection The default configuration of the ML555 board is to provide Master SelectMAP configuration with the FPGA providing the configuration clock CCLK to both the FPGA and Platform Flash devices Slave SelectMAP configuration is not supported on the ML555 Table 4 1 shows the Virtex 5 FPGA configuration mode along with the correct setting for the Mode Switch SW5 Table 4 7 shows the P2 connections for the CCLK source Table 4 7 SelectMAP Clock Mode Mode Function Header P2 Jumper Settings Master SelectMAP FPGA CCLK drives Platform Flash CLKIN 1 2 Notes 1 Xilinx recommends using an FPGA configuration clock frequency of 20 MHz rather than the
45. Clock Rev Rev O Rev2 C Rev3 Default Revision Cancel Apply Help UG201 c4 13 022007 Figure 4 15 PROM Revision Properties Virtex 5 FPGA ML555 Development Kit UG201 v1 4 March 10 2008 www xilinx com 107 Chapter 4 Configuration XILINX 108 www xilinx com Virtex 5 FPGA ML555 Development Kit UG201 v1 4 March 10 2008
46. Description XILINX Serial Bus Clocking with Optional ICS874003 02 Clock Jitter Attenuator PCI Express Operation By default the ML555 board connects the PCIE_REFCLK input from the add in card connector through two DC blocking capacitors and then to GTP XOY2 MGTREFCLK pins Y4 and Y3 The ML555 board layout accommodates end user installation of an ICS874003 02 PCI Express Clock Jitter attenuator module as shown in Figure 3 10 The ICS device should be installed in board location U16 and series resistors R450 and R451 need to be removed from the board assembly Contact Integrated Devices Technology IDT for information and availability of clock jitter attenuator circuits at www idt com The PCI Express system clock is an ICS874003 02 clock jitter attenuator circuit The ICS device has dual LVDS outputs one of which is connected to GTP DUAL tile X0Y2 MGTREFCLK and the other is connected to FPGA global clock input pins J16 and J17 The jitter attenuator can generate either a 100 MHz or a 250 MHz reference clock for the GTP transceiver and clock management tile CMT within the FPGA Figure 3 10 shows the connections from the PCI Express connector to the jitter attenuator and then to the FPGA The CPLD image provided with the ML555 board by default selects a 250 MHz reference clock to be generated by the ICS874003 02 Spare I O from the FPGA to CPLD could be used to dynamically select different GTP reference clocks to be generated by the j
47. FX BERG EPHY CPLD SPAREI B12 User defined CPLD SPARE2 A13 PCIW EN C13 Potential dynamic reconfiguration um ss a us Virtex 5 FPGA ML555 Development Kit UG201 v1 4 March 10 2008 www xilinx com 71 Chapter 3 Hardware Description Table 3 26 FPGA Clock Capable I O Connectivity Continued 2 XILINX Signal Name FPGA Pin FPGA Bank Bank Vcco Volts Function DQS2_B AA30 17 1 8 DDR2 memory data strobes for data bytes 2 1 and 0 DQS2 AA29 DQS1_B AC30 DOS1 AB30 DQS0_B AA31 DOSO AB31 DOQS5 B AJ26 21 1 8 DDR2 memory data strobes for data bytes 5 4 and 3 DQS5 AH27 DQS4_B AK27 DQS4 AK28 DQS3_B AJ29 DQS3 AK29 DQS7_B AJ11 22 1 8 DDR2 memory data strobes for data bytes 7 and 6 DOS7 AK1 DOS6_B AD11 DQS6 AD10 SCL AE8 DDR2 SODIMM serial clock for presence detection synchronization with the SDA bidirectional data signal IDELAYCTRL Reference Clock Generation A 200 MHz reference clock for the IDELAYCTRL block is required if the user application uses the IOB variable delay elements The ML555 board provides a dedicated 200 MHz LVPECL_25 oscillator on the board connected to the global clock inputs as shown in Table 3 19 page 57 The IDELAYCTRL reference clock can alternately be generated within the FPGA or using one of the clock synthesizers on the board There are three methods to generate the reference clock depending on application usage
48. HUNT ON SHUNT OFF SHUNT OFF 1 64 bit 133 MHz memory reference design for PCI X operation Notes 1 See XAPP1022 Ref 5 This application note demonstrates how to generate an Endpoint Block Plus PIO example design and test the design function in a PC using a memory endpoint test driver 86 In concert with the XC2C32 CPLD the XCF32PFS48C supports static and dynamic reconfiguration of the FPGA Chapter 4 Configuration provides more details concerning the ML555 board configuration www xilinx com Virtex 5 FPGA ML555 Development Kit UG201 v1 4 March 10 2008 XILINX Chapter 4 Configuration The Virtex 5 FPGA ML555 board includes several options to configure the XC5VLX50T FPGA XC2C32 CoolRunner II CPLD and the XCF32PF Platform Flash The basic configuration modes for the Virtex 5 family are e JTAG mode via Parallel Cable IV Platform Cable USB or equivalent e Master SelectMAP mode via CPLD and Platform Flash e Slave SelectMAP mode via CPLD and Platform Flash e Slave Serial mode via CPLD and Platform Flash e Master Serial mode via CPLD and Platform Flash The CPLD and Platform Flash can only be configured via JTAG The Platform Flash contains up to four unique bitstreams for programming the FPGA The unique combination of the FPGA connected to the Platform Flash through the CPLD allows for static and dynamic bitstream selection of the FPGA via Slave and Master SelectMAP modes This chapter provides a
49. High Risk Applications Xilinx specifically disclaims any express or implied warranties of fitness for such High Risk Applications You represent that use of the Design in such High Risk Applications is fully at your risk 2006 2008 Xilinx Inc All rights reserved XILINX the Xilinx logo and other designated brands included herein are trademarks of Xilinx Inc PCI PCI X PCle and PCI Express are trademarks or registered trademarks of PCI SIG All other trademarks are the property of their respective owners Revision History The following table shows the revision history for this document Date Version Revision 09 27 06 1 0 Initial Xilinx release 12 27 06 1 1 Changed device package to FFG1136 Inserted new Table 3 3 showing correlation between PCIe signals P13 connector FPGA pins and GTP DUAL tile Revised Chapter 3 Hardware Description to reflect board design change where ICS874003 02 PCI Express Clock Jitter attenuator module is now a customer option added Figure 3 8 and changed Table 3 1 Table 3 9 Table 3 18 Table 3 19 Table 3 20 and Serial Bus Clocking with Optional ICS874003 02 Clock Jitter Attenuator PCI Express Operation page 60 Removed Appendix A Virtex 5 FPGA ML555 Development Kit www xilinx com UG201 v1 4 March 10 2008 Date 02 27 07 Version 1 2 Revision Changed document title and updated Additional Documentation page 7 Specified FPGA de
50. IS PROVIDED AS IS WITH ALL FAULTS AND THE ENTIRE RISK AS TO ITS FUNCTION AND IMPLEMENTATION IS WITH YOU YOU ACKNOWLEDGE AND AGREE THAT YOU HAVE NOT RELIED ON ANY ORAL OR WRITTEN INFORMATION OR ADVICE WHETHER GIVEN BY XILINX OR ITS AGENTS OR EMPLOYEES XILINX MAKES NO OTHER WARRANTIES WHETHER EXPRESS IMPLIED OR STATUTORY REGARDING THE DESIGN INCLUDING ANY WARRANTIES OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE TITLE AND NONINFRINGEMENT OF THIRD PARTY RIGHTS IN NO EVENT WILL XILINX BE LIABLE FOR ANY CONSEQUENTIAL INDIRECT EXEMPLARY SPECIAL OR INCIDENTAL DAMAGES INCLUDING ANY LOST DATA AND LOST PROFITS ARISING FROM OR RELATING TO YOUR USE OF THE DESIGN EVEN IF YOU HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES THE TOTAL CUMULATIVE LIABILITY OF XILINX INCONNECTION WITH YOUR USE OF THE DESIGN WHETHER IN CONTRACT OR TORT OR OTHERWISE WILL IN NO EVENT EXCEED THE AMOUNT OF FEES PAID BY YOU TO XILINX HEREUNDER FOR USE OF THE DESIGN YOU ACKNOWLEDGE THAT THE FEES IF ANY REFLECT THE ALLOCATION OF RISK SET FORTH IN THIS AGREEMENT AND THAT XILINX WOULD NOT MAKE AVAILABLE THE DESIGN TO YOU WITHOUT THESE LIMITATIONS OF LIABILITY The Design is not designed or intended for use in the development of on line control equipment in hazardous environments requiring fail safe controls such as in the operation of nuclear facilities aircraft navigation or communications systems air traffic control life support or weapons systems
51. J10 and J11 connected to the global clock inputs These GTP transceivers are connected to the PCI Express connector J13 The ML555 board supports x1 x4 and x8 lane endpoint PCI Express applications ES silicon requires specific GTP DUAL tile connections for 8 lane PCI Express Endpoint applications Production silicon does not have these restrictions The 100 MHz differential PCI Express system board spread spectrum clock input goes to GTP MGTREFCLK inputs Y4 and Y3 For multilane PCI Express designs internal dedicated clock routing resources are used to distribute the PCI Express system clock to GTP DUAL tiles X0YO XOY1 and X0Y3 See Serial Bus Clocking with Optional ICS874003 02 Clock Jitter Attenuator PCI Express Operation page 60 for additional information 58 www xilinx com Virtex 5 FPGA ML555 Development Kit UG201 v1 4 March 10 2008 XILINX Clock Generation PCI Express applications can utilize the system board s 100 MHz clock input on the GTP MGTREFCLK clock input or synthesize a 100 MHz clock using the clock synthesizer a DCM and GTP clocking resources SATA applications must synthesize a 150 MHz clock using Clock Synthesizer 2 Gigabit Ethernet applications can use either the 125 MHz oscillator or a synthesized clock Fibre channel applications must synthesize either a 53 125 MHz or a 106 25 MHz clock When using the SFP connectors for Fibre channel and Gigabit Ethernet the REFCLK for the SFP must be either Fib
52. KEY NC 3 3V KEY NC 3 3V KEY NC A14 AUXV NC B14 unused NC A15 EDGE_RST_B J30 In B15 GND NC A16 VCC3V3 NC B16 CLK_FROM_EDGE L34 J14 In A17 EDGE_GNT_B N29 In B17 GND NC A18 GND NC B18 EDGE REO B M30 Out A19 EDGE PME B L30 Out B19 VCC3V3 NC A20 EDGE AD30 L31 In Out B20 EDGE AD31 K31 In Out A21 VCC3V3 NC B21 EDGE AD29 P31 In Out A22 EDGE AD28 P30 In Out B22 GND NC A23 EDGE AD26 N30 In Out B23 EDGE AD27 M31 In Out A24 GND NC B24 EDGE AD25 R28 In Out A25 EDGE AD24 R29 In Out B25 VCC3V3 NC A26 EDGE IDSEL P29 In B26 EDGE_CBE3 F33 In Out A27 VCC3V3 NC B27 EDGE AD23 T31 In Out A28 EDGE AD22 R31 In Out B28 GND NC A29 EDGE AD20 T30 In Out B29 EDGE AD 21 U30 In Out A30 GND NC B30 EDGE AD19 T28 In Out A31 EDGE AD18 T29 In Out B31 VCC3V3 NC 30 www xilinx com Virtex 5 FPGA ML555 Development Kit UG201 v1 4 March 10 2008 XILINX 64 bit Edge Connector for PCI Operation Table 3 4 P1 PCI Edge Connector Pinout Continued ane Signal FPGA Pin i3 A Signal FPGA Pin i A32 EDGE_ADI6 U28 In Out B32 EDGEADI7 U2 m Out A33 VCC3V3 NC B33 EDGE CBE2 E34 In Out A34 EDGE FRAME B F34 In Out B34 GND NC A35 GND NC B35 EDGE IRDY B J32 In Out A36 EDGE_TRDY_B H33 In Out B36 VCC3V3 NC A37 GND NC B37 EDGE DEVSEL B H34 In Out A38 EDGE STOP B J34 In Out B38 EDGE PCIXCAP E
53. MAX3008 RS 232 interface device operates from a 2 5V supply The interface between the MAX3008 and the FPGA is at LVCMOS 25 standard levels The user must provide a UART core internal to the FPGA to enable serial communication between the FPGA and USB attached serial port UART cores are available from the Xilinx IP center at www xilinx com ipcenter Table 3 16 describes the RS 232 interface pin assignments Table 3 16 RS 232 Interface Signal Names and Pin Assignments Signal Name FPGA In Out Description FPGA Pin Number USB_RX Out USB Receive Data FPGA UART Transmit port K21 USB TX In USB Transmit Data FPGA UART Receive port L20 USB RIS B In USB Request to Send L21 USB CTS B Out USB Clear to Send 22 USB_DSR_B Out USB Data Set Ready K16 USB_DTR_B In USB Data Terminal Ready L15 50 www xilinx com Virtex 5 FPGA ML555 Development Kit UG201 v1 4 March 10 2008 XILINX Universal Serial Bus Port Table 3 16 RS 232 Interface Signal Names and Pin Assignments Continued Signal Name FPGA In Out Description FPGA Pin Number USB_RST_B In Out Active Low USB Reset must be held Low for 15 us to J15 initiate a reset to the USB controller USB SUSPEND B In USB Suspend output from USB port driven High when L16 the USB controller enters the suspend state Notes 1 These signals are connected to FPGA bank 1 The FPGA reference voltage Veco for this bank is 2 5V See t
54. Memory Interface Generator MIG User Guide Ref 10 contains detailed technical information for designing memory controllers using Virtex 5 FPGAs Table 3 5 SDRAM Interface Signal Descriptions pes Signal FPGA Pin eee n Signal FPGA Pin aes 1 DDR2_VREF NC 2 GND NC 3 GND NC 4 DO4 V25 In Out 5 DQO W24 In Out 6 DO5 W25 In Out 7 DO1 V24 In Out 8 GND NC 9 GND NC 10 DMO V30 Out 11 DQS0_B AA31 In Out 12 GND NC 13 DOSO0 AB31 In Out 14 DO6 Y27 In Out 15 GND NC 16 DQ7 W27 In Out 17 DQ2 Y26 In Out 18 GND NC 19 DQ3 W26 In Out 20 DO12 W29 In Out 21 GND NC 22 DO13 V29 In Out 23 DOS V28 In Out 24 GND NC 25 DQ9 V27 In Out 26 DM1 AD30 Out 27 GND NC 28 GND NC 29 DQS1_B AC30 In Out 30 CKO AH9 Out 31 DOS1 AB30 In Out 32 CKO0 B AH10 Out 33 GND NC 34 GND NC 35 DO10 W31 In Out 36 DO14 Y28 In Out 37 DQ11 Y31 In Out 38 DQ15 Y29 In Out 39 GND NC 40 GND NC 41 GND NC 42 GND NC 43 DQ16 AC29 In Out 44 DQ20 AF29 In Out 45 DQ17 AF31 In Out 46 DQ21 AF30 In Out 47 GND NC 48 GND NC 49 DQS2_B AA30 In Out 50 No connect NC Virtex 5 FPGA ML555 Development Kit www xilinx com 35 UG201 v1 4 March 10 2008 Chapter 3 Hardware Description Table 3 5 SDRAM Interface Signal Descriptions Continued XILINX
55. O MR a Boundary Scan 22 SlaveSerial 3 SelectMAP 3 Desktop Configuration 3 Direct SPI Configuration E SystemAcE EIPROM File Formatter Modes Right click to Add Device or Initialize JTAG chain Operations Boundary Scan BATCH CMD setMode bs 3 BATCH CMD setMode bs gt lt Output Error Waring No Cable Connection No File Open UG201 c4 14 052307 Figure 4 11 Initialize JTAG Chain with iMPACT Tool PA BO da m File Edit View Operations Output Debug Window Help TDK Fa SAX SRN Gi 28008 Right click device to select operations Boundary Scan 38leveSerial Em R T 29 Desktop Configuration i e a a Direct SPI Configuration E SystemACE xc5vh Qt xc2c32a xcf32p xcf32p EPROM File Formatter mo zf e f e fe Modes x Operations Boundary Scan BB i es an en a a aii a Mani rt e pe P pr PPP Y a lt Output Error Waring Configuration Platform Cable USB 6 MHz usb hs UG201 c4 15 052307 Figure 4 12 ML555 JTAG Chain with All Four Programmable Devices in the Chain Virtex 5 FPGA ML555 Development Kit www xilinx com 105 UG201 v1 4 March 10 2008 Chapter 4 Configuration XILINX Programming Properties S Programming Properties Advanced PROM Programming Properties Revision Properties Verity r General CPLD
56. PCI Express Operation 00 000 e eee 23 64 bit Edge Connector for PCI Operation 0 0 e cee eee 29 ML555 Configuration Headers for PCI Operation 0 6 6 e eee eee 33 M66EN 66 MHz Enable Connector P9 0 eee ete eee 33 PME Power Management Event Connector P7 0 0 ccc cee eee eee 33 PCIXCAP PCI X Capability Connector P8 0 6 eee ene ee 33 Reference Designs for PCI and PCI X Operation 00 0 c eee eee eee 33 DDR2 SDRAM SODIMM 0 000 rhe 34 Small Form factor Pluggable SFP Module Interface 39 Serial ATA Interface iode IN tees oie sans 40 SMA Contnlectofs cd tnr Ner dedit Ke uentis tete e NS ues M inen a 41 Ethernet PHY Daughtercard Support 00 0 cece eee ee 41 LVDS Interface 5 odore eR ere Pe qe E HC pedes sae 44 SAMTEC Mezzanine Expansion Card Support 0 cee eee eens 50 Universal Serial Bus Port 0 00 cence eene 50 USB t UART Bridge u 22222 ORE ea an 51 Clock Generation eoe erahnen 52 Global Clocks Inputs mtu b eet ee pe ep ate dg tans eae ede ap dup dte ated eee eg 57 Virtex 5 FPGA ML555 Development Kit www xilinx com UG201 v1 4 March 10 2008 XILINX GTP Reference Clock Inputs 2eeeeeeeeeeeeeneeeeeenennnne nenn 58 Parallel Bus Clocking PCI Operation 0 0 6 0c cece eee ee 59 Serial Bus Clocking with Optional ICS874003 02 Clock Jitter Att
57. PCI Express and PCI bus applications where add in card power is limited by specification to 25W Power Supply Monitoring The ML555 board provides capabilities to monitor and measure the voltage and current for the FPGA internal voltage and all analog GTP voltage regulators Figure 3 17 shows a block diagram of the voltage sensing circuit Only those supplies central to PCI Express power functions are provided with power supply monitoring capabilities A 10 mQ Kelvin resistor is placed in series between the regulated output and the load on the board The input and output port of the series resistor is routed to a header that can be connected to a Volt Ohm Meter VOM to measure the voltage drop across the resistor The current then can be calculated dividing the voltage by 0 0109 Power equals voltage times current Virtex 5 FPGA ML555 Development Kit UG201 v1 4 March 10 2008 82 www xilinx com XILINX Voltage Regulators Voltage Kelvin Regulator Resistor To Load on ML555 ViN In o2 Voltage Measurement O1 Test Points UG201_c3_16_092706 Figure 3 17 Voltage Measurement Test Points The ML555 board provides headers that can be used to monitor the three GTP transceiver analog power supplies as well as the internal FPGA voltage Vccmr For PCI Express applications power sensing is provided on the output of the 12V to 5V power regulator so a total 5V power consumption for the PCI Express application can be determined
58. PGA global clock network on pins J16 and J17 Internal FPGA clock buffers distribute this clock to other GTP DUAL tiles for PCI Express operation The architecture of the FPGA permits an external MGTREFCLK to be driven a maximum of three GIP DUAL tiles up or down See Serial Bus Clocking with Optional ICS874003 02 Clock Jitter Attenuator PCI Express Operation page 60 for additional information 54 www xilinx com Virtex 5 FPGA ML555 Development Kit UG201 v1 4 March 10 2008 XILINX Clock Generation Figure 3 8 shows a block diagram of the default clock synthesis configuration provided on production ML555 boards U10 FPGA FPGA_GCLK_30MHZ L19 SMA_GCLKP J10 Hi7 MA_GCLKN J11 SMA_GC EIS P13 A13 X r ET DC Block Y4 MGT_REFCLKP 2 Capacitors v3 MGT_REFCLKN H19 GCLKP 10 MHz H20 GCLKN MGT_XOY1_RCLKP AF4 MGT_X0Y1_RCLKN AF3 MOTEL OT GTP X0Y1 25 MHz MGT_X0YO_RCLKP AL5 EVE MGT REFCLKP MGT XOYO RCLKN AL4 MGT REFCLKN GTP X0YO SMA s12 P MGT REFCLKP SMA Es GTP X0Y3 J13 MGT_REFCLKN SFP_MGT_GCLKP G15 GCLKP Clock Clock 0 SFP MGT GCLKN G16 GCLKN 125 MHz SFP MGT REFCLKP H4 i Driver Driver 9f 4 SFP MGT REFCLKN H3 dem s gt MGT_REFCLKP MGT_REFCLKN GTP XoY4 SATA MGT GCLKP J20 LKP SATA MGT GCLKN J21 CRM 2 5V SATA MGT REFCLKP EA MGT REFCLKP me S
59. See Clock Generation page 52 for information on how the PCI bus clock is connected on the ML555 board 32 www xilinx com Virtex 5 FPGA ML555 Development Kit UG201 v1 4 March 10 2008 XILINX 64 bit Edge Connector for PCI Operation The PCI bus on the board schematics has signal names of the form EDGE_ lt signal name gt denoting the card edge connector signals The signal names listed in the A Side and B Side columns of Table 3 4 and Table 3 1 page 24 are standard PCI signal names The ML555 board supports both PCI and PCI X applications The edge connector interfaces with the system board connector Xilinx has LogiCORE solutions available for both PCI and PCI X designs to facilitate getting started with the application specific design When installing the ML555 board in a PCI or PCI X add in card slot the PCI Express bracket must be removed from the ML555 board prior to plugging into the system The connectors on the ML555 board are oriented for PCI Express operation When using a PCI system the motherboard should be removed from the system chassis as the I O on the ML555 board is not oriented to escape out the back of the system unit frame ML555 Configuration Headers for PCI Operation M66EN 66 MHz Enable Connector P9 P1 B49 is wired to two pin header pin P9 1 With the P9 jumper shunt removed M66EN has a 0 01 uF capacitor to GND Placing the jumper shunt across pins 1 and 2 of P9 shorts M66EN to GND e M66EN GND
60. The Kelvin resistor for the 5V power sense point uses a 150 mQ resistor value instead of the 10 mQ resistor used in other sense circuits Current is calculated by dividing the sense voltage by 0 1509 Figure 3 18 shows the power measurement headers and Table 3 36 defines their functions Virtex 5 FPGA ML555 Development Kit www xilinx com 83 UG201 v1 4 March 10 2008 Chapter 3 Hardware Description XILINX Pam P44 20 G XaLyin XNTIX 3 apa P43 P42 P41 P19 UG201_c3_17_091706 Figure 3 18 Power Measurement Headers Table 3 36 ML555 Voltage Sensing Power Measurement Headers Header Pin Header Pin Series PCI Express Applications Applications Includes all 5V power loads Voltage Name Description SENSE SENSE Resistance AVTTX 1 2V GTP Analog Termination Voltage P41 1 P41 2 10 mQ AVCCPLL 1 2V GTP Analog PLL Supply Voltage P42 1 P42 2 10 m AVCC 1 0V GTP Analog Supply Voltage P43 1 P43 2 10 mQ VeccINT 1 0V FPGA Internal Voltage P44 1 P44 2 10 mQ 12V to 5V Converter for 5V Power Consumption in PCI Express P19 1 P19 2 150 mQ 84 www xilinx com Virtex 5 FPGA ML555 Development Kit UG201 v1 4 March 10 2008 XILINX XC2C32 CoolRunner ll CPLD U6 The ML555 board cannot margin any of the oncard power supplies Other Xilinx boards have power supply monitoring and margining capabilities for application specific functions such as memory interfaces a
61. Type Description C1 BUSY TO FLASH B I BUSY Active Low Busy signal connected from CPLD Pin 41 G1 CPLD_TDO I TDI JTAG TDI connected from CPLD JTAG TDO B4 FLASH_CE_B U1 or I CE Active Low Chip Enable connected from CPLD Pin FLASH_CE1_B U15 42 U1 or CPLD Pin 38 U15 D1 FLASH_CF_B I CF Active Low Configuration Pulse input connected to CPLD Pin 43 B3 FLASH_CLKIN I CLK Clock Input connected from Pin 1 of Header P2 C2 FLASH_CLKOUT O CLKOUT Clock Output connected to Pin 5 of Header P2 H6 FLASH DO O DO SelectMAP data bit 0 connected to FPGA Virtex 5 FPGA ML555 Development Kit UG201 v1 4 March 10 2008 www xilinx com 95 Chapter 4 Configuration Table 4 5 Pin Listing for Platform Flash Continued XILINX Pin Number Net Name Direction Pin Type H5 FLASH_D1 O D1 SelectMAP data bit 1 connected to FPGA E5 FLASH_D2 O D2 SelectMAP data bit 2 connected to FPGA D5 FLASH_D3 O D3 SelectMAP data bit 3 connected to FPGA C5 FLASH D4 O D4 SelectMAP data bit 4 connected to FPGA B5 FLASH D5 O D5 SelectMAP data bit 5 connected to FPGA A5 FLASH_D6 O D6 SelectMAP data bit 6 connected to FPGA A6 FLASH_D7 O D7 SelectMAP data bit 7 connected to FPGA H4 FLASH_EN_EXT_SEL_B I EN EXT SEL Enable External Selection input tied Low A3 FLASH OE RESET B I O OE RESET Output Enable Active Low Res
62. URL Go to http www xilinx com for the latest documentation Virtex 5 FPGA ML555 Development Kit UG201 v1 4 March 10 2008 www xilinx com 11 Preface About This Guide 12 www xilinx com XILINX Virtex 5 FPGA ML555 Development Kit UG201 v1 4 March 10 2008 XILINX Chapter 1 Introduction About the Virtex 5 FPGA ML555 Development Kit To develop parallel Peripheral Component Interconnect PCI bus and serial PCI Express bus add in card applications the Virtex 5 FPGA ML555 board is configured and then plugged into a parallel PCI bus system unit or a serial PCI Express system unit The board supports 32 bit or 64 bit PCI bus datapaths The ML555 board has an eight lane connector that allows the board to be plugged into an eight lane add in card socket for PCI Express operation The ML555 kit does not include a lane conversion adapter which would allow the eight lane ML555 board to plug into an add in card socket for single lane PCI Express operation Additional information and design resources associated with the ML555 development kit is available at http www xilinx com products devkits HW V5 ML555 G htm Parallel Bus Development for PCI Operation This Virtex 5 FPGA based kit provides a development platform for designing and verifying PCI and PCI X applications utilizing Xilinx LogiCORE intellectual property IP cores in a 3 3V signaling environment The ML555 board
63. Virtex 5 FPGA ML555 Development Kit for PCI and PCI Express Designs User Guide XILINX XILINX Xilinx is disclosing this Document and Intellectual Property hereinafter the Design to you for use in the development of designs to operate on or interface with Xilinx FPGAs Except as stated herein none of the Design may be copied reproduced distributed republished downloaded displayed posted or transmitted in any form or by any means including but not limited to electronic mechanical photocopying recording or otherwise without the prior written consent of Xilinx Any unauthorized use of the Design may violate copyright laws trademark laws the laws of privacy and publicity and communications regulations and statutes Xilinx does not assume any liability arising out of the application or use of the Design nor does Xilinx convey any license under its patents copyrights or any rights of others You are responsible for obtaining any rights you may require for your use or implementation of the Design Xilinx reserves the right to make changes at any time to the Design as deemed desirable in the sole discretion of Xilinx Xilinx assumes no obligation to correct any errors contained herein or to advise you of any correction if such be made Xilinx will not assume any liability for the accuracy or correctness of any engineering or technical support or assistance provided to you in connection with the Design THE DESIGN
64. ability of other compatible products including device capacity clock speeds and CAS latency options in the 200 pin SODIMM form factor The ML555 board memory interface design includes on board 50 Q termination resistors to 0 9V at the FPGA end of the interface for the 64 bit bidirectional DQ data bus The differential DQS signals sourced from the FPGA should use a DIFF_SSTL18_II primitive as the I O driver element The address and control signals have 50 Q termination resistors to 0 9V at the SODIMM end of the interface The SODIMM provides a 120 Qtermination network for the differential clock inputs On die termination ODT is used to terminate www xilinx com Virtex 5 FPGA ML555 Development Kit UG201 v1 4 March 10 2008 2 XILINX DDR2 SDRAM SODIMM the DQ and DQS ports on the SODIMM side of the interface The Xilinx Digitally Controlled Impedance DCI standard SSTL18_I_DCI can be utilized to terminate unidirectional address and control signals transmitted by the FPGA External 50 Q reference resistors are provided to VRN and VRP for the memory interface banks of the XC5VLX50T FPGA See the Virtex 5 FPGA User Guide for additional information on DCI For assistance designing a DDR2 interface refer to the Xilinx Memory Corner website at www xilinx com products design resources mem corner For application assistance specifically for Virtex 5 FPGA DDR2 memory controllers refer to XAPP858 Ref 8 and XAPP865 Ref 9 Xilinx
65. al information 2 Bank 1 GPIO clock capable I O signals All others are in FPGA Bank 19 w NC no connect 4 Bank 19 clock capable I O pins Table 3 13 SAMTEC Pin Connections P33 O2P DPP33 signal FPGA Ope pp pag signan FPGA Odd Pin Even Pn 1 GP1O2 1233 P2 AF13 2 GP1O2 ID22 PO AE13 3 GP102 D3 NO AG12 4 GP1O2 D2 NO AE12 5 GND N A 6 GND N A 7 No Connect N A 8 No Connect N A 9 No Connect N A 10 No Connect N A 11 GND N A 12 GND N A 13 GP1O2 D1 P ACA 14 GP1O2 DO P AB6 15 GP1O2 D1 N AC5 16 GP102 DO N AB7 17 GND N A 18 GND N A 19 GP10O2 I19 P AA5 20 GP102_I18_P ACT 21 GP1O2 I19 N AB5 22 GP1O2 I18 N AD7 23 GND N A 24 GND N A 25 GP10O2 I17 P Y8 26 GP1O2 I16 P AD4 27 GP102_I17_N Y9 28 GP102_116_N AD5 29 GND N A 30 GND N A 31 GP102_I15_P AA6 32 GP102_I14_P AD6 33 GP1O2 I15 N Y7 34 GP102_I14_N AE6 35 GND N A 36 GND N A 37 GP102_113_P W6 38 GP1O2 I12 P2 AE7 www xilinx com 47 Virtex 5 FPGA ML555 Development Kit UG201 v1 4 March 10 2008 Chapter 3 Hardware Description XILINX Table 3 13 SAMTEC Pin Connections P33 Continued OR DPP33 signat FPGA oas DpPa3s signal FPGA Odd Pin Even x 39 GPIO2TI3 NO ys 40 GPIO212 NO Ars 41 GP1O2 I1 PO AG5 42 GP10O2 H0 P W7 43 GP102_I11_N AF5 44 GP1O2 I10 NO V7 45 GND N A
66. aphic illustration Caution Failure to configure SW8 and P18 properly might result in damage to the ML555 onboard 12V to 5V regulator module PCI and or PCI X Application Add in Card Power Input For PCI or PCI X applications the host motherboard provides multiple power rails to the add in card as shown in Table 3 32 The ML555 board does not use 3 3V AUX 12V or 12V from the system unit in the PCI mode The PCI Card Electromechanical Specification places restrictions on the amount of power an add in card is permitted to consume from the system unit power supply An add in card can consume a maximum of 25 Watts from all power rails combined Current values specified in Table 3 32 are maximum supply currents provided by voltage An add in card cannot utilize all maximum capacities and stay under the 25W maximum specification Table 3 32 PCI and PCI X Add in Card Power Rail Capacities PCI or PCI X System Unit Power Rail 25W Slot Maximum 3 3V 7 6A 3 3V AUX 375 mA 5V 5 0A 12V 100 mA 12V 500 mA Notes 1 All values are maximum current permitted per voltage supply Cards must still stay within 25W maximum Virtex 5 FPGA ML555 Development Kit UG201 v1 4 March 10 2008 www xilinx com 79 Chapter 3 Hardware Description XILINX Add in Card DC Power Input PCI Express Operation For PCI Express applications the ML555 board has 3 3V and 12V power available from the system uni
67. as an output port to route internal debug signals for triggering or viewing on an oscilloscope Consult the Virtex 5 FPGA User Guide for additional information on clocking and the appropriate I O standards for high speed clock and data signals www xilinx com Virtex 5 FPGA ML555 Development Kit UG201 v1 4 March 10 2008 2 XILINX Clock Generation Table 3 18 lists the destination pins of these clock sources The PCI bus clock goes to a regional clock input and a global clock input of the FPGA as shown in Table 3 18 The differential 100 MHz reference clock input for PCI Express designs PCIE REFCLK P N is described in Serial Bus Clocking with Optional ICS874003 02 Clock Jitter Attenuator PCI Express Operation page 60 The two clock synthesizer outputs go to GTP REFCLK inputs as well as global clock inputs Table 3 18 ML555 Board Clock Sources Clock Designator Output Type Frequency Destination Pin Y1 Differential LVDS 125MHz Referto Figure 3 8 Y2 Single Ended LVCMOS 30 MHz Clock Buffer U9 input pin 1 P then to FPGA U10 Bank 3 L19 P See Figure 4 8 page 100 for 30 MHz clock distribution Y3 Differential LVPECL 200MHz FPGA U10 Bank 3 K17 P and L18 N P1 pin B16 Single Ended PCI3 3V 33 MHz to FPGA U10 Bank 3 J14 Global Clock P 133 MHz FPGA U10 Bank 3 Regional Clock input pin L34 P 8 put p U18 Clock Differential LVDS 3125 MHz to Refer to Figure 3
68. ck Synthesizer 1 and SW12 11 is for the NO input of Clock Synthesizer 2 Parallel Mode Operation Each clock synthesizer has one set of subminiature DIP switches to set the multiplier and divider settings in parallel mode Clock Synthesizer 1 with a 10 MHz reference clock input can be set to 0x019 through 0x046 as shown in Table 3 22 page 64 Clock Synthesizer 2 with a 25 MHz reference clock input can be set to 0x00A through 0x01C as shown in Table 3 23 page 66 DIP switches are provided on the board to allow user selection of multiplier values that result in valid VCO lock ranges Multiplier bits that would result in a VCO unlock condition are hardwired to a logic 0 level on the board Figure 3 11 shows the locations of the switches for both synthesizers www xilinx com Virtex 5 FPGA ML555 Development Kit UG201 v1 4 March 10 2008 X XILINX Clock Generation iii She inthe o 1 gt a o m o cat 6 E35 W08141795 nt eiii nier oe Ror unti amr EU SW12 EIRTERTENER 1515133532 EERE we Parallel Load Inputs for ICS2 SW10 Parallel Load Inputs for ICS1 P T oonsvact sa E E P A E SW11 Parallel Load ICS2 nz i SWSO9 Parallel Load ICS1 UG201 c3 10 092706 Figure 3 11 Clock Synthesizer Switches Parallel Mode Pushbutton switch SW is used to parallel load the multiplier and divisor selections for Synthesizer 1 U8 and switch SW11 is used to parallel load the multiplier a
69. connector when clocking the GTP transceiver with an external clock source Daughtercard Support The ML555 board provides a Xilinx Generic Interface XGI connector system wired to support attachment of the Xilinx Ethernet PHY Daughtercard part number HW AFX BERG EPHY The EPHY daughtercard is not included with the development kit but can be purchased separately The XC5VLX50T FPGA has up to four embedded tri mode Ethernet MAC blocks that provide the data link layer interface to the external PHY The Xilinx library of soft Ethernet LogiCORE products can also provide Ethernet connectivity solutions The PHY daughtercard contains two Marvell Alaska Gigabit Ethernet over copper transceivers part number 88E1111 The PHY devices perform all physical layer functions operate at 10 100 1000 Mb s and support the embedded tri mode Ethernet MAC within the Virtex 5 XC5VLX50T FPGA The PHY supports GMII MII SGMII and RGMII Ethernet physical interfaces The ML555 board contains a 125 MHz oscillator used for the embedded tri mode EMAC reference clock The ML555 development kit contains two plastic standoffs used with the PHY daughter card for mechanical support Refer to UG065 Ref 3 before powering up the ML555 board and PHY daughtercard because the configuration headers on both boards must be set up properly before power is applied Table 3 10 and Table 3 11 list the signal and pin assignments for the J15 and J16 connectors respectively www
70. ctromechanical Specification Additional Support Resources To search the database of silicon and software questions and answers or to create a technical support case in WebCase see the Xilinx website at http www xilinx com support Virtex 5 FPGA ML555 Development Kit www xilinx com 9 UG201 v1 4 March 10 2008 Preface About This Guide Typographical Conventions This document uses the following typographical conventions An example illustrates each 10 XILINX convention Convention Meaning or Use Example See the Virtex 5 FPGA References to other documents Configuration Guide for more Italic font information Emphasis in text The address F is asserted after clock event 2 Underlined Text Indicates a link to a web page http www xilinx com virtex5 www xilinx com Virtex 5 FPGA ML555 Development Kit UG201 v1 4 March 10 2008 X XILINX Online Document The following conventions are used in this document Typographical Conventions Convention Blue text Meaning or Use Cross reference link to a location in the current document Example See the section Additional Documentation for details Refer to Clock Management Technology CMT in Chapter 2 for details Red text Cross reference link to a location in another document See Figure 5 in the Virtex 5 FPGA Data Sheet Blue underlined text Hyperlink to a website
71. d 5 FPGA_DONE I 103 DONE pin from FPGA 6 FPGA_BUSY_B I 104 DOUT Busy pin from FPGA 7 VCC2V5 I VCCIO1 2 5V I O Power 8 PROG_SW_B I 105 Input from Pushbutton SW6 9 FPGA_TDO I TDI JTAG TDI from FPGA 10 JTAG_TMS I TMS JTAG TMS 11 JIAG TCK I TCK JTAG TCK 12 ICS_FSEL2 I 106 CPLD output to ICS874003 02 FSEL2 input 13 MAN_AUTO_B I 107 Manual Auto Select pin from Header P3 14 ICS_MR I O 108 CPLD output to ICS874003 02 master reset input 15 VCC1V8 I VCC 1 8V Power 16 ICS_OEA I O IO9 CPLD output to ICS874003 02 output enable port A input 17 GND I GND2 Ground 18 PB SW B I I CPLD input from Pushbutton SW7 Pin 18is CPLD input only 19 ICS FSEL1 I O IO10 CPLD output to ICS874003 02 FSEL1 input 20 ICS FSELO I O IO11 CPLD output to IC5874003 02 FSELO input 21 CPLD_SPARE1 I O IO12 Spare I O connected to FPGA pin B12 22 CPLD SPARE2 I O IO13 Spare I O connected to FPGA pin A13 23 FPGA CS B I IO14 Chip Select from FPGA 24 CPLD TDO O TDO JTAG TDO to Flash 25 GND I GND3 Ground 26 VCC2V5 I VCCIO2 2 5V I O Power 27 INIT_B O 1015 Output connected to INIT_B pin of FPGA 28 PROG_B O 1016 Output connected to PROG_B pin of FPGA 29 WIDE O IO17 Output connected to Pin F12 of FPGA 30 EDGE RST I B I IO GS R Input connected from Pin A15 of Edge PCI 31 FORCE oO IO GOE1 Output connected to Pin F13 of FPGA 94 www xilinx com Virtex 5 FPGA ML555 Development Kit UG201 v1 4 March 10 2008 XILINX Table 4 4 CPLD Pin Listi
72. d Figure 3 9 Virtex 5 FPGA ML555 Development Kit UG201 v1 4 March 10 2008 www xilinx com 57 Chapter 3 Hardware Description XILINX Table 3 19 FPGA Global Clock Inputs Continued FPGA Pins Signal Name Clock Source K18 K19 H13 No connects Unused global clock inputs to FPGA Notes 1 AC coupled 2 The SMA clock input can be differential or single ended When driven with a single ended clock source connector J10 should be used to input the clock to the FPGA Differential clock inputs to the FPGA should use the IBUFDS input buffer library primitive Setting the DIFF TERM attribute of the IBUFDS to TRUE provides 100 Qon chip termination for the LVDS clock source driver Single ended clock input All other clocks are differential inputs Control output port SATA MGT CLKSEL on FPGA pin H15 0 selects the fixed 125 MHz oscillator output 1 selects the variable frequency Clock Synthesizer 2 output as the clock source for the differential global clock inputs on FPGA pins J20 and J21 The SMA GCLK ports can be used as outputs to route internal single ended or differential signals to an oscilloscope for debugging ML555 designs GTP Reference Clock Inputs All GTP REFCLK inputs have clock inputs routed to them Table 3 20 shows GTP location designators FPGA pins and clock sources that drive the reference clock inputs of the GTP transceivers The lanes are for PCI Express applications Tab
73. d Receive Connections Between P32 and P33 Virtex 5 FPGA ML555 Development Kit www xilinx com 49 UG201 v1 4 March 10 2008 Chapter 3 Hardware Description XILINX SAMTEC Mezzanine Expansion Card Support The ML555 board supports the addition of mezzanine boards attached to connectors P32 and P33 5V DC power is provided to the mezzanine board on connector P48 see Table 3 14 A serial configuration interface is provided on connector P47 see Table 3 15 The P47 interface is connected to FPGA Bank 1 with a Vcco reference voltage of 2 5V Figure 3 5 page 45 shows the P47 and P48 mezzanine connectors Table 3 14 Connector P48 Pinout Connector Pin Signal Pin 1 5V Pin 2 GROUND Table 3 15 Connector P47 Pinout Connector Pin Signal FPGA Pin Pin 1 EXT_SEN K14 Pin2 EXT SDATA L14 Pin 3 EXT SCLK H22 Pin 4 EXT RESET G22 Universal Serial Bus Port The ML555 board provides a connector P1 for a Universal Serial Bus USB port A USB to RS 232 converter module is provided on the board The FPGA connection uses standard UART interface protocols while the external interface is USB 2 0 Device drivers are provided on the reference CD to enable a Microsoft Windows or Linux operating system personal computer to emulate a serial port The board uses the Maxim MAX3008EUP U4 device to convert the RD TD RTS and CTS signals from 3 3V CP2102 side to 2 5V FPGA side of the interface The
74. d sequence to demonstrate selection of 20 MHz CCLK configuration clock in Platform Flash Image Generation and Programming page 101 Virtex 5 FPGA ML555 Development Kit www xilinx com UG201 v1 4 March 10 2008 Table of Contents Preface About This Guide Guide Contents Mr 7 Additional Documentation suus eee eens 7 Additional Support Resources i e ere e ERE er RR CERRAR ee 9 Typographical Conventions 0 00 6 eh 10 Online Document s eset Gaede ee EE E Sea Mowe it een ete d 11 Chapter 1 Introduction About the Virtex 5 FPGA ML555 Development Kit 22220 13 Parallel Bus Development for PCI Operation 22cceeeeeeeeeneeeenn 13 Serial Bus Development cesse caine et hte eren ddd ale obere re n etn 15 Kit Contents idee er Sr o geb iR ea kie u 15 ML555 Board a0 oo hA a ee Ee TAE bb LEE Ue pere 15 Available Xilinx Accessories ssssssseseeses e 16 Conversion Module SMA to SATA HW AFX SMA SATA 0 0 cece eee 16 Conversion Module SMA to RJ45 HW AFX SMA RJ45 0 0 eee eee eee 16 Conversion Module SMA to HSSDC2 HW AFX SMA HSSDQ2 2 2 17 PHY Daughtercard HW AFX BERG EPHY 2 6 cece ce nen 17 Chapter 2 Getting Started Documentation and Reference Design CD 0 00 00 c eee 19 Initial Board Checks Before Applying Power 0 0 0005 19 Chapter 3 Hardware Description Edge Connector for
75. de Switch towards PCI Connector Serial PCI Express Mode Switch Position 2 towards PCIe Silkscreen on Board Slide Switch away from PCI Connector G X31LU1N XNIIX IZ P18 PCI Express 12 V to 5V Enable Parallel PCI Bus Mode Open Circuit Remove Shunts Serial PCI Express Mode Install Shunts to Connect P18 1 to P18 2 and P18 3 to P18 4 il zt UG201 c3 14 02270 on of SW8 and P18 z4 Figure 3 15 Locati Virtex 5 FPGA ML555 Development Kit www xilinx com 77 UG201 v1 4 March 10 2008 Chapter 3 Hardware Description XILINX Figure 3 16 shows the jumper settings on SW8 and P18 for Serial PCI Express and Parallel PCI X Bus power configurations Serial PCI Express Power Configuration Parallel PCI X Bus Power Configuration 2 1 2 1 Connect PCle Disconnect PCle 12V to 5V P18 12V to 5V P18 Converter to Converter from 5V Plane 5V Plane 4 3 4 3 Slide Switch Slide Switch Power FPGA Voc nt Power FPGA Vogiyt From Onboard 3 0V From 3 3V PCI Bus PCI Voltage Power Rail Regulator SODIMM SODIMM UG201_c3_15_092706 Figure 3 16 ML555 Power Configuration Before installing the ML555 board in a system unit the power system configuration header P18 must be checked to ensure that the proper 5V input voltage is selected for the onboard regulators on the ML555 board according to Table 3 30 Table 3 30 ML555 5V Regulator Input Source Selection ML555 Bus Mode Primary Voltage Re
76. does not include SFP modules to plug into the connectors The user must provide these UG201 v1 4 March 10 2008 www xilinx com 39 Chapter 3 Hardware Description XILINX Serial ATA Interface The ML555 board provides a single Serial ATA SATA disk drive interface connector J5 for attachment to an external SATA disk drive The board supports 1 5 Gbps and 3 Gbps SATA baud rates A second SATA interface can be supported using the SMA connectors on the board and an external SMA to SATA interface board available from Xilinx with part number HW AFX SMA SATA The SATA and SMA transceivers are connected to a common GTP primitive block in the FPGA One of the two provided clock synthesizer modules must be used to generate a 150 MHz reference clock for the SATA GTP transceiver The ML555 board does not provide DC power to the drive An external DC power supply must provide the drive power The SATA signal interface cable is not supplied with the development kit Xilinx Alliance Partners have IP cores that can be licensed for development and fielding a SATA interface solution The available Alliance Partners IP cores can be found at www xilinx com alliance XAPP870 Ref 11 provides a reference design demonstrating how to complete the SATA physical link initialization between the GTP transceiver in the Virtex 5 LXT FPGA and an external SATA device Table 3 8 lists the signal names and pin assignments for the SATA connector Th
77. e ML555 board does not provide DC power for the SATA drives Table 3 8 SATA Connector J5 Signal FPGA Pin 1 GND NCO 2 SATA TXPO B4 3 SATA TXNO B3 4 GND NC 5 SATA RXNO A2 6 SATA RXPO A3 7 GND NC Notes 1 NC no connect 2 The Host side transceiver ports are AC coupled with a 0 01 uF capacitor The SATA interface is connected to GTP DUAL tile X0Y5 40 www xilinx com Virtex 5 FPGA ML555 Development Kit UG201 v1 4 March 10 2008 X XILINX SMA Connectors SMA Connectors Ethernet PHY Virtex 5 FPGA ML555 Development Kit The ML555 board has a set of SMA connectors to facilitate routing one set of GTP transceiver signals off the card to an external device Another set of SMA connectors is also provided to input a clock to the GTP MGTREFCLK inputs There are a number of Xilinx evaluation boards that convert an SMA interface to SATA RJ45 or SFP for example GTP DUAL tile X0Y5 is connected to the SMA connectors Table 3 9 lists the signal names and pin assignments for the SMA connectors SMA connectors interface to GIP DUAL tile X0Y5 Table 3 9 SMA Connector SMA Reference Signal Name FPGA Pin FPGA I O Designator J6 SMA TXP E2 Out J7 SMA_TXN D2 Out J8 SMA_RXP D1 In Jo SMA RXN C1 In Ti2 SMA GTPCIK P4 P P4 In J13 SMA_GTPCLK_P3_N P3 In Notes 1 DC blocking a should be installed between the test equipment and the SMA
78. ence design CD e Time out evaluation licenses for the LogiCORE IP for PCI and PCI X designs e Drivers for Jungo Software Technologies WinDriver device driver development kit can be downloaded from www jungo com dnload html and evaluated for 60 days e Xilinx Platform Cable USB programming cable e JSE evaluation software For assistance with any of these items contact your local Xilinx distributor or visit the Xilinx online store at www xilinx com The heart of the kit is the ML555 board This manual provides comprehensive information on this board ML555 Board The ML555 board includes the following e XC5VLX50T FFG1136C 1 speed grade FPGA e 200 pin 1 8V SODIMM socket with 256 MB 32M x 64 bit DDR2 SDRAM SODIMM e Three on board clock sources two differential SMA clock inputs and two programmable clock synthesizers 30 MHz LVCMOS 125 and 200 MHz Epson 2 5V EG 2121CA LVDS and LVPECL respectively e One Universal Serial Bus USB 2 0 port USB interface cable not provided e Support for up to four FPGA design images in two Xilinx XCF32P FSG48C Platform Flash configuration PROM devices e Static or dynamic device reconfiguration support with the XC2C32 CoolRunner II CPLD Virtex 5 FPGA ML555 Development Kit www xilinx com 15 UG201 v1 4 March 10 2008 Chapter 1 Introduction XILINX e 64 bit 3 3V system board keyed connector for PCI or PCI X operation e Support for Endpoint designs in x1 x4 and x8
79. enuator PCI Express Op ration sesaria ure E EU PNR emt SP Lc ee 60 Clock Synthesizers eek co ere ek exe e pa e eed edo ede keds 61 Parallel Mode Operation 12 die ce EE mre res era E ded 62 Serial Mode Operation kyss abaa enau te en hh hn 68 Clock Capable I O Pins Associated with Clock Inputs 22222222 70 IDELAYCTRL Reference Clock Generation sees 72 User LEDS sua A eit iau arde ee DEA Mei deu ipia E oe eben Masi pida 73 Configuration INIT and DONE LEDs sss sess eese 73 User Pushbutton Switches u ans eoe e e EE RE yr Ran 74 Pushbutton Program Switch SW6 ouis 74 Pushbutton Reset Switch SW7 ssssssssssssssseeeee 74 Power CONTI qao eene have eure lip pp dac a idend Rp pd dor 74 Voltage Regulators uc ke oO dp ce EEG E Ig iare go ice ac doc 75 ML555 DC Power System sien eco Ee EORR rade nen ee idus 75 PCI and or PCI X Application Add in Card Power Input 22 79 Add in Card DC Power Input PCI Express Operation 2222ee00 80 ML555 Board DC Power Regulators 0 6 80 GTP Transceiver Power 2 ree bbb erie tees bee wayne ae e Uo tec 82 DDRZSODIMNMLPOWBE seien ead 82 Power Supply Monitoring lssssesssseee e 82 ML555 Board Physical Dimensions 222ceeeeeeeeeeeeeeeennnnnn 85 XC2C32 CoolRunner II CPLD U6 sseessss eere 85 XCF32PFS48C Platform Flash U1 and U15
80. er has a voltage controller oscillator VCO that operates in the 250 to 700 MHz range The VCO output can be divided by 1 2 4 or 8 to obtain various clock frequencies Input reference clock frequency for Clock Synthesizer 1 is 10 MHz The minimum clock adjustment granularity is 10 8 or 1 25 MHz steps Input reference clock frequency for Clock Synthesizer 2 is 25 MHz The minimum clock adjustment granularity is 25 8 or 3 125 MHz steps When SMA connectors J12 and J13 are used to provide a source clock to GTP DUAL tile X0Y3 MGTREFCLK in line DC blocking capacitors should be placed between the test equipment en and SMA clock inputs AC coupling is recommended for GTP clock inputs All GTP clock inputs with the exception of the SMA clock inputs are AC coupled on the ML555 board assembly The ML555 board layout provides two methods of interfacing the PCIE_REFCLK to the FPGA The default method is to AC couple the 100 MHz PCIE_REFCLK directly to the GTP DUAL tile X0Y2 MGTREFCLK input pins An alternative method is to remove two OC resistors and install an ICS874003 02 PCI Express Jitter attenuator module which provides a 100 125 or 250 MHz reference clock to the GTP transceiver The jitter attentuator has two LVDS outputs that connect to the GTP and FPGA global clock inputs One of the jitter attentuator LVDS outputs is connected to the MGTREFCLK inputs of GTP DUAL tile X0Y2 for PCI Express lanes 0 and 1 The PCIE REFCLK is also connected to the F
81. es reference designs for using the DSP48E e Virtex 5 FPGA Configuration Guide This all encompassing configuration guide includes chapters on configuration interfaces serial and SelectMAP bitstream encryption Boundary Scan and JTAG configuration reconfiguration techniques and readback through the SelectMAP and JTAG interfaces e Virtex 5 FPGA System Monitor User Guide The System Monitor functionality available in all the Virtex 5 devices is outlined in this guide e Virtex 5 FPGA Packaging Specifications This specification includes the tables for device package combinations and maximum I Os pin definitions pinout tables pinout diagrams mechanical drawings and thermal specifications e Virtex 5 PCB Designer s Guide This guide provides information on PCB design for Virtex 5 devices with a focus on strategies for making design decisions at the PCB and interface level The following documents provide supplemental material useful to this user guide DS090 CoolRunner II CPLD Family DS123 Platform Flash In System Programmable Configuration PROMs UG065 PHY Daughter Card User Guide XAPP938 Dynamic Bus Mode Reconfiguration of PCI X and PCI Designs XAPP1022 Using the Memory Endpoint Test Driver MET with the Programmed Input Output Example Design for PCI Express Endpoint Cores 6 XAPP1002 Using ChipScope Pro to Debug Endpoint Block Plus Wrapper Endpoint and Endpoint PIPE Designs for PCI Express 7 XAPP999 Reference Syste
82. et G3 FLASH REV SELO I REV SELO Revision Select 0 input connected to CPLD Pin 39 G4 FLASH_REV_SEL1 I REV_SEL1 Revision Select 1 input connected to CPLD Pin 40 H3 JTAG_TCK I TCK JTAG TCK E6 JTAG_TDO O TDO JTAG TDO connected to Header P5 E2 JTAG_TMS I TMS JTAG TMS Al GND I GND1 Ground A2 GND I GND2 Ground B6 GND I GND3 Ground F1 GND I GND4 Ground F5 GND I GND5 Ground F6 GND I GND6 Ground H1 GND I GND7 Ground B1 VCC1V8 I VCCINT1 1 8V Power El VCC1V8 I VCCINT2 1 8V Power G6 VCCIV8 I VCCINT3 1 8V Power H2 VCC1V8 I vec 1 8V Power D6 VCC2V5 I VCCO3 2 5V I O Power B2 VCC2V5 I VCCO1 2 5V I O Power C6 VCC2V5 I VCCO2 2 5V I O Power G5 VCC2V5 I VCCO4 2 5V I O Power A4 Unused I DNC1 Do Not Connect C3 Unused I DNC2 Do Not Connect C4 Unused I DNC3 Do Not Connect 96 www xilinx com Virtex 5 FPGA ML555 Development Kit UG201 v1 4 March 10 2008 XILINX Table 4 5 Pin Listing for Platform Flash Continued SelectMAP Interface A Net Name Direction Pin Type Description D2 Unused O CEO Do Not Connect D3 Unused I DNC4 Do Not Connect D4 Unused I DNC5 Do Not Connect E3 Unused I DNC6 Do Not Connect E4 Unused I DNC7 Do Not Connect F2 Unused I DNC8 Do Not Connect F3 Unused I DNC9 Do Not Connect F4 Unused I DNC10 Do Not Connect G2 Unused I DNC1 Do Not Connect Notes 1 The ML555 board uses 2 5V I O drivers for the JTAG chain The Platform Flash Vccj connection should
83. following documents are also available for download at http www xilinx com virtex5 e Virtex 5 Family Overview The features and product selection of the Virtex 5 family are outlined in this overview e Virtex 5 Data Sheet DC and Switching Characteristics This data sheet contains the DC and Switching Characteristic specifications for the Virtex 5 family e Virtex 5 FPGA User Guide This user guide includes chapters on Clocking Resources Clock Management Technology CMT Phase Locked Loops PLLs Block RAM and FIFO memory Configurable Logic Blocks CLBs SelectIO Resources I O Logic Resources Advanced I O Logic Resources Virtex 5 FPGA ML555 Development Kit www xilinx com 7 UG201 v1 4 March 10 2008 Preface About This Guide XILINX e Virtex 5 FPGA RocketIO GTP Transceiver User Guide This user guide describes the RocketIO GTP transceivers available in the Virtex 5 LXT and SXT platform devices e Virtex 5 FPGA Embedded Tri Mode Ethernet MAC User Guide This user guide describes the dedicated Tri Mode Ethernet Media Access Controller available in the Virtex 5 LXT and SXT platform devices e Virtex 5 Integrated Endpoint Block User Guide for PCI Express Designs This user guide describes the integrated Endpoint blocks in the Virtex 5 LXT and SXT platform devices for PCI Express designs e Virtex 5 FPGA XtremeDSP Design Considerations This guide describes the XtremeDSP slice and includ
84. for FPGA output H15 Added additional text to footnote 6 in Table 3 20 page 58 Updated Parallel Mode Operation page 62 to indicate pressing and releasing of SW9 and SW11 to parallel load clock synthesizers after power on to guarantee clock frequency Updated Figure 3 14 page 76 and Table 3 34 page 81 Added footnote 1 to Table 4 5 page 95 Updated Generic Dynamic Reconfiguration page 98 and Platform Flash Image Generation and Programming page 101 to include process steps and screen shots from ISE 9 1i Inserted two new figures Figure 4 11 page 105 and Figure 4 12 page 105 UG201 v1 4 March 10 2008 www xilinx com Virtex 5 FPGA ML555 Development Kit Date 03 10 08 Version 1 4 Revision Added additional reference documents and application notes in Additional Documentation page 7 Added link to ML555 website in About the Virtex 5 FPGA ML555 Development Kit page 13 Updated Serial Bus Development page 15 including removal of Virtex 5 LogiCORE Endpoint Block Wrapper Included Platform USB Programming Cable and ISE Evaluation Software in Kit Contents page 15 Specified 30 MHz LVCMOS oscillator as one of three on board clock sources in ML555 Board page 15 Updated Figure 3 1 page 21 to reflect as built 30 MHz LVCMOS oscillator Added reference and link to Xilinx application notes XAPP1022 and XAPP1002 in Edge Connector for PCI Express Operation page 23 Added footno
85. full system hardware evaluation versions of the Virtex 5 FPGA LogiCORE products for PCI and PCI X designs The following link provides additional information specific to the ML555 board and LogiCORE products www xilinx com ipcenter m 555 ml555 eval instr htm www xilinx com Virtex 5 FPGA ML555 Development Kit UG201 v1 4 March 10 2008 XILINX ML555 Board Serial Bus Development The ML555 board is supported by a LogiCORE endpoint wrapper to configure the Integrated Endpoint Block for PCI Express operation in Virtex 5 LXT and SXT FPGAs e Virtex 5 FPGA LogiCORE Endpoint Block Plus Wrapper for PCI Express designs This is the recommended wrapper for PCI Express designs It provides many ease of use features and optimal configuration for Endpoint applications while simplifying the design process and reducing the time to market The endpoint solution is delivered through the Xilinx CORE Generator tool Full access to the core including bitstream generation capability can be obtained through registration at no extra charge Additional technical information on Xilinx PCI Express solutions is available at www xilinx com pciexpress Refer to UG197 Virtex 5 Integrated Endpoint Block User Guide for PCI Express Designs for more information on the integrated Endpoint solution Kit Contents The ML555 board kit includes the following e Virtex 5 FPGA ML555 board XC5VLX50T FFG1136C 1 speed grade FPGA e Documentation and refer
86. gns Continued P13 A Side Signal P13 B Side Signal A30 PERN3 B30 RESERVED A31 GND B31 PCIE PRSNT2 B D A32 RESERVED B32 GND A33 RESERVED B33 PETP4 A34 GND B34 PETN4 A35 PERP4 B35 GND A36 PERN4 B36 GND A37 GND B37 PETP5 A38 GND B38 PETN5 A39 PERP5 B39 GND A40 PERN5 B40 GND A41 GND B41 PETP6 A42 GND B42 PETN6 A43 PERP6 B43 GND A44 PERN6 B44 GND A45 GND B45 PETP7 A46 GND B46 PETN7 A47 PERP7 B47 GND A48 PERN7 B48 PCIE_PRSNT2_BM A49 GND B49 GND Notes 1 PCIE PRSNTI B can be connected to one of three PCIE PRSNT2 B signals by connecting a shunt on connector P45 See Table 3 2 for application information 2 No connect on the ML555 board 3 The ML555 board layout provides two methods of interfacing the PCIE REFCLK to the FPGA The default method is to AC couple the 100 MHz PCIE REFCLK directly to the GTP DUAL tile X0Y2 MGTREFCLK input pins An alternative method is to remove two OQ resistors and install an 1CS874003 02 PCI Express Jitter attenuator module which provides a 100 125 or 250 MHz reference clock to the GTP transceiver The jitter attentuator has two LVDS outputs that connect to the GTP and FPGA global clock inputs One of the jitter attentuator LVDS outputs is connected to the MGTREFCLK inputs of GTP DUAL tile XOY2 for PCI Express lanes 0 and 1 The PCIE REFCLK is also connected to the FPGA global clock network on pins J16 and J17 Internal FPGA c
87. gulator DC Input Voltage SW8 5V Source Selection Header for Application Source Onboard DC Regulators PCIor PCI X 5V PCI Connector System Unit Power Open circuit e Remove shunts on connector P18 pins 1 2 e Remove shunts on connector P18 pins 3 4 PCI Express 12V PCI Express Connector System Unit Power Short circuit Onboard 12V to 5V DC converter powers most of Connect shunts on connector P18 pins 1 2 the voltage regulators on the ML555 board e Connect shunts on connector P18 pins 3 4 Shunts are provided on the board 78 www xilinx com Virtex 5 FPGA ML555 Development Kit UG201 v1 4 March 10 2008 XILINX Voltage Regulators The SW8 switch the source of the 3V power must be configured according to Table 3 31 to generate GTP transceiver analog and FPGA Vecmr power Table 3 31 Vec nt Voltage Source Selection for PCI or PCI Express Bus Applications 3 3V Power to GTP Analog Supplies and FPGA Vccint 1 0V Regulator Power Source Voltage Source for FPGA Vecint P11 3V Selection Header Connections PCI or PCI X ML555 on board 3 0V regulator e Slide SW8 to the OFF position power connecting pins 2 and 3 Move switch towards silkscreen on board labeled PCI See Figure 3 16 for graphic illustration PCI Express PCI Express system board 3 3V e Slide SW8 to the ON position power connecting pins 1 and 2 Move switch towards silkscreen on board labeled PCIe See Figure 3 16 for gr
88. he CD ROM for additional information 2 NC no connect These clocks are connected to FPGA clock capable I O pins 4 These clocks are connected to FPGA global clock pins e Virtex 5 FPGA ML555 Development Kit www xilinx com 43 UG201 v1 4 March 10 2008 Chapter 3 Hardware Description XILINX LVDS Interface 44 The ML555 board supports low voltage differential signaling LVDS applications with 24 transmit channels and 24 receive channels of LVDS signals Two Samtec QSE DP connectors are provided one for the transmit interface and a second for the receive interface Single data rate SDR and double data rate DDR LVDS applications can be designed targeting the ML555 board An SDR SFI 4 interface or XSBI interface consists of 16 LVDS data channels and a forwarded clock A DDR SPI4 2 like interface consists of 16 LVDS data channels and one forwarded clock Xilinx has several SDR and DDR LVDS reference designs that can be ported to run on the ML555 board The LVDS transmit and receive connectors can be connected to each other for loopback testing as shown in Figure 3 6 page 49 The loopback interface cables are not provided with the kit but can be ordered separately from Xilinx as part number HW LVDS CBL 80 The LVDS transmit and receive connectors can also be connected to either an ML450 or ML550 networking interfaces board from Xilinx Additional information on Xilinx board products is located at www xilinx com products de
89. he ML555 board schematics on the CD ROM for additional information Figure 3 7 is a high level block diagram of the RS 232 to USB 2 0 interface U5 U4 U10 28 USB DTROB 7 14 USB DTRB L15 24 USB RTS O B 9 9 USB RST I B 1 11 USB SUSPEND O B 6 Figure 3 7 RS 232 Interface Block Diagram USB D 5 18 USB DSRH B K16 USB VBUS 8 13 USB TX L20 17 USB RX K21 Virtex 5 12 USB RTS B L21 FPGA 16 USB_CTS_B J22 20 USB_RST_B J15 V USB_D 4 15 USB SUSPEND B L16 CP2102 MAX3008 UG201_c3_07_092706 The USB 2 0 cable is not included in the kit A USB Type A to USB Type B interface cable is required for ML555 to PC serial communications over the USB interface The Platform USB programming cable included with the Virtex 5 LXT ML555 FPGA Development Kit for PCI Express PCI X and PCI interfaces contains a USB Type A to USB Type B interface cable If the Platform USB programming cable is not being used to program devices on the ML555 board the cable could be used for USB communications between the ML555 board and a host computer USB to UART Bridge The ML555 board contains a CP2102 USB to UART bridge circuit from Silicon Laboratories The USB 2 0 interface is provided external to the board while the FPGA utilizes a UART interface The USB interface cable is not provided with the ML555 development kit USB interface cables are available at many office s
90. he pinouts for the FPGA CPLD and Platform Flash respectively The two Platform Flash devices are connected in parallel with the exception of the chip enable inputs The CPLD has one chip enable output for each Platform Flash device www xilinx com 91 UG201 v1 4 March 10 2008 Chapter 4 Configuration XILINX U1 U10 Platform Flash FPGA XCF32PF po D 7 0 XC5VLX50T CE1 U15 FORCE 1 CE U1 WIDE PCIW_EN BUSY ATR DONE DOUT_BUSY RDWR_B CS_B cr PROG B OE RESET INIT B To P2 CLKOUT REV SELO From P2 REV SEL1 CPLD SPARE 1 8 CCLK MOM1M2 HSWAPEN o o m o gigle 30 MHZ From To P2 2 CPLD CLK 32 S oz SW5 v O lt E E lz no wn EE LL Ww a v se UG201 c4 05 022608 Notes 1 FORCE WIDE PCIW EN and RTR are FPGA general purpose I Os Figure 4 5 Schematic of Flash CPLD FPGA SelectMAP Interface Table 4 3 FPGA Configuration Pin Listing en Net Name Direction Pin Type Description N15 FPGA_CCLK I O CCLK Configuration Clock Input or Output N23 FPGA RDWR B I RDWR B Active Low Read Write N22 FPGA CS B I CS B Active Low Chip Select AD21 MODEO I MO Mode Select 0 AC22 MODEI I M1 Mode Select 1 AD22 MODE2 I M2 Mode Select 2 M22 PROG_B I PROGRAM_B Active Low asynchronous full chip reset N14 INIT B I INIT B Active Low Delay Configuration
91. hematics on the CD ROM for additional information www xilinx com 73 UG201 v1 4 March 10 2008 Chapter 3 Hardware Description XILINX User Pushbutton Switches The ML555 board provides three user pushbutton switches The switch outputs are pulled up to 2 5V using 4 7 KQ resistors on the board The pushbuttons generate a switch closure to GND when pressed Switch contact debounce logic must be implemented inside the FPGA Table 3 29 lists the FPGA pin assignments Table 3 29 User Pushbutton Switch Assignments Pushbutton Switch Signal Description teeta di peu USER SWO0 USER1 SW1 AF21 USER SW1 USER2 SW2 AF20 USER SW2 USER3 SW3 AF14 Notes 1 These signals are connected to FPGA bank 2 The FPGA reference voltage Veco for this bank is 2 5V See the ML555 board schematics on the CD ROM for additional information Pushbutton Program Switch SW6 The ML555 board provides a pushbutton program switch for initiating reconfiguration of the Virtex 5 FPGA A CPLD image is provided with the ML555 board to enable pressing and releasing the program pushbutton switch SW6 to initiate a full FPGA device configuration cycle while the board is powered on The CPLD design files and bit image are on the reference CD included in the kit Pressing this switch causes the FPGA to clear its internal configuration memory and then load the currently selected image via the P3 image select jumper block from the Platform Flash U
92. ic 1 level to select the Clock Synthesizer 2 as the clock source or a logic 0 level to select the fixed 125 MHz LVDS clock source as input to the global clock pins Depending on which GTP elements are used in the design the second clock synthesizer might be available for IDELAYCTRL reference clock The ML555 board provides three user LEDs that can be turned ON by driving the LED signals to Ground Table 3 27 lists the FPGA pin assignments Table 3 27 User LED Pin Assignments LED Signal Designation js Be USER_LEDO USER1 D1 H8 USER_LED1 USER2 D2 G8 USER_LED2 USER3 D3 G10 Notes 1 These signals are connected to FPGA bank 20 The FPGA reference voltage Vcco for this bank is 2 5V See the ML555 board schematic on the CD ROM for additional information Configuration INIT and DONE LEDs Virtex 5 FPGA ML555 Development Kit The ML555 board provides INIT and DONE indicator LEDs that are turned ON by the FPGA during the configuration process The FPGA INIT pin N14 drives the INIT LED D5 buffer transistor Q2 The FPGA DONE pin M15 drives the DONE LED D6 buffer transistor Q1 Table 3 28 lists the FPGA pin assignments Table 3 28 Configuration INIT and DONE LED Pin Assignments LED Designation nr FPGA_INIT D5 INIT N14 FPGA DONE D6 DONE M15 Notes 1 These signals are connected to FPGA configuration bank 0 The FPGA reference voltage for this bank is 2 5V See the ML555 board sc
93. iguration interface is provided on the reference CD ROM included with the ML555 kit The output frequency of the synthesizer is M times the input reference clock frequency provided that the internal VCO is locked An eight position DIP switch selects the multiplier value M M can be any decimal value from 0 to 511 There are values of M where the VCO will not obtain frequency lock The relationship between the input clock FxrAL and the VCO frequency is given by the equation Fyco Fxtan X M The VCO can be divided by an integer value 1 2 4 or 8 using the DIP switches as shown in Table 3 21 The frequency output of the clock synthesizer is given by the equation Four Fyco N Fxqar X M N provided the VCO is locked Virtex 5 FPGA ML555 Development Kit www xilinx com 61 UG201 v1 4 March 10 2008 62 Chapter 3 Hardware Description XILINX Table 3 21 1CS8442 Divisor Switch Settings SW12 9 or SW10 9 or Output Frequency MHz SW12 1 0 2 SW12 11 3 Output Divisor N1 NO Value Minimum Maximum 0 0 1 250 700 0 1 2 125 350 1 0 4 62 5 175 1 1 8 31 25 87 5 Notes 1 A logic 0 is obtained by moving the switch to the OPEN position and a logic 1 is obtained by moving the switch to the CLOSED position 2 SW12 9 is for the N1 input of Clock Synthesizer 1 and SW12 10 is for the N1 input of Clock Synthesizer 2 3 SW10 9 is for the NO input of Clo
94. indicates 0 to 33 MHz operation e MO66EN open indicates 33 MHz to 66 MHz operation M66EN is pulled up on the system board PME Power Management Event Connector P7 P1 A19 is wired to a two pin header pin P7 1 PME is pulled up on the system board P7 2 is wired to U10 pin L30 allowing the FPGA to drive or sense the PME signal when a jumper shunt is placed across pins 1 and 2 of P7 The LogiCORE User Guide for PCI PCI X can be consulted for more information on proper use of PME By default the PME signal is not connected from the system board to the FPGA meaning the system boards sees only the pull up resistor and the FPGA input is not connected to the system board signal PCIXCAP PCI X Capability Connector P8 P1 B38 is wired to 3 pin header P8 center pin and PCIXCAP is connected to FPGA pin E31 e 8 1 is wired to GND through a 10 KQ pulldown resistor e P8 2 is wired to P1 B38 and a 0 01uF capacitor to GND e P8 3 is wired to GND e A jumper shunt across P8 pins 1 and 2 indicates that the card is PCI X 66 capable e Nojumper shunt across P8 indicates that the card is PCI X 133 capable e A jumper shunt across P8 pins 2 and 3 indicates that the card is not PCI X capable i e itis PCI capable and not PCI X capable Reference Designs for PCI and PCI X Operation The included FPGA bitstreams are example implementations of the PCI32 v4 1 and PCI X v6 1 LogiCORE solutions In these example implementations the c
95. ins two Platform Flash devices 6 Under Assign New Configuration File browse to the directory where the MCS and CFI file are stored on the computer Click the MCS file to select it and then click Open Right click the xcf32p icon and select Program Under the Programming Properties menu shown in Figure 4 13 select Parallel Mode 9 Under the Advanced PROM Programming Options menu shown in Figure 4 14 select PROM is Slave clocked externally 10 In the Revision Properties menu shown in Figure 4 15 select the following Inthe Design Revision column check the Rev boxes for the revisions to be programmed For this example both Rev0 and Rev1 are selected One XCF32P device stores a maximum of two XC5VLX50T FPGA design images Inthe Erase column check the Erase boxes for revisions that are going to be programmed In general you should make sure that the device is erased before programming For this example the previous Rev0 and Rev1 PROM design images are to be erased before new design images are programmed Click OK to begin programming the selected Platform Flash and PROM file using Boundary Scan After a pause Program Succeeded is displayed PROM programming is complete 104 www xilinx com Virtex 5 FPGA ML555 Development Kit UG201 v1 4 March 10 2008 XILINX Platform Flash Image Generation and Programming PA BO da m File Edit View Operations Options Output Debug Window Help SER CECENIEI BRIN H BB
96. ional information These clocks are connected to FPGA clock capable I O pins NC no connect www xilinx com Virtex 5 FPGA ML555 Development Kit UG201 v1 4 March 10 2008 XILINX Ethernet PHY Daughtercard Support Table 3 11 Ethernet PHY Daughtercard J16 Connection J16 EVEN Signal J16 ODD Signal FPGA Pin FPGA In Out 2 GND 1 Nocnet NOO 4 GND 3 P1_RXC_RXCLK J10 In 6 GND 5 P1 RD RXD1 Ell In 8 GND y P1 RXCTL RXDV M10 In 10 GND 9 P1 RCLK1 K18 In 12 GND 11 P1_CRS G11 In 14 GND 13 P1_RXER G12 In 16 GND 15 P1_RXD7 E6 In 18 GND 17 P1 RD RXDO T9 In 20 GND 19 No connect NC 22 GND 21 P1 RD RXD2 G6 In 24 GND 23 P1 RD RXD3 T10 In 26 GND 25 P1_RXD4 F5 In 28 GND 27 P1_RXD5 R9 In 30 GND 29 P1_RXD6 H5 In 32 GND 31 PO_CRS R11 In 34 GND 33 No connect NC 36 GND 35 PO RD RXDO M6 In 38 GND 37 PO_RD_RXD1 N8 In 40 GND 39 No connect NC 42 GND 41 P0_RD_RXD2 M7 In 44 GND 43 No connect NC 46 GND 45 PO_RXCTL_RXDV J6 In 48 GND 47 PO_RXD4 P5 In 50 GND 49 PO_RXD5 L5 In 52 GND 51 PO RXD6 P6 In 54 GND 53 PO RXD7 K6 In 56 GND 55 PO_RCLK1 H14 In 58 GND 57 PO_RD_RXD3 J5 In 60 GND 59 PO_RXER R8 In 62 GND 61 PO_RXC_RXCLK H7 In 64 GND 63 No connect NC Notes 1 These signals are connected to FPGA banks 12 and 20 The bank reference voltage Veco is 2 5V See the ML555 board schematics on t
97. itter attentuator circuit Source code for the CPLD design provided with the ML555 board is included on the CD ROM Clock Jitter Attenuator U10 FPGA PCIE250M_P Y4 a MGT_REFCLKP PCIE250M_N _Y3 MGT_REFCLKN gt GTE ZONE P13 A13 X 874003 02 P13 A14 X PCIE_REFCLK PCIE GCLK P J16 PCIE GCLK N Ji GCLKP CPLD SPARES8 CPLD SPARE2 CPLD_SPARE1 UG201_c3_09_121006 Figure 3 10 PCI Express Clocking and Control Spread spectrum clocking is supported by routing the system board clock into the transceiver and then generating a local clock for the FPGA design The external clock from one GTP DUAL tile can be used to drive the CLKIN ports of neighboring tiles A GTP DUAL tile shares its clock with its neighbors using dedicated internal clock routing resources Refer to the Virtex 5 FPGA RocketIO GTP Transceiver User Guide for additional information on clocking resources www xilinx com Virtex 5 FPGA ML555 Development Kit UG201 v1 4 March 10 2008 XILINX Clock Generation Clock Synthesizers The ML555 board contains two clock synthesizer circuits that support a wide range of frequency synthesis capabilities for end user applications One of the clock synthesizers should be used to generate the clock for the DDR2 SODIMM memory The second clock synthesizer can be used to generate the reference clock for the GTP transceivers Two Integrated Circuit Systems ICS ICS8442 Crystal Oscillator to Differe
98. ivisor 1 Divisor 2 N 1 0 10b Divisor 8 N 1 0 00b N 1 0 01b N 1 0 11b 0 0x00 0x18 Will not LOCK N A N A N A N A 0 19 250 250 125 62 5 31 25 0 1A 260 260 130 65 32 5 0 1B 270 270 135 67 5 33 75 0 1C 280 280 140 70 35 0 1D 290 290 145 72 5 36 25 0 1E 300 300 150 75 37 5 0 1F 310 310 155 77 5 38 75 0 20 320 320 160 80 40 0 21 330 330 165 82 5 41 25 0 22 340 340 170 85 42 5 0 23 350 350 175 87 5 43 75 0 24 360 360 180 90 45 0 25 370 370 185 92 5 46 25 0 26 380 380 190 95 47 5 0 27 390 390 195 97 5 48 75 0 28 400 400 200 100 50 0 29 410 410 205 102 5 51 25 0 2A 420 420 210 105 52 5 0 2B 430 430 215 107 5 53 75 0 2C 440 440 220 110 55 0 2D 450 450 225 112 5 56 25 0 2E 460 460 230 115 57 5 0 2F 470 470 235 117 5 58 75 0 30 480 480 240 120 60 0 31 490 490 245 122 5 61 25 0 32 500 500 250 125 62 5 0 33 510 510 255 127 5 63 75 0 34 520 520 260 130 65 64 www xilinx com Virtex 5 FPGA ML555 Development Kit UG201 v1 4 March 10 2008 X XILINX Clock Generation Table 3 22 Clock Synthesizer 1 Frequency Output for Multiplier Divider Values with a 10 MHz Input Clock Continued Multiplier Input Selection Output Output Output Output hex VCO Lock Frequency Frequency Frequency MHz Frequency FrequencyRange MHz with MHz with dioe d MHz with zx ss with Divisor 4 M8 M 7 0 MHz Divisor 1 Divisor 2 N 1 0 10b Divisor
99. le 3 20 GTP Reference Clock Inputs id Eee FPGA Pins Signal Name Clock Source 3 4 5 Application Usage Designator X0YO 9 AL5 AL4 MGT_XOYO_REFCLK Clock Synthesizer 2 Lanes 6 and 7 X0Y1 9 AF4 AF3 MGT X0OY1 REFCLK Clock Synthesizer 1 Lanes 2 and 3 X0Y2 9 Y4 Y3 PCIE REFCLKO Spread spectrum clock input from Lanes 0 and 1 PCI Express system unit connector P13 Pins A13 P and A14 N X0Y3 6 P4 P3 SMA_GTPCLK SMA connectors P12 P and P13 N Lanes 4 and 5 X0Y4 H4 H3 SFP_MGT_REFCLK 125 MHz Oscillator SFP1 and SFP2 interfaces X0Y5 E4 D4 SATA_MGT_REFCLK Selectable 125 MHz Oscillator or SATA and SMA interfaces Clock Synthesizer 2 Notes 1 2 GTP REFCLK input pins are listed as differential pairs MGTREFCLKP and MGTREFCLKN respectively Signal names for differential clocking have P N designators at the end to indicate positive or negative input output of the differential clock receiver See the ML555 board schematics and the ML555 FPGA design constraint file on the CD ROM for additional information The transceivers can still be utilized using internal clock routing resources either global or GTP clock buffering See the Virtex 5 FPGA RocketIO GTP Transceiver User Guide for additional information on GTP clocking Clock Synthesizer 1 is typically utilized to generate the clock for the DDR2 memory The GTP transceivers can also be clocked using the differential SMA clock inputs
100. lock buffers distribute this clock to other GTP DUAL tiles for PCI Express operation The architecture of the FPGA permits an external MGTREFCLK to be driven a maximum of three GTP DUAL tiles up or down See Serial Bus Clockin ur Optional ICS874003 02 Clock Jitter Attenuator PCI Express Operation page 60 for additiona information 4 The PETPX and PETNX pins connect to the PCI Express transmitter differential pair on the system board and the PCI Express receiver on the add in card 5 The PERPX and PERNX pins connect to the PCT PIS receiver differential pair on the system board and the PCI Express transmitter on the add in card 6 PCIE PERST connects to FPGA pin AE14 The PCI Express Card Electromechanical Specification requires add in cards to implement variable length edge finger pads and tie PRSNT1_B and PRSNT2 B signals together on the Virtex 5 FPGA ML555 Development Kit www xilinx com 25 UG201 v1 4 March 10 2008 Chapter 3 Hardware Description XILINX add in card More than one PRSNT2_B pin is defined in the x4 x8 and x16 PCI Express connectors these are necessary to support up plugging of the add in card Up plugging is defined as plugging a smaller link card into a larger link connector The ML555 board can be plugged into x8 or x16 lane link connectors Prior to installation in the PCI Express system unit connector P45 must be configured to indicate the number of PCI Express lanes used in the design as shown
101. m PLBv46 PCI Using the ML555 Embedded Development Platform 8 XAPP858 High Performance DDR2 SDRAM Interface in Virtex 5 Devices 9 XAPP865 Hardware Accelerator for RAID6 Parity Generation Data Recovery Controller with ECC and MIG DDR2 Controller 10 UG086 Xilinx Memory Interface Generator MIG User Guide 11 XAPP870 Serial ATA Physical Link Initialization with the GTP Transceiver of Virtex 5 LXT FPGAs a PF ON a 8 www xilinx com Virtex 5 FPGA ML555 Development Kit UG201 v1 4 March 10 2008 XILINX Additional Support Resources 12 XAPP693 A CPLD Based Configuration and Revision Manager for Xilinx Platform Flash PROMs and FPGAs The Endpoint Block Plus for PCI Express solution from Xilinx is a reliable high bandwidth scalable serial interconnect building block for use with the Virtex 5 LXT and SXT platform FPGAs The core instantiates the Virtex 5 FPGA Integrated Block for PCI Express designs found in the Virtex 5 LXT and SXT devices The Endpoint Block Plus core is a Xilinx CORE Generator IP core included in the latest IP Update on the Xilinx IP Center Included with the Xilinx IP are a data sheet a getting started guide and a user guide These documents are generated by the CORE Generator tool when starting a design project The documents can be downloaded from the Xilinx website at http www xilinx com support documentation ip_documentation pcie_blk_plus_ds551 pdf http www xilinx com support documentati
102. match JTAG I O voltages of devices in the chain Virtex 5 FPGA ML555 Development Kit CPLD Programming Examples Static Configuration Figure 4 6 shows one possibility of connecting the FPGA to the Flash This example allows the FPGA to be statically selected and programmed with up to four bitstreams located in the Flash The selection of the bitstream is based on the configuration of the Flash Image Select header P3 Table 4 6 shows the jumper settings for header P3 UG201 v1 4 March 10 2008 www xilinx com 97 Chapter 4 Configuration From P2 Notes CLKOUT U1 Platform Flash D 0 7 XCF32PF CE1 U15 CE U1 XILINX U10 FPGA XC5VLX50T FORCE WIDE PCIW_EN RTR D 7 0 BUSY DONE DOUT BUSY RDWR B CS B CF OE RESET PROG_B INIT_B REV_SELO REV_SEL1 Prog_SW_b o geO Select w Flash Ima gel Select w MAN AUTO B Flash Ima O10 1 FORCE WIDE PCIW EN and RTR are FPGA general purpose I Os 98 CPLD SPARE 1 10 CCLK MOM1M2 30 MHZ From To P2 CPLD CLK SW5 DIP SW UG201_c4_06_022608 Figure 4 6 CPLD Configuration for Static Configuration Table 4 6 Bitstream Selection Setting for Header P3 Bitstream Revision Jumper Settings for P3 0 U1 1 2 3 4 and 5 6 1 U1 3 4 and 5 6 0 U15 1 2 and 5 6 1
103. n of the ICS8442 this signal should always be deasserted inactive STROBE_2 ICS8442 serial load input used to load serialized multiplier and AL34 Output divisor constants into the ICS8442 Asserted to perform serial to parallel loading for user defined clock synthesis This signal should be deasserted during the serial data clocking asserted and then deasserted for one clock cycle to complete the serial to parallel loading of the data into the device SDATA_2 This signal contains the ICS8442 serial data input The serial AK32 Output data is provided in the sequence T1 TO NULL N1 NO M8 M7 M6 M5 M4 M3 M2 M1 and finally MO The ICS8442 data sheet provides a serial loading timing diagram and definitions for serial data bits SCLOCK_2 The ICS8442 serial clock input should only be active during AJ32 Output serial loading of the synthesizer The clock should be deasserted at all other times Data is clocked into the ICS8442 on the rising edge of the SCLOCK The ICS8442 data sheet provides a serial loading timing diagram and definitions for serial data bits LVDSCLKMOD2 PO The Clock Synthesizer 2 clock outputs go through clock J20 E4 Input Q multiplexer U3 which connects to the FPGA global clock and 51 B In LVDSCLKMOD2 N the GTP REFCLK inputs See Figure 3 8 for a schematic P put MGT X0YO RCLKP representation of the clock network on the ML555 board AL5 Input MGT X0YO RCLKN ALA Input Notes 1 These FPGA output signals
104. nd LVDS interfaces Characterization boards are available for GTP transceiver characterization ML555 Board Physical Dimensions The physical height of the ML555 board prevents the system unit covers from being used The ML555 board should only be used in a development environment The ML555 board is 4 7 inches high by 10 5 inches long XC2C32 CoolRunner Il CPLD U6 This CPLD supports static or dynamic reconfiguration of the FPGA design image A default design image for the CPLD is provided with the ML555 board to support static reconfiguration To select one of four designs the user configures the P3 configuration image select header and then either powers up the board or depresses and releases the PROG switch while the board is in a system unit The design image might require the board to be plugged into either a parallel PCI bus system board slot or a serial PCI Express system board slot Figure 4 5 page 92 and Table 4 4 page 94 summarize the CPLD connections to e Uland U15 XCF32PFSG48C Platform Flash configuration devices e U10 XC5VLX50T FPGA Bank 20 e U10 XC5VLX50T FPGA Bank 0 Configuration Interface e P3 Configuration Image select header e SW6 PROG SW7 General purpose pushbutton switches All XC2C32 I O are 2 5V and the XC2C32 Vcc r is 1 8V Chapter 4 Configuration includes more details concerning the ML555 board configuration Virtex 5 FPGA ML555 Development Kit www xilinx com 85 UG201 v1 4 March 10 2008
105. nd divisor DIP switch settings into Synthesizer 2 U7 Clock synthesizer outputs are not guaranteed to be in a known state after a power on cycle To establish a known clock frequency output using the parallel mode the switches must be configured to a valid operating range and then the SW9 and SW11 pushbutton switches must be pressed and released The clock synthesizer can also be configured using FPGA outputs The Serial Mode Operation section provides additional information Table 3 22 and Table 3 23 show all possible values that can be generated by the clock synthesizer circuit Table 3 22 shows the clock synthesis ranges with a 10 MHz reference clock input for Clock Synthesizer 1 There are ranges below and above the VCO operating range which must never be selected by the user where the VCO does not lock and an Virtex 5 FPGA ML555 Development Kit www xilinx com 63 UG201 v1 4 March 10 2008 Chapter 3 Hardware Description XILINX output clock is not deterministic Only one output frequency can be generated based upon the divisor selection Table 3 22 Clock Synthesizer 1 Frequency Output for Multiplier Divider Values with a 10 MHz Input Clock Multiplier Input Selection Output Output Output Output hex VCO Lock Frequency Frequency Frequency MHz Frequency Frequency Range MHz with MHz with with Divisor 4 MHz with Ms M 7 0 MHz D
106. ng Continued SelectMAP Interface Pin ni au Number Net Name Direction Pin Type Description 32 RTR I IO GOE2 Input connected from Pin F16 of FPGA 33 PCIW EN I IO GOE3 Input connected from Pin F11 of FPGA 34 FPGA RDWR B O IO GOE4 Output connected to RDWR B pin of FPGA 35 VCC2V5 I VAUX 2 5V auxiliary power 36 CPLD SPARE3 I O IO18 Spare I O connected to FPGA pin H9 37 PCIE RST I IO19 Active Low RESET input for PCI Express from P13 A11 38 FLASH CE1 B O 1020 Output connected to the CE pin of Platform Flash U15 39 FLASH_REV_SELO O 1021 Output connected to the REV_SELO pin of Platform Flash devices 40 FLASH_REV_SEL1 O 1022 Output connected to the REV_SEL1 pin of Platform Flash devices 41 BUSY_TO_FLASH_B O 1023 Output connected to the BUSY pin of Platform Flash devices 42 FLASH_CE_B O 1024 Output connected to the CE pin of Platform Flash U1 43 FLASH_CF_B O IO GC2 Output connected to the CF pin of Platform Flash devices 44 FLASH_OE_RESET_B O IO GC3 Output connected to the OE RESET pin of Platform Flash devices Notes 1 The Net Names and Directions for pins 29 through 33 were chosen to support a specific PCI PCI X design as described in CPLD Programming Examples The user can use these pins as spare bidirectional pins 2 All CPLD I O are 2 5V LVCMOS Table 4 5 Pin Listing for Platform Flash Tum Net Name Direction Pin
107. ntial LVDS Frequency Synthesizer devices are on the board each with a different crystal oscillator reference clock The ICS8442 device has the following features e Dual differential LVDS outputs e Output frequency range 31 25 MHz to 700 MHz e Crystal input frequency range 10 MHz to 25 MHz e VCO operating range 250 MHz to 700 MHz e Parallel or serial interface for programming multiplier and output dividers e RMS period jitter 2 7 ps typical e Cycle to cycle jitter 18 ps typical The complete data sheet for the ICS8442 device is available online at http www idt com products getDoc cfm docID 6914275 The synthesizer multiplies the reference clock input by a selectable multiplier The VCO operates locks in a range from 250 to 700 MHz The VCO output is routed through a programmable divider to generate the desired output frequency The supported VCO frequency divisors are 1 2 4 or 8 The resultant clock from the divisor block is then routed to differential output drivers The clock synthesizer can be programmed in either parallel or serial mode Parallel mode requires the user to set two DIP switches on the ML555 board and then press and release a pushbutton switch to load the desired configuration into the ICS8442 Serial configuration is accomplished using the FPGA to transmit serial data clock and controls to the synthesizer A reference design to program the ICS clock synthesizers using the FPGA to 1CS8442 serial conf
108. nx com 17 UG201 v1 4 March 10 2008 Chapter 1 Introduction 18 www xilinx com 2 XILINX Virtex 5 FPGA ML555 Development Kit UG201 v1 4 March 10 2008 XILINX Chapter 2 Getting Started This chapter describes the items needed to configure the Virtex 5 FPGA ML555 board The ML555 board is tested prior to shipment and should work out of the box The installer is recommended to inspect the board prior to use and confirm proper jumper and switch settings as directed in this user guide The ML555 board must be plugged into either a parallel bus expansion slot for PCI systems or a serial system bus expansion slot for PCI Express systems The DC power provided to the ML555 board from the PCI Express and PCI buses is different The ML555 system power configuration must be properly configured through board headers and shunts prior to plugging into the system unit Failure to configure the ML555 DC power system might result in damage to the ML555 board or the system unit Contact Xilinx Technical Support with any questions about proper configuration of the ML555 prior to powering up a system at http www xilinx com support clearexpress websupport htm Documentation and Reference Design CD The CD included in the Virtex 5 FPGA ML555 board kit contains the board design files including schematics PCB layout and bill of materials FPGA and CPLD design constraint files are included on the CD This file provides a signal
109. o the ML555 development kit Note Not all accessories are RoHS compliant and they might not be available in all countries Contact your local Xilinx Sales office to determine product availability Conversion Module SMA to SATA HW AFX SMA SATA The SMA to SATA module can be used in conjunction with the ML555 SMA connectors The ML555 only provides one set of SMA connectors whereas the HW AFX SMA SATA conversion module contains two sets of SMA connectors and two SATA connectors DC power is not provided to the SATA disk drive from either the ML555 board or the conversion module The SMA to SATA conversion module can be ordered from Xilinx as part number HW AFX SMA SATA Contact your local sales office for pricing information Additional information on the conversion module is available from the Xilinx website at www xilinx com xlnx xebiz designResources ip product details jsp key HW AFX SMA SATA Conversion Module SMA to RJ45 HW AFX SMA RJ45 The SMA to RJ45 module can be used in conjunction with the ML555 SMA connectors to convert the SMA interface to a RJ45 interface This adapter does not support 10 100 1000BASE T applications 16 www xilinx com Virtex 5 FPGA ML555 Development Kit UG201 v1 4 March 10 2008 XILINX ML555 Board The SMA to RJ45 conversion module can be ordered from Xilinx as part number HW AFX SMA RJ45 Contact your local sales office for pricing information Additional information on the conversion
110. on ip_documentation pcie_blk_plus_gsg343 pdf http www xilinx com support documentation ip documentation pcie blk plus ug341 pdf Additional technical information on PCI Express solutions is available at http www xilinx com pciexpress Xilinx provides customizable LogiCORE Initiator Target cores for PCI and PCI X applications designed to work with Virtex 5 FPGAs Included with the Xilinx IP are a data sheet getting started guide and user guide These documents are generated by the CORE Generator tool when starting a design project Additional information is available on the Xilinx website at http www xilinx com products design resources conn central protocols pci pcix htm PCI PCI X and PCI Express specifications are available from the PCI Special Interest Group PCISIG Contact the PCI Special Interest Group office to obtain the latest revision of these specifications Questions regarding the PCI Local Bus Specification or the PCI X Addendum or membership in the PCI Special Interest Group can be forwarded through PCI Special Interest Group PCI SIC 5440 SW Westgate Dr 217 Portland OR 97221 Phone 800 433 5177 inside the U S 503 291 2569 outside the U S Fax 503 297 1090 e mail administration pcisig com Website http www pcisig com e PCI Local Bus Specification Revision 3 0 e PCI X Addendum to the PCI Local Bus Specification e PCI Express Base Specification e PCI Express Card Ele
111. ores are configured to provide one PCI I O Space Base Address Register BAR and one Memory Space BAR The example application on the user interface in these PCI implementations is the same as Virtex 5 FPGA ML555 Development Kit www xilinx com 33 UG201 v1 4 March 10 2008 Chapter 3 Hardware Description XILINX provided with the cores a simple one doubleword DW register behind the I O BAR and a 16 DW memory behind the memory BAR To use the provided example implementation for PCI operation 1 Load the bitstream onto the ML555 FPGA see Table 3 37 page 86 2 Reboot the host computer without power cycling the ML555 board 3 The host BIOS will configure the core for PCI in the design 4 Use a configuration utility to verify that the device was configured properly and look for a device with a Vendor ID of 0x10EE and a Device ID of 0x0050 XAPP999 Ref 7 describes how to build a reference system for the Processor Local Bus Peripheral Component Interconnect PLBv46 PCI core using a MicroBlaze processor based embedded system using the ML555 board DDR2 SDRAM SODIMM 34 The ML555 board contains a 200 pin small outline dual in line memory module SODIMM connector J2 that supports installation of DDR2 SDRAM SODIMMs of 128 MB 256 MB or 512 MB Dual rank SODIMMs are not supported Xilinx provides a 256 MB DDR2 667 SODIMM Micron Semiconductor part number 4HTF3264HY 40E with the kit Table 3 5 provides a de
112. other with ICS2 generating a 150 MHz clock Table 3 24 M and N Constant Values Set Through ML555 DIP Switch Configuration Switch Position Parallel Load Pushbutton Synthesizer Circuit 1 SW9 Synthesizer Circuit 2 SW11 N1 SW12 pins 8 9 SW12 pins 7 10 NO SW10 pins 8 9 SW12 pins 6 11 M8 Tied to logic 0 Tied to logic 0 M7 Tied to logic 0 Tied to logic 0 M6 SW10 pins 7 10 Tied to logic 0 M5 SW10 pins 6 11 Tied to logic 0 M4 SW10 pins 5 12 SW12 pins 5 12 M3 SW10 pins 4 13 SW12 pins 4 13 M2 SW10 pins 3 14 SW12 pins 3 14 M1 SW10 pins 2 15 SW12 pins 2 15 MO SW10 pins 1 16 SW12 pins 1 16 Notes 1 The synt f arallel load pushbutton switch must be pressed and released to perform a parallel load of the esizer Alternatively the FPGA PLOAD1 or PLOAD2 output can be asserted and deasserted to perform a prs load without having to press and release the pushbutton switch associated with the clock synt esizer Virtex 5 FPGA ML555 Development Kit UG201 v1 4 March 10 2008 www xilinx com 67 Chapter 3 Hardware Description XILINX SW10 Position SW12 Position ME cst mo B cv B Jc B 2 10s2 m o E s ics1 m2 ol Bl sics2 vo rM aicsi us FI Bloc FIBI 5 ics1 m4 p 5 ICS2 M4 Bl e cs vs 6 ICS2 NO N jew NM ecs Logic 0 Position Logic 1 Position Logic O Position Logic 1 Position Example requests ICS1 330 MHz Clock Example reque
113. pment Kit UG201 v1 4 March 10 2008 X XILINX Edge Connector for PCI Express Operation Table 3 3 PCI Express Signals Add in Card Connector Pin and FPGA Pins per GTP_DUAL Tile Add in Card Connector PCI Express Signal Name P13 Pin FPGA Pin GTP DUAL Tile PCIE REFCLK P A13 Y4 PCIE REFCLK N A14 Y3 PETPO B14 W1 PETNO B15 Y1 PERPO A16 V2 X0Y2 PERNO A17 W2 PETP1 B19 AB1 PETN1 B20 AA1 PERP1 A21 AC2 PERN1 A22 AB2 PETP2 B23 AE1 PETN2 B24 AF1 PERP2 A25 AD2 PERN2 A26 AE2 X0Y1 PETP3 B27 AH1 PETN3 B28 AG1 PERP3 A29 AJ2 PERN3 A30 AH2 PETP4 B33 N1 PETN4 B34 P1 PERP4 A35 M2 PERN4 A36 N2 X0Y3 PETP5 B37 T1 PETN5 B38 R1 PERP5 A39 U2 PERN5 A40 T2 Virtex 5 FPGA ML555 Development Kit UG201 v1 4 March 10 2008 www xilinx com 27 Chapter 3 Hardware Description XILINX Table 3 3 PCI Express Signals Add in Card Connector Pin and FPGA Pins per GTP_DUAL Tile Add in Card Connector PCI Express Signal Name P13 Pin FPGA Pin 2 GTP_DUAL Tile PETP6 B41 AL1 PETN6 B42 AM1 PERP6 A43 AK2 PERN6 A44 AL2 X0YO PETP7 B45 AP3 PETN7 B46 AP2 PERP7 A47 AN4 PERN7 A48 AN3 PCIE_PERST A11 AE14 Not Applicable Notes 1 Signal names are with respect to the add in card connector slot nomenclature PETPx and PETNx connect to the endpoint port GTP receiver differential pai
114. r Figure 3 4 shows the PCI bus connector and power management headers Refer to Figure 3 16 page 78 to see how the SW8 switch and the P18 connector are configured for PCI power Min SW8 R en 0630 94V 8 WO 141795 as as Slide Switch SW8 P1 PCI Bus Connector M P9 60 TE LOSXINSOX G XALyin XNnix IS P8 e mE E P7 P18 Remove Shunts for PCI and PCI X Modes UG201_c3_04_092706 Notes 1 SW8 and P18 must be configured for PCI power mode Figure 3 4 PCI Connector and Power Management Headers Virtex 5 FPGA ML555 Development Kit www xilinx com 29 UG201 v1 4 March 10 2008 Chapter 3 Hardware Description XILINX Table 3 4 shows the edge connector P1 pin assignment The component side of the PCB is side A and the non component side or the back of the PCB is side B Table 3 4 P1 PCI Edge Connector Pinout iie Signal FPGA Pin jig Adis Signal FPGA Pin i 32 Bit Connector Al unused Nc Bl VCC_MINUS12 NC A2 VCC12 NC B2 unused NC A3 unused NC B3 GND NC A4 EDGE_JTAG NC B4 EDGE_JTAG NC A5 VCC5 NC BS VCC5 NC A6 EDGE INTA B J31 Out B6 VCC5 NC A7 EDGE INTC B H30 Out B7 EDGE INTB B G31 Out A8 VCC5 NC B8 EDGE_INTD_B K29 Out A9 unused NC B9 GND NC A10 VCC3V3 NC B10 unused NC A11 unused NC B11 unused NC 3 3V KEY NC 3 3V
115. r Generate PROM File Do you want to compress file click No 10 After a pause PROM File Generation Succeeded is displayed A PROM image file is now created and is ready for programming into the ML555 board A fully populated PROM file mcs with two design revisions must always be generated even if all of the Configuration Addresses 0 1 2 or 3 in the Platform Flash are not programmed The unused revisions can be populated with dummy bitstreams PROMGEN generates four output files The MCS and CFI files should always be in the same directory when the XCF32P Platform Flash is programmed The CFI file contains configuration information used by iMPACT during programming operations and the file is unique for each MCS file created Programming the PROM Connect the programming cable between the computer and the ML555 board Apply power to the ML555 board after the computer boots To program the XCF32P PROM follow these steps 1 Open iMPACT Start AII Programs Xilinx ISE Accessories AMPACT 2 Double click the Boundary Scan menu option 3 Right click on Right click to Add Device or Initialize JTAG chain Select Initialize Chain as shown in Figure 4 11 After a pause the ML555JTAG chain is graphically displayed as shown in Figure 4 12 4 Boundary Scan Summary indicates four devices are found Under Assign New Configuration File click Cancel A11 5 Double click the third or fourth device xc 32p The ML555 board conta
116. rdware Description 76 AVTTX RX 1 2V VR5 AVCCPLL 1 2V VR6 AVCC 1 0V VR7 PCle_VCC5 VR1 GTP Analog Power Jumper Off for PCI PCI X Operation P18 OO O Jumper On for PCI Express Operation 2 XILINX DDR2_1V8 VR2 DDR2_VREF VR3 PCI_VCC 3 0V U14 VCCO_2V5 U13 3 3V 12V 5V System Motherboard Slot Connector PCI Bus Sources 3 3V and 5V and PCI Express Sources 3 3V and 12V VCCAUX 2V5 HQ U12 for PCI PCI X Operation VCCINT 1VO VR4 sws 7 for PCI Express Operation UG201 c3 13 022708 Figure 3 14 Voltage Regulator Topology Caution The end user must configure the ML555 board prior to installing the board in the system unit Failure to configure the board jumpers prior to installation in the system unit might cause damage to the ML555 board www xilinx com Virtex 5 FPGA ML555 Development Kit UG201 v1 4 March 10 2008 X XILINX Voltage Regulators Figure 3 15 shows the location of SW8 and P18 on the ML555 board The switch and jumper MUST be configured prior to installing the board in the system unit SW8 selects the FPGA Vccnmr source PCI or PCI Express operation and P18 is the 12V to 5V enable for PCI Express operation on EIS eese s4v e WO 141795 zm EST SW8 FPGA Voc yr Source Selection Parallel PCI Bus Mode Switch Position 1 towards PCI Silkscreen on Board Sli
117. re channel or Ethernet speed and the SMA connectors should be used to route either the Fibre channel or Ethernet interface to an offboard connector interface The SMA connectors are not AC coupled on the ML555 board so either internal GTP AC coupling must be enabled or external AC coupling might be required for interfaces to offboard transceivers to be electrically compatible Parallel Bus Clocking PCI Operation The PCI specification calls for the PCI bus clock sourced from the motherboard PCI slot to have one load on the add in cards The LogiCORE solutions for PCI and PCI X designs depending upon bus mode and frequency require that the PCI bus clock enter the FPGA on a specific clock pin refer to Table 1 1 The ML555 board PCI bus clock is implemented as follows e The PCI bus clock signal CLK_FROM_EDGE enters the board on PCI edge connector P1 pin B16 e The clock is then routed in a Y topology to two parallel resistors R2 and R242 e The output side of R2 signal PCIBUSCLK1 is routed to FPGA pin L34 the regional clock pin of FPGA e The output side of R242 signal PCIBUSCLK2 is routed to FPGA pin J14 the global clock pin of FPGA If full electrical compliance is required the designer has the option to remove one of the two resistors R2 or R242 As shipped the ML555 board has both resistors installed Virtex 5 FPGA ML555 Development Kit www xilinx com 59 UG201 v1 4 March 10 2008 60 Chapter 3 Hardware
118. ripherals 5 perip VR2 PCI Connector 5V Input VR15V Output 1 8V 6A and FPGA 1 8V Veco reference voltage DDR2 memory interface VR3 PCI Connector 5V Input VR15V Output 0 9V 6A termination and FPGA 0 9V reference voltage U120 PCI Connector 5V Input VR15V Output 2 5V 5A FPGA VccAux supply FPGA Veco XGI U130 PCI Connector 5V Input VR15V Output 2 5V 5A headerand other ML555 2 5V peripherals PCI FPGA 3 0V V U146 PCI Connector 5V Input VR15V Output 3 0V 5A Sr Wyss reference voltage VR4 45 PCI Connector 3 3V U14 3 0V Output 10V 6A FPGA Vcecmr voltage Input PCI Connector 3 3V ee cd ed oe Wis m T VR5 45 poner d Connector 3 3V AVITTXand ee pu Input AVTRX dne termination voltages VR645 mn 33V v 4A eee PLL circuit Input AVCCPLL 8 y Input PCI Express GTP 1 0V analog VR745 Pel enm 95V Connector33V 1 0V AVCC 4A voltage P Input Notes 1 Refer to Figure 3 14 page 76 for a block diagram of the ML555 DC power system Additional design information is available on the ML555 board schematics 2 For PCI and PCI X design applications position switch SW8 Figure 3 16 page 78 to power the GTP transceiver analog supplies and FPGA Vcecmr from the 3 3V input voltage of the PCI connector Remove shunts on header P18 before applying power to the ML555 board 3 For PCI Express design applications position switch SW8 Figure 3 16 page 78 to power FPGA Vccmr from the 3 0V regulator U14 output GTP transceiver analog supplies are po
119. rmination voltages The GTP transceiver analog power supplies are filtered in accordance with the Virtex 5 FPGA RocketIO GTP Transceiver User Guide Eight of the 12 GTPs on the ML555 board are specifically targeted solely for PCI Express applications DDR2 SODIMM Power Power consumption for the DDR2 memory interface is dependent upon the density and speed of the memory installed in the SODIMM socket Table 3 35 shows approximate 1 8V current consumption requirements by density and transfer rate for Micron Semiconductor SODIMM s supported by the ML555 board Memory data sheet specifications should be consulted to determine specific power requirements for the SODIMM devices Higher densities and higher performance SODIMMs are supported however the user must calculate total application power and stay within the PCI and or PCI Express add in card specifications Table 3 35 DDR2 SODIMM Current Consumption versus Data Transfer Rate Memory Density 400 MT s 533 MT s 667 MT s 128 MB 480 mA 720 mA 860 mA 256 MB 620 mA 780 mA 940 mA 512 MB 720 mA 780 mA 1100 mA Current consumption can be even higher than shown in Table 3 35 if the four memory banks are interleaved in the DDR2 memory Interleaving is accomplished by using the BA 2 0 bank address as the least significant column address bits to the DDR2 memory While interleaving does not increase memory performance it increases power dissipation and should be avoided for
120. rs PERPx and PERNx connect to the endpoint port GTP transmitter differential pairs Port names at the connector are with respect to the downstream transmitter and receiver ports The downstream transmitter receiver ports connect to the upstream receiver transmitter ports respectively The PCIE REFCLK and PERNXx differential signals are AC coupled with a 0 1 pF capacitor Dedicated GTP DUAL tile assignments are required for 8 lane PCI Express Endpoint interfaces with ES silicon Production silicon removes GTP DUAL tile assignment restrictions 28 See XAPP1022 Ref 5 and XAPP1022 Ref 6 for examples of how to get started designing and debugging PCI Express endpoint applications using the Integrated Endpoint Block for PCI Express designs available in Virtex 5 LXT FPGAs www xilinx com Virtex 5 FPGA ML555 Development Kit UG201 v1 4 March 10 2008 XILINX 64 bit Edge Connector for PCI Operation 64 bit Edge Connector for PCI Operation Caution PCI and PCI Express system units provide different DC voltages to the add in card connectors Before plugging the ML555 board into the system unit the power configuration header settings must be reviewed to verify that the board will be powered properly Failure to configure the power system properly could result in damage to the system unit or the ML555 board Refer to Figure 3 16 page 78 to see how the SW8 switch and the P18 connector are configured for PCI or PCI X system bus powe
121. scription of the memory interface signal descriptions SODIMM connector pin assignments and associated FPGA pin assignments The SODIMM interface supports customer installation of DDR2 533 and or DDR2 400 SODIMMs One of the clock synthesizers must be used to generate the clock frequency for the SODIMM interface For most applications Clock Synthesizer 1 is used for DDR2 memory applications and Clock Synthesizer 2 is used for GTP transceiver applications The ML555 board does not support a 72 bit DDR data interface required for parity or error correction codes ECC The speed grade of the FPGA limits the DDR2 memory clock support to a range of 200 233 MHz or 400 466 million transfers per second Included on the CD ROM is a reference design for the DDR2 memory contained on the ML555 Verilog source code and a BIT file are included which can be loaded into the FPGA using the Platform Cable USB download cable and Xilinx iMPACT configuration software See the Readme txt file in the design directory for information about running and implementing the design Characteristics of the DDR2 SDRAM SODIMM provided with the kit e Organization 32M x 64 bit e Memory clock speed 5 ns 200 MHz using the clock synthesizer e CAS latency 3 or 4 DDR2 400 e 1 8V I O Stub Series Terminated Logic SSTL 18 compatible The data sheet for the DDR2 SDRAM SODIMM kit can be obtained from Micron Semiconductor at www micron com products modules Contact Micron for avail
122. sts ICS2 150 MHz Clock with M 8 0 0x021 and N 1 0 00 Serial Mode Operation with M 8 0 0x00C and N 1 0 01 UG201 c3 11 092706 Figure 3 12 Clock Synthesizer Parallel Load Switch Settings The FPGA provides interface signals to program each synthesizer in serial mode Table 3 25 lists the FPGA outputs and pin assignments that connect directly to the ICS8442 clock synthesizer control inputs A reference design is provided on the CD to demonstrate serial programming of the clock synthesizer modules from the FPGA Table 3 25 FPGA Signals for Serial Programming of the Clock Synthesizer Modules Signal PLOAD 1 Description 1CS8442 parallel load input used to parallel load the multiplier and divider switch inputs to the device A pushbutton switch is provided on the ML555 board to permit the user to load the settings into the synthesizer This signal must be a logic 0 level for serial mode operation FPGA Pin AP32 FPGA In Out Output STROBE 1 1CS8442 serial load input used to load serialized multiplier and divisor constants into the ICS8442 Asserted to perform serial to parallel loading for user defined clock synthesis This signal should be deasserted during serial data clocking asserted and then deasserted for one clock cycle to complete the serial to parallel loading of the data into the device AN33 Output SDATA_1 This signal contains the ICS8442 serial data input The serial da
123. t power supply The ML555 board does not use the 3 3V AUX power rail The PCI Express Card Electromechanical Specification places restrictions on the amount of power an add in card can draw from the system unit power supply The PCI Express add in card power consumption limits are shown in Table 3 33 Single lane PCI Express applications require the add in card to power up in the 10W mode After the host processor completes configuration the slot can utilize the full 25W power allocation The ML555 board can only plug into a x1 lane PCI Express connector using an adapter board to convert the eight lane ML555 PCI Express interface to a single lane form factor The ML555 board plugs into a x8 lane PCI Express slot in a server application with a 25W power restriction from the system unit The add in card slot can be wired for either x4 or x8 lanes depending on the server The 75W add in card slot is primarily for 16 lane PCT Express applications The ML555 board can plug into a 16 lane add in card slot providing a maximum application link capability of 8 lanes Table 3 33 Add in Card Power Rail Capacities for PCI Express Operation Power Rail 10 Watt Slot 25 Watt Slot 75 Watt Slot Standard Height PCI x1 X1 x4 or x8 lanes x16 lanes supported by the Express Card Lanes server applications ML555 board 3 3V 3 0A max 3 0A max 3 0A max 3 3V AUX 375 mA max 375 mA max 375 mA max 12V 0 5A max 2 1A max 5 5A max
124. ta is provided in the sequence T1 TO NULL N1 NO M8 M7 M6 M5 M4 M3 M2 M1 and finally MO The ICS8442 data sheet provides a serial loading timing diagram and definitions for serial data bits AN34 Output SCLOCK_1 The ICS8442 serial clock input should only be active during serial loading of the synthesizer The clock should be deasserted at all other times Data is clocked into the ICS8442 on the rising edge of the SCLOCK The ICS8442 data sheet provides a serial loading timing diagram and definitions for serial data bits AM32 Output 68 www xilinx com Virtex 5 FPGA ML555 Development Kit UG201 v1 4 M arch 10 2008 XILINX Table 3 25 FPGA Signals for Serial Programming of the Clock Synthesizer Modules Continued Clock Generation FPGA H 1 Signal Description FPGA Pin In Out LVDSCLKMOD1_P Clock Synthesizer 1 clock outputs See Figure 3 8 for a schematic H19 Input representation of the clock network on the ML555 board LVDSCLOCKMOD1_N H20 Input MGT X0Y1 RCLKP AF4 Input MGT X0Y1 RCLKN AF3 Input PLOAD 2 ICS8442 parallel load input used for parallel loading of AM33 Output multiplier and divider switch inputs to the device A pushbutton switch is provided on the ML555 board to permit the user to load the settings into the synthesizer This signal is asserted to perform a parallel load operation For serial configuratio
125. te 6 to Table 3 1 page 24 to identify FPGA connection of PCIE_PERST Added PCIE_PERST to Table 3 3 page 27 Added reference and link to XAPP999 in Reference Designs for PCI and PCI X Operation page 33 Added reference and links to Xilinx application notes XAPP858 and XAPP865 in DDR2 SDRAM SODIMM page 34 Corrected FPGA pin assignments for IIC_SDA_SFP 1 2 and IIC SCK SFP 1 2 signals and updated footnotes 2 and 5 in Table 3 7 page 39 Added reference and link to application note XAPP870 in Serial ATA Interface page 40 Corrected FPGA pin assignment for P1 RCLKI signal in Table 3 11 page 43 Added website link to download Silicon Laboratories VCP device drivers in the USB to UART Bridge page 51 Specify 30 MHz oscillator frequency for component Y2 in Table 3 18 page 53 Changed signal name for FPGA GCLK input pin L19 to FPGA_GCLK_30MHZ in Figure 3 8 page 55 Figure 3 9 page 56 and Table 3 19 page 57 Changed signal name for FPGA GCLK input pin AD32 to FPGA GCLK 30MHZ in Table 3 26 page 70 Added footnote to Table 3 37 page 86 Updated footnote 3 in Table 4 1 page 89 to recommend Master SelectMAP configuration of the ML555 Changed CPLD CLK to 30 MHz in Figure 4 5 page 92 Figure 4 6 page 98 and Figure 4 7 page 99 as well as Table 4 4 page 94 Changed oscillator Y2 frequency to 30 MHz in Figure 4 8 page 100 Added footnote to Table 4 7 page 100 concerning CCLK configuration frequency recommendation Added BitGen comman
126. to prepare the PROM files using iMPACT and the PROMGEN Wizard 1 Open iMPACT Start gt All Programs Xilinx ISE Accessories AMPACT 2 Double click PROM File Formatter Virtex 5 FPGA ML555 Development Kit www xilinx com 101 UG201 v1 4 March 10 2008 Chapter 4 Configuration 2 XILINX 3 Under Prepare PROM Files shown in Figure 4 9 select the following 102 Under I want to target a click the PROM Supporting Multiple Design Versions radio button and select XCFP PROM with Design Revisioning from the drop down menu Under PROM File Format select the MCS radio button In the PROM File Name box enter a filename of your choice The design example uses m1555xcf32p In the Location box browse to or enter the directory where your bitstreams are located This directory is the same location as where the generated PROM output files are stored The design example uses C Data Click Next iMPACT Prepare PROM Files E want to target a O Xilinx PROM Generic Parallel PROM 3rd Party SPI PROM 8 PROM Supporting Multiple Design Versions XCFP PROM with Design Revisioning v PROM File Format MCS QTEK UFP C format Exo BIN ISC HEX Swap Bits Checksum Fill Value 2 Hex Digits FF PROM File Name ml555xcf32p Location C Data UG201_c4_09_052307 Figure 4 9 Prepare PROM Files www xilinx com Virtex 5 FPGA ML555 Development Kit UG201 v1 4
127. tor header P38 is used to enable or bypass the Platform Flash device U1 and connector header P20 is used to enable or bypass the second Platform Flash device U15 To enable the CPLD for JTAG configuration the shunts on P39 are connected from pin 1 to pin 2 and a second shunt connects pin 3 to pin 4 To bypass the CPLD a single shunt is installed on P39 connected from pin 2 to pin 3 To enable the Platform Flash devices for JTAG configuration two shunts are installed on connectors P38 P20 connecting from pin 1 to pin 2 for the first shunt and connecting pin 3 and 4 for the second shunt To bypass the Platform Flash devices a single shunt on P38 P20 is connected from pin 2 to pin 3 The default board configuration enables all four devices in the JTAG scan chain P39 P38 O4 O4 O3 03 U1 U15 Platform Flash Platform Flash 2 JTAG Port 90 UG201_c4_03_070706 Figure 4 3 JTAG Chain The ML555 board provides a JTAG connector P5 to configure the FPGA and program JTAG devices located in the JTAG chain Figure 4 4 shows the pin assignments for the JTAG connector The JTAG cable connects to P5 and the connector on the ML555 board has a keyed plastic shroud to ensure that the device programming cable connects properly P5 JTAG Connector 25V TMS TCK TDO TDI 2mm UG201 c4 04 070306 Figure 4 4 JTAG Cable Hook up www xilinx com Virtex 5 FPGA ML555 De
128. upply and computer peripheral consumer stores A USB B to A cable is required to interface a PC USB A port to the ML555 USB B port Royalty free Virtual COM Port VCP device drivers are provided by Silicon Laboratories to permit the CP2102 USB to UART bridge to appear as a COM port to the personal computer PC application The UART interface side of the bridge implements all RS 232 interface signals including control and handshaking signals The VCP device driver must be installed on the PC prior to attempting to establish communications with the ML555 board The device driver is on the ML555 CD ROM The driver allows the PC USB port to Virtex 5 FPGA ML555 Development Kit www xilinx com 51 UG201 v1 4 March 10 2008 Chapter 3 Hardware Description XILINX be configured as a serial COM port for the user to continue working with serial communication utilities like HyperTerminal or Tera Term Pro The CP210x USB to UART Bridge VCP drivers can be downloaded from the Silicon Laboratories website at http www silabs com tgwWebApp public web content products Microcontrollers en MCU Downloads htm For technical information and support for the CP210x USB to UART bridge controller integrated circuit and the associated VCP device driver visit the Silicon Laboratories website at www silabs com The ML555 FPGA must have a UART design instantiated to communicate with the PC on the USB interface A reference design and
129. vboards index htm Figure 3 5 shows the P32 and P33 LVDS connectors www xilinx com Virtex 5 FPGA ML555 Development Kit UG201 v1 4 March 10 2008 Minin 6090n5Y9 11 34 a LOSXTASOX G XALYIA XNTIX 3 LVDS Interface P47 Mezzanine Card Serial Interface P48 Mezzanine Card 5V P33 24 Channel LVDS Interface P32 24 Channel LVDS Interface UG201_c3_05_092706 Figure 3 5 LVDS and Mezzanine Card Connectors Table 3 12 and Table 3 13 list the SAMTEC pin connections for P32 and P33 respectively Table 3 12 SAMTEC Pin Connections P32 Virtex 5 FPGA ML555 Development Kit UG201 v1 4 March 10 2008 www xilinx com SAMTEC QSE SAMTEC QSE 028 DP P32 Signal Foes 028 DP P32 Signal Fees Pin Pin Odd Even 1 GPIO1 I00 NO K22 2 GPIO1 I01 NO H23 3 GPIO1 Io0 PO K23 4 GPIO1 I01 P2 G23 5 GND N A 6 GND N A 7 No connect N A 8 No connect N A 45 Chapter 3 Hardware Description 46 Table 3 12 SAMTEC Pin Connections P32 Continued XILINX So2a DP P32 signan FPGA oepPPs2 Signat FPGA Odd Pin Even Fan 9 No connect N A 10 No connect N A 11 GND N A 12 GND N A 13 GPIO1_I02_N T24 14 GPIO1 103 N N25 15 GPIO1 102 P R24 16 GPIOI I03 P P25 17 GND N A 18 GND N A 19 GPIO1 I04 N P24 20 GPIO1_I05_N P27 21 GPIO1_104_P N24 22 GPIO1_I05_P P26 23 GND N A 2
130. velopment Kit UG201 v1 4 March 10 2008 XILINX SelectMAP Interface Table 4 2 P5 JTAG Header Signal Descriptions and Pin Assignments Signal Name Description P5 Pin FPGA Pin CPLD Pin Flash Pin g p Number Number Number Number JTAG_TMS JTAG TMS to 4 AC14 10 E2 FPGA CPLD Flash JTAG_TCK JTAG TCK to 6 AB15 11 H3 FPGA CPLD Flash JIAG_TDO JTAG TDO from Flash 8 N A N A Ee JTAG_TDI JTAG TDI to FPGA TDI 10 AC15 N A N A Notes 1 This JTAG connectivity assumes that all four devices are in the JTAG configuration chain 2 The JTAG_TDO connection is made to the second Platform Flash device U15 The JTAG TMS and JTAG TCK signals are connected to both U1 and U15 Platform Flash devices SelectMAP Interface Virtex 5 FPGA ML555 Development Kit The SelectMAP interface is connected to the Platform Flash devices indirectly through the CPLD For the SelectMAP interface to operate correctly the CPLD needs to be programmed via JTAG such that the correct connections are made between the FPGA and the Flash The CPLD on the ML555 board has a default image programmed into the device to permit selection of up to four static design images in the two Platform Flash configuration devices The source HDL code and CPLD constraint file are located on the CD ROM provided with the ML555 kit Figure 4 5 is a general schematic for the Flash CPLD FPGA SelectMAP Interface Table 4 3 through Table 4 5 list t
131. vice speed grade as 1C ES Updated Initial Board Checks Before Applying Power page 19 Corrected board reference designator for Table 3 4 page 30 to use P1 as PCI Edge Connector pinout Updated DDR2 SDRAM SODIMM page 34 to reference DDR2 reference design included with kit Added lane assignments to Table 3 20 page 58 Added link to www idt com for availability of clock jitter attenuator circuits on page 60 Updated Table 3 33 page 80 to include ML555 support for plugging board into 16 lane add in card connector Updated Table 3 37 page 86 to include reference designs pre loaded into ML555 Platform Flash devices Add Note 3 to Table 4 1 page 89 Slave SelectMAP not supported Updated SelectMAP Clock Selection including Table 4 7 and Figure 4 8 Added reference to the Development System Reference Guide for PROMGen and BitGen software applications Updated Specifying the Xilinx PROM Device including Figure 4 10 and Figure 4 13 Added Figure 4 14 and Figure 4 15 06 18 07 1 3 Updated Table 1 1 page 14 to clarify version and build information for PCI and PCI X IP cores Revised Serial Bus Development section Removed ES from FPGA part number Added footnote 3 to Table 3 3 page 27 Updated Figure 3 8 page 55 and Figure 3 9 page 56 to include a 4 7KQ pull up resistor on the SATA MGT CLKSEL FPGA output and labeled the Clock MUX inputs Defined the SATA MGT CLKSEL default selection in Table 3 19 page 57
132. wered from the 3 3V input voltage of the PCI Express connector Install two shunts on connector P18 P18 1 to P18 2 and P18 3 to P18 4 to connect VR1 5V output to power the onboard regulators 4 These voltage regulator output ports are connected in series through a 10 mQ Kelvin resistor to the load on the ML555 board VR1 has a 150 mQ series Kelvin resistor Refer to Power Supply Monitoring page 82 for additional information 5 lies can be turned on in any sequence The Virtex 5 FPGA data sheet provides a table for Power On Current for FPGA power supp Virtex 5 Devices for a specified voltage power on sequence V sg it need to have voltage sequencing circuitry for the DC to DC voltage converters on the board Virtex 5 FPGA ML555 Development Kit UG201 v1 4 March 10 2008 www xilinx com ms VCCAUX Veco The ML555 board does not have nor does 81 XILINX Chapter 3 Hardware Description GTP Transceiver Power Three low drop out LDO voltage regulators are provided for the analog voltage inputs to the GTP transceivers Each regulator has a voltage divider circuit that permits the voltage to be adjusted if required simply by changing resistance value of the voltage divider Each regulator can source up to 4A of current A single voltage regulator sources power to the AVTTX AVTRX and VVTTRXC inputs of the GTP transceivers The ML555 board does not provide separate power supplies for the transmitter and receiver te

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