AM1808 SOM-M1 Hardware Specification
Contents
1. ppp 2X R1 2 TOP 1 4 MAX m 0 L L I I PE I 4 IE rop FT IE FRE Jest THIS DRAWING PREPARED IN ACCORDANCE WITH ASME Y14 5 2000 ALL DIMENSIONS ARE IN MILLIMETERS UNLESS OTHERWISE2. 6 3 Electrical Specification sss iisen riter cede net HUE ce acta 7 3 1 Absolute Power Maximum 7 3 2 Recommended Power Operating 7 4 Peripheral SpecificatiOn rrserrnavnnnnnvnnnnnnnnnnvnnnnvnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnennnnnnnnnnnnnnennnner 8 P MEG Hlc P ILE 8 4 2 MOITIOLY eau ck RT SE ERR XU 8 42 1 Mobile DDR Feen 8 4 2 2 SSPDLEIaSI eme temm teu URSI d 8 4 3 1000 Ethi rnet PHY cii etri 8 4 4 Display Interface 528323 bee 84 58 24488378 9 4 57 Seral Interfaces itte RTI M EE E 9 45 WAR O22 m accep perdi san temm 9 4 5 2 gt SPION ea uc e dave Ve ain e uu 9 45 33 CE 9 45 4 Hin 10 4 5 5 gt MCASPO sau arr rear baade 10 4 6 USB Interface c aA a el ete 10 4 7 ADGC TouchInterfaceuin alae ee eee steele Galatians ayer 10 4 8 General Purpose I O 10 49 Expansion Feature 10 5 Sy
3. 4 7k pull down on SOM UPP XD 5 3 3V or 1 8V Used to latch boot mode at startup see 11 uP VPIF DOUT13 GP7 5 BOOT 5 Hi Z see Note 1 Note 2 VP DOUT 5 LCD_D 5 UPP XD 13 3 3V or 1 8V LCD G0 data bit when outputting RGB565 12 uP_VPIF_DOUT5 GP7 13 Hi Z see Note 1 to an RGB666 display LCD R4 data bit when outputting RGB565 VP DOUT 14 data to an RGB666 display LCD D 14 4 7k pull down on SOM UPP XD 6 3 3V or 1 8V Used to latch boot mode at startup see 13 uP VPIF DOUT14 GP7 6 BOOT 6 Hi Z see Note 1 Note 2 VP DOUT 6 LCD D 6 UPP XD 14 3 3V or 1 8V LCD G1 data bit when outputting RGB565 14 uP VPIF DOUT6 GP7 14 Hi Z see Note 1 data to an RGB666 display LCD R5 data bit when outputting RGB565 data to an RGB666 display Notice that LCD is omitted LCD R5 Red MSB is also connected to LCD Red LSB DOUTT 15 when driving an 18 bit display with 16 bits LCD D 15 4 7k pull down on SOM UPP_XD 7 3 3V or 1 8V Used to latch boot mode at startup see 15 uP DOUT15 GP7 7 BOOT 7 Hi Z see Note 1 Note 2 VP DOUT 7 LCD D 7y UPP XD 15 3 3V or 1 8V LCD G2 data bit when outputting RGB565 16 uP VPIF DOUT7 GP7 15 Hi Z see Note 1 data to an RGB666 display MMCGSD1 DAT 5 LCD HSYNC 3 3V or 1 8V 17 uP LCD HSYNC GP8 9 Hi Z see Note 1 MMCGSD1 DAT 7 LCD PCLK 3 3V or 1 8V 18 uP LCD PCLK GP8 1 1 Hi Z see Note 1 22 ohm series R on SOM 19 DGND I GND Gr
4. SPECIFIED TOLERANCES UNLESS OTHERWISE SPECIFIED x 0 5 gt 0 2 X XX 0 1 1 BOTTOM 102309 SLE DATE 5 1 KAG 10 23 09 LOGIC PMH 103309 411 Washington Ave Suite 400 Minneapolis MN 55401 scare NO SHEET GATE 612 672 9495 r 612 672 9489 1 www loglepd com 70 MANE DATE 41 1013825 10F2 8 7 6 5 4 3 2 1 BOTTOM TOP 246 920 09S S 0 88606 0 ET ISOMETRIC VIEWS FOR REFERENCE ONLY 2 PIN LOCATIONS 99 100 A A 13 0 17 0 RECOMMENDED BASEBOARD FOOTPRINT SHEET 2 OF 2 DWG NO 1013825 4 1 SCALE Appendix B Example Retaining Methods NOTES 1 BASED ON TESTING A LIMITED NUMBER OF SAMPLES THE 5 1 REVISIONS REV ECO NUMBER DESCRIPTION DATE A INITIAL RELEASE 10 28 09 B 029865 08 17 10 UPDATED SOM DESCRIPTION REQUIRES 10 LBS OF EXTRACTION FORCE AFTER ONE INSERTION CYCLE AFTER 30 INSERTION AND EXTRACTION CYCLES THIS IS REDUCED TO 7 LBS ENG DATE NWR 10 28 09 DATE KAG 10 28 09 MGR DATE PMH 10 28 09 MANE DATE 411 N Washington Ave Suite 400 Minneapolis MN 55401 T 612 672 9495 F 612 672 9489 1 www logicpd com n H N m SCALE TITLE System None DWG 1014513 THIS DRAW
5. use1 1 EMAC MMC SD EMIFA 8b 16B e Ctir OHCI Ctir 10 100 8b SATA NAND Flash DORZMDDR PHY PHY 2 16b SDRAM Figure 2 1 AM1808 Processor Block Diagram Note The block diagram pictured above comes from Tl s AM1808 ARM Microprocessor Data Sheet document number SPRS653 February 2010 Available from TI s website http www ti com am1808 2 2 SOM Interface Logic PD s common SOM interface allows for easy migration to new processors and technology Logic PD is constantly researching and developing new technologies to improve performance lower cost and increase feature capabilities By using the common SOM footprint it is possible to take advantage of Logic PD s work without having to re spin the old design in certain cases dependent upon peripheral usage Contact Logic PD sales for more information product sales logicpd com In fact encapsulating a significant amount of your design onto the SOM reduces any long term risk of obsolescence If a component on the SOM design becomes obsolete Logic PD will simply design for an alternative part that is transparent to your product Furthermore Logic PD tests all SOMs prior to delivery decreasing time to market and ensuring a simpler and less costly manufacturing process PN 1015746A Logic PD Inc All Rights Reserved 4 2 2 1 0 O O gt m o e a
6. EMA_D 5 3 3V or 1 8V 44 uP_EMIFA_D5 GP4 13 Hi Z see Note 1 A 12 3 3V or 1 8V 45 uP_EMIFA_A12 GP5 12 Hi Z see Note 1 D 6 3 3V or 1 8V 46 uP EMIFA D6 GP4 14 Hi Z see Note 1 47 DGND I GND Ground Connect to digital ground 48 DGND I GND Ground Connect to digital ground Designed for a standard lithium battery 49 MAIN BATT IN See Section 5 5 1 3 Designed for a standard lithium battery 50 MAIN BATT IN 10 See Section 5 5 1 3 Designed for a standard lithium battery 51 MAIN BATT IN See Section 5 5 1 3 Designed for a standard lithium battery 52 MAIN BATT IN See Section 5 5 1 3 53 DGND GND Ground Connect to digital ground PN 1015746A Logic PD Inc All Rights Reserved 24 AM1808 SOM M1 Hardware Specification J2 Pin SOM Net Name Processor Name I O Voltage Description 54 DGND I GND Ground Connect to digital ground EMA A 13 3 3V or 1 8V 55 uP A13 GP5 13 Hi Z see Note 1 56 RFU NA NA Reserved for future use Do not connect ETHER LINK Connect to cathode of Ethernet Act LED 57 LEDn 4 7k pull up on SOM 58 RFU NA NA Reserved for future use Do not connect 59 RFU NA NA Reserved for future use Do not connect SCS 6 12 0 bus is used for communication 12 0 SDA between the
7. 5 2 e 2 3 2 3 1 AM1808 SOM M1 Hardware Specification AM1808 SOM M1 Block Diagram Power TPS65070 4 wire touch PMIC Touch controller dd AM1808 UARTS x3 12c 2 Processor LCD VPIF__DOUT McASP Clock Generation USB HS OTG includes SATA USB FS Host SPI 10 100 NOR Flash Ethernet Ethernet select configurations Figure 2 2 AM1808 SOM M1 Block Diagram Mechanical Specifications Mechanical Characteristics of SOM 1 Parameter min Typical Unit Notes Dimensions mm rams 2 Connector nserionfRemoval s0 Cycles Notes The AM1808 SOM M1 in the Zoom AM1808 EVM Development Kit includes power measurement circuitry along one edge of the SOM This additional circuitry increases the PCB size to 33 7 x 40 x 4 1 mm All other AM1808 SOM M1 modules including those available in production volumes are the typical size listed above May vary depending on SOM configuration PN 1015746A Logic PD Inc All Rights Reserved 5 AM1808 SOM M1 Hardware Specification 2 3 2 Interface Connectors The AM1808 SOM M1 connects to a PCB baseboard through three 100 pin board to board BTB socket connectors Ref Designator Manufacturer SOM Connector P N Mating Connector P N J1 J2 J3 Hirose DF40C 100DP 0 4V 51 DF40C 100DS 0 4V 51
8. 1 4 7k pull up on SOM SPI1 SCS 1 EPWM1A GP2 15 3 3V or 1 8V 97 uP SPI1 SCSn1 TM64P2 IN12 Note 1 1k pull down on SOM SOMI 3 3V or 1 8V 98 uP SPI1 SOMI GP2 1 1 Note 1 AXR15 EPWMOTZ O 4 7k pull up on SOM ECAP2 APWM 2 3 3V or 1 8V This signal is also connected to 99 uP EPWMO 7710 GPO 7 Hi Z see Note 1 41 39 PN 1015746A Logic PD Inc All Rights Reserved 26 AM1808 SOM M1 Hardware Specification J2 Pin SOM Net Name Processor Name I O Voltage Description SIMO 3 3V or 1 8V 100 uP SPI1 SIMO GP2 10 Note 1 4 7k pull up on SOM Note 1 Most AM1808 SOM M1 I O pins are dual voltage capable that is the SOM I O pins may be configured to operate at 3 3V or 1 8V The desired I O voltage is set via J1 37 See Section 5 5 2 for more information 73 Connector 100 Pin Descriptions J3 SOM Net Name Processor Name I O Voltage Description 1 RFU NA Reserved for future use Do not connect Do not connect 3 3V or 1 8V Connected to J1 5 via zero ohm res on 2 BOOTBIT2 NA Note 1 SOM 3 RFU NA NA Reserved for future use Do not connect Do not connect 3 3V or 1 8V Connected to J1 9 via zero ohm res on 4 BOOTBIT4 NA Note 1 SOM 5 RFU NA NA Reserved for future use Do not connect
9. 45 1 8V Notes 1 General note CPU power rails are sequenced on the module 2 VREF represents the peripheral I O supply reference for the specific CPU voltage rail For and different values are provided for VREF 1 8V and 3 3V 3 Please see Section 5 5 1 1 for detailed information about 5V usage on the AM1808 SOM M1 4 Please see Section 5 5 1 3 for detailed information about MAIN BATT IN usage on the AM1808 SOM M1 5 Measurement was taken with a system consisting of SOM and baseboard The SOM was running the standard U Boot software image version 2009 11 This power measurement represents current consumption on the SOM only baseboard and UI board were excluded 6 Same setup as Note 5 with the exception that the SATA clock generator was disabled by populating R146 PN 1015746A Logic PD Inc All Rights Reserved 7 4 1 4 2 4 2 1 4 2 2 4 3 AM1808 SOM M1 Hardware Specification Peripheral Specification Clocks The AM1808 SOM M1 contains two crystals One crystal is used to generate clocks for the processor core s and peripherals The second crystal is dedicated to the RTC module The AM1808 processor includes on chip Phase Locked Loops PLLs and signal dividers which generate all core peripheral clocks from a single external 24 000 MHz crystal The maximum core processor operating frequency is 450 MHz Optionally on chip module PLLO provides an output SOM Pin SOM Net 1808 P
10. 8 3 3V or 1 8V 39 uP VPIF DINO RMII CRS DV Hi Z see Note 1 40 RFU NA Reserved for future use Do not connect VP DIN 4 UHPI_HD 12 UPP CHA D 12 3 3V or 1 8V 41 uP VPIF DIN4 RXD 1 Hi Z see Note 1 42 RFU NA Reserved for future use Do not connect VP DIN S UHPI HD 11 UPP CHA D 11 3 3V or 1 8V 43 uP VPIF DIN3 RXD 0 Hi Z see Note 1 44 RFU NA Reserved for future use Do not connect 45 RFU NA Reserved for future use Do not connect UHPI HCNTL1 uP UPP CH1 STAR UPP CHA STAR 3 3V or 1 8V 46 T T GP6 10 Hi Z Note 1 PN 1015746A Logic PD Inc All Rights Reserved 28 AM1808 SOM M1 Hardware Specification J3 Pin SOM Net Name Processor Name I O Description 3 3V or 1 8V 47 USB1 PWR EN CAS GP2 4 Hi Z Note 1 VP CLKIN1 UHPI HDS1 3 3V or 1 8V 48 uP VPIF CLKIN1 GP6 6 Hi Z see Note 1 VP DIN 1 UHPI HD 9 UPP CHA D 9 RMII MHZ 50 CL 3 3V or 1 8V 49 uP VPIF DIN1 K Hi Z see Note 1 UHPI HCNTLO UPP CHA CLK 3 3V or 1 8V 50 uP UPP CH1 GPe 11 Hi Z see Note 1 22 ohm series R on SOM 51 DGND I GND Ground Connect to digital ground UHPI HHWIL UP uP UPP CH1 ENAB P CHA ENABLE 3 3V or 1 8V 52 LE GP6 9 Hi Z see Note 1 3 3V or 1 8V 53 uP_McASP_CLKX ACLKX GPO 14 H
11. AM1808 processor and the TM64P3 OUT12 3 3V or 1 8V 565070 60 uP SPI1 SCSn6 GP1 4 see Note 1 4 7k pull up SOM 61 RFU NA Reserved for future use Do not connect SCS 7 12 0 bus is used for communication 12 0 SCL between the AM1808 processor and the TM64P2 OUT12 3 3V or 1 8V 565070 62 uP SPI1 SCSn7 GP1 15 Note 1 4 7k pull up on SOM 63 ETHER SPEED LED Connect cathode of Ethernet Speed LED 64 VRTC_IN I 3 3V or 1 8V 65 3 3V or 1 8V Note 1 MII bus is used to communicate between AXR6 CLKRO the AM1808 processor and LAN8710 GP1 14 3 3V or 1 8V Ethernet PHY the SOM 66 uP MCBSPO CLKR TXEN Note 1 22 ohm series R on SOM 3 3V or 1 8V 67 3 3V or 1 8V Note 1 bus is used to communicate between GP8 7 the AM1808 processor and LAN8710 TXD O 3 3V or 1 8V Ethernet PHY the SOM 68 uP MCBSPO CLKS CLKSO Note 1 22 ohm series on SOM ENA 3 3V or 1 8V 69 uP ENAn GP2 12 Note 1 4 7k pull up on SOM AXR3 MII bus is used to communicate between GP1 11 3 3V or 1 8V the AM1808 processor and LAN8710 70 uP FSX MII_TXD 3 Note 1 Ethernet PHY on the SOM 71 ETHER_TX 49 9 ohm pull up SOM AXR2 DRO bus is used to communicate between GP2 10 3 3V or 1 8V t
12. I see Note 1 4 7k pull down on SOM 45 SATA RXN SATA RXN I SPIO_SCS 3 UARTO_CTS 8 2 bus is used to communicate between MIL RXD 1 the AM1808 processor and LAN8710 SATA MP SWITC 3 3V or 1 8V Ethernet PHY on the SOM 46 uP SPIO SCSn3 H I Note 1 4 7k pull up on SOM 47 DGND I GND Ground Connect to digital ground SPIO_SCS 2 UARTO_RTS bus is used to communicate between the AM1808 processor and LAN8710 RXD O 3 3V or 1 8V Ethernet PHY the SOM 48 uP SPIO SCSn2 SATA CP DET I Note 1 4 7k pull up on SOM 49 RFU NA NA Reserved for future use Do not connect SPIO SCS B MII bus is used to communicate between UARTO RXD the AM1808 processor and LAN8710 GP8 4 3 3V or 1 8V Ethernet PHY on the SOM 50 uP_SPIO_SCSn5 RXD 3 I see Note 1 4 7k pull down on SOM 51 RFU NA Reserved for future use Do not connect AMUTE UART2_RTS 3 3V or 1 8V 52 uP_UART2_RTSn GPO 9 Note 1 53 DGND GND Ground Connect to digital ground RSVD UART2_CTS GPO 8 3 3V or 1 8V 54 uP UART2 CTSn DEEPSLEEP I see Note 1 4 7k pull up on SOM 55 SATA TXN SATA TXN EMA A 15 MMCSDO 6 3 3V or 1 8V 56 uP A15 GP5 15 Hi Z see Note 1 57 SATA TXP SATA TXP EMA A 14 MMCSDO DAT 7 3 3V or 1 8V 58 uP A14 GP5 14 Hi Z see Note 1 A 21 MMCSDO DAT O 3 3V or 1 8
13. found in their respective manuals and specification documents please see Section 1 5 for additional resources Additional Documentation Resources The following documents or documentation resources are referenced within this Hardware Specification m Tl s AM1808 ARM Microprocessor Datasheet User Guides Application Notes White Papers and Errata http www ti com am1808 m 115 7PS65070 Datasheet http focus ti com docs prod folders print tps65070 html m USB 2 0 Specification available from USB org http www usb org developers docs m U Boot documentation http www denx de wiki U Boot W ebHome m Logic PD AM1808 Hardware Design Files BOM Schematic and Layout for all boards included in the development kits as well as all standard configurations SOMs Sign into your account on Logic PD s website to access the files for your specific development kit and SOM http support logicod com auth PN 1015746A Logic PD Inc All Rights Reserved 2 AM1808 SOM M1 Hardware Specification 2 Functional Specification 2 1 Processor 2 1 1 AM1808 Processor The AM1808 SOM M1 uses Tl s high performance AM1808 microprocessor This device contains an ARM926EJ S MPU core and provides many integrated on chip peripherals including ARM ARM926EJ STM RISC core Integrated LCD Controller Up to 1024 x 1024 x 16 bit color Three UARTs 125 codec interface Universal Serial Bus USB One high speed USB 2 0 On the Go OTG interface One full
14. gt LOGIC PD AM1808 SOM M1 Hardware Specification Hardware Documentation Logic PD Products Published April 2010 Last revised 2011 This document contains valuable proprietary and confidential information and the attached file contains source code ideas and techniques that are owned by Logic PD Inc collectively Logic PD s Proprietary Information Logic PD s Proprietary Information may not be used by or disclosed to any third party except under written license from Logic PD Inc Logic PD Inc makes no representation or warranties of any nature or kind regarding Logic PD s Proprietary Information or any products offered by Logic PD Inc Logic PD s Proprietary Information is disclosed herein pursuant and subject to the terms and conditions of a duly executed license or agreement to purchase or lease equipment The only warranties made by Logic PD Inc if any with respect to any products described in this document are set forth in such license or agreement Logic PD Inc shall have no liability of any kind express or implied arising out of the use of the Information in this document including direct indirect special or consequential damages Logic PD Inc may have patents patent applications trademarks copyrights trade secrets or other intellectual property rights pertaining to Logic PD s Proprietary Information and products described in this document collectively Logic PD s Intellectual Prop
15. speed USB 1 1 host interface Serial ATA Controller SATA I 1 5Gb s or SATA II 3Gb s Many general purpose I O GPIO signals Programmable timers Real time clock RTC Low power modes IMPORTANT NOTE The AM1808 processor pinout is heavily multiplexed using one peripheral may preclude the use of another Users should carefully review the processor pinout SOM pinout and AM1808 multiplexing table See 5 AM1808 ARM Microprocessor Datasheet User Guides and Application Notes for additional information IMPORTANT NOTE Please visit Tl s website for errata on the AM1808 http www ti com am1808 PN 1015746A Logic PD Inc All Rights Reserved 3 AM1808 SOM M1 Hardware Specification 2 1 2 AM1808 Processor Block Diagram JTAG Interface ARM Subsystem System Control Moo ARM926EJ S CPU input PLL CIock With MMU Clock s Generator w OSC 4KB ETB M 16KB 16 Timer x3 PowerSieep D Cache Controller 8KB RAM RTC Vector Table 32 kHz Pin osc Multiplexing 64KB ROM 22 22 Switched Central Resource SCR 12 12 22 22 22 Peripherals DMA Audio Ports Serial Interfaces Display Video Parallel Port Internal Memory Customizable Interfa EDMA3 McASP McBSP SPI UART LCD VPIF uPP 128KB PRU Subsystem x2 wiFIFO x2 x2 x2 x3 RAM Control Timers Connectivity External Memory Interfaces PWM USB2 0
16. 2 4 Temperature Specifications Parameter Min Typical Max Unit Notes Commercial Operating Temperature 0 25 70 Industrial Operating Temperature 40 25 85 C ES Storage Temperature CAUTION Systems using the SATA interface on the AM1808 SOM M1 may require additional heat dissipation techniques in order to comply with the high end of the system temperature limitation It is the responsibility of the engineer to ensure the AM1808 SOM M1 maintains a safe operating temperature within the system PN 1015746A Logic PD Inc All Rights Reserved 6 AM1808 SOM M1 Hardware Specification 3 Electrical Specification 3 1 Absolute Power Maximum Ratings Parameter Symbol Rating DC 5 V Supply Voltage 5V sv 7 00072 DC Main Battery Input Voltage MAIN IN 0 0107 0 RTC Backup Battery Voltage 0 0 to 7 0 NOTE These siress ratings are only for transient conditions Operation at or beyond absolute maximum rating conditions may affect reliability and cause permanent damage to the SOM and its components 3 2 Recommended Power Operating Conditions Parameter f mn DC Main Battery Input Voltage 3 6 5 0 50 3 3 Pas 42 4 5 DC RTC Backup Battery Voltage 3 6 8 so aa VREF 2 40 3 3V Output Signal High Voltage VREF 0 45 1 8V VREF 0 40 3 3V Output Signal Low Voltage GND 0
17. 7 7 2 J2 Connector 100 Pin 23 7 3 J3 Connector 100 Pin 27 Appendix A SOM M1 Mechanical Drawing rasavrnnnavnnnnvvnnnvvnnnnvnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnn 31 Appendix B Example SOM M1 Retention Methods rssvrnnnvvnnnnvnnnnnnnnnnnnnnnvnnnnnvnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnennn 33 PN 1015746A Logic PD Inc All Rights Reserved iv AM1808 SOM M1 Hardware Specification Table of Figures Figure 2 1 AM1808 Processor Block 4 Figure 2 2 AM1808 SOM M1 Block 3 5 PN 1015746A Logic PD Inc All Rights Reserved 1 1 1 2 AM1808 SOM M1 Hardware Specification Introduction Product Overview The AM1808 System on Module SOM is a compact product ready hardware and software solution that fast forwards embedded designs while reducing risk and controlling cost Based on Texas Instruments AM1808 processor and designed in the SOM M1 form factor the AM1808 module offers essential features for handheld and embedded networking applications The AM1808 SOM M1 brings the industry leading low power ARM926 core to a small off the shelf solution The standard SOM M1 form factor allows developers to reuse existing baseboard designs when up
18. AXR7 EPWM 1TZ O 3 3V or 1 8V Note This signal is also connected to 6 uP EPWM 1 210 GP1 15 Hi Z see Note 1 J1 41 7 RFU NA Reserved for future use Do not connect 8 RFU PM I2C SCL NA Do not connect 9 RFU NA NA Reserved for future use Do not connect 10 RFU PM I2C SDA NA Do not connect 11 RFU NA Reserved for future use Do not connect Do not connect 3 3V or 1 8V Connected to J1 3 via zero ohm res on 12 BOOTBIT1 NA Note 1 SOM 13 RFU NA Reserved for future use Do not connect Do not connect 3 3V or 1 8V Connected to J1 7 via zero ohm res on 14 BOOTBIT3 NA Note 1 SOM 15 RFU NA Reserved for future use Do not connect 16 RFU NA Reserved for future use Do not connect Sense line for thermal resistor in battery 17 BATT TS 10 pack CLKOUT UHPI HDS2 3 3V or 1 8V 18 uP OBSCLK GPe 14 Hi Z see Note 1 22 ohm series R on SOM 19 DGND I GND Ground Connect to digital ground 20 DGND I GND Ground Connect to digital ground 21 RFU NA Reserved for future use Do not connect 22 RFU NA Reserved for future use Do not connect 23 RFU NA Reserved for future use Do not connect 24 RFU NA Reserved for future use Do not connect 25 RFU NA Reserved for future use Do not connect 26 RFU NA Reserved for future use Do not connect PN 1015746A Logic
19. ID USBO ID 5 or GND Also connects to TPS65070 PMIG 87 USB_VBUS USBO_VBUS 5 GND Note 4 88 USB_VBUS USBO_VBUS 5 or GND AHCLKX USB_REFCLKIN UART1_CTS 3 3V or 1 8V 89 uP_UART1_CTSn GPO 10 Hi Z see Note 1 22 ohm series on SOM 90 5V IN AHCLKR UART1_RTS 3 3V or 1 8V 91 uP_UART1_RTSn GPO 1 1 Hi Z see Note 1 22 ohm series on SOM 92 5V_IN 5 SCS 2 UART1 SATA CP POD 3 3V or 1 8V 93 uP SPI1 SCSn2 GP1 0 Note 1 94 DGND I GND Ground Connect to digital ground 5 SCS 3 UART1 RXD SATA LED 3 3V or 1 8V 95 uP_SPI1_SCSn3 GP1 1 Note 1 96 SVIN SPI1 SCS A UART2 TXD 3 3V or 1 8V 97 uP 5 SCSn4 I2C1 SDA GP1 2 Note 1 4 7k pull up on SOM 98 SVIN 5 SCS 5 UART2_RXD 3 3V or 1 8V 99 uP_SPI1_SCSn5 12 1 SCL GP1 3 Note 1 4 7k pull up on SOM 100 DGND GND Ground Connect to digital ground Note 1 Most AM1808 SOM M1 I O pins are dual voltage capable that is the SOM I O pins may be configured to operate at 3 3V or 1 8V The desired I O voltage is set via J1 37 See Section 5 5 2 for more information Note 2 At startup the boot mode is determined by sampling BOOT 0 7 i e LCD D 8 15 Resistors on the SOM pull these pins to a default value User boards may select alternate boot modes by pulling selected pins opposit
20. ING PREPARED IN ACCORDANCE WITH ASME Y14 5 2000 ALL DIMENSIONS ARE IN MILLIMETERS UNLESS OTHERWISE SPECIFIED TOLERANCES UNLESS OTHERWISE SPECIFIED 0 5 amp XX XX It I I I 0 2 0 1 1 THIRD ANGLE PROJECTION REV SOM M1 Retention SHEET 1 1 REVISIONS REV ECO NUMBER DESCRIPTION DATE A INITIAL RELEASE 10 28 09 B C029865 UPDATED SOM DESCRIPTION 08 17 10 NOTES 1 THE SOM M1 BE RETAINED IN PLACE BY THE SURROUNDING ENCLOSURE REPRESENTATIVE ENCLOSURE THIS DRAWING PREPARED IN ACCORDANCE WITH ASME Y14 5 2000 ALL DIMENSIONS ARE IN MILLIMETERS UNLESS OTHERWISE SPECIFIED TOLERANCES UNLESS OTHERWISE SPECIFIED x 0 5 X X 0 2 X XX 0 1 1 THIRD ANGLE PROJECTION oq TITLE REV It I I I SOM M1 Retention System A Housing B ENG DATE SIZE NWR 10 28 09 DATE KAG 10 28 09 LOGIC MGR TE DATE 411 N Washington Ave Suite 400 Minneapolis MN 55401 PMH 10 28 09 SCALE T 612 672 9495 F 612 672 9489 1 www logicpd com MANF DATE DWG NO SHEET 12 1014515 10F 1 8 7 6 5 4 ITEM DESCRIPTION VENDOR PART NUMBER Ei 1 REPRESENTATIVE PCB N A N A DEPENDENT ON SOM MI 5 2 5 1 LOGIC PD CONFIGURATION 3 STANDOFF M2 x 4MM PEM SMISO M2 4 4 CLIP RETENTION PLATE LOGIC PD LPD SOM CLIPI SCREW PAN HEAD M2 X AMM MCMASTER CAR
21. M1808 processor and resets the entire CPU IMPORTANT NOTE Any custom reset circuit design should guard the assertion of the reset lines during a low power state so as to prevent power up in a low or bad power condition Powering up in a low or bad power condition will cause data corruption and possibly temporary system lockup See the Power Management section of this document for further details A low pulse on the MSTR nRST signal will cause a system wide reset Low Pulse on MSTR nRST Signal A low pulse the MSTR nRST signal asserted by an external source for example the reset button on the custom design application will bring MSTR_nRST low until the assertion source is de asserted There is no delay beyond the de assertion of the external MSTR nRST signal source so the custom design must ensure that the assertion time is sufficient for all related peripherals Logic PD suggests that for any external assertion source that triggers the MSTR_nRST signal analog or digital de bouncing should be used to generate a clean one shot reset signal SOM Reset RESETOUTn Reset output All hardware peripherals should connect their hardware reset pin to the RESETOUTn signal on the expansion connector Internally all AM1808 SOM M1 peripheral hardware reset pins are connected to the RESET nOUT net If the output of the onboard voltage monitoring circuit is asserted active low the user can expect to lose information stored in RAM Th
22. OUCH X2 VO Processor reads via 2 EMA A 17 MMCSDO DAT 4 3 3V or 1 8V 71 uP A17 GP4 1 Hi Z see Note 1 Input to TPS65070 PMIC not AM1808 Touch Up Y 72 TOUCH Y1 Processor reads via I2C EMA A 16 MMCSDO DAT 5 3 3V or 1 8V 73 uP A16 GP4 0 Hi Z see Note 1 Input to TPS65070 PMIG not AM1808 Touch Down Y 74 TOUCH Y2 Processor reads via I2C EMA A 22 MMCSDO CMD 3 3V or 1 8V 75 uP A22 GP4 6 Hi Z see Note 1 MMCSD1 CMD uP UPP CHO ENAB UPP CHB ENAB 3 3V or 1 8V 76 LE LE GP8 13 Hi Z see Note 1 EMA A 23 MMCSDO CLK 3 3V or 1 8V 77 uP A23 GP4 7 Hi Z see Note 1 MMCSD1_CLK uP UPP CHO STAR UPP CHB STAR 3 3V or 1 8V 78 T T GP8 14 Hi Z see Note 1 79 DGND I GND Ground Connect to digital ground 80 DGND GND Ground Connect to digital ground 24 9 ohm series R on SOM 81 uP USB1 DM USB1 DM l O see Note 3 15k pull down on SOM 82 uP USBO DM USBO DM Note 3 PN 1015746A Logic PD Inc All Rights Reserved 21 AM1808 SOM M1 Hardware Specification J1 Pin SOM Net Name Processor Name I O Voltage Description 24 9 ohm series R on SOM 83 uP_USB1_DP USB1_DP see Note 3 15k pull down on SOM 84 uP USBO DP USBO DP see Note 85 RFU NA Reserved for future use Do not connect 86 uP USBO
23. PD Inc All Rights Reserved 27 AM1808 SOM M1 Hardware Specification J3 Pin SOM Net Name Processor Name I O Description SPIO SCS O TM64P1 OUT12 MDIO bus is used to communicate GP1 6 MDIO D 3 3V or 1 8V between AM1808 and LAN8710 Ethernet 27 uP SPIO SCSnO TM64P1 IN12 see Note 1 SOM 28 RFU NA Reserved for future use Do not connect SPIO SCS 1 TM64P0 OUT12 GP1 7 MDIO bus is used to communicate MDIO CLK 3 3V or 1 8 between AM1808 and LAN8710 Ethernet 29 uP SPIO SCSn1 TM64PO IN12 Note 1 on SOM 30 RFU NA NA Reserved for future use Do not connect VP DIN 7 HD 15 UPP CHA D 15 3 3V or 1 8V 31 uP_VPIF_DIN7 RMII TXD 1 Hi Z see Note 1 32 RFU NA Reserved for future use Do not connect VP DIN 5 UHPI HD 13 UPP CHA D 13 3 3V or 1 8V 33 uP VPIF DIN5 RMII TXEN Hi Z see Note 1 34 RFU NA Reserved for future use Do not connect VP DIN 6 UHPI HD 14 UPP CHA D 14 RMII TXD 3 3V or 1 8V 35 uP VPIF DING 0 Hi Z see Note 1 SPI1 SCS O EPWM1B GP2 14 3 3V or 1 8V 36 uP 5 5 0 TM64P3 IN12 Note 1 4 7k pull up on SOM VP DIN 2 HD 10 UPP CHA D 10 3 3V or 1 8V 37 uP RMII RXER Hi Z see Note 1 38 RFU NA NA Reserved for future use Do not connect VP DIN O UHPI HD 8 UPP CHA 0
24. PD Sales about custom configurations if your design requires different memory densities from Logic PD s standard SOM configurations product sales logicpd com 10 100 Ethernet PHY The AM1808 SOM M1 uses an SMSC LAN8710 Ethernet PHY to provide an easy to use networking interface The four analog PHY interface signals transmit receive each require an external impedance matching circuit to operate properly Logic PD provides an example circuit PN 1015746A Logic PD Inc All Rights Reserved 8 4 4 4 5 4 5 1 4 5 2 4 5 3 AM1808 SOM M1 Hardware Specification schematic in the AM1808 Baseboard Schematics Please note the TX and RX pairs must be routed as differential pairs on the baseboard PCB Display Interface The AM1808 has a built in LCD controller supporting both synchronous raster type and asynchronous memory mapped panels The synchronous raster module supports STN color STN and TFT panels at a resolution of up to 1024 x 1024 x 16 bit color The asynchronous memory mapped module supports a broad range of displays from monochrome character displays to TFT smart LCD panels Displays driven by this module must contain their own memory and timing circuitry The signals from the AM1808 LCD controller can be interfaced through the expansion connectors See Tl s AM1808 ARM Microprocessor Datasheet for further information on the integrated LCD controller IMPORTANT NOTE Using the internal graphics controll
25. R 92000A011 THERMAL PAD 009 THICK 6 LOGIC PD LPD SOM CLIP1 THPAD NOTES 1 THIS IS THE RECOMMENDED RETENTION METHOD IF USING THE LOGIC PD RETENTION CLIP 2 THERMAL PAD IS DIE CUT TO FIT RETENTION CLIP 3 DO NOT PLACE COMPONENTS WITHIN LAYOUT AREA OF SOM AND CLIP BASEBOARD CONNECTOR SPECIFICATION 4 HIROSE DFAOC 100DS 0 4V 5 DO NOT SCALE DRAWING B ENG DATE NWR 08 16 10 CHECK DATE KAG 08 16 10 MGR DATE PMH 08 16 10 MANF DATE 4 3 2 1 REVISIONS REV ECO NUMBER DESCRIPTION DATE A C029865 INITIAL RELEASE 08 16 10 LOGIC 411 Washington Ave Suite 400 Minneapolis MN 55401 T 612 672 9495 F 612 672 9489 1 www logicpd com 3 H N m SCALE 12 TITLE SOM MI CLIP RETENTION SYSTEM DWG NO 1016203 D C B THIS DRAWING PREPARED IN ACCORDANCE WITH ASME Y14 5 2000 ALL DIMENSIONS ARE IN MILLIMETERS UNLESS OTHERWISE SPECIFIED TOLERANCES UNLESS OTHERWISE SPECIFIED X 0 5 X X 0 2 X XX 0 1 x 1 A SHEET 1 OF 2 53 7 WITH 5 6 2 SOLDER PAD REQUIRED PLATING THRU HOLE NOT REQUIRED PIN LOCATIONS RECOMMENDED BASEBOARD FOOTPRINT SIZE TITLE REV a SOM MI CLIP B RETENTION SYSTEM SCALE DWG NO SHEET 2 1 1016203 2 2
26. Reserved 29 AM1808 SOM M1 Hardware Specification J3 Pin SOM Net Name Processor Name I O Description 74 RFU NA NA Reserved for future use Do not connect 75 RFU NA NA Reserved for future use Do not connect 76 RFU NA NA Reserved for future use Do not connect 77 RFU NA NA Reserved for future use Do not connect 78 RFU NA NA Reserved for future use Do not connect 79 DGND I GND Ground Connect to digital ground 80 DGND GND Ground Connect to digital ground 81 RFU NA NA Reserved for future use Do not connect 3 3V or 1 8V 82 uP TCK TCK I Note 1 83 RFU NA NA Reserved for future use Do not connect 3 3V or 1 8V 84 uP RTCK RTCK GP8 0 Note 1 85 RFU NA NA Reserved for future use Do not connect 3 3V or 1 8V 86 uP_EMU1 EMU1 Note 1 4 7k pull up on SOM 87 RFU NA NA Reserved for future use Do not connect 3 3V 1 8V 88 uP EMUO EMUO Note 1 4 7k pull up on SOM 89 RFU NA NA Reserved for future use Do not connect 3 3V or 1 8V 90 uP_TDO TDO Note 1 91 RFU NA NA Reserved for future use Do not connect 3 3V or 1 8V 92 uP TDI TDI see Note 1 93 RFU NA NA Reserved for future use Do not connect 3 3V or 1 8V 94 uP TMS TMS I Note 1 95 RFU NA NA Reserve
27. SOM M1 Schematics for more details Logic PD has experience implementing additional options including audio codecs Ethernet ICs PN 1015746A Logic PD Inc All Rights Reserved 10 AM1808 SOM M1 Hardware Specification co processors and components on SOMs Please contact Logic PD for potential reference designs before selecting your peripherals PN 1015746A Logic PD Inc All Rights Reserved 11 5 1 5 2 5 2 1 5 2 2 AM1808 SOM M1 Hardware Specification System Integration Custom Configuration The AM1808 SOM M1 was designed to meet multiple applications for users with specific design and budget requirements As a result this SOM supports a variety of embedded operating systems flexible mDDR and SPI flash memory footprints and other hardware configurations If your application needs require unique hardware or software configurations please contact Logic PD Sales about custom SOMs available in production volumes product sales logicpd com Resets The AM1808 SOM M1 has a reset input MSTR nRST and a reset output RESETOUTn External devices use MSTR_nRST to assert reset to the product The AM1808 SOM M1 uses RESETOUTn to indicate to other devices that the SOM is in reset Master Reset MSTR nRST Reset Input Logic PD suggests that custom designs implementing the AM1808 SOM M1 use the MSTR nRST signal as the pin hole reset used in commercial embedded systems The MSTR nRST triggers a power on reset event to the A
28. Section 5 5 1 3 Buffered version of this input can be read 33 PB IN 10 on AM1808 pin RAS GPIO2 5 DIN 12 UHPI HD 4 3 3V or 1 8V 34 uP VPIF DIN12 UPP CHA 0141 Hi Z see Note 1 35 RFU NA NA Reserved for future use Do not connect DIN 11 UHPI HD 3 3 3V or 1 8V 36 uP_VPIF_DIN11 UPP D 3 Hi Z see Note 1 Input to TPS65070 PMIG not AM1808 37 IO VOLTAGE SEL See Section 5 5 2 VP DIN 10 UHPI_HD 2 3 3V or 1 8V 38 uP_VPIF_DIN10 UPP Df 2 Hi Z see Note 1 AXR15 EPWMOTZIO 4 7k pull up on SOM ECAP2 APWM 2 3 3V or 1 8V This signal is also connected to 39 uP EPWMO 210 GPO 7 Hi Z see Note 1 1J2 99 VP DIN 9 UHPI HD 1 UPP CHA 3 3V or 1 8V 40 uP_VPIF_DIN9 D 1 Hi Z see Note 1 AXR7 EPWM1TZ 0 3 3V or 1 8V 41 uP EPWM1 TZ 0 GP1 15 Hi Z see Note 1 Note This signal is also connected to J3 6 VP DIN 8 UHPI HD O UPP CHA _ 3 3V or 1 8V 42 uP DIN8 D O GP6 5 Hi Z see Note 1 PN 1015746A Logic PD Inc All Rights Reserved 19 AM1808 SOM M1 Hardware Specification J1 Pin SOM Net Name Processor Name I O Voltage Description 43 SATA RXP SATA RXP I SPIO_SCS 4 MII bus is used to communicate between UARTO TXD the AM1808 processor and LAN8710 GP8 3 3 3V 1 8V Ethernet PHY on the SOM 44 uP SPIO SCSn4 RXD 2
29. V 59 uP 21 GP4 5 Hi Z see Note 1 MMCSD1 DAT 0 UPP CHB CLK 3 3V or 1 8V 60 uP UPP CHO GP8 15 Hi Z see Note 1 22 ohm series R on SOM EMA A 20 MMCSDO DAT 1 3 3V or 1 8V 61 uP EMIFA A20 GP4 4 Hi Z see Note 1 VP CLKIN3 MMCSD1 DAT 1 3 3V or 1 8V 62 uP_VPIF_CLKIN3 GP6 2 Hi Z see Note 1 1015746 Logic PD Inc Rights Reserved 20 AM1808 SOM M1 Hardware Specification J1 Pin SOM Net Name Processor Name I O Voltage Description EMA A 19 MMCSDO DAT 2 3 3V or 1 8V 63 uP A19 GP4 3 Hi Z see Note 1 VP_CLKOUT2 MMCSD1_DAT2 3 3V or 1 8V 64 uP_VPIF_CLKO2 GP6 3 Hi Z see Note 1 22 ohm series R on SOM Voltage Output from SOM Do not use 3 3V or 1 8V this as a general purpose power source 65 3 3V or 1 8V Note 1 Use this pin to power level shifters etc VP CLKIN2 MMCSD1 DAT 3 3 3V or 1 8V 66 uP_VPIF_CLKIN2 GP6 4 Hi Z see Note 1 I O Voltage Output from SOM Do not use 3 3V or 1 8V this as a general purpose power source 67 3 3V or 1 8V Note 1 Use this pin to power level shifters etc Input to TPS65070 PMIC not AM1808 Touch Right X 68 TOUCH X1 VO Processor reads via I2C A 18 MMCSDO DAT 3 3 3V or 1 8V 69 uP EMIFA A18 GP4 2 Hi Z see Note 1 Input to TPS65070 PMIC not AM1808 Touch Left X 70 T
30. Z see Note 1 22 ohm series on SOM MII bus is used to communicate between SPIO SOMI the AM1808 processor and LAN8710 EPWMSYNCI 3 3V or 1 8V Ethernet PHY on the SOM 83 uP_SPIO_SOMI GP8 6 RXER Note 1 4 7 pull down on SOM AXR11 FSX1 3 3V or 1 8V 84 uP MCBSP1 FSX 3 Hi Z see Note 1 SPIO SIMO MII bus is used to communicate between EPWMSYNCO 3 3V or 1 8V AM1808 processor LAN8710 85 uP SPIO SIMO GP8 5 I Note 1 Ethernet PHY on the SOM AXR9 DX1 3 3V or 1 8V 86 uP MCBSP1 DX GPO 1 Hi Z see Note 1 87 RFU NA NA Reserved for future use Do not connect AXR10 DR1 3 3V or 1 8V 88 uP MCBSP1 DR GPO 2 Hi Z see Note 1 89 RFU NA NA Reserved for future use Do not connect AXR14 CLKR1 3 3V or 1 8V 90 uP MCBSP1 CLKR GPO 6 Hi Z see Note 1 22 ohm series R on SOM BA O 3 3V or 1 8V 91 uP EMIFA BAO GP2 8 Hi Z see Note 1 1k pull down on SOM AXR8 CLKS1 1 1 3 3V or 1 8V 92 uP MCBSP1 CLKS GPO 0 Hi Z see Note 1 22 ohm series R on SOM EMA BA 1 3 3V or 1 8V 93 uP EMIFA BA1 GP2 9 Hi Z see Note 1 AXR12 FSR1 3 3V or 1 8V 94 uP MCBSP1 FSR GPO 4 Hi Z see Note 1 SPIO ENA MII bus is used to communicate between EPWMOB 3 3V or 1 8V the AM1808 processor and LAN8710 95 uP SPIO ENAn RXDV see Note 1 Ethernet PHY on the SOM CLK 3 3V or 1 8V 22 ohm series R on SOM 96 uP CLK GP2 13 Note
31. atic for further details Each JTAG tool vendor may define the IDC connector pin out differently Power Management System Power Supplies In order to ensure a flexible design the AM1808 SOM M1 has the following power areas MAIN BATT IN 5V RTC_BATT All power areas are inputs to the SOM The module also provides output reference voltage 3 3V 1 8V 3 3V or 1 8V is an output from the SOM and should only be used as a reference voltage input to level shifting devices on baseboard designs IMPORTANT NOTE If USBO VBUS is powered externally it will power the SOM even if MAIN BATT IN and 5V are disconnected Additionally USBO VBUS can charge MAIN Please refer to the 7565070 Datasheet for more information 5V The 5V input is the main source of power for the AM1808 SOM M1 If power is present at the 5V input the TPS65070 PMIC will preferentially select this power source over all other sources If appropriate voltage is applied to the 5V input the TPS65070 PMIC and AM1808 processor will immediately start up and run 5V input is capable of charging MAIN_BATT_IN For startup acceptable 5V input range is 3 6V lt input lt 5 8V At runtime 5V range is UVLO 5V input 5 8V UVLO UnderVoltage LockOut UVLO 3 0V default 2 8V UVLO 3 25V programmable USBO VBUS USBO VBUS is an optional power source for the AM1808 SOM M1 If power is present at the USBO VBUS input the TPS65070 PMIC will preferential
32. ch powers the AM1808 SOM M1 from MAIN BATT IN the user should first review the following documents TPS65070 Datasheet AM1808 SOM M1 Schematic and AM1808 Baseboard Schematic VRTC IN VRTC IN power rail is used to power the onboard RTC module Always power this rail to maintain the clock of the product A lithium ion coin cell typically supplies power to this rail Dual Voltage I O The AM1808 processor and AM1808 SOM M1 uniquely support dual voltage I O The user may select an operating voltage of either 1 8V or 3 3V through IO VOLTAGE SEL J1 37 For 3 3V operation J1 37 should be left unconnected For 1 8V operation J1 37 should be tied directly to GND System Power Management Good power management design is important in any system development and embedded system design is no exception In embedded system design power management is typically one of the most complicated areas due to the dramatic effect it has on product cost performance usability and overall customer satisfaction Many factors affect a power efficient hardware design power supply selection efficiency clocking design IC and component selection etc The AM1808 SOM M1 was designed with these aspects in mind while also providing maximum flexibility in software and system integration On the AM1808 there are many different software configurations that drastically affect power consumption microprocessor core clock frequency bus clock frequency peripheral c
33. d for future use Do not connect 3 3V or 1 8V 96 uP TRSTn TRST see Note 1 97 RFU NA NA Reserved for future use Do not connect 98 RFU NA NA Reserved for future use Do not connect 99 RFU NA NA Reserved for future use Do not connect 100 RFU NA NA Reserved for future use Do not connect Note 1 Most AM1808 SOM M1 I O pins are dual voltage capable that is the SOM I O pins may be configured to operate at 3 3V or 1 8V The desired I O voltage is set via J1 37 See Section 5 5 2 for more information PN 1015746A Logic PD Inc All Rights Reserved 30 8 7 6 5 Appendix SOM M1 Mechanical Drawing 40 0 REF REVISIONS DESCRIPTION INITIAL ENGINEERING RELEASE UPDATED CONNECTOR LABELS ADDED PIN LOCATIONS DATE 8 18 09 10 23 09 08 17 10 gt 2 ECO NUMBER 06955 029865 a e DO NOT PLACE ANY COMPONENTS WITHIN LAYOUT AREA OF SOM BASEBOARD CONNECTOR SPECIFICATION HIROSE DF40C 100DS 0 4V MACHINE PLACEMENT OF J1 J2 AND J3 IS HIGHLY RECOMMENDED ALL ALIGNED COMPONENTS TO BE WITHIN 075 DO NOT SCALE DRAWING 30 0 REF
34. e data loss occurs because the CPU is reset to its reset defaults PN 1015746A Logic PD Inc All Rights Reserved 12 5 3 5 4 5 5 5 5 1 5 5 1 1 5 5 1 2 AM1808 SOM M1 Hardware Specification Interrupts The AM1808 interrupt controller allows the ARM core to enable disable trigger or service all interrupts Most external GPIO signals can also be configured as interrupt inputs by configuring their pin control registers Logic PD BSPs setup and process all onboard system and external SOM interrupt sources Refer to Tl s AM1808 ARM Microprocessor Datasheet and User Guides for further information on using interrupts JTAG Debugger Interface The JTAG connection on the AM1808 allows recovery of corrupted flash memory real time application debug and ARM core development There are several third party JTAG debuggers available for TI microprocessors The following signals make up the JTAG interface to the 1808 processor TDI TMS nTRST RTCK EMUO EMU1 and MSTR nRST MSTR nRST is only required for some JTAG tools see the JTAG tool documentation for exact pinout These signals should interface directly to a 14 or 20 pin 0 1 through hole connector as shown on Logic PD s AM1808 Baseboard Schematic IMPORTANT NOTE When laying out the JTAG connector realize that it may not be numbered as a standard 14 or 20 pin 0 1 insulation displacement connector IDC through hole connector See the AM1808 Baseboard Schem
35. e their default value to do this the user s board must use resistors of much lower impedance than those used on the SOM User boards must ensure that other circuits do not drive or load down these pins at startup Driving loading these pins at startup may cause the processor to latch an incorrect boot mode For compatibility with the SOM M1 form factor BOOT 1 4 LCD D 9 10 11 12 or J1 3 5 7 9 are connected to BOOTBIT 1 4 J3 2 4 12 14 through zero ohm resistors Note 3 USB voltage levels follow the USB specification and depend on the USB operating speed Please see the USB specification for more information PN 1015746A Logic PD Inc All Rights Reserved 22 Note 4 USBO_VBUS can be used to power the SOM Please see the TPS65070 Datasheet for more information AM1808 SOM M1 Hardware Specification 7 2 J2 Connector 100 Pin Descriptions J2 Pin SOM Net Name Processor Name I O Voltage Description D 7 3 3V or 1 8V 1 uP EMIFA D7 GP4 15 Hi Z see Note 1 2 RFU NA NA Reserved for future use Do not connect 3 3V or 1 8V 3 uP_EMIFA_D8 0 8 GP3 0 Hi Z Note 1 EMA WAIT 1 3 3V or 1 8V 4 uP WAIT1 GP2 1 Hi Z see Note 1 4 7k pull up on SOM 3 3V or 1 8V 5 uP EMIFA D9 0 9 GP3 1 Hi Z Note 1 EMA WAIT O 3 3V or 1 8V 6 uP WAITO GP3 8 Hi Z see Note 1 4 7k
36. er will affect processor performance Selecting display resolutions and color bits per pixel will vary processor busload Serial Interfaces The AM1808 SOM M1 comes with the following serial channels UARTO 2 SPIO 1 12 0 1 McBSP0 1 and McASP If additional serial channels are required please contact Logic PD for reference designs Please see Tl s AM1808 User Guides for further information regarding serial communications UARTO 2 The AM1808 SOM M1 provides three UART ports UARTO UART1 and UART2 are asynchronous 16C550 compatible UARTs These UARTS are high speed serial interfaces that use 16 byte TX and RX FIFO registers they are capable of sending and receiving serial data simultaneously The signals from the SOM are not RS232 level signals The end product design must provide an external transceiver for RS232 applications Logic PD has provided an example reference design with the Zoom AM1808 Development Kits When choosing an RS232 transceiver the designer should keep in mind cost availability ESD protection and data rates 2 has been configured as the main SOM serial port The UART2 baud rate is set toa default 115 2 Kbits sec though it supports most common serial baud rates SPIO 1 The AM1808 SOM M1 provides two SPI ports with multiple chip selects SPI1 is the default boot source for the AM1808 SOM M1 A serial flash chip is attached to SPI1 CSO 12 0 1 The 1808 SOM M1 provides two 12 ports The clock a
37. erty Except as expressly provided in any written license or agreement from Logic PD Inc this document and the information contained therein does not create any license to Logic PD s Intellectual Property The Information contained herein is subject to change without notice Revisions may be issued regarding changes and or additions Copyright 2011 Logic PD Inc All Rights Reserved PN 1015746A Logic PD Inc All Rights Reserved i AM1808 SOM M1 Hardware Specification Revision History Schematic REV EDITOR REVISION DESCRIPTION PN amp REV APPROVAL DATE 1015138 Rev A 1 JCA Initial release 1015640 Rev A 04 20 10 1015138 Rev 2 JCA Added Appendix A and B containing mechanical drawings 1015640 Rev A 09 23 10 Section 2 4 Added Industrial temperature range Added Caution 1015138 Rev A 3 JCA about system temperatures when enabling SATA 1015640 RevA JCA 11 05 10 Section 1 5 Updated link for Logic PD hardware design files Section 7 1 Updated J1 31 description since this signal is no longer connected to the PMIC Updated J1 39 54 descriptions to add resistor value Section 7 2 Updated J2 91 97 amp 99 descriptions to add resistor value uP EPWMO TZ 0 is now connected to J2 99 Section 7 3 Added resistor value to J3 54 description 1015115 Rev C A SMC JCA uP SCSn0 is now connected to J3 36 1015774 RevB JCA 05 04 11 Please check www logicpd com fo
38. grading to new Sitara processors which extends roadmap possibilities for their end product Two Zoom Development Kit options allow developers to choose the platform best suited to their application needs By starting with the corresponding Zoom Development Kit engineers can write application software on the same hardware that will be used in their final product The compact size of the AM1808 SOM M1 is ideal for medical patient monitoring wearables and other portable instrumentation applications the built in Serial ATA SATA controller provides fast access to large capacity storage devices For medical industrial audio and communication products the AM1808 SOM M1 allows for powerful versatility long life and greener products Abbreviations Acronyms amp Definitions ADC Analog to Digital Converter BOM Bill of Materials BSP Board Support Package BTB Board to Board DAC Digital to Analog Converter DMA Direct Memory Access EDMA Enhanced Direct Memory Access EMIFA External Memory Interface ESD Electrostatic Discharge FIFO First In First Out HPI Host Port Interface GPIO General Purpose Input Output GPMC General Purpose Memory Controller Hi Z High Impedance 12 Inter Integrated Circuit 125 Inter Integrated Circuit Sound IC Integrated Circuit Input Output IRQ Interrupt Request LCD Liquid Crystal Display LDO Low Dropout Regulator McASP Multi channel Audio Serial Port McBSP Multi channel Buffered Serial Por
39. he AM1808 processor and LAN8710 72 uP MCBSPO DR TXD 2 Note 1 Ethernet PHY on the SOM 73 ETHER TX 49 9 ohm pull up on SOM AXR1 0 MII bus is used to communicate between GP1 19 3 3V or 1 8V the AM1808 processor and LAN8710 74 uP MCBSPO DX TXD 1 Note 1 Ethernet PHY on the SOM 75 ETHER RX 49 9 ohm pull up on SOM MII bus is used to communicate between the AM1808 processor and LAN8710 AXR4 FSRO 3 3V or 1 8V Ethernet PHY on the SOM 76 uP MCBSPO FSR GP1 12 MII_COL Note 1 4 7 pull up on SOM 77 ETHER_RX 49 9 ohm pull up on SOM PN 1015746A Logic PD Inc All Rights Reserved 25 AM1808 SOM M1 Hardware Specification J2 Pin SOM Net Name Processor Name I O Voltage Description MII bus is used to communicate between AXR5 the AM1808 processor and LAN8710 GP1 13 3 3V or 1 8V Ethernet PHY on the SOM 78 uP MCBSPO CLKX TXCLK I Note 1 22 ohm series on SOM 79 DGND I GND Ground Connect to digital ground 80 DGND GND Ground Connect to digital ground MII bus is used to communicate between the AM1808 processor and LAN8710 SPIO CLK Ethernet PHY on the SOM EPWMOA GP1 8 3 3V or 1 8V 22 ohm series R on SOM 81 uP SPIO CLK MIL RXCLK I Note 1 4 7 pull down on SOM AXR13 CLKX1 3 3V or 1 8V 82 uP MCBSP1 CLKX GPO 5 Hi
40. i Z see Note 1 22 ohm series R on SOM RESETOUT HAS 3 3V or 1 8V 54 uP RESETOUTn GP6 15 Hi Z see Note 1 4 7k pull up on SOM 3 3V or 1 8V 55 uP McASP CLKR A ACLKR GPO 15 Hi Z see Note 1 22 ohm series on SOM UHPI HRW UPP CH1 WAIT 3 3V or 1 8V 56 uP UPP CH1 WAIT GP6 8 Hi Z see Note 1 3 3V or 1 8V 57 uP McASP FSX AFX GPO 12 Hi Z see Note 1 UHPI HRDY GP6 3 3V or 1 8V 58 uP UHPI HRDY 13 Hi Z see Note 1 3 3V or 1 8V 59 uP McASP FSR AFSR GPO 13 Hi Z see Note 1 UHPI HINT GPe 1 3 3V or 1 8V 60 uP UHPI HINTn 2 Hi Z see Note 1 EMA SDCKE 3 3V or 1 8V 61 BUFF OEn GP2 6 Hi Z see Note 1 1k pull down on SOM UPP CHB WAIT 3 3V or 1 8V 62 uP UPP CHO WAIT GP8 12 Hi Z see Note 1 63 RFU NA NA Reserved for future use Do not connect 64 RFU NA NA Reserved for future use Do not connect 3 3V or 1 8V 65 3 3V or 1 8V Note 1 66 RFU NA NA Reserved for future use Do not connect 3 3V or 1 8V 67 3 3V or 1 8V Note 1 68 RFU NA NA Reserved for future use Do not connect 69 RFU NA NA Reserved for future use Do not connect 70 RFU NA NA Reserved for future use Do not connect 71 RFU NA NA Reserved for future use Do not connect 72 RFU NA NA Reserved for future use Do not connect 73 RFU NA NA Reserved for future use Do not connect PN 1015746A Logic PD Inc All Rights
41. ification J2 Pin SOM Net Name Processor Name I O Voltage Description CS 3 3 3V or 1 8V 26 uP CSn3 GP3 14 Hi Z see Note 1 3 3V or 1 8V 27 uP EMIFA A3 A 3 GP5 3 Hi Z see Note 1 _ 2 3 3V or 1 8V 28 uP_EMIFA_CSn2 GP3 15 Hi Z see Note 1 3 3V or 1 8V 29 uP EMIFA A4 A 4 GP5 4 Hi Z see Note 1 30 RFU NA NA Reserved for future use Do not connect 3 3V or 1 8V 31 uP_EMIFA_A5 A 5 GP5 5 Hi Z see Note 1 _ 0 3 3V or 1 8V 32 uP_EMIFA_CSn0 GP2 0 Hi Z see Note 1 3 3V or 1 8V 33 uP EMIFA A6 A 6 GP5 6 Hi Z see Note 1 3 3V or 1 8V 34 uP EMIFA DO EMA_D 0 GP4 8 Hi Z see Note 1 3 3V or 1 8V 35 uP A7 7 GP5 7 Hi Z see Note 1 3 3V or 1 8V 36 uP_EMIFA_D1 EMA D 1 GP4 9 Hi Z see Note 1 3 3V or 1 8V 37 uP EMIFA A8 A 8 GP5 8 Hi Z see Note 1 EMA D 2 3 3V or 1 8V 38 uP 02 GP4 10 Hi Z see Note 1 3 3V or 1 8V 39 uP EMIFA A9 A 9 GP5 9 Hi Z see Note 1 D S 3 3V or 1 8V 40 uP EMIFA D3 4 11 Hi Z see Note 1 A 10 3 3V or 1 8V 41 uP_EMIFA_A10 GP5 10 Hi Z see Note 1 D 4 3 3V or 1 8V 42 uP_EMIFA_D4 GP4 12 Hi Z see Note 1 EMA A 11 3 3V or 1 8V 43 uP EMIFA A11 GP5 11 Hi Z see Note 1
42. igured as either input or output Consult Logic PD s AM1808 SOM M1 Schematics and TI s AM1808 ARM Microprocessor Datasheet for more information Description If a pull up or pull down resistor is present on the AM1808 SOM M1 it will be noted here Special usage tips and cautions will be noted here Consult Logic PD s AM1808 SOM M1 Schematics and AM1808 ARM Microprocessor Datasheet for more information 7 1 J1 Connector 100 Pin Descriptions J1 Pin SOM Net Name Processor Name I O Voltage Description LCD data bit when outputting RGB565 VP DOUT S data to an RGB666 display LCD 0 8 4 7k pull down on SOM UPP XD O 3 3V or 1 8V Used to latch boot mode at startup see 1 uP VPIF DOUT8 7 0 BOOT 0 Hi Z see Note 1 Note 2 VP DOUT O LCD D O UPP XD 8 3 3V or 1 8V LCD B1 data bit when outputting RGB565 2 uP VPIF DOUTO GP7 8 Hi Z see Note 1 data to an RGB666 display LCD G4 data bit when outputting RGB565 VP DOUT 9 data to an RGB666 display LCD_D 9 4 7k pull down on SOM UPP XD 1 3 3V or 1 8V Used to latch boot mode at startup see 3 uP VPIF DOUT9 GP7 1 BOOT 1 Hi Z see Note 1 Note 2 VP DOUTT 1 LCD UPP XD 9 3 3V or 1 8V LCD B2 data bit when outputting RGB565 4 uP VPIF DOUT1 GP7 9 Hi Z see Note 1 data to an RGB666 display LCD G5 data bit when outputting RGB565 VP DOUT 10 data to an RGB666 display LCD D 10 4 7k pull up on SOM UPP XD 2 3 3V or 1 8V Used to latch boot mode at startup
43. locks bus PN 1015746A Logic PD Inc All Rights Reserved 14 5 5 4 5 6 AM1808 SOM M1 Hardware Specification modes power management states peripheral power states and modes product user scenarios interrupt handling and display settings resolution backlight refresh bits per pixel etc These settings are typically initialized in the startup software routines and may be modified later in the operating system and application software Information for these items can be found in the appropriate documents such as the U Boot User s Manual T s AM1808 ARM Microprocessor Datasheet and User Guides TPS65070 Datasheet and Logic PD s AM1808 SOM M1 Schematic Microprocessor The AM1808 processor s power management scheme was designed for ultra low power so naturally the static and dynamic power consumption has very flexible controls allowing designers to configure the processor to minimize end product power consumption Most peripheral modules can be powered on off individually and the core s can enter various levels of standby sleep To implement a low power system users should review AM1808 ARM Microprocessor Datasheet and User Guides TPS65070 Datasheet and Logic PD s AM1808 SOM M1 Schematic ESD Considerations The AM1808 SOM M1 was designed to interface to a customer s peripheral board while remaining low cost and adaptable to many different applications The SOM does not provide any onboard ESD protection circuitr
44. ly select this source over PN 1015746A Logic PD Inc All Rights Reserved 13 5 5 1 3 5 5 1 4 5 5 2 5 5 3 AM1808 SOM M1 Hardware Specification MAIN IN If appropriate voltage is applied to the 0580 VBUS input the TPS65070 and AM1808 processor will immediately start up and run The USBO VBUS input is capable of charging MAIN BATT IN MAIN BATT IN The MAIN IN input is designed to be connected to a typical single lithium ion battery TPS65070 PMIC will only power the SOM from MAIN BATT IN if power is not present at 5V or USBO VBUS inputs If appropriate voltage is applied to the MAIN BATT IN input the TPS65070 PMIC and AM1808 processor will NOT immediately start up and run a momentary low signal is also required on the PMIC PB IN pin The TPS65070 PMIC is capable of charging MAIN BATT IN from either the 5V input or the USBO VBUS input For startup MAIN IN range is 3 6V lt MAIN lt 4 2V At runtime MAIN BATT IN range is UVLO MAIN BATT IN 4 2V UVLO UnderVoltage LockOut UVLO 3 0V default 2 8V UVLO 3 25V programmable IMPORTANT NOTES Though UVLO may be set as low as 2 8V not all AM1808 SOM M1 circuits are capable of 2 8V operation The SOM contains an internal 3 3V power rail and devices connected to this rail may have dropout voltages much greater than UVLO See Section 3 2 for the recommended range of input voltages Before designing a system whi
45. nd data signals for both ports have 4 7K pull up resistors to their respective power rails on the SOM Please see 5 AM1808 User Guides for further information PN 1015746A Logic PD Inc All Rights Reserved 9 4 5 4 4 5 5 4 6 4 7 4 8 4 9 AM1808 SOM M1 Hardware Specification 12 0 has been configured as the main SOM 12 port 12 0 is used to control configure many ICs on the SOM as well as the Zoom AM1808 Development Kits McBSP0 1 The AM1808 SOM M1 supports two Multi channel Buffered Serial Port McBSP interfaces These interfaces are primarily designed to support AC97 and IIS modes but they can also be configured for other serial formats However the McBSPs are not intended to be used as high speed interfaces McASPO The AM1808 SOM M1 supports one Multi channel Audio Serial Port McASP The McASP interface supports TDM streams I2S protocols and DIT Logic PD has provided an example reference design with the Zoom AM1808 Development Kits this reference design interfaces the AM1808 McASP to a TLV320AIC3106 audio codec USB Interface The AM1808 SOM M1 supports one USB 1 1 full speed host port and one USB 2 0 OTG port which can function as a host or device client The USB 2 0 port can operate at up to 480 Mbit sec and the USB 1 1 port can operate at up to 12 Mbit sec Both the USB 1 1 and USB 2 0 controllers are internal to the AM1808 processor For more information on using both the USB host and OTG inte
46. ound Connect to digital ground 20 DGND I GND Ground Connect to digital ground MMCSD1 DAT 4 LCD VSYNC 3 3V or 1 8V 21 uP LCD VSYNC GP8 8 Hi Z see Note 1 MMCSD1 DAT 6 LCD MCLK 3 3V or 1 8V 22 uP LCD MCLK GP8 10 Hi Z see Note 1 22 ohm series on SOM uP LCD AC C LCD 3 3V or 1 8 23 Sn S GP6 0 Hi Z see Note 1 PN 1015746A Logic PD Inc All Rights Reserved 18 AM1808 SOM M1 Hardware Specification J1 Pin SOM Net Name Processor Name I O Voltage Description VP_CLKINO UHPI_HCS GP6 7 3 3V or 1 8V 24 uP_VPIF_CLKINO UPP_2xTXCLK Hi Z see Note 1 25 uP USBO DRVVBUS USBO DRVVBUS O VP DIN 14 _ HSYNC UHPI HD 6 3 3V or 1 8V 26 uP VPIF DIN14 UPP CHA 0161 Hi Z see Note 1 VP CLKOUT3 3 3V or 1 8V 27 uP VPIF CLKO3 GPe 1 Hi Z see Note 1 22 ohm series R on SOM VP DIN 15 _ VSYNC UHPI_HD 7 3 3V or 1 8V 28 uP_VPIF_DIN15 UPP CHA D 7 Hi Z see Note 1 4 7k pull up on SOM 3 3V 1 8V Also connected to PGOOD on TPS65070 29 uP RESETn RESET I see Note 4 PGOOD is an open drain output 30 RFU NA NA Reserved for future use Do not connect 3 3V or 1 8V Reserved 4 7k pull up on SOM 31 uP NMIn RSVDN I see Note 1 DIN 13 _ FIELD UHPI HD 5 3 3V or 1 8V 32 uP_VPIF_DIN13 UPP CHA D 5 Hi Z see Note 1 Input to TPS65070 PMIC not AM1808 See
47. pull up on SOM EMA D 10 3 3V or 1 8V 7 uP 010 GP3 2 Hi Z see Note 1 8 RFU NA NA Reserved for future use Do not connect EMA D 11 3 3V or 1 8V 9 uP D11 GP3 3 Hi Z see Note 1 10 RFU NA NA Reserved for future use Do not connect EMA D 12 3 3V or 1 8V 11 uP 012 GP3 4 Hi Z see Note 1 EMA WE 3 3V or 1 8V 12 uP WEn GP3 11 Hi Z see Note 1 EMA D 13 3 3V or 1 8V 13 uP 013 GP3 5 Hi Z see Note 1 3 3V or 1 8V 14 uP EMIFA OEn OE GP3 10 Hi Z Note 1 EMA D 14 3 3V or 1 8V 15 uP 014 GP3 6 Hi Z see Note 1 A RW 3 3V or 1 8V 16 uP EMIFA RnW GP3 9 Hi Z see Note 1 4 7k pull up SOM D 15 3 3V or 1 8V 17 uP EMIFA D15 GP3 7 Hi Z see Note 1 3 3V or 1 8V 18 uP EMIFA CLK CLK GP2 7 Hi Z Note 1 19 DGND I GND Ground Connect to digital ground 20 DGND I GND Ground Connect to digital ground 3 3V or 1 8V 21 uP EMIFA 0 A 0 GP5 0 Hi Z Note 1 CS 5 3 3V or 1 8V 22 uP EMIFA CSn5 GP3 12 Hi Z see Note 1 3 3V or 1 8V 23 uP EMIFA A1 A 1 GP5 1 Hi Z Note 1 CS 4 3 3V or 1 8V 24 uP EMIFA CSn4 GP3 13 Hi Z see Note 1 3 3V or 1 8V 25 uP EMIFA A2 A 2 GP5 2 Hi Z Note 1 PN 1015746A Logic PD Inc All Rights Reserved 23 AM1808 SOM M1 Hardware Spec
48. r the latest revision of this document product change notifications and additional documentation PN 1015746A Logic PD Inc All Rights Reserved AM1808 SOM M1 Hardware Specification Table of Contents T Introduction oie ee 1 1417 Product Overviemuer avisa Mote 1 1 2 Abbreviations Acronyms amp 1 13 Nomenclature ce htt ton mia CO tea ene ta ru etit dei ee diane 2 1 4 Scope of Documents ein e potete e ete nit ate bert ta 2 1 5 Additional Documentation 2 2 Functional Specification cusa 3 24 Processor surr DAT teas etn Mine ete ea HE T e eed 3 24 1 AMT1BOG PrOCOSSOE aiii iet Hh eatin ke ei a 3 2 1 2 AM1808 Processor Block 4 2 2 SOM Interface iade cath vero ta Poe beate ep ease ene 4 2 2 1 1808 SOM M1 Block 5 2 3 Mechanical 5 2 31 Mechanical Characteristics 5 2 3 2 Interface 6 24 Temperature
49. rfaces please see TI s AM1808 User Guides IMPORTANT NOTE In order to correctly implement USB on the SOM additional impedance matching circuitry may be required on the USBx_D and USBx D signals before they can be used USB 2 0 requirements specify the signals must be routed as differential pairs with a 90 ohm differential impedance Refer to the USB 2 0 Specification for detailed information ADC Touch Interface The touch screen controller TSC on the AM1808 SOM M1 is an integrated feature of the TPS65070 PMIC This TSC is used to support standard 4 wire resistive touch panels The TPS65070 is connected to the AM1808 by the 12 0 interface Please see Tl s TPS65070 Datasheet for more information General Purpose I O GPIO Logic PD designed the AM1808 5 1 to be flexible and provide multiple options for analog and digital GPIO There are numerous digital GPIO pins on the SOM that interface to the AM1808 See Section 7 of this document for more information If certain peripherals are not desired such as the LCD controller chip selects IRQs or UARTs then more GPIO pins become available Expansion Feature Options The AM1808 SOM M1 was designed for expansion and a variable feature set providing all the necessary control signals and bus signals to expand the user s design Some of these signals are buffered before reaching the expansion connectors See TI s AM1808 ARM Microprocessor Datasheet and User Guides and Logic PD s AM1808
50. rocessor Pin J3 18 uP OBSCLK CLKOUT UHPI_HDS2 GP6 14 IMPORTANT NOTE Please see 5 AM1808 ARM Microprocessor Datasheet and User Guides for additional information about processor clocking The AM1808 processor also contains an on chip Real Time Clock RTC module which is driven by an external 32 768 kHz crystal The highly configurable RTC module provides a time reference to applications running on the AM1808 The SOM contains a dedicated power input pin J2 64 VRTC and low dropout LDO which supplies the processor s dedicated RTC power rail RTC CVDD IMPORTANT NOTE For more information on RTC power see Section 5 5 1 4 For more information about software configuration of the RTC see 5 AM1808 ARM Microprocessor Datasheet and User Guides Memory Mobile DDR The AM1808 SOM M1 provides volatile memory via a single mDDR chip Please refer to the AM1808 SOM M1 Bill of Materials BOM for the memory density of your specific SOM Other memory densities may be available for SOMs in production volumes Please contact Logic PD Sales about custom configurations if your design requires different memory densities from Logic PD s standard SOM configurations product sales logicpd com SPI Flash The AM1808 SOM M1 provides non volatile memory via an 8 MB SPI flash chip This is also the default boot device Other memory densities may be available for SOMs in production volumes Please contact Logic
51. see 5 uP VPIF DOUT10 GP7 2 BOOT 2 Hi Z see Note 1 2 VP DOUT 2 LCD D 2 UPP XD 10 3 3V or 1 8V LCD B3 data bit when outputting RGB565 6 uP VPIF DOUT2 GP7 10 Hi Z see Note 1 data to an RGB666 display LCD R1 data bit when outputting RGB565 DOUT 11 data to an RGB666 display LCD D 11 4 7k pull up on SOM UPP XD S 3 3V or 1 8V Used to latch boot mode at startup see 7 uP VPIF DOUT11 GP7 S BOOT 3 Hi Z see Note 1 Note 2 DOUTT S LCD UPP XD 11 3 3V or 1 8V LCD BA data bit when outputting RGB565 8 uP VPIF DOUT3 GP7 11 Hi Z see Note 1 to an RGB666 display PN 1015746A Logic PD Inc All Rights Reserved 17 AM1808 SOM M1 Hardware Specification J1 Pin SOM Net Name Processor Name I O Voltage Description LCD_R2 data bit when outputting RGB565 VP_DOUT 12 data to an RGB666 display LCD D 12 4 7k pull down on SOM UPP XD 4 3 3V or 1 8V Used to latch boot mode at startup see 9 uP VPIF DOUT12 GP7 4 BOOT 4 Hi Z see Note 1 Note 2 LCD B5 data bit when outputting RGB565 VP DOUT 4 data to an RGB666 display Notice that LCD LCD BO is omitted LCD B5 Blue MSB is UPP XD 12 3 3V or 1 8V also connected to LCD BO Blue LSB 10 uP VPIF DOUT4 GP7 12 Hi Z see Note 1 when driving an 18 bit display with 16 bits LCD R3 data bit when outputting RGB565 VP DOUT 13 data to an RGB666 display LCD
52. stem Integration e aa 12 Custom Configuration aia m tr ve i WA 12 52 RESETS wv cease hate tan e i al 12 5 2 1 Master Reset MSTR nRST Reset 12 5 2 SOM Reset 12 13 5 4 JTAG Debugger Interface ee e Uo tr o e E a durs 13 5 5 Power Managerriernit e tte tse terere den n ette rister 13 5 5 1 System Power S ppll6sz uc ntt et t I o e e ER DR eet ede tn 13 5 5 1 nerder kinesere bakerier 13 5 5 1 2 USBO VBUS eit rane eat eres ind 13 5 5 1 3 MAIN BAT T IN uiii tSc peto et et e HE ect Po E EO naken 14 55 4 VRTG pe E o 14 552 Dual Voltage ayes e t cette e m E SC erd 14 5 53 System Power Management c nt dec P i eL E ERR RA Pet EP uae edu da 14 554 MICr proCessor eR 15 5 6 ESD Gorisideratloris sad cie ede perde t PA ud ea SE RE ata de pu REEL Ft denne 15 PN 1015746A Logic PD Inc All Rights Reserved iii AM1808 SOM M1 Hardware Specification 6 Memory amp te 16 7 Pin Descriptions amp Functions Rune Ur 17 7 1 Connector 100 Pin 1
53. t mDDR Mobile Double Data Rate RAM MDIO Management Data Input Output MMU Memory Management Unit MPU Memory Protection Unit ARM processor core OTG On the Go USB PN 1015746A Logic PD Inc All Rights Reserved 1 1 3 1 4 1 5 AM1808 SOM M1 Hardware Specification PCB Printed Circuit Board PCMCIA Personal Computer Memory Card International Association PC Cards PHY Physical Layer PLL Phase Lock Loop PWM Pulse Width Modulation RTC Real Time Clock SATA Serial ATA SDRAM Synchronous Dynamic Random Access Memory SOM System on Module SOM M1 SOM form factor type used for the AM1808 modules SPI Standard Programming Interface STN Super Twisted Nematic LCD TFT Thin Film Transistor LCD Tl Texas Instruments TSC Touch Screen Controller UART Universal Asynchronous Receive Transmit uPP Universal Parallel Port USB Universal Serial Bus VLIW Very Long Instruction Word VPIF Video Port Interface Nomenclature The terms SOM and SOM M1 are used interchangeably throughout this document and can be assumed to mean the same thing within this text The SOM M1 is a specific form factor type of Logic PD s SOM Scope of Document This Hardware Specification is unique to the design and use of the AM1808 SOM M1 as designed by Logic PD and does not intend to include information outside of that scope Detailed information about the Texas Instruments TI AM1808 processor or any other device component on the SOM can be
54. y this must be provided by the product it is used in Logic PD has extensive experience in designing products with ESD requirements Please contact Logic PD if you need any assistance in ESD design considerations PN 1015746A Logic PD Inc All Rights Reserved 15 AM1808 SOM M1 Hardware Specification 6 Memory amp I O Mapping AM1808 chip select signals are described listed below Chip Select pevceremue nos 50510 Sen scs LCD Backignt Poweron devit seseo Available for use by an offboard device sosa UARTTXDondevkt_ UARTRXD on 12 0 is used extensively for configuration control SPI SCS 6 Available on both the SOM and dev kit 12 0 is used extensively for configuration control SPI SCS 7 Available on both the SOM and dev kit CS 0 nm Available for use by an off board external device EMA CS 2 5 Available for use by off board external device UHPI 5 ie Fill Available for use by an off board external device PN 1015746A Logic PD Inc All Rights Reserved 16 AM1808 SOM M1 Hardware Specification 7 Pin Descriptions amp Functions SOM Net Name This is the name used in Logic PD s AM1808 SOM M1 Schematics Processor Name This is the name used 5 AM1808 ARM Microprocessor Datasheet I O This indicates the default pin configuration after booting U Boot Most pins can be reconf
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