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EL-407 VLSI SYSTEMS DESIGN

1. DE2 Boards Results and Observations Submit a small report on project with workbook or appear in demo session 36
2. There should be continuous layer of n and p diffusion e There must be a single rail of Vdd as well as for Vss e Width of PMOS is twice or 2 5 times as compared to NMOS transistor and length of all transistors should be same e Also draw stick diagram and mention Euler s path Equipment Required e Microwind Mentor Graphics software installed PCs Schematic Schematic of given function showing Euler s path Theory CMOS logic based function consists of a pair of NMOS and PMOS transistors Two different transistors have to be placed in Layout so it will be a good exercise for learning structure of both transistors The network consisting of all PMOS transistors known as P network is responsible for determining rise time of output While the network consisting of all NMOS transistors known as N network is responsible for determining fall time of output waveform For multiple inputs there should be optimum gate ordering in layout A simple method for finding the optimum gate ordering is the Euler path method Procedure Follow the instructions given during Lab to complete task successfully Results Attached layout of a given function Lab Session 04 Objective To design and verify the layout of a given logic function on CMOS logic e There should be continuous layer of n and p diffusion e There must be a single rail of Vdd as well as for Vss e Width of PMOS is twice or 2 5 times as compared to NMOS transist
3. logic states Processing speed can also be improved due to the relatively low resistance compared to the NMOS only or PMOS only type devices Inverters can also be constructed with Bipolar Junction Transistors BJT in either a _ resistor transistor logic RTL or a transistor transistor logic TTL configuration 34 Procedure Follow the instruction given in Lab session 09 and during the Lab to complete task successfully Results and Observations Draw attach the voltage transfer curve 35 Lab Session 14 Objective To develop a self selected assigned Lab project based on previous lab tasks e To select Lab project after discussion with course Lab teacher e Incase of Verilog project simulation should be on Quartus II and Modelsim software DE2 Board will be used for hardware verification Equipment Required e Linux and Mentor Graphics Microwind Quartus IH and Modelsim Installed PCs e ALTERA DE2 Boards in case of Verilog Project Theory All students should select different projects related to their interests or assigned by course teacher Students can perform these tasks in groups or individual Maximum number of students in a group is restricted to two persons Remaining matters discussion related to project will discuss in Lab Procedure e Identify selected assigned project and the scope of the project e Incase of Verilog project develop code and test simulation results on Modelsim and verify hardware implementation on
4. output lines The decoders are used to extract opcode from instruction in a computer These are widely used in communication and video transmission circuits By using the two instances of 2 to 4 line decoder designed in the previous lab session the 3 to 8 line decoder is designed Truth table o jo jo fo ft f ofa 0 f a f o Table 10 1 25 Note e The enable input is active high e The output out is active low e The two 2 to 4 line decoders are cascaded Block diagram InO out 0 In 1 2 to 4 out 1 Line decoder out 2 E po Enable 0 out 3 out 0 2 to 4 out 1 Line decoder out 2 out 3 Enable 1 Fig 10 1 Exercise Apply different combination of inputs and verify results and attach print out 26 Lab Session 11 Objective To understand the Mentor Graphic Software for schematic and Layout design for electronic circuit using standard and Generic MGC Libraries of Mentor Graphics Equipment Required e Linux and Mentor Graphics Installed PCs Procedure 1 Run the linux environment by open the virtual machine 2 Torun mentor graphics open the terminal by right click and type following commands gt Source adk_da_ic Enter gt Cd usr mentor graphic caliber 2008 2_rhelx86linux icflow_home bin Enter gt icstudio Enter Finally the Mentor Graphics environment will run 3 Now create a new project from File gt New gt Project File Edit Tools Help ar S x E3 A N
5. sounmes w GF imir alib 2008 2 heheh linur isiy home mge_iesid_Bb mge_ic veriieg G kalibo GNA 2 dherlehGling a hana m ed re i commlib E alibes 2008 2 rhel binuo hamam esd i a amm _ gs Calibre O08 2 hela Elin ge icaid brge ic oom n E aibe OG rele Glin keto ema mge d_b mye marose gE TARANCI Are eea e a ya E Spocka Edag Keys Eecaoe Abon mateo Eno e boga p wi ching 8 After step 7 there should be total eight 8 libraries will appear in Library List Editor wizard Now press OK and then Next 9 Now in Technology Settings open Setting Editor and include all technology file of your MGC Design Kit 10 Here include Process file DRC rules file LVS rules file SDL rules file and PEX rules file and then Next and Finish Write path for following rules files Process file 28 ba Project Preferences HDL Miscellaneous Angle mode as degrees ee Add path here Process file ei IG Layout DAG rules file LVS rules file SDL rules file PEX rules file DRC rules file LVS rules file SDL rules file PEX rules file 11 Now File gt New Library and create new Library 12 Now create a new schematic with suitable name in same created library in step 11 by right click on library and select New Cell View and select Schematic in View Type 13 Schematic window will appear Draw your circuit on Schematic level and selecting components and sources from suitable l
6. Da R W W ATA Q Attached the Layout of CMOS inverter Lab Session 02 Objective To design and verify the layout of aCMOS NAND gate e There should be continuous layer of n and p diffusion e There must be a single rail of Vdd as well as for Vss e Width of PMOS is twice or 2 5 times as compared to NMOS transistor and length of all transistors should be same e Also draw stick diagram and mention Euler s path Equipment Required e Microwind Mentor Graphics software installed PCs Schematic Vss Schematic of F A B Theory CMOS logic based function consists of a pair of NMOS and PMOS transistors Two different transistors have to be placed in Layout so it will be a good exercise for learning structure of both transistors The network consisting of all PMOS transistors known as P network is responsible for determining rise time of output While the network consisting of all NMOS transistors known as N network is responsible for determining fall time of output waveform There are two inputs involved 1 e A and B So there should be optimum gate ordering in layout A simple method for finding the optimum gate ordering is the Euler path method Procedure Follow the instructions given during Lab to complete task successfully Results Attached the Layout of CMOS logic NAND gate mentioning all diffusion layers Lab Session 03 Objective To design and verify the layout of given logic function on CMOS logic e
7. LABORATORY WORKBOOK for the course EL 407 VLSI SYSTEMS DESIGN Name Roll No Batch Year Dept Department of Electronic Engineering N E D University of Engineering amp Technology LABORATORY WORKBOOK for the course EL 407 VLSI SYSTEMS DESIGN Prepared by Abdur Rahim Quershi Assistant Professor Naveera Sami Lecturer Reviewed by Hashim Raza Khan Assistant Professor Approved by Board of Studies of Department Of Electronics Engineering CONTENTS 1 Getting familiar with Verilog HDL for digital design ii To simulate and verify the verilog code on ModelSim Software i To understand 4 to 1 MUX working principle ii To understand ModelSim Software for Development of Verilog HDL Codes ii To implement and Test 4 to 1 MUX on Verilog HDL by e Gate Level Modeling e Data Flow Modeling e Behavioral Modeling i To understand Quartus II Software for Development of Verilog HDL codes 1i To implement and test Verilog HDL code of a given function ii To test the given function program on ALTERA DE2 board Program FPGA with SR latch using Verilog HDL and getting the overview of Flip flops Design and compile 2 to 4 line decoder and program FPGA i Getting started with the concept of Instantiation in Verilog HDL 11 Design and compile 3 to 8 line decoder using instantiation and program FPGA To understand the Mentor Graphic Software for schematic and Layout design for electronic circuit using standard and Ge
8. Selector Release v20082_1 1 File Editi yaw Toole Heip Gand ay E e Camporeenl Breaser Hedel Beare Nane T tangua Mecot Name aise abe E BLACKBROE Aime khia o MULLELOCHOK Pabuil Bree ig a es Fires a ret Select ye r schematic name here intoved Changes 0 Ei TLiroupioge vemia k dia r eriin Higroundoge viewsAbcie uitoe defui cir written kal amp 19 Now select which type of analysis you want to run by select ac de Trans and any simulation For example in case of DC analysis 20 Check DC analysis and then select Setup Select any source and Sweep parameters Start point End point and step size of selected source then press OK 21 Now select Setup Output a window will appears as shown in Fig below 31 fi j i Parameters Sweeps Ean Forces amp Edi Waveforms Ea Comer Analysis k IES MC Anabysis M i a Attach Eldo A simulation file 7 22 Now you can run your simulations and by drag and drop option you can view waveforms Results and Observation 32 Lab Session 12 Objective To determine the behavior of MOS transistor using Mentor Graphics by analyzing its e Ip v s Vps curve e Ipv s Vas curve e Early Effect Equipment Required e Linux and Mentor Graphics Installed PCs Theory EARLY EFFECT When the MOS operated in the saturation region practical MOS shows some dependence of the drain current on the drain source voltage at a
9. constant Vas That dependency is almost linear with a slope equal 1 ro When extrapolated the curves the characteristics lines meet at a point on the Vps axis at Vps Va The voltage Va is called the early voltage This phenomenon is generated because of the reduction in the effective channel width due to the increase in the reverse bias voltage on the drain bulk junction Procedure Follow the instruction given in Lab session 09 and during the Lab to complete task successfully Results and Observations Draw attach the aforementioned curves 33 Lab Session 13 Objective To determine the behavior of a given circuit by modeling and simulation on Mentor Graphics Software Equipment Required e Linux and Mentor Graphics Installed PCs Theory Vdd Vss An inverter circuit outputs a voltage representing the opposite logic level to its input Inverters can be constructed using a single NMOS transistor or a single PMOS transistor coupled with a resistor Since this resistive drain approach uses only a single type of transistor it can be fabricated at low cost However because current flows through the resistor in one of the two states the resistive drain configuration is disadvantaged for power consumption and processing speed Alternately inverters can be constructed using two complimentary transistors in a CMOS configuration This configuration greatly reduces power consumption since one of the transistors is always off in both
10. e Selected CA MGC_DESIGN_KIT gMGC_IC_COMMLIB C4 MGC_IC_COMMLIB_OS CA MGC_IC_COMMLIB_RF C4MGC_IC_DEVICE_LIB gMGC_IC_GENERIC_LIB C4MGC_IC_SOURCES_LIB CAMGC_IC_VERILOG_LIB CA MGC_MACROLIB 29 libt New Project This wizard will guide you through the steps for creating and configuring an IC Design project Press the Next button to continue Cancel Heip 4 Give the proper name and location of project and press Next The location of the project should be home student 5 Then Open Library List Editor and include generic and standard libraries 6 Go to Edit Menu and Add standard MGC Libraries After that eight libraries will add in Library List Editor 7 Now add the generic Kit through Add MGS Design Kit from Edit Menu of Library List Editor from path write path here Applications Actions Py ap Wed Mar 28 1248 PM Q ul bestudla Project abc_t 5 Fie Edit Toots Help ae See W LF H d MOC_OESKHN_KIT J occ i SSMMLIG s AMOT Ic COMMLIB t _ MOC_IC_OOMMLIB GMGC_I _ DEVICE Ho ff A 4 i a 4MGC_Ic_GENERIC ew flow impor Find Mice Up M t _ MGC It _RAACE MGC_IC_VERILOG eg MOC AO CALI Library List Editor AphiOe bre POOR 2 Mebin nage eaa igana li Gai Pag PASSE a Pe EPG Prue RETR Peer Re iang _ E Dili SOURCES aphictcalibresD0082 rhe b Hinu iy homneingc_icsid_lib
11. el Fh The data flow level ip the behavioral or procedural level The Switch Level It includes MOS transistors modeled as switches The Gate or Structural Level At this level gates primitives are called to design the logic It is not synthesizable The Data Flow Level At this level continuous assignments are used by using the keyword assign Synthesizer is required It is also called Data Flow Models This level allows using every type of operators The Behavioral or Procedural Level At this level you just have to define the behavior It is user friendly It uses procedural blocks blocking and non blocking hence called procedural level 13 Procedure l 2 10 Open the ModelSim software Create a new project by File gt New gt Project from the Main window A Create Project window appears as shown in figure below Select a suitable name for your project leave the Default Library Name to work Project Name Project Location tera 0 modelsim ase examples Browse Default Library Name work Copy Settings From modelsim ase modelsim ini Browse Copy Library Mappings Reference Library Mappings OK Cancel After project name an Add items to the Project dialog pops out as shown in figure below From the Add items to the Project dialog click on Create a new file If you have closed the Add items to the Project dialog then select P
12. g B bits of each input and select them to B bits output 16 B bits Data Inputs B bits Data Output Total n inputs as s Select Lines A 4 to 1 MUX is shown in figure below There are four input lines IO to I3 and two selections lines SO and S1 are decoded to select a particular input to appear at output Single data output o0 S1 The truth table for the 4 1 MUX is given as 17 Procedure ay Understand Gate level modeling Create new Modelsim project for writing the code Open new Verilog file and write code for Multiplexer in it Simulate your project and verify results Understand Data flow modeling Repeat steps 3 to 5 Understand Behavioral Modeling Repeat steps 3 to 5 Ne Oo a Oe aoe te Results Attach the verified results Include Verilog file in your project and compile your project 18 Lab Session 07 Objective To understand Quartus II Software for Development of Verilog HDL codes e Toimplement and test Verilog HDL code of a given function e To test program on ALTERA DE2 board Equipment Required e Quartus II software installed PCs e ALTERA DE2 Board Procedure Connect USB blaster cable and power adaptor with ALTERA DE2 board 1 Open the Quartus II software 2 Create a new project by selecting Create a New Project New Project Wizard as shown in Figure below Getting Started With Quartus II Software Start Designing Start Learning we D
13. iap wth Quartus A software The dude yale teractie tutorial tesche 7 Peguei J pro you the barr lerturei of Quartus U software 3 Version 9 0 Open Recent Project raheem awai Web links i aE Cuu O ee a Don t show this screen again 3 Select a suitable name for your new directory or you can use the existing one and also the name of the project and click on next option 19 4 After creating new directory and project create a new file by selecting File gt New z and select Verilog HDL File type as shown in Figure below LY VUINVNIGUUTICI 1 1 aboration je rs tant Post Mappinc rtAnalvain gt A command window will appear Write your program and save it with the same name as given in module command Make sure that file should be saved in the New Quartus Il Project SOPC Builder System E Design Files AHDL File Block Diagram Schematic File EDIF File State Machine File SystemVerilog HDL File Tel Script File Verilog HDL File VHDL File E Memory Files Hexadecimal Intel Format File Memory Initialization File E Verification Debugging Files In System Sources and Probes File Logic Analyzer Interface File SignalTap II Logic Analyzer File Vector Waveform File E Other Files AHDL Include File Block Symbol File Chain Description File Synopsys Design Constraints File Text File same project directory mentioned in step 2 Now co
14. ibraries 14 When schematic will complete Check and Save your design The message will appear If there is no error you can move further for simulations 15 Now run the simulation a window will pop up Select New configuration and select AMS _ Simulation 29 ee o File Add Edit Select Wew Tools Setup Report Window Help Generic Kit TDK gt KOO R amp Dl oe m oe SS AR e El e JZUH HAIS S HS Sel Ur dae i abe schematic sheet i nmos rmos d 2 47585 1 01544 Hotkeys On xyz ab Schematic i e v a Lee D gt Be i z o o e a E Session gt Simulation pd Euit Draw Entering Simulation M Text C Existing AR Gerarie M aviges 1 Sn a IC Library zm pence on a eam Create New i Generic Lib cong ig arctan Type Sources Lib i Digital_Simulation Macro Lib 7 AMS Simulation Se Verilog Primitive Lik mr e Configuration name DesignConfig T OK Reset Cancel eee te OK Reset Cancel g 16 Select Eldo simulation by Setup Sim Session gt Simulator View gt Eldo 17 Now select and appropriate environment for your simulation View Waveforms After Simulation from Setup Sim Session and select Environment 18 Now select Model Selector and window will appear Select Component and Schematic as shown in Fig below 30 NAQda 2 AS gt rynke fault qroupdhogee vari habe Ade tll al Model
15. mpile your program by selecting Processing gt start compilation After completion of compilation a message will appear full compilation was successful To verify your verilog code on ALTERA board assign suitable pins switches LEDs to your input output terminals by Assignments gt Pin Planner A pin planner window will appear 20 sug Meo fe ect Navigator b Cyclone Ik EP2C35F672C6 Bes Top View Wire Bond p awaz dg 1 1 Named ji gt Cyclone I EP2C35F672C6 aie SAVER 242012 eb Editon 5 Files amp Design Un s i w Compilation 2000 8 O sS ske H 2000 VVOSS pee 3B E B gt Compile Design sae Rae DAYS AV R EON g v EP Analyses amp Syntheses HOO Ves fet RN SA f t HOG A OG ae t A i SAVO 288 9 v Lp Analysis amp Elaboraton P Panton Merge CI Netist Viewers gt Design Assistam Pos P_ WO Assannmant A oa a oe T Message Info Running Quarg Info Command quas Info Longest tpd amp Info Quartus II cl Info Quartus II Full Compilation was successful errors Mi 4 efeeee t System 2 Processing 48 Exainto A Into 45 Waring 3 A CriicalWaming A Enor A Suppressed 6 9 Assign switches and LEDs to all input and output terminals respectively and start I O assignment analysis as shown in above figure The location of ALTERA DE2 board can be selected from ALTERA DE2 user manual 10 After I O assignme
16. neric MGC Libraries of Mentor Graphics To determine the behavior of MOS transistor using Mentor Graphics by analyzing its e Ip v s Vps curve e Ip v s Vas curve e Early Effect To determine the behavior of a given circuit by modeling and simulation on Mentor Graphics Software Q 1 2 3 m m N UI To develop a self selected assigned Lab project based on previous lab tasks Lab Session 01 Objective To design and verify the layout of a CMOS inverter e There must be a single rail of Vdd as well as for Vss e Width of PMOS is twice or 2 5 times as compared to NMOS transistor e Also draw stick diagram and mention Euler s path Equipment Required e Microwind Mentor Graphics software installed PCs Schematic Vdd Vin Vss Schematic of CMOS Inverter Theory CMOS logic based function consists of a pair of NMOS and PMOS transistors Two different transistors have to be placed in Layout so it will be a good exercise for learning structure of both transistors The network consisting of all PMOS transistors known as P network is responsible for determining rise time of output While the network consisting of all NMOS transistors known as N network is responsible for determining fall time of output waveform Procedure Follow the instructions given during Lab to complete task successfully Results Q What will be the effect on rise and fall time of output waveform when W W
17. nt analysis now code 1s ready to be dumped in ALTERA DE2 board Select Tools gt Programmer and after selection of USB blaster option select Start A 100 completion message will appear when program is completely dump 11 Now you can test your program on ALTERA DE2 board Results and Observations 21 Lab Session 08 Objective Program FPGA with SR latch using Verilog HDL and getting the overview of Flip flops Equipment required e Xilinx Spartan III Virtex 5 kit and Altera cyclone II kit e Quartus II installed PCs Introduction Latches are level sensitive storage elements the action of data storage is dependent on the level value of the input clock or enable signal Flip flops are edge sensitive storage elements the action of data storage is synchronized to either a rising or falling edge of a signal SR latch set reset latches can be used by the implementation of nor gates or nand gates We will program active low input SR latch cross coupled with nand gates in the lab session Schematic Diagram of SR latch Ee a R Q Fig 8 1 Characteristic Table of active low input SR Latch with Cross Coupled Nand Gates Table 8 1 Note e First stage in the table is indeterminate or invalid e Second stage is called set e Third stage is called set e Fourth stage is called hold Exercise Attach the printout of SR latch observed values and make a table 23 Lab Session 09 Objective Design and compile 2
18. of AND gate by right click on input and select Force and write either 0 or 1 in value box and repeat same step for changing the value of other inputs 16 Click Run button in main window tool bar and can see the changes in the both the wave and objects windows Results amp Observations Design the modules using all basic gates AND OR XOR NOR NAND and XNOR gate and verify the results 15 Lab Session 06 Objective e To understand 4 to 1 MUX working principle e To understand ModelSim Software for Development of Verilog HDL Codes e To implement and Test 4 to 1 MUX on Verilog HDL by o Gate Level Modeling o Data Flow Modeling o Behavioral Modeling Equipment Required e Modelsim Installed PCs Theory A multiplexer MUX is a digital switch which connects data from one of n inputs to a single output A number of Select Inputs determine which data input is connected to the output The Block Diagram of MUX with n data inputs and s select lines is shown in figure below Single data output n data input s select line MUX acts like a digitally controlled multi position switch where the binary code applied to the select inputs controls the input source that will be switched on to the output At any given point of time only one input gets selected and is connected to output based on the select input signal Input can be single bit or multi bits in nature Following figure shows n to 1 MUX handlin
19. or and length of all transistors should be same e Also draw stick diagram and mention Euler s path Equipment Required e Microwind Mentor Graphics software installed PCs Schematic Schematic of given function showing Euler s path 10 Theory CMOS logic based function consists of a pair of NMOS and PMOS transistors Two different transistors have to be placed in Layout so it will be a good exercise for learning structure of both transistors The network consisting of all PMOS transistors known as P network is responsible for determining rise time of output While the network consisting of all NMOS transistors known as N network is responsible for determining fall time of output waveform For multiple inputs there should be optimum gate ordering in layout A simple method for finding the optimum gate ordering is the Euler path method Procedure Follow the instructions given during Lab to complete task successfully Results Attached the layout of a given function 11 Lab Session 05 Objective 1 Getting familiar with Verilog HDL for digital design 2 To simulate and verify the verilog code on ModelSim Software Equipment Required e Modelsim software installed PCs Introduction Traditionally digital design was done by the schematic entry This has been replaced today by the use of Hardware Description Language HDL In electronics HDL is the language used for formal description of electronic circ
20. roject gt Add to Project gt New File from the main window A Create Project File dialog pops out Select an appropriate file name for the file you want to add the name of file must be same as you write in Step 4 choose Verilog as the add file as type option and Top level as the Folder option see figure below and then click on OK On the workspace section of the Main Window double click on the file you have just created VLSL v in our case Type verilog code of the given task in the new window Save your code In workspace window do right click on project name 1 e VLSI select Compile gt Compile All A message Compile of VLSI v was successful will appear in message window 14 11 For simulating the design click on Simulation gt Start Simulation in main window simulation environment will appears as shown in figure below 12 Click on the sign next to the work library You should see the name of the entity of the code that we have just compiled VLSI select your desired file 13 Locate the signals window and select the signals that you want to monitor for simulation For this example of AND gate select all signals as shown figure below 14 Drag the above signals by selecting all then right click and select Add gt to Wave gt Selected items to the wave window 15 Now we are ready to simulate our design For this purpose we will change the values of inputs i e a and b in above example
21. to 4 line decoder and program FPGA Equipment required e Altera cyclone II kit e Model Sim Quartus II installed PCs Introduction The decoder is an integrated circuit that receives the input at its pins and then decodes the combination at the input and shows the unique output word in which only one bit is asserted A decoder has n inputs and 2 output lines These are widely used in communication and video transmission circuits Truth table The output pins are active low ES a out 1 2 to 4 out 2 Line decoder out 3 Enable Fig 9 1 Exercise Apply different combination of inputs and verify results and attach print out 24 Lab Session 10 Objective Getting started with the concept of Instantiation in Verilog HDL e Design and compile 3 to 8 line decoder using instantiation and program FPGA Equipment required e Altera cyclone II kit e Model Sim Quartus II installed PCs Introduction Instantiation A module provides a template from which you can create actual objects When a module is invoked Verilog creates a unique object from the template Each object has its own name variables parameters and I O interface The process of creating objects from a module template is called instantiation The decoder is an integrated circuit that receives the input at its pins and then decodes the combination at the input and shows the unique output word in which only one bit is asserted A decoder has n inputs and 2
22. uits HDL offers several advantages over traditional design techniques such as efficient and convenient way of designing simulation and synthesis of large electronic circuits containing larger number of electronic components and devices efficient verification of design in initial phase of development Two popular HDLs are Verilog and VHDL The HDL used in our lab will be Verilog Hardware and Software Used In Lab Hardware e Xilinx Spartan HI kit e Xilinx Virtex 5 kit e Altera cyclone II kit Software e Quartus II e Model Sim Modes of Programming There are two modes of programming into FPGA e JTAG 12 e AS active serial Modes can be selected manually by a two way sliding button on the board by keeping its position on RUN or PROG respectively The only advantage of AS mode is to keep your program saved into the flash memory of FPGA In this mode your program will not be lost even after turning off the device and you may be able to access it again by powering up it again For JTAG set up the switch on the board to RUN position Introduction to Verilog HDL Verilog is a hardware description language used to model electronic systems Verilog HDL 1s one of the HDLs used by the integrated circuits IC designers The other one is VHDL VHSIC Very High Speed Integrated Circuit Hardware Description Language Verilog uses four levels of abstraction to describe the designs G The switch level Fh The gate or structural lev

EL-407 VLSI SYSTEMS DESIGN

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