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User`s Manual (Rev.1.20)

1. Assignments ii 81 8 4 Processing of Unused Pins eee cer cd 82 8 5 Allocating GCS uit cede adi Ded dest e Dep t ede 82 8 6 BUSCYCLE 8 6 1 Single A NON 83 98 6 2 BUrst CYC E Ae e Ae ae dee eem dee n des IE Gor e EP 83 8 6 3 GWATT I hcc tiet en d dee ee nur aed on Ge eon HH and c d de n t nta eda a ene 8 6 4 GBTERM 8 7 8 7 1 Setup Time eiecit hen er t e ded ned dnd de eth dece d de eee iain 86 827 22 Delay Titne ehe Eae 86 9 APPENDIX A 32 BIT EXT BUS SPECIFICATIONS eene nnn 87 9 1 Pin Assignments 9 2 E Data Bus Connection ote bee e e det ede Dc dot eee 9 3 1 16 Bit Data Bus CPU Reference cona ie e aec an a n P 9 3 2 32 Bit Data Bus CPU for RTE MOTHER A Motherboard E MEME oem 9 5 Compatible Connectors une eta e pedea as 9 6 orm A Ete Dee ee Rd d eec Lr eee e te p vend 92 10 APPENDIX B 16 BIT EXT BUS SPECIFICATIONS 93 10 4 PincAssigimmernts uie Lo esed e oed di ER aee 93 10 2 Signals RUE ER eb UR ERR Rete bea Ee Res 94 1073 TALIA Cysts ete a MN LAM ES e De ue 95 RTE MOTHER A USER S MANUAL Rev 1 20 1 INTRODUCTION The RTE MOTHER A is a motherboard that is used by connecting it to a Midas lab CPU board in the RTE CB series It is co
2. esssseeseseeeeeenene nennen 6 5 9 Configuration ROM Switching Jumper JP8 ssssssssseseseeeeeenene tenente treten tnter tenente nene 6 5 10 Switch 7 5 11 Power Connector JPOWER 1 5312 LEDren eei ted 5 13 JGBUS Connector JGBUS 5 14 PCI Slots JPGCI JPGI2 rote ete merat mte n p d eei Aat 8 5 15 ISA Slots JISAT JIS A2 ette et ete eo hear Ee reae ae eee te eo uut 8 5 16 PCMCIA Slots JPCMCIA1 JPCMCIA2 5 17 Keyboard Mouse Connector JKEY MOUSE 5 18 USB Connector JUSB iiti e onec n Eee ed ilies c Lee Seiten 9 5 19 Serial Connectors JSIO1 JSIO 2 oociccicococococononnnnnnnnsrmr tette testen tttm ttt tete testa 10 5 20 Parallel Connector JP RT rte trier iare r eo opea ede ea Eo Rein 11 5 21 Audio Mini Jack JIN R JIN L JLINEOUT sss tentent 11 5 22 LAN Connector JEAN i 12 5 23 IDE Connectors JIDET JIDED cinc 12 5 24 EXT BUS Connectors JEXT32 JEXT16 ssss sees tette tette 12 6 HARDWARE RBEFERENGES tiere a 13 6 1 RN 13 6 1 1 GBUS Bus Mastership Arbitration sss ennt ntt tenente te tentent t tenens 13 6 1 2 Temporary Release of GBUS Bus lt 5 1 ntn tenens 14 6 13 GBUS BU s LOck nocet ee d tad e Pd edie 14 6 1 4 Time Over Ready en rci ep Ces UE a ettet ee eia t eae F
3. GBTERM Output input Bus cycle completion request signal This signal is sampled on the rising edge of GCLK When the accessed side requests completion of the bus cycle the GREADY and GBTERM signals go low If the bus master samples GBTERM as low when it samples GREADY as low it must complete the bus cycle even though GBLAST has not been asserted and start the bus cycle again by asserting GADS again GBTERM must be asserted at the same time as GREADY This signal is used to complete the bus cycle when the accessed side does not support burst cycles or when a burst cycle exceeding the supported number of bursts is requested GW R Input output Write Read signal This signal indicates the direction of the data bus It is always driven by a valid value during the bus cycle This signal indicates the direction of the data bus for the bus master 77 RTE MOTHER A USER S MANUAL Rev 1 20 inpuvoutput i i Chip select signals These signals are always driven by a valid value during the bus cycle When the CPU board is the bus master it makes the corresponding chip select signal active to specify the resources on the motherboard Each chip select signal specifies the type of memory or I O space and the size of each space See Section 8 5 Allocating GCS 7 0 Read timing signal This signal is asserted when the CPU board is the bus master This signal is not used by the motherboard When the CPU has a
4. High D 15 0 Cycle EXT BUS I O Space Access Address 4n 0 and or 4n 1 and or 4n 2 and or 4n 3 32 16Bit High D 15 0 Cycle Flyby DMA reference 32 16Bit High D 15 0 Cycle EXT BUS Memory Space Access Address 4n 0 and or 4n 1 32 16Bit Low EXT BUS User Board DI31 161 Cycle EXT BUS Space Access Address 4n 0 and or 4n 1 32 16Bit Low EXT BUS User Board DI31 161 Cycle Flyby DMA reference Access Memory Address 4n 0 and or 4n 1 32 16Bit Low RTE PC EXT BUS User Board DI31 161 USER S MANUAL Rev 1 20 32 Bit Data Bus CPU for RTE MOTHER A Motherboard Cycle EXT BUS Memory Space Access Address 4n 2 and or 4n 3 32 16Bit Low D 15 0 Cycle EXT BUS I O Space Access Address 4n 2 and or 4n 3 32 16Bit Low D 15 0 Cycle Flyby DMA reference Access Memory Address 4n 2 and or 4n 3 32 16Bit Low D 15 0 90 RTE MOTHER A 9 4 Timing USER S MANUAL Rev 1 20 A 1 23 A 1 23 DMAAK 0 1 DMAAK 0 1 MRD MRD IORD IORD 9 MWR 0 3 E IOWR D 0 31 D 0 31 READY A READY Read Cycle Write Cycle DMAAK 0 1 DMARQ 0 1 DMA Cycle EXT BUS Cycles Description T ADDR DMAAK gt MRD IORD 10 T2 MRD IORD ADDR DMAAK hodime 10 T12 T13 3 T14 T15 T16 T18 T19 TI2 MWR IOWR oyde me 3 3 3 O Interval between MWR and IOWR cyc
5. AUDIO_FIFO O_FIFO_FULL_LEVEL O_FIFO_HALF_LEVEL AUDIO_FIFO_DEPTH O_CONT2 O_STATUS2 NT_STATUSO NT_CLEARO NT_EDGEO NT_POLARITYO NT_STATUS1 NT CLEAR1 NT EDGE1 NT POLARITY1 TOO INTENO NTOO_INTEN1 GINTO1_INTENO GINTO1_INTEN1 O2 INTENO TO2 INTEN1 TO3_INTENO O3_INTEN1 XTBUS_MEM_AMASK EXTBUS_IO_AMASK EXTBUS_CORE_MEM_BANK_ADDR EXTBUS_CORE_IO_BANK_ADDR EXTBUS_DMA0_MEM_BANK_ADDR TBUS DMAO IO BANK ADDR TBUS DMA1 MEM BANK ADDR EXTBUS DMA1 IO BANK ADDR TBUS STATUS TBUS CONTROL SW1 RDOUT POWER CONTROL POWER STATUS ISA INT VECTOR ISA INT STATUS BREQ CONTROL FROM CONTROL BLOCK CONTROL TOVRDY LED CLR ABORT LED CLR BACKOFF LED CLR cic gt c ojo gt c eo z o z OJO 2 2 o z m E 1 m m e m m GCS2 0000 1000H to GCS2 0000 107FH GCS2 0000 2000H to GCS2 0000 207FH GCS2 0000 3000H to GCS2 0000 302FH GCS2 0000 4000H to GCS2 0000 401FH FAST PPCS FAST SLOW FAST FAST FAST MID FAST FAST FAST FAST FAST FAST FAST FAST FAST FAST FAST FAST FAST FAST FAST FAST FAST FAST FAST FAST FAST FAST FAST FAST FAST FAST FAST FAST FAST FAST FAST FAST FAST FAST FAST FAST FAST FAST FAST FAST FAST FAST 6 2 5 6 2 5 6 2 5 6 2 6 1 6 2 6 2 6 2 6 3 6 2 6 4 6 2 6 5 6 2 6 6 6 2 6 7 6 2 6 8 6 2 6 9 6 2 6 10 6 2 7 2 6 2 7 3 6 2 7 4 6 2 7 5 6 2 7 6 6 2 7 7 6 2 7 8 6 2 7 9 6 2 7 10 6 2 7 14 6 2 7 11
6. Deleted that the serial EEPROM is not installed when the motherboard is shipped from the factory e Added that the MAC address can be acquired from the serial 1 1 RTE MOTHER A USER S MANUAL Rev 1 20 CONTENTS T INTRODUCTION ET 1 1 1 NOTATION USED IN THIS MANUAL 12 6 TERMINOLOGY cR 1 ENIUejge l E I M 2 3 nWe udz uiii 2 4 BASIC SPECIFIGATIONS nn Rue 3 5 BOARD CONFIGURATION 1 nnne necia ccennesecdeccedsrseecevtlte coustencacectenecdsure 4 5 1 IDE ACCESS LED CONNECTOR JHDD sss te tenete 4 5 2 FRONT PANEL tenete tenete tette tenete teret tette tete 5 5 3 POWER SWITCH CONNECTOR JPOWERSWN sesseseseseeseeeeene nennen tnter te tnter 5 5 4 POWER SWITCH SW A 6 5 5 AUDIO INPUT SWITCHING JUMPERS JP1 JP2 JP4 ssssssssssseseeeeeenenenr nennen 6 5 6 EXT BUS Forced 16 Bit Jumper JP5 ssssssssesesseseseee nene nete tne te tette tenete etate tenete terne tette 6 5 7 Battery Backup Memory Clearing Jumper JP96 sssssseseseseeeeeenenete nennen nnne trennen nens 6 5 8 Front Panel Reset Switch Disabling Jumper JP7
7. POWER_STATUS GCS2 0000 8030H Read Only An interrupt can be generated when an over current state is detected See Section 6 2 7 1 Overview of Interrupt Resources 70 RTE MOTHER A USER S MANUAL Rev 1 20 7 SOFTWARE This chapter describes software for operating the hardware on the motherboard 7 1 Sample Programs The sample programs on the CD ROM included with the RTE MOTHER A motherboard will operate various circuits on the motherboard and check the operating status Some checks may require special purpose jigs and although the jigs cannot be operate directly the source code will provide a reference for how to control them 7 1 1 7 1 2 Precautions Concerning the Sample Programs Note the following points when referencing the sample programs The sample programs have been written for Green Hills Software s C compiler Ver 1 8 9 e Since the sample programs were written for checking the operation of hardware the control procedures or hardware settings are not necessarily reasonable For example interrupts are not prohibited for portions in which interrupts must be prohibited according to the application characteristics the setting sequence for I O is inappropriate or portions will not operate if an optimizing compilation mode is used The sample programs have been written with an emphasis placed on reducing the work required for porting them to different CPU boards Therefore execution efficiency has not
8. S MANUAL Rev 1 20 8 6 4 GBTERM If both the GBTERM signal and GREADY signal become active at the same time the bus master completes the bus cycle after the current micro cycle ends and then starts the burst cycle again by asserting GADS active The GBTERM signal is asserted active when the access target does not support burst cycles or when accesses are made more than the supported number of bursts Asserting the GBTERM signal only without asserting the GREADY signal is not allowed The following chart shows that the burst cycle is cancelled by the GBTERM signal GBTERM GDATA 31 0 GDATA 31 0 Write 85 RTE MOTHER A USER S MANUAL Rev 1 20 8 7 Timing This section describes timing on the RTE MOTHER A The CPU board is designed to satisfy this timing 8 7 1 Setup Time CADDA cewGo es 7 o Le 73 35 comarca 6 gt GLOCK 9 19 2 9t 1 8 7 2 Delay Time 86 RTE MOTHER A USER S MANUAL Rev 1 20 9 APPENDIX A 32 Bit EXT BUS Specifications The JEXT32 connector is a 32 bit EXT BUS connector that is provided so that memory or I O spaces can be expanded The local bus inside the RTE MOTHER A motherboard is connected to this connecior 9 1 Pin Assignments D24 DI A s sere 65 ABS eno Ln DMARQ1 32 1 6BIT tii fg A JEXT32 Pin Ass
9. PLAY RESET of AUDIO_CONT2 mese RESET oraupo mese When REC HFULL INTEN is set to 1 an interrupt will be generated if the number of data items in the recording FIFO becomes greater than or equal to the value set in REC FIFO HALF LEVEL 7 0 This interrupt is generated corresponding to the FIFO status when audio is not being recorded 4 BUS8_16 should not be set to 1 29 RTE MOTHER A USER S MANUAL Rev 1 20 6 2 6 10 Audio Status Register 2 AUDIO STATUS2 GCS2 0000 5080H Read Only o 1 PLAY UNDF2 0 No playing FIFO underflow occurred 1 Playing FIFO underflow occurred REC ORVF2 lt lt Cautions gt gt 1 PLAY UNDF2 and REC_ORVF2 are the same as PLAY_UNDF and REC_ORVF of the audio status register respectively o 0 No recording FIFO overflow occurred 1 Recording FIFO overflow occurred a aja AR a 30 RTE MOTHER A USER S MANUAL Rev 1 20 6 2 7 Interrupt Control Circuits The interrupt control circuits combine all interrupts that are generated on the motherboard to finally consolidate them at GINTO 3 0 6 2 7 1 Overview of Interrupt Resources The following table lists the types of interrupts on the motherboard and describes controls for the interrupt control circuits The Polarity control column in the table indicates function that can correspond to the interrupt line being either High active Low active or ri
10. S MANUAL Rev 1 20 2 FUNCTIONS The overview of each function block of the RTE MOTHER A is shown below RTE CB LINE MIC LINE MIC LINE Series ABT ABT EA lt IL Serial arallel 1 F Audio In Out GRUS 9 TL16PIR552 uP D63310 LOCAL BUS OC AL EXT BUS Bridge Bridge SRAM Flash ROM Programmable 2MB 8MB InterruptC ontroller PCI PCI LI Ld PCI Bus et Bridge Ethernet P CI9080 PCERIS 5882558 South Bridge M1523B ES Ee BUS16 BUS32 EN PCMCIA 4l Ea Eg mn a n gt a n gt EIDE mn Interrupt Keyboard Counter Controlle ase E Secondary Primary EIDE 4 Keyboard eo Speaker RTE MOTHER A Block Diagram 3 MAJOR FEATURES Can be housed in a case that conforms to ATX standards and an ATX standard power supply can be used Provides connectors for connecting to various types of standard buses PCIx2 ISAx2 PCMCIAx2 USBx2 and E IDEx2 Provides connectors for connecting to EXT BUS 32 bit and EXT BUS 16 bit which are compatible with the RTE PC series e Provides 2M bytes of SRAM which can be shared with the RTE PC series and the PCI bus Provides 8M bytes of flash ROM Provides an interface for audio input output e Provides various types of PC AT DOS V compatible functions e Provides a 100Base TX Ethernet interface e Provides a serial parallel interface RTE MOTHER A USER S MANUAL Rev 1 20
11. 00 e 523 999944 509099445 50 999944 509099449 50 0000440 00000004000 RTE MOTHER A Components Layout IDE ACCESS LED CONNECTOR JHDD If an LED is connected to the JHDD connector it will light up when a hard disk that is connected to the IDE bus is accessed or when a hard disk that is connected to the PCMCIA slot is accessed The pin arrangement is shown below Pin 1 and pin 4 are the same signal RTE MOTHER A USER S MANUAL Rev 1 20 5 2 FRONT PANEL CONNECTOR JPANEL The JPANEL connector is used for connecting to the front panel If the case conforms to ATX standards JPANEL enables the front panel s connectors to be connected The pin arrangement and functions are shown below N C indicates that there is no connection GND 1 KEYLOCK 3 GND 5 RESET 7 POWER_LED 9 SPEAKER 11 EG EE 5V 13 GND 15 N C 17 SPEAKER 19 EL A a When this pin is Low the keyboard is locked Since this pin signal is pulled up when nothing is connected the keyboard will not be locked connected to 5 V via a 330Q resistor tone is generated by the SouthBridge chip or by the PCMCIA card When this pin is Low the motherboard is reset Since this pin signal is pulled up do not connect anything unless a reset is required The cable connections for a typical ATX case are shown below 5 3 POWER SWITCH CONNECTOR JPOWERSW JPOWERSW is a connector for connecting the power switch Thi
12. 1 One of these registers exists for each of GINTO 3 0 In the above table Gln_xxxx_INTEN 2 Since INTEN is unrelated to the edge detection circuit an interrupt request being maintained by an edge detection circuit will continue to be maintained even if INTEN is set to 0 See 3 Use Gln_ALL_INTEN when GINTOn is connected to a CPU edge sensitive interrupt on the CPU board When the relevant interrupt handling routine ends set Gln ALL INTEN to 0 and edge is generated on the interrupt line to the CPU so that the next interrupt will be generated after control leaves an interrupt handling routine See Section 6 2 7 1 Overview of Interrupt 0 1 GlIn GINTI1 INTEN 0 Disable the interrupt due to the GBUS GINTI1 pin 1 Enable the interrupt due to the GBUS GINTI1 pin 0 1 Gln LAN INTEN Disable the interrupt due to the SB82558 INTA pin Enable the interrupt due to the SB82558 INTA pin GIn PCI INTEN Disable the interrupt due to the occurrence of a parity error on the PCI Disable the interrupt due to the occurrence of a time over ready 5 BACKOFF ERR INTE Disable the interrupt due to the occurrence of a back off N 1 Enable the interrupt due to the occurrence of a back off represents GIO xxxx INTEN to GI3_xxxx_INTEN Section 6 2 7 1 Overview of Interrupt Resources then return it to 1 If this is done when interrupts arrive from multiple interrupt resources an Resources 42 RTE MOTHER A USER S MANUAL
13. 1 is the upper JUSB connector 6 2 9 3 POWER Status Register POWER_STATUS GCS2 0000 8030H Read Only RST 0 The 5 V power status of USB channel 0 is not over current 1 The 5 V power status of USB channel 0 is over current 1 The 5 V power status of USB channel 1 is over current 1 The PCMCIA status is over current lt lt Cautions gt gt 1 USB channel 0 is the lower JUSB connector Channel 1 is the upper JUSB connector For information about when the USB power is ON OFF see Section 6 2 9 2 POWER Control Register POWER_CONTROL GCS2 0000 8020H Read Write 2 PCMCIA_OVCURRENT becomes 1 when the 3 3 V 5 V or 12 V power state of either of the two PCMCIA slots is over current The PCMCIA power is controlled according to a register within the RF5C396 PCMCIA controller See Section 6 5 PCMCIA Bus 3 Each over current state can cause an interrupt to be generated See Section 6 2 7 1 Overview of Interrupt Resources 50 RTE MOTHER A USER S MANUAL Rev 1 20 6 2 9 4 ISA Interrupt Vector Register ISA_INT_VECTOR GCS2 0000 8040H Read Only lt lt Cautions gt gt 1 ISA_INT_VECT 7 0 indicates the interrupt vector that is obtained by generating an interrupt acknowledge cycle on the PCI bus when an interrupt is generated due to an ISA INTR signal M1523B INTR pin request The software can determine which interrupt was requested by looking at this vector 2 The contents of this regi
14. 2 6 8 Audio FIFO_DEPTH Register AUDIO_FIFO_DEPTH GCS2 0000 5060H Read Only o PLAY_FIFO_DEPTHO This is the number of bytes of data that are entered in the playing FIFO 1 PLAY_FIFO_DEPTH1 1 Number of remaining bytes in playing FIFO PLAY FIFO DEPTH 7 0 1 2 PLAY_FIFO_DEPTH2 1 alo REC_FIFO DEPTHO 1 This is the number of bytes of data that are entered in the recording FIFO Number of remaining bytes in recording FIFO REC_FIFO_DEPTH 7 0 1 REC_FIFO_DEPTH4 15 lt lt Cautions gt gt 1 The following equation shows the relationship between the number of bytes of data remaining in the FIFO and PLAY_FIFO_DEPTH 7 0 and REC_FIFO_DEPTH 7 0 FIFO remaining bytes Setting value in xxx_FIFO_DEPTH 7 0 1 However when the value of xxx_FIFO_DEPTH 7 0 is FFH it indicates that no data is remaining in the FIFO m 2 KN 9 15 28 RTE MOTHER A USER S MANUAL Rev 1 20 6 2 6 9 Audio Control Register 2 AUDIO CONT2 GCS2 0000 5070H Read Write PLAY_HFULL_INTEN 0 Do not request an interrupt when the number of data values in the playing FIFO is less than the Half Full value 1 Request an interrupt when the number of data values in the playing FIFO is less than the Half Full value PLAY RESET REC HFULL INTEN 0 Do not request an interrupt when the number of data values in the n recording FIFO is greater than or equal to the Half Full value 0 Do
15. 4 BASIC SPECIFICATIONS Buses GBUS CPU board RTE CB series connection bus Data 32 bits address 31 bits 33 MHz burst mode available PCI BUS 2 slots PCI 2 1 compliant 33 33 MHz 32 bits 5 V ISA BUS 16 bit Type 2 slot PCMCIA 2 slots PCMCIA2 1 JEIDA4 2 compliant 5 V 3 3 V EXT BUS RTE PC series compatible EXT bus Either one of the 32 bit and 16 bit buses can be used Interfaces Serial 2 channels DB9 connecior 10 pin pin header Printer 1 channel IEEE1284 compliant ECP EPP mode support 26 pin pin header USB 2 channels OpenHCl 1 0a compliant EIDE 2 channels PIO mode 0 to 4 and Multiword DMA mode 0 to 2 support ATA CD ROM support Keyboard PS2 compatible Mouse PS2 compatible Memory SRAM 2 MB 512K words x 8 bits x 4 Can be accessed from RTE CB series and PCI bus Flash ROM 8 MB 2M words x 8 bits x 4 Others RTC PC AT compatible real time clock AUDIO Stereo input x 1 channel stereo output x 1 channel AD DA converter resolution 16 bits monaural Maximum 48 kHz sampling LAN 10 100Base T 10Base T 100Base TX automatic negotiation full duplex half duplex RTE MOTHER A USER S MANUAL Rev 1 20 5 BOARD CONFIGURATION The physical layout of the major components on the RTE MOTHER A board is shown below This chapter explains each component 5 1 JPCI2 D D e rro XD OO EE TT FTE CODO TEE 09909449 D 0 0000044 900000 4 0440900000440 00000449 PO 640000004 O A A
16. 6 2 7 15 6 2 7 12 6 2 7 16 6 2 7 13 6 2 7 17 6 2 8 2 6 2 8 3 6 2 8 4 6 2 8 5 6 2 8 6 6 2 8 7 6 2 8 8 6 2 8 9 6 2 8 10 6 2 8 11 6 2 9 1 6 2 9 2 6 2 9 3 6 2 9 4 6 2 9 5 6 2 9 6 6 2 9 7 6 2 9 8 6 2 9 9 6 2 9 10 6 2 9 11 18 RTE MOTHER A USER S MANUAL Rev 1 20 6 2 3 6 2 4 SRAM GCS0 0000 0000H to GCS0 001F FFFFH This is the SRAM space that can be accessed from both the CPU board and from the PCI bus When it is accessed from the CPU board it is allocated in the space shown above However when it is accessed from the bus master on the PCI bus it is allocated in 0000 0000H to 01FF FFFFH The actual SRAM size is 2M bytes The relationship between addresses on the PCI bus and addresses on the GBUS is determined by PCI9080 settings Flash ROM GCS1 0000 0000H to GCS1 007F FFFFH A 5 V single flash ROM is installed Four MBM29F016 chips each consisting of 2M words x 8 bits are provided The flash ROM can be overwritten in terms of individual bytes For information about how to overwrite the flash ROM refer to the MBM29F016 manual This area which is the CPU board memory space should be arranged in two areas One of the two areas is a UV EPROM area on the CPU board A switch on the CPU board determines whether the UV EPROM on the CPU board is accessed due to an access to this area or whether the flash ROM on the motherboard can be accessed This enables the IPL to be written to this flash ROM area and the CPU
17. ENE E Ee lt lt Cautions gt gt 1 INTEDGE is a register for setting whether an interrupt request from an interrupt resource is an edge mode or level mode request The edge detection circuit maintains an edge detection result regardless of the setting of this register When this register setting is switched from level mode to edge mode the edge detection circuit should be cleared by the relevant INTCLR before the switch A PCI bus slot interrupt is normally used in level mode When the 16 bit EXT BUS JEXT16 connector is used the EXT BUS interrupt is connected to EXT_INTO 40 RTE MOTHER A USER S MANUAL Rev 1 20 6 2 7 9 Interrupt Polarity Specification Register 1 INT_POLARITY1 GCS2 0000 6070H Read Write An interrupt request due to the PCI slot 1 INTA pin is Low falling edge An interrupt request due to the PCI slot 1 INTA pin is High rising edge An interrupt request due to the PCI slot 1 INTB pin is Low falling edge An interrupt request due to the PCI slot 1 INTB pin is High rising edge An interrupt request due to the PCI slot 1 INTC pin is Low falling edge An interrupt request due to the PCI slot 1 INTC pin is High rising edge An interrupt request due to the PCI slot 1 INTD pin is Low falling edge An interrupt request due to the PCI slot 1 INTD pin is High rising edge An interrupt request due to the PCI slot 2 INTA pin is Low falling edge An interrupt request due to the PCI slot 2 INTA p
18. GWR GHLDA GDMARQ1 126 GDMAAK1 130 Reserve 134 45V 138 GINTO3 142 GETC1 146 GETC5 150 Reserve Signal name GND GADDR4 GND GADDR10 GADDR14 GADDR16 GADDR20 GND GADDR26 GADDR30 GBENS3 GND GDATA29 GDATA25 GDATA23 GDATA19 GND GDATA13 GDATA9 GDATA7 GDATA3 GND GBTERM GBLAST GND GCS2 GCS6 Reserve GND GBREQ GDMARQ2 GDMAAK2 Reserve GINTOO GINTIO GETC2 GETC6 GAHI_EN Signal name 5V GADDR5 5V GADDR11 GADDR15 GADDR17 GADDR21 5V GADDR27 GADDR31 GBEN2 5V GDATA28 GDATA24 GDATA22 GDATA18 5V GDATA12 GDATA8 GDATA6 GDATA2 5V GREADY GWAITI 5V GCS3 GCS7 Reserve 5 N C GDMARQ3 GDMAAK3 Reserve GINTO1 GINTI1 GETC3 GETC7 GMOTHER_DETECT 10 14 18 N N N a N a jo a a A al alo o N ojo a o o Nd 12 Nos A o a 102 106 110 114 118 122 o 1 1 2 o a RB wo lt alo YIN wo N 2 oOololas zx 29 R ojo ala ays N GND GRESETO N C N C N C N C GND 154 5V 158 GBLOCKO 162 N C N C N C N C 45V a a GUSE_DIRECT_ACC 156 GCLK_
19. INTB INTHIGH 2 2 INTA INTHIGH 2 Cl2_INTC_INTHIGH 2 7 CI2 INTD INTHIGH mM N EXT_INT3_INTHIGH 14 PCMCIA_OC_INTHIGH lt lt Cautions gt gt 1 INTHIGH sets the polarity of an interrupt request from an interrupt resource RST X An interrupt request due to a PCMCIA over current is High rising edge When the INTEDGE setting is edge mode either rising edge or falling edge can be selected according to the INTHIGH setting When the INTEDGE setting is level mode either Low active or High active can be selected according to the INTHIGH setting When edge mode is set by INTEDGE an edge detection circuit may end up detecting an edge according to the polarity setting changes Therefore when this register setting is switched the edge detection circuit should be cleared by the relevant INTCLR after the switch A PCI bus slot interrupt is normally used with a Low level When the 16 bit EXT BUS JEXT16 connector is used the EXT BUS interrupt is connected to EXT_INTO 41 RTE MOTHER A USER S MANUAL Rev 1 20 6 2 7 10 GINTOO Interrupt Enable Register 0 GINTOO INTENO GCS2 0000 6100H Read Write 6 2 7 11 GINTO1 Interrupt Enable Register 0 GINTO1_INTENO GCS2 0000 6120H Read Write 6 2 7 12 GINTO2 Interrupt Enable Register 0 GINTO2_INTENO GCS2 0000 6140H Read Write 6 2 7 13 GINTO3 Interrupt Enable Register 0 GINTO3_INTENO GCS2 0000 6160H Read Write Gln ALL INTEN 0 Disable interrupts
20. MIC input You can switch whether the input is MIC input or LINE input by using the JP1 to JP4 jumper switches See Section 5 5 AUDIO INPUT SWITCHING JUMPERS JP1 JP2 JP4 During recording A D converted data is sent as serial data to the FPGA and converted to 8 bit data The 8 bit data is stored in queuable programmable 8 bit FIFOs up to a maximum of 254 bytes and when data is read from the local bus 2 bytes of data are read at one time During playing data written from the local bus is stored in queuable programmable 8 bit FIFOs up to a maximum of 254 bytes converted sequentially to serial data and sent to the 4PD63310 After the PD63310 converts the received data to parallel data it is D A converted and output Since the maximum number of bytes can be set under program control separately for the play and record 8 bit FIFOs you can evaluate the FIFO requirements by balancing them with CPU performance Although audio data can be transferred under software control according to FIFO related information in the AUDIO STATUS register it can also be transferred by using DMA transfers A DMA transfer uses channel 0 for GBUS playing and channel 1 for recording Although a FIFO itself has an 8 bit configuration writing and reading is performed in 16 bit units The 16 bit 8 bit conversion is performed by an internal circuit Also a DMA request is generated during playing when the FIFO has at least two bytes of free space and a DM
21. Register POWER_CONTROL GCS2 0000 8020H Read Write Also an over current state can be read see Section 6 2 9 3 POWER Status Register POWER_STATUS GCS2 0000 8030H Read Only and an interrupt can be generated by generating an over current state see Section 6 2 7 1 Overview of Interrupt Resources 6 3 9 6 Configuration Register The configuration space registers of the USB controller contain no USB function related registers 64 RTE MOTHER A USER S MANUAL Rev 1 20 6 3 10 IDE Bus Master Controller M1523B SouthBridge On chip Implementation 6 3 10 1 Specifications This is a controller for performing bus master transfers to the IDE bus that is implemented on the M1523B SouthBridge chip Besides this controller the IDE interface has a separate register for supporting PIO mode 6 3 10 2 Device Numbers For the device numbers that are assigned see Section 6 3 5 Device Numbers The vendor ID of this device configuration register is 10B9H and the device ID is 5219H 6 3 10 3 Addresses Since this is a device that is connected to the PCI bus the allocated addresses are determined by the value set in the register for the IDE controller s configuration space 6 3 10 4 Interrupts The IDE bus master controller s INTA pin and INTB pin are internally routed inside the M1523B They can be routed to any interrupt input of the i8259 controller that is implemented on the M1523B chip according to an M1523B confi
22. Section 6 2 9 1 SW1 Read Out Register SW1 RDOUT GCS2 0000 8000H Read Only When read from the register the value is 1 when the switch is OFF and 0 when the switch is ON No specific uses have been determined for any of the bits Power Connector JPOWER1 An ATX standard power supply can be connected The pin arrangement is shown below 0000000000 0000000000 If an ATX standard power supply is connected only 5 VSB is supplied when the power supply unit s AC power is first turned on In this state pushing the SW_POWER switch on the board or pushing the switch connected to JPOWERSW allows 5 V 3 3 V 12 V 5 V and 12 V to be supplied Pushing the switch again stops the supply of power other than 5 VSB The 3 3 V supplied from the JPOWER1 connector is not used within this board The 3 3 V within the board is created from the 5 V by the regulator on the board This takes into consideration cases in which a non ATX standard power supply is connected as described below If an ATX standard power supply cannot be provided refer to the following table and supply only the required power indicated there The current consumption shown in the following table indicates only the current consumed by the motherboard The current consumed by connected boards such as RTE CB series PCI board ISA board or PCMCIA card or equipment such as a USB device keyboard or mouse is not taken into consideration Always supply this power Max 3 5
23. Signal name LAY 0 LAY_UNDF_INTEN PLAY_OVRF_INTEN nused nused nused nused nused EC 2 2 px o 4 EC UNDF INTEN EC OVRF INTEN ES o c nused 1 ION c nused nused nused AUDIO RESET a P c 15 ale Cautions 1 2 When PLAY is set to 1 a DMA request is immediately asserted when it is not masked and the PLAY DOING bit of the AUDIO STATUS register becomes 1 When PLAY is set to 0 a DMA request is immediately de asserted However if the FIFO contains data playing will continue and the 1 state of the PLAY DOING bit of the AUDIO STATUS register will be maintained When the playing of all data within the FIFO ends the PLAY DOING bit becomes 0 Also after PLAY has been set to 1 if PLAY is set to 0 before playing begins the PLAY DOING bit immediately becomes 0 However in this case if CPU board DMA transfers are enabled playing data may end up remaining in the FIFO depending on the timing All enabled interrupt requests due to the occurrence of an overflow or underflow are combined by a logical OR operation and sent to the interrupt controller These interrupts can be allocated to GINTO 3 0 by setting the interrupt controller See Section 6 2 7 Interrupt Control Circuits When REC is set to 1 the DOING bit of the AUDIO STATUS register immediately becomes 1 and the fetching of data to the FIFO
24. a data size exceeding 16 bits When either JEXT32 16BIT or JEXT16 EN is 1 an access to the EXT BUS is performed using a data size not exceeding 16 bits JEXT16_EN essentially is a signal that is generated according to the level of the pin that is connected to GND If it cannot be detected normally by this method JEXT16_EN can be set to 1 by short circuiting JP5 See Section 5 6 EXT BUS Forced 16 Bit Jumper JP5 and Section 10 2 Signals 6 2 8 11 EXT BUS Control Register EXTBUS CONTROL GCS2 0000 7090h Read Write 1 DMAAK THROUGH 1 0 The EXT BUS DMAAK signal becomes active only during a DMA cycle 1 The EXT BUS DMAAK signal obeys the active timing of the DMAAK signal of the CPU board i unse ox Ooo O MAT E O IA E o ox unse E O lt lt Cautions gt gt The DMAAK_THROUGH signal controls the active timing of the EXT BUS DMAAK signal When DMAAK_THROUGH is set to 1 the EXT BUS DMAAK signal changes with almost the identical timing as the DMAAK signal from the CPU board Actually to guarantee the hold time for the RD WR signal the logical OR operation is performed with a signal that is latched within the motherboard Therefore for a DMA transfer from the CPU board to the EXT BUS the EXT BUS DMAAK signal becomes active somewhat before the EXT BUS DMA cycle begins because the DMAAK signal becomes active after the transfer cycle began on the CPU board When DMAAK_TH
25. accesses the PCI bus 6 3 4 6 Abort Error When a master and target abort or a retry timeout is generated by a bus cycle generated on the PCI bus by the PCI9080 the PCI9080 asserts the BTERMo pin GBUS GBTERM signal to abort the bus cycle When this abort error status occurs the ABORT LED on the motherboard lights up This LED stays lit until it is cleared under software control See Section 5 12 LED and Section 6 2 9 10 ABORT LED Clear Register ABORT LED CLR GCS2 0000 80A0H Write Only Also an interrupt can be generated due to the occurrence of this abort error status See Section 6 2 7 1 Overview of Interrupt Resources After the scanning of resources connected to the PCI bus PCI bus configuration is completed a master and target abort essentially will not occur Similarly when the PCI bus is operating normally a retry timeout will not occur Therefore a serious fault is possible when an abort error status occurs 6 3 4 7 Back Off Error If the PCI9080 requests a back off when the GBUS GUSE DIRECT ACC signal is Low a back off error status occurs When this back off error status occurs the BRKOFF LED on the motherboard lights up This LED stays lit until it is cleared under software control See Section 5 12 LED and Section 6 2 9 11 BACKOFF LED Clear Register BAFCKOFF LED CLR GCS2 0000 80B0H Write Only Also an interrupt can be generated due to the occurrence of this back off error status See Section
26. been taken into account e The sample programs use the safest possible contents for settings configuration space related to the MB1523B SouthBridge chip Therefore performance has been sacrificed somewhat for applications that frequently access the PCI bus ISA bus or PCMCIA bus Overview of Sample Programs The processing or checks performed by using the sample programs various files or directories are described below CPU name directory Individual files for each CPU board are stored in a directory whose name begins with an underscore The sample programs can be built by using the bld files that are in this directory CPU nameYsrc directory This directory contains files c and h specific to each CPU board common directory This directory contains common files that are not dependent on the contents of specific checks It contains various types of header files and initialization setting program files commonYpci c This file contains initialization routines for the configuration spaces of devices connected to the PCI bus It contains initialization routines related to the ISA IDE or USB of the M1523B SouthBridge chip and an initialization routine for the SB82558 LAN controller commonYpemcia c This file contains an initialization routine for the RF5C396 PCMCIA controller commonYrtev832 pc c This file contains an initialization routine that is used when a Midas lab RTE V832 PC board is connected to the PCI slot
27. board is connected to the JEXT16 connector memory and I O are not distinguished and all spaces of the connected board can be accessed The maximum area size is 1M byte e f a control register on the local bus has an address expansion bank register and a space of at least 64K bytes has been allocated by using this bank register access can be expanded to 16M bytes See Section 6 2 8 EXT BUS Control Registers When a board is connected to the JEXT32 connector two cycle DMAs are supported for two channels and an access expansion bank register is provided for each DMA channel See Section 6 2 8 EXT BUS Control Registers GCS4 64K bytes 16M bytes EXT BUS I O space e Can access the I O space of JEXT32 The maximum area is 16M bytes e JEXT16 cannot be accessed Ifa control register on the local bus has an address expansion bank register and a space of at least 64K bytes has been allocated by using this bank register access can be expanded to 16M bytes See Section 6 2 8 EXT BUS Control Registers Two cycle DMAs are supported for two channels and an access expansion bank register is provided for each DMA channel See Section 6 2 8 EXT BUS Control Registers GCS5 Memory 1M byte 2G bytes PCI bus memory space e Can access the memory or I O space of the PCI bus via the PCI9080 e The allocated area should be as large as possible e Abus lock can be applied by the GLOCK1 signal or by control from 1 0 on
28. board to be started up by using that IPL Also functions for resetting the flash ROM and reading the BUSY status of the flash ROM are provided in a local bus register See Section 6 2 9 7 Flash ROM Control Register FROM CONTROL GCS2 0000 8070H Read Write 19 RTE MOTHER A USER S MANUAL Rev 1 20 6 2 5 UART PRINTER TL16PIR552 GCS2 0000 0000H to GCS2 0000 302FH The Texas Instruments TL16PIR552 dual UART with 1284 parallel port LSI is used as the UART PRINTER controller The TL16PIR552 has a 2 channel UART and 1 channel IEEE1284 compliant bi directional printer port It also has a 16 character FIFO buffer in the transmission reception block of the UART and a function for automatically controlling RTS CTS flow Therefore an overrun error can be suppressed by the minimum interrupt Each register of the TL16PIR552 is assigned as listed below For an explanation of the function of each register refer to the TL16PIR552 manual The TL16PIR552 manual is available from the TI amp ME of the Texas Instruments home page http www ti com GCS2 0000 0000H UART CH 0 GCS2 0000 0020H WR GCS2 0000 0030H LCR GCS2 0000 0040H GCS2 0000 0050H LSR GCS2 0000 0060H MSR MSR GCS2 0000 0070H SCR GCS2 0000 1000H UART CH 1 RBR DLL THR DLL GCS2 0000 1010H IER DLM IER DLM GCS2 0000 1020H FCR GCS2 0000 1030H LC LCR E D i z GCS2 0000 1040H GCS2 0000 1050H LSR LSR GCS2 0000 1060H MSR MSR GCS2 0000 1070H SCR SCR GCS2 0000 200
29. can be set separately when the CPU is accessed when DMA channel 2 is accessed and when DMA channel is accessed In addition the memory and I O spaces are set separately for each of these cases However since the GBUS GDMAAK2 signal and GBUS GDMAAK3 signal must be active to enable bank addresses for DMA accesses DMA bank addresses cannot be used with a CPU board for which the DMAAK signal is not available 44 RTE MOTHER A USER S MANUAL Rev 1 20 6 2 8 2 EXT BUS Memory Space Address Mask Register EXTBUS MEM AMASK GCS2 0000 7000H Read Write o EXT MEMAMASKi6 o EXT MEM AMASK 23 16 specifies the address mask of the EXT BUS 1 ExT amaski7 memory space 2 o 3 MeMamaskig o 4 ExT 20 o 5 o ExT mem amaske2 o Lo EXT_MEM_AMASK23 lt lt Cautions gt gt 1 EXT_MEM_AMASK 23 16 determines the address to be output to the EXT BUS for an access to the EXT BUS memory space that is for an access when the GBUS GCS3 signal is active For the correspondence of the GBUS address and EXT BUS address see Section 6 2 8 1 Bank Window When a 16 bit EXT BUS JEXT16 connector is used the setting of this register is always used for an access to the EXT BUS and the EXT_IO_AMASK 23 16 register is not used 6 2 8 3 EXT BUS I O Space Address Mask Register EXTBUS IO AMASK GCS2 00
30. connector used by PC AT DOS V compatible devices The shape of the JSIO2 connector is a 2 54mm pitch pin header type connector For both connectors all signals are converted to RS 232C levels The following figures and table show the connector pin numbers and describe each pin The table shows the general cross cable reverse cable wiring when the other side is a D SUB 9 pin and D SUB 25 pin connector The JSIO2 pin arrangement will be the same as the JSIO1 pin arrangement when a pressure welded type connector is used for the ribbon cable 09000 JSIO1 Pin Arrangement Male 9 E Hr 10 2 JSIO2 Pin Arrangement JSIO1 JSIO2 Destination Destination pin No cross No cross Signal name Input Output pin No pin No D SUB9 D SUB25 _ oo ee 2 3 3 2 3 TxD SD Output DTR DR Output e 5 JSIO1 T JSIO2 Connector Signals 10 RTE MOTHER A USER S MANUAL Rev 1 20 5 20 Parallel Connector JPRT JPRT is a parallel printer connector controlled by a parallel controller TL16PIR552 connected to the local bus See Section 6 2 5 UART PRINTER TL16PIR552 GCS2 0000 0000H to GCS2 0000 302FH IEEE1284 compliant devices can be connected The shape of the JPRT connector is a 2 54 mm pitch pin header type connector All signals are at the 5 V level The following figure and table show the connector pin numbers and describe each pin The JPRT pin arrangement will be t
31. is Low falling edge interrupt request from the GBUS GINTIO pin is Low falling edge interrupt request from the GBUS GINTIO pin is High rising edge interrupt request due to the SB82558 INTA pin is Low falling edge interrupt request due to the SB82558 INTA pin is High rising edge Cautions 1 INTHIGH sets the polarity of an interrupt request from an interrupt resource When the INTEDGE setting is edge mode either rising edge or falling edge can be selected according to the INTHIGH setting When the INTEDGE setting is level mode either Low active or High active can be selected according to the INTHIGH setting When edge mode is set by INTEDGE an edge detection circuit may end up detecting an edge according to the polarity setting changes Therefore when this register setting is switched the edge detection circuit should be cleared by the relevant INTCLR after the switch Since an interrupt from the SB82558 LAN controller obeys PCI bus standards Low level should be used 37 RTE MOTHER A USER S MANUAL Rev 1 20 6 2 7 6 Interrupt Status Register 1 INT_STATUS1 GCS2 0000 6040H Read Only B RST There is no interrupt request due N a PCI2_INTA_INTRQ RQ a m a lt lt Cautions gt gt All INTRQ signals are common to all GINTO 3 0 pins Also the INTRQ signals that are read 1 from this register are the signals before they are masked by the controller PCH
32. is pending on the CPU board The RTE MOTHER A motherboard has a function for limiting the interval that the PCI9080 maintains the bus right according to local bus control register setting See Section 6 2 9 6 BREQ Control Register BREQ_CONTROL GCS2 0000 8060H Read Write DMA request signals Only two cycle DMA transfers are supported Fly by DMA is not supported These signals are asserted low when a DMA request is generated on the motherboard The CPU board must support all four DMA signals The number of DMA signals that can be asserted at the same time and can be supported by the GDMAAK signal depends on the CPU board The CPU board uses the DMAAK signal in preference to DMAAK 3 2 when the correspondence between all four GDMARQ signals and GDMAAK signals cannot be established The motherboard uses GDMARQO for Audio playing GDMARQ1 for Audio recording GDMARQ2 for the EXT BUS DMARQO and GDMARQ3 for the EXT BUS DMARQ1 78 RTE MOTHER A USER S MANUAL Rev 1 20 inpuvoutput GINTO 3 0 Output GMOTHER_ Output DETECT GUSE_ Input DIRECT_ACC DMA acknowledge signals These signals are asserted low to acknowledge DMA requests from the motherboard The CPU board uses the DMAAK signal in preference to DMAAK 3 2 when the correspondence between all four GDMARQ signals and GDMAAK signals cannot be established The motherboard uses GDMAAKO for Audio playing GDMAAK1 f
33. terms of byte units PLAY UNDF or PLAY ORVF is cleared when 1 is written to the relevant bit of this register Also the signal is cleared when the playing circuits are reset See Section 6 2 6 9 Audio Control Register 2 AUDIO CONT2 GCS2 0000 5070H Read Write The PLAY LED lights as follows according to the states of PLAY DOING PLAY UNDF and PLAY ORVF PLAY DOING PLAY UNDF PLAY ORVF PLAY LED a r x cjr cx wp gt du e O ee ee ee 24 RTE MOTHER A USER S MANUAL Rev 1 20 6 REC_UNDF or REC_ORVF is cleared when 1 is written to the relevant bit of this register Also the signal is cleared when the recording circuits are reset See Section 6 2 6 9 Audio Control Register 2 AUDIO_CONT2 GCS2 0000 5070H Read Write The REC LED lights as follows according to the states of REC_DOING REC_UNDF and REC_ORVF REC_ORVF o o o Tumsof nc e ee o x o Red Jp 7 PLAY FIFO EMPTY becomes 1 when the FIFO does not contain at least one byte of data PLAY FIFO FULL becomes 1 when the amount of empty space in the FIFO is less than two bytes relative to the maximum size of the playing FIFO which was set for AUDIO FIFO FULL LEVEL See Section 6 2 6 6 Audio FIFO FULL LEVEL Setting Register AUDIO_FIFO_FULL_LEVEL GCS2 0000 5040H Read Write PLAY_FIFO_HFULL becomes active when the number of data items in the FIFO is greater than or equal to the playing FIFO s
34. the JEXT space To ensure that the CPU recognizes the READY signal the READY signal must be maintained active until RD or WR becomes inactive This signal is pulled up to 10 kQ on the board INT Input Low active interrupt request signal This signal is connected to the INTO signal of the JEXT32 connector This signal is pulled up to 10 kQon the board See Section 6 2 7 6 Interrupt Status Register 1 INT STATUS1 GCS2 0000 6040H Read Only Low active system reset signal RESET Output Low active system reset signal Output Clock signal The GBUS GCLK pin is buffered and then connected to this signal JEXT16 Connector Signals lt lt Cautions gt gt 1 Although 49Pin is essentially the GND pin the RTE MOTHER A motherboard uses it to detect whether a board has been inserted in the JEXT16 connector Thatis if 49Pin is low a board has been connected to the JEXT16 connector To connect a board for which 49Pin is not connected to GND to the JEXT16 connector you can forcibly connect 49Pin to GND by short circuiting JP5 See Section 5 6 EXT BUS Forced 16 Bit Jumper JP5 94 RTE MOTHER A USER S MANUAL Rev 1 20 10 3 Timing A O 19 A O 19 BHE RD D 0 15 D 0 15 READY JEXT16 Bus Cycles Description RD address setup time T2 RD address hold time RD cycle time Interval between RD cycles T5 T6 T8 T9 20 n2 WReyoetime so Intervalbetw
35. the JEXT32 connector for this test The checks performed are an EXT BUS memory and I O check an EXT BUS 16 bit mode check an EXT BUS DMA transfer check and a check of interrupts from the EXT BUS flash_test directory This directory contains a program for testing the erasing or writing to flash ROM on the motherboard At the end of the test the contents of the CPU board s ROM are written to the flash ROM ide_testdirectory This directory contains a program for checking accesses to a hard disk that is connected to the JIDE connector on the motherboard The checks performed are a hard disk reset reading of hard disk information displaying the model number and firmware version which are part of the information and reading sector 0 partition information by using a DMA transfer and confirming that the last data is Ox55aa isa_bm_sram_test_mb directory This directory contains a program that is a companion to a program for checking access to common RAM SRAM on the motherboard from the bus master on the ISA bus A special purpose jig must be connected for this test key_mouse test directory This directory contains a program for checking the keyboard and mouse connectors on the motherboard The keyboard check resets the keyboard and then makes the keyboard LED blink and confirms that q is entered The mouse check also connects the keyboard and confirms that q is entered Both checks are performed with the keyboard is connected to each
36. the address on the PCI bus differs from the address viewed from the CPU as described in the section concerning the LAN controller A driver created for use in a PC AT compatible machine is often written under the assumption that the address on the PCI bus and the address viewed from the CPU are equal Therefore be careful concerning the address that is set when common RAM SRAM on the motherboard is accessed by the bus master on the PCI bus ISA bus or PCMCIA or by a DMA within the M1523B SouthBridge chip A common RAM address must be set by using an address on the PCI bus in a setting for a DMA within the SouthBridge chip or for a board on the PCI ISA bus However that address differs from the address used when the common RAM is accessed from the CPU For standard resources that are installed on the motherboard this precaution must be taken into account when the LAN controller IDE controller or USB controller bus master function is used Some legacy devices will not operate normally when accessed by using a 16 bit read cycle even when consecutive addresses are used for I O For example an access to the real time clock RTC must be an 8 bit access An 8 bit read cycle will not be generated by some CPUs such as a CPU with no byte enable signal or a CPU for which all byte enable signals are always active during a read access For a Midas lab CPU board on which this kind of CPU is installed for example RTE V850E MA1 CB a control port for f
37. 00 7010H 1 Read Write o 10 5 16 o EXT 1O AMASK 23 16 specifies the address mask of the EXT BUS I O 1 EXT IO AMASK17 o EXT IO 8 o 9 exrio Amasker o EXLIO AMASKZ2 o EXLIO AMASKS o lt lt Cautions gt gt EXT IO AMASK 23 16 determines the address to be output to the EXT BUS for an access to the EXT BUS I O space that is for an access when the GBUS GCS4 signal is active For the correspondence of the GBUS address and EXT BUS address see Section 6 2 8 1 Bank Window When a 16 bit EXT BUS JEXT16 connector is used the setting of this register is not used for an access to the EXT BUS and the EXT MEM AMASK 23 16 register is used 45 RTE MOTHER A USER S MANUAL Rev 1 20 6 2 8 4 EXT BUS CPU Memory Space Bank Address Register EXTBUS_CORE_MEM_BANK_ADDR GCS2 0000 7020H Read Write o EXT CORE MEM BANKAi6 o EXT_CORE_MEM_BANKA 23 16 specifies the bank address of a non 1 EXT_CORE_MEM_BANKAI7 o DMA access to the EXT BUS memory space 2 BANKAt8 o 3 core MEM BANKA9 o 4 exr core MEM BaNKazo 5 EXT coRE mem Banka2 o EXT coRE MEM Banka22 o 7 Ext coRE pankazs o lt lt Cautions gt gt 1 EXT_CORE_MEM_BANKA 23 16 determines the address to be output to the EXT BUS for an access to the EXT BUS memory space that is not a DMA access that i
38. 0H PRINTER PPCS DATA DATA ECPAFIFO GCS2 0000 2010H DSR GCS2 0000 2020H GCS2 0000 2030H EPPADDR GCS2 0000 2040H EPPDATA to GCS2 0000 2070H GCS2 0000 3000H PRINTER ECPCS PPDATAFIFO TESTFIFO CNFGA GCS2 0000 3010H CNFGB GCS2 0000 3020H ECR TL16PIR552 Register Arrangement g C EPPADDR EPPDATA 2 PPDATAFIFO TESTFIFO rm 20 The XIN input of the TL16PIR552 is connected to the 22 1184 MHz clock The UART CH 0 UART CH 1 and PRINTER interrupts can be output to GINTO 3 0 via the interrupt controller See Section 6 2 7 Interrupt Control Circuits UART CH 0 is connected to the JSIO1 connector UART CH 1 is connected to the JSIO2 connector and PRINTER is connected to JPRT The TL16PIR552 is reset when the system is reset 20 RTE MOTHER A USER S MANUAL Rev 1 20 6 2 6 Audio Circuits The audio circuits perform stereo audio input output NEC uPD63310 is used for the A D and D A converter the resolution is 16 bits per channel and the maximum sampling rate is 48 kHz These circuits have been designed to maintain upward compatibility with the audio features installed in the conventional Midas lab RTE V831 PC and RTE V832 PC In the following explanation audio input is called recording and audio output is called playing The following figure shows a block diagram of the audio circuits LOCAL BUS IH INFOIHIT The uPD63310 has amplifiers in its input circuits which are used for microphone
39. 4 5VSB Leave this unconnected Leave this unconnected 5V 12V This is supplied to JGBUS JPCI1 2 and JISA1 2 This is required by PCMCIA1 2 when using a card for which 12 V is required as Vpp This is supplied to JPCI1 2 and JISA1 2 PW OK Leave this unconnected 5v This is supplied to JISA1 2 PS ON Leave this unconnected we di To connect only some of the power supplies carefully confirm the amount of power required by the boards you intend to connect and make sure that the amount of power supplied is sufficient If the amount of power supplied is insufficient a board failure may occur d When a non ATX standard power supply is used the SW POWER switch on the board and the switch connected to JPOWERSW cannot be used RTE MOTHER A USER S MANUAL Rev 1 20 5 12 LED The LEDs on this board are shown below 42 is suppli IDE 12V USBO Lights when 5 V power is supplied to the lower USB connector Reflects the control pe register contents See Section 6 2 9 2 POWER Control Register POWER CONTROL GCS2 0000 8020H Read Write USB1 Lights when 5 V power is supplied to the upper USB connector Reflects the control bd register contents See Section 6 2 9 2 POWER Control Register POWER CONTROL GCS2 0000 8020H Read Write IDE Lights when the hard disk installed on the IDE bus or in the PCMCIA slot is accessed PLAY REC Lights when the Audio function is operating For detai
40. 55 RTE MOTHER A USER S MANUAL Rev 1 20 6 3 4 PCI9080 The PCI9080 is a PLX Technology PCI bus bridge chip The PCI9080 data sheet is available from the PLX Technology home page http www plxtech com 6 3 4 1 PCI9080 Control Register The PCI9080 control register can be accessed during cycles when the GBUS GCS6 pin is set to active The control register on the PCI9080 for determining the action of the PCI9080 which is called the CFG register can be accessed by using this space The CFG register can be used to make the following settings e Correspondence between a GBUS address and a memory space address on the PCI bus e Correspondence between a GBUS address and an I O space address on the PCI bus e Size of the PCI bus space that can be accessed from the GBUS e Setting for generating a configuration cycle on the PCI bus Detailed setting related to the PCI bus or GBUS cycle DMA controller setting that can be transferred to the on chip PCI bus GBUS installed in the PCI9080 6 3 4 2 PCI Bus Memory Area An access when the GBUS GCS5 signal is set to active will be a PCI bus directed access to the PCI9080 Since the settings will differ when the CPU board does not support the GBUS GCS7 signal see Section 6 3 4 4 When the GCS7 Signal Is Not Supported A cycle at this time is controlled by a motherboard circuit so that bit 31 LA31 of the PCI9080 local side address is always Low As a result the PCI9080 settin
41. 6 2 7 1 Overview of Interrupt Resources A case in which back off occurs is described below Assume for example that a board referred to as A is inserted in the PCI bus and the internal configuration of this board consists of PCI9080 SRAM CPU just like the motherboard 57 RTE MOTHER A USER S MANUAL Rev 1 20 In this case the PCI bus can become deadlocked according to the following scenario 1 The CPU board begins an access to board A s SRAM 2 At the same time the board A s CPU board begins an access to the motherboard s SRAM 3 The motherboard s PCI9080 obtains the PCI bus mastership and begins an access to board A s SRAM on the PCI bus 4 Since board A s local bus is being used by the CPU board A s PCI9080 requests a retry termination for a cycle from the PCI bus 5 The motherboard s PCI9080 replies to the retry termination and relinquishes the bus mastership 6 Board A obtains the bus mastership and begins an access to the motherboard s SRAM on the PCI bus 7 The motherboard s PCI9080 requests a retry termination becomes its own local bus is being used by the CPU board 8 Board A s PCI9080 replies to the retry termination and relinquishes the bus mastership 9 Return to 3 To avoid this status in the PCI9080 a back off request is issued to the CPU when the kind of situation described above is detected If the CPU replies to this back off and relinquishes the bus mastership the deadlock described above c
42. 6 2 8 1 Bank Window The EXT BUS spaces include individual 16M byte memory I O spaces for the 32 bit EXT BUS JEXT32 connector and a 1M byte space for the 16 bit EXT BUS JEXT16 connector The bank method is used as the address expansion method to support cases in which space for the EXT BUS cannot be allocated on the CPU board This bank method allows the window size to be programmable variable to match the CPU board The addresses that are output to the EXT BUS are determined by the following equation EXT BUS address bit23 16 QBUS address bit23 16 amp address mask bank address amp address mask For bits corresponding to address mask bits that are 1 the value set as the bank address is output to the high order 8 bits of the EXT BUS address and for bits corresponding to address mask bits that are 0 the GBUS address is output Therefore data having consecutive 1 high order bits and consecutive 0 low order bits such as FOH is set as the address mask The bank window size is determined by the number of low order bits that are 0 When FFH which has no O bits is set as the address mask the bank window size will be 64K bytes When COH is set the bank window size will be 4M bytes Also since two address masks can be set with one for the memory space and one for the I O space separate bank window sizes can be set for memory and I O However the 16 bit EXT BUS JEXT16 only uses memory The bank address
43. A request is generated during recording when the FIFO has at least two bytes of data A DMA request to the GBUS becomes inactive either when the corresponding GDMAAK signal becomes active or after the next rising edge of GCLK for which the GWAITI signal of the write cycle to the FIFO is sampled High A DMA cycle ends following eight consecutive GCLK pulses after the GWAITI signal is sampled High and GDMARQ will not become active again within four GCLK pulses after the DMA cycle ends This is done to prevent a DMA overrun 21 RTE MOTHER A USER S MANUAL Rev 1 20 6 2 6 1 1 PD63310 Register GCS2 0000 40000H to GCS2 0000 401FH The uPD63310 register is allocated as follows For details see the uPD63310 data sheet Address Funcion De D be Dt oo GCS2 0000 4000H Address register Register number GCS2 0000 4010H Data register 22 RTE MOTHER A USER S MANUAL Rev 1 20 6 2 6 2 Audio Control Register AUDIO_CONT GCS2 0000 5000H Read Write 0 Stop playing audio 1 Play audio 1 Request interrupt when playing FIFO underflow occurs 1 Request interrupt when playing FIFO overflow occurs _ _ A A 1 Record audio 1 Request interrupt when recording FIFO underflow occurs 0 Do not request interrupt when recording FIFO overflow occurs 1 Request interrupt when recording FIFO overflow occurs 0 Do not reset audio circuits 1 Reset all audio circuits
44. CI The GBUS side local bus side for the PCI9080 address for an access to the memory space of the PCI bus will start from address 0000 0000H PCI9080 control register AOH address Local Bus Base Address Register for Direct Master to PCI Memory The GBUS side address for an access to the I O space of the PCI bus will be the exact middle address of the area for the GCS5 signal PCI9080 control register A4H address Local Base Address Register for Direct Master to PCI IO CFG By setting 1 for bit 13 I O Remap Select of the PCI control register ABH address PCI Base Address Remap Register for Direct Master to PCI Memory the high order 16 bits bit 16 to bit 31 of the PCI address during I O cycle will be all 0 as a result the I O space on the PCI bus will be 64K bytes in size 6 3 4 5 PCI Bus Configuration Area The area for I O access is used to access the PCI bus configuration area Configuration cycle address information is set in the PCI9080 control register ACH address PCI Configuration Address Register for Direct Master to PCI IO CFG Also bit 31 Configuration Enable of this control register must be set to 1 After this information and bit are set an access to the area for PCI bus I O access can access the PCI bus configuration space Since the PCI9080 control register must be overwritten for a configuration space access interrupts must be prohibited during a configuration space access when a multitasking application
45. CMCIA over current 1 Clear an interrupt request due to a PCMCIA over current A AA A NUT When the 16 bit EXT BUS JEXT16 connector is used the EXT BUS interrupt is connected to EXT_INTO 39 RTE MOTHER A USER S MANUAL Rev 1 20 6 2 7 8 Interrupt Edge Specification Register 1 INT EDGE1 GCS2 0000 6060H Read Write EX PCI_INTA_INTEDGE 0 An interrupt request due to the PCI s PCI1_INTB_INTEDGE2 PCI INTC INTEDGE 0 An interrupt request due to the PCI s 0 An interrupt request due to the PCI s 0 An interrupt request due to the PCI s 0 An interrupt request due to the PCI s ot 1 INTA pin is a level mode request 1 An interrupt request due to the PCI slot 1 INTA pin is an edge mode request ot 1 INTB pin is a level mode request 1 An interrupt request due to the PCI slot 1 INTB pin is an edge mode request ot 1 INTC pin is a level mode request 1 An interrupt request due to the PCI slot 1 INTC pin is an edge mode request ot 1 INTD pin is a level mode request 1 An interrupt request due to the PCI slot 1 INTD pin is an edge mode request ot 2 INTA pin is a level mode request Te 0 2 1 An interrupt request due to the PCI slot 2 INTA pin is an edge mode request 0 An interrupt request due to the PCI slot 2 INTB pin is a level mode request 1 An interrupt request due to the PCI slot 2 INTB pin is an edge mode request 0 An interrupt request due to the PCI slot 2 INTC pin
46. Cautions gt gt 1 The following table shows the relationship of the values set for MCLK_DIV 4 0 and the MCLK frequency and sampling rate Transferred MCLK MHz Sampling cycle KHz MCLK DIV 4 0 49 152MHz DIV 2 me eee 0 0 0 1 0 48 0KHz 38 4KHz 0 0 1 0 0 32 0KHz 27 5KHz 0 0 1 1 0 24 0KHz 21 3KHz 0 1 0 0 0 19 2KHz 17 5KHz 0 1 0 1 0 16 0KHz 14 8KHz 13 7KHz 12 8KHz 0 0 eo a 192 0KB S 153 6KB S 128 0KB S 109 7KB S 96 0KB S 85 3KB S 76 8KB S 69 8KB S 64 0KB S 59 1KB S 54 9KB S 51 2KB S 48 0KB S 45 2KB S 42 7KB S 40 4KB S 38 4KB S 36 6KB S 34 9KB S 33 4KB S 32 0KB S 30 7KB S 29 5KB S 28 4KB S 27 4KB S 26 5KB S 25 6KB S 24 8KB S 24 0KB S 23 3KB S 12 0KHz ing eoma makez 107KHz 10 1KHz 1 zs RE 2 341MHz 9 1KHz 0 1 0 0 2 234MHz 8 7KHz 0 1 0 1 2 137MHz 8 3KHz 0 1 966MHz 77KHz 1 0 0 0 1 890MHz 7 4KHz 1 1 0 0 1 1 820MHz 7 1KHz 1 1 0 1 0 1 755MHz 6 9KHz 1 1 0 1 1 1 695MHz 6 6KHz 1 1 1 0 0 1 638MHz 6 4KHz 1 1 1 0 1 1 586MHz 6 2KHz 1 1 1 1 0 1 536MHz 6 0KHz 1 1 1 1 1 1 489MHz 5 8KHz 5 0KHz 1 1 1 1 1 1 1 0 0 1 0 2 458MHz 9 6KHz 1 1 1 1 0 1 1 1 1 26 RTE MOTHER A USER S MANUAL Rev 1 20 6 2 6 5 Audio FIFO AUDIO_FIFO GCS2 0000 5030H Read Write This is a register for accessing the playing and recording FIFOs Writing to this register will be writing to the playing FIFO Re
47. E paar Pee cas ee Serial P arallel 1 F Audio In Out TL16PIR552 uP D63310 LOCAL BUS QCAL B EXT BUS Bridge Bridge SRAM Flash ROM Programmable 2MB 8MB InterruptC ontroller PCI PCI BUS16 BUS32 oe ER Bridge Ethernet P CI9080 PCLRHS 5882558 South Bridge M1523B ET A EN PCMCIA T EA EM MA 4 Interrupt Counter Controlle EIDE USB1 USBO AMES EC EA Secondary Primary EIDE o Speaker This chapter describes the hardware of the RTE MOTHER A board The following figure shows the configuration of the bus connections 6 1 GBUS GBUS is a bus that connects a bridge to the local bus and the PCI9080 bridge to the PCI bus on the RTE MOTHER A board This bus is accessed from both the CPU board and from the bus master on the PCI bus via the PCI9080 For information about the GBUS bus cycle format see Chapter 8 GBUS SPECIFICATIONS 6 1 1 GBUS Bus Mastership Arbitration GBUS is accessed from both the CPU board and from the bus master on the PCI bus Therefore bus arbitration is required The GBUS arbitration method differs according to the status of the GUSE_DIRECT_ACC signal on the GBUS If the GUSE_DIRECT_ACC signal is High the bus master that accessed the bus last is made to wait If the CPU board is made to wait the wait is applied by the GREADY signal of GBUS If the PCI9080 is made to wait it is made to wait without asserting an LHOLDA signal in r
48. GBLOCKO signal is valid for the GCSO SRAM space The GBLOCKt1 signal is valid for the GCS5 PCI bus memory and GCS7 PCI bus I O spaces The RTE MOTHER A motherboard has a function for supplying the equivalent functions of GBLOCK 1 0 according to a local bus control register setting See Section 6 2 9 8 Bus Lock Control Register BLOCK CONTROL GCS2 0000 8080H Read Write 79 RTE MOTHER A USER S MANUAL Rev 1 20 Inputioutput Output e Power supply Supplies 5 V 5 from the motherboard to the CPU board 12V Output Power supply Supplies 12 V 10 from the motherboard to the CPU board However if 12 V is not supplied to the motherboara it is also not supplied to the CPU board 80 RTE MOTHER A USER S MANUAL Rev 1 20 8 3 Pin Assignments The following table shows the GBUS pin assignments Reserve indicates a reserved pin and N C indicates that a pin is not connected o Signal name 412V GADDR2 GADDR6 GADDR8 GADDR12 GND GADDR18 GADDR22 GADDR24 GADDR28 GND GBEN1 GDATA31 GDATA27 GND GDATA21 GDATA17 GDATA15 GDATA11 GND GDATA5 GDATA1 GND GRESETI GND GCSO0 GCS4 Reserve GRD GHOLD GDMARQO GDMAAKO Reserve GND GINTO2 GETCO GETC4 Reserve o Signal name 12V GADDR3 GADDR7 GADDR9 GADDR13 V GADDR19 GADDR23 GADDR25 GADDR29 5V GBENO GDATA30 GDATA26 5V GDATA20 GDATA16 GDATA14 GDATA10 V GDATA4 GDATAO GW R GADS GCLK GCS1 GCS5 Reserve
49. GCS6 02EH 9080H Expansion ROM Base Register GCS6 030H 0000 0001H Interrupt Line Register CS6 03CH 00H Interrupt Pin Register CS6 03DH 00H Min_Gnt Register GCS6 03EH 04H PCI Max_Lat Register GCS6 03FH 80H Local Address Space 0 Range Register for PCI to Local Bus GCS6 080H FFE0 0000H Local Address Space 0 Local Base Address Remap Register GCS6 084H 0000 0001H Mode Arbitration Register GCS6 088H 13E4 0000H Big Little Endian Descriptor Register GCS6 08CH 0000 0000H Expansion ROM Range Register GCS6 090H FFF8 0000H Expansion ROM Local Base Address Remap Register and BREQo Control GCS6 094H 0000 0012H Local Address Space 0 Expansion ROM Bus Region Descriptor Register GCS6 098H 47C3 24C3H Local Range Register for Direct Master to PCI GCS6 09CH 8000 0000H Local Bus Base Address Register for Direct Master to PCI Memory GCS6 0A0H 0000 0000H Local Base Address Register for Direct Master to PCI IO CFG CS6 0A4H 8000 0000H PCI Base Address Remap Register for Direct Master to PCI Memory GCS6 0A8H 0000 2807H PCI Configuration Address Register for Direct Master to PCI IO CFG GCS6 0ACH 0000 0000H Local Address Space 1 Range Register for PCI to Local Bus GCS6 170H FFF8 0000H Local Address Space 1 Local Base Address Remap Register GCS6 174H 0000 0000H Local Address Space 1 Bus Region Descriptor Register GCS6 178H 0000 02C3H U U U U U U U e G 59 RTE MOTHER A USER S MANUAL Rev 1 20 6 3 5 Device Numbers PCI bus device numbe
50. Half Full value which was set for AUDIO_FIFO_HALF_LEVEL See Section 6 2 6 7 Audio FIFO_HALF_LEVEL Setting Register AUDIO_FIFO_HALF_LEVEL GCS2 0000 5050H Read Write PLAY FIFO HFULL is used as a criterion for transferring multiple data in a batch such as for a block transfer when data is transferred under software control without using a DMA transfer 8 REC FIFO EMPTY becomes 1 when the FIFO contains less than two bytes of data REC FIFO FULL becomes 1 when the amount of empty space in the FIFO is less than one byte relative to the maximum size of the recording FIFO which was set for AUDIO FIFO FULL LEVEL See Section 6 2 6 6 Audio FIFO FULL LEVEL Setting Register AUDIO FIFO FULL LEVEL GCS2 0000 5040H Read Write REC FIFO HFULL becomes active when the number of data items in the FIFO is greater than or equal to the recording FIFO s Half Full value which was set for AUDIO FIFO HALF LEVEL See Section 6 2 6 7 Audio FIFO HALF LEVEL Setting Register AUDIO FIFO HALF LEVEL GCS2 0000 5050H Read Write REC FIFO HFULL is used as a criterion for transferring multiple data in a batch such as for a block transfer when data is transferred under software control without using a DMA transfer 25 RTE MOTHER A USER S MANUAL Rev 1 20 6 2 6 4 Audio MCLKDIV Setting Register AUDIO_MCLKDIV GCS2 0000 5020H Read Write o o The MCLK frequency to be input to the 4PD63310 is determined by ONE lt lt
51. It also detects whether or not the board is installed in the PCI slot audio dma test directory This directory contains a program for testing the motherboard audio recording playing circuits DMA transfers are used for transferring audio data Two blocks are allocated as an audio data buffer When one block of data has been recorded playing begins while recording continues When recording playing is executed a fixed number of times the program stops audio soft test directory This directory contains a program for testing the motherboard audio recording playing circuits Although the contents are equivalent to those of audio dma test DMA transfers are not used for transferring audio data Instead the audio data is transferred under software control by using a Half Full interrupt 71 RTE MOTHER A USER S MANUAL Rev 1 20 beep_test directory This directory contains a program for testing the Beep tone when the speaker is connected to the JPANEL connector of the motherboard extbus16_test directory This directory contains a program for testing the functions of the JEXT16 connector on the motherboard A special purpose jig must be connected to the JEXT16 connector for this test The checks performed are an EXT BUS memory check and a check of interrupts from the EXT BUS extbus32_test directory This directory contains a program for testing the functions of the JEXT32 connector on the motherboard A special purpose jig must be connected to
52. LOW GBLOCK1 N C N C N C N C N C N C N C N C N C 412V a ES E alo o Y Ni N E EM 25 Er NEM 49 59 EM 69 EM 85 so as EUM tos 109 us 117 121 125 133 us 153 157 161 165 169 173 ELM o a The following connectors are used CPU board side connector straight gt KEL 8817 180 170L Motherboard side connector straight gt KEL 8807 180 1705 Motherboard side connector L angle gt KEL 8807 180 170L 81 RTE MOTHER A USER S MANUAL Rev 1 20 8 4 8 5 Processing of Unused Pins Signals that are not used as input signals to the GBUS motherboard can be unconnected on the CPU board because pull up or pull down processing is performed on the motherboard The following table shows signals that can be unconnected and the processing performed on the motherboard because they are unconnected Signal name GADDR 31 26 e When GADDR 31 26 are not used GADDR 31 26 can be unconnected by setting the GAHI_EN signal high or by disconnecting it In this case when the CPU is the bus master all bits of GADDR 31 26 are treated as 0 on the motherboard GWAITI e Pull up processing is performed GBLAST GBTERM GCS 7 0 GHLDA GBREQ GDMAAK 3 0 GINTI 1 0 GAHI_EN GUSE_DIRECT_ACC GCLK_LOW e Pull up processing is perfo
53. MCIA slots The data sheet for the RF5C396 is available from the Ricoh home page http www ricoh co jp 6 4 5 2 Addresses The addresses shown in the following table are used to access the RF5C396 PCI 1 0 0000 03E0H Index register PCI 1 0 0000 03E1H Data register 6 4 5 3 Hardware type Connections The various pins of the RF5C396 are connected as shown in the following table ros CO Fo iSAbuwipos 69 RTE MOTHER A USER S MANUAL Rev 1 20 6 5 PCMCIA Bus The PCMCIA bus is bridged as PCI bus gt ISA bus PCMCIA bus This section describes the PCMCIA bus 6 5 1 6 5 2 Slots PCMCIA slot 1 JPCMCIA1 is the SLOT O side of the PCMCIA controller RF5C396 and PCMCIA slot 2 JPCMCIA2 is the SLOT 1 side Power Supply For the power supplied to the PCMCIA slots either 12 V or 5 V can be supplied as VPP and either 5 V or 3 3 V can be supplied as VCC The ON OFF state of the power supply and the voltage are selected according to a register in the RF5C396 The following table shows the settings for the RF5C396 and the power supplied to the PCMCIA slots a o x Dv E Index 2FH Voltage supplied to PCMCIA slot Bito VCC pin VPP pin Bito o o o Bit4 Bit1 EAEN NES EEE ERA ERA Although it cannot be detected individually for each slot an over current state can be detected for the power supplied to the PCMCIA slots See Section 6 2 9 3 POWER Status Register
54. MOTHER A USER S MANUAL Rev 1 20 6 2 8 6 EXT BUS DMAO Memory Space Bank Address Register EXTBUS_DMAO_MEM_BANK_ADDR GCS2 0000 7040H Read Write EXT_DMAO MEM _BANKA16 o EXT DMAO MEM BANKA 23 16 specifies the bank address of an EXT DMA0 MEM _BANKA17 o access to the EXT BUS memory space according to DMA channel 2 EXT DMA0 MEM BANKA18 o EXT pMAo MEM _BANKA19 0 EXT DMAO MEM BANKA20 EXT DMAO MEM BANKA21_ EXT DMAO MEM BANKA22_ o EXT MEM BANKA23 o lt lt Cautions gt gt 1 EXT DMAO MEM BANKA 23 16 determines the address to be output to the EXT BUS for an access to the EXT BUS memory space when the EXT BUS DMAAKO signal is active that is when the GBUS GDMAAKO signal is active For the correspondence of the GBUS address and EXT BUS address see Section 6 2 8 1 Bank Window 6 2 8 7 EXT BUS DMAO I O Space Bank Address Register EXTBUS DMAO IO BANK ADDR 1 GCS2 0000 7050H Read Write o ExT_DMAO IO BANKA16 o EXT DMAO IO BANKA 23 16 specifies the bank address of an access EXT_DMAO_IO_BANKA17 0 to the EXT BUS I O space according to DMA channel 2 EXT_DMA0_IO_BANKA18 o 4 ext omao lo Bankazo o 5 exr_pmao Bankazi_ o ExT Dmao BANK o 7 _ 0 o Bankas o lt lt Cautions gt gt EXT DMAO IO BANKA 23 16 determines the address to be output to the EXT BUS for an access to the EXT BUS I O sp
55. OM RESET 0 The flash ROM RESET pin is set to inactive 1 The flash ROM RESET pin is set to active 1 FROM BUSY x 0 The flash ROM status is not BUSY 1 The flash ROM status is BUSY 2 unsa E poo i ef lt lt Cautions gt gt 1 FROM_RESET manipulates the flash ROM reset pin 2 FROM_BUSY is a read only bit It becomes 1 when the status of any one of the four flash ROM is BUSY 6 2 9 8 Bus Lock Control Register BLOCK_CONTROL GCS2 0000 8080H Read Write Bit RST SRAM_BLOCK 0 The bus lock for accessing SRAM is disabled 1 The bus lock for accessing SRAM is enabled PCI_BLOCK 0 The bus lock for accessing the PCI bus is disabled 1 i The bus lock for accessing the PCI bus is enabled lt lt Cautions gt gt 1 The GBUS GBLOCKO signal is the bus lock signal for SRAM However if no bus lock signal is output from the CPU SRAM_BLOCK should be used A logical OR operation is performed on the GBUS GBLOCKO and SRAM_BLOCK signals After 1 is set for SRAM_BLOCK if the CPU attempts to access SRAM the bus mastership is no longer passed to the PCI9080 and a bus lock state occurs for this and subsequent accesses To escape from the bus lock state set 0 for SRAM_BLOCK 2 The GBUS GBLOCK1 signal is the bus lock signal for the PCI bus However if no bus lock signal is output from the CPU PCI_BLOCK should be used A logical OR operation is performed on the GBUS GBLOCK1 and PCI BLOCK signals When 1 is set
56. ROUGH is set to 0 the EXT BUS DMAAK signal becomes active only during the DMA cycle signal should be used when set to 1 Since the timing according to which the EXT BUS DMAAK signal becomes active will be slower when DMAAK_THROUGH is set to 0 superfluous DMA cycles may be generated for some CPU boards when executing a DMA transfer from the CPU board to the EXT BUS D Unless there is a special reason not to the DMAAK_THROUGH 49 RTE MOTHER A USER S MANUAL Rev 1 20 6 2 9 Other Control Registers This section explains other registers on the local bus 6 2 9 1 SW1 Read Out Register SW1_RDOUT GCS2 0000 8000H Read Only This is a register for reading the SW1 status The following table shows the data format Data bus os os os SW1 1 corresponds to the SW1 1 switch 5 1 8 corresponds to the SW1 8 switch Also 0 is read when the relevant bit s switch is ON and 1 is read when it is OFF SW1 is only used for software No hardware control is switched according to the SW1 setting No specific use has been fixed for SW1 6 2 9 2 POWER Control Register POWER CONTROL GCS2 0000 8020H Read Write Function Er _ _ 3 1 Supply 5 V to USB channel 0 0 Do not supply 5 V to USB channel 1 1 Supply 5 V to USB channel 1 O uL ee eee 6 unused lt lt Cautions gt gt 1 USB channel 0 is the lower JUSB connector Channel
57. RTE MOTHER A USER S MANUAL Rev 1 20 RTE MOTHER A USER S MANUAL Rev 1 20 Midas lab RTE MOTHER A USER S MANUAL Rev 1 20 REVISION HISTORY Chapter Explanation of revision January 15 1999 foto Preliminaryversion May 31 1999 0 6 1 5 e Added the restriction to the explanation of GCS7 in the table corresponding to when the size of the GCS7 space differs from that of the GCS5 space e Added EXTBUS CONTROL to the table e Added Cautions 1 and 3 e Added section e Added section e Added section e Changed T19 to DMAAK gt DMARO 20 September 10 1999 00 e Changed the character strings of the connector diagram Changed the explanation of JP6 Added Caution 2 Changed the name of each bit from xxxLOW to xxxHIGH Changed the name of each bit from xxxLOW to xxxHIGH e Changed the 1 0 1 combination of BREQ_EN BREQ_NUM 1 0 to a prohibited setting e Added section Added the list of legacy devices e Added the table related to power supplies e Added a great deal of contents 10 EEPROM and added the serial EEPROM contents October 30 1999 20 e Added that If the CPU board cannot access to the motherboard by using a 32 bit cycle this CPU board cannot use USB functions Added test that the reading signatures from connected USB device 20 January 20 2000 aa First edition of English version T October 6 1999 1 Added the subsystem vendor device ID Added lan test
58. Rev 1 20 6 2 7 14 GINTOO Interrupt Enable Register 1 GINTOO INTEN1 GCS2 0000 6110H Read Write 6 2 7 15 GINTO1 Interrupt Enable Register 1 GINTO1_INTEN1 GCS2 0000 6130H Read Write 6 2 7 16 GINTO2 Interrupt Enable Register 1 GINTO2_INTEN1 GCS2 0000 6150H Read Write 6 2 7 17 GINTO3 Interrupt Enable Register 1 GINTO3_INTEN1 GCS2 0000 6170H Read Write Bit 0 Disable the interrupt due to the PCI slot 1 INTA pin 1 Enable the interrupt due to the PCI slot 1 INT 1 0 Disable the interrupt due to the PCI slot 1 INTB pin 1 Enable the interrupt due to the PCI slot 1 INT Disable the interrupt due to the PCI slot 1 INTC pin Enable the interrupt due to the PCI slot 1 INTC pi Disable the interrupt due to the PCI slot 1 INTD pin Enable the interrupt due to the PCI slot 1 INTD pin Gin_PCI2_INTC_INTEN O 1 O 1 0 Disable the interrupt due to the PCI slot 2 INTA pin 1 Enable the interrupt due to the PCI slot 2 INTA pin 0 Disable the interrupt due to the PCI slot 2 INTB pin 1 Enable the interrupt due to the PCI slot 2 INTB pin 0 Disable the interrupt due to the PCI slot 2 INTC pin 1 Enable the interrupt due to the PCI slot 2 INTC pin 0 Disable the interrupt due to the PCI slot 2 INTD pin 1 O 1 O 1 O 1 O T 0 1 Gin PCI2 INTD INTEN Enable the interrupt due to the PCI slot 2 INTD pin Disable the interrupt due to the EXT bus EXT INTO pin Enable the
59. TBUS DMA1 IO BANK ADDR 1 GCS2 0000 7070H Read Write o ExT_DMA1 IO BANKA16 o EXT_DMA1_IO_BANKA 23 16 specifies the bank address of an access EXT DMA1 IO 17 o to the EXT BUS I O space according to DMA channel 3 EXT DMA1 IO BANKA18 o 4 ext omar Bankazo o 5 ExT omar o Bav o ExT omar o Bankazz o 7 ext omar o Bankas lt lt Cautions gt gt EXT DMA1 IO BANKA 23 16 determines the address to be output to the EXT BUS for an access to the EXT BUS I O space when the EXT BUS DMAAK 1 signal is active that is when the GBUS GDMAAK3 signal is active For the correspondence of the GBUS address and EXT BUS address see Section 6 2 8 1 Bank Window When a 16 bit EXT BUS JEXT16 connector is used the setting of this register is not used and the setting of EXT_DMA1_MEM_BANKA 23 16 is used for an access to the EXT BUS However since no DMA cycle is defined for the 16 bit EXT BUS there is no method for distinguishing whether or not a cycle is a DMA cycle on the EXT BUS 48 RTE MOTHER A USER S MANUAL Rev 1 20 6 2 8 10 EXT BUS Status Register EXTBUS_STATUS GCS2 0000 7080H Read Only x 0 32 bit EXT BUS size is 32 bits 1 32 bit EXT BUS size is 16 bits lt lt Cautions gt gt 1 The EXT BUS has no dynamic bus sizing function Therefore when a board having a bus size of 16 bits is connected to the EXT BUS the EXT BUS cannot be accessed using
60. TC M5819P is connected to the M1523B IRQ8 input pin 63 RTE MOTHER A USER S MANUAL Rev 1 20 6 3 9 USB Controller M1523B SouthBridge On chip Implementation 6 3 9 1 Specifications The USB controller that is implemented on the M1523B SouthBridge chip conforms to USB 1 0 specifications and OpenHCl1 0a specifications It also has functions for handling a USB compliant keyboard or mouse as a compatible legacy device bit cycle this CPU board cannot use USB functions Because OpenHCl specification requires a 32 bit access to USB registers D If the CPU board cannot access to the motherboard by using a 32 6 3 9 2 Device Numbers For the device numbers that are assigned see Section 6 3 5 Device Numbers The vendor ID of this device configuration register is 10B9H and the device ID is 5237H 6 3 9 3 Addresses Since this is a device that is connected to the PCI bus the allocated addresses are determined by the value set in the register for the USB controller s configuration space 6 3 9 4 Interrupts The USB controller s INTA pin is internally routed inside the M1523B It can be routed to any interrupt input of the i8259 controller that is implemented on the M1523B chip according to an M1523B configuration register setting 6 3 9 5 Power Supply The ON OFF state of the 5 V power that is supplied to the USB connector is controlled by the control register of the local bus See Section 6 2 9 2 POWER Control
61. TER pin 1 Clear the interrupt request from the TL16PRI552 PRINTER pin 4 Unused 5 unused ed 0 Do not clear the interrupt request from the GBUS GINTIO pin 2 3 4 5 x x 1 Clear the interrupt request from the GBUS GINTIO pin 1 Clear the interrupt request from the GBUS GINTI1 pin EN Lulu x 0 Do not clear the interrupt request due to the ISA bus INTR pin 9 x x x 1 Clear the interrupt request due to the ISA bus INTR pin LAN_INTCLR PCI_PERR_INTCLR 0 Do not clear the interrupt request due to the occurrence of a parity error on 0 Do not clear the interrupt request due to the SB82558 INTA pin 1 Clear the interrupt request due to the SB82558 INTA pi the PCI bus 1 Clear the interrupt request due to the occurrence of a parity error on the PCI bus TOVRDY_INTCLR 0 Do not clear the interrupt request due to the occurrence of a time over ready 1 Clear the interrupt request due to the occurrence of a time over ready 14 ABORT_ERR_INTCLR 0 Do not clear the interrupt request due to the occurrence of an abort termination 1 Clear the interrupt request due to the occurrence of an abort termination 1 Clear the interrupt request due to the occurrence of a back off lt lt Cautions gt gt 1 INTCLR is a bit for clearing an interrupt request that is being maintained by an edge detection circuit When a level mode interrupt is selected for an interrupt resource for which an edge mode or
62. _INTA_INTRQ PCH_INTB_INTRQ PCH_INTC_INTRQ EXT INT3 INTRQ PCH INTD INTRO USBO OC INTRQ USB1 OC INTRQ PCMCIA OC INTRQ There is an interrupt request due There is no interrupt request due to the PCI s There is an interrupt request due There is no interrupt request due to the PCI s There is an interrupt request due to the PCI s There is no interrupt request due There is an interru pt request due There is no interrupt request due There is an interrupt request due to the PCI s There is no interrupt request due There is an interrupt request due There is no interrupt request due to the PCI sl There is an interrupt request due There is no interrupt request due to the PCI s There is an interrupt request due There is no interrup There is an interrup request due request due request due request due request due o the PCI s o the PCI s o the PCI s o the PCI s o the PCI s o the PCI s ot 1 INTA pin O o o 1 INTA pin 1 INT 1 INT 1 INT to the PCI slot 1 INTD B pin ot 1 INTB pin C pin lot 1 INTC pin D pin ot 2 INTA pin ot 2 INTA pin ot 2 INTB pin o the PCI slot 2 INTB pin o the PCI s o the PCI s o the EXT bus EXT o the EXT bus EXT INT3 pin 0 There is no interrupt request due to a USB1 over current 1 There is an interrupt request due to a USB1 over current 0 There
63. ace when the EXT BUS DMAAKO signal is active that is when the GBUS GDMAAK2 signal is active For the correspondence of the GBUS address and EXT BUS address see Section 6 2 8 1 Bank Window When a 16 bit EXT BUS JEXT16 connector is used the setting of this register is not used and the setting of EXT DMAO MEM BANKA 23 16 is used for an access to the EXT BUS However since no DMA cycle is defined for the 16 bit EXT BUS there is no method for distinguishing whether or not a cycle is a DMA cycle on the EXT BUS 47 RTE MOTHER A USER S MANUAL Rev 1 20 6 2 8 8 EXT BUS DMA1 Memory Space Bank Address Register EXTBUS_DMA1_MEM_BANK_ADDR GCS2 0000 7060H Read Write EXT DMA1 MEM _BANKA16 o EXT DMA1 MEM BANKA 23 16 specifies the bank address of an EXT DMA1 MEM BANKAi7 o access to the EXT BUS memory space according to DMA channel 3 EXT DMAi MEM BANKAT8 o EXT DMA1 MEM 19 0 EXT MEM BANKA20 EXT_DMA1_MEM BANKA21_ 0 EXT_DMA1_MEM BANKA22 o EXT_DMA1_MEM_BANKA23 lt lt Cautions gt gt 1 EXT_DMA1_MEM_BANKA 23 16 determines the address to be output to the EXT BUS br an access to the EXT BUS memory space when the EXT BUS DMAAK1 signal is active that is when the GBUS GDMAAKG3 signal is active For the correspondence of the GBUS address and EXT BUS address see Section 6 2 8 1 Bank Window 6 2 8 9 EXT BUS DMA1 lO Space Bank Address Register EX
64. addresses shown in the following table are used to access the RTC PCI 1 0 0000 0070H CMOS RAM Address Port PCI I O 0000 0071H CMOS Data Register Port Address 70H is multiplexed with a register that is implemented within the M1523B chip 6 4 4 ISA Slots The motherboard has two slots for a 16 bit ISA board 6 4 4 1 Power Supply 5 V 5 V 12 V and 12 V power are supplied to each ISA slot Also when 5 V 12 V or 12 V power is not supplied to the motherboard it is also not supplied to the ISA slots 6 4 4 2 Hardware type Connections Both of the ISA slots are connected as follows e Although IRQ3 to IRQ7 IRQ9 to IRQ11 IRQ14 and IRQ15 can be used for interrupts since IRQ3 to IRQ5 IRQ7 IRQ11 and IRQ14 are also connected to the PCMCIA controller RF5C396 they must be shared e Although DRQO to DRQ3 and DRQ4 to DRQ7 can be used for DMA lines since DRQ7 is also connected to the PCMCIA controller RF5C396 it must be shared e The frequency of the OSC signal is 14 31 MHz e Either 1 2 the frequency of the OSC signal or 1 2 1 3 1 4 1 5 or 1 6 the frequency of the PCI clock 33 33 MHz can be selected for the CLK signal This option is selected according to the M1523B configuration register 68 RTE MOTHER A USER S MANUAL Rev 1 20 6 4 5 PCMCIA Controller RF5C396 6 4 5 1 Specifications The RF5C396 is a Ricoh PCMCIA controller LSI chip It is PCMCIA2 1 compliant and JEDA4 2 compliant and supports two PC
65. ading from this register will be reading from the recording FIFO Reading and writing should be performed according to 16 bit accesses An odd numbered access to this register will be data for the left channel and an even numbered access will be data for the right channel Therefore one set of 32 bit stereo data is transferred by using two accesses Also to use DMA to transfer data specify this register as the address to be DMA transferred Data that is written during an overflow state is ignored 6 2 6 6 Audio FIFO FULL LEVEL Setting Register AUDIO FIFO FULL LEVEL GCS2 0000 5040H Read Write EN PLAY FIFO FULL LEVELO The size maximum number of bytes of the playing FIFO is set in PLAY FULL LEVELI PLAY_FIFO_FULL_LEVEL 7 0 2 PLAY_FIFO_FULL_LEVEL2 Playing FIFO size bytes PLAY_FIFO_FULL_LEVEL 7 0 1 The size maximum number of bytes of the recording FIFO is set in REC FIFO FULL LEVEL 7 0 12 Recording FIFO size bytes REC FIFO FULL LEVEL 7 0 1 6 8 10 o N 1 1 wo sls a aja AJOJN lt lt Cautions gt gt 1 The values set in PLAY_FIFO_FULL_LEVEL 7 0 and REC_FIFO_FULL_LEVEL 7 0 must be odd numbers 2 The minimum setting value for PLAY_FIFO_FULL_LEVEL 7 0 and REC FIFO FULL LEVEL 7 0 is 01H and the maximum setting value is FDH Also the following equation shows the relationship between the setting value and FIFO size bytes FIFO size bytes Setti
66. aits may change according to the status of the GCLK_LOW signal of the GBUS Also each cell in the following table shows two numbers of waits separated by The first number indicates the number of waits for a single cycle or for the first micro cycle of a burst cycle The second number indicates the number of waits for the second and subsequent micro cycles of a burst cycle When different resources are accessed consecutively one additional wait than the number shown in the following table may be inserted for a single cycle or the first micro cycle of a burst cycle For the kinds of resources that correspond to each wait type see the following section Number of waits Wait type MID Pros ewaiewait 5waiv6wait 5waivswait 4Wai SWait The numbers shown in the above table when the Wait type is PPCS are the minimum number of waits Additional waits may be requested according to the resource to be accessed 17 RTE MOTHER A 6 2 2 List of Resources USER S MANUAL Rev 1 20 The following table lists the resources on the local bus For information about the Wait type in the following table see the previous section section SRAM GCS0 0000 0000H to GCS0 001F FFFFH SRAM Flash ROM GCS1 0000 0000H to GCS1 007F FFFFH FAST UARTO TL16PIR552 GCS2 0000 0000H to GCS2 0000 007FH FAST UART1 TL16PIR552 PRINTER PPCS TL16PIR552 PRINTER ECPCS TL16PIR552 uPD63310 register AUDIO_CONT AUDIO_STATUS AUDIO_MCLKDIV
67. an be avoided If the GBUS GUSE_DIRECT_ACC signal is High on the motherboard a motherboard circuit implements support for this back off Therefore the kind of deadlock described above will not occur However if the GUSE_DIRECT_ACC signal is Low back off cannot be supported and an error will occur 6 3 4 8 Access to the GBUS from the PCI Bus When the bus master on the PCI bus accesses a resource on the GBUS SRAM on the local bus or resource on the CPU board the PCI9080 must be configured so that an address on the local bus becomes a specific value Also when the bus master on the PCI bus accesses SRAM on the motherboard the correspondence between an address on the PCI bus and a CPU address on the CPU board depends on a PCI9080 setting See Section 6 1 6 GBUS Memory Map Access from the PCI Bus 58 RTE MOTHER A USER S MANUAL Rev 1 20 6 3 4 9 Initial Values The PCI9080 control register is initialized as follows by a serial EEPROM that is installed when the motherboard is shipped from the factory Since these initial values are set to suit a broad spectrum of typical devices these values must be changed according to the type of connected CPU board or according to the contents of the applications to be run Setting value PCI Configuration ID Register GCS6 000H 0030 1410H PCI Revision ID Register GCS6 008H 00H Class Code Register GCS6 009H FF FFFFH Subsystem Vendor ID Register GCS6 02CH 10B5H Subsytem ID Register
68. begins In this state when data is written to the FIFO a DMA request is asserted When REC is set to 0 a DMA request is immediately de asserted Therefore if any data had remained in the FIFO at that time it will not be transferred and will remain in the FIFO Also the fetching of audio data continues until a 16 bit data division and when that data fetching ends and the data is written to the FIFO the REC DOING bit of the AUDIO STATUS register becomes 0 After REC has been set to 1 if REC is set to 0 before recording begins the REC DOING bit immediately becomes 0 However in this case recording data may end up remaining in the FIFO depending on the timing The 1PD63310 playing circuits and recording circuits are all reset by AUDIO RESET The FIFOs are also flushed Besides the AUDIO RESET signal there are functions for resetting the playing circuits and recording circuits separately See Section 6 2 6 9 Audio Control Register 2 AUDIO CONT2 GCS2 0000 5070H Read Write 23 RTE MOTHER A USER S MANUAL Rev 1 20 6 2 6 3 Audio Status Register AUDIO_STATUS GCS2 0000 5010H Read Only Write Only 0 No audio is being played 0 No playing FIFO underflow occurred 0 No playing FIFO overflow occurred MEM 0 Playing FIFO is not empty 1 Playing FIFO is empty 0 Playing FIFO is not half full 0 Playing FIFO is not full A A ss I 0 No audio is being recorded 1 Audio is being recorded 0 N
69. ceeds 10 milliseconds A time over ready that is generated by an access to the PCI bus is generated when the entire bus cycle exceeds 10 milliseconds and the GREADY signal remains asserted until that bus cycle ends 14 RTE MOTHER A USER S MANUAL Rev 1 20 6 1 5 GBUS Memory and I O Map Access from the CPU Board Memory and I O are allocated according to the GCS 7 0 signals from the CPU board The following table shows the correspondence between the GCS 7 0 signals and the resources that are accessed If the CPU on the CPU board has an I O space you should allocate any space for which I O appears in the recommended space column of the table to an I O space GCSO0 Memory 2M bytes SRAM on the local bus Can also be accessed from the bus master on the PCI bus l O on the local bus GCS1 Memory 8M bytes e Flash ROM on the local bus This space can be mapped to a Boot ROM space according to Switch settings on the CPU board and the system can be booted from flash ROM Signal Recommende Minimum Maximum 9 d Accessed resources and remarks name range range space e Abus lock can be applied by the GLOCKO signal or by control from GCS2 luo 64K bytes Related to control registers on the local bus GCS3 Memory 64K bytes 16M bytes EXT BUS memory space When a board is connected to the JEXT32 connector the memory space of the connected board can be accessed from this space The maximum area size is 16M bytes When a
70. chip e PCI ISA bridge function e IDE controller e SMM function e Stop clock control e APM function e USB controller e Distributed DMA function e Interrupt controller function 18259 subset x 2 e Timer counter function i8254 PS 2 type keyboard mouse controller The RTE MOTHER A motherboard does not support the power management related functions SMM Stop clock APM 6 3 8 2 Device Numbers For the device numbers that are assigned see Section 6 3 5 Device Numbers The vendor ID of this device configuration register is 10B9H and the device ID is 1523H 6 3 8 3 Configuration Functions The following items can be configured summary according to the M1523B configuration space register on the PCI bus e Enabling disabling of write post function or line buffer of PCI ISA bridge function e ISA bus clock e ISA bus cycle timing e O recovery time e Enabling disabling of on chip IDE controller e Enabling disabling of on chip keyboard interface e Switching between PS 2 mouse and AT mouse Enabling disabling of DMA controller high address e Interrupt routing e PCI bus interrupt line mode e Power management control e Distributed DMA functions e IDE USB controller IDSEL address e Write only register s write data reading function 62 RTE MOTHER A USER S MANUAL Rev 1 20 6 3 8 4 Hardware type Connections The hardware type connections to the M1523B chip are as follows e The on chip keyboard and
71. connected The RTE MOTHER A motherboard has no flyby DMA feature 88 RTE MOTHER A 9 3 Data Bus Connection 9 3 1 16 Bit Data Bus CPU Reference Cycle EXT BUS Memory Space Access Address 4n 0 and or 4n 1 32 16Bit High EXT BUS D 31 16 CPU 0115 0 0115 0 Cycle EXT BUS I O Space Access Address 4n 0 and or 4n 1 32 16Bit High RTE PC User Board EXT BUS D 31 16 User Board D 15 0 Cycle Flyby DMA 32 16Bit High EXT BUS D 31 16 RTE PC CPU D 15 0 User Board Cycle EXT BUS Memory Space Access Address 4n 0 and or 4n 1 32 16Bit Low EXT BUS D 31 16 RTE PC CPU D 15 0 Cycle EXT BUS I O Space Access Address 4n 0 and or 4n 1 32 16Bit Low User Board EXT BUS D 81 16 User Board D 15 0 D 15 0 Cycle Flyby DMA 32 16Bit Low EXT BUS D 31 16 User Board D 15 0 USER S MANUAL Rev 1 20 Cycle EXT BUS Memory Space Access Address 4n 2 and or 4n 3 32 16Bit High EXT BUS D 31 16 User Board D 15 0 D 15 0 Cycle EXT BUS Memory Space Access Address 4n 2 and or 4n 3 32 16Bit Low EXT BUS D 31 16 RTE PC CPU D 15 0 Cycle EXT BUS I O Space Access Address 4n 2 and or 4n 3 32 16Bit Low User Board EXT BUS D 81 16 User Board D 15 0 DI15 0 89 RTE MOTHER A 9 3 2 Cycle EXT BUS Memory Space Access Address 4n 0 and or 4n 1 and or 4n 2 and or 4n 3 32 1 6Bit
72. connector after the user is prompted to do so by a message lan_test directory This directory contains a program for writing the LAN s MAC address to the serial EEPROM that is connected to the LAN controller SB82558 and then verifying that MAC address and a program for reading the LAN controller s vendor device ID pci_sram_test_mb directory This directory contains a program that is a companion to a program for checking access to common RAM SRAM on the motherboard from the bus master on the PCI bus pcmcia test directory This directory contains a program for testing the functions of the JPCMCIA1 and JPCMCIA2 connectors on the motherboard The functions that are tested are the switching of the VCC and VPP power supplies the generation of an over current interrupt an interrupt due to a change in the card status an access to the attribute space and an access to the memory space A special purpose PCMCIA card IO DATA s PCM 2M is required to test the access to the attribute space and access to the memory space printer_uart_test directory This directory contains a program for testing the functions of the JSIO1 JSIO2 and JPRT connectors on the motherboard A special purpose jig must be connected to these connectors for this test rte timer int test directory This directory contains a program for generating interrupts according to the GINTI 1 0 signals that are output from the RTC and timer 8254 on the motherboard and from the CPU boa
73. d as bidirectional in the table change direction depending on the bus cycle status Also signals described as input output change direction depending on whether the bus master is the CPU board or motherboard The direction written first is the signal direction when the CPU board is the bus master and the direction written second is the signal direction when the motherboard is the bus master A GBUS signal is a 5 V TTL level signal The motherboard is always little endian input output GCLK Input GBUS synchronization clock The maximum frequency is 33 33 MHz and the minimum frequency is 10 0 MHz The GBUS operates synchronized with the rising edge of this clock On the motherboard this clock is terminated at 330 Q with respect to 5 V and GND Therefore the circuit on the CPU board must be able to drive this resistance If the GCLK frequency is less than 16 67 MHz GCLK_LOW goes low In this way the motherboard can adjust the number of waits Since a Phase Lock Loop PLL zero delay buffer is used for this signal when the GCLK frequency is changed the motherboard must not be accessed for at least 1 ms after the frequency has been changed to allow the PLL to be locked GRESETI Input GBUS reset signal When a reset occurs on the CPU board this signal goes low The motherboard is reset by this signal as well as by a power on reset or a reset due to the reset switch GRESETO Output This signal goes low when a motherboard reset occurs T
74. d by M1523B which is a SouthBridge chip See Section 6 4 4 ISA Slots 5 V 12 V 5 V and 12 V power are supplied However this is limited to when the relevant power is supplied to JPOWER1 IRQ3 to IRQ7 IRQ9 to IRQ11 IRQ14 and IRQ15 can be used as interrupt lines However the interrupt lines are shared with the PCMCIA card DMAO to DMA3 DMAS and DMA6 can be used for DMA transfers 5 16 PCMCIA Slots JPCMCIA1 JPCMCIA2 These are connectors for inserting PCMCIA cards See Section 6 5 PCMCIA Bus They are RTE MOTHER A USER S MANUAL Rev 1 20 controlled by RFC5C396 which is on the ISA bus PCMCIA2 1 JEIDA4 2 compliant cards having 16 bit 5 V and 3 3 V specifications can be used To use a memory card for which 12 V is required as Vpp 12 V must be supplied to JROWER1 The power supplied to a PCMCIA slot is turned ON and OFF by controlling the controller RFC5C396 An over current state can be read by using a local bus register see Section 6 2 9 3 POWER Status Register POWER_STATUS GCS2 0000 8030H Read Only and an interrupt can be generated by generating an over current state see Section 6 2 7 1 Overview of Interrupt Resources JPCMCIA1 corresponds to SLOT 0 of the controller RFC5C396 and JPCMCIA2 corresponds to SLOT 1 F The JPCMCIA1 2 connectors do no support the CardBus specifications 5 17 Keyboard Mouse Connector JKEY_MOUSE The JKEY_MOUSE connector is used for connecting a PS2 compatible k
75. ddress Allocated resource Common RAM SRAM on the motherboard same area as 0080 0000H to 0000 0000H to 0007 FFFFH 0087 FFFFH Part of common RAM is also allocated here so that it can be accessed by the bus master of the ISA bus 007F E000H to 007F EFFFH USB controller 007F FEOOH to 007F FEFFH RTE V832 PC that is installed in the PCI slot 007F FFOOH to 007F FFFFH PCI9080 register 0080 0000H to 009F FFFFH Common RAM SRAM on the motherboard 0200 0000H to 03FF FFFFH Aiea for accessing memory on the CPU board when the CPU board supports direct access FFF8 0000 to FFFF FFFFH RTE V832 PC that is installed in the PCI slot FFOOH to FFFFH PCI9080 register Interrup 7 RTE MOTHER A USER S MANUAL Rev 1 20 7 2 LAN Coniroller To use the SB82558 LAN controller obtain the SB82558 driver from manufacturer of the real time OS or middleware Note the following points when porting the obtained driver for use with the RTE MOTHER A motherboard The MAC address can be obtained from the serial EEPROM that is connected to the LAN controller This method is described later e The work area for providing LAN controller command packets will be a common RAM SRAM area on the motherboard When setting the address of this work area for the LAN controller or when writing data in command packets the work area address in the address space of the PCI bus will be specified However the address when t
76. de local bus side for the PCI9080 address of an access to the I O space of the PCI bus will start from address 8000 0000H PCI9080 control register A4H address Local Base Address Register for Direct Master to PCI IO CFG Also the GBUS side address range will be the address range allocated to the PCI bus memory area PCI9080 control register 9CH address Local Range Register for Direct Master to PCI Since this address range setting is also valid for an access to the memory space of the PCI bus a memory range is set because the memory range is larger By setting 1 for bit 13 I O Remap Select of the PCI control register ABH address PCI Base Address Remap Register for Direct Master to PCI Memory the high order 16 bits bit 16 to bit 31 of the PCI address during an I O cycle will be all 0 as a result the I O space on the PCI bus will be 64K bytes in size 56 RTE MOTHER A USER S MANUAL Rev 1 20 6 3 4 4 When the GCS7 Signal Is Not Supported If the CPU board does not support a space according to the GBUS GCS7 signal an access to the PCI I O space will also be performed by using the GCS5 space In this case the first half of the GCS5 space will be allocated for PCI memory space use and the second half will be allocated for PCI I O space use The first half of the area that the CPU board allocates to the GCS5 space is set for the address range PCI9080 control register 9CH address Local Range Register for Direct Master to P
77. e is an interrupt request due to the PCI9080 LSERR pin 0 There is no interrupt request due to the occurrence of a parity error on the PCI bus 1 There is an interrupt request due to the occurrence of a parity error on the PCI bus 0 There is no interrupt request due to the occurrence of a time over ready 1 There is an interrupt request due to the occurrence of a time over ready 0 There is no interrupt request due to the occurrence of an abort termination 1 There is an interrupt request due to the occurrence of an abort termination 1 There is an interrupt request due to the occurrence of a back off lt lt Cautions gt gt 1 All INTRQ signals are common to all GINTO 3 0 pins Also the INTRQ signals that are read from this register are the signals before they are masked by the controller Therefore to specify the resource that is requesting the interrupt for GINTO 3 0 a logical AND operation must be performed on the contents of the interrupt status registers and the contents of the interrupt enable registers that are set individually for the GINTO 3 0 pins 2 An interrupt request from the AUDIO pin may be due to multiple interrupt sources such as a FIFO overflow or underflow 3 An interrupt request due to the PCI9080 LINTo pin is the result of multiple interrupt sources combined within the PCI9080 See Section 6 3 4 PCI9080 4 An interrupt request due to the ISA bus INTR pin is the source of an interrupt that is r
78. e signals is determined by GW R GADS Input output GBUS address strobe signals If this signal is sampled low on the rising edge of GCLK it indicates the start of a bus cycle The motherboard ignores GADS if none of the chip select signals GCS 7 0 is active GREADY Output input GBUS ready signal If this signal is sampled low and GWAITI is sampled high on the rising edge of GCLK during a micro cycle it indicates the end of the micro cycle The motherboard generates a time over ready when the CPU board accesses the motherboard This is done to avoid a collision with a GREADY signal GWAITI Input Wait request signal This signal is sampled on the rising edge of GCLK If the CPU board cannot support a cycle with few waits the CPU board samples GWAITI low according to the GREADY sample timing so that the motherboard cannot handle GREADY as a ready signal even though it is low at the time Usually this signal is used if the CPU board cannot support zero wait burst See Section 8 6 3 GWAITI This signal is valid only in a cycle in which the CPU board is the bus master GBLAST Input output Bus cycle completion notification signal This signal is sampled on the rising edge of GCLK This signal is asserted low by the bus master when a micro cycle that completes the bus cycle starts The bus cycle is completed when the low level of GBLAST the low level of GREADY and the high level of GWAITI are sampled on the rising edge of GCLK
79. eenWRoycles 20 T14 WRdatadelaytime Tis WRdatahodtime WRREADYWAITsetuptime o WRREADYsetuptime Ss o WRREADYhodtime o JEXT16 Bus AC Specifications 95 RTE MOTHER A Memo RTE MOTHER A User s Manual USER S MANUAL Rev 1 20 M881MNLO1 Midas lab 96
80. equested for the CPU INTR pin in a PC AT compatible DOS V machine Interrupt sources are combined within the M1523B SouthBridge chip See Section 6 3 8 M1523B SouthBridge 5 Aninterrupt request due to the ISA bus NMI pin is the source of an interrupt that is requested for the CPU NMI pin in a PC AT compatible DOS V machine Interrupt sources are combined within the M1523B SouthBridge chip See Section 6 3 8 M1523B SouthBridge 6 An interrupt request due to the PCI9080 LSERR pin is the result of multiple interrupt sources combined within the PCI9080 See Section 6 3 4 PCI9080 7 PCI PERR INTRQ is an interrupt request that is generated when a parity error is reported according to the PERR signal on the PCI bus Since the PCI bus master may replace a parity error with an SERR signal on the PCI bus PCI PERR INTRQ may be generated together with P9 LSERR INTRQ 8 ABORT ERR INTRQ and BACKOFF ERR INTRQ are errors that are generated in relation to PCI PERR INTRQ7 13 TOVRDY INTRQ ABORT ERR INTRG BACKOFF ERR INTRQ 5 33 RTE MOTHER A USER S MANUAL Rev 1 20 PCI bus access For details see Section 6 3 4 6 Abort Error and Section 6 3 4 7 Back Off Error 34 RTE MOTHER A USER S MANUAL Rev 1 20 6 2 7 3 Interrupt Clear Register 0 INT_CLEARO GCS2 0000 6010H Write Only 0 unused AA ed 2 unused AA AAA 0 Do not clear the interrupt request from the TL16PRI552 PRIN
81. er M 1523B SouthBridge On chip Implementation 6 3 10 1 Bus Master Controller 1523B SouthBridge On chip I mplementation 65 6 47 ISA BUS 6 4 1 ISA Bus connected Devices 6 4 2 M1523B On chip Legacy Devices nene tenen tenente tt ttn te ten tenete nette t tenens 64 3 RTC Real Time Clock M 5819 aiias item ca n e n P Oa i a DR i E UL MEET AO 6 4 5 PCMCIA Controller RF 5C396 6 55 4034 h 482 tse Le eo 6 5 T NN 6 5 2 Power Supply s o nete eI e tetra e RD eee UE EUER D Ea ede c eed Credis Ts SOFTWARE ii EM 7 1 Sample Programs 7 1 1 Precautions Concerning the Sample Programs 7 1 2 Overview of Sample Programs eee nennt tenen tenen ttt tenente nett t tenens 7 1 3 Sample Program Resource 7 2 LAN Controller 7 3 General Precautions 8 GBUS SPECIFICATIONS 5 oi conor a n 76 821 Terminology eR E Late Re dt did 76 8 1 1 CPU Board and Motherboard sse eene 76 RTE MOTHER A USER S MANUAL Rev 1 20 8 1 2 Bus Cycle ANd Micro Cydle sss nee tenente tenen tenen ttt tenente nte te tentent annann nenne aaa 76 9 2 Sighialssiii i RR A oe SE e e 76 8 3
82. esponse to the LHOLD signal asserted by the PCI9080 When the GUSE_DIRECT_ACC signal is High neither the CPU board nor the PCI9080 suffer much performance loss as long as accesses do not collide If the GUSE DIRECT ACC signal is Low HOLD based bus arbitration is performed If an LHOLD signal is asserted as a bus mastership request from the PCI9080 a GHOLD signal is asserted on the GBUS If GHLDA is asserted from the CPU board in response to this the PCI9080 begins GBUS access When the GUSE DIRECT ACC signal is Low as long as the 13 RTE MOTHER A USER S MANUAL Rev 1 20 6 1 4 CPU board has no special arbitration circuit the CPU processing efficiency will be lower than when the GUSE_DIRECT_ACC signal is High because the CPU will be stopped by a HOLD each time the PCI9080 accesses the bus However if the CPU board has resources that can be accessed from the PCI bus and this access is permitted the GUSE DIRECT ACC signal must be set to Low Temporary Release of GBUS Bus Mastership The burst length frequency on the GBUS is not limited Therefore once the bus master on the PCI bus obtains the GBUS bus mastership it may not relinquish that bus mastership for a long time Taking this possibility into consideration you can cause the bus mastership to be relinquished to the PCI9080 under fixed conditions The conditions at this time can be selected under program control from among several choices You can also cause the bus mas
83. eyboard and mouse It is controlled by M1523B which is a SouthBridge chip See Section 6 4 2 M1523B On chip Legacy Devices The lower connector is for the keyboard and the upper connector is for the mouse The pin arrangement of the connector is shown below The 5 V on the motherboard is always supplied for the 5 V power supply 5 18 USB Connector JUSB JUSB is the Universal Serial Bus USB root HUB connector It is controlled by M1523B which is a SouthBridge chip See Section 6 3 9 USB Controller M1523B SouthBridge On chip Implementation The pin arrangement of the connector is shown below Power is supplied to the USB connector by setting a local bus register See Section 6 2 9 2 POWER Control Register POWER CONTROL GCS2 0000 8020H Read Write An over current state can be read by using a local bus register see Section 6 2 9 3 POWER Status Register POWER STATUS GCS2 0000 8030H Read Only and an interrupt can be generated by generating an over current state see Section 6 2 7 1 Overview of Interrupt Resources lVcc 2 Data 3 Data 4 Ground RTE MOTHER A USER S MANUAL Rev 1 20 5 19 Serial Connectors JSIO1 JSIO2 JSIO1 and JSIO2 are RS 232C interface connectors controlled by a serial controller TL16PIR552 connected to the local bus See Section 6 2 5 UART PRINTER TL16PIR552 GCS2 0000 0000H to GCS2 0000 302FH The shape of the JSIO1 connector is the general D SUB 9 pin RS 232C
84. for PCI BLOCK the PCI9080 LLOCK pin becomes active This causes a bus lock state to occur for subsequent accesses to the PCI bus To escape from the bus lock state set 0 for PCI BLOCK Since a bus lock cycle on the PCI bus is set as a read modify write qcle the following sequence should be performed Set 1 for PCI BLOCK gt Read cycle for the PCI bus gt Write cycle for the PCI bus gt Set 0 for PCI BLOCK 53 RTE MOTHER A USER S MANUAL Rev 1 20 6 2 9 9 TOVRDY LED Clear Register TOVRDY LED CLR GCS2 0000 8090H Write Only When data is written to this register the TOVRDY LED goes off See Section 6 1 4 Time Over Ready 6 2 9 10 ABORT LED Clear Register ABORT_LED_CLR GCS2 0000 80A0H Write Only When data is written to this register the ABORT LED goes off See Section 6 3 4 6 Abort Error 6 2 9 11 BACKOFF LED Clear Register BAFCKOFF LED CLR GCS2 0000 80B0H Write Only When data is written to this register the BACKOFF LED goes off See Section 6 3 4 7 Back Off Error 54 RTE MOTHER A USER S MANUAL Rev 1 20 6 3 PCI Bus The PCI bus of the RTE MOTHER A motherboard conforms to PCI standards 2 1 An access to the PCI bus from the CPU board is performed via the PCI9080 6 3 1 6 3 2 6 3 3 Bus Arbitration The round robin method is used for bus arbitration of the PCI bus and the priority rotates according to the following sequence PCI9080 Interrupt acknowledge cycle ge
85. from all resources 1 Enable disable interrupt according to the bit for the individual resource eem mee E yy 1 Enable the interrupt from the TL16PRI552 UARTO pin Pei er oie 0 Disable the interrupt from the TL16PRI552 UART1 pin 1 Enable the interrupt from the TL16PRI552 UARTI pin Pr etic e merna ror ne Tisensszeantengn 1 Enable the interrupt from the TL16PRI552 PRINTER pin 0 Disable the interrupt from the AUDIO pin 1 Enable the interrupt from the AUDIO pin 0 Disable the interrupt due to the PCI9080 LINTo pin 1 Enable the interrupt due to the PCI9080 LINTO pin Disable the interrupt due to the GBUS GINTIO pin 4 Gln_GINTIO_INTEN Enable the interrupt due to the GBUS GINTIO pin n_ISAINTR_INTEN Disable the interrupt due to the ISA bus INTR pin Enable the interrupt due to the ISA bus INTR pin Gin ISANMI INTEN Disable the interrupt due to the ISA bus NMI pin Enable the interrupt due to the ISA bus NMI pin n P9 LSERR INTEN Disable the interrupt due to the PCI9080 LSERR pin Enable the interrupt due to the PCI9080 LSERR pin bus 1 Enable the interrupt due to the occurrence of a parity error on the PCI bus 13 TOVRDY INTEN 0 1 Enable the interrupt due to the occurrence of a time over ready ABROT ERR INTEN 0 Disable the interrupt due to the occurrence of an abort termination 1 Enable the interrupt due to the occurrence of an abort termination 0 lt lt Cautions gt gt
86. g for the GBUS side local bus side for the PCI9080 address of an access to the memory space of the PCI bus will start from address 0000 0000H PCI9080 control register AOH address Local Bus Base Address Register for Direct Master to PCI Memory Also the GBUS side address range will be the address range that the CPU board allocated to the GBUS GCS5 signal PCI9080 control register 9CH address Local Range Register for Direct Master to PCI Although this address range setting is also valid for an access to the I O space of the PCI bus a memory range normally is set because the memory range is larger The high order PCI addresses from this address range are set for the PCI control register A8H address PCI Base Address Remap Register for Direct Master to PCI Memory When a multitasking application performs a PCI access for which the PCI Base Address Remap Register for Direct Master to PCI Memory must be overwritten processing for saving this control register is required for each task 6 3 4 3 PCI Bus I O Area An access when the GBUS GCST signal is set to active will be a PCI bus directed access to the PCI9080 Since the settings will differ when the CPU board does not support the GBUS GCS7 signal see Section 6 3 4 4 When the GCS7 Signal Is Not Supported A cycle at this time is controlled by a motherboard circuit so that bit 31 LA31 of the PCI9080 local side address is always High As a result the PCI9080 setting for the GBUS si
87. guration register setting 6 3 10 5 Configuration Register The configuration space registers of the IDE bus master controller contain no IDE function related registers 65 RTE MOTHER A USER S MANUAL Rev 1 20 6 4 ISA Bus The ISA bus is bridged from the PCI bus inside the M1523B SouthBridge chip This section describes the devices that are connected to the ISA bus 6 4 1 ISA Bus connected Devices The following devices are connected to the ISA bus e IDE controller PIO mode M1523B on chip implementation e DMA controller M1523B on chip implementation e Interrupt controller 18259 subset x 2 M1523B on chip implementation Timer counter i8254 M1523B on chip implementation e PS 2 type keyboard mouse controller M1523B on chip implementation e RTC Real Time Clock M5819 e ISA slot x2 PCMCIA controller RF5C396 6 4 2 M1523B On chip Legacy Devices The following table shows legacy devices that are implemented on the M1523B chip and their addresses I O addresses in the table indicate I O address on the PCI bus address 0000H 0001H 0002H 0003H 0004H 0005H 0006H 0007H 0008H 0009H 000AH 000BH Register name ave CHO Base and Current Address ave CHO Base and Current Count ave CH1 Base and Current Address slave CH1 Base and Current Count ave CH2 Base and Current Address slave CH2 Base and Current Count ave CH3 Base and Current Address slave CH3 Base and Current Count ave Status C
88. hannel 7 Page Register DMA Channe 5 Page Register Refresh Address Register for Address 23 to 17 FAST RC GATE A20 Register INT_2 slave Control Register INT_2 slave Mask Register DMA2 master CHO Base and Current Address DMA2 master CHO Base and Current Count DMA2 master CH1 Base and Current Address DMA2 master CH1 Base and Current Count DMA2 master CH3 Base and Current Address DMA2 DMA2 master Write Mode DMA2 master Clear Byte Pointer DMA2 master Master Clear IDE2 Secondary Sector Number Register DMA2 master Write Request master Write Single Mask Bit IDE2 Secondary Cylinder Number Low Register IDE2 Secondary Cylinder Number High Register IDE2 Secondary Drive Head Register IDE2 Secondary Command Status Register IDE1 Primary Data Register IDE1 IDE1 IDE1 IDE1 Primary Error Register Primary Sector Count Register Primary Sector Number Register IDE1 Primary Cylinder Number Low Register Primary Cylinder Number High Register IDE1 Primary Drive Head Register IDE1 Primary Alternate Status Register DMA CH7 High Page Register DMA CH5 High Page Register INT 1 master Edge Level Control INT 2 slave Edge Level Control DMA2 Extended Mode Register 67 RTE MOTHER A USER S MANUAL Rev 1 20 6 4 3 RTC Real Time Clock M5819 The ALI M5819 is installed as the real time clock RTC 6 4 3 1 Addresses The
89. he motherboard ORs the reset signal on the motherboard with GRESETI as GRESETO Therefore the CPU board resets the circuits on the CPU board by ORing GRESETI and GRESETO GRESETI and GRESETO are ORed because there is a possibility that the motherboard is not connected 76 RTE MOTHER A USER S MANUAL Rev 1 20 Inputioutput GADDR 31 2 Input output GBUS address signals These signals are always driven by a valid value during a cycle GADDR 31 is ignored on the motherboard when the CPU is the bus master A 31 in the motherboard becomes 1 for an access for which GCS7 is active that is for an access to the I O space of the PCI bus Otherwise A 31 becomes 0 The low order addresses A1 and AO use a byte enable signal The EN signal enables GADDR 31 26 from the CPU board to be treated as 0 When the bus master is the motherboard if GADDR 25 is 0 it indicates that the SRAM on the motherboard is selected If GADDR 25 is 1 it indicates that a resource on the CPU board is selected GBEN 3 0 Input output Byte enable signals of GBUS These signals are always driven by a valid value during a cycle GBENO GBEN1 GBEN2 and GBENS correspond to byte lanes GDATA 7 0 GDATA 15 8 GDATA 23 16 and GDATA 31 24 respectively and the corresponding byte lane is valid when GBENx is low GDATA 31 0 Bidirectional GBUS bus data signals pem These signals are pulled up to 10 kO on the motherboard The direction of thes
90. he same as the pin arrangement of a general D SUB 25 pin connector used with a PC AT compatible device when a pressure welded type connector is used for the ribbon cable JPRT Pin Arrangement TERT Signal name APRI Signal name IEEE No 9 raed No 9 AUTO FD FD 8 SHETN Lm seem 3 1 5 21 Audio Mini Jack JIN R JIN L JLINEOUT db JIN R JIN L and JLINEOUT are audio input output connectors They are controlled by a uPD63310 connected to the local bus See Section 6 2 6 Audio Circuits JIN R and JIN L are audio input connectors that can be switched to either microphone input or line input according to JP1 to JP4 See Section 5 5 AUDIO INPUT SWITCHING JUMPERS JP1 JP2 JP4 JLINEOUT is an audio output connector for line output Compatible connectors and signal levels are shown below JIN R JIN L Electrical input conditions When MIC input is specified 140m Vp p internal amplification Approximately 20 When LINE input is specified 1 4 Vp p Compatible physical plug shape Monaural mini plug diameter 3 5 JLINEOUT Electrical output conditions 1 4 Vp p Compatible physical plug shape Stereo mini plug diameter 3 5 11 RTE MOTHER A USER S MANUAL Rev 1 20 5 22 LAN Connector JLAN JLAN is a LAN interface connector controlled by a LAN controller SB82558 connected to the PCI bus See Section 6 3 7 LAN Controller SB82558 It suppo
91. his work area is viewed from the CPU board will differ from the PCI bus address Therefore the driver must properly use both the address on the PCI bus and the address viewed from the CPU Note that a driver created for use in a PC AT compatible machine is generally written under the assumption that the address on the PCI bus and the address viewed from the CPU are equal Also note that the work area for command packets may be allocated in the stack for the same reason The data shown in the following table is entered in the serial EEPROM that is connected to the LAN controller The notation MAC x y in the table indicates MAC address bits and the contents will be the same as the MAC address printed on the sticker affixed to the LAN controller The soundness of the related data within the serial EEPROM other than the MAC address and subsystem vendor device ID should be determined according to the purpose of the driver or application Address Data D 15 0 00H MAC 39 32 MAC 47 40 01H MAC 23 16 MAC 31 24 02H MAC 7 0 MAC 15 8 03H 0100H 04H 0000H 05H 0201H 06H 4701H 07H 0000H 08H 0000H 09H 0000H OAH 4C01H OBH 0040H Subsystem Device ID OCH 1410H Subsystem Vendor ID ODH to 3EH 0000H 3FH CheckSum 74 RTE MOTHER A USER S MANUAL Rev 1 20 7 3 General Precautions General precautions that should be taken into account concerning programs are described below Be careful concerning problems that may occur because
92. iet s 14 RTE MOTHER A USER S MANUAL Rev 1 20 6 1 5 GBUS Memory and I O Map Access from the CPU Board sees 15 6 1 6 GBUS Memory Map Access from the PCI Bus nnns 16 6 25 EOCAlBUS ia deci uu iia 17 6 2 T Number of Waits atas ic senec ric rera cd e ek d nd d Tv Fe no dad 62 2 LISCO ResOUE CES aires ict eb eR dia dae Ta 6 2 3 SRAM GCS0 0000 0000H to 50 001 FFFFH 6 2 4 Flash ROM GCS1 0000 0000H to GCS1 007F FFFFH 6 2 5 UART PRINTER TL16PIR552 GCS2 0000 0000H to GCS2 0000 302FH sss 20 6 2 6 Audio Circuits tcc iac e ve ite ie brc ree n a c e d d Tv ic d 6 2 7 Interrupt Control Circuits sss 6 2 8 EXT BUS Control Registers 6 2 9 Other Contra Registers isse edendi died edd idee d dee ecc diee 6 3 PGIBUSus iue resa a tdt i e cete 55 6 3 1 BUS Arbitration usos oi cit aa na c ed Ro e e t rd RR a v dudes 55 6 3 2 Interrupt Acknowledge Cycle eese tenente tette teniente te tentent ene tte t tenens 6 3 3 Recommended M ap coccion rc 6 3 4 PCI9080 ete e bid en ava e d d d n nt fre de i e e fe et o e e 6 3 5 Device NUMDENS ses ttt enin destined ie to I e tora REG D e rnc png con na bold 0 3 0 PO Mosa erc t a v re o Ee a en ode dd i et re anna ni 637 LAN Controller SB82558 n is eee eit al ges her t eet ne te P cte e ELE a PR dea E 6 3 8 M1523B SouthBridge 6 3 9 USB Controll
93. ignments 87 RTE MOTHER A USER S MANUAL Rev 1 20 9 2 Signals signals These signals are pulled up to 10 kQ on the board these signals Memory read cycle timing signal This signal becomes active only for an access to the EXT BUS space MWR 0 3 Output Memory write cycle timing signals MWRO MWR1 MWR2 and MWR3 correspond to D O 7 D 8 15 D 16 23 and D 24 31 respectively These signals become active only for an access to the EXT BUS space AAA EXT BUS space EXT BUS space READY Input Signal for reporting the end of a cycle to the CPU This signal is valid only for the EXT BUS space To ensure that the CPU recognizes the READY signal the READY signal must be maintained active until MRD MWR 0 3 IORD or IOWR becomes inactive This signal is pulled up to 10 kQ on the board INT 0 3 Input Low active interrupt request signals These signals are connected to the interrupt controller on the board These signals are pulled up to 10 kQ on the board See Section 6 2 7 1 Overview of Interrupt Resources DMARQ 0 1 Input Low active DMA request signals These signals are buffered and then connected to the GBUS GDMARQ2 and GDMARQ3 signals These signals are pulled up to 10 kQ on the board DMAAK 0 1 Output Low active DMA acknowledge signals These signals are connected to the GBUS GDMAAK2 GDMAAK3 signals RESET Output Low active system reset signal 32 16BIT Input When this signal i
94. in is High rising edge An interrupt request due to the PCI slot 2 INTB pin is Low falling edge An interrupt request due to the PCI slot 2 INTB pin is High rising edge An interrupt request due to the PCI slot 2 INTC pin is Low falling edge An interrupt request due to the PCI slot 2 INTC pin is High rising edge An interrupt request due to the PCI slot 2 INTD pin is Low falling edge An interrupt request due to the PCI slot 2 INTD pin is High rising edge An interrupt request due to the EXT bus EXT_INTO pin is Low falling edge An interrupt request due to the EXT bus EXT_INTO pin is High rising edge An interrupt request due to the EXT bus EXT_INT1 pin is Low falling edge An interrupt request due to the EXT bus EXT_INT1 pin is High rising edge An interrupt request due to the EXT bus EXT_INT2 pin is Low falling edge An interrupt request due to the EXT bus EXT_INT2 pin is High rising edge An interrupt request due to the EXT bus EXT_INT3 pin is Low falling edge An interrupt request due to the EXT bus EXT_INT3 pin is High rising edge An interrupt request due to a USBO over current is Low falling edge An interrupt request due to a USBO over current is High rising edge An interrupt request due to a USB1 over current is Low falling edge An interrupt request due to a USB1 over current is High rising edge An interrupt request due to a PCMCIA over current is Low falling edge Bi Ure 2
95. in the timing diagram must be satisfied to ensure that the next DMA cycle does not occur However since this T19 greatly depends on the CPU capabilities it may be changed in future boards of the RTE series 92 RTE MOTHER A USER S MANUAL Rev 1 20 10 APPENDIX B 16 Bit EXT BUS Specifications The JEXT16 connector is a 16 bit EXT BUS connector that is provided so that memory or I O spaces can be expanded The local bus inside the RTE MOTHER A motherboard is connected to this connector 10 1 Pin Assignments The pin assignments of the JEXT16 connector are shown below m w gt w o gt a o o o 2 1 lt A A A 2 a N A a a o a 2 a 00 z o zx xs as e i jo n jo B Q z ES EN 234 EX JEXT16 Pin Assignments 93 RTE MOTHER A USER S MANUAL Rev 1 20 10 2 Signals inpuvoutput A 0 19 Output Address bus signals The CPU address signals are buffered and connected to these signals Output Byte high enable signal The CPU UBE signal is buffered and connected to this signal These signals are pulled up to 10 kQ on the board RD Output Read cycle timing signal This signal becomes active only for an access to the JEXT space READY Input Signal for reporting the end of a cycle to the CPU This signal is valid only for
96. interrupt due to the EXT bus EXT INTO pin Disable the interrupt due to the EXT bus EXT INT1 pin Enable the interrupt due to the EXT bus EXT INT1 pin Disable the interrupt due to the EXT bus EXT INT2 pin Enable the interrupt due to the EXT bus EXT INT2 pin Disable the interrupt due to the EXT bus EXT INT3 pin Enable the interrupt due to the EXT bus EXT_INT3 pin t t Gin EXT INTO INTEN Gin EXT INT1 INTEN O Gin EXT INT2 INTEN EXT INT3 INTEN Enable the interrupt due to a USBO over curren 1 Enable the interrupt due to a USB1 over curren 0 Disable the interrupt due to a PCMCIA over current 1 Enable the interrupt due to a PCMCIA over current Gin USB1 OC INTEN Gin PCMCIA OC INTEN x lt lt Cautions gt gt 1 One of these registers exists for each of GINTO 3 0 In the above table Gln_xxxx_INTEN represents GIO_xxxx_INTEN to GI3_xxxx_INTEN 2 Since INTEN is unrelated to the edge detection circuit an interrupt request being maintained by an edge detection circuit will continue to be maintained even if INTEN is set to 0 See Section 6 2 7 1 Overview of Interrupt Resources 3 When the 16 bit EXT BUS JEXT16 connector is used the EXT BUS interrupt is connected to EXT_INTO ea 5 43 RTE MOTHER A USER S MANUAL Rev 1 20 6 2 8 EXT BUS Conirol Registers The local bus registers include registers for controlling the EXT BUS Those registers are described below
97. ion 6 2 8 10 EXT BUS Status Register EXTBUS_STATUS GCS2 0000 7080H Read Only Do not connect a board the JEXT32 connector when 5 is set to Short This may cause a failure to occur Battery Backup Memory Clearing Jumper JP6 JP6 is used to clear the battery backup memory within the RTC This jumper should normally be used with 1 2 short circuited To clear the backup memory shut off the motherboard s power and short circuit 2 3 Then return the jumper to the 1 2 short circuited state and turn on the motherboard s power Use 1 2 short 2 3 short Clear battery backup memory To set JP6 to the 2 3 short circuited state turn off the motherboard s power If the motherboard s power is turned on when JP6 is set to the 2 3 short circuited state it may cause a failure to occur Front Panel Reset Switch Disabling Jumper JP7 To disable the front panel reset switch set the JP7 to Open state Configuration ROM Switching Jumper JP8 JP8 switches the FPGA FLEX series configuration ROM that is installed on the motherboard When JP8 is set to Short state the EPC1441PC8 installed in the socket becomes effective When JP8 is set to Open state the EPC2TC32 becomes effective Use the factory setting for JP8 RTE MOTHER A USER S MANUAL Rev 1 20 5 10 Switch 1 SW1 5 11 SW1 is a general purpose input register switch that is connected to the local bus Its setting is read from the input register See
98. is a level mode request 1 An interrupt request due to the PCI slot 2 INTC pin is an edge mode request 0 An interrupt request due to the PCI slot 2 INTD pin is a level mode request 1 An interrupt request due to the PCI slot 2 INTD pin is an edge mode request 0 An interrupt request due to the EXT bus EXT_INTO pin is a level mode request An interrupt request due to the EXT bus EXT_INTO pin is an edge mode request 0 An interrupt request due to the EXT bus EXT_INT1 pin is a level mode request 1 An interrupt request due to the EXT bus EXT_INT1 pin is an edge mode request 0 An interrupt request due to the EXT bus EXT_IN request An interrupt request due to the EXT bus EXT_INT2 pin is an edge mode INTD INTEDGE EXT INTO INTEDGE EXT INT1 INTEDGE EXT INT2 INTEDGE 2 pin is a level mode USBO OC INTEDGE USB1 OC INTEDGE 14 PCMCIA OC INTEDGE EXT INT3 INTEDGE 0 An interrupt request due to the EXT bus EXT INT3 pin is a level mode request An interrupt request due to the EXT bus EXT_INT3 pin is an edge mode request 0 An interrupt request due to a USBO over current is a level mode request 1 An interrupt request due to a USBO over current is an edge mode request 1 An interrupt request due to a USB1 over current is an edge mode request 0 An interrupt request due to a PCMCIA over current is a level mode request 1 An interrupt request due to a PCMCIA over current is an edge mode request
99. is no interrupt request due to a PCMCIA over current 1 There is an interrupt request due to a PCMCIA over current MA qa AA o the EXT bus EXT_INTO pin o the EXT bus EXT_INT1 pin o the EXT bus EXT_INT1 pin o the EXT bus EXT_INT2 pin o the EXT bus EXT_INT2 pin o the EXT bus EXT_INT3 pin Therefore to specify the resource that is requesting the interrupt for GINTO 3 0 a logical AND operation must be performed on the contents of the interrupt status registers and the contents of the interrupt enable registers that are set individually for the GINTO 3 0 pins 2 When the 16 bit EXT BUS JEXT16 connector is used the EXT BUS interrupt is connected to EXT_INTO 38 RTE MOTHER A USER S MANUAL Rev 1 20 6 2 7 7 Interrupt Clear Register 1 INT_CLEAR1 GCS2 0000 6050H Write Only Bit RST N a 0 a 2 a INTA INTCLR 1 INTB INTCLR PCI1 INTC INTCLR PClI1 INTD INTCLR PCI2 INTA INTCLR PCI2 INTB INTCLR PCI2 INTC INTCLR PCI2_INTD_INTCLR EXT INTO INTCLR EXT INT1 INTCLR EXT INT2 INTCLR EXT INT3 INTCLR USBO OC INTCLR USB1 OC INTCLR PCMCIA OC INTCLR U lt lt Cautions gt gt INTCLR is a bit for clearing an interrupt request that is being maintained by an edge detection circuit When a level mode interrupt is selected for an interrupt resource for which an edge mode or level mode interrupt can be selected INTRQ is not cleared even if 1 is w
100. les Ti4 MWR IOWR gt WR DATA delay time Ti5 MWR IOWR 2 WR DATA hold time MWR IOWR WRREADYdelay mo Tie MWR IOWR gt WR READY hold time gt DMARQ inactive delay time EXT BUS AC Specifications so A ES o WET A PEPA E ESL ED BEC SENE ARE TE E Ti MWR gt ADDR DMAAK holdtime 10 E A rl 0 pr ut a9 owe ur c AA al AE n 91 RTE MOTHER A USER S MANUAL Rev 1 20 9 5 Compatible Connectors The connectors used on the EXT BUS and the model numbers of compatible connectors that are certified for those connectors are shown below When multiple boards are connected to the EXT BUS use cables to connect them in a daisy chain configuration Connector used on EXT BUS KEL 8830E 100 170S Compatible connector for circuit board KEL 8802 100 170S Compatible connector for cable KEL 8825E 100 1705 Paired cable right angle for circuit board KEL 8830E 100 170L KEL 8831E 100 170L 9 6 Precautions The following precautions concern the design of boards to be connected to the EXT BUS 1 When multiple boards are connected to the EXT BUS Hi Z control must be performed so that the READY signal is driven only when a board has been selected 2 T7 and T16 must be satisfied to insert waits in an EXT BUS cycle 3 When a DMA cycle is performed in single transfer mode T19
101. level mode interrupt can be selected INTRQ is not cleared even if 1 is written to the relevant bit of this register End Of Interrupt EOI processing should be performed for the interrupt controller within the M1523B SouthBridge chip before 1 is written to ISAINTR INTCLR If an interrupt request from the M1523B is active when 1 is written to ISAINTR INTCLR the hardware will generate an interrupt acknowledge cycle on the PCI bus to obtain the vector ISAINTR INTRQ will become active again when the vector is obtained When the EOI is issued for this M1523B the resources on the PCI such as the mask register of the interrupt controller within the M1523B should be read while 1 is written to ISAINTR INTCLR This should be done to avoid the following kind of problem It may take some time until the interrupt line that is output from the M1523B becomes inactive after the EOI is issued for the M1523B Therefore if 1 is written to ISAINTR_INTCLR immediately after the EOI is issued the interrupt may end up being requested again due to the active state of the M1523B interrupt line before it becomes inactive due to the EOI 35 RTE MOTHER A USER S MANUAL Rev 1 20 6 2 7 4 Interrupt Edge Specification Register 0 INT EDGEO GCS2 0000 6020H Read Write PRT INTEDGE GINTIO INTEDGE 4 5 GINTI1_INTEDGE 10 LAN INTEDGE EE ES EE EE jat da jajojn lt lt Cautions gt gt INTEDGE is a regi
102. ls see Section 6 2 6 3 Audio Status Register AUDIO STATUS GCS2 0000 5010H Read Only Write Only Lights when Time Over Ready is generated See Section 6 1 4 Time Over Ready Lights when an Abort Termination is generated when accessing the PCI bus via the PCI9080 See Section 6 3 4 6 Abort Error Lights when the PCI9080 requests a back off when the GUSE DIRECT ACC signal which is a GBUS signal is Low and the PCI bus is being accessed via the PCI9080 See Section 6 3 4 7 Back Off Error LINK Lights when the LAN is in LINK state Lights when packets are being exchanged with the LAN 100TX Lights when the LAN is operating in 100Base TX mode 5 13 JGBUS Connector JGBUS JGBUS is a connector for connecting a Midas lab CPU board in the RTE CB series Either 5 V or 12 V is supplied as the power However this is limited to when the relevant power is supplied to JPOWER1 See Section 6 1 GBUS 5 14 PCI Slots JPCH JPCI2 These are connectors for inserting PCI cards See Section 6 3 6 PCI Slots They are controlled by the PCI9080 PCI 2 1 compliant cards having 32 bit 5 V specifications can be used 5 V 12 V and 12 V power are supplied 43 3 V is not supplied However this is limited to when the relevant power is supplied to JPOWER1 JPCI1 uses AD19 as IDSEL and JPCI2 uses AD20 as IDSEL 5 15 ISA Slots JISA1 JISA2 These are connectors for inserting 16 bit or 8 bit ISA cards They are controlle
103. mouse interface function can be used The on chip USB interface function can be used e The on chip IDE interface function can be used e For interrupts from the IDE the primary IDE is connected to the SIRQII pin and the secondary IDE is connected to the SIRQI pin e Two slots which are connected as ISA slots and a PCMCIA controller RF5C396 are connected to the ISA bus No BIOS ROM is connected The PCI interrupt input line is always inactive PCI interrupts are directly connected to the interrupt controller of the motherboard and do not pass through the M1523B chip The M1523B INTR output pin is connected to the ISA INTR pin of the motherboard s interrupt controller e The M1523B NMI output pin is connected to the ISA NMI pin of the motherboard s interrupt controller The result of a logical OR operation performed on the output from the voltage monitoring circuit and the GBUS GRESETI signal is connected to the M1523B PWG power good input pin e The M1523B RSTDRV output pin is connected to the GBUS GRESETO signal and used as a motherboard system reset The M1523B speaker output is output to the motherboard s JPANEL connector e The M1523B SPLED output pin is connected to the motherboard s SPEED LED e The M1523B FERR IRQ13 input pin is fixed at Low level A DMA request of the PCMCIA controller RF5C396 is connected to the M1523B DRQ7 input pin and is not connected to an ISA slot e An interrupt request of the R
104. n RD command signal that signal is usually connected Write timing signal This signal is asserted when the CPU board is the bus master This signal is not used by the motherboard When the CPU has a WR command signal that signal is usually connected Bus hold request signal This signal is asserted low when the motherboard accesses the resources on the CPU board to acquire bus mastership When the GUSE_DIRECT_ACC signal is high the GHOLD signal indicates to the CPU board that the motherboard has no resources that can be accessed In this case the CPU board does not have to support GHOLD Bus hold acknowledge signal This signal indicates that the CPU board releases bus mastership of GBUS to the motherboard It is asserted low at that time A CPU board that asserts the GUSE_DIRECT_ACC signal high can disconnect the GHLDA signal Bus mastership release request signal This signal is connected to the PCI9080 BREQ pin This signal is set to active to temporarily relinquish the bus mastership to the PCI9080 when the PCI9080 is using the GBUS If the motherboard is in a bus cycle when GBREQ is asserted low GBLAST is asserted in the next micro cycle the bus cycle is completed in the next micro cycle and then the bus mastership is relinquished GBREQ is used to temporarily return the bus mastership to the CPU board when the number of bursts of a PCI9080 bus cycle is high or when a high priority bus cycle such as a refresh cycle
105. n other words the 32M byte area of GBUS addresses from 0200 0000H to O3FF FFFFH will be allocated as a resource on the CPU board However to enable the bus master on the PCI bus to access a resource on the CPU board GUSE_DIRECT_ACC which is a signal on the GBUS must be Low When GUSE DIRECT ACC is High the CPU board is indicating that it has no resources that can be accessed by the bus master on the PCI bus The method of arbitrating access to SRAM differs significantly depending on whether GUSE DIRECT ACC is High or Low See Section 6 1 1 GBUS Bus Mastership Arbitration Also when the bus master on the PCI bus accesses a resource a PCI9080 setting determines how the address on the PCI bus is converted to an address on the GBUS 16 RTE MOTHER A USER S MANUAL Rev 1 20 6 2 Local Bus The local bus contains SRAM flash ROM Audio control registers and other control registers such as interrupt controller control registers Of these SRAM can be accessed from both the CPU board and from the bus master on the PCI bus Also access to the EXT BUS can also be performed from the CPU board via a bridge connected to the local bus The local bus resources are explained below The notation GCSx yyyy yyyH indicates the address yyyy yyyyH when the chip select GCSx signal is active 6 2 1 Number of Waits The following table shows the number of waits when accessing a resource on the local bus Depending on the resource the number of w
106. neration circuit M1523B SouthBridge SB82558 LAN controller ar PCI slot 1 PCI slot 2 A bus mastership request from the M1523B SouthBridge chip is a request from the on chip USB controller IDE controller or DMA controller installed on the M1523B Interrupt Acknowledge Cycle When the M1523B SouthBridge requests an interrupt according to the INTR pin a circuit on the motherboard generates an interrupt acknowledge cycle on the PCI bus and reads the interrupt vector from the M1523B The interrupt request is issued to the CPU board when the interrupt vector has been read See Section 6 2 7 3 Interrupt Clear Register 0 INT_CLEARO GCS2 0000 6010H Write Only and Section 6 2 9 4 ISA Interrupt Vector Register ISA INT VECTOR GCS2 0000 8040H Read Only Recommended Map The following table shows the recommended memory map on the PCI bus Address range Resources 0000 0000H to 0007 FFFFH SRAM on the local bus Same as the area that can be accessed from the range 0080 0000H to 0087 FFFFH SRAM is also allocated to this range so that SRAM can be accessed from a resource on the ISA bus The PCI9080 expanded ROM space is used 007F E000H to 007F EFFFH USB controller 007F FFOOH to 007F FFFFH PCI9080 registers 0080 0000H to 009F FFFFH SRAM on the local bus The PCI9080 SPO space is used FFFFH Resource on the CPU board when the GUSE DIRECT ACC signal is LOW The PCI9080 SP1 space is used
107. ng value xxx FIFO FULL LEVEL 7 0 1 Therefore the minimum size of a FIFO is 2 bytes and the maximum size is 254 bytes 3 The PLAY FIFO FULL REC FIFO FULL PLAY ORVF and REC ORVF signals of the AUDIO STATUS register are generated according to the value set in this register 1 a 27 RTE MOTHER A USER S MANUAL Rev 1 20 6 2 6 7 Audio FIFO HALF LEVEL Setting Register AUDIO FIFO HALF LEVEL GCS2 0000 5050H Read Write o PLAY_FIFO HALF LEVELO 1 The Half Full value bytes of the playing FIFO is set in PLAY FIFO HALF LEVEL 7 0 Playing FIFO Half Full value bytes PLAY FIFO HALF LEVEL 7 0 1 The Half Full value bytes of the recording FIFO is set in REC FIFO HALF LEVEL 7 0 lt lt Cautions gt gt 1 The minimum setting value for PLAY_FIFO_HALF_LEVEL 7 0 and REC FIFO HALF LEVEL 7 0 is 01H and the maximum setting value is FDH Also the following equation shows the relationship between the setting value and FIFO Half Full value bytes FIFO Half Full value bytes Setting value in xxx FIFO HALF LEVEL 7 0 1 Therefore the minimum Half Full value of a FIFO is 2 bytes and the maximum Half Full value is 254 bytes 2 The PLAY FIFO HFULL and REC FIFO HFULL signals of the AUDIO STATUS register are generated according to the value set in this register REC_FIFO_HALF_LEVE Recording FIFO Half Full bytes REC FIFO HALF LEVEL 7 0 1 6
108. nnected to the RTE CB series CPU board by the GBUS The RTE MOTHER A is equipped with various types of general purpose buses and connectors for connecting to interfaces You can use these functions in a great variety of ways such as developing or evaluating real time operating systems drivers or middleware 1 1 NOTATION USED IN THIS MANUAL This manual represents numbers according to the notation described in the following table Hexadecimal and binary numbers may be hyphenated at every four digits if they are difficult to read because of too many digits being in each number Notation rule Only numerals are indicated 10 represents number 10 in decimal Hexadecimal number A number is suffixed with letter H 10H represents number 16 in decimal A number is suffixed with letter B 10B represents number 2 in decimal Number Notation Rules Brackets are used to indicate multiple signals For example if there is a bus named ADDR the notation ADDR 19 16 indicates the four signals ADDR19 ADDR18 ADDR17 and ADDR16 In addition for a negative logic signal such as BE the notation BE 3 0 indicates the four signals BE3 BE2 BE1 and BEO Even when there is only one target signal this notation can be used such as in BE 3 which indicates the same signal as BE3 1 2 TERMINOLOGY Terms such as bus cycle micro cycle and burst cycle correspond to GBUS terminology For details see Section 8 1 Terminology RTE MOTHER A USER
109. not reset the playing circuits 1 Reset the playing circuits 1 Request an interrupt when the number of data values in the recording FIFO is greater than or equal to the Half Full value REC RESET BUS8_16 0 Do not reset the recording circuits 1 Reset the recording circuits e 9 a 0 Access the FIFO by using a 16 bit width 1 Access the FIFO by using an 8 bit width setting prohibited lt lt Cautions gt gt 1 When PLAY_HFULL_INTEN is set to 1 an interrupt will be generated if the number of data items in the playing FIFO becomes less than the value set in PLAY_FIFO_HALF_LEVEL 7 0 This interrupt is generated corresponding to the FIFO status when audio is not being played When PLAY_RESET is set to 1 only the playing circuits are reset under hardware control Also if REC_RESET is set to 1 only the recording circuits are reset under hardware control The uPD63310 is not reset by PLAY RESET REC RESET The uPD63310 can be reset by the AUDIO RESET signal of the AUDIO CONT register See Section 6 2 6 2 Audio Control Register AUDIO CONT GCS2 0000 5000H Read Write If the setting of PLAY RESET or REC RESET is not returned to 0 after it has been set to 1 the reset state is not canceled The following table shows the relationship between the various reset bits and the circuits that are reset Control bit LPD63310 Playing circuits Recording circuits AUDIO RESET of AUDIO CONT
110. o recording FIFO underflow occurred cording FIFO underflow occurred Signal name PLAY DOING 0 25 PLAY OVRF 5 c nused PLAY FIFO EMPTY 2 x x 0 LAY_FIFO_ HFULL LAY_FIFO_ FULL nused REC DOING EC UNDF 1 Re 0 No recording FIFO overflow occurred 1 Recording FIFO overflow occurred REC ORVF 945 nused REC FIFO EMPTY 1 0 Recording FIFO is not empty 1 Recording FIFO is empty 0 Recording FIFO is not half full 1 Recording FIFO is half full 0 Recording FIFO is not full 1 Recording FIFO is full EC FIFO HFULL EC FIFO FULL 15 Unused lt lt gt gt 1 For information about the actions of the PLAY DOING and REC DOING bits refer to the Cautions concerning PLAY and REC in Section 6 2 6 2 Audio Control Register AUDIO CONT GCS2 0000 5000H Read Write A playing FIFO underflow occurs when the playing FIFO contains no data to be sent to the uPD63310 A recording FIFO underflow occurs when the recording FIFO is read even though the recording FIFO contains no data A playing FIFO overflow occurs when data is written to the playing FIFO even though the playing FIFO is full A recording FIFO overflow occurs when data sent from the uPD63310 is written to the recording FIFO even though the recording FIFO is full Since a FIFO has an 8 bit configuration the occurrence of an underflow or overflow is detected in
111. ommand slave Write Request slave Write Single Mask Bit slave Write Mode 000CH slave Clear Byte Pointer 000DH DMA1 slave Master Clear 000EH MA1 slave Clear Mask 000FH DMA1 slave Read Write All Mask Register Bits 0020H NT 1 master Control Register 0021H NT 1 master Mask Register 0040H Timer Counter Channel 0 Count 0041H Timer Counter Channel 1 Count 0042H Timer Counter Channel 2 Count 0043H Timer Counter Command Mode Register 0060H Clear IRQ12 for PS2 IRQ1 Latched Status Keyboard Data Buffer 0061H NMI and Speaker Status and Control PORTB 0064H Keyboard Status Command 0070H CMOS RAM Address Port and NMI Mask Register 0071H CMOS Data Register Port a lalala ja e olojojolo ju o RIRN Es Ed Es Es E gt x gjo lt s z x 66 RTE MOTHER A USER S MANUAL Rev 1 20 VO address 0081H 0082H 0083H 0087H 0089H 008AH 008BH 008FH 0092H 00A0H 00A1H 00COH 00C2H 00C4H 00C6H 00C8H 00CAH 00CCH OOCEH 00DOH 00D2H 00D4H 00D6H 00D8H 00DAH 00DCH 00DEH OOFOH 0170H 0171H 0172H 0173H 0174H 0175H 0176H 0177H 01FOH 01F1H 01F2H 01F3H 01F4H 01F5H 01F6H 01F7H 0376H 0377H 03F6H 03F7H 040BH 0481H 0482H 0483H 0487H 0489H 048AH 048BH 04D0H 04D1H 04D6H DMA Channe DMA Channe 2 Page Register 3 Page Register DMA Channel 1 Page Register DMA Channel 0 Page Register DMA Channe 6 Page Register DMA C
112. on GADDR 31 26 When this signal is high it indicates that the CPU board is not driving a valid value on GADDR 31 26 and the circuits on the motherboard perform processes with all of the GADDR 31 26 signals low Motherboard detection signal This signal is pulled up on the CPU board and is connected to GND on the motherboard The CPU board uses this signal when it must determine if the motherboard is connected For example this signal is used by a CPU board time over ready generation circuit When this signal is low it indicates that the CPU board has resources that can be accessed from the motherboard When this signal is high Ready based bus arbitration is performed and GHOLD does not become active even when the PCI9080 requests the GBUS bus mastership When this signal is low GHOLD becomes active when the PCI9080 requests the GBUS bus mastership That is HOLD based bus arbitration is performed When this signal is low it indicates that the GCLK frequency does not exceed 16 67 MHz When this signal is high it indicates that the GCLK frequency is between 16 67 MHz and 33 33 MHz The circuits on the motherboard use this signal to determine the number of waits required to access resources on the motherboard Bus lock signals These signals must be valid during a bus cycle and between bus cycles to be locked When a bus lock signal is output from the CPU the bus lock signal is connected to the motherboard by using these pins The
113. on reception FIFO is 3K bytes in size e Conforms to the Advanced Configuration and Power Interface ACPI specifications e Conforms to the PCI Power Management specifications Revision 1 0 e Conforms to the Advanced Power Management APM specifications Revision 1 2 Supports ACPI Wake up packets Supports IEEE802 3u 100BASE TX and 10BASE T automatic negotiation Supports half duplex full duplex communication at 10 and 100 Mbps The RTE MOTHER A motherboard does not support the power management related functions of the SB82558 6 3 7 2 Device Numbers For the device numbers that are assigned see Section 6 3 5 Device Numbers The vendor ID of this device configuration register is 8086H and the device ID is 1229H Also the subsystem vendor ID is 1410H and the subsystem device ID is 0040H 6 3 7 3 Addresses Since this is a device that is connected to the PCI bus the allocated addresses are determined by the value set in the register for the SB82558 configuration space 6 3 7 4 Interrupts The SB82558 INTA pin is directly connected to the interrupt control circuit of the local bus and does not pass through the SouthBridge chip For details see Section 6 2 7 1 Overview of Interrupt Resources 61 RTE MOTHER A USER S MANUAL Rev 1 20 6 3 8 M1523B SouthBridge 6 3 8 1 Specifications The M1523B is a SouthBridge LSI chip for an ALI PC AT motherboard The following functions are implemented on the M1523B
114. or Audio recording GDMAAK2 for the EXT BUS DMAAKO and GDMAAKS for the EXT BUS DMAAK1 An Audio DMA transfer does not require a DMAAK signal Therefore the CPU board need not support GDMAAKO and GDMAAK1 However when GDMAAK 1 0 are not supported the timing for de asserting the GDMARQ signal is slower than when they are supported When GDMAAK2 and are not supported the corresponding EXT BUS DMAAK signals cannot be asserted Interrupt request signals Both level sensitive and edge sensitive interrupts can be supported A low level or a falling edge indicates the occurrence of an interrupt Interrupt request signals These interrupt signals are used to combine an interrupt on the CPU board with an interrupt on the other motherboard and return the combined signal to GINTO 3 0 Usually OUTO and OUT1 of the TIC uPD71054 on the CPU board are connected The motherboard can select the type of sensitivity and the polarity for these interrupt signals under program control CPU board dependent signals These signals are not used by the RTE MOTHER A motherboard The CPU board determines the contents of the GETC 7 0 signals including the signal directions and signal contents The CPU board uses these signals to exchange signals having a special purpose with the motherboard Upper address valid signal If the CPU board is the bus master when this signal is low it indicates that the CPU board is driving a valid value
115. or and performs the relevant interrupt handling 2 It performs End Of Interrupt EOI processing for the interrupt controller of the M1523B 3 It performs ISA_INTR clear processing for the interrupt controller of the motherboard If the M1523B is still asserting the INTR pin at the stage when the ISA INTR clear processing is performed processing returns to 2 and continues The SB82558 LAN controller interrupts and PCI bus slot interrupts are conventional level sensitive interrupts which are generated when the level is Low Therefore this mode normally is used However the mode can be switched to edge sensitive mode or the polarity can be selected in order to take into consideration cases that cannot correspond to a level sensitive interrupt The various interrupts are organized as shown in the following figure Edge detection INT EDGE Pereach GINT INT HIGH Edge Level selection Polarity control Per each interruption resource Interrupt requests from the various resources pass through the polarity control circuit edge detection circuit and edge level selection circuit required for each interrupt resource Then a logical OR operation is performed on the interrupt requests of all interrupt resources Finally an ALL_MASK and logical AND operation are performed and the result is connected to GINT 3 0 The ALL_MASK function is provided to support multiple interrupts when GINT 3 0 are connected to edge sensiti
116. orcing an 8 bit access is provided for a read cycle to the motherboard This port should be used When the CPU s data bus is 16 bits a 32 bit access to the motherboard cannot be performed For this kind of CPU a board that requires a 32 bit access cannot be connected to the EXT BUS or PCI bus 75 RTE MOTHER A USER S MANUAL Rev 1 20 8 GBUS SPECIFICATIONS This section explains the GBUS specifications 8 1 Terminology The terminology used in this section is explained below 8 1 1 CPU Board and Motherboard A board in the RTE CB series is called a CPU board and the RTE MOTHER A is called a motherboard 8 1 2 Bus Cycle and Micro Cycle GBUS is a general bus that can be accessed in burst mode A bus cycle including cases when the access is in burst mode is a sequence of cycles that is completed GADS must be asserted once to end a bus cycle Bus cycles are classified into single cycles and burst cycles A single cycle is a bus cycle in which data is transferred only once A burst cycle is a bus cycle in which data is transferred multiple times The cycle for each data transfer of a burst cycle is called a micro cycle 8 2 Signals The following table describes the GBUS signals The input output direction of each GBUS signal is described as viewed from the motherboard Therefore input means that a signal is output from the CPU board and input to the motherboard This criterion also applies to signal names Signals describe
117. rd normally TOUTO TOUT1 of the uPD71054 on the CPU board is connected and for testing the timer related interrupts For signals from the RTC interrupts are generated at an interval of approximately 1 ms from updates 1 s and for signals from the timer interrupts are generated at an interval of approximately 55 ms For signals from the uPD71054 on the CPU board interrupts are generated at an interval of 60 Hz 16 667 ms and 40 Hz 25 ms RTC date information is read and displayed on the screen for every three update 72 RTE MOTHER A USER S MANUAL Rev 1 20 interrupts At this time the accumulated number of seconds due to the various interrupts of 1 ms 55 ms 16 667 ms and 25 ms are displayed together with the date information sram_test directory This di rectory contains a program for memory testing all areas of common RAM SRAM on the motherboard usb test directory This directory contains a program for testing the functions of the USB connectors on the motherboard The functions that are tested are the ON OFF state of the power supply and the reading signatures from connected USB device and the generation of an over current interrupt The reading signatures from connected USB device is not work correctly on the CPU board that cannot access to the motherboard by using a 32 bit cycle Sample Program Resource Allocation The sample programs allocate the resources of the PCI bus or ISA bus as follows Memory PCI bus a
118. ritten to the 1 relevant bit of this register 1 Clear an interrupt request due to the PCI slot 1 INTA pin 1 Clear an interrupt request due to the PCI slot 1 INTB pin 1 Clear an interrupt request due to the PCI slot 1 INTC pin 0 Do not clear an interrupt request due to the PCI slot 1 INTD pin 1 Clear an interrupt request due to the PCI slot 1 INTD pin 1 Clear an interrupt request due to the PCI slot 2 INTA pin 1 Clear an interrupt request due to the PCI slot 2 INTB pin 1 Clear an interrupt request due to the PCI slot 2 INTC pin 1 Clear an interrupt request due to the PCI slot 2 INTD pin 0 Do not clear an interrupt request due to the EXT bus EXT_INTO pin 1 Clear an interrupt request due to the EXT bus EXT_INTO pin 0 Do not clear an interrupt request due to the EXT bus EXT_INT1 pin 1 Clear an interrupt request due to the EXT bus EXT_INT1 pin 0 Do not clear an interrupt request due to the EXT bus EXT_INT2 pin 1 Clear an interrupt request due to the EXT bus EXT_INT2 pin 0 Do not clear an interrupt request due to the EXT bus EXT_INT3 pin 1 Clear an interrupt request due to the EXT bus EXT INT3 pin 0 Do not clear an interrupt request due to a USBO over current 1 Clear an interrupt request due to a USBO over current 0 Do not clear an interrupt request due to a USB1 over current 1 Clear an interrupt request due to a USB1 over current 0 Do not clear an interrupt request due to a P
119. rmed e Pull up processing is performed e Pull up processing is performed e Pull up processing is performed e Pull up processing is performed e Pull up processing is performed e Pull up processing is performed e Pull up processing is performed e Pull up processing is performed e Pull up processing is performed GBLOCK 1 0 e Pull up processing is performed Allocating GCS 7 0 The following table shows the allocation of the chip select signals GCS 7 0 All of the spaces can be accessed in a burst cycle A space marked I O under the heading Recommended space means that if the CPU has an I O space it is recommended that the space be allocated as an I O space Minimum range indicates that the CPU board must allocate at least the indicated area for the corresponding chip select space Maximum range indicates that if the CPU board has an extra address range addresses can be allocated for the indicated range See Section 6 1 5 GBUS Memory and I O Map Access from the CPU Board Remarks name space range range bus register setting GCS1 Memory 2M bytes e Flash ROM space The program can be booted from this space instead of from UV EPROM on the CPU board according to switch settings on the CPU board GCS2 64K bytes Control register space on the local bus GCS3 Memory 64K bytes 16M bytes e EXT BUS memory space e When a board is connected to the 16 bit EXT BUS JEXT16 connector it can be acces
120. rs are assigned as shown in the following table PCI slot 1 No 8 AD19 PCI slot 2 No 9 AD20 LAN controller SB82558 No 10 AD21 M1523B SouthBridge configuration register No 7 AD18 USB controller M1523B on chip implementation Selected from among No 17 to No 20 AD28 to AD31 Default No 20 IDE controller M1523B on chip implementation Selected from among No 13 to No 16 AD24 to AD27 Default No 16 The device numbers of the USB controller and IDE controller can be selected by a setting in the M1523B configuration register 6 3 6 PCI Slots The motherboard has two slots for a PCI board 6 3 6 1 Power supply Although 5 V 12 V and 12 V power are supplied to each PCI slot 3 3 V power is not supplied Also when 12 V or 12 V power is not supplied to the motherboard it is also not supplied to the PCI slots 6 3 6 2 Device Numbers For device numbers that are assigned to each slot see Section 6 3 5 Device Numbers 6 3 6 3 Interrupts The interrupts of each PCI slot are directly connected to the interrupt control circuit of the local bus and do not pass through the SouthBridge chip For details see Section 6 2 7 1 Overview of Interrupt Resources 60 RTE MOTHER A USER S MANUAL Rev 1 20 6 3 7 LAN Controller SB82558 6 3 7 1 Specifications The SB82558 is an Intel LAN controller having the following features e Compatible with IEEE802 3 802 3u 10BASE T and 100BASE TX e Each transmissi
121. rts 100Base TX and 10Base T 5 23 IDE Connectors JIDE1 JIDE2 JIDE1 and JIDE2 are Enhanced IDE interface connectors controlled by M1523B which is a SouthBridge chip See Section 6 3 10 IDE Bus Master Controller M1523B SouthBridge On chip Implementation They support PIO modes 0 to 4 and MultiWord DMA modes 0 to 3 JIDE1 corresponds to the primary IDE and JIDE2 corresponds to the secondary IDE At most two hard disk drives or CD ROM drives can be connected to each connector 5 24 EXT BUS Connectors JEXT32 JEXT16 JEXT32 and JEXT16 are EXT BUS connectors that are compatible with the Midas lab expanded bus in the RTE PC series JEXT32 can connect a 32 bit EXT BUS board and JEXT16 can connect a 16 bit EXT BUS board For specifications of the JEXT32 and JEXT16 connectors see Chapter 9 APPENDIX A 32 Bit EXT BUS Specifications and Chapter 10 APPENDIX B 16 Bit EXT BUS Specifications respectively Also when a board is connected to the JEXT16 connector EXT BUS is automatically set to 16 bit mode If the automatic switching to this mode does not function normally you can forcibly switch it to 16 bit mode by using JP5 See Section 6 2 8 EXT BUS Control Registers di JEXT32 and JEXT16 cannot be used at the same time If boards are connected to both connectors a failure may occur Connect a board to only one of these connectors 12 RTE MOTHER A USER S MANUAL Rev 1 20 6 HARDWARE REFERENCES A LINE MIC LINE MIC LIN
122. s for an access when both the GBUS GDMAAK2 and GDMAAK3 signals are not active For the correspondence of the GBUS address and EXT BUS address see Section 6 2 8 1 Bank Window When a 16 bit EXT BUS JEXT16 connector is used although no DMA cycle is defined for the 16 bit EXT BUS the setting of this register is not used and the EXT DMAO MEM BANKA 23 16 register or EXT_DMA1_MEM_BANKA 23 16 register is used by cycles in which the GBUS GDMAAK2 and signals are active 6 2 8 5 EXT BUS CPU lO Space Bank Address Register EXTBUS CORE IO BANK ADDR 1 GCS2 0000 7030H Read Write o EXT IO 16 o EXT_CORE_IO_BANKA 23 16 specifies the bank address of a non DMA 1 Exr IO BANKA17 o access to the EXT BUS I O space EXT _IO_BANKA18 o LO Eum EXT_CORE_1O_BANKA21_ EXT CORE BANKA22 o EXT CORE JO BANKA23 o Cautions EXT CORE IO BANKA 23 16 determines the address to be output to the EXT BUS for an access to the EXT BUS I O space that is not a DMA access that is for an access when both the GBUS GDMAAK2 and GDMAAK3 signals are not active For the correspondence of the GBUS address and EXT BUS address see Section 6 2 8 1 Bank Window When a 16 bit EXT BUS JEXT16 connector is used the setting of this register is not used and the setting of EXT CORE MEM BANKA 23 16 is used for an access to the EXT BUS 46 RTE
123. s is not limited If the target of the access limits the number of bursts use the GBTERM signal to request canceling of the burst See Section 8 6 4 GBTERM The RTE MOTHER A motherboard has no resources that limit the number of bursts The following charts show a burst cycle when GBWAITI and GBTERM are always inactive and the CPU board is the bus master When the motherboard is the bus master the GCSx GDMAAK and GWAITI signals are not used GCLK GCSx GDMAAKx GADDR31 2 CBE 3 0 GDATA 31 0 GDATA 31 0 Write 83 RTE MOTHER A USER S MANUAL Rev 1 20 GBTERM GDATA 31 0 GDATA 31 0 Write 8 6 3 GWAITI The GWAITI signal can be used as follows in a cycle in which the CPU board is the bus master To delay sampling of data by a specific number of clocks because the data cannot be sampled in the read cycle due to a timing problem To hold the target of an access by the specific number of clocks because data for the next micro cycle is not ready immediately after the completion of the first micro cycle in the burst cycle of a write cycle In other words the roles of the read cycle and write cycle are switched but GREADY and GWAITI serve as data transmission ready and data reception ready signals The following charts show that a wait cycle is inserted by the GWAITI signal Read Cycle NAAA GBTERM GDATA 31 0 Write Cycle GBTERM GDATA 31 0 84 RTE MOTHER A USER
124. s asserted low only D 15 0 of the data bus are used 16 bit bus mode When this signal is asserted high D 31 0 of the data bus are used 32 bit bus mode This signal is pulled up to 10 k on the board Clock signal The GBUS GCLK signal is buffered and then connected to this signal PA e i Reserved signal For a board that uses the EXT BUS this pin must not be connected to anything JEXT32 Connector Signals lt lt Cautions gt gt Tis The 32 16BIT signal will not necessarily be supported by all future boards in the RTE series If you also plan to use a board that is connected to the EXT BUS with future boards in the RTE series you should design it so that it operates in 32 bit bus mode When the 32 16BIT signal is low the MWR2 and MWR3 signals are not asserted Instead the MWRO and MWR1 signals are asserted A1 is valid when the 32 16BIT signal is low Therefore A1 may not be output by a future board in the RTE series for which the 32 16BIT signal is not supported The maximum access bus width in a single cycle for the EXT BUS depends on the bus width of the CPU s data bus For example for a CPU having a 16 bit data bus up to 16 bits can be accessed for an access to I O or an access due to a flyby DMA transfer Therefore for a register that is accessed by an I O cycle or flyby DMA cycle of a board connected to the EXT BUS the data bus width must not exceed the data bus width of the CPU to which the board is to be
125. s switch is effective only when an ATX standard power supply is used The pin arrangement is shown below When pushed the switch short circuits pin 1 and GND The power supply toggles between ON and OFF each time the switch is pressed e 3 N C 2 GND Li POWER SWITCH RTE MOTHER A USER S MANUAL Rev 1 20 5 4 5 5 5 6 5 7 5 8 5 9 POWER SWITCH SW_POWER The SW_POWER switch performs the same action as the switch connected to the JPOWERSW connector When no switch is connected to the JPOWERSW connector the power can be turned ON or OFF by using the SW POWER switch Like JPOWERSW this switch is effective only when an ATX standard power supply is used AUDIO INPUT SWITCHING JUMPERS JP1 JP2 JP3 JP4 JP1 to JP4 are jumpers for switching between whether audio is to be input as microphone input or as line input See Section 6 2 6 Audio Circuits The following table shows the JP1 to JP4 settings The factory settings are for microphone input JIN R input JP1 Microphone input 1 2 Short 2 3 Short JIN L input JP4 Microphone input 1 2 Short 2 3 Short EXT BUS Forced 16 Bit Jumper JP5 JP5 is a jumper for forcibly causing a 16 bit board that has been connected to the JEXT16 connector but has not been recognized as a 16 bit board to be recognized as a 16 bit board Although the factory setting for this jumper is Open JEXT BUS can be forcibly set to 16 bit mode by setting this jumper to Short See Sect
126. sed by using this space 64K bytes 16Mbytes EXT BUS I O space GCS5 Memory 1M byte 2G bytes e PCI bus memory space A bus lock can be applied by the GLOCK1 signal or by a local bus register setting GCS6 512 bytes ie A e PCI9080 control register space 64K bytes 2G bytes e PCI bus I O space e A bus lock can be applied by the GLOCK1 signal or by a local bus register setting e f the CPU has I O space no chip select is provided for this space and the PCI bus I O space can also be accessed by using the GCS5 space A bus lock can be applied by the GLOCKO signal or by a local 82 RTE MOTHER A USER S MANUAL Rev 1 20 8 6 BUS CYCLE 8 6 1 Single Cycle The following chart shows a single cycle when GBWAITI and GBTERM are always inactive and the CPU board is the bus master When the motherboard is the bus master the GCSx GDMAAK and GWAITI signals are not used GDATA 31 0 GDATA 31 0 Write 8 6 2 Burst Cycle The following rules apply to a burst cycle e The addresses in a burst cycle can be in any sequence allowed by the GBUS specifications However the address sequence may be specified according to what is to be accessed For the RTE MOTHER A motherboard addresses must be in ascending order for an access to the PCI bus or an access to the PCI9080 control register During a burst cycle the GBE 3 0 signals must all be active e The number of bursts the number of micro cycle
127. sing edge falling edge Also Level edge selection indicates function that can correspond to the interrupt line being either level sensitive or edge sensitive Polari Level Interrupt resource eve ledge Remark control selection Yes Yes INTR interrupt of the ISA BUS see below ISA NMI interrupt Interrupt is generated when the NMI pin of the M1523B SouthBridge is High Yes OUTO OUT1 of the 4PD71054 timer which is normally installed on the CPU board are connected to the GINTIO and GINTI1 pins of the GBUS 31 RTE MOTHER A USER S MANUAL Rev 1 20 The ISA INTR interrupt is supplied to the CPU board as follows 1 When the internal interrupt controller i8259 compatible of the M1523B SouthBridge detects an interrupt the INTR pin of the M1523B becomes active 2 When the motherboard circuit detects that the INTR pin of the M1523B is active it causes an interrupt acknowledge cycle to be generated on the PCI bus to obtain the interrupt vector from the M1523B 3 When the motherboard circuit has obtained the interrupt vector it requests an ISA_INTR interrupt for the interrupt controller of the motherboard 4 When ISA_INTR is asserted the interrupt controller of the motherboard asserts GINTOx according to the interrupt controller settings The CPU board performs the following processing when an ISA INTR interrupt is generated 1 It reads the interrupt vect
128. ster are maintained until the interrupt is cleared by ISAINTR CLR If an interrupt is being held when the interrupt is cleared by ISAINTR CLR the interrupt acknowledge cycle is started again and a new interrupt vector is set in this register See Section 6 2 7 3 Interrupt Clear Register 0 INT CLEARO GCS2 0000 6010H Write Only 6 2 9 5 ISA Interrupt Status Register ISA INT STATUS GCS2 0000 8050H Read Only ISA INTR 0 The M1523B INTR pin is inactive 1 The M1523B INTR pin is active pt unused o e Unused lt lt Cautions gt gt 1 ISA_INTR indicates whether the INTR pin which is the ISA interrupt request pin of the M1523B SouthBridge chip is active or inactive This bit has no specific use but is intended for hardware debugging 51 RTE MOTHER A USER S MANUAL Rev 1 20 6 2 9 6 BREQ Control Register BREQ_CONTROL GCS2 0000 8060H Read Write BREQ_NUMO EH BREQ_NUM 1 0 sets the timing for issuing a bus mastership request to the PCI9080 BREQ 0 The bus mastership is not requested during the PCI9080 burst cycle 1 The bus mastership is requested during the PCI9080 burst cycle 6 Unused lt lt Cautions gt gt 1 The cycle that the PCI9080 generates for the GBUS is not limited to the burst count Therefore the CPU may be unable to obtain the GBUS bus mastership for a long period of time BREQ EN and BREQ_NUMI 1 0 are provided to enable the CPU to always obtain the bus mastership wi
129. ster for setting whether an interrupt request from an interrupt resource is an 1 edge mode or level mode request x x X X X X X 0 The interrupt request from the TL16PRI552 PRINTER pin is a level mode request 1 The interrupt request from the TL16PRI552 PRINTER pin is an edge mode request The interrupt request from the GBUS GINTIO pin is a level mode request The interrupt request from the GBUS GINTIO pin is an edge mode The interrupt request from the GBUS GINTI1 pin is a level mode request The interrupt request from the GBUS GINTI1 pin is an edge mode request 0 The interrupt request due to the SB82558 INTA pin is a level mode request 1 The interrupt request due to the SB82558 INTA pin is an edge mode request The edge detection circuit maintains an edge detection result regardless of the setting of this register When this register setting is switched from level mode to edge mode the edge detection circuit should be cleared by the relevant INTCLR before the switch An interrupt from a TL16PIR552 printer uses edge mode or level mode according to the mode of the printer port Since an interrupt from the SB82558 LAN controller obeys PCI bus standards level mode should be used 36 RTE MOTHER A USER S MANUAL Rev 1 20 6 2 7 5 Interrupt Polarity Specification Register 0 INT POLARITYO GCS2 0000 6030H Read Write Bit RST 0 The interrupt request from the TL16PRI552 PRINTER pin
130. tership to be relinquished to the PCI9080 according to a signal from the CPU board For details see Section 6 2 9 6 BREQ Control Register BREQ_CONTROL GCS2 0000 8060H Read Write GBUS Bus Lock Accesses to SRAM and the PCI bus support a bus lock function A bus lock can be applied due to an access to SRAM or the PCI bus from the CPU board by using the GBLOCK 1 0 signal on the GBUS or control registers on the local bus See Section 6 2 9 8 Bus Lock Control Register BLOCK_CONTROL GCS2 0000 8080H Read Write A bus lock can also be applied due to an access to SRAM from the bus master on the PCI bus via the PCI9080 This case is limited to when the bus lock is requested by the bus master on the PCI bus Time Over Ready If the GREADY signal is not active for at least 10 milliseconds when EXT BUS or the PCI bus is accessed from the CPU board a time over ready is generated and the bus cycle is forcibly terminated to avoid deadlock When a time over ready is generated the TOVRDY LED on the motherboard lights up This LED remains lit until it is cleared by software See Section 5 12 LED and Section 6 2 9 9 TOVRDY LED Clear Register TOVRDY LED CLR GCS2 0000 8090H Write Only addition the generation of a time over ready can cause an interrupt to be generated See Section 6 2 7 1 Overview of Interrupt Resources A time over ready that is generated by an access to EXT BUS will be generated when one micro cycle ex
131. the local bus HS 512 bytes PCI9080 control register space 64K bytes bytes PCI bus I O space e Accesses the I O space of the PCI bus via the PCI9080 An allocated area of 64K bytes is usually sufficient e Abus lock can be applied by the GLOCK1 signal or by control from I O on the local bus e f the CPU on the CPU board has no I O space this space should be eliminated In that case I O will be accessed from the GCS5 space e If the size of the GCS5 space differs from the size of the GCS7 space the address line of the portion corresponding to the difference in the sizes must be zeros For example if the GCS5 space is 1M byte and the GCS7 space is 64K bytes GADDR 19 16 must be zeros when accessing the GCS7 space This is a restriction related to the PCI9080 15 RTE MOTHER A USER S MANUAL Rev 1 20 6 1 6 GBUS Memory Map Access from the PCI Bus The following two kinds of resources on the GBUS can be accessed from the bus master on the PCI bus One kind of resource is SRAM on the motherboard All of the SRAM space can be accessed To access this space GADDR 25 which is a GBUS address is set to Low In other words SRAM will be allocated to the range of GBUS addresses from 0000 0000H to 01FF FFFFH However the actual size of SRAM is 2M bytes The other kind of resource is a resource on the CPU board To access a resource on the CPU board GADDR 25 which is a GBUS address is set to High I
132. thin a certain desired interval By setting BREQ EN and BREQ NUM 1 0 the PCI9080 BREQ pin can be set to active state according to the timing shown in the following table to direct the PCI9080 to relinquish the bus mastership When the BREQ pin becomes active the PCI9080 terminates the bus cycle within two micro cycles and relinquishes the bus mastership GBUS signal BREQ EN BREQ_NUM 1 BRE GUSE DIRECT ACC NUN 1 0 Q active timing o mx BREQ does not become active 0 0 When the CPU begins the cycle and GADS is set to active 0 1 Setting prohibited The slowest timing among the following two The PCI9080 continued the cycle for at least six micro cycles The CPU begins the cycle and GADS is set to active The slowest timing among the following two The PCI9080 continued the cycle for at least 14 micro cycles The CPU begins the cycle and GADS is set to active l o mu BREQ does not become active Immediately after the PCI9080 cycle begins Setting prohibited micro cycles micro cycles 2 Another method for setting the PCI9080 BREQ pin to active besides using BREQ EN and BREQ_NUM 1 0 is to set the GBUS GBREQ signal to active A logical OR operation is performed for the GBUS GBREQ signal and the BREQ signal generated according to BREQ EN and BREQ_NUM 1 0 52 RTE MOTHER A USER S MANUAL Rev 1 20 6 2 9 7 Flash ROM Control Register FROM_CONTROL GCS2 0000 8070H Read Write FR
133. ve interrupt request pins of the CPU An edge can be generated for GINT 3 0 by masking ALL_MASK at the end of interrupt handling for these kinds of cases 32 RTE MOTHER A USER S MANUAL Rev 1 20 6 2 7 2 Interrupt Status Register 0 INT_STATUSO GCS2 0000 6000H Read Only aa ny MA AA 1 There is an interrupt request from the TL16PRI552 UARTO pin 2 UART1_INTRQ 0 There is no interrupt request from the TL16PRI552 UART1 pin 1 There is an interrupt request from the TL16PRI552 UARTI pin A eee ere ee 1 There is an interrupt request from the TL16PRI552 PRINTER pin A MEI 1 There is an interrupt request from the AUDIO pin ES uL IAM 0 There is no interrupt request due to the PCI9080 LINTo pin 1 There is an interrupt request due to the PCI9080 LINTo pin GINTIO_INTRQ 0 There is no interrupt request due to the GBUS GINTIO pin 1 There is an interrupt request due to the GBUS GINTIO pin 0 There is no interrupt request due to the GBUS GINTI1 pin 1 There is an interrupt request due to the GBUS GINTI1 pin 1 There is an interrupt request due to the ISA bus INTR pin 1 There is an interrupt request due to the ISA bus NMI pin 0 There is no interrupt request due to the SB82558 INTA pin 1 There is an interrupt request due to the SB82558 INTA pin P9_LSERR_INTRQ Ea 0 There is no interrupt request due to the PCI9080 LSERR pin N GINTI1_INTRQ ISAINTR_INTRQ ISANMI_INTRQ 0 LAN INTRO 1 Ther

User`s Manual (Rev.1.20)

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