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APC8620A/APC8621A User`s Manual

1. DOD 2000000000000000000000000 000000000000000000000000 c OSes Ce e A BE H i g ge 851i E 88 ge oo oo 88 IPA 8 un i n oo oo F13 F15 F14 88 58 Oo i BB B8 55 88 0 88 2 12 BB oo oo oo oo 88 5 n nn na oo 88 55 3 525 3 362 224 CA Hu ooj ooj i EEA IPC Fi IPD BEEN IPE T SEIS 9 100 724 i 20 20 ss 1 i 00 1 1 88 88 nn F4 F7 ool ool i on nn 88 98 06 n 1 1 8 p i oo 88 1 oo 88 8
2. REMOVAL FROM RAIL SIDE VIEW NOTES DIMENSIONS ARE IN INCHES MILLIMETERS TOLERANCE 0 020 0 5 MODEL 5025 552 TERMINATION PANEL 4501 464A FRONT VIEW 9 SAIYAS MOVd WIYLSNAGNI ayog sna
3. 12 mechanical interface for up to three industry standard IP SERVICE AND REPAIR ASSISTANCE 12 modules IP Modules are available from Acromag and other PRELIMINARY SERVICE PROCEDURE 12 vendors in a wide variety of Input Output configurations to 6 0 SPECIFICATIONS 13 meet the needs of varied applications GENERAL 13 e Plug And Play PCI bus Carrier The carrier card contains PCI BUS 13 standard PCI bus configuration memory Upon power up INDUSTRIAL I O PACK COMPLIANCE 13 the system auto configuration process assigns the carrier s 14 base address memory space INDUSTRIAL I O PACK SERIES APC8620A APC8621A Plug And Play Interrupt Support The personal computer system software will allocate one interrupt line to the carrier The 5 interrupt pending register can be used to quickly identify IP module pending interrupts e Supports Two Interrupt Channels per IP Up to two interrupt requests are supported for each IP Additional registers are associated with each interrupt request for control and status monitoring Full IP Register Access Makes maximum use of logically organized programmable registers on the carrier boards to provide for easy conf
4. 10 Length slots Temperature IP Module Memory Space 10 Range GENERATING INTERRUPTS 220210 APC8620A 12 283 5 A B C D E 0 to 70 C Sequence of Events for an 1 10 APC8620AE 12 283 5 A B C D E 40 to 85 C 4 0 THEORY OF 10 APC8621A 6 6007 3 A B C 0 to 70 C CARRIER BOARD OVERVIEW e 0100 APC8621AE 6 600 40 to 85 C PCI BUS 10 Carrier Board 11 KEY APC8620A 21A FEATURES IP Logic 11 Carrier Board Clock 11 PCI Specification Version 2 2 Compliant Slave Carrier PCI Interrupter 11 Provides a PCI bus interface to control and communicate Power Failure 11 with industry standard IP modules Power Supply 12 Interface for IP Modules APC8620A provides Power Supply 12 electrical and mechanical interface for up to five industry Software Compatibility to the APC8620 APC8621 12 standard IP modules APC8621A provides an electrical and 5 0 SERVICE AND
5. 50 pin Male Header with For APC8620A ejector latches A C Carrier Field l O 50 pin Male Header without For APC8621A ejector latches P4 5 9 12 15 IP Field 1 50 male plug header P3 6 9 for APC8621A AMP 173280 3 or equivalent 7 10 13 16 IP Logic 50 pin male plug header AMP 7 10 for APC8621A 173280 3 or equivalent Power Board power requirements are a function of the installed IP modules This specification lists currents for the carrier board only The carrier board provides 5V 12V and 12V power to each IP from the PCI bus Each IP module supply line is individually filtered and fused In addition the carrier board utilizes 3 3 Volts and 5 Volts for hardware Note that the maximum amount of current provided to the carrier card via the PCI bus varies with each system Refer to your system documentation for more information on PCI power specifications Fuses 5 volts 2 amps minimum per slot 12 volts 1 amp minimum per slot Note that fuse type and current limit may vary Contact Acromag for further details The power failure monitor circuit provides a reset to IP modules when the 5 volt power drops below 4 38 volts typically 4 31 volts minimum Currents specified are for the carrier board only for Models AP8620A 21A add the IP module currents for the total current required from each supply 3 3 Volts 10 130
6. 12V 1 F2 F4 F7 oo oo oo H e 12V 1 F5 F8 H IPB E F4 loo Minimum Current Rating p E H JUMPER SETTINGS o D AE eer DISABLE umm Y Y Memory Space 321 0490 1 27 0 325 ENABLE yw A Memory Space 7 0 295 lt gt 0 591 lt lt 1 605 lt 2 508 10608 lt lt 2 213 gt 6 600 4502 027 9 9 SAIYAS WIYLSNANI ayog sna 9L IP MODULE TO CARRIER BOARD MECHANICAL ASSEMBLY ASSEMBLY PROCEDURE 1 THREADED SPACERS ARE PROVIDED BY ACROMAG IN TWO DIFFERENT LENGTHS WITH IP MODULES THE SHORTER LENGTH IS FOR USE WITH APC8620 CARRIER BOARD SHOWN 2 INSERT FLAT HEAD SCREWS ITEM A THROUGH SOLDER SIDE OF IP MODULE AND INTO HEX SPACERS ITEM B AND TIGHTEN 4 PLACES UNTIL HEX SPACER IS COMPLETELY SEATED 3 CAREFULLY ALIGN IP MODULE TO CARRIER BOARD AND PRESS TOGETHER UNTIL CONNECTORS AND SPACERS ARE SEATED 4 INSERT PAN HEAD SCREWS ITEM C THROUGH SOLDER SIDE OF CARRIER BOARD AND INTO HEX SPACERS ITEM B AND TIGHTEN 4 PLACES M2x6 FLAT HEAD e SOLDER SIDE OF IP MODULE SCREW T CO
7. 16 bit IP Memory Space accesses require an additional 31 25ns when the IP is operating at 32MHz 5 32 bit IP Memory Space accesses require an additional 62 5ns when the IP is operating at 32MHz 3 0 PROGRAMMING INFORMATION This Section provides the specific information necessary to program and operate the APC8620A 21A non intelligent carrier board This Acromag APC8620A 21A is a PCI Specification version 2 2 compliant PCI bus slave carrier board The carrier connects a PCI host bus to the IP module s 16 bit data bus per the Industrial I O Pack logic interface specification on the mezzanine IP boards that are installed on the carrier The PCI bus is defined to address three distinct address spaces memory and configuration space The IP modules can be accessed via the PCI bus memory space only The PCI card s configuration registers are initialized by System software at power up to configure the card The PCI carrier is a Plug and Play PCI card As a Plug and Play card the board s base address and system interrupt request line are not selected via jumpers but are assigned by system software upon power up via the configuration registers A PCI bus configuration access is used to access a PCI card s configuration registers INDUSTRIAL I O PACK SERIES APC8620A APC8621A PCI Configuration Address Space When the computer is first powered up the computer s System configuration software scans the PCI bus to determine wh
8. LRESET CONTROL 12 IP MODULE D FIELD READY CLOCK D CONTROL CONTROL SERRE aed CARRIER ID STOP REGISTERS _ i ADS EXP SUPPLY clocks 12 FILTERS ieee KK CLOCK FUSES IP MODULE E FIELD 32 MHz CLOCK CONTROL CONTROL 8 MHz MULTIPLY OSCILLATOR BY 4 CLOCKS TO TRANSCIEVERS IP MODULES NOTE FOR MODEL APC8621A IP MODULES D amp E ARE NOT AVAILABLE 4502 025 ayog sna 2 1 2 1 50 50 49 49 2 48 48 47 47 46 46 CARRIER BOARD 45 45 44 44 43 43 42 42 la x 41 41 40 40 FEET 39 39 29 37 37 36 36 35 35 34 34 33 33 STRAIN 32 31 RELIEF NON SHIELDED 30 1004 534 RIBBON CABLE 29 29 2002 211 28 28 27 27 26 26 25 25 24 24 23 23 22 22 21 21 20 20 19 19 18 18 17 17 16 16 15 15 14 14 13 13 12 12 H 11 11 2227 1 5 CONNECTOR 8 8 PIN 1 ON CABLE E 7 10045912 IS DESIGNATED WITH 6 6 RED INK 5 5 3 2 2 NOTE SEVEN DIGIT PART NUMBERS ARE 1 1 ACROMAG PART NUMBERS XXXX XXX MODEL 5025 550 SCHEMATIC
9. spaces are accessible via the PCI bus space as given in Tables 3 3 A 32 bit PCI bus access will result in two 16 bit accesses to the IP module A 16 bit or 8 bit PCI bus access results in a single 16 bit or 8 bit access to the IP module respectively Carrier Status Control Register Read Write PCIBar2 00H The Carrier Board Status Register reflects and controls functions globally on the carrier board This includes monitoring the IP Error signal enabling disabling or monitoring IP and timeout interrupts performing a software reset including the carrier and IP modules and identifying if memory space is enabled INDUSTRIAL I O PACK SERIES APC8620A APC8621A BUS CARRIER BOARD BIT IP Interrupt Pending Register Read PCIBar2 02H 15 12 Carried Identification These bits are used for carrier identification Writing to these bits will result in the data being stored Reading these bits will result in the inverse of the stored value Reset Condition 1010 if Memory Space is not supported 1011 if memory space is supported Memory space support is controlled via a configuration jumper 08 Software Reset Write Writing a 1 to this bit causes a software reset Only Writing a O or reading this bit has no effect When set the software reset pulse will have a duration of 1us microsecond IP Module Access Time Out Interrupt Pending This bit will be 1 when there is a IP Module bits read as logic 0 I
10. The carrier may not be compatible with IP module inputs that require 5V CMOS Switching thresholds IP Clocks Re Support 8MHZ default or 32MHz IP clocks that are independently selected per each IP slot 16 bit and 8 bit Supports 128 byte values per IP module 16 8 bit Supports 1 32 bytes per IP consecutive odd byte addresses Also supports 32 words per IP via D16 data transfers Memory 16 and 8 bit Supports up to 8M bytes per IP Disabled enabled via a jumper J1 Supports two interrupt requests per IP and interrupt acknowledge cycles via access to IP INT space ENVIRONMENTAL Operating Temperature 0 to 70 C 40 to 85 C E Versions Relative Humidity 5 95 non condensing Storage Temperature 55 to 125 C PCI bus and IP module logic commons have a direct electrical connection As such unless the IP module provides isolation between the logic and field side the field I O signals are not isolated from the PCI bus Radiated Field Immunity Complies with EN61000 4 3 3V m 80 to 1000 2 amp 900MHz keyed and European Norm EN50082 1 with no register upsets Conduc
11. 8 05 9 06 10 Do 13 Asterisk is used to indicate active low signal BOLD ITALIC Logic Lines are NOT USED by the carrier board TABLE 2 2 PCI Bus P1 CONNECTIONS REQ amp 18 18 Ground D D C BE 3 E D D A AD 25 A INDUSTRIAL I O PACK SERIES APC8620A APC8621A 40 SDONE KEYWAY KEYWAY KEYWAY KEYWAY Notes Table 2 2 s used to indicate an active low signal BOLD ITALIC Logic Lines are NOT USED by the carrier board 1 may be either 3 3V or 5V DATA TRANSFER TIMING All PCI bus read or write cycles to the APC8620A 21A are typically implemented within 150n seconds FRAME active to TRDY active After 150n seconds the PCI bus is available to the system for other PCI bus activity As the PCI bus is released the APC8620A 21A completes the read or write cycle to the targeted IP module or carrier register within the access times given in Table 2 3 FIELD GROUNDING CONSIDERATIONS Carrier boards are designed with passive filters on each supply line to each IP module This provides maximum filtering and signal decoupling between the IP modules and the carrier board However the boards are considered non isolated since there is electrical continuity between the PCI bus and the IP grounds Therefore unless isolation is provided on the IP module itself the field connections not isolated from the PCI bus Care should be take
12. APC8620A APC8621A The PCI bus interface is implemented in the logic of the carrier board s PCI bus target interface chip The PCI bus interface chip implements PCI specification version 2 2 as an interrupting slave including 8 bit and 16 bit data transfers to the IP modules 32 bit IP data transfers will be treated as two 16 bit data transfers Note the APC8620A 21A requires that system 3 3 volts is present on the PCI bus 3 3V pins There are some older systems that do not provide 3 3 Volts on the PCI bus 3 3 volt pins The APC8620A APC8621A boards will not work in these systems Note that the APC8620A APC8621A board are not hot swapable The carrier board s PCI bus data transfer rates are shown in Table 2 3 Carrier Board Registers The carrier board registers presented in section 3 are implemented in the logic of the carrier board s FPGA An outline of the functions provided by the carrier board registers includes Identifying if memory space is enabled in the Carrier Identification Bits Selecting either a 8MHz 32MHz clock for each IP module in the Clock Control Register Monitoring the error signal received from each module is possible via the IP Error Bit Enabling of PCI bus interrupt requests from each IP module is possible via the IP Module Interrupt Enable Bit Enabling of interrupt generation upon module access time out is implemented via the Time Out Interrupt Enable Bit
13. MODEL 5025 550 SIGNAL CABLE lt 5 2 MODEL 5025 5552 1 0 TERMINATION PANEL 5 PIN CONNECTOR 1004 512 POLARIZING PIN 1 STRAIN RELIEF 1004 534 4501 462A 9 SAIYAS WIYLSNANI ayog sna 19 1 PIN 50 OF P1 amp P2 CONNECT TO Z P2 a SHIELD 50 50 49 49 48 48 47 47 46 46 45 45 44 44 43 43 42 42 41 41 40 40 39 39 38 38 37 37 36 36 35 35 34 34 33 33 32 32 31 31 30 30 29 29 28 28 27 27 26 26 25 25 24 24 23 23 22 22 21 21 2 2 19 19 18 18 17 17 16 16 15 15 14 14 13 13 12 12 11 11 10 10 9 9 8 8 7 7 6 6 5 5 4 4 3 3 2 2 1 2 P1 MODEL 5025 552 CARRIER BOARD 1 0 TERMINATION PANEL X gt FEET TOP VIEW STRAIN PIN RELIEF 50 RIBBON CABLE BLACK LINE ON CABLE CONNECTOR 1004 534 2002 261 INDICATES PIN 50 1004 512 4 A x POLARIZING 7 PIN 1 59 1004 512 SNA PIN 1 ON CABLE MARKINGS STRAIN RELIEF 1004 534 FRONT VIEW NOTE SEVEN DIGIT PART NUMBERS ARE ACRO
14. Monitoring an IP module access time out is possible via the IP Module Access Time Out Status Bit Identify pending interrupts the carrier s IP Module Interrupt Pending Bit Lastly pending interrupts be individually monitored the IP Module Interrupt Pending register IP Logic Interface The IP logic interface is also implemented in the logic of the carrier board s FPGA The carrier board implements ANSI VITA 4 1995 Industrial I O Pack logic interface specification and includes five three for APC8621A IP logic interfaces The bus address and data lines are linked to the address and data of the IP logic interface This link is implemented and controlled by the carrier board s FPGA The PCI bus to IP logic interface link allows a PCI bus master to Access up to 64 ID Space bytes for IP module identification via 8 bit or 16 bit data transfers using PCI bus Access up to 128 I O Space bytes of IP data 8 bit or 16 bit data transfers e Access up to 8M byes of Memory Space data via 8 bit or 16 bit data transfers e Access IP module interrupt space 8 bit or 16 bit PCI bus data transfers Respond to two IP module interrupt requests per IP module 11 PCI BUS CARRIER BOARD As per the ANSI VITA 4 1995 Industrial I O Pack logic interface specification only 4 IP modules may be running at 32MHz on the APC8620A to comply with bus loading requirements When an IP modul
15. and electrically protected with an anti static bag during shipment It is recommended that the board be visually inspected for evidence of mishandling prior CAUTION BUS CARRIER BOARD Power should be removed from the board when changing jumper configurations or when installing IP modules cables termination panels and field wiring Refer to Mechanical Assembly Drawing 4501 672 and your IP module documentation for specific configuration and assembly instructions IP Memory Space Configuration A configuration jumper must be set on the carrier prior to power up to enable IP Memory Space Setting this jumper will allow each IP module to use up to 8M bytes of Memory Space Note that the board will request 64M bytes of system memory during PCI configuration This value cannot be altered See diagrams 4502 026 or 4502 027 located in the drawings portion of this manual for jumper location and settings The jumper must be present in one of the two configurations for proper board operation Factory default is memory space disabled Interrupt Configuration No hardware jumper configuration is required for interrupts to applying power Interrupt enables and status flags are configured or viewed via programmable registers on the carrier board see Section 3 for programming details The carrier board passes interrupt SENSITIVE ELECTRONIC DEVICES DO NOT SHIP OR STORE NEAR STRONG ELECTROSTATIC ELECTROMAGNETIC The boar
16. memory space and space is assigned In addition the base addresses of the IP modules and carrier board registers are assigned in 32 bit memory space requests from the IP modules to the PCI bus Refer to the IP modules for their specific configuration requirements CONNECTORS Connectors of the APC8620A carrier consist of five three for APC86214 carrier IP module field I O connectors five three for APC8621A IP module logic connectors and one PCI bus interface connector These interface connectors are discussed in the following sections Carrier Field Connectors IP modules A through E Field connections are made via 50 pin ribbon cable connectors A B C D and E A B and C for APC86214 for IP modules in positions A through E A through C for APC8621A IP module assignment is marked on the board for easy identification see IP location drawing 4502 026 or 4502 027 for physical locations of the IP modules Flat cable assemblies and Acromag termination panels or user defined terminations can be quickly mated to the field I O connectors Pin assignments are defined by the IP module employed since the pins from the IP module field side correspond identically to the pin numbers of the 50 pin connectors Carrier field I O connectors A through E A through C for APC86214 are industry standard 50 pin low profile headers male with short ejector latches no ejector latches for APC8621A and they mate to ribbon cabl
17. 001 040 Phoenix Contact Type FLKM 50 The 5025 552 termination panel facilitates the connection of up to 50 field 1 signals and connects to the carrier boards via a flat ribbon cable Model 5025 550 x or 5025 551 x The field connectors on the carrier board connect the I O signals to the P2 connector on each of the Industrial I O Pack modules Field signals are accessed via screw terminal strips The terminal strip markings on the termination panel 1 50 correspond to P2 pins 1 50 on the Industrial I O Pack IP Each Industrial I O Pack IP has its own unique P2 pin assignments Refer to the IP module manual for correct wiring connections to the termination panel Schematic and Physical Attributes See Drawing 4501 464 Field Wiring 50 position terminal blocks with screw clamps Wire range 12 to 26 AWG Connections to Carrier P1 50 pin male header with strain relief ejectors Use Acromag 5025 550 x or 5025 551 x cable to connect panel to carrier board Keep cable as short as possible to reduce noise and power loss Mounting Termination panel is snapped on the DIN mounting rail Printed Circuit Board Military grade FR 4 epoxy glass circuit board 0 063 inches thick Operating Temperature 40 C to 100 C Storage Temperature 40 C to 100 C Shipping Weight 1 25 pounds 0 6kg packed 9L APC8620A LOCATION DIAGRAM
18. 15 11 Bus Number Choose a specific PCI bus in the system Zero if only one PCI bus Device Number Choose a specific board on the bus Function Number Choose a specific function in a device Function number is zero for the APC8620A 21A Register Number Used to indicate which PCI Configuration Register to access The Configuration 10 8 7 2 Registers and their corresponding register 0 numbers are given in Table 3 2 10 Read Only bits that return 0 Table 3 2 Configuration Registers D8 DO Vendor ID 1085 Command Rev ID Cache Base Addr Memory Mapped Configuration Registers Base Address for I O Mapped Configuration Registers PCIBar2 Base Address for Carrier IO ID INT Space PCIBar3 Base Address for Memory Space Not Used Subsystem Vendor ID Not Used Reserved Reserved 1 Optional address space that is enabled disabled via a jumper prior to power up 0 1 Ea 3 5 6 840 12 13 215 This board consumes 1K byte block and an optional 64M byte block that is enabled via configuration jumper prior to power up The 1K byte block of memory consumed by the board is composed of blocks of memory for the ID I O and INT spaces corresponding to five IP modules In addition a small portion of the 1K byte address space contains registers specific to the function of the carrier board The 64M byte block of
19. 8 98 9656 1 1 1 i 1 Dx E JI 8 GUMTREE OU Basis e o OF SSO om Y w 0 325 Ps 0 200 lt 0 2559 ke gt 0 591 ke 1 605 gt lt 2 508 0 608 e 2 213 He 12 283 JUMPER SETTINGS FUSE IDENTIFICATION DISABLE MIENNE IPA IPB IPC IPD IPE Memory Space 321 5 2 F1 F6 F9 F10 F13 ENABLE Memory Space 52 12V 1 F2 F4 F7 1215 12V 1 FS F8 11 14 nem 3 4502 026 Minimum Current Rating H Vic980dV VOcC98DdV SAIYAS WIYLSNANI ayog sna 2 APC8621A LOCATION DIAGRAM he re ee ee ee MC CHO EE H F1 9 Hee oo 83 2 F7 FUSE IDENTIFICATION 1 88 oo 3 362 5 IPA IPB IPC EH a a E PALM S Gh POY E e GA RD Ol IPC EE 5 2 F1 F6 F9 4 200 lt I
20. Acromag 3 Series APC8620A APC8621A Industrial I O Pack PCI Bus Non Intelligent Carrier Board USER S MANUAL ACROMAG INCORPORATED 30765 South Wixom Road P O BOX 437 Wixom MI 48393 7037 U S A Tel 248 624 1541 Fax 248 624 9234 Copyright 2005 Acromag Inc Printed in the USA Data and specifications are subject to change without notice 8500 764 06 005 INDUSTRIAL I O PACK SERIES APC8620A APC8621A PCI BUS CARRIER BOARD The information contained in this manual is subject to change APPENDIX inh it aa te eb 15 without notice Acromag Inc makes no warranty of any kind with CABLE MODEL 5025 550 15 regard to this material including but not limited to the implied CABLE MODEL 5025 551 15 warranties of merchantability and fitness for a particular purpose TERMINATION PANEL MODEL 5025 552 15 UE DRAWINGS Page update or keep current the information contained in this manual 45021026 LOCATION DIAGRAM 16 No of this manual be copied or reproduced in any form caer 1 without the prior written consent of Acromag Inc 4901872 MECHANICAL ASSEMBLY st 18 4502 025 APC8620A 21A BLOCK DIAGRAM 19 Tabl ot Contents Page 4501 462 CABLE 5025 550 NON SHIELDED 20 10 GENERAL INFORMATION 4501 463 CA
21. BLE 5025 551 SHIELDED 21 np Wnypqe msc c E 4501 464 TERMINATION PANEL 5025 552 22 KEY APC8620A 21A PCI BUS INTERFACE 5 SIGNAL INTERFACE IP MODULE CONTROL 2 0 PREPARATION FOR UNPACKING AND CARD CAGE BOARD CONFIGURATION Memory Space Configuration Interrupt Configuration Carrier Field I O Connectors IP modules A E IP Field I O Connectors IP modules IP Logic Interface Connectors IP modules IP Logic Strobe PCI BUS Connections DATA TRANSFER TIMING FIELD GROUNDING CONSIDERATIONS 3 0 PROGRAMMING PCI Configuration Address Configuration Transactions ET Configuration MEMORY Carrier Board Status Control Register IP Interrupt Pending Clock Control Register m
22. IP Module Interrupt IMPORTANT SAFETY CONSIDERATIONS It is very important for the user to consider the possible adverse effects of power wiring component sensor or software failures in designing any type of control or monitoring system This is especially important where economic property loss or human life is involved It is important that the user employ satisfactory overall system design It is agreed between the Buyer and Acromag that this is the Buyer s responsibility 1 0 GENERAL INFORMATION The APC8620A 21A card is a personal computer Peripheral Component Interconnect PCI bus card and is a carrier for the Industrial I O Pack IP mezzanine board field I O modules The carrier board provides a modular approach to system assembly since each carrier can be populated with any combination of analog input output digital input output communication etc IP modules Thus the user can create a board which is customized to the application This saves money and space a single carrier board populated with IP modules may replace several dedicated function PCI bus boards The APC8620A 21A non intelligent carrier board provides impressive functionality at low cost OMODMDANNNNDMDMOAAGAAGTAHRHPHHPHRHRHRWBWWNDND IP Module ID 10 Board Size Supported IP Operating IP Module I O
23. MAG PART NUMBERS MODEL 5025 551 SCHEMATIC MODEL 5025 551 SIGNAL CABLE SHIELDED 4501 463A 9 SAIYAS WIYLSNANI ayog sna 76 1234 5 6 7 8 9101112 15 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 51 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 1 12 34 5 6 7 9 10 111213 14 15 16 17 18 19 20 21 22 2524 25 26 27 28 29 30 51 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 1 MODEL 5025 552 TERMINATION PANEL SCHEMATIC RAIL DIN MOUNTING SHOWN HERE DIN EN 50035 32mm TERMINATION PANEL ACROMAG PART NUMBER 4001 040 RAIL DIN MOUNTING SHOWN HERE DIN 50022 35mm m EN SCREWDRIVER SLOT FOR 3 032 77 0 TB1 o000000000000000000000Q00O040QO Q O OO 0 00 O0O0Q0O0O0O0 O0 O0O09O0 O0 O0 00 i d 5 315 gt 135 0 TOP VIEW A Ac 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 1 3 5 7 9 1113 15 17 19 21 25 25 27 29 31 33 35 37 39 41 43 45 47 49 2 203 58 5
24. MPONENT SIDE OF IP MODULE THREADED 2 gt COMPONENT SIDE OF CARRIER BOARD BRACKET l M2x6 HEAD SCREW 9 SAIYAS WIYLSNANI ayog sna APC8620A APC8621A BLOCK DIAGRAM 6L Vic982dV VOC98DdV Saldas IVIH LSDONI 45 _ POWER POWER FAILURE LOW VOLTAGE 27999 SUPPLY SS MONITOR 5V 12 5 FILTERS amp FUSES IP MODULE A FIELD PCI BUS 433 le CONTROL i PLX LBE3 FPGA DATA 0 15 amp IP ADDRESS 1 6 TECHNOLOGY 2 5 pc 19030 POWER or INTERRUPT SUPPLY J i2 gt PENDING 1247 RST INTERFACE REGISTER 12 gt FILTERS CHIP pees fees IP MODULE B FIELD LA 1 27 mi L 0 Mm lt A INTERRUPT C BE 3 CONTROL REGISTER DSEL LD 15 45 POWER gt SUPPLY FRAME IPMODULE d FILTERS ane ERROR RDYI LINT amp FUSES IP MODULE FIELD e STATUS CONTROL TRDY DEVSEL GPIO IPMODULE a dl ACCESS AD 0 31 TIME OUT 45 L2
25. OARDS WHERE TO GET HELP If you continue to have problems your next step should be to visit the Acromag worldwide web site at http www acromag com Our web site contains the most up to date product and software information Go to the Support tab to access e X Application Notes Frequently Asked Questions FAQ s Product Knowledge Base Tutorials Software Updates Drivers An email question can also be submitted from within the Knowledge Base or directly from the Contact Us tab 5 application engineers can also be contacted directly for technical assistance via telephone or FAX through the numbers listed below When needed complete repair services are also available Phone 248 624 1541 Fax 248 624 9234 Email solutions acromag com INDUSTRIAL I O PACK SERIES APC8620A APC8621A 6 0 SPECIFICATIONS PHYSICAL Physical PCI 5 3 3V dual Card Length 8620 12 283 inches 312 0 mm Length 8621 6 600 inches 167 64 mm Height 4 200 inches 106 68 mm Board Thickness 0 063 inches 1 60 mm Max Component Height 0 380 inches 9 65 mm Max Component Height Under IP Modules 0 180 inches 4 57 mm Connectors P1 PCI PCI Specification 2 2 5 3 3V dual board card edge finger spacing A E Carrier Field l O
26. Space e e lt lt E m elo T oju m ojm lt S m e lt EN m e N lt ES dt Note Shaded areas not used by APC8621A carrier 1 The board will return 0 for all address that are not used Table 3 3 APC8620A 21A Carrier Board Memory Map PCIBar3 High Byte Low Byte PCIBar3 Hex D15 008 007 000 Hex 0000001 O7FFFFF 0800001 OFFFFFF 1000001 17 1800001 1FFFFFF 2000001 27FFFFF 2800001 Memory Space IPB Memory Space IPC Memory Space IPD Memory Space IPE Memory Space Not Used 0000000 07FFFFE 1000000 17FFFFE 1800000 v 1FFFFFE 2800000 v 3FFFFFF 3FFFFFE Note Shaded areas not used by APC8621A carrier 1 The board will return 0 for all address that are not used The APC8620A 21A base addresses are determined through the PCI Configuration Registers The addresses given in the memory are relative to the base addresses 2 PCIBar3 of the APC8620A 21A carrier as shown in Table 3 2 The addresses within each IP s own space are specific to that IP module Refer to the IP module s User Manual for information relating to the IP specific addressing The Carrier registers IP Identification ID spaces IP Input Output IO IP Interrupt spaces and Memory MEM
27. at PCI devices are present The software also determines the configuration requirements of the PCI card The system software accesses the configuration registers to determine how many blocks of memory space the carrier requires It then programs the carrier s configuration registers with the unique memory address range assigned The configuration registers are also used to indicate that the PCI carrier requires an interrupt request line The system software then programs the configuration registers with the interrupt request line assigned to the PCI carrier Since this PCI carrier is portable and not hardwired in address space this carrier s device drive provided by Acromag uses the mapping information stored in the carrier s Configuration Space registers to determine where the carrier is mapped in memory space and which interrupt line will be used Configuration Transactions The PCI bus is designed to recognize certain I O accesses initiated by the host processor as a configuration access Configuration uses two 32 bit I O ports located at addresses OCF8 and OCFC hex These two ports are e 32 bit configuration address port occupying I O addresses OCF8 through OCFB hex 32 bit configuration data occupying I O addresses OCFC through OCFF hex Configuration space shown in Table 3 1 is accessed by writing a 32 bit long word into the configuration address port that specifies the PCI bus the carrier board on the bus and t
28. by executing the interrupt service routine corresponding to the interrupt line asserted The interrupt service routine is executed only if the IRQ on the PC AT s 8259 interrupt controller has been previously unmasked see section 3 for programming details The interrupt service routine should respond to an interrupt by accessing IP Interrupt Select INTSEL space The interrupt service routine should also conclude the interrupt routine by writing the End Of Interrupt command to the PC AT s 8259 interrupt controller see section 3 for more details Power Failure Monitor The carrier board contains a 5 volts undervoltage monitoring circuit which provides a reset to the IP modules when the 5 volt power drops below 4 38 volts typical 4 31 volts minimum This circuitry is implemented per the Industrial Pack specification Power On Reset The carrier board will provide an asynchronous reset signal to all IP modules for at least 200ms following power up The IP reset signal will remain active until the FPGA is initialized INDUSTRIAL I O PACK SERIES APC8620A APC8621A Power Supply Fuses The 5V supply lines to each of the IP modules are individually fused with a current limit of at minimum 2 amps imposed by the fuses In addition the 12 and 12 supply lines to each of the IP modules are individually fused with a current limit of at minimum 1 amp imposed by the fuses A blown fuse can be identified by visible inspection or b
29. d IP modules eliminating the need to perform low level reads writes of registers and the writing of interrupt handlers IP MODULE QNX SOFTWARE Acromag provides a software product sold separately consisting of board QNX software This software Model IPSW API QNX is composed of QNX real time operating system libraries for all Acromag IP modules and carriers including the AVME9670 AVME9660 9630 APC8620A 21A ACPC8630 35 and ACPC8625 The software supports X86 PCI bus only and is implemented as library of C functions These functions link with existing user code to make possible simple control of all Acromag IP modules and carriers INDUSTRIAL I O PACK SERIES APC8620A APC8621A 2 0 PREPARATION FOR USE UNPACKING AND INSPECTION Upon receipt of this product inspect the shipping carton for evidence of mishandling during transit If the shipping carton is badly damaged or water stained request that the carrier s agent be present when the carton is opened If the carrier s agent is absent when the carton is opened and the contents of the carton are damaged keep the carton and packing material for the agent s inspection For repairs to a product damaged in shipment refer to the Acromag Service Policy to obtain return instructions It is suggested that salvageable shipping cartons and packing material be saved for future use in the event the product must be shipped This board is physically protected with packing material
30. d utilizes static sensitive MAGNETIC OR RADIOACTIVE FIELDS components and should only be handled at a static safe workstation CARD CAGE CONSIDERATIONS Refer to the specifications for loading and power requirements Be sure that the system power supplies are able to accommodate the power requirements of the carrier board plus the installed IP modules within the voltage tolerances specified IMPORTANT Adequate air circulation must be provided to prevent a temperature rise above the maximum operating temperature The lack of air circulation within the computer chassis is a cause for some concern Most if not all computer chassis do not provide a fan for cooling of add in boards The dense packing of the IP modules to the carrier board alone results in elevated IP module and carrier board temperatures and the restricted air flow within the chassis aggravates this problem Adequate air circulation must be provided to prevent a temperature rise above the maximum operating temperature and to prolong the life of the electronics If the installation is in an industrial environment and the board is exposed to environmental air careful consideration should be given to air filtering BOARD CONFIGURATION The carrier board is plug and play compatible and as such its board addresses are automatically assigned by the system auto configuration routine upon power up The base address of the carrier board s configuration registers in
31. data 8620 121 0 00000000 Read return inverse of without Memory support Not used registered data Reset Set to A APC8620A 21A Write register data ith Memory Validaadre s Read return inverse of bh rt registered data Reset Set to 12 PCI BUS CARRIER BOARD 5 0 SERVICE AND REPAIR SERVICE AND REPAIR ASSISTANCE Surface Mounted Technology SMT boards are generally difficult to repair It is highly recommended that a non functioning board be returned to Acromag for repair The board can be damaged unless special SMT repair and service tools are used Further Acromag has automated test equipment that thoroughly checks the performance of each board When a board is first produced and when any repair is made it is tested placed in a burn in room at elevated temperature and retested before shipment Please refer to Acromag s Service Policy Bulletin or contact Acromag for complete details on how to obtain parts and repair PRELIMINARY SERVICE PROCEDURE Before beginning repair be sure that all of the procedures in Section 2 Preparation For Use have been followed Also refer to the documentation of your carrier board to verify that it is correctly configured Verify that there are no blown fuses Replacement of the carrier and or IP with one that is known to work correctly is a good technique to isolate a faulty board CAUTION POWER MUST BE TURNED OFF BEFORE REMOVING OR INSERTING B
32. dustry standard IP modules Acromag provides the following interface products all connections to field signals are made through the carrier board which passes them to the individual IP modules Cables Model 5025 551 X Shielded Cable or Model 5025 550 X Non Shielded Cable A Flat 50 pin cable with female connectors at both ends for connecting carrier boards to Model 5025 552 termination panels The unshielded cable is recommended for digital I O while the shielded cable is recommended for optimum performance with precision analog I O applications The cables are available 4 7 or 10 feet legnths Custom lengths 12 feet maximum are available upon request Termination Panel Model 5025 552 DIN rail mountable panel provides 50 screw terminals for universal field I O termination Connects to carrier boards via flat 50 pin ribbon cable Model 5025 550 X or 5025 551 IP MODULE Win32 DRIVER SOFTWARE Acromag provides a software product sold separately to facilitate the development of Windows 98 Me 2000 XP applications accessing Industry Pack modules installed on Acromag PCI Carrier Cards and CompactPCI Carrier Cards This software Model IPSW API WIN consists of low level drivers and Windows 32 Dynamic Link Libraries DLLS that are compatible with a number of programming environments including Visual C Visual Basic Borland C Builder and others The DLL functions provide a high level interface to the carriers an
33. e PCI carrier by reading the carrier interrupt pending register 11 The interrupt service routine accesses the interrupt space of the IP module selected to be serviced Note that the interrupt space accessed must correspond to the interrupt request signal driven by the IP module 12 The carrier board will assert the INTSEL signal to the appropriate IP together with carrier board generated address bit A1 to select which interrupt request is being processed A1 low corresponds to INTREQO A1 high corresponds to INTREQ1 13 The IP module receives an active INTSEL signal from the carrier and supplies its interrupt vector to the host system during this interrupt acknowledge cycle An IP module designed to release its interrupt request on acknowledge will release its interrupt request upon receiving an active INTSEL signal from the carrier If the IP module is designed to release it s interrupt request on register access the interrupt service routine must access the required register to clear the interrupt request 14 Write End Of Interrupt command to PC AT s 8259 15 Ifthe IP interrupt stimulus has been removed and no other IP modules have interrupts pending the interrupt cycle is completed i e the carrier board negates its interrupt request INTA 4 0 THEORY OF OPERATION This section describes the basic functionality of the circuitry used on the carrier board Refer to the Block Diagram shown in the Drawing 4502 025 as you r
34. e connectors Type P N 3425 6600 INDUSTRIAL I O PACK SERIES APC8620A APC8621A IP Field I O Connectors IP modules A through E The field side connectors of IP modules A through E A through C for APC8621A mate to AMP 173280 3 connectors P4 P5 P9 P12 and P15 P3 P6 and P9 for APC8621A respectively on the carrier board IP locations are labeled on the board for easy identification Field and logic side connectors are keyed to avoid incorrect assembly The AMP 173280 3 connectors mate to AMP 173279 3 connectors or similar on the IP modules This provides excellent connection integrity and utilizes gold plating in the mating area Threaded metric M2 screws and spacers supplied with Acromag IP modules provide additional stability for harsh environments see Drawing 4501 672 for assembly details Pin assignments for these connectors are made by the specific IP model used and correspond identically to the pin numbers of the front panel connectors IP Logic Interface Connectors IP modules A through E The logic interface sides of IP modules A through E A through C for APC8621A mate to AMP 173280 3 connectors P6 P7 P10 P13 and P16 P4 P7 and P10 for APC8621A respectively on the carrier board IP locations are labeled on the board for easy identification Field and logic side connectors are keyed to avoid incorrect assembly The AMP 173280 3 connectors mate to AMP 173279 3 connectors or similar on the IP modu
35. e places data on the bus for all data read cycles any undriven data lines are read by the PCI bus as high because of pull up resisters on the carrier board s data bus Carrier Board Clock Circuitry A 32MHz clock obtained from a multiplied 8MHz clock is used to control the FPGA and the local bus Clocks are then driven to each IP module via a high speed transceiver to allow for a module independent selectable clock All clock lines include series damping resistors to reduce clock overshoot and undershoot PCI Interrupter Interrupts are initiated from an interrupting IP module However the carrier board will only pass an interrupt generated by an IP module to the PCI bus if the carrier board has been first enabled for interrupts Each IP module can initiate two interrupts which can be individually monitored on the carrier board After interrupts are enabled on the carrier board via the Interrupt Enable Bits see section 3 for programming details an IP generated interrupt is recognized by the carrier board and is recorded in the carrier board s Interrupt Pending Register A carrier board pending interrupt will cause the board to pass the interrupt to the PCI bus provided the Interrupt Enable bits of the carrier s Status Register have been enabled see section 3 for programming details The PC interrupt request line assigned by the system configuration software will then be asserted The PC AT will respond to the asserted interrupt line
36. eproduced on IP modules without signal degradation from the carrier board logic signals Individually Fused Power Fused 5V 12V and 12V DC power is provided A fuse is present on each supply line serving each IP module DLL Software is Available Acromag provides Windows 32 Dynamic Link Libraries DLLS controls software for Windows 98 Me 2000 XP This software Model IPSW API WIN provide a high level interface to the carriers and IP modules They are also compatible with a number of programming environments including Visual C Visual Basic Borland C Builder and others PCI BUS INTERFACE FEATURES Slave Module All read and write accesses are implemented as either a 32 bit 16 bit or 8 bit single data transfer Immediate Disconnect on Read The PCI bus will immediately disconnect after a read The read data is then stored in a read FIFO Data in the read FIFO is then accessed by the PCI bus when the read cycle is retried This allows the PCI bus to be free for other system operations while the read data is moved to the read FIFO Interrupt Support PCI bus INTA interrupt request is supported All IP module interrupts are mapped to INTA Carrier board software programmable registers are utilized as interrupt request control and status monitors BUS CARRIER BOARD SIGNAL INTERFACE PRODUCTS See Appendix for more information on compatible products This IP carrier board will mate directly to all in
37. es that read to respond to an interrupt request via the IP Module s the error signals indicate a non recoverable INTREQ1 signal An access to an interrupt select space results error from the IP such as a component failure in the IP module serving up an interrupt vector In addition or hard wired configuration error Refer to access to the interrupt space will cause some IP modules to your IP specific documentation to see if the release their interrupt request See each IP module s User error signal is supported and what it indicates Manual for details Reset condition Set to 0 The IP Interrupt Pending Register is used to individually identify pending IP interrupts or a pending carrier generated interrupt as a result of IP module time out access If multiple IP interrupts are pending software must determine the order in which they are serviced jor os o oe po D7 DO IPD IP D Into Into Int1 IntO Int1 IntO Pend Pend Pend Pend Pend Pend Pend Pend Not Used Time Out IPE IPE MSB LSB D15 D5 00 INDUSTRIAL I O PACK SERIES APC8620A APC8621A IP Module ID Space Read Only Each IP contains identification ID information that resides in the ID space per the IP specification This area of memory contains either 32 bytes Format ID or 64 bytes Format 11 ID of information at most Format requires read of only the least significant byte Fo
38. eview this material CARRIER BOARD OVERVIEW The carrier board is a PCI bus slave target board providing up to five three for APC8621A industry standard IP module interfaces The carrier board s bus interface allows intelligent single board computer PCI bus Master to control and communicate with IP modules that are present on the PCI bus carrier IP module field I O connections link to the field I O connections of the carrier which in turn are used to connect field electronic hardware to the carrier board via ribbon cable The PCI bus and IP module logic commons have a direct electrical connection i e they are not electrically isolated However the field I O connections be isolated from the PCI bus if an IP module that provides this isolation between the logic and field side is utilized A wide variety of IP modules are currently available from Acromag and other vendors that allow interface to many external devices for digital I O analog I O and communication applications PCI Bus Interface The carrier board s PCI bus interface is used to program and monitor carrier board registers for configuration and control of the board s documented modes of operation see section 3 In addition the PCI bus interface is also used to communicate with and control external devices that are connected to an IP module s field 1 signals assuming an IP module is present on the carrier board INDUSTRIAL I O PACK SERIES
39. he configuration register on the carrier being accessed A read or write to the configuration data port will then cause the configuration address value to be translated to the requested configuration cycle on the PCI bus Accesses to the configuration data port determine the size of the access to the configuration register addressed and can be an 8 16 or 32 bit operation Any access to the Configuration address port that is not a 32 bit access is treated like a normal computer I O access Thus computer I O devices using 8 or 16 bit registers are not affected because they will be accessed as expected Configuration Registers The PCI specification requires software driven initialization and configuration via the Configuration Address space This carrier provides 256 bytes of configuration registers for this purpose The PCI carrier contains the configuration registers shown in Table 3 2 to facilitate Plug and Play compatibility The Configuration Registers are accessed via the Configuration Address and Data Ports The most important Configuration Registers are the Base Address Registers and the Interrupt Line Register which must be read to determine the base PCI BUS CARRIER BOARD address assigned to the carrier and the interrupt request line that goes active on a carrier interrupt request Table 3 1 Configuration Address Port 31 Enables accesses to Configuration Data to be reveled copra oes on ine Pi 23 16
40. ier register 500nS Typical 8MHz 8 bit and 16 bit IP module read 850nS Typical 8MHz 32 bit IP module read 300nS Typical 32MHz 8 bit and 16 bit IP module read 500nS Typical 32MHz 32 bit IP module read PClbus INTA interrupt signal Up to two requests sourced from each IP mapped to INTA Interrupt vectors come from IP modules via access to IP module INT space 32 bit Memory Upon power up the system auto configuration process plug amp play maps the carriers base addresses for a 1K byte and if necessary 64M byte block of memory into the PCI bus 32 bit Memory Space INDUSTRIAL I O PACK SERIES APC8620A APC8621A INDUSTRIAL I O PACK COMPLIANCE This device meets exceeds all written Industrial I O Pack specifications per ANSI VITA 4 1995 for 8MHz and 32MHz operation with a maximum of four IP modules Supports Type and Type II ID space formats Mechanical Interface Carrier supports five single For APC8620A size IP modules A E or two double size and one single size IP module 32 bit IP modules are not supported Mechanical Interface Carrier supports three single For APC8621A size IP modules A C or one double size and one single size IP module 32 bit IP modules are not supported Electrical Interface Carrier drivers use 3 3V CMOS logic
41. iguration and control of IP modules Supports accesses to IP input output interrupt ID ROM and Memory data spaces Module Access Time Out Allows access to empty slots without system failure If the IP module accessed does not respond within 32u seconds the bus access is terminated without system failure This allows each IP slot to be probed to determine if an IP is installed A control register bit will be set and or issue of an interrupt request to indicate IP module time out access has occurred IP Module Selectable Clock Allows for each IP module to be individual configured to an 8MHz or 32MHz clock e Optional Screw Termination Panel Model supports field connection via screw terminals using the optional DIN rail mount termination panels Connectors Access I O Access to field I O signals is provided via industry standard 50 pin headers with ejector latches A separate header is provided for each IP module Supervisory Circuit Reset Generation microprocessor supervisor circuit provides power on power off and low power detection reset signals to the IP modules per the IP specification Individually Filtered Power Filtered 5V 12V and 12 DC power is provided to the IP modules via passive filters present on each supply line serving each IP This provides optimum filtering and isolation between the IP modules and the carrier board and allows analog signals to be accurately measured or r
42. les This provides excellent connection integrity and utilizes gold plating in the mating area Threaded metric M2 screws and spacers supplied with Acromag IP modules provide additional stability for harsh environments see Drawing 4501 672 for assembly details Pin assignments for these connectors are defined by the IP module specification and are shown in Table 2 1 IP Logic Strobe Connectors Each IP module has an uncommitted Strobe signal on the logic interface connector pin 46 The Strobe signal may be used as an optional input or output from the IP module On the APC8620A 21A the Strobe signals for each of the five IP modules are routed to 0 Ohms resistors Contact Acromag for further information on using the Strobe signals PCI Bus Connections Table 2 2 indicates the pin assignments for the PCI bus signals at the card edge connector Connector pins are designated by a letter and a number The letter indicates which side of a particular connector the pin contact is on B is on the component side of the carrier board while A is on the solder side Connector gold finger numbers increase with distance from the bracket end of the printed circuit board Refer to the PCI bus specification for additional information on the PCI bus signals PCI BUS CARRIER BOARD Table 2 1 Standard IP Logic Interface Connections Pin Description Number Pin Description Number DO 4 DO 6 po4
43. mA Typical 200mA Maximum 5 Volts 590 30mA Typical 50mA Maximum 12 Volts 59 OmA Not Used 12 Volts 5 OmA Not Used PCI BUS COMPLIANCE This device meets exceeds all written PCI Local Bus specifications per revision 2 2 dated December 1998 PCI BUS CARRIER BOARD Data Transfer Slave with 32 bit 16 bit and PCI bus Write Cycle Time PCI bus Read Cycle Time Write Complete Time Read Complete Time 8 bit data transfer operation 32 bit read or write accesses are implemented as two 16 bit transfers to the IP modules 150nS Typical measured from falling edge of FRAME to the falling edge of TRDY 150nS Typical The carrier issues a RETRY which frees the PCI bus while the read request is completed The bus will repeat the same read request until it completes with the requested data Time from FRAME active until LRDYi active All values assume 0 IP module wait states 300nS Typical carrier register 525nS Typical 8MHz 8 bit and 16 bit IP module write 900 8 Typical 8MHz 32 bit IP module write 350nS Typical 32MHz 8 bit and 16 bit IP module write 550nS Typical 32MHz 32 bit IP module write Time from FRAME active until LRDYi active All values assume 0 IP module wait states 250nS Typical carr
44. memory is composed of the Memory Space for up to five IP modules The carrier is configured to map this 1K byte and 64M byte block of memory into 32 bit memory space The system configuration software will allocate space by writing the assigned addresses into the corresponding Base Address registers of the Configuration Registers The memory map for APC8620A 21A is shown in Tables 3 3 INDUSTRIAL I O PACK SERIES APC8620A APC8621A PCI BUS CARRIER BOARD Table 3 3 APC8620A 21A Carrier Board Memory Map Hex D15 008 D07 000 Hex WONG 22 M Register 0003 IP Interrupt Pending Register 0022 0005 IP A Interrupt O Select Space 0004 0007 IP A Interrupt 1 Select Space 0006 000F IP C Interrupt 1 Select Space 0006 0011 iPDinteruptO Select Space 0010 IP E Interrupt 0 Select Space IP E Interrupt 1 Select Space Clock Control Register 0015 0017 0014 0018 001B 001A v 003F 0041 v 007F 0081 v 00BF 00C1 0101 013F 0141 017 0181 01 0201 027 0281 02 0301 037 0381 Not Used IPA ID Space IPB ID Space ID Space IPD ID Space IPE ID Space IPA Space IPB Space IPC Space IPD Space IPE Space Not Used IPA ID Space IPB ID Space IP C ID Space IP D ID Space IP E ID Space IPA Space IP B Space IP C Space IP D Space IP E
45. n in designing installations without isolation to avoid ground loops and noise pickup This is particularly important for analog I O applications when a high level of accuracy resolution is needed 12 bits or more Contact your Acromag representative for information on our many isolated signal conditioning products that could be used to interface to the IP input output modules PCI BUS CARRIER BOARD TABLE 2 3 APC8620A 21A Write and Read Complete Time Data Transfer Time Carrier Registers Write 300ns Typical Carrier Register Read 250ns Typical 8MHz IP Opertaion 8 and 16 bit IP Write 25ns Typical 00 Typical 500ns Typical 32 bit IP Read 50ns Typical Notes Table 2 3 1 The data transfer times given in table 2 3 are measured from the falling edge of FRAME to the falling edge of READY The PCI bus starts a data transfer cycle by driving FRAME low The APC8620A 21A signals the completion of a read or write cycle by driving READY low Note that an additional delay will occur during read cycles as the data is transferred to the PCI Bus These values may vary up to 125ns due to the asynchronous relationship between the PCI bus clock and the local clock 2 This access time assumes zero IP module wait states For each IP module wait state 125n seconds must be added to this value 3 This access time assumes zero IP module wait states For each IP module wait state 31 25n seconds must be added to this value 4
46. nterrupt Int IntO Access Time Out interrupt pending This bit Pend Pend Pend will be 0 when there is no interrupt pending Note Shaded areas not used by ACP8621A carrier Reset condition Set to 0 Writing a 1 to this bit will release the pending interrupt Where IP Module Access Time Out Status Status bit to indicated that the last IP module All Bits A bit will be a 1 when the corresponding access has timed out This bit only reflects the IP Interrupt interrupt is pending A bit will be a 0 last IP module access Pending when its corresponding interrupt is not 0 if last IP module access did not time out Read pending Polling this bit will reflect the IP 1 if last IP module access did time out module s pending interrupt status even if Time Out Interrupt Enable the IP interrupt enable bit is set to 0 When set to 1 this bit will enable the carrier Reset Condition Set to 0 An IP board to generate an interrupt upon time out of module pending interrupt bit will be an IP module access The default setting or cleared if its correspond interrupt request reset condition is 0 interrupt generation upon signal is inactive time out disabled The interrupt service routine in responding to the Time Out Access Clock Control Register Read Write PCIBar2 018H interrupt will need to set this bit to 0 to clear the pending interrupt request The Clock Control Register is used to select the operational IP Module Inte
47. odel number The unshielded cable is recommended for digital I O while the shielded cable is recommended for optimum performance with precision analog I O applications Application Used to connect Model 5025 552 termination panel to carrier board 50 pin field connectors Length Last field of part number designates length in feet The standard lengths available are 4 7 or 10 feet Custom lengths maximum 12 feet are available Contact Acromag for further details It is recommended that this length be kept to a minimum to reduce noise and power loss Cable 50 wire flat ribbon cable 28 gage Non Shielded cable model uses Acromag Part 2002 211 C3365 50 or equivalent Shielded cable model uses Acromag Part 2002 261 3M Type 3476 50 or equivalent Headers Both Ends 50 pin female header with strain relief Header Acromag Part 1004 512 3M Type 3425 6600 or equivalent Strain Relief Acromag Part 1004 534 3M Type 3448 3050 or equivalent Keying Headers at both ends have polarizing key to prevent improper installation Schematic and Physical Attributes For Non Shielded cable model see Drawing 4501 462 For Shielded cable model see Drawing 4501 463 Shipping Weight 1 0 pound 0 5Kg packed 15 PCI BUS CARRIER BOARD TERMINATION PANEL MODEL 5025 552 Type Termination Panel For Carrier Boards Application To connect field I O signals to the Industrial I O Pack IP Termination Panel Acromag Part 4
48. rmat II requires read of a 16 bit value The carrier will implement 16 bit reads to the ID space to allow support for either Format or Format Il Both fixed and variable information may be present within the ID ROM Variable information may include unique information required for the module The identification Section for each IP module is located in the carrier board memory map per Table 3 3 Refer to the documentation of your IP module for specific information about each IP module s ID Space contents IP Module I O Space Read Write The I O space on each IP module is fixed at 128 16 bit words 256 bytes The five three for APC8621A IP module spaces are accessible at fixed offsets from PCIBar2 IP modules may not fully decode their I O space and may use byte or word only accesses See each IP module s User Manual for details IP Module Memory Space Read Write Each IP module may contain up to 8M bytes of Memory Space arranged into 16 bit words The five three for the APC8621A IP module Memory spaces are accessible at fixed offset from PCIBar3 IP modules may not fully decode their Memory space and may use only byte or word accesses See each IP module s User Manual for details GENERATING INTERRUPTS Interrupt requests originate from the carrier board in the case of an access time out and from the IP modules Each IP may support 0 1 or 2 interrupt requests Upon an IP module interrupt request the carrier passes the in
49. rrupt Enable frequency of the individual IP modules A 0 default indicates When set to 1 this bit will enable the that the IP module is supplied with an 8MHz clock A 1 generation of IP module interrupts The default indicates that the IP module is supplied a 32MHz clock A reset setting or reset condition is 0 IP module will set all bits of this register to 0 interrupt generation disabled Interrupts must also be supported and configured at the IPs IP Module Interrupt Pending This bit will be 1 when there is an interrupt pending This bit will be 0 when there is no Not Used IP E IPD IP C IP B IPA CLK CLK CLK CLK CLK interrupt pending Polling this bit will reflect the IP Module s pending interrupt status even if Note Shaded areas not used by 8621 carrier the IP Module Interrupt Enable bit is set to O Reset condition Set to O IP Module Error IP Module Interrupt Space Read Only This bit will be 1 when there is an active IP Module Error signal This bit will be 0 when The Interrupt space for each IP module is fixed at two 16 bit all IP module Error signals are inactive This words Interrupt 0 select space is read typically by an interrupt bit allows the user to monitor the Error signals service routine to respond to an interrupt request via the IP of IP modules A through E A through C for Module s INTREQO signal Likewise interrupt 1 select space is APC8621A The IP specification stat
50. ted RF Immunity Electromagnetic Interference Immunity EMI Electrostatic Discharge Immunity ESD Surge Electric Fast Transient Immunity Radiated Emissions 14 BUS CARRIER BOARD Complies with EN61000 4 6 3V rms 150KHz to 80 2 European Norm EN50082 1 with no register upsets digital upset under the influence of EMI from switching solenoids commutator motors and drill motors Complies with EN61000 4 2 Level 3 8KV enclosure port air discharge and Level 2 4KV enclosure port contact discharge and European Norm EN50082 1 Not required for signal I O per European Norm EN50082 1 Complies with EN61000 4 4 Level 2 0 5KV at field I O terminals and European Norm EN50082 1 Meets or exceeds European Norm EN50081 1 for class B equipment Shielded cable with connections in shielded enclosure are required to meet compliance INDUSTRIAL I O PACK SERIES APC8620A APC8621A APPENDIX CABLE MODEL 5025 550 x Non Shielded MODEL 5025 551 x Shielded Type Flat Ribbon Cable 50 wires female connectors at both ends The x suffix designates the length in feet The factory standard lengths are 4 7 or 10 feet Custom lengths 12 feet maximum are available upon request Choose shielded or unshielded cable according to m
51. terrupt request onto the host provided that the carrier board is enabled for interrupts within the Carrier Board Status Register Sequence of Events For an Interrupt 1 Clear the interrupt enable bits in the Carrier Board Status Register by writing a O to bit 2 bit 3 2 Write interrupt vector to the location specified on the IP and perform any other IP specific configuration required do for each supported IP interrupt request 3 Determine the IRQ line assigned to the carrier during system configuration within the configuration register 4 Setup the PC AT s interrupt vector for the appropriate interrupt 5 Unmask the IRQ on the PC AT s 8259 interrupt controller 6 ThelP asserts an interrupt request to the carrier board asserts interrupt request line IntReqO or IntReq1 7 carrier drives PCI bus interrupt request signal INTA active 8 PC AT s drives the IRQ line assigned to the active carrier 9 The interrupt service routine pointed to by the vector set up in step 4 starts 10 Interrupt service routine determines which IP module caused the interrupt by reading the carrier interrupt pending register If multiple interrupts are pending the interrupt service routine software determines which IP module to service first In a 10 PCI BUS CARRIER BOARD PC interrupts are shared and can be from any slot on the backplane or from the mother board itself The driver must first check that the interrupt came from th
52. y use of an ohm meter The fuses are located under each IP slot near the logic connectors see figure 4502 026 or 4502 027 Note that fuse type and current limit may vary Contact Acromag for further details Power Supply Filters Power line filters are dedicated to each IP module for filtering of the 5 12 and 12 volt supplies The power line filters are a T type filter circuit comprising ferrite bead inductors and a feed through capacitor The filters provide improved noise performance as is required on precision analog IP modules Software Compatibility to the APC8620 APC8621 To provide backwards compatibility with all software for the APC8620 8621 the APC8620A 21A has the same PCI Device and Vendor ID and the option to disable IP Memory space A jumper set prior to power up is used to select between one of two configurations to load into the PCI interface chip Note that 32MHz clock support is available with both of the APC8620A 21A configurations In order to determine the current configuration of the hardware use either the PCI configuration register PCIBar3 address and or the Carrier Identification Register as outlined in table 4 1 The default factory jumper configuration is to disabled memory space Table 4 1 PCIBar3 Carrier Identification Register 2 15 12 APC8620 8621 Write no effect Not used Read undefined Reset undefined Write register

APC8620A/APC8621A User`s Manual

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