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User Manual - General Standards Corporation

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1. a 3 1 5 CHANNEL 1 CONTROL STATUS LOC 0xIO entente tentent tnn tens 3 1 6 CHANNEL 2 Tx ALMOST LOC 0x20 3 1 7 CHANNEL 2 RX ALMOST LOC 0x24 iu 3 1 8 CHANNEL 2 FIFO LOC 0x28 2 us 3 1 9 CHANNEL 2 CONTROL STATUS LOC 0 2 3110 CHANNEL 3 TX ALMOST LOC 0x30 3 1 11 CHANNEL 3 RX Almost LOC 0x34 cte ER qa nn isete 3112 CHANNEL 3 FIFO LOC 0X38 u scettr tette tete greeted 3 1 13 CHANNEL 3 CONTROL STATUS LOC 0x3C 3 1 14 CHANNEL 4 TX ALMOST LOC 0 40 3 1 15 CHANNEL 4 RX ALMOST LOC 0X44 3 1 16 CHANNEL 4 FIFO LOC 0x48 ettet teet e Yeast ee eed e ue e ae rb teet Pe E ettet 3 1 17 CHANNEL 4 CONTROL STATUS LOC 0x4C 3 1 18 CHANNEL 1 SYNC DETECTED LOC 0x50 3 1 19 CHANNEL 2 SYNC DETECTED LOC 0x54 un 3 1 20 CHANNEL 3 SYNC DETECTED LOC 0 58 3 121 CHANNEL 4 SYNC DETECTED LOC OX5C 3 1 22 INTERRUPT CONTROL LOC 0 60 3 123 INTERRUPT STATUS LOC nne eie pr PR ROREM ERE ERR 3 1 24 CHANNEL 1 USC LOC 0x100 to Ox17E 3 1 25 CHANNEL 2 USC LOC 0x200 to 0x27E 3 1 26 CHAN
2. 2 9 LOCAL CONFIGURATION REGISTERS BIT DESCRIPTIONS 29 1 Local Address Space 0 Range Register for PCI to Local bus PCI 0x00 292 Local Address Space 0 Local Base Address Re map Register for PCI to Local Bus PCI 0x04 27 2 93 Mode Arbitration Register 0 08 27 2 9 4 Local Register seen tare ER DROP a Re ete PUR REP 28 2 9 5 Local Expansion ROM Range Register for PCI to Local Bus PCI 0x10 eee 29 2 9 6 Local Expansion ROM Local Base Address Re map register for PCI to Local Bus and BREQo Control 58 10 4 ED tete te b E eap ee ee Neh 2 9 7 Local Bus Region Descriptor for PCI to Local Accesses Register PCI 0x18 2 9 8 Local Range register for Direct Master to PCI PCI seen 2 9 9 Local Bus Base Address register for Direct Master to PCI Memory 0 20 2 9 10 Local Base Address for Direct Master to PCI IO CFG Register PCI 0x24 2 9 11 PCI Base Address Re map register for Direct Master to PCI PCI 0x28 29 12 Configuration Address Register for Direct Master to PCI IO CFG PCI 0x2C 29 13 Local Address Space I Range Register for PCI to Local Bus PCI OxFO 29 14 Local Address Space 1 Local Ba
3. 02 0 Tx Idle Line Condition 000 SYNC Flag Normal 001 Alternating 1 amp 0 010 All Zeros 68 011 All Ones 100 Reserved 101 Alternating Mark amp Space 110 Space 111 Mark D3 RW TxWait on Underrun D7 4 Transmit Command 0000 Null Command 0001 Reserved 0010 Preset CRC 0011 Reserved 0100 Reserved 0101 Select FIFO Status 1110 Select FIFO Interrupt Level 0111 Select FIFO Request Level 1000 Send Frame Message 1001 Send Abort 1010 Reserved 1011 Reserved 1100 Reset DLE Inhibit 1101 Set DLE Inhibit 1110 Reset EOF EOM 1111 Set EOF EOM 3 3 27 TRANSMIT INTERRUPT CONTROL REGISTER TICR 3 3 27 1 Low LOC 0xn6C D0 RW 1 Read Count TC DI RW Tx Overrun INTERRUPT ARMED D2 RW Wait for Send Command D3 RW Tx CRC Sent INTERRUPT ARMED D4 RW Tx EOF EOT Sent INTERRUPT ARMED D5 RW Tx Abort Sent INTERRUPT ARMED D6 RW Tx Idle Sent INTERRUPT ARMED D7 RW Tx Preamble Sent INTERRUPT ARMED 3 3 27 2 High LOC D7 0 RW Tx FIFO Control and Status Fill Interrupt DMA Level 3 3 28 TRANSMIT SYNC REGISTER TSR 3 3 28 1 Low LOC 0xn70 D7 0 RW TSYN 7 0 3 3 282 High LOC 0xn72 D7 0 RW TSYN 15 8 3 3 29 TRANSMIT COUNT LIMIT REGISTER TCLR 69 3 3 29 1 Low LOC 0xn74 070 RW TCL7 0 3 3 2902 High LOC 0xn76 D7 0 RW 15 8 3 3 30 TRANSMIT CHARACTER COUNT REGISTER TCCR 3 3 30 1 Low LOC 0xn78 D7 0 RO TCC 7 0 3 3 302 High LOC 0xn7A D7 0 RO 15 8 3 3 31 TIME CONSTANT 1 REGISTER TC1R
4. 2 4 5 2 4 6 2 4 7 2 4 8 BIG LITTLE ENDIAN DESCRIPTOR REGISTER PCI 0x0C DO Configuration Register Big Endian Mode D1 Direct Master Big Endian Mode D2 Direct Slave Address Space 0 Big Endian Mode D3 Direct Slave Address Expansion ROM 0 Big Endian Mode D4 Big Endian Byte Lane Mode D5 Direct Slave Address Space 1 Big Endian Mode D6 DMA Channel 1 Big Endian Mode D7 DMA Channel 0 Big Endian Mode D8 31 Reserved LOCAL EXPANSION ROM RANGE REGISTER FOR PCI TO LOCAL BUs PCI 0 10 D0 10 Reserved D11 31 Specifies which PCI address bits will be used to decode a PCI to local bus expansion ROM LOCAL EXPANSION ROM LOCAL BASE ADDRESS RE MAP REGISTER FOR PCI TO LOCAL BUS AND BREQO CONTROL PCI 0x14 D0 3 Direct Slave BREQo Delay Clocks D4 Local Bus BREQo Enable D6 10 Reserved D11 31 Re map of PCI Expansion ROM space into a Local address space LOCAL ADDRESS SPACE O EXPANSION ROM BUS REGION DESCRIPTOR REGISTER PCI 0X18 D0 1 Memory Space 0 Local Bus Width 02 5 Memory Space 0 Internal Wait States data to data D6 Memory Space 0 Input Enable D7 Memory Space 0 Bterm Input Enable D8 Memory Space 0 Prefetch Disable D9 Expansion ROM Space Prefetch Disable D10 Read Prefetch Count Enable D11 14 Prefetch Counter D15 Reserved D16 17 Expansion ROM Space Local Bus Width D18 21 Expansion ROM Space Internal Wait States D22 Expansion ROM Space Ready Input Enable D23 Expansion ROM Space Bterm Input Enable D24 Memor
5. 3 3 2241 LOW LOC OSE ere e terr Peer e eH HERR ee PARE ere n eie Oe Re pert 3 3 22 2High ODIO 3 3 23 Receive Character Count Register RCCR 3 3 23 1 Low 0xn58 l a 3 3 23 2 High EOCOxXn5A eerte 3 3 24 Time Constant 0 Register TC0R a 3324 1 LOC Oxn5G Le it eed A 3 3 24 2 1 5 5 u ak san oe e karakterenes 3 325 Transmit Mode Register MR ue peter P jesus 3 3 25 TL Low VENERE GENE 3 3 25 2 Hiph 0Xxn06 ete a e pcenis esee ettet erheben 3 3 26 Transmit Command Status Register 3 3261 Low LOG 0xn68 Z eee ree aen dete eet ate ec E eder E aon A RE 3 3 26 2 High LOC OXnGA ecscsssssssssssssesssssssvessssssecssssssvesssssssscssssssvessssssvecsssssvsesssuusesssssusesssssuvecesssuessssssusesssssussessssseees 3 3 27 Transmit Interrupt Control Register TICR esee seen tentent nter 3 32 27 T Low LOC iet ERR ONERE QE aaa k Sau 93272 High EOC OxnOB eee eH ahina E E etn 3 328 Transmit Sync Register ISR u scite eee e EN ce e E ene enl 33281 LOWS Sa a S h S ie 3 3 28 2 High LOC
6. 1 00 WO Mode Control encoded as follows D9 D8 0 0 Normal Operation 0 1 Auto Echo 1 0 External Local Loop back 1 1 Internal Local Loop back D2 Channel Reset D7 3 WO Channel Command encoded as follows D11 as the LSB 00000 Null Command 00001 Reserved 00010 Reset Highest IUS 00011 Trigger Channel Load DMA 00101 Trigger Rx DMA 00110 Trigger Tx DMA 00111 Trigger Rx amp Tx DMA 00100 Reserved 00100 Rx FIFO Purge 00101 Tx FIFO Purge 01011 Rx amp Tx FIFO Purge 01100 Reserved 01101 Load Rx Character Count 01110 Load Tx Character Count 01111 Reserved 10000 Load 10001 Load 1 10010 Load TC0 amp 1 10011 Select Serial Data LSB First 10100 Select Serial Data MSB First 10101 Select Straight Memory Data 10110 Select Swapped Memory Data 10111 Reserved 11000 Rx Purge 11001 Reserved 11010 Reserved 11011 Reserved 11100 Reserved 11101 Reserved 11110 Reserved 11111 Reserved Selected upon reset 3 2 2 CHANNEL MODE REGISTER 3 22 1 Low LOC Oxn04 03 00 Mode encoded as follows 0000 Asynchronous 0001 External Synchronous 0010 Isochronous 0011 Asynchronous with CV 0100 Monosync 0101 Bisync 0110 HDLC 0111 Transparent Bisync 1000 NBIP 1001 802 3 1010 Reserved 1011 Reserved 1100 Reserved 1101 Reserved 1110 Reserved 1111 Reserved D7 D4 Rx Submode 3 0 32 22 High LOC 0xn06 D3 0 Transmitter Mode encoded as follows 0000 Async
7. 3 3 31 1 Low LOC 0xn7C D7 0 RW TCI7 0 3 3 312 High LOC Oxn7E D7 0 RW TC1 15 8 CHAPTER 4 HARDWARE CONFIGURATION 40 THE ON BOARD MASTER amp TRANSMIT RECEIVE CLOCKS The oscillator U3 is used for generating the on board clock It is factory installed at 33 33 MHz The oscillator Ul is used for generating a transmit receive clock It is factory installed at 20 MHz and may changed to accommodate different baud rates Any standard 8 or 14 pin dip oscillator will fit into the socket of Ul 4 1 EEPROM JUMPER J12 The jumper J12 is a 2x3 header These jumpers are used for manufacturer uses only It should not be necessary for any users of the PMC SIO4 RS232 to perform any operations involving these Jumpers 4 2 CABLE INTERFACE CONNECTIONS There is a 68 pin DSUB user I O interface connector PLUG mounted at the front edge of the board Ref Des PA2 for row PB2 for row B The part number is PSOE 068PI SRI TG manufacturer Robinsen Nugent The mating part number is 50 68 5 This cable is used for all 4 channels See Table 4 2 1 below for pin out Table 4 2 1 User Cable Pin Out PA2 Row A Signal Names Pins 2 Row B SignalNames Noconneet 6 Noconnect 40 Channel RXCIk 8 Chamel3RXCKk Channel 1 Cable CTS 9 Chamel3Cabe CTS 7 43 Channel 2 Cable DCD Channel 4 Cable DCD 66 34 Noco 68 4 3 THE ZIL
8. COC OIA REENE AEA 3 3 8 Test Mode Control Register TMCR u yy slash kuah aa tenentes 3 3 8 1 ONICO mE 3 3 8 2 High eei esae ga is dr e ee eO ws 3 3 9 Clock Mode Control Register CMCR 3 3 9 1 Low LOC 0xn20 3 3 9 2 High LOC 0xn22 s 3 3 10 Hardware Configuration Register 3 3 10 1 Low 0x024 3 3 10 2 High EC 0Xxn26 u teo rete eet e e kle cut Leste ee eee ete 3 3 11 Interrupt Vector Register 3 3 11 1 Low LOC 0 28 3 3 11 2 High LOC 0xn24A 3 3 12 I O Control Register IOCR a sd Sn as 2842 Low LOC 2 ns sal ia oe E ete et E E E a RC A A aS 3 3 12 2 High OXE EH E a 3 3 13 interrupt Control Register tenente ette treten tnnt ten entente end 3 3 13 1Low LOC ONIO 3 3 13 2 Hiph EOC 0xn32 reet hee S A uu l 3 3 14 Daisy Chain Control Register DCCR a CM EIN Bro EE 0 GER SIS TER 33 42 Hish RW LOG Qxn36 er 3 3 15 Miscellaneous Interrupt Status Register MISR SE EN Low EECO OX
9. D0 16 is used for the Almost Empty Flag D17 31 is used for the Almost Full Flag CHANNEL 3 RX LOC 0x34 D0 31 Channel 3 Rx Almost Data The data in this register is used for programming the Almost Flags of the Tx FIFOs for this channel D0 16 is used for the Almost Empty Flag D17 31 is used for the Almost Full Flag CHANNEL 3 FIFO LOC 0x38 D7 0 Channel 3 FIFO Data The FIFOs are setup in a way that the Rx FIFO and the Tx FIFO are located at the same address A write to this address will be directed toward the Tx FIFO and a read from this address will be directed toward the Rx FIFO CHANNEL 3 CONTROL STATUS LOC 0x3C DO Reset Channel 3 Tx FIFO Pulsed Writing a 1 to this bit will cause the channel 3 Tx FIFOs to be reset If the channel 3 Tx Almost register is not a value of 0x00000000 then this will also cause the channel 3 Tx FIFOs almost flags to be programmed After setting this bit to a 1 it is the software s responsibility to delay approximately 10ms before accessing the local side of the board again This bit is a self timed pulse therefore it is not necessary for software to return to clear this bit it will clear itself D1 Reset Channel 3 Rx FIFO Pulsed 49 Writing a 1 to this bit will cause the channel 3 Rx FIFOs to be reset If the channel 3 Rx Almost register is not a value of 0x00000000 then this will also cause the channel 3 Rx FIFOs almost flags to be programmed After s
10. 00 7 Special register level programming interface 0x00 No Interface defined D8 15 Sub class Encoding 0x80 Other bridge device D16 D23 Base Class Encoding other Bridge Device PCI CACHE LINE SIZE REGISTER OFFSET D0 7 System cache line sze in units of 32 bit words PCI LATENCY TIMER REGISTER OFFSET OXOD 00 7 Latency Timer PCI HEADER TYPE REGISTER OFFSET D0 6 Configuration Layout Type D7 Header Type PCI BuILT IN SELF TEST BIST REGISTER OFFSET OXOF D0 3 0 means pass non zero means the device failed D4 5 Reserved D6 PCI writes a 1 to invoke BIST D7 Return 1 if device supports BIST 0 if the device is not BIST compatible PCI BASE ADDRESS REGISTER FOR MEMORY ACCESS TO RUNTIME REGISTERS OFFSET 0 010 DO Memory space indicator D1 2 Location of register 00 Locate anywhere in 32 bit memory address space 01 Locate below I Mbyte memory address space 10 Locate anywhere in 64 bit memory address space 11 Reserved Note Hardcoded to 0 D3 Prefectchable Note Hardcoded to 0 D4 7 Memory Base Address Note Hardcoded to 0 D8 31 Memory Base Address PCI BASE ADDRESS REGISTER FOR I O ACCESS TO RUNTIME REGISTERS OFFSET 0X14 DO Memory space indicator D1 Reserved 2 3 12 2 3 13 2 3 14 2 3 15 2 3 16 2 3 17 2 3 18 2 3 19 D2 7 I O Base Address Note Hardcoded to 0 D8 31 I O Base Address Note Hardcoded to 0 PCI BASE ADDRESS REGISTER FOR MEMORY ACCE
11. Offset OxOC nete 2 8 7 PCI Latency Timer Register Offset 2 8 8 PCI Header Type Register Offset 0 2 8 9 PCI Built In Self Test BIST Register Offset 0x0F a 2 8 10 PCI Base Address Register for Memory Access to Runtime Registers Offset 0x010 2 8 11 PCI Base Address Register for I O Access to Runtime Registers Offset 0x14 2 8 12 PCI Base Address Register for Memory Access to Local Address Space 0 Offset Ox18 2 8 13 Base Address Register for Memory Accesses to Local Address Space 1 Offset Ox1C 2 8 14 PCI Base Address Register Offset 0 20 Era ae A 2 8 15 PCI Base Address Register Offset 0x24 sees n 2 8 16 PCI Base Cardbus CIS Pointer Register Offset 0x28 2 8 17 PCI Subsystem Vendor ID Register Offset 0x2C 2 8 18 Subsystem ID Register Offset Ox2E E T 2 8 19 PCI Expansion ROM Base Register Offset 0X30 2 820 PCI Interrupt Line Register Offset 0 3 2 821 PCI Interrupt Pin Register Offset 0x3D n entente 2 8 22 PCI Min Gnt Register Offset OX3E solens te e eR 2 8 23 PCI Max Lat Register Offset 0x3F
12. bit by writing a 1 to that bit position 2 10 10 LOCAL TO PCI DOORBELL REGISTER DESCRIPTION PCI 0x64 00 31 Doorbell register The local processor can write to this register and it will generate a PCI interrupt A PCI master can then read this register to determine which doorbell bit was asserted The local processor sets a doorbell by writing a 1 to a particular bit The PCI master can clear a doorbell bit by writing a 1 to that bit position 2 10 11 INTERRUPT CONTROL STATUS PCI 0X68 DO Enable Local Bus LSERR D1 D2 D3 D4 7 D8 Do D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 A value of 1 enables PCI 9080 to assert LSERR interrupt output when PCI bus Target Abort or Master Abort status bit is set in the PCI Status configuration register Enable Local Bus SERR when PCI parity error occurs during PCI 9080 Master Transfer or PCI 9080 Slave access or Outbound Free List FIFO Overflow Init Generate PCI Bus SERR When this bit is set to 0 writing a 1 generates a PCI bus SERR Mailbox Interrupt Enable A value of 1 enables a Local Interrupt to be generated when the PCI bus writes to Mailbox register 0 3 To clear the Local Interrupt the Local master must read the Mailbox Used in conjunction with Local interrupt enable Reserved PCI Interrupt Enable A value of 1 enables PCI interrupts PCI Doorbell Interrupt Enable A value of 1 enables doorbell interrupts Used in conjunc
13. nunana tentes 2 3 15 PCI Base Address Register Offset 0x24 n n u 2 3 16 PCI Cardbus CIS Pointer Register Offset 0x28 a 2 3 17 Subsystem Vendor ID Register Offset 0x20 ue us 2 3 18 Subsystem ID Register Offset 0 2 2 3 19 PCI Expansion ROM Base Register Offset 0x30 ttem ten entente 2 320 PCI Interrupt Line Register Offset 0 3 2 321 PCI Interrupt Pin Register 0 3 tenente tenente tenente 2 3 22 PCI Min Register Offset Ox3E Au estet tette tette tente tete Qa A 2 3 23 PCI Lat Register Offset OX3F ieron i i ieai i a a 24 LOCAL CONFIGURATION 5 2 4 1 Local Address Space 0 Range Register for PCI to Local bus PCI 0x00 242 Local Address Space 0 Local Base Address Re map Register for PCI to Local Bus PCI 0x04 11 243 Mode Arbitration Register PCI 0x08 n nn nuna 11 244 Big Little Endian Descriptor Register PCI 0x0C 13 24 5 Local Expansion ROM Range Register for PCI to Local Bus PCI 0x10 esee 13 24 6 Local Expansion ROM Local Base Address Re map register for PCI to Local Bus and BREQo Control PEAK Se 2 4 7 Local Address
14. the Parity Error Response bit in the Command Register is clear One of three conditions can cause this bit to be set 1 the PCI9080 detected a parity error during a PCI address phase 2 the PCI9080 detected a data parity error when it was the target of a write 3 the PCI9080 detected a data parity error when performing a master read operation Writing a 1 to this bit clears the bit 0 PCI REVISION ID REGISTER OFFSET 0x08 D0 7 Revision ID The silicon revision of the PCI9080 PCI CLASS CODE REGISTER OFFSET 0x09 OB D0 7 Register level programming interface 0 00 Queue Ports at 0x40 and Ox44 0x01 Queue Ports at 0x40 and 0x44 and Int Status and Int Mask at 0x30 and 0x34 respectively 08 15 Sub class Code 0x80 Other bridge device 0x00 I 2 O Device D16 D23 Base Class Code 0x06 Bridge Device I 2 O controller PCI CACHE LINE SIZE REGISTER OFFSET 0X0C D0 7 System cache line size in units of 32 bit words PCI LATENCY TIMER REGISTER OFFSET OXOD D0 7 PCI Latency Timer Units of PCI bus clocks the amount of time the PCI9080 as a bus master burst data on the PCI bus PCI HEADER TYPE REGISTER OFFSET D0 6 Configuration Layout Type Specifies the layout of bits 0x10 through Ox3F in configuration space Only one encoding 0 is defined All other encodings are reserved D7 Header Type A 1 indicates multiple functions A 0 indicates a single function PCI BUILT IN SELF TEST BIS
15. 0X0n72 a a tae eet ree ees Renee eee dence 3 3 29 Transmit Count Limit Register 3 3 29 1 Low LOC 0xn74 3 3 29 2 High LOC 0xn76 3 3 30 Transmit Character Count Register 2 3330 1 Lows LOC re Rt a Rer eee Eee PARU Eee ro 3 3 30 2 High Oxn TA C 3 3 31 Time Constant 1 Register PCIR u retener tete me fere nter E aaa 70 33 3 T4 Lows 00 ds nt bol tts Su od MS ELEM 70 333 312 High E ODER SER pre EGRE 70 CHAPTER 4 HARDWARE CONFIGURATION 71 4 0 THE ON BOARD MASTER amp TRANSMIT RECEIVE CLOCKS 4 1 EEPROM JUMPER 7 19 ett tro tere ete Sas 42 CABLE INTERFACE CONNECTIONS ies 43 THE ZILOG CLOCK SELECT JUMPERS J3 J4 J7 18 CHAPTER 1 INTRODUCTION 10 INTRODUCTION The PMC SIO4 RS232 interface card is capable of transmitting and receiving serial data generating interrupts and providing loop back testing This card provides the following specific functionality s PMC bus Interface Interrupt functionality FIFOs are provided for data transmit and for data receive to increase the size of the receive buffers User interface signals connections are provided via connector
16. 11 2 DMA Channel 0 PCI Address Register PCI 0x84 a 2 11 3 DMA Channel 0 Local Address Register PCI 0x88 entente tenerte 2 11 4 DMA Channel 0 Transfer Size Bytes Register 2115 Channel 0 Descriptor Pointer Register 10 90 2 11 6 DMA Channel 1 Mode Register PCI 0x94 2 11 7 DMA Channel PCI Data Address Register PCI 0x98 2 11 8 DMA Channel 1 Local Data Address Register PCI 0x9C ais 2 11 9 DMA Channel 1 Transfer Size bytes register PCI OxAO essent 2 11 10 DMA Channel 1 Descriptor Pointer Register PCI OXAA4 sees 2 11 11 DMA Command Status Register PCI 0xA8 eene 2 11 12 DMA Command Status Register PCI 0xA9 eene tenente tentent entrent rentrer tenen 2 11 13 DMA Arbitration Register 0 PCI OXAC 2 11 14 DMA Threshold Register 1 PCI 0xB0 2 12 MESSAGING QUEUE REGISTERS esee 2 12 1 Outbound Post List FIFO Interrupt Status Register PCI 0x30 2 122 Outbound Post List FIFO Interrupt MASK Register PCI 0x34 2 12 3 Inbound Queue Port Register PCI 0x40 while QSR 0 U a 2 12 4 Outbound Queue Port Register PCI 0x44 while QSR DO 1 2 125 Messaging Queue Configuration Register PCI 0xC0 2 12 6 Queue Base Address Register PCI 0
17. 2 OUTBOUND POST LIST FIFO INTERRUPT MASK REGISTER PCI 0x34 D0 2 Reserved D3 Outbound Post List FIFO Interrupt Mask Interrupt is masked when this bit is set D4 31 Reserved 2 12 3 INBOUND QUEUE PORT REGISTER PCI 0 40 WHILE QSR D0 1 D0 31 Value written by PCI master is stored into the Inbound Post List FIFO which is located in local memory at the address pointed to by the Queue Base Address FIFO Size Inbound Post Head Pointer From the time of the PCI write until the local memory write and update of the Inbound Post Queue Head Pointer further accesses to this register result in a retry local interrupt is generated when the Inbound Post List FIFO is not empty When the port is read by the PCI master the value is read from the Inbound Free List FIFO which is located in local memory at the address pointed the by The Queue Base Address Inbound Free Tail Pointer If FIFO is empty a value of FFFFFFFh is returned 2 124 OUTBOUND QUEUE PORT REGISTER PCI 0X44 WHILE QSR 00 1 D0 31 Value written by PCI master is stored into the Outbound Free List FIFO which is located in local memory at the address pointed to by the Queue Base Address 3 FIFO Size Outbound Free Head Pointer From the time of the PCI write until the local memory write and update of the Outbound Free Head Pointer further accesses to this register result in a retry If FIFO fills up a local LSERR interrupt is generated When the port I s read by the PCI
18. 62 CHANNEL 1 CABLE TX CTS s CHANNEL_1_CABLE_CTS 29 CHANNEL 1 RX CTS 1 CABLE CTS ___ JUMPERS 2X3 J14 CHANNEL L TX DCD lo 02 CHANNEL 1 CABLE TX DCD __ CHANNEL 1 DCD gt o oO CHANNEL 1 CABLE DCD n n 99 _ CHANNEL 1 RX DCD 0 7 1 CHANNEL 1 GABLE RX DCD JUMPERS 2X3 J15 CHANNEL 2 TX OTS _ ______ lo 2 2 CABLE TX CTS __ CHANNEL 2 CTS L O lt C CHANNEL 2 CABLE CTS ec Qa CHANNEL 2 CTS ______ 23 L CHANNEL 2 CABLE ____ JUMPERS 2X3 J16 CHANNEL 2 TX RCD 2 lo 2 2 CABLE TX DCD___ s CHANNEL 2 DOD L gt O 094 lt 2 CHANNEL 2 CABLE DCD rib 06 CHANNEL 2 RX DCD E L CHANNEL 2 CABLE RX DCD _ _ _ JUMPERS 2X3 J17 CHANNEL 3 TX lo 2 3 CABLE TX CTS ___ CHANNEL 3 CTS L C 2 40 O lt C CHANNEL 3 CABLE CTS OR CHANNEL CIS di L CHANNEL ____ JUMPERS 2X3 J18 CHANNEL 3 TX RCD 2 lo o2 CHANNEL 3 CABLE TX DCD CHANNEL 3 DOD L gt O 04 lt 2 CHANNEL CABLE DCD oe CHANNEL 3 RX pop ar L 3 CABLE RX DCD _ _ _ JUMPERS 2X3 J19 CHANNEL 4 TX CIS gt lg CHANNEL 4 CABLE TX CTS_ muon CHANNEL 4 CTS L 29 29 4 lt 2 CHANNEL 4 CABLE CTS A CHANNEL 4 RX CTS l 4 CABLE RX CTS __ JUMPERS 2X3
19. Address 0x0000000 yes Ch I Transfer Byte Count 0x00000000 OxA yes Ch 1 Descriptor Pointer 0x00000000 LI Dep Register DMA Ch 0 Command Status kaki ee Dep Dep Table 2 2 3 MESSAGING QUEUE REGISTERS Offset From Runtime yes yes Inbound Post Head Pointer 0 000000 000 yes Inbound Post Tail Pointer Ox00000000 OxD4 OxEO 0 00000000 OxES Note 1 when bit 0 of queue Status Register is set addresses 0x40 and 0x44 access queue ports when bit 0 is clear they access mailboxes which are always available at 0x78 and 0x7C 2 3 PCI CONFIGURATION REGISTER BIT MAPS 231 PCI CONFIGURATION ID REGISTER OFFSET 0X00 D0 15 Vendor ID D16 31 Device ID 2 3 2 PCI COMMAND REGISTER OFFSET 0X04 DO I O Space D1 Memory Space D2 Master Enable D3 Special Cycle D4 Memory Write Invalidate D5 VGA Palette Snoop This bit is not supported D6 Parity Error Response D7 Wait Cycle Control D8 SERR Enable D9 Fast Back to Back Enable D10 15 Reserved 233 PCI STATUS REGISTER OFFSET 0X06 D0 5 Reserved 06 User definable features D7 Fast Back to Back Capable D8 Master Data Parity Error Detected D9 10 DEVSEL Timing D11 Target Abort D12 Received Target Abort D13 Master Abort 2 3 10 2 3 11 D14 Signaled System Error 015 Detected Parity Error PCI REVISION ID REGISTER OFFSET 0 08 D0 7 Revision ID PCI CLASS CODE REGISTER OFFSET 0X09 0B
20. D6 07 D8 Do D10 D11 D12 Local DMA Bus Width A value of 00 indicates a DMA bus width of 8 bits A value of 01 indicates DMA bus width of 16 bits A value of 10 or 11 indicates a DMA bus width of 32 bits Internal Wait States data to data Ready Input Enable A value of 1 enables Ready input A value of 0 disables the Ready input Bterm Input Enable A value of 1 enables Bterm input A value of 0 disables Bterm input Local Burst Enable A value of 1 enables bursting A value of 0 disables bursting Chaining A 1 value indicates chaining mode is enabled For chaining mode the DMA source address destination address and byte count are loaded from memory in PCI or Local Address Spaces A 0 value indicates non chaining mode is enabled Done Interrupt Enable A 1 value enables interrupt when done A 0 value disables interrupt when done If DMA clear count mode is enabled the interrupt won t occur until the byte count is cleared Local Addressing Mode A 1 value indicates local addresses LA 31 2 to be held constant A 0 value indicates local address is incremented Demand Mode A value of 1 causes the DMA controller to operate in demand mode In demand mode the DMA controller transfers data when its DREQ input is asserted It asserts DACK to indicate that the current local bus transfer is in response to the DREQ input The DMA 37 2 112 2 11 3 2 114 2 11 5 controller transfers Lwords 32bits of data This may res
21. FIFO Almost Empty Enable Channel 1 Interrupt on Rx FIFO Almost Full Enable Channel 1 Interrupt on USC Request Interrupt Enable Channel 2 Interrupt on Sync Detected Enable Channel 2 Interrupt on Tx FIFO Almost Empty Enable Channel 2 Interrupt on Rx FIFO Almost Full Enable Channel 2 Interrupt on USC Request Enable Channel 3 Interrupt on Sync Detected Enable Channel 3 Interrupt on Tx FIFO Almost Empty Enable Channel 3 Interrupt on Rx FIFO Almost Full Enable Channel 3 Interrupt on USC Request Interrupt Enable Channel 4 Interrupt on Sync Detected Enable Channel 4 Interrupt on Tx FIFO Almost Empty Enable Channel 4 Interrupt on Rx FIFO Almost Full Enable Channel 4 Interrupt on USC Request Interrupt A lin any of these positions will enable the corresponding interrupt source to perform interrupt A 0inany of these positions will disable the corresponding interrupt source from performing a PMC interrupt 3 1 22 INTERRUPT STATUS LOC 0x64 3 1 24 3 1 25 3 1 26 3 1 27 D0 D1 D2 D3 D4 D5 D6 D7 D8 Do D10 D11 D12 D13 D14 D15 Note Status on Channel 1 Interrupt for Sync Detected Status on Channel 1 Interrupt for Tx FIFO Almost Empty Status on Channel 1 Interrupt for Rx FIFO Almost Full Status on Channel 1 Interrupt for USC Request Interrupt Status on Channel 2 Interrupt for Sync Detected Status on Channel 2 Interrupt for Tx FIFO Almost Empty Status on Channel 2 Interrupt for Rx FIFO Almost Full Status on Cha
22. If local space 1 is mapped into memory space bits are not used If mapped I O space bit is included with bits 31 4 for remapping 04 31 Remap of PCI Address to Local Address space 1 into a Local Address Space The bits in this register remap replace the PCI Address bits used in decode as the Local Address bits LOCAL ADDRESS SPACE 1 BUS REGION DESCRIPTOR REGISTER PCI OXF8 D0 1 Memory Space Local Bus Width A value of 00 indicates bus width of 8 bits A value of 01 indicates bus width of 16 bits A value of 10 indicates bus width of 32 bits D2 5 Memory space I Internal Wait States data to data 0 15 wait states D6 Memory space 1 Ready Input Enable A value of 1 enabes input A value of 0 disables Ready input D7 Memory space I BTERM Input Enable A value of 1 enables BTERM input A value of 0 disables BTERM input If this bit is set to 0 PCI 9080 bursts four Lword maximum at a time D8 Memory space 1 Burst Enable A value of 1 enables bursting A value of 0 disables bursting If burst is disabled the local bus performs continuous single cycle for burst PCI read write cycles Do Memory space 1 Prefetch Disable If mapped into memory space A value of 0 enables read prefetching A value of 1 disables read prefetching If prefetching is disabled PCI 9080 disconnects after each memory read D10 Read Prefetch Count Enable When set to 1 and memory prefetching is enabled PCI 9080 prefetches up to the number of Lwords spec
23. Input pin 01 Tx DMA Request Output 10 Output 0 11 Output 1 DCD Pin Control encoded as follows D7 6 00 DCD Input 01 DCD SYNC Input 10 Output 0 11 Output 1 CTS Pin Control encoded as follows 00 CTS Input 01 CTS Input 10 Output 0 11 Output 1 3 3 13 INTERRUPT CONTROL REGISTER ICR 3 3 13 1 Low LOC 0xn30 D0 RW D1 RW D2 RW D3 RW D4 RW D5 RW D7 6 3 3 13 2 High LOC 0xn32 DO RW D3 1 D4 RW D5 RW D6 RW D7 RW Device Status IE I O Status IE Transmit Data IE Transmit Status IE Receive Data IE Receive Status IE IE Command encoded as follows 00 Null Command 01 Null Command 10 Reset IE 11 Set IE Reserved VIS Level encoded as follows 000 All 001 All 010 I O Status and Above 011 Transmit Data and Above 100 Transmit Status and Above 101 Receive Data and Above 110 Receive Status Only 111 DLC NV VIS 3 3 14 DAISY CHAIN CONTROL REGISTER DCCR 3 3 14 1 Low LOC 0xn34 D0 RW D1 RW D2 RW Device Status INTERRUPT PENDING T O Status INTERRUPT PENDING Transmit Data INTERRUPT PENDING D3 D4 DS D7 6 3 3 14 2 High RW DO DI D2 D3 D4 D5 D7 6 RW Transmit Status INTERRUPT PENDING RW Receive Data INTERRUPT PENDING RW Receive Status INTERRUPT PENDING INTERRUPT PENDING Command encoded as follows 00 Null Command 01 Reset INTERRUPT PENDING and IUS 10 Reset INTERRUPT PENDING 11 Set INTERRUPT PENDING LOC 0xn36 RW Device S
24. J20 CHANNEL 4 TX DGD s 22 G2 CHANNEL 4 CABLE TX DCD_ CHANNEL 4 Og 70 JCHANNEL 4 CABLE DCD CHANNEL 4 BX DCD ______________ 9 1 GHANNEL 4 CABLE RX DCD_ JUMPERS 2X3 Figure 4 3 3 CTS DCD Jumper Arrangements for All Channels
25. Master I O Access Enable A value of lenables decode of Direct Master I O accesses A value of 0 disables decode of Direct Master I O accesses D2 LOCK Input Enable A 1 value enables LOCK input A value of 0 disables the LOCK input D3 Direct Master Red Prefetch Size control 00 PCI 9080 continues to prefetch read data from the PCI bus until Direct Master access is finished This may result in an additional four unneeded Lwords being prefetched from the PCI bus 01 Prefetch up to four Lwords from the PCI bus 10 2 Prefetch up to eight Lwords from the PCI bus 11 2 Prefetch up to 16 Lwords from the PCI bus If PCI memory prefetch is not wanted performs a Direct Master single cycle The direct master burst reads must not exceed the programmed limit D4 Direct Master PCI read mode A value of 0 indicates that the PCI9080 should release the PCI bus when the read FIFO becomes full A value of 1 indicates that the PCI9080 should keep the PCI bus and de assert IRDY when the read FIFO becomes full D5 8 10 Programmable Almost Full flag When the number of entries in the 32 word direct master write FIFO exceed this value the output pin DMPAFZ is asserted low D9 Write and Invalidate Mode When set to 1 PCI 9080 waits for 8 or 16 Lwords to be written from the local bus before starting PCI accesses When set all local Direct Master to PCI write accesses must be 8 or 16 Lwords bursts Use in conjunction with PCI 0x04 D10 Direct Master Prefetch Limit If
26. Memory Base Address Memory base address for access to Local Address Space 0 2 8 13 2 8 14 2 8 15 2 8 16 2 8 17 2 8 18 2 8 19 2 8 20 PCI BASEADDRESS REGISTER FOR MEMORY ACCESSES TO LOCAL ADDRESS SPACE 1 OFFSET Ox1C D0 Memory Space Indicator A value of 0 indicates register maps into memory space A value of 1 indicates register maps into I O space Specified in LASIRR register D1 2 Location of Register Location values 00 Locate anywhere in 32 bit memory address space 01 Locate below 1 Mbyte memory address space 10 Locate anywhere in 64 bit memory address space 11 Reserved Specified in LAS 1RR register If I O Space bit 1 is always 0 and bit 2 is included in the base address PCI BASE ADDRESS REGISTER OFFSET 0X20 D0 31 Reserved PCI BASE ADDRESS REGISTER OFFSET 0X24 D0 31 Reserved PCI BASE CARDBUS CIS POINTER REGISTER OFFSET 0X28 00 31 Cardbus Information Structure Pointer for PCMCIA Not supported PCI SUBSYSTEM VENDOR ID REGISTER OFFSET 0X2C 00 31 Subsystem Vendor ID unique add in board Vendor ID PCI SUBSYSTEM ID REGISTER OFFSET OX2E 00 31 Subsystem ID unique add in board Device D PCI EXPANSION ROM BASE REGISTER OFFSET 0X30 DO Address Decode Enable A value of I indicates the device accepts accesses to the expansion ROM address A value of 0 indicates the device does not accept accesses to expansion ROM space Should be set to I by PCI host if expansion ROM is pres
27. SUSTULIT 3 3 15 2 Highs EOC OZA oreet eir pte dee deter eO tede ede eset re is ed rs eee QB e RR 3 3 16 status interrupt control Register SICR a 3 3 16 T Low LOC OxN3 GE e ect ederent ete aet e e deett dee 9 3162 High LOC OxXBSE c 2217 Tx RseDat amp R eister RDRZTDBY L eer nd RR ge EP PLU ERA s e eret aa usu 3 3 17 1 Low LOG Oxn40 enceinte eo enean eo ho cese 3 312 High LLOC OXn42 L ettet tb tere ete det h nte 3 3 18 Receiver Mode Register 33 18 1 E09 LOG Oxn424 3 3182 High 0xn490 eerte terere eta eene nk 3 3 19 Receive Command Status Register 3 3 19 1 Lows 8 3 19 2 Highs OXp4A rodeo e eer Mo HERPES a aat 3 320 Receive Interrupt Control Register 33 20 Lows LOC Oxn4G s dde eee bee esed tesis esed eroe tuts 3 3202 High Eee eh ee eeu ege ayaka e e EAE eae aS 3 3 2 Receive Sync Register RSR ete ted terea ae Ep RUE 3 3 21 1 Low LOG 0 3 3212 High LOC 0xn52 4 tetto GANG ees i ea a Me eo tert beet ren 3 3 22 Receive Count Limit Register RCLR teret te
28. Space 0 Expansion ROM Bus Region Descriptor Register PCI 0x18 24 8 Local Range register for Direct Master to PCI PCI Ox1C seen 24 9 Local Bus Base Address register for Direct Master to PCI Memory 0 20 2 4 10 Local Base Address for Direct Master to PCI IO CFG Register PCI 0x24 24 11 PCI Base Address Re map register for Direct Master to PCI Memory PCI 0x28 24 12 Configuration Address Register for Direct Master to PCI IO CFG PCI 0x2C 24 13 Local Address Space I Range Register for PCI to Local Bus PCI OXFO sete 24 14 Local Address Space 1 Local Base Address Remap Register PCI 0xF4 24 15 Local Address Space 1 Bus Region Descriptor Register 0 sse 2 5 RUNTIME REGISTERS 5 ehh E 2 5 1 Mailbox Register 0 PCI 0x40 2 5 2 Mailbox Register 1 PCI 0x44 2 5 3 Mailbox Register 2 PCI 0x48 2 5 4 Mailbox Register 3 PCI 0x4C 2 5 5 Mailbox Register 4 PCI 0x50 2 5 6 Mailbox Register 5 PCI 0 54 2 5 7 Mailbox Register 6 PCI 0x58 2 5 8 Mailbox Register 7 PCI OXSC essere 2 5 9 PCI to Local Doorbell Register Description PCI 0x60 2 5 10 Local to PCI Doorbell Register Description PCI 0x64 2 2 5 11 Interrupt Control Status PCI 0x68 u 2 5 12 Serial EEPROM Control PCI Command Codes
29. User I O Control Init Control Register PCI 0x6O 16 2 5 13 PCI Permanent Configuration ID Register 0 70 2 5 14 PCI Permanent Revision ID Register PCI 0x74 n na 2 6 LOCAL DMA REGISTERS 2 6 1 Channel 0 Mode Register PCI 0x80 2 6 2 DMA Channel 0 PCI Address Register PCI 0x84 T s 2 6 3 DMA Channel 0 Local Address Register 10 88 2 6 4 DMA Channel 0 Transfer Size Bytes Register PCI 0x8C 2 6 5 DMA Channel 0 Descriptor Pointer Register PCI 0X90 2 6 6 DMA Channel I Mode Register PCI 0x94 esses entente teneret tenete tenente tenent tenente ens 2 6 7 DMA Channel 1 PCI Data Address Register PCI 0x98 2 6 8 DMA Channel 1 Local Data Address Register PCI 0x9C 2 6 9 DMA Channel 1 Transfer Size bytes register PCI 0xA0 2 6 10 DMA Channel I Descriptor Pointer Register 2 6 11 DMA Command Status Register PCI OxA8 u naa 2 6 12 DMA Channel I Command Status Register 0 PCI 0xA8 a 2 6 13 DMA Arbitration Register same as Mode Arbitration Register at address PCI OXAC 2 7 MESSAGING QUEUE REGISTERS l aaa ana Gana nu aaa aa 2 7 1 Outbound Post List FIFO Interrupt Status Register PCI 0x30 272 Outbound Post List FIFO Interrupt Status Register PCI 0x34 ae 2 73 Inbound Queue Port Register PCI 0x40 enrn
30. a 1 to this bit causes the channel to abort the current transfer The channel enable bit must be cleared The channel complete bit is set when the abort has completed D3 Clear Interrupt Writing a 1 to this bit clears channel 0 interrupts D4 Channel 0 Done A I value indicates this channels transfer is complete A 0 value indicates the channel transfer is not complete D5 7 User Defined 2 11 12 COMMAND STATUS REGISTER PCI 0XA9 DO Channel 1 Enable A 1 value enables the channel to transfer data 40 D1 D2 D3 D4 05 7 A 0 value disables channel from starting transfer and if in process of transferring data suspend transfer Pause Channel 1 Start Writing a 1 to this bit causes the channel to start transferring data if the channel is enabled Channel 1 Abort Writing a 1 to this bit causes the channel to abort the current transfer The channel enable bit must be cleared The channel complete bit is set when the abort has completed Clear Interrupt Writing a 1 to this bit clears channel 1 interrupts Channel 1 Done I value indicates this channel s transfer is complete A 0 value indicates the channel transfer is not complete Reserved 2 11 13 ARBITRATION REGISTER 0 PCI 2 11 14 DMA THRESHOLD REGISTER PCI 0 3 D4 7 D8 11 D12 15 D16 19 020 23 024 27 028 31 Channel 0 PCI to Local Almost Full COPLAF of Full Entries minu
31. bits 10 32 bits 11 64 bits D4 Tx Flag Preamble D7 6 Tx Status Block Transfer encoded as follows 00 No Status Block 01 One word Status Block 10 Two word Status Block 11 Reserved PRIMARY RESERVED REGISTER RESERVED Low LOC 0xn10 DO D7 RW Reserved High LOC 0xn12 00 07 RW Reserved SECONDARY RESERVED REGISTER RESERVED Low LOC Oxn14 00 07 RW Reserved High LOC 0xn16 D0 D7 RW Reserved TEST MODE DATA REGISTER TMDR 33 7 1 Low LOC 0 18 3 3 7 2 3 3 8 1 3 3 8 2 00 07 RW Test Data 7 0 High LOC Oxn1A 00 07 RW Test Data 7 0 TEST MODE CONTROL REGISTER TMCR Low LOC 0xn1C D4 0 Test Register Address encoded as follows 00000 Null Address 00001 High Byte of Shifters 00010 CRC Byte 0 00011 CRC Byte 1 00100 Rx FIFO Write 00101 Clock Multiplexer Outputs 00110 CTRO and CTR1 Counters 00111 Clock Multiplexer Inputs 01000 DPLL State 01001 Low Byte of Shifters 01010 CRC Byte 2 01011 CRC Byte 3 01100 Tx FIFO Read 01101 Reserved 01110 I O and Device Status Latches 01111 Internal Daisy Chain 10000 Reserved 10001 Reserved 10010 Reserved 10011 Reserved 10100 Reserved 10101 Reserved 10110 Reserved 10111 Reserved 11000 4044H 11001 4044H 11010 4044H 11011 4044H 11100 4044H 11101 4044H 11110 4044 11111 4044 D7 5 RW Reserved High LOC Oxn1E D7 0 RW Reserved CLOCK MODE CONTROL REGISTER CMCR 3 3 9 1 3 3 9 2 Low LOC 0xn20 D2 0 RW Receive Clock Sour
32. is a self timed pulse therefore it is not necessary for software to return to clear this bit it will clear itself Note that after power up and after any reset to this component the next access to channel 1 or channel 2 USC must be a write of 0x00 to offset 0x00 of channel 1 USC Channel 2 Tx FIFO Empty TRUE 0 48 3 1 10 3 1 11 3 1 12 3 1 13 D9 Channel 2 Tx FIFO Almost Empty TRUE 0 D10 Channel 2 Tx FIFO Almost Full TRUE 0 D11 Channel 2 Tx FIFO Full TRUE 0 D12 Channel 2 Rx FIFO Empty TRUE 0 D13 Channel 2 Rx FIFO Almost Empty TRUE 0 D14 Channel 2 Rx FIFO Almost Full TRUE 0 D15 Channel 2 Rx FIFO Full TRUE 0 The FIFO status flags are active low indicators of the current FIFO status These flags are continuously being updated every 33ns A value of 0 indicates that the current status is true and a value of 1 indicates that it is not true There are only 5 valid combinations for each nibble D8 D11 or D12 D15 These combinations are as follows OxC 1100 Almost Empty and Empty OxD 1101 Almost Empty but not Empty OxF 1111 In between Almost Empty and Almost Full OxB 1011 Almost Full but not full 0x3 0011 Almost Full and Full If there are any other combinations observed this is a strong indication of a problem CHANNEL 3 TX ALMOST LOC 0x30 D0 31 Channel 3 Tx Almost Data The data in this register is used for programming the Almost Flags of the Tx FIFOs for this channel
33. ns HERE HR URS 5 22 PEX REGISTERS onte Rp e HER ee NGA De RT ORE RTI aispa 6 23 PCI CONFIGURATION REGISTER MAPBS 8 2 3 1 PCI Configuration ID Register Offset 0 00 8 2 3 2 PCI Command Register Offset 0x04 2 33 PCI Status Register Offset 0x06 298 23 4 PCI Revision ID Register Offset 0 0 l su u aa tenete tenente tenente te tenet retener tete treten 2 3 5 PCI Class Code Register Offset 0x09 0B L ette tenet tete teens 2 3 6 PCI Cache Line Size Register Offset 0x0C n 2 3 7 PCI Latency Timer Register Offset OxOD esses eene tenente netten tenente tenerent 2 3 8 PCI Header Type Regis ter Offset OxOE sese tenentem tenete tenente enne 2 3 9 PCI Built In Self Test BIST Register Offset 0x0F u 2 3 10 PCIBase Address Register for Memory Access to Runtime Registers Offset 0x010 23 11 PCI Base Address Register for I O Access to Runtime Registers Offset 0 14 2312 PCI Base Address Register for Memory Access to Local Address Space 0 Offset Ox18 10 2 3 13 Base Address Register for Memory Access to Local Address Space 1 Offset Ox1C 10 23 14 PCI Base Address Register Offset 0 20
34. of 0 indicates Local Address Space 1 maps into PCI memory space A value of 1 indicates Local Address Space 1 maps into PCI I O space Encoded for Memory Space If mapped into memory space encoding is as follows 00 Locate anywhere in 32 bit PCI address space 01 Locate below I MB in PCI address space 10 Locate anywhere in 64 bit PCI address space 11 Reserved If mapped into I O space bit 1 must be set to 0 Bit 2 is included with bits 31 3 to indicate decoding range If mapped into memory space a value of 1 indicates reads are prefetchable bit has no effect on the operation of the PCI 9080 but is for system status If mapped into I O space bit is included with bits 31 2 to indicate decoding range Specifies which PCI address bits to use for decoding a PCI access to local bus space 1 Each of the bits corresponds to a PCI address bit Bit 31 corresponds to Address bit 31 Write a value of 1 to all bits that must be included in decode and a 0 to all others Used in conjunction with PCI Configuration Register Default is 1 MB LOCAL ADDRESS SPACE LOCAL BASE ADDRESS REMAP REGISTER PCI OXF4 DO Space 1 Enable A value of 1 enables decoding of PCI addresses for Direct Slave access to local space 1 A value of 0 disables decoding 2 9 15 2 10 2 10 1 If this bit is set to 0 the PCI BIOS may not allocate assign the base address for Space 1 Note Must be set to 1 for any Direct Slave access to Space 1 D1 Reserved 02 3
35. only 5 valid combinations for each nibble D8 D11 or D12 D15 These combinations are as follows OxC 1100 Almost Empty and Empty xD 1101 Almost Empty but not Empty OxF 1111 In between Almost Empty and Almost Full OxB 1011 Almost Full but not full 0x3 0011 Almost Full and Full If there are any other combinations observed this is a strong indication of a problem 3 1 14 CHANNEL 4 TX ALMOST LOC 0x40 D0 31 Channel 4 Tx Almost Data The data in this register is used for programming the Almost Flags of the Tx FIFOs for this channel D0 16 is used for the Almost Empty Flag D17 31 is used for the Almost Full Flag 3 1 15 CHANNEL 4 RX ALMOST LOC 0x44 D0 31 Channel 4 Rx Almost Data The data in this register is used for programming the Almost Flags of the Tx FIFOs for this channel D0 16 is used for the Almost Empty Flag D17 31 is used for the Almost Full Flag 3 1 16 CHANNEL 4 FIFO LOC 0x48 Channel 4 FIFO Data The FIFOs are setup a way that the Rx FIFO and the Tx FIFO are located at the same address A write to this address will be directed toward the Tx FIFO and a read from this address will be directed toward the Rx FIFO 3 1 17 CHANNEL 4 CONTROL STATUS LOC 0 4 D0 D1 D2 D6 3 D7 D8 D9 D10 D11 D12 D13 D14 D15 Reset Channel 4 Tx FIFO Pulsed Writing a 1 to this bit will cause the channel 4 Tx FIFOs to be reset If the channel 4 Tx Almost register is not a value of 0x00000000 th
36. value enables the PCI9080 to assert the BREQo output D6 10 Reserved D11 31 Re map of PCI Expansion ROM space into a Local address space The bits in this register re map replace the PCI address bits used in decode as the Local address bits LOCAL BUS REGION DESCRIPTOR FOR PCI TO LOCAL ACCESSES REGISTER PCI 0x18 D0 1 Memory Space 0 Local Bus Width A value of 00 indicates a bus width of 8 bits A value of 01 indicates a bus width of 16 bits A value of 10 or 11 indicates a bus width of 32 bits The bus width is forced to 16 bits for the Sx mode D2 5 Memory Space 0 Internal Wait States data to data 0 15 wait states D6 Memory Space 0 Ready Input Enable A 1 value enables Ready input A value of 0 disables the Ready input D7 Memory Space 0 BTERM Input Enable A I value enables BTERM input A value of 0 disables the BTERMH input D8 Memory Space 0 Prefetch Disable If mapped into memory space A 0 enables read pre fetching A value of 1 disables prefetching 2 9 8 If prefetching is disabled the PCI9080 will disconnect after each memory read D9 Expansion ROM Space Prefetch Disable A 0 enables read prefetching A 1 disables prefetching If prefetching is disabled the PCI9080 will disconnect after each memory read D10 Read Prefetch Count Enable When set to a 1 and memory prefetching is enabled PCI 9080 prefetches up to the number of Lwords specified in the prefetch count When set to 0 PCI 9080 ignores the count and contin
37. 0 Biphase Mark Space 11 Biphase Level D3 D2 DPLL Clock Rate encoded as follows 00 32x Clock Mode 01 16x Clock Mode 10 8x Clock Mode 11 Reserved D4 RW Accept Code Violations DS RW Rate Match DPLL CTRO D7 6 CTRO Clock Rate encoded as follows 00 32x Clock Mode 01 16x Clock Mode 10 8x Clock Mode 11 4x Clock Mode 3 3 11 INTERRUPT VECTOR REGISTER 33 11 1 Low LOC 0xn28 D3 1 RW IV 7 0 3 3 11 2 High LOC 0xn2A 60 D7 4 D15 D12 RO Modified Vector encoded as follows 000 None 001 Device Status 010 I O Status 011 Transmit Data 100 Transmit Status 101 Receive Data 110 Receive Status 111 Not Used IV 7 4 3 3 12 I O CONTROL REGISTER 3 12 1 Low LOC 0xn2C D2 0 D5 D3 33 122 High LOC Oxn2E D1 D0 D3 D2 RxC Pin Control encoded as follows 000 Input Pin 001 Rx Clock Output 010 Rx Byte Clock Output 011 SYNC Output 100 BRG0 Output 101 Output 110 CTR0 Output 111 DPLL Rx Output TxC Pin Control encoded as follows 000 Input Pin 001 Tx Clock Output 010 Tx Byte Clock Output 011 Tx Complete Output 100 BRG0 Output 101 Output 110 Output 111 DPLL Tx Output TxD Pin Control encoded as follows 00 Tx Data Output 01 3 State Output 10 Output 0 11 Output 1 RxREQ Pin Control encoded as follows 00 Input pin 01 Rx DMA Request Output 10 Output 0 11 Output 1 TxREQ Pin Control encoded as follows 00
38. 1 Interrupt Enable A value of 1 enables DMA Channel 1 interrupts Used in conjunction with Local interrupt enable Clearing the DMA status bits also clears the interrupt Value of 1 indicates local doorbell interrupt is active Value of 1 indicates DMA Ch 0 interrupt is active Value of 1 indicates DMA Ch 1 interrupt is active Value of 1 indicates BIST interrupt is active BIST Built In Self Test interrupt is generated by writing 1 to bit 6 of the PCI Configuration BIST register Clearing bit 6 clears the interrupt Refer to the BIST Register for a description of self test Value of 0 indicates a Direct master was the bus master during a master or Target abort Not valid until abort occurs D25 D26 D27 D28 D29 D30 031 Value of 0 indicates 0 was bus master during master Target abort Not valid until abort occurs Value of 0 indicates a CH 1 was the bus master during a master or Target abort Not valid until abort occurs Value of 0 indicates a Target Abort was generated by the PCI 9080 after 256 consecutive Master retries to a Target Not valid until abort occurs Value of 1 indicates PCI wrote data to the Mailbox 0 Enabled only if MBOXINTENB is enabled bit 3 high Value of 1 indicates PCI wrote data to the Mailbox 1 Enabled only if MBOXINTENB is enabled bit 3 high Value of 1 indicates PCI wrote data to the Mailbox 2 Enabled only if MBOXINTENB is enabled bit 3 high Val
39. 23 A value of 1 indicates that the BIST interrupt is active D24 A value of 0 indicates that a Direct Master was the bus master during a Master or Target abort D25 A value of 0 indicates that DMA CH 0 was the bus master during a Master or Target abort D26 A value of 0 indicates that DMA CH 1 was the bus master during a Master or Target abort D27 A value of 0 indicates that a Target Abort was generated by the PCI9080 after 256 consecutive Master retries to a Target D28 A value of 1 indicates PCI wrote data to the MailBox 0 D29 A value of 1 indicates PCI wrote data to the MailBox 1 D30 A value of 1 indicates PCI wrote data to the Mailbox 2 D31 A value of 1 indicates PCI wrote data to the Mailbox 3 SERIAL EEPROM CONTROL PCI COMMAND CODES USER I O CONTROL INIT CONTROL REGISTER PCI 0x6C 00 3 Read Command Code for DMA 04 7 PCI Write Command Code for DMA D8 11 PCI Memory Read Conmand Code for Direct Master D12 15 PCI Memory Write Command Code for Direct Master D16 General Purpose Output D17 General Purpose Input D18 23 Reserved D24 Serial EEPROM clock for Local or PCI bus reads or writes to Serial EEPROM D25 Serial EEPROM chip select D26 Write bit to serial EEPROM 2 5 13 2 5 14 2 6 2 6 1 2 6 2 2 6 3 2 6 4 2 6 5 D27 Read serial EEPROM data bit D28 Serial EEPROM present D29 Reload Configuration Registers D30 PCI Adapter Software Reset D31 Local Status 1 local init done PC
40. 257 Fax 408 493 0652 E mail moore eng pko dec com PCI Local Bus Specification Revision 2 1 June 1 1995 Questions regarding the PCI specification be forwarded to PCI Special Interest Group P O Box 14070 Portland OR 97214 800 433 5177 U S 503 797 4207 International 503 234 6762 FAX Zilog User s Manual and Product Specifications Databook for the Z16C30 USC requests should be forwarded to ZILOG Inc 210 East Hacienda Ave Campbell CA 95008 6600 408 370 8000 TABLE OF CONTENTS CHAPTER 1 INTRODUCTION seseeveseeveneserereeneneseseenesesesneneneneeveneneseseenenesesneneneneevenenenesvsneneseneeneneneneevenenenesnenenesesneneneneevenenesennene 1 1 0 INTRODUCTION ar ete rike EO NU rispe EE d dire e e reta 1 11 FUNCTIONAL DESCRIPTION 1 2 BOARD CONTROL REGISTER us m 13 BOARD STATUS REGISTERS ette CR rere erred iisas 1 4 SYNC WORD SELECTION 2 1 5 DATA REGEPBTION a aasan ia BUB UR a Gan aasan 2 1 6 DATA TRANSMITI ON ttp nanan ER Ede Yer Ru ner Sunan ana N Ga 2 1 7 ERROR DETECTION ndo p ep eU DIR E RERO B PEN ERR t 2 1 8 INTERRUPTS 5 ob A IR RIEN DU INTE EDT Iud ia e ne 3 CHAPTER 2 PCI CONFIGURATION REGISTERS 5 2 1 PCL CONFIGURATION REGISTERS L nu HERE HORE AERE REM
41. 54 D7 0 Channel 2 Sync Detected Data The data in this register is used to watch the Rx data asit is being loaded into the main Rx FIFO If the data being loaded into the FIFO for this channel matches this data then an interrupt request will be generated to interrupt logic An actual interrupt to the host will only occur if this interrupt source is enable in the interrupt control register CHANNEL 3 SYNC DETECTED LOC 0x58 D7 0 Channel 3 Sync Detected Data The data in this register is used to watch the Rx data as it is being loaded into the main Rx FIFO If the data being loaded into the FIFO for this channel matches this data then an interrupt request will be generated to the interrupt logic An actual interrupt to the host will only occur if this interrupt source is enable in the interrupt control register CHANNEL 4 SYNC DETECTED LOC 0x5C D7 0 Channel 4 Sync Detected Data The data in this register is used to watch the Rx data as it is being loaded into the main Rx FIFO If the data being loaded into the FIFO for this channel matches this data then an interrupt request will be generated to the interrupt logic An actual interrupt to the host will only occur if this interrupt source is enable in the interrupt control register INTERRUPT CONTROL LOC 0x60 DO D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 Note Enable Channel 1 Interrupt on Sync Detected Enable Channel 1 Interrupt on Tx
42. Address bits Note Remap Address value must be multiple of Range not the Range register MODE ARBITRATION REGISTER PCI 0 08 D0 7 D8 15 D16 D17 D18 D19 20 D21 D22 D23 D24 D25 Local bus Latency Timer Number of local bus clock cycles before negating HOLD and releasing the local bus This timer is also used with bit 27 to delay BREQ input to give up the local bus only when this timer expires Local bus Pause Timer Number of local bus clock cycles before reasserting HOLD after releasing the local bus Note Applicable only to DMA operation Local bus Latency Timer Enable A value of 1 enables latency timer Local bus Pause Timer Enable A value of 1 enables pause timer Local bus BREQ Enable A value of 1 enables local bus BREQ input When the BREQ input is active PCI 9080 negates HOLD and releases the local bus DMA Channel Priority A value of 00 indicates a rotational priority scheme A value of 01 indicates Channel 0 has priority A value of 10 indicates Channel 1 has priority A value of 11 is reserved Local bus direct slave give up bus mode When set to 1 PCI 9080 negates HOLD and releases the local bus when the Direct Slave write FIFO becomes empty during a Direct Slave write or when the Direct Slave read FIFO becomes full during a Direct Slave read Direct slave LLOCKo Enable A value of 1 enables PCI Direct Slave locked sequences A value of 0 disables Direct Slave locked sequences PCI Request
43. Configuration Register address 0x00 and returns the Subsystem and Subsystem Vendor ID D30 31 Reserved LOCAL REGISTER PCI D0 Configuration Register Big Endian Mode A value of 1 specifies use of Big Endian data ordering for local accesses to the configuration registers A value of 0 specifies Little Endian ordering Big Endian mode can be specified for configuration register accesses by asserting the BIGEND pin during the address phase of the access D1 Direct Master Big Endian Mode A value of 1 specifies use of Big Endian data ordering for Direct Master accesses A value of 0 specifies Little Endian ordering Big BIGEND input pin during the address phase of the access D2 Direct Slave Address Space 0 Big Endian Mode A value of 1 specifies use of Big Endian data ordering for Direct Slave accesses to Local Address space 0 A value of 0 specifies Little Endian ordering D3 Direct Slave Address Expansion ROM 0 Big Endian Mode A value of 1 specifies use of Big Endian data ordering for Direct Slave accesses to Expansion ROM A value of 0 specifies Little Endian ordering D4 Big Endian Byte Lane Mode A vlaue of 1 specifies that in Big Endian mode use byte lanes 31 16 for a bit local bus and byte lanes 31 24 for an 8 bit local bus A value of 0 specifies that in Big Endian mode byte lanes 15 0 be used for a 16 bit local bus byte lanes 7 0 for an 8 bit local bus DS Direct Slave Address Space Big Endian Mode A value of specifies
44. D1 RW D2 RW Rx Character Available Rx Overrun Parity Error Frame Abort D3 D4 D5 D6 D7 RO RW RW RW RW CRC Framing Error Rx CV EOT EOF Rx Break Abort Rx Idle Exited Hunt 3 3 19 2 High LOC Oxn4A DO RO D1 RO D2 RO D3 RO D7 4 WO D6 RO D7 RO Short Frame CV Polarity Residue Code 0 Residue code 1 Residue Code 2 Receive Command encoded as follows D12 being the LSB 0000 Null command 0001 Reserved 0010 Preset CRC 0011 Enter Hunt Mode 0100 Reserved 0101 Select FIFO Status 0110 Select FIFO Interrupt Level 0111 Select FIFO Request Level 1000 Reserved 1001 Reserved 1010 Reserved 1011 Reserved 1100 Reserved 1101 Reserved 1110 Reserved 1111 Reserved First Byte in Error Second Byte in Error 3 3 200 RECEIVE INTERRUPT CONTROL REGISTER RICR 3 3 20 1 Low LOC 0xn4C D0 D1 D2 D3 D4 D5 D6 D7 3 3 20 2 High LOC 4 RW RW RW RW RW RW RW RW D7 0 RW TCOR Read Count TC Rx Overrun INTERRUPT ARMED Parity Error Frame Abort INTERRUPT ARMED Status on Words Rx CV EOT EOF INTERRUPT ARMED Rx Break Abort INTERRUPT ARMED Rx Idle INTERRUPT ARMED Exited Hunt INTERRUPT ARMED Rx FIFO Control and Status Fill Interrupt DMA Level 3 3 21 RECEIVE SYNC REGISTER RSR 3 3 21 1 Low LOC 0xn50 D7 0 RW RSYNO 7 3 3 21 2 High LOC 0xn52 D7 0 RW RSYN15 8 3 3 22 RECEIVE COUNT LIMIT REGISTER RCLR 3 3 22 1 Low LOC 0xn54 D7 0 RW RCL7 0 3 3 2222 High L
45. D2 19 Reserved Outbound Free Pointer Local Memory Offset for Outbound Free List FIFO This register is initialized as 3 FIFO Size by the local CPU software D20 31 Queue Base Address 2 12 13 OUTBOUND POST HEAD POINTER REGISTER PCI OXEO DO 1 Reserved D2 19 Outbound Post Head Pointer Local Memory Offset for Outbound Post List FIFO This register is initialized as 2 FIFO Size by the local CPU software D20 31 Queue Base Address 2 12 14 OUTBOUND POST TAIL POINTER REGISTER PCI 0XE4 DO 1 Reserved D2 19 Outbound Post Tail Pointer Local Memory Offset for Outbound Post List FIFO This register is initialized as 2 FIFO Size and maintained by the MU hardware and is incremented modulo the FIFO size D20 31 Queue Base Address 2 12 15 QUEUE STATUS CONTROL REGISTER PCI DO 1 2 Decode Enable When this bit is set Mailbox registers 0 and 1 are replaced by the Inbound and Outbound Queue Port Registers and redefines Space 1 as PCI Base Address 0 to be accessed by PCIBARO Former Space 1 registers F4 and F8 should be programmed to configure their shared I 2 O memory space defined as PCI Base Address 0 D1 Queue Local Space Select When this bit is set to 0 use Local Address Space 0 bus region descriptor for queue accesses When this bit is set to 1 use Local Address Space 1 bus region descriptor for queue accesses D2 Outbound Post List FIFO Prefetch Enable When this bit is set prefetching occurs from
46. EEPROM data bit For reads this input bit is the output of the serial EEPROM It is clocked out of the serial EEPROM by the serial EEPROM clock Serial EEPROM present A lin this bit indicates that an EEPROM is present Reload Configuration Registers When this bit is 0 writing a 1 causes the PCI9080 to reload the local configuration registers from the serial EEPROM PCI Adapter Software Reset A value of 1 written to this bit will hold the local bus logic in the PCI9080 reset and LRESETO asserted The contents of the PCI configuration registers and Shared Run 031 Time registers will not be reset Software Reset can only cleared from PCI bus Local bus remains reset until this bit is cleared Local Init Status Value of lindicates local init done Responses to PCI accesses will be RETRYs until this bit is set While Input NB is asserted low this bit will be forced to 1 2 10 13 PCI PERMANENT CONFIGURATION ID REGISTER PCI 0x70 D0 15 Permanent Vendor ID Identifies device manufacturer Note Hardcoded to the PCI SIG issued vendor ID of PLX 10B5 D16 31 Permanent Device ID Identifies the particular device Note Hardcoded to the PLX part number for PCI interface chip PCI 9080 2 10 14 PCI PERMANENT REVISION ID REGISTER PCI 0 74 D0 15 Permanent Revision ID Note Hardcoded to the silicon revision of the PCI 9080 2 11 LOCAL REGISTERS 2 11 1 CHANNEL MODE REGISTER PCI 0x80 D0 1 D2 5
47. EL 1 LOCAL DATA ADDRESS REGISTER PCI 9 00 31 Local data Address Register This indicates where in the local memory space the transfers reads or writes will start from 2 11 9 DMA CHANNEL I TRANSFER SIZE BYTES REGISTER PCI 0XAO 00 22 Transfer Size Bytes Indicates number of bytes to be transferred during operation D23 31 Reserved 2 11 10 CHANNEL 1 DESCRIPTOR POINTER REGISTER PCI 4 DO Descriptor Location A 1 value indicates PCI address space A 0 value indicates Local address space D1 End of Chain A 1 value indicates end of chain A 0 value indicates not end of chain descriptor Same as Nonchaining Mode D2 Interrupt after Terminal Count A value causes an interrupt to be generated after the terminal count for this descriptor is reached A 0 value disables interrupts from being generated D3 Direction of transfer A 1 value indicates transfers from local bus to PCI bus A 0 value indicates transfers from PCI bus to local bus D4 31 Next Descriptor Address Quad word aligned bits 3 0 0000 2 11 11 DMA COMMAND STATUS REGISTER PCI 0XAS8 DO Channel 0 Enable A 1 value enables the channel to transfer data A 0 value disables the channel from starting a DMA transfer and if in the process of transferring data suspend transfer Pause D1 Channel 0 Start Writing a 1 to this bit causes the channel to start transferring data if the channel is enabled D2 Channel 0 Abort Writing
48. I 0 4 D0 31 32 bit mailbox register MAILBOX REGISTER 4 PCI 0x50 D0 31 32 bit mailbox register MAILBOX REGISTER 5 PCI 0x54 D0 31 32 bit mailbox register MAILBOX REGISTER 6 PCI 0x58 D0 31 32 mailbox register MAILBOX REGISTER 7 PCI 0x5C D0 31 32 mailbox register PCI TO LOCAL DOORBELL REGISTER DESCRIPTION PCI 0x60 D0 31 Doorbell register 2 5 10 2 5 11 2 5 12 LOCAL TO PCI DOORBELL REGISTER DESCRIPTION PCI 0x64 D0 31 Doorbell register INTERRUPT CONTROL STATUS PCI 0x68 DO Enable Local bus LSERR D1 Enable Local bus LSERR when a PCI parity error occurs during a PCI9080 Master Transfer or a PCI9080 Slave access D2 Generate PCI Bus SERR D3 Mailbox Interrupt Enable D4 7 Reserved D8 PCI Interrupt Enable D9 PCI doorbell interrupt enable D10 PCI Abort interrupt enable D11 PCI local interrupt enable D12 Retry Abort Enable D13 A value of 1 indicates that the PCI doorbell interrupt is active D14 A value of I indicates that the PCI abort interrupt is active D15 A value of I indicates that the PCI local interrupt input is active D16 Local interrupt output enable D17 Local doorbell interrupt enable D18 Local DMA channel 0 interrupt enable D19 Local DMA channel 1 interrupt enable D20 A value of 1 indicates that the Local doorbell interrupt is active D21 A value of 1 indicates that the DMA ch 0 interrupt is active D22 A value of I indicates that the DMA ch I interrupt is active D
49. I O ACCESS TO RUNTIME REGISTERS OFFSET 0X14 D0 Memory space indicator A value of 0 indicates register maps into Memory space A value of 1 indicates the register maps into I O space Note Hardcoded to 1 D1 Reserved D2 7 T O Base Address Base Address for I O access to runtime registers Minimum Block Size 128 bytes Note Hardcoded to 0 D8 31 I O Base Address Base Address for I O access to Local Runtime and DMA Registers PCI BASE ADDRESS REGISTER FOR MEMORY ACCESS TO LOCAL ADDRESS SPACE 0 OFFSET 0x18 DO Memory space indicator A value of 0 indicates register maps into Memory space A value of I indicates the register maps into I O space Specified in Local Address Space 0 Range Register LOC 0x80 D1 2 Location of register if memory space Location values 00 Locate anywhere in 32 bit memory address space 01 Locate below 1 Mbyte memory address space 10 Locate anywhere in 64 bit memory address space 11 Reserved Specified in Local Address Space 0 Range Register LOC 0x80 D3 Prefetchable 1f memory space A value of 1 indicates there are no side effects on reads This bit reflects the value of bit 3 in the LASORR register and provides only status to the system This bit has no effect on the operation of the PCI 9080 Prefetching features of this address space are controlled by the associated Bus Region Descriptor Register Specified in LASORR register If I O Space bit 3 is included in the base address D4 31
50. I PERMANENT CONFIGURATION ID REGISTER PCI 0x70 D0 15 Permanent Vendor ID D16 31 Permanent Device ID PCI PERMANENT REVISION ID REGISTER PCI 0x74 D0 7 Permanent Revision ID LOCAL DMA REGISTERS DMA CHANNEL 0 MODE REGISTER PCI 0x80 D0 1 Local Bus Width D2 5 Internal Wait States data to data D6 Ready Input Enable D7 Bterm Input Enable DS Local Burst Enable D9 Chaining D10 Done Interrupt Enable D11 Local Addressing Mode D12 Demand Mode D13 Write and Invalidate Mode for DMA Transfers D14 EOT End Of Transfer Enable D15 DMA Stop Data Transfer Mode D16 Clear Count Mode D17 DMA Channel 0 Interrupt Select D18 31 Reserved CHANNEL PCI ADDRESS REGISTER PCI 0 84 00 31 PCI Address Register CHANNEL 0 LOCAL ADDRESS REGISTER PCI 0x88 D0 31 Local Address Register DMA CHANNEL 0 TRANSFER SIZE BYTES REGISTER PCI 0 8 0 22 DMA Transfer Size D23 31 Reserved DMA CHANNEL 0 DESCRIPTOR POINTER REGISTER PCI 0x90 2 6 6 2 6 7 2 6 8 2 6 9 2 6 10 2 6 11 DO Descriptor Location D1 End of Chain D2 Interrupt after Terminal Count D3 Direction of transfer D4 31 Next Descriptor Address DMA CHANNEL 1 MODE REGISTER PCI 0 94 D0 1 Local Bus Width D2 5 Internal Wait States data to data D6 Ready Input Enable D7 Bterm Input Enable DS Local Burst Enable D9 Chaining D10 Done Interrupt Enable D11 Local Addressing Mode D12 Demand Mode D13 Write
51. JUMPERS T EU t 22 us u lt CHANNEL 2 TX 19 5 e pee pem 4 TT CHANNEL 2 ZILOG TX CLK PIN t 3e of 4 lt CHANNEL 2 ZILOG RX CLK PIN 19 CHANNEL 2 RX CLK 94g 5 11 12 amp 4 LA iE 1 re CHANNEL 2 ZILOG TX CLK PIN 1359 214 GHANNEL2 TX CHANNEL 2 2109 564 JUMPERS 2X8 SMT 2MM CHANNEL 3 CLOCK JUMPERS SS lt CHANNEL 3 TX 20 Je ME 6 gt og Mr CHANNEL 3 ZILOG TX PIN pua Bf CHANNEL 3 ZILOG CLK PIN 20 CHANNEL 3 RX CLK 10799 Og 7 ale SD X gt CHANNEL 3 ZLOG TX CLK PIN 7780 214 17 CHANNEL 3 20 CHANNEL 3 ZILOG RX CK PIN Bo 6184 JUMPERS 2X8 SMT 2MM CHANNEL 4 CLOCK JUMPERS o d 2 lt CHANNEL 4 21 ok O ls lt TICHANNEL 4 ZILOG TX CLK PIN o AE menm EOS Z CHANNEL 4 ZILOG CLK PIN 21 CHANNEL 4 RX gt t 52 STE ER lia ole EEE GET SE CHANNEL 4 ZILOG TX CLK PIN 13029 Sag 1 0HANNEL 4 21 CHANNEL 4 ZILOG RX CLK PN 152 26 1 JUMPERS 2X8 SMT 2MM Figure 4 3 2 Clock Jumper Arrangements for All Channels CHANNEL 1 TX CTS 1 ATEN IN UP o l P lo CHANNEL 1 CTS L C gt J13
52. MC DMA Request Encoder 210 000 Request DMA on Chan 1 Rx FIFO Almost Full amp Hold until Chan 1 Rx FIFO Almost Empty 001 Request DMA on Chan 1 Tx FIFO Almost Empty amp Hold until Chan 1 Tx FIFO Almost Full 010 Request DMA on Chan 2 Rx FIFO Almost Full amp Hold until Chan 1 Rx FIFO Almost Empty 011 Request DMA on Chan 2 Tx FIFO Almost Empty amp Hold until Chan 1 Tx FIFO Almost Full 100 Request DMA on Chan 3 Rx FIFO Almost Full amp Hold until Chan 1 Rx FIFO Almost Empty 101 Request DMA on Chan 3 Tx FIFO Almost Empty amp Hold until Chan 1 Rx FIFO Almost Empty 110 Request DMA on Chan 4 Rx FIFO Almost Full amp Hold until Chan 1 Rx FIFO Almost Empty 111 Request DMA on Chan 4 Tx FIFO Almost Empty amp Hold until Chan 1 Rx FIFO Almost Empty D3 Reserved D4 6 DMA Channel 1 Request Encoder 654 000 Request DMA on Chan 1 Rx FIFO Almost Full amp Hold until Chan 1 Rx FIFO Almost Empty 001 Request DMA on Chan 1 Tx FIFO Almost Empty amp Hold until Chan 1 Tx FIFO Almost Full 010 Request DMA on Chan 2 Rx FIFO Almost Full amp Hold until Chan 1 Rx FIFO Almost Empty 011 Request DMA on Chan 2 Tx FIFO Almost Empty amp Hold until Chan 1 Tx FIFO Almost Full 100 Request DMA on Chan 3 Rx FIFO Almost Full amp Hold until Chan 1 Rx FIFO Almost Empty 101 Request DMA on Chan 3 Tx FIFO Almost Empty amp Hold until Chan 1 Rx FIFO Almost Empty 110 Request DMA on Chan 4 Rx FIFO Almost Full amp Hold until Chan 1 Rx FIFO Almost Empty 111 Request DMA on Cha
53. Mode A value of 1 causes PCI9080 to negate REQ when it asserts FRAME during a master cycle A value of 0 causes PCI 9080 to leave REQ asserted for the entire bus master cycle PCI Rev 2 1 Mode When set to 1 PCI 9080 operates in Delayed Transaction mode for Direct Slave Reads PCI 9080 issues a RETRY and prefetches the read data PCI Read No Write Mode 2 9 4 A value of 1 forces a retry on writes if read is pending A value of 0 allows writes to occur while read is pending D26 PCI Read with Write Flush Mode A value of 1 submits a request to flush a pending read cycle if a write cycle is detected A value of 0 submits a request to not effect pending reads when a write cycle occurs PCI v2 1 compatible D27 Gate the Local Bus Latency Timer with BREQ If this bit 15 set to 0 PCI 9080 gives up the local bus during Direct Slave transfer after the current cycle if enabled and BREQ is sampled If this bit is set to 1 PCI 9080 gives up the local bus only if BREQ is sampled and the Local Bus Latency Timer is enabled and expires during Direct Slave or DMA transfer D28 PCI Read No Flush Mode A value of 1 submits request to not flush the read FIFO if PCI read cycle completes Read Ahead mode A value of 0 submits request to flush read FIFO if PCI read cycle completes D29 Reads Device or Vendor ID If set to 0 reads from the PCI Configuration Register address 0x00 and returns the Device ID and Vendor ID If set to 1 reads from the PCI
54. NEL 3 USC LOC 0x300 0x37E 7 ET iade 3 127 CHANNEL 4 USC LOC 0x400 to OxA TE ttes bt eter te e CREER TRE ERROR 3 2 SERIAL CONTROLLER REGISTERS u aaah a a sere Eee pa 3 2 1 Channel Command Address Register 3 2 1 1 EO UNDO Dm 3 2 1 2 High LOC 02 3 2 2 Channel Mode Register CMR 3 2 2 1 Low LOC 0xn04 Si sias BDO De cH OC DID tese ett Ed 3 2 3 Channel Command Status Register CCSR nn nnsnssnsssnsssanssssssssass 3 2 3 1 Low LOC 8 l E 3 2 3 2 High COCOON seernes is eenaa ele ka tbe dta see 3 2 4 Channel Control Register CCR 3 2 4 1 Low LOC 0xn0O 3 2 5 Primary Reserved Register RESERVED ies 3 2 5 1 L w 1 O L tette estt bie 3 2 5 2 High 12 aw E NN PARU QE eb ese at 3 3 6 Secondary Reserved Register 3 3 6 1 Low LOC Oxi ois u n uum Wu n 3362 High LOC 16 3 3 7 Test Mode Data Register TMDR 3 3 7 1 Low LOC Oxn18 zT c 33 72 High
55. OC 0xn56 D7 0 RW RCL15 8 3 3 23 RECEIVE CHARACTER COUNT REGISTER RCCR 3 3 23 1 Low LOC 0xn58 D7 0 RO RCC7 0 3 3 2232 High LOC 0xn5A D7 0 RO 5 8 3 3 24 TIME CONSTANT 0 REGISTER TCOR 3 324 1 Low LOC 0xn5C D7 0 RW TC07 0 3 3242 High LOC OxnSE D7 0 RW 7TC015 8 3 3 25 TRANSMIT MODE REGISTER TMR 3 3 25 1 Low LOC 0xn64 DO 1 Tx Enable encoded as follows DO being the LSB 00 Disable Immediately 01 Disable After Transmission 10 Enable Without Auto Enables 11 Enable With Auto Enables D2 4 Tx Character Length encoded as follows 000 8 Bits 001 I Bit DS D7 6 3 3 25 2 High LOC 0xn66 DO D1 D2 D4 3 RW RW RW RW 010 2 Bits 011 3 Bits 100 4 Bits 101 5 Bits 110 6 Bits 111 7 Bits Tx Parity Enable Tx Parity Sense encoded as follows 00 Even 01 Odd 10 Space 11 Mark Tx CRC Preset Value Tx CRC Enable Tx CRC on EOF EOM Polynomial Tx CRC encoded as follows 00 CRC CCITT 01 CRC 16 10 CRC 32 11 Reserved Tx Data Encoding encoded as follows 000 NRZ 001 NRZB 010 NRZI Mark 011 NRZI Space 100 Biphase Mark 101 Biphase Space 110 Biphase Level 111 Diff Biphase Level 3 3 26 TRANSMIT COMMAND STATUS REGISTER TCSR 3 3 26 1 Low LOC 0xn68 DO D1 D2 D3 D4 D5 D6 D7 RO RW RO RW RW RW RW RW Tx Buffer Empty Tx Underrun All Sent Tx CRC Sent Tx EOF EOT Sent Tx Abort Sent Tx Idle Sent Tx Preamble Sent 3 3 26 2 High LOC 0xn6A
56. OG CLOCK SELECT JUMPERS J3 14 J7 amp 18 The purpose of these jumpers 15 to select where the Zilog clock comes from or goes to If the Zilog clock uses the on board transmit receive clock or the cable clock then jumpers should be installed If the Zilog is going to generate an output clock to the cable then some of the jumpers should not be installed The Zilog Clock Select Jumpers are 2x8 the pin out is shown below there are individual jumpers for each channel see Figure 4 3 1 below for a graphical description of how Channels 1 amp 2 are configured Note Channels 3 amp 4 are implemented in the same manner substituting the following parts Jumpers J4 for Channel 3 and J7 for Channel 4 Jumper Pin Out Signal Name Chan Tx CIk 2 12 14 amp 16 Channel 1 J3 Tx Clk ce C H Upr Rx Clk Lwr Tx Clk H A A N LwrRx Clk N N N L C L 1 1 Upr Tx Clk C H H A Upr Rx Lwr Tx Clk A N N N Lwr Rx Clk N E E L L 2 2 Figure 4 3 1 Clock Arrangements for Channels 1 and 2 CHANNEL 1 CLOCK JUMPERS PLEN TI CHANNEL 1 TX CLK 18 k quaes PNE E D lt CHANNEL 1 2106 TX CLK PIN onc MAS mem D ER CHANNEL 1 ZILOG RX PIN 18 CHANNEL 1 RX CLK LT J oes CHANNEL 1 ZLOG TX GLK PIN 189 S14 1 CHANNEL 1 TX TS CHANNEL 1 ZILOG RX 154 JUMPERS 2X8 SMT 2MM CHANNEL 2 CLOCK
57. PMC SIO4 RS232 User Manual Preliminary General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 Fax 256 880 8788 URL www generalstandards com E mail http www techsupport generalstandards com PREFACE Copyright 1998 General Standards Corp Additional copies of this manual or other General Standards Corporation literature may be obtained from General Standards Corporation 8302A Whitesburg Drive Huntsville Alabama 35802 Telephone 256 880 8787 Fax 256 880 8788 Company URL www generalstandards com The information in this document is subject to change without notice General Standards Corporation makes no warranty of any kind with regard to this material including but not limited to the implied warranties of merchantability and fitness for a particular purpose Although extensive editing and reviews are performed before release to ECO control General Standards Corporation assumes no responsibility for any errors that may exist in this document No commitment is made to update or keep current the information contained in this document General Standards Corporation does not assume any liability arising out of the application or use of any product or circuit described herein nor is any license conveyed under any patent right of any rights of others General Standards Corporation assumes no responsibility resulting from omissions or errors in this manual or from the us
58. SS TO LOCAL ADDRESS SPACE 0 OFFSET 0x18 DO Memory space indicator D1 2 Location of register 00 Locate anywhere in 32 bit memory address space 01 Locate below I Mbyte memory address space 10 Locate anywhere in 64 bit memory address space 11 Reserved D3 Prefetchable D4 31 Memory Base Address PCI BASE ADDRESS REGISTER FOR MEMORY ACCESS TO LOCAL ADDRESS SPACE 1 OFFSET Ox1C DO Memory Space Indicator D1 2 Reserved D3 Prefetchable 04 31 Memory Base Address PCI BASE ADDRESS REGISTER OFFSET 0X20 D0 31 Reserved PCI BASE ADDRESS REGISTER OFFSET 0X24 D0 31 Reserved PCI CARDBUS CIS POINTER REGISTER OFFSET 0 28 D0 31 Reserved PCI SUBSYSTEM VENDOR ID REGISTER OFFSET 0X2C D0 15 Reserved PCI SUBSYSTEM ID REGISTER OFFSET OX2E D0 15 Reserved PCI EXPANSION ROM BASE REGISTER OFFSET 0X30 DO Address Decode Enable D1 10 Reserved D11 31 Expansion ROM Base Address upper 21 bits 10 2 3 20 2 3 21 2 3 22 2 3 23 24 2 4 1 2 4 2 2 4 3 PCI INTERRUPT LINE REGISTER OFFSET 0X3C D0 7 Interrupt Line Routing Value PCI INTERRUPT PIN REGISTER OFFSET 0X3D 00 7 Interrupt Pin register PCI MIN_GNT REGISTER OFFSET 0X3E D0 7 Min_Gnt PCI MAX_LAT REGISTER OFFSET 0X3F D0 7 Max Lat LOCAL CONFIGURATION REGISTERS LOCAL ADDRESS SPACE 0 RANGE REGISTER FOR PCI TO LOCAL BUS PCI 0x00 DO Memory space indicator 01 2 If mapped into memory space encoded as follows 2 1 M
59. T REGISTER OFFSET OXOF D0 3 Avalue of 0 means the device has passed its test Non zero values mean the device failed Device specific failure codes can be encoded in the non zero value D4 5 Reserved Device returns 0 D6 PCI writes a 1 to invoke BIST Generates an interrupt to local bus Local bus resets the bit when BIST is complete Software should fail device if BIST is not complete after 2 seconds Refer to Runtime registers for interrupt control status D7 Return 1 if device supports BIST Return 0 if the device 15 not BIST compatible 2 8 10 PCI BASE ADDRESS REGISTER FOR MEMORY ACCESS TO RUNTIME REGISTERS OFFSET 0x010 D0 Memory space indicator A value of 0 indicates register maps into Memory space A value of 1 indicates the register maps into I O space Note Hardcoded to 0 D1 2 Location of register 2 8 11 2 8 12 00 Locate anywhere in 32 bit memory address space 01 Locate below 1 Mbyte memory address space 10 Locate anywhere in 64 bit memory address space 11 Reserved Note Hardcoded to 0 D3 Prefectchable A value of 1 indicates there are no side effects on reads This bit has no effect on the operation of thPCI 9080 Note Hardcoded to 0 D4 7 Memory Base Address Memory base address for access to Local Runtime and DMA registers default is 256 bytes Note Hardcoded to 0 D8 31 Memory Base Address Memory base address for access to Local Runtime and DMA registers PCI BASE ADDRESS REGISTER FOR
60. after Runtime Size R W Register Name Reset PCI Base Range for PCI to Local Address Space 0 xFFF00000 000 Local Base Address Re map for PCI to Local ne Address Space 0 BE eee D32 yes no Big LittleEndian Descriptor 1 0 Dep Expansion ROM and BREQo control Accesses Cx Mode Dep Gd bet FA e a Kall Dep Memory Memory Real Dep to PCI Master to PCI IO CFG Range f for PCI to Local Address Space 1 0x00000000 Ox170 Kel bal al a eal Led al Address Space 1 fa ha marines el to Local Accesses Table 2 2 2 RUN TIME REGISTERS Offset Access From Value Runtime Size R W Register Name after reset PCI Base Mailbox Register 0 see note 1 000 Ox40 Matic nes Mailbox Register 7 0x00000000 D32 PCI to Local Doorbell Register 0x00000000 Local to PCI Doorbell Register 0x00000000 Dep Dep I O Control Init Control Dep Dep Dep Dep Table 2 2 3 DMA REGISTERS Offset Access From Value after Runtime Size R W Register Name Reset PCI Base DMA Ch 0 Mode 0x00000003 Cx and Jx modes yes DMA Ch 0 PCI Address 0x00000000 yes DMA Ch 0 Local Address 0x00000000 EA DMA Ch 0 Transfer Byte Count 0x00000000 pem DMA Ch 0 Descriptor Pointer 0 00000000 Ch 1 Mode 0x00000003 a 5 yes DMA Ch 1 PCI Address mm 0x98 DMA Ch 1 Local
61. and Invalidate Mode for DMA Transfers D14 DMA EOT End of Transfer Enable D15 DMA Stop Data Transfer Mode D16 DMA Clear Count Mode D17 DMA Channel I Interrupt Select D18 31 Reserved DMA CHANNEL 1 PCI DATA ADDRESS REGISTER PCI 0X98 00 31 PCI Data Address Register DMA CHANNEL 1 LOCAL DATA ADDRESS REGISTER PCI 0x9C D0 31 Local Data Address Register DMA CHANNEL 1 TRANSFER SIZE BYTES REGISTER PCI OX 0 00 22 DMA Transfer Size Bytes D23 31 Reserved DMA CHANNEL 1 DESCRIPTOR POINTER REGISTER PCI 0X A4 DO Descriptor Location D1 End of Chain D2 Interrupt after Terminal Count D3 Direction of transfer D4 31 Next Descriptor Address DMA COMMAND STATUS REGISTER PCI 8 DO Channel 0 Enable D1 Channel 0 Control 18 2 6 12 2 6 13 27 2 7 1 2 722 2 7 3 2 7 4 D2 Channel 0 Abort D3 Clear Interrupt D4 Channel 0 Done 05 7 Reserved DMA CHANNEL I COMMAND STATUS REGISTER 0 PCI 0 8 0 Channel 1 Enable D1 Channel 1 Start D2 Channel 1 Abort D3 Clear Interrupt D4 Channel 1 Done 05 7 Reserved DMA ARBITRATION REGISTER SAME AS MODE ARBITRATION REGISTER AT ADDRESS PCI D0 3 Channel 0 PCI to Local Almost Full COPLAF D4 7 Channel 0 Local to PCI Almost Empty COLPAE D8 11 DMA Channel 0 Local to PCI Almost Full COLPAF D12 15 DMA Channel 0 PCI to Local Almost Empty COPLAE D16 19 DMA Channel 1 PCI to Local Almost Full CIPLAF D20 23 DMA Channel 1 Local t
62. ce encoded as follows 000 001 010 011 100 101 110 111 05 3 RW Transmit Clock Source encoded as follows 000 001 010 011 100 101 110 111 Disabled RxC Pin TxC Pin DPLL Output BRG0 Output Output CTRO Output Output Disabled RxC Pin TxC Pin DPLL Output BRGO Output BRGI Output CTRO Output Output D7 6 RW DPLL Clock Source encoded as follows 00 01 10 11 High LOC 0xn22 BRG0 Output Output RxC Pin TxC Pin 01 0 BRGO Clock Source encoded as follows 00 01 10 11 CTR0 Output Output RxC Pin TxC Pin 03 2 Clock Source encoded as follows 00 CTRO Output 01 Output 10 RxC Pin 11 TxC Pin 05 4 Clock Source encoded follows 00 BRG0 Output 01 BRGI Output 10 RxC Pin 11 TxC Pin D7 6 Clock Source encoded as follows 00 Disabled 01 Disabled 10 RxC Pin 11 TxC Pin 3 3 10 HARDWARE CONFIGURATION REGISTER HCR 3 3 10 1 Low LOC 0xn24 D1 RW BRGO Enable DO RW BRGO Single Cycle Continuous D3 2 Rx ACK Pin Control encoded as follows 00 3 State Output 01 Rx Acknowledge Input 10 Output 0 11 Output 1 DS RW BRGI Enable D4 RW Single Cycle Continuous D7 6 Tx ACK Pin Control encoded as follows 00 3 State Output 01 Tx Acknowledge Input 10 Output 0 11 Output 1 3 3 10 2 High LOC 0xn26 D1 D0 DPLL Mode encoded as follows 00 Disabled 01 NRZ NRZI 1
63. d toward the Rx FIFO CHANNEL 2 CONTROL STATUS LOC 0x2C DO D1 D2 D6 3 D7 D8 Reset Channel 2 Tx FIFO Pulsed Writing a 1 to this bit will cause the channel 2 Tx FIFOs to be reset If the channel 2 Tx Almost register is not a value of 0x00000000 then this will also cause the channel 2 Tx FIFOs almost flags to be programmed After setting this bit to a 1 it is the software s responsibility to delay approximately 10ms before accessing the local side of the board again This bit is a self timed pulse therefore it is not necessary for software to return to clear this bit it will clear itself Reset Channel 2 Rx FIFO Pulsed Writing a 1 to this bit will cause the channel 2 Rx FIFOs to be reset If the channel 2 Rx Almost register is not a value of 0x00000000 then this will also cause the channel 2 Rx FIFOs almost flags to be programmed After setting this bit to a 1 it is the software s responsibility to delay approximately 10ms before accessing the local side of the board again This bit is a self timed pulse therefore it is not necessary for software to return to clear this bit it will clear itself Enable the Channel 2 Transmitters for the cable will drive the cable Writing a 2 to this bit will turn on the transmitters for Channel 1 to the cable Reserved Reset Zilog for Channel 1 2 Pulsed Writing a 1 to this bit will cause the channel 1 2 Zilog Z16C30 USC to be reset This bit
64. disables the Bterm input If this bitis set to 0 PCI 9080 bursts four Lword maximum at a time D8 Local Burst Enable A 1 value enables Local bursting input A value of 0 disables Local bursting If burst is disabled the local bus performs continuous single cycles for burst PCI read write cycles D9 Chaining A 1 value indicates chaining mode enabled For chaining mode the DMA source address destination address and byte count are loaded from memory in PCI or Local address spaces A 0 value indicates non chaining mode D10 Done Interrupt Enable A value enables interrupt when done A 0 value disables the interrupt when done If DMA Clear Count Mode is enabled the interrupt won t occur until the byte count is cleared D11 Local Addressing Mode A 1 value indicates local addresses LA 31 2 to be held constant A 0 value indicates local addresses is incremented D12 Demand Mode A value of 1 causes the DMA controller to operate in demand mode In demand mode the DMA controller transfers data when its DREQ input is asserted It asserts DACK to indicate that the current local bus transfer is in response to the DREQ input The DMA controller transfers Lwords 32bits of data This may result in multiple transfers for an 8 or 16 bit bus D13 31 Reserved DMA CHANNEL 1 PCI DATA ADDRESS REGISTER PCI 0x98 D0 31 PCI Data Address Register This indicates where in the PCI memory space the DMA transfers reads or writes will start from DMA CHANN
65. e it is not necessary for software to return to clear this bit it will clear itself Reset Channel 1 Rx FIFO Pulsed Writing a 1 to this bit will cause the channel 1 Rx FIFOs to be reset If the channel 1 Rx Almost register is not a value of 0x00000000 then this will also cause the channel 1 Rx FIFOs almost flags to be programmed After setting this bit to a 1 it is software s responsibility to delay approximately 10ms before accessing the local side of the board again This bit is a self timed pulse therefore it is not necessary for software to return to clear this bit it will clear itself Enable the Channel 1 Transmitters for the cable will drive the cable Writing a 1 to this bit will turn on the transmitters for Channel 1 to the cable Reserved Reset Zilog for Channel 1 2 Pulsed Writing a 1 to this bit will cause the channel 1 2 Zilog Z16C30 USC to be reset This bit is a self timed pulse therefore it is not necessary for software to return to clear this bit it will clear itself Note that after power up and after any reset to this component the next access to channel 1 or channel 2 USC must be a write of 0x00 to offset 0x00 of channel 1 USC Channel 1 Tx FIFO Empty TRUE 0 Channel 1 Tx FIFO Almost Empty TRUE 0 Channel 1 Tx FIFO Almost Full TRUE 0 Channel 1 Tx FIFO Full TRUE 0 Channel 1 Rx FIFO Empty TRUE 0 Channel 1 Rx FIFO Almost Empty TRUE 0 Channel 1 Rx FIFO Alm
66. e of information contained herein General Standards Corporation reserves the right to make any changes without notice to this product to improve reliability performance function or design All rights reserved No parts of this document may be copied or reproduced in any form or by any means without prior written consent of General Standards Corporation This user s manual provides information on the register level programming of the PMC SIO4 RS232 board Information required for customized software development This manual assumes that the user is familiar with the PCI bus interface specification In an effort to avoid redundancy this manual relies on data books other manuals and specifications as indicated in the related publication section RELATED PUBLICATIONS EIA Standard for the RS 422A Interface EIA order number EIA RS 422A Draft Standard Physical and Environmental Layers for PCI Mezzanine Cards PMC Sponsored by the Bus Architecture Standards Committee of the IEEE Computer Society P1386 1 Draft 2 0 April 4 1995 Sponsor Ballot Draft For questions or comments regarding this draft please contact either the chair or draft editor of this proposed standard Wayne Fisher PMC Chair 2001 Logic Drive San Jose CA 95124 3456 USA Ph 408 369 6250 Fax 408 371 3382 Em wfisher fci com Dave Moore PMC Draft Editor Digital Equipment Corporation 146 Main Street MLO11 4 U32 Maynard MA 01754 2571 USA Ph 408 493 2
67. eaning 00 locate anywhere in 32 bit PCI address space 01 locate below 1 Meg in PCI address space 10 locate anywhere in 64 bit PCI address space 11 Reserved If mapped into I O space bit 1 must be 0 bit 2 is included with bits 3 through 31 to indicate decoding range D3 If mapped into memory space a indicates that reads are pre fetchable If mapped into I O space bit 3 is included with bits 2 through 31 to indicate decoding range D4 31 Specifies which PCI address bits will be used to decode a PCI access to local bus space 0 LOCAL ADDRESS SPACE 0 LOCAL BASE ADDRESS RE MAP REGISTER FOR PCI TO LOCAL BUS PCI 0x04 DO Space 0 Enable D1 Reserved 02 3 If local space is mapped into memory space bits are not used If mapped into I O space bits 2 3 are included with bits 4 through 31 for re mapping D4 31 Re map of PCI Address to Local Address Space 0 into a Local Address Space MODE ARBITRATION REGISTER PCI 0 08 D0 7 Local bus Latency Timer D8 15 Local bus Pause Timer D16 D17 D18 D19 D21 D22 D23 D24 D25 D26 D27 D28 D29 Local bus Latency Timer Enable Local bus Pause Timer Enable Local bus BREQ Enable 20 DMA Channel Priority Local bus direct slave give up bus mode Direct slave LLOCKo Enable PCI Request Mode PCI Rev 2 1 Mode PCI Read No Write Mode PCI Read with Write Flush Mode Gate the Local Bus Latency Timer with BREQ PCI Read No Flush Mode Reads Device or Vendor ID D30 31 Reserved 2 4 4
68. ed into I O space bit 1 must be a 0 Bit 2 is included with bits 3 through 31 to indicate decoding range D3 If mapped into memory space a value of 1 indicates that reads are pre fetchable bit has no effect on the PCI9080 but it is used for system status If mapped into I O space bit is included with bits 31 2 to indicate decoding range If mapped into I O space bit is included with bits 2 through 31 to indicate decoding range D4 31 Specifies which PCI address bits to use for decoding a PCI access to local bus space 0 Each bit corresponds to a PCI address bit Bit 31 corresponds to Address bit 31 Write a value of 1 to all others used in conjunction with PCI Configuration register 0x18 Default is 1 Meg 2 9 2 2 9 3 LOCAL ADDRESS SPACE 0 LOCAL BASE ADDRESS RE MAP REGISTER FOR PCI TO LOCAL BUS PCI 0x04 D0 D1 D2 3 D4 31 Space 0 Enable A 1 value enables decoding of PCI addresses for Direct Slave access to local space 0 A value of 0 disables Decode If this bit is set to 0 the PCI BIOS may not allocate assign the base address for Space 0 Note Must be set to 1 for any Direct Slave access to Space 0 Reserved If local space 0 is mapped into memory space bits are not used If mapped into space bit is included with bits 4 through 31 for re mapping Re map of PCI Address to Local Address Space 0 into a Local Address Space The bits in this register re map replace the PCI Address bits used in decode as the Local
69. en this will also cause the channel 4 Tx FIFOs almost flags to be programmed After setting this bit to a 1 it is software s responsibility to delay approximately 10ms before accessing the local side of the board again This bit is a self timed pulse therefore it is not necessary for software to return to clear this bit it will clear itself Reset Channel 4 Rx FIFO Pulsed Writing a 1 to this bit will cause the channel 4 Rx FIFOs to be reset If the channel 4 Rx Almost register is not a value of 0x00000000 then this will also cause the channel 4 Rx FIFOs almost flags to be programmed After setting this bit to a 1 it is software s responsibility to delay approximately 10ms before accessing the local side of the board again This bit is a self timed pulse therefore it is not necessary for software to return to clear this bit it will clear itself Enable the Channel 4 Transmitters for the cable will drive the cable Writing a 4 to this bit will turn on the transmitters for Channel 1 to the cable Reserved Reset Zilog for Channel 3 4 Pulsed Writing a 1 to this bit will cause the channel 3 4 Zilog Z16C30 USC to be reset This bit is a self timed pulse therefore it is not necessary for software to return to clear this bit it will clear itself Note that after power up and after any reset to this component the next access to channel 3 or channel 4 USC must be a write of 0x00 to offset 0x00 of channe
70. enenenervrenenererenenererenenererenenererenenererenenererenenererenenererenenerssenenerssenene 2 74 Outbound Queue Port Register PCI 0x44 n 2 75 Messaging Queue Configuration Register 2 7 6 Queue Base Address Register PCI 0xC4 na 277 Inbound Free Head Pointer Register PCI 0xC8 2 7 8 Inbound Free Head Tail Register PCI OxCC 2 79 Inbound Post Head Pointer Register PCI 0xD0 2 7 10 Inbound Post Tail Pointer Register 2 7 11 Outbound Free Head Pointer Register PCI 0xD8 u 2 7 12 Outbound Free Tail Pointer Register PCI 0xDO tenete tenente tnter nnne es 2 7 13 Outbound Post Head Pointer Register PCI 0xE0 u 20 2 7 14 Outbound Post Tail Pointer Register PCI 0xE4 n 21 27 15 Queue Status Control Register PCI OxE amp 8 21 2 8 PCI CONFIGURATION REGISTER BIT DESCRIPTIONS 21 2 8 1 PCI Configuration ID Register Offset 0x00 2 8 2 PCI Command Register Offset 0x04 2 83 PCI Status Register Offset 0x06 2 8 4 PCI Revision ID Register Offset 0x08 I 2 8 5 PCI Class Code Register Offset 0x09 0B u a 2 8 6 PCI Cache Line Size Register
71. ent D1 10 Reserved D11 31 Expansion ROM Base Address upper 2 lbits PCI INTERRUPT LINE REGISTER OFFSET 0X3C D0 7 Interrupt Line Routing Value Indicates which input of the system interrupt controller s to which the interrupt line of the device is connected 2 8 21 2 8 22 2 8 23 2 9 2 9 1 PCI INTERRUPT PIN REGISTER OFFSET 0X3D D0 7 Interrupt Pin register Indicates which interrupt pin the device uses The following values are decoded OzNo Interrupt Pin I INTA 2 INTB 3 INTC 4 INTD Note PCI 9080 supports only one PCI interrupt pin INTA PCI MIN_GNT REGISTER OFFSET 0X3E DO 7 Min Gnt Used to specify how long a burst period the device needs assuming a clock rate of 33 MHz Value is multiple of 1 4 usec increments PCI MAX LAT REGISTER OFFSET D0 7 Max Lat Specifies how often the device must gain access to the PCI bus Value is multiple of 1 4 usec increments LOCAL CONFIGURATION REGISTERS BIT DESCRIPTIONS LOCAL ADDRESS SPACE 0 RANGE REGISTER FOR PCI TO LOCAL BUS PCI 0x00 DO Memory space indicator A value of 0 indicates Local address space 0 maps into PCI memory space A value of I indicates address space 0 maps into PCI I O space 01 2 If mapped into memory space encoded as follows D1 being the LSB Meaning 00 locate any where in 32 bit PCI address space O1 locate below 1 Meg in PCI address space 10 locate anywhere in 64 bit PCI address space 11 If mapp
72. er definable features This bit can only be written from the local side It is read only from the PCI side Fast Back to Back Capable When this bit is set to a 1 it indicates the adapter can accept fast back to back transactions A 0 indicates the adapter cannot Master Data Parity Error Detected This bit is set to a I when three conditions are met 1 the PCI9080 asserted PERR itself or observed PERR asserted 2 the PCI9080 was the bus master for the operation in which the error occurred 3 the Parity Error Response bit in the Command Register is set Writing a 1 to this bit clears the bit to a 0 DEVSEL Timing Indicates timing for DEVSEL assertion A value of 01 indicates a medium decode Note Hardcode to 01 Target Abort When this bit is set to a 1 this bit indicates the PCI9080 has signaled a target abort Writing a 1 to this bit clears the bit 0 Received Target Abort When set to a 1 this bit indicates the PCI9080 has signaled a target abort Writing a 1 to this bit clears the bit 0 Master Abort When set to a 1 this bit indicates the PCI9080 has generated a master abort signal Writing a 1 to this bit clears the bit 0 Signal System Error When set to a 1 this bit indicates the PCI9080 has reported a system error on the SERR signal Writing a 1 to this bit clears the bit 0 Detected Parity Error When set to a 1 this bit indicates the PCI9080 has detected a PCI bus parity error even if parity error handling is disabled
73. etting this bit to a 1 it is the software s responsibility to delay approximately 10ms before accessing the local side of the board again This bit is a self timed pulse therefore it is not necessary for software to return to clear this bit it will clear itself D2 Enable the Channel 3 Transmitters for the cable will drive the cable Writing a 3 to this bit will turn on the transmitters for Channel 1 to the cable D6 3 Reserved D7 Reset Zilog for Channel 3 4 Pulsed Writing a 1 to this bit will cause the channel 3 4 Zilog Z16C30 USC to be reset This bit is a self timed pulse therefore it is not necessary for software to return to clear this bit it will clear itself Note that after power up and after any reset to this component the next access to channel 3 or channel 4 USC must be a write of 0x00 to offset 0x00 of channel 3 USC D8 Channel 3 Tx FIFO Empty TRUE 0 D9 Channel 3 Tx FIFO Almost Empty TRUE 0 D10 Channel 3 Tx FIFO Almost Full TRUE 0 D11 Channel 3 Tx FIFO Full TRUE 0 D12 Channel 3 Rx FIFO Empty TRUE 0 D13 Channel 3 Rx FIFO Almost Empty TRUE 0 D14 Channel 3 Rx FIFO Almost Full TRUE 0 D15 Channel 3 Rx FIFO Full TRUE 0 The FIFO status flags are active low indicators of the current FIFO status These flags are continuously being updated every 33ns A value of 0 indicates that the current status is true and a value of 1 indicates that it is not true There are
74. gister This indicates where in the local memory space the transfers reads or writes will start from DMA CHANNEL 0 TRANSFER SIZE BYTES REGISTER PCI 0 8 00 22 DMA Transfer Size Bytes Indicates number of bytes to be transferred during DMA operation D23 31 Reserved DMA CHANNEL 0 DESCRIPTOR POINTER REGISTER PCI 0x90 DO Descriptor Location Value of I indicates PCI address space Value of 0 indicates Local Address Space D1 End of Chain A 1 value indicates end of chain A 0 value indicates not end of chain descriptor Same as Nonchaining Mode D2 Interrupt after Terminal Count A value causes an interrupt to be generated after the terminal count for this descriptor is reached A 0 value disables interrupts from being generated 2 11 6 2 11 7 2 11 8 D3 Direction of transfer A 1 value indicates transfers from local bus to PCI bus A 0 value indicates transfers from PCI to local bus D4 31 Next Descriptor Address Quad word aligned Bit 3 0 0000 DMA CHANNEL 1 MODE REGISTER PCI 0x94 D0 1 Local Bus Width A value of 00 indicates a bus width of 8 bits A value of 01 indicates bus width of 16 bits A value of 10 or 11 indicates a DMA bus width of 32 bits The bus width is forced to 16 bits for the Sx mode D2 5 Internal Wait States data to data D6 Ready Input Enable A 1 value enables Ready input A value of 0 disables the Ready input D7 Bterm Input Enable A 1 value enables Bterm input A value of 0
75. hronous 0001 Reserved 0010 Isochronous 0011 Asynchronous with CV 0100 Monosync 3 2 3 1 3 2 3 2 3 24 0101 Bisync 0110 HDLC 0111 Transparent Bisync 1000 NBIP 1001 8023 1010 Reserved 1011 Reserved 1100 Slaved Monosync 1101 Reserved 1110 HDLC Loop 1111 Reserved D7 4 Tx Submode 3 0 CHANNEL COMMAND STATUS REGISTER CCSR Low LOC 0xn08 DO RO RxACK D1 RO TxACK D4 2 HDLC Tx Last Character Length encoded as follows 000 8 bits 001 I bit 010 2 bits 011 3 bits 100 4 bits 101 5 bits 110 6 bits 111 7 bits D5 Reserved D6 RO Loop Sending D7 RO On Loop High LOC 0xn0A D1 0 DPLL Adjust Sync Edge encoded as follows 00 Both Edges 01 Rising Edge Only 10 Falling Edge Only 11 Adjust Sync Inhibit D2 RW Clocks Missed Latched Unlatch D3 RW Clocks Missed Latched Unlatch D4 RW DPLL in Sync Quick Sync D5 WO RCC FIFO Clear D6 RO RCC FIFO Valid D7 RO RCC FIFO Overflow CHANNEL CONTROL REGISTER CCR 3 2 4 1 3 242 3 2 5 1 32 52 3 3 6 1 3 3 6 2 3 3 7 Low LOC 0xn0C D4 0 Reserved DS Wait for Rx DMA Trigger D7 6 Rx Status Block Transfer encoded as follows D6 being the LSB 00 No Status Block 01 One word Status Block 10 Two word Status Block 11 Reserved High LOC Oxn0E D1 0 Tx Preamble Pattern encoded as follows 00 All Zeros 01 All Ones 10 Alternating 1 amp 0 11 Alternating 0 amp 1 D3 2 Tx Preamble Length encoded as follows 00 8 bits 01 16
76. ified in the prefetch count When set to 0 PCI 9080 ignores the count and continues prefetching until terminated by the PCI bus D11 14 Prefetch Counter Number of Lwords to prefetch during memory read cycles 0 15 D15 31 Reserved SHARED RUNTIME REGISTERS BIT DESCRIPTIONS MAILBOX REGISTER 0 PCI 0x40 Note Accessible at these addresses while queue control registers bit 0 0 also accessible at 0x78 and 0x 7C at all times D0 31 32 mailbox register 2 10 2 MAILBOX REGISTER 1 PCI 0x44 Note Accessible at these addresses while queue control registers bit 0 0 also accessible at 0x78 and 0x7C at all times 00 31 32 mailbox register 2 10 3 MAILBOX REGISTER 2 PCI 0 48 00 31 32 mailbox register 2 10 4 MAILBOX REGISTER 3 PCI 0 4 00 31 32 mailbox register 2 10 5 MAILBOX REGISTER 4 PCI 0 50 00 31 32 bit mailbox register 2 10 6 MAILBOX REGISTER 5 PCI 0x54 00 31 32bit mailbox register 2 10 7 MAILBOX REGISTER 6 PCI 0 58 D0 31 32 mailbox register 2 10 8 MAILBOX REGISTER 7 PCI 5 D0 31 32 mailbox register 2 10 9 PCI TO LOCAL DOORBELL REGISTER DESCRIPTION PCI 0x60 D0 31 Doorbell register A PCI master can write to this register and it will generate a local interrupt to the local processor The local processor can then read this register to determine which doorbell bit was asserted The PCI master sets a doorbell by writing a 1 to a particular bit The local processor can clear a doorbell
77. l 3 USC Channel 4 Tx FIFO Empty TRUE 0 Channel 4 Tx FIFO Almost Empty TRUE 0 Channel 4 Tx FIFO Almost Full TRUE 0 Channel 4 Tx FIFO Full TRUE 0 Channel 4 Rx FIFO Empty TRUE 0 Channel 4 Rx FIFO Almost Empty TRUE 0 Channel 4 Rx FIFO Almost Full TRUE 0 Channel 4 Rx FIFO Full TRUE 0 The FIFO status flags are active low indicators of the current FIFO status These flags are continuously being updated every 33ns A value of 0 indicates that the current status is true and a value of 1 indicates that it is not true There are only 5 valid combinations for each nibble D8 D11 or D12 D15 These combinations are as follows 1100 Almost Empty and Empty xD 1101 Almost Empty but not Empty OxF 1111 In between Almost Empty and Almost Full OxB 1011 Almost Full but not full 0x3 0011 Almost Full and Full If there are any other combinations observed this is a strong indication of a problem 3 1 18 CHANNEL 1 SYNC DETECTED LOC 0x50 3 1 19 3 1 20 3 1 21 3 1 22 Channel 1 Sync Detected Data The data in this register is used to watch the Rx data as it is being loaded into the main Rx FIFO If the data being loaded into the FIFO for this channel matches this data then an interrupt request will be generated to the interrupt logic An actual interrupt to the host will only occur if this interrupt source is enable in the interrupt control register CHANNEL 2 SYNC DETECTED 0
78. lizing the features of the Z16C30 various forms of error detection are built into the board the following are some of the methods of error detection available Parity error detection CRC error detection Rx overrun Tx underrun 1 8 INTERRUPTS Interrupts will be provided for the following conditions DMA Complete Sync word detected Tx FIFO Almost Empty Rx FIFO Almost Full Exited Hunt Idle Rcvd Break Abort Rx Bound Abort Parity Error Rx Overrun Plus many others User Manual for the PMC SIO4 RS232 Card Revision B General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 gt CHAPTER 2 PCICONFIGURATION REGISTERS 2 1 PCI CONFIGURATION REGISTERS Table 2 1 1 PCI Configuration Registers Description Local PCI Side Access Offset Value after register Addr Size R W Register Name Rese t address Bus 5 Eg Dep Runtime Registers sl Configuration Registers S 0x00000000 3 0 o o Subsystem ID Subsystem Vendor ID 0x908010B Ox2C 0x30 32 PCI Base Address to Local Expansion ROM 0x00000000 Dep Ox 32 yes 0 00000000 0 032 yes Local Max_lat Min_Gnt Interrupt Pin Interrupt Line 0x0000010A Bus D32 Bit PCI Base Address 2 for Local Address Space 0 p 2 3 Cardbus CIS Pointer Not Supported 0x908010B 0x28 2 2 REGISTERS Table 2 2 1 LOCAL CONFIGURATION REGISTERS Offset Access From Value
79. master the value is read from the Outbound Post List FIFO which is located in local memory at the address pointed to by the Queue Base address 2 FIFO Size Outbound Trail Pointer If FIFO is empty a value of FFFFFFFh is returned A PCI interrupt is generated if Outbound Post List FIFO is not empty 2 12 5 MESSAGING QUEUE CONFIGURATION REGISTER PCI 0xCO DO Queue Enable Value of 1 allows accesses to the Inbound and Outbound Queue ports If cleared to 0 writes are accepted but ignored and reads return FFFFFFFF All pointer initialization and frame allocation should be completed before enabling this bit D1 5 Circular FIFO Size Defines the size of one of the circular FIFOs Each of the four FIFOs are the same size Each FIFO entry is one 32 bit word FIFO Size Encoding Max entries FIFO Total FIFO 5 1 Size Memory 00001 4K entries 16 KB 64 00010 entries 32 128 00100 16K entries 64 KB 256 KB 01000 32K entries 128 KB 512 KB 10000 64K entries 256 KB 1 06 31 2 12 6 QUEUE BASE ADDRESS REGISTER PCI 0 4 2 12 7 2 12 6 2129 D0 19 D20 31 Reserved Queue Base Address Local Memory base address of the Inbound and Outbound Queues four contiguous and equal size FIFOs Queue base address must be aligned on a 1 MB boundary INBOUND FREE HEAD POINTER REGISTER PCI 0 8 D0 1 D2 19 D20 31 Reserved Inbound Free Head Pointer Local memory Offset for Inbou
80. n 4 Tx FIFO Almost Empty amp Hold until Chan 1 Rx FIFO Almost Empty 07 31 Reserved CHANNEL 1 TXALMOST LOC 0 10 00 31 Channel 1 Tx Almost Data The data in this register is used for programming the Almost Flags of the Tx FIFOs for this channel D0 16 is used for the Almost Empty Flag D17 31 is used for the Almost Full Flag CHANNEL 1 RX ALMOST LOC 0 14 00 31 Channel 1 Rx Almost Data The data in this register is used for programming the Almost Flags of the Rx FIFOs for this channel 3 14 D0 16 is used for the Almost Empty Flag D17 31 is used for the Almost Full Flag CHANNEL 1 FIFO 0 18 D7 0 08 31 Channel 1 FIFO Data The FIFOs are setup a way that the Rx FIFO and the Tx FIFO are located at the same address A write to this address will be directed toward the Tx FIFO and a read from this address will be directed toward the Rx FIFO Reserved CHANNEL 1 CONTROL STATUS LOC 1 DO D1 D2 D6 3 D7 D8 D9 D10 D11 D12 D13 D14 D15 Reset Channel 1 Tx FIFO Pulsed Writing a 1 to this bit will cause the channel 1 Tx FIFOs to be reset If the channel 1 Tx Almost register is not a value of 0x00000000 then this will also cause the channel 1 Tx FIFOs almost flags to be programmed After setting this bit to a 1 it is software s responsibility to delay approximately 10ms before accessing the local side of the board again This bit is a self timed pulse therefor
81. nd Free List FIFO This register is initialized as 0 FIFO Size and maintained by the local CPU software Queue Base Address INBOUND FREE HEAD TAIL REGISTER PCI OXCC D0 1 D2 19 D20 31 Reserved Inbound Free Tail Pointer Local Memory Offset for Inbound Free List FIFO This register is initialized as 0 FIFO Size by the local CPU software It is maintained by the MU hardware and is incremented modulo the FIFO size Queue Base Address INBOUND POST HEAD POINTER REGISTER PCI 0xD0 D0 1 D2 19 D20 31 Reserved Inbound Post Head Pointer Local Memory Offset for Inbound Post List FIFO This register is initialized as 1 FIFO Size by the local CPU software It is maintained by the MU hardware and is incremented modulo the FIFO size Queue Base Address 2 12 10 INBOUND POST TAIL POINTER REGISTER PCI OXD4 2 12 11 D0 1 D2 19 D20 31 Reserved Inbound Post Tail Pointer Local Memory Offset for Inbound Post List FIFO This register is initialized as 1 FIFO Size by the local CPU software Queue Base Address OUTBOUND FREE HEAD POINTER REGISTER PCI 0xD 8 D0 1 D2 19 D20 31 Reserved Outbound Free Head Pointer Local Memory Offset for Outbound Free List FIFO This register is initialized as 3 FIFO Size by the local CPU software It is maintained by the MU hardware and is incremented modulo the FIFO size Queue Base Address 2 12 12 OUTBOUND FREE TAIL POINTER REGISTER PCI OXDC D0 1
82. nnel 2 Interrupt for USC Request Status on Channel 3 Interrupt for Sync Detected Status on Channel 3 Interrupt for Tx FIFO Almost Empty Status on Channel 3 Interrupt for Rx FIFO Almost Full Status on Channel 3 Interrupt for USC Request Interrupt Status on Channel 4 Interrupt for Sync Detected Status on Channel 4 Interrupt for Tx FIFO Almost Empty Status on Channel 4 Interrupt for Rx FIFO Almost Full Status on Channel 4 Interrupt for USC Request Interrupt A 1 in any of these positions will indicate that the corresponding source has either performed a PMC interrupt or that the source for the interrupt is currently active thus could perform a PMC interrupt if enabled in the interrupt control register Whether or not the interrupt was performed depends on the interrupt control register If the corresponding bit in the interrupt control register is 0 then the source has not performed PMC interrupt and is only indicating the current status of that source If the corresponding bit in the interrupt control register is a 1 then the source has performed a PMC interrupt and has latched itself Writing a 1 to the respective bit in the interrupt status register clears the interrupt status bit A second interrupt will not occur until after that status bit has been cleared The interrupts are not queued hence each potential interrupt should be observed when identifying the source and clearing the status register Failure to do s
83. o PCI Almost Empty CILPAE D24 27 DMA Channel 1 PCI to Local Almost Full CILPAF D28 31 DMA Channel 1 PCI to Local Almost Empty CIPLAE MESSAGING QUEUE REGISTERS OUTBOUND POST LIST FIFO INTERRUPT STATUS REGISTER PCI 0x30 D0 2 Reserved D3 Outbound Post List FIFO Interrupt D4 31 Reserved OUTBOUND POST LIST FIFO INTERRUPT STATUS REGISTER PCI 0x34 D0 2 Reserved D3 Outbound Post List FIFO Interrupt Mask D4 31 Reserved INBOUND QUEUE PORT REGISTER PCI 0x40 D0 31 Value written by PCI master is stored into the Inbound Post List FIFO OUTBOUND QUEUE PORT REGISTER PCI 0x44 D0 31 Value written by PCI master is stored into the Outbound Free List FIFO 19 2 7 5 2 7 6 2 7 7 2 7 8 2 7 9 2 7 10 2 7 11 2 7 12 2 7 13 MESSAGING QUEUE CONFIGURATION REGISTER PCI 0xC0 20 Queue Enable D1 5 Circular FIFO Size D6 31 Reserved QUEUE BASE ADDRESS REGISTER PCI 0xC4 D0 19 Reserved D20 31 Queue Base Address INBOUND FREE HEAD POINTER REGISTER PCI OXC8 D0 1 Reserved D2 19 Inbound Free Head Pointer D20 31 Queue Base Address INBOUND FREE HEAD TAIL REGISTER PCI OXCC D0 1 Reserved D2 19 Inbound Free Tail Pointer D20 31 Queue Base Address INBOUND POST HEAD POINTER REGISTER PCI 0 D0 1 Reserved D2 19 Inbound Post Head Pointer D20 31 Queue Base Address INBOUND POST TAIL POINTER REGISTER PCI OXD4 D0 1 Reserved D2 19 Inbound Post Tail Pointer D20 31 Queue Base Addre
84. o could prevent any other interrupts from occurring CHANNEL 1 USC LOC 0x100 TO OX17E D7 0 Channel 1 USC Data Zilog Data Bus See Serial Controller Registers CHANNEL 2 USC LOC 0x200 TO 0 27 D7 0 Channel 2 USC Data Zilog Data Bus See Serial Controller Registers CHANNEL 3 USC LOC 0x300 0x37E D7 0 Channel 3 USC Data Zilog Data Bus See Serial Controller Registers CHANNEL 4 USC LOC 0x400 TO OX47E D7 0 Channel 4 USC Data Zilog Data Bus See Serial Controller Registers 3 2 32 11 3 2 12 SERIAL CONTROLLER REGISTERS Important Write to Loc 0x100 and Loc 0x300 after every reset to confirm the USC address system Contact your local Zilog Representative for Data books and User manuals in reference to the Z16C30 USC Universal Serial Controller for a more detailed description of the following registers It is the advice of the design engineer of this product that both books be obtained by any persons desiring to design using this product See Related Publications section of this document for address of Zilog Note In the following register addresses n stands for Channel Number CHANNEL COMMAND ADDRESS REGISTER CCAR same format for Channels 0 3 USC Control Registers Low LOC 0xn00 DO _ Upper Lower Byte Select 05 01 WO Address 4 0 D6 WO Byte Word Access D7 WO DMA Continue The contents of this register should always be set to 0x00 for this product High LOC 0xn02
85. ost Full TRUE 0 Channel 1 Rx FIFO Full TRUE 0 The FIFO status flags are active low indicators of the current FIFO status These flags are continuously being updated every 33ns A value of 0 indicates that the current status is true and a value of 1 indicates that it is not true There are only 5 valid combinations for each nibble D8 D11 or D12 D15 These combinations are as follows OxC 1100 Almost Empty and Empty xD 1101 Almost Empty but not Empty OxF 1111 In between Almost Empty and Almost Full 3 1 7 1011 Almost Full but not full 0x3 0011 Almost Full and Full If there are any other combinations observed this is a strong indication of a problem CHANNEL 2 Tx ALMOST LOC 0x20 D7 0 Channel 2 Tx Almost Data The data in this register is used for programming the Almost Flags of the Tx FIFOs for this channel D0 16 is used for the Almost Empty Flag D17 31 is used for the Almost Full Flag CHANNEL 2 RX ALMOST LOC 0x24 D7 0 Channel 2 Rx Almost Data The data in this register is used for programming the Almost Flags of the Tx FIFOs for this channel D0 16 is used for the Almost Empty Flag D17 31 is used for the Almost Full Flag CHANNEL 2 FIFO LOC 0x28 D7 0 Channel 2 FIFO Data The FIFOs are setup in a way that the Rx FIFO and the Tx FIFO are located at the same address A write to this address will be directed toward the Tx FIFO and a read from this address will be directe
86. s 1 in FIFO before Requesting Local Bus for Writes COPLAF 1 COPLAE 1 should be lt FIFO Depth of 16 Channel 0 Local to PCI Almost Empty COLPAE of Empty Entries minus 1 in FIFO before Requesting Local Bus for Reads COLPAF 1 COLPAE 1 should be lt FIFO Depth of 16 DMA Channel 0 Local to PCI Almost Full COLPAF of Full Entries minus 1 in FIFO before requesting PCI bus for Writes DMA Channel 0 PCI to Local Almost Empty COPLAE of Empty Entries minus 1 in FIFO before Requesting PCI Bus for Reads DMA Channel PCI to Local Almost Full COPLAF of Full Entries minus 1 in FIFO before Requesting Local Bus for Writes COPLAF 1 COPLAE 1 should be lt FIFO Depth of 16 DMA Channel 1 Local to PCI Almost Empty COLPAE of Empty Entries minus 1 in FIFO before Requesting Local Bus for Reads COLPAF 1 COLPAE 1 should be lt FIFO Depth of 16 DMA Channel 1 Local to PCI Almost Full COLPAF of Full Entries minus 1 in FIFO before requesting PCI bus for Writes DMA Channel 1 PCI to Local Almost Empty COPLAE of Empty Entries minus 1 in FIFO before Requesting PCI Bus for Reads 2 12 MESSAGING QUEUE REGISTERS 2 12 1 OUTBOUND POST LIST FIFO INTERRUPT STATUS REGISTER PCI 0X30 DO 2 D3 D4 31 Reserved Outbound Post List FIFO Interrupt This bit is set when the Outbound Post List FIFO is not empty This bit is not affected by the interrupt mask bit Reserved 2 12
87. s on the front panel 1 1 FUNCTIONAL DESCRIPTION As shown in the functional block diagram see Figure 1 1 1 this board includes the following PMC Bus Slave Interface RS 232 ECL Transceivers 2 Universal Serial Controllers USC The Zilog ZI6C30s Transmit FIFO Buffers Receive FIFO Buffers Q m mr gt Figure 1 1 1 Functional Block Diagram 1 2 BOARD CONTROL REGISTER The board control register will provide configuration for the PMC DMA request priorities 1 3 BOARD STATUS REGISTER The board status register will provide status of the board for future expansion 1 4 SYNC WORD SELECTION REGISTERS The sync word selection registers are used to provide an interrupt upon the reception of a particular character on a particular channel This character is software programmable 1 5 DATA RECEPTION Data is received into the Zilog Z16C30 after which the software may retrieve the data from the Z16C30 or have the data buffered into the main Rx FIFOs and retrieved by the software at a latter time depending on how the Z16C30 has been initialized 1 6 DATA TRANSMITION Data is placed into the Zilog Z16C30 or buffered into the main Tx FIFOs depending on how the Z16C30 has been initialized The Zilog can transmit and receive in any of several serial protocols Asynchronous External Sync Isochronous Asynchronous with Code Violations Monosynchronous Bisynchronous HDLC SDLC more 1 7 ERROR DETECTION By uti
88. se Address Remap Register PCI 0xF4 29 15 Local Address Space 1 Bus Region Descriptor Register PCI OxF8 sse 2 10 SHARED RUNTIME REGISTERS BIT DESCRIPTIONS nn 2 10 1 Mailbox Register 0 PCI Ox4Q irre RH rette Re t te e PH 2 10 2 Mailbox Register 1 PCLO ana a uqa a qu a wai tenen entren enini sasa 2 10 3 Mailbox Register 2 PCI 0 48 2 10 4 Mailbox Register 3 PCI 0 4 2 10 5 Mailbox Register 4 PCI 0 50 ee 2 10 6 Mailbox Resister 5 PCLOX94 3 a u tte ee OR RR u un a cob tel R eene 2 10 7 Mailbox Register 6 PCI 0X58 5 ne a n UO RR ha EN RR PRU D E 2 10 8 Mailbox Register 7 PCI Ox5G iine teret aa EE eee 2 109 PCI to Local Doorbell Register Description PCI 0x60 n 34 2 10 10 Local to PCI Doorbell Register Description PCI 0x64 34 2 10 11 Interrupt Control Status 0 68 esee tenente tenent tenen entren enint tenen entren 34 2 10 12 EEPROM Control PCI Command Codes User I O Control Init Control Register PCI 0x6C 36 2 10 13 PCI Permanent Configuration ID Register PCI 0x70 2 10 14 PCI Permanent Revision ID Register PCI 0x74 211 LOCAL DMA REGISTERS L aS nnne nennen 2 11 1 DMA Channel 0 Mode Register PCI 0x80 I 2
89. set to 1 don t prefetch past 4K 4098 bytes boundaries D13 T O Remap Select When set tol forces PCI address bits 31 16 to all zeros When set to 0 uses bits 31 16 of this register as PCI address bits 31 16 D14 15 Direct Master Write Delay 2 9 12 2 9 13 2 9 14 D16 31 This register is used to delay the PCI bus request after direct master burst write cycle has started Values 00 No delay start the cycle immediately 01 Delay 4 PCI clocks 10 Delay 8 PCI clocks 11 Delay 16 PCI clocks Re map of Local to PCI space into a PCI address space The bits in this register re map replace the Local address bits used in decode as the PCI address bits This PCI Remap address is used for Direct Master memory and I O accesses PCI CONFIGURATION ADDRESS REGISTER FOR DIRECT MASTER TO PCI IO CFG PCI 0 2 D0 1 D2 7 D8 10 D11 15 D16 23 D24 30 D31 Configuration Type 00 Type 0 O12 Type 1 Register Number If different register read write is needed this register value must be programmed and a new PCI configuration cycle must be generated Function Number Device Number Bus Number Reserved Configuration Enable A value of 1 allows Local to PCI I O accesses to be converted to a PCI configuration cycle The parameters in this table are used to generate the PCI configuration address LOCAL ADDRESS SPACE 1 RANGE REGISTER FOR PCI TO LOCAL Bus PCI OXFO D0 D3 D4 31 Memory Space Indicator A value
90. space accesses D2 Master Enable Controls a device s ability to act as a master on the PCI bus A value of 1 allows the device to behave as a bus master A value of 0 disables the device from generating bus master accesses This bit must be set for the PCI 9080 to perform Direct Master or DMA cycles D3 Special Cycle This bit is not supported D4 Memory Write Invalidate A value of 1 enables memory write invalidate A value of 0 disables memory write invalidate DS VGA Palette Snoop This bit is not supported D6 Parity Error Response A value of 0 indicates that a parity error is ignored and operation continues A value of 1 indicates that parity checking is enabled D7 Wait Cycle Control Controls whether the device does address data stepping 2 8 3 D8 D9 A 0 value indicates the device never does stepping A value of 1 indicates that the device always does stepping Note Hardcoded to 0 SERR Enable A value of 1 enables the SERR driver A value of 0 disables the driver Fast Back to Back Enable Indicates what type of fast back to back transfers a Master can perform on the bus A value of 1 indicates that fast back to back transfers can occur to any agent on the bus A value of 0 indicates fast back to back transfers can only occur to the same agent as the previous cycle D10 15 Reserved PCI STATUS REGISTER OFFSET 0X06 0 5 D7 D8 D9 10 D11 D12 D13 D14 D15 Reserved If high supports Us
91. ss OUTBOUND FREE HEAD POINTER REGISTER PCI OxD8 D0 1 Reserved D2 19 Outbound Free Head Pointer D20 31 Queue Base Address OUTBOUND FREE TAIL POINTER REGISTER PCI OXDC D0 1 Reserved D2 19 Outbound Free Tail Pointer D20 31 Queue Base Address OUTBOUND POST HEAD POINTER REGISTER PCI OXEO D0 1 Reserved 2 7 14 2 7 15 2 6 D2 19 Outbound Post Head Pointer D20 31 Queue Base Address OUTBOUND POST TAIL POINTER REGISTER PCI OXE4 D0 1 Reserved D2 19 Outbound Post Tail Pointer D20 31 Queue Base Address QUEUE STATUS CONTROL REGISTER PCI OXE8 DO 1 2 Decode Enable D1 Queue Local Space Select D2 Outbound Post List FIFO Prefetch Enable D3 Inbound Free List FIFO Prefetch Enable D4 Inbound Post List FIFO Interrupt Mask D5 Inbound Post List FIFO Interrupt D6 Outbound Free List FIFO Overflow Interrupt Mask D7 Outbound Free List FIFO Overflow Interrupt 08 31 Unused PCI CONFIGURATION REGISTER BIT DESCRIPTIONS All registers may be written to or read from in byte word or Lword accesses PCI CONFIGURATION ID REGISTER OFFSET 0 00 D0 15 Returns 0x10B5 D16 31 Returns 0x9080 PCI COMMAND REGISTER OFFSET 0X04 D0 Space A value of 1 allows the device to respond to I O space accesses A value of 0 disables the device from responding to I O space accesses DI Memory Space A value of 1 allows the device to respond to memory space accesses A value of 0 disables the device from responding to memory
92. tatus IUS RW I O Status IUS RW Transmit Data IUS RW Transmit Status IUS RW Receive Data IUS RW Receive Status IUS IUS Command encoded as follows 00 Null Command 01 Null Command 10 Reset IUS 11 Set IUS 3 3 15 gt MISCELLANEOUS INTERRUPT STATUS REGISTER MISR 3 3 15 1 Low LOC 0xn38 DO D1 D2 D3 D4 D5 D6 D7 RW RW RW RW RO RW RO RW BRG0 ZC Latched Unlatch ZC Latched Unlatch DPLL SYNC Latched Unlatch RCC Overflow Latched Unlatch CTS CTS Latched Unlatch DCD DCD Latched Unlatch 3 3 15 2 High LOC 0xn3A DO D1 D2 D3 D4 D5 D6 D7 RO RW RO RW RO RW RO RW TxREQ TxREQ Latched Unlatch RxREQ RxREQ Latched Unlatch TxC TxC Latched Unlatch RxC RxC Latched Unlatch 3 3 16 STATUS INTERRUPT CONTROL REGISTER SICR 3 3 16 1 Low LOC 0xn3C D0 D1 RW RW BRG0 ZC INTERRUPT ENABLE BRG1 ZC INTERRUPT ENABLE D2 RW D3 RW 05 4 RW D7 6 RW 3 3 16 2 High LOC 0xn3E D1 0 RW D3 2 RW D5 4 RW D7 6 RW DPLL SYNC INTERRUPT ENABLE RCC Overflow INTERRUPT ENABLE CTS Interrupts encoded as follows D4 being the LSB 00 Disabled 01 Rising Edge Only 10 Falling Edge Only 11 Both Edges DCD Interrupts encoded as follows D6 being the LSB 00 Disabled 01 Rising Edge Only 10 Falling Edge Only 11 Both Edges TxREQ Interrupts encoded as follows 00 Disabled 01 Rising Edge Only 10 Falling Edge Only 11 Both Edges RxREQ Interr
93. the Outbound Post List FIFO if not empty D3 Inbound Free List FIFO Prefetch Enable When this bit is set prefetching occurs from the Inbound Free List FIFO if not empty D4 Inbound Post List FIFO Interrupt Mask When this bit is set interrupt is masked D5 Inbound Post List FIFO Interrupt This bit is set when the Inbound Post List FIFO if not empty This bit is not affected by the Interrupt Mask bit D6 Outbound Free List FIFO Overflow Interrupt Mask When this bit is set interrupt is masked D7 Outbound Free List FIFO Overflow Interrupt This bit is set when the Outbound Free List FIFO becomes full A local SERR NMI interrupt is generated if enabled in the Interrupt Control Status Register Writing 1 clears the interrupt D8 31 Unused 44 CHAPTER 3 LOCAL SPACE REGISTERS 3 0 REGISTER MAP Table 3 0 1 5104 Register Address Address after Programming Firmware Revision 0x08 Reserved pf Channel 1 Control Status 0x100 D8 see Zilog see Zilog Channel 2 USC Reference Data Book 040 DS RO read only WO write only RW read write capability BD Bit Dependent 3 1 BIT MAP FOR LOCALSPACE REGISTERS When writing to the registers all reserved bits should be set to 0 for future compatibility Also the value read from a reserved bit will be indeterminate 3 1 0 FIRMWARE REVISION Loc 0x00 D31 0 0 00000000 Original Revision BOARD CONTROL Loc 0xX04 D2 0 Channel 0 P
94. tion with PCI interrupt enable Clearing the doorbell interrupt bits that caused the interrupt also clears the interrupt PCI Abort Interrupt Enable A value of 1 enables a master abort or master detect of a target abort to generate a PCI interrupt Used in conjunction with PCI interrupt enable Clearing the abort status bits also clears the PCI interrupt PCI Local Interrupt Enable A value of 1 enables a local interrupt input to generate a PCI interrupt Use in conjunction with PCI Interrupt enable Clearing the local bus cause of the interrupt also clears the interrupt Retry Abort Enable A value of 1 enables PCI 9080 to treat 256 Master consecutive retries to a Target as a target abort A value of 0 enables PCI 9080 to attempt Master Retries indefinitely Note for diagnostic purposes only Value of 1 indicates PCI doorbell interrupt is active Value of 1 indicates PCI abort interrupt is active Value of I indicates local interrupt is active LINTi Local Interrupt Output Enable A value of 1 enables local interrupt output Local Doorbell Interrupt Enable A value of 1 enables doorbell interrupts Used in conjunction with Local interrupt enable Clearing the local doorbell interrupt bits that caused the interrupt also clears the interrupt Local DMA Channel 0 Interrupt Enable A value of 1 enables DMA Channel 0 interrupts Used in conjunction with Local interrupt enable Clearing the DMA status bits also clears the interrupt Local DMA Channel
95. ue of 1 indicates PCI wrote data to the Mailbox 3 Enabled only if MBOXINTENB is enabled bit 3 high 2 10 12 EEPROM CONTROL PCI COMMAND CODES USER I O CONTROL INIT CONTROL REGISTER PCI 0 6 D0 3 D4 7 08 11 D12 15 D16 D17 D18 23 D24 D25 D26 D27 D28 D29 D30 PCI Read Command Code for DMA This PCI command is sent out during DMA read cycles PCI Write Command Code for DMA This PCI command is sent out during DMA write cycles PCI Memory Read Command Code for Direct Master This PCI command is sent out during Direct Master read cycles PCI Memory Write Command Code for Direct Master This PCI command is sent out during Direct Master write cycles General Purpose Output A value of 1 will cause the USERO output to go high A value of 0 will cause the output to go low General Purpose Input A value of 1 indicates that USERI input pin is high A value of 0 indicates that USERI pin is low Reserved Serial EEPROM clock for Local or PCI bus reads or writes to serial EEPROM Toggling this bit generates a serial EEPROM clock Refer to the manufacturer s data sheet for the particular EEPROM being used Serial EEPROM chip select For Local or PCI bus reads or writes to serial EEPROM Setting this bit to a 1 provides the EEPROM chip select Write bit to serial EEPROM For writes this output bit is the input to the serial EEPROM It is clocked into the serial EEPROM by the serial EEPROM clock Read serial
96. ues prefetching until termintaed by the PCI bus D11 14 Prefetch Counter Number of Lwords to prefetch during memory read cycles 0 15 A count of zero selects a prefetch of 16 Lwords D15 Reserved D16 17 Expansion ROM Space Local Bus Width A value of 00 indicates a bus width of 8 bits A value of 01 indicates a bus width of 16 bits A value of 10 or 11 indicates a bus width of 32 bits D21 18 Expansion ROM Space Internal Wait States data to data 0 15 wait states D22 Expansion ROM Space Ready Input Enable A 1 value enables Ready input A value of 0 disables the Ready input D23 Expansion ROM Space BTERM Input Enable A I value enables BTERM input A value of 0 disables the BTERMH input If this bit is set to 1 PCI 9080 bursts four Lword maximum at a time D24 Memory Space 0 Burst Enable A 1 value enables bursting A value of 0 disables bursting If burst is disabled the local bus performs continuous single cycles for burst PCI read write cycles D25 Extra Long serial EEPROM A value of 1 loads the Subsystem ID and Local Address Space 1 registers A value of 0 indicates not to load them D26 Expansion ROM Space Burst Enable A 1 value enables bursting A value of 0 disables bursting If burst is disabled the local bus performs continuous single cycles for burst PCI read write cycles D27 Direct Slave PCI write mode A 0 indicates that the PCI9080 should disconnect when the Direct Slave write FIFO is full A 1 indicates that the PCI9080 sho
97. uld de assert TRDY when the write FIFO is full D28 31 PCI Target Retry Delay Clocks Contains the value multiplied by 8 of the of PCI bus clocks after receiving a PCI Local read or write access and not successfully completing a transfer Only pertains to Direct Slave writes when bit 27 is set to 1 LOCAL RANGE REGISTER FOR DIRECT MASTER TO PCI PCI OX1C 00 15 Reserved 64 KB increments D16 31 Specifies which local address bits to use for decoding a Local to PCI bus access Each of the bits corresponds to an address bit Bit 31 corresponds to Address bit 31 A value of 1 should be written to all bits that should be included in decode and a 0 to all others This range is used for Direct Master memory I O or configuration accesses 2 9 9 2 9 10 2 9 11 LocAL BUS BASEADDRESS REGISTER FOR DIRECT MASTER TO PCI MEMORY PCI 0 20 D0 15 Reserved D16 31 Assigns a value to the bits which will be used to decode a Local to PCI memory access LOCAL BASE ADDRESS FOR DIRECT MASTER TO PCI IO CFG REGISTER PCI 0x24 D0 15 Reserved D16 31 Assigns a value to the bits to be used for decoding a Local to PCI I O or configuration access This base address is used for Direct Master I O and configuration accesses PCI BASE ADDRESS RE MAP REGISTER FOR DIRECT MASTER TO PCI PCI 0x28 DO Direct Memory Access Enable A value of 1 enables decode of Direct Master Memory accesses A value of 0 disables decode of Direct Master Memory accesses DI Direct
98. ult in multiple transfers for an 8 or 16 bit bus D13 Write and Invalidate mode for DMA transfers When set to 1 PCI 9080 performs Write and Invalidate cycles to the PCI bus PCI 9080 supports Write and Invalidate sizes of 8 or 16 Lwords The size is specified in the PCI Cache Line Size Register If a size other than 8 or 16 is specified PCI 9080 performs write transfers rather than Write and Invalidate transfers Transfers must start and end at the Cache Line Boundaries 014 DMA EOT End Of Transfer Enable Value of 1 enables EOT input pin Value of 0 disables EOT input pin 015 Stop Data Transfer Mode Value of 0 sends a BLAST to terminate DMA transfer Value of 1 indicates an EOT asserted or DREQ negated during demand mode DMA terminates the DMA transfer D16 DMA Clear Count Mode When set to 1 the byte count in each chaining descriptor if it is in local memory is cleared when the corresponding DMA transfer is complete Note f chaining descriptor is in PCI memory the count is not cleared D17 DMA Channel 0 Interrupt Select Value of I routes the DMA Channel 0 interrupt to the PCI interrupt Value of 0 routes the DMA Channel 0 interrupt to the local bus interrupt D18 31 Reserved DMA CHANNEL PCI ADDRESS REGISTER PCI 0x84 00 31 PCI Address Register This indicates where in the PCI memory space the transfers reads or writes will start from DMA CHANNEL 0 LOCAL ADDRESS REGISTER PCI 0X88 00 31 Local Address Re
99. umber D16 23 Bus Number D24 30 Reserved D31 Configuration Enable LOCAL ADDRESS SPACE 1 RANGE REGISTER FOR PCI TO LOCAL Bus PCI OXFO DO Memory Space Indicator D1 2 Encoded for Memory Space D3 If mapped into memory space a value of 1 indicates reads are prefetchable If mapped into I O space bit is included with bits 31 2 to indicate decoding range 04 31 Specifies which PCI address bits to use for decoding a PCI access to local bus space 1 LOCALADDRESS SPACE 1 LOCAL BASE ADDRESS REMAP REGISTER PCI OXF4 DO Space 1 Enable D1 Reserved D2 3 Iflocal space 1 is mapped into memory space bits not used If mapped I O space bit is included with bits 31 4 for remapping 04 31 Remap of PCI Address to Local Address space 1 into a Local Address Space 14 2 4 15 2 5 1 2 5 3 2 5 5 2 5 6 2 5 7 LOCAL ADDRESS SPACE BUS REGION DESCRIPTOR REGISTER PCI OXF8 D0 1 Memory Space 1 Local Bus Width D2 5 Memory space 1 Internal Wait States D6 Memory space I Ready Input Enable D7 Memory space I Input Enable D8 Memory space 1 Burst Enable D9 Memory space 1 Prefetch Disable D10 Read Prefetch Count Enable D11 14 Prefetch Counter D15 31 Reserved RUNTIME REGISTERS MAILBOX REGISTER 0 PCI 0x40 D0 31 32 bit mailbox register MAILBOX REGISTER 1 PCI 0x44 00 31 32 mailbox register REGISTER 2 PCI 0 48 00 31 32 bit mailbox register MAILBOX REGISTER 3 PC
100. upts encoded as follows 00 Disabled 01 Rising Edge Only 10 Falling Edge Only 11 Both Edges TxC Interrupts encoded as follows D12 being the LSB 00 Disabled 01 Rising Edge Only 10 Falling Edge Only 11 Both Edges RxC Interrupts encoded as follows D14 being the LSB 00 Disabled 01 Rising Edge Only 10 Falling Edge Only 11 Both Edges 3 3 17 TX RX DATA REGISTER RDR TDR 3 3 17 1 Low LOC 0xn40 D7 0 RW 3 3 17 2 High LOC 0xn42 D7 0 RW Tx Rx D7 0 Tx Rx D7 0 3 3 18 RECEIVER MODE REGISTER RMR 64 3 3 18 1 Low LOC 0xn44 D1 0 D4 2 DS RW D7 6 3 3 18 2 High LOC 0xn46 DO RW D1 RW D2 RW D4 3 D7 5 Rx Enable encoded as follows 00 Disable Immediately 01 Disable After Reception 10 Enable Without Auto Enables 11 Enable With Auto Enables Rx Character Length encoded as follows 000 8 Bits 001 1 Bits 010 2 Bits 011 3 Bits 100 4 Bits 101 5 Bits 110 6 Bits 111 7 Bits Rx Parity Enable Rx Parity Sense encoded as follows 00 Even 01 Odd 10 Space 11 Mark Queue Abort Rx CRC Enable Rx CRC Preset Value Rx CRC Polynomial encoded as follows 00 CRC CCITT 01 CRC 16 10 CRC 32 11 Reserved Rx Data Decoding encoded as follows 000 NRZ 001 NRZB 010 NRZI Mark 011 NRZL Space 100 Biphase Mark 101 Biphase Space 110 Biphase Level 111 Diff Biphase Level 3 3 19 RECEIVECOMMAND STATUS REGISTER RCSR 3 3 19 1 Low LOC 0xn48 D0 RO
101. use of Big Endian data ordering for Direct Slave accesses to loal Address Space 1 A value of 0 specifies Little Endian ordering D6 DMA Channel Big Endian Mode 2 9 5 2 9 6 2 9 7 A value of 1 specifies use of Big Endian data ordering for Channel accesses to local Address Space A value of 0 specifies Little Endian ordering D7 DMA Channel 0 Big Endian Mode A value of 1 specifies use of Big Endian data ordering for DMA Channel 0 accesses to the local Address Space A value of 0 specifies Little Endian ordering D8 31 Reserved LOCAL EXPANSION ROM RANGE REGISTER FOR PCI TO LOCAL BUS PCI 0x10 D0 10 Reserved D11 31 Specifies which PCI address bits will be used for decoding a PCI to local bus expansion ROM Each of the bits corresponds to an Address bit Bit 31 corresponds to Address bit 31 Write a value of 1 to all bits to be included in decode and a 0 to all others Used in conjunction with PCI Configuration register 0x30 Default is 64 Kbytes LOCAL EXPANSION ROM LOCAL BASE ADDRESS RE MAP REGISTER FOR PCI TO LOCAL BUS AND BREQO CONTROL PCI 0x14 D0 3 Direct Slave BREQo Backoff Requests Out Delay Clocks Number of local bus clocks in which a Direct Slave HOLD request is pending and a Local Direct Master access is in progress and not being granted the bus HOLDA before asserting BREQo Once asserted BREQo remains asserted until the PCI900 receives HOLDA LSB 8 or 64 clocks D4 Local Bus BREQo Enable A 1
102. xC4 2 12 7 Inbound Free Head Pointer Register PCI OxC8 T s 2 12 8 Inbound Free Head Tail Register PCI 0xCO n 2 12 9 Inbound Post Head Pointer Register PCI 0xD0 ten tne ten nnne 2 12 10 Inbound Post Tail Pointer Register PCI OxDA esee eene ntnen entente tnter enn 2 12 11 Outbound Free Head Pointer Register PCI 0 08 2 12 12 Outbound Free Tail Pointer Register PCI OxDC 2 12 13 Outbound Post Head Pointer Register PCI OxEO 2 12 14 Outbound Post Tail Pointer Register PCI OxEA 2 12 15 Queue Status Control Register PCI OXE8 nennrrnenersrerervrsrenerersrenenersrererersrenerersrenerersrenerersrenerersrenererssensser CHAPTER 3 LOCAL SPACE REGISTERS enesesenenesesenenesenenenesenenenesenenenesenenenesenenenenenenenesensnenesensnenesenenenenenssenenensnenesensnenesens 45 3 0 REGISTER MAP I te MAT Ade en AAS I Ja Nb RE AG 3 1 BIT MAP FOR LOCAL SPACE REGISTERS 3 1 0 FIRMWARE REVISION loc 0x00 3 1 1 BOARD CONTROL loc 0x04 3 1 2 CHANNEL 1 Tx ALMOST LOC 0x10 3 1 3 CHANNEL 1 RX ALMOST LOC 0x14 nnaspan 3 1 4 CHANNEL 1 FIFO LOC x18
103. y Space 0 Burst Enable D25 Extra Long Load from serial Enable D26 Expansion ROM Space Burst Enable D27 Direct Slave PCI write mode D28 31 PCI Target Retry Delay Clocks LOCAL RANGE REGISTER FOR DIRECT MASTER TO PCI PCI 0 1 D0 15 Reserved D16 31 Specifies which local address bits will be used to decode a Local to PCI bus access 2 4 9 2 4 10 24 11 2 4 12 2 4 13 24 14 LOCAL BUS BASE ADDRESS REGISTER FOR DIRECT MASTER TO PCI MEMORY PCI 0X20 D0 15 Reserved D16 31 Assigns a value to the bits which will be used to decode a Local to PCI memory access LOCAL BASE ADDRESS FOR DIRECT MASTER TO PCI IO CFG REGISTER PCI 0x24 D0 15 Reserved D16 31 Assigns a value to the bits which will be used to decode a Local PCI I O or configuration access PCI BASE ADDRESS RE MAP REGISTER FOR DIRECT MASTER TO PCI MEMORY PCI 0x28 DO Direct Memory Access Enable D1 Direct Master I O Access Enable D2 LLOCK Input Enable D3 12 Direct Master Red Prefetch Size control D4 Direct Master PCI read mode D5 8 10 Programmable Almost Full flag 09 Write and Invalidate Mode D11 Direct Master Prefetch Limit D13 I O Remap Select D14 15 Direct Master Write Delay D16 31 Re map of Local to PCI space into a PCI address space PCI CONFIGURATION ADDRESS REGISTER FOR DIRECT MASTER TO PCI IO CFG PCI 0 2 D0 1 Configuration Type 00 0 01 I D2 7 Register Number D8 10 Function Number D11 15 Device N

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