User Manual - TTC Upgrade
Contents
1. di ag WT NECS Ln pt EE AN LO UM TE P ES N O O O Vdiff mV Pictures 2 4 1b Calibration Graphs 55 Document 24 of 29 2 4 2 THROUGH VME KNOWING THE SIGNALS AND PHOTODIODES USED The calibration can be done with monitor software like rfrxscope By Markus Joos or with readRXD monitor Tcl application that run over Markus Joos Vme Drivers If the user is close to the board and knows the type of receivers that are mounted and which signal type they are receiving Then apply these rules Photodiode Signal Vref Value OCP SRX 03 1Mhz to 100Mhz clocks No adjustment required OCP SRX 03 400Mhz or Pulses clocks Don t care Not supported OCP SRX 24 1Mhz to 500Mhz clocks No adjustment required OCP SRX 24 Pulses Don t care Not supported Truelight 0 5Mhz to 400Mhz clocks Required 0x00 Truelight Pulses Required 0x15 Truelight Any not optimal Required 0x0A Table 2 4 2 Manual Calibration Values 2 4 3 THROUGH VME UNKNOWING THE SIGNALS AND PHOTODIODES This will be the procedure algorithm to apply when the user doesn t know what types or receivers are installed in the board and which types of signals are received Like in the same procedure VME access software will be required in order to2. 55 Document No 10 of 29 REMOVE PSY LUPECL COAX DRIVER PECL TO LUFECL TRANSLATOR MC1BEFSSD i ES Es OHMS LINE gt 19 a z 3 peu si f ISO o HD 534 5 p Fal TUMPER le ud 5 Sel D a 3 afd P 3 5 a a Sy 8 1 da ls 855MA50014 q gt 8 iOELSS a TUMPER Output CAP FREQ_DIU AC DC coupling selector F IN Lem NE 4 3 Picture 2 2 2 Photodiodes Post Processing Logic 2 2 2 1 FREGUENCY DIVIDER The Freguency Divider is composed of 5 Flip Flops FF that divide the freguency by 16 2 2 2 2 OUTPUT FORMAT SELECTION In order to select the format of the output 500 AC coupled 800Vpp or DC coupled LVPECL you must place in the output of the system a capacitor of 100 nf AC or a 0O RESISTOR for DC coupling Insert picture capacitor output Picture 2 2 2 2 Location of the Output Capacitor ORO Resistor 55 Document 11 of 29 VMEBUS INTERFACE The VMEbus interface of the RF RX D cards is implemented in its FPGA and based on a VHDL Module developed by the AB RF group This Module has been developed especially for VME64 but adapted for using some functionality of VME64X like automatic addressing The firmware installed has been configured to w
3. d 202 202 R Voff mV DACvalue 4 7mV Where Vdiff is the differential voltage between the differential lines Voff is the DAC voltage value R is the Manual Thevenin modifier Supposing a R 0 we can obtain this graph where is possible to select graphically the value for the register the value is in Decimal do not forget to change to hexadecimal 55 Document 16 29 dic TEN JE EET JE Vdiff mV fp ri EE np fe irm eres ar En die an ei IEEE dd a dac VE qp b aar eae Tac e d ac oo Re d Mee RE P e dede aed AA cm Lii qE EE EN p di ee EE BEE C pe qb E TE ME ei dice JEL BEE IE ib dE EIE BESETE VIER ete Ie qj RIA Je a erar EE N HE EN TE dl Picture 2 3 3 3a Vdiff variation with Vref register Positive pulse Reference for BOTH LINES Negative pulse Noise when low level is keep more than 10us Picture 2 3 3 3b Positive pulse in balanced Thevenin network 55 Document 17 of 29 Positive New reference for Negative y pulse Line Con
4. coupled in the output In both cases the voltage must be selected between 3 3V and 5V with the Violet Resistors kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk In FPGA mode VME FPGA who unbalances the Thevenin network For this it is necessary write in the Vref Register a value different from 0 This makes it possible to unbalance the network from 0 to 750mv 2 2 1 3 SIGNAL DETECTION CIRCUIT The signal Detection circuit works ONLY with the OCP SRX photodiode This circuit will translate the signal detection state from the OCP to the Front panel LED on the FP indicates the presence of optical power in each channel through a GREEN light or the absence with a RED light In a future Firmware version signal detection for Truelight Photodiodes based on the frequency of the received signal will be added Meanwhile the Frequency detectors registers can be used to know the signal presence 2 2 2 PHOTODIODES MODULES POST PROCESSING LOGIC The post processing logic is based on a few ECL gates that will increase the signal power in order to drive the signal through long cables The user will be able to choose the output format between AC coupled 50 or DC coupled LVPCL Another function of the Post Processing circuit is to split the signal and apply a frequency divider with the objective to be able to monitor the frequency with the FPGA through the VME interface THE BOARD
5. 2 1 2 PHOTODIODE CONFIGURATION THRESHOLD AND SELECTION The table below shows a brief summary of the necessary adjusts that need to be done in each channel to select the photodiode that is going to be used 55 Document 8 of 29 Photodiode Mode Components to replace Manual HW FPGA SW NOT THRESHOLD OCP CONNECTED GREEN LIGHT DARK BLUE DB don t care LIGHT BLUE LB don t care PINK RESISTORS PR disconnected RED RESISTORS RR connected VIOLET RES VR just ORO in bottom 5V Truelight MANUAL THRESHOLD TRUELIGHT CONN GREEN DARK DARK BLUE DB 10ohms resistor LIGHT BLUE LB disconnected PINK RESISTORS PR connected RED RESISTORS RR disconnected VIOLET RES VR just ORO in bottom 5V Truelight THRESHOLD ADJUSTABLE DARK BLUE DB Oohms resistor Oy PRG LIGHT BLUE LB connected 1uH PINK RESISTORS PR connected RED RESISTORS RR disconnected VIOLET RES VR just ORO in bottom 5V Table 2 2 1 2 photodiode selection table Insert examples pictures 55 Document No 9 of 29 kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk In case that another photodiode is going to be used it has to be connected on OCP place if the Output format is pure PECL for all the bandwidth TRUELIGHT place if the Output is differential NO PECL with AGC in the last stage of the preamplifier or with and internal AC
6. 36 Freq This multiplication must be done in LONG UNSIGNED INT or FLOAT 55 Document 20 of 29 Examples Freduency ValueReg1 Value Reg2 Frequency Original MHz Measured MHz 10 0x0000 0 0 00 10 40 078 0 0000 0x02BF 40 0568 0x0000 0 02 40 113 0 0000 0 0047 396 619 0 0000 0 0046 402 285 1 2 0 0000 0x6e00 1MHz Pulse 11 245KHz 0x0026 0x361A 11 245027KHz No signal OxFFFF OxFFFF 6Hz Table 2 3 3 4 Typical examples of values of the frequency counter 2 3 3 5 BOARD IDENTIFICATION Offset Access BOARD ID 0x003A 16 bits This register contains the VME64x board ID of the RF RX and is set to the value 364 0x16C See http ess web cern ch ESS boardlDistribution PHP for details 55 Document 21 of 29 CALIBRATION PROCEDURES TRR OR SIMILAR PHOTODIODE The calibration procedure will apply only to the channels where TRUELIGHT or equivalent photodiode is installed The OCP photodiodes DO NOT REQUIRE ANY CALIBRATION Only be selected see section 2 2 1 1 The calibration procedure can be done manually or trough VME dividing this last option in two different scenarios Knowing the frequency and type of the signal received Unknowing the frequency and type of the signal received In order to read and modify the board s registers the program rfrxscope has been developed It helps the user accessing the board reg
7. NFORMATION Lasers and Photodiodes evaluation by Angel Monera EDA documents https edms cern ch nav eda 01382 RF RX D TCL console Manual RF TX D User Manual 55 Document 29 of 29 3 TTC COMMON SOFTWARE 3 3 INTRODUCTION 3 3 1 H W ENVIRONMENT 3 3 2 S W ENVIRONMENT 3 4 TEST PROGRAMS 3 5 THEUSER LIBRARY
8. T3 If ST3 is ON gt the FPGA will be reprogrammed when the VME crate reset will be activated triggered by a VMEbus SYSRESET 2 6 Connector name CH1 IN Optical Link Table 2 5 Jumpers and Switch descriptions FIBRE CABLE CONNECTIONS To be connected to RF Digital TX Format Optical Digital or Analog CH1 RF Out 50omhs LOAD LVPECL 50ohms AC DC coupled 2 IN Optical Link RF Digital TX Optical Digital or Analog CH2 RF Out 50ohms LOAD LVPECL 50 AC DC coupled CH3 IN Optical Link RF Digital TX Optical Digital or Analog CH3 RF Out 50ohms LOAD LVPECL 50ohms AC DC coupled J5 JTAG JTAG MODE FPGA J6 JTAG BIT BLASTER MODE EEPROM Table 2 6 Connectors and Descriptions 55 Document 28 of 29 2 7 FRONT PANEL LEDS LED VME COMM Description Indicates if the last VME cycle was successful or wrong ERROR LED CH1 LED SD CH1 Indicates Optical signal only OCP when is receiving gt 30dbm CH2 LED SD CH2 CH3 LED SD CH3 Indicates Optical signal only OCP when is receiving gt 30dbm Indicates Optical signal only OCP when is receiving gt 30dbm Table 2 7 Front Panel LEDS Possible modification in the definitive board for signal detection based in the Frequency detection valid for all photodiodes REFERENCES OR MORE I
9. USER MANUAL Function Optical to RF Class VME DIGITAL d Created 11 10 2006 PH ESS 02 01 Modified date RF RX D v1 0 Optical to RF Digital VMEbus Interface Card and S W Summary This document describes the functionality of the RF Rx Digital card as well as the generic S W that has been developed for it Prepared by Checked by Approved by Markus Joos PH ESS for information Tel Fax E Mails you can contact Markus Joos 41 22 7672364 41 22 7671025 markus joos cern ch Angel Monera 41 22 7678925 41 22 7678925 amoneram cern ch 55 Document 2 of 29 Table of Contents 1 Introduction 2 D Hardware 2 1 Power description 2 2 Optical Interface Photodiodes Modules LT 5 Photodiode selection Depending of the signal to transmit Photodiode configuration Threshold and Selection Signal Detection Circuit Photodiodes Modules Post processing Logic E 10 Output Format Selection 2 3 VMEbus interface 2 31 Addr module sellection 2 3 2 Software Vme addres map 2 3 3 Registers Description 2 3 3 1 EDA Identification 2 3 3 2 Signal Detection only for ocp srx 2 3 3 3 VRef Registers Only for TRR or equivalent photodiodes 2 3 3 4 Frequency Counters 2 3 3 5 Board Identification 2 4 Calibration procedures Trr or similar photodiode 2 4 1 Manual Calibration Fix Vr
10. Volts supply Only one connected VIOLET DOWN RES 5 Volts supply Only one connected PINK RESISTORS Truelight signal selected when ORO res Are placed RED RESISTORS back side OCP signal selected when ORO res Are placed BLUE RESISTORS Resistor unbalancing the Thevenin Network manually whenR ORO res BLUE INDUCTANCE FPGA Control Thevenin when placed 1uH Table 2 2 1 Block description 55 Document 7 29 2 2 1 1 PHOTODIODE SELECTION DEPENDING OF THE SIGNAL TO TRANSMIT To the table below summarizes review coming from the Laser and Photodiodes Evaluation that shows the bandwidth and signal types that each Photodiode can receive For more information and characteristics check the evaluation document or datasheets Photodiode Bandwidth Signal Supported Threshold Thevenin adjustable Example OCP SRX 03 Time of bit Tb lt 10us to 2ns 10 2 square Freq 100 KHz to 250 MHz OCP SRX 03 Tb gt 10us 10KHz square Freq gt 300Mhz 5ns width 11Khz pulse OCP SRX 24 Tb lt 10us to 1ns 10MHz square Freq 100 KHz to 500 MHz 400MHz square OCP SRX 24 Tb 10us 10KHz square 5ns width 11Khz pulse Truelight 2 to 400Mhz 10 2 square 400MHz square Truelight Tb high lt 16us Positive pulses maximum 16 5 width Table 2 2 1 1 Signals supported by each photodiode 2
11. d three LEDs have been installed to indicate the presence of 12V 12V and 3 3V generated from 5V indicating with this light both voltages If this LED is not lighting proceed checking the 5V fuse state OPTICAL INTERFACE The optical interface is composed of three equal channels based on two parallel circuits using two different photodiodes one being mounted at a time Both photodiodes have differential output and are connected to a group of ECL gates that will clean and prepare the signal to be amplified by a coaxial driver and processed with a FPGA COAX DRIVER SMA ONNECTOR MODULE PHOTODIODE PCL to LVPCL E S Lou FREQ SPLITTER SSS Picture 2 2 Optical Interface Diagram 55 Document No 5 of 29 2 2 1 PHOTODIODES MODULES TUMPER 9 TUMPER Power selector Hesistor Picture 2 2 1 a Photodiodes Module in EDA 1380 Truelight TRR Power supply selector PH ESS Document No 0000000000 a 44 t mem en 5 E ed J gt Mr Disconnect ME TRR selector OCP selector Inductance OCP selector Disconnect TRR selector Back side Picture 2 2 1 b points in the board EDA 1382 Block Light Green Signal OCP Place socket Vref Value Supported Not adjustable Dark Green Truelight Place socket Not supported VIOLET UP RES 3 3
12. d to identify the board This default value is 0x1382 which correspond to the EDA number assigned to the project 2 3 3 2 SIGNAL DETECTION ONLY FOR OCP SRX Offset Access SIG_DETEC 0x0004 3 bits 3 1 The register Signal Detect represents the signal detection in the OCP photodiodes if there are not OCP SRxX installed the value of this register can be false This register is connected to the front panel LEDs that indicate the signal presence with a green light and no signal with red light For other photodiodes use the frequency counters registers Examples Hex Value SD in Ch 1 SDinCh2 SDinCh3 0x00 X Signal Detected 0x02 Nothing No signal 0x04 g g 0x06 0x08 OxOA OXOC X OxOE X X Table 2 3 3 2 Signal detection combinations 55 Document 15 of 29 2 3 3 3 VREF REGISTERS ONLY FOR TRR OR EQUIVALENT PHOTODIODES These registers only work with the photodiodes plugged in the Truelight socket Name Offset Size Access Default Values 0x000A 8 bits R W OXOOOA 0 000 8 bits R W 0 000 0 000 8 bits R W OXOOOA 1 REF CH2 REF REF CHX REF are a group of register that control the previously mentioned Thevenin Network in the 3 channels The values of these registers will be sent to the DAC to modify the network The modification is linear and follows the equation Voff 202 R VcceR Vdiff V V 120
13. ef Values 2 4 2 Through VME Knowing the Signals and Photodiodes used 2 4 3 Through VME Unknowing the Signals and Photodiodes 2 5 Board configuration Jumpers and switch 2 6 Fibre cable connections 2 7 Front panel LEDs 2 8 References or more information 3 common software 3 3 Introduction 3 3 1 H W Environment 3 3 2 S W Environment 3 4 Test programs 3 5 The user library 55 Document 3 of 29 1 INTRODUCTION The RF RX D Optical to RF VMEbus card is an interface VME card developed as receiver of RF TX D VMEbus Interface card The two boards used together provide 3 digital optical channels with an 1bit analog to digital converter comparator and output LVPECL AC or DC coupled This document contains a hardware description of the board and all the accessible registers of the RF_RX_D card as well as a description of the generic S W that has been developed for this card At the end of this document some basic examples of configuration procedures are proposed 55 Document 4 of 29 2 RF RX D HARDWARE 2 1 POWER DESCRIPTION This board requires a VME crate with the standard VME64 power supply with 12 12 and 5 Volts available The nominal consumption for these power lines is the following Voltage Current A Fuse Current 5V 2A 3A 12V 150mA 0 5A 12V 16mA 0 1A Table 2 1 Power consumption In order to check the power supplied to the boar
14. isters in an interactive way rfrxscope has been written by Markus Joos 2 4 1 MANUAL CALIBRATION FIX VREF VALUES This configuration will be applied when VME controller is not present or block the references to avoid third part modifications or intromission The manual modification is done by modifying the Resistors R and disconnecting de soldering the inductance more information about full Truelight Set UP in section 2 2 1 55 Document 22 of 29 Inductance In order to calculate the R convenient the user must follow the equation Vcce R Vdiff V V 120 202 202 R a 202 e Vdiff Vcc e 0 594 Or the next Graphs 55 Document 23 of 29 tant values gt 1MHz centred in 0 dels Pulses EE All not optimal HHA EA 44 FIFI R in Ohms Freg TN Ma LT IE LEE NUS PST eds DNE Pe REG TOT T IBS ope p EE rid 21217171711 Mt TP ie idw m D EDD ini onc ni T 00860 i eks ei EE albei Ie Ee Fil
15. mode if the bit 0 or bit 1 1 Examples Rotary Switch 1 Rotary Switch 2 Module MODO ADDRESS SPACE OxF 0 Manual address Module address OxFO 0000 Board space 0 00000 to OxF3 FFFF Automatic address Module address Depends on the slot into which the card is plugged Manual address Module address 0 4 0000 Board space 0 40000 to OxF7 FFFF Table2 3 1 b Examples of Module Addr 55 Document 13 of 29 2 3 2 SOFTWARE VME ADDRES MAP Offset Size bytes Function Remarks 0x0000 EDA ID Read 0x1382 0x0004 SIG_DETEC Read bits 3 to 1 0x000A 2 CH1_REF Read Write 0x000C CH2_REF Read Write 0 000 REF Read Write 0 0010 CH1 FREO LOW Read Freq Ch1 15 0 0x0012 CH1 FREQ HIGH Read Freq Ch1 31 16 0x0014 CH2 FREQ LOW Read Freq Ch2 15 0 0x0016 CH2 FREQ HIGH Read Freq Ch2 31 16 0x0018 CH3 FREQ LOW Read Freq Ch3 15 0 0x001A CH3 FREQ HIGH Read Freq Ch3 31 16 0x003A BOARD ID CERN ID Read 0x016C Others Unused Table 2 3 2 VME Memory Map These Registers only modify or affect the TRR photodiode or any Photodiode placed in its sockets These Registers only affect the OCP photodiodes 55 Document 14 of 29 2 3 3 REGISTERS DESCRIPTION 2 3 3 1 EDA IDENTIFICATION Offset Access 0x0000 16 bits The EDA ID is just a register that can be use
16. ork in the addressing mode of A24 D16 and works as a memory decoder where all the memory space is available The access modes dictated by address modifier are only available for 0x39 and Ox3D where the there is no distinction between privilege user and normal user From this 24bits of memory address 6 bits are used for the module address A23 to A18 This address can be set up using the two rotary switches Picture 2 3 Module address selector In addition it is possible to fix automatically the module address by using the geographical address of VME64x In order to select the source of the module address rotary switches or GEO addr from the 8 bits of the R S the 2 lower bits are designated to select it 55 Document 12 of 29 2 3 1 ADDR MODULE SELLECTION Address space available Note represent any combination of 4 bits N represent XX any combination of 2 bits OxM N 0 0000 to OxM N 3 FFFF 2 256 Kbytes of memory Rotary Switch Rotary Module address MA 1 Switch 2 M Bits 3 2 Automatic GEO Address 5bits 0 Bits 1 0 1 to A23 A19 lt GEOGA 4 0 E A18 0 Bits 3 2 OxMN Manual Address Bits 1 0 0 A23 A20 lt M 19 18 lt Reguires VME64X crate Table 2 3 1 Address and ADDR Mode selection In others words the bottom rotary switch sw1 controls the addressing mode with the lower two bits which switches to automatic
17. read and modify the desired registers 55 Document No 25 of 29 Start as Write OxOA T vorks Picture 2 4 3 Remote Calibration Procedure This value is the minimum value to accept the pulse in good conditions and correspond to the worst scenario possible signal reception at 27dBm More values can be found in the next tables and graphs 55 Document 26 29 Power Received Value Hex for obtain a dBm 5 6ns width output Pulse widh of 5 6ns Value Dec TRR V reference value for Pulse transmision Vref Value por input output pulse 5 7V Tx Configuration Ch3 with Vref 0x70 560 5 6ns width pulse 15 10 5 dBm received TRR TRR V reference value for Pulse transmision Vref Value por input output pulse 5 7V Tx Configuration Ch3 with Vref 0x70 560mv 5 6ns width pulse 1 150 200 250 350 uW received in TRR 55 Document PH ESS THE 2 5 BOARD CONFIGURATION JUMPERS AND SWITCH Element Description LSB rotary switch See 2 3 1 section MSB rotary switch See 2 3 1 section Reset Front Panel button Generate a Soft reset of the FPGA when is pressed ST5 Always OFF ST4 Always ON TP25 Frequency selectorO for the JTAG TP26 Frequency selector1 for the JTAG S
18. tage some more for noise immunity Then the value to write in the register following the equations or the graph is Ox0A This value ensures the reception of all the signals with all the receivers but is not optimised Note any value different from O will generate duty cycle distortion in the high frequency signals The user must decide what he exactly needs and set up these values as convenient is for him Insert pictureeeeeeeeeeeeeeeeeeeeeeeeeee 55 Document 19 of 29 2 3 3 4 FREQUENCY COUNTERS CH1 Name Offset Size 0x0010 16 bits 0x0012 16 bits CH1 FREQ LOW CH1_FREQ_HIGH CH2 Offset Size Access cH2 FREQ Low 9x0014 16 bits 0x0016 16 bits R CH2_FREQ_HIGH CH3 Name Offset Size 0x0018 16 bits 0x001A 16 bits CH3 FREQ LOW FREO HIGH These registers are generated by internal counters that count the number of rising clocks between rising edges in the received signals In order to measure higher frequencies than the clock frequency a frequency divider has been installed on the board 4 hardware Flips Flops gt 1 16 and inside the FPGA software divider 1 22 Every counter has a size of 32 bits that is divided in two registers of 16bits that must be read separately due to the fact that the board has only A24 D16 access In order to calculate the frequency the equation is 8091622 Re gLow Re gHighe 655
19. trolled by Theoretical reference for BOTH LINES New reference for Positive Line Controlled by hardware Resistor Pulse width reduced New reference for Negative Line Controlled VME Theoretical reference for both LINES pulse V New reference for Positive Line Out No cross NY siaal Controlled by hardware Resistor u 7 Picture 2 3 3 3d Negative pulse in an Unbalanced Thevenin network Review When the network is balanced the user must avoid keeping a level for more than 10us When the network is UNBALANCED the network will force zero detection when there is no signal negative or zero signal When a positive level is received the output will change to positive following the received signal for a maximum of 10us will received Examples of Outputs with unbalanced network Input Output Low level 50 seconds Low level 50 seconds Low 505 high 5us low 50s Low 50s high 5us low 50s AGC actuation Low 50s high 50us low 50s Low 50s high 10us low 50s 40us 4 0 55 Document 18 of 29 Examples of VREF adjustment Supposing just FPGA modification R 0 the Vdiff can vary from 0 to 0 71Vots Voff 2V OxFF in the Vref Register The Comparator used ADCPM553 nees at least 10mv of differential voltage between its inputs If we don t want the comparator to oscillate we need to fix the Vdiff voltage in at least 20 30mV minimum vol
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