THDB-ADA User Manual 1 www.terasic.com October 19, 2015
Contents
1. ag TE LAR Ju A 5 sa LLL sa um tenti reve Mild re x ire reer ett wem zamma sina dada r NG AN eec www terasic com ter High Speed A D and D A Development Kit User Manual THDB ADA WA 4 y a 4 y i EP X yr y A dei pi Fa Fi ES y Y AW HE E PIG Poon of op D RO ED Copyright O 2003 2014 Terasic Technologies Inc All Rights Reserved ANTENA o CONTENTS Ca Chapter 1 ADOUL the KINANA AA 3 SA CR 3 AGENT 4 o GUN HEP o O PAPA APA AA 9 Chapter 2 Architecture of the ADA 10 Chapter 3 Using the ADA 11 AD ro miley CONN PAPA GAP HM E 000 ANA ik Rek 11 3 2 Analos to Digital CONV enter urraca AA 12 AA 13 75 0 Ce PP a yaa 18 Chapter 4 ADA Demons Oi 19 4 1 Arbitrary Waveform ale a ala an NU 19 4 2 A D and D A Converter Performance Evaluation maa 21 Chapter 5 ADDENOM a ta EAA 26 BLOOR IZ 26 5 2 Always Visit Terasic Webpage for New Applicatlons 26 THDB ADA User Manual 2 www terasic com Tijasic October 19 2015 www terasic com Chapter 1 About the Kit The THDB ADA ADA daughter board is designed to provide DSP solution on DE series and Cyclone III Starter Kit or other2. 0 0 5 1 1 5 2 2 5 3 3 5 4 4 5 Frequency Hz x Figure 4 6 Normalized Spectral Plot of The 14 bit DAC B Input Data ADA Development Kit Normalized spectral plot of the 14 bit output bus of ADC J2 Magnitude dB D 05 1 15 2 2 5 3 35 45 Frequency Hz x 10 Figure 4 7 Normalized Spectral Plot of The 14 bit ADC B Output Data asic THDB ADA User Manual 2 www terasic com terki October 19 2015 Chapter 5 Appendix 5 1 The Revision History Version Change Log V1 0 0 Initial Version Preliminary V1 1 0 Add Default Demo for DE1 and DE2 V1 2 0 DE4 and DE2 115 Demo added V1 2 1 Change Figure V1 2 2 Change ADC and DAC description V1 2 3 Update Section 1 2 Connectivity V1 2 4 Update Section 1 2 Connectivity 5 2 Always Visit Terasic Webpage for New Applications We will continually provide interesting examples and labs on our ADA webpage Please visit www terasic com for more information THDB ADA User Manual 26 www terasic com Tijasic October 19 2015 www terasic com
3. This section describes the board s clock inputs and outputs The clock sources available on the ADA daughter board include the 100MHz oscillator external SMA clock input and the PLL clock input from either HSMC or GPIO interface Each channel of the AD and DA converter has the selection of choosing one of the clock sources oscillator SMA and PLL corresponding to the CLK SEL jumper of the ADA daughter board enam ADC CLKA D A EXT CLK Input A D EXT CLK Input Ana DAC CLKA 100MHz SEL cem CLK IB DAC CLKB Figure 3 3 ADA Clock System THDB ADA User Manual 18 www terasic com Tijasic October 19 2015 www terasic com Chapter 4 ADA Demonstration This chapter illustrates how to setup the ADA kit as an arbitrary waveform generator and evaluate the performance of A D and D A converter 4 1 Arbitrary Waveform Generator This section illustrates the implementation of random waveform generator using ADA For Terasic mainboards with more than one HSMC connector please refer to the table below for recommended connection Terasic Reference Mainboard DE3 Figure 1 5 Connect ADA HSMC with DE3 HSTC conector D DE4 Figure 1 6 Connect ADA HSMC with DE4 HSMC port A TR4 Figure 1 9 Connect ADA HSMC with TR4 HSMC port A Figure 4 1 is the complete setup of an ADA connected on DE3 Simply perform the following steps to display any pattern generated from PC based GUI on an oscilloscope The lt path gt is
4. USB Blaster 58 0 1271 cells 23 auto sig Not running 143360 bits O blocks 35 blocks Device None Detected Scan Chain Chain log 2010 09 09 20 36 29 0 DAC DA 2822 ONS x LI TF TITLE ST LI SAL U1 lpm add Ipmidatab b l Data setup Hierarchy Display x Ll Data Log Ea BB auto signaltap 0 DEZ 7 ADDA GPIO TOP U1 Ipm add lpm 23 auto signaltap 0 5n 00 00 00 Figure 4 4 Connect ADA GPIO with DE2 70 B Collecting Data Using the SignalTap II Logic Analyzer l Click Program Device after Hardware and Device are detected correctly 2 Click Run Analysis and observe signals ADC DB and comb which shows attenuated and original combinations of two sine waves respectively 3 Choose File gt Create Update gt Create SignalTap II List File and the Quartus II will generate the file stpl auto signaltap O txt in the project directory If your Quartus II version is above 9 1 Please click ADC DB and right click to select Create SignalTap II List File for outputting the List file As show on the Figure 4 5 asic THDB ADA User Manual 23 www terasic com October 19 2015 T SignalTap II Logic Analyzer D test 1 THDB ADA v1 2 0 CDRON new DE2 70 ADA DE2 70 ADA DE 70 ADA stpl stp l Kok File Edit View Project Processing Tools Window Instance Manager a Ready to acquire X JTAG Chain Configuration JTAG ready Status LEs 1271 Memory 143360
5. www terasic com yaz Qa ri fe per l C 1 ET 2 A tw w 2 nu D TN n PE FI GAL ilan gt Figure 1 4 Connect ADA HSMC with Cyclone III Starter THDB ADA User Manual 5 www terasic com Tijasic October 19 2015 www terasic com eh s LSO Y MModu le OCRE Y LT Unt Limsov Eo MModule d ms onan DA if III 000000 a MT so Da 3 3 e e 000120 0 da x OF aaa osa n m t t E t t lA O a ya n nm mi i mlm Ori gt nod 3 a ppo 4 EE tratix TITI AA d prin min i LIL ba de t E ING AR than id ie Ino Mi Gk m MI Ing SMM Gunun a 1 q 007090019 e LL III Figure 1 5 Connect ADA HSMC with DES HSTC conector D Note an HFF or SFF adapter card is required in its connection part of the bundled package on the DE3 li Tik ma gana ak dI 4 m ate TIN Wow L mb gt Figure 1 6 Connect ADA HSMC with DE4 HSMC port A Note an 2 adapter card is required in its connection part of the bundled package on the DE4 Tasic THDB ADA User Manual www terasic com www terasic com October 19 2015 E ni wtb 4 va 239 va m peretidsigans nd TTETETT IT 14424141 TE aaa eee Figure 1 7 Connect ADA HSMC with 2 115 AAA AAA bal bed kd
6. M512 MLAB 0 0 M4K MOK 43 250 M RAN Hardware USB Blaster USB 0 CO EE use Device 1 EP2C70 0x020B60DD gt gt SOF Manager Ctrl F F DAC DA Ctrl Shift F DAC DB U1llpm add l Plug In Options Add State Machine Nodes Recreate State Machine Mnemonics U1llpm add l Locate Ungroup Rename Mnemonic Table Setup Create SignalTap II List File O Data Log Align Left v Align Right auto signaltap 0 MSB on Top LSB on Bottom v LSB on Top MSB on Bottom auto Bus Display Format Figure 4 5 Using Quartus 10 0 sp1 SignalTap II to generate the SignalTap II List File B Analyzing the Data in the MATLAB Software 1 Start the MATLAB software 2 Make sure the current directory is set to lt path gt Demonstrations DE2_70_ADA 3 If you are using the DEI Board please copy the file nstp plot m from lt path gt MATLAB to lt path gt Demonstrations DE1_ADA 4 Type nstp plot stpl auto signaltap 0 txt at the MATLAB command prompt The MATLAB will display normalized FFT plots of DAC B input and ADC B output similar to Figure 4 6 and Figure 4 7 respectively THDB ADA User Manual 24 www terasic com Tijasic October 19 2015 www terasic com ADA Development Kit Normalized spectral plot of 14 bits of input data of DAC J4 Magnitude dB
7. respectively 4 Clock sources include oscillator 100MHz SMA for AD and DA each and PLL from either HSMC or GPIO interface 5 AD converter analog input range 2V p p range 6 DA converter output voltage range 2V p p range 7 DA and AD converters do not support DC signaling THDB ADA User Manual 10 www terasic com Tijasic October 19 2015 www terasic com Chapter 3 Using the ADA This chapter illustrates some special features of the ADA including interleaved data mode for digital to analog converter and multiplexed data mode for analog to digital converter 3 1 Digital to Analog Converter This section will describe the interleaved data mode for D A converter of the ADA The DAC integrates two 14 bit TxDAC cores with dual port input while supporting refresh rate up to 125 MSPS The dual channel makes it capable of transmitting different data to two separate ports with different update rates But it is the interleaving mode that makes it special especially for processing 1 and Q data in communication applications The input data stream is demuxed into its original I and Q data and latched In the next phase they are converted by the two TxDAC cores and updated at half the input data rate Figure 3 1 shows the timing of DAC in interleaved mode THDB ADA User Manual 11 www terasic com Tijasic October 19 2015 www terasic com JA DTE n A e INTERLEAVED DATA ew PY I LI LIL IQCLK
8. 9 131 29 AD DB7 ia Data Output bit 7 Channel 30 132 30 AD DA7 T Data Output bit 7 Channel 33 127 33 AD_DB8 D Data Output bit 8 Channel 34 128 34 AD DA8 Ka Data Output bit 8 Channel 35 125 35 AD DB9 Data Output bit 9 Channel 36 126 36 AD DA9 Xp Data Output bit 9 Channel 39 121 39 AD DB10 s Data Output bit 10 Channel 40 122 40 AD DA10 in Data Output bit 10 Channel 41 119 41 AD DB11 A Data Output bit 11 Channel 42 120 42 AD DA11 D Data Output bit 11 Channel 45 115 45 AD_DB12 Data Output bit 12 Channel 46 116 46 AD DA12 in Data Output bit 12 Channel 47 113 47 AD DB13 Data Output bit 13 Channel B www terasic com THDB ADA User Manual 16 Tijasic October 19 2015 www terasic com 48 114 48 AD DA13 A D Data Output bit 13 Channel A 52 110 52 ADC OEB A D Output Enable Pin for Channel B 54 108 54 ADC OEA A D Output Enable Pin for Channel A 63 97 63 PLL OUT DA PLL Clock Input Channel A CO 64 98 64 SMA DAC4 SMA D A External Clock Input J5 65 95 65 PLL OUT DA PLL Clock Input Channel B C1 66 96 66 OSC SMA A SMAA D External Clock Input DC4 J5 or 100MHz Oscillator Clock Input 69 91 69 DA MODE Mode Select 1 dual port O interleaved 71 89 71 DA WRTA Input Write Signal Channel A 12 90 72 DA_WRTB Input Write Signal Channel B 75 85 75 DA_DA13 D A Data bit 13 Channel A 76 86 76 DA_DB13 D A Data bit 13 Channel B 77 83 77 DA DA12 D A Data bit 12 Channel A 18 84 18 DA DB12 D A Data bit 12 Channel B 81 19 81 DA DA11 D A Data bit 11 Chann
9. DC DB2 ADC DB4 ADC DB3 ADC DB5 ADC DB6 ADC DB8 GND ADC DB7 ADC DB9 ADC DB10 ADC DB12 ADC DB11 ADC DB13 Tasic THDB ADA User Manual www terasic com Description A D Out of Range Indicator Channel A A D Data Output bit 0 Channel B A D Out of Range Indicator Channel B A D Data Output bit 1 Channel B A D Data Output bit 2 Channel B A D Data Output bit 4 Channel B A D Data Output bit 3 Channel B A D Data Output bit 5 Channel B A D Data Output bit 6 Channel B A D Data Output bit 8 Channel B Ground A D Data Output bit 7 Channel B A D Data Output bit 9 Channel B A D Data Output bit 10 Channel B A D Data Output bit 12 Channel B A D Data Output bit 11 Channel B A D Data Output bit 13 Channel B 13 www terasic com October 19 2015 AU S n A e 19 PLL OUT ADCO PLL Clock input Channel A 20 ADC DAO A D Data Output bit O Channel A 21 PLL OUT ADC1 PLL Clock input Channel B 22 ADC DA1 A D Data Output bit 1 Channel A 23 ADC DA2 A D Data Output bit 2 Channel A 24 ADC DA4 A D Data Output bit 4 Channel A 25 ADC DA3 A D Data Output bit 3 Channel A 26 ADC DA5 A D Data Output bit 5 Channel A 27 ADC DA6 A D Data Output bit 6 Channel A 28 ADC DA8 A D Data Output bit 8 Channel A 29 VCC3 3 3V Power 30 GND Ground 31 ADC DA7 A D Data Output bit 7 Channel A 32 ADC DA9 A D Data Output bit 9 Channel A 33 ADC DA10 A D Data Output bit 10 Channel A 34 ADC DA12 A D Data Output bit 12 Channel A 35 ADC DA11 A D Data Output bit 11 C
10. IQRESET Ea SO N DAC OUTPUT ag PORT 1 D1 PS DAC OUTPUT PORT 2 D4 D2 Figure 3 1 Interleaved Mode Timing 3 2 Analog to Digital Converter This section will describe the multiplexed data mode for A D converter of the ADA The ADC features dual sample and hold amplifiers with data rate up to 65 MSPS at the resolution of 14 bit Its dual channel inputs can also operate as two independent ports with different clock rates Based on the state of the MUX option multiplexed data output can be achieved by mixing data from the dual ports and the data rate is twice the sample rate Figure 3 2 shows the multiplexed data format using the channel A output and the same clock tied to clock inputs of port A and B and the selection of MUX option THDB ADA User Manual 12 www terasic com October 19 2015 www terasic com 3 3 Board Components ANALOG INPUT ADC A ANALOG INPUT ADC B CLK A CLK B MUX SELECT DO ATO D11 A Figure 3 2 Multiplexed Data Format using the Channel A Output This section illustrates the detailed information of the connector interfaces and pin mapping tables of the ADA daughter board The clock control and data signals of the ADA daughter board are connected to the HSMC or GPIO connector The tables below list the pin no of the HSMC and GPIO connector Pin No GPIO 0 J7 0 ND OB ON 10 11 12 13 14 15 16 17 18 Schematic Name ADC_OTRA ADC DBO ADC OTRB ADC DB1 A
11. ata bit 0 Channel A PLL Clock Input Channel A Input Write Signal Channel A PLL Clock Input Channel B D A Data bit 13 Channel B D A Data bit 12 Channel B D A Data bit 11 Channel B D A Data bit 9 Channel B D A Data bit 10 Channel B D A Data bit 8 Channel B 3 3V Power Ground D A Data bit 5 Channel B D A Data bit 7 Channel B D A Data bit 4 Channel B D A Data bit 6 Channel B D A Data bit 1 Channel B D A Data bit 3 Channel B D A Data bit O Channel B D A Data bit 2 Channel B Input Write Signal Channel B Mode Select 1 dual port O interleaved Schematic Name PLL OUT AD CO AD OTRA PLL OUT AD C1 AD OTRB AD DBO AD DAO AD DB AD DAI Description PLL Clock Input Channel A A D Out of Range Indicator Channel A PLL Clock input Channel B A D Out of Range Indicator Channel B A D Data Output bit O Channel B A D Data Output bit 0 Channel A A D Data Output bit 1 Channel B A D Data Output bit 1 Channel A www terasic com October 19 2015 15 145 15 AD DB2 A D Data Output bit 2 Channel 16 146 16 AD DA2 z Data Output bit 2 Channel 17 143 17 AD DB3 n Data Output bit 3 Channel 18 144 18 AD DA3 M Data Output bit 3 Channel 21 139 21 AD DB4 E Data Output bit 4 Channel 22 140 22 AD DA4 in Data Output bit 4 Channel 23 137 23 AD DB5 Data Output bit 5 Channel 24 138 24 AD DA5 Data Output bit 5 Channel 27 133 27 AD DB6 Data Output bit 6 Channel 28 134 28 AD DA6 a Data Output bit 6 Channel 2
12. boards with HSMC or GPIO interface It is equipped with one ADC Analog to Digital Converter and DAC Digital to Analog Converter each to provide dual channel ports This chapter provides users key information about the kit 1 1 Kit Contents Figure 1 1 and Figure 1 2 show the picture of the ADA HSMC and ADA GPIO package respectively The package includes 1 The Terasic Analog to Digital and Digital to Analog ADA board 2 Complete reference design with source code osc PEZON GIA an sua BO CONCA pr EL IN GHA A www terasic com oem LU V Www x NO A n26OY o E v mann 5 Mt u 2 tinm I pag nunu Pa Umawat IK muni je i m 1 i i i 25 s a Yi Ne MN o Figure 1 1 ADA HSMC ter THDB ADA User Manual 3 m maa qu www terasic com October 19 2015 amn NI UG a A ter PAT N www terasic com d Ze kb r 3 E 2 Bl T 1 B Eu p s C8 m m 7 RAGI ped legis rs Ani po G Ng DA CHANNEL A mc Zum E ti OE DA CHANNEL B e E Figure 1 2 ADA GPIO 1 2 Connectivity There are two models available ADA GPIO and ADA HSMC which offer the compatibility of connection to DE2 DE1 DE0 DE2 70 and TR4 DE4 DE3 DE2 115 DE21 150 SoCkit DE1 SoC Cyclone V Starter Kit Cyclone III Starter Kit respectively THDB ADA User Manual 4 www terasic com Tijasic October 19 2015
13. el A 82 80 82 DA DB11 D A Data bit 11 Channel B 83 77 83 DA DA10 D A Data bit 10 Channel A 84 18 84 DA DB10 D A Data bit 10 Channel B 87 73 87 DA DA9 D A Data bit 9 Channel A 88 74 88 DA DB9 D A Data bit 9 Channel B 89 71 89 DA DA8 D A Data bit 8 Channel A 90 72 90 DA DB8 D A Data bit 8 Channel B 93 67 93 DA DA7 D A Data bit 7 Channel A 94 68 94 DA DB7 D A Data bit 7 Channel A 95 65 95 DA DAG D A Data bit 6 Channel A 96 66 96 DA DB6 D A Data bit 6 Channel B 99 61 99 DA DA5 D A Data bit 5 Channel A 100 62 100 DA DB5 D A Data bit 5 Channel B 101 59 101 DA DA4 D A Data bit 4 Channel A 102 60 102 DA DB4 D A Data bit 4 Channel B 105 55 105 DA DA3 D A Data bit 3 Channel A 106 56 106 DA DB3 D A Data bit 3 Channel B 107 53 107 DA DA2 D A Data bit 2 Channel A 108 54 108 DA DB2 D A Data bit 2 Channel B 111 49 111 DA DA D A Data bit 1 Channel A 112 50 112 DA DB1 D A Data bit 1 Channel B 113 47 113 DA DAO D A Data bit 0 Channel A THDB ADA User Manual 17 www terasic com Tijasic October 19 2015 www terasic com 114 48 114 DA DBO _D A Data bit Channel B 121 121 POWER ON Power Down Function for o Channel A 8 B 125 37 125 TDO TDI JTAG 126 38 126 TDO TDI JTAG 131 33 131 ID I2CDAT 2 EEPROM serial m address data I O 132 34 132 ID I2CSCL 12C EEPROM serial clock 3 4 Clock Circuitry
14. hannel A 36 ADC DA13 A D Data Output bit 13 Channel A 37 POWER ON Power Down Function for Channel A amp B 38 ADC OEB A D Output Enable Pin for Channel B 39 40 ADC_OEA A D Output Enable Pin for Channel A Pin No Schematic Description GPIO 1 J8 Name 1 SMA DAC4 SMA D A External Clock Input J5 2 DAC DA13 D A Data bit 13 Channel A 3 OSC SMA ADC4 SMA A D External Clock Input J5 or 100MHz Oscillator Clock Input 4 DAC DA12 D A Data bit 12 Channel A 5 DAC DA11 D A Data bit 11 Channel A 6 DAC DA9 D A Data bit 9 Channel A 7 DAC DA10 D A Data bit 10 Channel A 8 DAC DA8 D A Data bit 8 Channel A 9 DAC DA7 D A Data bit 7 Channel A 10 DAC DA5 D A Data bit 5 Channel A 11 12 GND Ground 13 DAC DA6 D A Data bit 6 Channel A 14 DAC DA4 D A Data bit 4 Channel A 15 DAC DA3 D A Data bit 3 Channel A 16 DAC DA1 D A Data bit 1 Channel A 17 DAC DA2 D A Data bit 2 Channel A THDB ADA User Manual 14 www terasic com www terasic com October 19 2015 AN S RYA o 18 DAC DAO 19 PLL OUT DACO 20 DAC WRTA 21 PLL OUT DACI 22 DAC DB13 23 24 DAC DB12 25 DAC DB11 26 DAC DB9 21 DAC DB10 28 DAC DB8 29 VCC3 30 GND 31 DAC DB5 32 DAC DB7 33 DAC DB4 34 DAC DB6 35 DAC DB1 36 DAC DB3 3 DAC_DBO 38 DAC_DB2 39 DAC WRIB 40 DAC MODE Pin No Pin No Pin No ADA HSMC HSMC HSTC DE3 J9 only 3 157 3 4 158 4 5 159 5 6 156 6 9 151 9 10 152 10 11 149 11 12 150 12 www terasic com THDB ADA User Manual D A D
15. hol 1 Figure 1 8 Connect ADA HSMC with C5G Cyclone V GX Starter Kit THDB ADA User Manual 7 www terasic com Tijasic October 19 2015 www terasic com wf iol WE B bn n do LAL 3 i Gtratx Il ge us dani iii Figure 1 10 Connect ADA HSMC with DE2i 150 THDB ADA User Manual 8 www terasic com Tijasic October 19 2015 www terasic com R SE 9 DA o Eo add ti l BURN 2 Ma us TANA J t 1203225287 y ot Si E ma Ill y ui 008100023 4 n AS gt ERE a ial pil pami pan Figure 1 12 Connect ADA HSMC with SoCkit 1 3 Getting Help This chapter describes the architecture of the tPad including block diagram and components e Email to support terasic com e Taiwan amp China 886 3 575 0880 e Korea 82 2 512 7661 e Japan 81 428 77 7000 THDB ADA User Manual 9 www terasic com Tijasic October 19 2015 www terasic com Chapter 2 Architecture of the ADA This chapter will illustrate the architecture of the ADA including device features and applications The feature set of the ADA 1s listed below 1 Dual AD channels with 14 bit resolution and data rate up to 65 MSPS 2 Dual DA channels with 14 bit resolution and data rate up to 125 MSPS 3 Dual interfaces include HSMC and GPIO which are fully compatible with Cyclone III Starter Kit and DE1 DE2 DE2 70 DE2 115 DE3 DE4
16. tes the steps to evaluate the performance of A D and D A converter on ADA based on the data collected from DE2 70 Similar steps can also be applied to DE2 115 DE2 DE1 or DE4 Cyclone III Starter Kit The lt path gt is the directory where you copy the reference design folder DE2 70 ADA from CD to your PC THDB ADA User Manual 21 www terasic com ter October 19 2015 www terasic com E 6 o 1 1 gt ang aa Figure 4 3 Connect ADA GPIO with DE2 70 B Configuring the Board 1 Connect the ADA GPIO to DE2 70 as shown in Figure 4 3 2 Use a SMA cable to connect DA Channel B with AD Channel B 3 Use a USB cable to connect DE2 70 with PC 4 Add appropriate jumpers for the mode and the clocks a For DAC B clock add a jumper to JP5 with pins labeled PLL b For ADC B clock add a jumper to JP2 with pins labeled PLL c For the selection of MUX option add a jumper to JP3 between pins and 2 5 Power on DE2 70 6 Open stpl stp from lt path gt Demonstrations DE2_70_ADA as shown in Figure 4 4 THDB ADA User Manual 22 www terasic com Cjasic October 19 2015 www terasic com E SignalTap II Logic Analyzer D test 1 THDB ADA v1 2 0 CDRON new DE2 TU ADA DE2 TU ADA DE 70 ADA OR File Edit View Project Processing Tools Window Instance Manager Fa ho m Invalid JTAG configuraton x JTAG Chain Configuration No device is selected o x Instance Status LEs he Memory 143360 M512 MLAB 0 0 MAMIK Hardware
17. the directory where you copy the reference design folder DE3 ADA from CD to your PC THDB ADA User Manual 19 www terasic com Tijasic October 19 2015 www terasic com Figure 4 1 Configuration Setup of Random Waveform Generator on DE3 B Configuring the Board 1 Connect the ADA HSMC to DE3 as shown in Figure 4 2 Use a SMA cable to connect DA Channel B with an oscilloscope For DAC B clock add a jumper to JP3 with pins labeled PLL Use a USB cable to connect DE3 with PC Power on DE3 Open DE3 ADA qsf from lt path gt Demonstrations DE3_ADA Open Quartus Programmer from Tools gt Programmer kN E A x NG Press Start on the left hand side B Starting PC Based Graphical User Interface 1 Open ADA Utility exe from path2VADA Utility If you are using Cyclone III Starter Board please first run the QB3 ADA bat file THDB ADA User Manual 20 www terasic com ter October 19 2015 www terasic com JA DTE RAM 2 Use your mouse to draw a custom waveform from left to right You may drag it or add more points to be sampled later on 3 Set the frequency and the amplitude 4 Press Start 5 Press Auto set on the oscilloscope if necessary Trig d M Pos 0 000s AUTUSET n Ge v0 0 0 Autoset M 250ns CH1 621m 16 Mar 06 16 44 2 00012P4H2 Figure 4 2 Pattern generated from DAC Channel B is displayed on an oscilloscope 4 2 AID and D A Converter Performance Evaluation This section illustra
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