User`s Manual (Rev.1.04)
Contents
1. EXT IO HIGH ORDER ADDRESS SETTING REGISTER 4500 6000H READ WRITE This register specifies a high order address A23 A22 to access the l O space of the external extension bus EXT bus Register or os o4 os o2 or oo 4500 6000H CMD 1 xX x x xX Xx EA23 EA22 initial value 0 0 17 RTE V832 PC USER S MANUAL Rev 1 03 8 7 UART PRINTER TL16PIR552 4500 8000H TO 4500 A03EH The Texas Instruments TL16PIR552 dual UART with 1 284 parallel port LSI is used as UART PRINTER TL16PIR552 has two UART channels and one bidirectional printer port channel conforming to IEEE1284 It also has a 16 character FIFO buffer in the transmission reception block of the UART and a function for automatically controlling RTS CTS flow Therefore an overrun error can be suppressed by the minimum interrupt Each register of the TL16PIR552 is assigned as listed below For an explanation of the function of each register refer to the manual provided with the TL16PIR552 The manual for TL16PIR552 is available from the TI amp ME corner of the Texas Instruments home page http www ti com UART CH 0 FCR UART CH 1 IR LSR LSR ae 4500 9008H MR Ms 4500 9001CH SR sch PANTER PPOS 4500 A004H 4500 AA to 4500 A01CH 4500 E000H PRINTER ECPCS PPDATAFIFO PPDATAFIFO TESTFIFO CNFGA TESTFIFO 4500 E004H CNFGB 4500 E008H ECR ECR T2. So be careful when extracting signals from the JCPU The 3 3 V signal level is used ar earn s wm we m 79 PB1 JCPU 1 Connector Signals 10 RTE V832 PC USER S MANUAL Rev 1 03 as KA s os w e c w c c e w ws mw w Rv ww w c m ao m e t Eee e S gt es m aeo w t m m 9 JCPU 2 Connector Signals The connector used is the FX2 80P 1 27SV manufactured by Hirose Electric Co Ltd 5 19 EXTENSION BUS CONNECTOR JEXT The JEXT connector is provided to enable memory or l O extension This connector is internally connected to the local bus of the board For details see Chapter 10 11 RTE V832 PC 6 6 1 lt 1 gt lt 2 gt lt 3 gt lt 4 gt 1 6 2 USER S MANUAL Rev 1 03 CONNECTION WITH THE HOST PC STANDALONE USE OF THE BOARD RS 232C CONNECTION Serially connect the host machine by means of the following procedure Get an RS 232C cable for connection with the host and an external power supply 5 V A on hand For the power supply watch for its voltage capacity and connector polarity The RS 232C cable is of the type generally called a cross cable Confirm the wiring before using this cable See Sections 5 14 and 5 2 f
3. Space Access Address 4n 0 and or 4n 1 32 16Bit Low EXT BUS DI31 161 User Board Cycle Flyby DMA 32 16Bit Low EXT BUS DI31 161 User Board USER S MANUAL Rev 1 03 Cycle EXT BUS Memory Space Access Address 4n 2 and or 4n 3 32 16Bit High EXT BUS ser Board Cycle EXT BUS Memory Space Access Address 4n 2 and or 4n 3 32 16Bit Low EXT BUS ser Board DI31 161 Cycle EXT BUS Space Access Address 4n 2 and or 4n 3 32 16Bit Low EXT BUS er Board DI31 161 28 RTE V832 PC 10 3 2 32 Bit Data Bus CPU with V832 Cycle EXT BUS Memory Space Access Address 4n 0 and or 4n 1 and or 4n 2 and or 4n 3 32 16Bit High User Board Cycle EXT BUS l O Space Access Address 4n 0 and or 4n 1 and or 4n 2 and or 4n 3 32 16Bit High User Board Cycle Flyby DMA Reference 32 16Bit High User Board Cycle EXT BUS Memory Space Access Address 4n 0 and or 4n 1 32 16Bit Low EXT BUS cor Board DI31 161 Cycle EXT BUS Space Access Address 4n 0 and or 4n 1 32 16Bit Low EXT BUS User Board DI31 161 Cycle Flyby DMA Reference Access Memory Address 4n 0 and or 4n 1 32 16Bit Low EXT BUS ser Board DI31 161 USER S MANUAL Rev 1 03 Cycle EXT BUS Memory Space Access Address 4n 2 and or 4n 3 32 16Bit Low Cycle EXT BUS I O Space Access Address 4n 2 and or 4n 3 32 16Bit Low Cycle Flyby
4. For interfacing with SDRAM the DRAM controller built into the V832 is used CS1 space x100 000 to x1FF FFFF x900 000 to x9FF FFFF SDRAM of 16M bytes is mapped Both the 16 bit and 32 bit data bus widths can be specified by using SW2 1 However the memory capacity is limited to 8M bytes when the 16 bit width is selected For interfacing with SDRAM the DRAM controller built into the V832 is used CS2 space x200 000 to x27F FFFF xA00 000 to xA7F FFFF A controller is mapped as a bridge to PCI CS3 space x300 000 to x3FF FFFF xB00 000 to xBFF FFFF CS3 is not used CS4 space 400 000 to x40F FFFF xC00 000 to xCOF FFFF The 16M byte memory area on the EXT bus is mapped CS5 space x500 000 to x5FF FFFF xD00 000 to xDFF FFFF The devices of the board such as the timer Audio and serial and parallel interfaces and EXT bus IO area are mapped Because full decoding is not performed image spaces appear at various locations So never attempt to access other than the specified 1 0 addresses Wait control is exercised by external FPGA For details of each 1 0 device see Chapter 8 CS6 space x600 000 to x6FF FFFF xE00 000 to xEFF FFFF A high speed SRAM of 512K bytes NEC s uPD431008LE 15 128K x8 bits 15 ns is mapped Both the 16 bit and 32 bit data bus widths can be specified by using SW2 1 A memory capacity of 512K bytes is allocated even when the 16 bit width is selected An SRAM image appears at 512K byte intervals
5. Selects either the upper or lower half when DIS OFF OFF Selects upper half Selects lower half factory setting SWITCH 3 SW3 SW3 physically cuts the interrupts used in this board All the bits of this switch are set to ON connected status at the factory Set the corresponding bit of this switch only when it is used externally and only when the internally used interrupt is unnecessary INTP12 EXTbus INT2 INTP11 EXTbus INT1 INTPIO EUM RTE V832 PC USER S MANUAL Rev 1 03 5 6 5 7 5 8 SWITCH 4 SW4 SWA physically cuts the DMA used by this board All the bits of this switch are set to ON connected status at the factory Set the corresponding bit of this switch only when it is used externally and only when the internally used DMA is unnecessary Internally used interrupt source DMARQ2 EXTbus DREQO DMAAK2 EXTbus DACKO DMARQ3 EXTbus DREQI DMAAK3 EXTbus DACKt Caution Set switch bits 1 and 2 and 3 and 4 to the same positions LED The LEDs are used to indicate statuses as listed below POWER Lights when power is supplied to the RTE V832 PC board PLY Lights in green when voice is output Lights in red if an error occurs during voice output REC Lights in green when voice is recorded Lights in red if an error occurs during voice recording PCI Lights if a parity error occurs in the PCI bus PCI9 DEAD Lights if the PCI controller is deadlocked
6. Usually this command should not be used 13 3 3 VER Format VER Displays the version number of the current RTE environment 13 3 4 INB INH INW Format INB address INH address INW address Reads from an I O register The INB INH and INW commands access in byte halfword and word units respectively If an address is omitted the previous address is assumed Example 1000 Reads a byte from an I O register at 1000H 42 RTE V832 PC USER S MANUAL Rev 1 03 13 3 5 13 3 6 13 3 7 13 3 8 13 3 9 OUTB OUTH OUTW lt Format gt OUTB address data OUTH address data OUTW address data Writes to an I O register The OUTB OUTH and OUTW commands access in byte halfword and word units respectively If an address or data is omitted the previous address or data is assumed Example OUTH 2000 55AA Writes the halfword 55AAH to the I O register at 2000H DCTR Command Format DCTR ALL Displays the contents of DCTR registers There are 256 DCTR registers Among these 256 registers the contents of the registers whose valid bit is on are displayed except when ALL is specified If ALL is specified the contents of all DCTR registers are displayed The DCTR registers are mapped on the I O space f2000000h f2000fffh ICTR Command Format ICTR ALL Displays the contents of ICTR registers There are 128 ICTR registers Among these 128 registers the contents of the registers
7. Wait control is exercised by the bus controller built into the CPU Access is possible with no wait clock cycles when a 33 MHz or less external clock is used CS7 space x700 000 to x7FF FFFF xF00 000 to xFFF FFFF This is a space for boot ROM that is booted by the 16 bit bus BT16B pin is fixed to 16 bits As an EPROM 27C1024 27C2048 or 274096 120 ns or less 40 pin DIP type can be used The evaluation board is factory fitted with a 27C1024 incorporating the monitor Wait control is exercised by the bus controller built into the CPU The ROM area requires an access time of 120 ns or longer Caution When SDRAM and SRAM are used at the 16 bit width set SW2 1 BSIZE32 to ON and then set the memory controller Only either one of SDRAM and SRAM can be used at the 16 bit width 14 RTE V832 PC USER S MANUAL Rev 1 03 8 devices such as Audio UART PRINTER TIC and EXT BUS are mapped to separate I O spaces These I O spaces mapped the space of CS5 This section explains the mapping and devices 8 1 I O LIST The table below lists the I O areas and functions UART CH 1 TL16PIR552 setting reference UART CH 2 TL16PIR552 setting reference PRINTER PP TL16PIR552 setting reference Timer controller 1uPD71054 setting reference PRINTER ECP TL16PIR552 setting reference 1 EXT BUS I O space As the EXT BUS I O space a 16M byte space is accessed by using the EXT IO hig
8. 03 11 2 LIBRARIES Libraries are required for programming using the C compiler for l O accesses and other purposes However the methods of writing these libraries and passing their parameters described below are specific to the MULTI So modifications may be required for example when another compiler is used VO library GHS V800 compiler parameter passing r6 argl r7 arg2 r8 return r10 inb int addr Byte 8 bits input _ asm in b O r6 10 inh int addr Half word 16 bits input _ asm in h O r6 r10 inw int addr Word 32 bits input asm in w O r6 r10 int addr int data asm out b r7 O r6 int addr int data asm out h r7 O r6 int addr int data Byte 8 bits output Half word 16 bits output Word 32 bits output asm out w r7 O r6 33 RTE V832 PC USING TIMERS USER S MANUAL Rev 1 03 A sample time measurement is indicated below which uses timer 1 and timer 2 cascaded with each other by an external timer 8254 on the board Timer 1 is initialized as an interval counter mode 2 and timer 2 is initialized as a down counter mode 0 By determining the counter values before and after a routine whose execution time is to be measured the execution time can be calculated Note that both timers function as down counters Note also that command recovery dummy read from
9. 03 12 4 RESTRICTIONS ON BREAK POINTS IN THE INTERRUPT HANDLING The following restrictions are imposed on breaks in the interrupt handling routine 1 During a break all maskable interrupts are rejected 2 The single step function sets a temporary breakpoint in the next instruction So when a user program placed in the El interrupt enable state is subject to single stepping an interrupt is accepted even during single stepping 3 After a break in the interrupt handling routine exiting from the interrupt handling routine by single stepping is impossible Specifically single stepping based on the last of the interrupt handling routine is disabled Similarly IRET instruction single stepping is impossible 4 The Return function of the debugger does not support return from an interrupt handling routine to the original routine 39 RTE V832 PC USER S MANUAL Rev 1 03 13 APPENDIX A MULTI MONITOR This chapter describes how to make the settings required to establish a connection between the Multi monitor stored in ROM and the Multi debugger on the host It also provides notes on the use of the Multi monitor 13 1 BOARD SETTING 13 1 1 RTE for Win 32 Installation When the board is used with the Multi debugger communication software called RTE for Win32 must be installed in the PC Refer to the RTE for Win32 Installation Manual supplied with this product for installation and test methods 13 1 2 SW1 Setting SW1 is a sw
10. 07 Do D4 DB Dt o 4500 1000H SW1 SW1 SW1 SW1 SW1 SW1 Swi 0 ON input 8 7 6 5 4 3 2 1 1 OFF SW1 1 corresponds to switch 1 of SW1 while SW1 8 corresponds to switch 8 of SW1 When a bit is 0 is read When a bit is OFF 1 is read SW1 is used to set the operation of the monitor For how to set this switch see Sections 13 2 1 and 14 1 1 7 SEGMENT LED DISPLAY DATA OUTPUT PORT 4500 2000H WRITE ONLY This port sets the data to be displayed on the 7 segment LED The table below indicates the data format When a bit is set to 0 the corresponding segment is turned on Data bus as o Logical address Setting 07 Do D4 DB De Dt o 4500 2000H 7SEG 7SEG 7SEG 7SEG 7SEG 7SEG 7SEG 7SEG 0 Turned on output DP G F E D C B 1 Turned off The figure below illustrates the correspondence between the bits and the segments of the 7 segment LED GA 2 16 RTE V832 PC USER S MANUAL Rev 1 03 8 5 8 6 COMMAND REGISTER 4500 5000H READ WRITE This register has the following functions Fo os s os v ve os 0o 4500 5000H CMD 1 x x xX X TOVEN initial value 0 TOVEN Controls the use of the time over function When the length of a bus cycle reaches 512 bus clocks the time over function returns READY and forcibly terminates the bus cycle TOVEN 0 Ud Used Reset value
11. DMA Reference Access Memory Address 4n 2 and or 4n 3 32 16Bit Low User Board User Board User Board 29 RTE V832 PC USER S MANUAL Rev 1 03 10 4 TIMING A 1 23 A 1 23 DMAAK 0 1 DMAAK 0 1 MRD Y MRD IORD IORD MWR 0 3 52 MWR 0 3 IOWR IOWR D 0 31 D 0 31 READY A READY Read cycle Write cycle DMAAK 0 1 IORD IOWR DMARQ 0 1 DMA cycle EXT BUS Cycle ADDR DMAAK gt IORD setup time ue e MRD IORD gt ADDR DMAAK hold time 10 MRD ORD oycetme TT oro po data AO READY 0 T6 MPD gt RD DATAhod me o f ro omo AO READY aay maa RD READY gt MRD IORD delay time Eee pe A peo omo gt AO READY had ime 0 110 ADDR gt IOWR setup ime 10 gt ADDR DARK hoa ime 0 T WR OWRode me ms T14 MWR IOWR WRDATAdey me 20 ms mwe WA DATA nda ime o Crie mne one owa REAY eyre AAA mr Wwa READY gt MWA IOWA Rene 118 MWR IOWR gt WR READY hodime o f ms lomo gt DMARG aedi ins EXT BUS AC Specifications RTE V832 PC USER S MANUAL Rev 1 03 10 5 APPLICABLE CONNECTORS The connectors used for EKT BUS and the connectors that can be connected to those connectors are listed below If E
12. NMI is recommended The differences between the two interrupts are listed below When is used A break can occur at any time during user program execution If however a break occurs during DMA operation the DMA is also terminated The DMA does not restart even upon reexecution When INTPOS is used No break will occur if the user program uses an interrupt with a higher priority than INTPO3 or if interrupts are disabled DMA operation is continued even during a break INIT SP Setting INIT SP stack pointer initial value is set to FE06 FFFOH highest SRAM address by the monitor INIT SP be changed in the Multi debugger environment Remote Connection Either serial or PCI bus connection can be selected to connect the monitor with the Multi debugger To switch from serial connection to PCI bus connection or vice versa it is necessary to reset the monitor by pressing the reset switch on the rear panel and run the Check RTE32 exe utility of RTE for Win32 Monitor Execution Area The 128K byte ROM contains two codes the lower 64K byte area contains the code to be executed in the cacheable area while the higher 64K byte area contains the code to be executed in the uncacheable area To enable a program to be downloaded at higher speed select the cacheable area Note that monitor intervention including profile timer operation temporarily flushes the cache used during user program execution so that data obtained from profile
13. a cascade connection HPD71054 PIC to interrupt controller From JP2 PIC to interrupt controller Examples of modes CH 0 Mode 2 rate generator CH 1 Mode 2 rate generator CH 2 Mode 0 down counter 19 RTE V832 PC USER S MANUAL Rev 1 03 8 9 INTERRUPT CONTROLLER PIC 4500 D000H TO 4500 D018H The PIC mainly exercises interruptrelated control The table below indicates the assignment of registers With the RTE V832 PC INTO of the is connected to NMI or of the V832 according to the specification of NMI INT3 INT1 is connected to INTPO2 Data bus pie mron o uos mos mox T mos fiee or E we iwa Cro re es ex es re mu The INTOM and INT1M registers mask interrupts applied to INTO and INT1 respectively When the IMOx or IM1x bit is set to 1 the interrupt is enabled When multiple bits are selected each OR value activates an interrupt Caution Always write 0 into bit 7 of INTOM and INT1M The INTR register is an interrupt status register for which 1 is read whenever there is an interrupt request This does not depend on the state of masking To clear an edge interrupt request the corresponding bit of this register must be set to 1 The table below indicates the interrupt source assigned to each bit of IMO 0 7 IM1 0 7 and IR O 7 meomeen 6 The INTEN
14. program uses an interrupt with a higher priority than or if interrupts are disabled DMA operation is continued even during a break SP Setting The stack pointer initial value is set to FE06 FFFOH highest SRAM address by the monitor The monitor uses a 32 byte stack area set by the user program Remote Connection Serial connection or PCI bus connection can be selected for connection of the debugger To change the connection from one to another reset the monitor press the reset switch on the rear panel and start RPTSETUP exe to change the communication path Monitor Execution Area The 128K byte ROM contains two codes the lower 64K byte area contains the code to be executed in the cacheable area while the higher 64K byte area contains the code to be executed in the uncacheable area If the monitor is executed in the casheable area the monitor execution speed is faster So the program is downloaded at a higher speed Normally use the cacheable area the area is factory set The use of the cacheable area is factory set with SW2 8 on Special Instruction The monitor uses the following instruction for the single step breakpoint and system call functions BRKPNT instruction 0x6cxx Do not use a code that may be interpreted as a break instruction in the user program 45 RTE V832 PC USER S MANUAL Rev 1 03 Memo RTE V832 PC User s Manual M813MNLO1 46
15. register enables or disables all interrupts NMIEN Disables a non maskable interrupt NMI by hardware At this time the NMI pin is high The NMI request from the JROM_EM1 connector is input to the CPU regardless of this bit o Sets mask Reset value Does not set a mask NMVINTP3 Specifies whether an INTO interrupt is to be applied to NMI or Nam 00 INTPOS Reset value Caution INTO is used with the monitor So never modify the related registers INT1 is released and can be used freely 20 RTE V832 PC USER S MANUAL Rev 1 03 8 10 AUDIO CONTROLLER AUDCNT 4580 0000H TO 4580 0010H 4580 2000H AUDONT controls digital data input to and output from the audio chip uPD63310 4580 0000H CONTROL os om vo os pst o o o o rw RC o7 os os os os o2 o vo 4580 0008H STATUS Ls fet o per s sec o7 os ps pe ps o2 ps po 0 Fro o Pov Pun Pex 4580 0010H MCLKDIV D15 D14 D13 D12 D11 o o o ave ove ova Towo A A 4580 2000H AUDIO DATA D15 to DO First time L channel 16 bits Second time R channel 16 bits The CONTROL register controls voice recording replay Read write RST Audio reset Reset clear Reset value Reset Replay operation Reset value Underflow interrupt upon replay Disable Res
16. whose valid bit is on are displayed except when ALL is specified If ALL is specified the contents of all ICTR registers are displayed The ICTR registers are mapped on the space fa000000h faO00fffh PLLCR Command Format PLLCR Displays the value of the PLLCR register CMCR Command Format CMCR VALUE Specifies a value in the cache memory control register CMCR 13 3 10 SFR Command Format SFR register name data When a register name is specified with data omitted the data read from the register is displayed When a register name is specified and data is specified after the data is written to the register The size of data is automatically determined according to the valid size of the specified register For details of the internal I O registers refer to the manual provided with the V832 CPU Example 1 gt SFR A list of registers is displayed Example 2 gt SFR IMR The contents of the IMR register are displayed Example 3 gt SFR IMR 55AA Data 55AAH is written into the IMR register 43 RTE V832 PC USER S MANUAL Rev 1 03 14 14 1 APPENDIK B PARTNER MONITOR This chapter describes how to make the settings reguired to establish a connection between the PARTNER monitor stored in ROM and the PARTNER on the host Italso provides notes on the use of the PARTNER monitor BOARD SETTING 14 1 1 SW1 Setting SW1 is a switch for general purpose input ports For the PARTNER monitor in the
17. 2 6 5 13 AUDIO INPUT LEVEL SELECT JUMPERS JP4 JP5 6 6 5 14 SERIAL CONNECTOR JSIO1 JSIO2 7 5 15 PARALLEL CONNECTOR JPRT eerte tette 8 5 16 AUDIO MINI JACKS JIN R JIN L JLINEOUT ettet 8 5 17 DEBUGGING CONNECTOR JDCU e ectetuer 9 5 18 CPU CONNECTOR JCPU T JCPUES en tu etr bao e ideo Debs 10 5 19 EXTENSION BUS CONNECTOR JEXT seeetettetet tette tette tetas 11 6 CONNECTION WITH THE HOST PC eene 12 6 1 STANDALONE USE OF THE BOARD RS 232C CONNECTION 12 6 2 INSERTING IN PCI SLOT PCI BUS 44 440 12 7 HARDWARE REFERENCES eee tette tette tette car 13 7 1 MEMORY AND I O MAP scat e a 13 UMBA A ads 15 a 15 82 DIPSW2 READ PORT 4500 0000H READ 16 8 3 DIPSW1 READ PORT 4500 1000H READ ONLY 16 84 7 SEGMENT LED DISPLAY DATA OUTPUT PORT 4500 2000H WRITE ONLY 16 8 5 COMMAND REGISTER 4500 5000H READ WRITE cette 17 8 6 HIGH ORDER ADDRESS SETTING REGISTER 4500 6000H READANBITETI s tct ts co E RO da 17 87 UART PRINTER TL16PIR552 4500 8000H TO 4500 1
18. 2 10 TBT gt 2 lt lt 8 SAD fix 0 lt lt 6 DAD inc 0 lt lt 5 DAL Low 0 4 DRL Low 1 lt lt 3 TM demand 1 lt lt 1 DS half word D Enable outh 0 45800000 0x100 Start recording while inh DMAl 12 amp 1 0 P Wait for DMA termination outh 0x45800000 0 Recording termination return 0 define COUNT 0x10000 L R data sample count int buffer COUNT L R data buffer main 1 inb 0xC000006E outb 0xC000006E 1 DMA DC MEM 1 AudioInit AudioRecord int buffer sizeof buffer AudioPlay int buffer sizeof buffer AudioTerm Initialization Recording Replay Termination return 0 Audio data consists of 16 bit data for each of Lch left and Rch right Data is to be input and output in order from L1 to R1 to L2 to R2 and so forth for both recording and replay Caution When recording playing back set the status in which Multi timer is not used set both SW1 3 and SW1 4 to ON If a timer interrupt occurs a voice overrun underrun error may occur 36 RTE V832 PC USER S MANUAL Rev 1 03 12 12 1 DEVELOPMENT OF APPLICATIONS USING MASKABLE INTERRUPTS This chapter describes the methods of developing an application on the RTE V832 PC by using a maskable interrupt and related restrictions INTERRUPT VECTOR The V832 interrupt vector area of addresses FFFF FEOOH to FF
19. 5 DEVELOPMENT OF APPLICATIONS USING MASKABLE INTERRUPTS 37 121 INTERRUPT VECTOR UN Ta E er e xh ras xxv v EE Y ea a e 37 12 2 INTERNAL INSTRUCTION RAM a a a a a A a r 38 12 8 GENERAL 5 8 38 12 4 RESTRICTIONS ON BREAK POINTS IN THE INTERRUPT HANDLING 39 APPENDIX A MULTI MONITOR namuna nza nananua nenne nasa nnn 40 139 5 BOARD SETTING oor Roe ERE ERE Ure Dia aee ea 40 13 1 1 RTE for Win 32 2 6500000000000000 0 40 ERAS ES A dd Eg E D HP 40 13 1 3 Connection of 4 00 00000000000000000000000 40 13 2 MULTI MONITOR 41 138 212 Monitor Work RAM ban a e e eat 41 13 2 2 Intefr pt iiis ido o ER E E t e od 41 13 2 3 Interrupt for Forced Break 2 41 41 13 25 H moite Connections 41 13 26 Monitor Execution Area iii ur aito ER 41 19 27 Special Instr clion d er EE Her d 41 13 3 RIE COMMANDS ii iride E vw 42 19 3 1 i kac tit AI ua Cice 42 ILE E BERANE 1N E EPET Matri eme dot keane 42 13 30 VER usui Hi c pede b ded 42 19 84 sINBOINEL INVM siet t esee de
20. 6 KB 2 234 MHz 34 9 KB 2 137 MHz 33 4 KB 2 048 MHz 32 0 KB 1 966 MHz 30 7 KB 1 890 MHz 29 5 KB 1 820 MHz 28 4 KB 1 755 MHz 27 4 1 695 MHz 26 5 KB 1 1 638 MHz 25 6 KB CIO CI oss ieee u PD63310 REGISTER 4580 1000H TO 4580 100FH The uPD63310 register is assigned as indicated below For details refer to the data sheet provided with the uPD63310 Wem 8 v s o 4580 1000H Address register Register number 4580 1008H Data register Gain control data 23 RTE V832 PC USER S MANUAL Rev 1 03 9 9 1 9 2 INTERRUPTS AND DMA This chapter describes the interrupts and DMA for the RTE V832 PC INTERRUPT INTPO INTPO2 TP TI ITP Remarks 1 All the interrupts except NMI are positive logical request signals 2 All the signals can be physically separated by using SW3 they are connected in the factory setting 3 All the interrupts from EXT BUS are inverted and connected to the V832 4 Two interrupts INTO INT1 can be generated by selecting interrupt requests from the interrupt sources listed below with the interrupt controller see Section 8 9 INTO is used for the system used with the monitor while INT1 is used for a user application Interrupt sources selectable by PIC Timer 0 mode 2 Serial CH 0 Host PCI communication Timer 1 mode 2 Serial CH 1 Parallel printer USING NMI This section describes the method of using NMI for transporting th
21. 8 0x20 INDACR mute outh 0x45800000 0 Stop command return 0 AudioPlay int addr int size Use replay processing DMAO 1 outh DMAO addr gt gt 16 outh DMAO addr DMA DSAOL outh DMAO AUDIO_DATA gt gt 16 DMA DDAOH outh DMAO AUDIO DATA DMA DDAOL size size 2 1 2 DMA transfer count outh DMAO 8 size gt gt 16 DMA DBCOH outh DMAO 10 size DMA DBCOL outh DMAO0 12 0 lt lt 12 DMA DCHCO TTYP DMARQ 1 10 Mem gt l 0 0 8 SAD Inc 2 6 DAD Fix 0 lt lt 5 DAL Low 0 4 DRL Low 1 lt lt 3 TM Demand l DS Half word 11 ya Enable outh 0x45800000 0x0001 Start replay while inh DMAO 12 amp 1 0 Wait for termination while inh 0x45800008 amp 0x10 0 Wait for FIFO empty outh 0x45800000 0 Replay termination 35 RTE V832 PC USER S MANUAL Rev 1 03 return 0 AudioRecord int addr int size Use record processing DMA1 outh DMA1 AUDIO DATA 16 DMA DSA1H outh DMA1 AUDIO DATA DMA DSA1L outh DMA1 addr 16 DMA DDA1H outh DMAl addr DMA DDA1L size size 2 1 2 DMA transfer count outh DMA1 8 size gt gt 16 DMA DBC1H outh DMAl 10 size DMA DBC1L outh DMA1 12 0 lt lt 12 DMA DCHC1 TTYP DMARQ
22. 8 8 8 uPD71054 4500 B000H TO 4500 19 8 9 INTERRUPT CONTROLLER PIC 4500 D000H TO 4500 018 20 RTE V832 PC USER S MANUAL Rev 1 03 10 11 12 13 8 10 AUDIO CONTROLLER AUDCNT 4580 0000H TO 4580 0010H 4580 2000H 21 8 11 uPD63310 REGISTER 4580 1000H TO 4580 100 23 INTERRUPTS 24 9 1 INTERRUBJT a d int eade tua 24 9 234 USING NN Milicia aaa x eaa HN ash 24 9 3 REQUEST 25 EXT BUS Ep DERE 26 1021 PINEARRANGEMBENT Ada 26 c kc IUE 27 10 3 CONNECTION OF DATA BUS 28 10 3 1 16 Bit Data Bus CPU 9 28 10 3 2 32 Bit Data Bus CPU with 832 2 00006000000000000000000 29 E YIN E rc T ACETUM 30 10 5 APPLICABLE 31 Oe NOTE S ON U SE 31 SOFTWARE EM EE 32 11 1 INITIALIZATION EEEE 32 11 2 LIBRARIES ii ete ei ded Data E 33 11 3 USING EIMERS A 34 1154 AUDIO OS 3
23. E PC series design the board so that it operates in 32 bit bus mode When 32 16BIT is low MWR2 and MWR3 are not asserted Instead MWRO and MWhR1 are asserted When 32 16BIT is low jumper D 15 0 and D 31 16 on the board connected to EXT BUS see Section 10 3 2 A1 is valid when the 32 16BIT signal is low Therefore A1 will not be output by future RTE PC series that do not support the 32 16BIT signal 3 The maximum access bus width in one cycle of the EXT BUS depends on the bus width of the data bus of the CPU This does not pose a problem to the V832 because it has a 32 bit data bus If a 16 bit CPU is used however the data size that can be accessed at any one time is limited to a maximum of 16 bits This must be taken into consideration when designing a general purpose board that is to be used with this bus 4 The DMA function will not be supported by all members of the RTEPC series in the future 27 RTE V832 PC 10 3 CONNECTION OF DATA BUS 10 3 1 16 Bit Data Bus CPU Reference Cycle EKT BUS Memory Space Access Address 4n 0 and or 4n 1 32 16Bit High EXT BUS DI31 161 User Board Cycle EXT BUS Space Access Address 4n 0 and or 4n 1 32 16Bit High EXT BUS DI31 161 User Board Cycle Flyby DMA 32 16Bit High EXT BUS DI31 161 User Board Cycle EXT BUS Memory Space Access Address 4n 0 and or 4n 1 32 16Bit Low EXT BUS DI31 161 User Board Cycle EXT BUS
24. FF FFFFH is fiked in the ROM and cannot be rewritten So for the NEC monitor an alternate vector area is allocated in the SRAM in a vector at addresses FFFF FEOOH to FFFF FFFFH an instruction for causing a branch to the alternate vector area is placed If for example an interrupt with exception code is generated the CPU interrupt function causes a branch to address FFFF FEOOH where an instruction for causing a branch to the corresponding alternate vector area is placed This means that by rewriting the alternate vector area in the same way as with the original vector area a branch to the user program interrupt handling routine can be caused when an interrupt is generated The difference from an ordinary V832 program is that a vector area is fixed in ROM and no rewriting by a program is required However a program running on the monitor must rewrite the alternate vector area to enable an interrupt With the monitor of the RTE V832 PC an alternate vector area is allocated at FE07 0000H to 07 01FFH in SRAM So for an interrupt with exception code FEOOH an instruction for causing a branch to the interrupt handling routine is to be written at address FE07 0000H for an interrupt with exception code FE10H an instruction for causing a branch to the interrupt handling routine is to be written at address FE07 0010H and so forth Moreover the V832 CPU contains cache memory so that the cache must be cleared after the vector is rewrit
25. JEXT connector PIN ABHANGEMENI INT3 DMAAK1 al lt EE ELE 9 EN 25 2 a X 4 49 53 57 6 69 73 S st es 89 93 97 Reserve a A11 DMARQ1 32 16BIT JEXT Pin Arrangement Signal name MWR3 READY 26 RTE V832 PC USER S MANUAL Rev 1 03 10 2 SIGNALS D 0 31 Input output Data bus signal connected to the CPU data bus signal via a buffer It is pulled up with 10 kQ resistor on the board A 1 23 Output Address bus signal connected to the CPU address signal via a buffer MRD Output Memory read cycle timing signal which becomes active only when the EXT BUS BR RAT space is accessed MWR 0 3 Output Memory write cycle timing signal MWRO corresponds to D 0 7 MWR1 to D 8 15 MWR2 to D 16 23 and MWR3 to D 24 31 This signal becomes lou Boa active only when the EXT BUS space is accessed Output Timing signal of the I O read cycle Asserted active when the EXT BUS space is RE adi accessed or in the flyby DMA cycle reference IOWR Output Timing signal of the I O write cycle Asserted active when the EXT BUS space is p accessed or in the flyby DMA cycle reference READY Input Signal for notifying the CPU of the end of a cycle It is valid for the EXT BUS space To have the CPU reliably recognize READY it is necessary to keep READY active until MRD MWR 0 3 IORD or IO
26. L16PIR552 Register Arrangement The XIN input of the TL16PIR552 is connected to the 22 1184 MHz clock Each interrupt of UART CH 0 UART CH 1 and PRINTER can be connected to the interrupts of the CPU via PIC The interrupt from PRINTER can be directly connected to INTP10 of the V832 via SW3 8 Interrupt source Connected CPU interrupt Interrupt edge PRINTER INTP10 Rising edge UART CH 0 is connected to the JSIO1 connector on the rear panel of the board UART CH 1 is connected to the JSIO2 connector and PRINTER is connected to JPRT UART CH 0 is used when the debugger is used in serial communication mode At this time INTP3 or NMI is used as the interrupt via PIC TL16PIR552 is reset when the system is reset 18 RTE V832 PC USER S MANUAL Rev 1 03 8 8 TIC uPD71054 4500 B000H TO 4500 B00CH The NEC uPD71054 is installed as a TIC The uPD71054 is compatible with the Intel i8254 It has three timers counters These timers counters are used to generate monitor timer interrupts Each register of the TIC is assigned as listed below 4500 B000H COUNTER 0 COUNTER 0 4500 B004H COUNTER COUNTER 4500 B008H COUNTER 2 COUNTER 2 4500 B00CH Control Word TIC Register Arrangement The channels of the TIC are connected as shown in the figure below Channel 0 is used as the interval timer for the monitor program Channels 1 and 2 can be used by a user program as necessary Channel 2 is connected to channel 1 by means of
27. Number Notation Rules MULTI is a trademark of Green Hills Software Inc in the US FUNCTIONS The overview of each function block of the RTE V832 PC is shown below 5 lt gt 83V Internal ONNECTOR Control Mini jack 3 RTE V832 PC Block Diagram RTE V832 PC MAJOR FEATURES USER S MANUAL Rev 1 03 Two types of monitor ROM are provided one is used for the Green Hills Multi and the other for the Midas PARTNER Real time execution and evaluation at a high level language level using Multi or PARTNER A ROM emulator can be connected 512K bytes of high speed SRAM and 32M bytes of SDRAM are provided as standard SRAM and DRAM can be evaluated in 16 bit bus mode Two serial interfaces and one printer interface are provided e Two timer channels are provided One channel is used for the monitor Two audio input channels and two audio output channels are provided 4 BASIC SPECIFICATIONS Processor CPU clock Bus clock Power consumption Memory SRAM DRAM Serial 2 ch Printer Audio input output 2 ch Timer port Others CPU connector 32 bit standard external extension bus Reset switch V832 142 8 MHz 47 6 MHz 5 V 2 128 64K x16 bits 40 pin DIP x 1 512K bytes max 512 128Kx8bitsx4 32 64 M SDRAM x 4 Equivalent to NS16550 10 pin header DB9 connector IEEE1284 compatible 26 pin header uPD63310 Mini jack MIC x 2 LINEO
28. RTE V832 PC USER S MANUAL Rev 1 04 RTE V832 PC USER S MANUAL Rev 1 04 Midas lab RTE V832 PC USER S MANUAL Rev 1 04 REVISION HISTORY Chapter Explanation of revision September 10 1998 102 Firstedition February 2 1999 Revised RFC set value The interrupt input from the printer of PIC is changed into the rising edge D 26 2 1 04 DAL p from high level The board of revision newer than Rev 2 1 corresponds RTE V832 PC USER S MANUAL Rev 1 03 CONTENTS 1 INTRODUCTION 1 1 1 NUMERIC NOTATION ss triste cid oett eet tbe d eto 1 A 1 3 MAJOR FEATURES 2 4 BASIC SPECIFICATIONS wwwemmusimimusi mwumini 2 5 BOARD 3 5 1 RESET SWITCH RESET 3 5 2 POWER JACK 8 53s SWT HANS WI ML La e a D LED ad 3 5 4 Pn 4 5 5 SWITCH 3 SVS so Mum Cre ie 4 5 6 4 WA 5 By BD ka sees Amo EA E 5 5 8 TEST PINS FOR ROM EMULATOR JROM EM 5 5 9 CLOCK BOBRETIOSOL A 6 5 10 ROM SOCKETS UG Ies aeos aces tacos 6 5 11 DMARQO 1 SEPARATION JUMPER 6 5 12 TIMER CLOCK FREQUENCY SELECT JUMPER
29. TOVER Lights when a time out occurs LED Indication Caution If PCI PERR and PCI9 DEAD light restart the system TEST PINS FOR ROM EMULATOR JROM EM Test pins JROM EMS are used to connect a ROM emulator They accept control signals from the ROM emulator The following table lists the signal names and functions related to each test pin Signal Function output RESET Input When a low level is supplied to this test pin the CPU is reset 1 A reset request signal from the ROM emulator is connected to the test pin The test pin is pulled up with 1 KQ NMI Input Whena low level is supplied to this test pin an NMI signal is given to the CPU This 2 signal can be masked by software so it is necessary to reset the mask See Section 8 9 An NMI request signal from the ROM emulator is connected to the test pin The test pin is pulled up with 1 GND This test pin is at a ground level The ground level of the ROM emulator is connected IE NEN EM Pin Functions RTE V832 PC USER S MANUAL Rev 1 03 5 9 5 10 5 11 5 12 5 13 CLOCK SOCKET 0 1 An oscillator for generating the clock signal to be supplied to the CPU is mounted in the OSC1 socket With the V832 a PLL is used to generate a system clock The frequency of the oscillator must be one sixth or one eighth the internal operating frequency of the V832 Accepts DIP 8 pin half type oscillators Caution When yo
30. USER S MANUAL Rev 1 03 This chapter describes the initialization of the hardware of the RTE V832 PC board and explains how to The boot routine initializes the bus controller built into the V832 for external memory or l O access as follows Bus clock 33 MHz Max mu ERN indicates the set value when e 1 BSIZE32 is ON 0 Pwco 000 0014 709 aftwod PWC 000 0016 400H halfword PO rafwod O Pei matwod soc co00 0020H MA matwod C000 0022H 0102H half word First time 33MHz gt gt 11 5 us DAA cooo 0084 00 4 bye Port select DMAContsig A select DMACont sig C000_00FA Eee Port B select INTPxx Bus clock 33 MHz Min A e EEES indicates the set value when A 1 BSIZE32 is ON 0 PWO 0000044 7200 hat wora S Pwcr 000 0016 halfwora PO 0000 0100 hafword E PO O00 102MH sc 941AH hafword C000 0022H 0104H halt word First ime 47 6MHz gt gt 13 4 us Ore cooooo4 byte PotA seletDMAContsg um a For detailed information about the registers refer to the manual provided with the V832 CPU 32 RTE V832 PC USER S MANUAL Rev 1
31. UT x 1 Equivalent to 18254 500 ns resolution LED 7 segment display switch input Connector with all function pins of the V832 connected RTE PC standard 32 bit interface 16M bytes 32 bit bus correspond to DMA Push type RTE V832 PC USER S MANUAL Rev 1 03 5 5 1 5 2 5 3 BOARD CONFIGURATION The physical layout of the major components on the RTE V832 PC board is shown below This chapter explains each component sooo gt JINA 1 3 JP5 JPA A os RTE V832 PC Components Layout RESET SWITCH RESET RESET is a reset switch for the entire board Pressing this switch causes all the circuits including the CPU to be reset POWER JACK JPOWER When this board is to be used as a standalone that is without being inserted in a PCI bus slot the board should be supplied with power from an external power supply by connecting it to the JPOWER connector The external power should be one rated as listed below Voltage 5V Current Maximum of 2 0 A excluding the current supplied to the JEXT connector Mating connector Type A 5 5 mm in diameter Polarity 5V GND D 45V Caution When attaching an external power supply to the board be careful about its connector polarity When inserting the board into the PCI bus slot do not attach the JPOWER connector to an external power supply It may result in a malfunction SWITCH 1 SW1 SW1 is a general purpose input port switch Whe
32. WR becomes inactive It is pulled up with a 10 kQ resistor on the board INT 0 3 Input Active low interrupt request signal Connected to the INTPO1 INTP11 INTP12 and INTP13 pins of the CPU respectively via SW3 after being buffered by the inverter It is pulled up by a 10 resistor on the board see Chapter 9 DMARQ O 1 Input Active low DMA request signals Connected to the DMARQ2 and DMARQS pins of the CPU via SWA after being buffered Pulled up by a 10 kO resistor on the board 0 1 Output Active low DMA acknowledge signals DMAAKO and DMAAK1 of the CPU are PUT uet nori vane ae Cep RESET Output Active low system reset signal 32 16BIT Input When this signal goes low only D 15 0 are used if the CPU is in the 16 bit data bus mode If the CPU is in the 32 bit data bus mode D 15 0 or D 31 16 are used as an address bus 16 bit bus mode When this signal goes high D 31 0 of the data bus are used 32 bit bus mode This signal must not be changed dynamically It is pulled up by a 10 kO resistor on the board Output _ Clock signal connected to the CLKOUT pin of the V832 after a buffer Reserve Reserved signal Connect nothing to this pin when the board uses EXT BUS JEXT Connector Signals Cautions 1 The 32 16BIT signal will not be supported by all the products of the RTE PC series in the future If it is planned to use the board connected to EXT BUS with a new member of the RT
33. XT BUS is connected to multiple boards use a cable to make a daisy chain connection 10 6 EXT BUS connector KEL 8830 100 170 Applicable connector for board KEL 8802 100 170S Applicable connector for cable KEL 8825E 100 175 Right angle for cable for board KEL 8830E 100 170L KEL 8831E 100 170L NOTES ON USE The following points must be noted when designing the board that is to be connected to EXT BUS 1 When two or more boards are connected to EXT BUS Hi Z control must be performed so that the READY signal is driven only when a board is selected T7 and T16 must be satisfied to insert a wait state into the cycles of EXT BUS To do so control with the normal not ready technique that retains the not ready status normally and returns ready when an access takes place and the slave device is ready is recommended When executing a DMA cycle in single transfer mode T19 in the timing chart must be satisfied if the next DMA cycle is not to be generated However T19 differs among the products because it is heavily dependent upon the specifications of the DMA controller Because there is not an enough space to access the 16M byte I O space of EXT BUS with RTE V832 PC the high order two bits A23 and A22 are accessed by the outputs from the EXT IO high order address setting register 1 port For details of this port see Section 8 6 31 RTE V832 PC 11 11 1 SOFTWARE use peripheral devices INITIALIZATION
34. cere oes ER da 42 13 3 5 QUTB QUTH QUT Lo teo eee gute te Tee do Eds 43 13 30 DCTR Gommand 5 ui cmt ee erai tre a E 43 RTE V832 PC USER S MANUAL Rev 1 03 1226 AG TR Command tede akin 43 13 38 PEECGR Command ii tO D eH Pci o ed dre pea badge 43 18 38 94 GMGR Gommand s HM tbe ty esie eaae acids 43 13 3 10 SEA COMMAN OG iii ii pere tg de td dubbed bt t 43 14 APPENDIX PARTNER MONITOR nasa nasa 44 14 1 BOARD se sre sen 44 E ES ES A e a 44 142 PARTNER MONITOR 22 Re fe c dao Ev aes 45 14 2 1 Monitor Work RAM 2 1 0 100066000000000000000 nnn nennen sers ase rn na nan 45 14 2 2 A RUE ee ee 45 14 2 3 Interrupt for Forced Break sss 45 re SP A i e RR aad dee ene es es 45 14 25 e RR e reta a Pe pa Pea ba Rr 45 14 2 6 Monitor Execution 1 0 6 660000 000000000000 45 14 2 7 Special Instruction cete nee ee 45 RTE V832 PC USER S MANUAL Rev 1 03 1 1 2 INTRODUCTION The RTEV832 PC is an evaluation board conforming to the PCI bus interface that is designed to evaluate the NEC V832 RISC processor This board can be inserted into the PCI slot of a DOS V c
35. e monitor for example to the board NMI is edge detected NMI can be masked by hardware because the interrupt source is a level output For an explanation of masking see the description of the INTEN register in Section 8 9 The following procedure applies when an NMI occurs lt 1 gt Set the NMIEN of the PIC to 0 to mask the NMI by hardware lt 2 gt Check the INTR of the PIC lt 3 gt Perform NMI processing for the interrupt source and clear the request 4 Resetthe NMIEN of the PIC to 1 to reset the mask 5 Return from NMI processing Caution When data is written to a register related to INTO of NMI and PIC the monitor may hang up RTE V832 PC USER S MANUAL Rev 1 03 9 3 DMAREQUEST CHO Replay request A DMA request for data to be written to the audio data buffer during replay A timeout results in an underrun error Recording request A DMA request for data to be read from the audio data buffer during recording A timeout results in an overflow error DMARQO request from EXT BUS DMARQ1 request from EXT BUS Remarks 1 Set DMARQ AK 3 0 to negative logic 2 CHO and CH1 JP1 and CH2 and CH3 can be physically separated by using SWA they are connected in the factory setting 25 RTE V832 PC 10 10 1 EKT BUS USER S MANUAL Rev 1 03 The JEXT connector is a connector for the EXT BUS provided to extend the memory or I O The local bus of this board is connected to the
36. e serial controller TL16PIR552PH JSIO1 is a 9 pin D SUB RS 232C connector like that commonly used on the PC AT while JSIO2 is a pin plug type connector with a pitch of 2 54 mm All signals on both of these connectors are converted to the RS 232C level The figures and table below indicate the pin and signal arrangements of these connectors For the signals to be connected to the host the table indicates two modes of wiring on the host one for a 9 pin D SUB connector and the other for a 25 pin D SUB connector Regular cross cable wiring is used for these connections The pin arrangement of JSIO2 will be identical to that of JSIO1 when a push fit connector is used with a ribbon cable JSIO1 Pin Arrangement Male JSIO2 Pin Arrangement JSIO1 JSIO2 Input Connector pin number on the host side Signal name No pin No output D SUB9 D SUB25 A A a a mom mu 3 2 3 0 80 Output A 4 rr Output eei omes ma 4 2 mens opt 8 s orses wma 7 m w wc 1 JSIO1 and JSIO2 Connector Signals RTE V832 PC USER S MANUAL Rev 1 03 5 15 PARALLEL CONNECTOR JPRT The JPRT connector is used for parallel communication controlled by the parallel printer controller TL16PIR552PH JPRT is a pin plug type connector with a 2 54 mm pitch All signals on the connector are 5V level signals The figure and table below i
37. et value Overflow interrupt upon replay Disable Reset value Recording operation 0 Reset value Underflow interrupt upon recording o Disable Reset value Overflow interrupt upon recording 0 Disable Reset value RTE V832 PC The STATUS register is a read only register for indicating various statuses Replay status 0 Stopped Being conducted Overflow upon replay 0 No overflow detected Overflow detected Underflow upon replay 00 No underflow detected Underflow detected Data buffer status for replay 1 Full buffer write disabled Recording status o Stopped Being conducted Overflow upon recording 0 No overflow detected Overflow detected Underflow upon recording No underflow detected Underflow detected Data buffer status for recording 1 buffer read disabled USER S MANUAL Rev 1 03 22 RTE V832 PC USER S MANUAL Rev 1 03 8 11 The MCLKDIV register is used to determine the MCLK frequency MCLK Sampling frequenc Bytes sec lojal CARNE 9 830 MHz 153 6 KB 8 192 MHz 128 0 KB 7 022 MHz 109 7 KB 6 144 MHz 96 0 KB 5 461 MHz 85 3 KB 4 915 MHz 76 8 KB 4 468 MHz 69 8 KB 4 096 MHz 64 0 KB 3 780 MHz 59 1 KB 3 511 MHz 54 9 KB 3 277 MHz 51 2 KB 3 072 MHz 48 0 KB 2 891 MHz 45 2 KB 2 731 MHz 42 7 KB 2 587 MHz 40 4 KB 2 458 MHz 38 4 KB 2 341 MHz 36
38. factory installed ROM SW1 is used as shown below ON 115200 baud 38400 baud 19200 baud 9600 baud Factory set Baud Rate Setting Always use this switch in this status Factory set Debug mode Setting ON 7 segment LED used by the monitor OFF Normal use state Factory set Debug Mode Setting Setting ON INTP3 used Factory set OFF NMI used Break Interrupt Setting SW1 7 and SW1 8 are not used 44 RTE V832 PC USER S MANUAL Rev 1 03 14 2 PARTNER MONITOR 14 2 1 14 2 2 14 2 3 14 2 4 14 2 5 14 2 6 14 2 7 Monitor Work RAM The monitor uses the first 64K bytes area in the SRAM as work RAM In other words user programs are not allowed to use logical addresses 07 0000 to FEO7 FFFFH Interrupt When using an interrupt with a user program see Chapter 12 Interrupt for Forced Break NMI or can be selected as an interrupt to be used by the monitor for communications and a forced break the ESC button INTPOS is to be selected when a program using the DMA is used for audio input output for example In other cases the use of NMI is recommended The differences between the two interrupts are listed below When is used A break can occur at any time during user program execution If however a break occurs during DMA operation the DMA is also terminated The DMA does not restart even upon reexecution When INTPOS is used No break will occur if the user
39. h order address setting register 4500 through 6000H to specify the high order address The relation between the address and the I O space that can be accessed is shown below Set value of EXT IO high order space of EXT BUS that be accessed by address setting register A23 A22 4540 0000H through 457F FFFFH 00 0000H to 3F FFFFH 0 1 40 0000H to 7F FFFFH 1 0 80 0000H to BF FFFFH 1 1 C0 0000H to FF FFFFH 15 RTE V832 PC USER S MANUAL Rev 1 03 8 2 8 3 8 4 DIPSW2 READ PORT 4500 0000H READ ONLY This port is used to read the status of DIP SW2 The data format of this port is shown in the table below Data bus tabs Logical address Ea bz Ds os D4 os pz Di Di Do 4500 0000H sw2 sw2 sw2 sw2 sw2 sw2 sw2 sw2 0 ON input 8 7 6 5 4 3 2 1 1 OFF Setting Hardware allocation BNK_ BNK ROM ROM PT CPU BCLK BSIZE MODE MODE TYPE PRT CVODE 32 1 0 1 0 EN SW2 1 corresponds to bit 1 of SW2 and SW2 8 corresponds to bit 8 of SW2 When a bit of the corresponding switch is set to ON 0 is read when it is set to OFF 1 is read SW2 is mainly used to set the hardware environment For how to set this switch see Section 5 4 DIPSW1 READ PORT 4500 1000H READ ONLY This port is used to read the status of DIP SW1 The table below indicates the data format Data bus E A 227 227 Logical address Setting
40. hine operates normally Start the debugger on the host machine and connect it via the PCI bus If an error occurs check whether the board is correctly mounted and whether the software has been correctly installed 12 RTE V832 PC USER S MANUAL Rev 1 03 7 HARDWARE REFERENCES This chapter describes the hardware of the RTE V832 PC 7 1 MEMORY AND I O The figure below shows the memory and l O mapping on the board 0000 0000 4000 0000 8000 0000 C000 0000 Internal data RAM Cacheable area Cacheable area Cacheable area EPROM mem area 4F80 0000 4FFF FFFF 7 CS space i FF80 0000 SRAM mem area CS6 space 4E00 0000 4E07 FFFF FE00 0000 FE07 FFFF E SYTEM IO area CSS space AUDIO toro d 4500 0000 45FF FFFF E e E EXF Mem mem area CS4 space EXT Mem B 4 4400 0000 44FF FFFF Free area CS3 space PoI ty Ai 4200 0000 427F FFFF CS2 space Q R 00 0000 CS1 space SDRAM DRAM mem area 0000 0000 01FF FFFF 4000 0000 41FF FFFF CS0 space SDRAM Memory and l O Mapping RTE V832 PC USER S MANUAL Rev 1 03 CSO space 000 000 to xOFF FFFF x800 000 to x8FF FFFF SDRAM of 16M bytes is mapped Both the 16 bit and 32 bit data bus widths can be specified by using SW2 1 However the memory capacity is limited to 8M bytes when the 16 bit width is selected
41. itch for general purpose input ports For the Multi monitor in the factory installed ROM SW1 is used as shown below ON used ON 38400 baud OFF 19200 baud OFF 9600 baud Factory set Baud Rate Setting ON Timer is not used 200 Hz 5ms 100 Hz 10 ms OFF 60Hz 16 67 ms Factory set Profiler Period Setting Debug mode Setting ON 7 segment LED used by the monitor OFF Normal use state Factory set Debug Mode Setting Setting ON INTP3 used Factory set OFF NMI used Break Interrupt Setting SW1 7 SW1 8 are not used with the Multi monitor 13 1 3 Connection of Board Connect the board to the PC by using either the serial or PCI bus by referring to Chapter 6 40 RTE V832 PC USER S MANUAL Rev 1 03 13 2 MULTI MONITOR 13 2 1 13 2 2 13 2 3 13 2 4 13 2 5 13 2 6 13 2 7 Monitor Work RAM The monitor uses the first 64K bytes area in the SRAM as work RAM In other words user programs are not allowed to use logical addresses 07 0000 to FEQ7 FFFFH Interrupt When using an interrupt with a user program see Chapter 12 Interrupt for Forced Break NMI or can be selected as an interrupt to be used by the monitor for a communication forced break the Halt button for the Multi debugger or a timer such as profiler INTPO3 is to be selected when a program using the DMA is used for audio input output for example In other cases the use of
42. its the contents of at least one register must be destroyed or a branch relay point must be created to cause a branch to the interrupt handling routine 3 An alternate vector area is protected as a ROM monitor management area so that the area cannot be rewritten by downloading a program The user may consider the use of the following method that is a vector area is defined as an independent section in the source program and such an area is assigned as an alternate vector area by a link time parameter This method cannot be used however because downloading will invariably fail 4 Immediately after rewriting an alternate vector area always flush the cache memory in the CPU Otherwise a vector existing before alternate vector rewriting may be used 5 All peripherals including interruptrelated peripherals can be initialized only with the reset switch on the board This means that if after a program is executed another program is loaded the peripherals will still be in the statuses set by the previous program So use the procedure below when after executing a program that uses a peripheral another program is to be loaded and executed 1 Forresetting press the reset switch of the RTE V832 PC 2 Load and execute another program 6 Before setting the El interrupt enable state set the DI interrupt disable state at the start of program execution then set the peripherals and vectors 38 RTE V832 PC USER S MANUAL Rev 1
43. latch Count of timer 1 Count of timer 2 Start count value Stop count value Seconds 34 RTE V832 PC USER S MANUAL Rev 1 03 11 4 AUDIO A sample program using the audio input output interface mounted on the board is indicated below For data input output the DMA built into the V832 is used Audio input output sample define DMAO 0xC0000030 Built in DMA 0 replay define 0xC0000040 Built in DMA ch1 recording define AUDIO DATA 0x45802000 Audio data FIFO static Set63310Reg int reg int data Set uPD63310 register 1 outb 0x45801000 reg Write address register outb 0x45801008 data Write data register return 0 static Get63310Reg int reg Acquire uPD63310 register 1 outb 0x45801000 reg Write address register return inb 0x45801008 8 0x3F Read data register 6 bits AudioInit Audio initialization outh 0x45800000 0x8000 Reset audio outh 0x45800010 8 fs 12 kHz inh 0x45800010 Dummy read outh 0x45800000 0 Reset clear Set63310Reg 0 0 IN1L Odb Set63310Reg 1 0 INTR Odb Set63310Reg 17 0 OUTDACL Odb Set63310Reg 18 0 OUTDACR 0db return 0 AudioTerm Audio termination processing 1 Set63310Reg 0 0x20 IN1L mute Set63310Reg 1 0x20 IN1R mute Set63310Reg 17 0x20 INDACL mute Set63310Reg 1
44. measurements may have a larger error To prevent this from occurring select the uncacheable area The use of the cacheable area is factory set with SW2 8 on Special Instruction The monitor uses the following instruction for single step breakpoint and system call functions BRKPNT instruction 0x6cxx Do not use a code that may be interpreted as a break instruction in the user program 41 RTE V832 PC USER S MANUAL Rev 1 03 13 3 RTE COMMANDS When the monitor and server are connected the TARGET window is opened The RTE commands can be issued in this window The following table lists the RTE commands HELP Displays help messages INT Displays the version number INB INH or INW read OUTB OUTH OUTW DCTR ICTR PLLCR Changes or displays the internal registers CMCR Displays or sets the internal 1 0 RTE Commands Some commands require parameters All numeric parameters such as addresses and data are assumed to be hexadecimal numbers The following numeric representations are invalid 0 1234 1234 1234 13 3 1 HELP Format HELP command name Displays a list of RTE commands and their formats A question mark can also be used in place of the character string HELP If no command name is specified in the parameter part the HELP command lists all usable commands Example HELP SFR Displays help messages for the SFR command 13 3 2 INIT Format INIT Initializes the RTE environment
45. n the monitor is used all SW1 switches except some are already set When the port is read a switch being set to OFF represents 1 while its being set to ON represents 0 Set this switch for assignment with the monitor by referring to the following sections and in accordance with your environment When using Multi see Section 13 1 2 When using PARTNER see Section 14 1 1 RTE V832 PC USER S MANUAL Rev 1 03 5 4 5 5 SWITCH 2 SW2 SW2 sets the H W status of this board All the bits of this switch can be read by software When this switch is read from a port OFF indicates 1 and ON indicates 0 For details see Section 8 2 1 BSIZE16 Specifies bus size of SRAM and SDRAM 32 bits factory setting ON 16 bits 2 BCLK HI Specifies frequency of bus clock Frequency exceeding 33 MHz factory setting ON Frequency less than 38 MHz 3 CMODE Directly connected to CMODE pin of CPU OFF Multiplied by 8 ON Multiplied by 6 factory setting TEST Mustalways be OFF ROM TYPEO jSpecifies the type of ROM to be used ROM TYPE1 ROM TYPE1 ROM TYPEO When monitor ROM is used factory setting OFF ON When 27C4096 is used ON OFF When 27C2048 is used ON ON When 27C1024 is used 7 BNK DIS Specifies whether the upper and lower halves banks of ROM are separated Upper and lower halves of ROM separated factory setting ON Upper and lower halves of ROM are used as a contiguous area LOW
46. ndicate the pin and signal arrangements of the connector The pin arrangement of JPRT will be identical to that of the 25 pin D SUB connector like that commonly used on the PC AT when a push fit connector is used with a ribbon cable a mgBiutkiiidiizaua HHH M7 NN JPRT Pin Arrangement A Y AUTO FD JPRT Connector Signals 5 16 AUDIO MINI JACKS JIN R JIN L JLINEOUT Audio jacks are provided for two monaural microphone or line input channels and one stereo output channel The input output conditions of these jacks are indicated below JIN R JIN L Electrical input condition When MIC input is specified 140 mVp p Internal amplification About 20 dB When LINE input is specified 1 4 Vp p Physical shape of mating plug Monaural mini plug 43 5 x 2 channels JLINEOUT Electrical output condition 1 4 Vp p Physical shape of mating plug Stereo mini plug 48 5 x 1 channel Supplement Selection between MIC and LINE is performed by setting JP3 JP4 JP5 and JP6 RTE V832 PC USER S MANUAL Rev 1 03 5 17 DEBUGGING CONNECTOR JDCU The JDCU connector is used to connect a debug tool based on the debug function built into the V832 On board connector 8830E 026 170S manufactured by KEL LL JDCU Connector Signals RTE V832 PC USER S MANUAL Rev 1 03 5 18 CPU CONNECTOR JCPU 1 JCPU 2 The CPU connector signals are connected directly to the V832 Many signals are used on the board
47. ompatible machine The board features a V832 capable of operating at a maximum speed of 143 MHz memory serial and parallel interfaces and inputs outputs such as audio inputs outputs As the memories a high speed SRAM and high capacity SDRAM are provided as standard The SDRAM is controlled by using the internal memory controller of the V832 These functions enable the RTE V832 PC to be used for a wide variety of applications including processor performance evaluation and application program development at the initial stage and to also be used as an engine for demonstration and simulation The GHS Multi or Midas PARTNER source evel debugger can be used as a development software tool with the RTE V832 PC The type of monitor to be stored in ROM depends on the debugger type In ROM the monitor specified at the time of purchase is stored Even when neither of the debuggers is purchased together with the RTE V832 PC they can be purchased at anytime subsequently NUMERIC NOTATION This manual represents numbers according to the notation described in the following table Hexadecimal and binary numbers are hyphenated at every four digits if they are difficult to read because of many digits being in each number Only numerals are indicated 10 represents number 10 in decimal Hexa decimal A number is suffixed with letter H 10H represents number 16 in decimal number A number is suffixed with letter B 10B represents number 2 in decimal
48. or RS 232C cable connection and the power supply respectively Set and check the setting of DIPSW on the board Specify a baud rate by using SW1 see Sections 13 1 2 and 14 1 1 Connect the JSIO1 connector and host machine with the RS 232C cable and supply power to the JPOWER connector Confirm that the POWER LED on the board lights If the LED does not light turn off the power immediately and check the connection Start the debugger on the host machine and connect it via the RS 232C interface If an error occurs confirm the setting of the serial cable and switches especially the baud rate Cautions When power is applied to the board while the board is not connected to the PCI bus also connect the supplied PCI bus terminator board 2 Place the board on an insulating material If a conductive material touches the board while power is supplied to the board the board may malfunction INSERTING INTO PCI SLOT PCI BUS CONNECTION Insert the board into the PCI slot of the host PC by means of the following procedure 1 c2 3 4 Set and check the DIPSW on the board Open the housing of the PC and insert the board into the PCI slot Confirm that the board is securely mounted and fix the back panel with a screw Turn on the power to the PC and check that the POWER LED on the board lights If the LED does not light turn off the PC power immediately and check the connection Also confirm that the host mac
49. ten Otherwise an instruction may be executed before rewriting A sample program for alternate vector rewriting is given below when the relative address from the interrupt handling routine to an alternate vector area is within 26 bits VECT CPU Oxfffffe00 Start of CPU interrupt vector VECT RAM 0 070000 Start of alternate interrupt vector define VECT n VECT CPU n VECT RAM Find interrupt vector address main extern void interrupt IntEntry Interrupt handling routine int addr offs inst Allocation of alternate vector address for Oxfffffe30 of CPU vector and creation of JR dest26 instruction for branching to interrupt handling routine addr VECT Oxfffffe30 offs int IntEntry addr inst 0xa8000000 offs amp Ox3fffffe 32 bit instruction JR dest26 Vector replacement di Interrupt disable __asm di unsigned short addr 0 inst gt gt 16 6 Oxffff Higher 16 bit code unsigned short addr 2 inst amp Oxffff Lower 16 bit code outw OxFFFFFFF4 3 Clear cache Interrupt device initialization etc Interrupt enable __asm ei 37 RTE V832 PC USER S MANUAL Rev 1 03 12 2 12 3 INTERNAL INSTRUCTION RAM With the V832 a maskable interrupt vector can be placed in the internal RAM IHA bit of the HCCW system register When this function is used the vec
50. the ROM area is required for successive accesses to the external timer Sample execution time measurement using timers 2000000 TIMERCLK 10 1000 char Ox4FFF0000 define TIMERCLK define INTERVAL define IOWAIT InitTimer outb 0x4500B00C 0x74 outb 0x4500B004 INTERVAL outb 0x4500B004 INTERVAL 256 outb 0x4500B00C OXBO outb 0x4500B008 OxFF outb 0x4500B008 OxFF return 0 IOWAIT IOWAIT IOWAIT IOWAIT IOWAIT IOWAIT LatchTimer int countl count2 counts outb 0x4500B00C OxDC countl inb 0x4500B004 countl inb 0x4500B004 256 count2 inb 0x4500B008 count2 inb 0x4500B008 256 counts INTERVAL OxFFFF count2 INTERVAL count1 return counts IOWAIT IOWAIT IOWAIT IOWAIT IOWAIT double total_time main 1 int start count stop count InitTimer start count LatchTimer func LatchTimer double stop count start count double TIMERCLK stop_count total_time return 0 include lt time h gt func Time measurement routine 2MHz 10 ms 1 100 For command recovery Timer initialization Timer 1 set to mode 2 Lower digit count of timer 1 Higher digit count of timer 1 Timer 2 set to mode 0 Lower digit count of timer 2 Higher digit count of timer 2 Count Latch Timer 1 2 multiple
51. tor setting reguirement does not differ between an ordinary V832 program and a program using the monitor on the RTE V832 PC For an explanation of the method of vector usage with the internal instruction RAM and that of modifying the contents of the internal instruction RAM refer to the manual provided with the CPU When a program is placed in the internal instruction RAM for purposes including interrupt handling the user is required to pay careful attention to the compiled object codes For the switch case statement of C in particular a jump table is created in the instruction code and a code for causing a branch by referencing the table may be generated Such a reference to the table is made with the LD instruction However the internal instruction RAM cannot be referenced by the LD instruction so that the program may perform an unpredictable operation GENERAL RESTRICTIONS NOTES This section describes restrictions and notes relating to the debugging of an application using a maskable interrupt 1 If an interrupt is generated before alternate vector setting or if an interrupt is generated with other than a valid alternate vector set a break occurs at the point where the interrupt is generated This is because the initial value of the alternate vector is an instruction for causing a branch to the break handling routine of the monitor ROM 2 If the relative address from an alternate vector area to the interrupt handling routine exceeds 26 b
52. u have to cut an oscillator pin for convenience be careful not to cut it too short or otherwise the frame housing of the oscillator may touch a tine in the socket resulting in a short circuit occurring ROM SOCKETS The RTE V832 PC has ROM sockets to hold 40 pin ROM chips to provide standard 128K bytes 64K x 16 bits When the ROM chips used here are to be replaced their type should be 27C1024 27C2048 or 27C4096 and the access time should be 120 ns or less SW2 may need to be set according to the type and purpose of the ROM chips to be used For details see Section 5 4 DMARQO DMARQ1 SEPARATION JUMPER JP1 JP1 is a jumper that physically cuts off DMARQO and DMARQt used for Audio data transfer from the V832 Usually jumper 1 2 and 4 Remark If this jumper is opened Audio data cannot be transferred by means of DMA TIMER CLOCK FREQUENCY SELECT JUMPER JP2 JP2 is used to select which of two clocks is to be supplied to the timers 1 2 that can be used by applications 1 2 2 MHz factory set 3 4 4 MHz 5 6 8 MHz AUDIO INPUT LEVEL SELECT JUMPERS JP3 JP4 JP5 JP6 These jumpers are used to select the input level of Audio Set these jumpers as shown below depending on whether MIC or LINE is used MIC is the factory setting RTE V832 PC USER S MANUAL Rev 1 03 5 14 SERIAL CONNECTOR JSIO1 JSIO2 The JSIO1 and JSIO2 connectors are used for the RS 232C interface that is controlled by th
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