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S3C2440 data sheet

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1. 10 10 53 2440 MICROCONTROLLER XXV List of Figures continued Figure Title Page Number Number 11 1 UART Block Diagram with 11 2 11 2 WARTARG ubere 11 4 11 3 Example showing UART Receiving 5 Characters with 2 Errors 11 6 11 4 IrDA Function Block 11 8 11 5 Serial Frame Timing Diagram Normal UART essem 11 9 11 6 Infrared Transmit Mode Frame Timing 11 9 11 7 Infrared Receive Mode Frame Timing 11 9 11 8 nCTS and Delta CTS Timing menn 11 19 12 1 USB Host Controller Block 12 1 13 1 USB Device Controller Block 13 2 14 1 Interrupt Process DIAG 2 2 14 1 14 2 Priority Generating BIOCK 14 5 15 1 LCD Controller Block Diagram nene 15 3 15 2 Monochrome Display Types 56 15 12 15 3 Color Display Types ne ete eg Hee 15 13 15 4 8 bit Single Scan Display Type STN LCD
2. some sem some oswmws some som WW oswmus oswwwc sopor n eoio eman comer soos sea sts orm oswmm R soms w oswwo saa 1 38 ELECTRONICS 53 2440 RISC MICROPROCESSOR PRODUCT OVERVIEW Table 1 4 S3C2440A Special Registers Sheet 14 of 14 Continued cwm at cee Name B Endian L Endian Write osso R global status register codec command stat AC_PCMADDR 0x5B000010 AC97 PCM out in channel FIFO address register AC_MICADDR 0x5B000014 AC97 mic in channel FIFO address register AC_PCMDATA 0x5B000018 R W AC97 PCM out in channel FIFO data register AC_MICDATA 0x5B00001C AC97 MIC in channel FIFO data register Cautions on S3C2440A Special Registers 1 the little endian mode 4 endian address must be used In the big endian mode endian address must be used The special registers have to be accessed for each recommended access unit All registers except A
3. ukata ks 4 24 m kuna a aaa a 4 24 EXAIMPlOS sis m 4 25 Format 11 SP Relative Load Store l ya A EA qas kamas EET nn nnne 4 26 Giorn 4 26 Instruction 225 4 27 D EE 4 27 Format 12 10 ee i 4 28 Gor Iro 4 28 serenus iem A 4 29 HE 4 29 Format 13 Add Offset to Stack PONTE awanapaq 4 30 4 30 Instruction Cycle 4 30 erepto decer h Samasqa kanal de faeta 4 30 53 2440 MICROCONTROLLER Table of ContentS continued Chapter 4 Thumb Instruction Set Continued Formar 14 PUSH FOD Registers S mA Ei DR e 4 31 OPS 4 31 INStruction Cycle Jur Em 4 32 EXAMES gt lt E 4 32 Format 15 Multiple Eoad Store 4 33 4 33 Instruction Cycle TIMES 4 33 Exampl6S 4 33 Format 16 Gonditional Brati
4. ucosaDon Ys ra buter san adis ae afr sian adress 1 0 3 St val sce acess uuo Semap O STN gon oopis STN te top 00 _ mea www 00000 ouo 1 Ye erupt source oaos TCONSEL TCON LPC3600 CC3600 control ELECTRONICS 1 29 PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR Table 1 4 S3C2440A Special Registers Sheet 5 of 14 Continued Register Address Address Read Name B Endian L Endian Write NN ouo NFADDR oaeo t mewecco NANO fash main area ECO fash main area ECG weecc NAND fash spare area ECC NANO fash operation satus NAND fash EC status ororo NAND fash ECC status 0054 flash main area ECOO status mewecci oeoo _ NANO fash main area E001 sas NAND fash area ECC
5. SDI Special SDI Control Register SDI Baud Rate Prescaler Register SDIPRE a a SDI Command Argument Register 5 SDI Command Control Register SDICmdCon SDI Command Status Register SDICmdSta a SDI Response Register 0 SDIRSP0 a ene nnne SDI Response Register 1 SDIRSP1 a a SDI Response Register 2 SDIRSP2 a SDI Response Register SDIRSP3 a SDI Data Busy Timer Register 5 SDI Block Size Register SDIBSize a aa SDI Data Control Register SDIDatCon SDI Data Remain Counter Register ADIDatCnt a a SDI Data Status Register ADIDatSta a a a SDI FIFO Status Register SDIFSTA a a SDI Interrupt Mask Register 5 SDI Data Register SDIDAT A aaa susya Chapter 20 IIC Bus Interface s
6. 22230 320183 E Table 27 17 USB Electrical Specifications Vpp 1 2 V 0 05 V T4 40 to 85 C 3 3V 0 3V Parameter Symbol Condition Min Unit Supply Current Leakage Curent YY Leakage Current ICI OV lt VIN lt 33V Input Levels Differential input sensitivity D D DiWeentarcommonmoderange VOM vorran ___ 25 _ Single ended vse ___________ 20 Output Levels Smowmukw vo _ V Statio von 28 Capacitance 27 40 ELECTRONICS 53 2440 RISC MICROPROCESSOR ELECTRICAL DATA Table 27 18 USB Full Speed Output Buffer Electrical Characteristics Vpp 1 2 V 0 05 V TA 40 to 85 3 3V 0 3V Parameter Symbol Min Mex Unit Driver Characteristics Transition time Rise time CL 50pF 4 0 20 Fall time CL 50pF 4 0 20 Rise Fall time matching TR 9 111 1 Ex Drive output resistance Steady state drive Table 27 19 USB Low Speed Output Buffer Electrical Characteristics Vpp 1 2 V 0 05 V TA 40 to 85 C 3 3V 0 3V Parameter Symbol Condition Min Mex Unit Driver Characteristics Rising time CL 50pF CL sas
7. DCLK Control Registers aus y ayauya EXTINTn External Interrupt Control Register EINTFLTn External Interrupt Filter Register n Hmmm EINTMASK External Interrupt Mask EINTPEND External Interrupt Pending Register en GSTATUSn General Status m emen nene DSCn Drive Strength Control a a nennen nennen a DSCn Drive Strength MSLCON Memory Sleep Control Register mme S3C2440A MICROCONTROLLER xi Table of Contents Continued Chapter 10 Basic Timer Xii er Bs 10 1 eret Co Ert d EEUU Menace 10 1 PWM Timer Operatiori er ee Eee eee ep 10 3 Prescaler amp e e teet eme ter ahh Sh 10 3 cede dde eva ide vd doe o e gea e E Lig deudas 10 3 Auto Reload amp Double 10 4 Timer Initialization Using Manual Update Bit and Inverter 22 20 220
8. P 1H Horizontal O width CAMPCLK 8 bit mode CAMDATA po AY ACAYACAYACAJAYAGAYACA Figure 23 2 ITU R 601 Input Timing Diagram CAMPCLK CAMDATA 7 0 Video timing Video timing reference reference codes codes Figure 23 3 ITU R BT 656 Input Timing Diagram There are two timing reference signals in ITU R BT 656 format one is at the beginning of each video data block start of active video SAV and other is at the end of each video data block end of active video EAV as shown in Figure 23 3 and Table 23 2 ELECTRONICS 23 3 53 2440 RISC MICROPROCESSOR CAMERA INTERFACE Table 23 2 Video Timing Reference Codes of ITU 656 Format Data Bit Number 9 MSB For compatibility with existing 8 bit interfaces the values of bits D1 and DO are not defined F 0 during field 1 1 during field 2 V 0 elsewhere 1 during field blanking 0 in SAV Start of Active Video 1 in EAV End of Active Video PO P1 P2 protection bit Camera interface logic can catch the video sync bits like H SAV EAV and V Frame Sync after reserved data as FF 00 00 NOTE All external camera interface 105 are recommended to be Schmitt trigger type 10 for noise reduction 23 4 ELECTRONICS 53 2440 RISC MICROPROCESSOR CAMERA INTERFACE CAMERA INTERFACE OPERATION TWO DMA PATHS CAMIF has 2 paths P path Preview p
9. Sa 2 15 ule Emm 2 15 53 2440 MICROCONTROLLER Table of ContentS continued Chapter 3 ARM Instruction Set Instr ction SUMMAY ei eoe ed ca ae EL ed ad 3 1 Format SUMM y eret b eibi De ie o DEBERE ERI 3 1 s VINEIS EE 3 2 The Condition Field yc oci peti etie 3 4 ee reet Gane tw ne ux Age tous 3 5 INStruction nive ec m 3 5 Assembler Syntax te arde Lebe 3 5 Using R Toas an e 3 5 Branch and Branch with Lmk 1B Bl coton Sunq nem t aa reta ua 3 7 41 14 19 ra aya uma ua Cana 3 7 Instruction Cycle Led nn 3 7 Assembler Syritax iie eet eta ie tpm 3 8 Data M 3 9 91971061 E e 3 11 3 12 Immediate Operand Rotate AA asas 3 16 Writing EE 3 16 Using R15 as an Operandgy 3 16 Cmn ODC6d68 er igh tod tel Bax RAS RR COH EH ERA PLATA CORR AA 3 16 Inst
10. V 4 33 4 17 Format 4 34 4 18 4 36 4 19 astu 4 37 4 20 Format I MCI 4 38 5 1 S3C2440A Memory after 5 2 5 2 S3C2440A External nWAIT Timing Diagram 4 5 6 5 3 S3C2440A nXBREQ nXBACK Timing Diagram a a 5 7 5 4 Memory Interface with 8 bit 5 8 5 5 Memory Interface with 8 bit 2 5 8 5 6 Memory Interface with 8 bit ROM x 4 a 5 9 5 7 Memory Interface with 16 bit mem menn nennen 5 9 5 8 Memory Interface with 16 bit SRAM 5 10 5 9 Memory Interface with 16 bit SRAM 2 5 10 5 10 Memory Interface with 16 bit SDRAM 4 16 4 5 11 5 11 Memory Interface with 16 bit SDRAM 4Mx16x4Bank 2 5 11 5 12 S3C2440A nGCS Timing 5 12 5 13 S3C2440A SDRAM Timing 5 13 xxiv 53 2440 MICROCONTROLLER List of Figures continued Figure Title Page Number Number 6 1 NAND Flash Controlle
11. 2 n ten 23 27 Chapter 24 AC97 Controller ea M rrr 24 1 M E 24 1 AC97 Controler Operations 24 2 Block B T To 1i CE 24 2 PaP yp nue tee utet mete een 24 3 Operation Flow Chart 2 2 e a ee Lad eee eg dae ie 24 4 AC Link Digital Interface 24 5 AC Link Output Frame SDATA OUT rrsan eia ae cue age 24 6 AC Link Input Frame 24 6 97 POWerd WnD uu 24 7 97 Controller Special Registers U 24 9 AC97 Global Control Register a 24 9 AC97 Global Status Register 5 24 10 97 Codec Command Register _ _ emen 24 10 97 Codec Status Register CODEC 5 24 11 AC97 PCM Out In Channel FIFO Address Register AC_PCMADDR 24 11 97 MIC in Channel FIFO Address Register AC_MICADDR 24 12 AC97 PCM Out In Channel FIFO Data Register
12. asua sapi 12 2 OHCI Registers for Usb Host Controller 12 2 53 2440 MICROCONTROLLER xiii Table of Contents Continued Chapter 13 USB Device Controller e nu akapa SS Qum au aaa 13 1 ERE DR ER nde 13 1 Usb Device Controller Special Registers 13 3 Function Address Register _ _ nnne 13 5 Power Management Register 13 6 Interrupt Register EP INT REG USB 13 7 Interrupt Enable Register EP INT EN REG USB INT EN_REG 13 9 Frame Number Register FPAME NUM1 REG FRAME 2 REGQG 13 10 Index Register INDEX 2 ner ntes nennen enhn nnne 13 11 MAX Packet Register _ eene 13 11 END Point0 Control Status Register EPO CSR emen nene nnne 13 12 END Point In Control Status Register IN CSR1 REG IN CSR2 13 13 END Point Out Control Status Register OUT CSR1 REG OUT CSR2 REG 13 15 END Point Out Write Count Register OUT FIFO CNT1 REG OUT FIFO
13. 2 7 3 1 ARM Instruction Set Fottmat Eee ed do e edt edd tad d ete s 3 1 3 2 Branch and Exchange mene nene nne 3 5 3 3 Branch INStrucCtions 3 7 3 4 Data Processing 3 9 3 5 ARM Shift OperatiOris 3 12 3 6 Logical 510114 3 12 3 7 Logical kaqa 3 13 3 8 Arithmetic 3 13 3 9 Rotate Right oot d etes n 3 14 3 10 Hotate Right Extended ERR ni REOS 3 14 3 11 PSP Transfer ice oet Dod PE ERE OUR 3 19 3 12 Multiply Instf ctiOns 3 22 3 13 Multiply Long Instr cti ris reote e rh t etat ie ee re age reve 3 25 3 14 Single Data Transfer 3 28 3 15 Little Endian Offset 3 30 3 16 Halfword and Signed Data Transfer with Register 3 34 3 17 Halfword and Signed Data Transfer with Immediate Offset and Auto Indexing 3 35 3 18 Block Data Transfer Instructions eesi aean A menn nne 3 40 3 19 P
14. EE 6 2 2 6 3 Nand Flash Memory Configuration 6 3 Flash Memory do detegere Ee 6 4 Software 6 5 Steppingstone 4 65 6 6 Ecc Error Correction 42 55 54 au 6 7 2048 Byte ECC Code Assignment 6 7 16 Byte ECC Code Assignment 6 7 ECG Mod le Features 6 8 ECO Programming 6 8 Flash Memory Mapping ak ete qe teme ER a 6 9 Nand Flash Memory Configuration cesses 6 10 Nand Flash Configuration Register 6 12 Control Fegisters co A unu pr i 6 13 Command Register 6 15 81 101 6 15 Data 6 15 Main a 6 16 Spare Aroa Ece Regio T es os d n E dede eov lek dee tour Eos 6 17 NFGON Status Rglster e Et
15. 14 14 Interrupt Offset INTOFFSET 14 16 Sub Source Pending SUBSRCPND Register emen 14 17 Interrupt Sub Mask INTSUBMSK 14 18 S3C2440A MICROCONTROLLER Table of Contents Continued Chapter 15 LCD Controller dep 15 1 ie X EI E M Meet pni Dates vite dete pei AREE RH 15 1 Common Dod Ped En 15 2 External Interface Signal netus tiere eva tenet os 15 2 Block Diagram D LLLI 15 3 STN ECD Controller Operation dee RS 15 4 Timing Generator FIMEGEN bet doe Rae ME aee hu tid 15 4 died oa R bet erc Lem dies 15 5 Dithering and Frame Rate Control nnns nennen 15 7 Memory Data Format STN BSWP Ojaras S nene nh ene nnns 15 9 TET ECD Controller Operation itte ina eet bet Echte eoe 15 16 Video enata ir tes 15 16 Memory Data Format TE T l et bee e EE ego 15 17 256 Palette Usage rante re Piste rode ter AEE
16. 58 7 8 SPICLK MOSI 0 0 0 0 0 0 0 Q MISO MSB of character just received CPOL 1 CPHA 1 Format B Cycle vos esas Y 4 Y s Y 2 Y TY EA MISO LSB of previously transmitted character Figure 22 2 SPI Transfer Format 22 4 FLECTRONICS 53 2440 RISC MICROPROCESSOR SPI TRANSMITTING PROCEDURE FOR DMA N SPI is configured mode DMA is configured properly SPI requests DMA service DMA transmits 1byte data to the SPI SPI transmits the data to card Return to Step 3 until DMA count becomes 0 SPI is configured as interrupt or polling mode with SMOD bits RECEIVING PROCEDURE FOR DMA ANP a gt oO N SPI is configured as DMA start with SMOD bits and TAGD bit set DMA is configured properly SPI receives 1byte data from card SPI requests DMA service DMA receives the data from the SPI Write data OxFF automatically to SPTDATn Return to Step 4 until DMA count becomes 0 SPI is configured as polling mode with SMOD bits and clear TAGD bit If SPSTAn s READY flag is set then read the last byte data NOTE Total received data DMA TC values the last data in polling mode Step 9 The first DMA received data is dummy and the user can neglect it FLECTRONICE 22 5 SPI 53 2440 RISC MICROPROCESSOR SPI SPECIAL REGISTERS SPI CONTROL REGISTER SPCONO 0x59000000 SPI channel 0 control register SPCON1 0x59000020 SPI channel 1
17. Ld 2 N3 N4 N5 6 2 2 R R R R NUM N12 CLKOUTO GPH9 DN1 PDN0 I2SSDO AC_SDATA _ OUT nRSTOUT GPA21 R10 EINT11 nSS1 GPG3 MPLLCAP EINT14 SPIMOSI1 GPG6 IICSCL GPE14 VDD RTC U VSSOP LCD LPCREVB GPC7 AIN2 EINT19 TCLK1 GPG11 VD5 GPC13 XM AIN6 EINT23 GPG15 VD7 GPC15 VSSA MPLL DP1 PDPO VD12 GPD4 VSSiarm VSSOP VD20 GPD12 VDDOP AIN1 P7 I2SLRCK AC_SYNC VD17 SPIMOSI1 GPD9 N13 12 13 14 1 2 3 4 5 6 7 8 9 N15 1 2 3 4 5 7 3 N17 amp 1 N10 1 P P2 P3 P4 1 P5 5 VD19 GPD11 6 SPIMOSI0 GPE12 VDDiarm P10 CLKOUT1 GPH10 7 CDCLK AC_nRESET P11 EINT12 LCD_PWREN T8 VDDiarm GPG4 9 14 VDDA ADC EINT21 GPG13 k d ELECTRONICS 1 9 PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR Table 1 2 S3C2440A 289 Pin FBGA Pin Assignments Sheet 1 of 9 Function BUS REQ Sleep nRESET oD oU ADORA gt gt OUO 29 10 ADD DDR6 DDR7 SISIS IS r ADDRB ADRS H EE gt f e Me gt o SI ISIS IS 9 S S Lu Q T Q ADDR17 GPA2 ADDR17 ADDR18 GPA3 ADDR18 F7 E7 B7 F8 7 8 07 8 B8 A8 C8 H8 E9 C9 G9 F9 H9 010 ADDR20 GPA5 ADD
18. a 21 2 BENI 21 3 Transmit and Receive 21 3 Audio Serial Interface Format 1c e eee AS edhe N a caa ee uu 21 3 21 3 Left Justified anvin a d ede Mav ec rea iie a deo ug EE eves Lig E dco eges 21 3 Sampling Frequency and Master Clock mene mene n nme n nne 21 4 15 Interface Special Registers a nnne nne nnne nnne 21 5 IIS Control IISCON Register uu e u Du ua yaa au ha 21 5 IIS Mode Register IISMOD 21 6 15 Prescaler IISPSR 0 2022 20 21 7 15 FIFO Control IISFCON BR giStl er naya nnne 21 8 IIS EIEQ IISEIEO ain tk 21 8 Chapter 22 SPI S CRUENTUM EM 22 1 F Gat res cac eee e e ee ie pug 22 1 Block Diagram e Ned ka 22 2 5154 22 3 Programming Procedures em 22 3 SPI Transfer 224 Transmitting Procedure for 22 5 Receiving Procedure for DMA EE nnne 22 5 SPI Special Registers onore eat eeu ese RR ELA RR
19. 23 12 23 11 image Miror ang Rotation etie d eau tere E 23 18 23 12 Scaling Schefri6 23 20 24 1 697 DIGO at t FS 24 2 24 2 Internal Data Patl 2 uu Er P coe Pac eoa E 24 3 24 3 97 Flow pr eni te etie cora ipee DR er Leste RR IR Oo DR Sens 24 4 24 4 Bi directional AC link Frame with Slot 24 5 24 5 AG link Outpu t Fratme it ve b o EE echter Fiore eR xe a nte ERE Ae Ra RA 24 6 24 6 AC link Input Frare eoo 24 6 24 7 97 Powerdown Timing 24 7 24 8 97 Power down Power up 4 erionenn ae 24 8 26 1 289 FBGA 1414 Package Dimension 1 Top 26 1 26 2 289 FBGA 1414 Package Dimension 2 Bottom 26 2 27 1 Power Consumption Example Comparison when Applied DVS 5 27 7 27 2 XTIpll Clock Timing Diagram s oet bbc e cod etas eee betae 27 8 27 3 EXTCLK Clock Input Timing Inn 27 8 27 4 EXTCLK HCLK in case when EXTCLK is used Without the PLL 27 8 27 5 HCLK CLK
20. a ei Sede i ieee 23 11 Window Option Register sieer rris 23 12 Global Control Register A el ieee an eee ee 23 13 Start Address Heglster ty ees 23 13 Y2 Start Address i eise 23 13 Yo Slart 5 Registr ocra roce cxt ta u rr a ER E dE C 23 14 Y4 Start Address ete eee e uen ene 23 14 CBT Start Address Hegister uapa el paqay 23 14 CB2 Start Address Register da eee node 23 14 CB3 Start Address Register e uta beoe nnde sh ET 23 15 Start Address Register 23 15 CRT Start Address Registe aine ee ein nena atta ete 23 15 CR2 Start Address Register 23 15 CRS Start Address Registe assaka 23 16 CR4 Start Address e nee diene ia 23 16 Codec Target Format 23 17 Codec Control Register nene a ai 23 19 Register Setting Guide for Codec Scaler and Preview Scaler
21. 27 12 TFT LCD Controller Module Signal Timing Constants 27 13 IIS Controller Module Signal Timing Constants 27 14 IIC BUS Controller Module Signal Timing 27 15 SD MMC Interface Transmit Receive Timing Constants 27 16 SPI Interface Transmit Receive Timing Constants 27 17 USB Electrical Specifications 27 18 USB Full Speed Output Buffer Electrical Characteristics 27 19 USB Low Speed Output Buffer Electrical Characteristics 27 20 NAND Flash Interface Timing Constants XXX Page Number 53 2440 MICROCONTROLLER 53 2440 RISC MICROPROCESSOR PRODUCT OVERVIEW PRODUCT OVERVIEW INTRODUCTION This user s manual describes SAMSUNG s S3C2440A 16 32 bit RISC microprocessor SAMSUNG s S3C2440A is designed to provide hand held devices and general applications with low power and high performance micro controller solution in small die size To reduce total system cost the S3C2440A includes the following components The S3C2440A is developed with ARM920T core 0 13um CMOS standard cells and a memory complier Its low power simple elegant and fully static design is particularly suitable for cost and power sensitive applications adopts a new bus architecture known as Advanced Micro
22. sor amy mua ame mua ww Jj ma ww Gm ma ww ams ma ww Gm ma ww ami ma SO amo ma we mak es E pe ami sea mua mua 7 7 p D a p mua arr 7 mua 9 4 ELECTRONICS 53 2440 RISC MICROPROCESSOR PORTS Table 9 1 S3C2440A Port Configuration Sheet 4 of 5 Continued mar Pin Functions 1 maa cs tmm ceu mua Emm 7 cres mum tmm ceo ame mna ama musa enro ae ma C ec mua tm ELECTRONICS 9 5 PORTS 53 2440 RISC MICROPROCESSOR Table 9 1 53 2440 Port Configuration Sheet 5 of 5 Continued Selectable Pin Functions ame ame amy ame no ams ama 0 ama ma
23. 10 19 S3C2440A MICROCONTROLLER Table of Contents Continued Chapter 11 UART OVEIVIOW 11 1 PSI RH Eme UR 11 1 Block T ED DIL ILLUS 11 2 EPE 11 3 Uant Special Registers teo oco ees obe te 11 10 Uart bine Cortrol Register iere EE ee e XE eve ba sue Rite ie ERE Rite Reed 11 10 Uart Control Register odores Por be Dee abe eod e od bela S Derek a edel audis 11 11 Uat FIFO Control 11 14 Uart Modem Control u tonc o eade arte aditu kde 11 15 Uart TARY Statis Registers et 11 16 Uart Error Status RESTOL y u y u u ua Bac n HARE CO Eee Ree eR rod bera 11 17 Wart FIFO Status Register L Id be tre ro erai be nr retta aa UE dabei 11 18 Modem Status Register nhe enne nnns 11 19 Uart Transmit Buffer Register HOLDING Register amp FIFO 11 20 Uart Receive Buffer Register HOLDING Register amp FIFO Register 11 20 Uart Baud Rate Divisor nennen 11 21 Chapter 12 USB HOST Controller 12 1 Usb Host Controller Special Registers
24. 3 3V 0 3V Os 4 Table 27 11 DMA Controller Module Signal Timing Constants Vpp 1 2 V 0 1 V TA 40 to 85 3 3V 0 3V Access to ack delay during low transition Access to ack delay during high transition External request delay ELECTRONICS 27 37 ELECTRICAL DATA S3C2440A RISC MICROPROCESSOR Table 27 12 TFT LCD Controller Module Signal Timing Constants Vpp 1 2 V 0 05 V TA 40 to 85 Vex_ 3 3V 0 3V Wm Units Venica sync pulse wath mew back porch delay ron porch delay Pe Wk b os Pe wu os Pe Hone soup to VOLK alng eoe o5 e setup 0 VOLK o5 e VBEN om VOLK ating eae o5 e setup to VOLK Tang eae os e fom faning mmu 5 e VSYNC setup to HSYNG edge Terse VSYNC hold from HSYNC falling edge Tf2hhold HBPD HFPD Pvclk HOZVAL 3 NOTES 1 HSYNC period 2 VCLK period Table 27 13 IIS Controller Module Signal Timing Constants Vpp 1 2 V 0 1 V TA 40 to 85 3 3V 0 3V 27 38 ELECTRONIC
25. DUO NC NN e A gt ADDR3 ADDR18 GPA3 1 A1 A2 A3 A4 A5 A6 A7 A8 A9 B1 B2 B3 B4 B5 B7 B8 C1 C2 C3 C4 5 C6 C7 C8 C9 10 12 13 14 17 D1 D2 D3 D4 D5 07 010 k E siola a v d ELECTRONICS 1 7 PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR Table 1 1 289 Pin FBGA Pin Assignments Pin Number Order Sheet 2 of 3 Continued VDDOP 1 LEND GPC0 VDDiarm CAMDATA1 GPJ1 CAMCLKOUT GPJ11 nXDACKO GPB9 VDDalive J4 CAMRESET GPJI2 VCLK GPC1 CAMPCLK GPJ8 J5 TOUTI GPBI nXBREQ GPB6 CAMVSYNC GPJ9 7 TOUT2 GPB2 VFRAME GPC3 ADDR8 98 CAMDATAG GPJ6 IPSSDI AC SDATA 5 G1 G2 G3 G4 G5 G6 G7 G8 G9 ADDR17 GPA2 9 SPICLKO GPE13 DO EINT15 SPICLK1 GPG7 we NN NEN we NEN we CAMDATA7 GPJ7 VD16 SPIMISO1 GPD8 K10 M10 EINT20 GPG12 H17 EINT4 GPF4 M M M M M M 7 N H1 H2 H3 H4 H5 H6 H7 H8 9 H 5 42 43 45 46 47 48 49 J11 J12 J15 J17 K1 K2 K3 4 5 K7 K8 K9 11 13 d 1 8 ELECTRONICS 53 2440 RISC MICROPROCESSOR PRODUCT OVERVIEW Table 1 1 289 FBGA Pin Assignments Pin Number Order Sheet 3 of 3 Continued
26. 2223 s ao o o o o d ELECTRONICS 1 15 PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR Table 1 2 53 2440 289 Pin FBGA Pin Assignments Sheet 7 of 9 Continued ot 14 VDDA ADC N16 VDDA MPLL M13 VDDA UPLL G4 VDDalive J17 VDDalive M5 M7 gt N4 R1 N3 P2 P3 R2 N5 R3 P4 R4 P5 N6 T4 5 5 7 U5 M lt EM _ OR OR EN EN NUM Gis 1 16 ELECTRONICS 53 2440 RISC MICROPROCESSOR PRODUCT OVERVIEW Table 1 2 S3C2440A 289 Pin FBGA Pin Assignments Sheet 8 of 9 Continued Default State State State Function BUS REQ Sleep nRESET Type A A10 A E zls 12 d12c d12c 12 12 d12c 12 L2 T6 T8 U J2 us A9 UJ 6 F1 1 1 C J1 T 1 12 T3 14 NN T S N o th st st s s s s s d ELECTRONICS 1 17 PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR Table 1 2 53 2440 289 Pin FBGA Pin Assignments Sheet 9 of 9 Continued
27. 3 61 Multiplication by Constant Using the Barrel 3 61 Loading a Word from an Unknown Alignment m emnes 3 63 Chapter 4 Thumb Instruction Set Thumb Instruction Set Format t cni its eo bete ttt e cii obe Dii ex puit dec ar Deer 4 1 Format SUMMALY deg ure E Boetii reu aa Q re dee dua rena 4 2 Opcode Summary C aS A u as awa Waaa asas 4 3 Format ts Move Shited Register 4 5 Sut UE 4 5 Instruction Cycle Tunes eo e ege eee ieu CE 4 6 Ee TUI 4 6 Format 2 Add Subtract 2 2 2 ete telas Pete 4 7 S cum E 4 7 Instruction Cycle Times t eere oreet eb no 4 8 E be erts 4 8 Format 3 Move Compare Add Subtract Immediate 4 9 SCELERE 4 9 Instruction Cycle Times eoo ee cote ie cb e Cen rev ee teg 4 10 m cm 4 10 vi 53 2440 MICROCONTROLLER Table of Contents Continued Chapter 4 Thumb Instruction Set Continued Format 4 ALU Qu code re 4 11 i us MEE 4 11 ies ieu 4 12 EXAMP cee der M
28. 4096 x 4096 pixel input support without scaling 2048 x 2048 pixel input support with scaling 4096 x 4096 pixel output support for CODEC path Max 640 x 480 pixel output support for PREVIEW path Image mirror and rotation X axis mirror Y axis mirror and 180 rotation and codec input image generation RGB 16 24 bit format and YCbCr 4 2 0 4 2 2 format SIGNAL DESCRIPTION Table 23 1 Camera Interface Signal Description vo Ame CAMPCLK Eo Pixel clock driven by the camera processor CAMVSYNC 1 H Frame sync driven by the camera processor CAMHREF 1 H Horizontal sync driven by the camera processor CAMDATA 7 0 Pixel data driven by the camera processor CAMCLKOUT Master clock to the camera processor CAMRESET HL Software reset or power down to the camera processor NOTE I O direction is on the AP side I input O output d ELECTRONICS 23 1 53 2440 RISC MICROPROCESSOR BLOCK DIAGRAM T patternMux ITU R BT 601 656 CatchCam YCbCr 4 2 2 Preview Scaler amp RGB Formatter Preview DMA AHB bus CAMERA INTERFACE gt o gt Codec Scaler Codec DMA Figure 23 1 CAMIF Overview ELECTRONICS 53 2440 RISC MICROPROCESSOR CAMERA INTERFACE TIMING DIAGRAM 46 4 frame J H s AMVSYNG _ __ Vertical tA V n lines
29. WemPonsuus WemPorsunea D 12 2 ELECTRONICS 53 2440 RISC MICROPROCESSOR USB DEVICE USB DEVICE CONTROLLER OVERVIEW Universal Serial Bus USB device controller is designed to provide a high performance full speed function controller solution with DMA interface USB device controller allows bulk transfer with DMA interrupt transfer and control transfer USB Device Controller Supports Full speed USB device controller compatible with the USB specification version 1 1 DMA interface for bulk transfer Five endpoints with FIFO EPO 16byte Register EP1 128byte IN OUT FIFO EP2 128byte IN OUT FIFO 128byte IN OUT FIFO 4 128byte IN OUT FIFO Integrated USB Transceiver dual port asynchronous RAM dual port asynchronous RAM dual port asynchronous RAM dual port asynchronous RAM interrupt or DMA interrupt or DMA interrupt or DMA interrupt FEATURE Fully compliant with USB Specification Version 1 1 Full speed 12Mbps device Integrated USB Transceiver Supports control interrupt and bulk transfer Five endpoints with FIFO One bi directional control endpoint with 16 byte FIFO EPO Four bi directional bulk endpoints with 128 byte FIFO EP1 EP2 EP3 and EP4 Supports interface for receive and transmit bulk endpoints EP2 and 4 Independent 128 byte receive and transmit FIFO
30. a mener 4 26 4 13 Load Addfesg 4 28 4 14 Tie DD InstrUCllOlr c 4 30 4 15 PUSH and POP Instructions co ete err eae ch EH e ng o e eee 4 31 4 16 The Multiple Load Store 4 33 4 17 The Conditional Branch Instructions mene 4 34 4 18 BEI 4 36 4 19 Summary of Branch 4 37 4 20 The BL Y Re i ee EG ED ee 4 39 5 1 Bank 6 7 A a ed ic mme vati biberit en 5 3 5 2 SDRAM Bank Address Configuration 5 5 7 1 Clock Source Selection at cece cents cece enemies 7 2 7 2 Clock and Power State in Each Power 7 11 7 3 CLKSLOW and CLKDIVN Register Settings for SLOW Clock 7 12 7 4 Pin configuration table in Sleep mode eee 7 16 53 2440 MICROCONTROLLER xxix List of Tables continued Table Title Number 8 1 DMA Request Sources for Each 9 1 S3C2440A Port Configuration Sheet 1 015 11 1 Interrupts in Connection with FIFO 15 1 Relation Between and CLKVAL STN HCLK 60
31. rax rax rue After setting PMS value it is required to set CLKDIVN register The value set for CLKDIVN will be valid after PLL lock time The value is also available for reset and changing Power Management Mode The setting value can also be valid after 1 5 HCLK Only 1HCLK can validate the value of CLKDIVN register changed from Default 1 1 1 to other Divide Ratio 1 1 2 1 2 2 1 2 4 FCLK CLKDIVN 0x00000000 0x00000001 1 1 2 0x00000003 1 2 4 0 00000000 1 1 1 ee HCLK PCLK 4 9 1 HCLK 4 1 5 HCLK 1 5 Figure 7 6 Example of Internal Clock Change 7 8 ELECTRONICS 53 2440 RISC MICROPROCESSOR CLOCK amp POWER MANAGEMENT NOTES CLKDIVN should be set carefully not to exceed the limit of HCLK and PCLK If HDIVN is not 0 the CPU bus mode has to be changed from the fast bus mode to the asynchronous bus mode using following instructions S3C2440 does not support synchronous bus mode MMU SetAsyncBusMode mrc p15 0 r0 c1 c0 0 rO0 r0 ZR1 nF OR R1 iA mcr p15 0 r0 c1 c0 0 If HDIVN is not 0 and the CPU bus mode is the fast bus mode the CPU will operate by the HCLK This feature can be used to change the CPU frequency as a half or more without affecting the HCLK and PCLK ELECTRONICS 7 9 CLOCK amp MANAGEMENT S3C2440A RISC MICROPROCESSOR POWER MANAGEMENT The Power Management block controls the syste
32. 060040 UART chanel 1 modem status register o0 Delta CTS 4 Indicate that the nCTS input to the S3C2440A has changed state since the last time it was read by CPU Refer to Figure 11 8 0 Has not changed 1 Has changed Clear to Send 0 CTS signal is not activated nCTS pin is high 1 CTS signal is activated nCTS pin is low Delta CTS Read UMSTAT Figure 11 8 nCTS and Delta CTS Timing Diagram ELECTRONICS 11 19 UART S3C2440A RISC MICROPROCESSOR UART TRANSMIT BUFFER REGISTER HOLDING REGISTER amp FIFO REGISTER There are three UART transmit buffer registers including UTXH0 UTXH1 and UTXH2 in the UART block UTXHn has an 8 bit data for transmission data UTXH0 0x50000020 L W UART channel 0 transmit buffer register 0x50000023 B by byte UTXH1 0x50004020 L UART channel 1 transmit buffer register UTXH2 0x50008020 L W UART channel 2 transmit buffer register 0x50008023 B byte TXDATAn 7 0 Transmit data for UARTn NOTE L The endian mode is Little endian B The endian mode is Big endian UART RECEIVE BUFFER REGISTER HOLDING REGISTER amp FIFO REGISTER There are three UART receive buffer registers including URXH0 URXH1 and URXH2 in the UART block URXHn has an 8 bit data for received data R URXHO 0x50000024 L R UART channel 0 receive buffer register 0 50000027 Y byte
33. 3 51 Instruction OyGle Tinesu TT 3 52 Exaimpl65S ua al h 3 52 53 2440 MICROCONTROLLER Table of ContentS continued Chapter 3 ARM Instruction Set Continued Coprocessor Data Transfers LDC 5 3 53 The Coprocessor Fields sup Re HERR ER D CBE bag ioe 3 54 Addressing Modes LU toco aee rM o HERE REL ERA EIE 3 54 Address stre uiu peii eite tb ee 3 54 ADDONS C S 3 54 Assembler SVAR e e 3 55 ae CES 3 55 Coprocessor Register Transfers 3 56 The Coprocessor Flelds tare dera Ade tated pre RE 3 56 Tiste Dei ea EE RENE BER ERI EMEN u awas 3 57 Transfers from R15 coii cot trot RR 3 57 Instruction Cycle TES e sae Lote ih ot cr sta pais 3 57 Assembler Syritax itte pex etu Reed E ts 3 57 Cages 3 57 Undefined 3 58 Instruction Cycle ett ete 3 58 Asserbler Syritax tad ele 3 58 Inistr ction Set 3 59 Using the Conditional Instructions 3 59 Pseudo Random Binary Sequence Generator
34. d Po B 3 27 st wu LU ah hoe LU ETE 3 27 S3C2440A MICROCONTROLLER Table of Contents Continued Chapter 3 ARM Instruction Set Continued Single Data Transtar STR tog eed eae E eae d ett ER e d aae 3 28 Offsets and A to Indexing exe EE E eret EE Ee E REND 3 29 Shifted Register OffSet t PH DH ERE SOR EH I Pe ERR Eod Ped 3 29 Bytes and Words uiae 3 29 IE od icc 3 31 EEX GIMP Oech wu MEUM 3 31 e 3 31 Instruction 3 31 ASSOMBIGI SY as eet 3 32 Examples RAI ERU Rue aet ei nf itd 3 33 Halfword and Signed Data Transfer LDRH STRH LDRSB LDRSH eme een 3 34 Offsets and Auto Iridexing re be tete Los tr 3 35 Halfword 3 36 WSS OF RAD m rcr ME 3 37 Data 3 37 Instruction Gycle TImes s s ssi creo o tite ee 3 37 Assembler SYNA etcetera ove utetur 3 38 terze A Sha a hae 3 39 Block Data T
35. e 15 15 15 5 16BPP Display Types TET a nx 15 22 15 6 TET LED Timing t ay tco sr tec o e 15 23 15 7 Example of Scrolling in Virtual Display Single 15 25 15 8 Example of PWREN Function PWREN 1 INVPWREN 0 HH 15 26 16 1 ADC and Touch Screen Interface Functional Block 16 2 16 2 ADC and Touch Screen Operation signal 16 4 17 1 Real Time Clock Block 17 2 17 2 Main Oscillator Circuit S L Da s meme nennen 17 3 18 1 Watchdog Timer Block Diagram e u eene nhe 18 2 19 1 SD lntertace Block Diagram bet adhd eid 19 1 20 1 IIG Bus Block Diagram as t d 20 2 20 2 Start and Stop Gonditlon 20 3 20 3 IIC Bus Interface Data 20 4 20 4 Data Transfer the 2 20 5 20 5 Acknowledge on the 20 5 20 6 Operations for Master Transmitter 20 7 20 7 Operations for Master Receiver 20 8 20
36. SPRDATO 0x59000014 R SPI channel 0 Rx data register SPRDAT1 0x59000034 R SPI channel 1 Rx data register Rx Data Register 7 0 This field contains the data to be received over the SPI channel ELECTAONICS 22 9 SPI S3C2440A RISC MICROPROCESSOR NOTES 22 10 FLECTRONICS 53 2440 RISC MICROPROCESSOR CAMERA INTERFACE CAMERA INTERFACE OVERVIEW This chapter will explain the specification and defines the camera interface CAMIF CAMera InterFace within the S3C2440A consists of 7 parts pattern mux capturing unit preview scaler codec scaler preview DMA codec DMA and SFR The CAMIF supports ITU R BT 601 656 YCbCr 8 bit standard Maximum input size is 4096x4096 pixels 2048x2048 pixels for scaling and two scalers exist Preview scaler is dedicated to generate smaller size image like PIP Picture In Picture and codec scaler is dedicated to generate codec useful image like plane type YCbCr 4 2 0 or 4 2 2 Two master DMAs can do mirror and rotate the captured image for mobile environments These features are very useful in folder type cellular phones and the test pattern generated can be useful in calibration of input sync signals as CAMHREF CAMVSYNC Also video sync signals and pixel clock polarity can be inverted in the CAMIF side by using register setting FEATURES ITU R 601 656 8 bit mode external interface support 011 Digital Zoom In capability Programmable polarity of video sync signals
37. 15 21 Samsung TFT LCD Panel 3 5 PORTRAIT 256K COLOR REFLECTIVE A SI TRANSFLECTIVE A SI TFT LCD 15 24 Virtual Display EF T S TIN rea nece ote edo deg 15 25 ECD PowerEnable STN TET iiiter ieee ee aite bein te riter ERES EE e b ERR dees RR 15 26 LCD Controller Special Registers 15 27 Frame Buffer Start Address 1 nnne nnne 15 33 Chapter 16 ADC amp Touch Screen Interface e M E 16 1 16 1 ADC Touch Screen Interface 16 2 DIT Te ED CE 16 2 FUNCTION Descriptiolis 16 3 ADC AND Touch Screen Interface Special Registers 16 5 ADC Control Register 16 5 ADC Touch Screen Control Register 5 16 6 ADC Start Delay Register 16 7 ADC Conversion Data Register 16 8 ADC Conversion Data Register ADCDAT1 16 9 ADC Touch Screen Up Down INT Check Register 16 9 53 2440 MICROCONTROLLER Table of Contents Continued Chapter 17 Real Time Clock e u
38. 24 12 97 MIC in Channel FIFO Data Register AC_MICDATA eme 24 12 S3C2440A MICROCONTROLLER Table of Contents Continued Chapter 25 Bus Priorities Overview soda ed dah us aw dd tive do 25 1 LEM 25 1 Chapter 26 Mechanical Data 26 1 Chapter 27 Electrical Data Absolute Maximum Ratings y AAA A 27 1 Recommended Operating 27 2 D C Electrical CharacteristiGs 4x 20 e 27 3 68165 Pha re tie cheats 27 8 53 2440 MICROCONTROLLER xxi List of Figures Figure Title Page Number Number 1 1 SIG2440A Block Diagtatm 2 22 1 5 1 2 53 2440 Pin Assignments 289 1 6 2 1 Big Endian Addresses of Bytes within 2 2 2 2 Little Endian Addresses of Bytes within Words 2 2 2 3 Register Organization in ARM State emen nemen 2 4 2 4 Register Organization in THUMB state eene 2 5 2 5 Mapping of THUMB State Registers onto ARM State Registers 2 6 2 6 Program Status Register
39. 4 7 0 Not requested 1 Requested EINT3 0 Not requested 1 Requested 2 0 Not requested 1 Requested EINT1 0 Not requested 1 Requested EINTO D 0 Not requested 1 Requested ELECTRONICS 14 15 INTERRUPT CONTROLLER S3C2440A RISC MICROPROCESSOR INTERRUPT OFFSET INTOFFSET REGISTER The value in the interrupt offset register shows which interrupt request of IRQ mode is in the INTPND register This bit can be cleared automatically by clearing SRCPND and INTPND INTOFFSET 0 4 000014 indicate the IRQ interrupt request source 0x00000000 The OFFSET value INT Source The OFFSET value INT Source INT ADC NOTE 14 16 INT_RTC INT SPI INT UARTO INT INT USBH INT USBD INT NFCON INT UARTI1 INT SPIO INT SDI INT INT DMA2 INT DMA1 INT DMAO INT LCD wr TER rites m wor acer um m mon iene mm ms m ew 3 je 0 3 3 2 2 2 2 2 2 2 2 2 2 1 0 9 8 7 6 5 4 3 2 1 0 19 18 17 16 FIQ mode interrupt does not affect the INTOFFSET register as the register is available only for IRQ mode interrupt ELECTRONICS 53 2440 RISC MICROPROCESSOR INTERRUPT CONTROLLER SUB SOURCE PENDING SUBSRCPND REGISTER You can clear a specific bit of the SUBSRCPND register by writing a data to this register It clears only the bit pos
40. Se esie ric ERES E p ERR 6 18 ECCO T Statis 2 acces 6 19 Main Data Area ECCO Status 6 20 Spare Area ECC Status 6 20 Block Address Regilor neo 6 21 53 2440 MICROCONTROLLER Table of Contents Continued Chapter 7 Clock amp Power Management er X aaa 7 1 nctional Description s co coo 7 2 911415 510011 11 10 15 7 2 Glock Source Selecto rre ua e reed el eth Ate REPRE I 7 2 Phase Locked Loop ee dae ios 7 4 Glock Control LOGIC ass zd snk deed cna eaves cual 7 6 Power Management 7 10 Clock Generator amp Power Management Special Register e 7 20 Lock Time Count Register 7 20 PLL Control Register MPLLCON amp 7 21 PEL Value Selection Table Eee eee clay den 7 21 Clock Control Register 7 02 Clock Slow Control CLKSLOW
41. External bus master TIC ARM920T 13 Reserved f PN O N a N Among these bus masters the four DMAs DMAO DMA1 DMA2 operate under rotation priority while the others run under fixed priority ELECTRONICS 25 1 BUS PRIORITIES S3C2440A RISC MICROPROCESSOR NOTES 25 2 ELECTRONICS 53 2440 RISC MICROPROCESSOR MECHANICAL DATA MECHANICAL DATA PACKAGE DIMENSIONS 289 FBGA 1414 SN SNWVS TOLERANCE 0 10 Figure 26 1 289 FBGA 1414 Package Dimension 1 Top View ELECTRONICS 26 1 MECHANICAL DATA 53 2440 RISC MICROPROCESSOR 17 16 1514 13 12 11109 8 7 6 5 4 3 2 1 A1 INDEX MARK ai I 289 0 45 0 05 07015 9 IEG PIG oce 0 0 TOLERANCE 0 10 Figure 26 2 289 FBGA 1414 Package Dimension 2 Bottom View The recommended land open size is 0 39 0 41mm diameter 26 2 ELECTRONICS 53 2440 RISC MICROPROCESSOR ELECTRICAL DATA 2 ELECTRICAL DATA ABSOLUTE MAXIMUM RATINGS Table 27 1 Absolute Maximum Rating DC Supply Voltage 1 2V Vpp 1 8V 2 5V 3 0V 3 3V 1 8V 2 5V 3 0V 3 3V lt DC Input Voltage VN 3 3V Input buffer 3 3V Interface 5V Tolerant input buffer 3 3V Output buffer Alo gt O O O O O BB 200 65 to
42. Level Edge mode on external interrupt source e Programmable polarity of edge and level e Supports Fast Interrupt request FIQ for very urgent interrupt request Timer with Pulse Width Modulation PWM e 4 ch 16 bit Timer with PWM 1 ch 16 bit internal timer with DMA based or interrupt based operation e Programmable duty cycle frequency and polarity e Dead zone generation Supports external clock sources RTC Real Time Clock Full clock feature msec second minute hour date day month and year 32 768 KHz operation Alarm interrupt e Time tick interrupt General Purpose Input Output Ports 24 external interrupt ports 130 Multiplexed input output ports DMA Controller 4 ch controller e Supports memory to memory to memory memory to IO and IO to IO transfers e Burst transfer mode to enhance the transfer rate LCD Controller STN LCD Displays Feature e Supports types of STN LCD panels 4 bit dual scan 4 bit single scan 8 bit single scan display type ELECTRONICS PRODUCT OVERVIEW e Supports monochrome mode 4 gray levels 16 gray levels 256 colors and 4096 colors for STN LCD e Supports multiple screen size Typical actual screen size 640x480 320x240 160x160 and others Maximum frame buffer size is 4 Mbytes Maximum virtual screen size in 256 color mode 4096x1024 2048x2048 1024x4096 and others TFT Thin Film Transistor Color
43. eene nnne 8 14 x S3C2440A MICROCONTROLLER Table of Contents Continued Chapter 9 PORTS OVEIVIOW eror rro UE Port Configuration Register Port Data Register Port Pull Up Register Miscellaneous Control External Interrupt Control A Registera meere en eeN 38542315 8540 02 Port A Control Registers GPACON Port Control Registers GPBCON GPBDAT Port C Control Registers GPCCON GPCDAT GPCUP a Port D Control Registers GPDCON GPDDAT 5 Port E Control Registers GPECON GPEDAT ee nennen Port Control Registers GPFCON Port G Control Registers GPGCON Port H Control Registers GPHCON GPHDAT eene nme nnne nnne Port J Control Registers GPJCON Miscellaneous Control Register
44. mesa WW NANO fash sta lock address ___ wemx fash end block adress 1 30 ELECTRONICS 53 2440 RISC MICROPROCESSOR PRODUCT OVERVIEW Table 1 4 S3C2440A Special Registers Sheet 6 of 14 Continued ae Name B Endian L Endian Write Camera Interface CIWDOFST 0x4F000004 Window offset register CIGCTRL ______ 042000008 Global control register CICOYSA 0x4F000018 Y 15 frame start address for codec CICOYSA2 00001 frame start address for codec _ CICOYSA3 0x4F000020 Y 3 frame start address for codec CICOYSA4 0x4F000024 Y ath start address for codec CICOCBSA 0x4F000028 Cb 1S frame start address for codec CICOCBSA2 0Ox4FO0002C 1 Cb 29 start address for codec cicocesas oaFooooso Cr 1Stirame start address for codec _ cr in b 4th frame start address for codec CIPRCLRSA1 Ox4F00000C Target image format of codec DMA Codec DMA control related E Codec pre scaler destination format Codec main scaler control RGB 15 frame start address for preview DMA RGB 279 frame start address for preview DMA 319 frame start address for preview DMA RGB 41 frame start address
45. 2 REQGQ 13 17 END Point FIFO Register 13 17 DMA Interface Control Register 13 18 DMA Unit Counter Register EPN 13 19 DMA FIFO Counter Register 13 20 DMA Total Transfer Counter Register TTC 1 M H HH Hem 13 21 Chapter 14 Interrupt Controller xiv QUGIVIOW HX 14 1 Interrupt Controller 1 1101 meme nme nnne nnne EER sua aa nnns 14 2 Interrupt Sources e 14 3 SUB SOUICES etn tn eh eaten etn ds apus 14 4 Interrupt Priority Generating 14 5 deco 14 6 Interrupt Controller Special 14 7 Source Pending SRCPND 14 7 Interrupt Mode INTMOD 14 9 Interrupt Mask INTMSK Register meme nmn nnne 14 11 Priority Register PRIORITY pontem e voe Up emer vp ee 14 13 Interrupt Pending INTPND
46. 7 23 Clock Divider Control CLKDIVN Register mener 7 24 Camera Clock Divider CAMDIVN 7 25 Chapter 8 DMA a LT 8 1 DMA Reguest HE chy E iet ete Endo e bee CO 8 2 DMA idee ti tete ttm I LO E ta 8 2 External DREQ DACK Protocol esien eane n ran ARRE ea EANES AA nennen nnne hn nenne nnn nennen 8 3 5 8 6 DMA Special Ete tes Pere 8 7 DMA Initial Source DISRC Register u eiat a meme 8 7 Initial Source Control DISRCC Register 8 7 Initial Destination DIDST Register Hmm nennen 8 8 Initial Destination Control DIDSTC 8 8 DMA Control DCON 8 9 Status DSTAT tee re ere e Gage coe ER 8 12 DMA Current Source DCSRO Register nnne 8 13 Current Destination DCDST 8 13 DMA Mask Trigger DMASKTRIG Register
47. If REQ1 is serviced SEL bits are changed to 010 If REQ2 is serviced SEL bits are changed to 10b If REQ3 is serviced SEL bits are changed to 116 If REQ4 is serviced ARB SEL bits are changed to 006 14 6 ELECTRONICS 53 2440 RISC MICROPROCESSOR INTERRUPT CONTROLLER INTERRUPT CONTROLLER SPECIAL REGISTERS There are five control registers in the interrupt controller source pending register interrupt mode register mask register priority register and interrupt pending register All the interrupt requests from the interrupt sources are first registered in the source pending register They are divided into two groups including Fast Interrupt Request FIQ and Interrupt Request IRQ based on the interrupt mode register The arbitration procedure for multiple IRQs is based on the priority register SOURCE PENDING SRCPND REGISTER The SRCPND register is composed of 32 bits each of which is related to an interrupt source Each bit is set to 1 if the corresponding interrupt source generates the interrupt request and waits for the interrupt to be serviced Accordingly this register indicates which interrupt source is waiting for the request to be serviced Note that each bit of the SRCPND register is automatically set by the interrupt sources regardless of the masking bits in the INTMASK register In addition the SRCPND register is not affected by the priority logic of interrupt controller In t
48. WDLY STN STN WDLY 1 0 bits determine the delay between VLINE and by counting the number of the HCLK WDLY 7 2 are reserved 00 16 HCLK 01 32 HCLK 10 48 HCLK 11 64 HCLK HOZVAL 18 8 TFT STN These bits determine the horizontal size of LCD panel 00000000000 HOZVAL has to be determined to meet the condition that total bytes of 1 line are 4n bytes If the x size of LCD is 120 dot in mono mode 120 cannot be supported because 1 line consists of 15 bytes Instead 128 in mono mode can be supported because 1 line is composed of 16 bytes 2n LCD panel driver will discard the additional 8 dot LINEBLANK STN These bits indicate the blank time in one horizontal line duration STN time These bits adjust the rate of the VLINE finely The unit of LINEBLANK is HCLK x 8 Ex If the value of LINEBLANK is 10 the blank time is inserted to VCLK during 80 HCLK HFPD TFT 7 0 TFT Horizontal front porch is the number of VCLK periods between 0X00 the end of active data and the rising edge of HSYNC Programming NOTE In case of STN LCD LINEBLANK WLH WDLY value should be bigger than 14 12Tmax LINEBLANK WLH WDLY 14 8xTmax1 4xTmax2 14 12Tmax LEGEND 1 14 SDRAM Auto refresh bus acquisition cycles 2 8x Tmax1 Cache fill cycle X the Slowest Memory access time Ex ROM 3 4 Tmax2 0xC 0xE address Frame memory Access time ELECTRONICS 15 29 LCD CONTROLLER S3C2440A RISC MICRO
49. eS ya NR Pu 22 6 SPI Control 22 6 58168 EET 22 7 SPI Pin Control Register 2 1 e 22 8 SPI Baud Rate Prescaler 22 9 SPI Tx Data Register cocer eee even ieee T 22 9 SPI Rx Data Registers ca coucou Ata 22 9 xviii 53 2440 MICROCONTROLLER Table of Contents Continued Chapter 23 Camera Interface 23 1 lw 23 1 Block DISgraffi P c el 23 2 TIMING IIR 23 3 Camera Interface Operation fecu V nude o 23 5 Two DMA Paltlis iere e 23 5 Clock ed ane a ed a 23 5 Frame Memory Hirerarchy gt gt 22241 a 05240 eli ete ees 23 6 Memory Storing aT 23 8 Timing Diagram for Register 23 9 Timing Diagram for Last u u Reed p 23 10 Camera Interface Special Registers u u a 23 11 Source Format bee
50. Qs um mmn n Function BUS REQ Sleep nRESET Type w vss P P P NOTES 1 The BUS REQ shows the pin state at the external bus which is used by the other bus master 2 mark indicates the unchanged pin state at Bus Request mode 3 Hi zor Pre means Hi z or early state and it is determined by the setting of MISCCR register 4 means analog input analog output 5 6 P and mean power input and output respectively The I O state n RESET shows the pin status in the nRESET duration below 4 OSCin nRESET I lt nRESET uud I 1 18 ELECTRONICS 53 2440 RISC MICROPROCESSOR PRODUCT OVERVIEW The table below shows types and descriptions t8 phbsu100ct8sm Bi directional pad LVCMOS schmitt trigger 100 pull up resistor with control tri state lo 8mA t12 phbsu1 00ct12sm Bi directional pad LVCMOS schmitt trigger 100kQ pull up resistor with control tri state lo 12mA d8 phbsd8sm Bi directional pad LVCMOS schmitt trigger open drain lo 8mA t10s phtot1 0 _10_2440 output pad LVCMOS tri state output drive strenth control lo 4 6 8 10mA b12s phtbsu100ct12cd_12_2440a Bi directional pad LVCMOS schmitt trigger 100kQ pull up resistor with control tri state output drive strenth control lo 6 8 10 12mA d2s phtbsd2_2440a Bi directional pad LVCMOS schmitt trigger open drain output drive strenth ignore r50 phoar50_abb
51. 1 2 VDD 1 2 Clock input is from the XTlIpll pin Figure 27 2 XTIpll Clock Timing Diagram tEXTCYC tEXTHIGH tEXTLOW s s tH OO VIH 1 2 Clock input is from the EXTCLK Figure 27 3 EXTCLK Clock Input Timing Diagram EXTCLK N N tEX2HC HCLK internal N Figure 27 4 EXTCLK HCLK case when EXTCLK is used Without the PLL 27 8 ELECTRONICS 53 2440 RISC MICROPROCESSOR ELECTRICAL DATA HCLK internal I gt CLKOUT HCLK I I d tHC2SCLK 4 Figure 27 5 HCLK CLKOUT SCLK case when EXTCLK is used nRESET Figure 27 6 Manual Reset Input Timing Diagram ELECTRONICS 27 9 ELECTRICAL DATA S3C2440A RISC MICROPROCESSOR V PLL can operate after OM 3 2 is latched nRESET or EXTCLK PLL is configured by S W first time lt gt Clock IPLL Disable L VCO is adapted to new clock frequency tRST2RUN 4 mcu operates by FCLK is new frequency or EXTCLK clcok Figure 27 7 Power On Oscillation Setting Timing Diagram 27 10 ELECTRONICS 53 2440 RISC MICROPROCESSOR ELECTRICAL DATA EXTCLK Disable Several slow clocks XTIpll or EXTCLK TT Power_OFF mode is initiated Figure 27 8 Sleep Mode Return Oscillation Setting Timing Diagram ELECTRONICS
52. 15 0 Set count observation value for Timer 0x00000000 Timer 3 observation register 10 18 ELECTRONICS 53 2440 RISC MICROPROCESSOR v m 2 TIMER 4 COUNT BUFFER REGISTER TCNTB4 4 0x5100003C Timer 4 count buffer register 0x00000000 15 0 Set count buffer value for Timer 4 0x00000000 4 Timer 4 count buffer register TIMER 4 COUNT OBSERVATION REGISTER TCNTO4 Timer 4 count observation register 0x00000000 Timer 4 observation register 15 0 Set count observation value for Timer 4 0x00000000 Register Address 4 0 51000040 ELECTRONICS 10 19 PWM TIMER S3C2440A RISC MICROPROCESSOR NOTES 10 20 ELECTRONICS 53 2440 RISC MICROPROCESSOR UART 11 OVERVIEW The S3C2440A Universal Asynchronous Receiver and Transmitter UART provide three independent asynchronous serial I O SIO ports each of which can operate in Interrupt based or DMA based mode In other words the UART can generate an interrupt or a DMA request to transfer data between CPU and the UART The UART can support bit rates up to 115 2K bps using system clock If an external device provides the UART with UEXTCLK then the UART can operate at higher speed Each UART channel contains two 64 byte FIFOs for receiver and transmitter The S3C2440A UART includes programmable baud rates infrared IR transmit receive one or two stop bit insertion 5 bit 6 bit 7 bit or 8 bit data wi
53. 7 3 VD 18 VD 10 or VD 2 and set FRM565 of LCDCONS register to 0 Table 15 4 5 6 5 Format morenos 15 sa ss ww 691656 51415236 Age Rusa we Rt as ae as az co Toana sa ne n es ae as ae er 0 axtoooo Es LI T ern rolce ae as aa 61 co 51 oxtooorrc number vo 22 20 9 5 1 0 56181418 Table 15 5 5 5 5 1 Format morero 16 sa ss 5 s o me nt c as ae co as 80 1 om pal ne c ao ae co se so as 1 j LL ILL 21211111 2111 _ Ge as e ar co se sz so 1 oxtoooorrc 23 22 20 8 e 5 1 0 40000400 is Palette start address 2 VD18 VD10 and VD2 have the same output value l 3 DATA 31 16 is invalid Palette Read Write When the user performs Read Write operation on the palette HSTATUS and VSTATUS of 1 5 register must be checked for Read Write operation is prohibited during the ACTIVE status of HSTATUS and VSTATUS Temporary Palette Configuration The S3C2440A allows the user to fill a frame with one color without complex modi
54. FLTEN23 31 EINT23 30 28 FLTEN22 27 EINT22 26 24 FLTEN21 23 EINT21 22 20 FLTEN20 19 EINT20 18 16 FLTEN19 15 EINT19 14 12 FLTEN18 11 EINT18 10 8 ELECTRONICS Filter enable for EINT23 0 Filter Disable 1 Filter Enable Setting the signaling method of the EINT23 000 Low level 001 High level 01x Falling edge triggered 10x Rising edge triggered 11x Both edge triggered Filter Enable for EINT22 0 Filter Disable 1 Filter Enable Setting the signaling method of the EINT22 000 Low level 001 High level 01x Falling edge triggered 10x Rising edge triggered 11x Both edge triggered Filter Enable for EINT21 0 Filter Disable 1 Filter Enable Setting the signaling method of the EINT21 000 Low level 001 High level 01x Falling edge triggered 10x Rising edge triggered 11x Both edge triggered Filter Enable for EINT20 0 Filter Disable 1 Filter Enable Setting the signaling method of the EINT20 000 Low level 001 High level 01x Falling edge triggered 10x Rising edge triggered 11x Both edge triggered Filter enable for EINT19 0 Filter Disable 1 Filter Enable Setting the signaling method of the EINT19 000 Low level 001 High level 01x Falling edge triggered 10x Rising edge triggered 11x Both edge triggered Filter enable for EINT18 0 Filter Disable 1 Filter Enable Setting the signaling method of the EINT18
55. Imm SUB R13 813 lmm Add Imm to the stack pointer SP NOTE The offset specified by Imm can be up to 508 but must be word aligned ie with bits 1 0 set to 0 since the assembler converts Imm to an 8 bit sign magnitude number before placing it in field SWord7 The condition codes are not set by this instruction INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 4 14 The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction EXAMPLES ADD SP 268 SP R13 SP 268 but don t set the condition codes Note that the THUMB opcode will contain 67 as the Word7 value and 5 0 ADD SP 44 104 SP R13 SP 104 but don t set the condition codes Note that the THUMB opcode will contain 26 as the Word7 value and 5 1 4 30 ELECTRONICS 3 2440 RISC MICROPROCESSOR THUMB INSTRUCTION SET FORMAT 14 PUSH POP REGISTERS 151413 12 11 4 7 0 0 9 8 7 0 Register List 8 PC LR Bit 0 Do not store LR Load 1 Store LR Load PG 11 Load Store Bit 0 Store to memory 1 Load from memory Figure 4 15 Format 14 OPERATION The instructions in this group allow registers 0 7 and optionally LR to be pushed onto the stack and registers 0 7 and optionally PC to be popped off the stack The THUMB assembler syntax is shown in Table 4 15 NOTE The stack is always assumed to be Full Desce
56. Where UBRDIVn should be from 1 to 216 1 but can be set 0 bypass mode only using the UEXTCLK which should be smaller than PCLK For example if the baud rate is 115200 bps and UART clock is 40 MHz UBRDIVn is UBRDIVn int 40000000 115200 x 16 1 z int 21 7 1 round to the nearest whole number 22 1 21 Baud Rate Error Tolerance UART Frame error should be less than 1 87 3 160 tUPCLK UBRDIVn 1 x 16 x 1Frame PCLK tUPCLK Real UART Clock tUEXACT 1Frame baud rate tUEXACT Ideal UART Clock UART error tUPCLK tUEXACT IUEXACT x 100 NOTES 1 1Frame start bit data bit bit stop bit 2 n specific condition we can support the UART baud rate up to 921 6K bps For example when PCLK is 6 2 you can use 921 6 bps under UART error of 1 69 Loopback Mode The S3C2440A UART provides a test mode referred to as the Loopback mode to aid in isolating faults in the communication link This mode structurally enables the connection of RXD and TXD in the UART In this mode therefore transmitted data is received to the receiver via RXD This feature allows the processor to verify the internal transmit and to receive the data path of each SIO channel This mode can be selected by setting the loopback bit in the UART control register UCONn ELECTRONICS 11 7 UART 53 2440 RISC MICROPROCESSOR Infrared IR Mode The S3C2440A UART block supports infrared IR transmission
57. 00000000 Rm 3 0 Source Register 11 4 Source operand is an immediate value 11 8 7 0 7 0 Unsigned 8 bit immediate value 11 8 Shift applied to Imm 31 28 Condition Field Figure 3 11 PSR Transfer ELECTRONICS 3 19 ARM INSTRUCTION SET 53 2440 RISC MICROPROCESSOR RESERVED BITS Only twelve bits of the PSR are defined in ARM920T N Z C V I F T M 4 0 the remaining bits are reserved for use in future versions of the processor Refer to Figure 2 6 for a full description of the PSR bits To ensure the maximum compatibility between ARM920T programs and future processors the following rules should be observed e reserved bits should be preserved while changing the value in a PSR e Programs should not rely on specific values from the reserved bits while checking the PSR status since they may read as one or zero in future processors A read modify write strategy should therefore be used when altering the control bits of any PSR register this involves transferring the appropriate PSR register to a general register using the MRS instruction changing only the relevant bits and then transferring the modified value back to the PSR register using the MSR instruction EXAMPLES The following sequence performs a mode change MRS RO CPSR Take a copy of the CPSR BIC R0 R0 0x1F Clear the mode bits ORR R0 R0 new_mode Select new mode MSR CPSR R0 Write back the modified CPSR
58. 1 An expression which generates an address The assembler will attempt to generate an instruction using the PC as a base anda corrected immediate offset to address the location given by evaluating the expression This will be a PC relative pre indexed address If the address is out of range an error will be generated 2 A pre indexed addressing specification Rn offset of zero Rn lt expression gt offset of lt expression gt bytes Rn Rm offset of contents of index register 3 A post indexed addressing specification Rn lt expression gt offset of lt expression gt bytes Rn Rm offset of contents of index register 4 Rn and Rm are expressions evaluating to a register number If Rn is R15 then the assembler will subtract 8 from the offset value to allow for ARM920T pipelining In this case base write back should not be specified n Writes back the base register set the W bit if is present 3 38 ELECTRONICS 53 2440 RISC MICROPROCESSOR ARM INSTRUCTION SET EXAMPLES LDRH R1 R2 R3 Load R1 from the contents of the halfword address contained in R2 R3 both of which are registers and write back address to R2 STRH R3 R4 4H 4 Store the halfword in R3 at R14 14 but don t write back LDRSB R8 R2 223 Load R8 with the sign extended contents of the byte address contained in R2 and write back R2 223 to R2 LDRNESH R11 RO Conditionally load R11 with the sign extended content
59. 2 15 2 Dither Duty Cycle 15 8 Relation between and CLKVAL TFT HCLK 60 2 15 4 0 25 cron 15 5 55 5 E hades 15 6 MV Value for Each Display 21 1 CODEC clock CODECLK 256 or 384fs 21 2 Usable Serial Bit Clock Frequency IISCLK 16 or 32 or 48fs 23 1 Camera Interface Signal 23 2 Video Timing Reference Codes of ITU 656 Format 27 1 Absolute Maximum Rating 27 2 Recommended Operating Conditions 27 3 Normal PAD DC Electrical Characteristics 27 4 USB DC Electrical Characteristics 27 5 S3C2440 Power Supply Voltage and Current 27 6 Typical Current Decrease by Register 27 7 Clock Timing Constants AN m 27 8 ROM SRAM Bus Timing Constants 27 9 Memory Interface Timing Constants 27 10 External Bus Request Timing 27 11 DMA Controller Module Signal Timing Constants
60. 8 In Interrupt Service Routine ISR auto reload and interrupt request are disabled to stop the timer 9 When the value of the TCNTn is same as the TCMPn the logic level of the TOUTn is changed from low to high 10 Even when the TCNTn reaches 0 the TCNTn is not any more reloaded and the timer is stopped because auto reload has been disabled 11 No more interrupt requests are generated 10 6 ELECTRONICS 53 2440 RISC MICROPROCESSOR PWM TIMER PULSE WIDTH MODULATION PWM Write Write Write TCMPBn 60 TCMPBn 40 TCMPBn 30 Write Write Write TCMPBn 50 TCMPBn 30 TCMPBn Next PWM Value Figure 10 5 Example of PWM PWM function can be implemented by using the TCMPBn PWM frequency is determined by TCNTBn Figure 10 5 shows a PWM value determined by TCMPBn For a higher PWM value decrease the TCMPBn value For a lower PWM value increase the TCMPBn value If an output inverter is enabled the increment decrement may be reversed The double buffering function allows the TCMPBn for the next PWM cycle written at any point in the current PWM cycle by ISR or other routine ELECTRONICS 10 7 PWM TIMER S3C2440A RISC MICROPROCESSOR OUTPUT LEVEL CONTROL Inverter off I I 1 L Inverter on 1 Initial State Period 1 Period 2 Timer Stop Figure 10 6 Inverter On Off The following procedure describes how to maintain TOUT as high or low assume the inverter is off 1 Turn off the
61. Configure MISCCR 1 0 for the pull up resisters on the data bus D 31 0 If there is an external BUS holder such as 74LVCH162245 turn off the pull up resistors If not turn on the pull up resistors Additionally The Memory concerning pins is set to two types one is Hi z and the other is Inactive state 7 Stop LCD by clearing LCDCON1 ENVID bit 8 Read rREFRESH and rCLKCON registers in order to fill the TLB 9 Let SDRAM enter the self refresh mode by setting the REFRESH 22 1b 10 Wait until SDRAM self refresh is effective 11 Set MISCCR 19 17 111b to make SDRAM signals SCLKO SCLK1 and SCKE protected during SLEEP mode 12 Set the SLEEP mode bit in the CLKCON register Caution When the system is operating in NAND boot mode The hardware pin configuration EINT 23 21 must be set as input for starting up after wakeup from sleep mode ELECTRONICS 7 15 CLOCK amp MANAGEMENT S3C2440A RISC MICROPROCESSOR Follow the Procedure to Wake up from SLEEP mode 1 The internal reset signal will be asserted if one of the wake up sources is issued It s exactly same with the case of the assertion of the external nRESET pin This reset duration is determined by the internal 16 bit counter logic and the reset assertion time is calculated as tRST 65535 XTAL frequency 2 Check GSTATUS2 2 in order to know whether or not the power up is caused by the wake up from SLEEP mode Release the SDRAM signal protection by setting
62. Contents of Rm Value of Operand 2 Figure 3 6 Logical Shift Left NOTE LSL 0 is a special case where the shifter carries out is the old value of the CPSR C flag The contents of Rm are used directly as the second operand A Logical Shift Right LSR is similar but the contents of Rm are moved to less significant positions in the result LSR 5 has the effect shown in Figure 3 7 3 12 ELECTRONICS 53 2440 RISC MICROPROCESSOR ARM INSTRUCTION SET 31 5 4 0 Contents of Rm carry out 00000 Value of Operand 2 Figure 3 7 Logical Shift Right The form of the shift field which might be expected to correspond to LSR 0 is used to encode LSR 32 which has a zero result with bit 31 of Rm as the carry output Logical shift right zero is redundant as it is the same as logical shift left zero so the assembler will convert LSR 0 and ASR 0 and ROR 0 into LSL 0 and allow LSR 32 to be specified An Arithmetic Shift Right ASR is similar to logical shift right except that the high bits are filled with bit 31 of Rm instead of zeros This preserves the sign in 2 s complement notation For example ASR 5 is shown in Figure 3 8 5 4 0 Contents of Rm carry out Value of Operand 2 Figure 3 8 Arithmetic Shift Right The form of the shift field which might be expected to give ASR 0 is used to encode ASR 32 Bit 31 of Rm is again used as the carry output and each bit of operand 2 is also eq
63. NOTE All instructions in this group set the CPSR condition codes Table 4 2 Summary of Format 1 Instructions LSL Rd Rs Offset5 MOVS Rs LSL Offset5 Shift Rs left by a 5 bit immediate value and store the result in Rd 01 LSR Rs Offset5 MOVS Rs LSR Offset5 Perform logical shift right on Rs by a 5 bit immediate value and store the result in Rd 10 ASR Rs Offset5 MOVS Rd Rs ASR Offset5 Perform arithmetic shift right on Rs by a 5 bit immediate value and store the result in Rd ELECTRONICS 4 5 THUMB INSTRUCTION SET 53 2440 RISC MICROPROCESSOR INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 4 2 The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction EXAMPLES LSR R2 R5 27 Logical shift right the contents of R5 by 27 and store the result in R2 Set condition codes on the result 4 6 ELECTRONICS 53 2440 RISC MICROPROCESSOR THUMB INSTRUCTION SET FORMAT 2 ADD SUBTRACT 14 11 lo mons 2 0 Destination Register 5 3 Source Register 8 6 Register Immediate Vale 9 Opcode 0 ADD 1 SUB 10 Immediate Flag 0 Register operand 1 Immediate oerand Figure 4 3 Format 2 OPERATION These instructions allow the contents of a Lo register or a 3 bit immediate value to be added to or subtracted fro
64. PORTS Table 9 1 S3C2440A Port Configuration Sheet 2 of 5 Continued Selectable Pin Functions woo ma Gm mur Gee mur me mur Gem Gems Gee Gm mue cmo mue ees maa x amu maoa we C j amu mana ws C j amu imana X j amu imana amu wma we ace imana Y J ame imana we mona o ame maoa tiem ams maoa SS a wapa c J ame mama ww c j ec mama c amo mana iw ELECTRONICS 9 3 PORTS 53 2440 RISC MICROPROCESSOR Table 9 1 53 2440 Port Configuration Sheet 3 of 5 Continued Selectable Pin Functions ono 117 Gm vo ws Gm vo S cmm 7 wm cmm ma vw con ma ww mua Gem v sos Gem
65. STMED SP RO R3 R14 BL somewhere LDMED SP RO R3 R15 3 46 Save RO to R3 to use as workspace and R14 for returning This nested call will overwrite R14 Restore workspace and return ELECTRONICS 53 2440 RISC MICROPROCESSOR ARM INSTRUCTION SET SINGLE DATA SWAP SWP 28 27 23 22 21 20 19 16 15 12 11 ow o9 o o 3 0 Source Register 15 12 Destination Register 19 16 Base Register 22 Byte Word Bit 0 Swap word quantity 1 Swap word quantity 31 28 Condition Field Figure 3 23 Swap Instruction The instruction is only executed if the condition is true The various conditions are defined in Table 3 2 The instruction encoding is shown in Figure 3 23 The data swap instruction is used to swap a byte or word quantity between a register and external memory This instruction is implemented as a memory read followed by a memory write which are locked together the processor cannot be interrupted until both operations have completed and the memory manager is warned to treat them as inseparable This class of instruction is particularly useful for implementing software semaphores The swap address is determined by the contents of the base register Rn The processor first reads the contents of the swap address Then it writes the contents of the source register Rm to the swap address and stores the old memory contents in the destination register Rd The same register may be specif
66. Table 4 1 THUMB Instruction Set Opcodes Lo Register Hi Register Condition Operand Operand Codes Set Add Ee lamin gE v o lt lt 9 LDMIA Load multiple Y hs lage sag or S A v way v _ v 5 lt S lt lt lt lt lt ELECTRONICS 4 3 THUMB INSTRUCTION SET 53 2440 RISC MICROPROCESSOR Table 4 1 THUMB Instruction Set Opcodes Continued pm wem emm Operand Operand Codes Set NEG 1 Y v _ 5 1 PUSH Pushregister x o Y j RoR SBC 22221 lt lt eal swi NOTES 1 The condition codes are unaffected by the format 5 12 and 13 versions of this instruction 2 The condition codes are unaffected by the format 5 version of this instruction 4 4 ELECTRONICS 53 2440 RISC MICROPROCESSOR THUMB INSTRUCTION SET FORMAT 1 MOVE SHIFTED REGISTER 15 14 13 12 11 10 6 5 3 2 0 2 0 Destination Register 5 3 Source Register 10 6 Immediate Vale 12 11 Opcode 0 LSL 1 LSR 2 ASR Figure 4 2 Format 1 OPERATION These instructions move a shifted value between Lo registers The THUMB assembler syntax is shown in Table 4 2
67. The NFSLK and NFEBLK can be changed while Soft lock bit NFCONT 12 is enabled But cannot be changed when Lock tight bit NFCONTT13 is set NAND Flash Memory When NFSBLK NFEBLK Address Locked area High Read only g NFEBLK NFEBLK 1 Prorammable NFSBLK Locked Area Readable NFEBLK gt Read only Area NFSBLK Locked area Read only Low when Lock tight 1 or SoftLock 1 6 22 ELECTRONICS 53 2440 RISC MICROPROCESSOR CLOCK amp POWER MANAGEMENT CLOCK amp POWER MANAGEMENT OVERVIEW The Clock amp Power management block consists of three parts Clock control USB control and Power control The Clock control logic in 3 2440 can generate the required clock signals including FCLK for CPU HCLK for the AHB bus peripherals and PCLK for the APB bus peripherals The S3C2440A has two Phase Locked Loops PLLs one for FCLK HCLK and PCLK and the other dedicated for USB block 48Mhz The clock control logic can make slow clocks without PLL and connect disconnect the clock to each peripheral block by software which will reduce the power consumption For the power control logic the 53 2440 has various power management schemes to keep optimal power consumption for a given task The power management block in the S3C2440A can activate four modes NORMAL mode SLOW mode IDLE mode and SLEEP mode NORMAL mode The block supplies clocks to CPU as well as all peripherals in the S3C2440A In t
68. to clear this bit IN PKT RDY SET CLEAR Set by the MCU after writing a packet of data into EPO FIFO The USB clears this bit once the packet has been successfully sent to the host An interrupt is generated when the USB clears this bit so as the MCU to load the next packet For a zero length data phase the MCU sets DATA END at the same time OUT PKT RDY SET Set by the USB once a valid token is written to the FIFO An interrupt is generated when the USB sets this bit The MCU clears this bit by writing a 1 to the SERVICED OUT PKT RDY bit 13 12 ELECTRONICS 53 2440 RISC MICROPROCESSOR USB DEVICE END POINT IN CONTROL STATUS REGISTER IN CSR1 REG IN CSR2 REG IN 5 1 REG 0x52000184 L R W IN END POINT control status register1 0x00 0x52000187 B byte REG ucu use mew m L CLR DATA R W R Used in set up procedure TOGGLE CLEAR 0 There are alternation of DATAO and DATA1 1 The data toggle bit is cleared and PID in packet will maintain DATAO SENT STALL 5 R SET Set by the USB when an IN token issues a CLEAR STALL handshake after the MCU sets SEND STALL bit to start STALL handshaking When the USB issues a STALL handshake IN PKT RDY is cleared SEND STALL 4 W R 0 The MCU clears this bit to finish the STALL condition 1 The MCU issues a STALL handshake to the USB mew IN PKT RDY R SET CLEAR Set by the after writing a pac
69. 0110 16 bpp for STN color mode 4096 color 1000 1 bpp for TFT 1001 2 bpp for TFT 1010 4 bpp for TFT 1011 8 bpp for TFT 1100 16 bpp for TFT 1101 24 bpp for TFT ENVID LCD video output and the logic enable disable 0 Disable the video output and the LCD control signal 1 Enable the video output and the LCD control signal ELECTRONICS 15 27 LCD CONTROLLER S3C2440A RISC MICROPROCESSOR LCD Control 2 Register LCDCON2 0X4D000004 LCD control 2 register 0x00000000 VBPD 31 24 TFT Vertical back porch is the number of inactive lines at the start of 0x00 a frame after vertical synchronization period STN These bits should be set to zero on STN LCD LINEVAL 23 14 TFT STN These bits determine the vertical size of LCD panel 0000000000 VFPD 13 6 TFT Vertical front porch is the number of inactive lines at the end of a 00000000 frame before vertical synchronization period STN These bits should be set to zero on STN LCD VSPW 5 0 TFT Vertical sync pulse width determines the VSYNC pulse s high 000000 level width by counting the number of inactive lines STN These bits should be set to zero on STN LCD 15 28 ELECTRONICS 53 2440 RISC MICROPROCESSOR LCD CONTROLLER LCD Control 3 Register LCDCON3 0X4D000008 LCD control 3 register 0x00000000 HBPD TFT 25 19 TFT Horizontal back porch is the number of VCLK periods between 0000000 the falling edge of HSYNC and the start of active data
70. 1 Moves the Link Register minus an offset where appropriate to the PC The offset will vary depending on the type of exception Copies the SPSR back to the CPSR Clears the interrupt disable flags if they were set on entry NOTE An explicit switch back to THUMB state is never needed since restoring the CPSR from the SPSR automatically sets the T bit to the value it held immediately prior to the exception 2 10 ELECTRONICS 53 2440 RISC MICROPROCESSOR PROGRAMMER S MODEL Exception Entry Exit Summary Table 2 2 summarizes the PC value preserved in the relevant R14 on exception entry and the recommended instruction for exiting the exception handler Table 2 2 Exception Entry Exit Return Instruction Previous State ARM R14 x THUMB R14 x ma sosro naran pore po ese NOTES 1 Where is the address of the BL SWI Undefined Instruction fetch which had the prefetch abort 2 Where PC is the address of the instruction which did not get executed since the FIQ or IRQ took priority 3 Where PC is the address of the Load or Store instruction which generated the data abort 4 The value saved R14_svc upon reset is unpredictable FIQ The FIQ Fast Interrupt Request exception is designed to support a data transfer or channel process and in ARM state has sufficient private registers to remove the need for register saving thus minimizing the overhead of context switching FIQ is externally generated by taking
71. CAMERA INTERFACE SPECIAL REGISTERS SOURCE FORMAT REGISTER CISRCFMT 0x4F000000 Input source format register ITU601_656n 31 0 ITU R 656 YCbCr 8 bit mode enable 1 ITU R BT 601 YCbCr 8 bit mode enable UVOffset 30 Cb Cr Value Offset Control 0 0 normally used for YCbCr 1 128 for YUV 29 This bit is reserved and the value must be 0 28 16 Source Horizontal Pixel Number must be multiple of 8 422 15 14 Input YcbCr order inform for input 8 bit mode 00 YCbYCr 01 YCrYCb 10 CbYCrY 11 CrYCbY 12 0 Source Vertical Pixel Number NOTE We recommend following sequence for preventing FIFO overflow at first frame of capture operation CODEC path ITU 601 Format 1 CISRCFMT 31 lt 1 2 S W reset 3 Initialize the Camera I F 4 Start Capturing lt ITU 656 Format gt 1 CISRCFMT 31 lt 1 2 S W reset 3 Initialize the Camera I F 4 CISRCFMT 31 lt 0 for ITU 656 format 6 Start Capturing 7 Clear Overflow of codec on First ISR ELECTRONICS 23 11 53 2440 RISC MICROPROCESSOR CAMERA INTERFACE WINDOW OPTION REGISTER CIWDOFST 0x4F000004 Window offset register WinOfsEn 31 0 No offset 1 Window offset enable ClrOvCoFiY 30 0 Normal 1 Clear the overflow indication flag of input CODEC FIFO Y WinHorOfst 26 16 Window Horizontal Offset the number which is the horizontal pixels except WinHorOfst 2 must b
72. Figure 11 1 UART Block Diagram with FIFO 11 2 ELECTRONICS 53 2440 RISC MICROPROCESSOR UART UART OPERATION The following sections describe the UART operations that include data transmission data reception interrupt generation baud rate generation Loopback mode Infrared mode and auto flow control Data Transmission The data frame for transmission is programmable It consists of a start bit 5 to 8 data bits an optional parity bit and 1 to 2 stop bits which can be specified by the line control register ULCONn The transmitter can also produce the break condition which forces the serial output to logic 0 state for one frame transmission time This block transmits break signals after the present transmission word is transmitted completely After the break signal transmission it continuously transmits data into the Tx FIFO Tx holding register in the case of Non FIFO mode Data Reception Like the transmission the data frame for reception is also programmable It consists of a start bit 5 to 8 data bits an optional parity bit and 1 to 2 stop bits in the line control register ULCONn The receiver can detect overrun error parity error frame error and break condition each of which can set an error flag The overrun error indicates that new data has overwritten the old data before the old data has been read The parity error indicates that the receiver has detected an unexpected parity condition The frame error
73. Pmomv W meno RW Interrupt request status INTOFFSET _R__ Intenupt request source ofset 5 _ RW source pending RW um ELECTRONICS 1 27 PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR Table 1 4 S3C2440A Special Registers Sheet 3 of 14 Continued Register Address Address Read Name B Endian L Endian Write A T osmcoo oum posto oaeo destination comro coo oun owmeou R Doom osoo 2 oem omao curent destinan Fw DAO mask tigger oem Opo mero Soma niar source comro oos oue owmoxoc TOMA nitan destination comro cow oues OA court oues oer oq destination MAT mask tigger sro osoo 2 source
74. RT C RTCCON 0 57000043 0 57000040 TICNT 0x57000047 05700004 Tick time count 0657000057 remsen i www 0670000668 Wemmmte i o 6700006F i 07000063 wv ome remm 07000088 msrooe 77 wsmomo scoww 0657000077 Emme osmoor oemew r copy 67000086 eme feco mon 057000088 ELECTRONICS 1 37 PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR Table 1 4 S3C2440A Special Registers Sheet 13 of 14 Continued atm 900 B Endian L Endian Write fabo toun soren cono xp acenso xov ooo ossoa RW Smis up or down satus C sistas sewer 016900000828 RW sens semp sew oswwoosn momo n soe osumw O Teor commana aromen socco
75. This CrcSta flag is cleared by setting to one this bit 0 Not detect 1 Crc status fail Data receive Data block received error CRC check failed This flag is cleared by CRC fail DatCrc Setting to one this bit 0 Not detect 1 Receive crc fail Data time out Data Busy receive timeout This flag is cleared by setting to one DatTout this bit 0 Not detect 1 Timeout Data transfer Data transfer completes data counter is zero This flag is cleared finish DatFin by setting to one this bit 0 Not detect 1 Data finish detect Busy finish Only busy check finish This flag is cleared by setting to one this BusyFin bit 0 Not detect 1 Busy finish detect Reseved 1 Data transmit progress on TxDatOn 0 Not active 1 Data Tx in progress Rx data progress Data receive in progress on RxDatOn 0 Not active 1 Data Rx in progress ELECTRONICS 19 11 MMC SD SDIO CONTROLLER 53 2440 RISC MICROPROCESSOR SDI Fifo Status Register SDIFSTA SDIFSTA 0x5A000038 SDI FIFO status register 0x0 FIFO reset FRST 16 Reset FIFO value This bit is automatically cleared 0 Normal mode 1 FIFO reset FIFO fail error FFfail 15 14 FIFO fail error when FIFO occurs overrun underrun data saving This flag is cleared by setting to one these bits 00 Not detect 01 FIFO fail 10 FIFO fail in the last transfer only FIFO reset nee
76. URXH1 0x50004024 L R UART channel 1 receive buffer register 0x50004027 B by byte URXH2 0x50008024 L R UART channel 2 receive buffer register 0x50008027 B by byte RXDATAn 7 0 Receive data for UARTn fF s o NOTE When an overrun error occurs the URXHn must be read If not the next received data will also make an overrun error even though the overrun bit of UERSTATn had been cleared 11 20 ELECTRONICS 53 2440 RISC MICROPROCESSOR UART UART BAUD RATE DIVISOR REGISTER There are three UART baud rate divisor registers including UBRDIV0 UBRDIV1 and UBRDIV2 in the UART block The value stored in the baud rate divisor register UBRDIVn is used to determine the serial Tx Rx clock rate baud rate as follows UBRDIVn int UART clock buad rate x 16 1 UART clock PCLK FCLK n or UEXTCLK Where UBRDIVn should be from 1 to 216 1 but can be set zero only using the UEXTCLK which should be smaller than PCLK For example if the baud rate is 115200 bps and UART clock is 40 MHz UBRDIVn is UBRDIVn int 40000000 115200 x 16 1 int 21 7 1 round to the nearest whole number 22 1 21 mw Smdraedwsermgsero usao 0600425 Smdraedwsermgsert orsoooecze mw Smdraedwsoregserz UBRDIV 15 0 Baud rate division value UBRDIVn gt 0 Using the UEXTCLK as input clock UBRDIVn can be set 0 ELECTRONICS 11 21 U
77. When the aim is simply to change the condition code flags in a PSR a value can be written directly to the flag bits without disturbing the control bits The following instruction sets the N Z C and V flags MSR CPSR flg 0xF0000000 Set all the flags regardless of their previous state does not affect any control bits No attempt should be made to write an 8 bit immediate value into the whole PSR since such an operation cannot preserve the reserved bits INSTRUCTION CYCLE TIMES PSR transfers take 1S incremental cycles where S is defined as Sequential S cycle 3 20 ELECTRONICS 53 2440 RISC MICROPROCESSOR ARM INSTRUCTION SET ASSEMBLY SYNTAX e MRS transfer PSR contents to a register Rd lt psr gt MSR transfer register contents to PSR MSR cond lt psr gt Rm e MSR transfer register contents to PSR flag bits only MSR cond lt psrf gt Rm The most significant four bits of the register contents are written to the N Z C amp V flags respectively e MSR transfer immediate value to PSR flag bits only MSR cond lt psrf gt lt expression gt The expression should symbolise a 32 bit value of which the most significant four bits are written to the N Z C and V flags respectively Key cond Two character condition mnemonic See Table 3 2 Rd and Rm Expressions evaluating to a register number other than R15 lt psr gt CPSR CPSR all SPSR or SPSR all CPSR and CPSR all are synonyms as
78. ame ma Tm amo v maoa cawreser emn ens mona caso eme cow eme mona cavone ems cows cma cow Gm mona Gus mana comm i eme 7 cabo 9 6 ELECTRONICS 53 2440 RISC MICROPROCESSOR PORTS PORT CONTROL DESCRIPTIONS PORT CONFIGURATION REGISTER GPACON GPJCON In S3C2440A most of the pins are multiplexed pins So It is determined which function is selected for each pins The PnCON port control register determines which function is used for each pin If PEO PE7 is used for the wakeup signal in power down mode these ports must be configured in interrupt mode PORT DATA REGISTER GPADAT GPJDAT If Ports are configured as output ports data can be written to the corresponding bit of PnDAT If Ports are configured as input ports the data can be read from the corresponding bit of PnDAT PORT PULL UP REGISTER GPBUP GPJUP The port pull up register controls the pull up resister enable disable of each port group When the corresponding bit is 0 the pull up resister of the pin
79. instructions take 15 b 1 l 1 incremental cycles to execute where S and are defined as sequential S cycle internal and coprocessor register transfer C cycle respectively MCR instructions take 1S bl 1 incremental cycles to execute where b is the number of cycles spent in the coprocessor busy wait loop ASSEMBLER SYNTAX MCR MRC cond p lt expression1 gt Rd cn cm lt expression2 gt MRC Move from coprocessor to ARM920T register L 1 MCR Move from ARM920T register to coprocessor L 0 cond Two character condition mnemonic See Table 3 2 p The unique number of the required coprocessor lt expression1 gt Evaluated to a constant and placed in the CP Opc field Rd An expression evaluating to a valid ARM920T register number cn and cm Expressions evaluating to the valid coprocessor register numbers CRn and CRm respectively lt expression2 gt Where present is evaluated to a constant and placed in the CP field EXAMPLES MRC p2 5 R3 c5 c6 Request coproc 2 to perform operation 5 c5 and transfer the single 32 bit word result back to R3 MCR p6 0 R4 c5 c6 Request coproc 6 to perform operation 0 on R4 and place the result in c6 MRCEQ p3 9 R3 c5 c6 2 Conditionally request coproc 3 to perform operation 9 type 2 on c5 and c6 and transfer the result back to ELECTRONICS 3 57 ARM INSTRUCTION SET 53 2440 RISC MICROPROCESSOR UNDEFINED INSTRUCTION Th
80. 0 illegal access is not detected 1 illegal access is detected nCE Read only status of output RnB Read only The status of RnB input 0 NAND Flash memory busy 1 NAND Flash memory ready to operate RnB TransDetect 2 When RnB low to high transition is occurred this value set and issue interrupt if enabled To clear this value write 1 0 RnB transition is not detected 1 RnB transition is detected Transition configuration is set in TransMode 8 6 18 ELECTRONICS 53 2440 RISC MICROPROCESSOR NAND FLASH CONTROLLER ECC0 1 STATUS REGISTER NFESTATO 0 4 000024 flash ECC Status register for I O 7 0 0 00000000 NFESTAT1 0 4 000028 flash ECC status register for 15 8 0 00000000 SErrorDataNo 24 21 In spare area Indicates which number data is error SErrorBitNo 20 18 In spare area Indicates which bit is error 00 MErrorDataNo 17 7 main data area Indicates which number data is error MErrorBitNo 6 4 In main data area Indicates which bit is error 00 SpareError 3 2 Indicates whether spare area bit fail error occurred 00 No Error 01 1 bit error correctable 10 Multiple error 11 ECC area error MainError 1 0 Indicates whether main data area bit fail error occurred 00 No Error 01 1 bit error correctable 10 Multiple error 11 ECC area error NOTE The above values are only valid when both EC
81. 011 Active 100 LP 101 Warm AC97 CODEC COMMAND REGISTER AC_CODEC_CMD AC_CODEC_CMD 0x5B000008 AC97 codec command register 0x00000000 Read enable 23 0 Command write NOTE 1 Status read 22 16 CODEC command address Data 15 0 CODEC command data 0x0000 NOTE When the commands are written on the AC_CODDEC_CMD register it is recommended that the delay time between the command and the next command is more than 1 48 Hz 24 10 ELECTRONICS 53 2440 RISC MICROPROCESSOR AC97 CONTROLLER AC97 CODEC STATUS REGISTER AC_CODEC_STAT CODEC STAT 0x5B00000C AC97 codec status register 0x00000000 WES m Data 15 0 CODEC status data 0x0000 NTOES If you want to read data from AC97 codec register via the AC CODEC STAT register you should follow these steps 1 Write command address and data on the AC CODEC register with Bit 23 21 2 Have delay time 3 Read command address and data from CODEC STAT register AC97 PCM OUT IN CHANNEL FIFO ADDRESS REGISTER AC PCMADDR AC PCMADDR 0x5B000010 EN AC97 PCM out in channel FIFO address 0 00000000 register Out read address 27 24 PCM out channel FIFO read address 0000 0000 Reserved 23 20 In read address 19 16 PCM in channel FIFO read address 0000 ELECTRONICS 24 11 97 CONTROLLER 53 2440 RISC MICROPROCESSOR AC97 MIC IN CHANNEL FIFO ADDRESS REGISTER AC MICADDR AC MICADDR 0
82. 0600000 oxsoo08008 _ UART2TWRxsiaus fuensrare oso jursrare oso 0006 ume 0660008023 UARTZvensmssontod 2 0660008027 1 32 ELECTRONICS 53 2440 RISC MICROPROCESSOR PRODUCT OVERVIEW Table 1 4 S3C2440A Special Registers Sheet 8 of 14 Continued fm e 0 B Endian L Endian Write Timer count buffer 0 count obsewation RW Tmecwntufers 7 2 TCNTO2 TCNTB3 TCMPB3 TCNTB4 TCNTO4 ELECTRONICS 1 33 PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR Table 1 4 S3C2440A Special Registers Sheet 9 of 14 Continued e mm B Endian L Endian Write FUNC ADDR 0x52000143 0x52000140 R W Function address PWR REG 0 52000147 0 52000144 7 Power management INT REG 052000148 Ox52000148 EP interrupt pending and clear USB INT REG 0662000158 06200158 __ USB interrupt pending and EP INT EN REG 0 5200015 0 52000150 _ imtemuptenabe USB INT EN REG 0 5200016 0 52000160
83. 0x77 1 0x91580 Example 3 LCD panel 320 240 color single scan Frame start address 0x0c500000 Offset dot number 1024 dots 512 half words LINEVAL 240 1 Oxef PAGEWIDTH 320 x 8 16 0 OFFSIZE 512 0 200 LCDBANK 0x0c500000 gt gt 22 0x31 LCDBASEU 0 100000 gt gt 1 0x80000 LCDBASEL 0x80000 0 0x200 x 0xef 1 0xa7600 15 34 ELECTRONICS 53 2440 RISC MICROPROCESSOR LCD CONTROLLER RED Lookup Table Register REDLUT 0X4D000020 STN Red lookup table register 0x00000000 REDVAL 31 0 These bits define which of the 16 shades will be chosen by each of 0x00000000 the 8 possible red combinations 000 REDVAL 3 0 001 REDVAL 7 4 010 REDVAL 1 1 8 011 REDVAL 15 12 100 REDVAL 19 16 101 REDVAL 23 20 110 REDVAL 27 24 111 31 28 GREEN Lookup Table Register GREENLUT 0 40000024 R W STN Green lookup table register 0x00000000 GREENVAL 31 0 These bits define which of the 16 shades will be chosen by each of 0x00000000 the 8 possible green combinations 000 GREENVAL 3 0 001 GREENVAL 7 4 010 GREENVAL 1 1 8 011 GREENVAL 15 12 100 GREENVAL 19 16 101 GREENVAL 23 20 110 GREENVAL 27 24 111 2 GREENVAL 31 28 BLUE Lookup Table Register BLUELUT 0 40000028 R W STN Blue lookup table register 0x0000 BLUEVAL 15 0 These bits define which of the 16 shades will be chosen by each of 0x0000 th
84. 1 else PreVerRatio xx 1 V Shift 0 PreDstHeight xx SRC Height PreVerRatio xx MainVerRatio xx 5 Height lt lt 8 DST Height lt lt V Shift SHfactor xx 10 H_Shit V Shift NOTE Preview path contains 640 pixel line buffer Codec path contains 2048 pixel line buffer So upper 1280 pixels input images must be pre scaled by over 1 2 for capturing valid preview image SourceHsize 2 WinHorOfst PreHorRatio Pr lt 640 CODEC PRE SCALER CONTROL REGISTER 1 CICOSCPRERATIO Ox4F000050 Codec pre scaler ratio control SHfactor Co 31 28 Shift factor for codec pre scaler PreHorRatio Co 22 16 Horizontal ratio of codec pre scaler PreVerRatio Co 6 0 Vertical ratio of codec pre scaler CODEC PRE SCALER CONTROL REGISTER 2 CICOSCPREDST Ox4F000054 Codec pre scaler destination format PreDstWidth_Co 27 16 Destination width for codec pre scaler PreDstHeight Co 11 0 Destination height for codec pre scaler um ELECTRONICS 23 21 53 2440 RISC MICROPROCESSOR CAMERA INTERFACE CODEC MAIN SCALER CONTROL REGISTER CICOSCCTRL 0x4F000058 Codec main scaler control ScalerBypass Co Codec scaler bypass for upper 2048 x 2048 size In this case ImgCptEn CoSC and ImgCptEn PrSC should be 0 but ImgCptEn should be 1 It is not allowed to capture preview image This mode is intended to capture JPEG input image for DSC application In this case input pixel bufferi
85. 16 Example 1 Target image size QCIF for RGB 32 01 format horizontal width 176 pixels 1 pixel 1 word 176 pixel 2 176 word 176 96 16 20 gt main burst 16 remained burst 16 Example 2 Target image size VGA for RGB 16 bit format horizontal width 640 pixels 2 pixel 1 word 640 2 320 word 160 16 0 main burst 16 remained burst 16 PREVIEW PRE SCALER CONTROL REGISTER 1 CIPRSCPRERATIO Ox4F000084 Preview pre scaler ratio control SHfactor Pr 31 28 Shift factor for preview pre scaler PreHorRatio Pr 22 16 Horizontal ratio of preview pre scaler PreVerRatio Pr 6 0 Vertical ratio of preview pre scaler EE ELECTRONICS 23 25 53 2440 RISC MICROPROCESSOR CAMERA INTERFACE PREVIEW PRE SCALER CONTROL REGISTER 2 CIPRSCPREDST 0x4F000088 Preview pre scaler destination format PreDstWidth_Pr 27 16 Destination width for preview pre scaler PreDstHeight Pr 11 0 Destination height for preview pre scaler PREVIEW MAIN SCALER CONTROL REGISTER CICOSCCTRL Bit Description Initial State Sample Pr 31 Sampling method for format conversion This bit is recommended to fix 1 RGBformat Pr 30 0 16 bit RGB 1 24 bit RGB ScaleUpDown Pr 29 28 Scale up down flag for preview scaler In 1 1 scale ratio this bit should be 1 00 down 11 up MainHorRatio Pr 24 16 Horizontal scale ratio for preview main scaler PrScalerStart 15 Preview scaler start MainV
86. 19 16 Destination Register 20 Set Condition Code 0 Do not after condition codes 1 Set condition codes 21 Accumulate 0 Multiply only 1 Multiply and accumulate 31 28 Condition Field Figure 3 12 Multiply Instructions The multiply form of the instruction gives Rd Rm Rs Rn is ignored and should be set to zero for compatibility with possible future upgrades to the instruction set The multiply accumulate form gives Rd Rm Rs Rn which can save an explicit ADD instruction in some circumstances Both forms of the instruction work on operands which may be considered as signed 2 s complement or unsigned integers The results of a signed multiply and of an unsigned multiply of 32 bit operands differ only in the upper 32 bits the low 32 bits of the signed and unsigned results are identical As these instructions only produce the low 32 bits of a multiply they can be used for both signed and unsigned multiplies For example consider the multiplication of the operands Operand A Operand B Result OxFFFFFFF6 0 0000001 OxFFFFFF38 3 22 ELECTRONICS 53 2440 RISC MICROPROCESSOR ARM INSTRUCTION SET If the Operands Are Interpreted as Signed Operand A has the value 10 operand B has the value 20 and the result is 200 which is correctly represented as OxFFFFFF38 If the Operands Are Interpreted as Unsigned Operand A has the value 4294967286 operand B has the value 20 and the result is 85899345720 which is represent
87. 258 1 0 258 Endpoint4 unit counter register 0x25C L 0x25F B Endpoint4 DMA FIFO counter register 0x260 L 0 263 Endpoint4 DMA transfer counter low 0x264 L 0x267 B byte register Endpoint4 DMA transfer counter 0x268 L 0x26B B middle byte register Endpoint4 transfer counter high 0x26C L 0x26F B byte register Endpoint MAX packet register 0x180 L 0x183 B EP In control status register 1 EP0 0x184 L 0x187 B control status register EP In control status register 2 0x188 L 0x18B B 041941 04197 04981 048611 Endpoint3 DMA transfer counter 0x250 L 0 253 middle byte register ELECTRONICS 53 2440 RISC MICROPROCESSOR USB DEVICE FUNCTION ADDRESS REGISTER FUNC ADDR REG This register maintains the USB device controller address assigned by the host The Micro Controller Unit MCU writes the value received through a SET ADDRESS descriptor to this register This address is used for the next token FUNC ADDR REG 0x52000140 L Function address register 0x00 0x52000143 B byte ADDR_UPDATE 7 Set by the MCU whenever it updates the EIE FUNCTION ADDR field in this register This bit will be cleared by USB when DATA END bit in register FUNCTION ADDR R W The MCU write the unique address assigned by host to this field ELECTRONICS 13 5 USB S3C2440A RISC MICROPROCESSOR POWER MANAGE
88. Base Register 11 Load Store Bit 0 Store to memory 1 2 Load from memory Figure 4 16 Format 15 OPERATION These instructions allow multiple loading and storing of Lo registers The THUMB assembler syntax is shown in the following table Table 4 16 The Multiple Load Store Instructions STMIA Rb Rlist STMIA Rb Rlist Store the registers specified by Rlist starting at the base address in Rb Write back the new base address LDMIA LDMIA Rlist Load the registers specified by Rlist starting at the base address in Rb Write back the new base address INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 4 16 The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction EXAMPLES STMIA RO 3 7 Store the contents of registers R3 R7 starting the address specified in RO incrementing the addresses for each word Write back the updated value of RO ELECTRONICS 4 33 THUMB INSTRUCTION SET S3C2440A RISC MICROPROCESSOR FORMAT 16 CONDITIONAL BRANCH 15 11 8 7 0 14 13 12 _ 7 0 8 bit Signed Immediate 11 8 Condition Figure 4 17 Format 16 OPERATION The instructions in this group all perform a conditional Branch depending on the state of the CPSR condition codes The branch offset must take account of the prefetch operation w
89. CURRENT DESTINATION DCDST REGISTER DCDSTO 0 4 00001 0 current destination register 0x00000000 DCDST2 0 4 00009 2 current destination register 0x00000000 DCDST3 0 4 00000 3 current destination register 0x00000000 CURR DST 30 0 Current destination address for DMAn 0x00000000 DCDST1 0x4B00005C R DMA 1 current destination register 0x00000000 ELECTRONICS 8 13 S3C2440A RISC MICROPROCESSOR DMA MASK TRIGGER DMASKTRIG REGISTER 0400020 mw BMAD mask vggerregiter 60 mw DMA 1 masictioger reger 99 mw owo oweskrmGs mw ow STOP 2 Stop the DMA operation 1 DMA stops as soon as the current atomic transfer ends If there is no current running atomic transfer DMA stops immediately The CURR TC CURR SRC and CURR DST will be 0 Note Due to possible current atomic transfer stop operation may take several cycles The finish of the operation i e actual stop time can be detected as soon as the channel on off bit DMASKTRIGn 1 is set to off This stop is actual stop ON OFF 1 DMA channel on off bit 0 DMA channel is turned off DMA request to this channel is ignored 1 DMA channel is turned on and the DMA request is handled This bit is automatically set to off if we set the DCONn
90. DatFin Interrupt Enable DatFinInt Determines SDI generate an interrupt if data counter is zero RWaitReq Interrupt 13 Determines SDI generate an interrupt if read wait request occur Enable RWReqlnt 0 Disable 1 Interrupt enable DatTout Interrupt Determines SDI generate an interrupt if data receive timeout Enable DatToutlnt occurs 0 Disable 1 Interrupt enable 0 Disable 1 Interrupt enable ELECTRONICS 19 13 50 50 CONTROLLER S3C2440A RISC MICROPROCESSOR SDI Interrupt Mask Register SDIIntMsk Continued BusyFin Interrupt Determines SDI generate an interrupt if only busy check Enable BusyFinlnt completes 0 Disable 1 Interrupt enable TFHalf Interrupt 4 Determines SDI generate an interrupt if Tx FIFO fills half Enable TFHalflnt 0 Disable 1 Interrupt enable TFEmpty Interrupt 3 Determines SDI generate an interrupt if Tx FIFO is empty Enable TF Emptint 0 Disable 1 Interrupt enable EN RFLast Interrupt 2 Determines SDI generate an interrupt if Rx FIFO has last data Enable RFLastint 0 Disable 1 Interrupt enable RFFull Interrupt 1 Determines SDI generate an interrupt if Rx FIFO fills full Enable RFFullint EE 0 Disable 1 Interrupt enable E RFHalf Interrupt Determines SDI generate an interrupt if Rx FIFO fills half Enable RFHalfInt 0 Disable 1 Interrupt enable BN SDI Data Register SDIDAT SDIDAT 0x5A000040 44 48 SDI data register 4
91. H16 nRESET nRESET L 0 G E B N O 9 I 9 C 04 5 05 5 6 1 4 5 01 5 F6 2 3 4 D3 2 D2 9 d ELECTRONICS 1 13 PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR Table 1 2 53 2440 289 Pin FBGA Pin Assignments Sheet 5 of 9 Continued nGCS7 nSRAS nWAIT TOUTO GPBO 2 0 gt ep H15 5 0 117 TXD2 nRTS1 GPH6 RXD2 nCTS1 GPH7 J15 K15 OE 06 ELM 6 fw EN _5 EM EN EUM EN os NUM 205 CLKOUT1 GPH10 vaoa Default Function Ly nXBACK GPB5 GPB5 nXBREQ GPB6 GPB6 GPH7 State State State REQ 22 nRESET 1105 1105 1105 1105 t12 t12 ELECTRONICS 53 2440 RISC MICROPROCESSOR PRODUCT OVERVIEW Table 1 2 53 2440 289 Pin FBGA Pin Assignments Sheet 6 of 9 Continued Function BUS REQ Sleep nRESET Type 00 uos oU HESLRCK AC SYNC H H H IPSLRCK AC SYNC _ i K1 SCLK1 i O SCLK 2 F I2SSCLK AC_BIT_CLK F L 2 2 2 2 4 B3 P7 R7 17 L8 U6 N8 K8 J9 K9 L9 U8 L1 L4 M1 L7 M4 2 1 2 L6 k o M
92. It is cleard by writing 1 0 Not occur 1 Occur interrupt It is cleard by writing 1 0 Not occur 1 Occur interrupt It is cleard by writing 1 0 Not occur 1 Occur interrupt It is cleard by writing 1 0 Not occur 1 Occur interrupt It is cleard by writing 1 0 Not occur 1 Occur interrupt PORTS 9 33 PORTS 53 2440 RISC MICROPROCESSOR 9 34 ELECTRONICS 53 2440 RISC MICROPROCESSOR PORTS GSTATUSn General Status Registers GSTATUSO oeste Gems n oo Status of BATT_FLT pin CHIP ID ID register 0x32440001 WDTRST 2 Boot is caused by Watch Dog Reset cleared by writing 1 SLEEPRST Boot is caused by wakeup reset in sleep mode cleared by writing 1 PWRST Boot is caused by power on reset cleared by writing 1 inform 31 0 Inform register This register is cleard by power on reset Otherwise preserve data value inform 31 0 Inform register This register is cleard by power on reset Otherwise preserve data value ELECTRONICS 9 35 PORTS 53 2440 RISC MICROPROCESSOR DSCn Drive Strength Control Control the Memory I O drive strength DSC0 0x560000c4 Strength control register 0 DSC1 0x560000c8 Strength control register 1 nEN_DSC 81 Enable Drive Strength Control 0 enable
93. RISC MICROPROCESSOR CAMERA INTERFACE FRAME MEMORY HIRERARCHY Frame memories consist of four ping pong memories for each of P and C paths as shown in the Figure 23 6 C path ping pong memories have three element memories luminance Y chrominance Cb and chrominance Cr If AHB bus traffic is not enough for the DMA operation to complete during one horizontal line period it may lead to mal functioning PLL USB PLL Variable S3C2440A 96 MHz Freq Divide Divide Normally use fmpil d Schmit External triggered Camera Level shifter Processor XT Y ler External MCLK Figure 23 5 CAMIF Clock Generation 23 6 ELECTRONICS 53 2440 RISC MICROPROCESSOR CAMERA INTERFACE 4 Pingpong Frame Memory SDRAM P port RGB 1 P port RGB 2 P port RGB 3 4 P port RGB 4 ITU 601 656 YCbCr AHB bus amp 4 2 2 Camera Interface 8 Memorycontroller 8 bits e Figure 23 6 Ping Pong Memory Hierarchy ELECTRONICS 23 7 53 2440 RISC MICROPROCESSOR CAMERA INTERFACE MEMORY STORING METHOD The little endian method in codec path is used to store in the frame memory The pixels are stored from LSB to MSB side AHB bus carries 32 bit word data So CAMIF makes each of the Y Cb Cr words in little endian style For preview path two different formats exist One pixel Color 1 pixel is one word for RGB 24 bit format Otherwise two pixels are one word for RGB 16 bit format Please refer the following figure P Little endian
94. RISC MICROPROCESSOR IIC BUS INTERFACE FLOWCHARTS OF OPERATIONS IN EACH MODE The following steps must be executed before any Tx Rx operations 1 Write own slave address on IICADD register if needed 2 Set IICCON register Enable interrupt b Define SCL period 3 Set IICSTAT to enable Serial Output START Master Tx mode has been configured Write slave address to IICDS Write OxFO M T Start to IICSTAT The data of the IICDS is transmitted ACK period and then interrupt is pending 2 N Write new data Write 0xD0 M T transmitted to IICDS Stop to IICSTAT Clear pending bit to resume Clear pending bit The data of the IICDS is Wait until the stop shifted to SDA condition takes effect Figure 20 6 Operations for Master Transmitter Mode ELECTRONICS 20 7 IIC BUS INTERFACE 53 2440 RISC MICROPROCESSOR Master Rx mode has been configured START Write slave address to IICDS Write OXBO Start to IICSTAT The data of the IICDS slave address is transmitted ACK period and then interrupt is pending Read new data Write 0x90 M R IICDS Stop to IICSTAT Clear pending bit to resume Clear pending bit Wait until the stop condition takes effect SDA is shifted to IICDS Figure 20 7 Operations for Master Receiver Mode 20 8 ELECTRONICS 53 2440 RISC MICROPROCESSOR IIC BUS INTERFACE START Slave Tx mode has been c
95. Sequential Fixed 1 Reserved 2 0 Burst length 000 1 Fixed Others Reserved NOTE MRSR register must not be reconfigured while the code is running on SDRAM IMPORTANT NOTE In sleep mode sdram has to enter sdram self refresh mode 5 20 ELECTRONICS 53 2440 RISC MICROPROCESSOR NAND FLASH CONTROLLER NAND FLASH CONTORLLER OVERVIEW In recent times NOR flash memory gets high in price while an SDRAM and a NAND flash memory is comparatively economical motivating some users to execute the boot code on a NAND flash and execute the main code on an SDRAM S3C2440A boot code can be executed on an external NAND flash memory In order to support NAND flash boot loader the S3C2440A is equipped with an internal SRAM buffer called Steppingstone When booting the first 4 KBytes of the NAND flash memory will be loaded into Steppingstone and the boot code loaded into Steppingstone will be executed Generally the boot code will copy NAND flash content to SDRAM Using hardware ECC the NAND flash data validity will be checked Upon the completion of the copy the main program will be executed on the SDRAM FEATURES 1 Auto boot The boot code is transferred into 4 kbytes Steppingstone during reset After the transfer the boot code will be executed on the Steppingstone NAND Flash memory 1 Support 256Words 512Bytes 1KWords and 2KBytes Page Software mode User can directly access NAND flash memory for example this feature c
96. The application program needs no knowledge of the amount of memory available to it nor is its state in any way affected by the abort After fixing the reason for the abort the handler should execute the following irrespective of the state ARM or Thumb SUBS PC R14_abt 4 fora prefetch abort or SUBS PC R14 abt 48 for a data abort This restores both the PC and the CPSR and retries the aborted instruction 2 12 ELECTRONICS 53 2440 RISC MICROPROCESSOR PROGRAMMER S MODEL Software Interrupt The Software Interrupt Instruction SWI is used for entering Supervisor mode usually to request a particular supervisor function A SWI handler should return by executing the following irrespective of the state ARM or Thumb MOV PC R14_svc This restores the PC and CPSR and returns to the instruction following the SWI NOTE nFIQ nIRQ ISYNC LOCK BIGEND and ABORT pins exist only in the ARM920T CPU core Undefined Instruction When 920 comes across an instruction which cannot be handled it takes the undefined instruction trap This mechanism may be used to extend either the THUMB or ARM instruction set by software emulation After emulating the failed instruction the trap handler should execute the following irrespective of the state ARM or Thumb MOVS PC R14 und This restores the CPSR and returns to the instruction following the undefined instruction Exception Vectors The following table shows the excepti
97. The assembler will adjust the offset appropriately ELECTRONICS 3 55 ARM INSTRUCTION SET 53 2440 RISC MICROPROCESSOR COPROCESSOR REGISTER TRANSFERS MRC MCR The instruction is only executed if the condition is true The various conditions are defined in Table 3 2 The instruction encoding is shown in Figure 3 27 This class of instruction is used to communicate information directly between ARM920T and a coprocessor An example of a coprocessor to 920 register transfer instruction would FIX of a floating point value held in a coprocessor where the floating point number is converted into a 32 bit integer within the coprocessor and the result is then transferred to ARM920T register A FLOAT of a 32 bit value in ARM920T register into a floating point value within the coprocessor illustrates the use of 920 register to coprocessor transfer MCR An important use of this instruction is to communicate control information directly from the coprocessor into the 920 CPSR flags As an example the result of a comparison of two floating point values within a coprocessor can be moved to the CPSR to control the subsequent flow of execution 31 28 27 24 23 21 20 19 16 15 12 11 8 7 543 om 3 0 Coprocessor Operand Register 7 5 Coprocessor Information 11 8 Coprocessor Number 15 12 ARM Source Destination Register 19 16 Coprocessor Source Destination
98. Update TCNTB3 TCMPB3 Timer 3 start stop 16 Determine start stop for Timer 3 0 Stop 1 Start for Timer 3 Timer 2 auto reload on off 15 Determine auto reload on off for Timer 2 0 One shot 1 Interval mode auto reload Timer 2 output inverter on off 14 Determine output inverter on off for Timer 2 0 Inverter off 1 Inverter on for TOUT2 Timer 2 manual update note 13 Determine the manual update for Timer 2 0 operation 1 Update 2 TCMPB2 Timer 2 start stop 12 Determine start stop for Timer 2 0 Stop 1 Start for Timer 2 Timer 1 auto reload on off 11 Determine the auto reload on off for Timer1 0 One shot 1 Interval mode auto reload Timer 1 output inverter on off 10 Determine the output inverter on off for Timer1 0 Inverter off 1 Inverter on for TOUT1 Timer 1 manual update note 9 Determine the manual update for Timer 1 0 operation 1 Update TCNTB1 TCMPB1 Timer 1 start stop 8 Determine start stop for Timer 1 0 Stop 1 Start for Timer 1 NOTE The bits have to be cleared at next writing ELECTRONICS 10 13 PWM TIMER S3C2440A RISC MICROPROCESSOR TIMER CONTROL TCON REGISTER Continued 11 Dead zone enable 4 Determine the dead zone operation 0 Disable 1 Enable Timer 0 auto reload on off 3 Determine auto reload on off for Timer 0 0 One shot 1 Interval mode auto reload Timer 0 output inverter on off 2 Determine the o
99. VDDRTC CLKOUTTI 0 Clock output signal The CLKSEL of MISCCR register configures the clock output mode among the MPLL CLK UPLL CLK FCLK HCLK PCLK nRESET ST nRESET suspends any operation in progress and places S3C2440A into a known reset state For a reset nRESET must be held to L level for at least 4 OSCin after the processor power has been stabilized nRSTOUT For external device reset control nRSTOUT nRESET amp nWDTRST amp SW RESET PWREN 1 2V 1 3V power on off control signal nBATT_FLT Probe for battery state Does not wake up at Sleep mode in case of low battery state If it isn t used it has to be High VDDOP 3 2 3 2 determines how the clock is made 3 2 00b Crystal is used for MPLL CLK source UPLL CLK source OM 3 2 01b Crystal is used for MPLL CLK source and is used for UPLL CLK source OM 3 2 10b EXTCLK is used for MPLL CLK source and Crystal is used for UPLL CLK source OM 3 2 11b EXTCLK is used for MPLL CLK source and UPLL CLK source EXTCLK External clock source When ON 3 2 11b EXTCLK is used for MPLL CLK source and UPLL CLK Source When 3 2 10b is used for MPLL CLK source only When 3 2 01b EXTCLK is used for UPLL CLK source only If it isn t used it has to be High VDDOP XTIpll Al Crystal Input for internal osc circuit When 3 2 00b is used for MPLL CLK source UPLL CLK Sourc
100. eng de 2 11 2 3 EXCEPTION Veglore u m T 2 13 3 1 The ARM Instructiori Set ei u to au aa 3 2 3 2 Condition CodesSuMMany ooo eedem tue de Adern 3 4 3 3 ARM Data Processing 1 3 11 3 4 Incremental Cycle TIMOS uuu to ee Pc te i to tet Ea ERE OH RE ERE PL Ra oder nta 3 16 3 5 Assembler Syntax Descriptions 3 27 3 6 Addressing Mode 3 45 4 1 THUMB Instruction Set Opcodes 4 3 4 2 Summary of Format 1 Instructions 4 5 4 3 Summary of Format 2 Instructions 4 7 4 4 Summary of Format Instructions 4 9 4 5 Summary of Format 4 Instructions 4 11 4 6 Summary of Format 5 Instructions 4 13 4 7 Summary of PC Relative Load Instruction 4 16 4 8 Summary of Format 7 Instructions u Aa NEEE EA Ea s akapa 4 19 4 9 Summary of Format 8 Instructions anene a apu mene nnne nnn 4 20 4 10 Summary of Format 9 Instructions 4 23 4 11 Halfword Data Transfer Instructions 4 24 4 12 SP Relative Load Store Instructions
101. interrupt enable 1 Enable FIFO is half full MIC in channel threshold interrupt 16 0 Disable enable 1 Enable FIFO is half full Reserved 15 14 PCM out channel transfer mode 13 12 Off PIO DMA Reserved in channel transfer mode 11 10 Off PIO DMA Reserved MIC in channel transfer mode 9 8 Off PIO DMA Reserved 7 4 Transfer data enable using AC 0 Disable link 1 Enable 3 AC link on 2 0 Off 1 SYNC signal transfer to Codec Warm reset 1 0 Normal 1 Wake up codec from power down Cold reset 0 Normal 1 Reset Codec and Controller logic ELECTRONICS 24 9 97 CONTROLLER 53 2440 RISC MICROPROCESSOR AC97 GLOBAL STATUS REGISTER AC GLBSTAT AC GLBSTAT 0 58000004 97 global status register 0x00000000 ac amenr tal Sate mew tw o 0 POM P 0 Not reauesied t Requested 0 POM overrun 0 Not requested t Remesed o MC overun 9 PCM out channel threshold iterrupt i6 0 Not requested 0 _ PCM in channel threshold interrupt 0 Notrequested 1 Requested 0 MIC in channel threshold interrupt 0 Notrequested 1 Requested 0 Controller main state 2 0 000 Idle 001 Init 010 Ready
102. m 12500 112 AC SDATA OUT 7 6 Input 01 12501 11 AC_SDATA IN 2 5 4 Input 01 Output a CDCLK 11 2 AC nRESET GPE1 3 2 Input 01 Output 10 255 11 AC GPEO 1 0 00 Input 01 Output 10 1251 11 AC SYNC 9 16 ELECTRONICS 53 2440 RISC MICROPROCESSOR PORTS PORT E CONTROL REGISTERS GPECON GPEDAT GPEUP Continued GPE 15 0 15 0 When the port is configured as an input port the corresponding bit is the pin state When the port is configured as an output port the pin state is the same as the corresponding bit When the port is configured as a functional pin the undefined value will be read Description GPE 13 0 13 0 0 The pull up function attached to the corresponding port pin is enabled 1 The pull up function is disabled ELECTRONICS 9 17 PORTS 53 2440 RISC MICROPROCESSOR PORT CONTROL REGISTERS GPFCON GPFDAT If GPFO GPFT7 will be used for wake up signals at power down mode the ports will be set in interrupt mode GPF7 15 14 Input 01 Output EINT 7 11 Reserved GPF6 13 12 Input 01 Output 0 EINT 6 11 Reserved GPF5 11 10 Input 01 Output TE EINT 5 11 Reserved 4 Input 01 Output Ge EINT 4 11 Reserved 7 6 Input 01 Output c EINT 3 11 Reserved GPF2 5 4 Input 01 Output ioc EINT2 11 Reserved GPF1 3 2 Inp
103. the Controller receives the stereo PCM data and the mono Mic data from the Codec and then stores them in the memories This chapter describes the programming model for the AC97 Controller Unit The information in this chapter requires an understanding of the AC97 revision 2 0 specifications NOTE The AC97 Controller and the PS Controller must not be used at the same time FEATURES Independent channels for stereo PCM In stereo PCM Out mono MIC In DMA based operation and interrupt based operation of the channels support only 16 bit samples Variable sampling rate AC97 Codec interface 48 KHz and below 16 bit 16 entry FIFOs per channel Only Primary CODEC support ELECTRONICS 24 1 97 CONTROLLER 53 2440 RISC MICROPROCESSOR AC97 CONTROLLER OPERATION BLOCK DIAGRAM Figure 24 1 shows the functional block diagram of the 53 2440 AC97 Controller The AC97 signals form the AC link which is a point to point synchronous serial interconnect that supports full duplex data transfers All digital audio streams and command status information are communicated over the AC link FSM amp Control PCM out FIFO Figure 24 1 AC97 Block Diagram Interrupt Control 24 2 ELECTRONICS 53 2440 RISC MICROPROCESSOR AC97 CONTROLLER INTERNAL DATA PATH Figure 24 2 shows the internal data path of the S3C2440A 97 Controller It has stereo Pulse Code Modulated PCM In Stereo PCM Out and mono
104. total transfer counter middle byte 0x00 0x52000253 byte EPS DMA TTC H 0x52000254 R W total transfer counter higher byte 0x00 0x52000257 byte EP4 DMA TTC L 0x52000264 R W total transfer counter lower byte 0x00 0x52000267 byte EP4 DMA TTC M 0x52000268 R W DMA total transfer counter middle byte 0x00 0x5200026B B byte EP4 DMA TTC H 0x5200026C L R W EP4 total transfer counter higher byte 0x00 0x5200026F B byte __ mcu USB nial State Emn meL 7 0 R DMA total transfer count value lower byte Emn rcM 7 0 Rw n DMA total transfer count value middle byte Emn 3 0 RW R total transfer count value higher byte Kuka sr 02120212 sr s s ELECTRONICS 13 21 USB S3C2440A RISC MICROPROCESSOR NOTES 13 22 ELECTRONICS 53 2440 RISC MICROPROCESSOR INTERRUPT CONTROLLER INTERRUPT CONTROLLER OVERVIEW The interrupt controller in the S3C2440A receives the request from 60 interrupt sources These interrupt sources are provided by internal peripherals such as DMA controller UART IIC and others In these interrupt sources the UARTn AC97 and EINTn interrupts are OR ed to the interrupt controller When receiving multiple interrupt requests from internal peripherals and external interrupt request pins the interrupt
105. 00 Input 10 EINT 10 1 3 2 00 10 9 GPG0 1 0 00 Input 10 EINT 8 NOTE GPG 15 13 must be selected as Input in NAND boot mode ELEGTRONIGS Description 01 Output 11 Reserved 01 Output 11 Reserved 01 Output 11 Reserved 01 Output 11 Reserved 01 Output 11 TCLK 1 01 Output 11 nCTS1 01 Output 11 nRTS1 01 Output 11 Reserved 01 Output 11 SPICLK1 01 Output 11 SPIMOSI1 01 Output 11 SPIMISO1 01 Output 11 LCD_PWRDN 01 Output 11 nSS1 01 Output 11 nSS0 01 Output 11 Reserved 01 Output 11 Reserved PORTS 53 2440 RISC MICROPROCESSOR PORT G CONTROL REGISTERS GPGCON GPGDAT Continued GPG 15 0 15 0 When the port is configured as an input port the corresponding bit is the pin state When the port is configured as an output port the pin state is the same as the corresponding bit When the port is configured as functional pin the undefined value will be read Bit scription 15 0 15 0 0 The pull up function attached to the corresponding port is enabled 1 The pull up function is disabled 9 20 ELECTRONICS 53 2440 RISC MICROPROCESSOR PORTS PORT H CONTROL REGISTERS GPHCON GPHDAT mew GPH10 21 20 Input 01 Output CLKOUT1 11 Reserved GPH9 19 18 Input 01 Output rE CL
106. 000 Low level 001 High level 01x Falling edge triggered 10x Rising edge triggered 11x Both edge triggered FLTEN12 19 Filter enable for EINT12 0 Filter Disable 1 Filter Enable EINT12 18 16 Setting the signaling method of the EINT12 000 Low level 001 High level 01x Falling edge triggered 10x Rising edge triggered 11x Both edge triggered FLTEN11 15 Filter enable for EINT11 0 Filter Disable 1 Filter Enable EINT11 14 12 Setting the signaling method of the EINT11 000 Low level 001 High level 01x Falling edge triggered 10x Rising edge triggered 11x Both edge triggered FLTEN10 11 Filter enable for EINT10 0 Filter Disable 1 Filter Enable EINT10 10 8 Setting the signaling method of the EINT10 000 Low level 001 High level 01x Falling edge triggered 10x Rising edge triggered 11x Both edge triggered FLTEN9 7 Filter enable for EINT9 0 Filter Disable 1 Filter Enable EINT9 6 4 Setting the signaling method of the 9 000 Low level 001 High level 01x Falling edge triggered 10x Rising edge triggered 11x Both edge triggered FLTEN8 3 Filter enable for EINT8 0 Filter Disable 1 Filter Enable EINT8 2 0 Setting the signaling method of the EINT8 000 Low level 001 High level 01x Falling edge triggered 10x Rising edge triggered 11x Both edge triggered 9 28 ELECTRONICS 53 2440 RISC MICROPROCESSOR EXTINTn External Interrupt Control Register n Continued
107. 1 I I I I Ps dS Figure 27 19 Masked ROM Consecutive READ Timing Diagram Tacs 0 Tcos 0 Tacc 3 Tpac 2 PMC 01 10 11 27 20 ELECTRONICS 53 2440 RISC MICROPROCESSOR ELECTRICAL DATA lt m tc Q Q lt Figure 27 20 SDRAM Single Burst READ Timing Diagram Trp 2 Trcd 2 Tcl 2 DW 16bit ELECTRONICS 27 21 53 2440 RISC MICROPROCESSOR ELECTRICAL DATA ADDR BA e x m c x tXnBRQL XnBREQ XnBACK tXnBACKD 2 2 Figure 27 21 External Bus Request in SDRAM Timing Diagram Trpz2 Trcd ELECTRONICS 27 22 ELECTRICAL DATA S3C2440A RISC MICROPROCESSOR lt m lt Figure 27 22 SDRAM MRS Timing Diagram 27 23 ELECTRONICS 53 2440 RISC MICROPROCESSOR ELECTRICAL DATA lt a lt 2 1 2 Figure 27 23 SDRAM Single READ Timing Diagram 1 Trpz2 Trcd ELECTRONICS 27 24 ELECTRICAL DATA S3C2440A RISC MICROPROCESSOR lt a Q Q lt 2 3 Figure 27 24 SDRAM Single READ Timing Diagram Il 2 Tred 27 25 ELECTRONICS 53 2440 RISC MICROPROCESSOR ELECTRICAL DATA ADDR BA 2 s m o 9 o wn 5 o lt c a o T o c o o o E 2 wn 2 8 5 c o 5 5 o 9 o 2 m NOTE Figure 27 25 SDRAM Auto Refresh Timing Diagram Trpz2 Trc 4 ELE
108. 1 No interrupt pending when read 2 Clear pending condition amp Resume the operation when write 1 1 Interrupt is pending when read 2 N A when write Transmit clock value 4 IIC Bus transmit clock prescaler Undefined transmit clock frequency is determined by this 4 bit prescaler value according to the following formula Tx clock IICCLK IICCONJ 3 0 1 NOTES 1 Interfacing with EEPROM the ack generation may be disabled before reading the last data in order to generate the STOP condition in Rx mode 2 AnlIC bus interrupt occurs 1 when a 1 byte transmits or receive operation is completed 2 when a general call or a slave address match occurs or 3 if bus arbitration fails 3 To adjust the setup time of SDA before SCL rising edge IICDS has to be written before clearing the interrupt pending bit 4 is determined by IICCON 6 Tx clock can vary by SCL transition time When 6 0 3 01 0 0 or 0x1 is not available 5 IICCON 5 0 IICCON 4 does not operate correctly So It is recommended that you should set IICCON 5 1 although you does not use the interrupt Interrupt pending flag 2 3 IIC bus Tx Rx interrupt pending flag This bit cannot be written to 1 When this bit is read as 1 the IICSCL is tied to L and the is stopped To resume the ELECTRONICS 20 11 IIC BUS INTERFACE 53 2440 RISC MICROPROCESSOR MULTI MASTER 5 CON
109. 12 bit color mode 4096 color mode 4 level gray scale mode 16 level gray scale mode as well as the monochrome mode For the gray or color mode it is required to implement the shades of gray level or color according to time based dithering algorithm and Frame Rate Control FRC method The selection can be made following a programmable lockup table which will be explained later The monochrome mode bypasses these modules FRC and lookup table and basically serializes the data in FIFOH and FIFOL if a dual scan display type is used into 4 bit or 8 bit if a 4 bit dual scan or 8 bit single scan display type is used streams by shifting the video data to the LCD driver The following sections describe the operation on the gray and color mode in terms of the lookup table and FRC Lookup Table The S3C2440A can support the lookup table for various selection of color or gray level mapping ensuring flexible operation for users The lookup table is the palette which allows the selection on the level of color or gray Selection on 4 gray levels among 16 gray levels in case of 4 gray mode selection on 8 red levels among 16 levels 8 green levels among 16 levels and 4 blue levels among 16 levels in case of 256 color mode In other words users can select 4 gray levels among 16 gray levels by using the lookup table in the 4 gray level mode The gray levels cannot be selected in the 16 gray level mode all 16 gray levels must be chosen among the possible 16 gr
110. 150 ELECTRONICS 27 1 ELECTRICAL DATA S3C2440A RISC MICROPROCESSOR RECOMMENDED OPERATING CONDITIONS Table 27 2 Recommended Operating Conditions Parameter Symbol Typ DC supply voltage for alive block Vppalive 300 2 1 2V DC supply voltage for internal 300MHz 1 2V Vpp VDDMPLL VppuPLL DC supply voltage for I O block 3 3V Vpp DC supply voltage for memory 1 8V 2 5V 3 0V 3 3V interface DC supply voltage for analog core 3 3V Vpp DC supply voltage for RTC 1 8V 2 5V 3 0V 3 3V Vpp VN 21 3 1 3 1 DC input voltage Tolerant input buffer DC output voltage 0 NOTE Inthe DVS Dynamic Voltage Scaling VDDiarm can be supplied with 1 0V in Idle mode Refer the Application Notes for detailed information 0 7 0 8 3 27 2 ELECTRONICS 53 2440 RISC MICROPROCESSOR ELECTRICAL DATA D C ELECTRICAL CHARACTERISTICS Table 27 3 27 4 defines the DC electrical characteristics for the standard LVCMOS buffers Table 27 3 Normal I O PAD DC Electrical Characteristics Normal I O PAD DC Electrical Characteristics for Memory V DDMOP 2 5V 0 2V T4 40 to 85 Parameters Condition Min Typ Max Unit High level input voltage V I I I IL Low level input voltage 09 Schmitt trigger positive going
111. 2 WDTis excluded interface for CPU access is included 3 SEL selectable O X O enable X disable OFF power is turned off ELECTRONICS 7 11 CLOCK amp POWER MANAGEMENT S3C2440A RISC MICROPROCESSOR NORMAL Mode In Normal mode all peripherals and the basic blocks including power management block the CPU core the bus controller the memory controller the interrupt controller DMA and the external master may operate completely But the clock to each peripheral except the basic blocks can be stopped selectively by software to reduce the power consumption IDLE Mode In IDLE mode the clock to the CPU core is stopped except the bus controller the memory controller the interrupt controller and the power management block To exit the IDLE mode EINT 23 0 or RTC alarm interrupt or the other interrupts should be activated EINT is not available until GPIO block is turned on SLOW Mode Non PLL Mode Power consumption can be reduced in the SLOW mode by applying a slow clock and excluding the power consumption from the PLL The is the frequency of divide by n of the input clock XTlpll or EXTCLK without PLL The divider ratio is determined by SLOW VAL in the CLKSLOW control register and CLKDIVN control register Table 7 3 CLKSLOW and CLKDIVN Register Settings for SLOW Clock example SLOW VAL HCLK PCLK 1 1 Option 1 2 Option 1 1 Option 1 2 Option HDIVN 0 HDIVN 1 PDIVN 0 PDIVN 1
112. 23 20 Codec Pre Scaler Control Register 1 esses nennen ennt enne 23 21 Codec Pre Scaler Control Register 2 23 21 Codec Main Scaler Control 23 22 Codec Target Area 23 22 Codec Status Hegister cede b 23 23 RGB1 Start Address 23 23 RGB2 Start Address Register eli 23 23 RGB3 Start Address kaska nnne 23 24 RGB4 Start Address Register a N eee easi ads 23 24 Preview Target Format Register 23 24 Preview DMA Control Register nnne nennen nnns nennen nnns nnns 23 25 53 2440 MICROCONTROLLER xix Table of Contents Continued Chapter 23 Camera Interface Continued Preview Pre Scaler Control Register 1 23 25 Preview Pre Scaler Control Register 2 23 26 Preview Main Scaler Control Register a nennen 23 26 Preview DMA Target Area 23 26 Preview Status Register dece Doa Hte SOR dedi dee OU 23 27 Image Capture Enable
113. 27 11 53 2440 RISC MICROPROCESSOR ELECTRICAL DATA gt gt gt 14 gt gt gt I EUNE EUM RENE viva sau 14 509 gt 1 gt 4 14 GVH ava gt lt av gt I I ie gt gt 8 I T 2 1 SOW j e i 58 I O 1 i ao 24 i 1 i 9 i 19 I a 3 i S5 1 cs 1 1 1 I 1 9 5 o 24 G ELECTRONICS 27 12 ELECTRICAL DATA S3C2440A RISC MICROPROCESSOR 1 i p 4 p Had gt Had e Ha gt gt I lt I M og 2125 2110 1211 Pi PI j gt 14 PIM sod gt i e I lt gt gt 1 gt gt 4 I 1 1 27 13 16bit DW 1 0 ST 0 0 0 Tacc 2 Toch Figure 27 10 ROM SRAM Burst READ Timing Diagram 11 5 0 Tcos ELECTRONICS 53 2440 RISC MICROPROCESSOR ELECTRICAL DATA e x a c x Y gt u XnBREQ tXnBACKD XnBACK Figure 27 11 External Bus Request in ROM SRAM Cycle 0 Tcah 0 PMC 0 ST 0 0 Tacc 8 Toch 0 Tcos Tacs ELECTRONI
114. 288 1 x 100 28 896 ELECTRONICS 15 43 LCD CONTROLLER S3C2440A RISC MICROPROCESSOR Register Setting Guide TFT LCD The CLKVAL register value determines the frequency of VCLK and frame rate Frame Rate 1 VSPW 1 VBPD 1 LIINEVAL 1 VFPD 1 x HSPW 1 HBPD 1 HFPD 1 HOZVAL 1 2 x CLKVAL 1 HCLK For applications the system timing must be considered to avoid under run condition of the fifo of the Icd controller caused by memory bandwidth contention Example 4 TFT Resolution 240 x 240 VSPW 2 VBPD 14 LINEVAL 239 VFPD 4 HSPW 225 HBPD 15 HOZVAL 239 HFPD 1 CLKVAL 5 HCLK 60 M hz The parameters below must be referenced by LCD size and driver specifications VSPW VBPD LINEVAL VFPD HSPW HBPD HOZVAL and HFPD If target frame rate is 60 70Hz then CLKVAL should be 5 So Frame Rate 67Hz 15 44 ELECTRONICS 53 2440 RISC MICROPROCESSOR ADC AND TOUCH SCREEN INTERFACE ADC amp TOUCH SCREEN INTERFACE OVERVIEW The 10 bit CMOS ADC Analog to Digital Converter is a recycling type device with 8 channel analog inputs It converts the analog input signal into 10 bit binary digital codes at a maximum conversion rate of 500KSPS with 2 5MHz A D converter clock A D converter operates with on chip sample and hold function and power down mode is supported Touch Screen Interface can control select pads XP XM YP YM of the Touch Screen for X Y pos
115. 53 2440 RISC MICROPROCESSOR PORTS ELECTRONICS 9 9 PORTS 53 2440 RISC MICROPROCESSOR PORT A CONTROL REGISTERS GPACON GPADAT Continued GPA 24 0 24 0 When the port is configured as output port the pin state is the same as the corresponding bit When the port is configured as functional pin the undefined value will be read NOTE nRSTOUT nRESET amp nWDTRST amp SW RESET 9 10 ELECTRONICS 53 2440 RISC MICROPROCESSOR PORT B CONTROL REGISTERS GPBCON GPBDAT GPBUP mew www Emaan Input rs nXDREQO Input e nXDACK0 Input nXDREQ1 Input nXDACK1 Input nXBREQ Input Input 10 TCLK 0 Input TOUT3 Input TOUT2 Input TOUT1 Input 12 TOUTO 01 Output 11 reserved 01 Output 11 reserved 01 Output 11 Reserved 01 Output 11 Reserved 01 Output 11 reserved 01 Output 11 reserved 01 Output 11 reserved 01 Output 11 reserved 01 Output 11 reserved 01 Output 11 reserved 01 Output 11 reserved PORTS When the port is configured as input port the corresponding bit is the pin state When the port is configured as output port the pin state is the same as the corresponding bit When the port is configured as functional pin the undefined value will be read 0 The pull up function attached to the corresponding po
116. 58000014 97 in channel FIFO address register 0x00000000 ea o o o oo w Read Address 19 16 MIC in channel FIFO read address 0000 Write Address 9 0 MIC in channel FIFO write address 0000 AC97 PCM OUT IN CHANNEL FIFO DATA REGISTER AC PCMDATA PCMDATA 0 5 000018 AC97 PCM out in channel FIFO data register 0 00000000 Left Data 31 16 out in left channel FIFO data 0x0000 Read POM in left channel Write PCM out left channel Right Data 15 0 PCM out in right channel FIFO data 0x0000 Read POM in right channel Write PCM out right channel AC97 MIC IN CHANNEL FIFO DATA REGISTER AC MICDATA AC MICDATA 0 5 00001 AC97 MIC in channel FIFO data register 0x00000000 Mono Data 15 0 MIC in mono channel FIFO data 0x0000 24 12 ELECTRONICS 53 2440 RISC MICROPROCESSOR BUS PRIORITIES BUS PRIORITIES OVERVIEW The bus arbitration logic determines the priorities of bus masters It supports a combination of rotation priority mode and fixed priority mode BUS PRIORITY MAP The S3C2440A holds 13 bus masters They include DRAM refresh controller LCD DMA CAMIF DMAO DMA1 DMA2 USB HOST DMA EXT BUS MASTER Test interface controller TIC and ARM920T The following list shows the priorities among these bus masters after a reset DRAM refresh controller LCD CAMIF codec DMA CAMIF preview DMA DMA0 DMA1 DMA2 USB host
117. 8 Spare area ECC status for l O 7 0 SECCO 0 7 0 Spare area ECCO status for 7 0 NOTE The NAND flash controller generate NFSECC when read or write spare area data while the SpareECCLock NFCONT 6 bit is O Unlock 6 20 ELECTRONICS 53 2440 RISC MICROPROCESSOR NAND FLASH CONTROLLER BLOCK ADDRESS REGISTER NFSBLK 0x4E000038 NAND flash programmable start block address 0x000000 NFEBLK 0x4E00003C R W NAND flash programmable end block address 0x000000 Nand Flash can be programmed between start and end address When the soft lock or lock tight is enabled and the start and end address has same value Entire area of NAND flash will be locked SBLK_ADDR2 23 16 The 379 block address of the block erase operation SBLK ADDR1 15 8 The 274 block address of the block erase operation SBLK ADDRO 7 0 The 13 block address of the block erase operation 0x00 Only bit 7 5 are valid NOTE Advance Flash s block Address start from 3 address cycle So block address register only needs 3 bytes EBLK ADDR2 23 16 The 3 block address of the block erase operation EBLK ADDR1 15 8 The 27 block address of the block erase operation EBLK ADDRO 7 0 The 1 block address of the block erase operation 0x00 Only bit 7 5 are valid NOTE Advance Flash s block Address start from 3 address cycle So block address register only needs 3 bytes ELECTRONICS 6 21 NAND FLASH CONTROLLER 53 2440 RISC MICROPROCESSOR
118. 8 Operations for Slave Transmitter Mode ene mener 20 9 20 9 Operations for Slave Receiver 20 10 xxvi S3C2440A MICROCONTROLLER List of Figures continued Figure Title Page Number Number 21 1 IIS Bus Block Diagram etr cec trea tt REO EHE RI Pere E Od esa 21 2 21 2 IIS Bus and MSB Left justified Data Interface Formats 21 4 22 1 SPI Block Diagramm D NO POI NH ERES 22 2 22 2 SPI Transfer u u au u a p ket iex o ELS M 224 23 1 EE 23 2 23 2 ITU R BT 601 Input Timing 23 3 23 3 ITU R BT 656 Input Timing 23 3 23 4 hier certi bo orient sec etri e pr tra DE OY Dep IE EU bed don 23 5 23 5 CAMIF OOCK Generation toe ates etek de Rae Mta 23 6 23 6 Ping Pong Memory Hierarchy u A mene nme 23 7 23 7 Memory Storing Poet eb lo SR 23 8 23 8 Timing Diagram for Register meme 23 9 23 9 Timing diagram for last tette ER npe 23 10 23 10 Window Offset 5
119. CONTROL STATUS REGISTER EP0_CSR This register has the control and status bits for Endpoint 0 Since a control transaction is involved with both IN and OUT tokens there is only one CSR register mapped to the IN CSR1 register Share INT CSR and can access writing index register 0 and read write INT CSR Reset Value 0x52000184 L R W Endpoint 0 status register 0x52000187 B byte EPOCSR Bit MCU USB Description Initial State UP END SETUP END Peer wv SOR cog emm PKT RDY OUT PKT RDY AN SEND STALL 5 R LEAR MCU should write a 1 to this bit at the same time it clears OUT PKT RDY if it decodes an invalid token 0 Finish the STALL condition 1 The USB issues a STALL and shake to the current control transfer SETUP END SET Set by the USB when a control transfer ends before DATA END is set When the USB sets this bit an interrupt is generated to the MCU When such a condition occurs the USB flushes the FIFO and invalidates MCU access to the FIFO 4 DATA END 3 CLEAR Set by MCU on the conditions below 1 After loading the last packet of data into the FIFO at the same time IN PKT RDY is set 2 While it clears OUT PKT RDY after unloading the last packet of data 3 For a zero length data phase SENT STALL CLEAR SET Set by the USB if a control transaction is stopped due to a protocol violation An interrupt is generated when this bit is set The MCU should write
120. Data Processing instructions vary in the number of incremental cycles taken as follows Table 3 4 Incremental Cycle Times Data processing with register specified shift 15 11 Data processing with written 25 1 Data processing with register specified shift and written 2 1N 11 NOTE 5 as defined sequential S cycle non sequential N cycle and internal I cycle respectively 3 16 ELECTRONICS 53 2440 RISC MICROPROCESSOR ARM INSTRUCTION SET ASSEMBLER SYNTAX e MOV MVN single operand instructions 5 Rd lt Op2 gt e CMP CMN TEQ TST instructions which do not produce a result lt opcode gt cond Rn lt Op2 gt AND EOR SUB RSB ADD ADC SBC RSC ORR BIC lt opcode gt cond S Rd Rn lt Op2 gt where lt Op2 gt Rm lt shift gt or expression cond A two character condition mnemonic See Table 3 2 5 Set condition codes if S present implied for TST Rd Rn and Rm Expressions evaluating to a register number lt expression gt If this is used the assembler will attempt to generate a shifted immediate 8 bit field to match the expression If this is impossible it will give an error shift Shiftname register shiftname expression or rotate right one bit with extend lt shiftname gt s ASL LSL LSR ASR ROR ASL is a synonym for LSL they assemble to the same code EXAMPLES ADDEQ R2
121. EXTCLK or EXTCLK or EXTCLK or HCLK HCLK 2 48 MHz XTIpll 1 XTIpll 1 2 001 2 48 MHz 2 2 4 010 HCLK 2 48 MHz 4 4 8 011 EXTCLKor EXTCLKor EXTCLKor HCLK HCLK 2 48 MHz 6 6 12 100 EXTCLKor EXTCLKor EXTCLKor HCLK HCLK 2 48 MHz XTIpII 8 XTIpII 8 16 101 EXTCLK or EXTCLKor EXTCLKor HCLK HCLK 2 48 MHz 10 10 XTlpll 20 110 EXTCLKor EXTCLKor EXTCLKor HCLK HCLK 2 48 MHz 12 12 XTlpll 24 111 EXTCLKor EXTCLKor EXTCLKor HCLK HCLK 2 48 MHz 14 XTlpll 14 28 In SLOW mode PLL will be turned off to reduce the PLL power consumption When the PLL is turned off in the SLOW mode and the user changes power mode from SLOW mode to NORMAL mode then the PLL needs clock stabilization time PLL lock time This PLL stabilization time is automatically inserted by the internal logic with lock time count register The PLL stability time will take 300us after the PLL is turned on During PLL lock time the FCLK becomes SLOW clock 7 12 ELECTRONICS 53 2440 RISC MICROPROCESSOR CLOCK amp POWER MANAGEMENT Users can change the frequency by enabling SLOW mode bit in CLKSLOW regi
122. Figure 3 15 Little Endian Offset Addressing Big Endian Configuration A byte load LDRB expects the data on data bus inputs 31 through 24 if the supplied address is on a word boundary on data bus inputs 23 through 16 if it is a word address plus one byte and so on The selected byte is placed in the bottom 8 bits of the destination register and the remaining bits of the register are filled with zeros Please see Figure 2 1 A byte store STRB repeats the bottom 8 bits of the source register four times across data bus outputs 31 through 0 The external memory system should activate the appropriate byte subsystem to store the data A word load LDR should generate a word aligned address An address offset of 0 or 2 from a word boundary will cause the data to be rotated into the register so that the addressed byte occupies bits 31 through 24 This means that half words accessed at these offsets will be correctly loaded into bits 16 through 31 of the register shift operation is then required to move and optionally sign extend the data into the bottom 16 bits An address offset of 1 or 3 from a word boundary will cause the data to be rotated into the register so that the addressed byte occupies bits 15 through 8 A word store STR should generate a word aligned address The word presented to the data bus is not affected if the address is not word aligned That is bit 31 of the register being stored always appears on data bus output 31 3 3
123. Immediate Offset High Nibble 15 12 Source Destination Register 19 16 Base Register 20 Load Store 0 Store to memory 1 2 Load from memory 21 Write back 0 No write back 1 Write address into base 23 Up Down 0 Down subtract offset from base 1 2 Up add offset to base 24 Pre Post Indexing 0 Post add subtract offset after transfer 1 Pre add subtract offset bofore transfer 31 28 Condition Field Figure 3 17 Halfword and Signed Data Transfer with Immediate Offset and Auto Indexing OFFSETS AND AUTO INDEXING The offset from the base may be either a 8 bit unsigned binary immediate value in the instruction or a second register The 8 bit offset is formed by concatenating bits 11 to 8 and bits 3 to 0 of the instruction word such that bit 11 becomes the MSB and bit 0 becomes the LSB The offset may be added to 9 1 subtracted from U 0 the base register Rn The offset modification may be performed either before pre indexed P 1 or after post indexed 0 the base register is used as the transfer address The W bit gives optional auto increment and decrement addressing modes The modified base value may be written back into the base W 1 or the old base may be kept W 0 In the case of post indexed addressing the write back bit is redundant and is always set to zero since the old base value can be retained if necessary by setting the offset to zero Therefore post indexed data transfers alwa
124. Jinemuptenabe FRAME NUM REG 0x52000173 Ox52000170 Frame number lower byte FRAME NUM2 REG 0x52000177 0 52000174 Frame number higher byte INDEX REG 0x5200017B 0 52000178 Register index EPO CSR Ox52000187 0 52000184 Endpoint status IN CSR REG 0x52000187 Ox52000184 In endpoint control status N REG 0652000188 05200088 in endpoint contol status REG 052000183 0 52000180 Endpoint max packet OUT REG 0x52000193 0 52000190 Out endpoint control status OUT CSR2 REG 052000197 0 52000194 Out endpoint control status OUT FIFO CNTi REG 0 52000198 0 52000198 Endpoint out write count OUT FIFO CNT2 REG 0x5200019F Ox5200019C Endpoint out write count EPO FIFO 0552000103 Ox520001CO R W jEndpontOFIO FIFO 7 02000107 0 82000104 Endpont FIFO 0620001CB os20001c8 Embom2FFO FIFO 0 520001 05520010 Endpon3FFo FIFO 0 52000103 52000100 _ Endpoint a EPIDMACON 052000203 Ox52000200 EP1 DMA Interface control UNT 0652000207 0520004 EPiDMATkuntcouver EPI FIFO 0552000208 0 52000208 _____ DMA Tx FIFO counter EPIDMATICL 0 5200020 Ox5200020C
125. M 7 0 XTIpll XII JH 070 EXTCLK 1 1 or 1 2 CLKCNTL FCLK m eoi UPLL Power Management Block Interrupt Controller Controller E H LCD Bus LCD CAMDIVN Controller Controller Arbitration DMA 4ch 4 i 1 1 LI LI 1 1 4 3 4 4 i i i 1 LI L 4 LI 4 4 4 i i 1 3 1 _ _ Device P USB Figure 7 1 Clock Generator Block Diagram ELECTRONICS 7 8 CLOCK amp MANAGEMENT S3C2440A RISC MICROPROCESSOR PHASE LOCKED LOOP PLL The MPLL within the clock generator as a circuit synchronizes an output signal with a reference input signal in frequency and phase In this application it includes the following basic blocks as shown in Figure 7 2 the Voltage Controlled Oscillator VCO to generate the output frequency proportional to input DC voltage the divider P to divide the input frequency Fin by p the divider M to divide the VCO output frequency by m which is input to Phase Frequency Detector PFD the divider S to divide the VCO output frequency by s which is Mpll the output frequency from MPLL block the phase difference detector the charge pump and the loop filter The output clock frequency Mpll is related to the reference input clock frequency Fin by the following equation Mpll 2 m Fin p 2 m M the value for divid
126. MISCCR 19 17 000b Configure the SDRAM memory controller Wait until the SDRAM self refresh is released Mostly SDRAM needs the refresh cycle of all SDRAM row The information in GSTATUS 3 4 can be used for user s own purpose because the value GSTATUS 3 4 has been preserved during SLEEP mode 7 For EINT 3 0 check the SRCPND register For EINT 15 4 check the EINTPEND instead of SRCPND SRCPND will not be set although some bits of EINTPEND are set Table 7 4 Pin configuration table in Sleep mode Pin Condition Guid of Pin Configuration which are configured as input Pull up enable which are configured as ouput Pull up disable and output low If external device doesn t always Pull up enable by external pull up resistor drive pin s level If external device s power is off Output low If external device s power is on High or low It depends on External device s status Data If memory power is off Output low Bus If memory power is and external buffer does exist If buffer can hold bus level pull up disable NOTE 1 ADC should be set to Standby mode 2 USB pads should be Suspend mode GPIO Pin Input pin which doesn t have internal pull up control Output pin which are connected to external device This table is just for informational use only User should consider his own board condition and application 7 16 ELECTRONICS 53 2440 RISC MICROPROCESSOR CLOCK amp POWER MANAGEM
127. Mic in buffers which consist of 16 bit 16 entries buffer Also it has a 20 bit I O shift register via AC link Command Addr Register Command Data Register SDATA OUT PCM Out Buffer Output Shift PWDATA Regfile 16 bit x 2 Register x 16 Entry 20 bit In Buffer Input Shift SDATA PRDATA Regfile 16 bit x 2 Register x 16 Entry 20 bit Mic In Buffer RegFile 16 bit x16 Entry Response Data Register Figure 24 2 Internal Data Path ELECTRONICS 24 3 97 CONTROLLER 53 2440 RISC MICROPROCESSOR OPERATION FLOW CHART System reset or Cold reset Set GPIO and Release INTMSK SUBINTMSK bits Enable Codec Ready interrupt Time out condition Codec Ready interrupt Disable Codec Ready interrupt DMA operation or PIO Interrupt or Polling operation Figure 24 3 AC97 Operation Flow Chart 24 4 ELECTRONICS 53 2440 RISC MICROPROCESSOR AC97 CONTROLLER AC LINK DIGITAL INTERFACE PROTOCOL Each AC97 Codec incorporates a five pin digital serial interface that links it to the 53 2440 AC97 Controller The is a full duplex fixed clock PCM digital stream It employs a time division multiplexing scheme to handle control register access and multiple input and output audio streams The AC link architecture divides each audio frame into 12 outgoing and 12 incoming data streams Each stream has a 20 bit sample resolution and requires a DAC and an analog to digital conv
128. Mode The output port should have a proper logic level in power off mode which makes the current consumption minimized If there is no load on an output port pin H level is preferred If output is L the current will be consumed through the internal parasitic resistance if the output is H the current will not be consumed For an output port the current consumption can be reduced if the output state is H is recommended that the output ports be in H state to reduce current consumption in SLEEP mode Battery Fault Signal nBATT FLT There are two functions in nBATT FLT pin they as follows When CPU is not in SLEEP mode nBATT_FLT pin will cause the interrupt request by setting BATT_FUNC MISCCR 22 20 as 10x b The interrupt attribute of the nBATT_FLT is L level triggered While CPU is in SLEEP mode assertion of the nBATT FLT will prohibit the wake up from the sleep mode which is achieved by setting BATT FUNC MISCCR 22 20 as 11x b So Any wake up source will be masked if nBATT FLT is asserted which is protecting the system malfunction of the low battery capacity ADC Power Down The ADC has an additional power down bit in ADCCON If the S3C2440A enters the SLEEP mode the ADC should enter its own power down mode ELECTRONICS 7 19 CLOCK amp MANAGEMENT S3C2440A RISC MICROPROCESSOR CLOCK GENERATOR amp POWER MANAGEMENT SPECIAL REGISTER LOCK TIME COUNT REGISTER LOCKTIME LOCKTIME 0 4 000000
129. PLL lock time count register 31 16 UPLL lock time count value for UCLK U LTIME gt 300uS M LTIME 15 0 MPLL lock time count value for FCLK HCLK and PCLK OxFFFF LTIME gt 300 5 MPLL Control Register Mpll 2 m Fin p 25 m 8 p PDIV 2 s SDIV UPLL Control Register m Fin p 25 m MDIV 8 p PDIV 2 s SDIV PLL Value Selection Guide MPLLCON 1 Four 2 m Fin 25 2 m Fin p where m MDIV 8 p PDIV 2 s SDIV 2 600MHz lt Fvco lt 1 2GHz 3 200MHz lt FCLKour lt 600MHz 4 Don t set the P or M value as zero that is setting the P 000000 M 00000000 can cause malfunction of the PLL 5 The proper range of P and M 1 lt P lt 62 1 lt M lt 248 NOTE Although there is the rule for choosing PLL value we recommend only the values in the PLL value recommendation table If you have to use another value please contact us 7 20 ELECTRONICS 53 2440 RISC MICROPROCESSOR CLOCK amp POWER MANAGEMENT PLL CONTROL REGISTER MPLLCON amp UPLLCON MPLLCON 0x4C000004 MPLL configuration register 0x00096030 UPLLCON 0x4C000008 UPLL configuration register 0x0004d030 m oeoo 00 NOTE When you set MPLL amp UPLL values you have to set the UPLL value first and then the MPLL value Needs intervals approximately 7 NOP PLL VALUE SELECTION TABLE
130. Ps re P Pe oo Po PH Pis Pz pee oe NN 1 HWSWP 0 _ PB pe P Pe P ma m mr me P Pio Ps Lp 2BPP Display BSWP 0 HWSWP 0 was evan m rm wm Pa Ps pacc xe mee e Pe em Pe ma P PG Pe Lap pug 15 20 ELECTRONICS 53 2440 RISC MICROPROCESSOR LCD CONTROLLER 256 PALETTE USAGE Palette Configuration and Format Control The S3C2440A provides 256 color palette for LCD Control The user can select 256 colors from the 64K colors in these two formats The 256 color palette consists of the 256 depth x 16 bit SPSRAM The palette supports 5 6 5 R G B format and R G B I format When the user uses 5 5 5 1 format the intensity data l is used as a common LSB bit of each RGB data So 5 5 5 1 format is the same as R 5 l G 5 l B 5 l format In 5 5 5 1 format for example the user can write the palette as in Table 15 5 and then connect VD pin to TFT LCD panel R 5 l VD 23 19 VD 18 VD 10 or VD 2 G 5 l VD 15 11 VD 18 VD 10 or VD 2 5 1
131. R4 R5 If the Z flag is set make R2 R4 R5 TEQS R4 3 Test R4 for equality with 3 The S is in fact redundant as the assembler inserts it automatically SUB R4 R5 R7 LSR R2 Logical right shift R7 by the number in the bottom byte of R2 subtract result from R5 and put the answer into R4 MOV PC R14 Return from subroutine MOVS PC R14 Return from exception and restore CPSR from SPSR mode ELECTRONICS 3 17 ARM INSTRUCTION SET 53 2440 RISC MICROPROCESSOR PSR TRANSFER MRS MSR The instruction is only executed if the condition is true The various conditions are defined in Table 3 2 The MRS and MSR instructions are formed from a subset of the Data Processing operations and are implemented using the TEQ TST CMN and CMP instructions without the S flag set The encoding is shown in Figure 3 11 These instructions allow access to the CPSR and SPSR registers The MRS instruction allows the contents of the CPSR or SPSR mode to be moved to a general register The MSR instruction allows the contents of a general register to be moved to the CPSR or SPSR mode register The MSR instruction also allows an immediate value or register contents to be transferred to the condition code flags N Z C and V of CPSR or SPSR mode without affecting the control bits In this case the top four bits of the specified register contents or 32 bit immediate value are written to the top four bits of the relevant PSR OPERAND RES
132. S3C2440A LCD controller can support a 12 bit per pixel 4096 color display mode The color display mode can generate 4096 levels of color using the dithering algorithm and FRC The 12 bit per pixel are encoded into 4 bits for red 4 bits for green and 4 bits for blue The 4096 color display mode does not use lookup tables 15 6 ELECTRONICS 53 2440 RISC MICROPROCESSOR LCD CONTROLLER DITHERING AND FRAME RATE CONTROL In case of STN LCD display except monochrome video data must be processed by a dithering algorithm The DITHFRC block has two functions such as Time based Dithering Algorithm for reducing flicker and Frame Rate Control FRC for displaying gray and color level on the STN panel The main principle of gray and color level display on the STN panel based on FRC is described For example to display the third gray 3 16 level from a total of 16 levels the 3 times pixel should be on and 13 times pixel off In other words 3 frames should be selected among the 16 frames of which 3 frames should have a pixel on on a specific pixel while the remaining 13 frames should have a pixel off on a specific pixel These 16 frames should be displayed periodically This is basic principle on how to display the gray level on the screen so called gray level display by FRC The actual example is shown in Table 15 2 To represent the 14h gray level in the table we should have a 6 7 duty cycle which mean that there are 6 times pixel on and one time pixel
133. SDRAM refresh controller bus priority section Refresh period 2 refresh_count 1 HCLK Ex If refresh period is 7 8 us and HCLK is 100 2 the refresh count is as follows Refresh count 211 1 100x7 8 1269 5 18 ELECTRONICS 53 2440 RISC MICROPROCESSOR MEMORY CONTROLLER BANKSIZE REGISTER BANKSIZE 0x48000028 Flexible bank size register 0x0 E EN ARM core burst operation enable 0 Disable burst operation 1 Enable burst operation mme wa _ SCKE EN 5 SDRAM power down mode enable control by SCKE 0 SDRAM power down mode disable 1 SDRAM power down mode enable SCLK EN 4 SCLK is enabled only during SDRAM access cycle for reducing power consumption When SDRAM is not accessed SCLK becomes L level 0 SCLK is always active 1 SCLK is active only during the access recommended BK76MAP 2 0 BANK6 7 memory map 010 010 128MB 128MB 001 64MB 64MB 000 32M 32M 111 2 16M 16M 110 2 8M 8M 101 4M 4M 100 2M 2M ELECTRONICS 5 19 MEMORY CONTROLLER S3C2440A RISC MICROPROCESSOR SDRAM MODE REGISTER SET REGISTER MRSR MRSRB6 0x4800002C Mode register set register bank6 MRSRB7 0x48000030 Mode register set register bank7 Write burst length 0 Burst Fixed 1 Reserved 8 7 Test mode 00 Mode register set Fixed 01 10 and 11 Reserved 6 4 CAS latency 000 1 clock 010 2 clocks 011 3 clocks Others reserved 3 Burst type 0
134. START ADDRESS REGISTER CIPRCLRSA2 0x4F000070 RGB 279 frame start address for preview CIPRCLRSA2 31 0 RGB 219 frame start address for preview DMA yog ELECTRONICS 23 23 53 2440 RISC MICROPROCESSOR CAMERA INTERFACE RGB3 START ADDRESS REGISTER CIPRCLRSA3 4 000074 379 frame start address for preview CIPRCLRSA3 31 0 RGB 379 frame start address for preview RGB4 START ADDRESS REGISTER CIPRCLRSA4 0x4F000078 RW RGB 41 frame start address for preview DMA CIPRCLRSA4 31 0 RGB 41 start address for preview PREVIEW TARGET FORMAT REGISTER CIPRTRGFMT 0 4 00007 Target image format of preview DMA TargetHsize Pr 28 16 Horizontal pixel number of target image for preview even Pr 15 14 Image mirror and rotation for preview 00 Normal 01 X axis mirror 10 Y axis mirror 11 180 rotation TargetVsize Pr 12 0 Vertical pixel number of target image for preview DMA 23 24 ELECTRONICS 53 2440 RISC MICROPROCESSOR CAMERA INTERFACE PREVIEW DMA CONTROL REGISTER CIPRCTRL 0x4F000080 Preview DMA control related _Pr KCN Main burst length for preview RGB frames RGBburst2 8 Remained burst length for preview RGB frames LastIRQEn_Pr 0 Normal 1 Enable last IRQ at the end of frame capture This bit is cleared automatically NOTE All burst lengths must be one of the 2 4 8
135. UCLK select register UCLK must be 48MHz for USB 0 UCLK UPLL clock 1 UCLK UPLL clock 2 Set to 0 when clock is set as 48MHz Set to 1 when UPLL clock is set as 96MHz HDIVN 2 1 00 HCLK FCLK 1 01 HCLK FCLK 2 10 HCLK FCLK 4 when CAMDIVN 9 0 FCLK 8 when CAMDIVN 9 1 11 HCLK FCLK 3 when CAMDIVN 8 0 HCLK FCLK 6 when CAMDIVN 8 1 PDIVN 0 PCLK has the clock same as the HCLK A 1 PCLK has the clock same as the HCLK 2 7 24 ELECTRONICS 53 2440 RISC MICROPROCESSOR CLOCK amp POWER MANAGEMENT CAMERA CLOCK DIVIDER CAMDIVN REGISTER CAMDIVN 0x4C000018 Camera clock divider register 0x00000000 DVS EN 12 0 DVS OFF ARM core will run normally with FCLK MPLLout 1 DVS ON ARM core will run at the same clock as system clock HCLK HCLK4 HALF HDIVN division rate change bit when CLKDIVN 2 1 1 Ob 0 HCLK FCLK 4 1 HCLK FCLK 8 Refer the CLKDIV register HDIVN division rate change bit when CLKDIVN 2 1 1 1b 0 HCLK FCLK 3 1 HCLK FCLK 6 HCLK3_HALF Refer the CLKDIV register CAMCLK_SEL 4 0 Use CAMCLK with UPLL output CAMCLK UPLL output 1 CAMCLK is divided by CAMCLK_DIV value CAMCLK_DIV 3 0 CAMCLK divide factor setting register O 15 Camera clock UPLL CAMCLK_DIV 1 x2 This bit is valid when CAMCLK_SEL 1 ELECTRONICS 7 25 53 2440 RISC MICROPROCESSOR OVERVIEW The S3C2440A supports four channel DMA co
136. UMLAL and SMLAL take two 32 bit numbers multiply them and add a 64 bit number to produce a 64 bit result of the form RdHi RdLo Rm Rs RdHi RdLo The lower 32 bits of the 64 bit number to add is read from RdLo The upper 32 bits of the 64 bit number to add is read from RdHi The lower 32 bits of the 64 bit result are written to RdLo The upper 32 bits of the 64 bit result are written to RdHi The UMULL and UMLAL instructions treat all of their operands as unsigned binary numbers and write an unsigned 64 bit result The SMULL and SMLAL instructions treat all of their operands as two s complement signed numbers and write a two s complement signed 64 bit result ELECTRONICS 3 25 ARM INSTRUCTION SET 53 2440 RISC MICROPROCESSOR OPERAND RESTRICTIONS e R15 must not be used as an operand or as a destination register e RdLo and Rm must all specify different registers CPSR FLAGS Setting the CPSR flags is optional and is controlled by the S bit in the instruction The N and Z flags are set correctly on the result N is equal to bit 63 of the result Z is set if and only if all 64 bits of the result are zero Both the C and V flags are set to meaningless values INSTRUCTION CYCLE TIMES MULL takes 15 1 and MLAL 15 2 1 cycles to execute where m is the number of 8 bit multiplier array cycles required to complete the multiply which is controlled by the value of the multiplier operand specified by Rs Its pos
137. UNT osos 0620055 EP4DMATxUnteouner FIFO EP4DMATxFIFO counter EPA TTC L ___ EPA DMA Total Tx counter Watchdog Timer WTCON 0x53000000 Watchdog timer mode WTDAT 0x53000004 Watchdog timer data how me uso 018600000606 oxssoo000e i uses _______ oxssoooo0e fis presar ISFOON ISO m ELECTRONICS 1 35 PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR Table 1 4 S3C2440A Special Registers Sheet 11 of 14 Continued em B Endian L Endian Write 05800004 O GPBCON 05600010 1 GPBDAT 0 56000014 O GPBUP 05600018 0 56000020 GPCDAT 0 56000024 004 GPCUP 0 56000028 0 56000030 Port control GPDDAT 06600004 GPDUP 0 56000038 GPECON 0 56000040 0 56000044 1 j PotEdaa GPEUP 056000048 PultupcontrolE GPFCON Ox5600050 0 56000054 GPFUP 0 56000058
138. address In this way the read write operation can be performed in various formats Start Stop Condition Condition Figure 20 2 Start and Stop Condition ELECTRONICS 20 3 IIC BUS INTERFACE 53 2440 RISC MICROPROCESSOR DATA TRANSFER FORMAT Every byte placed on the SDA line should be eight bits in length The bytes can be unlimitedly transmitted per transfer The first byte following a Start condition should have the address field The address field can be transmitted by the master when the IIC bus is operating in Master mode Each byte should be followed by an acknowledgement ACK bit The MSB bit of the serial data and addresses are always sent first Write Mode Format with 7 bit Addresses Slave Address 7bits DATA 1Byte Write Data Transferred Data Acknowledge Write Mode Formatl with 10 bit Addresses Slave Address Slave Address 1st 7 bits 2nd Byte PRTA Write Data Transferred Data Acknowledge Read Mode Formatl with 7 bit Addresses Slave Address 7 bits DATA Data Transferred Data Acknowledge Read Mode Format with 10 bit Addresses Slave Address Slave Address Slave Address F a Read Read Data Transferred Data Acknowledge NOTES 1 S Start rS Repeat Start P Stop A Acknowledge 2 L From Master to Slave Slave to Master Figure 20 3 IIC Bus Interface Data Format 20 4 ELECTRONICS 53 2440 RISC MICROPROCES
139. and then de asserted for each atomic transfer In contrast in the Whole service mode main FSM waits at state 3 until CURR becomes 0 Therefore is asserted during all the transfers and then de asserted when TC reaches 0 However INT is asserted only if CURR TC becomes 0 regardless of the service mode Single service mode or Whole service mode 8 2 ELECTRONICS 53 2440 RISC MICROPROCESSOR DMA EXTERNAL DMA DREQ DACK PROTOCOL There are three types of external DMA request acknowledge protocols Single service Demand Single service Handshake and Whole service Handshake mode Each type defines how the signals like DMA request and acknowledge are related to these protocols Basic DMA Timing The DMA service means performing paired Reads and Writes cycles during DMA operation which can make one DMA operation Figure 8 1 shows the basic Timing in the DMA operation of the S8C2440A The setup time and the delay time of XnXDREQ and XnXDACK are the same in all the modes If the completion of XnXDREQ meets its setup time it is synchronized twice and then XnXDACK is asserted After assertion of XnXDACK requests the bus and if it gets the bus it performs its operations XnXDACK is de asserted when DMA operation is completed XSCLK I I XnXDREQ E 19 3ns Setup 4 Min 2XSCLK I I I XnXDACK i Read Write Write Mii Min 3
140. and reception which can be selected by setting the Infrared mode bit in the UART line control register ULCONn Figure 11 4 illustrates how to implement the IR mode In IR transmit mode the transmit pulse comes out at a rate of 3 16 the normal serial transmit rate when the transmit data bit is zero In IR receive mode the receiver must detect the 3 16 pulsed period to recognize a zero value see the frame timing diagrams shown in Figure 11 6 and 11 7 Encoder Decoder IrDA Tx IrDA Rx Figure 11 4 IrDA Function Block Diagram 11 8 ELECTRONICS 53 2440 RISC MICROPROCESSOR UART SIO Frame Start 4 Datta Stop 4 Figure 11 5 Serial I O Frame Timing Diagram Normal UART lt Transmit Frame _ gt Start 4 Datta Bits Stop lt Pulse Width 3 16 Bit Frame Figure 11 6 Infrared Transmit Mode Frame Timing Diagram IR Receive Frame UA Start 4 Datta Bits Stop Figure 11 7 Infrared Receive Mode Frame Timing Diagram ELECTRONICS 11 9 UART 53 2440 RISC MICROPROCESSOR UART SPECIAL REGISTERS UART LINE CONTROL REGISTER There are three UART line control registers including ULCONO ULCON1 and ULCONe in the UART block Infrare
141. arises If the processor is operating in a privileged mode they can also be manipulated by software The T bit This reflects the operating state When this bit is set the processor is executed in THUMB state or otherwise it is executing in ARM state This is reflected on the external signal Note That the software must never change the state of the TBIT in the CPSR If this happens the processor will enter an unpredictable state Interrupt disable bits and F bits are the interrupt disable bits When set these disable the IRQ and FIQ interrupts respectively The mode bits The 4 2 M1 and MO bits M 4 0 are the mode bits These determine the processor s operating mode as shown in Table 2 1 Not all combinations of the mode bits define a valid processor mode Only those explicitly described shall be used The user should be aware that if any illegal value is programmed into the mode bits M 4 0 then the processor will enter an unrecoverable state If this occurs reset should be applied Reserved bits The remaining bits in the PSRs are reserved When changing a PSR s flag or control bits you must ensure that these unused bits are not altered Also your program should not rely on them containing specific values since in future processors they may read as one Or zero 2 8 ELECTRONICS 53 2440 RISC MICROPROCESSOR PROGRAMMER S MODEL Table 2 1 PSR Mode Bit Values M 4 0 Moe Visible THUMB state regis
142. auto position mode ADC conversion start delay value 2 Waiting for Interrupt Mode When stylus down occurs at SLEEP MODE generates Wake Up signal having interval several ms for exiting SLEEP MODE Note Don t use Zero value 0x0000 NOTE Before ADC conversion Touch screen uses X tal clock 3 68MHz During ADC conversion GCLK Max 50MHz is used ELECTRONICS 16 7 ADC AND TOUCH SCREEN INTERFACE S3C2440A RISC MICROPROCESSOR ADC CONVERSION DATA REGISTER ADCDATO ADCDATO 0x580000C R ADC conversion data register Se UPDOWN 15 Up or Down state of stylus at waiting for interrupt mode 0 Stylus down state 1 Stylus up state AUTO_PST 14 Automatic sequencing conversion of X position and Y Position 0 Normal ADC conversion 1 Sequencing measurement of X position Y position mag XPDATA X Position conversion data value include normal ADC conversion Normal ADC data value Data value 0 XY PST 13 12 Manually measurement of X position or Y position 00 No operation mode 01 X position measurement 10 Y position measurement 11 Waiting for Interrupt Mode 16 8 ELECTRONICS 53 2440 RISC MICROPROCESSOR ADC AND TOUCH SCREEN INTERFACE ADC CONVERSION DATA REGISTER ADCDAT1 ADCDAT1 0x5800010 R ADC conversion data register UPDOWN 15 Up or down state of stylus at waiting for interrupt mode 0 Stylus down state 1 Stylus up state AUTO PST 14 Automatically sequenci
143. auto reload bit And then TOUTn goes to high level and the timer is stopped after the TCNTn reaches 0 recommended 2 Stop the timer by clearing the timer start stop bit to 0 If TCNTn TCMPn the output level is high If TCNTn the output level is low 3 The can be inverted by the inverter on off bit in TCON The inverter removes the additional circuit to adjust the output level 10 8 ELECTRONICS 53 2440 RISC MICROPROCESSOR PWM TIMER DEAD ZONE GENERATOR The Dead Zone is for the PWM control in a power device This function enables the insertion of the time gap between a turn off of a switching device and a turn on of another switching device This time gap prohibits the two switching devices from being turned on simultaneously even for a very short time TOUTO is the PWM output nTOUTO is the inversion of the TOUTO If the dead zone is enabled the output wave form of TOUTO and nTOUTO will be TOUTO DZ and nTOUTO DZ respectively nNTOUTO_DZ is routed to the TOUT1 pin In the dead zone interval TOUTO DZ and nTOUTO DZ can never be turned on simultaneously Deadzone Interval TOUTO DZ 111 jji jj Figure 10 7 The Wave Form When a Dead Zone Feature is Enabled gt ELECTRONICS 10 9 PWM TIMER S3C2440A RISC MICROPROCESSOR DMA REQUEST MODE The PWM timer can generate a DMA request at every specific time The timer keeps DMA request signals nDMA_REQ low until the timer receives an
144. be compared against or added to Lo register values with the CMP and ADD instructions For more information Please refer to Figure 3 34 THE PROGRAM STATUS REGISTERS The ARM92OT contains a Current Program Status Register CPSR plus five Saved Program Status Registers SPSRs for use by exception handlers These register s functions are e Hold information about the most recently performed ALU operation e Control the enabling and disabling of interrupts e Set the processor operating mode The arrangement of bits is shown in Figure 2 6 Condition Code Flags Resverved Control Bits 7 6 5 4 3 2 1 0 sn 31 30 29 28 27 26 25 24 23 Overflow Mode bits Carry Borrow Extend State bits Zero FIQ disable Negative Less Than IRQ disable Figure 2 6 Program Status Register Format ELECTRONICS 2 7 PROGRAMMER S MODEL 53 2440 RISC MICROPROCESSOR The Condition Code Flags The N Z C and V bits are the condition code flags These may be changed as a result of arithmetic and logical operations and may be tested to determine whether an instruction should be executed In ARM state all instructions may be executed conditionally see Table 3 2 for details In THUMB state only the Branch instruction is capable of conditional execution see Figure 3 46 for details The Control Bits The bottom 8 bits of a PSR incorporating 1 F T and M 4 0 are known collectively as the control bits These will be changed when an exception
145. because multiple registers are read For example when the user reads the registers from BCDYEAR to BCDMIN the result is assumed to be 2059 Year 12 Month 31 Date 23 Hour and 59 Minute When the user read the BCDSEC register and the value ranges from 1 to 59 Second there is no problem but if the value is 0 sec the year month date hour and minute may be changed to 2060 Year 1 Month 1 Date 0 Hour and 0 Minute because of the one second deviation that was mentioned In this case the user should re read from BCDYEAR to BCDSEC if BCDSEC is zero BACKUP BATTERY OPERATION The RTC logic can be driven by the backup battery which supplies the power through the RTCVDD pin into the RTC block even if the system power is off When the system is off the interfaces of the CPU and RTC logic should be blocked and the backup battery only drives the oscillation circuit and the BCD counters to minimize power dissipation 17 2 ELECTRONICS 53 2440 RISC MICROPROCESSOR REAL TIME CLOCK ALARM FUNCTION The RTC generates an alarm signal at a specified time in the power off mode or normal operation mode In normal operation mode the alarm interrupt INT RTO is activated In the power off mode the power management wakeup PMWKUP signal is activated as well as the INT RTC The alarm register RTCALM determines the alarm enable disable status and the condition of the alarm time setting TICK TIME INTERRUPT The RTC tic
146. bit ELECTRONICS 10 5 PWM TIMER S3C2440A RISC MICROPROCESSOR TIMER OPERATION 14 Figure 10 4 Example of a Operation The above Figure 10 4 shows the result of the following procedure 1 Enable the auto re load function Set the to 160 50 110 and the to 110 Set the manual update bit and configure the inverter bit on off The manual update bit sets TCNTn and TCMPn to the values of TCNTBn and TCMPBn respectively And then set the TCNTBn and the TCMPBn to 80 40 40 and 40 respectively to determine the next reload value 2 Setthe start bit provided that manual update is 0 and the inverter is off and auto reload is on The timer starts counting down after latency time within the timer resolution 3 When the TCNTn has the same value as that of the TCMPn the logic level of the TOUTn is changed from low to high 4 When the TCNTn reaches 0 the interrupt request is generated and TCNTBn value is loaded into a temporary register At the next timer tick the is reloaded with the temporary register value 5 In Interrupt Service Routine ISR the TCNTBn and the TCMPBn are set to 80 20 60 and 60 respectively for the next duration 6 When the TCNTn has the same value as the TCMPn the logic level of TOUTn is changed from low to high 7 When the TCNTn reaches 0 the is reloaded automatically with the TCNTBn triggering an interrupt request
147. controller requests FIQ or IRQ interrupt of the ARM920T core after the arbitration procedure The arbitration procedure depends on the hardware priority logic and the result is written to the interrupt pending register which helps users notify which interrupt is generated out of various interrupt sources Request sources SUBSRCPND SUBMASK SRCPND INTPND with sub register Request sources without sub register O LCD interrupt has different features Please see the chapter 15 LCD Controller Figure 14 1 Interrupt Process Diagram ELECTRONICS 14 1 INTERRUPT CONTROLLER S3C2440A RISC MICROPROCESSOR INTERRUPT CONTROLLER OPERATION F bit and I bit of Program Status Register PSR If the F bit of PSR in ARM920T CPU is set to 1 the CPU does not accept the Fast Interrupt Request FIQ from the interrupt controller Likewise If I bit of the PSR is set to 1 the CPU does not accept the Interrupt Request IRQ from the interrupt controller So the interrupt controller can receive interrupts by clearing F bit or l bit of the PSR to 0 and setting the corresponding bit of INTMSK to O Interrupt Mode The ARM920T has two types of Interrupt mode or IRQ All the interrupt sources determine which mode is used at interrupt request Interrupt Pending Register The S3C2440A has two interrupt pending registers source pending register SRCPND and interrupt pending register INTPND These pending registers indicate whether an int
148. each DMA DCONO 000 nXDREQO 001 UARTO 010 SDI 100 USB device EP1 DCON1 000 nXDREQ1 100 USB device EP2 DCON2 000 1255 100 USB device EP3 DCON3 000 UART2 100 USB device EP4 011 Timer 001 UART1 010 I2SSDI 011 5 001 125501 010 01 011 Timer 001 SDI 010 SPI 011 Timer DCONO 101 12858DO DCON1 101 PCMOUT DCONe 101 PCMIN 110 PCMIN 110 SDI 110 MICIN DCONS 101 MICIN 110 PCMOUT These bits control the 4 1 MUX to select the DMA request source of each DMA These bits have meanings only if H W request mode is selected by DCONn 23 Select the DMA source between software S W request mode and hardware H W request mode 0 S W request mode is selected and DMA is triggered by setting SW TRIG bit of DMASKTRIG control register 1 DMA source selected by bit 26 24 triggers the DMA operation Set the reload on off option 0 auto reload is performed when a current value of transfer count becomes 0 i e all the required transfers are performed 1 channel is turned off when a current value of transfer count becomes 0 The channel on off bit DMASKTRIGn 1 is set to 0 DREQ off to prevent unintended further start of new DMA operation 5 53 2440 RISC MICROPROCESSOR CONTROL REGISTER Continued DSZ 21 20 Data size to be transferred 00 Byte 01 Half word 10 Word 11 reserved 19 0 Initial transfer count
149. ete A assaka aaa IMBUS 11 Stop Coriditioris Data Transfer Format RITE ACK Signal Read Wite Operation e seco Bus Arbitration Procedures Abort rot Gontiguring CH Flowcharts of Operations in Each 0 Interface Special Registers 0 asya apatawa Multi Master 5 Control IICCON Register mH Multi Master Control Status IICSTAT Register essem Multi Master Address IICADD Register essem Multi Master 5 Transmit Receive Data Shift ICDS Multi Master 5 Line Contro 53 2440 MICROCONTROLLER xvii Table of Contents Continued Chapter 21 IIS Bus Interface 21 1 1101 11 TL 21 2 Functional Descriptioris nese 21 2 Transmit or Receive Only Mode
150. fixed order See Exception Priorities on page 2 14 Action on Entering an Exception While handling an exception the ARM920T does following activities 1 Preserves the address of the next instruction in the appropriate Link Register If the exception has been entered from ARM state then the address of the next instruction is copied into the Link Register that is current PC 4 or PC 8 depending on the exception See Table 2 2 on for details If the exception has been entered from state then the value written into the Link Register is the current PC offset by a value such that the program resumes from the correct place on return from the exception This means that the exception handler need not determine which state the exception was entered from For example in the case of SWI MOVS PC R14 svc will always return to the next instruction regardless of whether the SWI was executed in ARM state Copies the CPSR into the appropriate SPSR Forces the CPSR mode bits to a value which depends on the exception Forces the PC to fetch the next instruction from the relevant exception vector It may also set the interrupt disable flags to prevent otherwise unmanageable nestings of exceptions If the processor is in THUMB state when an exception occurs it will automatically switch into ARM state when the PC is loaded with the exception vector address Action on Leaving an Exception On completion the exception handler
151. horizontal line corresponds to three times the number of pixels of one horizontal line These results in a horizontal shift register of length 3 times the number of pixels per horizontal line This RGB is shifted to the LCD driver as consecutive bits via the parallel data lines Figure 15 3 shows the RGB and order of the pixels in the parallel data lines for the 3 types of color displays 4096 Color Displays Color displays require 3 bits Red Green and Blue of image data per pixel and so the number of horizontal shift registers for each horizontal line corresponds to three times the number of pixels of one horizontal line This RGB is shifted to the LCD driver as consecutive bits via the parallel data lines This RGB order is determined by the sequence of video data in video buffers 15 8 ELECTRONICS 53 2440 RISC MICROPROCESSOR LCD CONTROLLER MEMORY DATA FORMAT STN BSWP 0 Mono 4 bit Dual Scan Display LCD Panel Video Buffer Memory 31 30 Address Data 0000H 81 0 0004H 31 0 1311 30 1000H L 31 0 1004H M 31 0 Mono 4 bit Single Scan Display amp 8 bit Single LCD Panel Scan Display 31 30 A 29 Video Buffer Memory Address Data 0000H 31 0 0004H B 31 0 0008H C 31 0 ELECTRONICS 15 9 LCD CONTROLLER S3C2440A RISC MICROPROCESSOR MEMORY DATA FORMAT STN BSWP 0 CONTINUED In 4 level gray mode 2 bits of video data correspond to 1 pixel In 16 level gray mode 4 bits o
152. in Figure 27 32 IIS Interface Timing Diagram tSCLHIGH tSCLLOW tSTOPH STARTS IICSDA Figure 27 33 IIC Interface Timing Diagram 27 32 ELECTRONICS 53 2440 RISC MICROPROCESSOR ELECTRICAL DATA SDCMD out 1 1 15005 4 150 0 out es an 1 1 15005 tSDDH 1 Figure 27 34 SD MMC Interface Timing Diagram SPICLK I I SPIMOSI 1 1 I I I I I tsPISIS tSPISIH I I SPIMOSI SI SPIMISO SO tsPIMIS i M tSPIMIH 1 1 Figure 27 35 SPI Interface Timing Diagram 1 CPOL 1 ELECTRONICS 27 33 ELECTRICAL DATA S3C2440A RISC MICROPROCESSOR tACLS tWRPHO tWRPH1 tACLS tWRPH1 e gt I I nFWE 1 I I I gt lt twos gt DATAI7 0 Command tWRPHO tWRPH1 tWRPH1 DATA 7 0 DATA 7 0 Figure 27 37 NAND Flash Timing Diagram 27 34 ELECTRONICS 53 2440 RISC MICROPROCESSOR ELECTRICAL DATA Table 27 7 Clock Timing Constants Parameter Crystal clock input frequency Crystal clock input cycle time External clock input frequency External clock input cycle time External clock input low level pulse width External clock to HCLK without HCLK internal to CLKOUT HCLK internal to SCLK 2 External clock input high level pulse width n tR t ns or E
153. in the transfer list and may have been overwritten before the abort occurred The data abort trap is taken when the load multiple has completed and the system software must undo any base modification and resolve the cause of the abort before restarting the instruction INSTRUCTION CYCLE TIMES Normal LDM instructions take nS 1N 11 PC takes n 1 S 2N 11 incremental cycles where S N and are defined as sequential S cycle non sequential N cycle and internal I cycle respectively STM instructions take n 1 S 2N incremental cycles to execute where n is the number of words transferred 3 44 ELECTRONICS 53 2440 RISC MICROPROCESSOR ARM INSTRUCTION SET ASSEMBLER SYNTAX lt LDM STM gt cond lt FD ED FA EA IA IB IDA DB gt Rn lt Rlist gt where cond Two character condition mnemonic See Table 3 2 Rn An expression evaluating to a valid register number lt Rlist gt A list of registers and register ranges enclosed in e g RO R2 R7 R10 n If present requests write back W 1 otherwise W 0 If present set bit to load the CPSR along with the PC or force transfer of user bank when in privileged mode Addressing Mode Names There are different assembler mnemonics for each of the addressing modes depending on whether the instruction is being used to support stacks or for other purposes The equivalence between the names and the values of the bits in the instruction are shown in
154. indicates that the received data does not have a valid stop bit The break condition indicates that RxDn input is held in the logic 0 state for a duration longer than one frame transmission time Receive time out condition occurs when it does not receive any data during the 3 word time this interval follows the setting of Word Length bit and the Rx FIFO is not empty in the FIFO mode ELECTRONICS 11 3 UART S3C2440A RISC MICROPROCESSOR Auto Flow Control AFC The S3C2440A s UART 0 and UART 1 support auto flow control with nRTS and nCTS signals In case it can be connected to external UARTs If users want to connect a UART to a Modem disable auto flow control bit in UMCONn register and control the signal of nRTS by software In AFC nRTS depends on the condition of the receiver and nCTS signals control the operation of the transmitter The UART s transmitter transfers the data in FIFO only when nCTS signals are activated in AFC nCTS means that other UART s FIFO is ready to receive data Before the UART receives data nRTS has to be activated when its receive FIFO has a spare more than 32 byte and has to be inactivated when its receive FIFO has a spare under 32 byte in AFC nRTS means that its own receive FIFO is ready to receive data Transmission Case in UART A Reception Case in UART A Figure 11 2 UART AFC interface NOTE UART 2 does not support AFC function because the S8C2440A has nRTS2 and 52 Exampl
155. is enabled When 1 the pull up resister is disabled If the port pull up register is enabled then the pull up resisters work without pin s functional setting input output DATAn EINTn and etc MISCELLANEOUS CONTROL REGISTER This register controls DATA port pull up resister in Sleep mode USB pad and CLKOUT selection EXTERNAL INTERRUPT CONTROL REGISTER The 24 external interrupts are requested by various signaling methods The EXTINT register configures the signaling method among the low level trigger high level trigger falling edge trigger rising edge trigger and both edge trigger for the external interrupt request Because each external interrupt pin has a digital filter the interrupt controller can recognize the request signal that is longer than 3 clocks EINT 15 0 are used for wakeup sources ELECTRONICS 9 7 PORTS 53 2440 RISC MICROPROCESSOR PORT CONTROL REGISTER PORT A CONTROL REGISTERS GPACON GPADAT S UM C Reseved meson Reseed j Dee 0 Output 1 ADDR26 0 Output 1 ADDR25 GPA9 9 0 Output 1 ADDR24 B8 0 Output 1 ADDR23 0 Output 1 ADDR22 GPA6 6 0 Output 1 ADDR21 0 Output 1 ADDR20 0 Output 1 ADDR19 0 Output 1 ADDR18 0 Output 1 ADDR17 0 Output 1 ADDR16 NOTE The GPA21 signal level depends on VDDOP the other pads GPA0 20 GPA22 24 are on VDDMOP 9 8 ELECTRONICS
156. is requested when LCD FIFO reaches trigger level LCD FIFO interrupt pending bit 0 The interrupt has not been requested LCD Source Pending Register LCDSRCPND 0 40000058 Indicate the LCD interrupt source pending register INT FrSyn 1 LCD frame synchronized interrupt source pending bit 0 The interrupt has not been requested 1 The frame has asserted the interrupt request INT FiCnt LCD FIFO interrupt source pending bit 0 The interrupt has not been requested 1 LCD FIFO interrupt is requested when LCD FIFO reaches trigger level 15 38 ELECTRONICS 53 2440 RISC MICROPROCESSOR LCD CONTROLLER LCD Interrupt Mask Register LCDINTMSK 0X4D00005C R W Determine which interrupt source is masked 0x3 The masked interrupt source will not be serviced FIWSEL 2 Determine the trigger level of LCD FIFO 0 4 words 1 8 words INT FrSyn 1 Mask LCD frame synchronized interrupt 1 0 The interrupt service is available 1 The interrupt service is masked INT FiCnt Mask LCD FIFO interrupt 1 0 The interrupt service is available 1 The interrupt service is masked ELECTRONICS 15 39 LCD CONTROLLER S3C2440A RISC MICROPROCESSOR TCON Control Register TCONSEL 0X4D000060 This register controls the LPC3600 LCC3600 modes OxF84 LCC SEL2 Select Line Dot inversion LCC SEL1 5 Select DG Normal mode 9 LCC 4 Determine LCC3600 Enable Disable M 0 2 LCC3600 Disable BH 1 2 LC
157. is set In practice fifteen different conditions may be used these are listed in Table 3 2 The sixteenth 1111 is reserved and must not be used In the absence of a suffix the condition field for most instructions is set to Always suffix AL This means the instruction will always be executed regardless of the CPSR condition codes Table 3 2 Condition Code Summary wm js 0 3 4 ELECTRONICS 53 2440 RISC MICROPROCESSOR ARM INSTRUCTION SET BRANCH AND EXCHANGE BX This instruction is only executed if the condition is true The various conditions are defined in Table 3 2 This instruction performs a branch by copying the contents of a general register Rn into the Program Counter PC The branch causes a pipeline flush and refill from the address specified by Rn This instruction also permits the instruction set to be exchanged When the instruction is executed the value of Rn 0 determines whether the instruction stream will be decoded as ARM or instructions 31 28 27 24 23 20 19 16 15 12 11 215 i 133 11669341 8 3 0 Register If bitO of Rn 1 subsequent instructions decoded as THUMB instructions If bitO of Rn 0 subsequent instructions decoded as ARM instructions 31 28 Condition Field Figure 3 2 Branch and Exchange Instructions INSTRUCTION CYCLE TIMES The BX instruction takes 2S 1N cycles to execute
158. is the data of line 9 of virtual screen The same size of LCD panel This is the data of line 10 of virtual screen This is the data of line 11 of virtual screen LCDBASEU Before Scrolling LCDBASEL This is the data of Nine 1 of virtual screen This i the data of line 1 of virtual screen This is the data of line 2 of virtual screen This is the data of line 2 of virtual screen This is the data of line 3 of virtual screen This is the data of line 4 of virtual screen This is the data of line 5 of virtual screen This is the data of line 6 of virtual screen This is the data of line 7 of virtual screen This is the data of line 8 of virtual screen This is the data of line 9 of virtual screen This is the data of line 9 of virtual screen This is the data of line 10 of virtual screen This is the data of line 10 of virtual screen This is the data of line 11 of virtual screen This is the data of line 11 of virtual screen After Scrolling Figure 15 7 Example of Scrolling in Virtual Display Single Scan ELECTRONICS 15 25 LCD CONTROLLER S3C2440A RISC MICROPROCESSOR LCD POWER ENABLE STN TFT The S3C2440A provides Power enable PWREN function When PWREN is set to make PWREN signal enabled the output value of LCD_PWREN pin is controlled by ENVID In other words If LCD PWREN pin is connected to the power on off control pin of the LCD panel the power of LCD panel is controlled by the setting of ENVID automati
159. method Y Frame Memory ITU 601 656 YCbCr Ss 4 2 2 8 bit input timing Little endian method Cb Frame Memory PCLK Camera Interface DATA 6 Y XCb1 X Y2 X Cri X XCb2X Y4 X Y n Little endian method Cr Frame Memory RGB Frame Memory 24 bit RGB Frame Memory 16 bit Figure 23 7 Memory Storing Style 23 8 ELECTRONICS 53 2440 RISC MICROPROCESSOR CAMERA INTERFACE TIMING DIAGRAM FOR REGISTER SETTING The first register setting for frame capture command can occur anywhere in the frame period But it is recommended that you set it at the CAMVSYNC L state first and the information can be read from the status SFR Please see next page All command include ImgCptEn is valid at falling edge But be careful that except for first SFR setting all command should be programmed in an ISR Interrupt Service Routine Especially capture operation should be disabled when related information for target size are changed CAMVSYNC CAMHREF INTERRUPT Multi frame capturing Image Capture SFR setting ImgCptEn Frame Capture Start gt CAMVSYNC 4 5 INTERRUPT 1 In Capturing i ooo I Image Capture New Command Reserved 1 New SFR command in ISR lt New Command Valid Timing Diagram gt Figure 23 8 Timing Diagram for Register Setting NOTE FIFO overflow of code
160. obsolete because of the execution time of Interrupt Service Routine ISR ELECTRONICS 15 33 LCD CONTROLLER S3C2440A RISC MICROPROCESSOR FRAME Buffer Start Address 3 Register LCDSADDR3 0X4D00001C STN TFT Virtual screen address set 0x00000000 OFFSIZE 21 11 Virtual screen offset size the number of half words 00000000000 This value defines the difference between the address of the last half word displayed on the previous LCD line and the address of the first half word to be displayed in the new LCD line PAGEWIDTH 10 0 Virtual screen page width the number of half words 000000000 This value defines the width of the view port in the frame NOTE The values of PAGEWIDTH OFFSIZE must be changed when ENVID bit is 0 Example 1 LCD panel 320 x 240 16 single scan Frame start address 0x0c500000 Offset dot number 2048 dots 512 half words LINEVAL 240 1 Oxef PAGEWIDTH 320 x 4 16 0x50 OFFSIZE 512 0x200 LCDBANK 0x0c500000 gt gt 22 0x31 LCDBASEU 0x100000 gt gt 1 0x80000 LCDBASEL 0x80000 0x50 0x200 x Oxef 1 Oxa2b00 Example 2 LCD panel 320 x 240 16gray dual scan Frame start address 0x0c500000 Offset dot number 2048 dots 512 half words LINEVAL 120 1 0x77 PAGEWIDTH 320 x 4 16 0x50 OFFSIZE 512 0x200 LCDBANK 0x0c500000 gt gt 22 0x31 LCDBASEU 0x100000 gt gt 1 0x80000 LCDBASEL 0x80000 0x50 0x200 x
161. off The other cases for all gray levels are also shown in Table 15 2 In the STN LCD display we should be reminded of one item i e Flicker Noise due to the simultaneous pixel on and off on adjacent frames For example if all pixels on first frame are turned on and all pixels on next frame are turned off the Flicker Noise will be maximized To reduce the Flicker Noise on the screen the average probability of pixel on and off between frames should be the same In order to realize this the Time based Dithering Algorithm which varies the pattern of adjacent pixels on every frame should be used This is explained in detail For the 16 gray level FRC should have the following relationship between gray level FRC 15th gray level should always have pixel on and the 141 gray level should have 6 times pixel on and one times pixel off and the 13th gray level should have 4 times pixel on and one times pixel off and the gray level should always have pixel off as shown in Table 15 2 Table 15 2 Dither Duty Cycle Examples gray level number s _ level number o 3 03 J w o J gt ELECTRONICS 15 7 LCD CONTROLLER S3C2440A RISC MICROPROCESSOR Display Types The LCD controller supports 3 types of LCD drivers 4 bit dual scan 4 bit single scan and 8 bit single scan display mode Figure 15 2 shows these 3 different display types for monochrome di
162. on the LCD control registers in the REGBANK the TIMEGEN can generate the programmable control signals suitable to support many different types of LCD drivers The VFRAME pulse is asserted for the duration of the entire first line at a frequency of once per frame The VFRAME signal is asserted to bring the LCD s line pointer to the top of the display to start over The VM signal helps the LCD driver alternate the polarity of the row and column voltages which are used to turn the pixel on and off The toggling rate of VM signals depends on the MMODE bit of the LCDCON1 register and MVAL field of the LCDCONA register If the MMODE bit is 0 the VM signal is configured to toggle on every frame If the MMODE bit is 1 the VM signal is configured to toggle on the every event of the elapse of the specified number of VLINE by the MVAL 7 0 value Figure 15 4 shows an example for MMODE 0 and for MMODE 1 with the value of MVAL 7 0 0x2 When MMODE 1 the VM rate is related to MVAL 7 0 as shown below VM Rate VLINE Rate 2 x MVAL The VFRAME and VLINE pulse generation relies on the configurations of the HOZVAL field and the LINEVAL field in the 203 registers Each field is related to the LCD size and display mode In other words HOZVAL and LINEVAL can be determined by the size of the LCD panel and the display mode according to the following equation HOZVAL Horizontal display size Number of the valid VD data line 1 In color mod
163. operand or operands to produce the result If the S bit is set and Rd is not R15 see below the V flag in the CPSR will be unaffected The C flag will be set to the carry out from the barrel shifter or preserved when the shift operation is LSL 0 the 7 flag will be set if and only if the result is all zeros and the N flag will be set to the logical value of bit 31 of the result Table 3 3 ARM Data Processing Instructions Assembler Mnemonic OPCode WUB Om oeno OOOO MOV Operand2 operand1 is ignored BIC Operand1 AND NOT operand Bit clear MVN operand2 operand1 is ignored The arithmetic operations SUB RSB ADD ADC SBC RSC CMP CMN treat each operand as a 32 bit integer either unsigned or 2 s complement signed the two are equivalent If the S bit is set and Rd is not R15 the V flag in the CPSR will be set if an overflow occurs into bit 31 of the result this may be ignored if the operands were considered unsigned but warns of a possible error if the operands were 2 s complement signed The C flag will be set to the carry out of bit 31 of the ALU the Z flag will be set if and only if the result was zero and the N flag will be set to the value of bit 31 of the result indicating a negative result if the operands are considered to be 2 s complement signed ELECTRONICS 3 11 ARM INSTRUCTION SET 53 2440 RISC MICROPROCESSOR SHIFTS When the second operand is specified to be a shifted registe
164. or External interrupt BusWidth R W NAND Flash Memory bus width for auto booting and H W Set general access GPG15 0 8 bit bus 1 16 bit bus This bit is determined by GPG15 pin status during reset and wake up from sleep mode After reset the GPG15 can be used as general port or External interrupt This bit can be changed by software 6 12 ELECTRONICS 53 2440 RISC MICROPROCESSOR CONTROL REGISTER NAND FLASH CONTROLLER NFCONT 0x4E000004 NAND flash control register 0x0384 ias Lock tight 13 Soft Lock 12 EnblllegalAccINT 10 EnbRnBINT RnB TransMode EG Reserved um ELECTRONICS Rem Lock tight configuration 0 Disable lock tight 1 Enable lock tight Once this bit is set to 1 you cannot clear Only reset or wake up from sleep mode can make this bit disable can not cleared by software When it is set to 1 the area setting in NFSBLK 0x4E000038 to NFEBLK 0x4E00003C 1 is unlocked and except this area write or erase command will be invalid and only read command is valid When you try to write or erase locked area the illegal access will be occur NFSTAT 3 bit will be set If the NFSBLK and NFEBLK are same entire area will be locked Soft Lock configuration 0 Disable lock 1 Enable lock Soft lock area can be modified at any time by software When it is set to 1 the area setting in NFSBLK 0x4E000038 to 0 4 00003 1 is unlocked and
165. or transfer beat Note that the actual number of bytes that are transferred is computed by the following equation DSZ x TSZ x TC Where DSZ TSZ 1 or 4 and TC represent data size DCONn 21 20 transfer size DCONn 28 and initial transfer count respectively This value will be loaded into CURR only if the CURR is 0 and the DMA ACK is 1 ELECTRONICS 8 11 S3C2440A RISC MICROPROCESSOR DMA STATUS DSTAT REGISTER 0000 9000008 n OMAt count regster 9000008 R DMAzcnnregser 9000008 DMA 8 count regster 9000008 STAT 21 20 Status of this controller 00 Indicates that DMA controller is ready for another DMA request 01 Indicates that DMA controller is busy for transfers CURR TC 19 0 Current value of transfer count 00000h Note that transfer count is initially set to the value of DCONn 19 0 register and decreased by one at the end of every atomic transfer 8 12 ELECTRONICS 53 2440 RISC MICROPROCESSOR CURRENT SOURCE DCSRC REGISTER DCSRC0 0 48000018 0 current source register 0x00000000 DCSRC1 0 48000058 1 current source register 0x00000000 DCSRC2 0 48000098 DMA 2 current source register 0x00000000 DCSRC3 0 48000008 DMA3 current source register 0x00000000 CURR_SRC 30 0 Current source address for DMAn 0x00000000
166. pa AS y 17 1 SG EEEE TE A 17 1 Time Clock Operation u cete e been 17 2 Leap Year Gerneraltor bett ctr ne E adie thes etn elas 17 2 Read Write 2 ra ee Sd dee ee 17 2 Backup Battery Operation u uu hakuyi ush pak u 17 2 Alarm FUNCtiOM eM S 17 3 TICK Aime Interrupt CE 17 3 32 768kHz X Tal Connection 17 3 Real Time Clock Special Registers 17 4 Real Time Clock Control RTCCON 17 4 TICK Time Count TICNT 17 4 RTC Alarm Control RTCALM 17 5 ALARM Second Data ALMSEC 17 6 ALARM Min Data ALMMIN 17 6 ALARM Hour Data ALMHOUR 17 6 ALARM Date Data ALMDATE 17 7 ALARM Data ALMMON 17 7 ALARM Year Data ALMYEAR 17 7 BCD Second BCDSEO Register uuu u a yaaa Qupa enhn nnne h nn esten e
167. pair NOTE All instructions in this group set the CPSR condition codes Table 4 5 Summary of Format 4 Instructions THUNB Assembler ARM Equipment 1011 CMN Rd Rs CMN Rd Rs Set condition codes on Rd Rs ELECTRONICS 4 11 THUMB INSTRUCTION SET 53 2440 RISC MICROPROCESSOR INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 4 5 The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction EXAMPLES EOR R3 R4 EOR and set condition codes ROR R1 RO Rotate Right R1 by the value in RO store the result in R1 and set condition codes NEG R5 R3 Subtract the contents of R3 from zero Store the result in R5 Set condition codes ie R5 R3 CMP R2 R6 Setthe condition codes on the result of R2 R6 MUL RO R7 RO R7 x RO and set condition codes 4 12 ELECTRONICS 53 2440 RISC MICROPROCESSOR THUMB INSTRUCTION SET FORMAT 5 HI REGISTER OPERATIONS BRANCH EXCHANGE 15 4 48 42 11 0 9 8 7 6 5 3 2 0 am am 2 0 Destination Register 5 3 Source Register 6 Hi Operand Flag 2 7 Hi Operand Flag 1 9 8 Opcode Figure 4 6 Format 5 OPERATION There are four sets of instructions in this group The first three allow ADD CMP and MOV operations to be performed between Lo and Hi registers or a pair of Hi registers The fourth BX allow
168. the form of compact discs digital audio tapes digital sound processors and digital TV sound The 53 2440 Inter IC Sound IIS bus interface can be used to implement a CODEC interface to an external 8 16 bit stereo audio CODEC IC for mini disc and portable applications The IIS bus interface supports both IIS bus data format and MSB justified data format The interface provides DMA transfer mode for FIFO access instead of an interrupt It can transmit and receive data simultaneously as well as transmit or receive data alternatively at a time ELECTRONICS 21 1 IIS BUS INTERFACE 53 2440 RISC MICROPROCESSOR BLOCK DIAGRAM TxFIFO MPLLin Figure 21 1 15 Block Diagram FUNCTIONAL DESCRIPTIONS Bus interface register bank and state machine BRFC Bus interface logic and FIFO access are controlled by the state machine 5 bit dual prescaler IPSR One prescaler is used as the master clock generator of the IIS bus interface and the other is used as the external CODEC clock generator 64 byte FIFOs TxFIFO and RxFIFO In transmit data transfer data are written to TxFIFO and in the receive data transfer data are read from RxFIFO Master IISCLK generator SCLKG In master mode serial bit clock is generated from the master clock Channel generator and state machine IISCLK and IISLRCK are generated and controlled by the channel state machine 16 bit shift register SFTR Parallel data is shifted to seria
169. the longest instruction to complete the longest instruction is LDM which loads all the registers including the PC plus the time for the data abort entry plus the time for entry Tfiq At the end of this time ARM920T will be executing the instruction at Ox1C Tsyncmax is 3 processor cycles Tldm is 20 cycles Texc is 3 cycles and Tfiq is 2 cycles The total time is therefore 28 processor cycles This is just over 1 4 microseconds in a system which uses a continuous 20 MHz processor clock The maximum IRQ latency calculation is similar but must allow for the fact that FIQ has higher priority and could delay entry into the IRQ handling routine for an arbitrary length of time The minimum latency for FIQ or IRQ consists of the shortest time the request can take through the synchronizer Tsyncmin plus Tfiq This is 4 processor cycles RESET When the nRESET signal goes LOW ARM920T abandons the executing instruction and then continues to fetch instructions from incrementing word addresses When nRESET goes HIGH again ARM920T 1 Overwrites R14 and SPSR svc by copying the current values of the and CPSR into them The value of the saved PC and SPSR is not defined Forces M 4 0 to 10011 Supervisor mode sets the and F bits in the CPSR and clears the CPSR s T bit Forces the PC to fetch the next instruction from address 0x00 Execution resumes in ARM state ELECTRONICS 2 15 PROGRAMMER S MODEL 5
170. the nFIQ input LOW This input can except either synchronous or asynchronous transitions depending on the state of the ISYNC input signal When ISYNC is LOW nFIQ and nIRQ are considered asynchronous and a cycle delay for synchronization is incurred before the interrupt can affect the processor flow Irrespective of whether the exception was entered from ARM or Thumb state a FIQ handler should leave the interrupt by executing SUBS PC R14 FIQ may be disabled by setting the CPSR s F flag but note that this is not possible from User mode If the F flag is clear ARM920T checks for a LOW level on the output of the FIQ synchronizer at the end of each instruction ELECTRONICS 2 11 PROGRAMMER S MODEL 53 2440 RISC MICROPROCESSOR IRQ The IRQ Interrupt Request exception is a normal interrupt caused by a LOW level on the nIRQ input IRQ has a lower priority than FIQ and is masked out when a FIQ sequence is entered It may be disabled at any time by setting I bit in the CPSR though this can only be done from a privileged non User mode Irrespective of whether the exception was entered from ARM or Thumb state an IRQ handler should return from the interrupt by executing SUBS PC R14_irg 4 Abort An abort indicates that the current memory access cannot be completed It can be signaled by the external ABORT input ARM920T checks for the abort exception during memory access cycles There are two types of abort Prefetch A
171. threshold CMOS 2 0 Schmitt trigger negative going threshold CMOS v _ lH High level input current mute neo Low level input current pub 9 puber High level output voltage V weBremz foa pop V Low level output voltage Type B4 to B12 1 4 loL 4 mA OL Type B10 lo 10 Type B12 12 mA NOTES 1 B6 means 6mA output driver cell 2 Type B8 means 8mA output driver cell ELECTRONICS 27 3 ELECTRICAL DATA S3C2440A RISC MICROPROCESSOR Normal I O PAD DC Electrical Characteristics for Memory V ppyop 3 0V 0 3V 3 3V 0 3V T 40 to 85 C Parameters Conon Mm High level input voltage V wowsmeme Low level input voltage V 11 21 261 v Vr vege negatve gong os High level input current HA Low level input current V Ll lcm NOTES 1 Type B6 means 6mA output driver cell 2 Type B8 means 8mA output driver cell 3 Type B12 means 12 output driver cells 27 4 ELECTRONICS 53 2440 RISC MICROPROCESSOR ELECTRICAL DATA Normal I O PAD DC Electrical Characteristics for V ppop 3 3V 0 3V T4
172. through to 16 if itis a word address plus one byte and so on The selected byte is placed in the bottom 8 bit of the destination register and the remaining bits of the register are filled with the sign bit bit 7 of the byte Please see Figure 2 1 A halfword load LDRSH or LDRH expects data on data bus inputs 31 through to 16 if the supplied address is on a word boundary and on data bus inputs 15 through to 0 if it is a halfword boundary A 1 1 The supplied address should always be on a halfword boundary If bit 0 of the supplied address is HIGH then the ARM920T will load an unpredictable value The selected halfword is placed in the bottom 16 bits of the destination register For unsigned half words LDRH the top 16 bits of the register are filled with zeros and for signed half words LDRSH the top 16 bits are filled with the sign bit bit 15 of the halfword A halfword store STRH repeats the bottom 16 bits of the source register twice across the data bus outputs 31 through to 0 The external memory system should activate the appropriate halfword subsystem to store the data NOTE Please note that the address must be halfword aligned if bit 0 of the address is HIGH this will cause unpredictable behavior USE OF R15 Write back should not be specified if R15 is specified as the base register Rn While using R15 as the base register you must remember it contains address 8 bytes on from the address of the current instruction R15 sh
173. timer only with no output pins The timer 0 has a dead zone generator which is used with a large current device The timer 0 and 1 share an 8 bit prescaler while the timer 2 3 and 4 share other 8 bit prescaler Each timer has a clock divider which generates 5 different divided signals 1 2 1 4 1 8 1 16 and TCLK Each timer block receives its own clock signals from the clock divider which receives the clock from the corresponding 8 bit prescaler The 8 bit prescaler is programmable and divides the PCLK according to the loading value which is stored in TCFGO and TCFG registers The timer count buffer register TCNTBn has an initial value which is loaded into the down counter when the timer is enabled The timer compare buffer register TCMPBn has an initial value which is loaded into the compare register to be compared with the down counter value This double buffering feature of and TCMPBn makes the timer generate a stable output when the frequency and duty ratio are changed Each timer has its own 16 bit down counter which is driven by the timer clock When the down counter reaches zero the timer interrupt request is generated to inform the CPU that the timer operation has been completed When the timer counter reaches zero the value of corresponding TCNTBn is automatically loaded into the down counter to continue the next operation However if the timer stops for example by clearing the timer enable bit of TCONn during t
174. true The various conditions are defined in Table 3 2 The instruction encoding is shown in Figure 3 14 The single data transfer instructions are used to load or store single bytes or words of data The memory address used in the transfer is calculated by adding an offset to or subtracting an offset from a base register The result of this calculation may be written back into the base register if auto indexing is required 28 27 26 25 24 23 22 21 20 19 16 15 12 11 0 ore S 15 12 Source Destination Registers 19 16 Base Register 20 Load Store Bit 0 Store to memory 1 Load from memory 21 Write back Bit 0 No write back 1 Write address into base 22 Byte Word Bit 0 Transfer word quantity 1 Transfer byte quantity 23 Up Down Bit 0 Down subtract offset from base 1 Up add offset to base 24 Pre Post Indexing Bit 0 Post add offset after transfer 1 Pre add offset before transfer 25 Immediate Offset 0 Offset is an immediate value 11 0 Offset 11 0 11 0 Unsigned 12 bit immediate offset 11 4 3 0 3 0 Offset register 11 4 Shift applied to Rm 31 28 Condition Field Figure 3 14 Single Data Transfer Instructions 3 28 ELECTRONICS 53 2440 RISC MICROPROCESSOR ARM INSTRUCTION SET OFFSETS AND AUTO INDEXING The offset from the base may be either a 12 bit unsigned binary immediate value in the instruction or a second register possibly s
175. where S and are defined as sequential S cycle and non sequential N cycle respectively ASSEMBLER SYNTAX BX branch and exchange BX cond Rn cond Two character condition mnemonic See Table 3 2 Rn is an expression evaluating to a valid register number USING R15 AS AN OPERAND If R15 is used as an operand the behavior is undefined ELECTRONICS 3 5 ARM INSTRUCTION SET 53 2440 RISC MICROPROCESSOR Examples ADR RO THUMB 1 Generate branch target address and set bit 0 high hence it comes in THUNB state BX RO Branch and change to THUMB state CODE16 Assemble subsequent code as Into THUMB THUMB instructions hence bit 0 is low and so change back to ARM state 3 6 ELECTRONICS 53 2440 RISC MICROPROCESSOR ARM INSTRUCTION SET BRANCH AND BRANCH WITH LINK B BL The instruction is only executed if the condition is true The various conditions are defined Table 3 2 The instruction encoding is shown in Figure 3 3 below 31 2827 252423 0 24 Link bit 0 Branch 1 Branch with link 31 28 Condition Field Figure 3 3 Branch Instructions Branch instruction contains a signed 2 s complement 24 bit offset This is shifted left two bits sign extended to 32 bits and added to the PC The instruction can therefore specify a branch of 32Mbytes The branch offset must take account of the prefetch operation which causes the PC to be 2 words 8 bytes ahea
176. 0 SDRAM SDRAM BANK BANK 0000 PANK nGCS6 BANK6 nGCS6 BANK BANK 0000 88 n GS nGCS5 SROM SROM nGCS4 4 nGCS4 0x2000 0000 SROM SROM nGCS3 nGCS3 SROM SROM EN BANK2 nGCS2 2 nGCS2 SROM SROM BANK1 nGCS1 BANK1 nGCS1 nGCS0 BootSRAM 4 0 0000_0000 1 0 01 10 ON 1 0 00 Figure 6 5 Flash Memory Mapping NOTE SROM means ROM or SRAM type memory ELECTRONICS 6 9 NAND FLASH CONTROLLER 53 2440 RISC MICROPROCESSOR NAND FLASH MEMORY CONFIGURATION DATAI7 DATA 6 DATA 4 DATAI3 DATA 2 DATA 1 DATA 0 Figure 6 6 A 8 bit NAND Flash Memory Interface When you write the address the same address is issued from data 7 0 and data 15 8 DATA 7 B DATA 15 DATA 6 RE DATA 14 DATA 5 DATA 13 DATA 4 DATA 12 DATA 3 ALE DATA 11 DATA 2 DATA 10 DATA 1 DATA 9 DATA 0 DATA 8 Figure 6 7 Two 8 bit NAND Flash Memory Interface 6 10 ELECTRONICS 53 2440 RISC MICROPROCESSOR NAND FLASH CONTROLLER DATA 15 DATA 14 DATA 13 DATA 12 DATA 11 DATA 10 DATA 9 DATA 8 DATAI7 DATA 6 5 DATA 4 DATA 3 DATA 2 DATA 1 DATA 0 Figure 6 8 A 16 bit NAND Flash Memory Interface ELECTRONICS 6 11 NAND FLASH CONTROLLER 53 2440 RISC MICROPROCESSOR NAND FLASH CONFIGURATION
177. 0 ELECTRONICS 53 2440 RISC MICROPROCESSOR ARM INSTRUCTION SET USE OF R15 Write back must not be specified if R15 is specified as the base register Rn While using R15 as the base register you must remember it contains an address of 8 bytes on from the address of the current instruction R15 must not be specified as the register offset Rm When R15 is the source register Rd of a register store STR instruction the stored value will be address of the instruction plus 12 Restriction are made depending on the use of base register When configured for late aborts the following example code is difficult to unwind as the base register Rn gets updated before the abort handler starts Sometimes it may be impossible to calculate the initial value After an abort the following example code is difficult to unwind as the base register Rn gets updated before the abort handler starts Sometimes it may be impossible to calculate the initial value EXAMPLE LDR RO R1 R1 Therefore a post indexed LDR or STR where Rm is the same register as Rn should not be used DATA ABORTS A transfer to or from a legal address may cause problems for a memory management system For instance in a System which uses virtual memory the required data may be absent from main memory The memory manager can signal a problem by taking the processor ABORT input HIGH whereupon the Data Abort trap will be taken It is up to the system software to resolve th
178. 000 Low level 001 High level 01x Falling edge triggered 10x Rising edge triggered 11x Both edge triggered PORTS 9 29 PORTS 53 2440 RISC MICROPROCESSOR EXTINTn External Interrupt Control Register n Continued FLTEN17 7 Filter enable for EINT17 0 Filter Disable 1 Filter Enable EINT17 6 4 Setting the signaling method of the EINT17 000 Low level 001 High level 01x Falling edge triggered 10x Rising edge triggered 11x Both edge triggered FLTEN16 3 Filter enable for EINT16 0 Filter Disable 1 Filter Enable EINT16 2 0 Setting the signaling method of the EINT16 000 Low level 001 High level 01x Falling edge triggered 10x Rising edge triggered 11x Both edge triggered 9 30 ELECTRONICS 53 2440 RISC MICROPROCESSOR PORTS EINTFLTn External Interrupt Filter Register n To recognize the level interrupt the valid logic level on EXTINTn pin must be retained for 40ns at least because of the noise filter EINTFLT2 0x5600009c External interrupt control register 2 0x000000 EINTFLT3 0x4c6000a0 External interrupt control register 3 0x000000 EINTFLT19 30 24 Filtering width of EINT19 FLTCLK18 23 Filter clock of EINT18 configured by OM 0 PCLK 1 EXTCLK OSC_CLK EINTFLT18 22 16 Filtering width of EINT18 FLTCLK17 15 Filter clock of EINT17 configured by OM 0 PCLK 1 EXTCLK OSC_CLK EINTFLT17 14 8 Filtering width of EINT17 FLTCLK16 7 Filter clo
179. 01 MOV Rd Op2 1110 BIC Rd Op1 AND NOT Op2 1111 MVN Rd NOT Op2 25 Immediate operand 0 Operand 2 is a register 1 Operand 2 is an immediate value 11 0 Operand 2 type selection 11 3 4 0 9 0 2nd operand register 11 4 Shift applied to Rm 11 8 7 7 0 Unsigned 8 bit immediate value 11 8 Shift applied to Imm 31 28 Condition field Figure 3 4 Data Processing Instructions ELECTRONICS 3 9 ARM INSTRUCTION SET 53 2440 RISC MICROPROCESSOR The instruction produces a result by performing a specified arithmetic or logical operation on one or two operands The first operand is always a register Rn The second operand may be a shifted register Rm or a rotated 8 bit immediate value Imm according to the value of the I bit in the instruction The condition codes in the CPSR may be preserved or updated as a result of this instruction according to the value of the S bit in the instruction Certain operations TST TEQ CMP CMN do not write the result to Rd They are used only to perform tests and to set the condition codes on the result and always have the S bit set The instructions and their effects are listed in Table 3 3 3 10 ELECTRONICS 53 2440 RISC MICROPROCESSOR ARM INSTRUCTION SET CPSR FLAGS The data processing operations can be classified as logical or arithmetic The logical operations AND EOR TST TEQ ORR MOV BIC MVN perform the logical action on all corresponding bits of the
180. 0A RISC MICROPROCESSOR FUNCTIONAL DESCRIPTION CLOCK ARCHITECTURE Figure 7 1 shows a block diagram of the clock architecture The main clock source comes from an external crystal or an external clock EXTCLK The clock generator includes an oscillator Oscillation Amplifier which is connected to an external crystal and also has two PLLs Phase Locked Loop which generate the high frequency clock required in the 53 2440 CLOCK SOURCE SELECTION Table 7 1 shows the relationship between the combination of mode control pins and 2 and the selection of source clock for the 53C2440A The OM 3 2 status is latched internally by referring the and OM pins at the rising edge of nRESET Table 7 1 Clock Source Selection at Boot Up Mode ON 3 2 MPLL State UPLL State Main Clock source USB Clock Source o O O ow NOTES 1 Although the MPLL starts just after a reset the MPLL output Mpll is not used as the system clock until the software writes valid settings to the MPLLCON register Before this valid setting the clock from external crystal or EXTCLK source will be used as the system clock directly Even if the user does not want to change the default value of MPLLCON register the user should write the same value into MPLLCON register 2 ON 32 is used to determine test mode when 1 01 is 11 7 2 ELECTRONICS 53 2440 RISC MICROPROCESSOR CLOCK amp POWER MANAGEMENT ON 3 2
181. 0x00000000 value will be loaded into SRC only if the CURR_SRC is 0 and the DMA ACK is 1 DMA INITIAL SOURCE CONTROL DISRCC REGISTER LOC 1 Bit 1 is used to select the location of source 0 the source is in the system bus AHB 1 the source is in the peripheral bus APB INC Bit 0 is used to select the address increment 0 Increment 1 Fixed If it is 0 the address is increased by its data size after each transfer in burst and single transfer mode If it is 1 the address is not changed after the transfer In the burst mode address is increased during the burst transfer but the address is recovered to its first value after the transfer ELECTRONICS 8 7 S3C2440A RISC MICROPROCESSOR DMA INITIAL DESTINATION DIDST REGISTER D ADDR 30 0 Base address start address of destination for the transfer This bit 0x00000000 value will be loaded into CURR_SRC only if the CURR DST is 0 and the DMA ACK is 1 DMA INITIAL DESTINATION CONTROL DIDSTC REGISTER DIDSTCn Bit Description Initial State CHK INT 2 Select interrupt occurrence time when auto reload is setting 0 Interrupt will occur when TC reaches 0 1 Interrupt will occur after auto reload is performed LOC 1 Bit 1 is used to select the location of destination 0 the destination is in the system bus AHB 1 the destination is in the peripheral bus APB INC Bit 0 is used to select the address increment 0 Increment 1 Fi
182. 1 THUMB INSTRUCTION SET 53 2440 RISC MICROPROCESSOR Now fix up the signs of the quotient RO and remainder R1 POP EOR EOR SUB EOR SUB MOV ARM Code signed divide ANDS RSBMI EORS bit 31 sign of result bit 30 sign of a2 RSBCS R2 R3 Get dividend divisor signs back R3 R2 Result sign RO R3 Negate if result sign 1 RO R3 R1 R2 Negate remainder if dividend sign 1 R1 R2 Ir Effectively zero a4 as top bit will be shifted out later a4 a1 amp 80000000 a1 a1 0 ip a4 a2 ASR 32 a2 a2 0 Central part is identical code to udiv without MOV a4 0 which comes for free as part of signed entry sequence MOVS BEQ just_l CMP MOVLS BLO div_ CMP ADC SUBCS TEQ MOVNE BNE MOV MOVS RSBCS RSBMI ce MOV 4 42 a3 al divide_by_zero Justification stage shifts 1 bit at a time a3 a2 LSR 1 a3 a3 LSL 1 NB LSL 1 is always OK if LS succeeds loop a2 a3 a4 a4 a4 a2 a2 a3 a3 a1 a3 a3 LSR 1 s_loop2 al a4 ip ip ASL 1 al a1 0 a2 a2 0 Ir ELECTRONICS 53 2440 RISC MICROPROCESSOR THUMB INSTRUCTION SET DIVISION BY A CONSTANT Division by a constant can often be performed by a short fixed sequence of shifts adds and subtracts Here is an example of a divide by 10 routine based on the algorithm in the ARM Cookbook in both Thumb and ARM code Thumb Code udiv10 Take argument in 1 retu
183. 1 otherwise perform short transfer N 0 cond Two character condition mnemonic See Table 3 2 p The unique number of the required coprocessor cd An expression evaluating to a valid coprocessor register number that is placed in the field lt Address gt can be 1 An expression which generates an address The assembler will attempt to generate an instruction using the PC as base anda corrected immediate offset to address the location given by evaluating the expression This will be a PC relative pre indexed address If the address is out of range an error will be generated 2 A pre indexed addressing specification Rn offset of zero Rn lt expression gt offset of lt expression gt bytes 3 A post indexed addressing specification Rn lt expression offset of lt expression gt bytes n write back the base register set the W bit if is present Rn is an expression evaluating to a valid ARM920T register number NOTE If Rn is R15 the assembler will subtract 8 from the offset value to allow for ARM920T pipelining EXAMPLES LDC p1 c2 table Load c2 of coproc 1 from address table using a PC relative address STCEQL p2 c3 R5 24 Conditionally store c3 of coproc 2 into an address 24 bytes up from R5 write this address back to R5 and use long transfer option probably to store multiple words NOTE Although the address offset is expressed in bytes the instruction offset field is in words
184. 1 Disable 8010 DSC ADR Address Drive strength 00 12mA 10 10 01 8mA 11 DSC_DATA3 7 6 DATA 31 24 I O Drive strength 00 12mA 10 10 01 8mA DSC_DATA2 5 4 DATA 23 16 Drive strength 00 12mA 10 10mA 01 8mA DSC DATA1 3 2 DATA 15 8 I O Drive strength 00 12 10 10mA 01 8mA DSC DATAO 1 0 DATA 7 0 Drive strength 00 12mA 10 10mA 01 8mA 9 36 ELECTRONICS 53 2440 RISC MICROPROCESSOR PORTS DSCn Drive Strength Control DSC SCK1 29 28 SCLK1 drive strength 00 12 10 10 01 8 11 DSC SCKO 27 26 SCLKO drive strength 00 12mA 10 10mA 01 8mA 11 DSC SCKE 25 24 SCKE drive strength 00 10mA 10 8mA 01 6mA 11 4mA DSC SDR 23 22 nSRAS nSCAS Drive strength 00 10mA 10 8mA 01 6mA 11 4mA DSC NFC 21 20 Nand flash control drive strength nFCE nFRE nFWE CLE ALE 00 10mA 10 8mA 01 6mA 11 4mA DSC BE 19 18 nBE 3 0 drive strength 00 10mA 10 8mA 01 6mA DSC WOE 17 16 nWE nOE drive strength 00 10mA 10 8mA 01 6mA DSC CS7 15 14 nGCS7 drive strength 00 10mA 10 8mA 01 6mA DSC CS6 13 12 nGCS6 drive strength 00 10mA 10 8mA 01 6mA DSC CS5 11 10 nGCS5 drive strength 00 10mA 10 8mA 01 6mA DSC 54 nGCS4 drive strength 00 10mA 10 8mA 01 6mA DSC 53 7 6 nGCS3 drive strength 00 10mA 10 8mA 01 6mA DSC CS2 5 4 nGCS2 drive strength 00 10mA 10 8mA 01 6mA DSC CS1 3 2 nGCS1 drive strength 00 10m
185. 1 to the corresponding bit Bom 19 2 ELECTRONICS 53 2440 RISC MICROPROCESSOR MMC SD SDIO CONTROLLER SDIO OPERATION There are two functions of SDIO operation SDIO Interrupt receiving and Read Wait Request generation These two functions can operate when RcvlOInt bit and RwaitEn bit of SDICON register is activated respectively And two functions have the steps and conditions like below SDIO Interrupt In SD 1 bit mode Interrupt is received through all range from RxDAT 1 pin In SD 4 bit mode RxDAT 1 pin is shared between data receiving and interrupt receiving When interrupt detection range Interrupt Period is 1 Single Block The time between A and B A 2clocks after the completion of a data packet B The completion of sending the end bit of the next withdata command 2 Multi Block PrdType 0 The time between A and B restart at C A 2clocks after the completion of a data packet B 2clocks after A C 2clocks after the end bit of the abort command response 3 Multi Block PrdType 1 The time between A and B restart at A A 2clocks after the completion of a data packet B 2clocks after A n case of last block interrupt period begins at A but not ends at B CMD53 case Read Wait Request Regardless of 1bit or 4 bit mode Read Wait Request signal transmits to TxDAT 2 pin in condition of below n read multiple operation request signal transmission begins at 2clocks after the en
186. 1 clock 10 2 clocks 11 4 clocks Tcos 12 11 Chip selection set up time before nOE 00 0 clock 01 1 clock 10 2 clocks 11 4 clocks Tacc 10 8 Access cycle 000 1 clock 001 2 clocks 010 3 clocks 011 4 clocks 100 6 clocks 101 8 clocks 110 10 clocks 111 14 clocks Note When nWAIT signal is used Tacc gt 4 clocks Tcoh 7 6 Chip selection hold time after nOE 00 0 clock 01 1 clock 10 2 clocks 11 4 clocks Tcah 5 4 Address hold time after nGCSn 00 0 clock 01 1 clock 10 2 clocks 11 4 clocks Tacp 3 2 mode access cycle mode 00 2 clocks 01 3 clocks 10 4 clocks 11 6 clocks 1 0 Page mode configuration 00 normal 1 data 01 4 data 10 8 data 11 16 data 5 16 ELECTRONICS 53 2440 RISC MICROPROCESSOR MEMORY CONTROLLER BANK CONTROL REGISTER BANKCONn nGCS6 nGCS7 BANKCON6 0x4800001C Bank 6 control register 0x18008 BANKCON7 0x48000020 Bank 7 control register 0x18008 MT 16 15 Determine the memory type for bank6 and bank7 00 ROM or SRAM 01 Reserved Do not use 10 Reserved Do not use 11 Sync DRAM Memory Type ROM or SRAM MT 00 15 bit Tacs 14 13 Address set up time before nGCS 00 0 01 1 clock 10 2 clocks clocks Tcos 12 11 Chip selection set up time before nOE 00 0 01 1 clock 10 2 clocks clocks Tacc 10 8 Access cycle 000 1 clock 001 2 clocks 010 3 clocks 011 4 clo
187. 10 Data receive mode 11 Data transmit mode Block Number 07 4095 don t care when stream mode 0x000 If you want one of TARSP RACMD BACMD bits SDIDatCon 20 18 to 1 you need to write on SDIDatCon register ahead of on SDICmdCon register always need for SDIO ELECTRONICS MMC SD SDIO CONTROLLER 53 2440 RISC MICROPROCESSOR 19 10 ELECTRONICS 53 2440 RISC MICROPROCESSOR MMC SD SDIO CONTROLLER SDI Data Remain Counter Register ADIDatCnt SDIDatCnt 0x5A000030 R SDI data remain counter register SDiDatCnt Initial Value CC BlkNumCnt 23 12 Remaining block number 0x000 BlkCnt 11 0 Remaining data byte of 1 block 0x000 SDI Data Status Register ADIDatSta SDIDatSta 0x5A000034 R C SDI data status register 0x0 SDIDatSta Initial Value Busy is not active during 16cycle after cmd packet transmitted in only busy check mode This flag is cleared by setting to 1 this bit 0 Not detect 1 No busy signal Read wait Read wait request signal transmits to sd card The request signal request occur is stopped and this flag is cleared by setting to one this bit RWaitReq 0 Not occur 1 Read wait request occur SDIO interrupt 9 SDIO interrupt detect This flag is cleared by setting to one this bit detect lOIntDet R C 0 Not detect 1 SDIO interrupt detect Reseved Bl CRC status fail CRC Status error when data block sent CRC check failed
188. 2 10 5 TH er Operallop mE 10 6 Pulse Width Modulation 10 7 QutputrLeverOoOntrolg n 10 8 Dead Zone Generator faves 10 9 DMA Request MOde ed eh She a A ie E el a ieee ets 10 10 PWM Timer Control Registers A E a deaa 10 11 Timer Configuration RegisterO TCFG0 10 11 Timer Configuration Register1 10 12 Timer Control T CON 10 13 Timer 0 Count Buffer Register amp Compare Buffer Register 10 15 Timer 0 Count Observation Register 10 15 Timer 1 Count Buffer Register amp Compare Buffer Register TCNTB1 TCMPB1 10 16 Timer 1 Count Observation Register TCNTO1 10 16 Timer 2 Count Buffer Register amp Compare Buffer Register TCNTB2 TCMPB2 10 17 Timer 2 Count Observation Register 2 10 17 Timer Count Buffer Register amp Compare Buffer Register 10 18 Timer Count Observation Register 10 18 Timer 4 Count Buffer Register 4 10 19 Timer 4 Count Observation Register 4
189. 22 bit to auto reload and or STOP bit of DMASKTRIGn to stop Note that when DCON 22 bit is no auto reload this bit becomes 0 when CURR reaches 0 the STOP bit is 1 this bit becomes 0 as soon as the current atomic transfer is completed Note This bit should not be changed manually during DMA operations i e this has to be changed only by using DCON 22 or STOP bit SW TRIG Trigger the DMA channel in S W request mode 1 it requests a DMA operation to this controller Note that this trigger gets effective after S W request mode has to be selected DCONn 23 and channel ON OFF bit has to be set to 1 channel on When DMA operation starts this bit is cleared automatically NOTE You are allowed to change the values of DISRC register DIDST registers and TC field of register Those changes take effect only after the finish of current transfer i e when CURR TC becomes 0 On the other hand any change made to other registers and or fields takes immediate effect Therefore be careful in changing those registers and fields 8 14 ELECTRONICS 53 2440 RISC MICROPROCESSOR PORTS I O PORTS OVERVIEW S3C2440A has 130 multi functional input output port pins and there are eight ports as shown below Port A GPA 25 output port Port B GPB 11 input out port Port C GPG Port D GPD Port E GPE 16 input output port Port F Port G GPG 16 input output port Port H GP
190. 3 2440 289 FBGA Pin Assignments Sheet 3 of 9 Continued Function un REQ en nRESET Type Do __ po po DN PDNO __ DPiPDPO DP NI7 16 L13 M15 M17 L14 L15 L16 J10 P11 PWREN GPG GPG4 2 1 K10 EINT13 SPIMISO1 GPG5 5 Hi z Hi zi R11 EINT14 SPIMOSH GPG6 GPG6 Hi z Hi z 110 EINT15 SPICLK1 GPG7 GPG7 Hi z Hi z EM EN EMI EMI e Gre EMI _ NUM ONE NUM _ NUM NUM NUM BE Lm NUM a af oa o o o o 1 12 ELECTRONICS 53 2440 RISC MICROPROCESSOR PRODUCT OVERVIEW Table 1 2 53 2440 289 Pin FBGA Pin Assignments Sheet 4 of 9 Continued Function BUS REQ Sleep nRESET Type j 2 N _ Al r50 z _ Hiz o Hy N N OJO I I Z Z 5 5 Hi Hi Hi Hi z Q 2 N ee all 21019 S IS IS S S N I MH EUM _ EUM ELM EN G6 CEN EEH S S 2 2
191. 3 2440 RISC MICROPROCESSOR 2 16 ELECTRONICS 53 2440 RISC MICROPROCESSOR ARM INSTRUCTION SET INSTRUCTION SET SUMMAY This chapter describes the ARM instruction set in the ARM920T core FORMAT SUMMARY The following figure shows the ARM instruction set 0123456789101112131415 16 17 18 19 20 21 22 2324 25 26 27 28 29 3031 Opcode 5 Operand2 ess jore Rn 00001001 Rm cond 27 r pps ager Cond Offset Cond 11111 CP Opc Cond CP CRn CP Cond a 1 Ignored by processor 0123456789101112131415 16 17 18 19 20 21 22 2324 25 26 27 28 29 3031 Figure 3 1 ARM Instruction Set Format ELECTRONICS ARM INSTRUCTION SET Data Processing PSR Transfer Multiply Multiply Long Single Data Swap Branch and Exchange Halfword Data Transfer register offset Halfword Data Transfer immendiate offset Single Data Transfer Undefined Block Data Transfer Branch Coprocessor Data Transfer Coprocessor Data Operation Coprocessor Register Transfer Software Interrupt 3 1 ARM INSTRUCTION SET 53 2440 RISC MICROPROCESSOR NOTES Some instruction codes are not defined but does not cause Undefined instruction trap to be taken for instance a multiply instruction with bit 6 changed t
192. 3 14 ELECTRONICS 53 2440 RISC MICROPROCESSOR CAMERA INTERFACE CB3 START ADDRESS REGISTER CICOCBSA3 0x4F000030 Cb 379 frame start address for codec DMA CICOCBSA3 31 0 Cb 379 frame start address for codec DMA y o gt a gt g o o m o m CICOCBSA4 0x4F000034 Cb 41 frame start address for codec DMA CICOCBSA4 31 0 Cb 41 frame start address for codec DMA CR1 START ADDRESS REGISTER CICOCRSA1 Ox4F000038 Cr 18 frame start address for codec DMA CICOCRSA1 31 0 1 frame start address for codec DMA N o gt a gt g o o m o m CICOCRSA2 Ox4F00003C Cr 214 frame start address for codec DMA CICOCRSA2 31 0 Cr 2nd frame start address for codec ELECTRONICS 23 15 53 2440 RISC MICROPROCESSOR CAMERA INTERFACE CR3 START ADDRESS REGISTER CICOCRSAS3 Ox4F000040 Cr 394 frame start address for codec CICOCRSA3 31 0 Cr 3nd frame start address for codec DMA CR4 START ADDRESS REGISTER CICOCRSA4 0x4F000044 Cr 41 frame start address for codec DMA CICOCRSA4 31 0 Cr 4th frame start address for codec DMA 23 16 ELECTRONICE 53 2440 RISC MICROPROCESSOR CAMERA INTERFACE CODEC TARGET FORMAT REGISTER CICOTRGFMT 0x4F000048 Target image format of codec DMA In422 Co 31 0 YCbCr 4 2 0 codec scaler input image format In this case horizontal line decimation is performed before codec scaler n
193. 31 24 4th ECC for I O 15 8 ECCData3 0 23 16 4th ECC for I O 7 0 0x00 Note In Software mode Read this register when you need to read 411 ECC value from NAND flash memory ECCData2 1 15 8 for 0 15 8 ECCData2 0 7 0 319 ECC for I O 7 0 0x00 Note In Software mode Read this register when you need to read ECC value from NAND flash memory This register has same read function of NFDATA NOTE Only word access is valid 6 16 ELECTRONICS 53 2440 RISC MICROPROCESSOR NAND FLASH CONTROLLER SPARE AREA ECC REGISTER NFSECCD 0x4E00001C R W NAND flash ECC Error Correction Code 0x00000000 register for spare area data read ECCData1_1 31 24 2nd ECC for 0 15 8 ECCData1_0 23 16 219 ECC for I O 7 0 Note In Software mode Read this register when you need to read 2 4 ECC value from NAND flash memory ECCDataO 1 15 8 st ECC for 15 8 ECCDataO 0 7 0 151 ECC for 7 0 Note In Software mode Read this register when you need to read 151 ECC value from NAND flash memory This register has same read function of NFDATA NOTE Only word access is valid ELECTRONICS 6 17 NAND FLASH CONTROLLER 53 2440 RISC MICROPROCESSOR NFCON STATUS REGISTER NFSTAT 0 4 000020 NAND flash operation status register 0xXX00 _ is IllegalAccess 3 Once Soft Lock or Lock tight is enabled The illegal access program erase to the memory makes this bit set
194. 31 24 Bit 2346 Bit 15 8 Bit 7 0 NFDATA Invalid value Invalid value 181 O 15 8 151 0 7 0 8 bit NAND Flash Memory Interface Word Access mess aaa wies NFDATA ath 7 0 39 0 7 0 279 0 750 180172 NFDATA Bg 151 7 0 2nd 7 0 and 7 0 4th O 7 0 A Half word Access sumas serra NFDATA Invalid value Invalid value 2nd yoy 7 0 18t O 7 0 NFDATA Big Ivaidvaue 15 0 70 219 0 750 A Access Register Bit 15 8 Bit 7 0 gt NFDATA value value Invalid value 151 I O 7 0 STEPPINGSTONE 4 SRAM The NAND Flash controller uses Steppingstone as the buffer on booting and also you can use this area for another purpose 6 6 ELECTRONICS 53 2440 RISC MICROPROCESSOR NAND FLASH CONTROLLER ECC ERROR CORRECTION CODE NAND Flash controller consists of four ECC Error Correction Code modules The two ECC modules one for data 7 0 and the other for data 15 8 can be used for up to 2048 bytes ECC code generation and the others one for data 7 0 and the other for data 15 8 can be used for up to 16 bytes ECC Parity code generation 28 bit ECC Code 22 bit Line 6bit Column Parity 14 bit ECC Code 8 bit Line 6bit Column 2048 BYTE ECC PARITY CODE ASSIGNMENT TABL
195. 40 to 85 C Symbol Parameters Condition High level input voltage Low level voltage LVCMOS interface WW Schmitt trigger positive going threshold CMOS Schmitt negative going threshold CMOS os fy Paa 5 1 B6 means output driver cell 2 Type B8 means 8mA output driver cell 3 12 means 12mA output driver cells ELECTRONICS 27 5 ELECTRICAL DATA S3C2440A RISC MICROPROCESSOR Table 27 4 USB DC Electrical Characteristics Symb Parameter Conaton min Unit Era rr V OH s meme pem Max ov eem RN 0000 9 m EUNT Table 27 5 53 2440 Power Supply Voltage Current m Max Operating Typical normal mode power 3 368 Total Vppi Vio Typical normal mode power 3 310 2 Typical idle mode power 3 FCLK 400MHz Total Vppi Vio F H P 1 3 6 Typical slow mode power 9 FCLK 12MHz Total Vppi Vio F H P 1 1 1 V temperature I other I O static Typical RTC power 3 3 0 Room temperature X tal 32 768kHz for RTC NOTES 1 ID cache ON MMU ON Code on SRAM FCLK HCLK PCLK 400MHz 133MHz 66 7MHz
196. 440 RISC MICROPROCESSOR MMC SD SDIO CONTROLLER ELECTRONICS 19 7 MMC SD SDIO CONTROLLER 53 2440 RISC MICROPROCESSOR SDI Response Register 2 SDIRSP2 SDIRSP2 0x5A00001C 501 Response Register 2 0 Response2 31 0 unused short card status 63 32 long 0x00000000 SDI Response Register 3 SDIRSP3 SDIRSP3 0x5A000020 R SDI response register 3 x0 Response3 31 0 unused short card status 31 0 long 0x00000000 SDI Data Busy Timer Register SDIDTimer SDIDTimer 0x5A000024 SDI data busy timer register 0x0 22 0 Data busy timeout period 0 10000 SDI Block Size Register SDIBSize SDIBSize 0x5A000028 SDI block size register BlkSize 11 0 Block size value 0 4095 byte don t care when stream mode NOTE n Case of multi block BlkSize must be aligned to word 4byte size BlkSize 1 0 00 19 8 ELECTRONICS 53 2440 RISC MICROPROCESSOR MMC SD SDIO CONTROLLER SDI Data Control Register SDIDatCon SDIDatCon 0 5 00002 SDI data control register Burst4 enable Burst4 Data Size DataSize SDIO Interrupt Period Type PrdType Transmit After Response TARSP Receive After Command RACMD Busy After Command BACMD Block mode BlkMode Wide bus enable WideBus DMA Enable EnDMA Data Transfer Start DTST Data Transfer Mode DatMode BlkNum 11 0 NOTE 24 Enable Burst4 mod
197. 5 8 se 64MB MEMORY CONTROLLER S3C2440A RISC MICROPROCESSOR nWAIT PIN OPERATION If WAIT bit WSn bit in BWSCON corresponding to each memory bank is enabled the nOE duration should be prolonged by the external nWAIT pin while the memory bank is active nWAIT is checked from tacc 1 nOE will be de asserted at the next clock after sampling nWAIT is high The nWE signal have the same relation with nOE Figure 5 2 S3C2440A External nWAIT Timing Diagram 4 5 6 ELECTRONICS 53 2440 RISC MICROPROCESSOR MEMORY CONTROLLER nXBREQ nXBACK Pin Operation If nXBREQ is asserted the S3C2440A will respond by lowering nXBACK If nXBACK L the address data bus and memory control signals are in Hi Z state as shown in Table 1 1 After nXBREQ is de asserted the nXBACK will also be de asserted SCLK SCKE A 24 0 D 31 0 nGCS nOE nWE nWBE nXBREQ nXBACK Figure 5 3 53C2440A nXBREQ nXBACK Timing Diagram ELECTRONICS 5 7 MEMORY CONTROLLER S3C2440A RISC MICROPROCESSOR ROM Memory Interface Examples nWBEO A10 nOE A11 nGCSn A12 A13 A14 A15 A16 Figure 5 5 Memory Interface with 8 bit ROM x 2 5 8 ELECTRONICS 53 2440 RISC MICROPROCESSOR MEMORY CONTROLLER Figure 5 7 Memory Interface with 16 bit ROM ELECTRONICS 5 9 MEMORY CONTROLLER S3C2440A RISC MICROPROCESSOR SRAM Memory Interface Examples Figure 5 9 Memory Interface with 16 bit SRAM x 2 5 10 ELECTRONI
198. 5000010 IISFIFO 0x55000010 Li HW R W IIS FIFO register 0x0 0x55000012 Bi HW n aa FENTRY 15 0 Transmit Receive data for IIS NOTES 1 The IISFIFO register is accessible for each halfword and word unit using and LDRH instructions or short int type pointer in Little Big endian mode 2 Li HW Little HalfWord Bi HW Big HalfWord 21 8 ELECTRONICS 53 2440 RISC MICROPROCESSOR SPI SPI OVERVIEW The S3C2440A Serial Peripheral Interface can interface with the serial data transfer The S3C24404A includes two SPI each of which has two 8 bit shift registers for transmission and receiving respectively During an SPI transfer data is simultaneously transmitted shifted out serially and received shifted in serially 8 bit serial data at a frequency is determined by its corresponding control register settings If you only want to transmit receive data can be kept dummy Otherwise if you only want to receive you should transmit dummy 1 data There are 4 I O pin signals associated with SPI transfers SCK SPICLKO 1 MISO SPIMISOO 1 data line MOSI SPIMOSIO 1 data line and active low SS nSS0 1 pin input FEATURES Support 2 ch SPI SPI Protocol ver 2 11 compatible 8 bit Shift Register for transmit 8 Shift Register for receive 8 bit Prescaler logic Polling Interrupt and DMA transfer mode ELECTAONICS 22 1 SPI S3C2440A RISC MICROPROCESSOR BLOC
199. 53 2440 32 BIT CMOS MICROCONTROLLER USER S MANUAL Revision 1 ELECTRONICS Important Notice The information in this publication has been carefully checked and is believed to be entirely accurate at the time of publication Samsung assumes no responsibility however for possible errors or omissions or for any consequences resulting from the use of the information contained herein Samsung reserves the right to make changes in its products or product specifications with the intent to improve function or design at any time and without notice and is not required to update this documentation to reflect such changes This publication does not convey to a purchaser of semiconductor devices described herein any license under the patent rights of Samsung or others Samsung makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Samsung assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation any consequential or incidental damages S3C2440A 32 Bit CMOS Microcontroller User s Manual Revision 1 Publication Number 21 S3 C2440A 072004 2004 Samsung Electronics Typical parameters can and do vary in different applications All operating parameters including Typicals must be validated for each customer application by the customer s technical expert
200. 6 color palette for various selection of color mapping providing flexible operation for users 15 16 ELECTRONICS 53 2440 RISC MICROPROCESSOR LCD CONTROLLER MEMORY DATA FORMAT TFT This section includes some examples of each display mode 24BPP Display BSWP 0 HWSWP 0 BPP24BL 0 BSWP 0 HWSWP 0 BPP24BL 1 Pr Pe 59 6 25 LCD Panel VD Pin Descriptions at 24BPP vp 23 22 21 20 19 18 17 16 15114 13 12 11 11019 817 5 4 3 2 1 0 zje s a s 2 Eae 1 1718 5 4 3 2 1 0 ELECTRONICS 15 17 LCD CONTROLLER S3C2440A RISC MICROPROCESSOR 16BPP Display BSWP 0 HWSWP 0 LCD Panel VD Pin Descriptions at 16BPP 5 6 5 VD 2 22 21 20 19 18 17 16 15 14 1 3 12 11 10 9 7 6 5 4 3 2 1 0 RED 4 3 2 io wc N N GREEN 514 321101 pue NOTE Theunused VD pins can be used as GPIO 15 18 ELECTRONICS 53 2440 RISC MICROPROCESSOR LCD CONTROLLER 8BPP Display BSWP 0 HWSWP 0 LCD Panel ELECTRONICS 15 19 LCD CONTROLLER S3C2440A RISC MICROPROCESSOR 4BPP Display BSWP 0 HWSWP 0 08128 oera D22320 onone omis oma pe
201. 7 29 28 Determines data bus width for bank 7 00 8 5 01 16 bit 10 32 bit 11 reserved ST6 27 Determines SRAM for using UB LB for bank 6 0 Not using UB LB The pins are dedicated nWBE 3 0 1 Using UB LB The pins are dedicated nBE 3 0 WS6 26 Determines WAIT status for bank 6 0 WAIT disable 1 WAIT enable DW6 25 24 data bus width for bank 6 00 8 5 01 16 bit 10 32 bit 11 reserved ST5 23 Determines SRAM for using UB LB for bank 5 0 Not using UB LB The pins are dedicated nWBE 3 0 1 Using UB LB The pins are dedicated nBE 3 0 WS5 22 Determines WAIT status for bank 5 0 WAIT disable 1 WAIT enable DW5 21 20 Determines data bus width for bank 5 00 8 5 01 16 bit 10 32 bit 11 reserved ST4 19 Determines SRAM for using UB LB for bank 4 0 Not using UB LB The pins are dedicated nWBE 3 0 1 Using UB LB The pins are dedicated nBE 3 0 WS4 18 Determines WAIT status for bank 4 0 WAIT disable 1 WAIT enable DW4 17 16 Determine data bus width for bank 4 00 8 bit 01 16 bit 10 32 bit 14 reserved ST3 15 Determines SRAM for using UB LB for bank 3 0 Not using UB LB The pins are dedicated nWBE 3 0 1 Using UB LB The pins are dedicated nBE 3 0 WS3 14 Determines WAIT status for bank 3 0 WAIT disable 1 WAIT enable DW3 13 12 Determines data bus width for bank 3 00 8 bit 01 16 bit 10 32 bit 14 reserved ST2 11 De
202. 7 EPIDMATotlTxcouner TTC M 0x52000213 0 52000210 EPTDMATotaTxcounter ox52000217 06200024 DMA Total Tx coumer 2 0 5200021 0 52000218 R W _ EP2 DMA interface control EP2 UNIT 0 5200021 0 5200021 EP2DMATxUnitcounter EP2 FIFO 0652000223 0520002 EP2 Tx FIFO couer 0652000227 0520002 2 Tx couer EP Tr M 0662000228 0x52000228 EP2 DMA total Tx counter 1 34 ELECTRONICS 53 2440 RISC MICROPROCESSOR PRODUCT OVERVIEW Table 1 4 S3C2440A Special Registers Sheet 10 of 14 Continued Lem e B Endian L Endian Write USB Device Continued CP oxs20002 F _ EPZ DMA Te Te counter Pi CON TEPS DMA interface contol UNT 0620002424 EPS Unt counter FIFO EP3 DMA Tx FIFO counter _ TTC omar EPS DMA Total Tx counter _ M 05200053 oxs2000260 EPSDMA Total Tx counter TTC 0620009257 EP3 DMA Total Tx counter EPA CON osos DMA nteraceconro
203. 827 25 24 23 22 21 20 19 16 15 0 em 002 19 16 Base Register 1201 Bit 0 Store to memory 1 Load from memory 21 Write back Bit 0 No write back 1 Write address into base 22 PSR amp Force User Bit 0 Do not load PSR or user mode 1 Load PSR or force user mode 23 Up Down Bit 0 Down subtract offset from base 1 Up add offset to base 24 Pre Post Indexing Bit 0 Post add offset after transfer 1 Pre add offset bofore transfer 31 28 Condition Field Figure 3 18 Block Data Transfer Instructions 3 40 ELECTRONICS 53 2440 RISC MICROPROCESSOR ARM INSTRUCTION SET ADDRESSING MODES The transfer addresses are determined by the contents of the base register Rn the pre post bit P and the up down bit U The registers are transferred in the order lowest to highest so R15 if in the list will always be transferred last The lowest register also gets transferred to from the lowest memory address By way of illustration consider the transfer of R1 R5 and R7 in the case where 0 1000 and write back of the modified base is required W 1 Figure 3 19 22 show the sequence of register transfers the addresses used and the value of Rn after the instruction has completed In all cases had write back of the modified base not been required W 0 Rn would have retained its initial value of 0x1000 unless it was also in the transfer list of a load multiple regis
204. A 10 8mA 01 6mA DSC CSO 1 0 nGCS0 drive strength 00 10mA 10 8mA 01 6mA ELECTRONICS 9 37 PORTS 53 2440 RISC MICROPROCESSOR MSLCON Memory Sleep Control Register Select memory interface status when in SLEEP mode MSLCON 0x560000cc Memory sleep control register PSC DATA 11 DATA 31 0 pin status in sleep mode 0 Hi Z 1 Output 0 PSC WAIT 10 nWAIT pin status in sleep mode 0 Input 1 Output 0 PSC RnB RnB pin status in sleep mode 0 Input 1 Output 0 PSC NF nSRAS nSCAS pin status in sleep mode PSC SDR 0 Inactive 1 1 Hi Z PSC DQN 3 0 nRWE 3 0 status in sleep mode 0 Inactive 1 Hi Z Flash I F pin status in sleep mode nFCE nFRE nFWE ALE CLE 0 Inactive nFCE nFRE nFWE ALE CLE 11100 1 Hi Z PSC WE nWE pin status in sleep mode 0 Inactive 1 1 Hi Z PSC 50 nGCS 0 pin status in sleep mode 0 Inactive 1 1 Hi Z PSC GCS51 nGCS 5 1 pin status in sleep mode PSC GCS6 nGCS 6 pin status in sleep mode 0 Inactive 1 1 Hi Z PSC GCS7 nGCS 7 pin status in sleep mode 0 Inactive 1 1 Hi Z 0 Inactive 1 1 Hi Z PSC OE nOE pin status in sleep mode 0 Inactive 1 1 Hi Z 7 5 4 3 2 1 0 9 38 ELECTRONICS 53 2440 RISC MICROPROCESSOR PWM TIMER PWM TIMER OVERVIEW The S3C2440A has five 16 bit timers Timer 0 1 2 and 3 have Pulse Width Modulation PWM function Timer 4 has an internal
205. ACK signal When the timer receives the ACK signal it makes the request signal inactive The timer which generates the DMA request is determined by setting DMA mode bits in TCFG1 register If one of timers is configured as DMA request mode that timer does not generate an interrupt request The others can generate interrupt normally DMA mode configuration and DMA interrupt operation m mes o o I o L o o INT4tmp DMAreq en nDMA ACK nDMA REQ Figure 10 8 Timer4 DMA Mode Operation 10 10 ELECTRONICS 53 2440 RISC MICROPROCESSOR PWM TIMER PWM TIMER CONTROL REGISTERS TIMER CONFIGURATION REGISTERO 0 Timer input clock Frequency PCLK prescaler 1 divider value prescaler value 0 255 divider value 2 4 8 16 TCFGO 0 51000000 Configures the two 8 bit prescalers 0x00000000 Bt Description Initial State Reserved 31 24 Dead zone length 23 16 These 8 bits determine the dead zone length The 1 unit time 0x00 of the dead zone length is equal to that of timer 0 Prescaler 1 15 8 These 8 bits determine prescaler value for Timer 2 3 and 4 Prescaler 0 7 0 These 8 bits determine prescaler value for Timer 0 and 1 ELECTRONICS 10 11 PWM TIMER S3C2440A RISC MICROPROCESSOR TIMER CONFIGURATION REGISTER1 TCFG1 0 51000004 5 amp selection register 0x00000000 DMA mode 23 20 Select DMA request channel 0000 No sel
206. AMPLES LDR R3 PC 844 Load into the word found at the address formed by adding 844 to PC bit 1 of PC is forced to zero Note that the THUMB opcode will contain 211 as the Word8 value ELECTRONICS 4 17 THUMB INSTRUCTION SET 53 2440 RISC MICROPROCESSOR FORMAT 7 LOAD STORE WITH REGISTER OFFSET 15 14 13 12 11 10 9 8 6 5 3 2 0 _ mw 2 0 Source Destination Register 5 3 Base Register 8 6 Offset Register 10 Byte Word Flag 0 Transfer word quantity 1 Transfer byte quantity 11 Load Store Flag 0 Store to memory 1 Load from memory Figure 4 8 Format 7 4 18 ELECTRONICS 53 2440 RISC MICROPROCESSOR THUMB INSTRUCTION SET OPERATION These instructions transfer byte or word values between registers and memory Memory addresses are pre indexed using an offset register in the range 0 7 The THUMB assembler syntax is shown in Table 4 8 Table 4 8 Summary of Format 7 Instructions STR Rd Rb Ro STR Rd Rb Ro Pre indexed word store Calculate the target address by adding together the value in Rb and the value in Ro Store the contents of Rd at the address STRB Rd Rb Ro STRB Rd Rb Ro Pre indexed byte store Calculate the target address by adding together the value in Rb and the value in Ro Store the byte value in Rd at the resulting address LDR Rd Rb Ro LDR Rd Rb Ro Pre indexed word load Calculate the source address by adding togethe
207. ART S3C2440A RISC MICROPROCESSOR NOTES 11 22 ELECTRONICS 53 2440 RISC MICROPROCESSOR USB HOST USB HOST CONTROLLER OVERVIEW S3C2440A supports 2 port USB host interface as follows Rev 1 0 compatible USB Rev1 1 compatible Two down stream ports Support for both LowSpeed and FullSpeed USB devices RCF0_RegData 32 FP DATA 32 CONTROL USB CONTROL STATE DATA 32 EUM ED TD DATA 32 PROCESSOR BLOCK APP MDATA 32 REGS 8 HCF DATA FIFO DATA EXT FIFO STATUS Figure 12 1 USB Host Controller Block Diagram 12 1 ELECTRONICS USB HOST S3C2440A RISC MICROPROCESSOR USB HOST CONTROLLER SPECIAL REGISTERS The S3C2440A USB host controller complies with OHCI Rev 1 0 Refer to Open Host Controller Interface Rev 1 0 specification for detailed information OHCI REGISTERS FOR USB HOST CONTROLLER Wecommonsaus 2 2 E eerwDeae pe a 2 9 E WemuHesdED Em WemukCuremto E Eu ma a
208. Analog output pad 50kQ resistor separated bulk bias t12s phtot1 2 12 2440 output pad LVCMOS tri state output drive strenth control lo 6 8 10 12mA ET ELECTRONICS 1 19 PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR SIGNAL DESCRIPTIONS Table 1 3 S3C2440A Signal Descriptions Sheet 1 of 6 Signal Input Output Bus Controller 1 0 1 0 sets S3C2440A in the TEST mode which is used only at fabrication Also it determines the bus width of nGCS0 The pull up down resistor determines the logic level during RESET cycle 00 Nand boot 01 16 bit 10 32 bit 11 Test mode ADDR 26 0 Address Bus outputs the memory address of the corresponding bank DATA 91 0 DATA 31 0 Data Bus inputs data during memory read and outputs data during memory write The bus width is programmable among 8 16 32 bit nGCS 7 0 nGCS 7 0 General Chip Select are activated when the address of a memory is within the address region of each bank The number of access cycles and the bank size can be programmed o nWE Write Enable indicates that the current bus cycle is write cycle O nOE Output Enable indicates that the current bus cycle is a read cycle 12010 nXBREQ Bus Hold Request allows another bus master to request control of the local bus BACK active indicates that bus control has been granted nXBACK Bus Hold Acknowledge indicates that the S3C2440A has surrendere
209. C Li W Li HW Li B Bi W 0x5A000041 Bi HW 0x5A000043 Bi B SDIDAT Bit Description Initial State Data Register 31 0 This field contains the data to be transmitted or received over the 0x00000000 SDI channel NOTE Li HW Li B Access Word HalfWord Byte unit when endian mode is Little Bi W Access by Word unit when endian mode is Big Bi HW Access by HalfWord unit when endian mode is Big Bi B Access by Byte unit when endian mode is Big 19 14 ELECTRONICS 53 2440 RISC MICROPROCESSOR IIC BUS INTERFACE IIC BUS INTERFACE OVERVIEW The S3C2440A RISC microprocessor can support a multi master serial interface A dedicated serial data line SDA and a serial clock line SCL carry information between bus masters and peripheral devices which are connected to the The SDA and SCL lines are bi directional In multi master 5 mode multiple 53 2440 RISC microprocessors can receive or transmit serial data to or from slave devices The master 53 2440 can initiate and terminate a data transfer over the The IIC bus in the S3C2440A uses Standard bus arbitration procedure To control multi master operations values must be written to the following registers Multi master IIC bus control register Multi master control status register 5 Multi master Tx Rx data shift register I
210. C register and ECC status register have valid value wesmn mv 8 tal State SEroatano area which number deia soror o in spere whieh btis enor o Menoio main area cates whieh btis enor oo SpareError 9 2 Indicates whether spare area bit fail error occurred 00 No Error 01 1 bit error correctable 10 Multiple error 11 ECC area error MainError 1 0 Indicates whether main data area bit fail error occurred 00 No Error 01 1 bit error correctable 10 Multiple error 11 ECC area error NOTE The above values are only valid when both ECC register and status register have valid value ELECTRONICS 6 19 CONTROLLER 53 2440 RISC MICROPROCESSOR MAIN DATA AREA ECCO STATUS REGISTER NFMECCO 0 4 0002 NAND flash ECC register for data 7 0 1 0 4 00000 NAND flash ECC register for data 15 8 ___ m _______ mita Sta ___ tal Stato NOTE The flash controller generate 1 when read or write main area data while the MainECCLock NFCONT 5 bit is O Unlock SPARE AREA ECC STATUS REGISTER NFSECC 0 4 000034 NAND flash ECC register for VO 15 0 SECCA 1 31 24 Spare area ECC1 status for l O 15 8 0 23 16 Spare area ECCO status for l O 15 8 SECCO 1 15
211. C3600 Enable MODE SEL 2 Select DE Sync mode 0 Sync mode 1 DE mode RES SEL 1 Select output resolution type 0 320 x 240 1 2 240 x 320 Determine LPC3600 Enable Disable 0 LPC3600 Disable 1 2 LPC3600 Enable NOTE Both EN and EN enable is not permitted Only one TCON be enabled at the same time 15 40 ELECTRONICS 53 2440 RISC MICROPROCESSOR LCD CONTROLLER Register Setting Guide STN The LCD controller supports multiple screen sizes by special register setting The CLKVAL value determines the frequency of VCLK This value has to be determined such that the VCLK value is greater than data transmission rate The data transmission rate for the VD port of the LCD controller is used to determine the value of CLKVAL register The data transmission rate is given by the following equation Data transmission rate HS x VS x FR x MV HS Horizontal LCD size VS Vertical LCD size FR Frame rate Mode dependent value Table 15 6 MV Value for Each Display Mode ode Mw The LCDBASEU register value is the first address value of the frame buffer The lowest 4 bits must be eliminated for burst 4 word access The LCDBASEL register value depends on LCD size and LCDBASEU The LCDBASEL value is given by the following equation LCDBASEL LCDBASEU LCDBASEL offset ELECTRONICS 15 41 LCD CONTROLLER S3C2440A RISC MICROPROCESSOR Example 1 160 x 160 4 level gray 80 f
212. CLK 15 5 serial clock AC 97 eWwhedrmesamiesm 2 io mesMMzswaldsaobk 0 ooo SATA IN __ _________ Seta ime division multiplexed ACO7 input steam AC SATA OUT O Seral ime division multiplexed output sream meo O o Minus on off contol signal y O on contol MON __ Minus omot contol 5 0 DATAC rom USB host Need to mto DATA om USB host Need PDNO for USB peripheral Need to 470kQ pull down for power consumption in sleep mode PDPO lO DATA for USB peripheral Need to 1 5kQ pull up CODEC system clock 1 22 ELECTRONICS 53 2440 RISC MICROPROCESSOR PRODUCT OVERVIEW Table 1 3 S3C2440A Signal Descriptions Sheet 4 of 6 Continued SPIMISO 1 0 SPIMISO is the master data input line when SPI is configured as a master When SPI is configured as a slave these pins reverse its role SPIMOSI 1 0 SPIMOSI is the master data output line when SPI is configured as a master When SPI is configured as a slave these pins reverse its role SPICLK 1 0 O SPI clock nSS 1 0 SPI chip select only for slave mode SDDAT 3 0 SD receive transmit data SDCMD 6 SD receive response transmit command SDCLK clock General Port GPn 1 29 0 W Ge
213. CO L R W End pointO FIFO register OxXX 0x520001C3 B byte EP1 FIFO 0x520001C4 L R W End point1 FIFO register OxXX 0x520001C7 B byte 2 EP2 FIFO 0 520001 8 1 R W End point2 FIFO register 0x520001CB B byte FIFO 0x520001CC L R W End point3 FIFO register OxXX 0x520001CF B byte EPA FIFO 0x520001D0 R W End point4 FIFO register OxXX 0x520001D3 byte m wr FIFO DATA 7 0 FIFO data value ELECTRONICS 13 17 USB S3C2440A RISC MICROPROCESSOR INTERFACE CONTROL REGISTER EPN DMA CON EP1 DMA CON 0x52000200 L R W EP1 DMA interface control register 0x00 0x52000203 B byte EP2 0x52000218 L R W EP2 DMA interface control register 0x00 0x5200021 B B byte 0x52000240 L R W EP3 DMA interface control register 0x00 0x52000243 B byte EP4 DMA CON 0x52000258 L R W EP4 DMA interface control register 0x00 0x5200025B B byte RUN OB 7 R W Read observation 0 1 DMA is running Write Ignore n register 0 DMA requests will be stopped if EPn TTC n reaches 0 1 DMA requests will be continued although n reaches 0 STATE 64 w DMA tate monitoring DEMAND MODE 3 R W DMA demand mode enable bit 0 Demand mode disable 1 Demand mode enable OUT RUN OB 2 R W R W Functionally separated into write and read OUT DMA RUN op
214. COLOR REFLECTIVE A SI TRANSFLECTIVE A SI TFT LCD The 3 2440 supports following SEC TFT LCD panels 1 SAMSUNG 3 5 Portrait 256K Color Reflective a Si TFT LCD LTS350Q1 PD1 TFT LCD panel with touch panel and front light unit LTS350Q1 PD2 TFT LCD panel only 2 SAMSUNG 3 5 Portrait 256K Color Transflective a Si TFT LCD LTS350Q1 PE1 TFT LCD panel with touch panel and front light unit LTS350Q1 PE2 TFT LCD panel only The S3C2440A provides timing signals as follows to use LTS350Q1 PD1 PD2 and LTS350Q1 PE1 LTS350Q1 PD1 PD2 LTS350Q1 PE1 PE2 STH Horizontal Start Pulse STH Horizontal Start Pulse TP Source Driver Data Load Pulse TP Source Driver Data Load Pulse INV Digital Data Inversion INV Digital Data Inversion LCD_HCLK Horizontal Sampling Clock LCD_HCLK Horizontal Sampling Clock CPV Vertical Shift Clock CPV Vertical Shift Clock STV Vertical Start Pulse STV Vertical Start Pulse OE Gate On Enable LCCINV Source drive IC sampling inversion signal REV Inversion Signal REV VCOM modulation Signal REVB Inversion Signal REVB Inversion Signal So LTS350Q1 PD1 2 and 1 2 can be connected with the 53 2440 without using the additional timing control logic But the user should additionally apply Vcom generator circuit various voltages INV signal and Gray scale voltage generator circuit which is recommended by PRODUCT INFORMATION SPEC of LTS350Q1 PD1 2 and PE1 2 Detailed timing diagram is als
215. CS 27 14 53 2440 RISC MICROPROCESSOR ELECTRICAL DATA Figure 27 12 ROWSRAM READ Timing Diagram I Tacs 2 Tcos 2 Tacc 4 Toch 2 Tcah 2 PMC 0 ST 0 ELECTRONICS 27 15 ELECTRICAL DATA S3C2440A RISC MICROPROCESSOR I gt I lt tnDH Figure 27 13 ROWSRAM READ Timing Diagram II Tacs 2 Tcos 2 Tacc 4 Toch 2 Tcah 2cycle PMC 0 ST 1 27 16 ELECTRONICS ELECTRICAL DATA S3C2440A RISC MICROPROCESSOR 2 Tcah 2 PMC 0 ST 0 Figure 27 14 ROM SRAM WRITE Timing Diagram 1 2 4 5 2 5 27 17 ELECTRONICS 53 2440 RISC MICROPROCESSOR ELECTRICAL DATA RAD 2 Tcah 2 PMC 0 ST 1 Figure 27 15 ROWSRAM WRITE Timing Diagram II Tacs 2 Tcos 2 Tacc 4 Toch ELECTRONICS 27 18 ELECTRICAL DATA S3C2440A RISC MICROPROCESSOR gt q E 5 oz lt u o 8 a x NE F 8 2cycle o 0 Tcah 0 PMC 0 ST 0 0 Tacc 4 Toch 0 Tcos Figure 27 17 External nWAIT WRITE Timing Diagram Tacs 27 19 ELECTRONICS ELECTRICAL DATA S3C2440A RISC MICROPROCESSOR Figure 27 18 Masked ROM Single READ Timing Diagram Tacs 2 Tcos 2 Tacc 8 PMC 01 10 11 I I tRAD gt 4 tRAD j tRAD RAD j q tR D ADDR 1 O 01 141 01
216. CS 53 2440 RISC MICROPROCESSOR MEMORY CONTROLLER SDRAM Memory Interface Examples DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 0011 0012 0013 0014 0015 5 5 nSRAS nSCAS nWE D0 2 03 D4 DS 06 07 08 09 Figure 5 11 Memory Interface with 16 bit SDRAM 4Mx16x4Bank 2ea NOTE Refer to Table 5 2 for the Bank Address configurations of SDRAM ELECTRONICS 5 11 53 2440 RISC MICROPROCESSOR MEMORY CONTROLLER PROGRAMMABLE ACCESS CYCLE 2 cycles Tcoh 1 cycle Tacp gt gt ru gg 2 cycles Tcah 3 cycles Tacc Figure 5 12 53 2440 nGCS Timing Diagram ELECTRONICS 5 12 MEMORY CONTROLLER S3C2440A RISC MICROPROCESSOR BA 2 CL 3 BL 1 Read CL Bank Precharge 2 cycle 2 cycle Tcas Tcp 26 gt gt O 9 CN Trp Trcd Figure 5 13 53 2440 SDRAM Timing Diagram 5 13 ELECTRONICS MEMORY CONTROLLER S3C2440A RISC MICROPROCESSOR BUS WIDTH amp WAIT CONTROL REGISTER BWSCON BWSCON 0x48000000 Bus width amp wait status control register 0x000000 BWSCON 77 Initialstate ST7 31 Determines SRAM for using UB LB for bank 7 0 Not using UB LB The pins are dedicated nWBE 3 0 1 Using UB LB The pins are dedicated 3 0 WS7 80 Determines WAIT status for bank 7 0 WAIT disable 1 WAIT enable DW
217. CTRONICS 27 26 ELECTRICAL DATA S3C2440A RISC MICROPROCESSOR dV OLV vg uaav Trcdz2 2 Figure 27 26 SDRAM Page Hit Miss READ Timing Diagram Trpz2 27 27 ELECTRONICS 53 2440 RISC MICROPROCESSOR ELECTRICAL DATA ADDR BA i a 2 9 D 5 o x c 5 o T c o 71 v 5 c E 5 x o 2 2 o m NOTE Figure 27 27 SDRAM Self Refresh Timing Diagram Trp 2 Trc 4 ELECTRONICS 27 28 ELECTRICAL DATA S3C2440A RISC MICROPROCESSOR lt m c lt 2 Figure 27 28 SDRAM Single Write Timing Diagram Trpz2 Trcd 27 29 ELECTRONICS 53 2440 RISC MICROPROCESSOR ELECTRICAL DATA E 01 vg dHaav z2 2 2 Trcd Figure 27 29 SDRAM Page Hit Miss Write Timing Diagram Trp ELECTRONICS 27 30 53 2440 RISC MICROPROCESSOR ELECTRICAL DATA I tCADH I XnXDACK Tl2csetup Tvclkh Tvclk 4 lt gt 4 x Tvdsetu Tve2hold PE p gt gt OOO INI Tle2chold lt Tlewidth lt Figure 27 31 TFT LCD Controller Timing Diagram ELECTRONICS 27 31 ELECTRICAL DATA S3C2440A RISC MICROPROCESSOR IISSCLK IISLRCK out IISLRCK out IISSDI
218. CmdSta SDICmdSta 0x5A000010 R C SDI command status register Response CRC 12 CRC check failed when command response received This is Fail RspCrc R C cleared by setting to one this bit 0 Not detect 1 fail Command Sent 11 Command sent not concerned with response This flag is CmaSent R C cleared by setting to one this bit 0 Not detect 1 Command end Command Time Out 10 Command response timeout 64CLK This flag is cleared by CmdTout R C setting to one this bit 0 Not detect 1 Timeout Response Receive 9 Command response received This flag is cleared by setting to End RspFin R C one this bit 0 Not detect 1 Response end CMD line progress Command transfer in progress On 0 Not detect 1 In progress Rsplndex 7 0 Response index 6 bit with start 2 bit 8 bit SDI Response Register 0 SDIRSPO SDIRSPO 0 5 000014 501 response register 0 SDIRSPO ResponseO Description 31 0 status 31 0 short card status 127 96 long SDI Response Register 1 SDIRSP1 SDIRSP1 0x5A000018 R SDI response register 1 Bt scription RCRC7 31 24 CRC7 with end bit short card status 95 88 long Response 23 0 unused short card status 87 64 long Reset Value 0x0 Initial Value Reset Value 0x0 Initial Value 0x00000000 Reset Value 0x0 Initial Value 0x00 0x000000 d ELECTRONICS 53 2
219. D counters 1 Reserved Separate BCD counters CLKSEL 1 BCD clock select 0 XTAL 1 215 divided clock 1 Reserved XTAL clock only for test RTCEN RTC control enable 0 Disable 1 Enable Note Only BCD time count and read operation can be performed NOTES 1 AII RTC registers have to be accessed for each byte unit using STRB and LDRB instructions or char type pointer 2 0 Little endian B Big endian TICK TIME COUNT TICNT REGISTER TICNT 0x57000044 L R W Tick time count register 0x0 0x57000047 B by byte TICK INT Enable 7 Tick time interrupt enable 0 Disable 1 Enable TICK Time Count Tick time count value 1 127 000000 This counter value decreases internally and users cannot read this counter value in working 17 4 ELECTRONICS 53 2440 RISC MICROPROCESSOR REAL TIME CLOCK RTC ALARM CONTROL RTCALM REGISTER The RTCALM register determines the alarm enable and the alarm time Please note that the RTCALM register generates the alarm signal through both INT RTC and PMWKUP in power down mode but only through INT_RTC in the normal operation mode RTCALM 0x57000050 L R W RTC alarm control register 0x0 0x57000053 B by byte 1 1 ALMEN Alarm global enable 0 Disable 1 Enable YEAREN 5 Year alarm enable 0 Disable 1 Enable MONREN 4 Month alarm enable 0 Disable 1 Enable DATEEN 3 Date alarm enable 0 Disable 1 Enable HOUREN 2 Hour alarm e
220. DC registers RTC registers and UART registers must be read write in word unit 32 bit in little big endian 4 Make sure that the ADC registers RTC registers and UART registers be read write by the specified access unit and the specified address Moreover one must carefully consider which endian mode is used 5 W 32 bit register which must be accessed by LDR STR or int type pointer int HW 16 bit register which must be accessed by LDRH STRH or short int type pointer short int B 8 bit register which must be accessed by LDRB STRB or char type pointer char int ELECTRONICS 1 39 53 2440 RISC MICROPROCESSOR PROGRAMMER S MODEL PROGRAMMER S MODEL OVERVIEW S3C2440A is developed using the advanced 9201 core which has been designed by Advanced RISC Machines Ltd PROCESSOR OPERATING STATES From the programmer s point of view the ARM920T can be in one of the two states ARM state which executes 32 bit word aligned ARM instructions e THUMB state is a state which can execute 16 bit halfword aligned THUMB instructions In this state the PC uses bit 1 to select between alternate halfwords NOTE Transition between these two states does not affect the processor mode or the contents of the registers SWITCHING STATE Entering THUMB State Entry into THUMB state can be achieved by executing a BX instruction with the state bit bit O set in the operand register Transition to THUMB state will also occu
221. Displays Feature Supports 1 2 4 or 8 bpp bit per pixel palette color displays for color TFT e Supports 16 24 bpp non palette true color displays for color TFT e Supports maximum 16M color at 24 bpp mode LPC3600 Timing controller embedded for LTS350Q1 PD1 2 SAMSUNG 3 5 Portrait 256K color Reflective a Si TFT LCD e 600 Timing controller embedded for LTS350Q1 PE1 2 SAMSUNG 3 5 Portrait 256K color Transflective a Si TFT LCD e Supports multiple screen size Typical actual screen size 640x480 320x240 160x160 and others Maximum frame buffer size is 4Mbytes Maximum virtual screen size in 64K color mode 2048x1024 and others UART e 3 channel UART with DMA based or interrupt based operation e Supports 5 bit 6 bit 7 bit or 8 bit serial data transmit receive Tx Rx e Supports external clocks for the UART operation UEXTCLK e Programmable baud rate e Supports IrDA 1 0 Loopback mode for testing Each channel has internal 64 byte Tx FIFO and 64 byte Rx FIFO 1 3 PRODUCT OVERVIEW FEATURES Continued A D Converter amp Touch Screen Interface e 8 ch multiplexed ADC Max 500KSPS and 10 bit Resolution Internal FET for direct Touch screen interface Watchdog Timer 16 bit Watchdog Timer e Interrupt request or system reset at time out IIC Bus Interface e 1 ch Multi Master IIC Bus e Serial 8 bit oriented and bi directional data tr
222. E sam onm omas DATA4 DATAY DATAO Pea me me me Pe Pe mecs 16 BYTE ECC PARITY CODE ASSIGNMENT TABLE wmm peras DATA2 DATAS cono me me re re m Pe Pe Pz sees m e rw me rae ELECTRONICS 6 7 NAND FLASH CONTROLLER 53 2440 RISC MICROPROCESSOR ECC MODULE FEATURES ECC generation is controlled by the ECC Lock MainECCLock SpareECCLock bit of the Control register ECC Register Configuration Little Big Endian 1 1 16 bit NAND Flash Memory Interface 2112 NFMECCDO 219 ECC for 15 8 279 ECC for VO 7 0 18 ECC for 15 8 19 ECC for 7 0 NFMECCD1 4th ECC for O 15 8 4 ECC for VO 7 0 379 ECC for 15 8 3 d ECC for 7 0 70 NFSECCD 219 for 5 8 279 ECC for 0 7 0 151 ECC for 15 8 18 ECC for 7 0 1 8 bit Flash Memory Interface C mess T NFMECCDO 29 19 ECC for VO 7 0 Weser 2107 ECC PROGRAMMING GUIDE In software mode ECC module generates ECC parity code for all read write data So you have to reset ECC value by writing the Init CC NFCONT 4 bit
223. ENT Power Control of VDDi and VDDiarm In SLEEP mode VDDi VDDiarm VDDMPLL and VDDUPLL will be turned off which is controlled by PWREN pin If PWREN signal is activated H VDDi and VDDiarm are supplied by an external voltage regulator If PWREN pin is inactive L the VDDi and VDDiarm are turned off NOTE Although VDDi VDDiarm VDDMPLL and VDDUPLL may be turned off the other power pins have to be supplied Regulator 1 2V 1 3V Power 1 2VA 3V S3C2440A Memory 3 3V lt v lt RTC Alarm Power CTRL d VDDi Alive Block VDDiarm VDDMPLL VDDUPLL External Interrupt Core amp Peripherals 3 3V Power Figure 7 12 SLEEP Mode NOTE During sleep mode if you don t use Touch Screen panel Touch ports XP XM YP and YM must be floating That is Touch ports XP XM YP and YM shouldn t be connected to GND sources Because XP YP will be maintained H during sleep mode ELECTRONICS 7 17 CLOCK amp MANAGEMENT S3C2440A RISC MICROPROCESSOR Signaling EINT 15 0 for Wakeup The S3C2440A can be woken up from SLEEP mode only if the following conditions are met a Level signals H or L or edge signals rising falling or both are asserted on EINTn input pin b The EINTn pin has to be configured as EINT in the GPIO control register c nBATT FLT pin has to be H level It is important to configure the EINTn in the GPIO control register as an external interrupt pins considering the c
224. EP4 Interrupt 4 1 R SET For BULK INTERRUPT IN endpoints CLEAR Set by the USB under the following conditions 1 IN PKT RDY bit is cleared 2 FIFO is flushed 3 SENT STALL set For BULK INTERRUPT OUT endpoints Set by the USB under the following conditions 1 Sets OUT RDY bit 2 Sets SENT STALL bit EPO Interrupt R SET Correspond to endpoint 0 interrupt CLEAR Set by the USB under the following conditions 1 OUT PKT RDY bit is set 2 IN PKT RDY bit is cleared 3 SENT bit is set 4 SETUP END bit is set 5 DATA END bit is cleared it indicates the end of control transfer ELECTRONICS 13 7 USB S3C2440A RISC MICROPROCESSOR INTERRUPT REGISTER EP INT REG USB INT REG Continued USB INT REG 0x52000158 L R W USB interrupt pending clear register 0x00 0x5200015B B byte RESET 2 R SET Set by the USB when it receives reset Interrupt CLEAR signaling RESUME 1 R SET Set by the USB when it receives resume Interrupt CLEAR signaling while_in Suspend mode If the resume occurs due to a USB reset then the MCU is first interrupted with a RESUME interrupt Once the clocks resume and the SEO condition persists for 3ms USB RESET interrupt will be asserted SUSPEND R SET Set by the USB when it receives suspend Interrupt CLEAR signalizing This bit is set whenever there is no activity for 3ms on the bus Thus if the MCU does not stop the clock after the first suspend interrupt i
225. Exit from Slow mode Command and the Instant PLL on Command n nennen 7 14 7 12 SEEEP Mode 5255 5223 7 17 8 1 Basic DMA Timing mene uha ua kS nnne 8 3 8 2 Demand Handshake Mode Comparison 8 4 8 3 Burta Trancio 26 ta e eite tetra n 8 5 8 4 Single service in Demand Mode with Unit Transfer 5 2 8 6 8 5 Single service in Handshake Mode with Unit Transfer Size 8 6 8 6 Whole service in Handshake Mode with Unit Transfer 5126 8 6 10 1 16 bit PWM Timer Block 10 2 10 2 Timer ODperatioris esti t Reve nr e PEE UR ehe Rude E Hte eb 10 3 10 3 Example of Double Buffering Function 10 4 10 4 Example ota Timer ODeratiori ii eret t iet dee eee tu ius 10 6 10 5 Example E oed ree ete eder talent cedem eoe dete tore 10 7 10 6 Inu eoe eeu 10 8 10 7 The Wave Form When a Dead Zone Feature is 10 9 10 8 Timer4 Mode
226. FFFF The masked interrupt source will not be serviced 0 Interrupt service is available 1 Interrupt service is masked tal State Br o 0 Service available 1 Masked 0 Service available 1 Masked 0 Service available 1 Masked INT CAM C 11 0 Service available 1 Masked INT ADC S 10 0 Service available 1 Masked 0 Service available INTER 8 0 Service available 0 Service available INTRO e 0 Service available 0 Service available 0 Service available 0 Service available 0 Service available 0 Service available INTRCO 0 Service available 14 18 1 Masked 1 Masked 1 Masked 1 Masked 1 Masked 1 Masked 1 Masked 1 Masked 1 Masked 1 Masked ELECTRONICS 53 2440 RISC MICROPROCESSOR LCD CONTROLLER LCD CONTROLLER OVERVIEW The LCD controller in the S3C2440A consists of the logic for transferring LCD image data from a video buffer located in system memory to an external LCD driver The LCD controller supports monochrome 2 bit per pixel 4 level gray scale or 4 bit per pixel 16 level gray scale mode on a monochrome LCD using a time based dithering algorithm and Frame Rate Control FRC method and it can be interfaced with a color LCD panel at 8 bit per pixel 256 level color and 12 bit per pixel 4096 level color for interfacing with STN LCD It can support 1 b
227. FIFO 0x52000220 0x52000223 BE EP1 DMA transfer FIFO counter base register byte EP2 DMA transfer FIFO counter base register byte EP3 DMA transfer FIFO counter base register byte EP4 DMA transfer FIFO counter base register byte FIFO 7 0 Rw R EP DMA transfer FIFO counter value Li EP3 DMA FIFO 0x52000248 0x5200024B 4 DMA FIFO 0x52000260 0x52000263 s 13 20 ELECTRONICS 53 2440 RISC MICROPROCESSOR USB DEVICE DMA TOTAL TRANSFER COUNTER REGISTER L M H This register should have total number of bytes to be transferred using DMA total 20 bit counter EP1 DMA TTC L 0x5200020C R W total transfer counter lower byte 0x00 0x5200020F byte EP1 DMA TTC M 0x52000210 R W DMA total transfer counter middle byte 0x00 0x52000213 byte EP1 DMA TTC H 0x52000214 R W 1 total transfer counter higher byte 0x00 0x52000217 byte EP2 DMA TTC L 0x52000224 R W EP2 total transfer counter lower byte 0x00 0x52000227 byte EP2 DMA TTC M 0x52000228 R W 2 total transfer counter middle byte 0x00 0x5200022B byte EP2 DMA TTC H 0x5200022C R W 2 total transfer counter higher byte 0x00 0x5200022F byte DMA TTC L 0x5200024C R W total transfer counter lower byte 0x00 0x5200024F byte EPS DMA TTC M 0x52000250 R W
228. GPGCON GPGDAT 0 56000064 O GPGUP 0 56000068 GPHCON 0 56000070 1 O 0 56000074 GPHUP Ox5600078 GPJCON 0 56000000 Port control GPJDAT 0556000004 7 O aue _ MISCCR 0 56000080 Miscellaneous control DCLKCON 0 56000084 bekon control EXTINTO 0556000088 71 External interrupt control registero EXTINT 0 5600008 Extmalintrruptcontolregister ExmNT2 0 56000090 Exemalintrrptcontolregster2 1 36 ELECTRONICS 53 2440 RISC MICROPROCESSOR PRODUCT OVERVIEW Table 1 4 S3C2440A Special Registers Sheet 12 of 14 Continued mmr sz 09 0 Name B Endian L Endian Write i o port continued Nm oxs6000008 esa ENTFLT2 ox5600009c External interrupt filter control register 2 ENTFLTS 0 560000 0 External interrupt filter control register3 EINTMASK 0 56000044 Extermal interruptmask EINTPEND 0 560000 8 External interrupt pending GSTATUSO 055600004 7 R status GSTATUS 0 56000080 Chip 1D 2 0 56000084 Reset status GSTATUS4 0 56000080 Informregister MSLCON __ 5 Memory sleep control register
229. H 9 input output port Port J GPJ 13 input output port 16 input output port 16 input output port GPF 8 input output port Each port can be easily configured by software to meet various system configurations and design requirements You have to define which function of each pin is used before starting the main program If a pin is not used for multiplexed functions the can be configured as ports Initial pin states are configured seamlessly to avoid problems ELECTRONICS 9 1 PORTS GPA22 21 20 GPA19 GPA18 GPA17 GPA16 GPA15 GPA14 GPA13 GPA12 11 GPA10 GPA8 GPA7 GPA6 GPA5 GPA4 GPA3 GPA2 GPA1 GPA0 S3C2440A RISC MICROPROCESSOR Table 9 1 S3C2440A Port Configuration Sheet 1 of 5 Selectable Pin Functions 72222111 1 owamy owamy ww owamy ww owamy SCS owamy xm owamy SC owumy owamy wow owamy mos owamy Mom owamy wow Moms owumy Mom S owamy om wow owamy wow owamy wow SCC owamy wow SO ELECTRONICS 53 2440 RISC MICROPROCESSOR
230. I data pins are used for transmitting and receiving serial data When SPI is configured as a master SPIMISO MISO is the master data input line SPIMOSI MOSI is the master data output line and SPICLK SCK is the clock output line When SPI becomes a slave these pins perform reverse roles In a multiple master system SPICLK SCK pins SPIMOSI MOSI pins and SPIMISO MISO pins are tied to configure a group respectively A master SPI can experience a multi master error when other SPI device working as a master selects the S3C2440A SPI as a slave When this error is detected the following actions are taken immediately But you must previously set SPPINn s ENMUL bit if you want to detect this error 1 The SPCONn s MSTR bit is forced to 0 to operate in slave mode 2 The SPSTAn s MULF flag is set and an SPI interrupt is generated 22 8 FLECTRONICS 53 2440 RISC MICROPROCESSOR SPI SPI BAUD RATE PRESCALER REGISTER SPPREO 0x5900000C SPI cannel 0 baud rate prescaler register SPPRE1 0x5900002C SPI cannel 1 baud rate prescaler register Prescaler Value 7 0 Determine SPI clock rate 0x00 Baud rate PCLK 2 Prescaler value 1 NOTE Baud rate should be less than 25 MHz SPI TX DATA REGISTER SPTDATO 0x59000010 SPI channel 0 Tx data register SPTDAT1 0x59000030 SPI channel 1 Tx data register Tx Data Register 7 0 This field contains the data to be transmitted over the SPI channel SPI RX DATA REGISTER
231. ICDS Multi master IIC bus address register IICADD When the is free the SDA and SCL lines should be both at High level High to Low transition of SDA can initiate a Start condition A Low to High transition of SDA can initiate a Stop condition while SCL remains steady at High Level The Start and Stop conditions can always be generated by the master devices A 7 bit address value in the first data byte which is put onto the bus after the Start condition has been initiated can determine the slave device which the bus master device has selected The 8th bit determines the direction of the transfer read or write Every data byte put onto the SDA line should be eight bits in total The bytes can be unlimitedly sent or received during the bus transfer operation Data is always sent from most significant bit MSB first and every byte should be immediately followed by acknowledge ACK bit ELECTRONICS 20 1 IIC BUS INTERFACE 53 2440 RISC MICROPROCESSOR Address Register IICCON IICSTAT 4 bit Prescaler Shift Register 4 SDA IIC Bus Control Logic Shift Register IICDS t Data Bus Figure 20 1 IIC Bus Block Diagram 20 2 ELECTRONICS 53 2440 RISC MICROPROCESSOR IIC BUS INTERFACE IIC BUS INTERFACE The S3C2440A IIC bus interface has four operation modes Master transmitter mode Master receive mode Slave transmitter mode Slave receive mode Functi
232. K DIAGRAM LSB M SPIMISO 0 Tx 8bit Shift Reg 0 Slave MISO Master SB MSB LSB SPIMOSI 0 Master E Rx 8bit Shift Reg 0 i Slave MOSI 8bit Prescaler 0 CLOCK Logico CPOL Prescaler Register 0 CPHA Status Register 0 0 INT DMA 0 Pin Control Logic 0 INT 0 INT 1 REQO gt Slave Master LSB MSB SPIMISO 1 8 Tx 8bit Shift Reg 1 MISO MSB LSB Master SPIMOSI 1 8bit Prescaler 1 or CLOCK Logic 1 CPOL Prescaler Register 1 CPHA Status Register 1 iu I F 1 INT 1 Pin Control Logic 1 INT 0 INT 1 REQO REQ1 Figure 22 1 Block Diagram 22 2 FLECTRONICS 53 2440 RISC MICROPROCESSOR SPI SPI OPERATION Using the SPI interface S3C2440A can send receive 8 bit data simultaneously with an external device A serial clock line is synchronized with the two data lines for shifting and sampling of the information When the SPI is the master transmission frequency can be controlled by setting the appropriate bit in SPPREn register You can modify its frequency to adjust the baud rate data register value When the is a slave other master supplies the clock When the programmer writes byte data to SPTDATn register SPI transmit receive operation will start simultaneously In some cases nSS should be activated before writing byte data to SPTDATn PROGRAMMING PROCEDURE When byte data is wr
233. KOUTO 11 Reserved GPH8 17 16 Input 01 Output UEXTCLK 11 Reserved GPH7 15 14 Input 01 Output RXD 2 11 nCTS1 GPH6 13 12 Input 01 Output TXD 2 11 nRTS1 GPH5 11 10 Input 01 Output m RXD 1 11 Reserved GPH4 Input 01 Output TXD 1 11 Reserved GPH3 7 6 Input 01 Output RXD 0 11 reserved GPH2 5 4 Input 01 Output 5 TXD 0 11 Reserved GPH1 3 2 Input 01 Output 102 nRTS0 11 Reserved 1 0 Input 01 Output m nCTS0 11 Reserved GPH 10 0 10 0 When the port is configured as an input port the corresponding bit is the pin state When the port is configured as an output port the pin state is the same as the corresponding bit When the port is configured as functional pin the undefined value will be read GPHUP 0 GPH 10 0 10 0 0 The pull up function attached to the corresponding port pin is enabled 1 The pull up function is disabled ELECTRONICS 9 21 PORTS 53 2440 RISC MICROPROCESSOR PORT J CONTROL REGISTERS GPJCON GPJDAT fl GPJ12 25 24 GPJ11 23 22 0 CAMCLKOUT GPJ10 21 20 GPJ9 19 18 Do GPJ8 17 16 7 15 14 15 GPJ6 13 12 GPJ5 11 10 10 GPu4 ne GPu3 7 6 GPJ2 5 4 GPJ1 3 2 c GPJO 1 0 9 22 Input CAMRESET Input Input CAMHREF Input CAMVSYNC Input CA
234. LCD ON 320x240x16bppx60Hz color TFT 13 kHz Timer internal mode 5 Channel run Audio IIS amp DMA CDCLK 16 9MHz LRCK 44 1kHz Integer data quick sort 65536 EA 2 Pocket PC 2003 MPEG play 3 The above power consumption data is measured in Room temperature with random sample Lot KZZ1FS Typical Sleep mode power 3 uA 1 2 3 3 Al A 27 6 ELECTRONICS 53 2440 RISC MICROPROCESSOR ELECTRICAL DATA 400Mhz Power consumption Without DVS With DVS Figure 27 1 Power Consumption Example Comparison when Applied DVS Scheme NOTE Condition Current measure condition Play Battlife wma bit rate 64kbps on PPC2003 SMDK2440 Core power Without DVS VDDiarm VDDi VDDupll VDDmpll VDDalive 1 3V using DVS VDDiarm VDDi 1 3V lt gt 1 0V VDDupll VDDmpll VDDalive 1 3V Power VDDOP VDDMOP VDDRTC VDDADC 3 3V Refer the Application notes for more information about DVS Table 27 6 Typical Current Decrease by CLKCON Register FCLK HCLK PCLK 300 100 50MHz 1 2V Random sample Unit mA nec 150 usao river s01 aoc ws Camera Tota NOTE This table includes power consumption of each peripheral For example If you do not use Camera and have turned off the Camera block by CLKCON register then you can save the 14 25mA of internal block ELECTRONICS 27 7 ELECTRICAL DATA S3C2440A RISC MICROPROCESSOR A C ELECTRICAL CHARACTERISTICS TXTALCYC
235. LEND STH Line end signal LCD PWREN LCD PWREN LCD PWREN LCD PWREN TH 15 2 ELECTRONICS 53 2440 RISC MICROPROCESSOR LCD CONTROLLER BLOCK DIAGRAM System Bus VCLK LCD_HCLK VLINE HSYNC CPV VFRAME VSYNC STV VM VDEN VIDEO LPC3600 MUX LCD LPCOE LCD LCCINV LCC3600 LCD LPCREV LCD LCCREV LCD LPCREVB LCD LCCREVB LCDCDMA VIDPRCS 23 0 LPC3600 is a timing control logic unit for LTS350Q1 PD1 or LTS350Q1 PD2 LCC3600 is a timing control logic unit for LTS350Q1 PE1 or LTS350Q1 PE2 Figure 15 1 LCD Controller Block Diagram The S3C2440A LCD controller is used to transfer the video data and to generate the necessary control signals such as VFRAME VLINE VCLK VM and so on In addition to the control signals the S3C2440A has the data ports for video data which are VD 23 0 as shown in Figure 15 1 The LCD controller consists of a REGBANK LCDCDMA VIDPRCS TIMEGEN and LPC3600 See the Figure 15 1 LCD Controller Block Diagram The REGBANK has 17 programmable register sets and 256x16 palette memory which are used to configure the LCD controller The LCDCDMA is a dedicated DMA which can transfer the video data in frame memory to LCD driver automatically By using this special DMA the video data can be displayed on the screen without CPU intervention The VIDPRCS receives the video data from the LCDCDMA and sends the video data through the VD 23 0 data ports to the LCD driver after changing th
236. LLANEOUS CONTROL REGISTER MISCCR Continued CLKSEL1 Note Select source clock with CLKOUT1 pad 000 MPLL output 001 UPLL output 010 RTC clock output 011 HCLK 100 PCLK 101 DCLK1 11x reserved mew 2 CLKSELO Note Select source clock with CLKOUTO pad 000 MPLL INPUT Clock XTAL 001 UPLL output 010 FCLK 011 HCLK 100 PCLK 101 DCLK0 11 reserved SEL USBPAD 3 0581 Host Device select register 0 Use USB1 as device 1 Use USB1 as host SPUCR1 1 0 DATA 91 16 port pull up resister is enabled 1 DATA 31 16 port pull up resister is disabled SPUCRO 0 DATA 15 0 port pull up resister is enabled 1 DATA 15 0 port pull up resister is disabled NOTE We recommend not to use this ouput pad to other device s pll clock source ELECTRONICS 9 25 PORTS 53 2440 RISC MICROPROCESSOR DCLK CONTROL REGISTERS DCLKCON DCLKCON 0x56000084 DCLKO 1 control register 0 0 DCLK1CMP 27 24 DCLK1 compare value clock toggle value lt DCLK1DIV If the DCLK1CMP is n Low level duration is n 1 High level duration is DCLK1DIV 1 n 1 DCLK1DIV 23 20 DCLK1 divide value DCLK1 frequency source clock DCLK1DIV 1 DCLK1SelCK 17 Select DCLK1 source clock 0 PCLK 1 UCLK USB DCLK1EN 16 DCLK1 enable 0 DCLK1 disable 1 DCLK1 enable DCLKOCMP 11 8 DCLKO compare value clock toggle value DCLKODIV If the DCLKOCMP is n Lo
237. MENT REGISTER PWR_REG This register acts as a power control register in the USB block PWR_REG 0x52000144 L R W Power management register 0x00 0x52000147 B byte ra USB RESET 3 SET Set by the USB if reset signaling is received from the host This bit remains set as long as reset signaling persists on the bus MCU RESUME 2 R Set by the MCU for MCU Resume CLEAR The USB generates the resume signaling during 10ms if this bit is set in suspend mode SUSPEND MODE 1 SET Set by USB automatically when the device CLEAR enter into suspend mode It is cleared under the following conditions 1 The MCU clears the MCU RESUME bit by writing in order to end remote resume signaling 2 The resume signal from host is received SUSPEND EN R Suspend mode enable control bit 0 Disable default The device will not enter suspend mode 1 Enable suspend mode R W AN 13 6 ELECTRONICS 53 2440 RISC MICROPROCESSOR USB DEVICE INTERRUPT REGISTER EP_INT_REG USB_INT_REG The USB core has two interrupt registers These registers act as status registers for the MCU when it is interrupted The bits are cleared by writing 1 0 to each bit that was set Once the MCU is interrupted MCU should read the contents of interrupt related registers and write back to clear the contents if it is necessary EP INT REG 0 52000148 1 R W EP interrupt pending clear register 0x00 0x5200014B B byte EP1
238. MES Swap instructions take 1 2N 11 incremental cycles to execute where S N and are defined as sequential S cycle non sequential and internal I cycle respectively ASSEMBLER SYNTAX lt SWP gt cond B Rd Rm Rn cond Two character condition mnemonic See Table 3 2 B If B is present then byte transfer otherwise word transfer Rd Rm Rn Expressions evaluating to valid register numbers Examples SWP RO R1 R2 Load RO with the word addressed by R2 and store R1 at R2 SWPB R2 R3 R4 Load R2 with the byte addressed by R4 and Store bits 0 to 7 of R3 at SWPEQ RO RO R1 Conditionally swap the contents of the word addressed by R1 with RO 3 48 ELECTRONICS 53 2440 RISC MICROPROCESSOR ARM INSTRUCTION SET SOFTWARE INTERRUPT SWI The instruction is only executed if the condition is true The various conditions are defined in Table 3 2 The instruction encoding is shown in Figure 3 24 below 31 28 27 24 23 0 Cond 1111 Comment Field Ignored by Processor 31 28 Condition Field Figure 3 24 Software Interrupt Instruction The software interrupt instruction is used to enter Supervisor mode in a controlled manner The instruction causes the software interrupt trap to be taken which effects the mode change The PC is then forced to a fixed value 0x08 and the CPSR is saved in SPSR svc If the SWI vector address is suitably protected by external memory management hardware from modificati
239. MPCLK Input CAMDATA T Input CAMDATA 6 Input CAMDATA 5 Input CAMDATA 4 Input CAMDATA S3 Input CAMDATA 2 Input CAMDATA 1 Input CAMDATA 0 01 Output 11 Reserved 01 Output 11 Reserved 01 Output 11 Reserved 01 Output 11 Reserved 01 Output 11 Reserved 01 Output 11 Reserved 01 Output 11 Reserved 01 Output 11 Reserved 01 Output 11 Reserved 01 Output 11 Reserved 01 Output 11 Reserved 01 Output 11 Reserved 01 Output 11 Reserved 53 2440 RISC MICROPROCESSOR PORTS PORT J CONTROL REGISTERS GPJCON GPJDAT Continued GPJ15 0 12 0 When the port is configured as an input port the corresponding bit is the pin state When the port is configured as an output port the pin state is the same as the corresponding bit When the port is configured as functional pin the undefined value will be read GPJ 12 0 12 0 0 The pull up function attached to the corresponding port pin is enabled 1 The pull up function is disabled ELECTRONICS 9 23 PORTS 53 2440 RISC MICROPROCESSOR MISCELLANEOUS CONTROL REGISTER MISCCR In Sleep mode the data bus D 31 0 or D 15 0 can be set as Hi Z and Output 0 state But because of the characteristics of IO pad the data bus pull up resisters have to be turned on or off to reduce the power consumption D 31 0 pin pull up resisters can be controlled b
240. N INTERFACE SPECIAL REGISTERS ADC CONTROL REGISTER ADCCON ADCCON 0x5800000 ADC control register 0x3FC4 ECFLG 15 End of conversion flag Read only 0 A D conversion in process 1 End of A D conversion PRSCEN 14 converter prescaler enable 0 Disable 1 Enable PRSCVL 13 6 A D converter prescaler value Data value 0 255 NOTE ADC should be set less than PCLK by 5times Ex PCLK 10MHZ ADC Freq 2MHz 5 3 Analog input channel select 000 0 001 1 010 2 011 3 100 101 110 111 2 Standby mode select 1 SEL_MUX M READ START A D conversion start by read 0 Disable start by read operation 1 Enable start by read operation ENABLE START A D conversion starts by enable If READ START is enabled this value is not valid 0 No operation 1 A D conversion starts and this bit is cleared after the start up NOTE When Touch Screen Pads YM YP XP are disabled these ports can be used as Analog input ports AIN4 AIN5 AIN6 AIN7 for ADC 0 Normal operation mode 1 Standby mode ELECTRONICS 16 5 ADC AND TOUCH SCREEN INTERFACE S3C2440A RISC MICROPROCESSOR ADC TOUCH SCREEN CONTROL REGISTER ADCTSC ADCTSC 0x5800004 ADC Touch Screen Control Register UD SEN Detect Stylus Up or Down status 0 Detect Stylus Down Interrupt Signal 1 Detect Stylus Up Interrupt Signal YM SEN YM Switch Enable 0 Outp
241. NAND flash controller operating mode 0 NAND flash controller disable Don t work 1 NAND flash controller enable 6 14 ELECTRONICS 53 2440 RISC MICROPROCESSOR NAND FLASH CONTROLLER COMMAND REGISTER NFCMMD 0x4E000008 NAND flash command set register 158 7 0 flash memory command value ADDRESS REGISTER NFADDR Ox4E00000C NAND flash address set register 0x0000XX00 NFADDR 7 0 NAND flash memory address value 0x00 DATA REGISTER NFDATA 0 4 000010 NAND flash data register NFDATA 31 0 NAND flash read program data value for I O OxXXXX Note Refer to data register configuration in Page 6 5 ELECTRONICS 6 15 NAND FLASH CONTROLLER 53 2440 RISC MICROPROCESSOR MAIN DATA AREA REGISTER NFMECCDO 0x4E000014 R W NAND Flash ECC 1 and 279 register for main 0x00000000 data read Note Refer to ECC module features in Page 6 8 NFMECCD1 0x4E000018 R W NAND Flash ECC 379 4th register for main data 0 00000000 read Note Refer to ECC module features in Page 6 8 NFMECCDO Bit Description ECCData1 0 2nd ECC for 7 0 0x00 Note In Software mode Read this register when you need to read 279 ECC value from flash memory ECCDataO 0 7 0 18 ECC for 7 0 0x00 Note In Software mode Read this register when you need to read 19 ECC value NAND flash memory This register has same read function of NFDATA NOTE Only word access is valid ECCData3 1
242. O which must be 0 and creates two THUMB instructions Instruction 1 H 0 In the first instruction the Offset field contains the upper 11 bits of the target address This is shifted left by 12 bits and added to the current PC address The resulting address is placed in LR Instruction 2 1 In the second instruction the Offset field contains an 11 bit representation lower half of the target address This is shifted left by 1 bit and added to LR LR which now contains the full 23 bit address is placed in PC the address of the instruction following the BL is placed in LR and bit 0 of LR is set The branch offset must take account of the prefetch operation which causes the PC to be 1 word 4 bytes ahead of the current instruction 4 38 ELECTRONICS 53 2440 RISC MICROPROCESSOR THUMB INSTRUCTION SET INSTRUCTION CYCLE TIMES This instruction format does not have an equivalent ARM instruction Table 4 20 The BL Instruction 1 temp next instruction address PC LR OffsetLow lt lt 1 LR temp 1 EXAMPLES BL faraway Unconditionally Branch to faraway next and place following instruction address ie next in R14 the Link register and set bit 0 of LR high Note that the THUMB opcodes will contain the number of halfwords to offset faraway Must be Half word aligned ELECTRONICS 4 39 THUMB INSTRUCTION SET 53 2440 RISC MICROPROCESSOR INSTRUCTION SET EXAMPLES The following examples sho
243. O request Only for UARTO request Only for UART2 11 DMA1 request Only for UART1 Determine which function is currently able to read data from UART receive buffer register UART Rx Enable Disable 00 Disable 01 Interrupt request or polling mode 10 DMAO request Only for UARTO request Only for UART2 11 request Only for UART1 NOTE When the UART does not reach the FIFO trigger level and does not receive data during 3 word time in DMA receive mode with FIFO the Rx interrupt will be generated receive time out and the users should check the FIFO status and read out the rest ELEGTRONIGS 11 13 UART 53 2440 RISC MICROPROCESSOR UART FIFO CONTROL REGISTER There are three UART FIFO control registers including UFCONO UFCON1 and 2 in the UART block Tx FIFO Trigger Level Determine the trigger level of transmit FIFO 00 Empty 01 16 byte 10 32 byte 11 48 byte Rx FIFO Trigger Level Determine the trigger level of receive FIFO 00 1 byte 01 8 byte 10 16 byte 11 2 32 byte Tx FIFO Reset 2 Auto cleared after resetting FIFO 0 Normal 1 Tx FIFO reset Rx FIFO Reset 1 Auto cleared after resetting FIFO 0 Normal 1 Rx FIFO reset FIFO Enable 10 0 Disable 1 Enable NOTE When the UART does not reach the FIFO trigger level and does not receive data during 3 word time in DMA receive mode with FIFO the Rx interrupt will be generated receive time o
244. OPROCESSOR INTERRUPT SUB SOURCES Sub Sources Desi INT ERR1 UART1 error interrupt INT UART1 INT TXD1 UART1 transmit interrupt INT_UART1 INT_RXD2 UART2 receive interrupt INT_UART2 INT_RXD1 UART1 receive interrupt INT_UART1 INT_ERRO UARTO error interrupt INT UARTO INT TXDO UARTO transmit interrupt INT UARTO INT RXDO UARTO receive interrupt INT UARTO 14 4 ELECTRONICS 53 2440 RISC MICROPROCESSOR INTERRUPT CONTROLLER INTERRUPT PRIORITY GENERATING BLOCK The priority logic for 32 interrupt requests is composed of seven rotation based arbiters six first level arbiters and one second level arbiter as shown in Figure 14 1 below 4 4 REQ2 EINT1 ARBITERO 2 lt REQ4 EINT3 ARBITER6 4 REQO EINT4 7 RBEQ2INT CAM lt ARBITER FLT lt TICK lt WDT AC97 4 REQO INT TIMERO REONT TIMER ARBITER2 REQ3 INT TIMER3 TIMERA REQ5 INT UART2 ARBITER3 ARBITER4 ARBITER5 Figure 14 2 Priority Generating Block ARM IRQ LCD REQ1 INT DMAO REQ2 INT DMA1 REQS INT REQ4 INT_DMA3 501 SPIO REQ1 INT UART1 2 USBD REQ4 INT_USBH REQ1 INT UARTO REQ2 INT SPI1 REQ4 INT lt q lt lt q lt _ lt q gt lt q g
245. OUT SCLK in case when EXTCLK is e 27 9 27 6 Manual Reset Input Timing 27 9 27 7 Power On Oscillation Setting Timing Diagram sess 27 10 27 8 Sleep Mode Return Oscillation Setting Timing 27 11 27 9 ROM SRAM Burst READ Timing Diagram 1 Tacs 0 Tcos 0 2 0 0 0 ST 0 DW 16bit 27 12 27 10 ROM SRAM Burst READ Timing Diagram 1 Tacs 0 Tcos 0 Tacc 2 0 0 0 5 1 DW 16bit 27 13 S3C2440A MICROCONTROLLER xxvii Figure Number 27 11 27 12 27 13 27 14 27 15 27 16 27 17 27 18 27 19 27 20 27 21 27 22 27 23 27 24 27 25 27 26 27 27 27 28 27 29 27 30 27 31 27 32 27 33 27 34 27 35 27 36 27 37 xxviii List of Figures Continued Title Page Number External Bus Request in ROM SRAM Cycle Tacs 0 0 Tacc 8 0 0 0 5 0 27 14 ROM SRAM READ Timing Diagram I Tacs 2 Tcos 2 Tacc 4 Toch 2 Tcah 2 PMC 0 0 27 15 ROM SRAM READ Timing Diagram II Tacs 2 Tcos 2 4 Toch 2 Tcah 2cycle 0 57 1 27 16 ROM SRAM WRITE Timing Diagram I T
246. PROCESSOR LCD Control 4 Register LCDCON4 0X4D00000C LCD control 4 register 0x00000000 MVAL 15 8 STN These bit define the rate at which the VM signal will toggle if the 0X00 MMODE bit is set to logic 1 7 0 TFT Horizontal sync pulse width determines the HSYNC pulse s high 0X00 level width by counting the number of the VCLK STN WLH 1 0 bits determine the VLINE pulse s high level width by counting the number of the HCLK WLH 7 2 are reserved 00 16 01 32 HCLK 10 48 HCLK 11 64 HCLK STN 15 30 ELECTRONICS 53 2440 RISC MICROPROCESSOR LCD CONTROLLER LCD Control 5 Register LCDCON5 0X4D000010 LCD control 5 register 0x00000000 Reserved 31 17 This bit is reserved and the value should be 0 VSTATUS 16 15 TFT Vertical Status read only 00 VSYNC 01 BACK Porch 10 ACTIVE 11 FRONT Porch HSTATUS 14 13 TFT Horizontal Status read only 00 HSYNC 01 BACK Porch 10 ACTIVE 11 FRONT Porch BPP24BL 12 TFT This bit determines the order of 24 bpp video memory 0 LSB valid 1 MSB Valid INVVCLK 10 STN TFT This bit controls the polarity of the VCLK active edge 0 The video data is fetched at VCLK falling edge 1 The video data is fetched at VCLK rising edge INVVLINE STN TFT This bit indicates the VLINE HSYNC pulse polarity 0 Normal 1 Inverted INVVFRAME STN TFT This bit indicates the VFRAME VSYNC pulse polarity 0 Normal 1 Inv
247. R 0x57000088 L R W BCD year register Undefined 0x5700008B B by byte YEARDATA 7 0 BCD value for year 00 99 17 10 ELECTRONICS 53 2440 RISC MICROPROCESSOR WATCHDOG TIMER WATCHDOG TIMER OVERVIEW The S3C2440A watchdog timer is used to resume the controller operation whenever it is disturbed by malfunctions Such as noise and system errors It can be used as a normal 16 bit interval timer to request interrupt service The watchdog timer generates the reset signal for 128 PCLK cycles FEATURES Normal interval timer mode with interrupt request Internal reset signal is activated for 128 PCLK cycles when the timer count value reaches 0 time out ELECTRONICS 18 1 WATCHDOG TIMER S3C2440A RISC MICROPROCESSOR WATCHDOG TIMER OPERATION Figure 18 1 shows the functional block diagram of the watchdog timer The watchdog timer uses only PCLK as its source clock The PCLK frequency is prescaled to generate the corresponding watchdog timer clock and the resulting frequency is divided again Interrupt PCLK gt 8 bit Prescaler WONT Reset Signal Generator RESET Down Counter WTCON 15 8 WTCON 4 3 WTCON 2 WTCON O0 Figure 18 1 Watchdog Timer Block Diagram The prescaler value and the frequency division factor are specified in the watchdog timer control WTCON register Valid prescaler values range from 0 to 28 1 The frequency division factor can be selected as 16 32 64 or 128 Use the f
248. R20 C10 ADDR21 GPA6 ADDR21 ADDR19 GPA4 ADDR19 lt pu 20 9 9 L I lt lt Q 2 2 2 2 2 2 2 2 2 2 2 2 2 2 EUM EEM ELM cH UN RIS OPUS EMI me 1 10 ELECTRONICS 53 2440 RISC MICROPROCESSOR PRODUCT OVERVIEW Table 1 2 53 2440 289 Pin FBGA Pin Assignments Sheet 2 of 9 Continued Function BUS REQ Sleep nRESET Type 8 H6 G3 H5 H4 H3 H7 J8 H2 G5 G7 G2 J3 J4 1 CAMCLKOUT GPJ11 O L o gt gt Hi z O L azoo 1 gt Dame DAT E1 gjg gt gt ho b12s b12s b12s b12s b12s b12s b12s b12s b12s b12s b12s b12s gt gt Hi z O L Hi z O L Hi z O L DATAS HizOQ Hi z 2 ololololololo 010 10 10 10 14 18 DATA18 d ELECTRONICS 1 11 PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR Table 1 2 5
249. REGISTER NFCONF 0 4 000000 NAND flash configuration register 0x0000100X NFCONF Bit Initial State 15 14 Reseved oo CLE amp ALE duration setting value 0 3 Duration HCLK x TACLS Reseved Hi __ __ TWRPHO duration setting value 0 7 Duration HCLK x TWRPHO 1 TWRPH1 duration setting value 0 7 Duration HCLK x TWRPH1 1 AdvFlash Read only Advance NAND flash memory for auto booting H W Set 0 Support 256 or 512 byte page NAND flash memory NCON0 1 Support 1024 or 2048 byte page NAND flash memory This bit is determined by NCONO pin status during reset and wake up from sleep mode PageSize Read only NAND flash memory page size for auto booting AdvFlash H W Set PageSize GPG13 When AdvFlash is 0 0 256 Word page 1 512 Bytes page When AdvFlash is 1 0 1024 Word page 1 2048 Bytes page This bit is determined by GPG13 pin status during reset and wake up from sleep mode After reset the GPG13 can be used as general port or External interrupt AddrCycle Read only NAND flash memory Address cycle for auto booting H W Set AdvFlash AddrCycle GPG14 When AdvFlash is 0 0 3 address cycle 1 4 address cycle When AdvFlash is 1 0 4 address cycle 1 5 address cycle This bit is determined by GPG14pin status during reset and wake up from sleep mode After reset the GPG14can be used as general port
250. RT D CONTROL REGISTERS GPDCON GPDDAT GPDUP Continued GPD 15 0 15 0 When the port is configured as input port the corresponding bit is the pin state When the port is configured as output port the pin state is the same as the corresponding bit When the port is configured as functional pin the undefined value will be read GPD 15 0 15 0 0 The pull up function attached to the corresponding port pin is enabled 1 The pull up function is disabled ELECTRONICS 9 15 PORTS 53 2440 RISC MICROPROCESSOR PORT E CONTROL REGISTERS GPECON GPEDAT GPEUP GPECON GPE15 31 30 00 Input 01 Output 10 IICSDA 11 Reserved This pad is open drain There is no Pull up option GPE14 29 28 00 Input 01 Output 10 IICSCL 11 Reserved This pad is open drain There is no Pull up option GPE13 27 26 Input 01 Output SPICLK0 11 Reserved GPE12 25 24 Input 01 Output SPIMOSIO 11 Reserved GPE11 23 22 Input 01 Output 1 SPIMISO0 11 Reserved GPE10 21 20 Input 01 Output ae SDDAT3 11 Reserved GPE9 19 18 Input 01 Output NS SDDAT2 11 Reserved 17 16 Input 01 Output 12 SDDAT1 11 Reserved GPE7 15 14 Input 01 Output SDDATO 11 Reserved GPE6 13 12 Input 01 Output 1 SDCMD 11 Reserved GPE5 11 10 Input 01 Output 1 SDCLK 11 Reserved GPE4 Input 01 Output
251. Register 20 Load Store Bit 0 Store to coprocessor 1 Load from coprocessor 21 Coprocessor Operation Mode 31 28 Condition Field Figure 3 27 Coprocessor Register Transfer Instructions THE COPROCESSOR FIELDS The CP field is used as for all coprocessor instructions to specify which coprocessor is being called upon The CP Opc CRn CP and CRm fields are used only by the coprocessor and the interpretation presented here is derived from convention only Other interpretations are allowed where the coprocessor functionality is incompatible with this one The conventional interpretation is that the CP Opc and CP fields specify the operation the coprocessor is required to perform CRn is the coprocessor register which is the source or destination of the transferred information and CRm is a second coprocessor register which may be involved in some way which depends on the particular operation specified 3 56 ELECTRONICS 53 2440 RISC MICROPROCESSOR ARM INSTRUCTION SET TRANSFERS TO R15 When coprocessor register transfer to ARM920T has R15 as the destination bits 31 30 29 and 28 of the transferred word are copied into the N Z C and V flags respectively The other bits of the transferred word are ignored and the PC and other CPSR bits are unaffected by the transfer TRANSFERS FROM R15 A coprocessor register transfer from ARM920T with R15 as the source register will store the 12 INSTRUCTION CYCLE TIMES
252. Ri Giheung Eup Yongin City Gyeonggi Do Korea 37 Suwon 449 900 TEL 82 031 209 1490 FAX 82 331 209 1909 Home Page URL Http Awww samsungsemi com Printed in the Republic of Korea Table of Contents Chapter 1 Product Overview u l T L ie Qua 1 1 eau ee eae u dog ae eee ped Sa Ate ee decade a apas RR ERI sayas 1 2 Block DiaQram iv a Rees s 1 5 Assignments u L S uu 1 6 Signal Descriptions ua eds eed 1 20 S3C2440A Special 1 26 Chapter 2 Programmer s Model OVelVieW A vba etre ique ER RE epe Eques n eques tete 2 1 Processor Operatirig States i i ii i eda e Dade 2 1 SWICHING State e veces riter bred A 2 1 Memory qua au Saa 2 1 Big Enden 2 2 Little Endian 2 2 INSTRUCTION u u 2 2 Operating eto For haec e ete 2 3 aep eer EET 2 3 The Program Status Registers a u tte set Ee Pete Doe Eget be ER kd 2 7 mela emen 2 10 1016
253. S 53 2440 RISC MICROPROCESSOR ELECTRICAL DATA Table 27 14 IIC BUS Controller Module Signal Timing Vpp 1 2 V 0 05 V 40 to 85 C 3 3V 0 3V SCL clock frequency scL std 100 kHz fast 400 SCL high level pulse width teci HIGH std 4 0 us fast 0 6 SCL low level pulse width tecLLOW std 4 7 us fast 1 3 fast 1 3 START hold time tsTARTS std 4 0 us fast 0 6 SDA hold time teDAH std 0 std us fast 0 fast 0 9 SDA setup time tspas std 250 ns fast 100 STOP setup time teTOPH std 4 0 us fast 0 6 NOTES Std means Standard Mode and fast means Fast Mode 1 ThellC data hold time tsDAH is minimum Ons data hold time is minimum Ons for standard fast bus mode specification v2 1 Please check whether the data hold time of your device is 0 nS or not 2 IIC controller supports only bus device standard fast bus mode and not C bus device Table 27 15 SD MMC Interface Transmit Receive Timing Constants Vpp 1 2 V 0 1 V TA 40 to 85 3 3V 0 3V SD command output delay time 9 o SD command input setup time 4 m SD command input hold time de 1 m ELECTRONICS 27 39 ELECTRICAL DATA S3C2440A RISC MICROPROCESSOR Table 27 16 SPI Interface Transmit Receive Timing Constants Vpp 1 2 V 0 1 V 40 to 85 3 3V 0 3V Min Typ Max
254. SDIO CONTROLLER SDI Interrupt Mask Register SDIIntMsk SDIIntMsk 0 5 00003 SDI interrupt mask register Interrupt 18 Determines SDI generate interrupt if busy signal is not active Enable NoBusylnt 0 Disable Interrupt enable RspCrc Interrupt 17 Determines SDI generate an interrupt if response CRC check Enable RspCrclnt fails 0 Disable 1 Interrupt enable CmdSent Interrupt 16 Determines SDI generate an interrupt if command sent no Enable response required CmdSentint 0 Disable 1 Interrupt enable CmdTout Interrupt 15 Determines SDI generate an interrupt if command response Enable timeout occurs 0 Disable 1 Interrupt enable RspEnd Interrupt 14 Determines SDI generate an interrupt if command response Enable RspEndlnt received 0 Disable 1 Interrupt enable lOIntDet Interrupt 12 Determines SDI generate an interrupt if sd host receives SDIO Enable IntDetint Interrupt from the card for SDIO 0 Disable 1 Interrupt enable FFfail Interrupt 11 Determines SDI generate an interrupt if FIFO fail error occurs Enable FFfaillnt 0 Disable 1 Interrupt enable Enable CrcStalnt 0 Disable 1 Interrupt enable CrcSta Interrupt 10 Determines SDI generate an interrupt if CRC status error occurs DatCrc Interrupt Determines SDI generate an interrupt if data receive CRC failed Enable DatCrcint 0 Disable 1 Interrupt enable
255. SIC TIMER OPERATION Start bit 1 Timer is started JTCNTn TCMPn Auto reload TCNTnZTCMPn Timer is stopped 0 Manual update 1 Manual update 0 Auto reload 1 Auto reload 1 Command C Status Figure 10 2 Timer Operations A timer except the timer ch 5 has TCNTBn TCNTn TCMPBn and TCMPn TCNTn and TCMPn are the names of the internal registers The TCNTn register can be read from the TCNTOn register The TCNTBn and the TCMPBn are loaded into the TCNTn and the TCMPn when the timer reaches 0 When the TCNTn reaches 0 an interrupt request will occur if the interrupt is enabled ELECTRONICS 10 3 PWM TIMER S3C2440A RISC MICROPROCESSOR AUTO RELOAD amp DOUBLE BUFFERING S3C2440A PWM Timers have a double buffering function enabling the reload value changed for the next timer operation without stopping the current timer operation So although the new timer value is set a current timer operation is completed successlully The timer value can be written into Timer Count Buffer register TCNTBn and the current counter value of the timer can be read from Timer Count Observation register If the TCNTBn is read the read value does not indicate the current state of the counter but the reload value for the next timer duration The auto reload operation copies the TCNTBn into TCNTn when the TCNTn reaches 0 value written into the is loaded to the TCNTn only when the TCN
256. SOR IIC BUS INTERFACE Acknowledgement Acknowledgement Signal from Receiver Signal from Receiver 9 1 2 Byte Complete Interrupt Clock Line Held Low by within Receiver receiver and or transmitter Figure 20 4 Data Transfer on the IIC Bus ACK SIGNAL TRANSMISSION To complete a one byte transfer operation the receiver should send an ACK bit to the transmitter The ACK pulse should occur at the ninth clock of the SCL line Eight clocks are required for the one byte data transfer The master should generate the clock pulse required to transmit the ACK bit The transmitter should release the SDA line by making the SDA line High when the ACK clock pulse is received The receiver should also drive the SDA line Low during the ACK clock pulse so that the SDA keeps Low during the High period of the ninth SCL pulse The ACK bit transmit function can be enabled or disabled by software IICSTAT However the ACK pulse on the ninth clock of SCL is required to complete the one byte data transfer operation Clock to Output I 1 4 i Data Output by Transmitter Data Output by Receiver SCL from Master Condition Clock Pulse for Acknowledgment Figure 20 5 Acknowledge on the IIC Bus ELECTRONICS 20 5 IIC BUS INTERFACE 53 2440 RISC MICROPROCESSOR READ WRITE OPERATION In Transmitter mode when the data is transferred the IIC bus interface will wait until lIC bus Data Shift IICDS register rec
257. SSOR INTERRUPT CONTROLLER INTERRUPT PENDING INTPND REGISTER Continued INT_ADG 31 0 Not requested 1 Requested INT 30 0 Not requested 1 Requested INT SPH 29 0 Not requested 1 Requested INT UARTO 28 0 Not requested 1 Requested INT 27 0 Not requested 1 Requested 20 INT_USBH 26 0 Not requested 1 Requested INT_USBD 25 0 Not requested 1 Requested INT_NFCON 24 0 Not requested 1 Requested INT_UART1 23 0 Not requested 1 Requested INT SPIO 22 0 Not requested 1 Requested INT 501 21 0 Not requested 1 Requested INT DMAS3 20 0 Not requested 1 Requested INT DMA2 19 0 Not requested 1 Requested INT DMA1 18 0 Not requested 1 Requested INT DMAO 17 0 Not requested 1 Requested INT LCD 16 0 Not requested 1 Requested INT_UART2 15 0 Not requested 1 Requested INT_TIMER4 14 0 Not requested 1 Requested INT_TIMER3 13 0 Not requested 1 Requested INT TIMER2 12 0 Not requested 1 Requested INT_TIMER1 11 0 Not requested 1 Requested INT_TIMER0 10 0 Not requested 1 Requested INT_WDT_AC97 0 Not requested 1 Requested INT TICK B 0 Not requested 1 Requested nBATT_FLT 0 Not requested 1 Requested INT CAM 0 Not requested 1 Requested 8_23 0 Not requested 1 Requested
258. Slave address 7 0 7 bit slave address latched from the IIC bus When serial output enable 0 in the IICSTAT IICADD is write enabled The IICADD value can be read any time regardless of the current serial output enable bit IICSTAT setting Slave address 7 1 Not mapped 0 MULTI MASTER TRANSMIT RECEIVE DATA SHIFT IICDS REGISTER IICDS 0x5400000C IIC Bus transmit receive data shift register Data shift 7 0 8 bit data shift register for Tx Rx operation When serial output enable 1 in the IICSTAT IICDS is write enabled The IICDS value can be read any time regardless of the current serial output enable bit IICSTAT setting ELECTRONICS 20 13 IIC BUS INTERFACE 53 2440 RISC MICROPROCESSOR MULTI MASTER IIC BUS LINE CONTROL IICLC REGISTER IICLC 0x54000010 multi master line control register Filter enable 2 IIC bus filter enable bit When SDA port is operating as input this bit should be High This filter can prevent from occurred error by a glitch during double of PCLK time 0 Filter disable 1 Filter enable SDA output delay SDA line delay length selection bits SDA line is delayed as following clock time PCLK 00 0 clocks 01 5 clocks 10 10 clocks 11 15 clocks 20 14 ELECTRONICS 53 2440 RISC MICROPROCESSOR IIS BUS INTERFACE 2 1 IIS BUS INTERFACE OVERVIEW Currently many digital audio systems are attracting the consumers on the market in
259. T oseo maen __ femena oweoo002e Mode register set or SDRAM BANKS Mode register set or SDRAM 1 26 ELECTRONICS 53 2440 RISC MICROPROCESSOR PRODUCT OVERVIEW Table 1 4 S3C2440A Special Registers Sheet 2 of 14 Continued mee ss B Endian L Endian Write USB Host Controller heo w Conran situs Tow j HeCommonsiatus ogo oao 1 0 0 moca oase ows oa 1 2 Famecounergoup _ Soo lowo Heroes oo 1 0 oum w FW memtmascono
260. THUMB INSTRUCTION SET FORMAT 18 UNCONDITIONAL BRANCH 15 10 14 13 12 11 10 0 Immediate Value Figure 4 19 Format 18 OPERATION This instruction performs a PC relative Branch The THUMB assembler syntax is shown below The branch offset must take account of the prefetch operation which causes the PC to be 1 word 4 bytes ahead of the current instruction Table 4 19 Summary of Branch Instruction B label BAL label halfword offset Branch PC relative Offset11 lt lt 1 where label is PC 2048 bytes NOTE The address specified by label is a full 12 bit two s complement address but must always be halfword aligned ie bit 0 set to 0 since the assembler places label gt gt 1 in the Offset11 field EXAMPLES here B here Branch onto itself Assembles to OxE7FE Note effect of PC offset B jimmy Branch to jimmy Note that the THUMB opcode will contain the number of halfwords to offset jimmy Must be halfword aligned ELECTRONICS 4 37 THUMB INSTRUCTION SET 53 2440 RISC MICROPROCESSOR FORMAT 19 LONG BRANCH WITH LINK 15 14 13 10 i 12 11 _ 10 0 Long Branch and Link Offset High Low 11 Low High Offset Bit 0 Offset high 1 Offset low Figure 4 20 Format 19 OPERATION This format specifies a long branch with link The assembler splits the 23 bit two s complement half word offset specified by the label into two 11 bit halves ignoring bit
261. TRICTIONS e n user mode the control bits of the CPSR are protected from change so only the condition code flags of the CPSR can be changed In other privileged modes the entire CPSR can be changed Note that the software must never change the state of the T bit in the CPSR If this happens the processor will enter an unpredictable state e The SPSR register which is accessed depends on the mode at the time of execution For example only SPSR is accessible when the processor is in mode e You must not specify R15 as the source or destination register Also do not attempt to access an SPSR in User mode since no such register exists 3 18 ELECTRONICS 53 2440 RISC MICROPROCESSOR ARM INSTRUCTION SET MRS transfer PSR contents to a register 31 28 27 23 22 21 16 15 12 11 0 Ps 001111 Rd 000000000000 15 12 Destination Register 22 Source PSR 0 CPSR 1 SPSR_ lt current mode 31 28 Condition Field MSR transfer register contents to PSR 31 28 27 23 22 21 12 11 4 00010 Pd 101001111 00000000 3 0 Source Register 22 Destination PSR 0 CPSR 1 SPSR current mode 31 28 Condition Field MSR transfer register contents or immediate value to PSR flag bits only 31 28 27 26 25 24 23 22 21 12 11 o 22 Destination PSR 0 CPSR 1 SPSR current mode 25 Immediate Operand 0 Source operand is a register 1 SPSR current mode 11 0 Source Operand 0
262. TROL STATUS 1 5 REGISTER IICSTAT 0x54000004 IIC Bus control status register 0 0 Mode selection IIC bus master slave Tx Rx mode select bits 00 Slave receive mode 01 Slave transmit mode 10 Master receive mode 11 Master transmit mode Busy signal status IIC Bus busy signal status bit START STOP condition 0 read Not busy when read write STOP signal generation 1 read Busy when read write START signal generation The data in IICDS will be transferred automatically just after the start signal Serial output 4 IIC bus data output enable disable bit 0 Disable Rx Tx 1 Enable Rx Tx Arbitration status flag 3 IIC bus arbitration procedure status flag bit 0 Bus arbitration successful 1 Bus arbitration failed during serial I O Address as slave status flag IIC bus address as slave status flag bit 0 Cleared when START STOP condition was detected 1 Received slave address matches the address value in the IICADD Address zero status flag IIC bus address zero status flag bit 0 Cleared when START STOP condition was detected 1 Received slave address is 00000000b Last received bit status flag IIC bus last received bit status flag bit 0 Last received bit is 0 ACK was received 1 Last received bit is 1 ACK was not received 20 12 ELECTRONICS 53 2440 RISC MICROPROCESSOR IIC BUS INTERFACE MULTI MASTER IIC BUS ADDRESS IICADD REGISTER IICADD 0x54000008 IIC Bus address register
263. Table 21 2 Usable Serial Bit Clock Frequency IISCLK 16 or 32 4815 Serial clock frequency IISCLK CODECLK 25615 16fs 32fs 32fs CODECLK 38415 1615 3215 4815 3216 4815 7 21 4 ELECTRONICS 53 2440 RISC MICROPROCESSOR IIS BUS INTERFACE IIS BUS INTERFACE SPECIAL REGISTERS IIS CONTROL IISCON REGISTER IISCON 0 55000000 Li HW Li W Bi W R W IIS control register 0x100 0x55000002 Left Right channel index 0 Left Read only 1 Right Transmit FIFO ready flag 0 Empty Read only 1 Not empty Receive FIFO ready flag 0 Full Read only 1 Not full Transmit DMA service request 5 0 Disable 1 Enable Receive service request 0 Disable 1 Enable Transmit channel idle command In Idle state the IISLRCK is inactive Pause Tx 0 Not idle 1 Idle Receive channel idle command In Idle state the IISLRCK is inactive Pause Rx 0 Not idle 1 Idle IIS prescaler 1 0 Disable 1 Enable IIS interface 0 Disable stop 1 Enable start NOTES 1 IISCON register is accessible for each byte halfword and word unit using STRB STRH STR and LDRB LDRH LDR instructions or char short int int type pointer in Little Big endian mode 2 Li HW W Little HalfWord Word Bi HW W Big HalfWord Word ELECTRONICS 21 5 IIS BUS INTERFACE 53 2440 RISC MICROPROCESSOR IIS MODE REGISTER IISMOD REGISTER IISMOD 0 55000004 Li W Li HW Bi W IIS mode re
264. Tn reaches 0 and auto reload is enabled If the TCNTn becomes 0 and the auto reload bit is 0 the TCNTn does not operate any further Write Write TONTBn 100 200 Start 150 Auto reload _ _ AM 4 gt 4 gt 150 100 100 200 Interrupt _____ Lb bL Figure 10 3 Example of Double Buffering Function 10 4 ELECTRONICS 53 2440 RISC MICROPROCESSOR PWM TIMER TIMER INITIALIZATION USING MANUAL UPDATE BIT AND INVERTER BIT An auto reload operation of the timer occurs when the down counter reaches 0 So a starting value of the TCNTn has to be defined by the user in advance In this case the starting value has to be loaded by the manual update bit The following steps describe how to start a timer 1 Write the initial value into TCNTBn and TCMPBn 2 Setthe manual update bit of the corresponding timer It is recommended that you configure the inverter on off bit Whether use inverter or not 3 Set start bit of the corresponding timer to start the timer and clear the manual update bit If the timer is stopped by force the TCNTn retains the counter value and is not reloaded from TCNTBn If a new value has to be set perform manual update NOTE Whenever TOUT inverter on off bit is changed the TOUTn logic value will also be changed whether the timer runs Therefore it is desirable that the inverter on off bit is configured with the manual update
265. UL CL 350pF p p 0 NOTE All measurement conditions are in accordance with the Universal Serial Bus Specification 1 1 Final Draft Revision ELECTRONICS 27 41 ELECTRICAL DATA S3C2440A RISC MICROPROCESSOR Table 27 20 NAND Flash Interface Timing Constants VDDalive VDDiarm 1 2 V 0 1 V 40 to 85 C 3 3V 0 3V 3 0V 0 3V 2 5V 0 2V 1 8V 0 1V NFCON read data hold requirement time 0 3 0 3 0 3 0 3 27 42 ELECTRONICS
266. XSCLK 6 6ns Del 8 615 Delay 6 8ns Delay Figure 8 1 Basic DMA Timing Diagram ELECTRONICS 8 3 S3C2440A RISC MICROPROCESSOR Demand Handshake Mode Comparison Demand and Handshake modes are related to the protocol between XnXDREQ and XnXDACK Figure 8 2 shows the differences between the two modes At the end of one transfer Single Burst transfer DMA checks the state of double synched XnXDREQ Demand Mode If XnXDREQ remains asserted the next transfer starts immediately Otherwise it waits for XnXDREQ to be asserted Handshake Mode If XnXDREQ is de asserted de asserts XnXDACK in 2cycles Otherwise it waits until XnXDREQ is de asserted Caution XnXDREQ has to be asserted low only after the de assertion high of XnXDACK Demand Mode XnXDREQ 2nd Transfer XnXDACK BUS Acquisiton Handshake BUS Acquisiton hod XnXDREQ 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Read Write coup 1 1 1 1 1 XnXDACK 4 5 2 Synch Figure 8 2 Demand Handshake Mode Comparison 8 4 ELECTRONK S 53 2440 RISC MICROPROCESSOR Transfer Size There are two different transfer sizes unit and Burst 4 holds the bus firmly during the transfer of the chunk of data Thus other bus masters cannot get the bus Burst 4 Transfer Size There will be four sequential Reads and Writes performe
267. XTCLK PLL Lock Time Sleep mode return oscillation setting time Interval before CPU runs after nRESET is released H Reset assert time after clock stabilization ELECTRONICS 27 35 ELECTRICAL DATA S3C2440A RISC MICROPROCESSOR Table 27 8 ROWSRAM Bus Timing Constants Vppi Vppiarm 1 2 V 0 1 V Ta 40 to 85 C 3 3V 0 3V 3 0 0 3V 2 5V 0 2V 1 8V Parameter Symbol Min 3 3V 3 0V 2 5V 1 8V 0 1V 3 3V 3 0V 2 5V 1 8V ROM SRAM output enable delay 2 2 2 3 5 5 5 6 ROM SRAM read data setup time ts 1 1 1 2 ROM SRAM read data hold time ma 0 0 7070 os ROM SRAM write byte enable delay _ 2 2 2 3 5 5 6 7 ROM SRAM external wait setup time 8 8 4044 ROM SRAM external wait hold time 0 0 0 0 write enable delay 2 2 2 3 5 5 6 7 Table 27 9 Memory Interface Timing Constants VpDiarm 1 2 V 0 1 V Ta 40 to 85 C 3 3V 0 3V 3 0V 0 3V 2 5V 0 2 1 8V 0 1V SDRAM clock enable delay NOTE Minimum tsps 2ns 3ns 3ns when 3 3V 3 0V 2 5V 1 8V respectively 27 36 ELECTRONICS 53 2440 RISC MICROPROCESSOR ELECTRICAL DATA Table 27 10 External Bus Request Timing Constants Vpp 1 2 V 0 1 V 40 to 85
268. YNC signal is asserted to cause the LCD s line pointer to start over at the top of the display The VSYNC and HSYNC pulse generation depends on the configurations of both the HOZVAL field and the LINEVAL field in the LCDCON2 3 registers The HOZVAL and LINEVAL can be determined by the size of the LCD panel according to the following equations HOZVAL Horizontal display size 1 LINEVAL Vertical display size 1 The rate of VCLK signal depends on the CLKVAL field in the LCDCON1 register Table 15 3 defines the relationship of VCLK and CLKVAL The minimum value of CLKVAL is 0 VCLK Hz HCLK CLKVAL 1 x2 The frame rate is VSYNC signal frequency The frame rate is related with the field of VSYNC VBPD VFPD LINEVAL HSYNC HBPD HFPD HOZVAL and CLKVAL in LCDCON1 LCDCON2 3 4 registers Most LCD drivers need their own adequate frame rate The frame rate is calculated as follows Frame Rate 1 VSPW 1 VBPD 1 LIINEVAL 1 VFPD 1 x HSPW 1 HBPD 1 1 HOZVAL 1 x 2 CLKVAL 1 HCLK Table 15 3 Relation between VCLK CLKVAL TFT HCLK 60MHz CLKVAL 60MHz X VCLK 60 MHz 4 15 0 MHz 60 MHz 6 10 0 MHz 60 MHz 2048 30 0 kHz VIDEO OPERATION The TFT LCD controller within the 53 2440 supports 1 2 4 or 8 bpp bit per pixel palettized color displays and 16 or 24 bpp non palettized true color displays 256 Color Palette The S3C2440A can support the 25
269. a D ADD Rb Ra Rb LSL n 3 If C MOD 4 3 say 2 n D 1 D odd n gt 1 D 1 RSB Rb Ra Ra LSL 0 lt gt 1 Rb Ra D RSB Rb Ra Rb LSL n This is not quite optimal but close An example of its non optimality is multiply by 45 which is done by RSB Rb Ra Ra LSL 2 Multiply by 3 RSB Rb Ra Rb LSL 2 Multiply by 4 3 1 11 ADD Rb Ra Rb LSL 2 Multiply by 4 11 1 45 rather than by ADD Rb Ra Ra LSL 3 Multiply by 9 ADD Rb Rb Rb LSL 2 Multiply by 5 9 45 3 62 ELECTRONICS 53 2440 RISC MICROPROCESSOR LOADING A WORD FROM AN UNKNOWN ALIGNMENT BIC LDMIA AND MOVS MOVNE RSBNE ORRNE ELECTRONICS Rb Ra 3 Rb Rd Rc Rb Ra 3 Rb Rb LSL 3 Rd Rd LSR Rb Rb Rb 32 Rd Rd Re LSL Rb ARM INSTRUCTION SET Enter with address in Ra 32 bits uses Rb Rc result in Rd Note d must be less than c e g 0 1 Get word aligned address Get 64 bits containing answer Correction factor in bytes now in bits and test if aligned Produce bottom of result word if not aligned Get other shift amount Combine two halves to get result 3 63 ARM INSTRUCTION SET 53 2440 RISC MICROPROCESSOR NOTES 3 64 ELECTRONICS 53 2440 RISC MICROPROCESSOR THUMB INSTRUCTION SET THUMB INSTRUCTION SET THUMB INSTRUCTION SET FORMAT The thumb instruction sets are 16 bit versions of ARM instruction sets 32 bit format The ARM instructions are reduced to 16 bit versions Thumb instructions at the cost of versatile func
270. acs 2 Tcos 2 Tacc 4 Toch 2 Tcah 2 0 5 0 27 17 ROM SRAM WRITE Timing Diagram 1 Tacs 2 5 2 4 Toch 2 2 0 1 27 18 External nWAIT READ Timing Diagram Tacs 0 Tcos 0 6 0 0 0 5 0 27 19 External nWAIT WRITE Timing Diagram Tacs 0 Tcos 0 4 Toch 0 0 0 0 27 19 Masked ROM Single READ Timing Diagram Tacs 2 5 2 Tacc 8 01 10 11 27 20 Masked ROM Consecutive READ Timing Diagram Tacs 0 Tcos 0 Tacc 3 2 0110 11 sse 27 20 SDRAM Single Burst READ Timing Diagram Trp 2 Trcd 2 2 DWz16bit 27 21 External Bus Request SDRAM Timing Diagram Trp 2 2 2 27 22 SDRAM MRS Timing 27 23 SDRAM Single READ Timing Diagram 1 Trp 2 Trcd 2 27 24 SDRAM Single READ Timing Diagram Il 2 Trcd 2 3 27 25 SDRAM Auto Refresh Timing Diagram Trp 2 4 27 26 SDRAM Page Hit Miss READ Timing Diagram Trp 2 2 Tcl 2 27 27 SDRAM Self Refresh Timing Dia
271. al 10 bit conversion time is as follows A D converter freq 50MHz 49 1 1MHz Conversion time 1 1MHz 5cycles 1 200KHz 5 us NOTE This A D converter was designed to operate at maximum 2 5MHz clock so the conversion rate can go up to 500 KSPS Touch Screen Interface Mode 1 Normal Conversion Mode Single Conversion Mode is the most likely used for General Purpose ADC Conversion This mode can be initialized by setting the ADCCON ADC Control Register and completed with a read and a write to the ADCDATO ADC Data Register 0 2 Separate X Y position conversion Mode Touch Screen Controller can be operated by one of two Conversion Modes Separate X Y Position Conversion Mode is operated as the following way X Position Mode writes X Position Conversion Data to ADCDATO so Touch Screen Interface generates the Interrupt source to Interrupt Controller Y Position Mode writes Y Position Conversion Data to ADCDAT1 so Touch Screen Interface generates the Interrupt source to Interrupt Controller 3 Auto Sequential X Y Position Conversion Mode Auto Sequential X Y Position Conversion Mode is operated as the following Touch Screen Controller sequentially converts X Position and Y Position that is touched After Touch controller writes X measurement data to ADCDATO and writes Y measurement data to ADCDAT1 Touch Screen Interface is generating Interrupt Source to Interrupt Controller in Auto Position Conversion Mode 4 Waiti
272. alid data received over the RXDn port 0 Empty 1 The buffer register has a received data In Non FIFO mode Interrupt or DMA is requested If the UART uses the FIFO users should check Rx FIFO Count bits and Rx FIFO Full bit in the UFSTAT register instead of this bit Transmit buffer empty Set to 1 automatically when transmit buffer register is empty 0 buffer register is not empty 1 Empty In Non FIFO mode Interrupt or DMA is requested In FIFO mode Interrupt or DMA is requested when Tx FIFO Trigger Level is set to 00 Empty If the UART uses the FIFO users should check Tx FIFO Count bits and Tx FIFO Full bit in the UFSTAT register instead of this bit 11 16 ELECTRONICS 53 2440 RISC MICROPROCESSOR UART UART ERROR STATUS REGISTER There are three UART Rx error status registers including UERSTATO UERSTAT1 and UERSTAT2 in the UART block ues UART chamelO x eror saus oo ues UART chanel 1 Fxemwrsauerpser 90 uemsrrs ooo UART 2 siaus register o0 Break Detect 3 Set to 1 automatically to indicate that a break signal has been received 0 No break receive 1 Break receive Interrupt is requested Parity Error 1 Set to 1 automatically whenever a parity error occurs during receive operation 0 No parity error during receive 1 Parity error Interrupt is requested Overrun Error Set to 1 automatically whenever an
273. an be used in read erase program NAND flash memory Interface 8 16 bit NAND flash memory interface bus Hardware ECC generation detection and indication Software correction SFR I F Support Little Endian Mode Byte half word word access to Data and ECC Data register and Word access to other registers SteppingStone I F Support Little Big Endian Byte half word word access The Steppingstone 4 KB internal SRAM buffer can be used for another purpose after NAND flash booting ELECTRONICS 6 1 NAND FLASH CONTROLLER 53 2440 RISC MICROPROCESSOR BLOCK DIAGRAM nFCE CLE ALE NAND FLASH nFRE Interface nFWE Control amp State Machine 4 AHB 1 00 1 015 Slave I F Stepping Stone Stepping Stone Controller 4KB SRAM Figure 6 1 NAND Flash Controller Block Diagram BOOT LOADER FUNCTION REGISTERS AUTO BOOT CORE ACCESS Boot Code Stepping Stone 4KB Buffer NAND FLASH NAND FLASH USER ACCESS Controller Memory Special Function Registers Figure 6 2 NAND Flash Controller Boot Loader Block Diagram During reset Nand flash controller will get information about the connected NAND flash through Pin status NCON Adv flash GPG13 Page size GPG14 Address cycle GPG15 Bus width refer to PIN CONFIGURATION After power on or system reset is occurred the NAND Flash controller load automatically the 4 KBytes boot loader codes After loading the boot loader codes the boot loa
274. ansfers can be made at up to 100 Kbit s in Standard mode or up to 400 Kbit s in Fast mode 115 Interface e 1 ch 5 for audio interface with DMA based operation Serial 8 16 bit per channel data transfers 128 Bytes 64 64 Byte FIFO for Tx Rx e Supports 15 format and MSB justified data format AC97 Audio CODEC Interface e Support 16 bit samples 1 ch stereo inputs 1 ch stereo PCM outputs 1 ch MIC input USB Host e 2 port USB Host e Complies with Rev 1 0 e Compatible with USB Specification version 1 1 USB Device 1 port USB Device 5 Endpoints for USB Device e Compatible with USB Specification version 1 1 SD Host Interface Normal Interrupt and data transfer mode byte halfword word transfer 53 2440 RISC MICROPROCESSOR burst4 access support only word transfer Compatible with SD Memory Card Protocol version 1 0 e Compatible with SDIO Card Protocol version 1 0 64 Bytes FIFO for Tx Rx e Compatible with Multimedia Card Protocol version 2 11 SPI Interface e Compatible with 2 ch Serial Peripheral Interface Protocol version 2 11 e 2x8 bits Shift register for Tx Rx DMA based or interrupt based operation Camera Interface e ITU R BT 601 656 8 bit mode support DZI Digital Zoom In capability e Programmable polarity of video sync signals Max 4096 x 4096 pixels input support 2048 2048 pixel input supp
275. ant En eee ee Et bee mI Ee cotes ita 4 43 viii 53 2440 MICROCONTROLLER Table of Contents Continued Chapter 5 Memory Controller 5 1 FUNCTION Description coii u 5 4 Banko Bus Width 5 4 Memory SROM SDRAM Address Pin 5 4 Sdram Bank Address Pin Connection 5 5 AWAIT MEO o rupem 5 6 NXBREQ nNXBACK Pin nhe n 5 7 Programmable Access a eee ei eee tend 5 12 Bus Width amp Wait Control Register 5 14 Bank Control Register Bankconn NGCS0 NGC9S5 eene nnne 5 16 Bank Control Register Bankconn NGCS6 NGCS7 5 17 Retresh Control Register 5 18 Register 5 19 Sdram Mode Register Set Register 5 20 Chapter 6 Flash Contorller OVEIMIOW 5 6 1 POGUES 21424825 6 1 BloCk DIAGU DLE 6 2 Boot
276. are SPSR and SPSR all psrf CPSR flg or SPSR flg lt expression gt Where this is used the assembler will attempt to generate a shifted immediate 8 bit field to match the expression If this is impossible it will give an error EXAMPLES In User mode the instructions behave as follows MSR CPSR all Rm CPSR 831 28 lt Rm 31 28 MSR CPSR flg Rm CPSR 831 28 lt Rm 31 28 MSR CPSR_flg 0xA0000000 CPSR 31 28 lt set N C clear Z V MRS Rd CPSR Rd 81 0 lt CPSR 31 0 In privileged modes the instructions behave as follows MSR CPSR all Rm CPSR 31 0 lt Rm 31 0 MSR CPSR flg Rm CPSR 31 28 lt Rm 31 28 MSR CPSR_flg 0x50000000 CPSR 31 28 lt 0x5 set Z V clear N C MSR SPSR all Rm SPSR 31 0 Rm 31 0 MSR SPSR flg Rm SPSR lt gt 31 28 lt Rm 31 28 MSR SPSH flg 0xC0000000 SPSR_ lt mode gt 31 28 lt OxC set N Z clear MRS Rd SPSR Rd 81 0 lt SPSR mode 31 0 ELECTRONICS 3 21 ARM INSTRUCTION SET 53 2440 RISC MICROPROCESSOR MULTIPLY AND MULTIPLY ACCUMULATE MUL MLA The instruction is only executed if the condition is true The various conditions are defined in Table 3 2 The instruction encoding is shown in Figure 3 12 The multiply and multiply accumulate instructions use an 8 bit Booth s algorithm to perform integer multiplication 28 27 22 21 20 19 16 15 12 11 15 12 11 8 3 0 Registers
277. are should be taken to use the malloc function LCDBASEU 20 0 For dual scan LCD These bits indicate A 21 1 of the start address of 0x000000 the upper address counter which is for the upper frame memory of dual scan LCD or the frame memory of single scan LCD For single scan LCD These bits indicate A 21 1 of the start address of the LCD frame buffer FRAME Buffer Start Address 2 Register LCDSADDR2 0X4D000018 STN TFT Frame buffer start address 2 register 0x00000000 20 0 LCDBASEL For dual scan LCD These bits indicate A 21 1 of the start address of 0x0000 the lower address counter which is used for the lower frame memory of dual scan LCD For single scan LCD These bits indicate A 21 1 of the end address of the LCD frame buffer LCDBASEL the frame end address gt gt 1 1 LCDBASEU PAGEWIDTH OFFSIZE x LINEVAL 1 NOTE Users change the LCDBASEU and LCDBASEL values for scrolling while the LCD controller is turned on But users must not change the value of the LCDBASEU and LCDBASEL registers at the end of FRAME by referring to the LINECNT field in LCDCON1 register for the LCD FIFO fetches the next frame data prior to the change in the frame So if you change the frame the pre fetched FIFO data will be obsolete and LCD controller will display an incorrect screen To check the LINECNT interrupts should be masked If any interrupt is executed just after reading LINECNT the read LINECNT value may be
278. are zero and bits 31 2 contain the PC In THUMB state bit 0 is zero and bits 31 1 contain the PC Register 16 This register is the CPSR Current Program Status Register This contains condition code flags and the current mode bits FIQ mode has seven banked registers mapped to R8 14 R8 fiq R14 In ARM state there many handlers which don t require saving registers User IRQ Supervisor Abort and Undefined each have two banked registers mapped to R13 and R14 allowing each of these modes to have a private stack pointer and link registers ELECTRONICS 2 3 PROGRAMMER S MODEL 53 2440 RISC MICROPROCESSOR ARM State General Registers and Program Counter System amp User FIQ Supervisor Undefined 2 ARM State Program Status Registers banked register Figure 2 3 Register Organization in ARM State 2 4 ELECTRONICS 53 2440 RISC MICROPROCESSOR PROGRAMMER S MODEL The THUMB State Register Set The THUMB state register set is a subset of the ARM state set The programmer has direct access to eight general registers R0 R7 as well as the Program Counter PC a stack pointer register SP a link register LR and the CPSR There are banked Stack Pointers Link Registers and Saved Process Status Registers SPSRs for each privileged mode This is shown in Figure 2 4 THUMB State General Registers and Program Counter System amp User FIQ Supervisor Abort IRQ Undefined THUMB State Pr
279. ared by reading SPSTAn 0 Not detect 1 Multi master error detect Transfer Ready This bit indicates that SPTDATn or SPRDATn is ready to transmit Flag REDY or receive This flag is automatically cleared by writing data to This flag is set if the is written or SPRDATn is read while a transfer is in progress and cleared by reading the SPSTAn 0 Not ready 1 Data Tx Rx ready FLECTRONICE 22 7 SPI S3C2440A RISC MICROPROCESSOR SPI PIN CONTROL REGISTER When the SPI system is enabled the direction of pins except nSS pin is controlled by MSTR bit of SPCONn register The direction of nSS pin is always input When the SPI is a master nSS pin is used to check multi master error provided that the SPPIN s ENMUL bit is active and another GPIO should be used to select a slave If the SPI is configured as a slave the nSS pin is used to select SPI as a slave by one master SPPINO 0x59000008 SPI channel 0 pin control register SPPIN1 0x59000028 SPI channel 1 pin control register z 3 Multi master 2 The nSS pin is used as an input to detect multi master error when error detect the SPI system is a master enable ENMUL 0 Disable general purpose 1 Multi master error detect enable Master out keep Determine MOSI drive or release when 1byte transmit is completed KEEP master only 0 Release 1 Drive the previous level m jew The SPIMISO MISO and SPIMOSI MOS
280. as 1 and have to clear theMainECCLock NFCONT 5 bit to Unlock before read or write data MainECCLock NFCONT 5 and SpareECCLock NFCONTT 6 control whether ECC code is generated or not Whenever data is read or written the ECC module generates ECC parity code on register NFMECCO After you completely read or write one page not include spare area data Set the MainECCLock bit to 1 Lock ECC Parity code is locked and the value of the ECC status register will not be changed To generate spare area ECC parity code Clear as 0 Unlock SpareECCLock NFCONT 6 bit Whenever data is read or written the spare area ECC module generates ECC parity code on register NFSECC After you completely read or write spare area Set the SpareECCLock bit to 1 Lock ECC Parity code is locked and the value of the ECC status register will not be changed Once completed you can use these values to record to the spare area or check the bit error NOTE NFSECCD is for ECC in the spare area Usually the user will write the ECC value of main data area to Spare area which value will be the same as NFMECCO 1 and which is generated from the main data area ELECTRONICS 53 2440 RISC MICROPROCESSOR NAND FLASH CONTROLLER NAND FLASH MEMORY MAPPING FFFF Not Used Not Used 0x6000 0000 SFR Area SFR Area 0x4800 0000 0x4000 OFFF TR BootSRAM 4KB 054000 0000 SDRAM SDRAM BANK7 nGCS7 BANK7 nGCS7 0x3800_000
281. as in the 16 gray levels ELECTRONICS 15 5 LCD CONTROLLER S3C2440A RISC MICROPROCESSOR 256 Level Color Mode Operation The S3C2440A LCD controller can support an 8 bit per pixel 256 color display mode The color display mode can generate 256 levels of color using the dithering algorithm and FRC The 8 bit per pixel are encoded into 3 bits for red 3 bits for green and 2 bits for blue The color display mode uses separate lookup tables for red green and blue Each lookup table uses the REDVAL 31 0 of REDLUT register GREENVAL 31 0 of GREENLUT register and BLUEVAL 15 0 of BLUELUT register as the programmable lookup table entries Similar to the gray level display 8 group or field of 4 bits in the REDLUR register i e REDVAL 31 28 REDLUT 27 24 REDLUT 23 20 REDLUT 19 16 REDLUT 15 12 REDLUT 11 8 REDLUT 7 4 REDLUT 3 0 are assigned to each red level The possible combination of 4 bits each field is 16 and each red level should be assigned to one level among possible 16 cases In other words the user can select the suitable red level by using this type of lookup table For green color the GREENVAL 31 0 of the GREENLUT register is assigned as the lookup table as was done in the case of red color Similarly the BLUEVAL 15 0 of the BLUELUT register is also assigned as a lookup table For blue color 2 bits are allocated for 4 blue levels different from the 8 red or green levels 4096 Level Color Mode Operation The
282. asc 4 12 Format 5 Hi Register Operations Branch Exchange 4 13 2 PT e CE 4 13 8 c X 4 14 BX T eeeee dinate 4 14 Emm 4 15 Using RTO AS an Operand eee pe eee pisc a 4 15 Format 6 PC Relative Load iiic 4 16 trae tren oc m seats 4 16 ifo 0 Em 4 17 n 4 17 Format 7 Load Store With Register nnne 4 18 eo te a 4 19 TIMES deine xe 4 19 Cer 4 19 Format 8 Load Store Sign Extended Byte Halfword 4 20 BEE EE E EE E R 4 20 HEU 4 21 Cher NM 4 21 Format 9 Load Store With Immediate Offset a 4 22 ete ETE 4 23 ce 4 28 4 23 Format 160 Eoad Store u u R
283. asks in parallel COPROCESSOR INSTRUCTIONS The S3C2440A unlike some other ARM based processors does not have an external coprocessor interface It does not have a on chip coprocessor also So then all coprocessor instructions will cause the undefined instruction trap to be taken on the S3C2440A These coprocessor instructions can be emulated by the undefined trap handler Even though external coprocessor can not be connected to the 3 2440 the coprocessor instructions are still described here in full for completeness Remember that any external coprocessor described in this section is a software emulation 31 28 27 24 23 20 19 16 15 12 11 8 7 543 om PL 3 0 Coprocessor operand register 7 5 Coprocessor information 11 8 Coprocessor number 15 12 Coprocessor destination register 19 16 Coprocessor operand register 23 20 Coprocessor operation code 31 28 Condition Field Figure 3 25 Coprocessor Data Operation Instruction Only bit 4 and bits 24 to 31 The coprocessor fields are significant to ARM920T The remaining bits are used by coprocessors The above field names are used by convention and particular coprocessors may redefine the use of all fields except CP as appropriate The CP field is used to contain an identifying number in the range 0 to 15 for each coprocessor and a coprocessor will ignore any instruction which does not contain its number in the CP field The conv
284. ate change to address in a register in the range 0 7 BX Hs BX Hs Perform branch plus optional state change to address in a register in the range 8 15 INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 4 6 The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction THE BX INSTRUCTION BX performs a Branch to a routine whose start address is specified in a Lo or Hi register Bit 0 of the address determines the processor state on entry to the routine Bit0 0 Causes the processor to enter ARM state Bit 0 1 Causes the processor to enter THUMB state NOTE The action of H1 1 for this instruction is undefined and should not be used 4 14 ELECTRONICS 53 2440 RISC MICROPROCESSOR EXAMPLES Hi Register Operations ADD PC R5 CMP R4 R12 MOV R15 R14 Branch and Exchange ADR R1 0utof THUMB MOV R11 R1 BX R11 ALIGN CODE32 outof THUMB USING R15 AS AN OPERAND THUMB INSTRUCTION SET PC PC R5 but don t set the condition codes Set the condition codes on the result of R4 R12 Move R14 LR into R15 PC but don t set the condition codes eg return from subroutine Switch from THUMB to ARM state Load address of outofTHUMB into R1 Transfer the contents of R11 into the PC Bit 0 of R11 determines whether ARM or state is entered ie In this case the state is ARM Now pro
285. ate the polarity of the row and column voltages which are used to turn the pixels on and off because the LCD plasma tends to deteriorate whenever subjected to a DC voltage It can be configured to toggle on every frame or to toggle every programmable number of VLINE signals Figure 15 4 shows the timing requirements for the LCD driver interface 15 14 ELECTROUNICS 53 2440 RISC MICROPROCESSOR LCD CONTROLLER Full Frame Timing MMODE 0 INT FrSyn _ C EU UR l VFRAME VM i VLINE LINE1 INESLINEG Full Frame Timing MMODE 1 MVAL 0x2 1 INT FrSyn VFRAME 1 VLINE LINE1 LINE3LINE3LINE4 I I I I I I INT_FrSyn eee First Line Timing I _ decreases amp Display the 1st line VLINE LINECNT Figure 15 4 8 bit Single Scan Display Type STN LCD Timing ELECTRONICS 15 15 LCD CONTROLLER S3C2440A RISC MICROPROCESSOR TFT LCD CONTROLLER OPERATION The TIMEGEN generates the control signals for LCD driver such as VSYNC HSYNC VCLK VDEN and LEND signal These control signals are highly related with the configurations on the LCDCON1 2 3 4 5 registers in the REGBANK Base on these programmable configurations on the LCD control registers in the REGBANK the TIMEGEN can generate the programmable control signals suitable for the support of many different types of LCD drivers The VS
286. ath and C path Codec path are separated from each other on the AHB bus In view of the system bus both the paths are independent The P path stores the RGB image data into memory for PIP The C path stores the YCbCr 4 2 0 or 4 2 2 image data into memory for Codec as MPEG 4 H 263 etc These two master paths support the variable applications like DSC Digital Steel Camera MPEG 4 video conference video recording etc For example P path image can be used as preview image and C path image can be used as JPEG image in DSC application Register setting can separately disable to P path or C path Frame Memory SDRAM PIP RGB External Camera Processor ITU format Codec image YCbCr 4 2 0 or YCbCr 4 2 2 Frame Memory SDRAM Window cut PIP RGB External Camera Processor ITU format Codec image YCbCr 4 2 0 or YCbCr 4 2 2 Figure 23 4 Two DMA Paths CLOCK DOMAIN CAMIF has two clock domains One is the system bus clock which is HCLK The other is the pixel clock which is 1 The system clock must be faster than pixel clock Figure 23 5 shows CAMCLKOUT must be divided from the fixed frequency like USB PLL clock If external clock oscillator is used CAMCLKOUT should be floated Internal scaler clock is system clock It is not necessary for two clock domains to synchronize each other Other signals such as CAMPCLK should be similarly connected to the Schmitt triggered level shifter ELECTRONICS 23 5 53 2440
287. available 0 Service available 0 Service available 0 Service available 0 Service available 0 Service available 0 Service available 0 Service available 0 Service available 0 Service available INT TIMER4 14 INT 13 INT TIMER2 12 INT TIMER1 11 0 Service available INT TIMERO 10 0 Service available INT WDT AC97 0 Service available 0 Service available 0 Service available B 0 Service available 0 Service available 0 Service available 0 Service available 0 Service available 0 Service available 0 Service available 0 Service available ENO 0 Service available 14 12 1 Masked 1 Masked 1 Masked 1 Masked 1 Masked 1 Masked 1 Masked 1 Masked 1 Masked 1 Masked 1 Masked 1 Masked 1 Masked 1 Masked 1 Masked 1 Masked 1 Masked 1 Masked 1 Masked NE NN 0 Service available 1 Masked p 1 Masked 1 Masked 1 Masked 1 Masked 1 Masked 1 Masked 1 Masked 1 Masked 1 Masked 1 Masked 1 Masked 1 Masked EN ELECTRONICS 53 2440 RISC MICROPROCESSOR INTERRUPT CONTROLLER PRIORITY REGISTER PRIORITY PRIORITY 0x4A00000C IRQ priority control register ARB_SEL6 20 19 Arbiter 6 group priority order set 00 REQ 0 1 2 3 4 5 01 REQ 0 2 3 4 1 5 10 REQ 0 3 4 1 2 5 11 REQ 0 4 1 2 3 5 ARB_SEL5 18 17 Arbiter 5 gro
288. ay levels In case of 256 color mode 3 bits are allocated for red 3 bits for green and 2 bits for blue The 256 colors mean that the colors are formed from the combination of 8 red 8 green and 4 blue levels 8x8x4 256 In the color mode the lookup table can be used for suitable selections Eight red levels can be selected among 16 possible red levels 8 green levels among 16 green levels and 4 blue levels among 16 blue levels In case of 4096 color mode there is no selection as in the 256 color mode Gray Mode Operation The S3C2440A LCD controller supports two gray modes 2 bit per pixel gray 4 level gray scale and 4 bit per pixel gray 16 level gray scale The 2 bit per pixel gray mode uses a lookup table BLUELUT which allows selection on 4 gray levels among 16 possible gray levels The 2 bit per pixel gray lookup table uses the BULEVAL 15 0 in Blue Lookup Table BLUELUT register as same as blue lookup table in color mode The gray level 0 will be denoted by BLUEVAL 3 0 value If BLUEVAL 3 0 is 9 level 0 will be represented by gray level 9 among 16 gray levels If BLUEVAL 3 0 is 15 level 0 will be represented by gray level 15 among 16 gray levels and so on Following the same method as above level 1 will also be denoted by BLUEVAL 7 4 the level 2 by BLUEVAL 11 8 and the level 3 by BLUEVAL 15 12 These four groups among BLUEVAL 15 0 will represent level 0 level 1 level 2 and level 3 In 16 gray levels there is no selection
289. below Little Endian Configuration A byte load LDRB expects the data on data bus inputs 7 through 0 if the supplied address is on a word boundary on data bus inputs 15 through 8 if it is a word address plus one byte and so on The selected byte is placed in the bottom 8 bits of the destination register and the remaining bits of the register are filled with zeros Please see Figure 2 2 A byte store STRB repeats the bottom 8 bits of the source register four times across data bus outputs 31 through 0 The external memory system should activate the appropriate byte subsystem to store the data A word load LDR will normally use a word aligned address However an address offset from a word boundary will cause the data to be rotated into the register so that the addressed byte occupies bits 0 to 7 This means that half words accessed at offsets 0 and 2 from the word boundary will be correctly loaded into bits O through 15 of the register Two shift operations are then required to clear or to sign extend the upper 16 bits A word store STR should generate a word aligned address The word presented to the data bus is not affected if the address is not word aligned That is bit 31 of the register being stored always appears on data bus output 31 ELECTRONICS 3 29 ARM INSTRUCTION SET 53 2440 RISC MICROPROCESSOR memory register LDR from word aligned address memory register 3 2 1 LDR from address offset by 2
290. blem is removed Independent power pin RTCVDD Supports millisecond tick time interrupt for RTOS kernel time tick ELECTRONICS 17 1 REAL TIME CLOCK S3C2440A RISC MICROPROCESSOR REAL TIME CLOCK OPERATION TIME TICK Time Tick Generator RTCRST 215 Clock Divider Reset Register Leap Year Generator XTIrtc XTOrtc Control Register Alarm Generator RTCCON RTCALM PMWKUP INT_RTC Figure 17 1 Real Time Clock Block Diagram LEAP YEAR GENERATOR The Leap Year Generator can determine the last date of each month out of 28 29 30 or 31 based on data from BCDDATE and BCDYEAR This block considers leap year in deciding on the last date An 8 bit counter can only represent 2 BCD digits so it cannot decide whether 00 year the year with its last two digits zeros is a leap year or not For example it cannot discriminate between 1900 and 2000 To solve this problem the RTC block in S3C2440A has hard wired logic to support the leap year in 2000 Note 1900 is not leap year while 2000 is leap year Therefore two digits of 00 in 53 2440 denote 2000 not 1900 READ WRITE REGISTERS Bit 0 of the RTCCON register must be set high in order to write the BCD register in RTC block To display the second minute hour date month and year the CPU should read the data in BCDSEC BCDMIN BCDHOUR BCDDAY BCDDATE BCDMON and BCDYEAR registers respectively in the RTC block However a one second deviation may exist
291. bort occurs during an instruction prefetch Data Abort occurs during a data access If a prefetch abort occurs the prefetched instruction is marked as invalid but the exception will not be taken until the instruction reaches the head of the pipeline If the instruction is not executed the abort doesn t take place because a branch occurs while it is in the pipeline data abort occurs the action taken depends on the instruction type e Single data transfer instructions LDR STR write back modified base registers the Abort handler must be aware of this e The swap instruction SWP is aborted as though it had not been executed Block data transfer instructions LDM STM complete If write back is set the base is updated If the instruction would have overwritten the base with data ie it has the base in the transfer list the overwriting is prevented All register overwriting is prevented after an abort is indicated which means in particular that R15 always the last register to be transferred is preserved in an aborted LDM instruction The abort mechanism allows the implementation of a demand paged virtual memory system In such a system the processor is allowed to generate arbitrary addresses When the data at an address is unavailable the Memory Management Unit MMU signals an abort The abort handler must then work out the cause of the abort make the requested data available and retry the aborted instruction
292. c path will be occurred if codec path is not operating when preview path is operated If you want to use codec path under this case you should stop preview path and reset CAMIF using SwRst bit of CIGCTRL register Then clear overflow of codec path and set special function registers that you want ELECTRONICS 23 9 53 2440 RISC MICROPROCESSOR CAMERA INTERFACE TIMING DIAGRAM FOR LAST IRQ IRQ except LastIRQ is generated before image capturing Last IRQ which means capture end can be set by following timing diagram LastIRQEn is auto cleared and mentioned SFR setting in ISR is for next command So for adequate last IRQ you should follow next sequence between LastIRQEn and ImgCptEn ImgCptEn_CoSc ImgCptEnPrSC It is recommended that ImgCptEn ImgCptEn CoSc ImgCptEnPrSC are set at same time and at last of SFR setting in ISR FrameCnt which is read in ISR means next frame count On following diagram last captured frame count is 1 That is Frame 1 is the last captured frame among frame 0 3 FrameCnt is increased by 1 at IRQ rising ISR region ISR region ISR region ISR region ISR region ISR region ISR region VSYNC mn ImgCptEn cmd H LastIRQEn LH IRQ gt Last FrameCnt 1 1 2 1 3 P 0 0 I Capture X fapture O Figure 23 9 Timing diagram for last IRQ 23 10 ELECTRONICE 53 2440 RISC MICROPROCESSOR CAMERA INTERFACE
293. cally The S3C2440A also supports INVPWREN bit to invert polarity of the PWREN signal This function is available only when LCD panel has its own power on off control port and when port is connected to LCD PWREN pin ENVID LCD PWREN VFRAME STN LCD LCD PWREN UT VSYNC HSYNC VDEN 1 FRAME TFT LCD Figure 15 8 Example of PWREN Function PWREN 1 INVPWREN 0 15 26 ELECTRONICS 53 2440 RISC MICROPROCESSOR LCD CONTROLLER LCD CONTROLLER SPECIAL REGISTERS LCD Control 1 Register LCDCON1 0X4D000000 LCD control 1 register 0x00000000 LINECNT 27 18 Provide the status of the line counter 0000000000 read only Down count from LINEVAL to 0 CLKVAL 17 8 Determine the rates of and CLKVAL 9 0 0000000000 STN VCLK HCLK CLKVAL x 2 CLKVAL 22 VCLK HCLK CLKVAL 1 x2 CLKVAL 20 MMODE 7 Determine the toggle rate of the VM 0 Each Frame 1 The rate defined by the MVAL PNRMODE 6 5 Select the display mode 00 4 bit dual scan display mode STN 01 4 bit single scan display mode STN 10 8 bit single scan display mode STN 11 2 TFT LCD panel BPPMODE 4 1 Select the BPP Bits Per Pixel mode 0000 1 bpp for STN Monochrome mode 0001 2 bpp for STN 4 level gray mode 0010 4 bpp for STN 16 level gray mode 0011 8 bpp for STN color mode 256 color 0100 packed 12 bpp for STN color mode 4096 color 0101 unpacked 12 bpp for STN color mode 4096 color
294. ce controller catches this frame number and loads it into this register automatically R byte FRAME NUM1 REG 0x520001 70 L Frame number lower byte register 0x00 0x52000173 B byte FRAME NUM1 70 w Frame number lower byte value R byte FRAME NUM2 REG 0x52000174 L Frame number higher byte register 0x00 0x52000177 B byte FRAME NUM2 70 w Frame number higher byte value 00 13 10 ELECTRONICS 53 2440 RISC MICROPROCESSOR USB DEVICE INDEX REGISTER INDEX_REG The INDEX register is used to indicate certain endpoint registers effectively The MCU can access the endpoint registers MAXP_REG IN CSR1 REG IN CSR2 REG OUT 5 1 REG OUT CSR2 REG OUT FIFO CNT1 REG and OUT FIFO CNT2 REG for an endpoint inside the core using the INDEX register INDEX REG 0x520001 78 L R W Register index register 0x00 0x5200017B B byte INDEX 7 0 RW n Indicate a certain endpoint 0 MAX PACKET REGISTER MAXP REG MAXP REG 0x52000180 L R W End Point MAX packet register 0x01 0x52000183 B byte Der meu vss 3 0 0000 Reserved 0001 8 Byte 0010 16 Byte 0100 32 Byte 1000 64 Byte For MAXP 8 is recommended For 1 4 64 is recommended And if 64 the dual packet mode will be enabled automatically ELECTRONICS 13 11 USB S3C2440A RISC MICROPROCESSOR END POINT0
295. ce interrupts or exceptions or to access protected resources REGISTERS 9201 has a total of 37 registers 31 general purpose 32 bit registers and six status registers but these cannot all be seen at once The processor state and operating mode decides which registers are available to the programmer The ARM State Register Set In ARM state 16 general registers and one or two status registers are visible at any one time In privileged non User modes mode specific banked registers are switched in Figure 2 3 shows which register is available in each mode the banked registers are marked with a shaded triangle The ARM state register set contains 16 directly accessible registers RO to R15 All of these except R15 are general purpose and may be used to hold either data or address values In addition to these there is a seventeenth register used to store status information Register 14 This register is used as the subroutine link register This receives a copy of R15 when a Branch and Link BL instruction is executed Rest of the time it may be treated as a general purpose register The corresponding banked registers R14 svc R14 irq R14 R14 abt and R14 und are similarly used to hold the return values of R15 when interrupts and exceptions arise or when Branch and Link instructions are executed within interrupt or exception routines Register 15 This register holds the Program Counter PC In ARM state bits 1 0 of R15
296. ceVsize 2 x WinVerOfst Figure 23 12 Scaling Scheme The other control registers of pre scaled like image size pre scale ratio pre scale shift ratio and main scale ratio are defined according to the following equations If SRC Width gt 64 x DST Width Exit 1 Out Of Horizontal Scale Range 7 else if 5 Width gt 32 x DST Width PreHorRatio xx 32 Shift 5 else if 5 Width gt 16 x DST Width PreHorRatio xx 16 Shift 4 else if 5 Width gt 8 x DST Width PreHorRatio xx 8 Shift 3 else if Width gt 4 x 5 Width PreHorRatio xx 4 Shift 2 else if Width gt 2 x 5 Width PreHorRatio xx 2 Shift 1 else PreHorRatio xx 1 H Shift 0 PreDstWidth xx 5 Width PreHorRatio xx MainHorRatio xx 5 Width lt lt 8 5 Width lt lt H Shift 23 20 ELECTRONICE 53 2440 RISC MICROPROCESSOR CAMERA INTERFACE If Height gt 64 x DST Height Exit 1 Out Of Vertical Scale Range else if Height gt 32 x DST Height PreVerRatio xx 32 V Shift 5 else if 5 Height gt 16 x DST Height PreVerRatio xx 16 V Shift 4 else if SRC Height gt 8 x DST Height PreVerRatio xx 8 V Shift 3 else if Height gt 4 x DST Height PreVerRatio 4 V Shift 2 else if 5 Height gt 2 x DST Height PreVerRatio 2 V Shift
297. cessing ARM instructions If R15 is used as an operand the value will be the address of the instruction 4 with bit O cleared Executing a BX PC in THUMB state from a non word aligned address will result in unpredictable execution ELEGTRONIGS THUMB INSTRUCTION SET 53 2440 RISC MICROPROCESSOR FORMAT 6 PC RELATIVE LOAD 15 14 13 7 0 12 11 10 8 m wes 7 0 Immediate Value 10 8 Destination Register Figure 4 7 Format 6 OPERATION This instruction loads a word from an address specified as a 10 bit immediate offset from the PC The THUMB assembler syntax is shown below Table 4 7 Summary of PC Relative Load Instruction LDR Rd PC lmm LDR Rd R15 Add unsigned offset 255 words 1020 bytes in Imm to the current value of the PC Load the word from the resulting address into Rd NOTE The value specified by 1 is a full 10 bit address but must always be word aligned ie with bits 1 0 set to 0 since the assembler places lmm 2 in field Word 8 The value of the PC will be 4 bytes greater than the address of this instruction but bit 1 of the PC is forced to 0 to ensure it is word aligned 4 16 ELECTRONICS 53 2440 RISC MICROPROCESSOR THUMB INSTRUCTION SET INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction EX
298. ch 4 34 4 34 Inistructiom Cycle 4 35 2 bote Deu te mapa tere Ed teo ito feu etae 4 35 Format 17 c ern rerba 4 36 ecu 4 36 Instruction Cycle ee e tere etel cte tede tdt des 4 36 erba eee tod tee des dutem 4 36 Format 18 Unconditional Brane iceren ee aa S 4 37 4 37 EXAMPpleS 4 37 Format 19 Tong branch with 4 38 Sau 4 38 INSTPUCTION a hy and sive 4 39 ecc ti ten 4 39 Instr ction Set Examples ute eee reet reo see tube ctae re cie ee ta ura 4 40 Multiplication by A Constant Using Shifts and Adds a 4 40 General Purpose Signed hen nnne enne enne nnns 4 41 Division by Const
299. character condition mnemonic See Table 3 2 Set condition codes if present Rd Rm Rs and Rn Expressions evaluating to a register number other than R15 EXAMPLES MUL R1 R2 R3 1 2 MLAEQS R1 R2 R3 R4 Conditionally R1 R2 R3 R4 Setting condition codes 3 24 ELECTRONICS 53 2440 RISC MICROPROCESSOR ARM INSTRUCTION SET MULTIPLY LONG AND MULTIPLY ACCUMULATE LONG MULL MLAL The instruction is only executed if the condition is true The various conditions are defined in Table 3 2 The instruction encoding is shown in Figure 3 13 The multiply long instructions perform integer multiplication on two 32 bit operands and produce 64 bit results Signed and unsigned multiplication each with optional accumulate give rise to four variations 28 27 23 22 21 20 19 16 15 12 11 sas 88 11 8 3 0 Operand Registers 19 16 15 12 Source Destination Registers 20 Set Condition Code 0 Do not alter condition codes 1 Set condition codes 21 Accumulate 0 Multiply only 1 Multiply and accumulate 22 Unsigned 0 Unsigned 1 Signed 31 28 Condition Field Figure 3 13 Multiply Long Instructions The multiply forms UMULL and SMULL take two 32 bit numbers and multiply them to produce a 64 bit result of the form RdHi RdLo Rm Rs The lower 32 bits of the 64 bit result are written to RdLo the upper 32 bits of the result are written to RdHi The multiply accumulate forms
300. ck and division factor is 1 NOTES 1 IISPSR register is accessible for each byte halfword and word unit using STRB STRH STR and LDRB LDRH LDR instructions or char short int int type pointer in Little Big endian mode 2 L HW W Little HalfWord Word Bi HW W Big HalfWord Word ELECTRONICS 21 7 IIS BUS INTERFACE 53 2440 RISC MICROPROCESSOR 1 CONTROL IISFCON REGISTER 0x5500000C Li HW Bi W R W IIS FIFO interface register 0x0 0x5500000E Bi HW Transmit FIFO access mode select 15 0 Normal 1 Receive FIFO access mode select 14 0 Normal 1 Transmit FIFO 13 0 Disable 1 Enable Receive FIFO i2 0 Disable 1 Enable Transmit FIFO data count 11 6 Data count value 0 32 000000 Read only Receive FIFO data count 5 0 Data count value 0 32 000000 Read only NOTES 1 The IISFCON register is accessible for each halfword and word unit using STRH STR and LDRH LDR instructions or short int int type pointer in Little Big endian mode 2 Li HW W Little HalfWord Word Bi HW W Big HalfWord Word IIS FIFO IISFIFO REGISTER IIS bus interface contains two 64 byte FIFO for the transmit and receive mode Each FIFO has 16 width and 32 depth form which allows the FIFO to handles data for each halfword unit regardless of valid data size Transmit and receive FIFO access is performed through FIFO entry the address of FENTRY is 0x5
301. ck of EINT16 configured by OM 0 PCLK 1 EXTCLK OSC_CLK EINTFLTiG 60 Fitering width of EINT16 FLTCLK23 81 Filter clock of EINT23 configured by OM 0 PCLK 1 EXTCLK OSC_CLK EINTFLT23 80 24 Filtering width of EINT23 FLTCLK22 23 Filter clock of EINT22 configured by OM 0 PCLK 1 EXTCLK OSC_CLK EINTFLT22 22 16 Filtering width of EINT22 21 15 Filter clock of EINT21 configured OM 0 PCLK 1 EXTCLK OSC_CLK EINTFLT21 14 8 Filtering width of EINT21 FLTCLK20 7 Filter clock of EINT20 configured by 0 PCLK 1 EXTCLK OSC_CLK EINTFLT20 60 Filtering width of EINT20 ELECTRONICS 9 31 PORTS 53 2440 RISC MICROPROCESSOR EINTMASK External Interrupt Mask Register EINTMASK 0x560000a4 External interrupt mask register Ewa eit O O 0 enable interrupt 1 masked 0 enable interrupt 1 masked 0 enable interrupt 1 masked 0 enable interrupt 1 masked 0 enable interrupt 1 masked 0 enable interrupt 1 masked 0 enable interrupt 1 masked 0 enable interrupt 1 masked 0 enable interrupt 1 masked 0 enable interrupt 1 masked 0 enable interrupt 1 masked 0 enable interrupt 1 masked 0 enable interrupt 1 masked 0 enable interrupt 1 masked M 0 enable interrupt 12 masked EN8 B 0 enable interrupt 12 masked 0 enable interrupt 12 masked 0 enable interrupt 12 masked 0 enable interrupt 12 mas
302. ck tap to be maximal length i e 2 32 1 cycles before repetition so this example uses a 33 bit register with taps at bits 33 and 20 The basic algorithm is newbit bit 33 eor bit 20 shift left the 33 bit number and put in newbit at the bottom this operation is performed for all the newbits needed i e 32 bits The entire operation can be done in 5 S cycles Enter with seed in Ra 32 bits Rb 1 bit in Rb Isb uses Rc TST Rb Rb LSR4H Top bit into carry MOVS Rc Ra RRX 33 bit rotate right ADC Rb Rb Rb Carry into Isb of Rb EOR Rc Rc Ra LSL 12 involved EOR Ra Rc Rc LSR 20 similarly involved new seed in Ra Rb as before MULTIPLICATION BY CONSTANT USING THE BARREL SHIFTER Multiplication by 2 1 2 4 8 16 32 MOV Ra Rb LSL n Multiplication by 2 1 3 5 9 17 ADD Ra Ra Ra LSL n Multiplication by 2 1 3 7 15 RSB Ra Ra Ra LSL n ELECTRONICS 3 61 ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR Multiplication by 6 ADD Ra Ra Ra LSL 1 Multiply by 3 MOV Ra Ra LSL 1 and then by 2 Multiply by 10 and add in extra number ADD Ra Ra Ra LSL 2 Multiply by 5 ADD Ra Rc Ra LSL 1 Multiply by 2 and add in next digit General recursive method for Rb C a constant 1 If C even say C 2 n D D odd D 1 MOV Rb Ra LSL sin 0 lt gt 1 Rb Ra D MOV Rb Rb LSL n 2 If C MOD 4 1 say C 24n D 1 D odd n gt 1 D 1 ADD Rb Ra Ra LSL sin lt gt 1 Rb R
303. cks 100 6 clocks 101 8 clocks 110 10 clocks 111 14 clocks Tcoh 7 6 Chip selection hold time after nOE 00 0 clock 01 1 clock 10 2 clocks 11 4 clocks Tcah 5 4 Address hold time after nGCSn 00 0 clock 01 clock 10 2clocks 11 4 clocks Tacp 3 2 mode access cycle Page mode 00 2 clocks 01 3 clocks 10 4 clocks 11 6 clocks 1 0 Page mode configuration 00 normal 1 data 01 4 consecutive accesses 10 8 consecutive accesses 11 16 consecutive accesses Memory Type SDRAM MTz11 4 bit Trcd 3 2 RAS to CAS delay 00 2clocks 01 3 clocks 10 4 clocks SCAN 1 0 Column address number 00 8 bit 01 9 bit 10 10 bit ELECTRONICS 5 17 MEMORY CONTROLLER S3C2440A RISC MICROPROCESSOR REFRESH CONTROL REGISTER REFRESH 0x48000024 SDRAM refresh control register 0 0000 23 SDRAM Refresh Enable 1 0 Disable 1 Enable self or CBR auto refresh TREFMD 22 SDRAM Refresh Mode 0 CBR Auto Refresh 1 Self Refresh In self refresh time the SDRAM control signals are driven to the appropriate level Trp 21 20 SDRAM RAS pre charge Time 00 2 clocks 01 3 clocks 10 4 clocks 11 Not support Tsrc 19 18 SDRAM Semi Row cycle time 00 4 clocks 01 25clocks 10 6 clocks 11 7 clocks SDRAM Row cycle time Trc Tsrc Trp If Trp 3clocks amp Tsrc 7clocks 3 7 10clocks 1744 sua ism soo Refresh Counter SDRAM refresh count value Refer to chapter 6
304. clock is not supplied to the internal blocks in the S3C2440A Figure 7 5 shows the timing diagram u PMS setting PLL Lock time FCLK It changes to new clock after automatic lock time Figure 7 5 Changing Slow Clock by Setting PMS Value USB Clock Control USB host interface and USB device interface needs 48Mhz clock In the S3C2440A the USB dedicated PLL UPLL generates 48Mhz for USB UCLK does not fed until the PLL UPLL is configured After reset XTIpll or EXTCLK After UPLL configuration L During PLL lock time On 48MHz After PLL lock time UPLL is turned off by CLKSLOW register or EXTCLK UPLL is turned on by CLKSLOW register 48MHz ELECTRONICS 7 7 CLOCK amp POWER MANAGEMENT 53 2440 RISC MICROPROCESSOR FCLK HCLK and PCLK is used by ARM920T HCLK is used for AHB bus which is used by the ARM920T the memory controller the interrupt controller the LCD controller the DMA and USB host block PCLK is used for bus which is used by the peripherals such as WDT IIS 12 PWM timer MMC interface ADC UART GPIO RTC and SPI The S3C2440A supports selection of Dividing Ratio between and PCLK This ratio is determined by HDIVN and PDIVN of CLKDIVN control register HDIVN PDIVN HALF FCLK HCLK PCLK Divide Ratio HCLK4 HALF FCLK FCLK FCLK Default o 1 1 rax roaka a rax rax roe
305. comro intial destination conrad 040002 R osoo 2 oem 2 curent destinan oeoo RW oma 2 maskwigger osmccs YMA tal source comro DD ome nia destination postos ____ destination conrad cos ____ oo ostas a _ esaeas ox4B000008 oem osoo OMA curent destinan Fw maskwigger 1 28 ELECTRONICS 53 2440 RISC MICROPROCESSOR PRODUCT OVERVIEW Table 1 4 S3C2440A Special Registers Sheet 4 of 14 Continued 2 Name B Endian L Endian Write 0400004 ems tk cer conor ommon women S canera cock oubxomc 1
306. control register SPI Mode Select 6 5 Determine how SPTDAT is read written SMOD 00 polling mode 01 interrupt mode 10 mode 11 reserved SCK Enable Determine whether you want SCK enabled or not master only ENSCK 0 disable 1 enable 4 Master Slave 3 Determine the desired mode master slave Select MSTR 0 slave 1 master Note In slave mode there should be set up time for master to initiate Tx Rx Clock Polarity 2 Determine an active high or active low clock Select CPOL LEE 0 active high 1 active low Phase 1 Select one of the two fundamentally different transfer format Select CPHA EN 0 format A 1 format B EN Tx Auto Garbage Decide whether the receiving data is required or not Data mode c mod 1 Tx auto garbage data mod enable TAGD x auto data mode Note In normal mode if you only want to receive data you should transmit dummy 0xFF data 22 6 FLECTRONICS 53 2440 RISC MICROPROCESSOR SPI SPI STATUS REGISTER SPSTAO 0x59000004 R SPI channel 0 status register SPSTA1 0 59000024 SPI channel 1 status register um 2 1 Data Collision Error Flag DCOL 0 Not detect 1 Collision error detect Multi Master This flag is set if the nSS signal goes to active low while the SPI is Error Flag configured as a master and SPPINn s ENMUL bit is multi master MULF error detect mode MULF is cle
307. controller Bus Architecture AMBA The S3C2440A offers outstanding features with its CPU core a 16 32 bit ARM920T RISC processor designed by Advanced RISC Machines Ltd The 920 implements AMBA BUS and Harvard cache architecture with separate 16KB instruction and 16KB data caches each with an 8 word line length By providing a complete set of common system peripherals the S3C2440A minimizes overall system costs and eliminates the need to configure additional components The integrated on chip functions that are described in this document include e Around 1 2V internal 1 8V 2 5V 3 3V memory 3 3V external I O microprocessor with 16KB 16 D Cache MMU External memory controller SDRAM Control and Chip Select logic LCD controller up to 4K color STN and 256K color TFT with LCD dedicated 4 ch DMA controllers with external request pins e 3 ch UARTS IrDA1 0 64 Byte Tx FIFO and 64 Rx FIFO 2 ch SPIs e bus interface multi master support e IIS Audio CODEC interface e AC 97 CODEC interface SD Host interface version 1 0 amp MMC Protocol version 2 11 compatible 2 ch USB Host controller 1 ch USB Device controller ver 1 1 4 ch PWM timers 1 ch Internal timer Watch Dog Timer e 8 ch 10 bit ADC and Touch screen interface RTC with calendar function e Camera interface 4096 x 4096 pixels input support 2048 x 2048 pixel input support for scal
308. d 11 Reserved FIFO available detect for Tx TFDET This bit indicates that FIFO data is available for transmit when DatMode is data transmit mode If DMA mode is enable sd host requests DMA operation 0 Not detect FIFO full 1 Detect 0 lt FIFO lt 63 FIFO available detect for RFDET Tx FIFO half full 11 This bit sets to 1 whenever Tx FIFO is less than 33byte 0 33 lt Tx FIFO lt 64 1 0 lt Tx FIFO lt 32 Tx FIFO empty 10 This bit sets to 1 whenever Tx FIFO is empty Rx FIFO last data 9 This bit sets to 1 when Rx FIFO occurs to behave last data of ready RFLast all block This flag is cleared by setting to one this bit 0 Not received yet 1 Rx FIFO gets Last data Rx FIFO full RFFull This bit sets to 1 whenever FIFO is full Rx FIFO half full 7 This bit sets to 1 whenever Rx FIFO is more than 31byte 0 0 lt Rx FIFO 31 1 32 lt Rx FIFO lt 64 FIFO count FFCNT 6 0 Number of data byte in FIFO 0000000 NOTE Although the last Rx data size is lager than remained count of FIFO data you could read this data If this event happens you should clear FFfail field and FIFO reset field This bit indicates that FIFO data is available for receive when DatMode is data receive mode If mode is enable sd host requests DMA operation 0 Not detect FIFO empty 1 Detect 1 lt FIFO lt 64 19 12 ELECTRONICS 53 2440 RISC MICROPROCESSOR MMC SD
309. d control of the local bus to another bus master ore current bus cycle cannot be completed SDRAM SRAM mRS ___ row address strobe ___ nscas 0 ____ column address strobe _ 180510 0 SDRAM chip select 0 data 0 SDRAM clock SCKE 0 SDRAM clock enable O 3 0 O byte lower byte enable In case of 16 bit SRAM nWBE 3 0 _ Write byte enable O Commandiachenabie O JjAddesslachenabe O Nandfashchipenabe O Nandfiashreadenbe O jNendfashw teenabe Eu Nand flash configuration If NAND flash controller isn t used it has to be pull up VDDMOP Nand flash ready busy 1 20 ELECTRONICS 53 2440 RISC MICROPROCESSOR PRODUCT OVERVIEW Table 1 3 S3C2440A Signal Descriptions Sheet 2 of 6 Continued Input Descriptions Output LCD Control Unit VD 23 0 O STNTFT SEC TFT LCD data bus LCD PWREN O STN TFT SEC TFT LCD panel power enable control signal VCLK sTNTFT LCD clock signal VFRAME STN LCD frame signal VLINE STN LCD line signal O STN VM alternates the polarity of the row and column voltage VSYNC Oo TFT Vertical synchronous signal HSYNC Horizontal synchronous signal VDEN 20 Data enable signal LEND O Line end signal sv o SEC TFT SEC Samsung Electronics Company TFT LCD panel cont
310. d Mode Determine whether or not to use the Infrared mode 0 Normal mode operation 1 Infrared mode 5 3 Specify the type of parity generation and checking during UART transmit and receive operation 0xx No parity 100 Odd parity 101 Even parity 110 Parity forced checked as 1 111 Parity forced checked as 0 BN 7 Number of Stop 2 Specify how many stop bits are to be used for end of frame signal Bit 0 One stop bit per frame 1 Two stop bit per frame Word Length 1 0 Indicate the number of data bits to be transmitted or received per frame 00 5 bits 01 6 bits 10 7 bits 11 8 bits 11 10 ELECTRONICS 53 2440 RISC MICROPROCESSOR UART CONTROL REGISTER There are three UART control registers including UCONO UCON1 and 2 in the UART block FCLK Divider 15 12 Clock Selection 11 10 ELECTRONICS Divider value when the Uart clock source is selected as FCLK n n is determined by UCONO 15 12 UCON1 15 12 UCON2 1 4 12 0 21151 is FCLK n Clock Enable Disable bit For setting n from 7 to 21 use UCONO 15 12 For setting n from 22 to 36 use UCON1 15 12 For setting n from 37 to 43 use UCON2 14 12 UCON2 15 0 Disable FCLK n clock 1 Enable FCLK n clock In case of UCONO UART clock divider 6 where divider gt 0 1 UCON2 must be zero ex 1 UART clock FCLK 7 2 UART clock FCLK 8 3 UART cloc
311. d in the Burst 4 Transfer respectively NOTE Unit Transfer size One read and one write is performed XSCLK J XnXDREQ 3 XnXDACK q Double Synch Figure 8 3 Burst 4 Transfer Size ELECTRONICS 8 5 S3C2440A RISC MICROPROCESSOR EXAMPLES Single service in Demand Mode with Unit Transfer Size The assertion of XnXDREQ will be a need for every unit transfer Single service mode The operation continues while the XnXDREQ is asserted Demand mode and one pair of Read and Write Single transfer size is performed XnXDACK Figure 8 4 Single service in Demand Mode with Unit Transfer Size Single service in Handshake Mode with Unit Transfer Size XnXDREQ XnXDACK 1 1 Figure 8 5 Single service Handshake Mode with Unit Transfer Size Whole service in Handshake Mode with Unit Transfer Size XnXDACK esa whic coap Figure 8 6 Whole service in Handshake Mode with Unit Transfer Size 8 6 ELECTRONICS 53 2440 RISC MICROPROCESSOR DMA DMA SPECIAL REGISTERS Each DMA channel has nine control registers 36 in total since there are four channels for DMA controller Six of the control registers control the DMA transfer and other three ones monitor the status of DMA controller The details of those registers are as follows DMA INITIAL SOURCE DISRC REGISTER S ADDR 30 0 Base address start address of source data to transfer This bit
312. d of the current instruction Branches beyond 32Mbytes must use an offset or absolute destination which has been previously loaded into a register In this case the PC should be manually saved in R14 if a Branch with Link type operation is required THE LINK BIT Branch with Link BL writes the old PC into the link register R14 of the current bank The PC value written into R14 is adjusted to allow for the prefetch and contains the address of the instruction following the branch and link instruction Note that the CPSR is not saved with the PC and 1411 0 are always cleared To return from a routine called by Branch with Link use MOV 14 if the link register is still valid LDM Rn PC if the link register has been saved onto a stack pointed to by Rn INSTRUCTION CYCLE TIMES Branch and Branch with Link instructions take 2S 1N incremental cycles where S and are defined as sequential S cycle and internal ELECTRONICS 3 7 ARM INSTRUCTION SET 53 2440 RISC MICROPROCESSOR ASSEMBLER SYNTAX Items in are optional Items in lt gt must be present B L cond expression L Used to request the Branch with Link form of the instruction If absent R14 will not be affected by the instruction cond A two character mnemonic as shown in Table 3 2 If absent then AL ALways will be used The destination The assembler calculates the offset Examples here BAL here Assemble
313. d of the data block Transmission ends when user sets to one RwaitReq bit of SDIDatSta register ELECTRONICS 19 3 50 50 CONTROLLER S3C2440A RISC MICROPROCESSOR SDI SPECIAL REGISTERS SDI Control Register SDICON SDICON 0x5A000000 SDI control register 0 0 s SDMMC Reset Reset whole sdmmc block This bit is automatically cleared SDreset 0 Normal mode 1 SDMMC reset x 1292 Determines which clock type used SDCLK 0 SD type 1 MMC type Byte Order Determines byte order type when you read write data from to Type ByteOrder sd host FIFO with word boundary 0 Type A 1 Receive SDIO Determines whether sd host receives SDIO Interrupt from the Interrupt from card card or not for SDIO RcvlOlnt 0 Ignore 1 Receive SDIO Interrupt Read Wait Determines read wait request signal generate when sd host Enable RWaitEn waits the next block in multiple block read mode This bit needs to delay the next block to be transmitted from the card for SDIO 0 Disable no generate 1 Read wait enable use SDIO Reseved Clock Out Enable Determines whether SDCLK Out enable or not ENCLK 0 Disable prescaler off 1 Clock enable NOTE Byte Order Type Type A Access by Word D 7 0 D 15 8 D 23 16 0 31 24 Access by Halfword D 7 0 D 15 8 Type B Access by Word D 31 24 D 23 16 D 15 8 D 7 0 Access b
314. der code in steppingstone is executed NOTE During the auto boot the ECC is not checked So the first 4 KB of NAND flash should have no bit error 6 2 ELECTRONICS 53 2440 RISC MICROPROCESSOR NAND FLASH CONTROLLER PIN CONFIGURATION 0 00 Enable NAND flash memory boot NCON NAND flash memory selection Normal Advance 0 Normal NAND flash 256Words 512Bytes page size 3 4 address cycle 1 Advance NAND flash 1KWords 2KBytes page size 4 5 address cycle GPG13 NAND flash memory page capacitance selection 0 Page 256Words NCON 0 or Page 1KWords NCON 1 1 Page 512Bytes NCON 0 or Page 2KBytes NCON 1 GPG14 NAND flash memory address cycle selection 0 3 address cycle NCON 0 or 4 address cycle NCON 1 1 4 address cycle NCON 0 or 5 address cycle NCON 1 GPG15 NAND flash memory bus width selection 0 8 bit bus width 1 16 bit bus width NOTE The configuration pin NCON GPG 15 13 will be fetched during reset In normal status these pins must be set as input so that the pin status is not to be changed when enters Sleep mode by software or unexpected cause NAND FLASH MEMORY CONFIGURATION TABLE 0 Normal NAND 0 256Words 0 3 Addr 0 8 bit bus width 1 512Bytes 1 4 Addr 1 Advance NAND 0 1Kwords 0 4 Addr 1 16 bit bus width 1 2Kbytes 1 5 Addr NOTE With above 4 bit Possible total combinations are 16 but not all the value can be used Example Nand flash configuration sett
315. disable the Watchdog timer WTCON 0x53000000 Watchdog timer control register 0x8021 Prescaler value 15 8 Prescaler value The valid range is from 0 to 255 28 1 Reserved 7 6 Reserved These two bits must be 00 in normal operation Watchdog timer 5 Enable or disable bit of Watchdog timer 0 Disable 1 Enable Clock select 4 3 Determine the clock division factor 00 16 01 32 10 64 11 128 Interrupt generation 2 Enable or disable bit of the interrupt 0 Disable 1 Enable Reserved 1 Reserved This bit must be 0 in normal operation Reset enable disable Enable or disable bit of Watchdog timer output for reset signal 1 Assert reset signal of the S3C2440A at watchdog time out 0 Disable the reset function of the watchdog timer ELECTRONICS 18 3 WATCHDOG TIMER S3C2440A RISC MICROPROCESSOR WATCHDOGQ TIMER DATA WTDAT REGISTER The WTDAT register is used to specify the time out duration The content of WTDAT cannot be automatically loaded into the timer counter at initial watchdog timer operation However using 0x8000 initial value will drive the first time out In this case the value of WTDAT will be automatically reloaded into WTCNT WTDAT 0x53000004 Watchdog timer data register 0x8000 Count reload value 15 0 Watchdog timer count value for reload 0x8000 WATCHDOG TIMER COUNT WTCNT REGISTER The WTONT register contains the current count values for the watchdog timer during normal operati
316. down mode in SDRAM ELECTRONICS 5 1 MEMORY CONTROLLER S3C2440A RISC MICROPROCESSOR 1 0 01 10 Boot Internal SRAM 4 1 0 00 0x4000 0000 SROM SDRAM SROM SDRAM 2MB AMB 8MB 16MB nGCS7 nGCS7 32MB 64MB 128MB 0x3800_0000 Table 5 SROM SDRAM SROM SDRAM 2MB 4MB 8MB 16MB nGCS6 nGCS6 32MB 64MB 128MB 0x3000_0000 SROM SROM nGCS5 nGCS5 0x2800_0000 SROM SROM nGCS4 nGCS4 1GB HADDR 29 0 0x2000 0000 Accessible SRON SROM Region nGCS3 nGCS3 0x1800_0000 SROM SROM nGCS2 nGCS2 0x1000_0000 SROM SROM nGCS1 nGCS1 0x0800_0000 SROM nGCS0 Boot Internal SRAM 4KB Not using NAND tlash for boot ROM Using NAND flash for boot ROM 0 0000 0000 Figure 5 1 S3C2440A Memory Map after Reset NOTE SROM means ROM or SRAM type memory 5 2 ELECTRONICS 53 2440 RISC MICROPROCESSOR MEMORY CONTROLLER Table 5 1 Bank 6 7 Addresses Bank 6 Start address 0 3000 0000 0 3000 0000 0 3000 0000 0 3000 0000 0 3000 0000 0 3000 0000 0x3000 0000 End address Ox301F FFFF 0X307F_FFFF FFFF OX31FF_FFFF 0X37FF_FFFF Bank 7 Start address 0 3020 0000 0 3040 0000 0x3080 0000 0 3100 0000 0 3200 0000 0x3400 0000 0 3800 0000 End address FFFF OX307F FFFF FFFF 1 FFFF FFFF OX37FF FFFF NOTE Bank 6 and 7 must
317. dth and parity checking Each UART contains a baud rate generator transmitter receiver and a control unit as shown in Figure 11 1 The baud rate generator can be clocked by PCLK FCLK n or UEXTCLK external input clock The transmitter and the receiver contain 64 byte FIFOs and data shifters Data is written to FIFO and then copied to the transmit shifter before being transmitted The data is then shifted out by the transmit data pin TxDn Meanwhile received data is shifted from the receive data pin RxDn and then copied to FIFO from the shifter FEATURES RxD0 TxD0 RxD1 TxD1 RxD2 TxD2 with DMA based or interrupt based operation UART Ch 0 1 and 2 with IrDA 1 0 amp 64 byte FIFO UART Ch 0 and 1 with nRTSO nCTSO nRTS1 and nCTS1 Supports handshake transmit receive ELECTRONICS 11 1 UART S3C2440A RISC MICROPROCESSOR BLOCK DIAGRAM Peripheral BUS Transmitter Transmit FIFO Register FIFO mode Transmit Buffer Register 64 Byte Transmit Holding Register Non FIFO mode Y Transmit Shifter Control gt Buad rate Clock Source amp T Unit Generator PCLK FCLK n UEXTCLK Receiver Receive Shifter Receive Holding Register Receive Buffer Non FIFO mode only Register 64 Byte Receive FIFO Register FIFO mode In FIFO mode all 64 Byte of Buffer register are used as FIFO register In non FIFO mode only 1 Byte of Buffer register is used as Holding register
318. e When OM 3 2 01b XTIpll is used for MPLL CLK source only When 3 2 10b is used for UPLL CLK source only If it isn t used has to be High VDDOP 1 24 ELECTRONICS 53 2440 RISC MICROPROCESSOR PRODUCT OVERVIEW Table 1 3 S3C2440A Signal Descriptions Sheet 6 of 6 Continued It should be always supplied whether normal mode or in Sleep mode aw awu Dess P AS zs Haw VSSi MPLL P S3C2440A MPLL analog and digital Vss VDDOP P_ S3C244A I O port VDD 3 3V VDDMOP S3C2440A memory 3 3V SCLK up to 135 MHz 2 5V SCLK up to 135 MHz 1 8V SCLK up to 93 MHz VSSOP S3C2440A VO port VSS RTCVDD 3 0V Input range 1 8 3 6V This pin must be connected to power properly if RTC isn t used Monum 1121 12 21 11 eee NOTES 1 means Input Output 2 means analog input analog output 3 ST means schmitt trigger 4 P means power ELECTRONICS 1 25 PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR S3C2440A SPECIAL REGISTERS Table 1 4 S3C2440A Special Registers Sheet 1 of 14 er cam es B Endian L Endian Write w RW Bus wetn a war sratus comro BANKCONO BwROMcmo 6 oeoo J
319. e Horizontal display size 3 x Number of Horizontal Pixel In the 4 bit single scan display mode the Number of valid VD data line should be 4 In case of 4 bit dual scan display the Number of valid VD data lineshould also be 4 while in case of 8 bit single scan display mode the Number of valid VD data line should be 8 LINEVAL Vertical display size 1 In case of single scan display type LINEVAL Vertical display size 2 1 In case of dual scan display type The rate of VCLK signal depends on the configuration of the CLKVAL field in the LCDCON1 register Table 15 1 defines the relationship of and CLKVAL The minimum value of CLKVAL is 2 VCLK Hz HCLK CLKVAL x 2 The frame rate is the VFRAM signal frequency The frame rate is closely related to the field of WLH 1 0 VLINE pulse width WDLY 1 0 the delay width of after VLINE pulse HOZVAL LINEBLANK and LINEVAL in the LCDCON1 2 3 4 registers as well as VCLK and HCLK Most LCD drivers need their own adequate frame rate The frame rate is calculated as follows frame rate Hz 1 1 1 x HOZVAL 1 1 HCLK x A B LINEBLANK x 8 x LINEVAL 1 A 20995 pg p4 WDLY 15 4 ELEGTRONIGS 53 2440 RISC MICROPROCESSOR LCD CONTROLLER Table 15 1 Relation Between VCLK and CLKVAL STN HCLK 60MHz CLKVAL 60MHz X VCLK 1023 60 MHz 2046 29 3 kHz VIDEO OPERATION The S3C2440A LCD controller supports 8 bit color mode 256 color mode
320. e 4 possible blue combinations 00 01 BLUEVAL 7 4 10 BLUEVAL 11 8 11 BLUEVAL 15 12 NOTE Address from 0x14A0002C to 0x14A00048 should not be used This area is reserved for Test mode ELECTRONICS 15 35 LCD CONTROLLER S3C2440A RISC MICROPROCESSOR Dithering Mode Register DITHMODE 0X4D00004C R W STN Dithering mode register 0x00000 This register reset value is 0x00000 But user can change this value to 0x12210 Refer to a sample program source for the latest value of this register DITHMODE Bit Description Initial state state DITHMODE 18 0 Use one of following value for your LCD 0x00000 0x00000 or 0x12210 15 36 ELECTRONICS 53 2440 RISC MICROPROCESSOR LCD CONTROLLER Temp Palette Register TPAL 0X4D000050 R W TFT Temporary palette register 0x00000000 This register value will be video data at next frame TPALEN 24 Temporary palette register enable bit 0 Disable 1 Enable TPALVAL 23 0 Temporary palette value register 0x000000 TPALVAL 23 16 RED TPALVAL 15 8 GREEN TPALVAL 7 0 BLUE ELECTRONICS 15 37 LCD CONTROLLER S3C2440A RISC MICROPROCESSOR LCD Interrupt Pending Register LCDINTPND 0X4D000054 Indicate the LCD interrupt pending register INT_FrSyn 1 LCD frame synchronized interrupt pending bit 0 The interrupt has not been requested 1 The frame has asserted the interrupt request LCDINTPND INT_FiCnt 1 LCD FIFO interrupt
321. e VM alternating period to get the best quality As viewing 16 gray bars select a good gray level which is displayed well on your LCD Use only the good gray levels quality LCD Refresh Bus Bandwidth Calculation Guide The S3C2440A LCD controller can support various LCD display sizes To select a suitable size for the flicker free LCD system application the user have to consider the LCD refresh bus bandwidth determined by the LCD display size bit per pixel bpp frame rate memory bus width memory type and so on LCD Data Rate Byte s bpp x Horizontal display size x Vertical display size x Frame rate 8 LCD Burst Count Times s LCD Data Rate Byte s 16 Byte LCD using 4words 16Byte burst Pdma means LCD DMA access period In other words the value of Pdma indicates the period of four beat burst 4 words burst for video data fetch So Pdma depends on memory type and memory setting Eventually LCD System Load is determined by LCD DMA Burst Count and Pdma LCD System Load LCD Burst Count x Pdma Example 3 640 x 480 8bpp 60 frame sec 16 bit data bus width SDRAM Trp 2HCLK Trcd 2HCLK CL 2HCLK and HCLK frequency is 60 MHz LCD Data Rate 8 x 640 x 480 x 60 8 18 432Mbyte s LCD Burst Count 18 432 16 1 152M s Trp Trcd CL 2 x 4 1 x 1 60MHz 0 250ms LCD System Load 1 152 x 250 0 288 System Bus Occupation Rate 0
322. e assembler places lmm gt gt 2 in the Word8 field 4 26 ELECTRONICS 53 2440 RISC MICROPROCESSOR THUMB INSTRUCTION SET INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 4 12 The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction EXAMPLES STR R4 SP 492 Store the contents of R4 at the address formed by adding 492 to SP R13 Note that the THUMB opcode will contain 123 as the Word8 value ELECTRONICS 4 27 THUMB INSTRUCTION SET S3C2440A RISC MICROPROCESSOR FORMAT 12 LOAD ADDRESS 15 14 13 7 0 12 11 10 8 o i Wos o 7 0 8 bit Unsigned Constant 10 8 Destination Register 11 Source 0 1 5 Figure 4 13 Format 12 OPERATION These instructions calculate an address by adding a 10 bit constant to either the PC or the SP and load the resulting address into a register The THUMB assembler syntax is shown in the following table Table 4 13 Load Address ADD Rd PC ADD Rd R15 Imm Add to the current value of the program counter PC and load the result into Rd 1 ADD Ra SP ADD Rd R13 lmm Add Imm to the current value of the stack pointer SP and load the result into Rd NOTE The value specified by Imm is a full 10 bit value but this must be word aligned ie with bits 1 0 set to 0 since the assembler places 1 gt gt 2 in field Wo
323. e cause of the problem then the instruction can be restarted and the original program continued INSTRUCTION CYCLE TIMES Normal LDR instructions take 1S 1N 11 and LDR PC take 2 2N 11 incremental cycles where S N and are defined as sequential S cycle non sequential N cycle and internal I cycle respectively STR instructions take 2N incremental cycles to execute ELECTRONICS 3 31 ARM INSTRUCTION SET ASSEMBLER SYNTAX 53 2440 RISC MICROPROCESSOR lt LDR STR gt cond B T Rd lt Address gt where LDR STR T Rd Rn and Rm lt Address gt can be 1 lt shift gt 3 32 Load from memory into a register Store from a register into memory Two character condition mnemonic See Table 3 2 is present then byte transfer otherwise word transfer is present the W bit will be set in a post indexed instruction forcing non privileged mode for the transfer cycle T is not allowed when a pre indexed addressing mode is specified or implied An expression evaluating to a valid register number Expressions evaluating to a register number If Rn is R15 then the assembler will subtract 8 from the offset value to allow for ARM920T pipelining In this case base write back should not be specified An expression which generates an address The assembler will attempt to generate an instruction using the PC as a base anda corrected immediate offset to address the location given by
324. e crystal oscillator begins oscillation within several milliseconds When nRESET is released after the stabilization of OSC XTlIpll clock the PLL starts to operate according to the default PLL configuration However PLL is commonly known to be unstable after power on reset so Fin is fed directly to FCLK instead of the Mpll PLL output before the software newly configures the PLLCON Even if the user does not want to change the default value of PLLCON register after reset the user should write the same value into PLLCON register by software The PLL restarts the lockup sequence toward the new frequency only after the software configures the PLL with a new frequency FCLK can be configured as PLL output Mpll immediately after lock time PLL can operate after OM 3 2 is latched nRESET OSC PLL is configured by S W first time Clock gt Disable Lock Time p ow is adapted to new clock frequency The logic operates by XTIpll FCLK is new frequency Figure 7 4 Power On Reset Sequence when the external clock source is a crystal oscillator 7 6 ELECTRONICS 53 2440 RISC MICROPROCESSOR CLOCK amp POWER MANAGEMENT Change PLL Settings In Normal Operation Mode During the operation of the S3C2440A in NORMAL mode the user can change the frequency by writing the PMS value and the PLL lock time will be automatically inserted During the lock time the
325. e first register where more than one is to be transferred and the bit is used to choose one of two transfer length options For instance N 0 could select the transfer of a single register and N21 could select the transfer of all the registers for context switching ADDRESSING MODES 9201 is responsible for providing the address used by the memory system for the transfer and the addressing modes available are a subset of those used in single data transfer instructions Note however that the immediate offsets are 8 bits wide and specify word offsets for coprocessor data transfers whereas they are 12 bits wide and specify byte offsets for single data transfers The 8 bit unsigned immediate offset is shifted left 2 bits and either added to 0 1 subtracted from U 0 the base register Rn this calculation may be performed either before 1 or after 0 the base is used as the transfer address The modified base value may be overwritten back into the base register if W 1 or the old value of the base may be preserved W 0 Note that post indexed addressing modes require explicit setting of the W bit unlike LDR and STR which always write back when post indexed The value of the base register modified by the offset in a pre indexed instruction is used as the address for the transfer of the first word The second word if more than one is transferred will go to or come from an address one word 4 bytes higher than the first t
326. e in DMA mode This bit should be set only when Data Size is word 0 Disable 1 Burst4 enable 23 22 Indicates the size of the transfer with FIFO which is typically byte halfword or word 00 Byte transfer 01 Halfword transfer 10 Word transfer 11 Reserved 21 Determines whether SDIO Interrupt period is 2 cycle or extend more cycle when data block last is transferred for SDIO 0 Exactly 2 cycle 1 More cycle likely single block 20 Determines when data transmit start after response receive or not 0 Directly after DatMode set 1 After response receive assume DatMode sets to 2 b11 19 Determines when data receive start after command sent or not 0 Directly after DatMode set 1 After command sent assume DatMode sets to 2 b10 18 Determines when busy receive start after command sent or not 0 Directly after DatMode set 1 After command sent assume DatMode sets to 2001 17 Data transfer mode 0 Stream data transfer 16 Determines enable wide bus mode 0 Standard bus mode only SDIDAT 0 used 1 Wide bus mode SDIDAT 3 0 used 15 Enable DMA 0 Disable polling 1 enable When DMA operation is completed this bit should be disabled 14 Determines whether data transfer start or not This bit is auto matically cleared 0 Data ready 1 Data start 13 12 1 Block data transfer Determines which direction of data transfer 00 No operation 01 Only busy check mode
327. e instruction is only executed if the condition is true The various conditions are defined in Table 3 2 The instruction format is shown in Figure 3 28 31 2827 2524 cod or Figure 3 28 Undefined Instruction If the condition is true the undefined instruction trap will be taken Note that the undefined instruction mechanism involves offering this instruction to any coprocessors which may be present and all coprocessors must refuse to accept it by driving CPA and CPB HIGH INSTRUCTION CYCLE TIMES This instruction takes 2S 11 1N cycles where S and are defined as sequential S cycle non sequential N cycle and internal I cycle ASSEMBLER SYNTAX The assembler has no mnemonics for generating this instruction If it is adopted in the future for some specified use suitable mnemonics will be added to the assembler Until such time this instruction must not be used 3 58 ELECTRONICS 53 2440 RISC MICROPROCESSOR INSTRUCTION SET EXAMPLES ARM INSTRUCTION SET The following examples show ways in which the basic ARM920T instructions can combine to give efficient code None of these methods saves a great deal of execution time although they may save some mostly they just save code USING THE CONDITIONAL INSTRUCTIONS Using Conditionals for Logical OR CMP Label CMP Rm q BEQ Label This can be replaced by CMP Rn p CMPNE Rm q BEQ Label Abs
328. e multiple of 8 WinHorOfst gt SourceHsize 640 PreHorRatio Pr 2 ClrOvCoFiCr 14 0 Normal 1 Clear the overflow indication flag of input CODEC FIFO Cr ClrOvPrFiCb 13 0 Normal 1 Clear the overflow indication flag of input PREVIEW FIFO Cb ClrOvPrFiCr 12 0 Normal 1 Clear the overflow indication flag of input PREVIEW FIFO Cr WinVerOfst 10 0 Window Vertical Offset NOTE Werecommend you to clear all the overflow bits before starting the capture operation ClrOvCoFiCb 15 0 Normal 1 Clear the overflow indication of input CODEC FIFO Cb SourceHsize TargetHsize xx SourceVsize Window Cut xx 2 15 1 WinHorOfst TargetHsize xx WinVerOfst TargetHsize Co or TargetHsize Pr Figure 23 10 Window Offset Scheme 23 12 ELECTRONICS 53 2440 RISC MICROPROCESSOR CAMERA INTERFACE GLOBAL CONTROL REGISTER CIGCTRL 0x4F000008 Global control register 31 Camera interface software reset 30 External camera reset power down Reserved 29 This bit is reserved and the value must be 1 TestPattern 28 27 This register should be set only at ITU T 601 8 bit mode It is not allowed with ITU T 656 mode max 1280 X 1024 00 External camera processor input normal 01 Color bar test pattern 10 Horizontal increment test pattern 11 Vertical increment test pattern InvPoICAMPCLK 26 0 Normal 1 Inverse the polarit
329. e of Non Auto Flow Control Controlling nRTS and nCTS by Software Rx Operation with FIFO 1 Select receive mode Interrupt or DMA mode 2 Check the value of Rx FIFO count in UFSTATn register If the value is less than 32 users have to set the value of 0 to 1 activating nRTS and if it is equal or larger than 32 users have to set the value to 0 inactivating nRTS 3 Repeat the Step 2 Tx Operation with FIFO 1 Select transmit mode Interrupt or DMA mode 2 Check the value of UMSTATn 0 If the value is 1 activating nCTS users write the data to Tx FIFO register 11 4 ELECTRONICS 53 2440 RISC MICROPROCESSOR UART RS 232C interface Ifthe user wants to connect the UART to modem interface instead of null modem nRTS nCTS nDSR nDTR DCD and nRI signals are needed In this case the users can control these signals with general I O ports by software because the AFC does not support the RS 232C interface Interrupt DMA Request Generation Each UART of the S3C2440A has seven status Tx Rx Error signals Overrun error Parity error Frame error Break Receive buffer data ready Transmit buffer empty and Transmit shifter empty all of which are indicated by the corresponding UART status register UTRSTATn UERSTATn The overrun error parity error frame error and break condition are referred to as the receive error status Each of which can cause the receive error status interrupt request if the rece
330. e state FSM Finite State Machine for its operation which is described in the three following steps State 1 initial state the waits for request Once the request is reached it goes to state 2 At this state and INT are 0 State 2 In this state DMA ACK becomes 1 and the counter CURR TO is loaded from DCON 19 0 register Note that the DMA ACK remains 1 until it is cleared later State 3 In this state sub FSM which handles the atomic operation of DMA is initiated The sub FSM reads the data from the source address and then writes it to destination address In this operation data size and transfer size single or burst are considered This operation is repeated until the counter CURR TO becomes 0 in Whole service mode while performed only once in Single service mode The main FSM this FSM counts down the CURR TC when the sub FSM finishes each of atomic operation In addition this main FSM asserts the INT REQ signal when CURR TC becomes 0 and the interrupt setting of DCON 29 register is set to 1 In addition it clears ACK if one of the following conditions is met 1 CURR TC becomes 0 in the Whole service mode 2 Atomic operation finishes in the Single service mode Note that in the Single service mode these three states of main FSM are performed and then stops and wait for another DMA REQ And if DMA REQ comes in all three states are repeated Therefore DMA ACK is asserted
331. ears this bit to end the STALL condition handshake IN PKT RDY is cleared ELECTRONICS 13 15 USB S3C2440A RISC MICROPROCESSOR END POINT OUT CONTROL STATUS REGISTER OUT CSR1 REG OUT CSR2 REG Continued OUT CSR2 REG 0x52000194 L R W End point out control status register2 0x00 0x52000197 B byte AUTO_CLR If the MCU is set whenever the MCU reads data from the OUT FIFO OUT_PKT_RDY will automatically be cleared by the logic without any intervention from the MCU Determine endpoint transfer type 0 Configures endpoint to Bulk mode 1 Reserved OUT DMA INT MASK Determine whether the interrupt should be issued or not OUT PKT RDY condition happens This is only useful for DMA mode 0 Interrupt Enable 1 Interrupt Disable 13 16 ELECTRONICS 53 2440 RISC MICROPROCESSOR USB DEVICE END POINT OUT WRITE COUNT REGISTER OUT FIFO CNT1 REG OUT FIFO CNT2 REG These registers maintain the number of bytes in the packet as the number is unloaded by the MCU OUT FIFO CNT1 REG 0x52000198 L point out write count register1 0x00 0x5200019B B Tus OUT CNT LOW 7 0 w Lower byte of write count OUT FIFO CNT2 REG 0x5200019C L KEE point out write count register2 0x00 0x5200019F B OUT HIGH 7 0 W Higher byte of write count The OUT CNT HIGH may be always 0 normally END POINT FIFO REGISTER EPN FIFO REG The EPn FIFO REG enables the MCU to access to the EPn FIFO EPO FIFO 0x520001
332. ect all interrupt 0001 0010 Timer1 0011 Timer2 0100 Timer3 0101 Timer4 0110 Reserved 4 19 16 Select MUX input for PWM Timer4 0000 1 2 0001 1 4 0010 1 8 0011 1 16 01 External TCLK1 3 15 12 Select input for PWM Timer3 0000 1 2 0001 1 4 0010 1 8 0011 1 16 01xx External TCLK1 MUX 2 11 8 Select input for PWM Timer2 0000 1 2 0001 1 4 0010 1 8 0011 1 16 01xx External TCLK1 MUX 1 7 4 Select input for PWM Timer1 0000 1 2 0001 1 4 0010 1 8 0011 1 16 01 External TCLK0 MUX 0 3 0 Select MUX input for PWM 0000 1 2 0001 1 4 0010 1 8 0011 1 16 01 External TCLK0 10 12 ELECTRONICS 53 2440 RISC MICROPROCESSOR PWM TIMER TIMER CONTROL TCON REGISTER Timer 4 auto reload on off 22 Determine auto reload on off for Timer 4 0 One shot 1 Interval mode auto reload Timer 4 manual update note 21 Determine the manual update for Timer 4 0 operation 1 Update TCNTB4 Timer 4 start stop 20 Determine start stop for Timer 4 0 Stop 1 Start for Timer 4 Timer 3 auto reload on off 19 Determine auto reload on off for Timer 3 0 One shot 1 Interval mode auto reload Timer 3 output inverter on off 18 Determine output inverter on off for Timer 3 0 Inverter off 1 Inverter on for TOUT3 Timer 3 manual update note 17 Determine manual update for Timer 3 0 operation 1
333. ed as 0x13FFFFFF38 so the least significant 32 bits are OxFFFFFF38 Operand Restrictions The destination register Rd must not be the same as the operand register Rm R15 must not be used as an operand or as the destination register All other register combinations will give correct results and Rd Rn and Rs may use the same register when required ELECTRONICS 3 23 ARM INSTRUCTION SET 53 2440 RISC MICROPROCESSOR CPSR FLAGS Setting the CPSR flags is optional and is controlled by the S bit in the instruction The N Negative and Z Zero flags are set correctly on the result N is made equal to bit 31 of the result and Z is set if and only if the result is zero The C Carry flag is set to a meaningless value and the V oVerflow flag is unaffected INSTRUCTION CYCLE TIMES MUL takes 15 ml and MLA 1 1 cycles to execute where S and are defined as sequential S cycle and internal I cycle respectively m The number of 8 bit multiplier array cycles is required to complete the multiply which is controlled by the value of the multiplier operand specified by Rs Its possible values are as follows If bits 32 8 of the multiplier operand are all zero all one 2 If bits 32 16 of the multiplier operand are all zero or all one 3 If bits 32 24 of the multiplier operand are all zero or all one 4 In all other cases ASSEMBLER SYNTAX MUL cond S Rd Rm Rs Rd Rm Rs Rn cond Two
334. efined in Table 3 2 The instruction encoding is shown in Figure 3 26 This class of instruction is used to load LDC or store STC a subset of coprocessors s registers directly to memory 920 is responsible for supplying the memory address and the coprocessor supplies or accepts the data and controls the number of words transferred 2827 25 24 23 22 21 20 19 16 15 12 11 0 Lus Doc ome 7 0 Unsigned 8 Bit Immediate Offset 11 8 Coprocessor Number 15 12 Coprocessor Source Destination Register 19 16 Base Register 20 Load Store Bit 0 Store to memory 1 Load from memory 21 Write back Bit 0 No write back 1 Write address into base 22 Transfer Length 23 Up Down Bit 0 Down subtract offset from base 1 Up add offset to base 24 Pre Post Indexing Bit 0 Post add offset after transfer 1 Pre add offset before transfer 31 28 Condition Field Figure 3 26 Coprocessor Data Transfer Instructions ELECTRONICS 3 53 ARM INSTRUCTION SET 53 2440 RISC MICROPROCESSOR THE COPROCESSOR FIELDS The field is used to identify the coprocessor which is required to supply or accept the data and a coprocessor will only respond if its number matches the contents of this field The CRd field and the N bit contain information for the coprocessor which may be interpreted in different ways by different coprocessors but by convention CRd is the register to be transferred or th
335. efore the MSB is transmitted This allows the slave transmitter to derive synchronous timing of the serial data that will be set up for transmission Furthermore it enables the receiver to store the previous word and clear the input for the next word MSB LEFT JUSTIFIED MSB left justified bus format is the same as IIS bus format architecturally Only different from the IIS bus format the MSB justified format realizes that the transmitter always sends the MSB of the next word whenever the IISLRCK is changed ELECTRONICS 21 3 IIS BUS INTERFACE 53 2440 RISC MICROPROCESSOR MSB justified Format 8 16 Figure 21 2 IIS Bus and MSB Left justified Data Interface Formats SAMPLING FREQUENCY AND MASTER CLOCK Master clock frequency PCLK or MPLLin can be selected by sampling frequency as shown in Table 21 1 Because Master clock is made by IIS prescaler the prescaler value and Master clock type 256 or 384fs should be determined properly Serial bit clock frequency type 16 32 48fs can be selected by the serial bit per channel and Master clock as shown in Table 21 2 Table 21 1 CODEC clock CODECLK 256 or 38415 IISLRCK 8 000 11 025 16 000 22 050 32 000 44 100 48 000 64 000 88 200 96 000 fs kHz kHz kHz kHz kHz kHz kHz kHz kHz kHz 256fs CODECLK 2 0480 2 8224 4 0960 5 6448 8 1920 11 2896 12 2880 16 3840 22 5792 24 5760 MHz 38415 3 0720 4 2336 6 1440 8 4672 12 2880 16 9344 18 4320 24 5760 33 8688 36 8640
336. eives a new data Before the new data is written into the register the SCL line will be held low and then released after it is written The 53 2440 should hold the interrupt to identify the completion of current data transfer After the CPU receives the interrupt request it should write a new data into the IICDS register again In Receive mode when data is received the IIC bus interface will wait until IICDS register is read Before the new data is read out the SCL line will be held low and then released after it is read The S3C2440A should hold the interrupt to identify the completion of the new data reception After the CPU receives the interrupt request it should read the data from the IICDS register BUS ARBITRATION PROCEDURES Arbitration takes place on the SDA line to prevent the contention on the bus between two masters If a master with a SDA High level detects the other master with a SDA active Low level it will not initiate a data transfer because the current level on the bus does not correspond to its own The arbitration procedure will be extended until the SDA line turns High However when the masters simultaneously lower the SDA line each master should evaluate whether the mastership is allocated itself or not For the purpose of evaluation is that each master should detect the address bits While each master generates the slaver address it should also detect the address bit on the SDA line because the SDA line is likely to
337. em into a suitable data format for example 4 8 bit single scan or 4 bit dual scan display mode The TIMEGEN consists of programmable logic to support the variable requirements of interface timing and rates commonly found in different LCD drivers The TIMEGEN block generates VFRAME VLINE VCLK VM and so on The description of data flow is as follows FIFO memory is present in the LCDCDMA When FIFO is empty or partially empty the LCDCDMA requests data fetching from the frame memory based on the burst memory transfer mode consecutive memory fetching of 4 words 16 bytes per one burst request without allowing the bus mastership to another bus master during the bus transfer When the transfer request is accepted by bus arbitrator in the memory controller there will be four successive word data transfers from system memory to internal FIFO The total size of FIFO is 28 words which consists of 12 words FIFOL and 16 words FIFOH respectively The S3C2440A has two FIFOs to support the dual scan display mode In case of single scan mode one of the FIFOs FIFOH can only be used ELECTRONICS 15 3 LCD CONTROLLER S3C2440A RISC MICROPROCESSOR STN LCD CONTROLLER OPERATION TIMING GENERATOR TIMEGEN The TIMEGEN generates the control signals for the LCD driver such as VFRAME VLINE VCLK and VM These control signals are closely related to the configuration on the LCDCON1 2 3 4 5 registers in the REGBANK Based on these programmable configurations
338. enable 1 0 Priority does not rotate 1 Priority rotate enable P r ELECTRONICS 14 13 INTERRUPT CONTROLLER S3C2440A RISC MICROPROCESSOR INTERRUPT PENDING INTPND REGISTER Each of the 32 bits in the interrupt pending register shows whether the corresponding interrupt request which is unmasked and waits for the interrupt to be serviced has the highest priority Since the INTPND register is located after the priority logic only one bit can be set to 1 and that interrupt request generates IRQ to CPU In interrupt service routine for IRQ you can read this register to determine which interrupt source is serviced among the 32 sources Like the SRCPND register this register has to be cleared in the interrupt service routine after clearing the SRCPND register We can clear a specific bit of the INTPND register by writing a data to this register It clears only the bit positions of the INTPND register corresponding to those set to one in the data The bit positions corresponding to those that are set to 0 in the data remains as they are INTPND 0X4A000010 R W Indicate the interrupt request status 0x00000000 0 The interrupt has not been requested 1 The interrupt source has asserted the interrupt request NOTE Ifthe mode interrupt occurs the corresponding bit of INTPND will not be turned on as the INTPND register is available only for IRQ mode interrupt 14 14 ELECTRONICS 53 2440 RISC MICROPROCE
339. entional interpretation of the instruction is that the coprocessor should perform an operation specified in the CP Opc field and possibly in the CP field on the contents of CRn and CRm and place the result in CRd ELECTRONICS 3 51 ARM INSTRUCTION SET 53 2440 RISC MICROPROCESSOR INSTRUCTION CYCLE TIMES Coprocessor data operations take 1S bl incremental cycles to execute where b is the number of cycles spent in the coprocessor busy wait loop S and l are defined as sequential S cycle and internal I cycle Assembler syntax p lt expression1 gt cd cn cm lt expression2 gt cond lt expression1 gt cd cn and cm lt expression2 gt EXAMPLES CDP CDPEQ 3 52 Two character condition mnemonic See Table 3 2 The unique number of the required coprocessor Evaluated to a constant and placed in the CP Opc field Evaluate to the valid coprocessor register numbers CRd CRn and CRm respectively Where present is evaluated to a constant and placed in the CP field p1 10 c1 c2 c3 Request coproc 1 to do operation 10 on CR2 and and put the result in CR1 2 5 1 2 3 2 If Z flag is set request 2 to do operation 5 type 2 on CR2 and and put the result in CR1 ELECTRONICS 53 2440 RISC MICROPROCESSOR ARM INSTRUCTION SET COPROCESSOR DATA TRANSFERS LDC STC The instruction is only executed if the condition is true The various conditions are d
340. equivalent ARM instruction as shown in Table 4 11 The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction EXAMPLES STRH R6 R1 56 Store the lower 16 bits of R4 at the address formed by adding 56 R1 Note that the THUMB opcode will contain 28 as the Offset5 value LDRH R4 R7 4 Load into R4 the halfword found at the address formed by adding 4 to R7 Note that the THUMB opcode will contain 2 as the Offset5 value ELECTRONICS 4 25 THUMB INSTRUCTION SET S3C2440A RISC MICROPROCESSOR FORMAT 11 SP RELATIVE LOAD STORE 15 7 0 14 13 12 11 10 8 7 0 Immediate Value 10 8 Destination Register 11 Load Store Bit 0 Store to memory 1 Load from memory Figure 4 12 Format 11 OPERATION The instructions in this group perform an SP relative load or store The THUMB assembler syntax is shown in the following table Table 4 12 SP Relative Load Store Instructions STR STR Rd R13 lmm Add unsigned offset 255 words 1020 bytes in Imm to the current value of the SP R7 Store the contents of Rd at the resulting address LDR Imm LDR Rd R13 lmm Add unsigned offset 255 words 1020 bytes in Imm to the current value of the SP R7 Load the word from the resulting address into Rd NOTE The offset supplied in Imm is a full 10 bit address but must always be word aligned ie bits 1 0 set to 0 since th
341. er 8 p P the value for divider P 2 The UPLL within the clock generator is similar to the MPLL in every aspect The following sections describes the operation of the PLL including the phase difference detector the charge pump the Voltage controlled oscillator VCO and the loop filter Phase Frequency Detector PFD The PFD monitors the phase difference between Fref and Fvco and generates a control signal tracking signal when the difference is detected The Fref means the reference frequency as shown in the Figure 7 2 Charge Pump PUMP The charge pump converts PFD control signals into a proportional change in voltage across the external filter that drives the VCO Loop Filter The control signal which the PFD generates for the charge pump may generate large excursions ripples each time the Fvco is compared to the Fref To avoid overloading the VCO a low pass filter samples and filters the high frequency components out of the control signal The filter is typically a single pole RC filter with a resistor and a capacitor Voltage Controlled Oscillator VCO The output voltage from the loop filter drives the VCO causing its oscillation frequency to increase or decrease linearly as a function of variations in average voltage When the Fvco matches Fref in terms of frequency as well as phase the PFD stops sending control signals to the charge pump which in turn stabilizes the input voltage to the loop filter The VCO
342. er word quantity 1 Transfer byte quantity Figure 4 10 Format 9 4 22 ELECTRONICS 53 2440 RISC MICROPROCESSOR THUMB INSTRUCTION SET OPERATION These instructions transfer byte or word values between registers and memory using an immediate 5 or 7 bit offset The THUMB assembler syntax is shown in Table 4 10 Table 4 10 Summary of Format 9 Instructions STR Imm STR Imm Calculate the target address by adding together the value in Rb and Imm Store the contents of Rd at the address LDR Rd LDR Rd Rb Calculate the source address by adding together the value in Rb and Imm Load Rd from the address STRB Rd STRB Rd Calculate the target address by adding together the value in Rb and Imm Store the byte value in Rd at the address LDRB Rd Rb LDRB Rd Rb lmm Calculate source address by adding together the value in Rb and Imm Load the byte value at the address into Rd NOTE For word accesses 0 the value specified by Imm is a full 7 bit address but must be word aligned ie with bits 1 0 set to 0 since the assembler places lmm gt gt 2 in the Offset5 field INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 4 10 The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction EXAMPLES LDR R2 R5 116 Load
343. erRatio Pr 8 0 Vertical scale ratio for preview main scaler PREVIEW DMA TARGET AREA REGISTER CIPRTAREA 25 0 Target area for preview DMA Target H size x Target V size 23 26 ELECTRONICE 53 2440 RISC MICROPROCESSOR CAMERA INTERFACE PREVIEW STATUS REGISTER CIPRSTATUS OvFiCb Pr 31 Overflow state of preview source FIFO Cb OvFiCr_Pr 80 Overflow state of preview source FIFO Cr FlipMd_Pr 24 23 Flip mode of preview DMA ImgCptEn_PrSC 21 Image capture enable of preview path FrameCnt Pr 27 26 Frame count of preview DMA IMAGE CAPTURE ENABLE REGISTER This register must be set at last CIIMGCPT 0x4F0000A0 Image capture enable command ImgCptEn 31 Camera interface global capture enable ImgCptEn_CoSc 80 Capture enable for codec scaler This bit must be 0 scaler bypass mode ImgCptEn_PrSc 29 Capture enable for preview scaler This bit must be 0 in scaler bypass mode ELECTRONICS 23 27 53 2440 RISC MICROPROCESSOR CAMERA INTERFACE NOTES 23 28 ELECTRONICE 53 2440 RISC MICROPROCESSOR AC97 CONTROLLER AC97 CONTROLLER OVERVIEW AC97 Controller Unit of the S3C2440A supports AC97 revision 2 0 features AC97 Controller communicates with AC97 Codec using an audio controller link AC link Controller sends the stereo PCM data to Codec The external digital to analog converter DAC in the Codec then converts the audio sample to an analog audio waveform Also
344. eration Write operation 0 Stop 1 Run Read operation OUT DMA Run Observation IN DMA RUN 1 R W Start DMA operation 0 Stop DMA MODE EN R W R Clear Set mode lf the RUN OB has been wrtten as 0 and n reaches 0 DMA MODE EN bit will be cleared by USB 0 Interrupt Mode 1 Mode 13 18 ELECTRONICS 53 2440 RISC MICROPROCESSOR USB DEVICE DMA UNIT COUNTER REGISTER EPN_DMA_UNIT This register is valid in Demand mode In other modes this register value must be set to 0x01 EP1_DMA UNIT 0x52000204 L R W EP1 DMA transfer unit counter base register 0x00 0x52000207 byte EP2 UNIT 0x5200021C R W EP2 DMA transfer unit counter base register 0x00 0x5200021F byte EP3 DMA UNIT 0x52000244 R W EP3 DMA transfer unit counter base register 0x00 0x52000247 byte sr sr Be EP4 DMA UNIT 0 5200025 R W EP4 DMA transfer unit counter base register 0x00 0x5200025F byte UNIT CNT 7 0 Rw R EP DMA transfer unit counter value ELECTRONICS 13 19 USB S3C2440A RISC MICROPROCESSOR DMA FIFO COUNTER REGISTER EPN_DMA_FIFO This register has values in byte size in FIFO to be transferred by DMA In case of OUT_DMA_RUN enabled the value in OUT FIFO Write Count Register1 will be loaded in this register automatically In case of IN DMA mode the MCU should set proper value by software EP1_DMA FIFO 0x52000208 0x5200020B EP2 DMA
345. errupt Thus only one bit of INTMOD can be set to 1 INTMOD 0X4A000004 R W Interrupt mode register 0x00000000 0 IRQ mode 1 mode NOTE If an interrupt mode is set to mode in the INTMOD register interrupt will not affect both INTPND and INTOFFSET registers In this case the two registers are valid only for IRQ mode interrupt source ELECTRONICS 14 9 INTERRUPT CONTROLLER INTERRUPT MODE INTMOD REGISTER Continued S3C2440A RISC MICROPROCESSOR 14 10 ELECTRONICS 53 2440 RISC MICROPROCESSOR INTERRUPT CONTROLLER INTERRUPT MASK INTMSK REGISTER This register also has 32 bits each of which is related to an interrupt source If a specific bit is set to 1 the CPU does not service the interrupt request from the corresponding interrupt source note that even in such a case the corresponding bit of SRCPND register is set to 1 If the mask bit is 0 the interrupt request can be serviced INTMSK 0X4A000008 R W Determine which interrupt source is masked OxFFFFFFFF The masked interrupt source will not be serviced 0 Interrupt service is available 1 Interrupt service is masked ELECTRONICS 14 11 INTERRUPT CONTROLLER INTERRUPT MASK INTMSK REGISTER Continued S3C2440A RISC MICROPROCESSOR INT ADC 31 0 Service available 0 Service available 0 Service available 0 Service available 0 Service available 0 Service available 0 Service available 0 Service
346. errupt request is pending or not When the interrupt sources request interrupt the service the corresponding bits of SRCPND register are set to 1 and at the same time only one bit of the INTPND register is set to 1 automatically after arbitration procedure If interrupts are masked then the corresponding bits of the SRCPND register are set to 1 This does not cause the bit of INTPND register changed When pending bit of INTPND register is set the interrupt service routine will start whenever the 1 or F flag is cleared to 0 The SRCPND and INTPND registers can be read and written so the service routine must clear the pending condition by writing a 1 to the corresponding bit in the SRCPND register first and then clear the pending condition in the INTPND registers by using the same method Interrupt Mask Register This register indicates that an interrupt has been disabled if the corresponding mask bit is set to 1 If an interrupt mask bit of INTMSK is 0 the interrupt will be serviced normally If the corresponding mask bit is 1 and the interrupt is generated the source pending bit will be set 14 2 ELECTRONICS 53 2440 RISC MICROPROCESSOR INTERRUPT CONTROLLER INTERRUPT SOURCES The interrupt controller supports 60 interrupt sources as shown in the table below INT_UART1 UART1 Interrupt ERR RXD and TXD ARB4 INT_DMAO DMA channel 0 interrupt ARB3 ELECTRONICS 14 3 INTERRUPT CONTROLLER S3C2440A RISC MICR
347. erted INVVD 7 STN TFT This bit indicates the VD video data pulse polarity 0 Normal 1 VD is inverted FRM565 11 TFT This bit selects the format of 16 bpp output video data 0 5 5 5 1 Format 1 5 6 5 Format ELECTRONICS 15 31 LCD CONTROLLER S3C2440A RISC MICROPROCESSOR LCD Control 5 Register Continued INVVDEN TFT This bit indicates the VDEN signal polarity 0 normal 1 inverted INVPWREN 5 STN TFT This bit indicates the PWREN signal polarity 0 normal 1 inverted INVLEND 4 TFT This bit indicates the LEND signal polarity 0 normal 1 inverted 3 PWREN 3 STN TFT LCD PWREN output signal enable disable 0 Disable PWREN signal 1 Enable PWREN signal ENLEND 2 TFT LEND output signal enable disable 0 Disable LEND signal1 Enable LEND signal BSWP 1 STN TFT Byte swap control bit 0 Swap Disable 1 Swap Enable HWSWP STN TFT Half Word swap control bit 0 Swap Disable 1 Swap Enable 15 32 ELEGTRONIGS 53 2440 RISC MICROPROCESSOR LCD CONTROLLER FRAME BUFFER START ADDRESS 1 REGISTER LCDSADDR1 0X4D000014 STN TFT Frame buffer start address 1 register 0x00000000 LCDBANK 29 21 These bits indicate A 30 22 of the bank location for the video buffer in the system memory LCDBANK value cannot be changed even when moving the view port LCD frame buffer should be within aligned 4MB region which ensures that LCDBANK value will not be changed when moving the view port So c
348. erter ADC with a minimum of 16 bit resolution Slot 0 1 2 3 4 5 6 7 8 SYNC CMD CMD PCM PCM SDATA OUT Figure 24 4 Bi directional AC link Frame with Slot Assignments Figure 24 4 shows the slot definitions supported by the 53 2440 97 Controller 53 2440 AC97 Controller provides synchronization for all data transaction on the AC link A data transaction is made up of 256 bits of information broken up into groups of 13 time slots and is called a frame Time slot 0 is called as Tag Phase and it is 16 bits long The remaining 12 time slots are called as Data Phase The Tag Phase contains a bit that identifies a valid frame and 12 bits that identify the time slots in the Data Phase that contain a valid data Each time slot in the Data Phase is 20 bits long A frame begins when the SYNC goes high The amount of time the SYNC is high corresponds to the Tag Phase AC97 frames occur at fixed 48 kHz intervals and are synchronous to the 12 288 MHz bit rate clock BITCLK The controller and the CODEC use the SYNC and BITCLK to determine when to send the transmit data and when to sample the received data A transmitter transitions the serial data stream on each rising edge of BITCLK and a receiver samples the serial data stream on falling edges of BITCLK The transmitter must tag the valid slots in its serial data stream The valid slots are tagged in slot 0 Serial data on the AC link is from MSB to LSB The Tag Phase s first bit is b
349. es Rt 0 1 cycle and a register BNE overflow 2 Overflow in signed multiply with a 32 bit result SMULL Rd Rt Rm Rn 3106 cycles TEQ Rt Rd ASR 31 1 cycle and a register BNE overflow 3 Overflow in unsigned multiply accumulate with a 32 bit result UMLAL Rd Rt Rm Rn 4107 cycles TEQ Rt 0 1 cycle and a register BNE overflow 4 Overflow in signed multiply accumulate with a 32 bit result SMLAL Rd Rt Rm Rn 4107 cycles TEQ Rt Rd ASR 31 1 cycle and a register BNE overflow 3 60 ELECTRONICS 53 2440 RISC MICROPROCESSOR 5 Overflow in unsigned multiply accumulate with a 64 bit result UMULL RI Rh Rm Rn 3106 cycles ADDS RI RI Ra1 Lower accumulate ADC Rh Rh Ra2 Upper accumulate BCS overflow 1 cycle and 2 registers 6 Overflow in signed multiply accumulate with a 64 bit result SMULL RI Rh Rm Rn 3106 cycles ADDS RI RI Ra1 Lower accumulate ADC Rh Rh Ra2 Upper accumulate BVS overflow 1 cycle and 2 registers NOTE ARM INSTRUCTION SET Overflow checking is not applicable to unsigned and signed multiplies with a 64 bit result since overflow does not occur in such calculations PSEUDO RANDOM BINARY SEQUENCE GENERATOR It is often necessary to generate pseudo random numbers and the most efficient algorithms are based on shift generators with exclusive OR feedback rather like a cyclic redundancy check generator Unfortunately the sequence of a 32 bit generator needs more than one feedba
350. es Endpoint Direction as IN 0 Configures Endpoint Direction as OUT IN DMA INT EN 4 R W Determine whether the interrupt should be issued or not when the IN_PKT_RDY condition happens This is only useful for DMA mode 0 Interrupt enable 1 Interrupt Disable mew S 13 14 ELECTRONICS 53 2440 RISC MICROPROCESSOR USB DEVICE END POINT OUT CONTROL STATUS REGISTER OUT CSR1 REG OUT CSR2 REG OUT CSR1 REG 0x52000190 L R W End point out control status register 0x00 0x52000193 B OUT REG Bit USB Description Initial State CLR DATA TOGGLE 7 R W CLEAR When the MCU writes a 1 to this bit the data toggle sequence bit is reset to DATAO SENT STALL CLEAR SET Set by the USB when an OUT token is IR ended with a STALL handshake The USB issues a stall handshake to the host if it sends more than MAXP data for the OUT TOKEN FIFO FLUSH 4 R W CLEAR The MCU writes a 1 to flush the FIFO This bit can be set only when OUT PKT RDY 00 is set The packet due to be unloaded by the MCU will be flushed OUT PKT RDY R SET Set by the USB after it has loaded a CLEAR packet of data into the FIFO Once the MCU reads the packet from FIFO this bit should be cleared by MCU write a SEND STALL 5 R W The MCU clears this bit to end the STALL condition handshake IN PKT RDY is cleared The MCU issues a STALL handshake to the USB The MCU cl
351. evaluating the expression This will be a PC relative pre indexed address If the address is out of range an error will be generated A pre indexed addressing specification Rn offset of zero Rn lt expression gt Rn Rm lt shift gt offset of lt expression gt bytes offset of contents of index register shifted by lt shift gt A post indexed addressing specification Rn lt expression gt Rn Rm lt shift gt offset of lt expression gt bytes offset of contents of index register shifted as by lt shift gt General shift operation see data processing instructions but you cannot specify the shift amount by a register Writes back the base register set the W bit if is present ELECTRONICS 53 2440 RISC MICROPROCESSOR EXAMPLES STR STR LDR LDR LDREQB STR PLACE ELECTRONICS 1 82 84 R1 R2 R4 R1 R2 46 R1 R2 R3 LSL 2 R1 R6 5 R1 PLACE ARM INSTRUCTION SET Store R1 at R2 R 4 both of which are registers and write back address to R2 Store R1 at R2 and write back R2 R4 to R2 Load R1 from contents of R2 16 but don t write back Load R1 from contents of R2 R3 4 Conditionally load byte at R6 5 into R1 bits O to 7 filling bits 8 to 31 with zeros Generate PC relative offset to address PLACE 3 33 ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR HALFWORD AND SIGNED DATA TRANSFER LDRH STRH LDRSB LDRSH The instruction is only e
352. except this area write or erase command will be invalid and only read command is valid When you try to write or erase locked area the illegal access will be occur NFSTAT 3 bit will be set If the NFSBLK and NFEBLK are same entire area will be locked Reserved Illegal access interrupt control 0 Disable interrupt 1 Enable interrupt Illegal access interrupt is occurred when CPU tries to program or erase locking area the area setting ay NFSBLK 0x4E000038 to NFEBLK 0x4E00003C RnB status input signal transition interrupt control 0 Disable RnB interrupt 1 Enable RnB interrupt RnB transition detection configuration 0 Detect rising edge 1 Detect falling edge Reed NAND FLASH CONTROLLER 53 2440 RISC MICROPROCESSOR CONTROL REGISTER Continued SpareECCLock Lock spare area ECC generation 0 Unlock spare ECC 1 Lock spare ECC Spare area ECC status register is FSECC 0x4E000034 MainECCLock Lock Main data area ECC generation 0 Unlock main data area ECC generation 1 Lock main data area ECC generation Main area ECC status register is NFMECCO 1 0x4E00002C 30 InitECC 4 Initialize ECC decoder encoder Write only 1 Initialize ECC decoder encoder Reg nCE 1 NAND Flash Memory nFCE signal control 0 Force nFCE to low Enable chip select 1 Force nFCE to high Disable chip select Note During boot time it is controlled automatically This value is only valid while MODE bit is 1 MODE
353. f video data correspond to 1 pixel In 256 level color mode 8 bits 3 bits of red 3 bits of green and 2 bits of blue of video data correspond to 1 pixel The color data format in a byte is as follows murs me Ge Be In 4096 level color mode Packed 12 BPP color mode 12 bits 4 bits of red 4 bits of green 4 bits of blue of video data correspond to 1 pixel The following table shows color data format in words Video data must reside at 3 word boundaries 8 pixel as follows RGB Order DATA Unpacked 12 BPP color mode 12 bits 4 bits of red 4 bits of green 4 bits of blue of video data correspond to 1 pixel The following table shows color data format in words RGB Order man nes Gema reao vera reaa Ge sus mee Bere 15 10 ELECTRONICS 53 2440 RISC MICROPROCESSOR LCD CONTROLLER 16 BPP color mode 16 bits 5 bits of red 6 bits of green 5 bits of blue of video data correspond to 1 pixel But stn controller will use only 12 bit color data It means that only upper 4bit each color data will be used as pixel data R 15 12 G 10 7 B 4 1 The following table shows color data format i
354. fication to fill the one color to the frame buffer or palette The one colored frame can be displayed by the writing a value of the color which is displayed on LCD panel to TPALVAL of TPAL register and enable TPALEN ELECTRONICS 15 21 LCD CONTROLLER S3C2440A RISC MICROPROCESSOR A 31 A 30 A 29 A 28 A 27 26 25 A 24 A 23 A 22 A 21 20 19 18 17 A 16 ce at E o es e s A 15 A 14 A 13 A 12 A 11 10 9 A 8 A 7 A 6 5 A S A 2 0 LCD Panel 16BPP 5 5 5 1 Format Non Palette A 81 A 30 A 29 A 28 A 27 A 26 A 25 A 24 23 A 22 21 A 20 A 19 A 18 A 17 A 16 m At as 94 Br re re os e os A 15 A 14 A 13 12 11 A 10 9 A 8 A 7 A 6 5 A 4 A 3 A 2 A 1 0 LCD Panel 16BPP 5 6 5 Format Non Palette Figure 15 5 16BPP Display Types TFT 15 22 ELECTRONICS 53 2440 RISC MICROPROCESSOR LCD CONTROLLER 1 i Fog 1 I 1 I HBPD 1 HOZVAL 1 HFPD 1 Figure 15 6 TFT LCD Timing Example ELECTRONICS 15 23 LCD CONTROLLER S3C2440A RISC MICROPROCESSOR SAMSUNG TFT LCD PANEL 3 5 PORTRAIT 256
355. for preview DMA _ Target image format of preview DMA Preview DMA control related Preview pre scaler ratio control Preview pre scaler destination Preview main scaler control Preview scaler targetarea Preview path status image capture enable command CIPRCLRSA2 0 4 000070 CIPRCLRSA3 0x4F000074 S i Codecprescalerratio contro um ELECTRONICS 1 31 PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR Table 1 4 S3C2440A Special Registers Sheet 7 of 14 Continued veer dem me e Name B Endian L Endian Write oxs000000c fuensraro jursraro oso 0660000023 06000020 B w URTOrensissonoi 0660000027 oxsooo002 R UART receno buter uco umeona moni oso oswo umm osoo J usmm osoo Oosa _____ _____ umm 0660004023 umen 0660004027 20006
356. frequency then remains constant and the PLL remains fixed onto the system clock Usual Conditions for PLL amp Clock Generator PLL amp Clock Generator generally uses the following conditions Loop filter capacitance MPLLCAP 1 3 nF 5 UPLLCAP 700 pF 596 External X tal frequency 12 20 MHz note External capacitance used for X tal 15 22 pF NOTES 1 The value could be changed 2 FCLKour must be bigger than 200MHz It does not mean that the ARM core has to run more than 200MHz 7 4 ELECTRONICS 53 2440 RISC MICROPROCESSOR CLOCK amp POWER MANAGEMENT MPLLCAP P 5 0 UPLLCAP 7 0 External S 1 0 S Figure 7 2 PLL Phase Locked Loop Block Diagram External OSC X TAL Oscillation OM 3 2 00 b External Clock Source OM 3 2 11 Figure 7 3 Main Oscillator Circuit Examples ELECTRONICS 7 5 CLOCK amp POWER MANAGEMENT 53 2440 RISC MICROPROCESSOR CLOCK CONTROL LOGIC The Clock Control Logic determines the clock source to be used i e the PLL clock Mpll or the direct external clock XTlpll or EXTCLK When PLL is configured to a new frequency value the clock control logic disables the FCLK until the PLL output is stabilized using the PLL locking time The clock control logic is also activated at power on reset and wakeup from power down mode Power On Reset XTIpll Figure 7 4 shows the clock behavior during the power on reset sequence Th
357. get Low rather than to keep High Assume that one master generates a Low as first address bit while the other master is maintaining High In this case both masters will detect Low on the bus because the Low status is superior to the High status in power When this happens Low as the first bit of address generating master will get the mastership while High as the first bit of address generating master should withdraw the mastership If both masters generate Low as the first bit of address there should be arbitration for the second address bit again This arbitration will continue to the end of last address bit ABORT CONDITIONS If a slave receiver cannot acknowledge the confirmation of the slave address it should hold the level of the SDA line High In this case the master should generate a Stop condition and to abort the transfer If a master receiver is involved in the aborted transfer it should signal the end of the slave transmit operation by canceling the generation of an ACK after the last data byte received from the slave The slave transmitter should then release the SDA to allow a master to generate a Stop condition CONFIGURING IIC BUS To control the frequency of the serial clock SCL the 4 bit prescaler value can be programmed in the IICCON register The IIC bus interface address is stored in the IIC bus address IICADD register By default the IIC bus interface address has an unknown value 20 6 ELECTRONICS 53 2440
358. gister TIMER 1 COUNT OBSERVATION REGISTER TCNTO1 0x51000020 Timer 1 count observation register 0x00000000 Register TCNTO1 Timer 1 observation register 15 0 Set count observation value for Timer 1 0x00000000 10 16 ELECTRONICS 53 2440 RISC MICROPROCESSOR PWM TIMER TIMER 2 COUNT BUFFER REGISTER amp COMPARE BUFFER REGISTER TCNTB2 TCMPB2 TCNTB2 0x51000024 Timer 2 count buffer register 0x00000000 TCMPB2 0x51000028 Timer 2 compare buffer register 0x00000000 Timer 2 compare buffer register 15 0 Set compare buffer value for Timer 2 0x00000000 15 0 Set count buffer value for Timer 2 0x00000000 TCNTB2 Timer 2 count buffer register TIMER 2 COUNT OBSERVATION REGISTER TCNTO2 2 0 5100002 Timer 2 count observation register 0x00000000 15 0 Set count observation value for Timer 2 0x00000000 TCNTO2 Timer 2 observation register ELECTRONICS 10 17 PWM TIMER S3C2440A RISC MICROPROCESSOR TIMER 3 COUNT BUFFER REGISTER amp COMPARE BUFFER REGISTER TCNTB3 TCMPB3 TCNTB3 0x51000030 Timer 3 count buffer register 0x00000000 TCMPB3 0x51000034 Timer 3 compare buffer register 0x00000000 Timer 3 compare buffer register 15 0 Set compare buffer value for Timer 3 0x00000000 15 0 Set count buffer value for Timer 0x00000000 TCNTB3 Timer 3 count buffer register TIMER 3 COUNT OBSERVATION REGISTER TCNTO3 0 51000038 Timer 3 count observation register 0x00000000
359. gister 0x55000006 Bi HW Master clock select Master clock select 0 PCLK 1 MPLLin Master slave mode select 0 Master mode IISLRCK and IISCLK are output mode 1 Slave mode IISLRCK and IISCLK are input mode Transmit receive mode 7 6 00 No transfer 01 Receive mode select 10 Transmitmode 11 Transmit and receive mode Active level of left right 5 0 Low for left channel High for right channel channel 1 High for left channel Low for right channel Serial interface format IIS compatible format MSB Left justified format Serial data bit per 0 8 bit 1 16 bit channel Master clock frequency 0 256fs 1 38415 select fs sampling frequency Serial bit clock frequency 1 0 00 16fs 01 32fs select 10 48fs 11 N A NOTES 1 The IISMOD register is accessible for each halfword and wordunit using STRH STR and LDRH LDR instructions or short int int type pointer in Little Big endian mode 2 Li HW W Little HalfWord Word Bi HW W Big HalfWord Word 21 6 ELECTRONICS 53 2440 RISC MICROPROCESSOR IIS BUS INTERFACE IIS PRESCALER IISPSR REGISTER IISPSR 0x55000008 Li HW Li W Bi W IIS prescaler register 0 5500000 Bi HW Prescaler control A s Data value 0 31 Note Prescaler A makes the master clock that is used the internal block and division factor is 1 Prescaler control B Data value 0 31 Note Prescaler B makes the master clock that is used the external blo
360. gram Trp 2 Trc 4 a 27 28 SDRAM Single Write Timing Diagram Trp 2 Trcd 2 a 27 29 SDRAM Page Hit Miss Write Timing Diagram Trp 2 Trcd 2 2 27 30 External DMA Timing Diagram Handshake Single transfer 27 31 TFT LCD Controller Timing S asus mmm 27 31 IIS Interface Timing Damani C Au Qu un u meer 27 32 Interface Timing 27 32 SD MMC Interface Timing 27 33 SPI Interface Timing Diagram 1 CPOL 1 a een 27 33 NAND Flash Address Command Timing 27 34 Flash Timing 27 34 53 2440 MICROCONTROLLER List of Tables Table Title Page Number Number 1 1 289 Pin FBGA Pin Assignments Pin Number Order Sheet 1 of 3 1 7 1 2 S3C2440A 289 Pin FBGA Pin Assignments Sheet 1 of 9 1 10 1 3 S3C2440A Signal Descriptions Sheet 1 1 20 14 S3C2440A Special Registers Sheet 1 14 1 26 2 1 FSR Mode Er Values ie e bet e eb tte boe e bte tins 2 9 2 2 Exception Entty EXIE uku eroe
361. have the same memory size ELECTRONICS 5 3 MEMORY CONTROLLER S3C2440A RISC MICROPROCESSOR FUNCTION DESCRIPTION BUS WIDTH The data bus of BANK0 nGCS0 should be configured with a width as one of 16 bit and 32 bit ones Because the BANKO works as the booting ROM bank map to 0x0000 0000 the bus width of BANKO should be determined before the first ROM access which will depend on the logic level of OM 1 0 at Reset OM1 Operating Mode 1 Operating Mode 0 Booting ROM Data width 90010214112 16 e MEMORY SROM SDRAM ADDRESS PIN CONNECTIONS MEMORY ADDR PIN 53 2440 ADDR 53 2440 ADDR 53 2440 ADDR 8 bit DATA BUS 16 bit DATA BUS 32 bit DATA BUS 5 4 ELECTRONICS 53 2440 RISC MICROPROCESSOR MEMORY CONTROLLER SDRAM BANK ADDRESS PIN CONNECTION EXAMPLE Table 5 2 SDRAM Bank Address Configuration Example ELE Base Component Memory Configuration Bank Address 2MByte 16Mbit 1M x 2Bank 1 5612Kx16x2B x1 __ 2 7 qMxexzx2 1 8 4 64Mb PN 2K x 32 x 4B 64Mb 52 2M x 16 x 2B i E 22 Mx8x4Bx1 2M x 16 x 4B x 1 Mx 4x 2B x4 O OAA O dii n 4M x 8x 2B 2M x 8 x 4B 24 23 128Mb 4M x 8 x 4B x2 2M x 16 x 5 2 4M x 16 x EACUS x1 128Mb 25 24 256 Mx8x4B x2 x 8 x 4B se O o9 ramone ar 128MB 26 2
362. he LCD controller has a dedicated DMA that supports to fetch the image data from video buffer located in system memory Its features also include Dedicated interrupt functions INT FrSyn and INT_FiCnt The system memory is used as the display memory Supports Multiple Virtual Display Screen Supports Hardware Horizontal Vertical Scrolling Programmable timing control for different display panels Supports little and big endian byte ordering as well as WinCE data formats Supports 2 type SEC TFT LCD panel SAMSUNG 3 5 Portrait 256K Color Reflective and Transflective a Si TFT LCD LTS350Q1 PD1 TFT LCD panel with touch panel and front light unit Reflective type LTS350Q1 PD2 TFT LCD panel only LTS350Q1 PE1 TFT LCD panel with touch panel and front light unit Transflective type LTS350Q1 PE2 TFT LCD panel only NOTE WinCE doesn t support the 12 bit packed data format Please check if WinCE can support the 12 bit color mode EXTERNAL INTERFACE SIGNAL 31r 1 LTS350Q1 PD1 2 LTS350Q1 PE1 2 Signal Signal ignal ignal STN VFRAME VSYNC STV STV Frame sync Signal Vertical sync Signal VLINE HSYNC CPV CPV Line sync pulse signal Horizontal sync Signal VCLK VCLK LCD_HCLK LCD_HCLK Pixel clock signal Pixel clock signal VD 23 0 VD 23 0 VD 23 0 VD 23 0 LCD pixel data output ports LCD pixel data output ports VM VDEN TP TP AC bias signal for LCD driver Data enable signal
363. he interrupt service routine for a specific interrupt source the corresponding bit of the SRCPND register has to be cleared to get the interrupt request from the same source correctly If you return from the ISR without clearing the bit the interrupt controller operates as if another interrupt request came in from the same source In other words if a specific bit of the SRCPND register is set to 1 it is always considered as a valid interrupt request waiting to be Serviced The time to clear the corresponding bit depends on the user s requirement If you want to receive another valid request from the same source you should clear the corresponding bit first and then enable the interrupt You can clear a specific bit of the SRCPND register by writing a data to this register It clears only the bit positions of the SRCPND corresponding to those set to one in the data The bit positions corresponding to those that are set to 0 in the data remains as they are SRCPND 0X4A000000 R W Indicate the interrupt request status 0x00000000 0 The interrupt has not been requested 1 The interrupt source has asserted the interrupt request ELECTRONICS 14 7 INTERRUPT CONTROLLER S3C2440A RISC MICROPROCESSOR SOURCE PENDING SRCPND REGISTER Continued __ Depo 0 Not requested 1 Requested 0 Not requested 1 Requested 0 Not requested 1 Requested 0 Not requested 1 Requested 0 Not requested 1 Reques
364. he timer running mode the value of TCNTBn will not be reloaded into the counter The value of TCMPBn is used for pulse width modulation PWM The timer control logic changes the output level when the down counter value matches the value of the compare register in the timer control logic Therefore the compare register determines the turn on time or turn off time of a PWM output FEATURE Five 16 bit timers Two 8 bit prescalers amp Two 4 bit divider Programmable duty control of output waveform PWM Auto reload mode or one shot pulse mode Dead zone generator ELECTRONICS 10 1 PWM TIMER S3C2440A RISC MICROPROCESSOR Dead Zone Generator 8 Bit Prescaler 8 Bit Prescaler Clock Divider Figure 10 1 16 bit PWM Timer Block Diagram 10 2 ELECTRONICS 53 2440 RISC MICROPROCESSOR PWM TIMER PWM TIMER OPERATION PRESCALER amp DIVIDER 8 bit prescaler and 4 bit divider make the following output frequencies 4 bit Divider Settings Minimum Resolution Maximum Resolution Maximum Interval prescaler 0 prescaler 255 TCNTBn 65535 1 2 PCLK 50 MHz 0 0400 us 25 0000 MHz 10 2400 97 6562 kHz 0 6710 1 4 POLK 50 MHz 0 0800 us 12 5000 MHz 20 4800 48 8281 kHz 1 3421 1 8 PCLK 50 MHz 0 1600 6 2500 MHz 40 9601 24 4140 kHz 2 6843 1 16 PCLK 50 MHz 0 3200 3 1250 MHz 81 9188 12 2070 kHz 5 3686 BA
365. hich causes the PC to be 1 word 4 bytes ahead of the current instruction The THUMB assembler syntax is shown in the following table Table 4 17 The Conditional Branch Instructions Branch if Z clear not equal Branch if C set unsigned higher or same Branch if C clear unsigned lower Branch if N clear positive or zero Branch if V clear no overflow Branch if C set and Z clear unsigned higher 4 34 ELECTRONICS 53 2440 RISC MICROPROCESSOR THUMB INSTRUCTION SET Table 4 17 The Conditional Branch Instructions Continued 1001 BLS label BLS label Branch if C clear or Z set unsigned lower or same 1010 BGE label BGE label Branch if N set and V set or N clear and V clear greater or equal 1011 label BLT label Branch if N set and V clear or N clear and V set less than 1100 label label Branch if Z clear and either set and V set or N clear and V clear greater than 1101 BLE label BLE label Branch if Z set or N set and V clear or N clear and V set less than or equal NOTES 1 While label specifies a full 9 bit two s complement address this must always be halfword aligned ie with bit 0 set to 0 since the assembler actually places label gt gt 1 in field SOffset8 2 1110 is undefined and should not be used Cond 1111 creates the SWI instruction see INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown
366. hifted in some way The offset may be added to U 1 or subtracted from U 0 the base register Rn The offset modification may be performed either before pre indexed 1 or after post indexed 0 the base is used as the transfer address The W bit gives optional auto increment and decrement addressing modes The modified base value may be written back into the base W 1 or the old base value may be kept W 0 In the case of post indexed addressing the write back bit is redundant and is always set to zero since the old base value can be retained by setting the offset to zero Therefore post indexed data transfers always write back the modified base The only use of the W bit in a post indexed data transfer is in privileged mode code where setting the W bit forces non privileged mode for the transfer allowing the operating system to generate a user address in a system where the memory management hardware makes suitable use of this hardware SHIFTED REGISTER OFFSET The 8 shift control bits are described in the data processing instructions section However the register specified shift amounts are not available in this instruction class See Figure 3 5 BYTES AND WORDS This instruction class may be used to transfer a byte 1 or a word 0 between an ARM920T register and memory The action of LDR B and STR B instructions is influenced by the BIGEND control signal of ARM920T core The two possible configurations are described
367. his mode the power consumption will be maximized when all peripherals are turned on It allows the user to control the operation of peripherals by software For example if a timer is not needed the user can disconnect the clock CLKCON register to the timer to reduce power consumption SLOW mode Non PLL mode Unlike the Normal mode the Slow mode uses an external clock XTlpll or EXTCLK directly as FCLK in the S3C2440A without PLL In this mode the power consumption depends on the frequency of the external clock only The power consumption due to PLL is excluded IDLE mode The block disconnects clocks FCLK only to the CPU core while it supplies clocks to all other peripherals The IDLE mode results in reduced power consumption due to CPU core Any interrupt request to CPU can be woken up from the Idle mode SLEEP mode The block disconnects the internal power So there occurs no power consumption due to CPU and the internal logic except the wake up logic in this mode Activating the SLEEP mode requires two independent power sources One of the two power sources supplies the power for the wake up logic The other one supplies other internal logics including CPU and should be controlled for power on off In the SLEEP mode the second power supply source for the CPU and internal logics will be turned off The wakeup from SLEEP mode can be issued by the EINT 15 0 or by RTC alarm interrupt ELECTRONICS CLOCK amp MANAGEMENT S3C244
368. ice block 0 Disable 1 Enable USB host Control HCLK into USB host block 0 Disable 1 Enable LCDC 5 Control HCLK into LCDC block 0 Disable 1 Enable NAND Flash Controller 4 Control HCLK into NAND Flash Controller block 0 Disable 1 Enable SLEEP Control SLEEP mode of S3C2440A 0 Disable 1 Transition to SLEEP mode IDLE BIT Enter IDLE mode This bit is not cleared automatically 0 Disable 1 Transition to IDLE mode Reeve 7 22 ELECTRONICS 53 2440 RISC MICROPROCESSOR CLOCK amp POWER MANAGEMENT CLOCK SLOW CONTROL CLKSLOW REGISTER CLKSLOW 0x4C000010 Slow clock control register 0x00000004 UCLK ON 7 0 UCLK ON UPLL is also turned on and the UPLL lock time is inserted automatically 1 UCLK OFF UPLL is also turned off MPLL OFF 5 0 Tum on PLL After PLL stabilization time minimum 300us SLOW can be cleared to 0 1 Turn off PLL PLL is turned off only when SLOW BIT is 1 BH SLOW VAL 2 0 The divider value for the slow clock when SLOW is on SLOW BIT 4 0 FCLK Mpll MPLL output 1 SLOW mode input clockK 2xXSLOW VAL when SLOW_VAL gt 0 FCLK input clock when SLOW 0 Input clock or EXTCLK ELECTRONICS 7 23 CLOCK amp POWER MANAGEMENT 53 2440 RISC MICROPROCESSOR CLOCK DIVIDER CONTROL CLKDIVN REGISTER CLKDIVN 0 4 000014 R W Clock divider control register 0x00000000 DIVN UPLL 3
369. ied as both the source and destination The LOCK output goes HIGH for the duration of the read and write operations to signal to the external memory manager that they are locked together and should be allowed to complete without interruption This is important in multi processor systems where the swap instruction is the only indivisible instruction which may be used to implement semaphores control of the memory must not be removed from a processor while it is performing a locked operation BYTES AND WORDS This instruction class may be used to swap a byte 1 or a word 0 between an 920 register and memory The SWP instruction is implemented as a LDR followed by a STR and the action of these is as described in the section on single data transfers In particular the description of Big and Little Endian configuration applies to the SWP instruction ELECTRONICS 3 47 ARM INSTRUCTION SET 53 2440 RISC MICROPROCESSOR USE OF R15 Do not use R15 as an operand Rd Rn or Rs in a SWP instruction DATA ABORTS If the address used for the swap is unacceptable to a memory management system the memory manager can flag the problem by driving ABORT HIGH This can happen on either the read or the write cycle or both and in either case the Data Abort trap will be taken It is up to the system software to resolve the cause of the problem then the instruction can be restarted and the original program continued INSTRUCTION CYCLE TI
370. ighest numbered byte the most significant Byte 0 of the memory system is therefore connected to data lines 7 through 0 Higher Address Word Address Least significant byte is at lowest address Lower Address Word is addressed by byte address of least significant byte Figure 2 2 Little Endian Addresses of Bytes within Words INSTRUCTION LENGTH Instructions are either 32 bits long in ARM state or 16 bits long in THUMB state Data Types ARM920T supports byte 8 bit halfword 16 bit and word 32 bit data types Words must be aligned to four byte boundaries and half words to two byte boundaries 2 2 ELECTRONICS 53 2440 RISC MICROPROCESSOR PROGRAMMER S MODEL OPERATING MODES ARM920T supports seven modes of operation User usr The normal ARM program execution state Designed to support a data transfer or channel process IRQ irq Used for general purpose interrupt handling Supervisor svc Protected mode for the operating system Abort mode abt Entered after a data or instruction prefetch abort System sys A privileged user mode for the operating system e Undefined und Entered when an undefined instruction is executed Mode changes can be made using the control of software or may be brought about by external interrupts or exception processing Most application programs will execute in User mode The non user modes known as privileged modes are entered in order to servi
371. in Table 3 1 The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction EXAMPLES 45 Branch to over if gt 45 over Note that the THUMB opcode will contain the number of halfwords to offset over Must be halfword aligned ELECTRONICS 4 35 THUMB INSTRUCTION SET S3C2440A RISC MICROPROCESSOR FORMAT 17 SOFTWARE INTERRUPT 15 14 13 12 11 10 7 0 9 8 7 0 Comment Field Figure 4 18 Format 17 OPERATION The SWI instruction performs a software interrupt On taking the SWI the processor switches into ARM state and enters Supervisor SVC mode The THUMB assembler syntax for this instruction is shown below Table 4 18 The SWI Instruction SWI Value 8 SWI Value 8 Perform Software Interrupt Move the address of the next instruction into LR move CPSR to SPSR load the SWI vector address 0x8 into the PC Switch to ARM state and enter SVC mode NOTE Value8 is used solely by the SWI handler it is ignored by the processor INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 4 18 The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction EXAMPLES SWI 18 Take the software interrupt exception Enter Supervisor mode with 18 as the requested SWI number 4 36 ELECTRONICS 3 2440 RISC MICROPROCESSOR
372. ing 9 3 ELECTRONICS 6 3 NAND FLASH CONTROLLER 53 2440 RISC MICROPROCESSOR NAND FLASH MEMORY TIMING TACLS TWRPHO I TWRPH1 CLE ALE TWRPHO TWRPH1 nWE nRE Figure 6 4 nWE amp nRE Timing TWRPH0 0 TWRPH1z0 6 4 ELECTRONICS 53 2440 RISC MICROPROCESSOR NAND FLASH CONTROLLER SOFTWARE MODE S3C2440A supports only software mode access Using this mode you can completely access the NAND flash memory The NAND Flash Controller supports direct access interface with the NAND flash memory i Writing to the command register the Flash Memory command cycle Writing to the address register the NAND Flash Memory address cycle Writing to the data register write data to the NAND Flash Memory write cycle Reading from the data register read data from the NAND Flash Memory read cycle Reading main ECC registers and Spare ECC registers read data from the NAND Flash Memory NOTE In the software mode you have to check the RnB status input pin by using polling or interrupt ELECTRONICS 6 5 NAND FLASH CONTROLLER 53 2440 RISC MICROPROCESSOR Data Register Configuration 1 16 bit NAND Flash Memory Interface A Word Access messe NFDATA 2ndyopts g 279 0 7 0 i15tyops s 15 0 7 0 NFDATA 19058 190170 2790058 274 vor 7 0 Half word Access Register
373. ing e 130 General Purpose ports 24 ch external interrupt source e Power control Normal Slow Idle and Sleep mode e On chip clock generator with PLL ELECTRONICS 1 1 PRODUCT OVERVIEW FEATURES Architecture Integrated system for hand held devices and general embedded applications 16 32 Bit RISC architecture and powerful instruction set with ARM920T CPU core Enhanced ARM architecture MMU to support WinCE EPOC 32 and Linux Instruction cache data cache write buffer and Physical address TAG RAM to reduce the effect of main memory bandwidth and latency on performance ARM920T CPU core supports the ARM debug architecture Internal Advanced Microcontroller Bus Architecture AMBA AMBA2 0 AHB APB System Manager Little Big Endian support Support Fast bus mode and Asynchronous bus mode Address space 128M bytes for each bank total 1G bytes Supports programmable 8 16 32 bit data bus width for each bank Fixed bank start address from bank 0 to bank 6 Programmable bank start address and bank size for bank 7 Eight memory banks Six memory banks for ROM SRAM and others Two memory banks for ROM SRAM Synchronous DRAM Complete Programmable access cycles for all memory banks Supports external wait signals to expand the bus cycle Supports self refresh mode in SDRAM for power down Supports various types of ROM for booting NOR NAND Flash EEPROM and othe
374. into R2 the word found at the address formed by adding 116 to R5 Note that the THUMB opcode will contain 29 as the Offset5 value STRB R1 R0 13 Store the lower 8 bits of R1 at the address formed by adding 13 to RO Note that the THUMB opcode will contain 13 as the Offset5 value ELECTRONICS 4 23 THUMB INSTRUCTION SET S3C2440A RISC MICROPROCESSOR FORMAT 10 LOAD STORE HALFWORD 15 14 13 10 6 5 3 2 0 12 11 ote 2 0 Source Destination Register 5 3 Base Register 10 6 Immediate Value 11 Load Store Flag 0 Store to memory 1 Load from memory Figure 4 11 Format 10 OPERATION These instructions transfer halfword values between a Lo register and memory Addresses are pre indexed using a 6 bit immediate value The THUMB assembler syntax is shown in Table 4 11 Table 4 11 Halfword Data Transfer Instructions Rd lmm STRH Rd lmm Add lmm to base address in Rb and store bits 0 15 of Rd at the resulting address Rb lmm LDRH Rb Imm Add Imm to base address in Rb Load bits 0 15 from the resulting address into Rd and set bits 16 31 to zero NOTE lmm is a full 6 bit address but must be halfword aligned ie with bit 0 set to 0 since the assembler places lmm gt gt 1 in the Offset field 4 24 ELECTRONICS 53 2440 RISC MICROPROCESSOR THUMB INSTRUCTION SET INSTRUCTION CYCLE TIMES All instructions in this format have an
375. is not easy to find a proper PLL value So we recommend referring to the following PLL value recommendation table 96 00 MHz Note 56 0x38 rem NOTE The 48 00MHz and 96MHz output is used for UPLLCON register ELECTRONICS 7 21 CLOCK amp MANAGEMENT S3C2440A RISC MICROPROCESSOR CLOCK CONTROL REGISTER CLKCON CLKCON 0 4 00000 Clock generator control register OxFFFFFO mE ______ _______________ AC97 20 Control PCLK into AC97 block 0 Disable 1 Enable Camera 19 Control HCLK into Camera block 0 Disable 1 Enable 18 Control PCLK into SPI block 0 Disable 1 Enable 17 Control PCLK into IIS block 0 Disable 1 Enable IIC 16 Control PCLK into IIC block 0 Disable 1 Enable ADC amp Touch Screen 15 Control PCLK into ADC block 0 Disable 1 Enable RTG 14 Control PCLK into RTC control block Even if this bit is cleared to 0 RTC timer is alive 0 Disable 1 Enable GPIO 13 Control PCLK into GPIO block 0 Disable 1 Enable UART2 12 Control PCLK into UART2 block 1 0 Disable 1 Enable UART1 11 Control PCLK into UART1 block 1 0 Disable 1 Enable UARTO 10 Control PCLK into UARTO block 1 0 Disable 1 Enable SDI Control PCLK into SDI interface block 0 Disable 1 Enable PWMTIMER Control PCLK into PWMTIMER block 0 Disable 1 Enable USB device 7 Control PCLK into USB dev
376. it 15 and the first bit of each slot in the Data Phase is bit 19 The last bit in any slot is bit 0 ELECTRONICS 24 5 97 CONTROLLER 53 2440 RISC MICROPROCESSOR AC LINK OUTPUT FRAME SDATA OUT e Tag Phase pe Data Phase 1 48kHz mE J 97 samples SYNC assertion here B 2 97 Controller samples first SDATA OUT bit of frame here nin J 11 Valid SDATA OUT POS AEDE END of Audio Frame START of 4 phase Slot 1 END of Data A Slot 12 Figure 24 5 AC link Output Frame AC LINK INPUT FRAME SDATA IN f SYNC AC 97 samples SYNC assertion here AC 97 Controller samples first SDATA bit of frame here Ru MS Codec _ OUT T END of Audio Frame START 9 Data phase END of Data Slot 1 Slot 12 Figure 24 6 AC link Input Frame 24 6 ELECTRONICS 53 2440 RISC MICROPROCESSOR AC97 CONTROLLER AC97 POWERDOWN OJA slot 12 Write to Data slot 12 Figure 24 7 AC97 Powerdown Timing Diagram Powering Down the AC link The AC link signals enter a low power mode when the AC97 CODEC Powerdown register 0x26 bit PR4 is set to 1 i e by writing 0x1000 Then the Primary CODEC drives both the BITCLK SDATA_IN to a logic low voltage level The sequence follows the timing diagram shown above in the Figure 24 7 The AC97 Controller transmits the write to Powerdown register 0x26 o
377. it per pixel 2 bit per pixel 4 bit per pixel and 8 bit per pixel for interfacing with the palletized TFT color LCD panel and 16 bit per pixel and 24 bit per pixel for non palletized true color display The LCD controller can be programmed to support different requirements on the screen related to the number of horizontal and vertical pixels data line width for the data interface interface timing and refresh rate FEATURES STN LCD Displays Supports 3 types of LCD panels 4 bit dual scan 4 bit single scan and 8 bit single scan display type Supports the monochrome 4 gray levels and 16 gray levels Supports 256 colors and 4096 colors for color STN LCD panel Supports multiple screen size Typical actual screen size 640 x 480 320 x 240 160 x 160 and others Maximum virtual screen size is 4Mbytes Maximum virtual screen size in 256 color mode 4096 x 1024 2048 x 2048 1024 x 4096 and others TFT LCD Displays Supports 1 2 4 or 8 bpp bit per pixel palletized color displays for TFT Supports 16 24 bpp non palletized true color displays for color TFT Supports maximum 16M color TFT at 24bit per pixel mode Supports multiple screen size Typical actual screen size 640 x 480 320 x 240 160 x 160 and others Maximum virtual screen size is 4Mbytes Maximum virtual screen size in 64K color mode 2048 x 1024 and others ELECTRONICS 15 1 LCD CONTROLLER S3C2440A RISC MICROPROCESSOR COMMON FEATURES T
378. ith R15 in Transfer List and S Bit Set User Bank Transfer The registers transferred are taken from the User bank rather than the bank corresponding to the current mode This is useful for saving the user state on process switches Base write back should not be used when this mechanism is employed R15 not in List and S Bit Set User Bank Transfer For both LDM and STM instructions the User bank registers are transferred rather than the register bank corresponding to the current mode This is useful for saving the user state on process switches Base write back should not be used when this mechanism is employed When the instruction is LDM care must be taken not to read from a banked register during the following cycle inserting a dummy instruction such as MOV RO RO after the LDM will ensure safety USE OF R15 AS THE BASE R15 should not be used as the base register in any LDM or STM instruction ELECTRONICS 3 43 ARM INSTRUCTION SET 53 2440 RISC MICROPROCESSOR INCLUSION OF THE BASE IN THE REGISTER LIST When write back is specified the base is written back at the end of the second cycle of the instruction During a STM the first register is written out at the start of the second cycle A STM which includes storing the base with the base as the first register to be stored will therefore store the unchanged value whereas with the base second or later in the transfer order will store the modified value A LDM will always overwri
379. ition conversion Touch Screen Interface contains Touch Screen Pads control logic and ADC interface logic with an interrupt generation logic FEATURES Resolution 10 bit Differential Linearity Error 1 0 LSB Integral Linearity Error 2 0158 Maximum Conversion Rate 500 KSPS Low Power Consumption Power Supply Voltage 3 3V Analog Input Range 0 3 3V On chip sample and hold function Normal Conversion Mode Separate X Y position conversion Mode Auto Sequential X Y Position Conversion Mode Waiting for Interrupt Mode ELECTRONICS 16 1 ADC AND TOUCH SCREEN INTERFACE S3C2440A RISC MICROPROCESSOR ADC amp TOUCH SCREEN INTERFACE OPERATION BLOCK DIAGRAM Figure 16 1 shows the functional block diagram of A D converter and Touch Screen Interface Note that the A D converter device is a recycling type ouch Screen ADG Interface amp Touch Screen A D Converter Waiting for Interrupt Mode Figure 16 1 ADC and Touch Screen Interface Functional Block Diagram NOTE symbol When Touch Screen device is used XM or PM is only connected ground for Touch Screen I F When Touch Screen device is not used XM or PM is connecting Analog Input Signal for Normal ADC conversion 16 2 ELECTRONICS 53 2440 RISC MICROPROCESSOR ADC AND TOUCH SCREEN INTERFACE FUNCTION DESCRIPTIONS A D Conversion Time When the GCLK frequency is 50MHz and the prescaler value is 49 tot
380. itions of the SUBSRCPND register corresponding to those set to one in the data The bit positions corresponding to those that are set to 0 in the data remains as they are SUBSRCPND 0X4A000018 R W Indicate the interrupt request status 0x00000000 0 The interrupt has not been requested 1 The interrupt source has asserted the interrupt request 0 Not requested 1 Requested 0 Not requested 1 Requested 0 Not requested 1 Requested 0 Not requested 1 Requested 0 Not requested 1 Requested 0 Not requested 1 Requested Map To SRCPND 1 Requested 1 Requested 1 Requested 1 Requested 1 Requested 1 Requested 1 Requested 1 Requested 1 Requested sme s AT L Wruem 7 INT ADC 5 INT TC INT CAM INT CAM C INT CAM P ERN INT WDT AC97 INT INT AC97 ELECTRONICS 14 17 INTERRUPT CONTROLLER S3C2440A RISC MICROPROCESSOR INTERRUPT SUB MASK INTSUBMSK REGISTER This register has 11 bits each of which is related to an interrupt source If a specific bit is set to 1 the interrupt request from the corresponding interrupt source is not serviced by the CPU note that even in such a case the corresponding bit of the SUBSRCPND register is set to 1 If the mask bit is 0 the interrupt request can be serviced INTSUBMSK 0X4A00001C R W Determine which interrupt source is masked Ox
381. itten into the SPTDATn register SPI starts to transmit if ENSCK of SPCONn register are set You can use a typical programming procedure to operate an SPI card To program the SPI modules follow these basic steps 1 Set Baud Rate Prescaler Register SPPREn 2 Set SPCONn to configure properly the SPI module 3 Write data OxFF to SPTDATn 10 times in order to initialize MMC or SD card 4 Seta GPIO pin which acts as nSS low to activate the MMC or SD card 5 Tx Check the status of Transfer Ready flag 1 and then write data to SPTDATn 6 Rxdata 1 SPCONn s TAGD bit disable normal mode 7 write OXFF to SPTDATn then confirm REDY to set and then read data from Read Buffer 8 Rx data 2 SPCONn s TAGD bit enable Tx Auto Garbage Data mode 9 confirm REDY to set and then read data from Read Buffer then automatically start to transfer 10 Set a GPIO pin which acts as nSS high to deactivate the MMC or SD card FLECTRONICE 22 3 SPI S3C2440A RISC MICROPROCESSOR SPI TRANSFER FORMAT The S3C2440A supports 4 different formats to transfer data Figure 22 2 shows the four waveforms for SPICLK CPOL 0 CPHA 0 Format A Cycle SPICLK MSB of character just received CPOL 0 CPHA 1 Format B Cycle 4 5 7 vs Ms KS wey e Y 5 Y 4 Y 3 Y 2 Y t ie LSB of previously transmitted character CPOL 1 CPHA 0 Format A
382. ive error status interrupt enable bit is set to one in the control register UCONn When a receive error status interrupt request is detected the signal causing the request can be identified by reading the value of UERSTSTn When the receiver transfers the data of the receive shifter to the receive FIFO register in FIFO mode and the number of received data reaches Rx FIFO Trigger Level Rx interrupt is generated If the Receive mode is in control register UCONn and is selected as 1 Interrupt request or polling mode In the Non FIFO mode transferring the data of the receive shifter to receive holding register will cause Rx interrupt under the Interrupt request and polling mode When the transmitter transfers data from its transmit FIFO register to its transmit shifter and the number of data left in transmit FIFO reaches Tx FIFO Trigger Level Tx interrupt is generated if Transmit mode in control register is selected as Interrupt request or polling mode In the Non FIFO mode transferring data from the transmit holding register to the transmit shifter will cause Tx interrupt under the Interrupt request and polling mode If the Receive mode and Transmit mode in control register are selected as the DMAn request mode then DMAn request occurs instead of Rx or Tx interrupt in the situation mentioned above Table 11 1 Interrupts in Connection with FIFO FIFO Mode Non FIFO Mode Rx Interrupt Generated whenever receive data reaches the Generated by the
383. ixels 1 pixel 1 Byte 1 word 4 pixel 176 4 44 word 44 968 2 4 main burst 8 remained burst 4 Example 2 Target image size VGA horizontal Y width 640 pixels 1 pixel 1 Byte 1 word 4 pixel 640 4 2 160 word 16096 162 0 main burst 16 remained burst 16 Example 3 Target image size QCIF horizontal C width 88 pixels 1 pixel 1 Byte 1 word 4 pixel 88 4 22 word 2296422 main burst 4 remained burst 2 HTRANS INCR ELECTRONICS 23 19 53 2440 RISC MICROPROCESSOR CAMERA INTERFACE REGISTER SETTING GUIDE FOR CODEC SCALER AND PREVIEW SCALER SRC_Width and DST_ Width satisfy the word boundary constraints such that the number of horizontal pixel can be represented to kn where n 1 2 3 and k 1 2 8 for 24bppRGB 16bppRGB YCbCr420 image respectively TargetHsize should not be larger than SourceHsize Similarly TargetVsize should not be larger than SourceVsize SourceHsize Original Input TargetHsize xx i SRC Width SourceHsize TargetHsize xx TargetHsize Co or TargetHsize Pr SRC Height SourceVsize DST Width TargetHsize xx B DST Height TargetVsize xx SourceVsize ZISA1 SourceHsize TargetHsize xx SourceVsize XX 9715 19 lt WinHorOtst TargetHsize xx TargetHsize Co TargetHsize Pr Winverotst DST_Width TargetHsize_xx DST Height TargetVsize xx SRC Width SourceHsize 2 x WinHorOfst SRO Height Sour
384. k FCLK 9 15 UART clock FCLK 21 In case of UCON1 UART clock divider 21 where divider gt 0 UCONO UCON2 must zero ex 1 UART clock FCLK 22 2 UART clock FCLK 23 3 UART clock FCLK 24 15 UART clock FCLK 36 In case of UCON2 UART clock divider 36 where gt 0 UCONO UCON1 must be zero ex 1 UART clock FCLK 37 2 UART clock FCLK 38 3 UART clock FCLK 39 7 UART clock FCLK 43 If UCONOO0 1 15 12 and UCON2 14 12 are all 0 the divider will be 44 that is UART clock FCLK 44 Total division range is from 7 to 44 Select PCLK UEXTCLK or FCLK n for the UART baud rate UBRDIVn int selected clock baudrate x 16 1 00 10 PCLK 01 UEXTCLK 11 FCLK n you would select FCLK n you should add the code of NOTE after selecting or deselecting the FCLK n UART 11 11 UART 53 2440 RISC MICROPROCESSOR UART CONTROL REGISTER Continued Interrupt request type 0 Pulse Interrupt is requested as soon as the Tx buffer becomes empty in Non FIFO mode or reaches Tx FIFO Trigger Level in FIFO mode 1 Level Interrupt is requested while Tx buffer is empty in Non FIFO mode or reaches Tx FIFO Trigger Level in FIFO mode Rx Interrupt Type Interrupt request type 0 Pulse Interrupt is requested the instant Rx buffer receives the data in Non FIFO mode or reaches Rx FIFO Trigger Level in FIFO mode 1 Leve
385. k time is used for interrupt request The TICNT register has an interrupt enable bit and the count value for the interrupt The count value reaches 0 when the tick time interrupt occurs Then the period of interrupt is as follows Period 1 128 second Tick time count value 1 127 This RTC time tick may be used for real time operating system RTOS kernel time tick If time tick is generated by the RTC time tick the time related function of RTOS will always synchronized in real time 32 768 2 X TAL CONNECTION EXAMPLE The Figure 17 2 shows a circuit of the RTC unit oscillation at 32 768Khz 15 22pF 32768Hz Figure 17 2 Main Oscillator Circuit Example ELECTRONICS 17 3 REAL TIME CLOCK S3C2440A RISC MICROPROCESSOR REAL TIME CLOCK SPECIAL REGISTERS REAL TIME CLOCK CONTROL RTCCON REGISTER The RTCCON register consists of 4 bits such as the RTCEN which controls the read write enable of the BCD registers CLKSEL CNTSEL and CLKRST for testing RTCEN bit can control all interfaces between the CPU and the RTC so it should be set to 1 in an RTC control routine to enable data read write after a system reset Also before power off the RTCEN bit should be cleared to 0 to prevent inadvertent writing into RTC registers RTCCON 0x57000040 L R W RTC control register 0x0 0x57000043 B by byte CLKRST 3 RTC clock count reset 0 reset 1 Reset CNTSEL 2 BCD count select 0 Merge BC
386. ked 0 enable interrupt 12 masked 9 32 ELECTRONICS 53 2440 RISC MICROPROCESSOR EINTPEND External Interrupt Pending Register EINTPEND 0x560000a8 External interrupt pending register EINTPEND Bit 7 Reset Value M NE EINT21 EINT18 EINT15 12 3 0 0000 EINT9 EINT6 It is cleard by writing 1 0 Not occur 1 Occur interrupt It is cleard by writing 1 0 Not occur 1 Occur interrupt It is cleard by writing 1 0 Not occur 1 Occur interrupt It is cleard by writing 1 0 Not occur 1 Occur interrupt It is cleard by writing 1 0 Not occur 1 Occur interrupt It is cleard by writing 1 0 Not occur 1 Occur interrupt It is cleard by writing 1 0 Not occur 1 Occur interrupt It is cleard by writing 1 0 Not occur 1 Occur interrupt It is cleard by writing 1 0 Not occur 1 Occur interrupt It is cleard by writing 1 0 Not occur 1 Occur interrupt It is cleard by writing 1 0 Not occur 1 Occur interrupt It is cleard by writing 1 0 Not occur 1 Occur interrupt It is cleard by writing 1 0 Not occur 1 Occur interrupt It is cleard by writing 1 0 Not occur 1 Occur interrupt It is cleard by writing 1 0 Not occur 1 Occur interrupt
387. ket of data into the FIFO The USB clears this bit once the packet has been successfully sent to the host An interrupt is generated when the USB clears this bit so the MCU can load the next packet While this bit is set the MCU will not be able to write to the FIFO If the MCU sets SEND STALL bit this bit cannot be set FIFO FLUSH 3 R W CLEAR Set by the MCU if it intends to flush the packet in Input related FIFO This bit is cleared by the USB when the FIFO is flushed The MCU is interrupted when this happens If a token is in process the USB waits until the transmission is complete before FIFO flushing If two packets are loaded into the FIFO only first packet The packet is intended to be sent to the host is flushed and the corresponding IN PKT RDY bit is cleared ELECTRONICS 13 13 USB S3C2440A RISC MICROPROCESSOR END POINT IN CONTROL STATUS REGISTER IN CSR1 REG IN CSR2 REG Continued IN CSR2 REG 0 52000188 1 R W IN END POINT control status register2 0x20 0x5200018B B byte AUTO SET 7 R W If set whenever the MCU writes MAXP data IN PKT RDY will automatically be set by the core without any intervention from MCU If the MCU writes less than MAXP data IN PKT RDY bit has to be set by the MCU ISO R W Used only for endpoints whose transfer type is programmable 1 Reserved 0 Configures endpoint to Bulk mode MODE IN 5 R W Used only for endpoints whose direction is programmable 1 Configur
388. l Interrupt is requested while Rx buffer is receiving data in Non FIFO mode or reaches Rx FIFO Trigger Level in FIFO mode Rx Error Status Enable the UART to generate an interrupt upon an exception such Interrupt Enable as a break frame error parity error or overrun error during a receive operation 0 Do not generate receive error status interrupt 1 Generate receive error status interrupt Loopback Mode 5 Setting loopback bit to 1 causes the UART to enter the loopback mode This mode is provided for test purposes only 0 Normal operation 1 Loopback mode Send Break Setting this bit causes the UART to send a break during 1 frame Signal time This bit is automatically cleared after sending the break signal 0 Normal transmit 1 Send break signal Rx Time Out Enable Disable Rx time out interrupt when UART FIFO is enabled Enable The interrupt is a receive interrupt 0 Disable 1 Enable NOTE You should add following codes after selecting or deselecting the FCLK n rGPHCON rGPHCON amp 3 lt lt 16 GPH8 UEXTCLK input Delay 1 about 100us rGPHCON rGPHCON amp 3 lt lt 16 1 17 GPH8 UEXTCLK UEXTCLK 11 12 ELECTRONICS 53 2440 RISC MICROPROCESSOR UART UART CONTROL REGISTER Continued Determine which function is currently able to write Tx data to the UART transmit buffer register UART Tx Enable Disable 00 Disable 01 Interrupt request or polling mode 10 DMA
389. l data output in the transmit mode and serial data input is shifted to parallel data in the receive mode TRANSMIT OR RECEIVE ONLY MODE Normal Transfer IIS control register has FIFO ready flag bits for transmit and receive FIFOs When FIFO is ready to transmit data the FIFO ready flag is set to 1 if transmit FIFO is not empty If transmit FIFO is empty FIFO ready flag is set to 0 While receiving FIFO is not full the FIFO ready flag for receive FIFO is set to 1 it indicates that FIFO is ready to receive data If receive FIFO is full FIFO ready flag is set to 0 These flags can determine the time that CPU is to write or read FIFOs Serial data can be transmitted or received while the CPU is accessing transmit and receive FIFOs in this way 21 2 ELECTRONICS 53 2440 RISC MICROPROCESSOR IIS BUS INTERFACE DMA TRANSFER In this mode transmit or receive FIFO is accessible by the DMA controller DMA service request in transmit or receive mode is made by the FIFO ready flag automatically TRANSMIT AND RECEIVE MODE In this mode IIS bus interface can transmit and receive data simultaneously AUDIO SERIAL INTERFACE FORMAT IIS BUS FORMAT The IIS bus has four lines including serial data input IISDI serial data output IISDO left right channel select IISLRCK and serial bit clock IISCLK the device generating IISLRCK and IISCLK is the master Serial data is transmitted in 25 complement with the MSB first The MSB is
390. les assume that suitable supervisor code exists for instance 0x08 B Supervisor SWI entry point EntryTable Addresses of supervisor routines ReadC Writel 3 50 DCD ZeroRin DCD ReadCRin DCD WritelRtn Zero EQU 0 EQU 256 EQU 512 Supervisor STMFD R13 RO R2 R14 LDR RO R14 4 BIC 0 0 0 000000 R1 R0 LSR 8 ADR R2 EntryTable LDR R15 R2 R1 LSL 2 WritelRtn eee LDMFD R13 RO R2 R15 4 SWI has routine required in bits 8 23 and data if any in bits 0 7 Assumes R13_svc points to a suitable stack Save work registers and return address Get SWI instruction Clear top 8 bits Get routine offset Get start address of entry table Branch to appropriate routine Enter with character in RO bits 0 7 Restore workspace and return restoring processor mode and flags ELECTRONICS 53 2440 RISC MICROPROCESSOR ARM INSTRUCTION SET COPROCESSOR DATA OPERATIONS CDP The instruction is only executed if the condition is true The various conditions are defined in Table 3 2 The instruction encoding is shown in Figure 3 25 This class of instruction is used to tell a coprocessor to perform some internal operation No result is communicated back to ARM920T and it will not wait for the operation to complete The coprocessor could contain a queue of such instructions awaiting execution and their execution can overlap other activity allowing the coprocessor and ARM920T to perform independent t
391. m a Lo register The THUMB assembler syntax is shown in Table 4 3 NOTE All instructions in this group set the CPSR condition codes Table 4 3 Summary of Format 2 Instructions ADD Rd Rs Rn ADDS Rd Rs Rn Add contents of Rn to contents of Rs Place result in Rd ADD Rd Rs Offset3 ADDS Rd Rs Offset3 Add 3 bit immediate value to contents of Rs Place result in Rd 1 SUB Rd Rs Rn SUBS Rd Rs Rn Subtract contents of Rn from contents of Rs Place result in Rd 1 1 SUB Rd Rs Offset3 SUBS Rd Rs Offset3 Subtract 3 bit immediate value from contents of Rs Place result in Rd ELECTRONICS 4 7 THUMB INSTRUCTION SET 53 2440 RISC MICROPROCESSOR INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 4 3 The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction EXAMPLES ADD RO R3 R4 RO R4 and set condition codes on the result SUB R6 R2 6 R6 R2 6 and set condition codes 4 8 ELECTRONICS 53 2440 RISC MICROPROCESSOR THUMB INSTRUCTION SET FORMAT 3 MOVE COMPARE ADD SUBTRACT IMMEDIATE 15 14 13 7 0 12 11 10 8 Popo T 7 0 Immediate Vale 10 8 Source Destination Register 12 11 Opcode 0 MOV 1 2 ADD 3 SUB Figure 4 4 Format 3 OPERATIONS The instructions in this group perform operations between a Lo register and an 8 bit i
392. m clocks by software for the reduction of power consumption in the S3C2440A These schemes are related to PLL clock control logics HCLK and PCLK and wakeup signals Figure 7 7 shows the clock distribution of the S8C2440A The S3C2440A has four power modes The following section describes each power management mode transition between the modes is not allowed freely Please see Figure 7 8 for available transitions among the modes Clock Control Register ARM920T MEMCNTL FCLK HCLK Input Clock Power p Management PCLK UPLL 96 48 MHz INTCNTL BUSCNTL ARB DMA ExtMaster FCLK defination LCDCNTL If SLOW mode FCLK input clock divider ratio Nand Flash Controller If Normal mode P M amp S value MPLL clock MPLLin Camera T c 0 UJ a c 0 00 Figure 7 7 The Clock Distribution Block Diagram 7 10 ELECTRONICS 53 2440 RISC MICROPROCESSOR CLOCK amp POWER MANAGEMENT IDLE_BIT 1 Interrupts EINT 0 23 RTC alarm EINT 15 0 RTC alarm NORMAL SLOW BIT 0 SLOW LOW BIT 1 SLOW SLEEP BIT 1 Figure 7 8 Power Management State Diagram Table 7 2 Clock and Power State in Each Power Mode ARM920T AHB Modules 1 Power 32 768kHz APB Modules 2 p ME ES clock amp USBH LCD NAND INORMAL BEL Ls pos SLEEP 00 22 for wake up event state NOTES 1 USB host LCD and NAND are excluded
393. mmediate value The THUMB assembler syntax is shown in Table 4 4 NOTE All instructions in this group set the CPSR condition codes Table 4 4 Summary of Format 3 Instructions 00 MOV Rd sOffset8 MOVS Rd Offset8 Move 8 bit immediate value into Rd CMP Rd Offset8 CMP Rd Offset8 Compare contents of Rd with 8 bit immediate value 10 ADD Ra Offset8 ADDS Offset8 Add 8 bit immediate value to contents of Rd and place the result in Rd 11 SUB Offset8 SUBS Rd Rd Offset8 Subtract 8 bit immediate value from contents of Rd and place the result in Rd ELECTRONICS 4 9 THUMB INSTRUCTION SET 53 2440 RISC MICROPROCESSOR INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 4 4 The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction EXAMPLES MOV RO 44128 128 and set condition codes CMP R2 62 Set condition codes on R2 62 ADD R1 4255 R1 R1 255 and set condition codes SUB R6 145 R6 145 and set condition codes 4 10 ELECTRONICS 53 2440 RISC MICROPROCESSOR THUMB INSTRUCTION SET FORMAT 4 ALU OPERATIONS 15 14 13 9 6 5 32 0 12 11 10 _ re 2 0 Source Destination Register 5 3 Source Register 2 9 6 Opcode Figure 4 5 Format 4 OPERATION The following instructions perform ALU operations on a Lo register
394. n words RGB Order Lom mm mes mos ms Red 1 Green 1 Blue 1 Red 2 Blue 2 Red 3 Green 3 Red 4 Blue 4 Red 5 Green 5 Blue 5 Red 6 Green 6 Blue 6 ELECTROUNICS 15 11 LCD CONTROLLER S3C2440A RISC MICROPROCESSOR 4 bit Dual Scan Display 4 bit Single Scan Display 8 bit Single Scan Display Figure 15 2 Monochrome Display Types STN 15 12 ELECTRONICS 53 2440 RISC MICROPROCESSOR LCD CONTROLLER VD3 VD2 VD1 VD0 VD3 VD2 VD1 VD0 R1 G1 B1 R2 G2 B2 R3 G3 1 Pixel VD7 VD6 VD5 VD4 VD7 VD6 VD5 VD4 R1 G1 B1 R2 G2 B2 R3 G3 4 bit Dual Scan Display VD3 VD2 VD1 VDO VD2 VD1 VDO Ri G1 B1 R2 G2 B2 1 Pixel 4 bit Single Scan Display VD7 VD6 05 VD4 VD3 VD2 VD1 VDO R1 G1 B1 R2 G2 B2 R3 G3 1 Pixel 8 bit Single Scan Display Figure 15 3 Color Display Types STN ELECTRONICS 15 13 LCD CONTROLLER S3C2440A RISC MICROPROCESSOR Timing Requirements Image data should be transferred from the memory to the LCD driver using the VD 7 0 signal VCLK signal is used to clock the data into the LCD driver s shift register After each horizontal line of data has been shifted into the LCD driver s shift register the VLINE signal is asserted to display the line on the panel The VM signal provides an AC signal for the display The LCD uses the signal to altern
395. nable 0 Disable 1 Enable MINEN 1 Minute alarm enable 0 Disable 1 Enable Second alarm enable 0 Disable 1 Enable ELECTRONICS 17 5 REAL CLOCK S3C2440A RISC MICROPROCESSOR ALARM SECOND DATA ALMSEC REGISTER ALMSEC 0x57000054 L R W Alarm second data register 0x0 0x57000057 B by byte fm OSS SECDATA 6 4 BCD value for alarm second 0 5 ao ALARM MIN DATA ALMMIN REGISTER ALMMIN 0x57000058 L R W Alarm minute data register 0x00 0x5700005B B by byte mew SSCS MINDATA 6 4 BCD value for alarm minute 0 5 ao ALARM HOUR DATA ALMHOUR REGISTER ALMHOUR 0x5700005C L R W Alarm hour data register 0x0 0x5700005F B by byte ga ____ HOURDATA 5 4 BCD value for alarm hour po 0 2 Em soo 17 6 ELECTRONICS 53 2440 RISC MICROPROCESSOR REAL TIME CLOCK ALARM DATE DATA ALMDATE REGISTER ALMDATE 0x57000060 L R W Alarm date data register 0x01 0x57000063 B by byte 7 0 p 9 DATEDATA 5 4 BCD value for alarm date from 0 to 28 29 30 31 EN 0 3 Em 0 ALARM MON DATA ALMMON REGISTER ALMMON 0x57000064 L R W Alarm month data register 0x01 0x57000067 B by byte e BCD value for alarm month 0 1 MONDATA 4 EE 0 ALARM YEAR DATA REGISTER ALMYEAR 0x57000068 L R W Alarm year data register 0x0 0x5700006B B b
396. nding Table 4 15 PUSH and POP Instructions PUSH Rlist STMDB R13 Rlist Push the registers specified by Rlist onto the stack Update the stack pointer 1 PUSH Rlist LR STMDB 13 Push the Link Register and the registers Rlist R14 specified by Rlist if any onto the stack Update the stack pointer 1 POP Rlist R13 Rlist Pop values off the stack into the registers specified by Rlist Update the stack pointer 1 1 POP Rlist PC LDMIA R13 Rlist R15 Pop values off the stack and load into the registers specified by Rlist Pop the PC off the stack Update the stack pointer ELECTRONICS 4 31 THUMB INSTRUCTION SET 53 2440 RISC MICROPROCESSOR INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 4 15 The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction EXAMPLES PUSH RO R4 LR Store RO R1 R2 R3 R4 and R14 LR at the stack pointed to by R13 SP and update R13 Useful at start of a sub routine to save workspace and return address POP R2 R6 PC Load R2 R6 and R15 PC from the stack pointed to by R13 SP and update R13 Useful to restore workspace and return from sub routine 4 32 ELECTRONICS 53 2440 RISC MICROPROCESSOR THUMB INSTRUCTION SET FORMAT 15 MULTIPLE LOAD STORE 15 14 13 7 0 12 11 10 8 e 7 0 Register List 10 8
397. ndpoint DMA transfer counter high Ox214 L Ox217 B byte register EP2 DMA CON Endpoint2 DMA control register 0 218 1 0 21 ELECTRONICS 13 3 USB S3C2440A RISC MICROPROCESSOR USB DEVICE CONTROLLER SPECIAL REGISTERS Continued Register Name EP2 UNIT EP2 DMA FIFO EP2 TTC EP2 DMA TTC M EP2 DMA TTC H EP3 DMA CON EP3 DMA UNIT EP3 DMA FIFO EP3 DMA TTC L EP3 DMA TTC M EP3 DMA TTC H 4 DMA CON 4 UNIT 4 4 TTC L 4 TTC M 4 TTC Common Indexed Registers MAXP REG In Indexed Registers IN CSR1 REG EPO CSR IN CSR2 REG Out Indexed Registers OUT CSR1 REG OUT CSR2 REG OUT FIFO CNT1 REG OUT FIFO CNT2 REG Endpoint2 DMA unit counter register 0x21C L 0 21 Endpoint2 FIFO counter register 0 220 1 0x223 B Endpoint2 DMA transfer counter low 0x224 L 0x227 B byte register Endpoint2 DMA transfer counter 0x228 L 0 22 middle byte register Endpoint2 transfer counter high Ox22C L 0 22 byte register Endpoint3 DMA control register 0x240 L 0x243 B Endpoint3 DMA unit counter register 0x244 L 0x247 B Endpoint3 DMA FIFO counter register 0 248 1 0x24B B Endpoint3 DMA transfer counter low 0x24C L Ox24F B byte register Endpoint3 DMA transfer counter high OX254 L 0x247 B byte register Endpoint4 DMA control register 0
398. neral input output ports some ports are output only TIMMER PWM O Timeroutput 3 0 TCLK 1 0 External timer clock input JTAG TEST LOGIC nTRST nTRST TAP Controller Reset resets the TAP controller at start If debugger is used A 10K pull up resistor has to be connected If debugger black ICE is not used nTRST pin must be issued by a low active pulse Typically connected to nRESET Controller Mode Select controls the sequence of the controller s r A 10K pull up resistor has to be connected to TMS pin TCK TAP Controller Clock provides the clock input for the JTAG logic A pull up resistor must connected to pin Controller Data Input is the serial input test instructions and A io pull up resistor must be connected to TDI pin TDO TAP Controller Data Output is the serial output for test instructions and data ELECTRONICS 1 23 PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR Table 1 3 S3C2440A Signal Descriptions Sheet 5 of 6 Continued Reset Clock amp Power XTOpll AO Crystal Output for internal osc circuit When 3 2 00b is used for MPLL CLK source and UPLL CLK Source When OM 3 2 01b XTIpll is used for MPLL CLK source only When 3 2 10b is used for UPLL CLK source only If it isn t used it has to be a floating pin 32 kHz crystal input for RTC If it isn t used it has to be High
399. ng conversion of X position and Y position 0 Normal ADC conversion 1 Sequencing measurement of X position Y position XY PST 13 12 Manually measurement of X position or Y position 00 No operation mode 01 X position measurement 10 Y position measurement 11 for interrupt mode Reserve YPDATA NNI position conversion data value Data value 0 ADC TOUCH SCREEN UP DOWN INT CHECK REGISTER ADCUPDN ADCUPDN 0x5800014 Stylus up or down interrupt status register 0x0 TSC UP 1 Stylus Up Interrupt 0 No stylus up status 1 Stylus up interrupt occurred TSC DN Stylus Down Interrupt 0 No stylus down status 1 Stylus down interrupt occurred ELECTRONICS 16 9 ADC AND TOUCH SCREEN INTERFACE S3C2440A RISC MICROPROCESSOR NOTES 16 10 ELECTRONICS 53 2440 RISC MICROPROCESSOR REAL TIME CLOCK REAL TIME CLOCK OVERVIEW The Real Time Clock RTC unit can be operated by the backup battery while the system power is off The RTC can transmit 8 bit data to CPU as Binary Coded Decimal BCD values using the STRB LDRB ARM operation The data include the time by second minute hour date day month and year The RTC unit works with an external 32 768kHz crystal and also can perform the alarm function FEATURES BCD number second minute hour date day month and year Leap year generator Alarm function alarm interrupt wake up from power off mode Year 2000 pro
400. ng depends on only input FIFOs so the system bus should be not busy in this mode ScaleUpDown Co 30 29 Scale up down flag for codec scaler In 1 1 scale ratio this bit should be 1 00 Down 11 Up MainHorRatio Co 24 16 Horizontal scale ratio for codec main scaler CoScalerStart 15 Codec scaler start MainVerRatio Co Vertical scale ratio for codec main scaler CODEC DMA TARGET AREA REGISTER CICOTAREA Ox4F00005C Codec scaler target area CICOTAREA Bit Description CICOTAREA 25 0 Target area for codec Target H size x Target V size Initial State 23 22 ELECTRONICS 53 2440 RISC MICROPROCESSOR CAMERA INTERFACE CODEC STATUS REGISTER CICOSTATUS 0 4 000064 R path status tel Stat ovo overiow siate of codec sowo o VSYNC 28 Camera VSYNC This bit can be referred by CPU for first SFR setting And it can be seen in the ITU R BT 656 mode too FrameCnt_Co 27 26 Frame count of codec DMA This counter value indicates the next frame number WinOfstEn_Co 25 Window offset enable status _ Flip mode of ImgCptEn Image capture enable of camera interface ImgCptEn CoSC Image capture enable of codec path RGB1 START ADDRESS REGISTER CIPRCLRSA1 Ox4F00006C RGB 15 frame start address for preview DMA CIPRCLRSA1 31 0 RGB 15 frame start address for preview RGB2
401. ng for Interrupt Mode Touch Screen Controller generates interrupt INT TC signal when the Stylus is down Waiting for Interrupt Mode setting value is rADCTSC 0xd3 XP PU XP Dis XM Dis Dis YM En After Touch Screen Controller generates interrupt signal INT Waiting for interrupt Mode must be cleared XY PST sets to the No operation Mode Standby Mode Standby mode is activated when ADCCON 2 is set to 1 In this mode A D conversion operation is halted and ADCDATO ADCDAT register contains the previous converted data ELECTRONICS 16 3 ADC AND TOUCH SCREEN INTERFACE S3C2440A RISC MICROPROCESSOR Programming Notes 1 The A D converted data can be accessed by means of interrupt or polling method With interrupt method the overall conversion time from A D converter start to converted data read may be delayed because of the return time of interrupt service routine and data access time With polling method by checking the ADCCON 15 end of conversion flag bit the read time from ADCDAT register can be determined 2 Another way for starting A D conversion is provided After ADCCON 1 A D conversion start by read mode is set to 1 A D conversion starts simultaneously whenever converted data is read X Conversion Y Conversion 1 1 Figure 16 2 ADC and Touch Screen Operation signal 16 4 ELECTRONICS 53 2440 RISC MICROPROCESSOR ADC AND TOUCH SCREEN INTERFACE ADC AND TOUCH SCREE
402. not generate any error interrupt because the character which is received with an error would have not been read The error interrupt will occur once the character is read Figure 11 3 shows the UART receiving the five characters including the two errors Sequence Fiow 2 AfterAisreadout frame error interrupt occurs The B has to be read out 3 AtterBisreadout EN EM 0 1 2 3 4 5 6 After C is read out The parity error in D interrupt occurs The D has to be read out After D is read out p eu Error Status FIFO break error parity error rame error Figure 11 3 Example showing UART Receiving 5 Characters with 2 Errors 11 6 ELECTRONICS 53 2440 RISC MICROPROCESSOR UART Baud rate Generation Each UART s baud rate generator provides the serial clock for the transmitter and the receiver The source clock for the baud rate generator can be selected with the S8C2440A s internal system clock or UEXTCLK In other words dividend is selectable by setting Clock Selection of UCONn The baud rate clock is generated by dividing the source clock PCLK FCLK n or UEXTCLK by 16 and a 16 bit divisor specified in the UART baud rate divisor register UBRDIVn The UBRDIVn can be determined by the following expression UBRDIVn int UART clock buad rate x 16 1 UART clock PCLK FCLK n or UEXTCLK
403. nses 17 8 BCD Minute BCDMIN mH enne n ener nhe nnn enne 17 8 BCD Hour BCDHOUR uN uuu aqu ea 17 8 BCD Date BCDDATE Register viii 17 9 BCD Day BCDDAY a 17 9 BCD Month BCDMON Tae 17 9 BCD Year BCDYEAR Register 17 10 Chapter 18 Watchdog Timer era RI 18 1 gc hag ole edie beg Su La es ee ae dt eee 18 1 Watchdog Timer u 18 2 18 2 Consideration of Debugging Environment 18 2 Watchdog Timer Special 18 3 Watchdog Timer Control WTCON 18 3 Watchdog Timer Data WTDAT 18 4 Watchdog Timer Count WTCNT Register a 18 4 xvi 53 2440 MICROCONTROLLER Table of Contents Continued Chapter 19 MMC SD SDIO Controller Features sob eoo o eaa aeo ud doter doe ua Qu Block Diagratn x i se oe ce E EE EE ER eI SD Operation sce T
404. ntroller located between the system bus and the peripheral bus Each channel of controller can perform data movements between devices in the system bus and or peripheral bus with no restrictions In other words each channel can handle the following four cases 1 Both source and destination in the system bus The source is in the system bus while the destination is in the peripheral bus The source is in the peripheral bus while the destination is in the system bus Both source and destination are in the peripheral bus The main advantage of the DMA is that it can transfer the data without CPU intervention The operation of DMA can be initiated by software or requests from internal peripherals or external request pins ELECTRONICS 8 1 S3C2440A RISC MICROPROCESSOR DMA REQUEST SOURCES Each channel of the controller can select one of the request source among four sources if H W request mode is selected by DCON register Note that if S W request mode is selected this request sources have no meaning at all Table 8 1 shows four DMA sources for each channel Table 8 1 DMA Request Sources for Each Channel Soureet Souree2 Sources Sources Sources Sources Here nXDREQO and nXDREQ1 represent two external sources External Devices and 125500 and 125501 represent IIS transmitting and receiving respectively DMA OPERATION DMA uses thre
405. o Oo I E Or GOOD OU OI D eo o QOO O SW OO 06000000 QUO OQ QD OOOO QU OO OOO QU IR QUO Qc OOOO OO quU X QUO OD OG XD Du DX X CODO ODO CQ Qt DO OE OO e QUO X OO OU X D DD ID DD OD SO 00 12 13 14 15 16 17 10 11 VIEW Figure 1 2 S3C2440A Pin Assignments 289 FBGA ELECTRONICS 53 2440 RISC MICROPROCESSOR PRODUCT OVERVIEW Table 1 1 289 Pin FBGA Pin Assignments Pin Number Order Sheet 1 of 3 Ee EM EN EN ew DAT nFRE GPA20 VSSMOP nGCS7 0 A vssi vssmoP S 660 vssmop ADDR4 ADDR10 ADDR11 ADDR6 VDDMOP ADDR15 ADDR14 2 ADDR23 GPA8 SRAS i C En 5 k k DATA1 E12 DATA20 m 5 gt 5 gt O gt 8 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 17 F1 F2 F3 F4 F5 F6 F7 F8 F9 10 11 DATA24 VSSMOP ALE GPA18 VDDi nGCS1 GPA12 nGCS6 VSSi A _ 57 EM 08 nacsaiapais F9 nFWE GPAI9 F4 nFOE GPA22 mE 0 CLEGPAI7 vopmop nscas Fe OE EN
406. o a 1 These instructions should not be used as their action may change in future ARM implementations INSTRUCTION SUMMARY Table 3 1 The ARM Instruction Set Mmemonc 8 femm 0 CDP Coprocessor specific EOR Rd Rn AND NOT OR Op2 AND NOT Hn LDM Stack manipulation Pop MCR Move CPU register to coprocessor cRn rRn lt gt register MLA Multiply accumulate Rm x Rs 3 2 ELECTRONICS 53 2440 RISC MICROPROCESSOR ARM INSTRUCTION SET Table 3 1 The ARM Instruction Set Continued Move from coprocessor register to Rn cRn lt op gt cRm CPU register om o STM Stack manipulation Push sw Swe ELECTRONICS 3 3 ARM INSTRUCTION SET 53 2440 RISC MICROPROCESSOR THE CONDITION FIELD In ARM state all instructions are conditionally executed according to the state of the CPSR condition codes and the instruction s condition field This field bits 31 28 determines the circumstances under which an instruction is to be executed If the state of the C N Z and V flags fulfils the conditions encoded by the field the instruction is executed otherwise it is ignored There are sixteen possible conditions each represented by a two character suffix that can be appended to the instruction s mnemonic For example a Branch B in assembly language becomes BEQ for Branch if Equal which means the Branch will only be taken if the Z flag
407. o described in PRODUCT INFORMATION SPEC of LTS350Q1 PD1 2 and PE1 2 Refer to the documentation PRODUCT INFORMATION of LTS350Q1 PD1 2 and PE1 2 which is prepared by AMLCD Technical Customer Center of Samsung Electronics Co LTD Caution S3C2440A has HCLK working as the clock of AHB bus SEC TFT LCD panel LTS350Q1 PD1 2 and PE1 2 has Horizontal Sampling Clock HCLK These two HCLKs may cause a confusion So note that HCLK of the S3C2440A is HCLK and other HCLK of the LTS350 is LCD HCLK Check that the HCLK of SEC TFT LCD panel LTS350Q1 PD1 2 and PE1 2 is changed to LCD HCLK 15 24 ELECTRONICS 53 2440 RISC MICROPROCESSOR LCD CONTROLLER VIRTUAL DISPLAY TFT STN The S3C2440A supports hardware horizontal or vertical scrolling If the screen is scrolled the fields of LCDBASEU LCDBASEL in LCDSADDR 1 2 registers need to be changed see Figure 15 8 except the values of PAGEWIDTH and OFFSIZE The video buffer in which the image is stored should be larger than the LCD panel screen in size PAGEWIDTH OFFSIZE This is the data of line 1 of virtual screen This is the ddta of line 2 of virtual screen This is the d ta of line 3 of virtual screen This is the ddta of line 4 of virtual screen LINEVAL 1 This is the d ta of line 5 of virtual screen This is the d ta of line 6 of virtual screen This is the data of line irtual screen This is the data of line 8 of virtual screen View Port This
408. ock time automatically Figure 7 11 Issuing Exit from Slow mode Command and the Instant PLL on Command Simultaneously 7 14 ELECTRONICS 53 2440 RISC MICROPROCESSOR CLOCK amp POWER MANAGEMENT SLEEP Mode The block disconnects the internal power So there occurs no power consumption due to CPU and the internal logic except the wake up logic in this mode Activating the SLEEP mode requires two independent power sources One of the two power sources supplies the power for the wake up logic The other one supplies other internal logics including CPU and should be controlled for power on off In the SLEEP mode the second power supply source for the CPU and internal logics will be turned off The wakeup from SLEEP mode can be issued by the EINT 15 0 or by RTC alarm interrupt Follow the Procedure to Enter SLEEP mode 1 Setthe GPIO configuration adequate for SLEEP mode 2 Mask all interrupts in the INTMSK register 3 Configure the wake up sources properly including RTC alarm The bit of EINTMASK corresponding to the wake up source has not to be masked in order to let the corresponding bit of SRCPND or EINTPEND set Although a wake up source is issued and the corresponding bit of EINTMASK is masked the wake up will occur and the corresponding bit of SRCPND or EINTPEND will not be set Set USB pads as suspend mode MISCCR 13 12 1 1b Save some meaning values into GSTATUS 4 3 register These register are preserved during SLEEP mode
409. ogram Status Registers 4 banked register Figure 2 4 Register Organization in THUMB state ELECTRONICS 2 5 PROGRAMMER S MODEL 53 2440 RISC MICROPROCESSOR The relationship between ARM and THUMB state registers The relationship between ARM and THUMB state registers are as below e THUMB state RO R7 and ARM state RO R7 are identical e THUMB state CPSR and SPSRs and ARM state CPSR and SPSRs are identical e THUMB state SP maps onto ARM state R13 e THUMB state LR maps onto ARM state R14 The THUMB state Program Counter maps onto the ARM state Program Counter R15 This relationship is shown in Figure 2 5 THUMB State ARM State Lo Registers Hi Registers Program Counter PC CPSR SPSR ro r1 r2 r3 r4 r5 r6 r7 r11 Stack Pointer Stack Pointer r13 Z s SP PC Figure 2 5 Mapping of THUMB State Registers onto ARM State Registers 2 6 ELECTRONICS 53 2440 RISC MICROPROCESSOR PROGRAMMER S MODEL Accessing Hi Registers in THUMB State In THUMB state registers R8 R15 Hi registers are not part of the standard register set However the assembly language programmer has limited access to them and can use them for fast temporary storage A value may be transferred from a register in the range RO R7 a Lo register to a Hi register and from a Hi register to a Lo register using special variants of the MOV instruction Hi register values can also
410. ollowing equation to calculate the watchdog timer clock frequency and the duration of each timer clock Cycle t watchdog 1 PCLK Prescaler value 1 Division factor WTDAT amp WTCNT Once the watchdog timer is enabled the value of watchdog timer data WTDAT register cannot be automatically reloaded into the timer counter WTCNT In this reason an initial value must be written to the watchdog timer count WTCNT register before the watchdog timer starts CONSIDERATION OF DEBUGGING ENVIRONMENT When the S3C2440A is in debug mode using Embedded ICE the watchdog timer must not operate The watchdog timer can determine whether or not it is currently in the debug mode from the CPU core signal DBGACK signal Once the DBGACK signal is asserted the reset output of the watchdog timer is not activated as the watchdog timer is expired 18 2 ELECTRONICS 53 2440 RISC MICROPROCESSOR WATCHDOG TIMER WATCHDOG TIMER SPECIAL REGISTERS WATCHDOG TIMER CONTROL WTCON REGISTER The WTCON register allows the user to enable disable the watchdog timer select the clock signal from 4 different sources enable disable interrupts and enable disable the watchdog timer output The Watchdog timer is used to resume the S3C2440A restart on mal function after its power on if controller restart is not desired the Watchdog timer should be disabled If the user wants to use the normal timer provided by the Watchdog timer enable the interrupt and
411. olute Value TEQ Rn 0 RSBMI Rn Rn 0 Multiplication by 4 5 or 6 Run Time MOV Rc Ra LSL 2 CMP Rb 5 ADDCS Rc Rc Ra ADDHI Combining Discrete and Range Tests TEQ 127 1 MOVLS Rc ELECTRONICS If Rn p OR Rm q THEN GOTO Label If condition not satisfied try other test Test sign and 2 s complement if necessary Multiply by 4 Test value Complete multiply by 5 Complete multiply by 6 Discrete test Range test IF lt OR Rc ASCII 127 THEN 3 59 ARM INSTRUCTION SET 53 2440 RISC MICROPROCESSOR Division and Remainder A number of divide routines for specific applications are provided in source form as part of the ANSI C library provided with the ARM Cross Development Toolkit available from your supplier A short general purpose divide routine follows Enter with numbers in Ra and Rb MOV Rcnt 1 Bitto control the division Div1 CMP Rb 0x80000000 Move Rb until greater than Ra CMPCC Rb Ra MOVCC Rb Rb ASL 1 MOVCC Rent Rent ASL 1 BCC Div1 MOV Rc 0 Div2 CMP Ra Rb Test for possible subtraction SUBCS Ra Ra Rb Subtract if ok ADDCS Rc Rc Rcnt Putrelevant bit into result MOVS Rent Rent 5841 Shift control bit MOVNE Rb Rb LSR 1 Halve unless finished BNE Div2 Divide result in Rc remainder in Ra Overflow Detection in the ARM920T 1 Overflow in unsigned multiply with a 32 bit result UMULL Rd Rt Rm Rn 3106 cycl
412. on Note that the content of the WTDAT register cannot be automatically loaded into the timer count register when the watchdog timer is enabled initially so the WTCNT register must be set to an initial value before enabling it WTCNT 0x53000008 Watchdog timer count register 0x8000 Count value 15 0 The current count value of the watchdog timer 0x8000 8 4 ELECTRONICS 53 2440 RISC MICROPROCESSOR MMC SD SDIO CONTROLLER MMC SD SDIO CONTROLLER FEATURES SD Memory Card Spec ver 1 0 MMC Spec 2 11 compatible SDIO Card Spec Ver 1 0 compatible 16 words 64 bytes FIFO for data Tx Rx 40 bit Command Register 136 bit Response Register 8 bit Prescaler logic Freq System Clock P 1 Normal data transfer mode byte halfword word transfer DMA burst4 access support only word transfer 1 bit 4 bit wide bus mode amp block stream mode switch support BLOCK DIAGRAM CMD Reg CMD Control bbyte PADDR 8bit Shift Reg Resp Reg 7 PSEL 17byte PCLK DAT Control PWDATA 31 0 8bit Shift Reg PRDATA CRC16 4 RxDAT 3 0 31 0 DREQ DACK INT Figure 19 1 SD Interface block diagram ELECTRONICS 50 50 CONTROLLER 53 2440 RISC MICROPROCESSOR SD OPERATION A serial clock line synchronizes shifting and sampling of the information on the five data lines The transmission frequency is controlled by making the appropriate bit
413. on by the user a fully protected operating system may be constructed RETURN FROM THE SUPERVISOR The PC is saved in R14 svc upon entering the software interrupt trap with the PC adjusted to point to the word after the SWI instruction MOVS PC R14 svc will return to the calling program and restore the Note that the link mechanism is not re entrant so if the supervisor code wishes to use software interrupts within itself it must first save a copy of the return address and SPSR COMMENT FIELD The bottom 24 bits of the instruction are ignored by the processor and may be used to communicate information to the supervisor code For instance the supervisor may look at this field and use it to index into an array of entry points for routines which perform the various supervisor functions INSTRUCTION CYCLE TIMES Software interrupt instructions take 2S 1N incremental cycles to execute where S and are defined as sequential S cycle and non sequential N cycle ELECTRONICS 3 49 ARM INSTRUCTION SET 53 2440 RISC MICROPROCESSOR ASSEMBLER SYNTAX SWI cond expression cond Two character condition mnemonic Table 3 2 expression Evaluated and placed in the comment field which is ignored by ARM920T Examples SWI ReadC Get next character from read stream SWI Writel k Output a k to the write stream SWINE 0 Conditionally call supervisor with 0 in comment field Supervisor code The previous examp
414. on vector addresses Table 2 3 Exception Vectors abort da ELECTRONICS 2 13 PROGRAMMER S MODEL 53 2440 RISC MICROPROCESSOR Exception Priorities When multiple exceptions arise at the same time a fixed priority system determines the order in which they are handled Highest priority 1 Reset 2 Data abort 3 FIQ 4 IRQ 5 Prefetch abort Lowest priority 6 Undefined Instruction Software interrupt Not Exceptions Can Occur at Once Undefined Instruction and Software Interrupt are mutually exclusive since they each correspond to particular non overlapping decodings of the current instruction If a data abort occurs at the same time as a FIQ and FlQs are enabled ie the CPSR s F flag is clear ARM920T enters the data abort handler and then immediately proceeds to the FIQ vector A normal return from FIQ will cause the data abort handler to resume execution Placing data abort at a higher priority than FIQ is necessary to ensure that the transfer error does not escape detection The time for this exception entry should be added to worst case FIQ latency calculations 2 14 ELECTRONICS 53 2440 RISC MICROPROCESSOR PROGRAMMER S MODEL INTERRUPT LATENCIES The worst case latency for FIQ assuming that it is enabled consists of the longest time the request can take to pass through the synchronizer Tsyncmax if asynchronous plus the time for
415. onal relationships among these operating modes are described below START AND STOP CONDITIONS When the interface is inactive it is usually in Slave mode In other words the interface should be in Slave mode before detecting a Start condition on the SDA line a Start condition can be initiated with a High to Low transition of the SDA line while the clock signal of SCL is High When the interface state is changed to Master mode a data transfer on the SDA line can be initiated and SCL signal generated A Start condition can transfer a one byte serial data over the SDA line and a Stop condition can terminate the data transfer A Stop condition is a Low to High transition of the SDA line while SCL is High Start and Stop conditions are always generated by the master The gets busy when a Start condition is generated A Stop condition will make the free When a master initiates a Start condition it should send a slave address to notify the slave device One byte of address field consists of a 7 bit address and a 1 bit transfer direction indicator showing write or read If bit 8 is 0 it indicates a write operation transmit operation if bit 8 is 1 it indicates a request for data read receive operation The master will complete the transfer operation by transmitting a Stop condition If the master wants to continue the data transmission to the bus it should generate another Start condition as well as a slave
416. ondition a above Just after the wake up the corresponding EINTn pin will not be used for wakeup This means that the pin can be used as an external interrupt request pin again Entering IDLE Mode If CLKCON 2 is set to 1 to enter the IDLE mode the 53 2440 will enter IDLE mode after some delay until the power control logic receives ACK signal from the CPU wrapper PLL On Off The PLL can only be turned off for low power consumption in slow mode If the PLL is turned off in any other mode MCU operation is not guaranteed When the processor is in SLOW mode and tries to change its state into other state with the PLL turned on then SLOW BIT should be clear to move to another state after PLL stabilization Pull up Resistors on the Data Bus and SLEEP Mode In SLEEP mode the data bus D 31 0 or D 15 0 can be selected as Hi z state and Output Low state The data bus can be set as Hi z status with turning on pull up register or can be set as output low with turning off pull up register for low power consumption in SLEEP mode D 31 0 pin pull up resistors can be controlled by the GPIO control register MISCCR However if there is an external bus holder such as 74LVCH162245 on the data bus User can select one of two status one is output low with pull up off the other is Hi z with pull up off which consumes less power 7 18 ELECTRONICS 53 2440 RISC MICROPROCESSOR CLOCK amp POWER MANAGEMENT Output Port State and SLEEP
417. ondition code flags in the CPSR may be updated from the ALU flags as described above When Rd is R15 and the S flag in the instruction is not set the result of the operation is placed in R15 and the CPSR is unaffected When Rd is R15 and the S flag is set the result of the operation is placed in R15 and the SPSR corresponding to the current mode is moved to the CPSR This allows state changes which automatically restore both PC and CPSR This form of instruction should not be used in User mode USING R15 AS AN OPERANDY If R15 the PC is used as an operand in a data processing instruction the register is used directly The PC value will be the address of the instruction plus 8 or 12 bytes due to instruction prefetching If the shift amount is specified in the instruction the PC will be 8 bytes ahead If a register is used to specify the shift amount the PC will be 12 bytes ahead TST CMP AND CMN OPCODES NOTE TST and do not write the result of their operation but do set flags in the CPSR An assembler should always set the S flag for these instructions even if this is not specified in the mnemonic The TEQP form of the TEQ instruction used in earlier ARM processors must not be used the PSR transfer operations should be used instead The action of TEQP in the ARM920T is to move SPSR mode to the CPSR if the processor is in a privileged mode and to do nothing if in User mode INSTRUCTION CYCLE TIMES
418. onfigured detects start signal and IICDS receives data IIC compares IICADD and IICDS the received slave address mec Y The IIC address match interrupt is generated Write data to IICDS Clear pending bit to resume N The data of the IICDS is shifted to SDA Interrupt is pending Figure 20 8 Operations for Slave Transmitter Mode ELECTRONICS 20 9 IIC BUS INTERFACE 53 2440 RISC MICROPROCESSOR Slave Rx mode has been configured detects start signal and IICDS receives data IIC compares IICADD and IICDS the received slave address The address match interrupt is generated Read data from IICDS Clear pending bit to resume SDA is shifted to IICDS Interrupt is pending Figure 20 9 Operations for Slave Receiver Mode 20 10 ELECTRONICS 53 2440 RISC MICROPROCESSOR IIC BUS INTERFACE IIC BUS INTERFACE SPECIAL REGISTERS MULTI MASTER IIC BUS CONTROL IICCON REGISTER IICCON 0x54000000 IIC Bus control register Acknowledge generation 1 IIC bus acknowledge enable bit 0 Disable 1 Enable In Tx mode the IICSDA is free in the ack time In Rx mode the IICSDA is L in the ack time Tx clock source selection Source clock of IIC bus transmit clock prescaler selection bit 0 fPCLK 16 1 IICCLK fPCLK 512 Tx Rx Interrupt 5 5 Tx Rx interrupt enable disable bit 0 Disable 1 Enable operation clear this bit as 0 0
419. ormally used 1 YCbCr 4 2 2 codec scaler input image format Out422 Co 30 0 YCbCr 4 2 0 codec scaler output image format This mode is mainly for MPEG 4 codec amp H W JPEG DCT normally used 1 YCbCr 4 2 2 codec scaler output image format This mode is mainly for S W JPEG TargetHsize Co 28 16 Horizontal pixel number of target image for codec multiple of 16 FligMd Co 15 14 Image mirror and rotation for codec 00 Normal 01 X axis mirror 10 Y axis mirror 11 180 rotation TargetVsize Co 12 0 Vertical pixel number of target image for codec ELECTRONICS 23 17 53 2440 RISC MICROPROCESSOR CAMERA INTERFACE X Axis Flip Original Image Y Axis Flip 180 Rotation Figure 23 11 Image Mirror and Rotation 23 18 ELECTRONICE 53 2440 RISC MICROPROCESSOR CAMERA INTERFACE CODEC DMA CONTROL REGISTER CICOCTRL 0x4F00004C Codec DMA control related ecocm sk busco fmi burst eng Tor codec Y rames o bust co Remained burst ength tor codec Y rames o xus Main burst length for codec Cwr rames o Cburst2_Co 8 4 Remained burst length for codec Cb Cr frames LastlRQEn Co 2 0 normal 1 enable last IRQ at the end of the frame capture This bit is cleared automatically NOTE All burst lengths must be one of the 2 4 8 16 Example 1 Target image size QCIF horizontal Y width 176 p
420. ort for scaling e Image mirror and rotation X axis mirror Y axis mirror and 180 rotation Camera output format RGB 16 24 bit and YCbCr 4 2 0 4 2 2 format Operating Voltage Range Core 1 20V for 300MHz 1 30V for 400MHz Memory 1 8V 2 5V 3 0V 3 3V 3 3V Operating Frequency e Up to 400MHz Up to 136MHz Pclk Up to 68MHz Package 289 FBGA ELECTRONICS 53 2440 RISC MICROPROCESSOR PRODUCT OVERVIEW BLOCK DIAGRAM ARM920T IPA 31 0 InstructionC External ACHE Coproc 16KB Interface C13 pue V ARM9TDMI Processor core Internal Embedded ICE wes 1 0 DVA 81 0 WriteBack WBPA 31 0 PA Tag RAM DPA 31 0 LCD LCD BUS CONT CONT gt Arbitor Decode Interrupt CONT BH NT USB Host CONT 2 0 Management ExtMaster Ctrl Flash Boot Loader Clock Generator MPLL 8 4Ch z GPIO Watchdog ADC BUS CONT Arbitor Decode Timer PWM _ 0 3 4 Internal Figure 1 1 53 2440 Block Diagram ELECTRONICS 1 5 53 2440 RISC MICROPROCESSOR PRODUCT OVERVIEW PIN ASSIGNMENTS E C TUO DA e OUO CD CH ODDO OX OU oux QOO QOO OOO OD OO Oo D TO OU C SM T1 Ox
421. ost Increment Addressing 3 41 3 20 Pre Increment Addressing ss 03081010020000000000000000000 00100015 3 42 3 21 Post Decrement Addressihg 3 42 3 22 Pre Decrement Addressing i e eee hu 3 43 3 23 Swap 3 47 3 24 Software Interr pt 3 49 3 25 Coprocessor Data Operation 3 51 3 26 Coprocessor Data Transfer Instructions 3 53 3 27 Coprocessor Register Transfer Instructions 3 56 3 28 Undefined x o ettet ep 3 58 53 2440 MICROCONTROLLER xxiii List of Figures continued Figure Title Page Number Number 4 1 THUMB Instruction Set 4 2 4 2 EE 4 5 4 3 FOTIT c 4 7 4 4 ML 4 9 4 5 4 11 4 6 EEUU EE 4 13 4 7 4 16 4 8 4 18 4 9 Format 4 20 4 10 9 4 22 4 11 Format 10 5 be cues a ade ee 4 24 4 12 4 26 4 13 TZ aA 4 28 4 14 ROMAE EE 4 30 4 15 14 f 4 31 4 16 motus
422. ould not be specified as the register offset Rm When 15 is the source register Rd of a Half word store STRH instruction the stored address will be address of the instruction plus 12 DATA ABORTS A transfer to or from a legal address may cause problems for a memory management system For instance in a system which uses virtual memory the required data may be absent from the main memory The memory manager can signal a problem by taking the processor ABORT input HIGH whereupon the Data Abort trap will be taken It is up to the system software to resolve the cause of the problem then the instruction can be restarted and the original program continued INSTRUCTION CYCLE TIMES Normal LDR H SH SB instructions take 1S 1N 11 LDR H SH SB PC take 25 2N 11 incremental cycles 5 and l are defined as sequential S cycle non sequential N cycle and internal I cycle respectively instructions take 2N incremental cycles to execute ELECTRONICS 3 37 ARM INSTRUCTION SET 53 2440 RISC MICROPROCESSOR ASSEMBLER SYNTAX lt LDR STR gt cond lt H SH SB gt Rd lt address gt LDR Load from memory into a register STR Store from a register into memory cond Two character condition mnemonic See Table 3 2 H Transfer halfword quantity SB Load sign extended byte Only valid for LDR SH Load sign extended halfword Only valid for LDR Rd An expression evaluating to a valid register number lt address gt can be
423. overrun error occurs during receive operation 0 No overrun error during receive 1 Overrun error Interrupt is requested NOTE These bits UERSATn 3 0 are automatically cleared to 0 when the UART error status register is read Frame Error 2 Set to 1 automatically whenever a frame error occurs during receive operation 0 No frame error during receive 1 Frame error Interrupt is requested ELECTRONICS 11 17 UART 53 2440 RISC MICROPROCESSOR UART FIFO STATUS REGISTER There are three UART FIFO status registers including UFSTATO UFSTAT1 and UFSTAT2 in the UART block urs ooo UART chanel O FIFO satus eee ursa 0000016 8 UART chanel 1 FIFO satus ester 7 oco UART channel 2 FIFO satus register 000 Reserve n j S Tx FIFO Full 14 Set to 1 automatically whenever transmit FIFO is full during transmit operation 0 0 byte lt Tx FIFO data lt 63 byte 1 Full Tx FIFO Count 13 8 Number of data in Tx FIFO Rx FIFO Full Set to 1 automatically whenever receive FIFO is full during receive operation 0 0 byte lt Rx FIFO data lt 63 byte 1 Full Rx FIFO Count 5 0 Number of data in Rx FIFO 11 18 ELECTRONICS 53 2440 RISC MICROPROCESSOR UART UART MODEM STATUS REGISTER There are two UART modem status registers including UMSTATO UMSTAT1 in the UART block 7 00000016 R UART aranne 0 modem satus regser 90
424. puts 15 through to 8 if it is a word address plus one byte and so on The selected byte is placed in the bottom 8 bit of the destination register and the remaining bits of the register are filled with the sign bit bit 7 of the byte Please see Figure 2 2 A halfword load LDRSH or LDRH expects data on data bus inputs 15 through to 0 if the supplied address is on a word boundary and on data bus inputs 31 through to 16 if it is a halfword boundary A 1 1 The supplied address should always be on a halfword boundary If bit 0 of the supplied address is HIGH then the ARM920T will load an unpredictable value The selected halfword is placed in the bottom 16 bits of the destination register For unsigned half words LDRH the top 16 bits of the register are filled with zeros and for signed half words LDRSH the top 16 bits are filled with the sign bit bit 15 of the halfword A halfword store STRH repeats the bottom 16 bits of the source register twice across the data bus outputs 31 through to 0 The external memory system should activate the appropriate halfword subsystem to store the data Note that the address must be halfword aligned if bit O of the address is HIGH this will cause unpredictable behaviour 3 36 ELECTRONICS 53 2440 RISC MICROPROCESSOR ARM INSTRUCTION SET Big Endian Configuration A signed byte load LDRSB expects data on data bus inputs 31 through to 24 if the supplied address is on a word boundary on data bus inputs 23
425. r the operation of the barrel shifter is controlled by the Shift field in the instruction This field indicates the type of shift to be performed logical left or right arithmetic right or rotate right The amount by which the register should be shifted may contain an immediate field in the instruction or in the bottom byte of another register other than R15 The encoding for the different shift types is shown in Figure 3 5 11 TI lj 6 5 Shift type 6 5 Shift type 00 logical left 01 logical right 00 logical left 01 logical right 10 arithmetic right 11 rotate right 10 arithmetic right 11 rotate right 11 7 Shift amount 11 8 Shift register 5 bit unsigned integer Shift amount specified in bottom byte of Rs Figure 3 5 ARM Shift Operations Instruction specified shift amount When the shift amount is specified in the instruction it is contained in a 5 bit field which can take any value from 0 to 31 A Logical Shift Left LSL takes the contents of Rm and moves each bit by the specified amount to a more significant position The least significant bits of the result are filled with zeros and the high bits of Rm which do not map into the result are discarded except that the least significant discarded bit becomes the shifter carry output which may be latched into the C bit of the CPSR when the ALU operation is in the logical class see above For example the effect of LSL 5 is shown in Figure 3 6 31 27 26
426. r Block 6 2 6 2 NAND Flash Controller Boot Loader Block Diagram 6 2 6 3 CLE amp ALE Timing TACLS 1 TWRPH0 0 TWRPH120 sse 6 4 6 4 nWE amp nRE Timing 0 TWRPH1 0 ennt 6 4 6 5 NAND Flash Memory nne nennen 6 9 6 6 8 bit NAND Flash Memory Interface mme emere 6 10 6 7 Two 8 bit NAND Flash Memory 6 10 6 8 16 bit NAND Flash Memory 6 11 7 1 Clock Generator Block 7 3 7 2 PLL Phase Locked Loop Block Diagram en 7 5 7 3 Main Oscillator Circuit menm nennen 7 5 7 4 Power On Reset Sequence when the external clock source is a crystal oscillator 7 6 7 5 Changing Slow Clock by Setting PMS 7 7 7 6 Example of Internal Clock 7 8 7 7 The Clock Distribution Block Diagram He en 7 10 7 8 Power Management State 7 11 7 9 Issuing Exit from Slow mode Command in on 7 13 7 10 Issuing Exit from Slow mode Command After Lock Time 7 13 7 11 Issuing
427. r automatically on return from an exception IRQ FIQ UNDEF ABORT SWI etc if the exception is entered with the processor in THUMB state Entering ARM State Entry into ARM state can be done by the following methods e On execution of the BX instruction with the state bit clear in the operand register e On the processor taking an exception IRQ FIQ RESET UNDEF ABORT SWI In this case the PC is placed in the exception mode s link register and execution commences at the exception s vector address MEMORY FORMATS ARM920T views memory as a linear collection of bytes numbered upwards from zero Bytes 0 to 3 hold the first stored word bytes 4 to 7 the second and so on ARM920T can treat words in memory as being stored either in Big Endian or Little Endian format ELECTRONICS 2 1 PROGRAMMER S MODEL 53 2440 RISC MICROPROCESSOR BIG ENDIAN FORMAT In Big Endian format the most significant byte of a word is stored at the lowest numbered byte and the least significant byte at the highest numbered byte Byte 0 of the memory system is therefore connected to data lines 31 through 24 Higher Address Most significant byte is at lowest address Lower Address _ Word is addressed by byte address of most significant byte Figure 2 1 Big Endian Addresses of Bytes within Words LITTLE ENDIAN FORMAT In Little Endian format the lowest numbered byte in a word is considered the word s least significant byte and the h
428. r the value in Rb and the value in Ro Load the contents of the address into Rd LDRB Rd Rb Ro LDRB Rd Rb Ro Pre indexed byte load Calculate the source address by adding together the value in Rb and the value in Ro Load the byte value at the resulting address INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 4 8 The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction EXAMPLES STR R2 R6 Store word in R3 at the address formed by adding R6 to R2 LDRB R2 RO R7 Loadinto R2 the byte found at the address formed by adding R7 to RO ELECTRONICS 4 19 THUMB INSTRUCTION SET 53 2440 RISC MICROPROCESSOR FORMAT 8 LOAD STORE SIGN EXTENDED BYTE HALFWORD 15 14 13 12 11 10 9 8 6 5 3 2 0 i s m 2 0 Destination Register 5 3 Base Register 8 6 Offset Register 10 Sign Extended Flag 0 Operand not sing extended 1 Operand sing extended 11 H Flag Figure 4 9 Format 8 OPERATION These instructions load optionally sign extended bytes or halfwords and store halfwords The THUMB assembler syntax is shown below Table 4 9 Summary of Format 8 Instructions STRH Rd Rb Ro STRH Rd Rb Ro Store halfword Add Ro to base address in Rb Store bits 0 15 of Rd at the resulting address LDRH Rd Rb Ro LDRH Rd Rb Ro Load halfword Add Ro
429. rame sec 4 bit single scan display HCLK frequency is 60 MHz WLH 1 WDLY 1 Data transmission rate 160 x 160 x 80 x 1 4 512 kHz CLKVAL 58 VCLK 517KHz HOZVAL 39 LINEVAL 159 LINEBLANK 10 LCDBASEL LCDBASEU 3200 NOTE The higher the system load is the lower the CPU performance Example 2 Virtual screen register 4 level gray Virtual screen size 1024 x 1024 LCD size 320 x 240 LCDBASEU 0x64 4 bit dual scan 1 halfword 8 pixels 4 level gray Virtual screen 1 line 128 halfword 1024 pixels LCD 1 line 320 pixels 40 halfword OFFSIZE 128 40 88 0x58 PAGEWIDTH 40 0x28 LCDBASEL LCDBASEU PAGEWIDTH OFFSIZE x LINEVAL 1 100 40 88 x 120 0x3C64 15 42 ELECTRONICS 53 2440 RISC MICROPROCESSOR LCD CONTROLLER Gray Level Selection Guide The S3C2440A LCD controller can generate 16 gray level using Frame Rate Control FRC The FRC characteristics may cause unexpected patterns in gray level These unwanted erroneous patterns may be shown in fast response LCD or at lower frame rates Because the quality of LCD gray levels depends on LCD s own characteristics the user has to select an appropriate gray level after viewing all gray levels on user s own LCD Select the gray level quality through the following procedures 1 Getthe latest dithering pattern register value from SAMSUNG Display 16 gray bar in LCD Change the frame rate into an optimal value Change th
430. ransfer LDM SIM EORR Ie ded 3 40 8 45551101 218 oerte buske puede iR Rudd ae 3 40 Addressing MODES emu tovc aa A A 3 41 Addiess Alignmert eii ha ree tender Er UR RARE AEE 3 41 5 5 EHE 3 43 RIS as The Base uu u Qu ku 3 43 Inclusion of the Base in the Register List a 3 44 ADONE EE 3 44 Instruction Cycle 68 Emm 3 44 Assemble t SyritaX 3 45 EM 3 46 Single 3 47 Bytes anad WOtdS iioi eee tete AA EE AEE A E Deed a ut dd 3 47 Use erben olet 3 48 Data EM 3 48 Instruction Gycle TINGS y 3 48 Assembler Syntax coi etras eta cedet bae reel see ra Ert gat ve tase te Boka 3 48 Sottware 3 49 Reetun rom tho Supervisor Deae oer ie Mert eoe us Rede hanes 3 49 leui H meE IE 3 49 Instruction Cycle TMCS isch 3 49 Assembler Sylitax 3 50 Coprocessor Data Operations 3 51 Coprocessor Instrctlonis
431. ransfer and the address will be incremented by one word for each subsequent transfer ADDRESS ALIGNMENT The base address should normally be a word aligned quantity The bottom 2 bits of the address will appear on A 1 0 and might be interpreted by the memory system Use of R15 If Rn is R15 the value used will be the address of the instruction plus 8 bytes Base write back to R15 must not be specified DATA ABORTS If the address is legal but the memory manager generates an abort the data trap will be taken The write back of the modified base will take place but all other processor state will be preserved The coprocessor is partly responsible for ensuring that the data transfer can be restarted after the cause of the abort has been resolved and must ensure that any subsequent actions it undertakes can be repeated when the instruction is retried Instruction cycle times Coprocessor data transfer instructions take n 1 S 2N bl incremental cycles to execute where n The number of words transferred b The number of cycles spent in the coprocessor busy wait loop S are defined as sequential S cycle non sequential N cycle and internal I cycle respectively 3 54 ELECTRONICS 53 2440 RISC MICROPROCESSOR ARM INSTRUCTION SET ASSEMBLER SYNTAX lt LDC STC gt cond L p cd lt Address gt LDC Load from memory to coprocessor STC Store from coprocessor to memory L When present perform long transfer N
432. rd 8 Where the PC is used as the source register SP 0 bit 1 of the PC is always read as 0 The value of the PC will be 4 bytes greater than the address of the instruction before bit 1 is forced to O The CPSR condition codes are unaffected by these instructions 4 28 ELECTRONICS 53 2440 RISC MICROPROCESSOR THUMB INSTRUCTION SET INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 4 13 The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction EXAMPLES ADD R2 PC 572 R2 572 but don t set thecondition codes bit 1 of PC is forced to zero Note that the THUMB opcode willcontain 143 as the Word8 value ADD R6 SP 212 SP R13 212 but don tset the condition codes Note that the THUMB opcode will contain 53 as the Word 8 value ELECTRONICS 4 29 THUMB INSTRUCTION SET S3C2440A RISC MICROPROCESSOR FORMAT 13 ADD OFFSET TO STACK POINTER 15 14 13 6 0 12 11 10 9 8 7 lt 6 0 7 bit Immediate Value 7 Sign Flag 0 Offset is positive 1 Offset is negative Figure 4 14 Format 13 OPERATION This instruction adds a 9 bit signed constant to the stack pointer The following table shows the THUMB assembler syntax Table 4 14 The ADD SP Instruction ADD SP ADD R13 R13 Imm Add stlmm to the stack pointer SP ADD SP
433. receiving holding trigger level of receive FIFO register whenever receive buffer becomes Generated when the number of data in FIFO does full not reaches Rx FIFO trigger Level and does not receive any data during 3 word time receive time out This interval follows the setting of Word Length bit Tx Interrupt Generated whenever transmit data reaches the Generated by the transmitting holding trigger level of transmit FIFO Tx FIFO trigger Level register whenever transmit buffer becomes empty Error Interrupt Generated when frame error parity error or break Generated by all errors However if another signal are detected error occurs at the same time only one Generated when it gets to the top of the receive interrupt is generated FIFO without reading out data in it overrun error ELECTRONICS 11 5 UART 53 2440 RISC MICROPROCESSOR UART Error Status FIFO UART has the error status FIFO besides the Rx FIFO register The error status FIFO indicates which data among FIFO registers is received with an error The error interrupt will be issued only when the data which has an error is ready to read out To clear the error status FIFO the URXHn with an error and UERSTATn must be read out For example It is assumed that the UART Rx FIFO receives A B C D and E characters sequentially and the frame error occurs while receiving B and the parity error occurs while receiving D The actual UART receive error will
434. result will exactly match that of an instruction specified shift with the same value and shift operation If the value in the byte is 32 or more the result will be a logical extension of the shift described above 1 N N LSL 32 has result zero carry out equal to bit 0 of Rm LSL by more than 32 has result zero carry out zero LSR by 32 has result zero carry out equal to bit 31 of Rm LSR by more than 32 has result zero carry out zero ASR by 32 or more has result filled with and carry out equal to bit 31 of Rm ROR by 32 has result equal to Rm carry out equal to bit 31 of Rm ROR by n where n is greater than 32 will give the same result and carry out as ROR by n 32 therefore repeatedly subtract 32 from n until the amount is in the range 1 to 32 and see above NOTE The zero in bit 7 of an instruction with a register controlled shift is compulsory a one in this bit will cause the instruction to be a multiply or undefined instruction ELECTRONICS 3 15 ARM INSTRUCTION SET 53 2440 RISC MICROPROCESSOR IMMEDIATE OPERAND ROTATES The immediate operand rotate field is a 4 bit unsigned integer which specifies a shift operation on the 8 bit immediate value This value is zero extended to 32 bits and then subject to a rotate right by twice the value in the rotate field This enables many common constants to be generated for example all powers of 2 WRITING TO R15 When Rd is a register other than R15 the c
435. rns quotient in 1 remainder in a2 MOV a2 al LSR a3 a1 2 SUB a1 a3 LSR a3 al 4 ADD al a3 LSR a3 a1 8 ADD a1 a3 LSR a3 al 16 ADD al a3 LSR al 3 ASL a3 al 2 ADD al ASL a3 1 SUB a2 a3 CMP a2 10 BLT ADD al 1 SUB a2 10 0 MOV pc Ir ARM Code udiv10 Take argument in a1 returns quotient in a1 remainder in a2 SUB a2 a1 10 SUB a1 a1 a1 Isr 2 ADD a1 al a1 Isr 4 ADD a1 a1 a1 Isr 8 ADD a1 a1 1 Isr 16 MOV a1 a1 Isr 3 ADD 83 a1 a1 asl 2 SUBS a2 a2 a3 asl 1 ADDPL a1 a1 1 ADDMI a2 a2 10 MOV Ir ELECTRONICS 4 43 THUMB INSTRUCTION SET S3C2440A RISC MICROPROCESSOR NOTES 4 44 ELECTRONICS 53 2440 RISC MICROPROCESSOR MEMORY CONTROLLER MEMORY CONTROLLER OVERVIEW The S3C2440A memory controller provides memory control signals that are required for external memory access The S3C2440A has the following features Little Big endian selectable by a software Address space 128Mbytes per bank total 1GB 8 banks Programmable access size 8 16 32 bit for all banks except 16 32 bit Total 8 memory banks Six memory banks for ROM SRAM etc Remaining two memory banks for ROM SRAM SDRAM etc Seven fixed memory bank start address One flexible memory bank start address and programmable bank size Programmable access cycles for all memory banks External wait to extend the bus cycles Supporting self refresh and power
436. rol signal erv o SEC TFT SEC Samsung Electronics Company TFT LCD panel control signal LCD SEC SEC Samsung Electronics Company TFT LCD panel control signal HP o SEC TFT SEC Samsung Electronics Company TFT LCD panel control signal ISH SEC TFT SEC Samsung Electronics Company TFT LCD panel control signal LCD 1 0 Timing control signal for specific TFT LCD LCD LPCREV Oo 5 Timing control signal for specific TFT LCD LCD LPCREVB O SEC TFT Timing control signal for specific TFT LCD CAMERA Interface CAMCLKOUT Master clock to camera CAMPCLK 1 Pixel clock from camera CAMHREF 1 Horizontal sync signal from camera CAMVSYNC _ Vertical sync signal from camera CAMDATA 7 0 I Pixeldata for YCbCr Interrupt Control Unit EINT 23 0 External interrupt request nXDREQ 1 0 External DMA request nXDACK 1 0 External DMA acknowledge ELECTRONICS 1 21 PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR Table 1 3 S3C2440A Signal Descriptions Sheet 3 of 6 Continued Signal 0 1 UART vransmis oaa oop 00002 UART clear to send UART request to send output sgnal CO c 06 posa mesa 251 00 IIS bus channel select clock 1255 IIS bus serial data output 12550 15 serial data input l28S
437. rs 53 2440 RISC MICROPROCESSOR NAND Flash Boot Loader Supports booting from NAND flash memory 4KB internal buffer for booting Supports storage memory for NAND flash memory after booting Supports Advanced NAND flash Cache Memory 64 set associative cache with 16KB and D Cache 16KB 8words length per line with one valid bit and two dirty bits per line Pseudo random or round robin replacement algorithm Write through or write back cache operation to update the main memory The write buffer can hold 16 words of data and four addresses Clock amp Power Manager On chip MPLL and UPLL UPLL generates the clock to operate USB Host Device MPLL generates the clock to operate MCU at maximum 400Mhz 1 3V Clock can be fed selectively to each function block by software Power mode Normal Slow Idle and Sleep mode Normal mode Normal operating mode Slow mode Low frequency clock without PLL Idle mode The clock for only CPU is stopped Sleep mode The Core power including all peripherals is shut down Woken up by EINT 15 0 or RTC alarm interrupt from Sleep mode ELECTRONICS 53 2440 RISC MICROPROCESSOR FEATURES Continued Interrupt Controller 60 Interrupt sources One Watch dog timer 5 timers 9 UARTs 24 external interrupts 4 2 2 ADC 1 2 SPI 1 SDI 2 USB 1 LCD 1 Battery Fault 1 NAND and 2 Camera 1 AC97
438. rt is configured as functional pin the undefined value will be read 0 The pull up function attached to the corresponding port pin is enabled 1 The pull up function is disabled ELEGTRONIGS PORTS 53 2440 RISC MICROPROCESSOR PORT D CONTROL REGISTERS GPDCON GPDDAT GPDUP GPDCON GPD15 31 30 00 Input 10 VD 23 GPD14 29 28 00 Input 10 VD 22 GPD13 27 26 00 Input 10 VD 21 GPD12 25 24 00 Input 10 VD 20 GPD11 23 22 00 Input 10 VD 19 GPD10 21 20 00 Input 10 VD 18 GPD9 19 18 00 Input 10 VD 17 GPD8 17 16 00 Input 10 VD 16 GPD7 15 14 00 Input 10 VD 15 GPD6 13 12 00 Input 10 VD 14 GPD5 11 10 00 Input 10 VD 13 GPD4 00 Input 10 VD 12 GPD3 7 6 00 Input 10 VD 11 GPD2 5 4 00 Input 10 VD 10 GPD1 3 2 00 Input 10 VD 9 GPDO 1 0 00 Input 10 VD 8 01 Output 11 nSS0 01 Output 11 1551 01 Output 11 Reserved 01 Output 11 Reserved 01 Output 11 Reserved 01 Output 11 SPICLK1 01 Output 11 SPIMOSI1 01 Output 11 SPIMISO1 01 Output 11 Reserved 01 Output 11 Reserved 01 Output 11 Reserved 01 Output 11 Reserved 01 Output 11 Reserved 01 Output 11 Reserved 01 Output 11 Reserved 01 Output 11 Reserved ELECTRONICS 53 2440 RISC MICROPROCESSOR PORTS PO
439. rt pin is enabled 1 The pull up function is disabled ELECTRONICS PORTS 53 2440 RISC MICROPROCESSOR PORT C CONTROL REGISTERS GPCCON GPCDAT GPCUP l GPC15 31 30 Input 01 Output VD 7 11 Reserved GPC14 29 28 Input 01 Output 105 VD 6 11 Reserved GPC13 27 26 Input 01 Output foe VD 5 11 Reserved GPC12 25 24 Input 01 Output pin VD 4 11 Reserved GPC11 23 22 Input 01 Output VD 3 11 Reserved GPC10 21 20 Input 01 Output 105 VD 2 11 Reserved GPC9 19 18 Input 01 Output VD 1 11 Reserved GPC8 17 16 Input 01 Output to VD 0 11 Reserved GPC7 15 14 Input 01 Output i LCD LPCREVB 11 Reserved GPC6 13 12 Input 01 Output 02 LCD LPCREV 11 Reserved GPC5 11 10 Input 01 Output LCD LPCOE 11 Reserved Input 01 Output Wc VM 11 125501 7 6 Input 01 Output VFRAME 11 Reserved GPC2 5 4 Input 01 Output 0 VLINE 11 Reserved GPC1 3 2 Input 01 Output VCLK 11 Reserved GPCO 1 0 Input 01 Output as LEND 11 Reserved 9 12 ELECTRONICS 53 2440 RISC MICROPROCESSOR PORTS PORT C CONTROL REGISTERS GPCCON GPCDAT GPCUP Continued When the port is configured as input port the corresponding bit is the pin state When the port is configured as output port the pin state is the same as the corresponding bit When the po
440. ruction 91 16 1 2110 3 16 Assembler Syritax L L 3 17 EXAIMPIOS 3 17 Per Transfer MRS u eiii A 3 18 stds pada anions 3 18 Reserved ed tec a te tele ttam urea 3 20 Examples eee eie ibt ice EE EBEN Ut 3 20 Instruction Cycle Times oe Eoo a e Let rt Eee M Lote eo E Lee CO 3 20 ASSEMDIY 20 lng 3 21 PSD SS aa EE 3 21 Multiply And Multiply Accumulate MUL 3 22 GOST FAQS m 3 24 Instruction Cycle TIfIGS 3 24 a a akak aa 3 24 NIRE ENTRE 3 24 Multiply Long And Multiply Accumulate Long MULL 3 25 Operand REStriCtiOns re i 3 26 PU 3 26 Instruction Mer 3 26 Assembler SYNTAX edes
441. s Samsung products are not designed intended or authorized for use as components in systems intended for surgical implant into the body for other applications intended to support or sustain life or for any other application in which the failure of the Samsung product could create a situation where personal injury or death may occur Should the Buyer purchase or use a Samsung product for any such unintended or unauthorized application the Buyer shall indemnify and hold Samsung and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages expenses and reasonable attorney fees arising out of either directly or indirectly any claim of personal injury or death that may be associated with such unintended or unauthorized use even if such claim alleges that Samsung was negligent regarding the design or manufacture of said product All rights reserved No part of this publication may be reproduced stored in a retrieval system or transmitted in any form or by any means electric or mechanical by photocopying recording or otherwise without the prior written consent of Samsung Electronics Samsung Electronics microcontroller business has been awarded full ISO 14001 certification BVQ1 Certificate No 9330 All semiconductor products are designed and manufactured in accordance with the highest quality standards and objectives Samsung Electronics Co Ltd San 24 Nongseo
442. s of the halfword address contained in RO HERE Generate PC relative offset to address FRED STRH R5 PC FRED HERE 8 Store the halfword in R5 at address FRED FRED ELECTRONICS 3 39 ARM INSTRUCTION SET 53 2440 RISC MICROPROCESSOR BLOCK DATA TRANSFER LDM STM The instruction is only executed if the condition is true The various conditions are defined in Table 3 2 The instruction encoding is shown in Figure 3 18 Block data transfer instructions are used to load LDM or store STM any subset of the currently visible registers They support all possible stacking modes maintaining full or empty stacks which can grow up or down memory and are very efficient instructions for saving or restoring context or for moving large blocks of data around main memory THE REGISTER LIST The instruction can cause the transfer of any registers in the current bank and non user mode programs can also transfer to and from the user bank see below The register list is a 16 bit field in the instruction with each bit corresponding to a register A 1 in bit O of the register field will cause RO to be transferred a 0 will cause it not to be transferred similarly bit 1 controls the transfer of R1 and so on Any subset of the registers or all the registers may be specified The only restriction is that the register list should not be empty Whenever R15 is stored to memory the stored value is the address of the STM instruction plus 12 2
443. s 0 TSZ 28 Select the transfer size of an atomic transfer i e transfer performed each time DMA owns the bus before releasing the bus 0 A unit transfer is performed 1 A burst transfer of length four is performed SYNC 30 Select DREQ DACK synchronization 0 DREQ and DACK are synchronized to PCLK APB clock 1 DREQ and DACK are synchronized to HCLK AHB clock Therefore for devices attached to AHB system bus this bit has to be set to 1 while for those attached to APB system it should be set to 0 For the devices attached to external systems the user should select this bit depending on which the external system is synchronized with between AHB system and APB system ELECTRONICS 8 9 53 2440 RISC MICROPROCESSOR CONTROL REGISTER Continued SERVMODE HWSRCSEL 26 24 SWHW_SEL RELOAD Select the service mode between Single service mode and Whole service mode 0 Single service mode is selected in which after each atomic transfer single or burst of length four DMA stops and waits for another DMA request 1 Whole service mode is selected in which one request gets atomic transfers to be repeated until the transfer count reaches to 0 In this mode additional request are not required Note that even in the Whole service mode DMA releases the bus after each atomic transfer and then tries to re get the bus to prevent starving of other bus masters Select DMA request source for
444. s a Branch to be performed which may also be used to switch processor state The THUMB assembler syntax is shown in Table 4 6 NOTE In this group only CMP Op 01 sets the CPSR condition codes The action of H1 0 H2 0 for Op 00 ADD Op 01 CMP and Op 10 MOV is undefined and should not be used Table 4 6 Summary of Format 5 Instructions 1 ADD Rd Hs ADD Rd Rd Hs Add a register in the range 8 15 to a register in the range 0 7 ADD Hd Rs ADD Hd Hd Rs Add a register in the range 0 7 to a register in the range 8 15 ADD Hd Hs ADD Hd Hd Hs Add two registers in the range 8 15 Compare a register in the range 0 7 with a register in the range 8 15 Set the condition code flags on the result 01 1 CMP Hd Rs CMP Hd Rs Compare a register in the range 8 15 with a register in the range 0 7 Set the condition code flags on the result ELECTRONICS 4 13 THUMB INSTRUCTION SET 53 2440 RISC MICROPROCESSOR Table 4 6 Summary of Format 5 Instructions Continued 01 1 1 CMP Hd Hs CMP Hd Hs Compare two registers in the range 8 15 Set the condition code flags on the result 10 1 MOV Rd Hs MOV Rd Hs Move a value from a register in the range 8 15 to a register in the range 0 7 10 1 MOV Hd Rs MOV Hd Rs Move a value from a register in the range 0 7 to a register in the range 8 15 10 MOV Hd Hs MOV Hd Hs Move a value between two registers in the range 8 15 BX Rs BX Rs Perform branch plus optional st
445. s to OXEAFFFFFE note effect of PC offset B there Always condition used as default CMP R1 0 Compare R1 with zero and branch to fred if R1 was zero otherwise continue BEQ fred Continue to next instruction BL sub ROM Call subroutine at computed address ADDS R1 1 Add 1 to register 1 setting CPSR flags on the result then call subroutine if BLCC sub the C flag is clear which will be the case unless R1 held 0xFFFFFFFF 3 8 ELECTRONICS 53 2440 RISC MICROPROCESSOR ARM INSTRUCTION SET DATA PROCESSING The data processing instruction is only executed if the condition is true The conditions are defined in Table 3 2 The instruction encoding is shown in Figure 3 4 31 28 27 26 25 24 21 20 19 16 15 12 11 0 o 15 12 Destination register 0 Branch 1 Branch with link 19 16 1st operand register 0 Branch 1 Branch with link 20 Set condition codes 0 Do not after condition codes 1 Set condition codes 24 21 Operation codes 0000 AND Rd Op1 AND Op2 0001 EOR Rd Op1 EOR Op2 0010 SUB Rd Op1 Op2 0011 RSB Rd Op2 Op1 0100 ADD Rd Op1 Op2 0101 ADC Rd 1 2 0110 SBC Rd OP1 Op2 C 1 0111 RSC Rd Op2 Op1 C 1 1000 TST set condition codes on Op1 AND Op2 1001 TEO set condition codes on OP1 EOR Op2 1010 CMP set condition codes on Op1 Op2 1011 SMN set condition codes on Op1 Op2 1100 ORR Rd Op1 OR Op2 11
446. settings to the SDIPRE register You can modify its frequency to adjust the baud rate data register value Programming Procedure common To program the SDI modules follow these basic steps 1 Set SDICON to configure properly with clock amp interrupt enable 2 Set SDIPRE to configure with a proper value 3 Wait 74 SDCLK clock cycle in order to initialize the card CMD Path Programming Write command argument 32bit to SDICmdArg Determine command types and start command transmit with setting SDICmdCon Confirm the end of SDI CMD path operation when the specific flag of SDICmdSta is set The flag is CmaSent if command type is no response The flag is RspFin if command type is with response Clear the flags of SDICmdSta by writing 1 to the corresponding bit DAT Path Programming Write data timeout period to SDIDTimer Write block size block length to SDIBSize normally 0x80 word Determine the mode of block wide bus dma etc and start data transfer with setting SDIDatCon Tx data Write data to Data Register SDIDAT while Tx FIFO is available TFDET is set or half TFHalf is set empty TFEmpty is set 5 Rx data Read data from Data Register SDIDAT while Rx FIFO is available RFDET is set or full RFFull is set or half RFHalf is set or ready for last data RFLast is set 6 Confirm the end of SDI DAT path operation when DatFin flag of SDIDatSta is set 7 Clear the flags of SDIDatSta by writing
447. shows a general purpose signed divide and remainder routine in both Thumb and ARM code Thumb code signed divide Signed divide of R1 by RO returns quotient in RO remainder in R1 Get abs value of RO into R3 ASR R2 RO 31 or 1 in R2 depending on sign of RO EOR RO R2 EOR with 1 OxFFFFFFFF if negative SUB RO R2 and ADD 1 SUB 1 to get abs value SUB always sets flag so go amp report division by 0 if necessary BEQ divide by zero Get abs value of R1 by xoring with OxFFFFFFFF and adding 1 if negative ASR RO R1 31 or 1 in depending on sign of R1 EOR R1 RO EOR with 1 OxFFFFFFFF if negative SUB R1 RO and ADD 1 SUB 1 to get abs value Save signs 0 or 1 in RO amp R2 for later use in determining sign of quotient amp remainder PUSH RO R2 Justification shift 1 bit at a time until divisor RO value is just lt than dividend R1 value To do this shift dividend right by 1 and stop as soon as shifted value becomes gt LSR RO R1 1 MOV R2 R3 B FTO just LSL R2 1 0 CMP R2 R0 BLS just MOV R0 0 Set accumulator to 0 B Branch into division loop LSR R2 1 0 CMP R1 R2 Test subtract BCC FTO SUB R1 R2 If successful do a real subtract 0 ADC RO RO Shift result and add 1 if subtract succeeded CMP R2 R3 Terminate when R2 R3 ie we have just BNE div tested subtracting the ones value ELECTRONICS 4 4
448. sible values are as follows For Signed INSTRUCTIONS SMULL SMLAL e f bits 31 8 of the multiplier operand are all zero or all one e f bits 31 16 of the multiplier operand are all zero or all one e f bits 31 24 of the multiplier operand are all zero or all one e other cases For Unsigned Instructions UMULL UMLAL e f bits 31 8 of the multiplier operand are all zero e If bits 31 16 of the multiplier operand are all zero e If bits 31 24 of the multiplier operand are all zero e other cases S and are defined as sequential S cycle and internal I cycle respectively 3 26 ELECTRONICS 53 2440 RISC MICROPROCESSOR ARM INSTRUCTION SET ASSEMBLER SYNTAX Table 3 5 Assembler Syntax Descriptions UMULL cond S RdLo RdHi Rm Rs Unsigned Multiply Long 32 x 32 64 SMULL cond S RdLo RdHi Rm Rs Signed Multiply Long 32 x 32 64 SMLAL cond S RdLo RdHi Rm Rs Signed Multiply amp Accumulate Long 32 x 32 64 64 cond Two character condition mnemonic See Table 3 2 S Set condition codes if S present RdLo RdHi Rm Rs Expressions evaluating to a register number other than R15 EXAMPLES UMULL R1 R4 R2 R3 R4 R1 R2 R3 UMLALS R1 R5 R2 R3 R5 R1 R2 R3 R5 R1 also setting condition codes ELECTRONICS 3 27 ARM INSTRUCTION SET 53 2440 RISC MICROPROCESSOR SINGLE DATA TRANSFER LDR STR The instruction is only executed if the condition is
449. splays and Figure 15 3 show these 3 different display types for color displays 4 bit Dual Scan Display Type A 4 bit dual scan display uses 8 parallel data lines to shift data to both the upper and lower halves of the display at the same time The 4 bits of data in the 8 parallel data lines are shifted to the upper half and 4 bits of data is shifted to the lower half as shown in Figure 15 2 The end of frame is reached when each half of the display has been shifted and transferred The 8 pins VD 7 0 for the LCD output from the LCD controller can be directly connected to the LCD driver 4 bit Single Scan Display Type A 4 bit single scan display uses 4 parallel data lines to shift data to successive single horizontal lines of the display at a time until the entire frame has been shifted and transferred The 4 pins VD 3 0 for the LCD output from the LCD controller can be directly connected to the LCD driver and the 4 pins VD 7 4 for the LCD output are not used 8 bit Single Scan Display Type An 8 bit single scan display uses 8 parallel data lines to shift data to successive single horizontal lines of the display at a time until the entire frame has been shifted and transferred The 8 pins VD 7 0 for the LCD output from the LCD controller can be directly connected to the LCD driver 256 Color Displays Color displays require 3 bits Red Green and Blue of image data per pixel so the number of horizontal shift registers for each
450. ster in PLL on state The SLOW clock is generated during the SLOW mode Figure 7 11 Please check the figure correctly shows the timing diagram SLOW Slow mode enable x Slow mode disable MPLL_OFF Divided external clock It changes to PLL clock after slow mode off Figure 7 9 Issuing Exit from Slow mode Command PLL on State If the user switches from SLOW mode to Normal mode by disabling the SLOW BIT in the CLKSLOW register after PLL lock time the frequency is changed just after SLOW mode is disabled Figure 7 12 Please check for the figure number correctly shows the timing diagram Software lock time SLOW BIT Slow mode enable Slow mode disable MPLL OFF y Poti on Divided OSC clock It changes to PLL clock after slow mode off Figure 7 10 Issuing Exit from Slow mode Command After Lock Time ELECTRONICS 7 13 CLOCK amp MANAGEMENT S3C2440A RISC MICROPROCESSOR If the user switches from SLOW mode to Normal mode by disabling SLOW_BIT and MPLL_OFF bit simultaneously in the CLKSLOW register the frequency is changed just after the PLL lock time Figure 7 13 Please check for the figure number correctly shows the timing diagram Hardware lock time 4 y Mpll SLOW BIT Slow mode enable Slow mode disable MPLL OFF PLL off PLL on FCLK Divided It changes to PLL clock OSC clock after l
451. t lt gt lt q ELECTRONICS 14 5 INTERRUPT CONTROLLER S3C2440A RISC MICROPROCESSOR INTERRUPT PRIORITY Each arbiter can handle six interrupt requests based on the one bit arbiter mode control and two bits of selection control signals SEL as follows If ARB SEL bits are 006 the priority order is REQ2 REQ3 REQ4 and REQ5 If ARB SEL bits are 010 the priority order is REQO REQ2 REQ3 REQ4 and If ARB SEL bits are 10b the priority order is REQO REQ3 4 REQ1 REQ2 and REQ5 If ARB SEL bits are 11b the priority order is REQ4 REQ1 REQ2 and REQ5 Note that REQO of an arbiter always has the highest priority and REQ5 has the lowest one In addition by changing the SEL bits we can rotate the priority of REQ1 to Here if ARB MODE bit is set to 0 ARB SEL bits doesn t change automatically changed making the arbiter to operate in the fixed priority mode note that even in this mode we can reconfigure the priority by manually changing the ARB SEL bits On the other hand if ARB MODE bit is 1 ARB SEL bits are changed in rotation fashion e g if REQ1 is serviced SEL bits are changed to 01b automatically so as to put REQM into the lowest priority The detailed rules of ARB SEL change are as follows If REQO or 5 is serviced SEL bits are not changed at all
452. t will continue to be interrupted every 3ms as long as there is no activity on the USB bus By default this interrupt is disabled 13 8 ELECTRONICS 53 2440 RISC MICROPROCESSOR USB DEVICE INTERRUPT ENABLE REGISTER EP INT EN REG USB INT EN REG Corresponding to each interrupt register The USB device controller also has two interrupt enable registers except resume interrupt enable By default usb reset interrupt is enabled If bit 0 the interrupt is disabled If bit 1 the interrupt is enabled EP INT EN REG 0x5200015C L R W Determine which interrupt is enabled OxFF 0x5200015F B byte 4 INT EN EP4 Interrupt Enable bit 0 Interrupt disable 1 Enable EP3_INT_EN EP3 Interrupt Enable bit 0 Interrupt disable 1 Enable EP2_INT_EN EP2 Interrupt Enable bit 0 Interrupt disable 1 Enable Interrupt Enable bit Interrupt disable 1 Enable EPO INT EN R W i Interrupt Enable bit Interrupt disable 1 Enable USB INT EN REG 0x520016C L ELM Determine which interrupt is enabled 0x04 0x520001 byte RESET INT EN R W interrupt enable bit ERN disable 1 Enable SUSPEND INT EN R W EMEN interrupt enable bit 0 Interrupt disable 1 Enable ELECTRONICS 13 9 USB S3C2440A RISC MICROPROCESSOR FRAME NUMBER REGISTER FPAME NUM1 REG FRAME NUM2 REG When the host transfers USB packets each Start Of Frame SOF packet includes a frame number The USB devi
453. te the updated base if the base is in the list DATA ABORTS Some legal addresses may be unacceptable to a memory management system and the memory manager can indicate a problem with an address by taking the ABORT signal HIGH This can happen on any transfer during a multiple register load or store and must be recoverable if ARM920T is to be used in a virtual memory system Abort during STM Instructions If the abort occurs during a store multiple instruction ARM920T takes little action until the instruction completes whereupon it enters the data abort trap The memory manager is responsible for preventing erroneous writes to the memory The only change to the internal state of the processor will be the modification of the base register if write back was specified and this must be reversed by software and the cause of the abort resolved before the instruction may be retried Aborts during LDM Instructions When 920 detects a data abort during a load multiple instruction it modifies the operation of the instruction to ensure that recovery is possible e Overwriting of registers stops when the abort happens The aborting load will not take place but earlier ones may have overwritten registers The PC is always the last register to be written and so will always be preserved base register is restored to its modified value if write back was requested This ensures recoverability in the case where the base register is also
454. ted 0 Not requested 1 Requested 0 Not requested 1 Requested 0 Not requested 1 Requested 0 Not requested 1 Requested 0 Not requested 1 Requested 0 Not requested 1 Requested 0 Not requested 1 Requested 0 Not requested 1 Requested 0 Not requested 1 Requested 0 Not requested 1 Requested 0 Not requested 1 Requested 0 Not requested 1 Requested INT_TIMER4 14 0 Not requested 1 Requested INT_TIMER3 13 0 Not requested 1 Requested INT_TIMER1 0 Not requested 1 Requested INT_WDT_AC97 9 0 Not requested 1 Requested B 0 Not requested 1 Requested 0 Not requested 1 Requested x 0 Not requested 1 Requested 0 Not requested 1 Requested 0 Not requested 1 Requested 0 Not requested 1 Requested 0 Not requested 1 Requested 0 Not requested 1 Requested ENO 0 Not requested 1 Requested 14 8 ELECTRONICS 53 2440 RISC MICROPROCESSOR INTERRUPT CONTROLLER INTERRUPT MODE INTMOD REGISTER This register is composed of 32 bits each of which is related to an interrupt source If a specific bit is set to 1 the corresponding interrupt is processed in the FIQ fast interrupt mode Otherwise it is processed in the IRQ mode normal interrupt Please note that only one interrupt source can be serviced in the FIQ mode in the interrupt controller you should use the FIQ mode only for the urgent int
455. ted when an nRESET pin is asserted through the AC_GLBCTRL Asserting and de asserting nRESET activates the BITCLK and SDATA OUT All the AC97 control registers are initialized to their default power on reset values nRESET is an asynchronous 97 input Warm AC97 Reset A warm 97 reset reactivates the AC link without altering the current AC97 register values A warm reset is generated when BITCLK is absent and SYNC is driven high In normal audio frames SYNC is a synchronous AC97 input When BITCLK is absent SYNC is treated as an asynchronous input used to generate a warm reset to AC97 The AC97 Controller must not activate BITCLK until it samples the SYNC to low again This prevents a new audio frame from being falsely detected 24 8 ELECTRONICS 53 2440 RISC MICROPROCESSOR AC97 CONTROLLER AC97 CONTROLLER SPECIAL REGISTERS AC97 GLOBAL CONTROL REGISTER AC_GLBCTRL R W AC_GLBCTRL 0x5B000000 R W AC97 global control register 0x000000 AC_GLBCTRL Bit Initial State Reserved 312 Codec ready interrupt enable 22 0 Disable 1 Enable PCM out channel underrun 21 0 Disable interrupt enable 1 Enable FIFO is empty PCM in channel overrun interrupt 20 0 Disable Enable 1 Enable FIFO is full MIC in channel overrun interrupt 19 0 Disable enable 1 Enable FIFO is full out channel threshold 18 0 Disable interrupt enable 1 Enable FIFO is half empty in channel threshold 17 0 Disable
456. ter instruction when it would have been overwritten with the loaded value Please check the meaning again ADDRESS ALIGNMENT The address should normally be a word aligned quantity and non word aligned addresses should not affect the instruction However the bottom 2 bits of the address will appear on A 1 0 and might be interpreted by the memory system 0 100 nq 0 100 0 1000 0 1000 OxOFF4 1 0 1000 OxOFF4 Figure 3 19 Post Increment Addressing ELECTRONICS 3 41 ARM INSTRUCTION SET 53 2440 RISC MICROPROCESSOR 0 100 0 100 1 0 1000 OxOFF4 ___________ OxoFF4 0 100 5 0 100 0 1000 OxOFF4 0x1000 5 OxOFF4 OxOFF4 E 3 Figure 3 21 Post Decrement Addressing 3 42 ELECTRONICS 53 2440 RISC MICROPROCESSOR ARM INSTRUCTION SET 0 100 lQOQ 0x100C 0x1000 0x1000 OxOFF4 1 0x1000 OxOFF4 4 Figure 3 22 Pre Decrement Addressing USE OF THE S BIT When the S bit is set in a LDM STM instruction it depends on R15 is available in the transfer list and on the type of instruction The S bit should only be set if the instruction is to execute in a privileged mode LDM with R15 in Transfer List and S Bit Set Mode Changes If the instruction is a LDM then SPSR_ lt mode gt is transferred to CPSR at the same time as R15 is loaded STM w
457. termines SRAM for using UB LB for bank 2 0 Not using UB LB The pins are dedicated nWBE 3 0 1 Using UB LB The pins are dedicated nBE 3 0 5 14 ELECTRONICS 53 2440 RISC MICROPROCESSOR MEMORY CONTROLLER BUS WIDTH amp WAIT CONTROL REGISTER BWSCON Continued miarsa 10 Determines WAIT status for bank 2 0 WAIT disable 1 WAIT enable LE data bus width for bank 2 8 54 01 16 bit 10 32 bit 11 reserved Determines SRAM for using UB LB for bank 1 0 Not using UB LB The pins are dedicated nWBE 3 0 1 Using UB LB The pins are dedicated nBE 3 0 EB WAIT status for bank 1 WAIT disable 1 WAIT enable 5 4 Determines data bus width for bank 1 00 8 5 01 16 bit 10 32 bit 11 reserved DW0 2 1 Indicate data bus width for bank 0 read only 01 16 bit 10 32 bit The states are selected by OM 1 0 pins mew NOTES 1 Alltypes of master clock in this memory controller correspond to the bus clock For example HCLK in SRAM is the same as the bus clock and SCLK in SDRAM is also the same as the bus clock In this chapter Memory Controller one clock means one bus clock 2 nBE 3 0 is the signal nWBE 3 0 and nOE ELECTRONICS 5 15 MEMORY CONTROLLER S3C2440A RISC MICROPROCESSOR BANK CONTROL REGISTER BANKCONN NGCS0 NGCS5 Tacs 14 13 Address set up time before nGCSn 00 0 clock 01
458. ters Visible ARM state registers 10000 User R7 R0 R14 R0 LR SP PC CPSR PC CPSR 10001 FIQ R7 R0 R7 R0 LR fig SP_fiq R14 fig R8 PC CPSR SPSR fiq PC CPSR SPSR fiq 10010 7 12 LR SP R14 irg R13 irq PC CPSR SPSR irq PC CPSR SPSR irq 10011 Supervisor 7 12 LR svc 14 svc R13 CPSR SPSR_svc PC CPSR SPSR_svc 10111 Abort R7 R0 R12 R0 LR abt SP abt R14 abt R13 abt PC CPSR SPSR abt PC CPSR SPSR abt 11011 Undefined R7 RO 12 LR und SP und R14 und R13 und PC CPSR SPSR und PC CPSR 11111 System 7 14 LR SP PC CPSR PC CPSR Reserved bits The remaining bits in the PSR s are reserved While changing a PSR s flag or control bits you must ensure that these unused bits are not altered Also your program should not rely on them containing specific values since in future processors they may read as one or zero ELECTRONICS 2 9 PROGRAMMER S MODEL 53 2440 RISC MICROPROCESSOR EXCEPTIONS Exceptions arise whenever the normal flow of a program has to be halted temporarily for example to service an interrupt from a peripheral Before an exception can be handled the current processor state must be preserved so that the original program can resume when the handler routine has finished It is possible for several exceptions to arise at the same time If this happens they are dealt with in a
459. the following table 3 6 Table 3 6 Addressing Mode Names ms 1 ome m m o PreDevementicad wwe o wA imp 9 9 Sm sme o sme sma o 9 PreDecrementsioe SF sm o 9 smeo su o 9 9 FD ED FA EA define pre post indexing and the up down bit by reference to the form of stack required The F and E refer to a full or empty stack i e whether a pre index has to be done full before storing to the stack The A and D refer to whether the stack is ascending or descending If ascending a STM will go up and LDM down if descending vice versa IA IB DA DB allow control when LDM STM are not being used for stacks and simply mean Increment After Increment Before Decrement After Decrement Before ELECTRONICS 3 45 ARM INSTRUCTION SET EXAMPLES LDMFD 1 2 STMIA RO RO R15 LDMFD 15 LDMFD 15 STMFD 13 0 14 53 2440 RISC MICROPROCESSOR Unstack 3 registers Save all registers R15 lt SP CPSR unchanged R15 SP CPSR SPSR mode allowed only in privileged modes Save user mode regs on stack allowed only in privileged modes These instructions may be used to save state on subroutine entry and restore it efficiently on return to the calling routine
460. tions of the ARM instruction sets The thumb instructions are decompressed to the ARM instructions by the Thumb decompressor inside the ARM920T core As the Thumb instructions are compressed ARM instructions the Thumb instructions have the 16 bit format instructions and have some restrictions The restriction by 16 bit format is fully notified for using the Thumb instructions ELECTRONICS 4 1 THUMB INSTRUCTION SET 53 2440 RISC MICROPROCESSOR FORMAT SUMMARY The THUMB instruction set formats are shown in the following figure 15 14 13 12 11 Move Shifted register Add subtract Offset8 Move compare add subtract immediate ALU operations H2 Hi register operations branch exchange Word8 PC relative load Load store with register offset H S Load store sign extended byte halfword Offset5 Load store with immediate offset Offset5 Rb Load store halfword SP relative load store Load address Add offset to stack pointer Push pop register Multiple load store Conditional branch Software interrupt Offset 1 Unconditional branch 19 14 Offset Long branch with link 15 14 13 12 11 Figure 4 1 THUMB Instruction Set Formats 4 2 ELECTRONICS 53 2440 RISC MICROPROCESSOR THUMB INSTRUCTION SET OPCODE SUMMARY The following table summarizes the THUMB instruction set For further information about a particular instruction please refer to the sections listed in the right most column
461. to base address in Rb Load bits 0 15 of Rd from the resulting address and set bits 16 31 of Rd to 0 LDSB Rd Rb Ro LDRSB Rb Ro Load sign extended byte Add Ro to base address in Rb Load bits 0 7 of Rd from the resulting address and set bits 8 31 of Rd to bit 7 LDSH Rd Rb Ro LDRSH Rd Rb Load sign extended halfword Add Ro to base address in Rb Load bits 0 15 of Rd from the resulting address and set bits 16 31 of Rd to bit 15 4 20 ELECTRONICS 53 2440 RISC MICROPROCESSOR THUMB INSTRUCTION SET INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 4 9 The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction EXAMPLES STRH R4 R3 RO Store the lower 16 bits of R4 at the address formed by adding RO to R3 LDSB R2 R7 R1 Load into R2 the sign extended byte found at the address formed by adding R1 to R7 LDSH R3 R4 R2 Load into the sign extended halfword found at the address formed by adding R2 to ELECTRONICS 4 21 THUMB INSTRUCTION SET 53 2440 RISC MICROPROCESSOR FORMAT 9 LOAD STORE WITH IMMEDIATE OFFSET 15 14 13 12 11 10 6 5 3 2 0 011 _ 2 0 Source Destination Register 5 3 Base Register 10 6 Offset Register 11 Load Store Flag 0 Store to memory 1 Load from memory 12 Byte Word Flad 0 Transf
462. to maximize throughput Supports suspend and remote wakeup function NOTE PCLK should be more than 20MHz to use USB Controller in stable condition ELECTRONICS 13 1 USB S3C2440A RISC MICROPROCESSOR ADDR 13 0 DATA IN 31 0 RT VM IN MC DATA OUT 31 0 RT VP IN 22 USB_CLK RXD SYS_CLK SYS_RESETN RT_VP_OUT MC_WR M T RT_VM_OU WR_RDN RT_UX_OEN MC_CSN MC_INTR RT_UXSUSPEND DREQN 3 0 DACKN 3 0 Figure 13 1 USB Device Controller Block Diagram 13 2 ELECTRONICS 53 2440 RISC MICROPROCESSOR USB DEVICE USB DEVICE CONTROLLER SPECIAL REGISTERS This section describes detailed functionalities about register sets of USB device controller All special function register is byte accessible or word accessible If you access byte mode offset address is different in little endian and big endian All reserved bit is zero Common indexed registers depend on INDEX register INDEX REG offset address 0X178 value For example if you want to write EPO CSR register you must write 0x00 on the INDEX REG before writing IN CSR1 register NOTE All register must be resettled after performing host reset signaling EP INT REG 4 0x148 L 0 14 10 78 70105 EP1 DMA TTC L Endpoint DMA transfer counter low Ox20C L 0x20F B byte register EP1 DMA TTC M Endpoint DMA transfer counter 0x210 L 0 213 middle byte register 1_ TTC H E
463. transmitted first because the transmitter and receiver may have different word lengths The transmitter does not have to know how many bits the receiver can handle nor does the receiver need to know how many bits are being transmitted When the system word length is greater than the transmitter word length the word is truncated least significant data bits are set to 0 for data transmission If the receiver gets more bits than its word length the bits after the LSB are ignored On the other hand if the receiver gets fewer bits than its word length the missing bits are set to zero internally And therefore the MSB has a fixed position whereas the position of the LSB depends on the word length The transmitter sends the MSB of the next word at one clock period whenever the IISLRCK is changed Serial data sent by the transmitter may be synchronized with either the trailing HIGH to LOW or the leading LOW to HIGH edge of the clock signal However the serial data must be latched into the receiver on the leading edge of the serial clock signal and so there are some restrictions when transmitting data that is synchronized with the leading edge The LR channel select line indicates the channel being transmitted IISLRCK may be changed either on a trailing or leading edge of the serial clock but it does not need to be symmetrical In the slave this signal is latched on the leading edge of the clock signal The IISLRCK line changes one clock period b
464. ual to bit 31 of Rm The result is therefore all ones or all zeros according to the value of bit 31 of Rm ELECTRONICS 3 13 ARM INSTRUCTION SET 53 2440 RISC MICROPROCESSOR Rotate right ROR operations reuse the bits which overshoot in a logical shift right operation by reintroducing them at the high end of the result in place of the zeros used to fill the high end in logical right operations For example 5 is shown in Figure 3 9 31 5 4 0 Contents of Rm carry out Value of Operand 2 Figure 3 9 Rotate Right The form of the shift field which might be expected to give ROR 0 is used to encode a special function of the barrel shifter rotate right extended RRX This is a rotate right by one bit position of the 33 bit quantity formed by appending the CPSR C flag to the most significant end of the contents of Rm as shown in Figure 3 10 31 10 Contents of Rm C N carry out in Value of 2 Figure 3 10 Rotate Right Extended 3 14 ELECTRONICS 53 2440 RISC MICROPROCESSOR ARM INSTRUCTION SET Register Specified Shift Amount Only the least significant byte of the contents of Rs is used to determine the shift amount Rs can be any general register other than R15 If this byte is zero the unchanged contents of Rm will be used as the second operand and the old value of the CPSR C flag will be passed on as the shifter carry output If the byte has a value between 1 and 31 the shifted
465. up priority order set 00 REQ 1 2 3 4 01 REQ 2 3 4 1 10 REQ 3 4 1 2 11 REQ 4 1 2 3 ARB_SEL4 16 15 Arbiter 4 group priority order set 00 REQ 0 1 2 3 4 5 01 REQ 0 2 3 4 1 5 10 REQ 0 3 4 1 2 5 11 REQ 0 4 1 2 3 5 ARB_SEL3 14 13 Arbiter 3 group priority order set 00 REQ 0 1 2 3 4 5 01 REQ 0 2 3 4 1 5 10 REQ 0 3 4 1 2 5 11 REQ 0 4 1 2 3 5 ARB_SEL2 12 11 Arbiter 2 group priority order set 00 REQ 0 1 2 3 4 5 01 REQ 0 2 3 4 1 5 10 REQ 0 3 4 1 2 5 11 REQ 0 4 1 2 3 5 ARB_SEL1 10 9 Arbiter 1 group priority order set 00 REQ 0 1 2 3 4 5 01 REQ 0 2 3 4 1 5 10 REQ 0 3 4 1 2 5 11 REQ 0 4 1 2 3 5 ARB SELO 8 7 Arbiter O group priority order set 00 REQ 1 2 3 4 01 REQ 2 3 4 1 10 REQ 3 4 1 2 11 REQ 4 1 2 3 ARB_MODE6 EN MODE5 5 0 Priority does not rotate 1 Priority rotate enable ARB_MODE4 4 Arbiter 4 group priority rotate enable 0 Priority does not rotate 1 Priority rotate enable ARB_MODE3 Arbiter 3 group priority rotate enable Arbiter 2 group priority rotate enable 1 Arbiter 6 group priority rotate enable 0 Priority does not rotate 1 Priority rotate enable Arbiter 5 group priority rotate enable 0 Priority does not rotate 1 Priority rotate enable ARB_MODE2 0 Priority does not rotate 1 Priority rotate enable ARB_MODE1 Arbiter 1 group priority rotate enable 0 Priority does not rotate 1 Priority rotate enable ARB MODEO Arbiter O group priority rotate
466. ut and the users should check the FIFO status and read out the rest 11 14 ELECTRONICS 53 2440 RISC MICROPROCESSOR UART UART MODEM CONTROL REGISTER There are two UART MODEM control registers including UMCONO and UMCONI1 in the UART block Reseved 00008000 7 5 These bits must be 05 Auto Flow Control 4 0 Disable 1 Enable 3 Request to Send If AFC bit is enabled this value will be ignored In this case the S3C2440A will control nRTS automatically If AFC bit is disabled nRTS must be controlled by software 0 H level Inactivate nRTS 1 L level Activate nRTS NOTE UART 2 does not support AFC function because the S3C2440A has no nRTS2 and nCTS2 ELECTRONICS 11 15 UART 53 2440 RISC MICROPROCESSOR UART TX RX STATUS REGISTER There are three UART Tx Rx status registers including UTRSTATO UTRSTAT1 and UTRSTAT2 in the UART block ums oec R UART reger os usan UART channel 1 Tx status register 8 usa UART charnel 2 status reiser 96 _ Transmitter empty Set to 1 automatically when the transmit buffer register has no valid data to transmit and the transmit shift register is empty 0 Not empty 1 Transmitter transmit buffer amp shifter register empty Receive buffer data Set to 1 automatically whenever receive buffer register ready contains v
467. ut 01 Output 02 EINT 1 11 Reserved GPF0 1 0 Input 01 Output EINT 0 11 Reserved 7 0 7 0 When the port is configured input the corresponding bit is the pin state When the port is configured as an output port the pin state is the same as the corresponding bit When the port is configured as functional pin the undefined value will be read GPUP scription GPF 7 0 7 0 0 The pull up function attached to the corresponding port pin is enabled 1 The pull up function is disabled 9 18 ELECTRONICS 53 2440 RISC MICROPROCESSOR PORT G CONTROL REGISTERS GPGCON GPGDAT If GPG0 GPG7 will be used for wake up signals at Sleep mode the ports will be set in interrupt mode PORTS GPGCON 0x56000060 Configures the pins of port G GPGDAT 0x56000064 The data register for port G GPGUP 0x56000068 Pull up disable register for port G 0 00 15 31 30 00 Input 10 EINT 23 GPG14 29 28 00 Input 10 EINT 22 GPG13 27 26 00 Input 10 EINT 21 GPG12 25 24 00 Input 10 EINT 20 GPG11 23 22 00 Input 10 EINT 19 GPG10 21 20 00 Input 10 EINT 18 GPG9 19 18 00 Input 10 EINT 17 GPG8 17 16 00 10 6 GPG7 15 14 00 Input 10 EINT 15 GPG6 13 12 00 Input 10 EINT 14 GPG5 11 10 00 10 EINT 13 00 10 EINT 12 7 6 00 10 EINT 11 GPG2 5 4
468. ut Driver Disable 1 Output Driver Enable YP SEN YP Switch Enable 0 Output Driver Enable 1 Output Driver Disable XM SEN XM Switch Enable 0 XM Output Driver Disable 1 XM Output Driver Enable XP SEN XP Switch Enable 0 XP Output Driver Enable 1 XP Output Driver Disable PULL UP Pull up Switch Enable 0 XP Pull up Enable 1 XP Pull up Disable AUTO PST Automatically sequencing conversion of X Position and Y Position 0 Normal ADC conversion 1 Auto Sequential measurement of X position Y position XY PST Manually measurement of X Position or Y Position 00 No operation mode 01 X position measurement 10 Y position measurement 11 Waiting for Interrupt Mode NOTES 1 While waiting for Touch screen Interrupt SEN bit should be set to 1 XP Output disable PULL bit should be set to 0 XP Pull up enable 2 AUTO PST bit should be set 1 only in Automatic amp Sequential X Y Position conversion 3 should be disconnected with GND source during sleep mode to avoid leakage current Because XP will be maintained as H states in sleep mode Touch screen pin conditions in X Y position conversion YP 16 6 ELECTRONICS 53 2440 RISC MICROPROCESSOR ADC AND TOUCH SCREEN INTERFACE ADC START DELAY REGISTER ADCDLY ADCDLY 0x5800008 ADC Start or interval delay register 0x00ff DELAY 15 0 1 Normal Conversion Mode XY position mode
469. utput inverter on off for Timer 0 0 Inverter off 1 Inverter on for TOUTO Timer 0 manual update note Determine the manual update for Timer 0 0 operation 1 Update 0 start stop Determine start stop for Timer 0 0 Stop 1 Start for Timer 0 NOTE The bit has to be cleared at next writing 10 14 ELECTRONICS 53 2440 RISC MICROPROCESSOR PWM TIMER TIMER 0 COUNT BUFFER REGISTER amp COMPARE BUFFER REGISTER TCNTB0 TCMPB0 TCNTB0 0x5100000C Timer 0 count buffer register 0x00000000 TCMPBO 0x51000010 Timer 0 compare buffer register 0x00000000 Timer 0 compare buffer register 15 0 Set compare buffer value for Timer 0 0x00000000 Timer 0 count buffer register 15 0 Set count buffer value for Timer 0 0x00000000 TIMER 0 COUNT OBSERVATION REGISTER TCNTOO 0x51000014 Timer 0 count observation register 0x00000000 Timer 0 observation register 15 0 Set count observation value for Timer 0 0x00000000 Register TCNTOO ELECTRONICS 10 15 PWM TIMER S3C2440A RISC MICROPROCESSOR TIMER 1 COUNT BUFFER REGISTER amp COMPARE BUFFER REGISTER 1 1 TCNTB1 0x51000018 Timer 1 count buffer register 0x00000000 TCMPB1 0 5100001 Timer 1 compare buffer register 0x00000000 Timer 1 compare buffer register 15 0 Set compare buffer value for Timer 1 0x00000000 15 0 Set count buffer value for Timer 1 0x00000000 TCNTB1 Timer 1 count buffer re
470. ver the AC link Set up the AC97 Controller so that it does not transmit data to slots 3 12 when it writes to the Powerdown register bit data 0x1000 and it does not require the CODEC to process other data when it receives a power down request When the CODEC processes the request it immediately transitions BITCLK and SDATA IN to a logic low level The AC97 Controller drives the SYNC and SDATA OUT to a logic low level after programming the GLBCTRL register ELECTRONICS 24 7 97 CONTROLLER 53 2440 RISC MICROPROCESSOR Waking up the AC link Wake Up Triggered by the AC97 Controller AC link protocol is provided for a cold AC97 reset and a warm AC97 reset The current power down state ultimately dictates which AC97 reset is used Registers must stay in the same state during all power down modes unless a cold AC97 reset is performed In a cold AC97 reset the AC97 registers are initialized to their default values After a power down the AC link must wait for a minimum of four audio frame time after the frame in which the power down occurred before it can be reactivated by reasserting the SYNC signal When AC link powers up it indicates readiness through the Codec ready bit input slot 0 bit 15 PR0 1 PR2 1 ADOs off DACs off PRO PRI PRO 0 PR1 0 amp amp ADC 1 1 Warm Reset Cold Reset Ready 1 Figure 24 8 AC97 Power down Power Flow Cold AC97 Reset cold reset is genera
471. w level duration is n 1 High level duration is DCLKODIV 1 n 1 DCLKODIV 7 4 DCLKO divide value DCLKO frequency source clock DCLKODIV 1 DCLKOSelCK 1 Select DCLKO source clock 0 PCLK 1 UCLK USB DCLKOEN DCLKO enable 0 DCLKO disable 1 DCLKO enable DCLKnDIV 1 9 26 ELECTRONICS 53 2440 RISC MICROPROCESSOR PORTS EXTINTn External Interrupt Control Register n The 8 external interrupts can be requested by various signaling methods The EXTINT register configures the signaling method between the level trigger and edge trigger for the external interrupt request and also configures the signal polarity To recognize the level interrupt the valid logic level on EXTINTn pin must be retained for 40ns at least because of the noise filter EINT7 30 28 Setting the signaling method of the EINT7 000 Low level 001 High level 01x Falling edge triggered 10x Rising edge triggered 11x Both edge triggered EINT6 26 24 Setting the signaling method of the EINT6 000 Low level 001 High level 01x Falling edge triggered 10x Rising edge triggered 11x Both edge triggered EINT5 22 20 Setting the signaling method of the EINT5 000 Low level 001 High level 01x Falling edge triggered 10x Rising edge triggered 11x Both edge triggered EINT4 18 16 Setting the signaling method of the EINT4 000 Low level 001 High level 01x Falling edge triggered 10x Rising edge triggered 11
472. w ways in which the THUMB instructions may be used to generate small and efficient code Each example also shows the ARM equivalent so these may be compared MULTIPLICATION BY A CONSTANT USING SHIFTS AND ADDS The following instructions are the code to multiply by various constants using 1 2 or 3 Thumb instructions alongside the ARM equivalents For other constants it is generally better to use the built in MUL instruction rather than using a sequence of 4 or more instructions Thumb ARM 1 Multiplication by 2 n 1 2 4 8 LSL Ra Rb LSL Ra Rb LSL n 2 Multiplication by 2 1 3 5 9 17 LSL Rt Rb 4 ADD Ra Rb Rb LSL n ADD Ra Rt Rb 3 Multiplication by 2 n 1 3 7 15 LSL Rt Rb RSB Rb Rb LSL n SUB Ra Rt Rb 4 Multiplication by 2 n 2 4 8 LSL Ra Rb MOV Rb LSL n MVN Ra Ra RSB Ra Ra 0 5 Multiplication by 2 1 3 7 15 LSL Rt Rb SUB Ra Rb Rb LSL n SUB Ra Rb Rt Multiplication by any C 24n 1 2 n 1 2 n or 2 1 2 n Effectively this is any of the multiplications in 2 to 5 followed by a final shift This allows the following additional constants to be multiplied 6 10 12 14 18 20 24 28 30 34 36 40 48 56 60 62 2 5 2 5 LSL Ra Ra n MOV Ra LSL n 4 40 ELECTRONICS 53 2440 RISC MICROPROCESSOR THUMB INSTRUCTION SET GENERAL PURPOSE SIGNED DIVIDE This example
473. x Both edge triggered EINT3 14 12 Setting the signaling method of the EINT3 000 Low level 001 High level 01x Falling edge triggered 10x Rising edge triggered 11x Both edge triggered EINT2 10 8 Setting the signaling method of the EINT2 000 Low level 001 High level 01x Falling edge triggered 10x Rising edge triggered 11x Both edge triggered EINT1 6 4 Setting the signaling method of the EINT1 000 Low level 001 High level 01x Falling edge triggered 10x Rising edge triggered 11x Both edge triggered EINTO 2 0 Setting the signaling method of the EINTO 000 Low level 001 High level 01x Falling edge triggered 10x Rising edge triggered 11x Both edge triggered ELECTRONICS 9 27 PORTS 53 2440 RISC MICROPROCESSOR EXTINTn External Interrupt Control Register n Continued FLTEN15 31 Filter enable for EINT15 0 Filter Disable 1 Filter Enable EINT15 30 28 Setting the signaling method of the EINT15 000 Low level 001 High level 01x Falling edge triggered 10x Rising edge triggered 11x Both edge triggered FLTEN14 27 Filter enable for EINT14 0 Filter Disable 1 Filter Enable EINT14 26 24 Setting the signaling method of the EINT14 000 Low level 001 High level 01x Falling edge triggered 10x Rising edge triggered 11x Both edge triggered FLTEN13 23 Filter enable for EINT13 0 Filter Disable 1 Filter Enable EINT13 22 20 Setting the signaling method of the EINT13
474. xecuted if the condition is true The various conditions are defined in Table 3 2 The instruction encoding is shown in Figure 3 16 These instructions are used to load or store half words of data and also load sign extended bytes or half words of data The memory address used in the transfer is calculated by adding an offset to or subtracting an offset from a base register The result of this calculation may be written back into the base register if auto indexing is required 2827 25 24 23 22 21 20 19 16 15 12 11 876543 Lu Dm TEPPI 3 0 Offset Register 6 5 S H 0 0 SWP instruction 0 1 Unsigned halfword 1 1 Signed byte 1 1 Signed halfword 15 12 Source Destination Register 19 16 Base Register 20 Load Store 0 Store to memory 1 Load from memory 21 Write back 0 No write back 1 Write address into base 23 Up Down 0 Down subtract offset from base 1 Up add offset to base 24 Pre Post Indexing 0 Post add subtract offset after transfer 1 Pre add subtract offset bofore transfer 31 28 Condition Field Figure 3 16 Halfword and Signed Data Transfer with Register Offset 3 34 ELECTRONICS 53 2440 RISC MICROPROCESSOR ARM INSTRUCTION SET 2827 25 24 23 22 21 20 19 16 15 12 11 876543 Lu gt Dow Dew 3 0 Immediate Offset Low Nibble 6 5 S H 0 0 SWP instruction 0 1 2 Unsigned halfword 1 1 Signed byte 1 1 Signed halfword 11 8
475. xed If it 0 the address is increased by its data size after each transfer in burst and single transfer mode If itis 1 the address is not changed after the transfer In the burst mode address is increased during the burst transfer but the address is recovered to its first value after the transfer 8 8 ELECTRONICS 53 2440 RISC MICROPROCESSOR DMA DMA CONTROL DCON REGISTER DMD HS 31 Select one between Demand mode and Handshake mode 0 Demand mode will be selected 1 Handshake mode will be selected In both modes DMA controller starts its transfer and asserts DACK for a given asserted DREQ The difference between the two modes is whether it waits for the de asserted DACK or not In the Handshake mode DMA controller waits for the de asserted DREQ before starting a new transfer If it finds the de asserted DREQ it de asserts and waits for another asserted DREQ In contrast in the Demand mode DMA controller does not wait until the DREQ is de asserted It just de asserts DACK and then starts another transfer if DREQ is asserted We recommend using Handshake mode for external DMA request Sources to prevent unintended starts of new transfers INT 29 Enable Disable the interrupt setting for TC terminal count 0 CURR interrupt is disabled The user has to view the transfer count in the status register i e polling 1 Interrupt request is generated when all the transfer is done i e TC become
476. y Halfword D 15 8 D 7 0 SDI Baud Rate Prescaler Register SDIPRE SDIPRE 0x5A000004 SDI buad rate prescaler register Prescaler Value 7 0 Determines SDI clock SDCLK rate as above equation 0x01 Baud rate PCLK Prescaler value 1 NOTE Prescaler Value should be greater than zero 19 4 ELECTRONICS 53 2440 RISC MICROPROCESSOR MMC SD SDIO CONTROLLER SDI Command Argument Register SDICmdArg SDICmdArg 0x5A000008 SDI command argument register SDI Command Control Register SDICmdCon SDICmdCon 0 5 00000 SDI command control register 0x0 SDICommand Bit Description Initial Value EE Abort Command 12 Determines whether command type is for abort for SDIO 0 Normal command 1 Abort command CMD12 CMD52 Command with 11 Determines whether command type is with data for SDIO Data DAD 0 Without data 1 With data LongRsp 10 Determines whether host receives a 136 bit long response or not 0 Short response 1 Long response NUN WaitRsp Determines whether host waits for a response or not 12 0 1 Wait response Determines whether command operation starts not This bit is Start CMST automatically cleared 0 Command ready 1 Command start Cmdindex 7 0 Command index with start 2 bit 8 bit ELECTRONICS 19 5 MMC SD SDIO CONTROLLER 53 2440 RISC MICROPROCESSOR SDI Command Status Register SDI
477. y MISCCR register Pads related USB are controlled by this register for USB host or for USB device MISCCR 0x56000080 Miscellaneous control register 0x10020 MISCCR pesened pesened 13 FUNC 22 20 Battery fault function selection 0XX In nBATT_FLT 0 The system will be in reset status After reset Change this bit to other values this bit is only for preventing from booting in Battery fault status 10X In sleep mode status when nBATT_FLT 0 the system will wake up In normal mode when nBATT_FLT 0 the Battery fault interrupt will occur 110 In sleep mode status during nBATT_FLT 0 the system will ignore all the wake up events the system will not wake up by wake up source In normal mode nBATT FLT signal cannot affect the system 111 nBATT function disable OFFREFRESH 19 0 Self refresh retain disable 1 Self refresh retain enable When 1 After wake up from sleep The self refresh will be retained nEN SCLK1 18 SCLK1 output enable 0 SCLK1 SCLK 1 SCLK1 0 nEN_SCLK0 17 SCLKO output enable 0 SCLK0 SCLK 1 SCLK 0 0 nRSTCON 16 nRSTOUT signal manual control 1 0 nRSTOUT signal level will be low 0 1 nRSTOUT signal level will be high 1 SEL SUSPND 1 13 USB Port 1 Suspend mode 0 Normal mode 1 Suspend mode SEL SUSPNDO 12 USB Port 0 Suspend mode 0 Normal mode 1 Suspend mode 9 24 ELECTRONICS 53 2440 RISC MICROPROCESSOR PORTS MISCE
478. y byte YEARDATA 7 0 BCD value for year 0x0 00 99 ELECTRONICS 17 7 REAL TIME CLOCK S3C2440A RISC MICROPROCESSOR BCD SECOND BCDSEC REGISTER BCDSEC 0x57000070 L R W BCD second register Undefined 0x57000073 B by byte SECDATA 5 4 BCD value for second 0 5 Ba ons 1 BCD MINUTE BCDMIN REGISTER BCDMIN 0x57000074 L R W BCD minute register Undefined 0x57000077 B by byte MINDATA 6 4 BCD value for minute 0 5 9 21 24 BCD HOUR BCDHOUR REGISTER BCDHOUR 0x57000078 L R W BCD hour register Undefined 0x5700007B B by byte HOURDATA 5 4 BCD value for hour EE 0 2 ors 1 24 17 8 ELECTRONICS 53 2440 RISC MICROPROCESSOR REAL TIME CLOCK BCD DATE BCDDATE REGISTER BCDDATE 0x5700007C L R W BCD date register Undefined 0x5700007F B by byte m DATEDATA 5 4 BCD value for date 0 3 Ba ors 1 24 BCD DAY BCDDAY REGISTER BCDDAY 0x57000080 L R W BCD a day of the week register Undefined 0x57000083 B by byte DAYDATA 2 0 BCD value for a day of the week 1 7 BCD REGISTER BCDMON 0x57000084 L R W BCD month register Undefined 0x57000087 B by byte m 2 MONDATA BCD value for month 0 1 Ba ors o do oo y i ELECTRONICS 17 9 REAL TIME CLOCK S3C2440A RISC MICROPROCESSOR BCD YEAR BCDYEAR REGISTER BCDYEA
479. y of CAMPCLK InvPoICAMVSYNC 25 0 Normal 1 Inverse the polarity of CAMVSYNC InvPolCAMHREF 24 0 Normal 1 Inverse the polarity of CAMHREF Y1 START ADDRESS REGISTER CICOYSA1 Ox4F000018 Y 15 frame start address for codec DMA CICOYSA1 31 0 Y 15 frame start address for codec NOTE Address of buffers must be multiple of 1024 Y2 START ADDRESS REGISTER CICOYSA2 Ox4F00001C Y 2nd frame start address for codec DMA CICOYSA2 31 0 Y 279 frame start address for codec ELECTRONICS 23 13 53 2440 RISC MICROPROCESSOR CAMERA INTERFACE Y3 START ADDRESS REGISTER CICOYSA3 0x4F000020 3nd frame start address for codec DMA CICOYSA3 Bit Description CICOYSAS3 31 0 Y 378 frame start address for codec DMA Reset Value Initial State 4 START ADDRESS REGISTER CICOYSA4 0x4F000024 Y 4th frame start address for codec DMA CICOYSA4 Bit Description CICOYSA4 31 0 Y 4th frame start address for codec DMA Reset Value Initial State CB1 START ADDRESS REGISTER CICOCBSA1 Ox4F000028 Cb 15 frame start address for codec DMA CICOCBSA1 Bit Description CICOCBSA1 31 0 Cb 15 frame start address for codec DMA Reset Value Initial State CB2 START ADDRESS REGISTER CICOCBSA2 Ox4F00002C Cb 219 frame start address for codec CICOCBSA2 Bit Description CICOCBSA2 31 0 Cb 278 frame start address for codec Reset Value Initial State 2
480. ys write back the modified base The Write back bit should not be set high W 1 when post indexed addressing is selected ELECTRONICS 3 35 ARM INSTRUCTION SET 53 2440 RISC MICROPROCESSOR HALFWORD LOAD AND STORES Setting 5 0 and 1 may be used to transfer unsigned Half words between an ARM920T register and memory The action of LDRH and STRH instructions is influenced by the BIGEND control signal The two possible configurations are described in the section below Signed byte and halfword loads The S bit controls the loading of sign extended data When 5 1 the H bit selects between Bytes H 0 and Half words 1 The L bit should not be set low Store when Signed 5 1 operations have been selected The LDRSB instruction loads the selected Byte into bits 7 to 0 of the destination register and bits 31 to 8 of the destination register are set to the value of bit 7 the sign bit The LDRSH instruction loads the selected Half word into bits 15 to 0 of the destination register and bits 31 to 16 of the destination register are set to the value of bit 15 the sign bit The action of the LDRSB and LDRSH instructions is influenced by the BIGEND control signal The two possible configurations are described in the following section Endianness and byte halfword selection Little Endian Configuration A signed byte load LDRSB expects data on data bus inputs 7 through to 0 if the supplied address is on a word boundary on data bus in

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