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USER`S MANUAL

1. 7 14 8 1 Hardware Operation During Power Down 8 2 8 2 System Operating Mode Comparison seen 8 3 8 3 Unused Pin Connections for Reducing Power Consumption 8 7 9 1 Hardware Register Values after 9 2 10 1 VO Port acit ndn t iet t te a ers 10 2 10 2 Port Pin Status During Instruction 10 2 10 3 Port Mode Group Flags eei eode enit 10 3 10 4 Pull Up Resistor Mode Register PUMOD 10 4 11 1 Basic Timer Register 11 3 11 2 Basic Timer Mode Register BMOD 11 5 11 3 Watchdog Timer Interval 11 8 11 4 TOO R gister OVERVIOW e PX ER 11 11 11 5 Settings for TCLO Edge Detection 11 14 11 6 TCO Mode Register Organization esee 11 17 11 7 TMODO 6 TMODO 5 and TMOD0 4 Bit 11 18 11 8 TC1 Register 11 23 11 9 TMOD1 Settings for Edge Detection 2 11 26 11 10 TC1 Mode Register TMOD1
2. EA HL leaves RAM location 20H with the value 3FH 00111111B and the extended accumulator with the value 75H 01110101 5 94 ELECTRONICS S3C72P9 P72P9 Preliminary Spec SAM47 INSTRUCTION SET XCHD Exchange and Decrement XCHD dst src A HL Exchange A and data memory contents decrement 1 2 5 contents of register L and skip borrow Description instruction XCHD exchanges the contents of the accumulator with the RAM location addressed by register pair HL and then decrements the contents of register L If the content of register L is OFH the next instruction is skipped The value of the carry flag is unaffected A HL A HL then L L 1 skip L Example Register pair HL contains the address 20H and internal RAM location 20H contains the value OFH LD HL 20H LD A 0H XCHD A HL lt OFHandL L 1 HL 0 JPS XXX Skipped since a borrow occurred JPS YYY H lt 2H L 0FH YYY XCHD A QGHL lt lt 2FH L L 1 OEH JPS YYY instruction is executed since a skip occurs after the XCHD instruction ELECTRONICS 5 95 SAM47 INSTRUCTION SET S3C72P9 P72P9 Preliminary Spec Exchange and Increment XCHI dst src A HL Exchange A and data memory contents increment 1 2 5 contents of register L and skip on overflow Description instruction exchanges the contents of t
3. 8 5 9 1 Timing for Oscillation Stabilization after RESET eene 9 1 10 1 Port 0 Circuit DIagEalm eee c eene e 10 5 10 2 Port 1 Circ it DIAQram s a ne do E e eb 10 6 10 3 Port 2 Circuit Diagram inhi 10 7 10 4 Port 3 Girc it DIAagrarm s cento ii ete ade ned ped 10 8 10 5 Ports 4 5 6 7 8 and 9 Circuit 10 9 Basic Timer Circuit Diagram 11 4 Circuit Diagram 11 12 11 3 EGO Timing Diagrami citt tre D bie ede 11 19 1 Circuit Diagram cci eco he fie EA ECT eire needed 11 24 11 5 TCA Timing Diagram ee om e 11 31 11 6 Watch Timer Circuit 11 36 12 1 LGD Function Diagram 12 1 12 2 ECD Circuit ene eed ees 12 2 12 3 LCD Display Data RAM Organization essen 12 3 12 4 LCD Bias Circuit 12 8 12 5 Internal Voltage Dividing Resistor and Contrast Control Circuit 1 5 Bias Display ON o eid este p te ep Er e 12 9 12 6 LCD Signal Waveforms 1 16 Duty 1 5 Bias sse 12 11 12 7 LCD Signal Waveforms 1 8 Duty 1 4 Bias 12 13 xii 3 72 9 72 9 MICROCONTR
4. ELECTRONICS S3C72P9 P72P9 Preliminary Spec ADDRESSING MODES PROGRAMMING TIP 4 Bit Addressing Modes Continued 4 Bit Indirect Addressing Example 1 1 If EMB 0 compare bank 0 locations 040 046 with bank 0 locations 060 066 ADATA EQU 46H BDATA EQU 66H SMB 1 Non essential instruction since EMB 0 LD HL BDATA LD WX ADATA COMP LD A WL lt bank 0 040H 046H CPSE A HL If bank 0 060H 066H A skip SRET DECS L JR COMP RET 2 If EMB 1 compare bank 0 locations 040 046 to bank 1 locations 160H 166H ADATA EQU 46H BDATA EQU 66H SMB 1 LD HL BDATA LD WX ADATA COMP LD A WL lt bank 0 040H 046H CPSE A HL If bank 1 160H 166H A skip SRET DECS L JR COMP RET ELECTRONICS 3 11 ADDRESSING MODES S3C72P9 P72P9 Preliminary Spec 58 PROGRAMMING TIP 4 Bit Addressing Modes Concluded 4 Bit Indirect Addressing Example 2 1 If EMB 0 exchange bank 0 locations 040H 046H with bank 0 locations 060H 066H ADATA BDATA TRANS 2 If EMB ADATA BDATA TRANS EQU EQU SMB LD LD LD XCHD JR 46H 66H 1 Non essential instruction since EMB 0 HL BDATA WX ADATA A WL bank 0 040H 046H A HL Bank 0 060 066 lt TRANS 1 exchange bank 0 locations 040 046 to bank 1 locations 160 166 EQU EQU SMB LD LD LD XCHD JR 46H 66H 1 HL BDATA WX ADATA A WL
5. 0 1 Load enable memory bank flag and the enable ERB 0 1 register bank flag ERB and program counter to vector ADR address then branch to the corresponding location Table 5 10 Program Control Instructions High Level Summary CPSE R im Compare and ll if iiia equals im 2 2 8 C a 8 FE HE Compare and skip FEA equals indirect data memory 2 258 twm Compare and skip YEA egas ue tae un der oes i508 a e ADR Les cass 2 m dump mediate adress 1 3 owx o wres e 2 __ Long eal arectin page Sun 3 faon Cal retin page oaei J o ous aon 3 mr ___ Penmon suoi fo finer Return tom erupt wer ___ ______ am 5 10 ELECTRONICS S3C72P9 P72P9 Preliminary Spec SAM47 INSTRUCTION SET Table 5 11 Data Transfer Instructions High Level Summary 2 Exchange and register Ra contents Exchange EA and register pair RRb contents A HL Exchange A and indirect data memory contents increment contents of register L and skip on carry 3 Exchange A indirect data memory contents decrement contents of register L and skip on carry Load 4 bit immediate data to A Load indirect data memory contents to A Load di
6. E 2 22 Skip Condition Flags SC2 SC1 2 23 Carry Flag G iD a navette oit toes eu eique visto rend 2 23 S3C72P9 P72P9 MICROCONTROLLER Table of Contents continued Chapter 3 Addressing Modes etd tie 3 1 and ERB Initialization Values oo eee cee ceeeeeseeeeee sees eeseeeaeseaeeceaeseaeeeaeesaeeseaeeeaeesaeeseeeeeaeeeaeeaes 3 3 Enable Memory Bank Settirgs ated E ee Rates 3 4 Select Bank Register SB Eee dierent 3 5 Select Register Bank SRB 1 12 1 211 0200000 00000 00000 00000000000 nennen nennen 3 5 Select Memory Bank SMB Instruction sse entente nennen nennen nnne 3 5 Direct and Indirect Addressirig 3 in nri ne Ire inen aio Pieri 3 6 iE s Dare o ctio 3 6 4 Bit Addressing er tite qnid dee qe eei eden 3 9 8 Brit Addressitig 2 cides koe PED teen esp 3 13 Chapter 4 Memory Map EE 4 1 Map for Hardware Registers 4 1 Register Descriptions Deed e ied o sr 4 6 Chapter 5 SAM47 Instruction Set d trei a tu tecti oett edicta ote te es dae o 5 1 Instructi
7. ERE ko ge 6 5 System Clock Mode Register 5 6 6 Switching the GPU Clock viii iste cits Gis Ho iege n ie ert ieee 6 8 Clock Output Mode Register 0 6 10 Clock Output Circuits Dp certae cet sii aie Santee ieee ode 6 11 Clock Output Procedure cca i ode ee d EP lax e te diseases 6 11 Chapter 7 Interrupts in t i el dU Re e de eU m ED REL e a dn rc 7 1 Interrupt Priority Register IPR 7 7 External Interrupt 0 1 and 2 Mode Registers IMODO IMOD1 AND 2 7 8 External Key Interrupt Mode Register 1 7 10 Interrupt 7 13 Chapter 8 Power Down OVGIVIOW to eateries a 8 1 Idle Mode Timing Diagrams sie a a 8 4 Stop Mode Timing Diagrams de ode RIP ep ee 8 5 Recommended Connections for Unused 8 7 Chapter 9 RESET OVOIVIOW OP an eai cie nii d tei 9 1 Hardware Register Values After 9 1 3C72P9 P72P9 MICROCONTROLLER vii Table of Contents continued Chapter 10 Ports OVGIVIOW TREES 10 1 Port Mode Flags
8. eu mom Far as oe ee ar a Far ss as ue us ws oo Fes o oe e mon p pepe mecnm Feo v o mo o o heo Far as as ae us oo po pep eua me _ Far as as ae s amex amon ms oA Ls ye 91914199141 A HL oo HL then L L 1 L 0H A HL then L lt L 1 E oc Eee 1 RRC A 1 1 C lt A 0 C A n 1 lt A n n 1 2 3 au SP D z9 SP 2 lt SRB SP at ELECTRONICS 5 19 E MAL 8 1 gna lt RR SAM47 INSTRUCTION SET S3C72P9 P72P9 Preliminary Spec Table 5 17 Data Transfer Instructions Binary Code Summary Concluded ame oporana Binary Code Operation Notation 1 1 2 rt RR lt SP RR lt SP 1 SP SP 2 1 1 1 1 1 SRB lt SP SMB lt SP 1 SP lt 2 94111 1 Table 5 18 Logic Instructions Binary Code Summary _ _ _ bwan code opeten noton EA EA AND RR ao
9. Input High Leakage Current Input Low Leakage Current Output High Leakage Current Output Low Leakage Current Pull Up Resistor LCD Voltage Dividing Resistor IVDD COMi Voltage Drop i 0 15 IVDD SEGx Voltage Drop x 0 55 Vict Output Voltage Vic2 Output Voltage Voltage Voltage ELECTRONICS All input pins except those LV below for ijo lLIH 7 Vpp our XTN and RESET s and XTN Lite e and XTN Yo All output pins All output pins 0 9 VUE IVpp 3V 3V 0 8V pp 0 2 0 8V pp 0 2 V 0 6V pp 0 2 0 6Vpp 0 2 0 4V pp 0 2 0 2V pp 0 2 0 2V pp 0 2 0 4V DD 0 4V pp 0 2 14 3 ELECTRICAL DATA S3C72P9 P72P9 Preliminary Spec Table 14 2 D C Electrical Characteristics Concluded Supply 5 V 10 6 0 MHz Current Crystal oscillator 4 19 MHz C1 C2 22 pF 3 V 10 6 0 MHz 4 19 MHz 2 Idle mode 6 0 MHz Vpp 5 V 10 4 19 MHz Crystal oscillator C1 C2 22 pF Vpp 3 V 10 6 0 MHz 4 19 MHz 3 V 10 32 kHz crystal oscillator Idle mode Vpp 3 V 10 32 kHz crystal oscillator Ipps Stop mode Vpp 5 V 10 Stop mode Vpp 3 V 10 Stop mode SCMOD Vpp 5 V 10 0100B Ippe 24 mode 3 V 10 NOTES 1 Data includes power consumption for subsystem clock oscillation 2 When the system clock
10. eed 11 10 aS 11 10 TCO Function SUMMA 11 10 TGO Gomponent Summary 11 11 TCO Enable Disable neinei etie tt eer 11 12 TCO Programmable Timer Counter 11 13 TCO Operation Sequernc6 ac tied cette tete tU utter m eite 11 13 T GO Event Counter FUNCION IR ette eter ttbi eee Le 11 14 TCO Glock Frequency Output tee rete 11 15 TCO Serial VO Clock 11 16 TGO External Input Signal Divider ceti ttt ee 11 16 TCO Mode Register TMO DO ie ee Aisi aac ento qb eg dae ee Do ed 11 17 TCO Counter Register 0 11 19 TCO Reference Register 0 11 20 TGO Output Enable Flag TOEO ait eek Ont einen te aee 11 20 TCO Output Latch e rae Eee eet 11 20 viii 3 72 9 72 9 MICROCONTROLLER Table of Contents continued Chapter 11 Timers and Timer Counters Continued 16 Bit Timer GOUnlter a door e RE add a Senet ae Ove MOW go Timer Counter 1 Function Timer
11. 1 A lt A HL skip on borrow EA lt EA RR skip on borrow RRb EA RRb lt RRb EA skip on borrow IR ft lt R 1 skip on borrow lets ai Ties Ta RR lt 1 skip on borrow R jJo rjo r s e rn r ReRessiponcay DA lt DA 1 skip carry as as a2 at er 1 HL lt 1 skip on carry ERES Rm jqrjojojojojrz rr o skipon cary ELECTRONICS 5 21 SAM47 INSTRUCTION SET S3C72P9 P72P9 Preliminary Spec Table 5 20 Bit Manipulation Instructions Binary Code Summary _ sr 1 b1 1 1 SkipitDAb 1 PY ele Skip if mema b 1 mema b H DA b 3 1 1 1 0 0 1 Skip if memb 7 2 L 3 2 L 1 0 1 _ _ cel Skpit H DA3 0 b 1 n 2 2 See Skip if mema b 0 o o Skip if 7 2 L 3 2 L 1 0 aes Skip if H 3 0 6 0 HRS en EM Skip if memb 7 2 L 3 2 L 1 0 1 and clear mmu con 1 1 Skip if H DA 3 0 b 1 and clear feo Fas ss oe ss us PE ETP memb L fafa t a 1 1
12. 1 lt 0 and skip BITS CFLAG Else if OBAH 0 0 OBAH O lt 1 3 8 ELECTRONICS S3C72P9 P72P9 Preliminary Spec ADDRESSING MODES 4 BIT ADDRESSING Table 3 3 4 Bit Direct and Indirect RAM Addressing Operand Addressing Mode EMB Flag Addressable Memory Hardware I O Notation Description Setting Area Bank Mapping DA Direct 4 bit address indicated 000H 07FH by the RAM address DA and F80H FFFH Bank 15 All 4 bit the memory bank selection addressable pe ripherals 1 000H FFFH SMB 0 1 SMB 15 2 3 4 15 1 000H FFFH All 4 bit addressable pe ripherals SMB 15 Indirect 4 bit address indicated X 000 Bank 0 by register WX Indirect 4 bit address indicated x 000 Bank 0 by register WL NOTE x means don t care HL Indirect 4 bit address indicated 000 Bank 0 by the memory bank selection and register HL ELECTRONICS 3 9 ADDRESSING MODES PROGRAMMING TIP 4 Bit Addressing Modes 4 Bit Direct Addressing 1 If EMB 0 ADATA EQU 46H BDATA EQU 8EH SMB 15 LD A P3 SMB 0 LD ADATA A LD BDATA A 2 If EMB 1 ADATA EQU 46H BDATA EQU 8EH SMB 15 LD A P3 SMB 0 LD ADATA A LD BDATA A 3 10 S3C72P9 P72P9 Preliminary Spec Non essential instruction since EMB 0 lt Non essential instruction since 0 046 A F8EH LCON A lt P3 046 lt
13. EA instructions jump to the address in the page in which the instruction is located However if the first byte of the instruction code is located at address xxFEH or xxFFH the instruction will jump to the next page ___ 12540 PCS to Pone WX e First Byte Ee 20 lt to pens 5 60 ELECTRONICS S3C72P9 P72P9 Preliminary Spec JR Jump Relative Very Short SAM47 INSTRUCTION SET JR Continued Examples 1 short form for a relative jump to label KK is the instruction JR KK where KK must be within the allowed range of current PC 15 to current PC 16 The JR instruction has in this case the effect of an unconditional JP instruction 2 In the following instruction sequence if the instruction LD WX 02H were to be executed in place of LD WX 00H the program would jump to 1004H and JPS would be executed If LD WX 03H were to be executed the jump would be to1006H and DDD would be executed ORG 1000H JPS AAA JPS BBB JPS CCC JPS DDD XXXLD WX 00H LD EA WX ADS WX EA JR WX 3 Here is another example ORG 1100H LD A 0H LD LD LD A 3H LD 30H A JPS YYY XXXLD EA 00H JR EA WX lt 00H WX lt WX EA Current PC12 8 10H WX 00
14. SP 2 ERB SP 4 PC7 0 SP 6 PC14 8 ELECTRONICS S3C72P9 P72P9 Preliminary Spec SAM47 INSTRUCTION SET PC PC 2 to 16 PC PC 1 to PC 15 PC14 8 lt SP 1 SP PC7 0 lt SP 3 SP 2 EMB ERB lt SP 5 SP 4 SP lt SP 6 PC14 8 lt SP 1 SP PC7 0 lt SP 3 SP 2 PSW lt SP 5 SP 4 SP lt SP 6 14 8 SP 1 SP PC7 0 SP 3 SP 2 lt SP 5 SP 4 SP lt 6 ELECTRONICS 5 17 SAM47 INSTRUCTION SET S3C72P9 P72P9 Preliminary Spec Table 5 17 Data Transfer Instructions ae Code Summary Binary Code Operation Notation Notation A DA 1 1 47 a5 4 as 2 at a0 AGRa o AeRRo EU 1 1 AG DAEGDA 1 lt gt RRb HL 1 HL then L lt L 1 skip if L OH D skip L LD ra a ao cim wen re e um obese Far as as se ur ENEZEXERENEZEZESZ 2 5 18 ELECTRONICS S3C72P9 P72P9 Preliminary Spec SAM47 INSTRUCTION SET Table 5 17 Data Transfer Instructions Binary Code Summary Continued Binary Code Operation Notation wm Fe o fo
15. 1 4 1 3 1 8 1 4 Pin Gircuit Ainest ini ig en ai eia 1 8 1 5 25 5 nce tou eee bebe Raia 1 8 1 6 Pint Gircuit Ty pe estes ue nf ede d aa 1 8 1 7 Piri Gircuit Typa E e 1 9 1 8 PirrGircuit Type E 1 ee eres tute Ier reato adn 1 9 1 9 Pin Circuit uoti eterne tite 1 10 1 10 Piri Gircuit Type oii e e i et 1 11 1 11 Pin Circuit Type H 13 Ee tue eerte a 1 11 1 12 Pin Circuit Type paar tete tige 1 12 1 13 Gircult Type H 1O yee ee acd ad vede EIER aeree de ee pee 1 12 2 1 ROM Address Str ctutre 2 2 2 2 Vector Address Map i eie Re de een cte dox OR shed a even ae 2 2 2 3 Data Memory RAM 2 8 2 4 Working Register Map eiecit oct ente titii ie her eed 2 11 2 5 Register Pair Configuration 2 12 2 6 1 Bit 4 Bit and 8 Bit Accumulator 2 13 2 7 Push Type Stack 2 16 2 8 Pop Type Stack Operations teo err tessa acts ten eee aes 2 17 3 1 RAM Address Struct re cidit de edge decedit edet dens 3 2 3 2 SMB SRB Values in the SB 3 5 4 1 Register Descriptio
16. 7 2 3 2 1 0 1 25 a4 as 22 o bt as at ao 5 22 ELECTRONICS S3C72P9 P72P9 Preliminary Spec SAM47 INSTRUCTION SET Table 5 20 Bit Manipulation Instructions Binary Code Summary Continued Binary Code Operation Notation 2 pese ue er er a m PB o memb L 1 1 1 4 4 1 1 Imemo7 2 L3 2 L 1 0 0 H DAb 1 1 1 1 1 1 1 0 1 0 o C mema b EEERERENERERERES C amp C AND mema b poen C memb L C amp C AND memb 7 2 L 3 2 L 1 0 rao o s os C H DA b pipe eae ise fas ae C C AND H DA 3 0 b o bt aa at a0 C mema b C amp C OR mema b C memb L C OR memb 7 2 L 3 2 L 1 0 Fe o as a C H DA b C H DA 3 0 b 2 C mema b mma C C XOR mema b C memb L 1 C C XOR memb 7 2 L 3 2 L 1 0 es a C H DAb 1 1 1 0 1 1 DA2 0 b o o as 22 20 Second Byte 0 Addresses Addresses memab eere e Far rera s 22 ao Fron ELECTRONICS 5 23 SAM47 INSTRUCTION SET S3C72P9 P72P9 Preliminary Spec Table 5 20 Bit Manipulation Instructions Bin
17. LD H 0AH BTSTZ QH FLAG If bank 0 AH 0H 0 1 clear and skip BITS H FLAG 0 then lt 1 5 44 ELECTRONICS S3C72P9 P72P9 Preliminary Spec SAM47 INSTRUCTION SET BXOR Bit Exclusive OR BXOR C src b Exclusive OR carry with memory bit SS C memb L C H DA b Description specified bit of the source is logically XORed with the carry bit value The resultant bit is written to the carry flag The source value is unaffected Binary Code Operation Notation C mema b C amp C mema b C memb L pee e C memb 7 2 L 3 2 L 1 0 0 150 0 as a4 c HDAb 1 1 1 1 0 1 1 XOR H DA3 0 b o bt a2 Jat Second Byte BitAddresses Addresses ________ 1 bt as 2 FFonFF Examples 1 flag is logically XORed with the P1 0 value RCF BXOR C P1 0 If P1 0 1 then C lt 1 if P1 0 0 then 2 The P1 address is FF1H and register L contains the value 1H 0001B The address memb 7 2 is 111100B and L 3 2 00B The resulting address is 11110000B or FFOH specifying PO The bit value for the BXOR instruction L 1 0 15 01B which specifies bit 1 Therefore P1 L 1 LD L 0001B BXOR C P0 L P1 QL is specified as P0 1 1 ELECTRONICS 5 45
18. SMB F83H SRB F82H Bn SMB3 SMB2 SMB 1 SMB 0 rele SRB 1 SRB 0 Figure 3 2 SMB and SRB Values in the SB Register SELECT REGISTER BANK SRB INSTRUCTION The select register bank SRB value specifies which register bank is to be used as a working register bank The SRB value is set by the SRB n instruction where 0 1 2 3 One of the four register banks is selected by the combination of ERB flag status and the SRB value that is set using the SRB n instruction The current SRB value is retained until another register is requested by program software PUSH SB and POP SB instructions are used to save and restore the contents of SRB during interrupts and subroutine calls RESET clears the 4 bit SRB value to logic zero SELECT MEMORY BANK SMB INSTRUCTION To select one of the six available data memory banks you must execute an SMB n instruction specifying the number of the memory bank you want 0 1 2 3 4 or 15 For example the instruction SMB 1 selects bank 1 and SMB 15 selects bank 15 And remember to enable the selected memory bank by making the appropriate EMB flag setting The upper four bits of the 12 bit data memory address are stored in the SMB register If the SMB value is not specified by software or if a RESET does not occur the current value is retained RESET clears the 4 bit SMB value to logic zero The PUSH SB and POP SB instructions save and restore
19. or LD HL imm is written more than two times in succession only the first LD will be executed the other similar instructions that immediately follow the first LD will be treated like a NOP This is called the redundancy effect see examples below ADA ELECTRONICS 5 63 SAM47 INSTRUCTION SET S3C72P9 P72P9 Preliminary Spec L D Load LD Continued Description Binary Gods Ope onNosion mam afee ano eua 1 Far as a5 as us at 0 ee __ pp epe np owe Examples 1 RAM location contains the value 4H The RAM location values are 40H 41H and OAH 3H respectively The following instruction sequence leaves the value 40H in point pair HL OAH in the accumulator and in RAM location 40H and 3H in register E LD HL 30H HL lt 30H LD A HL A lt 4H LD HL 40H HL lt 40H LD EA lt LD HL A RAM 40H lt OAH 5 64 ELECTRONICS S3C72P9 P72P9 Preliminary Spec SAM47 INSTRUCTION SET LD Load LD Continued Examples 2 If an instruction such as LD A im LD EA imm or LD HL imm is written more than two times in succession o
20. 5 8 ELECTRONICS S3C72P9 P72P9 Preliminary Spec SAM47 INSTRUCTION SET HIGH LEVEL SUMMARY This section contains a high level summary of the SAM47 instruction set in table format The tables are designed to familiarize you with the range of instructions that are available in each instruction category These tables are a useful quick reference resource when writing application programs If you are reading this user s manual for the first time however you may want to scan this detailed information briefly and then return to it later on The following information is provided for each instruction Instruction name Operand s Brief operation description Number of bytes of the instruction and operand s Number of machine cycles required to execute the instruction The tables in this section are arranged according to the following instruction categories CPU control instructions Program control instructions Data transfer instructions Logic instructions Arithmetic instructions Bit manipulation instructions ELECTRONICS 5 9 SAM47 INSTRUCTION SET S3C72P9 P72P9 Preliminary Spec Table 5 9 CPU Control Instructions High Level Summary s 2 s Engage CPU 8 mer
21. Jy ne and are igh pony oo owNmmempssangpiny __ f ttf nly NT interrupts is at high priory o1 0 interrupts is at high priority o1 otf Only INTO interrupts is at high priority o1 1 0 interrupts is at high priority NOTE When interrupts are low priority the lower three bits of the IPR register are logic zero the interrupt requested first will have high priority Therefore the first request interrupt cannot be superceded by any other interrupt If two or more interrupt requests are received simultaneously the priority level is determined according to the standard interrupt priorities in Table 7 3 the default priority assigned by hardware when the lower three IPR bits 0 In this case the higher priority interrupt request is serviced and the other interrupt is inhibited Then when the high priority interrupt is returned from its service routine by an IRET instruction the inhibited service routine is started ELECTRONICS 7 7 INTERRUPTS S3C72P9 P72P9 Preliminary Spec PROGRAMMING Setting the INT Interrupt Priority The following instruction sequence sets the INT1 interrupt to high priority BITS EMB SMB 15 DI lt 0 LD A 3H LD IPR A EI IPR 3 IME 1 EXTERNAL INTERRUPT 0 1 AND 2 MODE REGISTERS IMODO IMOD1 AND IMOD2 The following components are used to process external interrupts at the INTO INT1 and INT2
22. mw owo s v w no ves No Locations FD1H FD5H are not mapped FD6H FD7H Locations FD9H is not mapped roa vw v o wj Ye Locations FDBH is not mapped Locations FDFH is not mapped Locations 2 are not SBUF 4 4 ELECTRONICS 3 72 9 72 9 Preliminary Spec MEMORY MAP Table 4 1 Map for Memory Bank 15 Concluded Memory Bank 15 Addressing Mode m em Yes Yes No me a E ES 3 3 3 3 2 4 2 41 0 rons s 2 1 em s 2 5 Locations FFAH FFFH are not mapped IN NOTES 1 the WMOD register is read only 2 0 F9AH 1 and F9AH 2 are fixed to 0 3 Thecarry flag can be read or written by specific bit manipulation instructions only 4 The means that the bit is undefined ELECTRONICS 4 5 MEMORY MAP S3C72P9 P72P9 Preliminary Spec REGISTER DESCRIPTIONS In this section register descriptions are presented in a consistent format to familiarize you with the memory mapped locations in bank 15 of the RAM Figure 4 1 describes features of the register description format Register descriptions are arranged in alphabetical order Programmers can use this section as a quick reference so
23. OFFH OH OFEH EMB ERB OFDH 2H OFCH OFBH OFAH 1H PC Data is written to stack locations OFFH OFAH as follows SP 6 SP 5 SP 4 SP 3 SP 2 SP 1 SP gt ELECTRONICS 5 47 SAM47 INSTRUCTION SET S3C72P9 P72P9 Preliminary Spec CALLS Procedure Short CALLS dst Description Example SP 6 SP 5 SP 4 SP 3 SP 2 SP 1 SP gt 5 48 The CALLS instruction unconditionally calls a subroutine located at the indicated address The instruction increments the PC twice to obtain the address of the following instruction Then it pushes the result onto the stack decreasing the stack pointer six times The higher bits of the PC with the exception of the lower 11 bits are cleared The CALLS instruction can be used in the all range 0000H 7FFFH but the subroutine call must therefore be located within the 2 byte block 0000H 07FFH of program memory a E 10 a9 SP 1 SP 2 lt ERB EN a SP 3 SP 4 lt PC7 0 SP 5 SP 6 lt PC14 8 The stack pointer value is 00H and the label PLAY is assigned to program memory location 0345H Executing the instruction CALLS PLAY at location 0123H will generate the following values SP OFFH OFEH EMB ERB OFDH 2H OFCH OFBH OFAH 1H PC 0345H Data is written to stack locations OFFH OFAH as follows
24. The watch timer WT module consists of an 8 bit watch timer mode register a clock selector and a frequency divider circuit Watch timer functions include real time and watch time measurement main and subsystem clock interval timing buzzer output generation It also generates a clock signal for the LCD controller ELECTRONICS 11 1 TIMERS and TIMER COUNTERS S3C72P9 P72P9 Preliminary Spec BASIC TIMER BT OVERVIEW The 8 bit basic timer BT has six functional components Clock selector logic 4 bit mode register BMOD 8 bit counter register BCNT 8 bit watchdog timer mode register WDMOD Watchdog timer counter clear flag WDTCF The basic timer generates interrupt requests at precise intervals based on the frequency of the system clock You can use the basic timer as a watchdog timer for monitoring system events or use BT output to stabilize clock oscillation when stop mode is released by an interrupt and following RESET Bit settings in the basic timer mode register BMOD turns the BT module on and off selects the input clock frequency and controls interrupt or stabilization intervals Interval Timer Function The basic timer s primary function is to measure elapsed time intervals The standard time interval is equal to 256 basic timer clock pulses To restart the basic timer one bit setting is required bit 3 of the mode register BMOD should be set to logic one The input clock frequency and the
25. in bank 0 are addressable regardless of SMB value To address the peripheral hardware register bank 15 using indirect addressing the EMB flag must first be set to 1 and the SMB value to 15 When a RESET occurs the EMB flag is set to the value contained in bit 7 of ROM address 0000H EMB Independent Addressing At any time several areas of the data memory can be addressed independent of the current status of the EMB flag These exceptions are described in Table 3 1 Table 3 1 RAM Addressing Not Affected by the EMB Value Address Addressing Method Affected Hardware Program Examples 000H 0FFH 4 bit indirect addressing using WX Not applicable and WL register pairs 8 bit indirect addressing using SP FBOH FBFH 1 bit direct addressing PSW SCMOD BITS FFOH FFFH IEx IRQx I O IE4 FCOH FFFH 1 bit indirect addressing using the BSC BTST FC3H L L register BAND C P3 L 3 4 ELECTRONICS S3C72P9 P72P9 Preliminary Spec ADDRESSING MODES SELECT BANK REGISTER SB The select bank register SB is used to assign the memory bank and register bank The 8 bit SB register consists of the 4 bit select register bank register SRB and the 4 bit select memory bank register SMB as shown in Figure 3 2 During interrupts and subroutine calls SB register contents can be saved to stack in 8 bit units by the PUSH SB instruction You later restore the value to the SB using the POP SB instruction 4
26. oso Example The label SYSCON is assigned to the instruction at program location 5FFFH The instruction LJP SYSCON at location 0123H will load the program counter with the value 5FFFH ELECTRONICS 5 73 SAM47 INSTRUCTION SET S3C72P9 P72P9 Preliminary Spec NOP No Operation NOP Operation Operation Summary Bytes Cycles 7407134 Description operation is performed by a NOP instruction It is typically used for timing delays One NOP causes a 1 cycle delay with a 1 us cycle time five NOPs would therefore cause a 5 us delay Program execution continues with the instruction immediately following the NOP Only the PC is affected At least three NOP instructions should follow a STOP or IDLE instruction Binary Code Operation Notation __ ___ fod Nooperation Three NOP instructions follow the STOP instruction to provide short interval for clock stabilization before power down mode is initiated STOP NOP NOP NOP 5 74 ELECTRONICS S3C72P9 P72P9 Preliminary Spec SAM47 INSTRUCTION SET OR Logical OR OR dst src Logical OR immediate data to A A HL Logical OR indirect data memory contents to A RRb EA Logical OR EA to double register Description The source operand is logically ORed with the destination operand The result is stored in the destination The contents of the source are unaffected Operand Binary Code Operation Notation A i
27. 0 ADS EA HL EA lt 0C3H 0AAH 6DH ADS skips on overflow but carry flag value is not affected JPS XXX This instruction is skipped since ADS had an overflow JPS YYY Jump to YYY 5 28 ELECTRONICS S3C72P9 P72P9 Preliminary Spec SAM47 INSTRUCTION SET ADS Add and Skip on Overflow ADS Examples Continued 2 If the extended accumulator contains the value OC3H register pair HL the value 12H and the carry 0 ADS EA HL lt 12H 005 JPS XXX Jump to XXX no skip after ADS 3 If ADC A HL is followed by an ADS the ADC skips on overflow to the instruction mmediately after the ADS An ADS instruction immediately after the ADC A HL does not skip even if overflow occurs This function is useful for decimal adjustment operations 8 9 decimal addition the contents of the address specified by the HL register is RCF 0 LD A 8H ADS A 6H lt 8H 6H ADC A HL lt 9H C 0 7H lt 1 ADS A 0AH Skip this instruction because 1 after ADC result JPS XXX b 344 decimal addition the contents of the address specified by the HL register is RCF 0 LD A 3H A lt 3H ADS A 6H A 3H 6H 9H A HL lt 9H 4H C 0 C lt 0 ADS A 0AH skip lt OAH 7H The skip function for ADS A im is inhibited
28. 0 lt 1 ELECTRONICS 5 35 SAM47 INSTRUCTION SET S3C72P9 P72P9 Preliminary Spec BITS Bit set BITS Continued Examples LD BP2 BITS INCS CPSE JR 3 For setting P0 2 0 3 and P1 0 P1 3 to 1 L 2H PO L First PO 02H PO 2 111100B 00B 10B 2 L L 8H BP2 4 If bank 0 location is set to 1 and the 0 BITS has the following effect FLAG EQU LD BITS 0 H 0AH H FLAG Bank 0 AH 0 lt 1 NOTE Since the BITS instruction is used for output functions pin names used in the examples above may change for different devices in the SAM47 product family 5 36 ELECTRONICS S3C72P9 P72P9 Preliminary Spec SAM47 INSTRUCTION SET BOR Bit Logical OR BOR C src b Logical OR carry with specified memory bit SS C memb L C H DA b Description specified bit of the source is logically ORed with the carry flag bit value The value of the source is unaffected Binary Code Operation Notation C amp C memab C memb L OR memb 7 2 L 3 2 L 1 0 0 1 00 a4 c HDAb 1 1 1 14 1 0 OR 3 0 o o bt bo a2 20 Second Byte BitAddesses Addresses FFonFF Examples 1 The carry flag is logically ORed with the P1 0 v
29. 1 8V to 5 5 V Instruction Cycle Vpp 2 7 V to 5 5V Time note TCLO TCL1 Input fq fm Frequency E SCK Cycle Time luy 8 3 TCLO TCL1 Input trio trio Vpp 2 7 V to 5 5 V High Low Width trun s 1 6 SCK High Low tk 2 7 V to 5 5 V Input 2 Width 5 1 Internal SCK source Output Vpp 2 0 V to 5 5 V Input 1600 Internal S CK source Output SI Setup Time to tok 2 7 V to 5 5 V Input 100 SCK High 27 V to 5 5 V Output Vpp 2 0 V to 5 5 V Vpp 2 0 V to 5 5 V Output 5 SI Hold Time to tks 2 7 V to 5 5 V Input 40 SCK High Vpp 27 V to 5 5 V Output Vpp 2 0 V to 5 5 V Input 2 0 V to 5 5 V Output NOTE Unless otherwise specified Instruction Cycle Time condition values assume a main system clock fx source 67 95 48 8 00 50 5 0 50 0 0 0 0 I 14 8 ELECTRONICS 557 22532 22532 Preliminary Spec ELECTRICAL DATA Table 14 8 A C Electrical Characteristics Continued Ta 40 C to 85 1 8V to 5 5 V Output Delay for tkso 2 7 V to 5 5 V Input SCK to SO 2 7 V to 5 5 V Output Vpp 2 0 V to 5 5 V Input 2 0 V to 5 5 V Output TU Mn INT2 INT4 10 NOTE Minimum value for INTO is based on a clock of 2toy or 128 fx as assigned by the IMODO register setting Main Oscillator Frequency CPU Clock Divided by 4 iE uu Ld
30. Contents addressed by RR Interrupt priority register IPR Enable memory bank flag EMB Enable register bank flag ERB ELECTRONICS 5 7 SAM47 INSTRUCTION SET S3C72P9 P72P9 Preliminary Spec OPCODE DEFINITIONS Table 5 7 Opcode Definitions Direct Table 5 8 Opcode Definitions Indirect _2 d HL 1 0 1 WX 1 1 0 WL 1 1 1 i Immediate data for indirect addressing 0 0 0 0 1 1 1 1 0 0 1 1 sesel e e ofa r Immediate data for register CALCULATING ADDITIONAL MACHINE CYCLES FOR SKIPS A machine cycle is defined as one cycle of the selected CPU clock Three different clock rates can be selected using the PCON register In this document the letter S is used in tables when describing the number of additional machine cycles required for an instruction to execute given that the instruction has a skip function 5 skip The addition number of machine cycles that will be required to perform the skip usually depends on the size of the instruction being skipped whether it is a 1 byte 2 byte or 3 byte instruction A skip is also executed for SMB and SRB instructions The values in additional machine cycles for S for the three cases in which skip conditions occur are as follows Case 1 No skip S 0 cycles Case 2 Skip is 1 byte or 2 byte instruction 1 cycle Case 3 Skip is 3 byte instruction S 2 cycles NOTE REF instructions are skipped in one machine cycle
31. SAM47 INSTRUCTION SET S3C72P9 P72P9 Preliminary Spec BXOR Bit Exclusive OR BXOR Examples 5 46 Continued 3 Register H contains the value 2H and FLAG 20H 3 The address of H is 0010B and FLAG 3 0 is 0000B The resulting address is 00100000B or 20H The bit value for the BOR instruction is 3 Therefore H FLAG 20H 3 FLAG EQU 20H 3 LD H 2H BXOR C H FLAG XOR FLAG 20H 3 ELECTRONICS S3C72P9 P72P9 Preliminary Spec SAM47 INSTRUCTION SET CALL Call Procedure CALL dst Operation Operand Operation Summary An page 14 bis s 4 Description calls a subroutine located at the destination address The instruction adds three to the program counter to generate the return address and then pushes the result onto the stack decreasing the stack pointer by six The EMB and ERB are also pushed to the stack Program execution continues with the instruction at this address The subroutine may therefore begin anywhere in the full 16 K byte program memory address space operand Binary Gode operation Notation La ID D o re ear ere o ara az ar aro ao ise y par as as as se 18959 Gen Example The stack pointer value is 00H and the label PLAY is assigned to program memory location OESFH Executing the instruction CALL PLAY at location 0123H will generate the following values SP
32. SP 1 SP PC7 0 lt 5 3 SP 2 EMB ERB lt SP 5 SP 4 SP lt SP 6 Example If the stack pointer contains the value OFAH and RAM locations OFAH OFBH OFCH and OFDH contain the values 1H OH 5H and 2H respectively the instruction SRET leaves the stack pointer with the value OOH and the program returns to continue execution at location 0125H then skips unconditionally During a return from subroutine data is popped from the stack to the PC as follows SP gt PC11 PC8 SP 1 14 PC13 PC12 SP 2 PC3 PCO SP 3 4 5 6 5 90 ELECTRONICS S3C72P9 P72P9 Preliminary Spec SAM47 INSTRUCTION SET STOP STOP Operation Description Example Stop Operation The STOP instruction stops the system clock by setting bit 3 of the power control register PCON to logic one When STOP executes all system operations are halted with the exception of some peripheral hardware with special power down mode operating conditions In application programs a STOP instruction must be immediately followed by at least three NOP instructions This ensures an adequate time interval for the clock to stabilize before the next instruction is executed If three or more NOP instructions are not used after STOP instruction leakage current could be flown because of the floating state in the internal bus Given that bit 3 of the
33. 1 If EMB 0 ADATA EQU 46H SMB 1 Non essential instruction since EMB 0 LD HL ZADATA LD EA HL lt 046H E lt 047H 2 If EMB 1 ADATA EQU 46H SMB 1 LD HL ZADATA LD EA QHL A lt 146H lt 147H 3 14 ELECTRONICS 3 72 9 72 9 Preliminary Spec MEMORY MAP MEMORY MAP OVERVIEW To support program control of peripheral hardware I O addresses for peripherals are memory mapped to bank 15 of the RAM Memory mapping lets you use a mnemonic as the operand of an instruction in place of the specific memory location Access to bank 15 is controlled by the select memory bank SMB instruction and by the enable memory bank flag EMB setting If the EMB flag is 0 bank 15 can be addressed using direct addressing regardless of the current SMB value 1 bit direct and indirect addressing can be used for specific locations in bank 15 regardless of the current EMB value MAP FOR HARDWARE REGISTERS Table 4 1 contains detailed information about I O mapping for peripheral hardware in bank 15 register locations F80H FFFH Use the I O map as a quick reference source when writing application programs The I O map gives you the following information Register address Register name mnemonic for program addressing Bit values both addressable and non manipulable Read only write only or read and write addressability 1 bit 4 bit or 8 bit data manipulation characteristics ELEC
34. 1 8 MACHINE CYCLES N A 1 MACHINE CYCLES PCON 1 1 16 MACHINE CYCLES 1 MACHINE CYCLES N A fx 4 NOTES 1 Even if oscillation is stopped by setting SCMOD 3 during main system clock operation the stop mode is not entered 2 Since the Xyinput is connected internally to Vgs to avoid current leakage due to the crystal oscillator in stop mode do not set SCMOD 3 to 1 or do not use stop instruction when an external clock is used as the main system clock 3 When the system clock is switched to the subsystem clock it is necessary to disable any interrupts which may occur during the time intervals shown in Table 6 4 N A means not available 5 fx Main system clock fxt Sub system clock When fx is 4 19 MHz and fxt is 32 768 kHz 6 8 ELECTRONICS S3C72P9 P72P9 Preliminary Spec OSCILLATOR CIRCUITS PROGRAMMING Switching Between Main System and Subsystem Clock 1 Switch from the main system clock to the subsystem clock MA2SUB BITS SCMOD 0 Switches to subsystem clock CALL DLY80 Delay 80 machine cycles BITS SCMOD 3 Stop the main system clock RET DLY80 LD A 0FH DEL1 NOP NOP DECS A JR DEL1 RET 2 Switch from the subsystem clock to the main system clock SUB2MA BITR SCMOD 3 Start main system clock oscillation CALL DLY80 Delay 160 machine cycles CALL DLY 80 BITR SCMOD 0 Switch to main system clock RET ELECTRONICS 6 9 OSCILLATOR CIRCUITS S3C72P9 P72P9 Preliminary Spec CLOCK OUTP
35. LD LD LD 5 66 EA HL EA DA EA RRb HL A DA EA RRb EA HL EA S3C72P9 P72P9 Preliminary Spec Operation Description and Guidelines Load data memory contents pointed to by 8 bit register HL to the A register and the contents of HL 1 to the E register The contents of register L must be an even number If the number is odd the LSB of register L is recognized as a logic zero an even number and it is not replaced with the true value For example LD HL 36H loads immediate 36H to HL and the next instruction LD EA HL loads the contents of 36H to register A and the contents of 37H to register E Load direct data memory contents of DA to the A register and the next direct data memory contents of DA 1 to the E register The DA value must be an even number If it is an odd number the LSB of DA is recognized as a logic zero an even number and it is not replaced with the true value For example LD EA 37H loads the contents of 36H to the A register and the contents of 37H to the E register Load 8 bit RRb register HL WX YZ to the EA register H W and Y register values are loaded into the E register and the L X and Z values into the A register Load A register contents to data memory location pointed to by the 8 bit HL register value Load the A register contents to direct data memory and the E register contents to the next direct data memory location The DA value must be an even number If
36. The following instruction sequence leaves the value OFFH in register A Since a borrow occurs the CALL PLAY1 instruction is skipped and the CALL PLAY2 instruction is executed DECS A Borrow occurs CALL PLAY1 Skipped CALL PLAY2 Executed 5 52 ELECTRONICS S3C72P9 P72P9 Preliminary Spec SAM47 INSTRUCTION SET DI Disable Interrupts DI Operation Operation Summary Bytes Cycles Description Bit of the interrupt priority register IPR IME is cleared to logic zero disabling all interrupts Interrupts can still set their respective interrupt status latches but the CPU will not directly service them ERERBBBEITU __ fee Ee Example If the IME bit bit 3 of the IPR is logic one e g all instructions are enabled the instruction sets the IME bit to logic zero disabling all interrupts ELECTRONICS 5 53 SAM47 INSTRUCTION SET S3C72P9 P72P9 Preliminary Spec El Enable Interrupts El Operation Operation Summary Bytes Cycles Description Bit of the interrupt priority register IPR IME is set to logic one This allows all interrupts to be serviced when they occur assuming they are enabled If an interrupt s status latch was previously enabled by an interrupt this interrupt can also be serviced If the IME bit bit 3 of the IPR is logic zero 0 all instructions are disabled the instru
37. bank EMB and enable register bank ERB flag values that are needed to initialize the service routines 16 byte vector addresses are organized as follows To set up the vector address area for specific programs use the instruction VENTn The programming tips on the next page explain how to do this Vector Address Area 16 Bytes General Purpose Area 16 Bytes Instruction Reference Area 96 Bytes General Purpose Area 32 640 Bytes Figure 2 1 ROM Address Structure Figure 2 2 Vector Address Map 2 2 ELECTRONICS S3C72P9 P72P9 Preliminary Spec 59 PROGRAMMING Defining Vectored Interrupts ADDRESS SPACES The following examples show you several ways you can define the vectored interrupt and instruction reference areas in program memory 1 When all vector interrupts are used ORG VENTO VENT1 VENT2 VENT4 VENT5 VENT6 VENT7 0000H 1 0 RESET 0 0 INTB 0 0 INTO 0 0 INT1 0 0 INTS 0 0 INTTO 0 01 1 0 0 INTK EMB EMB EMB EMB EMB EMB EMB EMB TT T FT 1 ERB 0 ERB 0 ERB 0 ERB 0 ERB 0 ERB 0 ERB 0 ERB c amp lt amp amp 0 Jump to RESET address by RESET 0 Jump to INTB address by INTB 0 Jump to INTO address by INTO 0 Jump to INT1 address by INT1 0 Jump to INTS address by INTS 0 Jump to INTTO address by INTTO 0 Jump to INTT1 address by INTT1 0 Jump to INTK address by INTK 2 When a specific vecto
38. lt bank 0 040H 046H A HL Bank 1 16 166 TRANS ELECTRONICS S3C72P9 P72P9 Preliminary Spec ADDRESSING MODES 8 BIT ADDRESSING Table 3 4 8 Bit Direct and Indirect RAM Addressing Instruction Addressing Mode EMB Flag Addressable Memory Hardware I O Notation Description Setting mc pe Direct 8 bit address indicated 000 07 07FH Banko 0 by the RAM address DA F80H FFFH Bank 15 so 8 bit even number and memory addressable pe bank selection ripherals 000H FFFH SMB 0 1 SMB 15 2 3 4 15 Indirect the 8 bit address indi 000 Bank 0 cated by the memory bank selection and register HL the 4 bit L register value must be an even number 1 000H FFFH All 8 bit 1 addressable pe ripherals SMB 15 PROGRAMMING 8 Bit Addressing Modes 8 Bit Direct Addressing 1 If EMB 0 ADATA EQU 46H BDATA EQU 8EH SMB 15 Non essential instruction since EMB 0 LD EA P4 lt lt P4 SMB 0 LD ADATA EA 046 lt 047 lt LD BDATA EA FBEH lt lt E 2 If EMB 1 ADATA EQU 46H BDATA EQU 8EH SMB 15 LD EA P4 lt lt P4 SMB 0 LD ADATA EA 046 lt 047 lt LD BDATA EA lt 08 lt E ELECTRONICS 3 13 ADDRESSING MODES S3C72P9 P72P9 Preliminary Spec 58 PROGRAMMING TIP 8 Bit Addressing Modes Continued 8 Bit Indirect Addressing
39. so the user should link object file Object files can be linked with other object files and loaded into memory HEX2ROM HEX2ROM file generates ROM code from HEX file which has been produced by assembler ROM code must be needed to fabricate a microcontroller which has a mask ROM When generating the ROM code file by HEX2ROM the value is filled into the unused ROM area up to the maximum ROM size of the target device automatically TARGET BOARDS Target boards are available for all KS57 series microcontrollers All required target system cables and adapters are included with the device specific target board OTPs One time programmable microcontroller OTP for the S3C72P9 microcontroller and OTP programmer Gang are now available ELECTRONICS 17 1 DEVELOPMENT TOOLS 17 2 IBM PC AT or Compatible RS 232C SMDS2 gt PROM OTP Writer Unit lt gt Break Display Unit 5 lt gt Trace Timer Unit SAM4 Base Unit gt Power Supply Unit S3C72P9 P72P9 Preliminary Spec Target Application System Probe Adapter TB72P9 Target Board EVA Chip Figure 17 1 SMDS Product Configuration SMDS2 ELECTRONICS S3C72P9 P72P9 Preliminary Spec DEVELOPMENT TOOLS TB72P9 TARGET BOARD The TB72P9 target board is used for the S3C79P9 microcontroller It is supported by the SMDS2 development system TB72P9 To User Vcc Stop Idle 74 11 2 B XTAL O
40. the IRQx flag is cleared automatically when the interrupt has been serviced When two interrupts are enabled the request flag is not automatically cleared so that the user has an opportunity to locate the source of the interrupt request In this case the IRQx setting must be cleared manually using a BTSTZ instruction Table 7 8 Interrupt Request Flag Conditions and Priorities Source External Priority Name INTS Completion signal for serial transmit and receive IRQS or receive only operation INTO Signals for TCNTO and TREFO registers match Signals for TCNT1 and TREF1 registers match 6 INTK E When a rising or falling edge detected at any 7 IRQK one of the K0 K7 pins INT2 Rising or falling edge detected at INT2 mae Ls Time interval of 0 5 secs or 3 19 msecs 7 14 ELECTRONICS S3C72P9 P72P9 Preliminary Spec INTERRUPTS 59 PROGRAMMING Enabling the INTB and INT4 Interrupts To simultaneously enable INTB and INT4 interrupts INTB INT4 DI BTSTZ IRQB JR INT4 EI IRET BITR IRQ4 EI IRET ELECTRONICS 1 If no INT4 interrupt if yes INTB interrupt is processed INT4 is processed INTERRUPTS S3C72P9 P72P9 Preliminary Spec NOTES 7 16 ELECTRONICS 3 72 9 72 9 Preliminary Spec POWER DOWN POWER DOWN OVERVIEW The S3C72P9 microcontroller has two power down modes to reduce power consumption idle and sto
41. whose value is automatically incremented by counter logic An 8 bit mode register TMODO is used to activate the timer counter and to select the basic clock frequency to be used for timer counter operations To dynamically modify the basic frequency new values can be loaded into the TMODO register during program execution TCO FUNCTION SUMMARY 8 bit programmable timer Generates interrupts at specific time intervals based on the selected clock fre quency External event counter Counts various system events based on edge detection of external clock sig nals at the TCO input pin TCLO To start the event counting operation TMODO 2 is set to 1 and TMODO 6 is cleared to 0 Arbitrary frequency output Outputs selectable clock frequencies to the TCO output pin TCLOO External signal divider Divides the frequency of an incoming external clock signal according to a modi fiable reference value TREFO and outputs the modified frequency to the TCLOO pin Serial I O clock source Outputs a modifiable clock signal for use as the SCK clock source 11 10 ELECTRONICS S3C72P9 P72P9 Preliminary Spec TIMERS and TIMER COUNTERS TCO COMPONENT SUMMARY Mode register Activates the timer counter and selects the internal clock frequency or the external clock source at the TCLO pin Reference register TREFO Stores the reference value for the desired number of clock pulses between in terrupt requests Counter register TCNTO Co
42. 0 0 0 0 0 0 0 Read Write W W W W W W W W Bit Addressing 8 8 8 8 8 8 8 8 7 Bit 7 0 Always logic 0 PNE1 6 P2 2 N Channel Open Drain Configurable Bit Configure 2 2 as a push pull Configure P2 2 as a n channel open drain PNE1 5 P2 1 N Channel Open Drain Configurable Bit Configure P2 1 as a push pull Configure P2 1 as a n channel open drain PNE1 4 P2 0 N Channel Open Drain Configurable Bit Configure P2 0 as a push pull Configure P2 0 as a n channel open drain PNE1 3 P0 3 N Channel Open Drain Configurable Bit Configure 0 3 as a push pull Configure P0 3 as a n channel open drain PNE1 2 0 2 N Channel Open Drain Configurable Bit Configure 2 as a push pull Configure P0 2 as a n channel open drain PNE1 1 0 1 N Channel Open Drain Configurable Bit Configure PO 1 as a push pull Configure P0 1 as a n channel open drain PNE1 0 P0 0 N Channel Open Drain Configurable Bit Configure P0 0 as a push pull Configure P0 0 as a n channel open drain ELECTRONICS 4 MEMORY MAP S3C72P9 P72P9 Preliminary Spec PNE2 n channel Open Drain Mode Register 2 FD8H Bit 3 2 1 0 RESET Value 0 0 0 0 Read Write W W Bit Addressing 4 4 4 4 PNE2 3 P3 3 N Channel Open Drain Configurable Bit Configure P3 3 as a push pull Configure P3 3 as a n channel open drain PNE2 2 P3 2 N Channel Open Drain Configurable Bit Configure P3 2 as a push pull le Configure P3
43. 0 Output Enable Flag Disable timer counter 0 clock output at the TCLOO Enable timer counter 0 clock output at the TCLOO pin 4 Bits 1 This bit is undefined 0 Bits 0 Always logic zero 4 2 4 40 3 72 9 72 9 Preliminary Spec MEMORY MAP WDFLAG Watch Dog Timer s Counter Clear Flag WT F9AH 3 Bit 3 2 1 0 RESET Value 0 0 0 0 Read Write Bit Addressing 1 4 1 4 1 4 1 4 WDTCF Watch dog Timer s Counter Clear Bit Clear the WDT s counter to zero and restart the WDT s counter WDFLAG 2 0 Bit2 0 Always logic zero ELECTRONICS 4 41 MEMORY MAP 3 72 9 72 9 Preliminary Spec WDMOD Watch Dog Timer Mode Control Register WT F99H F98H Bit 3 2 1 0 3 2 1 0 RESET Value 1 0 1 0 0 1 0 1 Read Write W W Bit Addressing 8 8 8 8 8 8 8 8 WMOD 7 0 Watch Dog Timer Enable Disable Control 4 42 11 Disable watch dog timer function Other Values Enable watch dog timer function ELECTRONICS S3C72P9 P72P9 Preliminary Spec MEMORY MAP WMOD watch Timer Mode Register WT F89H F88H Bit 7 6 5 4 3 2 1 0 Identifier __7 5 a 3 2 a 0 RESET Value 0 0 0 0 note 0 0 0 Read Write R W W W Bit Addressing 8 8 8 8 1 8 8 8 WMOD 7 Enable Disable Buzzer Output Bit WMOD 6 WMOD 5 4 WMOD 3 WMOD 2 WMOD 1 WMOD 0 0 Disable buzzer BUZ signal output at the BUZ pin Enable buzzer BUZ signal output
44. 0 mema b C Sey ot memb L c 1 1 14114 0 memb 7 2 L 3 2 L 1 0 C as a4 as ce He 0 bt a2 at Cmemab 1 1 1 1 t P LLL uL CGmembQL 1 1 1 4 0 1 o 0 Ce memb 7 2 L 3 2 L 1 0 as a4 Cc H DAb 1 1 1 1 0 o CcIH DA3 0 b o bo a2 at Second Byte Bit Addresses 1 0 bt bo a2 at a0 FBOH FBFH 1 bt as FFonFF ELECTRONICS 5 67 SAM47 INSTRUCTION SET S3C72P9 P72P9 Preliminary Spec LDB Load Bit LDB Continued Examples 1 The carry flag is set and the data value at input pin P1 0 is logic zero The following instruction clears the carry flag to logic zero LDB C P1 0 2 The P1 address is FF1H and the L register contains the value 1H 0001B The address memb 7 2 is 111100B and L 3 2 is 008 The resulting address is 11110000 or FFOH and is addressed The bit value L 1 0 is specified as 01B bit 1 LD L 0001B LDB C P1 L P1 L specifies P0 1 and lt 1 3 The H register contains the value 2H and FLAG 20H 3 The address for is 0010B and for FLAG 3 0 the address is 0000B The resulting address is 00100000B or 20H The bit value is 3 Therefore H FLAG 20H 3 FLAG EQU 20H 3 LD H 2H LDB C H FLAG C lt FLAG 20H 3 4 follow
45. 1 sub oscillator stops halting the CPU operation Main oscillator still runs stops Set SCMOD 3 to 0 or RESET Sub Main oscillator runs Oscillation Sub oscillator runs STOP Mode System clock is the main oscillation clock Set SCMOD 2 to 0 or RESET Main oscillator runs stops Sub oscillator runs System clock is the sub oscillation clock NOTES 1 This mode must not be used 2 Oscillation stabilization time by interrupt is 1 256 x BT clocks Oscillation stabilization time by a reset is 31 3ms at 4 19Mhz main oscillation clock ELECTRONICS 6 7 OSCILLATOR CIRCUITS S3C72P9 P72P9 Preliminary Spec SWITCHING THE CPU CLOCK Together bit settings in the power control register PCON and the system clock mode register SCMOD determine whether a main system or a subsystem clock is selected as the CPU clock and also how this frequency is to be divided This makes it possible to switch dynamically between main and subsystem clocks and to modify operating frequencies SCMOD 3 SCMOD 2 SCMOD 0 select the main system clock fx or a subsystem clock and start or stop main system clock oscillation PCON 1 and 0 control the frequency divider circuit and divide the selected fx clock by 4 8 or 64 or fxt clock by 4 NOTE A clock switch operation does not go into effect immediately when you make the SCMOD and PCON register modifications the previously selected clock con
46. 1 Set P6 1 to output mode PM6 0 P6 0 I O Mode Selection Flag Set P6 0 to input mode 1 Set P6 0 to output mode N ELECTRONICS 4 MEMORY MAP S3C72P9 P72P9 Preliminary Spec PMG5 Port Mode Register 5 Group 5 Ports 8 9 y o FEFH FEEH Bit 7 6 5 4 3 2 1 0 Identifier PM9 3 PM9 1 PM9 0 8 3 8 2 8 1 8 0 RESET Value 0 0 0 0 0 0 0 0 Read Write W W W W Bit Addressing 8 8 8 8 8 8 8 8 PM9 3 P9 3 I O Mode Selection Flag Set P9 3 to input mode Set P9 3 to output mode 9 2 P9 2 I O Mode Selection Flag Set P9 2 to input mode 1 Set P9 2 to output mode PM9 1 P9 Mode Selection Flag Set P9 1 to input mode Set P9 1 to output mode 1 9 0 P9 e Mode Selection Flag Set P9 0 to input mode Set P9 0 to output mode 1 PM8 3 P8 3 I O Mode Selection Flag Set P8 3 to input mode Set P8 3 to output mode 8 2 P8 2 I O Mode Selection Flag Set P8 2 to input mode Set P8 2 to output mode 1 PM8 1 P8 Mode Selection Flag Set P8 1 to input mode 1 Set P8 1 to output mode PM8 0 P8 0 I O Mode Selection Flag Set P8 0 to input mode 1 Set P8 0 to output mode 4 30 ELECTRONICS 3 72 9 72 9 Preliminary Spec MEMORY MAP PNE1 n channel Open Drain Mode Register 1 vO FD7H FD6H Bit 7 6 5 4 3 2 1 0 Identifier o PNE1 6 PNE1 5 PNE1 4 PNE1 3 1 2 PNET 1 PNE1 0 RESET Value 0
47. 1 a pull up resistor is assigned to the corresponding I O port for port 3 PUR for port 2 and so on 59 PROGRAMMING Enabling and Disabling I O Port Pull Up Resistors P6 and P7 enable pull up resistors BITS EMB SMB 15 LD LD PUMOD1 EA P7 enable N CHANNEL OPEN DRAIN MODE REGISTER PNE The n channel open drain mode register PNE is used to configure ports 0 2 and 3 to n channel open drain or as push pull outputs When a bit in the PNE register is set to 1 the corresponding output pin is configured to n channel open drain when set to 0 the output pin is configured to push pull The PNE register consists of an 8 bit register and a 4 bit register PNEO can be addressed by 8 bit write instructions only and by 4 bit write instructions only FD6H PNEO 3 PNEO 2 PNEO 1 PNE1 FD7H PNE2 3 PNE2 2 PNE2 1 PNE2 0 FD8H PNE3 3 PNE3 2 1 PNE3 0 PNE2 10 4 ELECTRONICS 3 72 9 72 9 Preliminary Spec PORTS PORT 0 CIRCUIT DIAGRAM VDD Ep in ep eT DHe M P0 1 SO 4 PO 2 SI P0 3 BUZ CMOS Push Pull N Channel Open Drain NOTE When port pin serves as output its pull up resistor is automatically disabled even though the port s pull up resistor is enabled by bit settings in the pull up resistor mode register PUMOD Figure 10 1 Port 0 Circuit Diagra
48. 1 100H 1FFH Bank 1 is used for general purpose Bank 2 200 2 224 nibbles of bank 2 for display registers or general purpose use locations 2xE and 2xF x 0 are for general purpose use in bank 2 Detailed map on bank 2 is shown in Section 12 LCD Controller Driver Bank 3 Bank 3 is used for general purpose Bank 4 400H 4FFH Bank 4 is used for general purpose Bank 15 The microcontroller uses bank 15 for memory mapped peripheral I O Fixed RAM locations for each peripheral hardware address are mapped into this area Data Memory Addressing Modes The enable memory bank EMB flag controls the addressing mode for data memory banks 0 1 2 3 4 or 15 When the EMB flag is logic zero the addressable area is restricted to specific locations depending on whether direct or indirect addressing is used With direct addressing you can access locations 000 07 of bank 0 and bank 15 With indirect addressing only bank 0 000 can be accessed When the flag is set to logic one all four data memory banks can be accessed according to the current SMB value For 8 bit addressing two 4 bit registers are addressed as a register pair Also when using 8 bit instructions to address RAM locations remember to use the even numbered register address as the instruction operand Working Registers The RAM working register area in data memory bank 0 is further divided into
49. 2 Interrupt Generated Generated Status 0 Figure 7 4 Multi Level Interrupt Handling 7 6 S3C72P9 P72P9 Preliminary Spec INTERRUPTS INTERRUPT PRIORITY REGISTER IPR The 4 bit interrupt priority register IPR is used to control multi level interrupt handling Its reset value is logic zero Before the IPR can be modified by 4 bit write instructions all interrupts must first be disabled by a DI instruction By manipulating the IPR settings you can choose to process all interrupt requests with the same priority level or you can select one type of interrupt for high priority processing A low priority interrupt can itself be interrupted by a high priority interrupt but not by another low priority interrupt A high priority interrupt cannot be interrupted by any other interrupt source Table 7 3 Standard Interrupt Priorities interrupt Default Pony wm 5 wm s The MSB of the IPR the interrupt master enable flag IME enables and disables all interrupt processing Even if an interrupt request flag and its corresponding enable flag are set a service routine cannot be executed until the IME flag is set to logic one The IME flag can be directly manipulated by El and DI instructions regardless of the current enable memory bank EMB value Table 7 4 Interrupt Priority Register Settings imo o ie
50. 2 as a n channel open drain PNE2 1 P3 1 N Channel Open Drain Configurable Bit Configure P3 1 as a push pull Configure P3 1 as n channel open drain PNE2 0 P3 0 N Channel Open Drain Configurable Bit Configure P3 0 as a push pull Configure P3 0 as a n channel open drain 4 Ir 4 32 3 72 9 72 9 Preliminary Spec MEMORY MAP PSW Program Status Word CPU FB1H FBOH Bit 7 6 5 4 3 2 1 0 RESET Value 1 0 0 0 0 0 0 0 Read Write R W R R R R W R W R W R W Bit Addressing 2 8 8 8 1 4 8 1 4 8 1 4 8 1 4 8 C Carry Flag EN No overflow or borrow condition exists An overflow or borrow condition does exist SC2 SCO Skip Condition Flags No skip condition exists no direct manipulation of these bits is allowed A skip condition exists no direct manipulation of these bits is allowed 151 ISO Interrupt Status Flags Service only the high priority interrupt s as determined in the interrupt priority register IPR Do not service any more interrupt requests 1 Undefined EMB Enable Data Memory Bank Flag Restrict program access to data memory to bank 15 F80H FFFH and to the locations 000H 07FH in the bank 0 only Enable full access to data memory banks 0 1 2 3 4 and 15 ERB Enable Register Bank Flag Select register bank 0 as working register area the select register bank SRB instruction operand Select register banks 0 1 2 or 3 as working register area in accordance with
51. 5 5 3 Skip Conditions for ADC SBC 5 6 5 4 Data Type Symbols dione nep abre 5 7 5 5 Register Identifiers aici ated acd ud tes 5 7 5 6 Instruction Operand 5 7 5 7 Opcode Definitions Direct cccecceeeeceeeeeceeeeeeceeeeeeeceeeeeceeeeeaeeecaeeeeeeeseeesseaeeeees 5 8 5 8 Opcode Definitions 5 8 5 9 CPU Control Instructions High Level Summary 2 5 10 5 10 Program Control Instructions High Level 5 10 5 11 Data Transfer Instructions High Level 5 11 5 12 Logic Instructions High Level 5 12 5 13 Arithmetic Instructions High Level 5 12 5 14 Bit Manipulation Instructions High Level 5 13 5 15 CPU Control Instructions Binary Code 5 15 5 16 Program Control Instructions Binary Code 5 16 5 17 Data Transfer Instructions Binary Code 5 18 5 18 Logic Instructions Binary Code Summary see 5 20 5 19 Arithmetic Instructions Binary Code
52. 7 2 L 3 2 L 1 0 0 fas H DAb 1 1 1 1 0 0 DA3 0 b 0 as 22 a0 Second Byte Bit Addresses E 22 FFOHFFFH Examples 1 If RAM bit location 30H 2 is set to 0 the following instruction sequence will cause the program to continue execution from the instruction identifed as LABEL2 BTSF 30H 2 If 30H 2 0 then skip RET If 30H 2 1 return JP LABEL2 2 You can use BTSF in the same way to test a port pin address bit BTSF P1 0 If P1 0 0 then skip RET If P1 0 1 then return JP LABEL3 ELECTRONICS 5 39 SAM47 INSTRUCTION SET BTSF Test and Skip on False BTSF Examples 5 40 Continued S3C72P9 P72P9 Preliminary Spec 3 2 P0 3 and P1 0 P1 3 are tested BP2 LD L 2H BTSF PO L RET INCS L CPSE L 8H JR BP2 First P1 02H 2 111100B 00B 10B 2 4 Bank 0 location 0 is tested and regardless of the current EMB value BTSF has the following effect FLAG EQU 0 0 LD H 0AH BTSF H FLAG RET If bank 0 0 0 then skip ELECTRONICS S3C72P9 P72P9 Preliminary Spec SAM47 INSTRUCTION SET BTST Bit Test and Skip on True BTST dst b C Operation c Test carry bit and skip if set 1 DA b Test specifie
53. 72 9 72 9 Preliminary Spec ADDRESS SPACES WORKING REGISTERS Working registers mapped to RAM address 000H 01FH in data memory bank 0 are used to temporarily store intermediate results during program execution as well as pointer values used for indirect addressing Unused registers may be used as general purpose memory Working register data can be manipulated as 1 bit units 4 bit units or using paired registers as 8 bit units Working Register Register Register Register Figure 2 4 Working Register Map ELECTRONICS 2 11 ADDRESS SPACES S3C72P9 P72P9 Preliminary Spec Working Register Banks For addressing purposes the working register area is divided into four register banks bank 0 bank 1 bank 2 and bank 3 Any one of these banks can be selected as the working register bank by the register bank selection instruction SRBn and by setting the status of the register bank enable flag ERB Generally working register bank 0 is used for the main program and banks 1 2 and 3 for interrupt service routines Following this convention helps to prevent possible data corruption during program execution due to contention in register bank addressing Table 2 3 Working Register Organization and Addressing SRB Settings Selected Register Bank NOTE x means don t care Paired Working Registers Each of the register banks is subdivided into eight 4 bit registers These registers named Y Z W X L E a
54. 9 3 Serial data output 12 1 1 Serial data input 13 P0 2 K2 B UZ 2 kHz 4 kHz 8 kHz 16 kHz frequency output for 14 P0 3 K3 buzzer signal INTO INT1 External interrupts The triggering edge for INTO and 23 24 P1 0 P1 1 INT1 is selectable ELECTRONICS 1 5 O PRODUCT OVERVIEW S3C72P9 P72P9 Preliminary Spec Table 1 1 53C72P9 P72P9 Pin Descriptions Continued Quasi interrupt with detection of rising or falling edges External interrupt with detection of rising or falling edges Clock output INT2 INT4 CLO LCDCK LCD clock output for display expansion i LCDSY LCD synchronization clock output for display expansion TCLOO Timer counter 0 clock output TCLO1 Timer counter 1 clock output i i O LCD common signal output SEGO SEG39 K0 K3 External interrupt The triggering edge is 11 14 0 3 selectable K4 K7 6 0 6 3 vo _ La __ RESET __ pee 46 49 5 0 5 3 LCD segment signal output 9 3 9 0 EN Tuo __ int or o mE 57 54 7 3 7 0 Main power supply XN Crystal Ceramic or RC oscillator pins for system clock XTN Crystal oscillator pins for subsystem clock 20 21 TEST Test signal input must be connected
55. 90H A F90H lt A bank 15 is selected LD 34H A 034H lt A bank 0 is selected SMB 15 Non essential instruction since EMB 0 LD 20H A 020H lt A bank 0 is selected LD 90H A F90H lt A bank 15 is selected 2 When EMB 1 SMB 1 Select memory bank 1 LD A 9H LD 90H A 190H lt A bank 1 is selected LD 34H A 134 lt A bank 1 is selected SMB 0 Select memory bank 0 LD 90H A 090 A bank 0 is selected LD 34H A 034H lt A bank 0 is selected SMB 15 Select memory bank 15 LD 20H A Program error but assembler does not detect it LD 90H A F90H lt A bank 15 is selected ELECTRONICS 2 21 ADDRESS SPACES S3C72P9 P72P9 Preliminary Spec ERB FLAG ERB The 1 bit register bank enable flag ERB determines the range of addressable working register area When the ERB flag is 1 the working register area from register banks 0 to 3 is selected according to the register bank selection register SRB When the ERB flag is 0 register bank 0 is the selected working register area regardless of the current value of the register bank selection register SRB When an internal RESET is generated bit 6 of program memory address 0000H is written to the ERB flag This automatically initializes the flag When a vectored interrupt is generated bit 6 of the respective address table in program memory is written to the ERB flag setting the correct flag status before the interrupt servi
56. A0 NOTE 0 means Low level 1 means High level um ELECTRONICS 16 3 S3P72P9 OTP 3 72 9 72 9 Preliminary Spec Table 16 4 D C Electrical Characteristics Supply 5 V 10 6 0 MHz Current Crystal oscillator 4 19 MHz C1 C2 22 pF Idle mode 6 0 MHz Vpp 5 V 10 4 19 MHz Crystal oscillator C1 C2 22 pF 3 V 10 6 0 MHz 4 19 MHz 3 V 10 32 kHz crystal oscillator Idle mode 3 V 10 32 kHz crystal oscillator Vpp 5 V 10 Vpp 3 V 10 Stop mode SCMOD Vpp 5 V 10 0100B 24 mode 3 V 10 NOTES 1 Data includes power consumption for subsystem clock oscillation 2 When the system clock control register SCMOD is set to 1001B main system clock oscillation stops and the subsystem clock is used 3 Currents in the following circuits are not included on chip pull up resistors internal LCD voltage dividing resistors output port drive currents 16 4 ELECTRONICS 3 72 9 72 9 Preliminary Spec S3P72P9 OTP Main Oscillator Frequency CPU Clock 1 5 MHz 1 05 MHz 750 kHz 15 6 kHz Supply Voltage V CPU clock 1 n x oscillator frequency n 4 8 or 64 Figure 16 2 Standard Operating Voltage Range ELECTRONICS 16 5 S3P72P9 OTP 3 72 9 72 9 Preliminary Spec NOTES 16 6 ELECTRONICS S3C72P9 P72P9 Preliminary Spec DEVELOPMENT TOOLS DEVELOPMENT TOOLS OVERVIEW Samsung provides
57. ADC Add with Caltry 5 26 ADS Add and Skip on 5 28 AND Eogical eR E E etd 5 30 BAND BitiEogical ee deo ere a e ea eet 5 31 BITR Bit Ren RN RE 5 33 BITS zB 5 35 BOR Bit Logical e etu t RR e ite reed 5 37 BTSF Bit Test and Skip On False 5 39 BTST Bit Test and Skip on Tru irent fed 5 41 BTSTZ Bit Test and Skip on True Clear 5 43 BXOR Bit EXcluSiVe Linie acie 5 45 CALL Call Procedure ed acevo 5 47 CALLS Gall Procedure Short ete ite tee cesta 5 48 CCF Complement Carry 5 49 COM Complement 5 50 CPSE Compare and Skip if 2 1 5 51 DECS Decrement and Skip on 5 52 DI Disable Interr pts ie dede n edens 5 53 Enable Interrupts 5 54 IDLE 5 55 INCS Increment and Skip 5 56 IRET Return From Interrupt ce 5 57 JP eee 5 58 JPS a intes
58. Binary Code Summary table Programming example s to show how the instruction is used ELECTRONICS 5 25 SAM47 INSTRUCTION SET S3C72P9 P72P9 Preliminary Spec ADC Add with Carry ADC dst src Add indirect data memory to A with carry EA RR Add register pair RR to EA with carry RRb EA Add EA to register pair RRb with carry Description source operand along with the setting of the carry flag is added to the destination operand and the sum is stored in the destination The contents of the source are unaffected If there is an overflow from the most significant bit of the result the carry flag is set otherwise the carry flag is cleared If ADC is followed by an ADS A im instruction in a program ADC skips the ADS instruction if an overflow occurs If there is no overflow the ADS instruction is executed normally This condition is valid only for ADC A HL instructions If an overflow occurs following ADS A im instruction the next instruction will not be skipped GppipIeseeess o EX e s 0 Examples 1 The extended accumulator contains the value 0C3H register pair HL the value OAAH and the carry flag is set to 1 SCF lt EA HL 0C3H 1H 6EH 1 JPS XXX Jump to XXX no skip after ADC 2 Ifthe extended accumulator contains the value 0C3H regi
59. Counter 1 Component TCI Enable Disable Procedure ae leget De edes cre Den ae Pie e EO e Bede TC1 Programmable Timer Counter Function esses eene nennen TC1 Timer Counter Operation Sequence eese nne TOI Event Counter 2 n ped enitn nae e Ro eee e Nae cgo ee Rusa ta TG1 Glock Frequency OUtpUt 2 nr itor cde ter irt iecit decir te Eten TG1 External Inp t Signal Divider iu cobi e teas Mode Register e e TOT Register TON T T octo pet Porte exe E tal ad TC1 Reference Register TREF1 cc cccesccceseeeeeeeeeeeeeeeeeeeeeeeaeceaeeesaeeseaeeeeeaeeseeeessaeessaeeeseeeeeaeess Output Enable Flag eee ier ente TOT Output Eatch T OLET ihe cree oid eee eee re e ne et eios Watch m OVOtVIQW nie ese E poete e etia Peres dieat ese Watch Timer Mode Register WMOD enne nnne nnne nnne nennen Chapter 12 LCD Controller Driver i i UM LGD RAM Address nia
60. Disconnect port 1 pull up resistor Connect port 1 pull up resistor 1 PURO Connect Disconnect Port 0 Pull up Resistor Control Bit Disconnect port 0 pull up resistor Connect port 0 pull up resistor fel 4 34 ELECTRONICS 3 72 9 72 9 Preliminary Spec MEMORY MAP PUMOD2 Pull up Resistor Mode Register 2 y o FDEH Bit 3 2 1 0 RESET Value 0 0 0 0 Read Write W W Bit Addressing 4 4 4 4 3 2 Bits 3 2 EN Always cleared to logic zero PUR9 Connect Disconnect Port 9 Pull up Resistor Control Bit Disconnect port 9 pull up resistor 1 Connect port 9 pull up resistor PUR8 Connect Disconnect Port 8 Pull up Resistor Control Bit Disconnect port 8 pull up resistor Connect port 8 pull up resistor 1 ELECTRONICS 4 MEMORY MAP S3C72P9 P72P9 Preliminary Spec SCMOD System Clock Mode Control Register CPU FB7H Bit 3 2 1 0 RESET Value 0 0 0 0 Read Write W W W W Bit Addressing 1 1 1 1 SCMOD 3 Bit 3 SCMOD 2 Bit 2 SCMOD 1 Bit 1 Always logic zero SCMOD 0 Bit 0 NOTES 1 Sub oscillation goes into stop mode only by SCMOD 2 PCON which revokes stop mode cannot stop the sub oscillation 2 You use SCMOD 2 as follows ex after data bank was used few minutes have passed Main operation gt sub operation sub idle LCD on after a few minutes later without any external input gt sub operation gt main operation gt SCMOD 2 1 gt main stop mode LCD off 3 SCMOD bits 3 0
61. EA LD EA 00H CALL DISPLAY JPS MAIN ORG 0500H DB 66H DB 77H DB 88H DB 99H DISPLAY LDC EA EA lt address 0500H 66H RET If the instruction EA 01H is executed in place of LD EA 00H The content of 0501H 77H is loaded to the EA register If LD EA 02H is executed the content of address 0502H 88H is loaded to EA ELECTRONICS 5 69 SAM47 INSTRUCTION SET S3C72P9 P72P9 Preliminary Spec LDC Load Code Byte LDC Continued Examples 2 The following instructions will load one of four values defined by the define byte DB directive to the extended accumulator ORG 0500H DB 66H DB 77H DB 88H DB 99H DISPLAY LD WX 00H LDC EA WX EA lt address 0500H 66H RET If the instruction LD WX 01H is executed in place of LD WX 00H then EA lt address 0501H 77H If the instruction LD WX 02H is executed in place of LD WX 00H then EA lt address 0502H 88H 3 Normally the LDC EA EA and the LDC EA WxX instructions reference the table data on the page on which the instruction is located If however the instruction is located at address xxFFH it will reference table data on the next page In this example the upper 4 bits of the address at location 0200H is loaded into register E and the lower 4 bits into register A ORG 01FDH 01FDH LD WX 00H 01FFH LDC EA WX E lt upper 4 bits of 0200H address A amp lower 4 bits of 0200H address 4 Here is another example of
62. FLAG If bank 0 AH 0 1 then skip RET ELECTRONICS S3C72P9 P72P9 Preliminary Spec SAM47 INSTRUCTION SET BTSTZ Bit Test and Skip on True Clear Bit BTSTZ dst b Test specified bit skip and clear if memory bit is set Description specified bit within the destination operand is tested If it is a 1 the instruction immediately following the BTSTZ instruction is skipped otherwise the instruction following the BTSTZ is executed The destination bit value is cleared snes cet on oc a memb L ee gem Skip if memb 7 2 L 3 2 L 1 0 1 and clear H DAb 1 4 4141 4 4 0 1 3 0 1 and clear bt a2 at 20 Second Byte Bit Addresses me 1 FFonFF Examples 1 Port pin 0 0 is toggled by checking the 0 0 value level BTSTZ 0 0 lf P0 0 1 then PO 0 lt and skip BITS P0 0 If P0 0 0 then 0 0 lt 1 JP LABEL3 2 For toggling P2 2 P2 3 and P3 0 P3 3 LD L 0AH BP2 BTSTZ P2 L First 2 P2 2 111100B 10B 10B 2 2 BITS P2 L INCS L JR BP2 ELECTRONICS 5 43 SAM47 INSTRUCTION SET S3C72P9 P72P9 Preliminary Spec BTSTZ Bit Test and Skip on True Clear Bit BTSTZ Continued Examples 3 Bank 0 location 0 is tested and 0 FLAG EQU 0
63. INSTRUCTION SET S3C72P9 P72P9 Preliminary Spec BINARY CODE SUMMARY This section contains binary code values and operation notation for each instruction in the SAM47 instruction set in an easy to read tabular format It is intended to be used as a quick reference source for programmers who are experienced with the SAM47 instruction set The same binary values and notation are also included in the detailed descriptions of individual instructions later in Section 5 If you are reading this user s manual for the first time please just scan this very detailed information briefly Most of the general information you will need to write application programs can be found in the high level summary tables in the previous section The following information is provided for each instruction Instruction name Operand s Binary values Operation notation The tables in this section are arranged according to the following instruction categories CPU control instructions Program control instructions Data transfer instructions Logic instructions Arithmetic instructions Bit manipulation instructions 5 14 ELECTRONICS S3C72P9 P72P9 Preliminary Spec SAM47 INSTRUCTION SET Table 5 15 CPU Control Instructions Binary Code Summary operara Binary Code Operation SCF RCF CCF Po fo fo ear IT o fefee 1 SRBenmn 0 1 2 3 PC13 0 lt memc 5 0
64. NOTES 1 The value of the carry flag after aRESET occurs during normal operation is undefined If aRESET occurs during power down mode IDLE or STOP the current value of the carry flag is retained 2 carry flag can only be addressed by a specific set of 1 bit manipulation instructions See Section 2 for detailed information ELECTRONICS 4 33 MEMORY MAP S3C72P9 P72P9 Preliminary Spec PUMOD1 pull up Resistor Mode Register 1 O FDDH FDCH Bit 7 6 5 4 3 2 1 0 RESET Value 0 0 0 0 0 0 0 0 Read Write Bit Addressing z Ww W W W 8 8 8 8 8 8 8 PUR7 Connect Disconnect Port 7 Pull up Resistor Control Bit Disconnect port 7 pull up resistor 1 Connect port 7 pull up resistor PUR6 Connect Disconnect Port 6 Pull up Resistor Control Bit Disconnect port 6 pull up resistor Connect port 6 pull up resistor 5 Connect Disconnect Port 5 Pull up Resistor Control Disconnect port 5 pull up resistor 1 Connect port 5 pull up resistor PUR4 Connect Disconnect Port 4 Pull up Resistor Control Bit Disconnect port 4 pull up resistor 1 Connect port 4 pull up resistor PUR3 Connect Disconnect Port 3 Pull up Resistor Control Bit Disconnect port 3 pull up resistor 1 Connect port pull up resistor PUR2 Connect Disconnect Port 2 Pull up Resistor Control Bit Disconnect port 2 pull up resistor 1 Connect port 2 pull up resistor PUR1 Connect Disconnect Port 1 Pull up Resistor Control Bit
65. O MDS O O o 160 S3E72P0 EVA Chip 50 Pin Connector 50 Pin Connector External Triggers che SM1255A Figure 17 2 TB72P9 Target Board Configuration ELECTRONICS 17 3 DEVELOPMENT TOOLS S3C72P9 P72P9 Preliminary Spec Table 17 1 Power Selection Settings for TB72P9 To User Vcc Settings To User Vcc Operating Mode TB72P9 Vcc gt Vss gt To User Vcc External TB72P9 Vcc Vss gt Comments The SMDS2 SMDS2 supplies Vcc to the target board evaluation chip and the target system The SMDS2 SMDS2 supplies Vcc only to the target board evaluation chip The target system must have its own power supply Table 17 2 Main Clock Selection Settings for TB72P9 Main Clock Setting Operating Mode EVA Chip S3E72P0 XOUT XIN lt No Connection 100 Pin Connector SMDS2 SMDS2 EVA Chip S3E72P0 4 XOUT XIN XTAL Target Board 17 4 Comments Set the Xy switch to MDS when the target board is connected to the SMDS2 SMDS2 Set the Xy switch to XTAL when the target board is used as a standalone unit and is not connected to the SMDS2 SMDS2 ELECTRONICS S3C72P9 P72P9 Preliminary Spec DEVELOPMENT TOOLS Table 17 3 Sub Clock Selection Settings for TB72P9 Sub Clock Setting Operating Mode Set the XTI switch to MDS xe when the target board is c
66. Organization eene 11 29 11 11 TMOD 1 6 TMOD1 5 and TMOD1 4 Bit Settings 11 30 11 12 Watch Timer Mode Register WMOD 11 37 xvi 3 72 9 72 9 MICROCONTROLLER List of Tables concluded Table Title Page Number Number 12 1 Common and Segment Pins per Duty 12 3 12 2 LCD Control Register LCON 12 4 12 3 LMOD 10 Bits t tee 12 4 12 4 LCD Clock Signal LCDCK Frame Frequency see 12 5 12 5 LCD Mode Register LMOD Organization 2 12 6 12 6 LCD Clock Signal LCDCK Frame Frequency ee 12 7 13 1 SIO Mode Register SMOD Organization eene 13 3 14 1 Absolute Maximum 2 14 2 14 2 Electrical Char cteristies 1 cogeret nex 14 2 14 3 Main System Clock Oscillator 14 5 14 4 Recommended Oscillator 14 6 14 5 LCD Contrast Controller 14 6 14 6 Subsystem Clock Oscillator 14 7 14 7 Input Output Gapaecitarice 2 irte rre ihe 14 7 14 8 Electrical Characteristics eescceseceeneeeeeceseeesneeeseeeseeeseeseneeeseeesneeeneeeses
67. P3 1 lt output mode BITR P3 1 1 clear BITS TOE1 11 28 ELECTRONICS S3C72P9 P72P9 Preliminary Spec TIMERS and TIMER COUNTERS TC1 MODE REGISTER TMOD1 TMOD1 is the 8 bit mode register for timer counter 1 It is addressable by 8 bit write instructions The TMOD1 3 bit is also 1 bit write addressable RESET clears all TMOD1 bits to logic zero Following a RESET timer counter 1 is disabled TMOD1 2 is the enable disable bit for timer counter 1 When TMOD1 3 is set to 1 the contents of TCNT1 IRQT1 and TOL 1 are cleared counting starts from 0000H and TMOD1 3 is automatically reset to 0 for normal TC1 operation When TC1 operation stops TMOD1 2 0 the contents of the TC1 counter register TCNT1 are retained until TC1 is re enabled The TMOD1 6 TMOD1 5 and TMOD1 4 bit settings are used together to select the TC1 clock source This selection involves two variables Synchronization of timer counter operations with either the rising edge or the falling edge of the clock signal input at the TCL1 pin and Selection of one of four frequencies based on division of the incoming system clock frequency for use in internal TC1 operations Table 11 10 TC1 Mode Register TMOD1 Organization Resulting TC1 Function Always logic zero FA1H TMOD 1 7 TMOD1 6 TMOD1 5 TMOD1 4 Specify input clock edge and internal frequency Disable timer counter 1 retain TCNT1 contents Enable timer counter 1 Always log
68. PM FIags ee IR che Ee ible eb aia 10 3 Pull Up Resistor Mode Register PUMOD 10 4 N Channel Open Drain Mode Register 10 4 Port o Circuit Diagrams cocci eua ep etu 10 5 Port 1 Circuit Diagrami in ec n eI aet e HO ot d e id aed vere 10 6 Port 2 Circuit 10 7 Ports Circuit Diagram exces sii e dr c e e Diss 10 8 Port4 5 6 7 8 9 Clrc it EP ee arde see oed mo gre E ene 10 9 Chapter 11 Timers and Timer Counters X 11 1 Basie Timer BT desta 11 2 i e 11 2 Basic Timer Mode Register BMOD c cccescceeeeeeeeeseeeeeeeeeeaeeecaeeeeaeeeesaeeseaaesesaeeeseaeetsneeeeseeeeees 11 5 Basic Timer Counter BONT 11 6 Basic Timer Operation 11 6 Watchdog Timer Mode Register 11 8 Watchdog Timer Counter WDCNT 22 cccecccceeseeeeeeeeeeseeeeeeeeeeseeecaaeeesaeeeseneeesaaeeesaeeeseaeeeseeeessaeeenenees 11 8 Watchdog Timer Counter Clear Flag 11 8 8 Bit Timer Gounter 0 1 CO evista den teagan Urt
69. Preliminary Spec TMOD1 rimer Counter 1 Mode Register Bit Identifier RESET Value Read Write Bit Addressing TMOD1 7 TMOD1 6 4 TMOD1 3 TMOD1 2 TMOD1 1 TMOD1 0 ELECTRONICS MEMORY MAP T C FA1H FAOH 3 2 1 0 3 2 1 0 _ 6 5 4 3 2 0 0 0 0 0 0 0 0 W W 8 8 8 8 1 8 8 8 8 Bit 7 EN Always logic zero Timer Counter 1 Input Clock Selection Bit External clock input at TCL1 on rising edge 1 External clock input at TCL1 pin falling edge 210 4 09 kHz 7 is selected system clock of 4 19 MHz Clear Counter and Resume Counting Control Bit 1 Clear TCNT1 IRQT1 and resume counting immediately This bit is cleared automatically when counting starts Enable Disable Timer Counter 1 Bit Disable timer counter 1 retain TCNT1 contents 1 Enable timer counter 1 Bit 1 Always logic zero Bit 0 Always logic zero gt MEMORY MAP S3C72P9 P72P9 Preliminary Spec TOE rimer Output Enable Flag Register T C F92H Bit 3 2 1 0 Identifier 1 Toco RESET Value 0 0 U 0 Read Write R W R W R W R W Bit Addressing 1 4 1 4 1 4 1 4 TOE1 Timer Counter 1 Output Enable Flag Disable timer counter 1 clock output at the TCLO1 pin Enable timer counter 1 clock output at the TCLO1 pin TOEO Timer Counter
70. RESET Value 0 0 0 0 Read Write W Bit Addressing 4 4 4 4 IMOD1 3 1 Bits 3 1 Always logic zero IMOD1 0 External Interrupt 1 Edge Detection Control Bit Rising edge detection Falling edge detection 4 18 ELECTRONICS 3 72 9 72 9 Preliminary Spec MEMORY MAP IMOD2 External Interrupt 2 INT2 Mode Register CPU FDAH Bit 3 2 1 0 RESET Value 0 0 0 0 Read Write W W Bit Addressing 4 4 4 4 IMOD2 3 1 Bits 3 1 EN Always logic zero IMOD2 0 External Interrupt 2 Edge Detection Selection Bit ELECTRONICS Interrupt request at INT2 pin trigged by rising edge Interrupt request at INT2 pin trigged by falling edge MEMORY MAP S3C72P9 P72P9 Preliminary Spec IMODK external Key Interrupt Mode Register CPU FB6H Bit 3 2 1 0 RESET Value 0 0 0 0 Read Write W W W Bit Addressing 4 4 4 4 IMODK 3 Bit 3 EO Always logic zero IMODK 2 External Key Interrupt Edge Detection Selection Bit Falling edge detection Rising edge detection IMODK 1 0 External Key Interrupt Mode Control Bits EN Disable key interrupt Enable edge detection at K0 K3 pins Enable edge detection at K0 K7 pins NOTES 1 To generate a key interrupt all of the selected pins must be configured to input mode If any one of the selected pins is configured to output mode only falling edge can be detected 2 Togenerate a key interrupt all of the selected pins must be at input high state for falling edge dete
71. SP SP 6 v D s ren s rene gt gt D gt gt CD 0 CD v gt gt Co D v gt gt 7 4 7 Upper Register n 2 4 2 05 gt o Figure 2 7 Push Type Stack Operations 2 16 ELECTRONICS 3 72 9 72 9 Preliminary Spec ADDRESS SPACES POP OPERATIONS For each push operation there is a corresponding pop operation to write data from the stack back to the source register or registers for the PUSH instruction it is the POP instruction for CALL the instruction RET or SRET for interrupts the instruction IRET When a pop operation occurs the SP is incremented by a number determined by the type of operation and points to the next free stack location POP Instructions A POP instruction references the SP to write data stored in two 4 bit stack locations back to the register pairs and SB register The value of the lower 4 bit register is popped first followed by the value of the upper 4 bit register After the POP has executed the SP is incremented by two and points to the next free stack location RET and SRET Instructions The end of a subroutine call is signaled by the return instruction RET or SRET The RET or SRET uses the SP to reference the six 4 bit stack locations used for the CALL and to write this data back to the PC the EMB and the ERB After the RET or SRET has executed the SP is inc
72. Summary een 5 21 5 20 Bit Manipulation Instructions Binary Code Summary 5 22 S3C72P9 P72P9 MICROCONTROLLER List of Tables continued Table Title Page Number Number 6 1 Power Control Register PCON Organization 2 2 6 4 6 2 Instruction Cycle Times for CPU Clock 6 5 6 3 System Clock Mode Register SCMOD 6 6 6 4 Main Sub Oscillation Stop 6 7 6 5 Elapsed Machine Cycles During CPU Clock Switch 6 8 6 6 Clock Output Mode Register Organization 6 10 7 1 Interrupt Types and Corresponding Port Pin 7 1 7 2 151 and ISO Bit Manipulation for Multi Level Interrupt Handling 7 6 7 8 Standard Interrupt nennen 7 7 7 4 Interrupt Priority Register 05 7 7 7 5 IMODO 1 and 2 Register Organization 7 8 7 6 IMODK Register Bit Settings nennen 7 10 7 7 Interrupt Enable and Interrupt Request Flag 7 13 7 8 Interrupt Request Flag Conditions and
73. When Initiated by Interrupt Request ELECTRONICS 14 11 ELECTRICAL DATA 557 22532 22532 Preliminary Spec 0 8 VDD oy 0 8 VDD Measurement Points 0 2 Vpp amp 02 Vpp Figure 14 4 A C Timing Measurement Points Except for Xi and VDD 0 1 V 0 1V Figure 14 5 Clock Timing Measurement at Xi Vpp 0 1 V 0 1V Figure 14 6 Clock Timing Measurement at 14 12 ELECTRONICS 557 22532 22532 Preliminary Spec ELECTRICAL DATA Figure 14 7 TCL Timing Figure 14 8 Input Timing for RESET Signal INTO 1 2 4 KO to K7 Figure 14 9 Input Timing for External Interrupts and Quasi Interrupts ELECTRONICS 14 13 ELECTRICAL DATA 557 22532 22532 Preliminary Spec Input Data Output Data Figure 14 10 Serial Data Transfer Timing 14 14 ELECTRONICS S3C72P9 P72P9 Preliminary Spec MECHANICAL DATA OVERVIEW This section contains the following information about the device package Package dimensions in millimeters Pad diagram Pad pin coordinate data table ELECTRONICS MECHANICAL DATA MECHANICAL DATA S3C72P9 P72P9 Preliminary Spec 23 90 0 30 100 QFP 1420C 17 90 0 30 14 00 0 20 M 2 0 05 lt 2 65 0 10 0 80 0 20 ossoa NOTE Dimensions are in millimeters Figure 15 1 100 QFP 1420C Package Dimensions 15 2 ELECTRONICS 3 72 9 72 9 Preliminary Spec S3P72P9 OTP
74. address by replacing the contents of the program counter with the address specified in the destination operand The destination can be anywhere in the 16 K byte program memory address space Opwani inary Code Operation Notation BEBE POIS ADRIS o o sss ar ano s as Fer as e so 2 o Example The label SYSCON is assigned to the instruction at program location 07FFH The instruction JP SYSCON at location 0123H will load the program counter with the value 07FFH 5 58 ELECTRONICS S3C72P9 P72P9 Preliminary Spec SAM47 INSTRUCTION SET JPS Jump Short JPS Operation Description Example dst Operand Operation Summary Bytes Cycles Aon Jump deat in page 12 vits JPS causes an unconditional branch to the indicated address with the 4 byte program memory address space Bits 0 11 of the program counter are replaced with the directly specified address The destination address for this jump is specified to the assembler by a label or by an actual address in program memory Binary Operation tation 14 0 14 12 11 0 Far as as e The label SUB is assigned to the instruction at program memory location OOFFH The instruction JPS SUB at location OEABH will load the program counter with the value OOFFH Normally the JPS instruction jumps to the address in the block in which the instructio
75. address stack registers in bank 0 addresses 000H OFFH regardless of the current value of the enable memory bank EMB flag and the select memory bank SMB flag Although general purpose register areas can be used for stack operations be careful to avoid data loss due to simultaneous use of the same register s Since the reset value of the stack pointer is not defined in firmware we recommend that you initialize the stack pointer by program code to location 00H This sets the first register of the stack area to OFFH NOTE A subroutine call occupies six nibbles in the stack an interrupt requires six When subroutine nesting or interrupt routines are used continuously the stack area should be set in accordance with the maximum number of subroutine levels To do this estimate the number of nibbles that will be used for the subroutines or interrupts and set the stack area correspondingly PROGRAMMING TIP Initializing the Stack Pointer To initialize the stack pointer SP 1 When EMB 1 SMB 15 Select memory bank 15 LD EA 00H Bit 0 of SP is always cleared to 0 LD SP EA Stack area initial address lt SP 1 2 When EMB 0 LD EA 00H LD SP EA Memory addressing area 00H 7FH F80H FFFH ELECTRONICS 2 15 ADDRESS SPACES S3C72P9 P72P9 Preliminary Spec PUSH OPERATIONS Three kinds of push operations reference the stack pointer SP to write data from the source register to the stack PUSH inst
76. automatically However when TC1 is disabled TMOD1 2 0 the contents of the TOL1 latch are retained and can be read if necessary 11 32 ELECTRONICS S3C72P9 P72P9 Preliminary Spec PROGRAMMING Setting a TC1 Timer Interval To set a 30 ms timer interval for TC1 given fxx 4 19 MHz follow these steps 1 Select the timer counter 1 mode register with a maximum setup time of 16 seconds assume the TC1 counter clock 210 and is set to FFFFH 2 Calculate the TREF1 value 30 ms TREF1 1 TREF1 value 4 09 kHz 30 ms 244 us TREF1 value 1 122 9 7AH 79H 3 Load the value 79H to the TREF1 register BITS SMB LD LD LD LD LD LD ELECTRONICS EMB 15 EA 79H TREF1A EA EA 00H TREF1B EA EA 4CH TMOD1 EA TIMERS and TIMER COUNTERS 11 33 TIMERS and TIMER COUNTERS S3C72P9 P72P9 Preliminary Spec WATCH TIMER OVERVIEW The watch timer is a multi purpose timer which consists of three basic components 8 bit watch timer mode register WMOD Clock selector Frequency divider circuit Watch timer functions include real time and watch time measurement and interval timing for the main and sub system clock It is also used as a clock source for the LCD controller and for generating buzzer BUZ output Real Time and Watch Time Measurement To start watch timer operation set bit 2 of the watch timer mode register WMOD 2 to logic one
77. be released by an interrupt request signal when the interrupt enable flag has been set In such cases the interrupt routine will not be executed since IME 0 7 2 ELECTRONICS S3C72P9 P72P9 Preliminary Spec INTERRUPTS Interrupt is generated INT xx Request flag IRQx lt 1 Retain value until IEx 1 Generate corresponding vector interrupt and release power down mode Retain value until IME 1 Retain value until interrupt service routine is completed ee IS1 0 1 0 Store contents of PC and PSW in the stack area set PC contents to corresponding vector address Are both interrupt sources of shared vector address used IRQx flag value remains 1 Reset corresponding IRQx flag Jump to interrupt start address Jump to interrupt start address Verify interrupt source and clear IRQx with a BTSTZ instruction Figure 7 1 Interrupt Execution Flowchart ELECTRONICS 7 3 INTERRUPTS S3C72P9 P72P9 Preliminary Spec mon Power Down Mode Release Signal 151 150 Interrupt Control Unit Vector Interrupt Edge Detection Circuit Generator Figure 7 2 Interrupt Control Circuit Diagram 7 4 ELECTRONICS S3C72P9 P72P9 Preliminary Spec INTERRUPTS Multiple Interrupts The interrupt controller can service multiple interrupts in two ways as two level interrupts where either all interrupt requests or only those of highest priority are serviced or as multi level interrupts when the int
78. by hardware to logic zero gt Basic timer resumes counting clock pulses 11 6 ELECTRONICS S3C72P9 P72P9 Preliminary Spec TIMERS and TIMER COUNTERS 59 PROGRAMMING Using the Basic Timer 1 To read the basic timer count register BITS EMB SMB 15 BCNTR LD LD YZ EA LD CPSE EA YZ JR BCNTR 2 When stop mode is released by an interrupt set the oscillation stabilization interval to 31 3 ms BITS EMB SMB 15 LD A 0BH LD BMOD A Wait time is 31 3 ms NOP STOP Set stop power down mode NOP NOP NOP CPU Normal Mode Stop Mode Idle Mode Normal Mode Operation 4 31 3 ms STOP Stop Mode is Instruction Released by Interrupt 3 To set the basic timer interrupt interval time to 1 95 ms at 4 19 MHz BITS EMB SMB 15 LD A 0FH LD BMOD A EI BITS IEB Basic timer interrupt enable flag is set to 1 4 Clear BCNT and the IRQB flag and restart the basic timer BITS EMB SMB 15 BITS BMOD 3 ELECTRONICS 11 7 TIMERS and TIMER COUNTERS S3C72P9 P72P9 Preliminary Spec WATCHDOG TIMER MODE REGISTER WDMOD The watchdog timer mode register WDMOD is a 8 bit write only register WDMOD register controls to enable or disable the watchdog function WDMOD values are set to logic following RESET and this value enables the watchdog timer Watchdog timer is set to the longest interval because BT overflow signal is generated with the longest in
79. cannot be modified simultaneously by a 4 bit instruction they can only be modified by separate 1 bit instructions 4 36 ELECTRONICS 3 72 9 72 9 Preliminary Spec MEMORY MAP SMOD serial 1 0 Mode Register SIO FE1H Bit 6 5 4 3 2 1 0 Identifier 323 RESET Value 0 0 0 0 0 0 0 Read Write Bit Addressing od W W W 8 8 8 1 8 8 8 8 SMOD 7 5 Serial I O Clock Selection and SBUF R W Status Control Bits Ul or Enable SBUF when SIO operation is halted or when SCK goes high Enable SBUF when SIO operation is halted when SCK goes high tt Use the selected CPU clock fxx 4 8 or 64 is the system clock then enable SBUF read write operation x means don t care 1 0 0 4 09 kHz clock 210 1 1 1 262 kHz clock 24 Note You cannot select a fxx 24 clock fre quency if you have selected a CPU clock of fxx 64 NOTE All kHz frequency ratings assume a system clock of 4 19 MHz X SMOD 4 Bit 4 Always logic zero SMOD 3 Initiate Serial Operation Bit 1 Clear IRQS flag and 3 bit clock counter to logic zero then initiate serial trans mission When SIO transmission starts this bit is cleared by hardware to logic zero SMOD 2 Enable Disable SIO Data Shifter and Clock Counter Bit Disable the data shifter and clock counter the contents of
80. consumption please configure unused pins according to the guidelines described in Table 8 2 Table 8 3 Unused Pin Connections for Reducing Power Consumption Pin Share Pin Names Recommended Connection PO 0 SCK KO Input mode Connect to Vpp 1 5 1 Output mode No connection P0 2 SI K2 P0 3 BUZ K3 P2 0 CLO Input mode Connect to Vpp P2 1 LCDCK Output mode No connection P2 2 LCDSY P3 0 TCLOO P3 1 TCLO1 P3 2 TCLO P3 3 TCL1 4 0 8 4 3 1 1 P5 0 COM12 P5 3 COM15 P6 0 SEG55 K4 P6 3 SEG52 K7 P7 0 SEG51 P7 3 SEG48 P8 0 SEG47 P8 3 SEG44 P9 0 SEG43 P9 3 SEG40 SEGO SEG39 No connection COMO COM7 XT py note Stop sub oscillator by setting the SCMOD 2 to logic 1 TEST Connect to Vss NOTE You stop the sub oscillator by setting the SCMOD 2 to one ELECTRONICS 8 7 POWER DOWN 8 8 NOTES S3C72P9 P72P9 Preliminary Spec ELECTRONICS 3 72 9 72 9 Preliminary Spec RESET RESET OVERVIEW When a RESET signal is input during normal operation or power down mode a hardware reset operation is initiated and the CPU enters idle mode Then when the standard oscillation stabilization interval of 31 3 ms at 4 19 MHz has elapsed normal system operation resumes Regardless of when the RESET occurs during normal operating mode or during a power down mode most hardware register values are set to the reset values described in Table 9 1 The current status of several reg
81. detailed information in Chapters 4 and 5 very briefly Later you can refer back to Chapters 4 and 5 as necessary Part Il hardware Descriptions has detailed information about specific hardware components of the S3C72P9 P72P9 microcontroller Also included in Part are electrical mechanical OTP and development tools data Part I has 12 chapters Chapter 6 Oscillator Circuit Chapter 12 LCD Controller Driver Chapter 7 Interrupts Chapter 13 Battery Level Detector Chapter 8 Power Down Chapter 14 Electrical Data Chapter 9 RESET Chapter 15 Mechanical Data Chapter 10 Ports Chapter 16 S3P72P9 OTP Chapter 11 Timers and Timer Counters Chapter 17 Development tools Two order forms are included at the back of this manual to facilitate customer order for S3C72P9 P72P9 microcontrollers the Mask ROM Order Form and the Mask Option Selection Form You can photocopy these forms fill them out and then forward them to your local Samsung Sales Representative 3C72P9 P72P9 MICROCONTROLLER iii Table of Contents Part Programming Model Chapter 1 Product Overview See eek cnet aes dues value alos A iad 1 1 tiene 1 1 FGatUres uite de e de td e Ed dU epe eh 1 2 Block Diagram erobert mete eee esteso eee QU 1 3 Pin Assignments feeb sh ied eoe tpi nier petere tek De Re PED ae RELY Die He belli dad wetter he etui 1 4 P
82. flag with memory bit SS C memb L C H DA b Description specified bit of the source is logically ANDed with the carry flag bit value If the Boolean value of the source bit is a logic zero the carry flag is cleared to 0 otherwise the current carry flag setting is left unaltered The bit value of the source operand is not affected _ Binary Code operation Notation C mema b C lt AND mema b C memb L BERE C lt C AND memb 7 2 L 3 2 L 1 0 opnan Te Fes for on a us far ao Second Byte Bit Addresses 1 FFOHFFFH Examples 1 The following instructions set the carry flag if P1 0 port 1 0 is equal to 1 and assuming the carry flag is already set to 1 SMB 15 enn BAND C P1 0 If P1 0 1 If P1 0 0 C e 0 2 Assume the P1 address is FF1H and the value for register L is 5H 0101B The address memb 7 2 is 111100B L 3 2 is 01B The resulting address is 11110001B or FF1H specifying P1 The bit value for the BAND instruction L 1 0 is 01B which specifies bit 1 Therefore P1 L P1 1 LD L 5H BAND C P1 L P1 L is specified as P1 1 C AND P1 1 ELECTRONICS 5 31 SAM47 INSTRUCTION SET S3C72P9 P72P9 Preliminary Spec BAND Bit Logical AND BAND Continued Examples 3 Register H contains the value 2H and FLAG 20H 3 The address
83. four register banks bank 0 1 2 and 3 Each register bank has eight 4 bit registers and paired 4 bit registers are 8 bit addressable Register A is used as a 4 bit accumulator and register pair EA as an 8 bit extended accumulator The carry flag bit can also be used as a 1 bit accumulator Register pairs WX WL and HL are used as address pointers for indirect addressing To limit the possibility of data corruption due to incorrect register addressing it is advisable to use register bank 0 for the main program and banks 1 2 and 3 for interrupt service routines LCD Data Register Area Bit values for LCD segment data are stored in data memory bank 2 Register locations in this area that are not used to store LCD data can be assigned to general purpose use ELECTRONICS 2 9 ADDRESS SPACES S3C72P9 P72P9 Preliminary Spec Table 2 2 Data Memory Organization and Addressing 000H 01FH Working registers 020 Stack and general purpose registers 100H 1FFH General purpose registers Bank registers 300H 3FFH General purpose registers 400H 4FFH General purpose registers F80H FFFH O mapped hardware registers 59 PROGRAMMING Clearing Data Memory Banks 0 and 1 Clear banks 0 and 1 of the data memory area RAMCLR SMB 1 RAM 100H 1FFH clear LD HL 00H LD A 0H RMCL1 LD HL A INCS HL JR RMCL1 SMB 0 RAM 01 clear LD RMCLO LD HL A INCS HL JR RMCLO 2 10 ELECTRONICS 3
84. frequency outputs to BUZ pin e Clock source generation for LCD Interrupts Four internal vectored interrupts e Four external vectored interrupts e Two quasi interrupts Bit Sequential Carrier Supports 16 bit serial data transfer in arbitrary format Power Down Modes Idle mode only CPU clock stops Stop mode main system oscillation stops Subsystem clock stop mode Oscillation Sources Crystal ceramic or RC for main system clock Crystal oscillator for subsystem clock e Main system clock frequency 0 4 6 MHz Subsystem clock frequency 32 768 kHz e CPU clock divider circuit by 4 8 or 64 Instruction Execution Times e 0 67 1 33 10 7 us at 6 MHz 0 95 1 91 15 3 us at 4 19 MHz 122 us at 32 768 kHz Operating Temperature e 40 C to 85 C Operating Voltage Range 18V to 55V Package Type 100 QFP ELECTRONICS S3C72P9 P72P9 Preliminary Spec BLOCK DIAGRAM P1 0 P1 3 XIN INTO INT4 Input Port 1 XOUT XTIN XTouT P2 0 CLO P2 1 LCDCK lt P2 2 LCDSY Port 2 Interrupt P3 0 TCLOO Control P3 1 TCLO1 Block gt P3 2 TCLO P3 3 TCL1 t P4 0 P4 3 EN Internal 8 11 Interrupts P5 0 P5 3 COM12 COM15 P6 0 P6 3 SEG55 SEG52 gt Port 6 K4 K7 P7 0 P7 3 SEG51 SEG48 P8 0 P8 3 sEG47 sEG44 l OPort8 P9 0 P9 3 SEG43 SEG40 lt gt 5 Arithmetic
85. fxx 26 512 Hz When 1 12 duty 25 1024 Hz 110 When 1 12 duty fxx 24 2048 Hz When 1 12 duty fxx 23 4096 Hz ELECTRONICS 4 23 MEMORY MAP S3C72P9 P72P9 Preliminary Spec LMOD Mode Register LCD F8DH F8CH Bit Identifier RESET Value Read Write Bit Addressing LMOD 7 5 LMOD 4 3 LMOD 2 LMOD 1 0 4 24 3 2 1 0 3 2 1 0 _ e 5 4 3 2 9 0 0 0 0 0 0 0 0 w w w w w w w w 8 8 8 8 8 8 8 8 LCD Output Segment and Pin Configuration Bits Segments 40 43 44 47 48 51 and 52 55 70 Segments 40 43 and 44 47 at pon and port Normal at ports 6 7 8 and 9 NOTE Segment pins that also can used for normal I O should be configured to output mode when the SEG function is used 910 EIER LCD Clock LCDCK Frequency Selection Bits 9 0 When 1 8 duty fxx 2 256 Hz when 1 12 1 16 duty fxx 26 512 Hz When 1 8 duty 26 512 Hz when 1 12 1 16 duty 25 1024 Hz When 1 8 duty fxx 2 1024 Hz when 1 12 1 16 duty 24 2048 Hz When 1 8 duty fxx 24 2048 Hz when 1 12 1 16 duty fxx 23 4096 Hz NOTE LCDCK is supplied only when the watch timer operates To use the LCD controller bit 2 in the watch mode register WMOD should be set to 1 LCD Duty and Selection Bits 1 8 duty 0 select 1 16 duty 0 15 select NOTE When 1
86. increments the value of the destination operand by An original value of OFH will for example overflow to OOH If a carry occurs the next instruction is skipped The carry flag value is unaffected Binary Code Operation Notation lo 1 R lt 1 skip on carry lt DA 1 skip carry a2 at 20 ES ESESES HL HL 1 skip on carry ofifo 2 lt 1 skip on cary Example Register pair HL contains the value 7EH 01111110B RAM location 7EH contains OFH The instruction sequence 1 2 2 1 1 E Lo o 67 ES INCS HL lt INCS HL Skip INCS HL lt 1 leaves the register pair HL with the value 7EH and RAM location 7EH with the value 1H Since a carry occurred the second instruction is skipped The carry flag value remains unchanged 5 56 ELECTRONICS S3C72P9 P72P9 Preliminary Spec SAM47 INSTRUCTION SET Return from Interrupt IRET Description IRET is used the end of an interrupt service routine It pops the PC values successively from the stack and restores them to the program counter The stack pointer is incremented by six and the PSW enable memory bank EMB bit and enable register bank ERB bit are also automatically restored to their pre interrupt values Program execution continues from the resulting ad
87. logic zero selecting the main system clock fx as the CPU clock and starting clock oscillation The reset value of the SCMOD is 0 SCMOD 0 SCMOD 2 and SCMOD 3 bits can be manipulated by 1 bit write instructions In other words SCMOD 0 SCMOD 2 and SCMOD 3 cannot be modified simultaneously by a 4 bit write Bit 1 is always logic zero A subsystem clock fxt can be selected as the system clock by manipulating the SCMOD 3 and SCMOD O bit settings If SCMOD 3 0 SCMOD 0 1 the subsystem clock is selected and main system clock oscillation continues If SCMOD 3 1 and SCMOD 0 1 fxt is selected but main system clock oscillation stops Even if you have selected fx as the CPU clock setting SCMOD 3 to 1 will stop main system clock oscillation and malfunction may be occured To operate safely main system clock should be stopped by a stop instruction is main system clock mode Table 6 3 System Clock Mode Register SCMOD Organization SCMOD Register Bit Settings Resulting Clock Selection SCMOD 3 SCMOD 0 CPU Clock Source fx Oscillation T SCMOD 2 Sub oscillation on off Eco gt Enable sub system clock Disable sub system clock NOTE You can use SCMOD 2 as follows ex after data bank was used few minutes have passed Main operation gt sub operation sub idle LCD on after few minutes later without any external input gt sub operation main operation gt SCMOD 2 1 main
88. logic zero F91H Specify input clock edge and internal frequency Bit Name TMODO 7 TMODO 6 TMODO 5 TMODO 4 Enable timer counter 0 Always logic zero Always logic zero TMODO 1 TMODO 0 TMODO 3 1 Clear TCNTO IRQTO and TOLO and resume counting immedi F90H ately This bit is automatically cleared to logic zero immediately after counting resumes TMODO 2 Disable timer counter 0 retain TCNTO contents ELECTRONICS 11 17 TIMERS and TIMER COUNTERS S3C72P9 P72P9 Preliminary Spec Table 11 7 TMODO 6 TMODO 5 and TMODO 4 Bit Settings TMODO 6 TMODO 5 TMODO 4 Resulting Counter Source and Clock Frequency Lue o o External clock input TCLO on rising edges 1 External clock input TCLO on faling edges fees 1 1 o rf 262 it NOTE selected system clock of 4 19 MHz PROGRAMMING Restarting TCO Counting Operation 1 Set TCO timer interval to 4 09 kHz BITS EMB SMB 15 LD EA 4CH LD TMODO EA EI BITS IETO 2 Clear TCNTO IRQTO and TOLO and restart TCO counting operation BITS EMB SMB 15 BITS TMODO 3 11 18 ELECTRONICS S3C72P9 P72P9 Preliminary Spec TIMERS and TIMER COUNTERS TCO COUNTER REGISTER TCNTO The 8 bit counter register for timer counter 0 TCNTO is read only and can be addressed by 8 bit RAM control instructions RESET sets all TCNTO register values to logic zero 00H Whenever TMODO 3 is enabled TCNTO is cleared to
89. low as 122 us at 32 768 kHz and with very low power consumption Watch Timer Main system Sub system LCD Controller Oscillator Oscillator Circuit Circuit Stop XTN fxx Oscillator 1 1 1 4096 Stop Basic Timer Frequency Timer Counter Dividing Watch Timer Circuit LCD Controller Clock Output Circuit 1 2 1 16 gt SCMOD3 SCMODO SCMOD2 CPU stop signal CPU Clock IDLE mode PCON 1 Wait release signal PCON 2 Oscillator Control internal RESET signal PCON 3 Circuit Power down release signal PCON 3 2 clear fx Main system clock fxt Sub system clock fxx System clock Figure 6 1 Clock Circuit Diagram 6 2 ELECTRONICS S3C72P9 P72P9 Preliminary Spec OSCILLATOR CIRCUITS MAIN SYSTEM OSCILLATOR CIRCUITS SUB SYSTEM OSCILLATOR CIRCUITS XIN XOUT 32 768 kHz Figure 6 2 Crystal Ceramic Oscillator fx Figure 6 5 Crystal Ceramic Oscillator fxt XIN External Clock XOUT Figure 6 3 External Oscillator fx Figure 6 6 External Oscillator fxt XIN R XOUT Figure 6 4 RC Oscillator fx ELECTRONICS 6 3 OSCILLATOR CIRCUITS S3C72P9 P72P9 Preliminary Spec POWER CONTROL REGISTER PCON The power control register PCON is a 4 bit register that is used to select the CPU clock frequency and to control CPU operating and power down modes PCON can be addressed directly by 4 bit write instructions or indirectly by the instructions IDLE
90. main oscillation clock Sub operating Main oscillator is stopped by mode SCMOD 3 Sub oscillator runs System clock is the sub oscillation clock Sub Idle Mode Main oscillator is stopped by IDLE instruction SCMOD 3 Sub oscillator runs System clock is the sub oscillation clock Sub Stop mode Main oscillator is stopped by Setting SCMOD 2 to 1 SCMOD 3 This mode can be released only Sub oscillator runs by an external RESET System clock is the sub oscillation clock Main Sub Stop Main oscillator runs STOP instruction mode Sub oscillator is stopped by This mode can be released by SCMOD 2 an interrupt and RESET System clock is the main oscillation clock NOTE Thecurrent consumption is A B C D E ELECTRONICS 8 3 POWER DOWN S3C72P9 P72P9 Preliminary Spec IDLE MODE TIMING DIAGRAMS Oscillator Idle Stabilization Wait Time Instruction 31 3 ms 4 19 MHz Y RESET Normal Mode Idle Mode Normal Mode O o Normal Oscillation Figure 8 1 Timing When Idle Mode is Released by RESET Idle Instruction Mode i Release Signal Normal Mode Idle Mode Normal Mode Normal Oscillation Figure 8 2 Timing When Idle Mode is Released by an Interrupt 8 4 ELECTRONICS 3 72 9 72 9 Preliminary Spec POWER DOWN STOP MODE TIMING DIAGRAMS Oscillator Stop Stabilization Wait Time Instruction 31 3 ms 4 19 MHz Y pee RESET Normal Mode Stop mode Idle Mode Normal Mode
91. mode stop or idle Bits 3 and 2 of the PCON register can be manipulated by STOP or IDLE instruction to engage stop or idle power down mode The SCMOD lets you select the main system clock fx or a subsystem clock fxt as the CPU clock and start or stop main sub system clock oscillation The resulting clock source either main system clock or subsystem clock is referred to the selected system clock fxx The main system clock is selected and oscillation started when all SCMOD bits are cleared to 0 By setting SCMOD 3 SCMOD 2 and SCMOD 0 to different values you can select a subsystem clock source and start or stop main sub system clock oscillation To stop main system clock oscillation you must use the STOP instruction assuming the main system clock is selected or manipulate SCMOD 3 to assuming the sub system clock is selected The main system clock frequencies can be divided by 4 8 or 64 and a subsystem clock frequencies can only be divided by 4 By manipulating PCON bits 1 and 0 you select one of the following frequencies as the CPU clock fx 4 fxt 4 fx 8 fx 64 ELECTRONICS 6 1 OSCILLATOR CIRCUITS S3C72P9 P72P9 Preliminary Spec Using a Subsystem Clock If a subsystem clock is being used as the selected system clock the idle power down mode can be initiated by executing an IDLE instruction The watch timer buzzer and LCD display operate normally with a subsystem clock source since they operate at very low speed as
92. of H is 0010B and FLAG 3 0 is OOOOB The resulting address is 00100000B or 20H The bit value for the BAND instruction is 3 Therefore H FLAG 20H 3 FLAG EQU 20H 3 LD H 2H BAND C H FLAG AND FLAG 20H 3 5 32 ELECTRONICS S3C72P9 P72P9 Preliminary Spec SAM47 INSTRUCTION SET BITR Bit Reset BITR dst b Operation Operand Operation Summary Bytes Clear specified memory bit to logic zero 2 2 H DA b Description instruction clears to logic zero resets the specified bit within the destination operand No other bits in the destination are affected operand Binary ode Operation Notation DA b 1 4 DAb O _______ NN d a ____ Fe po oo fas Lar Second Byte Bit Addresses L 48 a ________ 22 Examples 1 If the Bit location 30H 2 in the RAM has a current value of 1 The following instruction clears the third bit of location 30H to 0 BITR 30H 2 2 lt 2 You can use BITR in the same way to manipulate port address bit BITR 0 0 0 lt 0 ELECTRONICS 5 33 SAM47 INSTRUCTION SET S3C72P9 P72P9 Preliminary Spec BITR Bit Reset BITR Continued Examples 3 For clearing P0 2 P0 3 and P1 0 P1 3
93. operations are initiated When the SIO transmission starts SMOD 3 is cleared to logical zero Table 13 1 SIO Mode Register SMOD Organization Most significant bit MSB is transmitted first Least significant bit LSB is transmitted first Receive only mode Transmit and receive mode Disable the data shifter and clock counter retain contents of IRQS flag when serial transmission is halted Enable the data shifter and clock counter set IRQS flag to 1 when serial transmission is halted Clear IRQS flag and 3 bit clock counter to 0 initiate transmission and then reset this bit to logic zero SBUF is enabled when SIO operation is halted or when SCK goes high Use TOLO clock from TCO CPU clock fxx 4 fxx 8 fxx 64 Enable SBUF read write SBUF is enabled when SIO operation is halted or when SCK goes high NOTES 1 system clock x means don t 2 kHzfrequency ratings assume a system clock fxx running at 4 19 MHz 3 The SIO clock selector circuit cannot select a fxx 24 clock if the CPU clock is fxx 64 4 must be selected MSB first LSB first transmission mode before loading the data to SBUF I ELECTRONICS 13 3 SERIAL INTERFACE S3C72P9 P72P9 Preliminary Spec SERIAL 1 TIMING DIAGRAMS HO O IROS Transmit Y Complete T SET SMOD 3 Figure 13 2 SIO Timing in Transmit Receive Mode High Impendence IROS Transmit Complete p SET SMOD 3 Figure 13
94. page referencing with the LDC instruction ORG 0100H DB 67H SMB 0 LD HL 30H Even number LD WX 00H LDC EA WX E lt upper 4 bits of 0100H address A lt lower 4 bits of 0100H address LD HL EA RAM 30H lt 7 RAM 31H lt 6 5 70 ELECTRONICS S3C72P9 P72P9 Preliminary Spec SAM47 INSTRUCTION SET LDD Load Data Memory and Decrement LDD dst A HL Load indirect data memory contents to A decrement 1 2 5 register L contents and skip on borrow Description contents of a data memory location are loaded into the accumulator and the contents of the register L are decreased by one If a borrow occurs e g if the resulting value in register L is OFH the next instruction is skipped The contents of data memory and the carry flag value are not affected A HL lt HL then L lt L 1 skip i L Example In this example assume that register pair HL contains 20H and internal RAM location 20H contains the value OFH LD HL 20H LDD A HL A lt HL and L L 1 JPS XXX Skip JPS YYY 2H and L e 0FH The instruction JPS is skipped since a borrow occurred after the LDD A HL and instruction JPS YYY is executed ELECTRONICS 5 71 SAM47 INSTRUCTION SET S3C72P9 P72P9 Preliminary Spec LDI Load Data Memory and Increment LDI Operation Description Example 5 72 dst src A HL Load indirect data memory to A increment register L
95. pins Edge detection circuit Three mode registers IMODO IMOD1 and IMOD2 The mode registers are used to control the triggering edge of the input signal IMODO IMOD1 and IMOD2 settings let you choose either the rising or falling edge of the incoming signal as the interrupt request trigger The INT4 interrupt is an exception since its input signal generates an interrupt request on both rising and falling edges Since INT2 is a qusi interrupt the interrupt request flag IRQ2 must be cleared by software 9 ow w IMODO IMOD1 and IMOD2 are addressable by 4 bit write instructions RESET clears all IMOD values to logic zero selecting rising edges as the trigger for incoming interrupt requests FDAH Table 7 5 IMODO 1 and 2 Register Organization o won etect of MOBO Setings Rising exe dtecton ating eae detection 1 ana taling edge detection IMOD1 0 Effect of IMOD1 and IMOD2 Settings IMOD2 0 0 Rising edge detection Falling edge detection IMODO IMOD1 IMOD2 7 8 ELECTRONICS S3C72P9 P72P9 Preliminary Spec INTERRUPTS EXTERNAL INTERRUPT 0 1 and 2 MODE REGISTERS Continued Figure 7 5 Circuit Diagram for INTO INT1 and INT2 Pins When modifying the IMOD registers it is possible to accidentally set an interrupt request flag To avoid unwanted interrupts take these precautions when writing your programs 1 D
96. referenced by a REF instruction ELECTRONICS 5 79 SAM47 INSTRUCTION SET S3C72P9 P72P9 Preliminary Spec REF Reference Instruction REF Continued Examples 1 Instructions can be executed efficiently using REF as shown in the following example ORG 0020H AAA LD HL 00H BBB LD EA FFH CCC TCALL SUB1 DDD TJP SUB2 ORG 0080H REF AAA LD HL 00H REF BBB LD EA FFH REF CCC CALL 5081 REF DDD JP SUB2 2 The following example shows how the REF instruction is executed in relation to LD instructions that have redundancy effect ORG 0020H AAA LD EA 40H ORG 0100H LD EA 30H REF AAA Not skipped REF AAA LD EA 50H Skipped SRB 2 5 80 ELECTRONICS S3C72P9 P72P9 Preliminary Spec SAM47 INSTRUCTION SET REF Reference Instruction REF Concluded Examples 3 In this example the binary code of REF 1 at locations 20H 21H is 20H for REF 2 at locations 22H 23H it is 21H and for REF at 24H 25H the binary code is 22H Opcode Symbol Instruction ORG 0020H 83 00 Al LD HL 00H 83 03 A2 LD HL 03H 83 05 LD HL 05H 83 10 A4 LD 83 26 A5 LD HL 26H 83 08 A6 LD HL 08H 83 OF A7 LD HL 0FH 83 FO 8 LD HL 0FOH 83 67 AQ LD HL 067H 41 08 10 TCALL 5081 01 00 11 SUB2 20 REF Al LD HL 00H 21 REF A2 LD HL 03H 22 REF LD HL 05H 23 REF A4 LD 24 REF 5 LD HL 26H 25 REF A6 LD HL 08H 26 REF LD HL 0FH 27 REF 8 LD H
97. register is cleared to logic zero and all systems are operational the instruction sequence STOP NOP NOP NOP sets bit 3 of the PCON register to logic one stopping all controller operations with the exception of some peripheral hardware The three NOP instructions provide the necessary timing delay for clock stabilization before the next instruction in the program sequence is executed ELECTRONICS 5 91 SAM47 INSTRUCTION SET S3C72P9 P72P9 Preliminary Spec VENT Load EMB ERB and Vector Address VENTn dst operation operara Operation Summary 0 1 Load enable memory bank flag EMB and the enable 2 2 ERB 0 1 register bank flag ERB and program counter to vector ADR address then branch to the corresponding location Description The VENT instruction loads the contents of the enable memory bank flag EMB and enable register bank flag ERB into the respective vector addresses It then points the interrupt service routine to the corresponding branching locations The program counter is loaded automatically with the respective vector addresses which indicate the starting address of the respective vector interrupt service routines The EMB and ERB flags should be modified using VENT before the vector interrupts are acknowledged Then when an interrupt is generated the EMB and ERB values of the previous routine are automatically pushed onto the stack and then popped back when the routine
98. resistor clear bits 0 and 1 of the LCON register 1 4 Bais 1 5 Bais S3C72P S3C72P9 NM VcL2 VCL3 4 VCL5 Figure 12 4 LCD Bias Circuit Connection 12 8 ELECTRONICS S3C72P9 P72P9 Preliminary Spec LCD CONTROLLER DRIVER S3C72P9 Interval Voltage Dividing Resistor LCON 1 Contrast 16 steps of voltages Variable Resistor for Controller 9 1 Brightness Control LCD contrast control enable bit LCNST 7 cono Vss NOTES 1 When the LCD module is turned off clear 0 and LCON 1 0 to reduce power consumption 2 Ifan external variable is uesd to connect V Lc5 to ground you can control LCD contrast using the variable resistor Figure 12 5 Internal Voltage Dividing Resistor and Contrast Control Circuit 1 5 Bias Display On ELECTRONICS 12 9 LCD CONTROLLER DRIVER S3C72P9 P72P9 Preliminary Spec COMMON COM SIGNALS The common signal output pin selection COM pin selection varies according to the selected duty cycle n 1 8 duty mode 7 pins are selected 1 12 duty mode COMO COM 1 pins are selected n 1 16 duty mode 15 pins are selected When 1 8 duty is selected by clearing LMOD 2 to zero COM8 COM15 4 0 5 3 can be used for normal I O port When 1 12 duty is selected by setting LCON 3 to one ports 4 should be configured as output mode and port5 can be used for Normal I O port SEGMENT SEG SIGNALS The 56
99. service routines The 16 byte area can be used alternately as general purpose ROM REF Instructions Locations 0020 007 are used as a reference area look up table for 1 byte REF instructions The REF instruction reduces the byte size of instruction operands REF can reference one 2 byte instruction two 1 byte instructions and one 3 byte instructions which are stored in the look up table Unused look up table addresses can be used as general purpose ROM Table 2 1 Program Memory Address Ranges ROM Area Function Address Ranges Area Size in Bytes General purpose program memory 0010H 001FH REF instruction look up table area 0020H 007FH General purpose program memory 0080H 7FFFH 32 640 ELECTRONICS 2 1 ADDRESS SPACES S3C72P9 P72P9 Preliminary Spec GENERAL PURPOSE MEMORY AREAS The 16 byte area at ROM locations 0010 001 and the 32 640 byte area at ROM locations 0080H 7FFFH used as general purpose program memory Unused locations in the vector address area and REF instruction look up table areas can be used as general purpose program memory However care must be taken not to overwrite live data when writing programs that use special purpose areas of the ROM VECTOR ADDRESS AREA The 16 byte vector address area of the ROM is used to store the vector addresses for executing system resets and interrupts The starting addresses of interrupt service routines are stored in this area along with the enable memory
100. significant bit of the BMOD register BMOD 3 is used to restart the basic timer When BMOD 3 is set to logic one by a 1 bit write instruction the contents of the BT counter register BCNT and the BT interrupt request flag IRQB are both cleared to logic zero and timer operation restarts The combination of bit settings in the remaining three registers BMOD 2 BMOD 1 and BMOD 0 determine the clock input frequency and oscillation stabilization interval Table 11 2 Basic Timer Mode Register BMOD Organization BMOD 3 Basic Timer Start Control Bit 1 Start basic timer clear BCNT BMOD 3 to 0 BMOD 2 BMOD 1 BMOD 0 Basic Timer Input Clock Interrupt Interval Time Wait Time 212 1 02 kHz 220 fxx 250 ms fxx 29 8 18 kHz 217 31 3 ms 27 32 7 kHz 215 7 82 ms 9 3 35 9 3 NOTES 1 Clock frequencies and interrupt interval time assume a system oscillator clock frequency fxx of 4 19 MHz 2 fxx system clock frequency 3 Wait time is the time required to stabilize clock signal oscillation after stop mode is released The data in the table column Interrupt Interval Time can also be interpreted as Oscillation Stabilization 4 The standard stabilization time for system clock oscillation following a RESET is 31 3 ms at 4 19 MHz ELECTRONICS 11 5 TIMERS and TIMER COUNTERS S3C72P9 P72P9 Preliminary Spec BASIC TIMER COUNTER BCNT BONT is an 8 bit counter
101. the L register BSC data can also be manipulated using direct addressing For 8 bit manipulations the 4 bit register names BSCO and BSC2 must be specified and the upper and lower 8 bits manipulated separately If the values of the L register are OH at BSCO L the address and bit location assignment is FCOH O If the L register content is FH at BSCO L the address and bit location assignment is FC3H 3 Table 2 4 BSC Register Organization me Ames me BSCO FCOH BSCO 3 5 0 2 BSCO 1 BSCO 0 BSC1 FC1H BSC1 3 BSC1 2 BSC1 1 BSC1 0 BSC2 FC2H BSC2 3 BSC2 2 BSC2 1 BSC2 0 BSC3 FC3H BSC3 3 BSC3 2 BSC3 1 BSC3 0 PROGRAMMING Using the BSC Register to Output 16 Bit Data To use the bit sequential carrier BSC register to output 16 bit data 5937 to the P3 0 pin BITS EMB SMB 15 LD EA 37H LD BSCO EA BSCO lt 1 lt E LD EA 59H LD BSC2 EA BSC2 lt BSC3 lt E SMB 0 LD L 0H LDB C BSCO L LDB P3 0 C P3 0 lt INCS L JR AGN RET 2 18 ELECTRONICS 3 72 9 72 9 Preliminary Spec ADDRESS SPACES PROGRAM COUNTER PC A 14 bit program counter PC stores addresses for instruction fetches during program execution Whenever a reset operation or an interrupt occurs bits PC13 through PCO are set to the vector address Usually the PC is incremented by the number of bytes of the instruction being fetched One exception is the 1 byte REF instr
102. to 0 LD L 2H BP2 BITR PO L First PO 2H 2 111100B 00B 10B 2 INCS L CPSE L 8H JR BP2 4 If bank 0 location is cleared and regardless of whether the value is logic zero BITR has the following effect FLAG EQU 0AOH 0 BITR EMB LD H 0AH BITR QH FLAG Bank 0 0 lt 0 NOTE Since the BITR instruction is used for output functions the pin names used in the examples above may change for different devices in the SAM47 product family 5 34 ELECTRONICS S3C72P9 P72P9 Preliminary Spec SAM47 INSTRUCTION SET BITS Bit set BITS dst b H DA b Description This instruction sets the specified bit within the destination without affecting any other bits in the destination BITS can manipulate any bit that is addressable using direct or indirect addressing modes DA b 1 1 DAbet MEET aT 1 4 a2 o ot a2 at 20 Second Byte Bit Addresses memab 1 0 bt 3 a2 at a0 as a2 FOHFFFH i Examples 1 If the bit location 30H 2 in the RAM has a current value of 0 the following instruction sets the second bit of location 30H to 1 BITS 30H 2 2 lt 1 2 You use BITS in the same way to manipulate a port address bit BITS 0 0
103. to Vas NOTE Pull up resistors for all ports are automatically disabled if they are configured to output mode I 1 6 ELECTRONICS S3C72P9 P72P9 Preliminary Spec PRODUCT OVERVIEW Table 1 2 Overview of S3C72P9 P72P9 Pin Data Share Pins 107 Reset Value Grout Type ema w _ 5 0 5 3 12 15 sesaka scos e ma 8 0 8 3 SEG47 SEG44 9 0 9 3 SEG43 SEG40 SEGO SEG39 ELECTRONICS 1 7 PRODUCT OVERVIEW 3 72 9 72 9 Preliminary Spec PIN CIRCUIT DIAGRAMS P Channel Pull up Resistor N Channel Schmitt Trigger Figure 1 3 Pin Circuit Type A Figure 1 5 Pin Circuit Type B Pull Up Resistor Pull Up P Channel lt Resistor Enable In P Channel Out Output N Channel Disable Schmitt Trigger Figure 1 4 Pin Circuit Type A 3 Figure 1 6 Pin Circuit Type C 1 8 ELECTRONICS S3C72P9 P72P9 Preliminary Spec PRODUCT OVERVIEW VDD Pull up Resistor Resistor Enable Disable Figure 1 7 Pin Circuit Type E Pull up Resistor Resistor Enable Data Output Disable Schmitt Trigger Figure 1 8 Pin Circuit Type E 1 ELECTRONICS 1 9 PRODUCT OVERVIEW S3C72P9 P72P9 Preliminary Spec VDD Pull up Resistor Resistor Disable Schmitt Trigger Figure 1 9 Pin Circuit Type E 2 1 10 ELECTRONICS S3C72P9 P72P9 Prelimina
104. 00H 0FFH Bank 0 lower four bits of the address DA memory bank selection and the H register identifier 000H FFFH 5 0 1 All 1 bit addressable peripherals SMB 15 NOTE x means don t care 3 6 ELECTRONICS S3C72P9 P72P9 Preliminary Spec PROGRAMMING TIP 1 Bit Addressing Modes 1 Bit Direct Addressing 0 1 If EMB AFLAG BFLAG CFLAG 2 If EMB AFLAG BFLAG CFLAG EQU EQU EQU SMB BITS BITS BTST BITS BITS 1 EQU EQU EQU SMB BITS BITS BTST BITS BITS ELECTRONICS 34H 3 85H 3 0 0 AFLAG BFLAG CFLAG BFLAG P3 0 34H 3 85H 3 0 0 AFLAG BFLAG CFLAG BFLAG P3 0 34H 3 lt 1 F85H 3 1 If FBAH O 1 skip Else if FBAH 0 0 F85H 3 BMOD 3 lt 1 FF3H 0 P3 0 lt 1 34H 3 lt 1 85H 3 lt 1 If OBAH O 1 skip Else if OBAH 0 0 085 3 lt 1 0 P3 0 lt 1 ADDRESSING MODES 3 7 ADDRESSING MODES S3C72P9 P72P9 Preliminary Spec 55 PROGRAMMING TIP 1 Bit Addressing Modes Continued 1 Bit Indirect Addressing 1 If EMB 0 AFLAG EQU 34H 3 BFLAG EQU 85H 3 CFLAG EQU 0 SMB 0 LD H 0BH lt 0BH BTSTZ H CFLAG 1 0 lt 0 and skip BITS CFLAG Else if 0 FBAH O lt 1 2 If EMB 1 AFLAG EQU 34H 3 BFLAG EQU 85H 3 CFLAG EQU 0 SMB 0 LD H 0BH H lt 0BH BTSTZ H CFLAG
105. 1 2 5 contents and skip on overflow The contents of a data memory location are loaded into the accumulator and the contents of the register L are incremented by one If an overflow occurs e g if the resulting value in register L is OH the next instruction is skipped The contents of data memory and the carry flag value are unaffected A HL lt HL then L lt L 1 skip L 0H Assume that register pair HL contains the address 2FH and internal RAM location 2FH contains the value OFH LD HL 2FH LDI A HL A lt HL and L 1 JPS XXX Skip JPS 2H and L lt 0H The instruction JPS XXX is skipped since an overflow occurred after the 01 A HL and the instruction JPS YYY is executed ELECTRONICS S3C72P9 P72P9 Preliminary Spec SAM47 INSTRUCTION SET LJP Long Jump JP dst Operation Operand Operation Summary Bytes ADR15 Jump to direct address 15 bits Description causes an unconditional branch to the indicated address by replacing the contents of the program counter with the address specified in the destination operand The destination can be any where in the 32 Kbyte program memory address space The LJP instruction can be used in the all range 0000H 7FFFH while the JP instruction can be used in the only range 0000H 3FFFH operand Binary Code operaron Norion ws 1 9 9 9 ams o su ao ae as aso so 26 Fees
106. 11B and register pair HL contains 55H 01010101 the instruction Operand Bin A HL yc ary Cod a 1 Es ERE 1 XOR EA HL leaves the value 96H 10010110B in the extended accumulator ELECTRONICS 5 97 SAM47 INSTRUCTION SET S3C72P9 P72P9 Preliminary Spec NOTES 5 98 ELECTRONICS S3C72P9 P72P9 Preliminary Spec OSCILLATOR CIRCUITS OSCILLATOR CIRCUITS OVERVIEW The S3C72P9 microcontroller have two oscillator circuits a main system clock circuit and a subsystem clock circuit The CPU and peripheral hardware operate on the system clock frequency supplied through these circuits Specifically a clock pulse is required by the following peripheral modules LCD controller Basic timer Timer counters 0 and 1 Watch timer Serial interface Clock output circuit CPU Clock Notation In this document the following notation is used for descriptions of the CPU clock fx Main system clock fxt Subsystem clock fxx Selected system clock Clock Control Registers When the system clock mode register SCMOD and the power control register PCON are both cleared to zero after RESET the normal CPU operating mode is enabled a main system clock is selected as fx 64 and main System clock oscillation is initiated The PCON is used to select normal CPU operating mode or one of two power down
107. 16 duty is selected ports 4 and 5 should be configured as output mode when 1 8 duty is selected ports 4 and 5 can be used as normal I O ports LCD Display Mode Selection Bits o uicem ELECTRONICS 3 72 9 72 9 Preliminary Spec MEMORY MAP PCON Power Control Register CPU FB3H Bit 3 2 1 0 RESET Value 0 0 0 0 Read Write W W W Bit Addressing 4 4 4 4 PCON 3 2 CPU Operating Mode Control Bits Enable normal CPU operating mode Initiate idle power down mode race Initiate stop power down mode PCON 1 0 CPU Clock Frequency Selection Bits fx 64 if SCMOD 0 1 fxt 4 0 fx 8 if SCMOD O 1 fxt 4 0 fx 4 if SCMOD O0 1 fxt 4 NOTE fx is the main system clock fxt is the subsystem clock ELECTRONICS 4 25 MEMORY MAP S3C72P9 P72P9 Preliminary Spec PMG1 Port 1 0 Mode Register 1 Group 1 Ports 0 2 y o FE7H FE6H Bit 7 6 5 4 3 2 1 0 RESET Value 0 0 0 0 0 0 0 0 Read Write W W W W W Bit Addressing 8 8 8 8 8 8 8 8 7 Bit 7 EN Always logic zero PM2 2 P2 2 I O Mode Selection Flag EN Set P2 2 to input mode Set P2 2 to output mode PM2 1 P2 1 I O Mode Selection Flag 0 Set P2 1 to input mode Set P2 1 to output mode PM2 0 P2 0 I O Mode Selection Flag 0 Set P2 0 to input mode Set P2 0 to output mode PMO 3 P0 3 I O Mode Selection Flag 0 Set P0 3 to input mode Set P0 3 to output mode 2 PO 2 I O Mode Selec
108. 2 2 2 cael a3 a2 at ao o lt OR RR LX o oic e ES 1 EX EE EEE e 07 rjo ojmnjo ER NER A HL EA RR RRb EA Fas ae a Ps fo __ Ea aa ee po feta 0 RRb lt RRb EA A HL EA RR RRb EA ERE ES ERE _ 0 1 EA RR ERE ERE ERE TN o 1 5 20 ELECTRONICS S3C72P9 P72P9 Preliminary Spec SAM47 INSTRUCTION SET Table 5 19 Arithmetic Instructions Binary Code Summary Lame operand Operation Noton wc to o r 1 pese arn Depp 1 oo jenem e mec 1 lt EA imm ERESESESERTAEJIESR EA lt EA imm skip on carry rar as os ue as ar oo SY TE TT 1 o EA EA skip 1 11 0 11 111 0 skip E d xem 1 rts SA muc C lt EA RR C o CAR
109. 2 FF2H Same as port 0 except that port 2 is 3 bit port 4 0 4 3 FF4H 4 bit ports 5 0 5 3 FF5H 1 4 bit or 8 bit read write and test is possible Individual pins are software configurable as input or output 4 bit pull up resistors are software assignable pull up resistors are automatically disabled for output pins P6 0 P6 3 FF6H Same as P4 and P5 P7 0 P7 3 FF7H 8 0 8 3 FF8H Same as P4 and P5 9 0 9 3 FF9H Table 10 2 Port Pin Status During Instruction Execution Instruction Type Example Input Mode Status Output Mode Status 1 bit test BTST PO 1 Input or test data at each pin Input or test data at output latch 1 bit input LDB 1 3 4 bit input LD A P7 8 bit input L EA P4 D BITR P2 3 Output latch contents undefined Output pin status is modified 4 bit output LD 2 Transfer accumulator data to the Transfer accumulator data to the 8 bit output LD P6 EA output latch output pin 10 2 ELECTRONICS 3 72 9 72 9 Preliminary Spec PORTS PORT MODE FLAGS PM FLAGS Port mode flags PM are used to configure ports to input or output mode by setting or clearing the corresponding buffer For convenient program reference PM flags are organized into five groups PMG1 PMG2 PMG3 PMG4 and PMG5 as shown in Table 10 3 They are addressable by 8 bit write instructions only When a PM is 0 the port is set to input mode when it is 1 the port is enabled
110. 20 S3 C72P9 P72P9 1199 USER S MANUAL 53 72 9 72 9 4 Bit CMOS Microcontroller Revision 0 ELECTRONICS S3C72P9 P72P9 4 BIT CMOS MICROCONTROLLER USER S MANUAL Revision 0 ELECTRONICS Important Notice The information in this publication has been carefully checked and is believed to be entirely accurate at the time of publication Samsung assumes no responsibility however for possible errors or omissions or for any consequences resulting from the use of the information contained herein Samsung reserves the right to make changes in its products or product specifications with the intent to improve function or design at any time and without notice and is not required to update this documentation to reflect such changes This publication does not convey to a purchaser of semiconductor devices described herein any license under the patent rights of Samsung or others Samsung makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Samsung assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation any consequential or incidental damages S3C72P 4 Bit CMOS Microcontroller User s Manual Revision 0 Publication Number 20 S3 C72P9 P72P9 1199 1999 Samsung Electronics Typical parameters can and do vary in different applications All ope
111. 3 SIO Timing in Receive Only Mode 13 4 ELECTRONICS S3C72P9 P72P9 Preliminary Spec SERIAL I O INTERFACE SERIAL BUFFER REGISTER SBUF The serial I O buffer register SBUF be read or written using 8 bit RAM control instructions Following a RESET the value of SBUF is undetermined When the serial interface operates in transmit and receive mode SMOD 1 1 transmit data in the SIO buffer register are output to the SO pin 0 1 at the rate of one bit for each falling edge of the SIO clock Receive data are simultaneously input from the SI pin 0 2 to SBUF at the rate of one bit for each rising edge of the SIO clock When receive only mode is used incoming data are input to the SIO buffer at the rate of one bit for each rising edge of the SIO clock 59 PROGRAMMING Setting Transmit Receive Modes for Serial 1 Transmit the data value 48H through the serial I O interface using an internal clock frequency of fxx 2 and in MSB first mode BITS EMB SMB 15 LD EA 03H LD PMG1 EA LD EA 0E6H LD SMOD EA P0 0 SCK and 0 1 SO lt Output LD EA 48H LD SBUF EA BITS SMOD 3 510 data transfer SCK PO 0 External SO PO 1 Device S3C72P9 2 Use CPU clock to transfer and receive serial data at high speed BITS EMB SMB 15 LD EA 03H LD PMG1 EA P0 0 SCK and 0 1 50 lt Output P0 2 SI LD EA 47H LD SMOD EA lt Input LD EA TDATA LD SBUF EA BITS SMOD 3 SIO start BITR I
112. 4 E 1 05 2 750 2 15 6 2 Supply Voltage V CPU clock 1 n x oscillator frequency n 4 8 or 64 Figure 14 1 Standard Operating Voltage Range ELECTRONICS 14 9 ELECTRICAL DATA 57 22532 22532 Preliminary Spec Table 14 9 RAM Data Retention Supply Voltage in Stop Mode 40 85 C Data retention supply voltage Data retention supply current Vpppn 1 8 V Min Release signal set time tsREL Oscillator stabilization wait Released by RESET time 1 Released by interrupt NOTES 1 During oscillator stabilization wait time all CPU operations must be stopped to avoid instability during oscillator start up 2 Use the basic timer mode register BMOD interval timer to delay execution of CPU instructions during the wait time 14 10 ELECTRONICS 557 22532 22532 Preliminary Spec ELECTRICAL DATA TIMING WAVEFORMS Internal RESET Operation lt 2 Stop Mode Idle Mode Data Retention Mode Normal Mode 5 Execution of STOP Instrction iSREL 4 Figure 14 2 Stop Mode Release Timing When Initiated by RESET Idle Mode Y 1 1 Stop Mode gt lt Normal Mode Data Retention Mode A Execution of STOP Instrction Power down Mode Terminating Signal Interrupt Request Figure 14 3 Stop Mode Release Timing
113. 7 3 17 3 50 Pin Connectors for 2 9 222 2 6 17 6 17 4 TB72P9 Adapter Cable for 100 QFP Package 53 72 9 17 6 3C72P9 P72P9 MICROCONTROLLER xiii List of Tables Table Title Page Number Number 1 1 S3C72P9 P72P9 Pin 1 5 1 2 Overview of S3C72P9 P72P9 Pin 1 7 2 1 Program Memory Address Ranges seen 2 1 2 2 Data Memory Organization and Addressing 2 2 2 10 2 3 Working Register Organization and 2 12 2 4 BSC Register Organization sees nne 2 18 2 5 Program Status Word Bit Descriptions sese 2 19 2 6 Interrupt Status Flag Bit Settings 2 20 2 7 Valid Carry Flag Manipulation 2 23 3 1 RAM Addressing Not Affected by the 3 4 3 2 1 Bit Direct and Indirect RAM Addressing esee 3 6 3 3 4 Bit Direct and Indirect RAM 0 3 9 3 4 8 Bit Direct and Indirect RAM Addressing eee 3 13 4 1 Map for Memory Bank 15 4 2 5 1 Valid 1 Byte Instruction Combinations for REF Look UPS 5 2 5 2 Bit Addressing Modes and 5
114. 9 Preliminary Spec SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 P9 3 SEG40 P9 2 SEG41 P9 1 SEG42 P9 0 SEG43 P8 3 SEG44 P8 2 SEG45 P8 1 SEG46 P8 0 SEG47 P7 3 SEG48 P7 2 SEG49 P7 1 SEG50 P7 0 SEG51 P6 3 SEG52 K7 P6 2 SEG53 K6 P6 1 SEG54 K5 S3C72P9 P72P9 Preliminary Spec PRODUCT OVERVIEW PIN DESCRIPTIONS Table 1 1 53C72P9 P72P9 Pin Descriptions 4 bit I O port 11 SCK KO 1 bit and 4 bit read write and test are possible 12 SO K1 Individual pins are software configurable as input or 13 SI K2 output 14 BUZ K3 Individual pins are software configurable as open drain or push pull output 4 bit pull up resistors are software assignable pull up resistors are automatically disabled for output pins 4 bit input port 1 bit and 4 bit read and test are possible 4 bit pull up resistors are assignable by software Same as port 0 except that port 2 is 3 bit I O port Same as port 0 4 0 4 3 4 bit I O ports 1 4 bit or 8 bit read write and test are possible Individual pins are software configurable as input or output 4 bit pull up resistors are software assignable pull up resistors are automatically disabled for output pins Same as P4 P5 SEG55 K4 SEG52 K7 SEG51 SEG48 Same as P4 P5 SEG47 SEG44 SEG43 SEG40 Serial I O interface clock signal 11 P0 0 K0 5 0 5 3 6 0 6 3 7 0 7 3 8 0 8 3 9 0
115. 9 P72P9 Preliminary Spec S Programming Tip Example of The Instruction Redundancy Effect ABC ORG LD ORG 0020H EA 30H 0080H EA 40H ABC ABC EA 50H Stored in REF instruction reference area Redundancy effect is encountered skip EA lt 30 EA lt 30 Skip ELECTRONICS S3C72P9 P72P9 Preliminary Spec SAM47 INSTRUCTION SET FLEXIBLE BIT MANIPULATION In addition to normal bit manipulation instructions like set and clear the SAM47 instruction set can also perform bit tests bit transfers and bit Boolean operations Bits can also be addressed and manipulated by special bit addressing modes Three types of bit addressing are supported mema b memb L H DA b The parameters of these bit addressing modes are described in more detail in Table 5 2 Table 5 2 Bit Addressing Modes and Parameters Addressing Mode Addressable Peripherals Address Range mema b ERB 151 150 IEx IRQx FBOH FBFH memb ImmbQL BSCx Ports 00000 Ports sd FFFH H DA b All bit manipulatable peripheral hardware All bits of the memory bank specified by EMB and SMB that are bit manipulatable NOTE Some devices in the SAM47 product family don t have BSC INSTRUCTIONS WHICH HAVE SKIP CONDITIONS The following instructions have a skip function when an overflow or borrow occurs XCHI INCS XCHD DECS LDI ADS LDD SBS If there is an overflow or borrow from the result
116. COUNTER FUNCTION Timer counter 1 can be programmed to generate interrupt requests at variable intervals based on the system clock frequency you select The 8 bit TC1 mode register TMOD1 is used to activate the timer counter and to select the clock frequency the 16 bit reference register TREF1 is used to store the value for the desired number of clock pulses between interrupt requests The 16 bit counter register TCNT1 counts the incoming clock pulses which are compared to the TREF1 value When there is a match an interrupt request is generated To program timer counter 1 to generate interrupt requests at specific intervals select one of the four internal clock frequencies divisions of the system clock fxx and load a counter reference value into the TREF1 register TCNT1 is incremented each time an internal counter pulse is detected with the reference clock frequency specified by TMOD 1 4 TMOD 1 6 settings To generate an interrupt request the TC1 interrupt request flag IRQT1 is set to logic one the status of is inverted and the interrupt is output The content of TCNT1 is then cleared to OOOOH and TC1 continues counting The interrupt request mechanism for TC1 includes an interrupt enable flag IET1 and an interrupt request flag IRQT1 TC1 TIMER COUNTER OPERATION SEQUENCE The general sequence of operations for using TC1 can be summarized as follows Set TMOD1 2 to 1 to enable TC1 Set TMOD1 6 to 1 to enable t
117. ERRUPT FLAGS There are three types of interrupt flags interrupt request and interrupt enable flags that correspond to each interrupt the interrupt master enable flag which enables or disables all interrupt processing Interrupt Master Enable Flag IME The interrupt master enable flag IME enables or disables all interrupt processing Therefore even when an IRQx flag is set and its corresponding IEx flag is enabled the interrupt service routine is not executed until the IME flag is set to logic one The IME flag is located in the IPR register IPR 3 It can be directly be manipulated by El and DI instructions regardless of the current value of the enable memory bank flag EMB Inhibit all interrupts Enable all interrupts Interrupt Enable Flags IEx IEx flags when set to logical one enable specific interrupt requests to be serviced When the interrupt request flag is set to logical one an interrupt will not be serviced until its corresponding IEx flag is also enabled Interrupt enable flags can be read written or tested directly by 1 bit instructions IEx flags can be addressed directly at their specific RAM addresses despite the current value of the enable memory bank EMB flag Table 7 7 Interrupt Enable and Interrupt Request Flag Addresses ms sm meo 9 Ew mw _ ram e e me __ ram e e s me ren e ma mm rm o e ee mm NOT
118. ES 1 IEx refers to all interrupt enable flags 2 IRQx refers to all interrupt request flags 3 IEx 0 is interrupt disable mode 4 IEx 2 1 is interrupt enable mode ELECTRONICS 7 13 INTERRUPTS S3C72P9 P72P9 Preliminary Spec Interrupt Request Flags IRQx Interrupt request flags are read write addressable by 1 bit or 4 bit instructions IRQx flags can be addressed directly at their specific RAM addresses regardless of the current value of the enable memory bank EMB flag When a specific IRQx flag is set to logic one the corresponding interrupt request is generated The flag is then automatically cleared to logic zero when the interrupt has been serviced Exceptions are the watch timer interrupt request flags IRQW and the external interrupt 2 flag IRQ2 which must be cleared by software after the interrupt service routine has executed IRQx flags are also used to execute interrupt requests from software In summary follow these guidelines for using IRQx flags 1 IRQxis set to request an interrupt when an interrupt meets the set condition for interrupt generation 2 1 set to 1 by hardware and then cleared by hardware when the interrupt has been serviced with the exception of IRQW and 1802 3 When IRQx is set to 1 by software an interrupt is generated When two interrupts share the same service routine start address interrupt processing may occur in one of two ways When only one interrupt is enabled
119. ES STEST BTSTZ IRQS JR STEST LD EA SBUF SMB 0 LD RDATA EA ELECTRONICS 13 5 SERIAL INTERFACE S3C72P9 P72P9 Preliminary Spec PROGRAMMING Setting Transmit Receive Modes for Serial I O Continued 3 Transmit and receive an internal clock frequency of 4 09 kHz at 4 19 MHz in LSB first mode BITS EMB SMB 15 LD EA 03H LD PMG1 EA LD EA 87H LD SMOD EA P0 0 SCK 1 50 lt Output PO 2 SI lt Input LD EA TDATA LD SBUF EA BITS SMOD 3 SIO start EI BITS IES INTS PUSH SB Store SMB SRB PUSH EA Store EA LD EA TDATA EA lt Transmit data SMB 15 XCH EA SBUF EA lt Receive data SMB 0 LD RDATA EA RDATA lt Receive data BITS SMOD 3 SIO start POP EA POP SB IRET SCK PO 0 External SO PO 1 2 Device S3C72P9 13 6 ELECTRONICS S3C72P9 P72P9 Preliminary Spec SERIAL I O INTERFACE 58 PROGRAMMING Setting Transmit Receive Modes for Serial I O Continued 4 Transmit and receive an external clock in LSB first mode INTS BITS SMB LD LD LD LD LD LD BITS EI BITS PUSH PUSH LD SMB XCH SMB LD BITS POP POP IRET EMB 15 EA 02H PMG1 EA EA 07H SMOD EA EA TDATA SBUF EA SMOD 3 IES SB EA EA TDATA 15 EA SBUF 0 RDATA EA SMOD 3 EA SB SCK PO 0 SO PO 1 SI P0 2 S3C72P9 ELECTRONICS P0 1 SO lt Output 0 SCK and 2 51 lt Input SIO start Store SMB SRB Store EA EA lt
120. Flags n 4 12 IES IRQS INTS Interrupt Enable Request Flags 4 13 IETO IRQTO INTTO Interrupt Enable Request 4 14 IET1 IRQT1 INTT1 Interrupt Enable Request 4 15 IEK IRQTK Interrupt Enable Request Flags 4 15 IEW IRQW INTW Interrupt Enable Request Flags 4 16 IMODO External Interrupt 0 INTO Mode 4 17 IMOD1 External Interrupt 1 INT1 Mode 4 18 IMOD2 External Interrupt 2 INT2 Mode 4 19 IMODK External Key Interrupt Mode Register see 4 20 IPR Interrupt Priority 4 21 3 72 9 72 9 MICROCONTROLLER xxi List of Register Descriptions Continued Register Full Register Name Page Identifier Number LCNST LCD Contrast Control 4 22 LCON LCD Output Control Register sene 4 23 LMOD LGD Mode Register n cete e t dea 4 24 PCON Power Control 4 25 PMG1 Port I O Mode Flags Grou
121. G3 SEG1 VLC5 VLC3 VLC1 P0 1 SO K1 PO 3 BUZ KS Vss XIN XTIN RESET P1 1 INT1 1 4 P2 1 LCDCK P3 0 TCLOO P3 2 TCLO COMO COM2 COM6 P4 0 COM8 P4 2 COM10 P5 0 COM12 P5 2 COM14 P6 0 SEG55 K4 P6 1 SEG54 K5 P6 3 SEG52 K7 P7 1 SEG50 P7 3 SEG48 P8 1 SEG46 P8 3 SEG44 P9 1 SEG42 P9 3 SEG40 SEG38 SEG36 SEG34 SEG32 SEG30 SEG28 SEG26 SEG24 SEG22 SEG20 SEG18 SEG16 SEG14 SEG12 SEG10 SEG8 SEG6 S3C72P9 P72P9 Preliminary Spec Figure 17 3 50 Pin Connectors for TB72P9 Target Board J101 2 49 50 J102 Target Cable for 50 Pin Connector Part Name AS50D A Order Cods SM6305 40JD9UUOD 09 Target System J102 J101 1 49 5 2 0 Figure 17 4 TB72P9 Adapter Cable for 100 QFP Package S3C72P9 JOJNSUUOD 09 P6 2 SEG53 K6 P7 0 SEG51 P7 2 SEG49 P8 0 SEG47 P8 2 SEG45 P9 0 SEG43 P9 2 SEG41 SEG39 SEG37 SEG35 SEG33 SEG31 SEG29 SEG27 SEG25 SEG23 SEG21 SEG19 SEG17 SEG15 SEG13 SEG11 SEG9 SEG7 SEG5 ELECTRONICS S3C72P9 P72P9 Preliminary Spec DEVELOPMENT TOOLS DEVELOPMENT TOOLS OVERVIEW Samsung provides a powerful and easy to use development support system in turnkey form The development support system is configured with a host system debugging tools and support software For the host system any standard computer that operates with MS DOS as its operating system can be used One type of debugging tool includi
122. H 1000H Jump to address 1000H and execute JPS AAA Address lt A EA lt 00H Jump to address 1100H Address 30H lt 00H EA 01H were to be executed in place of LD EA 00H the program would jump to 1101H and address 30H would contain the value 1H If LD EA 02H were to be executed the jump would be to 1102H and address 30H would contain the value 2H ELECTRONICS 5 61 SAM47 INSTRUCTION SET S3C72P9 P72P9 Preliminary Spec LCALL Long Call Procedure CALL Operation Description Example LCALL 5 62 dst Opend Operation Summary Bytes ADR15 Call direct in page 15 bits CALL calls a subroutine located at the destination address The instruction adds three to the program counter to generate the return address and then pushes the result onto the stack decrementing the stack pointer by six The EMB and ERB are also pushed to the stack Program execution continues with the instruction at this address The subroutine may therefore begin anywhere in the full 32 Kbyte program memory address space The LCALL instruction can be used in the all range 0000H 7FFFH while the CALL instruction can be used the only range 0000H 3FFFH operand Binary Code operation Notation ADR15 1 1 0 1 1 0 11 0 ISP 1 SP 3 lt ERB Cv su sis sz an wo isa tora 5 The stack po
123. I 5 Oscillation Oscillation Resumes Signal Figure 8 3 Timing When Stop Mode is Released by RESET Oscillator Stabilization Wait Time Stop BMOD Setting Instruction Mode 4 INT ACK IME 1 Release signal Normal Mode Stop mode Idle Mode Normal Mode s f AA A lt Oscillation uu Clock Oscillation Resumes Signal Figure 8 4 Timing When Stop Mode is Released by an Interrupt ELECTRONICS 8 5 POWER DOWN S3C72P9 P72P9 Preliminary Spec PROGRAMMING Reducing Power Consumption for Key Input Interrupt Processing The following code shows real time clock and interrupt processing for key inputs to reduce power consumption In this example the system clock source is switched from the main system clock to a subsystem clock and the LCD display is turned on KEYCLK DI CALL SMB LD LD LD LD SMB BITR BITR BITS BITS CLKS1 CALL BTSTZ JR CALL subroutine EI RET CIDLE IDLE NOP NOP JPS 8 6 MA2SUB 15 EA 00H P4 EA A 3H IMODK A 0 IRQW IRQK IEW IEK WATDIS IRQK CIDLE SUB2MA CLKS1 Main system clock subsystem clock switch subroutine All key strobe outputs to low level Select K0 K7 enable Execute clock and display changing subroutine Subsystem clock main system clock switch Engage idle mode ELECTRONICS 3 72 9 72 9 Preliminary Spec POWER DOWN RECOMMENDED CONNECTIONS FOR UNUSED PINS To reduce overall power
124. IRQS flag is retained when serial transmission is completed Enable the data shifter and clock counter The IRQS flag is set to logic one when serial transmission is completed SMOD 1 Serial I O Transmission Mode Selection Bit Receive only mode Transmit and receive mode SMOD 0 LSB MSB Transmission Mode Selection Bit lo Transmit the most significant bit MSB first Transmit the least significant bit LSB first ELECTRONICS 4 37 MEMORY MAP 3 72 9 72 9 Preliminary Spec TMODO rimer Counter 0 Mode Register T CO F91H F90H Bit y 6 5 4 3 2 1 0 RESET Value 0 0 0 0 0 0 0 0 Read Write W W W W W W W W Bit Addressing 8 8 8 8 1 8 8 8 8 TMODO 7 Bit 7 EN Always logic zero TMODO 6 4 Timer Counter 0 Input Clock Selection Bits 9 9 External clock input at TCLO pin on rising edge olola External clock input at TCLO pin on falling edge 210 4 09 kHz 26 65 5 kHz EJEDES fxx 24 262 kHz fxx 4 19 MHz NOTE is selected system clock of 4 19 MHz TMODO 3 Clear Counter and Resume Counting Control Bit 1 Clear TCNTO IRQTO and TOLO and resume counting immediately This bit is cleared automatically when counting starts TMODO 2 Enable Disable Timer Counter 0 Bit IS Disable timer counter 0 retain TCNTO contents Enable timer counter 0 TMODO 1 Bit 1 E Always logic zero TMODO 0 Bit 0 4 38 Always logic zero ELECTRONICS S3C72P9 P72P9
125. L 0FOH 30 REF AQ LD HL 067H 31 REF A10 CALL SUB1 32 REF 11 SUB2 ELECTRONICS 5 81 SAM47 INSTRUCTION SET S3C72P9 P72P9 Preliminary Spec RET Return from Subroutine RET jmwsmnshme OOOO Description RET pops the PC values successively from the stack incrementing the stack pointer by six Program execution continues from the resulting address generally the instruction immediately following a CALL LCALL or CALLS a Tes lt SP 1 SP PC7 0 lt SP 3 SP42 EMB ERB lt 5 5 SP 4 SP lt SP 6 Example The stack pointer contains the value OFAH RAM locations OFAH OFBH OFCH and OFDH contain 1H OH 5H and 2H respectively The instruction RET leaves the stack pointer with the new value of 00H and program execution continues from location 0125H During a return from subroutine PC values are popped from stack locations as follows SP gt PC11 PC8 SP 1 o PC14 PC13 12 SP 2 PC3 PCO SP 3 4 5 6 5 82 ELECTRONICS S3C72P9 P72P9 Preliminary Spec SAM47 INSTRUCTION SET RRC Rotate Accumulator Right through Carry RRC A Description four bits in the accumulator and the flag are together rotated one bit to the right Bit 0 moves into the carry flag and the original carry value moves into the bit 3 accumulator position A 1 1 C A 0 A3 C A n 1 n 1 2 3 Example The accumulator cont
126. LCD segment signal pins are connected to corresponding display RAM locations at bank 2 Bits of the display RAM are synchronized with the common signal output pins When the bit value of a display RAM location is 1 a select signal is sent to the corresponding segment pin When the display bit is 0 a no select signal is sent to the corresponding segment pin 12 10 ELECTRONICS S3C72P9 P72P9 Preliminary Spec LCD CONTROLLER DRIVER BG comz Bl J I coms UR come OOOO coms 0 12 l Figure 12 6 LCD Signal Waveforms 1 16 Duty 1 5 Bias ELECTRONICS 12 11 LCD CONTROLLER DRIVER S3C72P9 P72P9 Preliminary Spec SEGO COMO SEG1 COMO Figure 12 6 LCD Signal Waveforms 1 16 Duty 1 5 Bias Continued 12 12 ELECTRONICS S3C72P9 P72P9 Preliminary Spec LCD CONTROLLER DRIVER BE com 0 1 2 3 4 5 6 7 0 1 2 3 4 5 61 7 comz BI IL coms OO 1 5 come 6 gt 1 Frame VDD VLC1 VLC2 VLC3 Vics OOO ILLUS somo E a n S F G 2 VDD VLC1 VLC3 Vics VDD VLC2 VLC3 Vics VDD VLC1 VLC3 Vics VDD VLC1 VLC2 VLC3 0
127. NTB VENT2 0 1 INTO EMB lt 0 ERB lt 1 Jump to INTO address by INTO VENTS 0 1 INT1 EMB lt 0 ERB lt 1 Jump to INT1 address by INT1 VENTA 0 1 INTS EMB lt 0 ERB lt 1 Jump to INTS address by INTS VENT5 0 1 INTTO EMB lt 0 ERB lt 1 Jump to INTTO address by INTTO VENT6 0 1 INTT1 EMB lt 0 ERB lt 1 Jump to INTT1 address by INTT1 VENT7 0 1 INTK lt 0 ERB lt 1 Jump to INTK address by RESET BITR EMB ELECTRONICS 3 3 ADDRESSING MODES S3C72P9 P72P9 Preliminary Spec ENABLE MEMORY BANK SETTINGS EMB 1 When the enable memory bank flag EMB is set to logic one you can address the data memory bank specified by the select memory bank SMB value 0 1 2 3 4 or 15 using 1 4 or 8 bit instructions You can use both direct and indirect addressing modes The addressable RAM areas when EMB 1 are as follows If SMB 0 000H 0FFH If SMB 1 100H 1FFH If SMB 2 200H 2FFH If SMB 3 300H 3FFH If SMB 4 400H 4FFH If SMB 15 F80H FFFH EMB 0 When the enable memory bank flag EMB is set to logic zero the addressable area is defined independently of the SMB value and is restricted to specific locations depending on whether a direct or indirect address mode is used If 0 the addressable area is restricted to locations 000H 07FH in bank 0 and to locations in bank 15 for direct addressing For indirect addressing only locations 000
128. O L Sd 47 pLNOD e Sd C4 87 SLAOO Sd C4 67 99 045 0 09 The bolds indicate an OTP pin Figure 16 1 S3P72P9 Pin Assignments 100 QFP Package 16 2 ELECTRONICS 3 72 9 72 9 Preliminary Spec S3P72P9 OTP Table 16 1 Descriptions of Pins Used to Read Write the EPROM Main Chip During Programming 2 SDAT Serial data pin Output port when reading and input port when writing Can be assigned as a Input push pull output port TEST V pp TEST Power supply pin for EPROM cell writing indicates that OTP enters into the writing mode When 12 5 V is applied OTP is in writing mode and when 5 V is applied OTP is in reading mode Option RESET RESET Chip initialization Logic power supply pin Vpp should be tied to 5 V during programming Table 16 2 Comparison of S3P72P9 and S3C72P9 Features Program Memory 16 KByte EPROM 16 KByte mask ROM Operating Voltage V 1 8 V to 55V 1 8 V to 55V DD OTP Programming Mode 5 V Vpp TEST 12 5V EE Pin Configuration 100 QFP 100 QFP EPROM Programmability User Program 1 time Programmed at the factory OPERATING MODE CHARACTERISTICS When 12 5 V is supplied to the Vpp TEST pin of the S3P72P9 the EPROM programming mode is entered The operating mode read write or read protection is selected according to the input signals to the pins listed in Table 16 3 below Table 16 3 Operating Mode Selection Criteria Address A15
129. OLLER List of Figures Continued Figure Title Page Number Number 13 1 Serial I O Interface Circuit 13 2 13 2 SIO Timing Transmit Receive 13 4 13 3 SIO Timing Receive Only 13 4 14 1 Standard Operating Voltage 14 9 14 2 Stop Mode Release Timing When Initiated by RESET 14 11 14 3 Stop Mode Release Timing When Initiated by Interrupt Request 14 11 14 4 A C Timing Measurement Points Except for Xi and 14 12 14 5 Clock Timing Measurement at enn nennen 14 12 14 6 Clock Timing Measurement at XT sss 14 12 14 7 TOL Timing e et dt ut dme 14 13 14 8 Input Timing for RESET nennen 14 13 14 9 Input Timing for External Interrupts and 14 13 14 10 Serial Data Transfer Timing enne 14 14 15 1 100 QFP 1420C Package Dimensions eene 15 2 16 1 S3P72P9 Pin Assignments 100 QFP Package 16 2 16 2 Standard Operating Voltage Range seen 16 5 17 1 SMDS Product Configuration 5 52 17 2 17 2 TB72P9 Target Board 1
130. Output external TCLO clock pulse to the TCLOO pin divided by four External TCLO Clock Pulse TCLOO Output Pulse BITS EMB SMB 15 LD EA 01H LD TREFO EA LD EA 0CH LD TMODO EA LD EA 01H LD PMG2 EA P3 0 lt output mode BITR P3 0 P3 0 clear BITS TOEO 11 16 ELECTRONICS S3C72P9 P72P9 Preliminary Spec TIMERS and TIMER COUNTERS TCO MODE REGISTER TMODO TMODO is the 8 bit mode control register for timer counter O It is addressable by 8 bit write instructions One bit TMODO 3 is also 1 bit writeable RESET clears all TMODO bits to logic zero and disables TCO operations TMODO 2 is the enable disable bit for timer counter 0 When TMODO 3 is set to 1 the contents of TCNTO IRQTO and TOLO are cleared counting starts from 00H and TMODO 3 is automatically reset to 0 for normal TCO operation When TCO operation stops TMODO 2 0 the contents of the TCO counter register TCNTO are retained until TCO is re enabled The TMODO 6 TMODO 5 and TMOD0 4 bit settings are used together to select the TCO clock source This selection involves two variables Synchronization of timer counter operations with either the rising edge or the falling edge of the clock signal input at the TCLO pin and Selection of one of four frequencies based on division of the incoming system clock frequency for use in internal TCO operation Table 11 6 TCO Mode Register TMODO Organization Resulting TCO Function Always
131. P72P9 Preliminary Spec INSTRUCTION CYCLE TIMES OSCILLATOR CIRCUITS The unit of time that equals one machine cycle varies depending on whether the main system clock fx or a subsystem clock fxt is used and on how the oscillator clock signal is divided by 4 8 or 64 Table 6 2 shows corresponding cycle times in microseconds Table 6 2 Instruction Cycle Times for CPU Clock Rates Selected Resulting Frequency Oscillation Cycle Time usec CPU Clock Source fx 8 524 0 kHz fx 4 19 MHz fxt 4 8 19 kHz fxt 32 768 kHz 122 0 ELECTRONICS 6 5 OSCILLATOR CIRCUITS S3C72P9 P72P9 Preliminary Spec SYSTEM CLOCK MODE REGISTER SCMOD The system clock mode register SCMOD is a 4 bit register that is used to select the CPU clock and to control main and sub system clock oscillation The SCMOD is mapped to the RAM address FB7H The main clock oscillation is stopped by setting SCMOD 3 when the clock source is subsystem clock and subsystem clock can be stopped by setting SCMOD 2 when the clock source is main system clock SCMOD 0 SCMOD 3 cannot be simultaneously modified The subsystem clock is stopped only by setting SCMOD 2 and PCON which revokes stop mode cannot stop the subsystem clock The stop of subsystem clock is released by RESET when the selected system clock is main system clock or subsystem clock and is released by setting SCMOD 2 when the selected system clock is main System clock RESET clears all SCMOD values to
132. P72P9 Preliminary Spec TCO SERIAL I O CLOCK GENERATION Timer counter 0 can supply a clock signal to the clock selector circuit of the serial interface for data shifter and clock counter operations These internal SIO operations are controlled in turn by the SIO mode register SMOD This clock generation function enables you to adjust data transmission rates across the serial interface Use TMODO and TREFO register settings to select the frequency and interval of the TCO clock signals to be used as SCK input to the serial interface The generated clock signal is then sent directly to the serial I O clock selector circuit the TOEO flag may be disabled TCO EXTERNAL INPUT SIGNAL DIVIDER By selecting an external clock source and loading a reference value into the TCO reference register TREFO you can divide the incoming clock signal by the TREFO value and then output this modified clock frequency to the TCLOO pin The sequence of operations used to divide external clock input can be summarized as follows 1 Load a signal divider value to the TREFO register Clear TMODO 6 to 0 to enable external clock input at the TCLO pin Set TMODO 5 and TMODO 4 to desired TCLO signal edge detection Set port 3 0 mode flag PM3 0 to output 1 Set P3 0 output latch to O Set TOEO flag to 1 to enable output of the divided frequency to the TCLOO pin oa fF 59 PROGRAMMING External TCLO Clock Output to the TCLOO Pin
133. P9 1 SEG42 P9 3 SEG40 SEG38 SEG36 SEG34 SEG32 SEG30 SEG28 SEG26 SEG24 SEG22 SEG20 SEG18 SEG16 SEG14 SEG12 SEG10 SEG8 SEG6 S3C72P9 P72P9 Preliminary Spec Figure 17 3 50 Pin Connectors for TB72P9 Target Board J101 2 49 50 J102 Target Cable for 50 Pin Connector Part Name AS50D A Order Cods SM6305 40JD9UUOD 09 Target System J102 J101 1 49 5 2 0 Figure 17 4 TB72P9 Adapter Cable for 100 QFP Package S3C72P9 JOJNSUUOD 09 P6 2 SEG53 K6 P7 0 SEG51 P7 2 SEG49 P8 0 SEG47 P8 2 SEG45 P9 0 SEG43 P9 2 SEG41 SEG39 SEG37 SEG35 SEG33 SEG31 SEG29 SEG27 SEG25 SEG23 SEG21 SEG19 SEG17 SEG15 SEG13 SEG11 SEG9 SEG7 SEG5 ELECTRONICS
134. PC14 PC13 PC12 PCO 7 PC4 ELECTRONICS S3C72P9 P72P9 Preliminary Spec SAM47 INSTRUCTION SET CCF Complement Carry Flag CCF Description carry flag is complemented if C 1 it is changed to C 0 and vice versa __ 1 Example If the carry flag is logic zero the instruction CCF changes the value to logic one ELECTRONICS 5 49 SAM47 INSTRUCTION SET S3C72P9 P72P9 Preliminary Spec COM Complement Accumulator COM A Operation Operand Operation Summary Bytes Cycles Description accumulator value is complemented if the bit value of A is 1 it is changed to and vice versa ACA EZEXEHESKSESENEN Example If the accumulator contains the value 4H 0100B the instruction COM A leaves the value OBH 1011B in the accumulator 5 50 ELECTRONICS S3C72P9 P72P9 Preliminary Spec SAM47 INSTRUCTION SET CPSE Compare and Skip if Equal CPSE dst src Operation Operand Operation Summary Bytes Compare and skip if register equals im HL im Compare and skip if indirect data memory equals im A HL Compare and skip if A equals indirect data memory EA HL Compare and skip if EA equals indirect data memory EA RR Compare and skip if EA equals RR 228 4 Description CPSE compares the source operand subtracts it from the destination operand and skips the next instruction if the values
135. QT1 INTT1 Interrupt Request Flag ELECTRONICS Generate INTT1 interrupt This bit is set and cleared automatically by hardware when contents of TCNT1 and TREF1 registers match 4 1 MEMORY MAP S3C72P9 P72P9 Preliminary Spec IEW IRQW intw Interrupt Enable Request Flags CPU FBAH Bit 3 2 1 0 RESET Value 0 0 0 0 Read Write R W R W R W R W Bit Addressing 1 4 1 4 1 4 1 4 3 2 Bits 3 2 Ea Always logic zero IEW INTW Interrupt Enable Flag Disable INTW interrupt requests 1 Enable INTW interrupt requests IRQW INTW Interrupt Request Flag Generate INTW interrupt This bit is set when the timer interval is set to 0 5 seconds or 3 91 milliseconds NOTE Since INTW is a quasi interrupt the IRQW flag must be cleared by software 4 16 ELECTRONICS 3 72 9 72 9 Preliminary Spec MEMORY MAP IMODO External Interrupt 0 INTO Mode Register CPU FB4H Bit 3 2 1 0 RESET Value 0 0 0 0 Read Write Bit Addressing 4 4 4 4 IMODO 3 2 Bits 3 2 Always logic zero IMODO 1 0 External Interrupt Mode Control Bits Interrupt request is triggered by a rising signal edge nterrupt request is triggered by falling signal edge Interrupt request is triggered by both rising and falling signal edges Interrupt request flag IRQO cannot be set to logic one ELECTRONICS 4 17 MEMORY MAP S3C72P9 P72P9 Preliminary Spec IMOD1 External Interrupt 1 INT1 Mode Register CPU FB5H Bit 3 2 1 0
136. S3P72P9 OTP OVERVIEW The S3P72P9 single chip CMOS microcontroller is the OTP One Time Programmable version of the S3C72P9 microcontroller It has an on chip OTP ROM instead of masked ROM The EPROM is accessed by serial data format S3P72P9 is fully compatible with the S3C72P9 both in function and in pin configuration Because of its simple programming requirements the S3P72P9 is ideal for use as an evaluation chip for the S3C72P9 ELECTRONICS 16 1 S3P72P9 OTP 3 72 9 72 9 Preliminary Spec 00 99035 96 5 01935 v6 EA 11995 06 r3 31035 68 91045 88 Fy 41935 48 81035 98 61935 68 r3 22045 c8 Eq 22935 18 Fo veoas 4 SEG2 5 SEGO VLC5 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 VLC3 SEG32 VLC2 SEG33 VLC1 SEG34 P0 0 S CK KO SEG35 P0 1 SO K1 SEG36 SDAT P0 2 SI K2 SEG37 SCLK P0 3 BUZ K3 SEG38 VDD VDD S3P72P9 SEG39 Vss Vss P9 3 SEG40 XOUT 100 QFP 1420C P9 2 SEG41 XIN P9 1 SEG42 VPP TEST P9 0 SEG43 XTIN P8 3 SEG44 XT ouT P8 2 SEG45 RESETRESET P8 1 SEG46 P1 0 INTO P8 0 SEG47 P1 1 INT1 P7 3 SEG48 P1 2 INT2 P7 2 SEG49 P1 3 INT4 P7 1 SEG50 P2 0 CLO P7 0 SEG51 P2 1 LCDCK P6 3 SEG52 K7 P2 2 LCDSY P6 2 SEG53 K6 P3 0 TCLOO P6 1 SEG54 K5 C4 26 L10L d EE 8 NOO 0 vd 27 6 OO L vd 87 5 HE vd 77 LLNOOD E td 97 0 97 1INO
137. SB 2 0 EA 00H 80H EA HL 40H HL WX EA YZ EA SB lt 1 lt 1 Jump to INTO address Store current SMB SRB Select register bank 2 because of ERB 1 Restore SMB SRB ELECTRONICS 3 72 9 72 9 Preliminary Spec ADDRESS SPACES STACK OPERATIONS STACK POINTER SP The stack pointer SP is an 8 bit register that stores the address used to access the stack an area of data memory set aside for temporary storage of data and addresses The SP can be read or written by 8 bit control instructions When addressing the SP bit 0 must always remain cleared to logic zero F80H SP3 SP2 sa vw F81H SP7 SP6 SP5 SP4 There are two basic stack operations writing to the top of the stack push and reading from the top of the stack pop A push decrements the SP and a pop increments it so that the SP always points to the top address of the last data to be written to the stack The program counter contents and program status word are stored in the stack area prior to the execution of a CALL or a PUSH instruction or during interrupt service routines Stack operation is a LIFO Last In First Out type The stack area is located in general purpose data memory bank 0 During an interrupt or a subroutine the PC value and the PSW are saved to the stack area When the routine has completed the stack pointer is referenced to restore the PC and PSW and the next instruction is executed The SP can
138. Sub system Clock fx 128 fw Watch Timer Frequency Figure 11 6 Watch Timer Circuit Diagram 11 36 ELECTRONICS S3C72P9 P72P9 Preliminary Spec TIMERS and TIMER COUNTERS WATCH TIMER MODE REGISTER WMOD The watch timer mode register WMOD is used to select specific watch timer operations It is 8 bit write only addressable An exception is WMOD bit the XT y input level control bit which is 1 bit read only addressable A RESET automatically sets WMOD 3 to the current input level of the subsystem clock XT jy high if logic one low if logic zero and all other WMOD bits to logic zero In summary WMOD settings control the following watch timer functions Watch timer clock selection WMOD 0 Watch timer speed control WMOD 1 Enable disable watch timer WMOD 2 XTyinput level control WMOD 3 Buzzer frequency selection WMOD 4 and WMOD 5 Enable disable buzzer output WMOD 7 Table 11 12 Watch Timer Mode Register WMOD Organization Values Address WMOD 7 Disable buzzer BUZ signal output at the BUZ pin F89H 1 Enable buzzer BUZ signal output at the BUZ pin WMOD 6 Always logic zero offo 2 kHz buzzer BUZ signal output ofa 4 kHz buzzer BUZ signal output afo 8 kHz buzzer BUZ signal output 16 kHz buzzer BUZ signal output 1 1 1 Normal mode sets IRQW to 0 5 seconds WMOD 1 Mud High speed mode sets IRQW to 3 91 ms WMOD 0 Select fx 128 as the watch ti
139. TO address INTS VENT6 0 0 INTT1 lt 0 ERB lt 0 Jump to INTT1 address by INTTO VENT7 0 0 INTK lt 0 ERB lt 0 Jump to INTK address by INTT1 ORG 0010H General purpose ROM area In this example when an INTS interrupt is generated the corresponding vector area is not VENT4 INTS but VENT5 INTTO This causes an INTS interrupt to jump incorrectly to the INTTO address and causes a CPU malfunction to occur 2 4 ELECTRONICS 3 72 9 72 9 Preliminary Spec ADDRESS SPACES INSTRUCTION REFERENCE AREA Using 1 byte REF instructions you can easily reference instructions with larger byte sizes that are stored in ad dresses 0020H 007FH of program memory This 96 byte area is called the REF instruction reference area or look up table Locations in the REF look up table may contain two 1 byte instructions one 2 byte instruction or one 3 byte instruction such as a JP jump or CALL The starting address of the instruction you are referencing must always be an even number To reference a JP or CALL instruction it must be written to the reference area in a two byte format for JP this format is TJP for CALL it is TCALL In summary there are three ways to the REF instruction By using REF instructions you can execute instructions larger than one byte In summary there are three ways you can use the REF instruction Using the 1 byte REF instruction to execute one 2 byte or two 1 byte instructions Branchi
140. TRONICS 4 1 MEMORY MAP S3C72P9 P72P9 Preliminary Spec Table 4 1 Map for Memory Bank 15 Register mw vm gt F87H 2 F8CH LMOD ee me iw 2 wl w ves Locations F8FH is not mapped E WERE E UR ZG UE NE XS Locations F93H is not mapped F94H TONTO coy _ ped eet o v w 3 3e Locations F9BH F9FH are not mapped Locations 2 are not mapped TCNT1A No No Yes TCNT1B 4 2 ELECTRONICS 3 72 9 72 9 Preliminary Spec MEMORY MAP Table 4 1 I O Map for Memory Bank 15 Continued M A TREF1B FABH Locations are not mapped LS 80 ewe me aw Yes E EE PME GE IPR 222 EOM X red vv vw w Ye redd v v v o Ww Ye No ee d Locations FB9H is not mapped rear Jo o mw 8 ram e ma En rm w w sm wan rm o es Locations FCAH FCFH are not mapped ELECTRONICS 4 3 MEMORY MAP S3C72P9 P72P9 Preliminary Spec Table 4 1 I O Map for Memory Bank 15 Continued Register exo uw em
141. The watch timer starts the interrupt request flag IRQW is automatically set to logic one and interrupt requests commence in 0 5 second intervals Since the watch timer functions as a quasi interrupt instead of a vectored interrupt the IRQW flag should be cleared to logic zero by program software as soon as a requested interrupt service routine has been executed Using a Main System or Subsystem Clock Source The watch timer can generate interrupts based on the main system clock frequency or on the subsystem clock When the zero bit of the WMOD register is set to 1 the watch timer uses the subsystem clock signal fxt as its source if WMOD 0 0 the main system clock fx is used as the signal source according to the following formula Main system clock fx Watch timercioceiwy 222 E clock 1 _ 768 kHz fx 4 19 MHz This feature is useful for controlling timer related operations during stop mode When stop mode is engaged the main system clock fx is halted but the subsystem clock continues to oscillate By using the subsystem clock as the oscillation source during stop mode the watch timer can set the interrupt request flag IRQW to 1 thereby releasing stop mode Clock Source Generation for LCD Controller The watch timer supplies the clock frequency for the LCD controller fj Therefore if the watch timer is disabled the LCD controller does not operate 11 34 ELECTRONICS S3C72P9 P72P9 Preliminar
142. Timer dee dined dete eh peed die eect eid 11 7 Using tlie Watchdog terim id 11 9 TGO Signal Output to the Pin 11 15 External TCLO Clock Output to the TCLOO Pin essen eene 11 16 Restarting TCO Counting 11 18 Setting TCO Timer cui hates 11 21 Signal Output to the TCOLO4 11 27 External Clock Output the 2 11 28 Restarting TC Counting Operatlon 11 30 setting a 161 Timer Interval 11 33 Using the Watch Timers io oie 11 38 Chapter 13 Serial I O Interface Setting Transmit Receive Modes for Serial 1 13 5 XX 3 72 9 72 9 MICROCONTROLLER List of Register Descriptions Register Full Register Name Page Identifier Number BMOD Basic Timer Mode 4 8 CLMOD Clock Output Mode Register 41 1 8 4 221 4 9 IEO 1 IRQO 1 INTO 1 Interrupt Enable Request Flags eene 4 10 IE2 IRQ2 INT2 Interrupt Enable Request Flags een 4 11 IE4 IRQ4 INT4 Interrupt Enable Request Flags en 4 12 IEB IRQB INTB Interrupt Enable Request
143. Transmit data EA lt Receive data RDATA lt Receive data SIO start External Device High Speed SIO Transmission SERIAL INTERFACE 52 PROGRAMMING Setting Transmit Receive Modes for Serial Concluded S3C72P9 P72P9 Preliminary Spec Use CPU clock to transfer and receive serial data at high speed STEST BITS SMB LD LD LD LD LD LD BITS BITR BTSTZ JR LD SMB LD EMB 15 EA 03H PMG1 EA EA 47H SMOD EA P0 0 SCK and 1 SO Output 0 2 SI Input EA TDATA SBUF EA SCMOD 3 SIO start IES IRQS STEST EA SBUF 0 RDATA EA ELECTRONICS S3C72P9 P72P9 Preliminary Spec ELECTRICAL DATA OVERVIEW ELECTRICAL DATA In this section information on S3C72P9 electrical characteristics is presented as tables and graphics The information is arranged in the following order Standard Electrical Characteristics Absolute maximum ratings electrical characteristics Main system clock oscillator characteristics Subsystem clock oscillator characteristics capacitance electrical characteristics Operating voltage range Miscellaneous Timing Waveforms A C timing measurement point Clock timing measurement at Clock timing measurement at XT jy TCL timing Input timing for RESET Input timing for external interrupts Serial data transfer timing Stop Mode Characteristics an
144. UT MODE REGISTER CLMOD The clock output mode register CLMOD is a 4 bit register that is used to enable or disable clock output to the CLO pin and to select the CPU clock source and frequency CLMOD is addressable by 4 bit write instructions only RESET clears CLMOD to logic zero which automatically selects the CPU clock as the clock source without initiating clock oscillation and disables clock output CLMOD 3 is the enable disable clock output control bit CLMOD 1 and CLMOD 0 are used to select one of four possible clock sources and frequencies normal CPU clock fxx 8 fxx 16 or fxx 64 Table 6 6 Clock Output Mode Register CLMOD Organization 0 CPU clock fx 4 fx 8 fxt 4 CLMOD 3 Result of CLMOD 3 Setting OOo OE Disable clock output at the CLO pin Enable clock output at the CLO pin NOTE Frequencies assume that fxx fx 4 19 MHz and fxt 32 768 kHz 6 10 ELECTRONICS S3C72P9 P72P9 Preliminary Spec OSCILLATOR CIRCUITS CLOCK OUTPUT CIRCUIT The clock output circuit used to output clock pulses to the CLO pin has the following components 4 bit clock output mode register CLMOD Clock selector Output latch Port mode flag CLO output pin P2 0 CLMOD 3 CLMOD 2 CLMOD 1 Clock Selector P1 2 Output Latch En Clocks fxx 8 fxx 16 fxx 64 CPU clock CLMOD 0 Figure 6 7 CLO Output Pin Circuit Diagram CLOCK OUTPUT PROCEDURE The procedure for outputting clock p
145. VLC5 VLC4 VLc2 VLC3 VLC1 VDD Figure 12 7 LCD Signal Waveforms 1 8 Duty 1 4 Bias ELECTRONICS 12 13 LCD CONTROLLER DRIVER S3C72P9 P72P9 Preliminary Spec 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 FR 1 Frame VDD VLC1 VLC3 VLC5 VDD VLC1 VLC2 VLC3 5 0 VLC5 VLC4 2 VLC3 VDD Figure 12 7 LCD Signal Waveforms 1 8 Duty 1 4 Bias Continued 12 14 ELECTRONICS S3C72P9 P72P9 Preliminary Spec SERIAL I O INTERFACE SERIAL I O INTERFACE OVERVIEW The serial I O interface SIO has the following functional components 8 bit mode register SMOD Clock selector circuit 8 bit buffer register SBUF 3 bit serial clock counter Using the serial I O interface 8 bit data can be exchanged with an external device The transmission frequency is controlled by making the appropriate bit settings to the SMOD register The serial interface can run off an internal or an external clock source or the TOLO signal that is generated by the 8 bit timer counter TCO If the TOLO clock signal is used you can modify its frequency to adjust the serial data transmission rate SERIAL I O OPERATION SEQUENCE The general operation sequence of the serial I O interface be summarized as follows Set SIO mode to transmit and receive or to receive only Select MSB first or LSB first transmission mode Set the SCK clock
146. a atiis 5 59 JR Jump Relative Very 5 60 3 72 9 72 9 MICROCONTROLLER xxiii List of Instruction Descriptions Continued Instruction Full Instruction Name Page Mnemonic Number LCALL Long Call Procedure icit tre reiten ut 5 62 LD Porn 5 63 LDB Evil 5 67 LDC Load Code Byte 5 ne ce che das ipee e pete taire 5 69 LDD Load Data Memory and 5 71 LDI Load Data Memory and 5 72 LJP LONG JUMP E RP rre REN ee ERU e tente d utt 5 73 NOP No Operation iro erri det deu 5 74 OR Logical OB 2 e ehe e bdo tae 5 75 POP Pop From Stack cack ste cect side e t dedu eaae 5 76 PUSH Push Onto Stack 2 Son didi eed ei rtt dud 5 77 RCF Reset Carty aime pr E cite DUE Pepe 5 78 REF Reference InstFUCtOnD 5 79 RET Return form Subroutine 5 82 RRC Rotate Accumulator Right through 5 83 SBC Subtract with Carty sient cheek She ee 5 84 SBS jefe 5 86 SCF Set Carry Flag nci eee ri addet de 5 87 SMB Select Memory Bank eese nennen 5 88 SRB Select Register Bank 5 89 SRET Return From Subroutine and 5 2 5 90 STOP SLOP OPera
147. a powerful and easy to use development support system in turnkey form The development support system is configured with a host system debugging tools and support software For the host system any standard computer that operates with MS DOS as its operating system can be used One type of debugging tool including hardware and software is provided the sophisticated and powerful in circuit emulator SMDS2 for S3C7 S3C8 S3C9 families of microcontrollers The SMDS2 is a new and improved version of SMDS2 Samsung also offers support software that includes debugger assembler and a program for setting options SHINE Samsung Host Interface for In Circuit Emulator SHINE is a multi window based debugger for SMDS2 SHINE provides pull down and pop up menus mouse support function hot keys and context sensitive hyper linked help It has an advanced multiple windowed user interface that emphasizes ease of use Each window can be sized moved scrolled highlighted added or removed completely SAMA ASSEMBLER The Samsung Arrangeable Microcontroller SAM Assembler SAMA is a universal assembler and generates object code in standard hexadecimal format Assembled program code includes the object code that is used for ROM data and required SMDS program control data To assemble programs SAMA requires a source file and an auxiliary definition DEF file with device specific information SASM57 The SASM57 is an relocatable assembler for Samsung
148. after an ADC A QHL instruction even if an overflow occurs JPS XXX ELECTRONICS 5 29 SAM47 INSTRUCTION SET S3C72P9 P72P9 Preliminary Spec AND Logical AND AND dst src Operation oporana Operation Summary eyes Logical AND A immediate data to A Logical AND A indirect data memory to A EA RR Logical AND register pair RR to EA RRb EA Logical AND EA to register pair RRb Description source operand is logically ANDed with the destination operand The result is stored in the destination The logical AND operation results 1 whenever the corresponding bits in the two operands are both 1 otherwise a 0 is stored in the corresponding destination bit The contents of the source are unaffected Operand Binary Code Operation Notation Km ee ar ao aca amy Fo EA anb lt olo RRb EA Example If the extended accumulator contains the value 11000011B and register pair HL the value 55H 01010101 the instruction AND EA HL leaves the value 41H 01000001 in the extended accumulator EA 5 30 ELECTRONICS S3C72P9 P72P9 Preliminary Spec SAM47 INSTRUCTION SET BAND Bit Logical AND BAND C src b Operation Operana Operation Summary Cycles Logical AND carry
149. ains the value 5H 0101B and the carry flag is cleared to logic zero The instruction RRC A leaves the accumulator with the value 2H 0010B and the carry flag set to logic one ELECTRONICS 5 83 SAM47 INSTRUCTION SET S3C72P9 P72P9 Preliminary Spec SBC subtract with Carry SBC dst src A HL Subtract indirect data memory from A with carry EA RR Subtract register pair RR from EA with carry ee RRb EA Subtract EA from register pair RRb with carry Description SBC subtracts the source and carry flag value from the destination operand leaving the result in the destination SBC sets the carry flag if a borrow is needed for the most significant bit otherwise it clears the carry flag The contents of the source are unaffected If the carry flag was set before the SBC instruction was executed a borrow was needed for the previous step in multiple precision subtraction In this case the carry bit is subtracted from the destination along with the source operand Loewe sy core prt ttn 1 9 5 eu o o t 1 1 O peee RRb EA 1 o CRRb lt 2 Examples 1 The extended accumulator contains the value 0C3H register pair HL the value OAAH and the carry flag is set to 1 SCF 3 gt SBE EA HL EA 1H lt 0 JPS XXX Jump to XXX no skip after SBC 2 Ifthe extended accumulator contai
150. alue RCF Ce 0 BOR C P1 0 lf P1 0 1 then C lt 1 if P1 0 0 then C 2 The P1 address is FF1H and register L contains the value 1H 0001B The address memb 7 2 is 111100B and L 3 2 00B The resulting address is 11110000B or FFOH specifying PO The bit value for the BOR instruction L 1 0 is 01B which specifies bit 1 Therefore P1 L 1 LD BOR C P1 L P1 L is specified as P0 1 C ELECTRONICS 5 37 SAM47 INSTRUCTION SET S3C72P9 P72P9 Preliminary Spec BOR Bit Logical OR BOR Examples 5 38 Continued 3 Register H contains the value 2H and FLAG 20H 3 The address of H is 0010B and FLAG 3 0 is 0000B The resulting address is 00100000B or 20H The bit value for the BOR instruction is 3 Therefore H FLAG 20H 3 FLAG EQU 20H 3 LD H 2H BOR C H FLAG FLAG 20H 3 ELECTRONICS S3C72P9 P72P9 Preliminary Spec SAM47 INSTRUCTION SET BTSF Bit Test and Skip on False BTSF dst b Test specified memory bit and skip if bit equals 0 H DA b Description specified bit within the destination operand is tested If it is 0 the BTSF instruction skips the instruction which immediately follows it otherwise the instruction following the BTSF is executed The destination bit value is not affected DA b 4 1 skipitDAb 0 a6 5 ad a2 at a0 m CC Skip if memb
151. am to branch to the basic timer s interrupt service routine INTA and to set the EMB value to 0 and the ERB value to 1 VENT2 then branches to INTB VENTS to INTC and so on setting the appropriate EMB and ERB values NOTE The number of VENTn interrupt names used in the examples above may change for different devices in the SAM47 product family ELECTRONICS 5 93 SAM47 INSTRUCTION SET S3C72P9 P72P9 Preliminary Spec XCH Exchange A or EA with Nibble or Byte XCH dst src Exchange A and data memory contents 2 Exchange A and register Ra contents A RRa Exchange A and indirect data memory 1 EA DA Exchange EA and direct data memory contents EA RRb Exchange EA and register pair RRb contents EA HL Exchange EA and indirect data memory contents Description instruction loads the accumulator with the contents of the indicated destination variable and writes the original contents of the accumulator to the source Binary Code Operation Notation 1 a2 at a0 0 lt gt 1 1 Double register HL contains the address 20H The accumulator contains the value 00111111B and internal RAM location 20H the value 75H 01110101B The instruction EA RRb EA HL 25 a4 Ee ekle a7 a6 25 a4 as
152. and 7 Logic Unit 1 056 x 4 Bit Data lt gt Port 9 Memory Instruction Decoder Instruction Register Program Counter Program Status Word Stack Pointer 32 768 x 8 Bit Program Memory PRODUCT OVERVIEW Watchdog Timer Watch Timer VLC1 VLC5 LCD COMO COM7 Driver P4 0 P4 3 Controller CO8 COM1 1 P5 0 P5 3 COM12 COM15 LCD Contrast Controller SEGO SEG39 P9 3 P6 0 SEG40 SEG55 Port 0 8 Bit Timer Counter 16 Bit Timer Counter PO 0 S CK KO P0 1 SO K1 P0 2 SI K2 P0 3 BUZ K3 Figure 1 1 S3C72P9 P72P9 Simplified Block Diagram ELECTRONICS PRODUCT OVERVIEW PIN ASSIGNMENTS SEG4 SEG3 SEG2 SEG1 SEGO VLC5 VLC3 VLC2 VLC1 P0 0 S CK KO P0 1 SO K1 P0 2 SI K2 PO 3 BUZ KS VDD Vss XOUT XIN TEST XTIN XT OUT RESET P1 0 INTO P1 1 INT1 P1 2 INT2 P1 3 INT4 P2 0 CLO P2 1 LCDCK P2 2 LCDSY P3 0 TCLOO 001 E gt 9935 0012l L d C3 HE 26 LIOL S Ed EE 96 r3 01935 m m om ul S3C72P9 100 QFP 1420C 88 3 21935 48 8193 98 r3 02945 78 r3 12945 8 NOO O vd 27 6 NOO L vd 7 0LINOO Z vd 77 LLNOO td lt 57 ZLWOD 0 Sd 97 LINOO L Sd 27 SLINO2 Sd 67 87 vX sG93S 0 9d 09 18 veoas Figure 1 2 S3C72P9 100 QFP Pin Assignment Diagram S3C72P9 P72P
153. and STOP PCON bits 3 and 2 are addressed by the STOP and IDLE instructions respectively to engage the idle and stop power down modes Idle and stop modes can be initiated by these instruction despite the current value of the enable memory bank flag EMB PCON bits 1 and 0 are used to select a specific system clock frequency There are two basic choices Main system clock fx or subsystem clock fxt Divided fx 4 8 64 or fxt 4 clock frequency PCON 1 and 0 settings are also connected with the system clock mode control register SCMOD If SCMOD 0 0 the main system clock is always selected by the PCON 1 and 0 setting if SCMOD 0 1 the subsystem clock is selected RESET sets PCON register values and SCMOD to logic zero SCMOD 3 and SCMOD 0 select the main system clock fx and start clock oscillation PCON 1 and 0 divide the selected fx frequency by 64 and PCON 3 and PCON 2 enable normal CPU operating mode Table 6 1 Power Control Register PCON Organization PCON Bit Settings Resulting CPU Operating Mode PCON 3 PCON 2 0 __ CPU operatingmode 0 1 jMepowedowmode Stop power down mode PCON Bit Settings Resulting CPU Clock Frequency PCON 1 0 If SCMOD 0 0 If SCMOD 0 1 PROGRAMMING TIP Setting the CPU Clock To set the CPU clock to 0 95 us at 4 19 MHz BITS EMB SMB 15 LD A 3H LD PCON A 6 4 ELECTRONICS S3C72P9
154. ank columns indicate RAM areas that are not addressable given the addressing method and enable memory bank EMB flag setting shown in the column headers Figure 3 1 RAM Address Structure 3 2 ELECTRONICS S3C72P9 P72P9 Preliminary Spec ADDRESSING MODES EMB AND ERB INITIALIZATION VALUES The EMB and ERB flag bits are set automatically by the values of the RESET vector address and the interrupt vector address When a RESET is generated internally bit 7 of program memory address 0000H is written to the EMB flag initializing it automatically When a vectored interrupt is generated bit 7 of the respective vector address table is written to the EMB This automatically sets the EMB flag status for the interrupt service routine When the interrupt is serviced the EMB value is automatically saved to stack and then restored when the interrupt routine has completed At the beginning of a program the initial EMB and ERB flag values for each vectored interrupt must be set by using VENT instruction The EMB and ERB can be set or reset by bit manipulation instructions BITS BITR despite the current SMB setting 59 PROGRAMMING Initializing the EMB and ERB Flags The following assembly instructions show how to initialize the EMB and ERB flag settings ORG 0000H ROM address assignment VENTO 1 0 RESET lt 1 ERB lt 0 Jump to RESET address by RESET VENT1 0O INTB lt 0 ERB lt 1 Jump to INTB address by I
155. are equal Neither operand is affected by the comparison Binary Code Operation Notation R im 111 1 1 0101 1 SkipitR im 2 rope es oo 1 Skip if A m 2 pu m 2 pope eerie 4 79141919171 The extended accumulator contains the value 34H and register pair HL contains 56H The second instruction RET in the instruction sequence EN E EN E E EH EN CPSE EA HL RET is not skipped That is the subroutine returns since the result of the comparison is not equal ELECTRONICS 5 51 SAM47 INSTRUCTION SET S3C72P9 P72P9 Preliminary Spec DECS Decrement and Skip on Borrow DECS dst Ro Decrement register R skip on borrow PRR Decrement register pair RR skip on borrow Description destination is decremented by one An original value of will underflow to OFFH If a borrow occurs a skip is executed The carry flag value is unaffected ____ 2 skip onborow aa aa alo RR lt RR 1 skip on borrow Examples 1 Register pair HL contains the value 7FH 01111111B The following instruction leaves the value 7EH in register pair HL DECS HL 2 Register A contains the value OH
156. ary Code Summary Concluded omne ETE Er Er ETE Te memb Lc 1 fo memb7 2 L 3 3 L 1 0 C as aa H DA b C 1 1 1 1 1 1 o 0 H4DA3 0Lb lt C o bt bo mma rnnt CmembQL 1 1 1 1 0 1 0 7 2 1 3 2 1 1 0 ose e d a2 Second Byte Bit Addresses memab 1 0 bt bo as a2 at 20 FBOH FBFH 20 FFoHFFFH 5 24 ELECTRONICS S3C72P9 P72P9 Preliminary Spec SAM47 INSTRUCTION SET INSTRUCTION DESCRIPTIONS This section contains detailed information and programming examples for each instruction of the SAM47 instruction set Information is arranged in a consistent format to improve readability and for use as a quick reference resource for application programmers If you are reading this user s manual for the first time please just scan this very detailed information briefly in order to acquaint yourself with the basic features of the instruction set The information elements of the instruction description format are as follows Instruction name mnemonic Full instruction name Source destination format of the instruction operand Operation overview from the High Level Summary table Textual description of the instruction s effect Binary code overview from the
157. at the BUZ pin Bit 6 EN Always logic zero Output Buzzer Frequency Selection Bits 2 kHz buzzer BUZ signal output EZEN 4 kHz buzzer BUZ signal output 0 8 kHz buzzer BUZ signal output 16 kHz buzzer BUZ signal output XT y Input Level Control Bit EN Input level to XT pin is low 1 bit read only addressable for tests Input level to pin is high 1 bit read only addressable for tests Enable Disable Watch Timer Bit EN Disable watch timer and clear frequency dividing circuits Enable watch timer Watch Timer Speed Control Bit EI Normal speed set IRQW to 0 5 seconds High speed operation set IRQW to 3 91 ms Watch Timer Clock Selection Bit 0 Select main system clock fx 128 as the watch timer clock Select a subsystem clock as the watch timer clock NOTE RESET sets WMOD 3 to the current input level of the subsystem clock y If the input level is high WMOD 3 is set to logic one if low WMOD 3 is cleared to zero along with all the other bits in the WMOD register ELECTRONICS 4 MEMORY MAP S3C72P9 P72P9 Preliminary Spec NOTES 4 44 ELECTRONICS S3C72P9 P72P9 Preliminary Spec SAM47 INSTRUCTION SET SAM47 INSTRUCTION SET OVERVIEW The SAM47 instruction set is specifically designed to support the large register files typically founded in most S3C7 series microcontrollers The SAM47 instruction set includes 1 bit 4 bit and 8 bit instructions for data manipulation logi
158. ay be directed to the TCLOO pin or it can be output directly to the serial I O clock selector circuit as the SCK signal Assuming TCO is enabled when bit 3 of the TMODO register is set to 1 the TOLO latch is cleared to logic zero along with the counter register TCNTO and the interrupt request flag IRQTO and counting resumes immediately When TCO is disabled TMODO 2 0 the contents of the TOLO latch are retained and can be read if necessary 11 20 ELECTRONICS S3C72P9 P72P9 Preliminary Spec TIMERS and TIMER COUNTERS PROGRAMMING Setting a TCO Timer Interval To set a 30 ms timer interval for TCO given fxx 4 19 MHz follow these steps 1 Select the timer counter 0 mode register with a maximum setup time of 62 5 ms assume the TCO counter clock fxx 210 and TREFO is set to 2 Calculate the TREFO value TREFO value 1 ons 4 09 kHz 30 ms TREFO 1 244 us 122 9 7AH TREFO value 7AH 1 79H 3 Load the value 79H to the TREFO register BITS EMB SMB 15 LD EA 79H LD TREFO EA LD EA 4CH LD TMODO EA ELECTRONICS 11 21 TIMERS and TIMER COUNTERS S3C72P9 P72P9 Preliminary Spec 16 BIT TIMER COUNTER OVERVIEW Timer counter 1 TC1 is used to count system events by identifying the transition high to low or low to high of incoming square wave signals To indicate that an event has occurred or that a specified time interval has elapsed TC1 generates an interr
159. by the stack pointer thereby adding a new element to the top of the stack 2 1 SP 1 lt SP 2 lt RRL SP SP 2 M d M o BELL 1 5 1 SMB 5 2 SRB SP SP 2 Example As an interrupt service routine begins the stack pointer contains the value OFAH and the data pointer register pair HL contains the value 20H The instruction PUSH HL leaves the stack pointer set to OF8H and stores the values 2H and 0H in RAM locations OF9H and OF8H respectively ELECTRONICS 5 77 SAM47 INSTRUCTION SET S3C72P9 P72P9 Preliminary Spec RCF Reset Carry Flag RCF Description flag is cleared to logic zero regardless of its previous value Example Assuming the carry flag is set to logic one the instruction RCF resets clears the carry flag to logic zero 5 78 ELECTRONICS S3C72P9 P72P9 Preliminary Spec SAM47 INSTRUCTION SET REF Reference Instruction REF dst NOTE The instruction referenced by REF determines instruction cycles Description The REF instruction is used to rewrite into 1 byte form arbitrary 2 byte or 3 byte instructions or two 1 byte instructions stored in the REF instruction reference area in program memory REF reduces the number of program memory accesses for a program memc t7 tb t4 t3 t2 tl o 0 lt memc 5 0 memc 1 7 0 TJP and TCALL are 2 byte p
160. cal and arithmetic operations program control and CPU control instructions for peripheral hardware devices are flexible and easy to use Symbolic hardware names can be substituted as the instruction operand in place of the actual address Other important features of the SAM47 instruction set include 1 referencing of long instructions REF instruction Redundant instruction reduction string effect Skip feature for ADC and SBC instructions Instruction operands conform to the operand format defined for each instruction Several instructions have multiple operand formats Predefined values or labels can be used as instruction operands when addressing immediate data Many of the symbols for specific registers and flags may also be substituted as labels for operations such DA mema memb b and so on Using instruction labels can greatly simplify programming and debugging tasks INSTRUCTION SET FEATURES In this section the following SAM47 instruction set features are described in detail Instruction reference area Instruction redundancy reduction Flexible bit manipulation ADC and SBC instruction skip condition NOTES 1 The ROM size accessed by instruction may change for different devices in the SAM47 product family JP JPS CALL and CALLS 2 The number of memory bank selected by SMB may change for different devices in the SAM47 product family 3 The port names used in the instruction
161. ce routine is executed During the interrupt routine the ERB value is automatically pushed to the stack area along with the other PSW bits Afterwards it is popped back to the 0 bit location The initial ERB flag settings for each vectored interrupt are defined using VENTn instructions PROGRAMMING Using the ERB Flag to Select Register Banks ERB flag settings for register bank selection 1 When ERB 0 SRB 1 Register bank 0 is selected since ERB 0 the SRB is configured to bank 0 LD EA 34H 0 lt 34 LD HL EA BankOHL EA SRB 2 Register bank 0 is selected LD YZ EA BankO YZ EA SRB 3 Register bank 0 is selected LD WX EA 0 lt EA 2 When ERB 1 SRB 1 Register bank 1 is selected LD EA 34H Bank1EA lt 34 LD HL EA Bank1 HL lt 1 SRB 2 Register bank 2 is selected LD YZ EA Bank2 YZ lt BANK2 EA SRB 3 Register bank 3 is selected LD WX EA Bank3WX lt 3 2 22 ELECTRONICS 3 72 9 72 9 Preliminary Spec ADDRESS SPACES SKIP CONDITION FLAGS SC2 SC1 SCO The skip condition flags SC2 SC1 and SCO in the PSW indicate the current program skip conditions and are set and reset automatically during program execution Skip condition flags can only be addressed by 8 bit read instructions Direct manipulation of the SC2 SC1 and SCO bits is not allowed CARRY FLAG C The carry flag
162. control register SCMOD is set to 1001B main system clock oscillation stops and the subsystem clock is used 3 Currents in the following circuits are not included on chip pull up resistors internal LCD voltage dividing resistors output port drive currents 14 4 ELECTRONICS S3C72P9 P72P9 Preliminary Spec ELECTRICAL DATA Table 14 3 Main System Clock Oscillator Characteristics 40 C 85 Vpp 1 8V to 5 5 V Clock Parameter Test Condition Typ E Ceramic Oscillator Stabilization time 2 Stabilization occurs when Vpp is equal to the minimum oscillator voltage range Vpp 3 0 V Crystal Oscillation frequency 1 Oscillator Stabilization time 2 External Xour Xy input frequency 1 0 4 MHz Clock Xy input high and low 83 3 1250 level width ty RC Xout Frequency MHz Oscillator 39 1 NOTES 1 Oscillation frequency and Xy input frequency data are for oscillator characteristics only 2 Stabilization time is the interval required for oscillator stabilization after a power on occurs or when stop mode is terminated ELECTRONICS 14 5 ELECTRICAL DATA S3C72P9 P72P9 Preliminary Spec Table 14 4 Recommended Oscillator Constants TA 40 85 1 8 V to 5 5 V Series Frequency Range Load Cap pF Oscillator Voltage Number 1 Range V c ww 5 FCR 5 3 58 2 6 0 MHz 2 2 2 0 5 5 On chi
163. ction sets the IME bit to logic one enabling all interrupts 5 54 ELECTRONICS S3C72P9 P72P9 Preliminary Spec SAM47 INSTRUCTION SET IDLE Operation IDLE Description IDLE causes the CPU clock to stop while the system clock continues oscillating by setting bit 2 of the power control register PCON After an IDLE instruction has been executed peripheral hardware remains operative In application programs an IDLE instruction must be immediately followed by at least three NOP instructions This ensures an adequate time interval for the clock to stabilize before the next instruction is executed If three or more NOP instructions are not used after IDLE instruction leakage current could be flown because of the floating state in the internal bus Example The instruction sequence IDLE NOP NOP NOP sets bit 2 of the PCON register to logic one stopping the CPU clock The three NOP instructions provide the necessary timing delay for clock stabilization before the next instruction in the program sequence is executed ELECTRONICS 5 55 SAM47 INSTRUCTION SET S3C72P9 P72P9 Preliminary Spec INCS increment and Skip on Carry INCS dst Ro Increment register R skip on carry Increment direct data memory skip on carry ESI Increment indirect data memory skip on carry RR Increment register pair RRb skip on carry te tas Description instruction INCS
164. ction or all of the selected pins must be at input low state for rising edge detection If any one of them or more is at input low state or input high state the interrupt may be not occurred at falling edge or rising edge 3 Togenerate a key interrupt first configure pull up resistors or external pull down resistors And then select edge detection and pins by setting IMODK register 4 20 ELECTRONICS 3 72 9 72 9 Preliminary Spec MEMORY MAP IPR Interrupt Priority Register CPU FB2H Bit 3 2 1 0 RESET Value 0 0 0 0 Read Write W W Bit Addressing 1 4 4 4 4 IME Interrupt Master Enable Bit IPR 2 0 ELECTRONICS Disable all interrupt processing Enable processing for all interrupt service requests Interrupt Priority Assignment Bits Process all interrupt requests at low priority ofofo EREZES Only INTB and INT4 interrupts are at high priority ofa 0 Li Only INTO interrupt is at high priority Only INT1 interrupt is at high priority 1 Only INTS interrupt is at high priority ag Only INTTO interrupt is at high priority fa Only INTT1 interrupt is at high priority Only INTK interrupt is at high priority 4 21 MEMORY MAP S3C72P9 P72P9 Preliminary Spec LCNST Contrast Control Register LCD F8BH F8AH Bit 7 RESET Value 0 Read Write W W Bit Addressing 8 8 8 8 8 8 8 8 LCNST 7 Enable Disable LCD Contrast Control Bit Disable LCD contrast control Enab
165. ctured in accordance with the highest quality standards and objectives Samsung Electronics Co Ltd San 24 Nongseo Lee Kiheung Eup Yongin City Kyungi Do Korea Box 37 Suwon 449 900 TEL 02 760 6530 0331 209 6530 FAX 02 760 6547 Home Page URL Http www samsungsemi com Printed in the Republic of Korea Preface The S3C72P9 P72P9 Microcontroller User s Manual is designed for application designers and programmers who are using the S8C72P9 P72P9 microcontroller for application development It is organized in two parts Part Programming Model Part Il Hardware Descriptions Part contains software related information to familiarize you with the microcontroller s architecture programming model instruction set and interrupt structure It has five chapters Chapter 1 Product Overview Chapter 4 Memory Map Chapter 2 Address Spaces Chapter 5 SAM47 Instruction Set Chapter 3 Addressing Modes Chapter 1 Product Overview is a high level introduction to the S8C72P9 P72P9 ranging from a general product description to detailed information about pin characteristics and circuit types Chapter 2 Address Spaces introduces you to the S3C72P9 P72P9 programming model the program memory ROM and data memory RAM structures and how to address them Chapter 2 also includes information about stack operations CPU registers and the bit sequential carrier BSC register Chapter 3 Addressing Modes descriptions typ
166. d Timing Waveforms RAM data retention supply voltage in stop mode Stop mode release timing when initiated by RESET Stop mode release timing when initiated by an interrupt request ELECTRONICS 14 1 ELECTRICAL DATA S3C72P9 P72P9 Preliminary Spec Table 14 1 Absolute Maximum Ratings TA 25 C Parameter Symbol Conditions unts Bere m _ muva oww o Output Current Low lot One pin active A 100 Peak value 60 note _____ 60 note _____ NOTE The values for Output Current Low loj are calculated as Peak Value x N Duty Table 14 2 D C Electrical Characteristics Input High View input pins except those 0 7V pp Voltage specified below for Vijo V Vip _ Ports 0 1 6 P3 2 P3 3 and 0 8Vpp RESET Ving aM XT XT in Input Low input pins except those Voltage specified below for Vi gt 3 Vito Ports 0 1 6 P3 2 P3 3 and RESET Jw XT Vpp 45V to 55V Output High Voltage 1 mA Ports 0 2 9 Output Low Vpp 4 5 V to 5 5 V Voltage lg 15 mA Ports 0 2 9 14 2 ELECTRONICS S3C72P9 P72P9 Preliminary Spec ELECTRICAL DATA Table 14 2 D C Electrical Characteristics Continued TA 40 to 85 C 1 8 V to 5 5 V Parameter Symbol Conditions
167. d bit and skip if memory bit is set H DA b Description specified bit within the destination operand is tested If it is 1 the instruction that immediately follows the BTST instruction is skipped otherwise the instruction following the BTST instruction is executed The destination bit value is not affected DA b m od memb L Skip if memb 7 2 L 3 2 L 1 0 1 Dis H DAb 1 1 1 1 1 Skpitf H DA3 OJb 1 bt bo 2 at ao Second Byte Bit Addresses EL ies et 7 fot 2 FFOHFFFH Examples 1 If RAM bit location 30H 2 is set to 0 the following instruction sequence will execute the RET instruction BTST 30H 2 If 30H 2 1 then skip RET If 830H 2 0 return JP LABEL2 ELECTRONICS 5 41 SAM47 INSTRUCTION SET S3C72P9 P72P9 Preliminary Spec BTST Bit Test and Skip on True BTST Examples 5 42 Continued 2 You can use BTST in the same way to test a port pin address bit BTST P1 0 If P1 0 1 then skip RET If P1 0 0 then return LABEL3 3 2 P0 3 and P1 0 P1 3 are tested BP2 LD L 2H BTST PO L First PO 02H PO 2 111100B 00B 10B 2 RET INCS L CPSE L 8H JR BP2 4 Bank 0 location 0 is tested and regardless of the current EMB value BTST has the following effect FLAG EQU 0 LD H 0AH BTST H
168. dling ELECTRONICS 7 5 INTERRUPTS S3C72P9 P72P9 Preliminary Spec Multi Level Interrupt Handling With multi level interrupt handling a lower priority interrupt request can be executed while a high priority interrupt is being serviced This is done by manipulating the interrupt status flags ISO and IS1 see Table 7 2 When an interrupt is requested during normal program execution interrupt status flags ISO and IS1 are set to 1 and 0 respectively This setting allows only highest priority interrupts to be serviced When a high priority request is accepted both interrupt status flags are then cleared to 0 by software so that a request of any priority level can be serviced In this way the high and low priority requests can be serviced in parallel see Figure 7 4 Table 7 2 I 1 and ISO Bit Manipulation for Multi Level Interrupt Handling Process Status After INT ACK Effect of ISx Bit Setting ANNE current settings in the IPR register are serviced 2 3 9 Noadationalnterupt requests wil be serviced Pe cadem eee Normal Program Processing Status 0 INT Disable gt Set IPR INT Enable Low or High Level Interrupt Generated Single Interrupt 2 Level Interrupt INT Disable Status 1 8 evel Interrupt odify Status INT Enable gt Status 0 Low gt High Level High Level Interrupt Status 1 Status
169. dress which is generally the instruction immediately after the point at which the interrupt request was detected If a lower level or same level interrupt was pending when the IRET was executed IRET will be executed before the pending interrupt is processed Since the 15th bit of an interrupt start address is not loaded in the PC when the interrupt is occured this bit of PC values is always interpreted as a logic zero at that time The start address of an interrupt the ROM must for this reason be located 0000H 3FFFH PC14 8 SP 1 SP PC7 0 SP 3 SP 2 PSW c SP 5 SP 4 SP SP 6 Example The stack pointer contains the value OFAH An interrupt is detected in the instruction at location 0123H RAM locations OFDH OFCH and OFAH contain the values 2H 3H and 1H respectively The instruction IRET leaves the stack pointer with the value OOH and the program returns to continue execution at location 0123H During a return from interrupt data is popped from the stack to the program counter The data in stack locations OFFH OFAH is organized as follows SP gt PC11 PC8 SP 1 14 12 SP 2 SP 3 SP 4 5 6 ELECTRONICS 5 57 SAM47 INSTRUCTION SET S3C72P9 P72P9 Preliminary Spec JP Jump JP dst Operation Operand Operation Summary Bytes Cycles Description causes an unconditional branch to the indicated
170. e TCLO1 pin 59 PROGRAMMING TC1 Signal Output to the TCLO1 Pin Output a 30 ms pulse width signal to the TCLO1 pin BITS EMB SMB 15 LD EA 79H LD TREF1A EA LD EA 00H LD TREF1B EA LD EA 4CH LD TMOD1 EA LD EA 02H LD PMG2 EA P3 1 lt output mode BITR P3 1 1 clear BITS TOE1 ELECTRONICS 11 27 TIMERS and TIMER COUNTERS S3C72P9 P72P9 Preliminary Spec TC1 EXTERNAL INPUT SIGNAL DIVIDER By selecting an external clock source and loading a reference value into the TC1 reference register TREF1 you can divide the incoming clock signal by the TREF1 value and then output this modified clock frequency to the TCLO1 pin The sequence of operations used to divide external clock input and output the signals to the TCLO1 pin can be summarized as follows i oa gN Load a signal divider value to the TREF1 register Clear TMOD1 6 to 0 to enable external clock input at the TCLO1 pin Set TMOD1 5 and TMOD1 4 to desired TCL signal edge detection Set P3 1 mode flag PM3 1 to output 1 Clear the P3 1 output latch Set TOE1 flag to 1 to enable output of the divided frequency 59 PROGRAMMING External TCL1 Clock Output to the TCLO1 Pin Output the external TCL1 clock source to the TCLO1 pin divide by four External TCL1 Clock Pulse TCLO1 Output Pulse BITS EMB SMB 15 LD EA 01H LD TREF1A EA LD EA 00H LD TREF1B EA LD EA 0CH LD TMOD1 EA LD EA 02H LD PMG2 EA
171. e notre deci ad tede ndash LGD Mode Register EMOD 2 eo est tall e ere ed the LCD Contrast Control Register LONST ccccceeeeecceeeeceeeeceeseeeeeeaeeceaaeeesaeeeceaeeeseaeeesseeeeeaeeeeeaeeeeas LED Voltage Dividing Resistors 2 e eR eee ih Common 510 EL ep dg eee Liste Segment SEG Signals roe dp deserere DA dere aeri bu o De dede deis Chapter 13 Serial I O Interface neatis etate e tb en tet zea iie nm e one ete Serial lO Operation Sequere rettet eei het eae eite Serial I O Mode Register SMOD 2 cccssccceeeeeeeeeeeeeeeeeeeeeeeeceeeeeeaeeeesaeeseeaeseeaaeeseaeeeseaeeeeeaeeteneeeeaeess Serial l O Timing Diagrams serial I O Buffer Register 5 iiiter certc oerte et S3C72P9 P72P9 MICROCONTROLLER Table of Contents concluded Chapter 14 Electrical Data OVCIVIOW MERI MEM Timing Waveforms Chapter 15 Mechanical Data Overview Chapter 16 S3C72P9 OTP IX Operating Mode Characteristics Chapter 17 Development Tools TB72P9 Target Board 3 72 9 72 9 MICROCONTROLLER List of Figures Figure Title Page Number Number 1 1 S3C72P9 P72P9 Simplified Block 1 3 1 2 S3C72P9 100 QFP Pin Assignment
172. e watch timer must be enabled when the LCD display is turned on RESET clears the LMOD register values to logic zero The LCD display can continue to operate during idle and stop modes if a subsystem clock is used as the watch timer source The LCD mode register LMOD controls the output mode of the 16 pins used for normal outputs P9 3 P6 0 Bits LMOD 7 5 define the segment output and normal bit output configuration Table 12 4 LCD Clock Signal LCDCK Frame Frequency LCDCK 2048 Hz 4096 Hz Display Duty Cycle m NOTE COMO 1 Frame ELECTRONICS 12 5 LCD CONTROLLER DRIVER S3C72P9 P72P9 Preliminary Spec Table 12 5 LCD Mode Register LMOD Organization Segment Port Output Selection Bits LMOD 7 LMOD 6 LMOD 5 SEG40 43 SEG44 47 SEG48 51 Total Number of Segment ster sea pon see por nomaron s2 se pon pon nomaron 4 1 1 SEG port Normal port Normal port Normal port Normal port Normal port Normal port Normal port NOTE Segment pins that also can used for normal I O should be configured to output mode when the SEG function is used LCD Clock Selection Bits LMOD 4 LMOD 3 LCD Clock LCDCK NE oas He NOTE LCDCK is supplied only when the watch timer is operating use the LCD controller you must set bit 2 i
173. ec PORTS I O PORTS OVERVIEW The S3C72P9 has 10 ports There total of 4 input pins and 35 configurable I O pins for a maximum number of 39 pins Pin addresses for all ports are mapped to bank 15 of the RAM The contents of I O port pin latches can be read written or tested at the corresponding address using bit manipulation instructions Port Mode Flags Port mode flags PM are used to configure ports to input or output mode by setting or clearing the corresponding buffer Pull up Resistor Mode Register PUMOD The pull up register mode registers PUMOD1 2 are used to assign internal pull up resistors by software to specific ports When a configurable I O port pin is used as an output pin its assigned pull up resistor is automatically disabled even though the pin s pull up is enabled by a corresponding PUMOD bit setting ELECTRONICS 10 1 PORTS S3C72P9 P72P9 Preliminary Spec Table 10 1 I O Port Overview Address Function Description P0 0 P0 3 FFOH 4 bit port 1 bit and 4 bit read write and test is possible Individual pins are software configurable as input or output Individual pins are software configurable as open drain or push pull output 4 bit pull up resistors are software assignable pull up resistors are automatically disabled for output pins P1 0 P1 3 FF1H 4 bit input port 1 bit and 4 bit read and test is possible 4 bit pull up resistors are assignable 2 0 2
174. ec TIMERS and TIMER COUNTERS TCO CLOCK FREQUENCY OUTPUT Using timer counter 0 a modifiable clock frequency can be output to the TCO clock output pin TCLOO To select the clock frequency load the appropriate values to the TCO mode register TMODO The clock interval is selected by loading the desired reference value into the reference register TREFO To enable the output to the TCLOO pin the following conditions must be met TCO output enable flag TOEO must be set to 1 mode flag for P3 0 PM3 0 must be set to output mode 1 Output latch value for P3 0 must be set to 0 In summary the operational sequence required to output a TCO generated clock signal to the TCLOO pin is as follows 1 Load areference value to TREFO Set the internal clock frequency in TMODO Initiate TCO clock output to TCLOO TMODO 2 1 Set P3 0 mode flag PM3 0 to 1 Set P3 0 output latch to 0 Set TOEO flag to 1 oak Each time TCNTO overflows and an interrupt request is generated the state of the output latch TOLO is inverted and the TCO generated clock signal is output to the TCLOO pin 59 PROGRAMMING TIP TCO Signal Output to the TCLOO Pin Output a 30 ms pulse width signal to the TCLOO pin BITS EMB SMB 15 LD EA 79H LD TREFO EA LD EA 4CH LD TMODO EA LD EA 01H LD PMG2 EA P3 0 lt output mode BITR P3 0 P3 0 clear BITS TOEO ELECTRONICS 11 15 TIMERS and TIMER COUNTERS S3C72P9
175. eeneees 14 8 14 9 RAM Data Retention Supply Voltage in Stop 14 10 16 1 Descriptions of Pins Used to Read Write the e 16 3 16 2 Comparison of S3P72P9 and S3C72P9 16 3 16 3 Operating Mode Selection Criteria 2 16 3 16 4 D C Electrical Characteristics esses 16 4 17 1 Power Selection Settings for 72 9 17 4 17 2 Main Clock Selection Settings for TB72P9 sese 17 4 17 3 Sub Clock Selection Settings for 72 9 17 5 17 4 Using Single Header Pins as the Input Path for External Trigger Sources 17 5 S3C72P9 P72P9 MICROCONTROLLER xvii List of Programming Tips Description Chapter 2 Address Spaces Defining Vectored Interrupts 2 Wsing the REF Look Up Table e ee ege edi Clearing Data Memory Banks 0 1 Selecting the Working Register Initializing the Stack Using the BSC Register to Output 16 Bit Setting ISx Flags for Interrupt Using the Flag to Select Memory Using the ERB Flag to Select Register Using
176. elect TCL1 edge detection for rising or falling signal edges by loading the appropriate values to TMOD1 5 and TMOD1 4 Pin P3 3 must be set to input mode Table 11 9 TMOD1 Settings for TCL1 Edge Detection TMOD1 5 TMOD1 4 TCL1 Edge Detection Rising edges 11 26 ELECTRONICS S3C72P9 P72P9 Preliminary Spec TIMERS and TIMER COUNTERS TC1 CLOCK FREQUENCY OUTPUT Using timer counter 1 a modifiable clock frequency can be output to the TC1 clock output pin TCLO1 To select the clock frequency load the appropriate values to the TC1 mode register TMOD1 The clock interval is selected by loading the desired reference value into the 16 bit reference register TREF1 To enable the output to the TCLO1 pin at I O port 3 1 the following conditions must be met TC1 output enable TOE1 must be set to 1 mode flag for P3 1 PM3 1 must be set to output mode 1 P3 1 output latch must be cleared to 0 In summary the operational sequence required to output a TC1 generated clock signal to the TCLO1 pin is as follows 1 Load your reference value to TREF1 Set the internal clock frequency in TMOD1 Initiate TC1 clock output to TCLO1 TMOD1 2 1 Set port 3 1 mode flag PM3 1 to 1 Clear the P3 1 output latch Set TOE1 flag to 1 Oak oD Each time TCNT1 overflows and an interrupt request is generated the state of the output latch TOL1 is inverted and the TC1 generated clock signal is output to th
177. eliminary Spec TIMERS and TIMER COUNTERS TIMER COUNTER 1 COMPONENT SUMMARY Mode register TMOD1 Activates the timer counter and selects the internal clock frequency or the external clock source at the TCL 1 pin Reference register TREF1 Stores the reference value for the desired number of clock pulses between in terrupt requests Counter register TCNT1 Counts internal clock pulses that are generated based on bit settings in the mode register and reference register Clock selector circuit Together with the mode register TMOD1 lets you select one of four internal clock frequencies or the external system clock source 16 bit comparator Determines when to generate an interrupt by comparing the current value of the counter TCNT1 with the reference value previously programmed into the reference register TREF1 Output latch TOL 1 Where a TC1 clock pulse is stored pending output to the TC1 output pin TCLO1 When the contents of the TCNT1 and TREF1 registers coincide the timer counter interrupt request flag IRQT1 is set to 1 the status of TOL 1 is in verted and an interrupt is generated Output enable flag TOE1 Must be set to logic one before the contents of the TOL1 latch can be output to TCLO1 Interrupt request flag IRQT1 Cleared when TC1 operation starts and set to logic one whenever the counter value and reference value match Interrupt enable flag IET1 Must be set to logic one before the interrupt requests
178. errupt service routine for a lower priority request is accepted during the execution of a higher priority routine Two Level Interrupt Handling Two level interrupt handling is the standard method for processing multiple interrupts When the IS1 and ISO bits of the PSW FBOH 3 and FBOH 2 respectively are both logic zero program execution mode is normal and all interrupt requests are serviced see Figure 7 3 Whenever an interrupt request is accepted 151 and ISO are incremented by one and the values are stored in the stack along with the other PSW bits After the interrupt routine has been serviced the modified 1 1 and ISO values are automatically restored from the stack by an IRET instruction 150 and 151 can be manipulated directly by 1 bit write instructions regardless of the current value of the enable memory bank flag EMB Before you can modify an interrupt service flag however you must first disable interrupt processing with a DI instruction When 151 0 and ISO 1 all interrupt service routines are inhibited except for the highest priority interrupt currently defined by the interrupt priority register IPR Normal Program High or Low Level Processing Interrupt Processing Status 0 Status 1 High Level Interrupt INT Disable Processing Set IPR gt Status 2 INT Enable gt Low or High Level High Level Interrupt Interrupt gt Generated Generated Figure 7 3 Two Level Interrupt Han
179. es of addressing supported by the SAM47 instruction set direct indirect and bit manipulation and the addressing modes which are supported 1 bit 4 bit and 8 bit Numberous programming examples make the information practical and usable Chapter 4 Memory Map contains a detailed map of the addressable peripheral hardware registers in the memory mapped area of the RAM bank 15 Chapter 4 also contains detailed descriptions in standard format of the most commonly used hardware registers These easy to read register descriptions can be used as a quick reference source when writing programs Chapter 5 SAM47 Instruction Set first introduces the basic features and conventions of the SAM47 instruction set Then two summary tables orient you to the individual instructions One table is a high level summary of the most important information about each instruction the other table is designed to give expert programmers a summary of binary code and instruction notation information The final part of Chapter 5 contains detailed descriptions of each instruction in a standard format Each instruction description includes one or more practical examples A basic familiarity with the information in Part will make it easier for you to understand the hardware descriptions in Part Il If you are familiar with the SAM47 product family and are reading this user s manual for the first time we recommend that you read Chapters 1 3 carefully and just scan the
180. et P5 1 to input mode 1 Set P5 1 to output mode PM5 0 P5 Mode Selection Flag Set P5 0 to input mode Set P5 0 to output mode 1 PM4 3 P4 3 I O Mode Selection Flag Set P4 3 to input mode Set P4 3 to output mode PM4 2 P4 2 I O Mode Selection Flag Set P4 2 to input mode Set P4 2 to output mode 1 PM4 1 P4 Mode Selection Flag Set P4 1 to input mode Set P4 1 to output mode 1 4 0 P4 0 I O Mode Selection Flag Set P4 0 to input mode 1 Set P4 0 to output mode 4 28 ELECTRONICS 3 72 9 72 9 Preliminary Spec MEMORY MAP PMG4 Port Mode Register 4 Group 4 Ports 6 7 y o FEDH FECH Bit 7 6 5 4 3 2 1 0 Identifier PM7 3 PM7 2 PM7 1 PM7 0 PM6 3 6 2 6 1 6 0 RESET Value 0 0 0 0 0 0 0 0 Read Write W W W W W W W Bit Addressing 8 8 8 8 8 8 8 8 PM7 3 P7 3 Mode Selection Flag Set P7 3 to input mode 1 Set P7 3 to output mode PM7 2 P7 2 I O Mode Selection Flag Set P7 2 to input mode 1 Set P7 2 to output mode PM7 1 P7 1 Mode Selection Flag Set P7 1 to input mode Set P7 1 to output mode 1 7 0 P7 0 I O Mode Selection Flag Set P7 0 to input mode Set P7 0 to output mode 1 PM6 3 P6 3 I O Mode Selection Flag Set P6 3 to input mode Set P6 3 to output mode 1 PM6 2 P6 2 I O Mode Selection Flag Set P6 2 to input mode Set P6 2 to output mode 1 6 1 P6 1 I O Mode Selection Flag Set P6 1 to input mode
181. for output RESET clears all port mode flags to logical zero automatically configuring the corresponding ports to input mode Table 10 3 Port Mode Group Flags PM Group ID PMG1 PMG2 PMG3 PMG4 PMG5 NOTE If bit 0 the corresponding pin is set to input mode If bit 1 the pin is set to output mode for P0 0 PMO 1 for 1 etc All flags are cleared to 0 following RESET PROGRAMMING Configuring I O Ports to Input or Output Configure ports 0 and 2 as an output port BITS EMB SMB 15 LD EA 7FH LD PMG1 EA PO P2 lt Output ELECTRONICS 10 3 PORTS S3C72P9 P72P9 Preliminary Spec PULL UP RESISTOR MODE REGISTER PUMOD The pull up resistor mode registers PUMOD1 and PUMOD2 are used to assign internal pull up resistors by soft ware to specific ports When a configurable port pin is used as an output pin its assigned pull up resistor is automatically disabled even though the pin s pull up is enabled by a corresponding PUMOD bit setting PUMOD 1 is addressable by 8 bit write instructions only and PUMOD2 by 4 bit write instruction only RESET clears PUMOD register values to logic zero automatically disconnecting all software assignable port pull up resistors Table 10 4 Pull Up Resistor Mode Register PUMOD Organization PUMODID Address 2 PUMOD1 FDCH PURS PUR2 PUR1 PURO FDDH PUR7 PUR6 PUR5 PUR4 NOTE When bit
182. for the basic timer It can be addressed by 8 bit read instructions RESET leaves the BCNT counter value undetermined BCNT is automatically cleared to logic zero whenever the BMOD register control bit BMOD 3 is set to 1 to restart the basic timer It is incremented each time a clock pulse of the frequency determined by the current BMOD bit settings is detected When BCNT has incrementing to hexadecimal FFH 255 clock pulses it is cleared to OOH and an overflow is generated The overflow causes the interrupt request flag IRQB to be set to logic one When the interrupt request is generated BCNT immediately resumes counting incoming clock signals NOTE Always execute a BONT read operation twice to eliminate the possibility of reading unstable data while the counter is incrementing If after two consecutive reads the BCNT values match you can select the latter value as valid data Until the results of the consecutive reads match however the read operation must be repeated until the validation condition is met BASIC TIMER OPERATION SEQUENCE The basic timer s sequence of operations may be summarized as follows 1 Set BMOD 3 to logic one to restart the basic timer BONT is then incremented by one after each clock pulse corresponding to BMOD selection BCNT overflows if BCNT 255 BCNT FFH When an overflow occurs the IRQB flag is set by hardware to logic one The interrupt request is generated BCNT is then cleared
183. for the number of clock pulses to be generated between interrupt requests The counter register TCNTO counts the incoming clock pulses which are compared to the TREFO value as is incremented When there is a match TREFO an interrupt request is generated To program timer counter 0 to generate interrupt requests at specific intervals choose one of four internal clock frequencies divisions of the system clock fxx and load a counter reference value into the TREFO register TCNTO is incremented each time an internal counter pulse is detected with the reference clock frequency specified by TMODO 4 TMODO 6 settings To generate an interrupt request the TCO interrupt request flag IRQTO is set to logic one the status of TOLO is inverted and the interrupt is generated The content of TCNTO is then cleared to 00H and TCO continues counting The interrupt request mechanism for TCO includes an interrupt enable flag IETO and an interrupt request flag IRQTO TCO OPERATION SEQUENCE The general sequence of operations for using TCO can be summarized as follows Set TMODO 2 to 1 to enable TCO Set TMODO 6 to 1 to enable the system clock fxx input Set TMODO 5 and TMODO 4 bits to desired internal frequency fxx 2 Load a value to TREFO to specify the interval between interrupt requests Set the TCO interrupt enable flag IETO to 1 Set TMODO 3 bit to 1 to clear TCNTO IRQTO and and start coun
184. generated by timer counter 1 can be processed Table 11 8 TC1 Register Overview Register Type Description RAM Addressing Reset Name Address Mode Value TMOD1 Control Controls TC1 enable disable bit FAOH FA1H 8 bit write 2 clears and resumes counting only operation bit 3 sets input TMOD1 3 is clock and the clock frequency also 1 bit bits 6 4 writeable TCNT1 Counter Counts clock pulses matching 16 bit FA4H FABH 8 bit the TMOD1 frequency setting FAGH FA7H read only TREF1 Reference Stores reference value for TC1 16 bit FA8H FA9H 8 bit FFFFH interval setting write only TOE1 Flag Controls TC1 output to the 1 bit F92H 3 1 4 bit TCLO1 pin read write ELECTRONICS 11 23 TIMERS and TIMER COUNTERS S3C72P9 P72P9 Preliminary Spec Clocks fxx 2 10 fxx 2 8 6 fxx 2 4 TCL1 TMOD1 7 TMOD1 6 TMOD1 5 olak Selector TMOD1 4 Inverted Figure 11 4 TC1 Circuit Diagram TC1 ENABLE DISABLE PROCEDURE Enable Timer Counter 1 Setthe TC1 interrupt enable flag IET1 to logic one Set TMOD1 3 to logic one TCNT1 IRQT1 and TOL1 are cleared to logic zero and timer counter operation starts Disable Timer Counter 1 Set TMOD1 2 to logic zero Clock signal input to the counter register TCNT1 is halted The current TCNT1 value is retained and can be read if necessary 11 24 ELECTRONICS S3C72P9 P72P9 Preliminary Spec TIMERS and TIMER COUNTERS TC1 PROGRAMMABLE TIMER
185. he WDMOD is toggled for 8 times where toggle means change from 5AH to other value and vice versa 3 When the watchdog timer is enabled or the 3 bit counter of the watchdog timer is cleared to 0 the 3 bit counter of the watchdog timer WDCNT can be increased by 1 For example when the BMOD value is x000B and the watchdog timer is enabled the watchdog timer interval time is from 2 x 212 x 2 8 fxx to 2 3 1 x 2 12 x 2 8 box Figure 11 1 Basic Timer Circuit Diagram ELECTRONICS S3C72P9 P72P9 Preliminary Spec TIMERS and TIMER COUNTERS BASIC TIMER MODE REGISTER BMOD The basic timer mode register BMOD is a 4 bit write only register Bit 3 the basic timer start control bit is also 1 bit addressable All BMOD values are set to logic zero following RESET and interrupt request signal generation is set to the longest interval BT counter operation cannot be stopped BMOD settings have the following effects Restart the basic timer Control the frequency of clock signal input to the basic timer Determine time interval required for clock oscillation to stabilize following the release of stop mode by an interrupt By loading different values into the BMOD register you can dynamically modify the basic timer clock frequency during program execution Four BT frequencies ranging from 212 to fxx 25 are selectable Since BMOD s reset value is logic zero the default clock frequency setting is fxx 21 The most
186. he accumulator with the RAM location addressed by register pair HL and then increments the contents of register L If the content of register L is OH a skip is executed The value of the carry flag is unaffected A HL A HL then L L 1 skip L 0H Example Register pair HL contains the address 2FH and internal RAM location 2FH contains OFH LD HL 2FH LD A 0H XCHI A HL lt amp 120 HL lt JPS XXX Skipped since an overflow occurred JPS YYY He 29 lt YYY XCHI A HL 20H lt lt 20H _L lt L 1 1H The JPS YYY instruction is executed since a skip occurs after the XCHI instruction 5 96 ELECTRONICS S3C72P9 P72P9 Preliminary Spec SAM47 INSTRUCTION SET XOR Logical Exclusive OR XOR dst src Exclusive OR immediate data to A A HL Exclusive OR indirect data memory to A Exclusive OR register pair RR to EA Exclusive OR register pair RRb to EA Description performs a bitwise logical operation between the source and destination variables and stores the result in the destination The source contents are unaffected Operation Notation 1 1 im 92 do 1 4 0 0 EA EA XOR RR EXE co MR RRb EA o lt EA 2 If the extended accumulator contains 110000
187. he system clock fxx input Set TMOD1 5 and TMOD1 4 bits to desired internal frequency fxx 2 Load a value to TREF1 to specify the interval between interrupt requests Set the TC1 interrupt enable flag IET1 to 1 Set TMOD1 3 bit to 1 to clear TCNT1 IRQT1 and and start counting TCNT1 increments with each internal clock pulse When the comparator shows TCNT1 TREF1 the IRQT1 flag is set to 1 and an interrupt request is generated Output latch TOL1 logic toggles high or low N e WO 0 TCNT1 is cleared to 0000H and counting resumes k Programmable timer counter operation continues until TMOD1 2 is cleared to 0 ELECTRONICS 11 25 TIMERS and TIMER COUNTERS S3C72P9 P72P9 Preliminary Spec TC1 EVENT COUNTER FUNCTION Timer counter 1 can monitor system events by using the external clock input at the TCL1 pin as the counter source The TC1 mode register selects rising or falling edge detection for incoming clock signals The counter register is incremented each time the selected state transition of the external clock signal occurs With the exception of the different TMOD1 4 TMOD 1 6 settings the operation sequence for TC1 s event counter function is identical to its programmable timer counter function To activate the TC1 event counter function Set TMODI 2 to 1 to enable TC1 Clear TMOD1 6 to 0 to select the external clock source at the TCL1 pin S
188. iate data to A and skip on overflow 1 5 Add 8 61 immediate data to EA and skip on overflow 2 5 A HL Add indirect data memory to A and skip on overflow 1 5 Add register pair RR contents to EA and skip 2 2 5 overflow RRb EA Add EA to register pair RRb and skip on overflow 248 Description The source operand is added to the destination operand and the sum is stored in the destination The contents of the source are unaffected If there is an overflow from the most significant bit of the result the skip signal is generated and a skip is executed but the carry flag value is unaffected If ADS A im follows an ADC A HL instruction in a program ADC skips the ADS instruction if an overflow occurs If there is no overflow the ADS instruction is executed normally This skip condition is valid only for ADC A HL instructions however If an overflow occurs following an ADS instruction the next instruction is not skipped e e at acAemsiponoetos EA imm 1 1 EA lt imm skip on overflow 95 a4 d3 a2 at do EJ 6 Po fa 1 1 1 1 0 lt HU skip on overtiow 122 22 277 1 2 4 1 1 0 RRb lt RRb EA skip on overflow EA RR E s RRb EA Examples 1 The extended accumulator contains the value 0C3H register pair HL the value OAAH and the carry
189. ic zero Always logic zero TMOD1 2 TMOD1 1 TMOD1 0 TMOD1 3 1 Clear TCNT1 IRQT1 and TOL1 and resume counting immedi FAOH ately This bit is automatically cleared to logic zero immediately after counting resumes ELECTRONICS 11 29 TIMERS and TIMER COUNTERS S3C72P9 P72P9 Preliminary Spec Table 11 11 TMOD1 6 TMOD1 5 and TMOD1 4 Bit Settings TMOD1 6 TMOD1 5 TMOD1 4 Resulting Counter Source and Clock Frequency External clock input TCL1 on rising edges 1 External clock input TCL1 on falling edges 1 Ls La v 5 meam v esum NOTE selected system clock of 4 19 MHz 1 1 1 PROGRAMMING Restarting TC1 Counting Operation 1 Set TC1 timer interval to 4 09 kHz BITS EMB SMB 15 LD EA 4CH LD TMOD1 EA EI BITS 2 Clear TCNT1 IRQT1 and TOL1 and restart TC1 counting operation SBITS EMB SMB 15 BITS TMOD1 3 11 30 ELECTRONICS S3C72P9 P72P9 Preliminary Spec TIMERS and TIMER COUNTERS TC1 COUNTER REGISTER TCNT1 The 16 bit counter register for timer counter 1 TCNT1 is mapped to RAM addresses FASH FA4H TCNT1A and FA7H FA6H TCNT1B The two 8 bit registers are read only and can be addressed by 8 bit RAM control in structions RESET sets all TCNT1 register values to logic zero 00H Whenever TMOD1 2 and TMOD1 3 are enabled TCNT1 is cleared to logic zero and counting begins The TCNT1 register value is inc
190. in Descriptioris s itte e ye estu ist b e EU RES EC dete i dd 1 5 PincGircuit DIAgratmis et d E e ote a ehe Rt ee Re ipe BU Lex 1 8 Chapter 2 Address Spaces Program Memory nde RR tee OR pe cee MNES ee e e e ipee d 2 1 OVEM OW 2 1 General Purpose Memory 2 2 Vector Adress Area uiui nee e ree rre 2 2 Instruction Reference Area tuetur dete 2 5 Data Memory tede tene 2 7 OVGIVIOW eee edie es 2 7 Working Registers i i 5 3 D YU te Hensel 2 11 Stack Operations dert da Hcet Het tere ddan alien 2 15 Stack Pointer SP BEC er e ied dac Ep ee 2 15 Push Operaltiolis 2 2 PA Les wee ree cute 2 16 Pop Operations oaie deodata a p aaen 2 17 Bit Sequential Carrier BSC ee 2 18 Program Gountet PG eet Ga hates 2 19 Program Status Word PSW 2 e Rei eoe ed 2 19 Interrupt Status Flags SO O me 2 20 EMB Flag e dete len t iet e dette decis 2 21
191. ing instruction sequence sets the carry flag and the loads the 1 data value to the output pin P1 0 setting it to output mode SCF Cen LDB P1 0 C P10c 5 The P1 address is FF1H and L 01H 0001B The address memb 7 2 is 111100B and L 3 2 is OOB The resulting address 11110000B specifies PO The bit value L 1 0 is specified as 01B bit 1 Therefore P1 L PO 1 SCF Cet LD L 0001B LDB P1 L C P1 L specifies PO 1 lt 1 6 In this example 2H and FLAG 20H 3 and the address 20H is specified Since the bit value is 3 H FLAG 20H 3 FLAG EQU 20H 3 RCF LD H 2H LDB H FLAG C FLAG 20H 3 lt NOTE Port pin names used in examples 4 and 5 may vary with different SAM47 devices 5 68 ELECTRONICS S3C72P9 P72P9 Preliminary Spec SAM47 INSTRUCTION SET LDC Load Code Byte LDC dst src EA WX Load code byte from WX to EA EA EA Load code byte from EA to EA Description X This instruction is used to load a byte from program memory into an extended accumulator The address of the byte fetched is the six highest bit values in the program counter and the contents of an 8 bit working register either WX or EA The contents of the source are unaffected mew a o lo eneon Examples 1 The following instructions will load one of four values defined by the define byte DB directive to the extended accumulator EA
192. input low state for rising edge detection If any one of them or more is at input low state or input high state the interrupt may be not occurred at falling edge or rising edge 3 To generate a key interrupt first configure pull up resistors or external pull down resistors And then select edge detection and pins by setting IMODK register 7 10 ELECTRONICS S3C72P9 P72P9 Preliminary Spec INTERRUPTS P6 3 K7 P6 2 K6 Disable P6 1 K5 P6 0 K4 Rising Falling Edge P0 3 K3 Selector P0 2 K2 Enable Disable P0 1 K1 P0 0 KO gt gt gt gt b gt gt Figure 7 6 Circuit Diagram for INTK ELECTRONICS 7 11 INTERRUPTS S3C72P9 P72P9 Preliminary Spec PROGRAMMING Using INTK as a Key Input Interrupt When the key interrupt is used the selected key interrupt source pin must be set to input 1 When 7 are selected eight pins BITS SMB LD LD LD LD LD LD LD EMB 15 A 3H IMODK A EA 00H PMG1 EA PMG4 EA EA 41H PUMOD1 EA 2 When K0 K3 are selected four pins BITS SMB LD LD LD LD LD LD EMB 15 1 EA 00H PMG1 EA PUMOD1 EA IMODK lt KO K7 falling edge select PO lt input mode P6 lt input mode Enable PO and P6 pull up resistors IMODK lt K0 K3 falling edge select PO lt input mode Enable PO pull up resistors ELECTRONICS S3C72P9 P72P9 Preliminary Spec INTERRUPTS INT
193. inter value is OOH and the label PLAY is assigned to program memory location 5E3FH Executing the instruction PLAY at location 0123H will generate the following values SP OFFH OH OFEH EMB ERB OFDH 2H OFCH OFBH OH OFAH 1H PC 5E3FH Data is written to stack locations OFFH OFAH as follows OFAH PC11 PC8 OFBH PC14 PC13 PC12 OFCH OFDH o o tne 0 o ELECTRONICS S3C72P9 P72P9 Preliminary Spec SAM47 INSTRUCTION SET LD Load LD dst src Load data memory conensioA 3 o ADA Load drect data memory conenstoa 2 Am e Load ata 2 Anm Load contents of A to direct datamemoy 2 oed comens Ato rse 2 data memory conons o EA tADA Load drect data memory coments Load contents ot A toinrectdaamemoy omes mi mj nmj gt DA EA Load contents of EA to data memory RRb EA Load contents of EA to register HL EA Load contents of EA to indirect data memory Description contents of the source are loaded into the destination The source s contents are unaffected If an instruction such as LD A im LD
194. interface Operates only if external SCK input is Operates if a clock other than the CPU selected as the serial I O clock clock is selected as the serial I O clock Timer counter 0 Operates only if TCLO is selected as the Timer counter 0 operates counter clock Timer counter 1 Operates only if TCL1 is selected as the Timer counter 1 operates counter clock Watch timer Operates only if subsystem clock fxt is Watch timer operates selected as the counter clock LCD controller Operates only if a subsystem clock is se LCD controller operates lected as LCDCK External interrupts INTO INT1 INT2 INT4 and INTK are INTO INT1 INT2 INT4 and INTK are acknowledged acknowledged PU All CPU operations are disabled All CPU operations are disabled Mode release signal Interrupt request signals are enabled by Interrupt request signals are enabled by an interrupt enable flag or by RESET input an interrupt enable flag or by RESET input 8 2 ELECTRONICS 3 72 9 72 9 Preliminary Spec POWER DOWN Table 8 2 System Operating Mode Comparison Condition STOP IDLE Mode Start Current Consumption Method Main operating Main oscillator runs mode Sub oscillator runs stops System clock is the main oscillation clock Main Idle mode Main oscillator runs IDLE instruction Sub oscillator runs stops System clock is the main oscillation clock Main Stop mode Main oscillator runs STOP instruction Sub oscillator runs System clock is the
195. interrupt and stabilization interval are selected by loading the appropriate bit values to BMOD 2 BMOD 0 The 8 bit counter register BCNT is incremented each time a clock signal is detected that corresponds to the frequency selected by BMOD BCNT continues incrementing as it counts BT clocks until an overflow occurs gt 255 An overflow causes the BT interrupt request flag IRQB to be set to logic one to signal that the designated time interval has elapsed An interrupt request is than generated BONT is cleared to logic zero and counting continues from 00H Watchdog Timer Function The basic timer can also be used as a watchdog timer to signal the occurrence of system or program operation error For this purpose instruction that clear the watchdog timer BITS WDTCF should be executed at proper points in a program within given period If an instruction that clears the watchdog timer is not executed within the given period and the watchdog timer overflows reset signal is generated and the system restarts with reset status An operation of watchdog timer is as follows Write some values except 5AH to watchdog timer mode register WDMOD If WDONT overflows system reset is generated 11 2 ELECTRONICS S3C72P9 P72P9 Preliminary Spec TIMERS and TIMER COUNTERS Oscillation Stabilization Interval Control Bits 2 0 of the BMOD register are used to select the input clock frequency for the basic timer This setting also dete
196. is completed After the return from interrupt IRET you do not need to set the EMB and ERB values again Instead use BITR and BITS to clear these values in your program routine The starting addresses for vector interrupts and reset operations are pointed to by the VENTn instruction These starting addresses must be located in ROM ranges 0000H 3FFFH Generally the VENTn instructions are coded starting at location 0000H The format for VENT instructions is as follows VENTn d1 d2 ADDR lt d 0 or 1 ERB lt d2 0 1 lt ADDR address to branch device specific module address code 0 Operand 000 Code Operation Notation EMB 0 1 a13 12 a11 a10 ROM 2 x n 7 6 gt ERB ERB 0 1 ROM 2 x n 5 4 PC13 12 ADR ROM 2 x n 3 0 PC11 8 ROM 2 x n 1 7 0 2 PC7 0 n 0 1 2 3 4 5 6 7 Fer as e so 10 5 92 ELECTRONICS S3C72P9 P72P9 Preliminary Spec SAM47 INSTRUCTION SET VENT Load EMB ERB and Vector Address VENTn Continued Example The instruction sequence ORG 0000H VENTO 1 0 RESET VENT1 0 1 INTA VENT2 0 1 INTB VENT3 0 1 INTC VENT4 0 1 INTD VENT5 0 1 INTE VENT6 0 1 INTF VENT7 0 1 INTG causes the program sequence to branch to the RESET routine labeled RESET setting to 1 and ERB to 0 when RESET is activated When a basic timer interrupt is generated VENT1 causes the progr
197. is compared to the TCNTO value When TCNTO TREFO the TCO output latch TOLO is inverted and an interrupt request is generated to signal the interval or event The TREFO value together with the TMODO clock frequency selection determines the specific TCO timer interval Use the following formula to calculate the correct value to load to the TREFO reference register 1 frequency setting TCO timer interval TREFO value 1 x TREFO value 0 TCO OUTPUT ENABLE FLAG The 1 bit timer counter 0 output enable flag TOEO controls output from timer counter 0 to the TCLOO TOEO is addressable by 1 bit read and write instructions MSB LSB NOTE means that the bit is undefined When you set the TOEO flag to 1 the contents of TOLO can be output to the TCLOO pin Whenever a RESET occurs TOEO is automatically set to logic zero disabling all TCO output Even when the TOEO flag is disabled timer counter 0 can continue to output an internally generated clock frequency to the serial I O clock selector circuit TCO OUTPUT LATCH TOLO TOLO is the output latch for timer counter 0 When the 8 bit comparator detects a correspondence between the value of the counter register TCNTO and the reference value stored in the TREFO register the TOLO value is inverted the latch toggles high to low or low to high Whenever the state of TOLO is switched the TCO signal is output TCO output m
198. is used to save the result of an overflow or borrow when executing arithmetic instructions involving a carry ADC SBC The carry flag can also be used as a 1 bit accumulator for performing Boolean operations involving bit addressed data memory If an overflow or borrow condition occurs when executing arithmetic instructions with carry ADC SBC the carry flag is set to 1 Otherwise its value is 0 When a RESET occurs the current value of the carry flag is retained during power down mode but when normal operating mode resumes its value is undefined The carry flag can be directly manipulated by predefined set of 1 bit read write instructions independent of other bits in the PSW Only the ADC and SBC instructions and the instructions listed in Table 2 7 affect the carry flag Table 2 7 Valid Carry Flag Manipulation Instructions Operation Type Carry Flag Manipulation Direct manipulation Set carry flag to 1 Clear carry flag to 0 reset carry flag Bit transfer LDB operand 1 Load carry flag value to the specified bit LDB C operand 1 Load contents of the specified bit to carry flag Boolean manipulation BAND 1 AND the specified bit with contents of carry and save the result to the carry flag BOR C operand 1 OR the specified bit with contents of carry flag and save the result to the carry flag Test carry and skip if 1 BXOR C operand 1 XOR the specified bit with contents of ca
199. isable all interrupts with a DI instruction Modify the IMOD register Clear all relevant interrupt request flags Enable the interrupt by setting the appropriate IEx flag a Enable all interrupts with an El instructions ELECTRONICS 7 9 INTERRUPTS S3C72P9 P72P9 Preliminary Spec EXTERNAL KEY INTERRUPT MODE REGISTER IMODK The mode register for external key interrupts at the 7 pins IMODK is addressable only by 4 bit write instructions RESET clears all IMODK bits to logic zero FB6H IMODK 2 IMODK 1 0 27 IMODK2 IMODKO Rising or falling edge can be detected by bit IMODK 2 settings If a rising falling edge is detected at any one of the selected pin by the IMODK register the IRQK flag is set to logic one and a release signal for power down mode is generated Table 7 6 IMODK Register Bit Settings 779 monk mooki Erect or MOBK Setings 1 Enabeedpe at KOKS pis 3 erable edge detection at he 7 pi IMODK IMODK 2 Falling edge detection Rising edge detection NOTES 1 generate a key interrupt the selected pins must be configured to input mode If any one pin of the selected pins is configured to output mode only falling edge can be detected 2 generate key interrupt all of the selected pins must be at input high state for falling edge detection or all of the selected pins must be at
200. ister values is however always retained when a RESET occurs during idle or stop mode If a RESET occurs during normal operating mode their values are undefined Current values that are retained in this case are as follows Carry flag Data memory values General purpose registers E A L H X W Z and Y Serial buffer register SBUF Oscillator Stabilization Wait Time 31 3 ms 4 19 MHz RESET It Input Normal Mode or Idle Mode Operatng Mode Power down Mode RESET Operation Figure 9 1 Timing for Oscillation Stabilization after RESET HARDWARE REGISTER VALUES AFTER RESET Table 9 1 gives you detailed information about hardware register values after a RESET occurs during power down mode or during normal operation ELECTRONICS 9 1 RESET S3C72P9 P72P9 Preliminary Spec Table 9 1 Hardware Register Values After RESET Hardware Component If RESET Occurs During If RESET Occurs During or Subcomponent Power Down Mode Normal Operation Program counter PC Lower six bits of address 0000H Lower six bits of address 0000H are transferred to 13 8 and are transferred to PC13 8 and the contents of 0001H to 7 0 the contents of 0001H to PC7 0 seos 9 status tags SIS 9 9 Bank enable flags EMB ERB Bit 6 of address 0000H in program Bit 6 of address 0000H in program memory is transferred
201. ister LCON Organization Select duty by means of LMOD 2 0 Select 1 12 duty COMO COM 1 is selected Disable LCDCK and LCDSY signal outputs Setting Oo 0 Enable LCDCK and LCDSY signal outputs ofai ERES LCON Bit LCON 3 LCON 2 LCON 1 LCON 0 LCD display off cut off current to dividing resistor LCD display on application with internal contrast control LCD display on application with external contrast control LCD display on NOTE lf the external variable resistor for control connected to V ce you can select only one contrast control method External or Internal contrast control Table 12 3 LMOD 1 0 Bits Settings LMOD 1 0 0 15 SEGO SEG55 SEG40 P9 3 SEG55 P6 0 Power Supply to the Dividing Resistor n Al of the LCD dots off Normal port function All of the LCD dots on 1 1 Common and segment signal output corresponds to display data normal display mode 12 4 ELECTRONICS S3C72P9 P72P9 Preliminary Spec LCD CONTROLLER DRIVER LCD MODE REGISTER LMOD The LCD mode control register LMOD is used to control display mode LCD clock segment or port output and display on off LMOD can be manipulated using 8 bit write instructions The LCD clock signal LCDCK determines the frequency of COM signal scanning of each segment output This is also referred to as the frame frequency Since LCDCK is generated by dividing the watch timer clock fw th
202. it is an odd number the LSB of the DA value is recognized as logic zero an even number and is not replaced with the true value Load contents of EA to the 8 bit RRb register HL WX YZ The E register is loaded into the H W and Y register and the A register into the L X and Z register Load the A register to data memory location pointed to by the 8 bit HL register and the E register contents to the next location HL 1 The contents of the L register must be an even number If the number is odd the LSB of the L register is recognized as logic zero an even number and is not replaced with the true value For example LD HL 36H loads immediate 36H to register HL the instruction LD HL EA loads the contents of A into address 36H and the contents of E into address 37H ELECTRONICS S3C72P9 P72P9 Preliminary Spec SAM47 INSTRUCTION SET LDB Load Bit LDB dst src b LDB dst b src Load carry bit to a specified memory bit 2 memb QL C Load carry bit to a specified indirect memory bit H DA b C Load memory bit to a specified carry bit C memb L_ Load indirect memory bit to a specified carry bit C H DA b Description Boolean variable indicated by the first or second operand is copied into the location specified by the second or first operand One of the operands must be the carry flag the other may be any directly or indirectly addressable bit The source is unaffected Binary Code Operation Notation
203. ive vector address Then if necessary you can modify the enable flags during the interrupt service routine When the interrupt service routine is returned to the main routine by the IRET instruction the original values saved in the stack are restored and the main program continues program execution with these values Software Generated Interrupts To generate an interrupt request from software the program manipulates the appropriate IRQx flag When the interrupt request flag value is set it is retained until all other conditions for the vectored interrupt have been met and the service routine can be initiated Multiple Interrupts By manipulating the two interrupt status flags ISO and IS1 you can control service routine initialization and thereby process multiple interrupts simultaneously If more than four interrupts are being processed at one time you can avoid possible loss of working register data by using the PUSH RR instruction to save register contents to the stack before the service routines are executed in the same register bank When the routines have executed successfully you can restore the register contents from the stack to working memory using the POP instruction Power Down Mode Release An interrupt can be used to release power down mode stop or idle Interrupts for power down mode release initiated by setting the corresponding interrupt enable flag Even if the IME flag is cleared to zero power down mode will
204. kHz 1 Select system clock fxx 16 262 kHz Select system clock fxx 64 65 5 kHz Select CPU clock source fx 4 fx 8 fx 64 1 05 MHz 524 kHz or 65 5 kHz NOTE fxx is the system clock given a clock frequency of 4 19 MHz ELECTRONICS 4 9 MEMORY MAP S3C72P9 P72P9 Preliminary Spec IEO 1 IRQO 1 INTO 1 Interrupt Enable Request Flags CPU FBEH Bit 3 2 1 0 RESET Value 0 0 0 0 Read Write R W R W R W R W Bit Addressing 1 4 1 4 1 4 1 4 IE1 INT1 Interrupt Enable Flag Disable interrupt requests at the INT1 pin 1 Enable interrupt requests at the INT1 pin IRQ1 INT1 Interrupt Request Flag Generate INT1 interrupt This bit is set and cleared by hardware when rising or falling edge detected at INT1 pin IEO INTO Interrupt Enable Flag Disable interrupt requests at the INTO pin 1 Enable interrupt requests at the INTO pin IRQO INTO Interrupt Request Flag Generate INTO interrupt This bit is set and cleared automatically by hardware when rising or falling edge detected at INTO pin 3 72 9 72 9 Preliminary Spec MEMORY MAP IE2 IRQ2 2 Interrupt Enable Request Flags CPU FBFH Bit 3 2 1 0 RESET Value 0 0 0 0 Read Write R W R W R W R W Bit Addressing 1 4 1 4 1 4 1 4 3 2 Bits 3 2 EN Always logic zero IE2 INT2 Interrupt Enable Flag Disable INT2 interrupt requests at the INT2 pin 1 Enable INT2 interrupt requests at the INT2 pin IRQ2 INT2 Interrupt Request Flag Generate INT2 q
205. le ELECTRONICS 7 1 INTERRUPTS S3C72P9 P72P9 Preliminary Spec Vectored Interrupts Interrupt requests may be processed as vectored interrupts in hardware or they can be generated by program Software A vectored interrupt is generated when the following flags and register settings corresponding to the specific interrupt INTn are set to logic one Interrupt enable flag IEX Interrupt master enable flag IME Interrupt request flag IRQx Interrupt status flags ISO 151 Interrupt priority register IPR If all conditions are satisfied for the execution of a requested service routine the start address of the interrupt is loaded into the program counter and the program starts executing the service routine from this address EMB and ERB flags for RAM memory banks and registers are stored in the vector address area of the ROM during interrupt service routines The flags are stored at the beginning of the program with the VENT instruction The initial flag values determine the vectors for resets and interrupts Enable flag values are saved during the main routine as well as during service routines Any changes that are made to enable flag values during a service routine are not stored in the vector address When an interrupt occurs the EMB and the ERB flags before the interrupt is initiated are saved along with the pro gram status word PSW and the EMB and the ERB flag for the interrupt is fetched from the respect
206. le INTS interrupt requests 1 Enable INTS interrupt requests when serial data transfer completion signal received from serial interface ELECTRONICS MEMORY MAP S3C72P9 P72P9 Preliminary Spec IETO IRQTO Interrupt Enable Request Flags CPU FBCH Bit 3 2 1 0 Identifier IETO IRGTO RESET Value 0 0 0 0 Read Write R W R W R W R W Bit Addressing 1 4 1 4 1 4 1 4 3 2 Bits 3 2 Ea Always logic zero IETO INTTO Interrupt Enable Flag Disable INTTO interrupt requests Enable INTTO interrupt requests IRQTO INTTO Interrupt Request Flag when contents of TCNTO and TREFO registers match Generate INTTO interrupt This bit is set and cleared automatically by hardware ELECTRONICS 3 72 9 72 9 Preliminary Spec MEMORY MAP 1 Interrupt Enable Request Flags CPU FBBH IEK IRQK iNTK Interrupt Enable Request Flags CPU FBBH Bit 3 2 1 0 Identifier IET RESET Value 0 0 0 0 Read Write R W R W R W R W Bit Addressing 1 4 1 4 1 4 1 4 1 INTK Interrupt Enable Flag Disable interrupt requests at 7 pins Enable interrupt requests at the 7 pins IROK INTK Interrupt Request Flag Generate INTK interrupt This bit is set and cleared automatically by hardware when rising or falling edge detected at 7 pins IET1 INTT1 Interrupt Enable Flag E Disable INTT1 interrupt requests Enable INTT1 interrupt requests IR
207. le LCD contrast control LCNST 6 4 Bits 6 4 Always logic zero LCNST 3 0 LCD Contrast Level Control Bits 16 steps 1 16 step The dimmest level 2 16 step The dimmest level 3 16 step The dimmest level 16 16 step The brightest level NOTE Vicp n 17 32 where 0 15 4 22 ELECTRONICS 3 72 9 72 9 Preliminary Spec MEMORY MAP Output Control Register LCD F8EH Bit 3 2 1 0 RESET Value 0 0 0 0 Read Write Bit Addressing 4 4 4 4 LCON 3 LCD Duty and Selection Bits Select duty by means of LMOD 2 0 1 Select 1 12 duty COMO 11 is selected NOTE When 1 12 duty is selected ports 4 should be configured as output mode and port 5 can be used for Normal I O port LCON 2 LCD Clock Output Disable Enable Bit Disable LCDCK and LCDSY signal outputs Enable LCDCK and LCDSY signal outputs LCON 1 0 LCD Output Control Bit LCD display off cut off current to dividing resistor LCD display on application with internal contrast control 1 LCD display on application with external contrast control LCD display on NOTES 1 If the external variable resistor for contrast control connected to VLC5 you can select only one contrast control method External or Internal contrast control 2 When 1 12 duty is selected by LCON 3 the LCD Clock LCDCK Frequency is following LMOD 4 3 LCD Clock LCDCK Frequency Selection Bits When 1 12 duty
208. lock frequency 3 When the watchdog timer is enabled or the 3 bit counter of the watchdog timer is cleared to 0 the BCNT value is not cleared but increased continuously As a result the 3 bit counter of the watchdog timer WDCNT can be increased by 1 For example when the BMOD value is x000b and the watchdog timer is enabled the watchdog timer interval time is either 23 x 212 x 28 fxx or 23 1 x 212 x 28 11 8 ELECTRONICS S3C72P9 P72P9 Preliminary Spec TIMERS and TIMER COUNTERS 59 PROGRAMMING TIP Using the Watchdog Timer RESET MAIN ELECTRONICS EA 00H SP EA A 0DH BMOD A WDTCF MAIN WDONT input clock is 7 82 ms Main routine operation period must be shorter than watchdog timer s period TIMERS and TIMER COUNTERS S3C72P9 P72P9 Preliminary Spec 8 BIT TIMER COUNTER 0 TCO OVERVIEW Timer counter 0 TCO is used to count system events by identifying the transition high to low or low to high of incoming square wave signals To indicate that an event has occurred or that a specified time interval has elapsed TCO generates an interrupt request By counting signal transitions and comparing the current counter value with the reference register value TCO can be used to measure specific time intervals TCO has a reloadable counter that consists of two parts an 8 bit reference register TREFO into which you write the counter reference value and an 8 bit counter register TCNTO
209. logic zero and counting resumes The TCNTO register value is incremented each time an incoming clock signal is detected that matches the signal edge and frequency setting of the TMODO register specifically TMODO 6 TMODO 5 and TMODO 4 Each time TONTO is incremented the new value is compared to the reference value stored in the TCO refer ence buffer TREFO When TCNTO TREFO an overflow occurs in the TCNTO register the interrupt request flag IRQTO is set to logic one and an interrupt request is generated to indicate that the specified timer counter interval has elapsed Reference Value n DRM o e 2 Match Match Timer Start Instruction IRQTO Set IRQTO Set TMODO 3 is set Figure 11 3 TCO Timing Diagram ELECTRONICS 11 19 TIMERS and TIMER COUNTERS S3C72P9 P72P9 Preliminary Spec TCO REFERENCE REGISTER TREFO The TCO reference register TREFO is an 8 bit write only register It is addressable by 8 bit RAM control instructions RESET initializes the TREFO value to FFH TREFO is used to store a reference value to be compared to the incrementing TCNTO register in order to identify an elapsed time interval Reference values will differ depending upon the specific function that TCO is being used to perform as a programmable timer counter event counter clock signal divider or arbitrary frequency output source During timer counter operation the value loaded into the reference register
210. ly using 1 bit RAM control instructions By manipulating interrupt status flags in conjunction with the interrupt priority register IPR you can process multiple interrupts by anticipating the next interrupt in an execution sequence The interrupt priority control circuit determines the ISO and IS1 settings in order to control multiple interrupt processing When both interrupt status flags are set to 0 all interrupts are allowed The priority with which interrupts are processed is then determined by the IPR When an interrupt occurs ISO and IS1 are pushed to the stack as part of the PSW and are automatically incremented to the next higher priority level Then when the interrupt service routine ends with an IRET instruction ISO 151 values are restored to the PSW Table 2 6 shows the effects of ISO and 151 flag settings Table 2 6 Interrupt Status Flag Bit Settings 151 150 Status of Currently Effect of ISO and IS1 Settings Value Value Executing Process on Interrupt Request Control All interrupt requests are serviced No more interrupt requests are serviced Not applicable these bit settings are undefined 1 1 Only high priority interrupt s as determined in the interrupt priority register IPR are serviced 92 7 EE Wes E we Since interrupt status flags can be addressed by write instructions programs can exert direct control over interrupt processing status Before interrupt status flags can be addressed howe
211. m 1 OR im 92 ao eqno IHE RN 0 110 RRb EA Example If the accumulator contains the value 1100001 1B and register pair HL the value 55H 01010101B the instruction OR EA leaves the value 0D7H 11010111B in the accumulator ELECTRONICS 5 75 SAM47 INSTRUCTION SET S3C72P9 P72P9 Preliminary Spec POP Pop from Stack POP dst Pop SMB and SRB values from stack Description contents of the RAM location addressed by the stack pointer is read and the SP is incremented by two The value read is then transferred to the variable indicated by the destination operand RRL lt SP lt SP 1 SP lt 2 SRB lt SP SMB lt SP 1 SP lt 2 Example The SP value is equal to OEDH and RAM locations OEFH through OEDH contain the values 2H and 4H respectively The instruction POP HL leaves the stack pointer set to OEFH and the data pointer pair HL set to 34H 5 76 ELECTRONICS S3C72P9 P72P9 Preliminary Spec SAM47 INSTRUCTION SET PUSH Push Onto Stack PUSH src RR o Push register pair onto stack 1 Push SMB and SRB values onto stack 2 Description SP is then decreased by two and the contents of the source operand are copied into the RAM location addressed
212. m ELECTRONICS 10 5 PORTS S3C72P9 P72P9 Preliminary Spec PORT 1 CIRCUIT DIAGRAM INTO INT1 INT2 INT4 PUMOD 1 P1 0 INTO P1 1 INT1 P1 2 INT2 P1 3 INT4 N R Noise Reduction Figure 10 2 Port 1 Circuit Diagram 10 6 ELECTRONICS 3 72 9 72 9 Preliminary Spec PORTS PORT 2 CIRCUIT DIAGRAM PUR2 L o gt PUR2 Ho Mo P2 0 CLO P2 1 LCDCK o ype B P2 2 LCDSY o Type B a CMOS Push Pull N Channel Open Drain 2 0 O PM2 1 O NOTE When port pin serves as an output its pull up resistor is automatically disabled even though the port s pull up resistor is enabled by bit settings in the pull up resistor mode register PUMOD 2 2 O Figure 10 3 Port 2 Circuit Diagram ELECTRONICS 10 7 PORTS S3C72P9 P72P9 Preliminary Spec PORT 3 CIRCUIT DIAGRAM VDD PUR3 gt o e r D PUR3 Hyo 5 P3 0 TCLOO P3 1 TCLO1 P3 2 TCLO P3 3 TCL1 CMOS Push Pull N Channel Open Drain PM30 H gt o Output 1 Data 2 D TCLO gt NOTE When port pin serves as an output its pull up resistor is automatically disabled even though the port s pull up resistor is enabled by bit settings in the pull up resistor mode register PUMOD TCL1 Figure 10 4 Port 3 Circuit Diagram 10 8 ELECTRONICS 3 72 9 72 9 Preliminary Spec PORTS PORT 4 5 6 7 8 9 CIRCUIT DIAGRAM VDD BUB gt 51 por
213. m A skip on borrow EA RR Subtract register pair RR from EA skip on borrow RRb EA Subtract EA from register pair RRb skip on borrow Description source operand is subtracted from the destination operand and the result is stored in the destination The contents of the source are unaffected A skip is executed if a borrow occurs The value of the carry flag is not affected ane 1 AC A sp on toros EA RR 0 EA EA RR skip on borrow m dues 77 pE8 p co quens Examples 1 accumulator contains the value 0C3H register pair HL contains the value 0C7H and the carry flag is cleared to logic zero RCF Cce SBS EA HL EA lt 0C7H SBS instruction skips on borrow but carry flag value is not affected JPS XXX Skip because a borrow occurred JPS YYY Jump to YYY is executed 2 The accumulator contains the value OAFH register pair HL contains the value OAAH and the carry flag is set to logic one SCF Ce 1 SBS EA HL EA lt JPS XXX Jump to XXX JPS was not skipped since no borrow occurred after SBS 5 86 ELECTRONICS S3C72P9 P72P9 Preliminary Spec SAM47 INSTRUCTION SET SCF set Carry Flag SCF Description SCF instruction sets the carry flag to logic one regardless of its previous value Example If the carry flag is cleared to logic zero the inst
214. memc 1 ROM 2 x 7 6 gt EMB ERB ROM 2222 ROM 2 x n 3 0 5 11 8 ROM 2 1 7 0 gt PC7 0 n 0 1 2 3 4 5 6 7 ELECTRONICS 5 15 SAM47 INSTRUCTION SET S3C72P9 P72P9 Preliminary Spec Table 5 16 Program Control Instructions Binary Code Summary ENES CAKAEE Skip if R 98 2 dt go o rr 10 duin fe at __ 1 EA HL EPEFESESEHERESESL Skip if EA RR E 0 13 anz a9 as 47 as a4 ae at 40 1 Peso 13 0 o 13 2 faio ao as 47 as a4 ae at R im HL im EA RR ADR 10 ao 14 0 lt PCt4 12 ADR11 0 7 as 4 2 a0 203068046 NN ERESENESESESESES EN RTE ET NN SP 1 SP 3 SP 5 SP 1 SP 3 SP 5 SP 2 ERB SP 4 PC7 0 SP 6 PC14 8 SP 2 lt ERB SP 4 PC7 0 SP 6 PC13 8 ENSHESEHENEXEHE 0 ars ars anz an aio a9 as 47 46 as a4 2 at FARES ERASER o ao a8 47 as a4 ae at 40 SP 1 SP 3 SP 5
215. memory These locations can be addressed by 1 bit 4 bit or 8 bit instructions When the bit value of a display segment is 1 the LCD display is turned on when the bit value is O the display is turned off Display RAM data are sent out through segment pins SEGO SEG55 using a direct memory access DMA method that is synchronized with the signal RAM addresses in this location that are not used for LCD display can be allocated to general purpose use eafb oot bajos Figure 12 3 LCD Display Data RAM Organization Table 12 1 Common and Segment Pins per Duty Cycle NOTE When 1 8 duty is selected 8 15 P4 0 P5 3 can be used for normal I O pins When 1 12 duty is selected COM12 COM15 P5 0 P5 3 can be used for normal I O pins ELECTRONICS 12 3 LCD CONTROLLER DRIVER S3C72P9 P72P9 Preliminary Spec LCD CONTROL REGISTER LCON The LCD control register LCON is used to turn the LCD display on and off to output LCD clock LCDCK and synchronizing signal LCDSY for LCD display expansion and to control the flow of current to dividing resistors in the LCD circuit Following a RESET all LCON values are cleared to 0 This turns the LCD display off and stops the flow of current to the dividing resistors The effect of the LCON O setting is dependent upon the current setting of bits LMOD 0 and LMOD 1 Bit 1 in the LCON is used for contrast control application Table 12 2 LCD Control Reg
216. mer clock fw 1 Select subsystem clock as watch timer clock fw NOTE Main system clock frequency fx is assumed be 4 19 MHz subsystem clock fxt is assumed to be 32 768 kHz D uw E NN WMOD 3 Input level to XT yy pin is low F88H e Input level to XT pin is high WMOD 2 Disable watch timer clear frequency dividing circuits one Enable watch timer M NN UN HN __ OOt a gt ELECTRONICS 11 37 TIMERS and TIMER COUNTERS S3C72P9 P72P9 Preliminary Spec PROGRAMMING Using the Watch Timer 1 Select a subsystem clock as the LCD display clock a 0 5 second interrupt and 2 kHz buzzer enable BITS EMB SMB 15 LD EA 8H LD PMG1 EA P0 3 lt output mode BITR P0 3 LD EA 85H LD WMOD EA BITS IEW 2 Sample real time clock processing method CLOCK BTSTZ IRQW 0 5 second check RET No return Yes 0 5 second interrupt generation Increment HOUR MINUTE SECOND 11 38 ELECTRONICS S3C72P9 P72P9 Preliminary Spec LCD CONTROLLER DRIVER LCD CONTROLLER DRIVER OVERVIEW The S3C72P9 microcontroller can directly drive an up to 896 dot 56 segments x 16 commons LCD panel Its LCD block has the following components LCD controller driver Display RAM for storing display data 56 segment output pins SEGO SEG55 16 common output pins 0 15 Five LCD operating power supply pins Vi c4 V ca Vigs pin for co
217. mple If the result of Then the execution Reason Instruction Sees instruction 1 is sequence is ADC A HL Overflow ADS cannot skip ADS A im instruction 3 even if it XXX No overflow 2 3 has a skip function XXX SBC A HL Borrow 2 3 ADS cannot skip ADS A im instruction 3 even if it XXX No borrow has a skip function XXX 5 6 ELECTRONICS S3C72P9 P72P9 Preliminary Spec SAM47 INSTRUCTION SET SYMBOLS AND CONVENTIONS Table 5 4 Data Type Symbols Table 5 6 Instruction Operand Notation Direct address Indirect address prefix Source operand Destination operand Contents of register R Flag data Indirect addressing data memc x 0 5 immediate data Bit location 4 bit immediate data number Register data 8 bit immediate data number Immediate data prefix Table 5 5 Register Identifiers 000 immediate address Ful Register Name w 4 bit accumulator A 4 bit working registers E L H X W Z Y 8 bit extended accumulator EA n bit address A E L H X W Z Y L H X W Z Y EA HL WX YZ HL WX WL HL WX YZ WX WL FBOH FBFH FFOH FFFH FCOH FFFH 8 bit memory pointer HL 8 bit working registers WX YZ WL Select register bank n SRB n Select memory bank n SMB n Carry flag Code direct addressing 0020H 007FH Select bank register 8 bits Program status word PSW Port n Pn m th bit of port n Pn m Logical exclusive OR Logical OR Logical AND
218. n Format eese nennen 4 7 6 1 Glock Circult Diagram s toic ihn eret dtt 6 2 6 2 Crystal Ceramic Oscillator 1 nnne 6 3 6 3 External Oscillator fx eh el genre eo dete ree tee de 6 3 6 4 RG Oscillator ec etti eter te niente E 6 3 6 5 Crystal Ceramic Oscillator 6 3 6 6 External Oscillator eere eg etre sauce 6 3 6 7 CLO Output Pin Circuit Diagratmi 6 11 3 72 9 72 9 MICROCONTROLLER xi List of Figures Continued Figure Title Page Number Number 7 1 Interrupt Execution 7 3 7 2 Interrupt Control Circuit 7 4 7 3 Two Level Interrupt 7 5 7 4 Multi Level Interrupt 2 7 6 7 5 Circuit Diagram for INTO INT1 and INT2 Pins seen 7 9 7 6 Cireuit Diagram for eir eft eth htec 7 11 8 1 Timing When Idle Mode is Released by 8 4 8 2 Timing When Idle Mode is Released by an 8 4 8 3 Timing When Stop Mode is Released by RESET 8 5 8 4 Timing When Stop Mode is Released by an
219. n is located If the first byte of the instruction code is located at address xFFEH or xFFFH the instruction will jump to the next block If the instruction JPS SUB were located instead at program memory address OFFEH OFFFH the instruction JPS SUB would load the PC with the value 10FFH causing a program malfunction ELECTRONICS 5 59 SAM47 INSTRUCTION SET S3C72P9 P72P9 Preliminary Spec JR Jump Relative Very Short JR dst m Branch to relative immediate address __ 1 2 __ Branch relative to contents of WX register 3 Branch relative to contents of EA Description causes the relative address to be added to the program counter and passes control to the instruction whose address is now in the PC The range of the relative address is current PC 15 to current PC 16 The destination address for this jump is specified to the assembler by a label an actual address or by immediate data using a plus sign or a minus sign For immediate addressing the range is from 2 to 16 and the range is from 1 to 15 If a O 1 or any other number that is outside these ranges are used the assembler interprets it as an error For JR WX and JR EA branch relative instructions the valid range for the relative address is OH OFFH The destination address for these jumps can be specified to the assembler by a label that lies anywhere within the current 256 byte block Normally the WX
220. n the watch mode register WMOD to 1 NN Duty Selection Bits LMOD 2 Duty 0 1 8duty select 1 16 duty 15 select NOTE When 1 16 duty is selected ports 4 and 5 should be configured as output mode when 1 8 duty is selected ports 4 and 5 be used as normal I O ports Display Mode Selection Bits v Ci 12 6 ELECTRONICS S3C72P9 P72P9 Preliminary Spec LCD CONTROLLER DRIVER LCD CONTRAST CONTROL REGISTER LCNST The LCD contrast control register LCNST is used to control the LCD contrast up to 16 step contrast level Following RESET all LCNST values are cleared to 0 Table 12 6 LCD Clock Signal LCDCK Frame Frequency Enable Disable LCD Contrast Control Bit LCNST 7 Disable LCD contrast control Enable LCD contrast control Bits 6 4 Always logic zero LCD Control Level Control Bits 16 steps 0 Mi sep Thedmmesieve poo o 1 pex ge 3 16 step NOTE cp Vpp x 17 32 where n 0 15 ELECTRONICS 12 7 LCD CONTROLLER DRIVER S3C72P9 P72P9 Preliminary Spec LCD VOLTAGE DIVIDING RESISTORS On chip voltage dividing resistors for the LCD drive power supply are fixed to the Vi c4 V c5 pins Power can be supplied without an external dividing resistor Figure 12 4 shows the bias connections for the S3C72P9 LCD drive power supply To cut off the flow of current through the dividing
221. nd A can either be manipulated individually using 4 bit instructions or together as register pairs for 8 bit data manipulation The names of the 8 bit register pairs in each register bank are EA HL WX YZ and WL Registers A L X and Z always become the lower nibble when registers are addressed as 8 bit pairs This makes a total of eight 4 bit registers or four 8 bit double registers in each of the four working register banks Figure 2 5 Register Pair Configuration 2 12 ELECTRONICS 3 72 9 72 9 Preliminary Spec ADDRESS SPACES Special Purpose Working Registers Register A is used as a 4 bit accumulator and double register EA as an 8 bit accumulator The carry flag can also be used as a 1 bit accumulator 8 bit double registers WX WL and HL are used as data pointers for indirect addressing When the HL register serves as a data pointer the instructions LDI LDD XCHI and XCHD can make very efficient use of working registers as program loop counters by letting you transfer a value to the L register and increment or decrement it using a single instruction 1 Bit Accumulator 4 Bit Accumulator 8 Bit Accumulator Figure 2 6 1 Bit 4 Bit and 8 Bit Accumulator Recommendation for Multiple Interrupt Processing If more than four interrupts are being processed at one time you can avoid possible loss of working register data by using the PUSH RR instruction to save register contents to the stack before the service routine
222. ng hardware and software is provided the sophisticated and powerful in circuit emulator SMDS2 for S3C7 S3C8 S3C9 families of microcontrollers The SMDS2 is a new and improved version of SMDS2 Samsung also offers support software that includes debugger assembler and a program for setting options SHINE Samsung Host Interface for In Circuit Emulator SHINE is a multi window based debugger for SMDS2 SHINE provides pull down and pop up menus mouse support function hot keys and context sensitive hyper linked help It has an advanced multiple windowed user interface that emphasizes ease of use Each window can be sized moved scrolled highlighted added or removed completely SAMA ASSEMBLER The Samsung Arrangeable Microcontroller SAM Assembler SAMA is a universal assembler and generates object code in standard hexadecimal format Assembled program code includes the object code that is used for ROM data and required SMDS program control data To assemble programs SAMA requires a source file and an auxiliary definition DEF file with device specific information SASM57 The SASM57 is an relocatable assembler for Samsung s S3C7 series microcontrollers The SASM57 takes a source file containing assembly language statements and translates into a corresponding source code object code and comments The SASM57 supports macros and conditional assembly It runs on the MS DOS operating system It produces the relocatable object code only
223. ng to any location by referencing a branch instruction stored in the look up table Calling subroutines at any location by referencing a call instruction stored in the look up table ELECTRONICS 2 5 ADDRESS SPACES S3C72P9 P72P9 Preliminary Spec 59 PROGRAMMING Using the REF Look Up Table Here is one example of how to use the REF instruction look up table JMAIN KEYCK WATCH INCHL ABC MAIN 2 6 ORG TJP BTSF TCALL LD INCS LD ORG NOP NOP REF REF REF REF REF 0020H MAIN KEYFG CLOCK HL A HL EA 00H 0080 KEYCK JMAIN WATCH INCHL ABC 0 MAIN 1 KEYFG CHECK 2 Call CLOCK 3 HL lt A 47 lt 00H BTSF KEYFG 1 byte instruction KEYFG 1 jump to MAIN 1 byte instruction KEYFG 0 CALL CLOCK 1 byte instruction LD HL A INCS HL LD EA 00H 1 byte instruction ELECTRONICS 3 72 9 72 9 Preliminary Spec ADDRESS SPACES DATA MEMORY RAM OVERVIEW In its standard configuration the 1298 x 4 bit data memory has four areas 32 4 bit working register area in bank 0 224 x 4bit general purpose area in bank 0 which is also used as the stack area 256 x 4 bit general purpose area in bank 1 224 x 4 bit area for LCD data in bank 2 32 4 bit general purpose area in bank 2 256 x 4 bit general purpose area in bank 3 256 x 4 bit general purpose area in bank 4 128 x 4 bit area in bank 15 for memory ma
224. nly the first LD is executed the next instructions are treated as NOPs Here are two examples of this redundancy effect LD ACdH LD EA 2H NOP LD A 3H NOP LD 23H A 23H lt 1H LD HL 10H HL lt 10H LD HL 20H NOP LD A 3H A lt 3H LD 35 NOP LD HL A 10H lt The following table contains descriptions of special characteristics of the LD instruction when used in different addressing modes Instruction Operation Description and Guidelines LD Since the redundancy effect occurs with instructions like LD EA imm if this instruction is used consecutively the second and additional instructions of the same type will be treated like NOPs LD A RRa_ Load the data memory contents pointed to by 8 bit RRa register pairs HL WX WL to the A register LD A DA Load direct data memory contents to the A register LD A Ra Load 4 bit register Ra E L H X W Z Y to the A register LD Load 4 bit immediate data into the Ra register E L H X W Y Z LD RR imm_ Load 8 bit immediate data into the Ra register EA HL WX YZ There is a redundancy effect if the operation addresses the HL or EA registers LD DA A Load contents of register A to direct data memory address LD Ra A Load contents of register A to 4 bit Ra register E L H X W Z Y ELECTRONICS 5 65 SAM47 INSTRUCTION SET LD Load LD Concluded Examples Instruction LD LD LD LD
225. ns the value 0C3H register pair HL the value and the carry flag is cleared to 0 RCF SBC EA HL EA lt 19H lt 0 JPS XXX Jump to XXX no skip after SBC 5 84 ELECTRONICS S3C72P9 P72P9 Preliminary Spec SBC subtract with Carry SBC Continued SAM47 INSTRUCTION SET Examples 3 If SBC A HL is followed by an ADS A im the SBC skips on to the instruction immediately after the ADS An ADS A im instruction immediately after the SBC A HL instruction does not skip even if an overflow occurs This function is useful for decimal adjustment operations 8 6 decimal addition the contents of the address specified by the HL register is 6H RCF LD SBC ADS JPS A 8H A HL A 0AH XXX C c A lt 8H 8H 6H C 0 2H C lt 0 Skip this instruction because no borrow after SBC result b 3 4 decimal addition the contents of the address specified by the HL register is 4H RCF LD SBC ADS JPS ELECTRONICS A 3H A HL A 0AH XXX C lt 0 lt 3H lt C O C lt 1 No skip lt OFH OAH 9H The skip function of ADS A im is inhibited after a SBC A HL instruction even if an overflow occurs 5 85 SAM47 INSTRUCTION SET S3C72P9 P72P9 Preliminary Spec SBS Subtract SBS dst src A HL Subtract indirect data memory fro
226. ntrolling the driver and bias voltage To use the LCD controller bit 2 in the watch mode register WMOD must be set to 1 because LCDCK is supplied by the watch timer The frame frequency duty and bias and the segment pins used for display output are determined by bit settings in the LCD mode register LMOD The LCD control register LCON is used to turn the LCD display on and off to switch current to the dividing resistors for the LCD display and to output LCD clock LCDCK and synchronizing signal LCDSY for LCD display expansion Data written to the LCD display RAM can be transferred to the segment signal pins automatically without program control When a subsystem clock is selected as the LCD clock source the LCD display is enabled even during main clock stop and idle modes O VLC1 VLC5 o COM0 COM7 LCD 8 1 1 P4 0 P4 3 Controller Driver COM12 COM15 P5 0 P5 3 2 RU 00 SEGO SEGS39 SEG40 SEG55 P9 3 P6 0 Figure 12 1 LCD Function Diagram ELECTRONICS 12 1 LCD CONTROLLER DRIVER Data Bus gt S3C72P9 P72P9 Preliminary Spec SEG55 P6 0 SEG54 P6 1 Selector SEG40 P9 3 SEGO COM15 P5 3 Timing COM COM14 P5 2 Controller Control COMO Contrast Controller LCD Voltage Control Figure 12 2 LCD Circuit Diagram ELECTRONICS S3C72P9 P72P9 Preliminary Spec LCD CONTROLLER DRIVER LCD RAM ADDRESS AREA RAM addresses of bank 2 are used as LCD data
227. of an increment or decrement a skip signal is generated and a skip is executed However the carry flag value is unaffected The instructions BTST BTSF and CPSE also generate a skip signal and execute a skip when they meet a skip condition and the carry flag value is also unaffected ELECTRONICS 5 5 SAM47 INSTRUCTION SET S3C72P9 P72P9 Preliminary Spec INSTRUCTIONS WHICH AFFECT THE CARRY FLAG The only instructions which do not generate a skip signal but which do affect the carry flag are as follows ADC LDB C operand SBC BAND C operand SCF BOR C operand RCF BXOR C operand CCF IRET RRC ADC AND SBC INSTRUCTION SKIP CONDITIONS The instructions ADC A HL and SBC A HL can generate skip signal and set or clear the carry flag when they are executed in combination with the instruction ADS A im If an ADS A im instruction immediately follows an ADC A HL or SBC A HL instruction in a program sequence the ADS instruction does not skip the instruction following ADS even if it has a skip function If however an ADC A HL SBC A HL instruction is immediately followed by an ADS A im instruction the ADC or SBC skips on overflow or if there is no borrow to the instruction immediately following the ADS and program execution continues Table 5 3 contains additional information and examples of the ADC A HL and SBC A HL skip feature Table 5 3 Skip Conditions for ADC and SBC Instructions Sa
228. on Set Features eed e ERR eee ere tetas Deh Iden Reden ntes 5 1 Instruction Reference 5 2 Reducing Instruction 5 3 Flexible Bit Manipulations Ghats eet 5 5 Instructions Which have Skip 5 5 Instructions Which Affect the Carry 5 6 ADC and SBC Instruction Skip Conditions sese 5 6 Conventions ec Loi tci 5 7 aBr s 5 8 Calculating Additional Machine Cycles for 5 8 High Level SUMIMANY veces uicti re e 5 9 5 14 Instruction Descriptions 1 reir p aerei E PD EE Ueber e PUR ERES 5 25 vi S3C72P9 P72P9 MICROCONTROLLER Table of Contents continued Part 11 Hardware Descriptions Chapter 6 Oscillator Circuits iR ii dE e PCR nU e d e e ERE eR e D o edm 6 1 Main System Oscillator 7 6 3 Sub System Oscillator Circults 6 3 Power Control Register PCON eh nre 6 4 Instruction
229. onnected to the SMDS2 SMDS2 m UN L No Connection 100 Pin Connector SMDS2 SMDS2 Set switch to TAL EVA Chip when s Vai 2 Mira S3E72P0 as a standalone unit and is not connected to the SMDS2 SMDS2 Table 17 4 Using Single Header Pins as the Input Path for External Trigger Sources Target Board Part Comments External Triggers Em Target Board Connector from External Trigger Sources of the Application System You can connect an external trigger source to one of the two external trigger channels CH1 or CH2 for the SMDS2 breakpoint and trace functions IDLE LED This LED is ON when the evaluation S3E72P0 is in idle mode STOP LED This LED is ON when the evaluation S3E72P0 is in stop mode ELECTRONICS 17 5 SEG4 SEG2 SEGO P0 0 S CK KO P0 2 SI K2 VDD XOUT TEST XT OUT P1 0 INTO P1 2 INT2 P2 0 CLO P2 2 LCDSY P3 1 TCLO1 P3 3 TCL1 COM1 COM5 P4 1 COM9 P4 3 COM11 P5 1 COM13 P5 3 COM15 17 6 KH 2 5 9 U 5 5 5 DEVELOPMENT TOOLS 1 1029 0 09 SEG3 SEG1 VLC5 VLC3 VLC1 P0 1 SO K1 PO 3 BUZ KS Vss XIN XTIN RESET P1 1 INT1 1 4 P2 1 LCDCK P3 0 TCLOO P3 2 TCLO COMO COM2 COM6 P4 0 COM8 P4 2 COM10 P5 0 COM12 P5 2 COM14 P6 0 SEG55 K4 P6 1 SEG54 K5 P6 3 SEG52 K7 P7 1 SEG50 P7 3 SEG48 P8 1 SEG46 P8 3 SEG44
230. ontrast control function OTP The S3C72P9 microcontroller is also available in OTP One Time Programmable version S8P72P9 S3P72P9 microcontroller has an on chip 32K byte one time programmable EPROM instead of masked ROM The S3P72P9 is comparable to 3 72 9 both in function and in pin configuration ELECTRONICS 1 1 PRODUCT OVERVIEW FEATURES Memory e 1 056 x 4 bit RAM excluding LCD display RAM e 32 768 x 8 bit ROM 39 I O Pins 35 pins e nput only 4 pins LCD Controller Driver 56 segments 16 common terminals e 8 12 and 16 common selectable e Internal resistor circuit for LCD bias All dot can be switched on off LCD contrast control by software 8 bit Basic Timer interval timer functions Watch dog timer 8 bit Timer Counter Programmable 8 bit timer External event counter Arbitrary clock frequency output External clock signal divider e Serial I O interface clock generator 16 Bit Timer Counter Programmable 16 bit timer e External event counter Arbitrary clock frequency output e External clock signal divider 8 bit Serial I O Interface e 8 bit transmit receive mode e 8 bit receive mode e LSB first or MSB first transmission selectable Internal or external clock source Memory Mapped I O Structure Data memory bank 15 S3C72P9 P72P9 Preliminary Spec Watch Timer e Time interval generation 0 5 s 3 9 ms at 32768 Hz 4
231. p Leaded CCR 3 58 2 6 0 MHz 3 3 2 0 5 5 On chip SMD NOTES 1 Please specify normal oscillator frequency 2 On chip C 30pF built in 3 On chip C 38pF built in TDK Table 14 5 LCD Contrast Controller Characteristics TA 40 85 C 4 5V to 5 5 V Peson Voltage Accuracy Max Output Voltage Vics LCNST 8FH 14 6 ELECTRONICS 557 22532 22532 Preliminary Spec ELECTRICAL DATA Table 14 6 Subsystem Clock Oscillator Characteristics TA 40 85 C 1 8V to 5 5 V Clock Parameter Test Condition Typ Configuration Crystal XTIN XTouT Oscillation 32 32 768 35 kHz Oscillator frequency 1 T Stabilization ime 2 Vpp 2 7 V to 5 5 V 2 5 External XTiN XTour XT jy input 32 100 kHz Clock frequency 1 XT jy input high and low 5 15 us level width tyTH NOTES 1 Oscillation frequency and XT yy input frequency data are for oscillator characteristics only 2 Stabilization time is the interval required for oscillating stabilization after a power on occurs Table 14 7 Input Output Capacitance Ty 25 C 0 V Input CN f 1 MHz Unmeasured pins Capacitance are returned to Vac Output Cour Capacitance Capacitance ELECTRONICS 14 7 ELECTRICAL DATA 57 22532 22532 Preliminary Spec Table 14 8 A C Electrical Characteristics Ta 40 to 85 C
232. p Idle mode is initiated by the IDLE instruction and stop mode by the instruction STOP Several NOP instructions must always follow an IDLE or STOP instruction in a program In idle mode the CPU clock stops while peripherals and the oscillation source continue to operate normally When RESET occurs during normal operation or during a power down mode a reset operation is initiated and the CPU enters idle mode When the standard oscillation stabilization time interval 31 3 ms at 4 19 MHz has elapsed normal CPU operation resumes In stop mode main system clock oscillation is halted assuming it is currently operating and peripheral hardware components are powered down The effect of stop mode on specific peripheral hardware components CPU basic timer serial I O timer counters 0 and 1 watch timer and LCD controller and on external interrupt requests is detailed in Table 8 1 Idle or stop modes are terminated either by a RESET or by an interrupt which is enabled by the corresponding interrupt enable IEx When power down mode is terminated by RESET a normal reset operation is executed Assuming that both the interrupt enable flag and the interrupt request flag are set to 1 power down mode is released immediately upon entering power down mode When an interrupt is used to release power down mode the operation differs depending on the value of the interrupt master enable flag IME Ifthe IME flag 0 If the po
233. p 1 Ports 0 2 4 26 PMG2 Port I O Mode Flags Group 2 Ports 3 4 27 PMG3 Port I O Mode Flags Group 3 Ports 4 5 4 28 PMG4 Port I O Mode Flags Group 4 Ports 6 7 4 29 PMG5 Port I O Mode Flags Group 5 Ports 8 9 4 30 PNE 1 N Channel Open Drain Mode Register 1 4 31 PNE 2 N Channel Open Drain Mode Register 2 4 32 PSW Program Status 4 33 PUMOD1 Pull up Resistor Mode Register 1 4 34 PUMOD2 Pull up Resistor Mode Register 2 4 35 SCMOD System Clock Mode Control Register 4 36 SMOD Serial Mode Register essen 4 37 TMODO Timer Counter 0 Mode Register 2 4 38 TMOD1 Timer Counter 1 Mode 4 39 TOE Timer Output Enable Flag Register eee 4 40 WDFLAG Watchdog Timer s Counter Clear Flag 4 41 WDMOD Watchdog Timer Mode Register 4 42 WMOD Watch Timer Mode 4 43 xxii 3 72 9 72 9 MICROCONTROLLER List of Instruction Descriptions Instruction Full Instruction Name Page Mnemonic Number
234. pped I O addresses To make it easier to reference the data memory area has six memory banks bank 0 bank 1 bank 2 bank 3 bank 4 and bank 15 The select memory bank instruction SMB is used to select the bank you want to select as working data memory Data stored in RAM locations are 1 4 and 8 bit addressable Initialization values for the data memory area are not defined by hardware and must therefore be initialized by program software following power RESET However when RESET signal is generated in power down mode the most of data memory contents are held ELECTRONICS 2 7 ADDRESS SPACES Working Registers 32 x 4 Bits General purpose Registers and Stack Area 224 x 4 Bits General purpose Registers 256 x 4 Bits LCD Data Registers 224 x 4Bits General purpose Registers 32 x 4 Bits General purpose Registers 256 x 4 Bits General purpose Registers 256 x 4 Bits Memory mapped I O Address Registers 128 x 4 Bits Figure 2 3 Data Memory RAM Map 2 8 S3C72P9 P72P9 Preliminary Spec ELECTRONICS 3 72 9 72 9 Preliminary Spec ADDRESS SPACES Memory Banks 0 1 2 3 4 and 15 Bank 0 000 The lowest 32 nibbles of bank 0 000H 01FH used as working registers the next 224 nibbles 020H 0FFH can be used both as stack area and as general purpose data memory Use the stack area for implementing subroutine calls and returns and for interrupt processing Bank
235. r 8 bit ELECTRONICS Figure 4 1 Register Description Format 4 7 MEMORY MAP S3C72P9 P72P9 Preliminary Spec BMOD Basic Timer Mode Register BT F85H Bit 3 2 1 0 RESET Value 0 0 0 0 Read Write W W W W Bit Addressing 1 4 4 4 4 BMOD 3 Basic Timer Restart Bit Restart basic timer then clear IRQB flag BCNT and BMOD 3 to logic zero BMOD 2 0 Input Clock Frequency and Interrupt Interval Time Input clock frequency fxx 212 1 02 kHz Interrupt interval time wait time 220 250 ms Input clock frequency fxx 29 8 18 kHz Interrupt interval time wait time 217 fxx 31 3 ms Input clock frequency fxx 2 32 7 kHz 1 1 Interrupt interval time wait time 215 7 82 ms 1 1 1 Input clock frequency fxx 25 131 kHz Interrupt interval time wait time 213 fxx 1 95 ms NOTES 1 When aRESET occurs the oscillator stabilization wait time is 31 3 ms 217 at 4 19 MHz 2 fxx is the system clock rate given a clock frequency of 4 19 MHz 4 8 ELECTRONICS 3 72 9 72 9 Preliminary Spec MEMORY MAP CLMOD clock Output Mode Register CPU FDOH Bit 3 2 1 0 RESET Value 0 0 0 0 Read Write Bit Addressing 4 4 4 4 CLMOD 3 Enable Disable Clock Output Control Bit EN Disable clock output at the CLO pin Enable clock output at the CLO pin CLMOD 2 Bit 2 ES Always logic zero CLMOD 1 0 Clock Source and Frequency Selection Control Bits or fxt 4 1 Select system clock fxx 8 524
236. rating parameters including Typicals must be validated for each customer application by the customer s technical experts Samsung products are not designed intended or authorized for use as components in systems intended for surgical implant into the body for other applications intended to support or sustain life or for any other application in which the failure of the Samsung product could create a situation where personal injury or death may occur Should the Buyer purchase or use a Samsung product for any such unintended or unauthorized application the Buyer shall indemnify and hold Samsung and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages expenses and reasonable attorney fees arising out of either directly or indirectly any claim of personal injury or death that may be associated with such unintended or unauthorized use even if such claim alleges that Samsung was negligent regarding the design or manufacture of said product All rights reserved No part of this publication may be reproduced stored in a retrieval system or transmitted in any form or by any means electric or mechanical by photocopying recording or otherwise without the prior written consent of Samsung Electronics Samsung Electronics microcontroller business has been awarded full ISO 14001 certification BSI Certificate No FM24653 All semiconductor products are designed and manufa
237. rect data memory contents to A ARa Load register contents to Load 4 bit immediate data to register 2 2 42 RRb EA Load contents of EA to register HL EA Load contents of EA to indirect data memory contents and skip on carry register L contents and skip on carry _____ Push register pair omo sack 2 42 2 5 1 1 1 1 1 1 1 1 1 1 2 1 Pop to register pair from stack Pop SMB and SRB values from stack 2 ELECTRONICS 5 11 SAM47 INSTRUCTION SET S3C72P9 P72P9 Preliminary Spec Table 5 12 Logic Instructions High Level Summary 2 2 Logical AND A immediate data to A Logical AND A indirect data memory to A Logical AND register pair RR to EA Logical AND EA to register pair RRb Logical OR immediate data to A Logical OR indirect data memory contents to A Logical OR double register to EA Logical OR EA to double register Exclusive OR immediate data to A Exclusive OR indirect data memory to A Exclusive OR register pair RR to EA Exclusive OR register pair RRb to EA 1 2 2 2 1 2 2 2 1 2 2 eem Add indirect data memory to A with carry Add register pair RR to EA with carry Add EA to register pair RRb with carry Add 4 bit immediate data to A and skip on carry EA imm Add 8 bit immediate data to EA and skip on carry A Add indirect data memory to A and skip on carry EA RR Add register pair RR conten
238. red interrupt such as INTO and INTTO is not used the unused vector interrupt locations must be skipped with the assembly instruction ORG so that jumps will address the correct locations ORG VENTO VENT1 ORG VENT3 VENT4 ORG VENT6 VENT7 ORG ELECTRONICS 0000H 1 0 RESET 0 0 INTB 0006H 0 0 INT1 0 0 INTS 000CH 0 01 1 0 0 INTK 0010H lt 1 ERB lt 0 Jump to RESET address by RESET lt 0 ERB lt 0 Jump to INTB address by INTB INTO interrupt not used lt 0 ERB lt 0 Jump to INT1 address by INT1 lt 0 ERB lt 0 Jump to INTS address by INTS INTTO interrupt not used lt 0 ERB lt 0 Jump to INTT1 address by lt 0 ERB lt 0 Jump to address by 2 3 ADDRESS SPACES S3C72P9 P72P9 Preliminary Spec PROGRAMMING Defining Vectored Interrupts Continued 3 If an INTO interrupt is not used and if its corresponding vector interrupt area is not fully utilized or if it is not written by a ORG instruction as in Example 2 a CPU malfunction will occur ORG 0000H VENTO 1 0 RESET lt 1 ERB lt 0 Jump to RESET address by RESET VENT1 0 0 INTB lt 0 ERB lt 0 Jump to INTB address by INTB VENT3 0 0 INT1 0 ERB lt 0 Jump to INT1 address by INTO VENT4 0 0 INTS lt 0 ERB lt 0 Jump to INTS address by INT1 VENT5 0 0 INTTO lt 0 ERB lt 0 Jump to INT
239. reference register compared to the TCNT1 value When TCNT1 TREF1 the TC1 output latch TOL1 is inverted and an interrupt request is generated to signal the interval or event The TREF1 value together with the TMOD1 clock frequency selection determines the specific TC1 timer interval Use the following formula to calculate the correct value to load to the TREF1 reference register 1 TMOD 1 frequency setting TC1 timer interval TREF1 value 1 x TREF1 value 0 TC1 OUTPUT ENABLE FLAG TOE1 The 1 bit timer counter 1 output enable flag TOE1 flag controls output from timer counter 1 to the TCLO1 pin TOE1 is addressable by 1 bit read and write instructions Bit 3 Bit 2 Bit 1 Bit 0 NOTE The U means that the bit is undefined When you set the TOE1 flag to 1 the contents of can be output to the TCLO1 pin Whenever a RESET occurs TOE1 is automatically set to logic zero disabling all TC1 output TC1 OUTPUT LATCH TOL1 TOL1 is the output latch for timer counter 1 When the 16 bit comparator detects a correspondence between the value of the counter register TCNT1 and the reference value stored in the TREF1 register the TOL1 logic toggles high to low or low to high Whenever the state of TOL1 is switched the TC1 signal exits the latch for output TC1 output is directed if TOE1 1 to the TCLO1 pin at I O port 3 1 When timer counter 1 is started TMOD1 3 0 the contents of the output latch are cleared
240. remented by six and points to the next free stack location IRET Instructions The end of an interrupt sequence is signaled by the instruction IRET IRET references the SP to locate the six 4 bit stack addresses used for the interrupt and to write this data back to the PC and the PSW After the IRET has executed the SP is incremented by six and points to the next free stack location POP RET or SRET IRET SP SP 2 SP lt SP 6 SP 5 6 Upper Register 14 12 PCO 11 8 q lt 9 14 12 n v 54 lt PCO wo 7 4 1 v wo 7 PC4 p lt 0 ERB PSW 0 0 n 79 A 49 U 4 v v 79 Figure 2 8 Stack Operations ELECTRONICS 2 17 ADDRESS SPACES S3C72P9 P72P9 Preliminary Spec BIT SEQUENTIAL CARRIER BSC The bit sequential carrier BSC is a 16 bit general register that can be manipulated using 1 4 and 8 bit RAM control instructions RESET clears all BSC bit values to logic zero Using the BSC you can specify sequential addresses and bit locations using 1 bit indirect addressing nemb L Bit addressing is independent of the current EMB value In this way programs can process 16 bit data by moving the bit location sequentially and then incrementing or decrementing the value of
241. remented each time an incoming clock signal is detected that matches the signal edge and frequency setting of the TMOD1 register specifically TMOD1 6 TMOD1 5 and TMOD1 4 Each time TCNT1 is incremented the new value is compared to the reference value stored in the TC1 reference register TREF1 When TCNT1 TREF1 an overflow occurs in the TCNT1 register the interrupt request flag IRQT1 is set to logic one and an interrupt request is generated to indicate that the specified timer counter interval has elapsed Reference Value n GHENA DRM DRE Match Timer Start Instruction IRQT1 Set IRQT1 Set TMOD1 3 is set Figure 11 5 TC1 Timing Diagram ELECTRONICS 11 31 TIMERS and TIMER COUNTERS S3C72P9 P72P9 Preliminary Spec TC1 REFERENCE REGISTER TREF1 The TC1 reference register is a 16 bit write only register that is mapped to RAM locations FA9H FA8H TREF1A and FABH FAAH TREF1B It is addressable by 8 bit RAM control instructions RESET clears the TREF1 value to FFFFH TREF1 is used to store a reference value to be compared to the incrementing TCNT1 register in order to identify an elapsed time interval Reference values will differ depending upon the specific function that TC1 is being used to perform as a programmable timer counter event counter clock signal divider or arbitrary frequency output source During timer counter operation the value loaded into the
242. rmines the time interval also referred to as wait time required to stabilize clock signal oscillation when stop mode is released by an interrupt When a RESET signal is inputted the standard stabilization interval for system clock oscillation following the RESET is 31 3 ms at 4 19 MHz Table 11 1 Basic Timer Register Overview Register Type Description RAM Addressing Reset Name Address Mode Value BMOD Control Controls the clock frequency mode 4 bit F85H 4 bit write only of the basic timer also the BMOD 3 1 bit oscillation stabilization interval after writeable stop mode release or RESET BONT Counter Counts clock pulses matching the F86H F87H 8 bit read only U note BMOD frequency setting WDMOD Controls watchdog timer operation F98H F99H 8 bit write WDTCF Clears the watchdog timer s counter F9AH 3 NOTE U means the value is undetermined after aRESET ELECTRONICS 11 3 TIMERS and TIMER COUNTERS S3C72P9 P72P9 Preliminary Spec Clear Signal Clear BITS gt IRQB Instruction Interrupt Clock Overflow Request Selector BONT CPU Clock Start Signal Clock Input Power Down Release 1 Pulse Period BT Input Clock 2 1 2 Duty 3 Bit Counter Overflow Reset Signal Generation WAIT note Stop Clear BITS RESET Instruction NOTES 1 WAIT means stabilization time after RESET or stabilization time after STOP mode release 2 The RESET signal can be generated if t
243. routines at any location by referencing a call address that is stored in the look up table If necessary a REF instruction can be circumvented by means of a skip operation prior to the REF in the execution sequence In addition the instruction immediately following a REF can also be skipped by using an appropriate reference instruction or instructions Two byte instruction can be referenced by using a REF instruction An exception is XCH A DA If the MSB value of the first one byte instruction in the reference area is 0 the instruction cannot be referenced by a REF instruction Therefore if you use REF to reference two 1 byte instruction stored in the reference area specific combinations must be used for the first and second 1 byte instruction These combination examples are described in Table 5 1 Table 5 1 Valid 1 Byte Instruction Combinations for REF Look Ups First 1 Byte Instruction Second 1 Byte Instruction instruction Operand Instruction Operana R A im INCS note INCS RRb DECS note R LD RRa INCS note R INCS LD HL A INCS note INCS NOTE The MSB value of the instruction is 0 5 2 ELECTRONICS S3C72P9 P72P9 Preliminary Spec SAM47 INSTRUCTION SET REDUCING INSTRUCTION REDUNDANCY When redundant instructions such as LD A im and LD EA imm are used consecutively in a program sequence only the first instruction is executed The redundant instructions which follow are ignored tha
244. rry flag and save the result to the carry flag INTn 2 Save carry flag to stack with other PSW bits IRET Restore carry flag from stack with other PSW bits NOTES 1 The operand has three bit addressing formats mema a memb L and OH DA b 2 INTn refers to the specific interrupt being executed and is not an instruction Invert carry flag value complement carry flag ELECTRONICS 2 23 ADDRESS SPACES S3C72P9 P72P9 Preliminary Spec PROGRAMMING Using the Carry Flag as a 1 Bit Accumulator 1 Set the carry flag to logic one SCF 1 LD EA 0C3H EA e 0C3H LD HL 0AAH HL lt 0AAH ADC EA HL EA e 0C3H lt 1 2 Logical AND bit 3 of address 3FH with P3 3 and output the result to P5 0 LD H 3H Set the upper four bits of the address to the H register value LDB C H 0FH 3 bit 3 of 3FH BAND C P3 3 C AND P3 3 LDB P5 0 C Output result from carry flag to P5 0 2 24 ELECTRONICS S3C72P9 P72P9 Preliminary Spec ADDRESSING MODES ADDRESSING MODES OVERVIEW The enable memory bank flag EMB controls the two addressing modes for data memory When the EMB flag is set to logic one you can address the entire RAM area when the EMB flag is cleared to logic zero the addressable area in the RAM is restricted to specific locations The EMB flag works in connection with the select memory bank instruction SMBn You will recall that the SMBn inst
245. ruction SCF sets the carry flag to logic one ELECTRONICS 5 87 SAM47 INSTRUCTION SET S3C72P9 P72P9 Preliminary Spec SMB select Memory Bank SMB n Description SMB instruction sets the upper four bits of a 12 bit data memory address to select a specific memory bank The constants 0 n and 15 are usually used as the SMB operand to select the corresponding memory bank All references to data memory addresses fall within the following address ranges Please note that since data memory spaces differ for various devices in the SAM4 product family the n value of the SMB instruction will also vary 01 Working registers O20H OFFH si OFFH Stack and general purpose registers nOOH nFFH General purpose registers 14 MON i 14 F80H FFFH l O mapped hardware registers The enable memory bank EMB flag must always be set to 1 in order for the SMB instruction to execute successfully for memory banks 0 15 Format Binary Code Operation Notation n g Fo 119 o s e ar Example If the EMB flag is set the instruction SMB 0 selects the data memory address range for bank 0 000H OFFH as the working memory bank NOTE The number of memory balk selected by SMB may change for different devices the SAM47 product family 5 88 ELECTRONICS S3C72P9 P72P9 Preliminary Spec SAM47 INSTRUCTION SET SRB select Register Bank SRB n Operation Operation Summary B
246. ruction is used to select RAM bank 0 1 2 3 4 or 15 The SMB setting is always contained in the upper four bits of a 12 bit RAM address For this reason both addressing modes EMB 0 and EMB 1 apply specifically to the memory bank indicated by the SMB instruction and any restrictions to the addressable area within banks 0 1 2 8 4 or 15 Direct and indirect 1 bit 4 bit and 8 bit addressing methods can be used Several RAM locations are addressable at all times regardless of the current EMB flag setting Here are a few guidelines to keep in mind regarding data memory addressing When you address peripheral hardware locations in bank 15 the mnemonic for the memory mapped hardware component can be used as the operand in place of the actual address location Always use an even numbered RAM address as the operand in 8 bit direct and indirect addressing With direct addressing use the RAM address as the instruction operand with indirect addressing the instruction specifies a register which contains the operand s address ELECTRONICS 3 1 ADDRESSING MODES S3C72P9 P72P9 Preliminary Spec Addressing DA Registers and Stack Bank 1 General SMB 1 SMB 1 Registers Working Registers Bank 0 General Bank 2 Display Registers SMB 2 SMB 2 amp General Registers HEN General Registers General Registers 1 SMB 15 SMB 15 Registers 1 X means don t care 2 Bl
247. ructions CALL instructions and interrupts In each case the SP is decremented by a number determined by the type of push operation and then points to the next available stack location PUSH Instructions A PUSH instruction references the SP to write two 4 bit data nibbles to the stack Two 4 bit stack addresses are referenced by the stack pointer one for the upper register value and another for the lower register After the PUSH has executed the SP is decremented by two and points to the next available stack location CALL Instructions When a subroutine call is issued the CALL instruction references the SP to write the PC s contents to six 4 bit stack locations Current values for the enable memory bank EMB flag and the enable register bank ERB flag are also pushed to the stack Since six 4 bit stack locations are used per CALL you may nest subroutine calls up to the number of levels permitted in the stack Interrupt Routines An interrupt routine references the SP to push the contents of the PC and the program status word PSW to the stack Six 4 bit stack locations are used to store this data After the interrupt has executed the SP is decremented by six and points to the next available stack location During an interrupt sequence subroutines may be nested up to the number of levels which are permitted in the stack area INTERRUPT PUSH CALL LCALL When INT is acknowledged After PUSH SP 2 After CALL or LCALL SP SP 6
248. ry Spec PRODUCT OVERVIEW Figure 1 10 Pin Circuit Type H 3 Pull up Resistor Enable COM SEG Output Disable Data Figure 1 11 Pin Circuit Type H 13 ELECTRONICS 1 11 PRODUCT OVERVIEW S3C72P9 P72P9 Preliminary Spec Figure 1 12 Pin Circuit Type H 15 Pull up Resistor Pull up Resistor M Enable SEG Type H 15 Output Disable Data Schmitt Trigger Figure 1 13 Pin Circuit Type H 16 1 12 ELECTRONICS 3 72 9 72 9 Preliminary Spec ADDRESS SPACES ADDRESS SPACES PROGRAM MEMORY ROM OVERVIEW ROM maps for S3C72P9 devices are mask programmable at the factory In its standard configuration the device s 32 768 x 8 bit program memory has three areas that are directly addressable by the program counter PC 16 byte area for vector addresses 96 byte instruction reference area 16 byte general purpose area 32 640 byte general purpose area General purpose Program Memory Two program memory areas are allocated for general purpose use One area is 16 bytes in size and the other is 32 640 bytes Vector Addresses A 16 byte vector address area is used to store the vector addresses required to execute system resets and interrupts Start addresses for interrupt service routines are stored in this area along with the values of the enable memory bank EMB and enable register bank ERB flags that are used to set their initial value for the corresponding
249. s S3C7 series microcontrollers The SASM57 takes a source file containing assembly language statements and translates into a corresponding source code object code and comments The SASM57 supports macros and conditional assembly It runs on the MS DOS operating system It produces the relocatable object code only so the user should link object file Object files can be linked with other object files and loaded into memory HEX2ROM HEX2ROM file generates ROM code from HEX file which has been produced by assembler ROM code must be needed to fabricate a microcontroller which has a mask ROM When generating the ROM code file by HEX2ROM the value is filled into the unused ROM area up to the maximum ROM size of the target device automatically TARGET BOARDS Target boards are available for all KS57 series microcontrollers All required target system cables and adapters are included with the device specific target board OTPs One time programmable microcontroller OTP for the S3C72P9 microcontroller and OTP programmer Gang are now available ELECTRONICS 17 1 DEVELOPMENT TOOLS 17 2 IBM PC AT or Compatible RS 232C SMDS2 gt PROM OTP Writer Unit lt gt Break Display Unit 5 lt gt Trace Timer Unit SAM4 Base Unit gt Power Supply Unit S3C72P9 P72P9 Preliminary Spec Target Application System Probe Adapter TB72P9 Target Board EVA Chip Figure 17 1 SMDS Produc
250. s are executed in the same register bank When the routines have executed successfully you can restore the register contents from the stack to working memory using the POP instruction ELECTRONICS 2 13 ADDRESS SPACES S3C72P9 P72P9 Preliminary Spec PROGRAMMING Selecting the Working Register Area The following examples show the correct programming method for selecting working register area 1 When ERB 0 VENT2 INTO PUSH SRB PUSH PUSH PUSH PUSH SMB LD LD LD INCS LD LD POP POP POP POP POP IRET 1 0 INTO SB 2 HL WX YZ EA 0 EA 00H 80H EA HL 40H HL WX EA YZ EA EA YZ WX HL SB EMB lt 1 ERB lt 0 Jump to INTO address PUSH current SMB SRB Instruction does not execute because ERB 0 PUSH HL register contents to stack PUSH WX register contents to stack PUSH YZ register contents to stack PUSH EA register contents to stack POP EA register contents from stack POP YZ register contents from stack POP WX register contents from stack POP HL register contents from stack POP current SMB SRB The POP instructions execute alternately with the PUSH instructions If an SMB n instruction is used in an interrupt service routine a PUSH and POP SB instruction must be used to store and restore the current SMB and SRB values as shown in Example 2 below 2 When ERB 1 VENT2 INTO PUSH SRB SMB LD LD LD INCS LD LD POP IRET 1 1 INTO
251. set may change for different devices in the SAM4 product family 4 Theinterrupt names and the interrupt numbers used in the instruction set may change for different devices in the SAM 47 product family ELECTRONICS 5 1 SAM47 INSTRUCTION SET S3C72P9 P72P9 Preliminary Spec INSTRUCTION REFERENCE AREA Using the 1 byte REF Reference instruction you can reference instructions stored in addresses 0020H 007FH of program memory the REF instruction look up table The location referenced by REF may contain either two 1 byte instructions or a single 2 byte instruction The starting address of the instruction being referenced must always be an even number 3 byte instructions such as JP or CALL may also be referenced using REF To reference these 3 byte instructions the 2 byte pseudo commands TJP and TCALL must be written in the reference instead of JP and CALL The PC is not incremented when a REF instruction is executed After it executes the program s instruction execution sequence resumes at the address immediately following the REF instruction By using REF instructions to execute instructions larger than one byte as well as branches and subroutines you can reduce program size To summarize the REF instruction can be used in three ways Using the 1 byte REF instruction to execute one 2 byte or two 1 byte instructions Branching to any location by referencing a branch address that is stored in the look up table Calling sub
252. seudo instructions that are used only to specify the reference area 1 When the reference area is specified by the TJP instruction memc 7 6 00 PC13 0 lt 5 0 1 7 0 2 When the reference area is specified by the TCALL instruction memc 7 6 01 5 1 SP 2 lt EMB ERB SP 3 SP 4 lt PC7 0 SP 5 SP 6 lt PC13 8 SP lt SP 6 PC13 0 lt memc 5 0 memc 1 7 0 When the reference area is specified by any other instruction the memc and memc 1 instructions are executed Instructions referenced by REF occupy 2 bytes of memory space for two 1 byte instructions or one 2 byte instruction and must be written as an even number from 0020H to 007FH in ROM In addition the destination address of the TJP and TCALL instructions must be located with the 3FFFH address TJP and TCALL are reference instructions for JP JPS and CALL CALLS If the instruction following a REF is subject to the redundancy effect the redundant instruction is skipped If however the REF follows a redundant instruction it is executed On the other hand the binary code of a REF instruction is 1 byte The upper 4 bits become the higher address bits of the referenced instruction and the lower 4 bits of the referenced instruction becomes the lower address producing a total of 8 bits or 1 byte see Example 3 below NOTE Ifthe MSB value of the first one byte binary code in instruction is 0 the instruction cannot be
253. signal in the mode register SMOD Set SIO interrupt enable flag IES to 1 Initiate SIO transmission by setting bit 3 of the SMOD to 1 When the SIO operation is complete IRQS flag is set and an interrupt is generated oa fF oO gt ELECTRONICS 13 1 SERIAL INTERFACE IRQS PO OSCK TOLO gt CPU CLK S3C72P9 P72P9 Preliminary Spec 2 2 SO SBUF 8 bit gt Over Flow Selector Clear gt IN mu SMOD 7 SMOD 6 SMOD 5 EN SMOD 3 SMOD 2 SMOD 1 SMOD 0 8 BITS nete Internal Bus NOTE Instruction Execution Figure 13 1 Serial I O Interface Circuit Diagram ELECTRONICS S3C72P9 P72P9 Preliminary Spec SERIAL I O INTERFACE SERIAL MODE REGISTER SMOD The serial mode register SMOD is an 8 bit register that specifies the operation mode of the serial interface Its reset value is logical zero SMOD is organized in two 4 bit registers as follows SMOD register settings enable you to select either MSB first or LSB first serial transmission and to operate in transmit and receive mode or receive only mode SMOD is a write only register and can be addressed only by 8 bit RAM control instructions One exception to this is SMOD 3 which can be written by a 1 bit RAM control instruction When SMOD 3 is set to 1 the contents of the serial interface interrupt request flag IRQS and the 3 bit serial clock counter are cleared and SIO
254. ster pair HL the value and the carry flag is cleared to 0 RCF lt ADC EA HL EA 6DH lt 1 JPS XXX Jump to XXX no skip after ADC 5 26 ELECTRONICS S3C72P9 P72P9 Preliminary Spec ADC Add with Carry ADC Continued SAM47 INSTRUCTION SET Examples 3 If ADC A HL is followed an ADS the ADC skips on carry to the instruction immediately after the ADS An ADS instruction immediately after the ADC does not skip even if an overflow occurs This function is useful for decimal adjustment operations 8 9 decimal addition the contents of the address specified by the HL register is 9H RCF LD ADS ADC ADS JPS A 8H A 6H A HL A 0AH XXX C 0 lt 8H lt 8H 6H lt OEH 9H C 0 lt 1 Skip this instruction because C 1 after ADC result b 3 4 decimal addition the contents of the address specified by the HL register is 4H RCF LD ADS ADS JPS ELECTRONICS A 3H A 6H A HL A 0AH C e 0 A lt lt 3H 6H lt C 0 No skip lt 7H The skip function for ADS A im is inhibited after an ADC A QHL instruction even if an overflow occurs 5 27 SAM47 INSTRUCTION SET S3C72P9 P72P9 Preliminary Spec ADS Add and Skip on Overflow ADS dst src Add 4 bit immed
255. stop mode LCD off I 6 6 ELECTRONICS S3C72P9 P72P9 Preliminary Spec OSCILLATOR CIRCUITS Table 6 4 Main Sub Oscillation Stop Mode Main Main oscillator runs Oscillation Sub oscillator runs STOP Mode stops System clock is the main oscillation clock STOP instruction Main oscillator stops CPU is in idle mode Sub oscillator still runs stops Interrupt and RESET After releasing stop mode main oscillation starts and oscillation stabilization time is elapsed And then the CPU operates Oscillation stabilization time is 1 256 x BT clock fx When SCMOD 3 is set to 1 1 main oscillator stops halting the CPU operation RESET Interrupt can t start the main oscillation Therefore the CPU operation can never Main oscillator runs Sub oscillator runs System clock is the sub oscillation clock Sub oscillator still runs stops STOP instruction Main oscillator stops CPU is in idle mode Sub oscillator still runs be restarted BT overflow interrupt and RESET After the overflow of basic timer 1 256 x BT clock fxt CPU operation and main oscillation automatically start stops Sub oscillator still runs When SCMOD 3 is set to 1 main oscillator stops The CPU however would still operate Sub oscillator still runs When SCMOD 2 to 1 sub oscillator stops while main oscillator and the CPU would still operate When SCMOD 2 to
256. t Configuration SMDS2 ELECTRONICS S3C72P9 P72P9 Preliminary Spec DEVELOPMENT TOOLS TB72P9 TARGET BOARD The TB72P9 target board is used for the S3C79P9 microcontroller It is supported by the SMDS2 development system TB72P9 To User Vcc Stop Idle 74 11 2 B XTAL O O MDS O O o 160 S3E72P0 EVA Chip 50 Pin Connector 50 Pin Connector External Triggers che SM1255A Figure 17 2 TB72P9 Target Board Configuration ELECTRONICS 17 3 DEVELOPMENT TOOLS S3C72P9 P72P9 Preliminary Spec Table 17 1 Power Selection Settings for TB72P9 To User Vcc Settings To User Vcc Operating Mode TB72P9 Vcc gt Vss gt To User Vcc External TB72P9 Vcc Vss gt Comments The SMDS2 SMDS2 supplies Vcc to the target board evaluation chip and the target system The SMDS2 SMDS2 supplies Vcc only to the target board evaluation chip The target system must have its own power supply Table 17 2 Main Clock Selection Settings for TB72P9 Main Clock Setting Operating Mode EVA Chip S3E72P0 XOUT XIN lt No Connection 100 Pin Connector SMDS2 SMDS2 EVA Chip S3E72P0 4 XOUT XIN XTAL Target Board 17 4 Comments Set the Xy switch to MDS when the target board is connected to the SMDS2 SMDS2 Set the Xy switch to XTAL when
257. t is they are handled like a NOP instruction When LD HL imm instructions are used consecutively redundant instructions are also ignored In the following example only LD A im instruction will be executed The 8 bit load instruction which follows it is interpreted as redundant and is ignored LD Load 4 bit immediate data im to accumulator LD EA imm Load 8 bit immediate data imm to extended accumulator In this example the statements LD A 2H and LD A 3H are ignored BITR EMB LD Execute instruction LD A 2H Ignore redundant instruction LD A 3H Ignore redundant instruction LD 23H A Execute instruction 023H lt 1 If consecutive LD HL imm instructions load 8 bit immediate data to the 8 bit memory pointer pair HL are detected only the first LD is executed and the LDs which immediately follow are ignored For example LD HL 10H HL lt 10H LD HL 20H Ignore redundant instruction LD A 3H LD EA 35H Ignore redundant instruction LD HL A 10H 3H If an instruction reference with a REF instruction has a redundancy effect the following conditions apply Ifthe instruction preceding the REF has a redundancy effect this effect is cancelled and the referenced instruction is not skipped Ifthe instruction following the REF has a redundancy effect the instruction following the REF is skipped ELECTRONICS 5 3 SAM47 INSTRUCTION SET S3C72P
258. t number 4 5 6 7 8 9 X O gt gt PURx gt PURx 0 PMx 1 PMx 2 O PMx 3 o NOTE When port pin serves as an output its pull up resistor is automatically disabled even though the port s pull up resistor is enabled by bit settings in the pull up resistor mode register PUMOD Port 6 is a schmitt trigger input Figure 10 5 Ports 4 5 6 7 8 and 9 Circuit Diagram ELECTRONICS 10 9 PORTS S3C72P9 P72P9 Preliminary Spec NOTES 10 10 ELECTRONICS S3C72P9 P72P9 Preliminary Spec TIMERS and TIMER COUNTERS 1 1 TIMERS and TIMER COUNTERS OVERVIEW The S3C72P9 microcontroller has four timer and timer counter modules 8 bit basic timer BT 8 bit timer counter TCO 16 bit timer counter TC1 Watch timer WT The 8 bit basic timer BT is the microcontroller s main interval timer and watch dog timer It generates an interrupt request at a fixed time interval when the appropriate modification is made to its mode register The basic timer is also used to determine clock oscillation stabilization time when stop mode is released by an interrupt and after a RESET The 8 bit timer counter TCO and the 16 bit timer counter TC1 are programmable timer counters that are used primarily for event counting and for clock frequency modification and output In addition TCO generates a clock signal that can be used by the serial I O interface
259. terval wDMOD _ Watchdog Timer Enable Disable Control Disable watchdog timer function Any other value Enable watchdog timer function WATCHDOG TIMER COUNTER WDCNT The watchdog timer counter WDCNT is a 3 bit counter WDCNT is automatically cleared to logic zero and restarts whenever the WDTCF register control bit is set to 1 RESET stop and wait signal clears the WDONT to logic zero also WDONT increments each time a clock pulse of the overflow frequency determined by the current BMOD bit setting is generated When WDCNT has incremented to hexadecimal 07H it is cleared to 00H and an overflow is generated The overflow causes the system RESET When the interrupt request is generated BCNT immediately resumes counting incoming clock signals WATCHDOG TIMER COUNTER CLEAR FLAG WDTCF The watchdog timer counter clear flag WDTCF is a 1 bit write instruction When WDTCF is set to one it clears the WDONT to zero and restarts the WDCNT WDTCF register bits 2 0 are always logic zero Table 11 3 Watchdog Timer Interval Time BMOD BT Input Clock WDT Interval Time 3 x000b 28 x 212 x 28 or 23 1 x 212 x 28 fxx 1 75 2 0 sec x011b 23 x 29 x 28 fxx or 23 1 x 29 x 28 fxx 218 7 250 ms x101b 23 x 27 x 28 fxx or 23 1 x 27 x 28 54 6 62 5 5 x111b 23 x 25 x 28 fxx or 23 1 x 25 28 fxx 13 6 15 6 ms NOTES 1 Clock frequencies assume a system oscillator clock frequency fx of 4 19 MHz 2 xx system c
260. the Carry Flag as a 1 Bit enne Chapter 3 Addressing Modes Initializing the and ERB Flags T Bit Addressing MOGeS ad eae vende Sa A qe ed 4 deg e ipe e ce vie e CE Cd 8 Bit Addressing Chapter 5 SAM47 Instruction Set Example of the Instruction Redundancy Chapter 6 Oscillator Circuits Setting the CPU Glock wii Switching Between Main System and Subsystem CPU Clock Output to the CLO Pin iesise perioade ennei ai Chapter 7 Interrupts Setting the INT Interrupt nennen nennen Using INTK as a Key Input Enabling the INT4 3C72P9 P72P9 MICROCONTROLLER Page Number xix List of Programming Tips Continued Description Page Number Chapter 8 Power Down Reducing Power Consumption for Key Input Interrupt 8 6 Chapter 10 I O Ports Configuring I O Ports to Input or 10 3 Enabling and Disabling I O Port Pull Up Resistors 10 4 Chapter 11 Timers and Timer Counters Using the Basie
261. the contents of the SMB register to and from the stack area during interrupts and subroutine calls ELECTRONICS 3 5 ADDRESSING MODES S3C72P9 P72P9 Preliminary Spec DIRECT AND INDIRECT ADDRESSING 1 bit 4 bit and 8 bit data stored in data memory locations can be addressed directly using a specific register or bit address as the instruction operand Indirect addressing specifies a memory location that contains the required direct address The KS57 instruction set supports 1 bit 4 bit and 8 bit indirect addressing For 8 bit indirect addressing an even numbered RAM address must always be used as the instruction operand 1 BIT ADDRESSING Table 3 2 1 Bit Direct and Indirect RAM Addressing Operand Addressing Mode EMB Flag Addressable Memory Hardware I O Notation Description Setting Area Bank Mapping DA b Direct bit is indicated by the 000H 07FH Banko RAM address DA memory F80H FFFH Bank 15 All 1 bit bank selection and specified addressable bit number b peripherals SMB 15 1 000H FFFH SMB 0 1 2 3 4 15 mema b Direct bit is indicated by ad X FBOH FBFH Bank 15 150 51 dressable area mema bit FFOH FFFH EMB ERB IEx number b IRQx Pn n memb L Indirect address is indicated X FCOH FFFH Bank 15 BSCn x by the upper 10 bits of RAM Pn n area memb and the upper two bits of register L and bit is indicated by the lower two bits of register L H DA b Indirect bit is indicated by the 0
262. the target board is used as a standalone unit and is not connected to the SMDS2 SMDS2 ELECTRONICS S3C72P9 P72P9 Preliminary Spec DEVELOPMENT TOOLS Table 17 3 Sub Clock Selection Settings for TB72P9 Sub Clock Setting Operating Mode Set the XTI switch to MDS xe when the target board is connected to the SMDS2 SMDS2 m UN L No Connection 100 Pin Connector SMDS2 SMDS2 Set switch to TAL EVA Chip when s Vai 2 Mira S3E72P0 as a standalone unit and is not connected to the SMDS2 SMDS2 Table 17 4 Using Single Header Pins as the Input Path for External Trigger Sources Target Board Part Comments External Triggers Em Target Board Connector from External Trigger Sources of the Application System You can connect an external trigger source to one of the two external trigger channels CH1 or CH2 for the SMDS2 breakpoint and trace functions IDLE LED This LED is ON when the evaluation S3E72P0 is in idle mode STOP LED This LED is ON when the evaluation S3E72P0 is in stop mode ELECTRONICS 17 5 SEG4 SEG2 SEGO P0 0 S CK KO P0 2 SI K2 VDD XOUT TEST XT OUT P1 0 INTO P1 2 INT2 P2 0 CLO P2 2 LCDSY P3 1 TCLO1 P3 3 TCL1 COM1 COM5 P4 1 COM9 P4 3 COM11 P5 1 COM13 P5 3 COM15 17 6 KH 2 5 9 U 5 5 5 DEVELOPMENT TOOLS 1 1029 0 09 SE
263. tiOn era eed rae ti den 5 91 VENT Load ERB and Vector 5 92 XCH Exchange or EA with Nibble or Byte 5 94 XCHD Exchange and 5 95 XCHI Exchange and 5 96 XOR Logical Exclusive e ES ete cient edes 5 97 xxiv 3C72P9 P72P9 MICROCONTROLLER S3C72P9 P72P9 Preliminary Spec PRODUCT OVERVIEW PRODUCT OVERVIEW OVERVIEW The S3C72P9 single chip CMOS microcontroller has been designed for high performance using Samsung s newest 4 bit CPU core SAM47 Samsung Arrangeable Microcontrollers With an up to 896 dot LCD direct drive capability flexible 8 bit and 16 bit timer counters and serial I O interface the S3C72P9 offers an excellent design solution for a wide variety of applications which require LCD functions Up to 39 pins of the 100 pin QFP package can be dedicated to I O Eight vectored interrupts provide fast response to internal and external events In addition the S3C72P9 s advanced CMOS technology provides for low power consumption and a wide operating voltage range The S3C72P9 is made by shrinking the KS57C21516 S3C72P9 is comparable to KS57C21516 both in function and in pin configuration except that S8C72P9 have 32 768 x8 bit ROM 1056x4 bit RAM 12 common selectable and LCD c
264. ting TONTO increments with each internal clock pulse When the comparator shows TCNTO TREFO the IRQTO flag is set to 1 and an interrupt request is generated Output latch TOLO logic toggles high or low P PND a PF WO 0 is cleared to and counting resumes 1 Programmable timer counter operation continues until TMODO 2 is cleared to 0 ELECTRONICS 11 13 TIMERS and TIMER COUNTERS S3C72P9 P72P9 Preliminary Spec TCO EVENT COUNTER FUNCTION Timer counter 0 can monitor or detect system events by using the external clock input at the TCLO pin as the counter source The TCO mode register selects rising or falling edge detection for incoming clock signals The counter register TCNTO is incremented each time the selected state transition of the external clock signal occurs With the exception of the different TMODO 4 TMODO 6 settings the operation sequence for TCO s event counter function is identical to its programmable timer counter function To activate the TCO event counter function Set TMODO 2 to 1 to enable TCO Clear TMODO 6 to 0 to select the external clock source at the TCLO pin Select TCLO edge detection for rising or falling signal edges by loading the appropriate values to TMODO 5 and TMODO 4 P3 2 must be set to input mode Table 11 5 TMODO Settings for TCLO Edge Detection TMODO 5 TMODO 4 TCLO Edge Detection 11 14 ELECTRONICS S3C72P9 P72P9 Preliminary Sp
265. tinues to run for a certain number of machine cycles For example you are using the default CPU clock normal operating mode and a main system clock of fx 64 and you want to switch from the fx clock to a subsystem clock and to stop the main system clock To do this you first need to set SCMOD 0 to 1 This switches the clock from fx to fxt but allows main system clock oscillation to continue Before the switch actually goes into effect a certain number of machine cycles must elapse After this time interval you can then disable main system clock oscillation by setting SCMOD 3 to 1 This same stepped approach must be taken to switch from a subsystem clock to the main system clock first clear SCMOD 3 to 0 to enable main system clock oscillation Then after a certain number of machine cycles has elapsed select the main system clock by clearing all SCMOD values to logic zero Following a RESET CPU operation starts with the lowest main system clock frequency of 15 3 us at 4 19 MHz after the standard oscillation stabilization interval of 31 3 ms has elapsed Table 6 4 details the number of machine cycles that must elapse before a CPU clock switch modification goes into effect Table 6 5 Elapsed Machine Cycles During CPU Clock Switch AFTER SCMOD 0 0 SCMOD 0 1 BEFORE 1 0 PCON 0 0 1 1 0 0 PCON 1 1 0 1 PCON 1 0 N A 1 MACHINE CYCLE 1 MACHINE CYCLE N A 0 SCMOD 0 0 PCON 1
266. tion Flag EN Set P0 2 to input mode Set P0 2 to output mode 1 P0 1 I O Mode Selection Flag 0 Set P0 1 to input mode Set P0 1 to output mode 0 0 0 I O Mode Selection Flag Set P0 0 to input mode Set P0 0 to output mode 1 4 26 ELECTRONICS 3 72 9 72 9 Preliminary Spec MEMORY MAP PMG2 Port 1 0 Mode Register 2 Group 2 Port 3 y o FE9H FE8H Bit 7 6 5 4 3 2 1 0 RESET Value 0 0 0 0 0 0 0 0 Read Write Bit Addressing 8 8 8 8 8 8 8 8 7 4 Bits 7 4 EN Always logic zero PM3 3 P3 3 I O Mode Selection Flag Set P3 3 to input mode Set P3 3 to output mode PM3 2 P3 2 I O Mode Selection Flag Set P3 2 to input mode Set P3 2 to output mode 1 P3 1 I O Mode Selection Flag Set P3 1 to input mode Set P3 1 to output mode PM3 0 P3 0 I O Mode Selection Flag Set P3 0 to input mode 1 Set P3 0 to output mode ELECTRONICS 4 MEMORY MAP S3C72P9 P72P9 Preliminary Spec PMG3 Port 1 0 Mode Register 3 Group 3 Ports 4 5 y o FEBH FEAH Bit 7 6 5 4 3 2 1 0 Identifier PM5 3 5 1 5 0 4 3 4 2 4 1 4 0 RESET Value 0 0 0 0 0 0 0 0 Read Write W W W W Bit Addressing 8 8 8 8 8 8 8 8 PM5 3 P5 3 I O Mode Selection Flag Set P5 3 to input mode Set P5 3 to output mode PM5 2 P5 2 Mode Selection Flag Set P5 2 to input mode 1 Set P5 2 to output mode 5 1 5 Mode Selection Flag S
267. to the ERB memory is transferred to the ERB flag and bit 7 of the address to flag and bit 7 of the address to the EMB flag the EMB flag Stack pointer SP Undefined Undefined Data Memory RAM General registers E A L H X W Z Y Undefined General purpose registers Values retained note Undefined Bassedonmgmes Gu amp SR BSC regiter sco asc 0 7 NOTE The values of the OF8H OFDH not retained when a RESET signal is input 9 2 ELECTRONICS 53 72 9 72 9 Preliminary Spec RESET Table 9 1 Hardware Register Values After RESET Continued or Subcomponent Power Down Mode Normal Operation VO Ports Output buffers Output latches Port mode flags PM Pull up resistor mode reg PUMOD1 2 Basic Timer Count register BCNT Mode register BMOD Mode register WDMOD Counter clear flag WDTCF Timer Counters 0 and 1 Count registers TCNTO 1 Reference registers TREFO 1 Output enable flags TOEO 1 Watch Timer Watch timer mode register WMOD LCD Driver Controller LCD contrast control register LCNST SE LCD mode register LMOD L _____ LCD control register LCON Display data memory Serial I O Interface SIO mode register SMOD SIO interface buffer SBUF Undefined N Channel Open Drain Mode Register PNE0 3 ELECTRONICS 9 3 RESET S3C72P9 P72P9 Preliminary Spec NOTES 9 4 ELECTRONICS 3 72 9 72 9 Preliminary Sp
268. ts to EA and skip on carry RRb EA Add EA to register pair RRb and skip on carry Subtract indirect data memory from A with carry Subtract register pair RR from EA with carry Subtract EA from register pair RRb with carry Subtract indirect data memory from A skip on borrow Subtract register pair RR from EA skip on borrow Subtract EA from register pair RRb skip on borrow Decrement register amp skip on borrow Decrement register pair RR skip on borrow Increment register amp skip on carry Increment direct data memory skip on carry Increment indirect data memory skip on carry Increment register pair RRb skip on carry 5 12 ELECTRONICS S3C72P9 P72P9 Preliminary Spec SAM47 INSTRUCTION SET Table 5 14 Bit Manipulation Instructions High Level Summary Test specified bit and skip if memory bit is set Test specified memory bit and skip if bit equals 0 Test specified bit skip and clear if memory bit is set a Set specified memory bit Clear specified memory bit to logic zero Logical AND carry flag with specified memory bit Logical OR carry with specified memory bit Exclusive OR carry with specified memory bit C IDE b Load carry bit to a specified memory bit memb a Load carry bit to a specified indirect memory bit H DA b C Load specified memory bit to carry bit C memb L_ Load specified indirect memory bit to carry bit C C OD _ i1 y b ELECTRONICS 5 13 SAM47
269. uasi interrupt This bit is set and is not cleared automatically by hardware when a rising or falling edge is detected at INT2 Since INT2 is a quasi interrupt IRQ2 flag must be cleared by software ELECTRONICS 4 11 MEMORY MAP S3C72P9 P72P9 Preliminary Spec IEA IRQ4 iNT4 Interrupt Enable Request Flags CPU IEB IRQB intB Interrupt Enable Request Flags CPU Bit 3 2 1 0 RESET Value 0 0 0 0 Read Write R W R W R W R W Bit Addressing 1 4 1 4 1 4 1 4 IEA INT4 Interrupt Enable Flag Disable interrupt requests at the INT4 pin 1 Enable interrupt requests at the INT4 pin IRQ4 INT4 Interrupt Request Flag when rising and falling signal edge detected at INT4 pin IEB INTB Interrupt Enable Flag Disable INTB interrupt requests 1 Enable INTB interrupt requests IRQB INTB Interrupt Request Flag when reference interval signal received from basic timer FB8H FB8H Generate INT4 interrupt This bit is set and cleared automatically by hardware Generate INTB interrupt This bit is set and cleared automatically by hardware 3 72 9 72 9 Preliminary Spec MEMORY MAP IES IRQS Interrupt Enable Request Flags CPU FBDH Bit 3 2 1 0 RESET Value 0 0 0 0 Read Write R W R W R W R W Bit Addressing 1 4 1 4 1 4 1 4 3 2 Bits 3 2 EN Always logic zero IES INTS Interrupt Enable Flag IRQS INTS Interrupt Request Flag Generate INTS interrupt This bit is set and cleared automatically by hardware Disab
270. uction which is used to reference instructions stored in the ROM PROGRAM STATUS WORD PSW The program status word PSW is an 8 bit word that defines system status and program execution status and which permits an interrupted process to resume operation after an interrupt request has been serviced PSW values are mapped as follows MSB LSB FBOH 151 150 ERB SC2 SC1 SCO The PSW can be manipulated by 1 bit or 4 bit read write and by 8 bit read instructions depending on the specific bit or bits being addressed The PSW can be addressed during program execution regardless of the current value of the enable memory bank EMB flag Part or all of the PSW is saved to stack prior to execution of a subroutine call or hardware interrupt After the in terrupt has been processed the PSW values are popped from the stack back to the PSW address When a RESET is generated the EMB and ERB values are set according to the RESET vector address and the carry flag is left undefined or the current value is retained PSW bits ISO 51 SCO SC1 and 5 2 are all cleared to logical zero Table 2 5 Program Status Word Bit Descriptions PSW Bit Identifier Bit Addressing Read Write Enable memory bank flag R W ELECTRONICS 2 19 ADDRESS SPACES S3C72P9 P72P9 Preliminary Spec INTERRUPT STATUS FLAGS 150 151 PSW bits ISO and 151 contain the current interrupt execution status values You can manipulate ISO and 1 1 flags direct
271. ulses to the CLO pin may be summarized as follows 1 a Disable clock output by clearing CLMOD 3 to logic zero Set the clock output frequency CLMOD 1 CLMOD 0 Load a 0 to the output latch of the CLO pin P2 0 Set the P2 0 mode flag PM2 0 to output mode Enable clock output by setting CLMOD 3 to logic one PROGRAMMING TIP CPU Clock Output to the CLO Pin To output the CPU clock to the CLO pin BITS EMB SMB 15 LD EA 10H LD PMG1 EA 2 0 lt Output mode 2 0 Clear P2 0 output latch LD A 9H LD CLMOD A ELECTRONICS 6 11 OSCILLATOR CIRCUITS S3C72P9 P72P9 Preliminary Spec NOTES 6 12 ELECTRONICS S3C72P9 P72P9 Preliminary Spec INTERRUPTS INTERRUPTS OVERVIEW The S3C72P9 interrupt control circuit has five functional components Interrupt enable flags IEx Interrupt request flags IRQx Interrupt master enable register IME Interrupt priority register IPR Power down release signal circuit Three kinds of interrupts are supported Internal interrupts generated by on chip processes External interrupts generated by external peripheral devices Quasi interrupts used for edge detection and as clock sources Table 7 1 Interrupt Types and Corresponding Port Pin s Interrupt Type Interrupt Name Corresponding Port Pins External interrupts INTO INT1 INT4 INTK P1 0 P1 1 P1 3 KO K7 Internal interrupts INTB INTTO INTT1 INTS Not applicable INTW Not applicab
272. unts internal or external clock pulses based on the bit settings in TMODO and TREFO Clock selector circuit Together with the mode register TMODO lets you select one of four internal clock frequencies or an external clock 8 bit comparator Determines when to generate an interrupt by comparing the current value of the counter register TCNTO with the reference value previously programmed into the reference register TREFO Output latch TOLO Where a clock pulse is stored pending output to the serial I O circuit or to the TCO output pin TCLOO When the contents of the TCNTO and TREFO registers coincide the timer counter interrupt request flag IRQTO is set to 1 the status of TOLO is in verted and an interrupt is generated Output enable flag TOEO Must be set to logic one before the contents of the TOLO latch can be output to TCLOO Interrupt request flag IRQTO Cleared when TCO operation starts and the TCO interrupt service routine is executed and set to 1 whenever the counter value and reference value coincide Interrupt enable flag IETO Must be set to logic one before the interrupt requests generated by timer counter 0 can be processed Table 11 4 TCO Register Overview Register Type Description RAM Addressing Reset Name Address Mode Value TMODO Control Controls TCO enable disable bit F90H F91H 8 bit write 2 clears and resumes counting only operation bit 3 sets input TMODO 3 is clock and clock frequenc
273. upt request By counting signal transitions it can be used to measure time intervals The TC1 circuit also has 16 bit comparator logic TC1 has a reloadable counter that consists of two parts a 16 bit reference register TREF1 into which you can write data for use as a reference value and a 16 bit counter register TCNT1 whose contents are automatically incremented by counter logic The 8 bit mode register TMOD1 is used to activate the timer counter and to select the basic clock frequency to be used for timer counter operations You can modify the basic frequency dynamically by loading new values into TMOD1 during program execution The only functional differences between TCO and TC1 are the size of the counter and reference value registers 8 bit versus 16 bit and the fact that only TCO can generate a clock signal for the serial I O interface TIMER COUNTER 1 FUNCTION SUMMARY 16 bit programmable timer Generates interrupts at specific time intervals based on the selected clock frequency External event counter Counts various system events based on edge detection of external clock signals at the TC1 input pin TCL1 Arbitrary frequency output Outputs selectable clock frequencies to the TC1 output pin TCLO1 External signal divider Divides the frequency of an incoming external clock signal according to the modifiable reference value TREF 1 and outputs the modified frequency to the TCLO1 pin 11 22 ELECTRONICS S3C72P9 P72P9 Pr
274. urce when writing application programs Counter registers buffer registers and reference registers as well as the stack pointer and port I O latches are not included in these descriptions More detailed information about how these registers are used is included Part Il of this manual Hardware Descriptions in the context of the corresponding peripheral hardware module descriptions 4 6 ELECTRONICS 3 72 9 72 9 Preliminary Spec MEMORY MAP Register and bit IDs Name of individual used for bit addressing bit or related bits Register ID Associated Register location Register name hardware module in RAM bank 15 CLMOD Clock Output Mode Control Register Bit Identifier RESE TValue Read Write Bit Addressing CLMOD 3 CLMOD 2 CLMOD 1 0 R Read only W Write only R W Read write 3 2 1 0 2 al 0 0 0 0 w w 4 4 4 4 Enable Disable Clock Output Control bit Bit 2 0 Always logic zero po Clock Source and Frequency Selection Control Bits Sect ceu cock t tu uet i MHz Soa or OSB Ssestersemcokoneeeoweaa bu Eo E Bit value immediately Bit number in after a RESET MSB to LSB order Type of addressing Description of the Bit identifier used that must be used to effect of specific for bit addressing address the bit bit settings 1 bit 4 bit o
275. ver you must first execute a DI instruction to inhibit additional interrupt routines When the bit manipulation has been completed execute an instruction to re enable interrupt processing 59 PROGRAMMING Setting ISx Flags for Interrupt Processing The following instruction sequence shows how to use the ISO and IS1 flags to control interrupt processing INTB DI Disable interrupt BITR IS1 I81 0 BITS ISO Allow interrupts according to IPR priority level El Enable interrupt 2 20 ELECTRONICS 3 72 9 72 9 Preliminary Spec ADDRESS SPACES EMB FLAG EMB The EMB flag is used to allocate specific address locations in the RAM by modifying the upper 4 bits of 12 bit data memory addresses In this way it controls the addressing mode for data memory banks 0 1 2 3 4 or 15 When the EMB flag is 0 the data memory address space is restricted to bank 15 and addresses 000 07 of memory bank 0 regardless of the SMB register contents When the EMB flag is set to 1 the general purpose areas of bank 0 1 2 3 4 and 15 can be accessed by using the appropriate SMB value 59 PROGRAMMING Using the EMB Flag to Select Memory Banks EMB flag settings for memory bank selection 1 When EMB 0 SMB 1 Non essential instruction since EMB 0 LD A 9H LD 90H A F90H lt A bank 15 is selected LD 34H A 034H lt A bank 0 is selected SMB 0 Non essential instruction since EMB 0 LD
276. wer down mode release signal is generated after releasing the power down mode program execution starts immediately under the instruction to enter power down mode without execution of interrupt service routine The interrupt request flag remains set to logic one Ifthe IME flag 1 If the power down mode release signal is generated after releasing the power down mode two instructions following the instruction to enter power down mode are executed first and the interrupt service routine is executed finally program is resumed However when the release signal is caused by INT2 or INTW the operation is identical to the IME 0 condition because INT2 and INTW are a quasi interrupt NOTE Do not use stop mode if you are using an external clock source because Xy input must be restricted internally to Vas to reduce current leakage ELECTRONICS 8 1 POWER DOWN S3C72P9 P72P9 Preliminary Spec Table 8 1 Hardware Operation During Power Down Modes Stop Mode STOP Idle Mode IDLE System clock status STOP mode can be used only if the main Idle mode can be used if the main system System clock is selected as system clock clock or subsystem clock is selected as CPU clock system clock CPU clock Clock oscillator Main system clock oscillation stops CPU clock oscillation stops main and subsystem clock oscillation continues Basic timer Basic timer stops Basic timer operates with IRQB set at each reference interval Serial I O
277. y bits also 1 bit 6 4 writeable TONTO Counter Counts clock pulses matching F94H F95H 8 bit the TMODO frequency setting read only TREFO Reference Stores reference value for the F96H F97H 8 bit timer counter 0 interval setting write only TOEO Flag Controls timer counter 0 output 1 bit F92H 2 1 4 bit to the TCLOO pin read write ELECTRONICS 11 11 TIMERS and TIMER COUNTERS S3C72P9 P72P9 Preliminary Spec Clocks fxx 2 10 boy2 6 fxx 2 4 box TCLO TMODO 7 TMODO 6 Clock Selector TMODO 4 TMODO 3 Inverted Serial I O Figure 11 2 TCO Circuit Diagram TCO ENABLE DISABLE PROCEDURE Enable Timer Counter 0 Set TMODO 2 to logic one Set the TCO interrupt enable flag IETO to logic one Set TMODO 3 to logic one IRQTO and are cleared to logic zero and timer counter operation starts Disable Timer Counter 0 Set 0 2 to logic zero Clock signal input to the counter register TCNTO is halted The current TCNTO value is retained and can be read if necessary 11 12 ELECTRONICS S3C72P9 P72P9 Preliminary Spec TIMERS and TIMER COUNTERS TCO PROGRAMMABLE TIMER COUNTER FUNCTION Timer counter 0 can be programmed to generate interrupt requests at various intervals based on the selected system clock frequency Its 8 bit TCO mode register TMODO is used to activate the timer counter and to select the clock frequency The reference register TREFO stores the value
278. y Spec TIMERS and TIMER COUNTERS Buzzer Output Frequency Generator The watch timer can generate a steady 2 kHz 4 kHz 8 kHz or 16 kHz signal to the BUZ pin To select the desired BUZ frequency load the appropriate value to the WMOD register This output can then be used to actuate an external buzzer sound To generate a BUZ signal three conditions must be met The WMOD 7 register bit is set to 1 The output latch for I O port 0 3 is cleared to 0 The port 0 3 output mode flag PMO 3 set to output mode Timing Tests in High Speed Mode By setting WMOD 1 to 1 the watch timer will function in high speed mode generating an interrupt every 3 91 ms At its normal speed WMOD 1 0 the watch timer generates an interrupt request every 0 5 seconds High speed mode is useful for timing events for program debugging sequences Check Subsystem Clock Level Feature The watch timer can also check the input level of the subsystem clock by testing WMOD 3 If WMOD 3 is 1 the input level at the XTjn pin is high if WMOD 3 is 0 the input level at the XT in pin is low ELECTRONICS 11 35 TIMERS and TIMER COUNTERS S3C72P9 P72P9 Preliminary Spec P0 3 Latch PMO 3 4 fw 2 16 kHz ENABLE DISABLE fw 4 8 kHz fw 8 4 kHz Selector fw A6 Circuit 2 kHz fw 2 fw 214 2 Hz Frequency Dividing 82 768 kHz Circuit Clock Selector fw 2 4096Hz fx Main system Clock fxt
279. ytes Cycles Description SRB instruction selects one of four register banks in the working register memory area The constant value used with SRB is 0 1 2 or 3 The following table shows the effect of SRB settings ERB Setting SRB Settings Selected Register Bank Always set to bank 0 NOTE applicable The enable register bank flag ERB must always be set for the SRB instruction to execute successfully for register banks 0 1 2 and 3 In addition if the ERB value is logic zero register bank 0 is always selected regardless of the SRB value Binary Code Operation Notation Example If the ERB flag is set the instruction SRB 3 selects register bank 3 018H 01FH as the working memory register bank ELECTRONICS 5 89 SAM47 INSTRUCTION SET S3C72P9 P72P9 Preliminary Spec SRET Return from Subroutine and Skip SRET Return from subroutine and skip Description SRET is normally used to return to the previously executing procedure at the end of a subroutine that was initiated by a CALL LCALL or CALLS instruction SRET skips the resulting address which is generally the instruction immediately after the point at which the subroutine was called Then program execution continues from the resulting address and the contents of the location addressed by the stack pointer are popped into the program counter Binary Code Operation Notation 14 8 lt

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