(M-LVDS) Transceiver Evaluation Kit User Manual
Contents
1. lolxi fo Calculatej B Calculate Ce fis Calculate jo Calculate a Calculate More Figure 11 130 ohm Differential Stripline olar Si6000 Controlled Impedanc k Solver am Files YPolar YSi6000b Yatca I ard Si6 File Edit Structures Configure Help Surface Micr 4 Height H Edge coupled Symmetrical Stripline Width fi Width WI Edge coupled f Coated Micr Separation Thickness ip je Dielectric Er Edge coupled Diff Impedance Zo Embedded Edge coupled Symmetrical Notes Units ER Add your comments here Mils Edge coupled Inches Offset Stripline C Microns C Millimetres Broadside c Stripline mA ma Jim m Design and Test Tools for Controlled Impedance and Signal Integrity Figure 12 80 ohm Differential Stripline 11 EEI Calculate fo Calculate fo ls Calculate bz Calculate a Calculate More Layer Stack Up 1 2 OZ SIG1 10 mills 1 2 OZ GND 15 mills 1 2 OZ SIG2 15 mills 1 2 OZ GND 3 mills 1 2 OZ PWR 3 mills 1 2 OZ PWR 3 mills 1 2 OZ GND 15 mills 1 2 OZ SIG3 15 mills 1 2 OZ GND 10 mills 1 2 OZ SIG4 Bill Of Materials DS91D176 Evaluation Board User Manual 22u SM7343 C1 Not Installed 0 1u SM062. At 87 hag7X a DET FRE B BI GND Hey 1 3 GND Dz DE A GND C7 Hp and 1 TXE D GND ct D7 l BorX 4 SIG S91D176 Di GND E7 1 157 ono GND EX GND va El F7 l Farx 2 R3 4 FI GND bay TT 4 a vec H GND 67 he SMA2 6 rr ER H7 6 l DET 37 RE B Gt H7 l HerX 137 eno 8 Hio Dt DE A Ht anD FE 4 GND 1 TX 10 73 FT D GND GND Tyco HM ZD 1469001 1 AG 4 yp S S 12 44 TS Es ML 13 14 i6 6 Bae GND 16 Hg us B2 GND Fes 0 1 18 RA GND ce bee x A 22194 DET 3 RE B D2 GND he 137 ono 24 DT DE A GND ES Fe X GND RX FSIS OCT ao D GND E2 F6 l E ox E die jal Molex 90130 3124 SETE Ea Elo FGE 157 oND GND G6 l iis X GND us G2 H6 l Hoex R5 4 H2 GND FE 4 SMA4 0 Z mr A VOR GND Fen Re eee Sag en estes Fawr mice wee 2 DET 37 RE B 286885825810 GOODLO IG VRSSASHLGSLS w e eno Fees JATI dd dd GND sig Re D GND ACAGSSSARLL SLL BAAS SAS AALS Wasser 4 L 5910176 75 eNO R6 ve GND voc al DET 3 RE B 3 DE SIDE A Dt 910176 SMA5 bi SMA7 2 5 137 ono GND GND 1 uz GND H 4 J5 4 ony fl la voc SG ono H E eho wH RE B eno L H DE A VCC 3V D GND SMA8 T Pomona 3267 SMA6 D591D176 5 c3 c2 C1 GND 01 22 J6 tH GND gay 0 01u u T u ae 6 GND 1 SIG 3 s 1 SIG Not Installed GND 1 ono SER eno FT GND GND Pomona 3267 J7 1 VCC_3V ql i I 1 1 T 1 vcc 3V Ji C10 cg C8 c7 C6 C5 C4 Johnson Components 108 0902 001 VCC 3V 1 2 VCC 3V GND 0 1u 0 1u 01u f ot 0 1u tu 0 1u c20 c19 018 as 12h DE 4 4 4 4 4 A ob R J8 GN
3. jii SMAG SMAS Naitomal e Ton 2 Semiconductor o ES to o lt 2 G gt Q i lt Cr gt ow RO un M LVDS Line Card 1 STUB 1 STUB B P N DS91D176EVK ion wr ima Mall SMA4 HHI HIE E HH FRE 1 fea a1 82 a 63 43 Ba As U6 US Ud U3 2 TX TX RX4 RX BS AS BS A6 16 JA 5 1 1 42 STUB J4 PIN ASSIGNMENT ig eee ee WN Hess mum gt SMA 3 Gle Es FO mn gt E is oe 8 w TaT eona 1 4 STUB ls a i ee Claes o om gt E E jj e CHEERS ER Ale e o ri i gt Figure 1 DS91D176 Evaluation Board Top View Devices U1 through U6 can serve as building blocks for M LVDS clock distribution networks in ATCA backplanes Their M LVDS I O pins directly connect to the first two row pins of JA which is an ADF Advanced Differential Fabric connector When J4 is inserted into any ATCA backplane slot location J20 P20 for those of you familiar with ATCA backplanes the M LVDS I O pins of each device electrically connect to one of the clock busses there are six clock busses in an ATCA backplane See Figure 3 The PCB traces that connect device M LVDS pins with the J4 connector pins have different characteristics for each device These traces are also 2 DS91D176 Evaluation Board User Manual called stubs Table 1 provides characteristic of each stub M LVDS pins to J
4. 03 C2 Not Installed 0 01u SM0603 C3 Not Installed Molex 90131 0123 Molex 90130 3124 Tyco HM ZD 1469001 1 Pomona 3267 Not Installed Johnson Components 108 0902 001 Johnson Components 108 0903 001 Johnson Components 142 0701 231 Item Quantity Reference Part 1 2 C18 C1 9 C2 C4 C5 C6 C7 C8 C9 C10 C19 3 9 C3 C11 C12 C13 C14 C15 C16 C17 C20 4 2 J3 J1 5 1 J2 6 1 J4 7 2 J5 J6 8 1 J7 9 1 J8 10 4 SMA1 SMA2 SMA3 SMA4 Not Installed 11 4 SMA5 SMA6 SMA7 SMA8 11 7 U1 U2 U3 U4 U5 U6 U7 DS91D176TMA 12 1 R1 50 SM0603 Not Installed 12 DS91D176 Evaluation Board User Manual Schematic J3 VCC 3V 1 2 VCC 3V BET Sii 254 DET GND sis ES GND 5 6 ut Molex 90131 0123 Y R vec pet SDE A 4 SLAGS FTT D GND gga slaldalaBooAaAJQI c eelco col lca col 5910176 J4 ZJIMMOJOJOLWILILJONII aoaaa LOTT coa auto TT 2299990990990 2808808208720 2goggoggogeo u2 ZB OBZULZOrLz TAZODZWUZOTZ TdMZOBZWUZOTZ AZ R2 1 SGC o bio 6 6 6 0 6 6 6 6 ABr i i JA vec
5. 090 800 1002 SMA1 TX SMA2 TX SMA3 RX SMA4 RX SMAS R7 SMAT B7 SMAS8 A7 SMAS D7 Figure 2 Simplified Signal Path Block Diagram DS91D176 Evaluation Board User Manual Building an Evaluation M LVDS Clock Distribution Network in an ATCA Backplane The following is a recommended procedure for building an evaluation M LVDS clock distribution network with DS91D176 evaluation boards The assumption is that the user already has an ATCA backplane Figure 3 depicts configuration of a generic M LVDS clock network in an ATCA backplane 1 Use two or more DS91D176 evaluation boards and install them at backplane location J20 P20 in the desired slots Apply the power to the boards 3 3 V typical between J7 and J8 banana plug receptacles observe the value of Icc and compare it with the expected value refer to the datasheet to ensure that the devices are functional Select the board you want to configure as a clock driver distributor This is accomplished by setting DE and RE pins to VDD J1 Connect a clock generator to one of the driver inputs J2 Configure the remaining boards as clock receivers This is accomplished by setting DE and RE pins to GND J1 Observe clock waveforms by either connecting receiver LVCMOS output pins J1 directly to an oscilloscope or by probing receiver M LVDS input pins with a differential p
6. 2 U4 U6 M LVDS nets U3 M LVDS nets 80 ohm Differential Stripline Figure 12 U5 M LVDS nets Table 2 Trace Type to Electrical Net Cross reference Polar Si6000 Controlled Impedance Quick Solver Untitled Si6 File Edit Structures Configure Help Surface Microstrip Coated Microstrip Embedded Microstrip Notes Add your comments here Polar Symmetrical Stripline Offset Stripline Edge coupled y Surface Microstrip la x Height H 10 Calculate Width wW 19 Calculate Width WI Po Thickness T 07 Calculate Dielectric Er 4 Calculate Impedance m Units Mils C Inches Microns Millimetres Design and Test Tools for Controlled Impedance and Signal Integritv Figure 8 50 ohm Single ended Microstrip DS91D176 Evaluation Board User Manual d Impedance malk File Edit Structures Configure Help Height H po O Calculate Embedded Edge coupled Surface Microstrip igh w Calculate Microstrip WWidth1 WI 10 Separation S 4 Calculate re Thickness JE 0 7 Calculate Symmetrical Stripline Dielectric Er 4 Calculate Diff Impedance Zo 100 23 More Offset Stripline Notes Units Edge coupled Surface Micr Add your comments here Mils C Inches a Microns Edge coupled Millimetres Coated Miet Design and Test Tools for pes a Controlled Impedance Edge co
7. 4 pin mapping and LVCMOS pins to J2 pins mapping Device M LVDS Pins J4 Pins Stub Length Zstus LVCMOS Pins J2 Pins U1 Al B1 0 25 1000 R1 2 B1 A1 D1 4 U2 A2 D1 0 50 1000 R1 6 B2 C1 D1 8 U3 A3 F1 1 00 1300 R1 10 B3 El D1 12 U4 A4 H1 1 00 100 Q R1 14 B4 G1 D1 16 U5 A5 D2 1 00 80 Q R1 18 B5 C2 D1 20 U6 A6 B2 2 00 1000 R1 22 B6 A2 D1 24 Table 1 U1 U6 Stub Characteristics and Pin Mapping J1 configures U1 through U6 as either driver or receiver J7 and J8 are power and ground banana plug receptacles J5 and J6 are redundant power and ground connections U7 is for a standalone evaluation Its I O pins both M LVDS and LVCMOS connect to SMA connectors SMA5 SMAS8 for easy interface with instrumentation J3 configures U7 as either driver or receiver There is a provision to terminate M LVDS inputs of the U7 with a SM0603 sized resistor Connectors SMA1 SMA2 SMA3 and SMA4 connect to J4 pins H2 G2 F2 and E2 respectively If the board is plugged in an ATCA backplane locations J21 P21 J22 P22 J23 P23 and J24 P24 in any slot fabric interface is accessed with these connectors Figure 2 provides a simplified block diagram view of the signal paths between the connecters and IC s DS91D176 Evaluation Board User Manual LVCMOS ATCA Signal ADF Connector Connector 1002 1300 1 00 stub mmmmmmnmannennnnnnannnnannnnznnzenzanjonmennnnnnnannenn 10
8. 91D176 Evaluation Board User Manual Building an Evaluation Point Point Link with DS91D176 Evaluation Boards The following is a recommended procedure for building an evaluation M LVDS point point network with DS91D176 evaluation boards Figure 6 depicts a typical setup and instrumentation used for evaluation of a point to point link 1 Use two DS91D176 evaluation boards 2 Apply the power to the boards 3 3 V typical between J7 and J8 banana plug receptacles observe the value of Icc and compare it with the expected value refer to the datasheet to ensure that the devices are functional 3 Configure U7 on one board as a driver This is accomplished by setting DE and RE pins to VDD J3 Connect a signal generator to the driver inputs SMA6 4 Configure U7 on the other board as a receiver This is accomplished by setting DE and RE pins to GND J3 5 Select a differential interconnect with balanced 100 ohm differential impedance i e UTP cable and connect the M LVDS pins of both devices with it 6 Terminate the interconnect with a matching resistor on the inputs of U7 on the receiver board R1 7 Observe waveforms by either connecting the receiver LVCMOS output pins SMA5 directly to an oscilloscope or by probing receiver M LVDS input pins with a differential probe Figure 6 M LVDS Point to Point Link with DS91D176 Boards and UTP Cable DS91D176 Evaluation Board User Manual Figure 7 shows eye diagrams acquired at the
9. D 5 6 GND GND 5 6 Place one 0 luF and one 0 0luF cap close to VDD pin of each DS91D176 1 1 Molex 90131 0123 i edu Johnson Components 108 0903 001 Cir C16 C15 C14 C13 C12 C11 GND 0 01u 0 01u o otu 001 0 01u 0 01u 0 01u Title ATCA Line Card M LVDS ize Document Number Rev ate Wednesday January 18 2006 Bheet 1 of I 13 DS91D176 Evaluation Board User Manual Revision History Revision 0 1 Initial draft dglisic 12Apr2006 Revision 0 2 Minor edits added simplified block diagram bstearns 14 April2006 15
10. National Semiconductor DS91D176 Multipoint LVDS M LVDS Transceiver Evaluation Kit User Manual April 2006 Rev 0 2 DS91D176 Evaluation Board User Manual Overview The purpose of this document is to familiarize you with the DS91D176 evaluation board suggest the test setup procedures and instrumentation and to guide you through some typical measurements that will demonstrate the performance of the device The primary function of the board is to assist a system designer in development and analysis of an M LVDS clock distribution network in an ATCA backplane The board also enables the user to examine performance and all functions of the DS91D176 as a standalone device As a side feature one can utilize the board to access switch fabric interface of an ATCA backplane The DS91D176 is a high speed M LVDS differential transceiver designed for multipoint applications with multiple drivers or receivers The device conforms to TIA EIA 899 standard It utilizes M LVDS technology for low power high speed and superior noise immunity Description Figure 1 below represents the top layer drawing of the board with the silkscreen annotations It is a 6 x 4 inch 10 layer printed circuit board PCB that features seven DS91D176 U1 U7 devices SMA om Ji il 00 PEPPY TT asal ue mm ie 229000000 eee ees ba D R DS R5 DA PA D3 R3 D2 R2 DI RI TX _ E GND Ned J8 RE4 DE RE4 e THNIT SMA2 RoHS TERESI ha ltr 2 2 l E l
11. output of the DS91D176 driver loaded with a 100 ohm resistor and after 50 m Cat5e cable terminated with a 100 ohm resistor The generator connected to the driver input simulated a 100 Mb s PRBS 7 NRZ File Edt View Setup Utiiies Help 1000 Waveforms BAcas 1000 of 1000 Tarn lal Help iodd Waveforms RAcgs 1000 of 1000 Tal Ex HE EF sox ala TE sA TIC Fun Stop Acq Mode Sample 2 Trig Extemal Direct FI Z ffpe somv En F Fuse Z arado FI 0 900 afna jfur ffe aja lia BR Ju Tu e Ausi aca Made Sample FI TnafEntema Direct FI A Pasony BE 50 R2 Pulse FJ Ampituce FI ne nnn En an 00 5 00 95 4 63 00 ja als pit M1 200 0mV div E M1 200 0mV div 1WIMDE M1 y 1WIMDE M1 yA ma oo omw BJ 7 EH man ajaj von BH pao B 1 37PM 3 24 06 BE mn Q Q par a EE 1 42PM 3 24 06 Figure 7 Eye Diagram Before and After 50 m of Cat5e Mi aj 200 0mv fal a DS91D176 Evaluation Board User Manual Microstrip and Stripline Geometries Used Figures 8 to 12 show trace geometries used in the board design Table 2 provides trace type to electrical net cross reference Trace Type Figure DS91D176 Evaluation Board Nets 50 ohm Single ended Microstrip Figure 8 All LVCMOS nets 100 ohm Differential Microstrip Figure 9 U7 M LVDS nets SMA1 SMA4 nets 130 ohm Differential Stripline Figure 11 100 ohm Differential Stripline Figure 10 U1 U
12. robe 8002 R 8002 R 8002 R 8002 R 8002 R 800 R PICMG 3 0 Backplane lt 100 MHz Z 1300 Figure 3 M LVDS Clock Distribution Network in an ATCA Backplane The above block diagram details the clock channels They are all 130 ohm differential and doubly terminated with 80 ohms at either end of the backplane The parallel combination of 80 ohm resistors means that the MLVDS devices will be driving a 40 ohm load termination The maximum stub length from the backplane is defined in the ATCA standard as 1 inch or 2 5 cm DS91D176 Evaluation Board User Manual Figure 4 shows a picture of a 14 slot ATCA backplane fully populated with DS91D176 evaluation boards bores gy eveceeree Figure 4 DS91D176 Evaluation Boards in an ATCA Backplane Figure 5 shows 19 44 MHz clock waveforms obtained with a differential probe Tektronix P6330 on the M LVDS input pins of U1 U2 U4 and U6 devices of the receiver board in slot 8 The14 Slot backplane was fully populated The clock driver distributor board was in slot 7 File Edit Vert Horz Acq Trig Display Cursor Meas Mask Math App MyScope Utilities Help Button Tek Stopped 9830 Acqs 21 Mar 06 14 10 47 Ref1 Position 0 0div Refi Scale 200 0mv fic2 200mva R4 200mV 10 0ns 10 0ns div R1 200mvV 10 0ns 40 0GS s 25 0ps pt R2 200mV 10 0ns Mc2 0 0v R3 200mV 10 0ns Figure 5 19 44 MHz Clock Waveforms Show Stub Length Effects on Signal Integrity DS
13. upled sl m E and Signal Integrity Figure 9 100 ohm Differential Microstrip Polar Si6000 Controlled Impedance Quick Solver C Program Files Polar Si6000b atca_line_card Sio J x File Edit Structures Configure Help a Height H jo Calculate Edge coupled Symmetrical Stripline Was w B Catt Width Separation S fs Calculate Thickness T fz o Calculate Dielectric Er 4 Calculate Diff Impedance Zo foise Surface Micr Edge coupled Coated Micr Edge coupled Embedded More Edge coupled Symmetrical Notes Units Add your comments here Mils Edge coupled C Inches Offset Stripline C Microns C Millimetres ES Design and Test Tools for Stripline mi Controlled Impedance sl re and Signal Integrity Figure 10 100 ohm Differential Stripline 10 DS91D176 Evaluation Board User Manual olar Si6000 Controlled Impedance Q File Edit Structures Configure Help Surface Micr 4 Height H Edge coupled Width wW Edge coupled Symmetrical Stripline Width1 WI Coated Micr pen b Thickness T tea Dielectric Er Edge coupled Diff Impedance Zo Embedded Edge coupled Symmetrical Notes Units ER Add your comments here Mils Edge coupled C Inches Offset Stripline C Microns C Millimetres Broadside c Stripline ma ME m Design and Test Tools for Controlled Impedance and Signal Integrity
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