UM10120 Volume 1: LPC213x User Manual
Contents
1. address 0xE000 C004 when DLAB 1 bit description Bit Symbol Description Reset value 7 0 DLMSB The UARTO Divisor Latch MSB Register along with the UODLL 0x00 register determines the baud rate of the UARTO UARTO Baua rate calculation Example Using UARTOpaudrate Equation 1 from above it can be determined that system with PCLK 20 MHz UODL 130 UODLM 0x00 and UODLL 0x82 will enable UARTO with UART Opaudrate 96 15 baud Table 78 Some baud rates available when using 20 MHz peripheral clock PCLK 20 MHz Desired UODLM U0DLL errorl Desired UODLM UODLL error baud rate hex dec baud rate hex dec 50 0x61A8 25000 0 4800 0x0104 260 0 1603 75 0x411B 16667 0 0020 7200 0x00AE 174 0 2235 110 0x2C64 11364 0 0032 9600 0x0082 130 0 1603 134 5 0x244E 9294 0 0034 19200 0x0041 65 0 1603 150 0x208D 8333 0 0040 38400 0x0021 33 1 3573 300 0x1047 4167 0 0080 56000 0x0021 22 1 4610 600 0x0823 2083 0 0160 57600 0x0016 22 1 3573 1200 0x0412 1042 0 0320 112000 0x000B 11 1 4610 1800 0x02B6 694 0 0640 115200 0x000B 11 1 3573 2000 0x0271 625 0 224000 0x0006 6 6 9940 2400 0x0209 521 0 0320 448000 0x0003 3 6 9940 3600 0x015B 347 0 0640 1 Relative error calculated as actual_baudrate desired_baudrate 1 Actual baudrate based on Equation 1 UARTO Interrupt Enable Register UOIER 0xE000 C004 when DLAB 0 The UOIER is used to enable the three UARTO interrupt sources Koninklijke Philips2. but no further characters are sent until this bit is set again In other words a 0 in this bit blocks the transfer of characters from the THR or TX FIFO into the transmit shift register Software implementing software handshaking can clear this bit when it receives an XOFF character DC3 Software can set this bit again when it receives an XON DC1 character 9 4 Architecture The architecture of the UARTO is shown below in the block diagram The VPB interface provides a communications link between the CPU or host and the UARTO The UARTO receiver block UORX monitors the serial input line RXDO for valid input The UARTO RX Shift Register UORSR accepts valid characters via RXDO After a valid character is assembled in the UORSR it is passed to the UARTO RX Buffer Register FIFO to await access by the CPU or host via the generic host interface The UARTO transmitter block UOTX accepts data written by the CPU or host and buffers the data in the UARTO TX Holding Register FIFO UOTHR The UARTO TX Shift Register UOTSR reads the data stored in the UOTHR and assembles the data to transmit via the serial output pin TXDO The UARTO Baud Rate Generator block UOBRG generates the timing enables used by the UARTO TX block The UOBRG clock input source is the VPB clock PCLK The main clock is divided down per the divisor specified in the UODLL and UODLM registers This divided down clock is a 16x oversample clock NBAUDOUT T
3. 20 ja Volume 1 9 3 7 9 3 8 Chapter 9 UARTO The UARTO THRE interrupt UOIIR 3 1 001 is a third level interrupt and is activated when the UARTO THR FIFO is empty provided certain initialization conditions have been met These initialization conditions are intended to give the UARTO THR FIFO a chance to fill up with data to eliminate many THRE interrupts from occurring at system start up The initialization conditions implement a one character delay minus the stop bit whenever THRE 1 and there have not been at least two characters in the UOTHR at one time since the last THRE 1 event This delay is provided to give the CPU time to write data to UOTHR without a THRE interrupt to decode and service A THRE interrupt is set immediately if the UARTO THR FIFO has held two or more characters at one time and currently the UOTHR is empty The THRE interrupt is reset when a UOTHR write occurs or a read of the UOIIR occurs and the THRE is the highest interrupt UOIIR 3 1 001 UARTO FIFO Control Register UOFCR 0xE000 C008 The UOFCR controls the operation of the UARTO Rx and TX FIFOs Table 82 UARTO FIFO Control Register UOFCR address 0xE000 C008 bit description Bit Symbol Value Description Reset value 0 FIFO Enable 0 UARTO FIFOs are disabled Must not be used in the 0 application 1 Active high enable for both UARTO Rx and TX FIFOs and UOFCR 7 1 access This bit must be set for proper UARTO operation Any transition o
4. Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 87 Philips Semiconductors UM10120 ia Volume 1 9 3 6 Chapter 9 UARTO Table 79 UARTO Interrupt Enable Register UOIER address 0xE000 C004 when DLAB 0 bit description Bit Symbol Value Description Reset value 0 RBR UOIER 0 enables the Receive Data Available interrupt 0 Interrupt for UARTO It also controls the Character Receive Enable Time out interrupt 0 Disable the RDA interrupts 1 Enable the RDA interrupts 1 THRE UOIER 1 enables the THRE interrupt for VARTO The 0 Interrupt status of this can be read from UOLSR 5 Enable 0 Disable the THRE interrupts 1 Enable the THRE interrupts 2 RX Line UOIER 2 enables the UARTO RX line status interrupts 0 Status The status of this interrupt can be read from UOLSR 4 1 Interrupt Enable 0 Disable the RX line status interrupts 1 Enable the RX line status interrupts 713 Reserved user software should not write ones to NA reserved bits The value read from a reserved bit is not defined UARTO Interrupt Identification Register UOIIR OxE000 C008 Read Only The UOIIR provides a status code that denotes the priority and source of a pending interrupt The interrupts are frozen during an UOIIR access If an interrupt occurs during an UOIIR access the interrupt is recorded for the next UOIIR access Table 80 UARTO Interrupt Identification R
5. FIFO The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available UARTO Divisor Latch Registers 0 and 1 UODLL OxE000 C000 and UODLM 0xE000 C004 when DLAB 1 The UARTO Divisor Latch is part of the UARTO Baud Rate Generator and holds the value used to divide the VPB clock PCLKk in order to produce the baud rate clock which must be 16x the desired baud rate Equation 1 The UODLL and UODLM registers together form a 16 bit divisor where UODLL contains the lower 8 bits of the divisor and UODLM contains the higher 8 bits of the divisor A 0x0000 value is treated like a 0x0001 value as division by zero is not allowed The Divisor Latch Access Bit DLAB in UOLCR must be one in order to access the UARTO Divisor Latches Details on how to select the right value for UODLL and UODLM can be found later on in this chapter Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 86 Philips Semiconductors UM1 01 20 ia Volume 1 9 3 4 9 3 5 Chapter 9 UARTO 1 clk UARTO baudrate 16 x 16 x UODLM UODLL Table 76 UARTO Divisor Latch LSB register UODLL address 0xE000 C000 when DLAB 1 bit description Bit Symbol Description Reset value 7 0 DLLSB The UARTO Divisor Latch LSB Register along with the UODLM 0x01 register determines the baud rate of the UARTO Table 77 UARTO Divisor Latch MSB register UODLM
6. is full In this case the UARTO RBR FIFO will not be overwritten and the character in the UARTO RSR will be lost 0 Overrun error status is inactive 1 Overrun error status is active 2 Parity Error When the parity bit of a received character is in the wrong state a parity error 0 PE occurs An UOLSR read clears UOLSR 2 Time of parity error detection is dependent on UOFCR 0 Note A parity error is associated with the character at the top of the UARTO RBR FIFO 0 Parity error status is inactive 1 Parity error status is active Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 91 Philips Semiconductors UM1 01 20 R volume 1 Chapter 9 UARTO Table 84 UARTO Line Status Register UOLSR address 0xE000 C014 read only bit description Bit Symbol Value Description Reset value 3 Framing Error When the stop bit of a received character is a logic 0 a framing error occurs 0 FE An UOLSR read clears UOLSR 3 The time of the framing error detection is dependent on UOFCRO Upon detection of a framing error the Rx will attempt to resynchronize to the data and assume that the bad stop bit is actually an early start bit However it cannot be assumed that the next received byte will be correct even if there is no Framing Error Note A framing error is associated with the character at the top of the UARTO RBR FIFO 0 Framing error status is inactiv
7. one of four error conditions occur on the UARTO Rx input overrun error OE parity error PE framing error FE and break interrupt BI The UARTO Rx error condition that set the interrupt can be observed via UOLSR 4 1 The interrupt is cleared upon an UOLSR read The UARTO RDA interrupt UOIIR 3 1 010 shares the second level priority with the CTI interrupt UOIIR 3 1 110 The RDA is activated when the UARTO Rx FIFO reaches the trigger level defined in UOFCR 7 6 and is reset when the UARTO Rx FIFO depth falls below the trigger level When the RDA interrupt goes active the CPU can read a block of data defined by the trigger level The CTI interrupt UOIIR 3 1 110 is a second level interrupt and is set when the UARTO Rx FIFO contains at least one character and no UARTO Rx FIFO activity has occurred in 3 5 to 4 5 character times Any UARTO Rx FIFO activity read or write of UARTO RSR will clear the interrupt This interrupt is intended to flush the UARTO RBR after a message has been received that is not a multiple of the trigger level size For example if a peripheral wished to send a 105 character message and the trigger level was 10 characters the CPU would receive 10 RDA interrupts resulting in the transfer of 100 characters and 1 to 5 CTI interrupts depending on the service routine resulting in the transfer of the remaining 5 characters Table 81 UARTO interrupt handling UOIIR 3 0 Priority Interrupt Ty
8. C The UOSCR has no effect on the UARTO operation This register can be written and or read at user s discretion There is no provision in the interrupt interface that would indicate to the host that a read or write of the UOSCR has occurred Table 85 UARTO Scratch pad register UOSCR address 0xE000 C01C bit description Bit Symbol Description Reset value 7 0 Pad A readable writable byte 0x00 Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 92 Philips Semiconductors UM1 01 20 ia Volume 1 Chapter 9 UARTO 9 3 11 UARTO Transmit Enable Register UOTER 0xE000 C030 LPC2131 2 4 6 8 s UOTER enables implementation of software flow control When TXEn 1 UARTO transmitter will keep sending data as long as they are available As soon as TXEn becomes 0 UARTO transmittion will stop Table 86 describes how to use TXEn bit in order to achieve software flow control Table 86 UARTO Transmit Enable Register UOTER address 0xE000 C030 bit description Bit Symbol Description Reset value 6 0 Reserved user software should not write ones to reserved bits The NA value read from a reserved bit is not defined 7 TXEN When this bit is 1 as it is after a Reset data written to the THR is output 1 on the TXD pin as soon as any preceding data has been sent If this bit is cleared to 0 while a character is being sent the transmission of that character is completed
9. SB 8 bit Data R W 0x00 0xE000 C004 DLAB 1 UOIER Interrupt Enable Reserved Reserved Reserved Reserved Reserved Enable Enable Enable R W 0x00 0xE000 C004 Register RX Line THRE RX Data DLAB 0 Status Interrupt Available Interrupt Interrupt UOIIR Interrupt ID FIFOs Enabled Reserved Reserved IIR3 IIR2 IIR1 IIRO RO 0x01 0xE000 C008 Register UOFCR FIFO Control RX Trigger Reserved Reserved Reserved TX FIFO RXFIFO FIFO WO 0x00 0xE000 C008 Register Reset Reset Enable UOLCR Line Control DLAB Set Stick Even Parity Number Word Length Select R W 0x00 0xE000 C00C Register Break Parity Parity Enable of Stop Select Bits UOLSR Line Status RX FIFO TEMT THRE BI FE PE OE DR RO 0x60 0xE000 C014 Register Error UOSCR Scratch Pad 8 bit Data R W 0x00 0xE000 C01C Register UOTER Transmit Enable TXEN Reserved Reserved Reserved Reserved Reserved Reserved Reserved R W 0x80 0xE000 C030 Register 1 Reset value relects the data stored in used bits only It does not include reserved bits content L WnJoA s10 2NnpuosIw s Sdijiud OLYVN 6 139 dey9 Oc LOLNN Philips Semiconductors UM1 01 20 ja Volume 1 9 3 1 9 3 2 9 3 3 Chapter 9 UARTO UARTO Receiver Buffer Register UORBR 0xE000 C000 when DLAB 0 Read Only The UORBR is the top byte of the UARTO Rx FIFO The top byte of the Rx FIFO contains the oldest character received and can be read via the bus interface The LSB bit 0 represents the oldest
10. UM10120 Chapter 9 Universal Asynchronous Receiver Transmitter 0 UARTO Rev 01 24 June 2005 User manual E Semiconductors 9 1 Features e 16 byte Receive and Transmit FIFOs e Register locations conform to 550 industry standard e Receiver FIFO trigger points at 1 4 8 and 14 bytes e Built in baud rate generator s LPC2131 2 4 6 8 UARTO contains mechanism that enables software flow control implementation 9 2 Pin description Table 72 UARTO pin description Pin Type Description RXDO Input Serial Input Serial receive data TXDO Output Serial Output Serial transmit data 9 3 Register description UARTO contains registers organized as shown in Table 73 The Divisor Latch Access Bit DLAB is contained in UOLCR 7 and enables access to the Divisor Latches Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 84 soog eunr rz L0 A99 jenuew sasn ss ponasa SUBH TY 9002 XN 910 93 Sdiliyd Sla Table 73 UARTO register map Name Description Bit functions and addresses Access Reset Address MSB LSB value BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO UORBR Receiver Buffer 8 bit Read Data RO NA 0xE000 C000 Register DLAB 0 UOTHR Transmit Holding 8 bit Write Data WO NA 0xE000 C000 Register DLAB 0 UODLL Divisor Latch LSB 8 bit Data R W 0x01 0xE000 C000 DLAB 1 UODLM Divisor Latch M
11. e 1 Framing error status is active 4 Break Interrupt When RXDO is held in the spacing state all 0 s for one full character 0 Bl transmission start data parity stop a break interrupt occurs Once the break condition has been detected the receiver goes idle until RXDO goes to marking state all 1 s An UOLSR read clears this status bit The time of break detection is dependent on UOFCR 0 Note The break interrupt is associated with the character at the top of the UARTO RBR FIFO 0 Break interrupt status is inactive 1 Break interrupt status is active 5 Transmitter THRE is set immediately upon detection of an empty UARTO THR and is 1 Holding cleared on a UOTHR write Register Empty YOTHR contains valid data THRE 1 UOTHR is empty 6 Transmitter TEMT is set when both UOTHR and UOTSR are empty TEMT is cleared when 1 Empty either the UOTSR or the UOTHR contain valid data CEMT 0 UOTHR and or the UOTSR contains valid data 1 UOTHR and the UOTSR are empty 7 Errorin RX UOLSR 7 is set when a character with a Rx error such as framing error parity 0 FIFO error or break interrupt is loaded into the UORBR This bit is cleared when the RXFE UOLSR register is read and there are no subsequent errors in the UARTO FIFO 0 UORBR contains no UARTO RX errors or UOFCR 0 0 1 UARTO RBR contains at least one UARTO RX error 9 3 10 UARTO Scratch pad register UOSCR 0xE000 C01
12. egister UOIIR address 0xE000 C008 read only bit description Bit Symbol Interrupt Pending Value Description Reset value Note that UOIIR 0 is active low The pending interrupt can 1 be determined by evaluating UOIIR 3 1 At least one interrupt is pending No pending interrupts 3 1 Interrupt Identification 011 UOIER 3 1 identifies an interrupt corresponding to the 0 UARTO Rx FIFO All other combinations of UOIER 3 1 not listed above are reserved 000 100 101 111 1 Receive Line Status RLS 010 2a Receive Data Available RDA 110 2b Character Time out Indicator CTI 001 3 THRE Interrupt 5 4 Reserved user software should not write ones to reserved NA bits The value read from a reserved bit is not defined 7 6 FIFO Enable These bits are equivalent to UOFCR O 0 Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 88 Philips Semiconductors UM1 01 20 ia Volume 1 Chapter 9 UARTO Interrupts are handled as described in Table 81 Given the status of UOIIR 3 0 an interrupt handler routine can determine the cause of the interrupt and how to clear the active interrupt The UOIIR must be read in order to clear the interrupt prior to exiting the Interrupt Service Routine The UARTO RLS interrupt UOIIR 3 1 011 is the highest priority interrupt and is set whenever any
13. haracter length 10 7 bit character length 11 8 bit character length 2 Stop Bit Select 0 1 stop bit 0 1 2 stop bits 1 5 if VOLCR 1 0 00 l 3 Parity Enable 0 Disable parity generation and checking 0 1 Enable parity generation and checking 5 4 Parity Select 00 Odd parity Number of 1s in the transmitted character andthe 0 attached parity bit will be odd 01 Even Parity Number of 1s in the transmitted character and the attached parity bit will be even 10 Forced 1 stick parity 11 Forced 0 stick parity 6 Break Control 0 Disable break transmission 0 1 Enable break transmission Output pin UARTO TXD is forced to logic 0 when UOLCRI 6 is active high 7 Divisor Latch 0 Disable access to Divisor Latches 0 Access Bit DLAB 4 Enable access to Divisor Latches 9 3 9 UARTO Line Status Register UOLSR OxE000 C014 Read Only The UOLSR is a read only register that provides status information on the UARTO TX and RX blocks Table 84 UARTO Line Status Register UOLSR address 0xE000 C014 read only bit description Bit Symbol Value Description Reset value 0 Receiver Data UOLSRO is set when the UORBR holds an unread character and is cleared 0 Ready when the UARTO RBR FIFO is empty RDR 0 UORBR is empty 1 UORBR contains valid data 1 Overrun Error The overrun error condition is set as soon as it occurs An UOLSR read clears 0 OE UOLSR1 UOLSR1 is set when UARTO RSR has a new character assembled and the UARTO RBR FIFO
14. he interrupt interface contains registers UOIER and UOIIR The interrupt interface receives several one clock wide enables from the UOTX and UORX blocks Status information from the UOTX and UORX is stored in the UOLSR Control information for the UOTX and UORX is stored in the UOLCR Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 93 Philips Semiconductors UM10120 ja Volume 1 Chapter 9 UARTO NTXRDY TXDO bi UOTHR i UOTSR a NBAUDOUT RCLK NRXRDY UORBR UORSR oom OINTR UOIER x pL LT UOIIR UOFCR UOLSR UOSCR UOLCR PA 2 0 PSEL PSTB PWRITE PD 7 0 Niece PRIS AR MR PCLK Fig 18 LPC2131 2 4 6 8 UARTO block diagram Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 94
15. n this bit will automatically clear the UARTO FIFOs 1 RX FIFO 0 No impact on either of UARTO FIFOs 0 Reset 4 l Writing a logic 1 to UOFCR 1 will clear all bytes in UARTO Rx FIFO and reset the pointer logic This bit is self clearing 2 TX FIFO 0 No impact on either of UARTO FIFOs 0 Reset 1 Writing a logic 1 to UOFCR 2 will clear all bytes in UARTO TX FIFO and reset the pointer logic This bit is self clearing 5 3 0 Reserved user software should not write ones to NA reserved bits The value read from a reserved bit is not defined 7 6 RX Trigger These two bits determine how many receiver 0 Level UARTO FIFO characters must be written before an 00 interrupt is activated Trigger level 0 1 character or 0x01 01 Trigger level 1 4 characters or 0x04 10 Trigger level 2 8 characters or 0x08 11 Trigger level 3 14 characters or OxOE UARTO Line Control Register UOLCR 0xE000 CO0C The UOLCR determines the format of the data character that is to be transmitted or received Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 90 Philips Semiconductors UM10120 R volume 1 Chapter 9 UARTO Table 83 UARTO Line Control Register UOLCR address 0xE000 COOC bit description Bit Symbol Value Description Reset value 1 0 Word Length 00 5 bit character length 0 Select 01 6 bit c
16. pe Interrupt Source Interrupt Reset value 0001 None None a 0110 Highest RX Line Status Error OEL or PEL or FELI or BIZ UOLSR Readl2 0100 Second RX Data Available Rx data available or trigger level reached in FIFO UORBR Read or UOFCRO 1 UARTO FIFO drops below trigger level 1100 Second Character Time out Minimum of one character in the Rx FIFO and no UORBR Read indication character input or removed during a time period depending on how many characters are in FIFO and what the trigger level is set at 3 5 to 4 5 character times The exact time will be word length x 7 2 x 8 trigger level number of characters x 8 1 RCLKs 0010 Third THRE THRE UOIIR Read if source of interrupt or THR write 1 Values 0000 0011 0101 0111 1000 1001 1010 1011 1101 1110 1111 are reserved 2 For details see Section 9 3 9 UARTO Line Status Register UOLSR OxE000 C014 Read Only 3 For details see Section 9 3 1 UARTO Receiver Buffer Register UORBR 0xE000 C000 when DLAB 0 Read Only 4 For details see Section 9 3 6 UARTO Interrupt Identification Register UOIIR 0xE000 C008 Read Only and Section 9 3 2 UARTO Transmit Holding Register UOTHR 0xE000 C000 when DLAB 0 Write Only Koninklijke Philips Electronics N V 2005 All rights reserved User manual Rev 01 24 June 2005 89 Philips Semiconductors UM1 01
17. received data bit If the character received is less than 8 bits the unused MSBs are padded with zeroes The Divisor Latch Access Bit DLAB in UOLCR must be zero in order to access the UORBR The UORBR is always Read Only Since PE FE and BI bits correspond to the byte sitting on the top of the RBR FIFO i e the one that will be read in the next read from the RBR the right approach for fetching the valid pair of received byte and its status bits is first to read the content of the UOLSR register and then to read a byte from the UORBR Table 74 UARTO Receiver Buffer Register UORBR address 0xE000 C000 when DLAB 0 Read Only bit description Bit Symbol Description Reset value 7 0 RBR The UARTO Receiver Buffer Register contains the oldest undefined received byte in the UARTO Rx FIFO UARTO Transmit Holding Register UOTHR 0xE000 C000 when DLAB 0 Write Only The UOTHR is the top byte of the UARTO TX FIFO The top byte is the newest character in the TX FIFO and can be written via the bus interface The LSB represents the first bit to transmit The Divisor Latch Access Bit DLAB in UOLCR must be zero in order to access the UOTHR The UOTHR is always Write Only Table 75 UARTO Transmit Holding Register UOTHR address 0xE000 C000 when DLAB 0 Write Only bit description Bit Symbol Description Reset value 7 0 THR Writing to the UARTO Transmit Holding Register causes the data NA to be stored in the UARTO transmit
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