Quartus II Introduction
Contents
1. Specify the other EDA tools used with the Quartus II software to develop your project Run Tool Automatically Run this tool automatically to synthesize the current design _ Run gate4evel simulation automatically after compilation Figure 4 Setting EDA Tools default 6 Click Next at the Summary window 7 Click Finish 8 Anew project named tutorial should be created in the Quartus window as shown in Figure 5 Q Quartus I 32 bit C Ngo classes EC262 Fall2012 Quartus_Tutorial tutorial tutorial lolo x File Edit View Project Assignments Processing Tools Window Help Search altera com OSG Z e oo fmt BY 27GVS Tr SH ME OO 4 Entity Cydone II EP2C35F672C7 gt tutorial 4E Take an bhi Online Training SS Class for Free Learn What s New Download S l Take Free Online Training Task 4 Compile Design 4 Analysis amp Synthesis E Edit Settings ES View Report Analysis amp Elaboration gt Partition Merge n E Version 12 U 4 C Netist Viewers RTL Viewer State Machine Viewer a Technology Map Viewer Post gt Design Assistant Post Mapping gt B 1 0 Assignment Analysis ee S S Ww Buy Software Documentation x Y lt lt Search gt gt Type Message Messages x Locate 0 00 00 00 Figure 5 Quartus II window with a new project ll Creating a New Schematic Block Diagram As a design examp2. figure below File Edit View Simulation Help 5 Search altera com ET b eq 2 8 h Ze ae Mc XG XP Mn ee An Master Time Bar 20 0 ns m Pointer 21 44n5 Interval 1 44ns Timing simulation mode shows Tiea 10 0 ns 20 0 ns 30 0 ns 40 0 ns l ee l a propagation 7 ue 20 0 ns C 5 139 95 I delay of 5 139 ns F o 00 00 00 Figure 31 Simulation Report for timing simulation mode with propagation delay 20 V Pin Assignments Some of the most commonly used features of the DE2 board are listed in the table below Refer to the user manual for the complete list of pin assignments For DE2 70 boards refer to the user manual for pin assignments Swit PIN_N26 SW 2 PIN P25 sw 3 Ss PIN_AE14 KEY 0 _ PIN_G26 KEY _ PIN_N23 KEY 2 PIN_P23 PIN_AF23 PIN_AB21 PIN_AC22 PIN_AD22 PIN_AD23 PIN_AD21 PIN_AC21 PIN_AA14 PIN_Y13 PIN_AA13 PIN_AC14 PIN_AD15 PIN_AE15 PIN_AF13 PIN_AE13 PIN_AE12 PIN_AD12 PIN_AE22 PIN_AF22 PIN_W19 PIN_V18 PIN_U18 PIN_U17 PIN_AA20 PIN_Y18 LEDG 8 PIN Y12 2 y CLOCK 27 PIN_D13 2 MHz clock input CLOCK_50 PIN_N2 90 MHz clock input EXT CLOCK PIN _ P26 External SMA clock input Assign pins to input and output signals For this example we will use SW1 for x2 SWO for x1 and LEDG O green LED O for output f 1 Select Assignments gt Pin Planner From th
3. is made to the any files the project must be saved and compiled again 12 IV Simulating the Designed Circuit Before implementing the designed circuit in the FPGA chip it is important to simulate it to verify the correct functionality of the circuit First we need to create waveforms for all the input signals of the circuit The simulator will generate the output waveforms after successful simulation 1 From Quartus II software select File gt New Then click on the University Program VWF option Block Diagram Schematic File EDIF File Osys System File State Machine File SystemVerilog HDL File Td Script File Verilog HDL File VHDL File 4 Memory Files Hexadecimal Intel Format File Memory Initialization File 4 Verification Debugging Files In System Sources and Probes File Logic Analyzer Interface File SignalTap II Logic Analyzer File University Program VWF 4 Other Files AHDL Indude File Block Symbol File Synopsys Design Constraints File Text File Figure 17 Create a new input waveform file 2 A simulation waveform editor will be displayed as shown in Figure 18 13 File Edit View Simulation Help Ey Search altera com HS A amp AZ Xe Mew XE OD XA we oe A Master Time Bar 0 ps a gt Pointer 203 13 ns Interval 203 13ns Start End 560 0 ns 640 0 ns 720 0 ns 800 0 ns 880 0 ns 960 0 n Figure 18 Simulation Waveform Editor 3 From the Simulation Waveform Edito
4. 0 0 ns 240 0 ns zi 1 1 1 1 POL TOTOO OII ST TOTOO T I RT TO T I R RT TO O I I T T OTO I R S T OO I WOO WO WW OW WWW R R RT RTO R T RT OW WOW R ROOI Figure 26 Setting x2 to logic 1 between 40ns and 60ns 18 File Edit View Simulation Help 5 Search altera com a ee DA eo A ZEE BEE We oR ne Aa RE com bi nations Master Time Bar 0 ps gt Pointer 94 15ns Interval 94 15ns Start 80 0ns End 160 0 ns of X 1 an d x2 zume Ops 20 0 ns 40 0 ns 60 0 ns 80 0 ns 100 0 ns 120 0 ns 140 0 ns 160 0 ns 180 0 ns 200 0 ns 220 0 ns 240 0 ns Name I I i I I I I 0ps U ps ie 00 01 10 B xi BO eal 7 eee eee 3 out f BX EESSI generated in 80 ns aa a p 0 00 00 00 Figure 27 Input waveforms 17 Save the input waveform file 18 To verify the correctness of the circuit perform functional simulation To include propagation delay of the circuit in the simulation perform timing simulation We will use functional simulation in this example 19 From the Simulation Waveform Editor window click Simulation Options Then select one of the installed simulators 9 arch ateracomn TB AZ Xe Me OW XC XE R mR mS A BE Master Time Bar 0 ps a gt Pointer 16 74ns Interval 16 74ns Start 80 0 ns End 160 0 ns Ops 20 0 ns 40 0 ns 60 0 ns 80 0 ns 100 0 ns 120 0 ns 140 0 ns 160 0 ns 180 0 ns 200 0 ns 220 0 ns 240 0 ns Name Value at 1 1 1 1 1 1 i 1 1 1 1 1 D 0ps
5. Hardware Figure 35 USB Blaster hardware setup W Programmer C Documents and Settings Hau Ngo My Documents EC262 Fall2012 Quartus_Tutorial tutorial tutorial tutorial cdf File Edit view Processing Tools Window Hep lt i Hardware Setup USB Blaster USB 0 Mode sTaG Progress fe C Enable real time ISP to allow background programming for MAX II and MAX devices File Device Checksum Usercode Program verify Blank Examine Security Erase ISP pl start Configure Check Bit CLAMP WA tutorial sof EP2C35F672 002F836D FFFFFFFF Sto p X Delete ee Change File a Save File 5 up Down ABERA gt EP2C35F672 Figure 36 Programming the DE2 board with USB Blaster cable 5 The configuration file tutorial sof should be selected and shown as default Press Start 6 You can now test the designed circuit with SWO SW1 and LEDGO 24 VII Working with Multiple Files in a Project Now let s expand the previous example to control a single light from one of the four switches x1 X2 X3 and x We will use three copies of the previous circuit in this example as shown in the figure below Figure 37 Light controller circuit with 4 switches 1 First we will create a symbol for the previous circuit From the Quartus II software open the schematic file name light bdf 2 Select File gt Create Update gt Create Sy
6. Quartus II Introduction Software version Quartus II version 13 0 or later Altera board DE2 board Topics to be covered l Il IIl IV V VI VII Create a new project Create a schematic design entry Or create a VHDL design entry Compile the design Simulate the designed circuit Assign pins Program and configure the FPGA device Work with multiple design files in a project This document is created based on Quartus II Introduction Using Schematic Designs from Altera l Creating a New Quartus II Project 1 Select File gt New Project Wizard Click Next 2 You should create a new folder for each project Set this folder as the working directory You will need to select a name for the project Choose tutorial for both the project and the top level design entity as shown in Figure 1 Then click Next Directory Name Top Level Entity page 1 of 5 What is the working directory for this project C Ngo classes EC262 Fall20 12 Quartus_Tutorial What is the name of this project tutorial What is the name of the top4evel design entity for this project This name is case sensitive and must exactly match the entity name in the design file tutorial Figure 1 Creating a new project 3 Specify any design files you want to include in this project Assuming that we don t have any existing files click Next Add Files page 2 of 5 Note you can always add design files to the project later Select the
7. Tools Window Help amp Search altera com 2 Doha amp tO om nto Y EGVS Grr sS wer oO ig Project Navigator eax light bdf x Entity Cydone II EP2C35F672C7 gt tutorial 2E by ewe Tasks 98x ron Task 4 Compile Design 4 Analysis amp Synthesis a E Edit Settings ES View Report Analysis amp Elaboration gt P Partition Merge 4 C Netist Viewers RTL Viewer Q State Machine Viewer x Y lt lt Search gt gt v Type Message Messages Location v Locate 626 157 0 00 00 00 Figure 8 A Graphic Editor window 3 Double click inside the Graphic Editor window to bring up the Symbol Importing window as shown in Figure 9 Select the item you want from the Libraries list box To expand or contract the list click on the plus or minus sign respectively Note that most items you need will be in the primatives logic or primatives pin folder Alternatively you may type the name of the item you want in the Name box from Table 1 and2 2 input AND gate in this case Click OK Libraries 4 amp c altera 12 0sp1 quartus libraries gt I megafunctions gt I others 4 amp primitives gt 5 buffer 4 amp logic tF andiz ET and and3 Er and4 m Name and Repeatinsert mode Insert symbol as block Launch MegaWizard Plug In MegaWizard Plug In Manager Figure 9 Importing a logic symbol
8. ate Update IPS File aeoe ihe Aa tipi AN E E E E aa E a aE E E Gi fp sig 4 A E a E E aed Sn eo a a ee ota doe 4 v a Analysis amp Synthesis Create Board Level Boundary Scan File Sah med g els ray o Sana E a aleve ake Gras a Mee gen once ae Gnu ght den Gaels Mae Arges Sane sy a Edit Settings SSS S A es Sara prt EE Sale e Ge emt ee O alge ts a A es Ree Skee eee ee es amp So a a a a A l ee ee ee ee ee B View Report ESE ee ee a a eee ee Y Analysis amp Elaboration Be E eta cyte Sik ae Grate hae ae Gace ye th ee gates sd le aun ag ee ae se ae ans ate ay the fede ay ete es ae ae He Figure 38 Creating a symbol for light controller circuit 25 Create a new schematic file by selecting File gt New and choosing Block Diagram Schematic File and click OK Double click in the empty schematic file to bring up the Symbol window Click the arrow next to the Project folder to see all components in your project You should have a component named light under the Project folder as shown in the Figure below 4 amp Project EI light b c altera 12 0sp1 quartus libraries Repeat nsert mode E Insert symbol as block _ Launch MegaWizard Plug In Figure 39 Inserting new light component 6 Insert 3 light components 4 inputs and one output 7 Connect all components to create a new circuit as shown in the figure below ee Seen eee x2 Ss S anes bas ica ONs A E E a T we light E e ee 4 o on ee we mE e a a aa
9. design files you want to include in the project Click Add All to add all design files in the project directory to the project File name File Name Type Library Design Entry Synthesis Tool Specify the path names of any non default libraries User Libraries HDL Version Remove Up Down Properties Figure 2 Add ing existing files 4 Specify the FPGA device as shown in Figure 3 Select Cyclone II from the Family drop down list Select EP2C35F672C6 or EP2C70F896C6 if Family amp Device Settings page 3 of 5 Select the family and device you want to target for compilation DE2 70 is used from the Available devices Device family ray Devices All bl Target device Auto device selected by the Fitter Specific device selected in Available devices list Other n a Core Voltage EP2C35F484C7 1 2V EP2C35F484C8 1 2V LEs 33216 33216 User I Os 322 322 483840 483840 EP2C35F672C7 1 2V EP2C35F672C8 1 2V 483840 322 483840 475 483840 475 475 aA Show in Available devices list padage Pn cant Seed grade Name filter Show advanced devices HardCopy compatible only amp Memory Bits Embedded multiplier 9 bit elements 16 16 16 is Ul HardCopy _ Limit DSP amp RAM to HardCopy device resources Figure 3 Selecting a device 3 5 Keep all EDA Tools settings Figure 4 Click Next EDA Tool Settings page 4 of 5
10. e 33 Assigning pins to inputs and output 3 Close the Pin Planner window Save and re compile the Quartus project VI Programming and Configuring the FPGA Device 1 Verify the RUN PROG switch is in Run position 2 Connect the power and USB cables to the DE2 board USB Blaster Port 3 Turn on the power to the DE2 board 4 From the Quartus II software select Tools gt Programming Note that No Hardware is shown as default as shown in Figure below press Hardware Setup button and select USB Blaster USB 0 Y Programmer C Ngo classes EC262 Fall2012 Quartus_Tutorial tutorial tutorial tutorial cdf E Fie Edit View Processing Tools Window Help amp sora E Enable real time ISP to allow background programming for MAX II and MAX V devices Search altera com pis Device Verify Blank Examine Security Erase Start e Check Bit gilt Stop EP2C35F672 de Auto Detect X Delete a Add File at Change File fet Save File Add Device Down EP2C35F672 Figure 34 Programming window 23 gt Hardware Setup Hardware Settings JTAG Settings Select 4 programming hardware setup to use when programming devices This programming hardware setup applies only bo the current programmer window Currently selected hardware USB Blaster USB 0 wt Available hardware items Hardware Server Add Hardware LISB Blaster Local Remove
11. e Pin Planner window select View and make sure that All Pins List option is checked as shown in the Figure below Named Top View Wire Bond Cyclone II EP2C35F672C6 i23 4 5 6 7 8 10 11 2 13 14 15 16 17 18 8 20 21 22 23 24 235 W Aw A SHVOOOVOAOOK ONE ONY WC wh 25 HOPE A ml INO O O O amp 0 x ANOOOOVO O INVAN NNG OV A ZVANVV VV ANANA OOO QO ANYAVAYAVAYAVZIN SA N V 2 VOAR O OEO SC gt ae DOBOOODOOOS WR OS Feo Fi oo Bi SX OOOOODOOOOOOOOOOOO lt 10 AO V OVA VOOOOOCOVA YAO OOOO OOAOOOOOOOOOOAG VA OOOAA OAOCVOAADVAOVOOA 100 OV OOMOO0 CAMO SAOO QOS YIOIVVIOVIOOOOOYOOOOIOMIYV4 CIGIGIC TPO OOOOOOLS lt F lt SOOOCOOOL s SOOOHOOOS VO00000080000MO00V000 O00 1 2 3 4 5 6 7 8 0 11 2 13 14 15 16 17 18 8 2 2 2 23 24 25 4 mee ON N Nn _ ET h Node Name Direction Location I O Bank VREF Group Fitter Location 1 O Standard Reserved Current Strength Differential Pair D f Output PIN_C11 3 3 V LV default 24mA default D x1 Input PIN_C13 3 3 V LV default 24mA default D x2 Input PIN_D13 3 3 V LV default 24mA default lt lt new node gt gt Figure 32 Pin Planner window 2 Inthe Location column assign PIN _AE22 green LED 0 to f PIN_N25 SWO to x1 and PIN_N26 SW1 to x2 T a A 0 andat Reserved 1 0 Bank Current Strength VREF Group KS amp ganen node gt gt Figur
12. e a a e w ceereeserece R OUTPUT oe SEa x1 f ae i eee eee 7 ees ee ee x2 U xd a ka O insti Figure 40 Drawing the new design with 4 switches 26 10 11 12 Save the new file as light2 bdf Set the light2 bdf as the Top Level Entity Then compile and simulate the design as before Verify the correctness of the new design Assign pins to 4 switches and LEDG 0 Compile the project again Then program the DE2 board with the new design Verify the design using 4 switches and LEDG 0 on the DE2 board 27
13. from libraries Table 1 Devices and corresponding symbol names 4 Using the mouse move the symbol to a desirable location and click to place it there 5 Repeat steps 3 and 4 to import one and2 one or2 and two not symbols You can rotate a symbol by clicking on the symbol to select it right click gt Rotate by Degrees 6 Import 2 inputs and 1 output symbols 7 Assign name to input and output symbols For example double click on the first input and type x1 in the Pin name s box as shown in Figure 10 Assign x2 to the second input and f to the output symbols WS iA To create multiple pins enter a name in AHDL bus notation For example name 3 0 or enter a comma seperated list of names Pin name s xil pefault value Figure 10 Assigning input name PocetocedocefesoteoNocobosobose ose scot esAocotocoboce sse soodes osobosotoes sses o o o o o 8 o o o o o o o o o o o o o o o Figure 11 Assigning names to input and output symbols 8 Connect the symbols by drawing lines wires with the Orthogonal Node Tool icon I Figure 12 Block diagram for a light controller circuit 9 Save the file Creating a VHDL File Instead of creating your design with a schematic file you can implement your design with VHDL For example to implement the light controller circuit above we can follow these steps 1 Select File gt New and choose VHDL File and click OK 2 Type in y
14. le we will use the two way light controller circuit shown in Figure 6 The circuit can be used to control a single light from either of the two switches x and x2 Note that this can be achieved by an XOR gate but we will implement it using the gates shown X1 X2 Figure 6 Light controller circuit with 2 switches Steps to create a new block diagram for the light controller circuit 1 Select File gt New to get the window in Figure 7 choose Block Diagram Schematic File and click OK New Quartus II Project 4 Design Files AHOL File Block Diagram Schematic File EDIF File Qsys System File State Machine File SystemVerilog HDL File Td Script File VHDL File Verilog HDL File 4 Memory Files Hexadecimal Intel Format File Memory Initialization File 4 Verification Debugaing Files In System Sources and Probes File Logic Analyzer Interface File SignalTap IT Logic Analyzer File Synopsys Design Constraints File Text File Figure 7 Creating a new block diagram 6 2 Specify a name for the file Select File gt Save As Save this file in the same project directory default as light bdf Note that a filename must have no spaces Put a checkmark in the box Add file to current project Click Save This step should open a Graphic Editor window as shown in Figure 8 Q Quartus II 32 bit C Ngo classes EC262 i i i o x File Edit View Project Assignments Processing
15. mbol Files for Current File 3 Use the default file name light bsf and press Save a o classes EC262 Fa Qua gt Tu stor File Edit View Project Assignments Processing Tools Window Help amp O New Ctrl N a Open Ctrl 0 Close Ctri F4 New Project Wizard Open Project ctrl J Save Project Close Project Le Save Ctrl s Save As Gi Save all Ctrl Shift S File Properties Create Update Create HDL Design File from Current File if o E ee Export Create Symbol Files for Current File ENS a a Mea Convert Programming Files Create AHDL Include Files for Current File sagi en p Ae ara amp a Comer adem RI i Gd BE yh Da Tie NE aTe gn AI Page Setup Create Verilog Instantiation Template Files for Current File FT ee A Print Preview Create VHDL Component Dediaration Files for Current File fo amp Print Ctrl P Create Design File from Selected Block Ea aA e E a AE EE E a Sick a E a a Gob Mca Gb G AE E N 66 4 DES IDA EE E TA Recent Files 7 Update Design File from Selected Block Se eet eaa a nE ra Gedy E a a a a a ch ee a a E a ce Recent Projects gt Create SignalTap II File from Design Instance s as E Reais dee Oho ace acne E sas dns GaresanGre a Grane o Emtnas A ar ete ao ene aed Stnace ated Create SignalTap TllistFile ee ee usa Create JAM JBC SVF or ISC Fil SSELSEET TOE AEDT ES SESS ELSE REE ORT REL TE DR ORE TE OEE TEE SIRT TELLS SOURS v a Compile Design Cre
16. ount every field Note that all combinations of the two input waveforms x1 and x2 are generated within the first 80 ns of the simulation window they repeat the same patterns after that Sometimes you will need to modify the input signals manually for specific time periods to better simulate the circuit behavior For instance in this example only one switch should be changed at a time However with the current settings both switches are sometimes changed at the same time Click on x2 waveform at 40ns mark hold and drag the mouse to 60ns mark and release the mouse to highlight that duration 40ns to 60ns 17 File Edit View Simulation Help 5 Search altera com MA He A Ze a Wy YC TF Re oe Ay BK Master Time Bar 0 ps 100 0 ns 120 0 ns 140 0 ns 160 0 ns 180 0 ns 200 0 ns 220 0 ns 240 0 ns I j Figure 25 Selecting and highlighting x2 between 40ns and 60ns duration 1 14 Click Forcing High 1 icon 1 to set x2 to logic 1 between 40ns and 60ns 15 Repeat to set x2 to logic O0 between 60ns and 80ns marks 16 The final input waveform file is shown in Figure 27 Note that all possible combinations of switches x1 and x2 are generated appropriately between 0 and 160ns marks File Edit View Simulation Help 5 Search altera com ge Ma Ko A ZX ye WC ER A EE Master Time Bar 0 ps a gt Pointer 24 71ns Interval 24 71ns Start 40 0 ns End 60 0ns 120 0 ns 140 0 ns 160 0 ns 180 0 ns 200 0 ns 22
17. our VHDL code for the design as shown in Figure 13 u oo oy in w Pi je h peb peh pei pb pb pi je 0 U b whe G Library declaration library IEEE Declare which VHDL library use IEEE std logic 116 all and packages to use Entity declaration ENTITY li ght vhdl I5 PORT Xl XZ IN SID LOGIC OUT SID LOGIC bs END light vhdl Architecture body ARCHITECTURE arch OF light vhdl I5 _BEGIN E lt x1 AND NOT x2 OR NOT x1 AND x2 END arch Figure 13 VHDL code for a light controller circuit 1 Save the VHDL file as light_vhdl vhd Note that the entity name and the file name must be the same 10 Hl Compiling the Design File Circuit 1 From the Quartus II window click on the Files tab Right click file that you want to compile light bdf and Set as Top Level Entity This step instructs the compiler to look for the correct design file to compile Project Navigator vax tal E3 Files light bdf Open Remove File from Project Set as Top Level Entity Ctrl4Shift J Properties Figure 14 Setting the top level entity 2 Runthe Compiler by selecting Processing gt Start Compilation Alternatively you may clicking on the toolbar icon that looks like a purple triangle When the compilation is finished with no errors a Summary window will be displayed as shown in Figure 15 If errors occur the compiler should indica
18. ps boj xi BO DI x2 BO on f BX DOO OO OOT OOT T N O T N OT O T O T O T O O N O T N T N OT O NO T N O N O O N O OO Options Simulator ModelSim Recommended Quartus II Simulator Lox cancel al 0 00 00 00 Figure 28 Simulation settings 20 Select Simulation gt Run Functional Simulation 19 File Edi Simulati econ tt 5 Wa cba Run Functional Simulation Master Time Bar q Interval 20 3ins Start 80 0ns End 160 0 ns 4 Run Timing Simulation Prarie a a leek 100 0ns 120 0ns 140 0ns 160 0ns 180 0ns 200 0ns 220 0ns 240 0ns COCCCOCUTOCCLCOTUOCV ONOONO ONOONO ONNENN NNN Figure 29 Starting simulation 21 Simulation Waveform Report should be displayed as shown in the figure below Note that the output waveform f is generated based on the behavior of the designed circuit Verify its correctness for all possible input combinations Search altera com l MA Ae A Ze Xo Me BY Xe RA wm ee A EE Master Time Bar 0 ps gt Pointer 20 31ins Interval 20 3ins Start 80 0 ns End 160 0ns G Simulation Waveform Editor tutorial sim vwf Read Only ol xs Figure 30 Simulation Report 22 Exercise repeat the simulation using timing simulation mode Simulation gt Run Functional Simulation The output should show propagation delay as illustrated in the
19. r window Select File gt Save As and save the file as light vwf in the same project directory es G o 0 UBE Figure 19 Saving the new input waveform file 14 4 Set the simulation time by selecting Edit gt Set End Time from the Waveform Editor Entering 1us for the simulation time 160 0 ns 240 0 ns 320 0 ns 400 0 ns 480 0 ns 560 0 ns 640 0 ns 720 0 ns 800 0 ns 880 0 ns 960 0 ns F j j I I I p 0 00 00 00 Figure 20 Setting simulation time 5 Add input and output signals Click Edit gt Insert gt Insert Node or Bus or double click on the left pane of the waveform to open a node finder window W Insert Node or Bus Mode Finder Finder Display gray code count as binary count Figure 21 Insert Node or Bus window 6 Click Node Finder button Make sure to select Pins all from the drop down list of the Filter field then click List button 7 Click gt gt button 15 x Node Finder ook a Nodes Found Selected Nodes Figure 22 Node finder window 8 Click OK button to close Node Finder window Again Click OK button close Insert Node or Bus window File Edit View Simulation Help 5 Search altera com Pa gen AEREE R R e An Ey Start 0ps End 0ps Master Time Bar 0ps a gt Pointer 5 49 ns Interval 5 49 ns 640 0 ns 720 0 ns 800 0 ns 880 0 ns 960 0 ns z P Lo a Value at Ops 80 0 n
20. s 160 0 ns 240 0 ns 320 0 ns 400 0 ns 480 0 ns 560 0 ns Ops 0 ps x1 BO a x2 BO u f BX COO O46 OOO OVO ONON T ON TO O OCO O OCO COC OCOC OC OCOC OCO OCOC OCOC OCOC TOC aC T a a NaCN Oaa Oa aO OO OO OCO OOOO OO rii lt m 0 00 00 00 Figure 23 Waveform file with inputs and output 9 Note that it is possible to rearrange the waveforms To move a waveform up or down in the Waveform Editor window click within the node s row i e on its name icon or value and 16 10 11 T2 13 release the mouse button The waveform is now highlighted to show the selection Click again on the waveform and drag it up or down in the Waveform Editor Move f waveform to the bottom Specify logic values for all input waveforms Ideally we want to specify all possible combinations of the input signals For large circuit it may not be possible to generate all possible combinations so we have to select a small but representative number of combinations For this example it is simple enough to generate all combinations of input signals Click on waveform x2 to highlight it Then click the Count Value icon ME Enter 20ns in the Count every field Click OK button Count Value Radix Count type Binary Gray code Transitions occur Count every Figure 24 Simulating input signal x2 to toggle every 20 ns Click on waveform x1 to highlight it Then click the Count Value icon Le Enter 40ns in the C
21. te what these errors are in the message box Warnings can be ignored Flow Summary Flow Status Quartus II 32 bit Version Revision Name Toptevel Entity Name Family Device Timing Models 4 Total logic elements Total combinational functions Dedicated logic registers Total registers Total pins Total virtual pins Total memory bits Embedded Multiplier 9 bit elements Total PLLs Successful Thu Aug 30 14 43 37 2012 12 0 Build 232 07 05 2012 SP 15 Web Edition tutorial light Cyclone II Final 1 33 216 lt 1 1 33 216 lt 1 0 33 216 0 0 3 475 lt 1 0 0 483 840 0 0 70 0 0 4 0 Figure 15 Summary of a successful compilation 11 x Y lt lt Search gt gt v Type Message Wp Info 332001 The selected device family is not supported by the report _metastability command i Info 332102 Design is not fully constrained for setup requirements Sy Info 332102 Design is not fully constrained for hold requirements gt i Info Quartus II 32 bit TimeQuest Timing Analyzer was successful 0 errors 4 warnings b gt W Info Quartus II 32 bit Assembler was successful 0 errors 0 warnings Wp Info 293026 Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE POWER_ANALYZER Wi Info 293000 Quartus II Full Compilation was successful 0 errors 12 warnings acatinn Figure 16 Message box indicates 0 errors 12 warnings Note that every time a change
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