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FT-86C and FT-86C/FP USER`S MANUAL FORWARD

1. rooroor soq Bie TIUORIO 86 SELECTED PAD LOCATIONS 3 2 4 STRAPPING 2 gt wy ere 7 72 gt 2 AS BUS PRIORITY STRAPPING CUT TO ENABLE H28B 5 06006 Nee PPL PELPPPLPPLILIPPPEPOLPELELOGLLEOLAEOEL LT EE 7 MN t US NUN o at rrr 1o nor 22222924 NOE 27720 2022702729722 202222275555 555555526 22222224 p X NE 44 SANA SS SS aS 9 642440666076 OEP Hy Srey NS 257 e 24 2 2 Figure 2 2 MULTIBUS CONTROL STRAPPING CUT amp JUMPER TO PAD 8 FOR ANYROST HIGH BUS CLOCK STRAPPING CUT TO DISABLE COMMON CLOCK STRAPPING CUT TO DISABLE EXAMPLE 1 Change Channel to 9600 1 Cut trace between 7D 11 and 99 to free trace from pad 99 to pad 16 2 Add jumper between pads 98 and 99 to place 9600 baud clock on pad 16 Cut jumpers between pads 15 and 17 to separate Channel A and B clocks Jumper pad 16 to pad 15 make sure jumper between 13 15 is intact R9 9600 og 2999597 3D1 on schematic 2400 596 8D on board 1200 o5 19 20 UO 18 15 16 3D2 on schematic e O 6H on board 13 _14 600 102
2. Compiled within system object code to indicate that the next byte is a single character literal i e in range 255 Used only in system code not by application program i e user Appli cation programs use LITERAL which uses CLIT or LIT as appropriate GROUP ATTR CONTROL MEMORY DICTIONARY INPUT OUTPUT MEMORY MISC STACK WORD CMOVE COLD COMPILE CONSTANT CONTEXT STACK NOTATION DEF INITION addrl addr2 n c move Moves n bytes from memory area beginning at address addrl to memory area starting at addr2 The contents of addrl is moved first proceeding toward high memory If n is zero or negative nothing is moved cold The cold start procedure to adjust the dictionary pointer to the minimum standard and restart via ABORT be called from the terminal to remove application programs and restart Per forms the same functions as entering control FORTH by a reset or power on sequence compile When the word containing executes the compilation address of the next non immediate word following COMPILE is copied compiled into the dictionary This allows specific compilation situations to be handled in addition to simply compiling an execution address which the inter preter already does n lt name gt compile time lt name gt run time constant A defining word used in the form n CONSTANT lt name gt To create a dictiona
3. blanks Fills an area of memory beginning at addr with the ASCII value for blank the number of bytes specified by count n will be blanked addr B ke leaves the address of a user variable containing the number of the mass storage block being inter preted as the input stream If the content is zero the input stream is taken from the terminal This variable is used internally and is included so that later mass storage words can be added GROUP NUMERIC 1 CONTROL INPUT OUTPUT MEMORY MASS U 15 WORD BRANCH C L CFA CLIT STACK NOTATION DEF INITION branch The run time procedure to unconditionally branch An in line offset is added to the interpretive pointer IP to branch ahead or back BRANCH is compiled by ELSE AGAIN and REPEAT n addr e store Stores the least significant 8 bits of n into the byte at the address n c comma Stores the least significant 8 bits of n into the next available dictionary byte advancing the dictionary pointer characters line Leaves the number of characters default value 80 per input line addr byte c fetch Leaves the 8 bit contents of the byte at the address on the top of the stack in the low order byte high order byte is zero pfa cfa Converts the parameter field address pfa of definition to its code field address cfa db
4. 40 APPENDIX RECOMMENDED READING BRODIE L FORTH INC Starting FORTH Prentice Hall Englewood Cliffs New Jersey 07632 HARRIS FORTH Extensibility or How to Write a Compiler in 25 Words or Less BYTE Magazine August 1980 pp 164 184 INTEL CORPORATION The 8086 Family User s Manual Santa Clara CA 95051 INTEL CORPORATION The 8085 Family User s Manual Numerics Supplement Santa Clara CA 95051 JAMES J S What is FORTH Tutorial Introduction BYTE Magazine August 1980 pp 100 126 Power Supplies Bus Controls Bus Controls and Address Interrupts Address Data Power Supplies APPENDIX C 86 PIN ASSIGNMENTS Pin Assignment of Bus Signals on 796 Bus Board Connector P1 COMPONENT SIDE GND 5V 5 12V GND DBCLI BPRN BUSY MRDC IORC XACK LOCK BHEN CBRQ CCLK INTA INTS INT4 INT2 INTO ADRE ADRC ADRA ADR8 ADR6 ADR4 ADR2 ADRO DATE DATC DATA DAT8 DAT6 DATA DAT2 DATO GND 12V 5V 5V GND DESCRIPTION Signal GND 5 Vde 5 Vde 12 Reserved Bussed Signal GND Bus Clock Bus Priority In Bus Busy Memory Read Command I O Read Command XFER Acknowledge Lock Byte High Enable Common Bus Request Constant Clock Intr Acknowledge Parallel Interrupt Requests Address Bus Data Bus Signal GND Reserved Bussed 12 5 Vde 5 Vde Si
5. 86 FT 86C FP USER S MANUAL FORWARD TECHNOLOGY INCORPORATED documen t number 4301000 9 81 This manual is intended to give the user of the FT 86C FT 86C FP a guide to system functionality and also to enable the user to add peripheral memory and other devices to satisfy specific requirements The FT 86C and FT 86C FP give users the capability to quickly add components without needing a detailed understanding of the 8086 or its support chips For specific device timings we recommend that you refer to the manufacturer s literature listed in Appendix B 1981 FORWARD TECHNOLOGY INC FORWARD TECHNOLOGY 2595 Martin Avenue Santa Clara 95050 PHONE 408 988 2378 TWX 910 558 2186 SEC 1 0 2 0 TABLE OF CONTENTS TITLE SPECIFICATIONS INTRODUCTION INSTALLATION PROCEDURE AND OPTIONS 2 1 MULTIBUS CONTROL 2 1 1 MUL TIBUS OPTIONS 2 2 COMMUNICATIONS OPTIONS 2 2 1 COMMUNICATIONS CLOCK STRAPPING 2 3 EPROM TYPE 2 4 WAIT STATE TIMING 2 5 INTERRUPT STRAPPING THEORY OF OPERATION FT 86C 3 1 BUS ELEMENTS 5 1 1 BUS CONTROL 5 1 2 LOCAL BUS 5 1 5 I O BUIS s 5 2 MEMORY 5 2 1 RANDOM ACCESS MEMORY 5 2 2 PROGRAMMABLE READ ONLY MEMORY 5 5 TIMING 5 5 1 CLOCK GENERATOR 5 5 2 PROCESSOR TIMING 5 5 5 BUS CONTROL TIMING 5 5 4 BUS TIMING 5 4 COMMUNICATIONS 5 4 1 READ REGISTER FUNCTIONS 5 4 2 WRITE REGISTER FUNCTIONS 5 4 3 PROGRAMMING THE WRITE REGISTERS
6. If the 8087 numeric data processor option is ordered an enhanced FORTH system is supplied in EPROM The enhancements follow the guidelines of the proposed standards committee working group version of Floating Point FORTH TIMING Two timing elements are used in the 86 the processor clock and the bus clock The processor clock is generated by an Intel 8284 The oscillator input is 15 MHz The 8284 divides by three and provides a 5 MHz 33 duty cycle clock to the processor and to the bus control elements The bus clock can either be generated by the 86 and fed onto the Multibus or can be driven via the Multibus from another bus master The bus clock is used by the bus arbiter in its bus contention circuits and also to synchronize its output commands to the bus controllers 5 3 1 In addition to providing the processor clock the 8284 synchronizes and controls the READY and RESET lines to the 8086 8087 Generation of the Multibus initialization signal INIT holds the RESET line active The READY line to the 8086 is controlled by two pairs of input signals on the 8284 One pair of inputs are used for controlling wait states for on board devices the other pair is used for external bus control i e Multibus 5 5 2 PROCESSOR TIMING The 8086 processor cycle operates in a minimum of four clock cycles called T1 T2 T3 and T4 Depending on the speed of attached memory or I O devices a variabl
7. 5 4 4 PROGRAMMING THE READ REGISTERS 5 5 INTERRUPT CONTROL PAGE 1 1 2 1 2 1 2 2 2 2 2 2 2 9 2 10 2 11 5 1 5 2 5 2 5 2 5 2 5 2 5 2 4 5 5 5 5 5 3 9 3 6 5 7 2 9 5 9 2 9 5 10 5 12 SECTION TABLE OF CONTENTS Cont TITLE 4 0 BREADBOARD INTERF ACE MEMORY ADDRESS BUS 4 1 4 2 4 5 4 4 4 5 ADDRESS BUS DATA LINES MEMORY DATA BUS DATA BUS 4 3 1 4 5 2 I O SELECT LINES CHIP SELECT DECODING 4 5 1 EPROM CHIP SELECTS 4 5 2 RAM SELECT LINES 2 0 FIRMWARE 2 1 2 2 1 CONTROLFORTH MONITOR COMMANDS oe ue 5 2 2 SUBSTITUTE 5 2 3 5 2 4 5 2 5 AND WPI ee s 5 2 6 AND WPB S27 ue o de ue hA Uu uA IR 5 2 8 RECEIVE 5 2 9 SEND 2 2 10 DUMP MONITOR COMMANDS WITH EXPLICIT SEGMENT ADDRESSES a we cx 5 X 9 8 4 9 3 1 7 2 5 3 2 SMATCH MONITOR CONTROL COMMANDS 5 4 1 SEGMENT s e gt e o o 2 4 2 TIMES RUN 2 4 5 MISMATCHES gt e e gt PAGE 4 1 4 1 4 1 4 1 4 1 4 5 4 3 4 3 4 5 5 1 5 1 5 1 5 1 5 2 5 2 5 2 5 5 5 3 5 3 5 4 5 4 5 4 5 5 5 5 5 5 5 5 5 5 5 6 5 6 FIGURE NUMBER 2 1 2 2 2 3 2 4 2 5 2 6 2 7 3 1 3 2 3 3 3 4 3 5 4 1 4 2 4 5 4 4 TABLE OF FIGURES TITLE FT 86C SELECTED PAD
8. 7 50 5 1 _ FAULTIBUS BUS ADD LATCHES ON BOARD ADD LATCHES PROM ARRAY gt 48 8 7 8 MULTIBUS BUS Bl ON BOARD BI DIRECT DATA DRIVERS CHIP SELECT LOGIC LOCAL BUS CONTROLLER 5B 9B 3B 3C 3E 3F DR j OPTIONAL EXTERNAL TCOM CLOCK f TIL TO EA lt _ CHANNEL _ CHANNEL A P TCOM CLOCK INTR LOCAL 1 0 TCOM ZILOG SIO BI DIRECT CLK GEN DRIVERS DBO 46 CHANNEL 60 70 80 90 087 gt EA TO TTL INT BUS 36 CHA CONTROLLER M CHANNEL B EA TO TIL E59 00 gk INT CHB nT 101 86 96 181 187 1 0 CONTROL LATCHES Figure 3 1 MULTIBUS CONTROL SIGNALS INTAI MRD1 MWRI IORI 10 MTROL LOGIC P1 MULTIBUS BUS INTERFACE gt BCLK amp CCLK ADRO ADR13 DATO DATF gt 0 13 10 50 10 57 SIGNALS TO CUSTOMIZING AREA OF PCB DBO DBF RXDB CTSB DCDB RXDA CTSA DCDA J1 EXTERNAL COMMUNICATIONS TXDA RTSA DTRA TXDB RTSB DTRB DIAGRAM FT 86C FP 3 3 3 4 5 5 If the FORTH monitor is ordered with the T 86C it will be in 32 Kbit EPROMs located at board positions 3A and 7A The FORTH monitor resides at memory addresses Hex FEOOO through Hex FFFFF and also at addresses Hex 0 000 through Hex OFFFF
9. DIGIT DLITERAL DNEGATE DO 2 20 STACK NOTATION DEF INITION char n n2 tf valid conversion char nl ff invalid conversion digit Converts the ASCII character using BASE nl to its binary equivalent n2 accompanied by a true flag 1 If the conversion is invalid leaves only a false flag ff d executing compiling d literal If compiling compiles a stack double number into a literal Later execution of the definition con taining the literal will push it to the stack If executing the number will remain on the stack dl dl d negate leaves the two s complement of a double precision number nl n2 run time addr n compile time Occurs in a colon definition in form LOOP DO At run time DO begins a sequence with repetitive execution controlled by a loop limit nl and an index with initial value n2 DO removes these from the stack Upon reaching LOOP the index is incremented by one At the LOOP the index is modified by a positive or negative value Until the new index equals or exceeds the limit execu tion loops back to just after DO otherwise the loop parameters are discarded and execution con tinues ahead Both nl and n2 are determine at run time and may be the result of other opera tions loops be nested Within a loop I will copy the current value of the index to the stack See I LOOP LOOP LEAVE At comp
10. LES 2 xx Mog gt 5 gt G oc002000000000002000000000000 oo oo c 00 MEMORY DATA BUS PADS GO O U 009202079 ot Q S o00000000000000020080 gt MNT ws 5 gt A RSS o E Oe 0900005000075 8G G Ho e rocroor as9 2 382 Figure 41 MEMORY ADDRESS AND DATA BUS S PAD ADDRESS Hex 4 4 I O SELECT LINES All addresses in the range of Hex 00 to Hex 53 are automatically considered on board addresses even though not all of the I O addresses are decoded The I O select lines are decoded on 8 byte boundaries Address line O is not used All I O port addresses must be even addresses Address lines 2 and 1 are available for port addressing within the selected chip Select lines 0 and 1 are used for the ZSIO and 8259A respectively Refer to Figure 4 3 for I O select line information 4 5 CHIP SELECT DECODING Chip select lines are provided for RAM EPROM and I O Spare lines are available for user added components 4 5 1 EPROM CHIP SELECTS ERPOM chip select lines are available on pads at board location B2 Select lines are decoded 8 Kbyte boundaries If the user adds PROM s using the spare select lines they must be con
11. TABLE 2 1 SIGNAL NAME Transmit Clock Channel 150 Baud TCOM Clock RXCB Receive Clock Channel B 75 Baud TCOM Clock RXCA Receive Clock Channel A 600 Baud TCOM Clock TXCA Transmit Clock Channel A 300 Baud Clock Option Strappable to 1200 2400 4800 9600 RXDB Receive Data Channel RXDB Receive Data Channel B DCDB Data Carrier Detect Channel B DCDB Data Carrier Detect Channel B CTSB Clear to Send Channel B CTSB Clear to Send Channel B TXCB Transmit Clock Channel B TXCB Transmit Clock Channel B RXCB Receive Clock Channel B RXCB Receive Clock Channel B RXDA Receive Data Channel A RXDA Receive Data Channel A RXCA Receive Clock Channel RXCA Receive Clock Channel A TXCA Transmit Clock Channel A Transmit Clock Channel A CTSA Clear to Send Channel A CTSA Clear to Send Channel A RTSB Request to Send Channel B RTSB Request to Send Channel B DTRB Data Terminal Ready Channel B DTRB Data Terminal Ready Channel B RTSA Request to Send Channel A TELECOMMUNICATION PAD ASSIGNMENTS SOURCE DESTINATION To USART Option Strap To USART Option Strap To USART Option Strap To USART From Driver To USART From Driver To USART From Driver To USART From Driver To USART via pad 13 From Driver To USART via pad 15 From Driver To USART From Driver To USART via pad 17 From Driver To USART via pad
12. Leaves a true flag 1 if the number is equal to zero otherwise leaves a false flag Same as fi addr d number Converts a character string left at addr with a preceeding count to a signed double precision number using the current number BASE If a decimal point is encountered in the text its position will be given DPL but no other effect occurs If numeric conversion is not possible an error message will be given GROUP ATTR SECURITY ARITHME TIC ARITHME TIC ARITHME TIC DICTIONARY COMPARISON FORMAT 29 WORD OR OVER PAD PFA PICK QUERY QUIT 30 STACK NOTATION DEF INITION nl n2 n3 or Leaves the bit wise logical or of two 16 bit values nl n2 nl nl over Copies the second stack value placing it as the new top of stack addr Leaves the address of a scratch area used to hold character strings for intermediate processing The maximum capacity is 64 characters nfa pfa p f a Converts the name field address nfa of a dic tionary definition to its parameter field address pfa n nth pick Returns the contents of the nth stack value not counting n itself error conditions results for n less than one 2 PICK is equivalent to OVER query Accepts input of up to characters of text or until a return from the keyboard into the ter minal input buffer TIB WORD may be used to accept text from t
13. tion of a definitions name It must be 1 through 31 with a default value of 31 The name char acter count and its natural characters are saved up to the value in WIDTH The value may be changed at any time within the above limits char addr word Receives characters from the input stream until the non zero delimiting character in the stack is encountered or the input stream is exhausted ignoring leading delimiters The characters are stored as a packed string with the character count in the first character position The actual de limiter encountered char or null is stored at the end of the text but not included in the count If the input stream was exhausted as WORD is called then a zero length will result The address of the beginning of this packed string is left on the stack 2 n5 yor Leaves the bitwise logical exclusive or of two values left bracket Ends the compilation mode The text from the input stream is subsequently executed See bracket compile Used in a colon definition in form COMPILE lt name gt Forces compilation of the following word This allows compilation of an IMMEDIATE word when it would otherwise be executed GROUP ATTR SECURITY U COMPILER ARITHMETIC COMPILER COMPILER WORD STACK NOTATION DEF INITION GROUP ATTR COMPILER 1 right bracket Sets the compilation mode The text from the input stream is subsequently compiled See 39
14. See DEFINITIONS new definitions will be created in that list New vocabularies chain to FORTH This is when all of a dictionary search through a vocabu lary is exhausted FORTH will be searched y list Lists the names of the definitions in the CONTEXT vocabulary Depression of any key will terminate the listing addr warning Leaves the address of user variable containing a value controlling messages If value 1 mass storage is present and screen 4 of drive f is the base location for messages If value f no disk is present and messages will be presented by number If value execute ABORT for a user specified procedure See MESSAGE ERROR run time while Occurs in a colon definition in the form BEGIN WHILE tp REPEAT At run time WHILE selects conditional execution based on Boolean flag If flag is true non zero WHILE continues execution of the true part through to REPEAT which then branches back to BEGIN If flag is false zero execution skips to just after REPEAT exiting the structure At compile time WHILE emplaces ABRANCH and leaves addr2 of the reserved offset The stack values will be resolved by REPEAT GROUP ATTR VOCABULARY SECURITY 1 CONTROL WORD WIDTH WORD XOR COMPILE STACK NOTATION DEF INITION addr width leaves the address of user variable containing the maximum number of letters saved in the compila
15. To read the contents of a selected read register other than RRO the user program must first write the pointer byte to in exactly the same way as a write register operation Then by executing an input instruction the contents of the addressed read register can be read The status bits of RRO and RRI are grouped to simplify status monitoring This enables the user to read all the appropriate error bits from one register RR1 READ REGISTER 0 07 os na o2 or vo Rx CHARACTER AVAILABLE INT PENDING CH A ONLY Tx BUFFER EMPTY DCD SYNCIHUNT CTS Tx UNDERRUN EOM BREAK ABORT eUSED WITH EXTERNAL STATUS INTERRUPT MODE READ REGISTER 11 07 os oa n2 or oo ALL SENT 1 FIELD BITS 1 FIELD BITS HI PREVIOUS SECOND PREVIOUS BYTE BYTE 1 0 0 0 3 0 1 0 0 4 1 1 0 0 5 T 0 0 1 0 6 1 0 1 0 7 0 1 1 0 8 1 1 1 1 8 0 0 0 2 8 PARITY ERROR RESIDUE DATA FOR EIGHT Rx OVERRUN ERROR Rx BITS CHARACTER PROGRAMMED CRC FRAMING ERROR END OF FRAME SDLC TUSED WITH SPECIAL RECEIVE CONDITION MODE READ REGISTER 2 os va o2 o1 vo v0 Vit V2t V3t INTERRUPT V4 VECTOR TVARIABLE IF STATUS AFFECTS VECTOR IS PROGRAMMED Figure 3 4 READ REGISTER FUNCTIONS 5 10 WRITE REGISTER 0 0 0 0 REGISTER 0 0 0 1 REGISTER 1 0 1 0 REGISTER 2 0 1 1 REGISTER 3 1 0 0 REGISTER 4 1 0 1 REGISTER 5 1 1 0 REGISTER 6 1 1 1 REGISTER 7 NULL CODE SEND AB
16. fa n leaves the highest address plus one available in the data or mass storage buffer Usually this is the highest contiguous system memory n lig Within a colon definition LIT is automatically compiled before each 16 bit literal number encountered in input text Later execution of LIT causes the contents of the next dictionary address to be pushed to the stack n compiling literal If compiling then compile the stack value n as a 16 bit literal which when later executed will leave n on the stack This definition is immediate so that it will execute during a colon definition The intended use is xxx calculation LITERAL Compilation is suspended for the compile time calculation of a value Compilation is then resumed and LITERAL compiles this value into the definition GROUP ATTR CONTROL DICTIONARY MISC COMPILER COMPILER A 27 WORD LOOP M MOD MAX A 28 STACK NOTATION DEF INITION addr n compiling loop Occurs in a colon definition in form DO LOOP At run time LOOP selectively controls branching back to the corresponding DO based on the loop index and limit The loop index is incremented by one and compared to the limit The branch back to DO occurs until the index equals or exceeds the limit at that time the parameters are discarded and execution continues ahead At compile time compiles LOOP and uses ad
17. 19 To USART From Driver To Driver From USART To Driver From USART To Driver TELECOMMUNICATION PAD ASSIGNMENTS Cont TABLE 2 1 PAD SIGNAL NAME SOURCE DESTINATION 44 RTSA Request to Send Channel A From USART 45 DTRA Data Terminal Ready Channel A To Driver 46 DTRA Data Terminal Ready Channel A From USART 47 TXDA Transmit Data Channel A To Driver 48 TXDA Transmit Data Channel A From USART 49 TXDB Transmit Data Channel B From USART 50 TXDB Transmit Data Channel B To Driver 187 DCDA Data Carrier Detect Channel A From Driver 188 DCDA Data Carrier Detect Channel A To USART 2 5 EPROM When ordered with firmware chip locations 3A 7A will be strapped for the appropriate EPROM type Locations 4A and 9A are capable of being user optioned for 2532 2732 or 2764 parts A gate must be added to use 2764 parts in locations 4A and 9A If 2732 or 2532 parts are used they should be left justified in the EPROM pads i e pin 1 of the 2732 or 2532 should be put in pin 3 of the EPROM pad and pin 24 into pin 26 of the pad PCB COORDINATE 1A PROM n ELE To strap sockets 5A and 7A for the following devices strap indi cated 2532 2764 PAD PAD PAD TO PAD PCB COORDINATE 1215192 120 121 135 136 122 125 147 149 143 146 160 368 Y 150 153 139 138 mena mm x NS ENG j RGN A 168 1
18. 300 101 3D2 on schematic 150 100 7D on board 14 Figure 2 3 CLOCK GENERATOR STRAPPING NOTE Labeled baud are for 64 USART clock mode The FT 86C can also be strapped to operate from external clock source Figure 2 4 is a schematic representation of the telecommunications circuitry EXAMPLE 2 OPERATE CHANNEL B FROM MODEM CLOCK 1 Remove jumpers between pads 13 15 17 removing the internal clock from Channel B 2 Jumper pad 27 to 28 25 Jumper pad 29 to 30 Clock now comes from Jl pins 44 for TXCB and 46 for RXCB EXAMPLE 2 75189 10 8 x 75189 13 1 33 8 7 4 E 75189 P 5 75188 35 2H de d EE 75189 38 1 3 pum Do E 13 oU omen 89 i FROM J1 46 45 2 75188 751 us 4 2 3H 75189 2 TO Ji EPA 4G 43 20 2 75188 3 75189 USART 4 44 43 gt O 25 75188 p 3H 4 10 8 2 40 39 75188 12 42 41 75188 3H Figure 2 4 MODEM CONTROL AND COMMUNICATIONS STRAPPING Additional straps may be needed if modem control signals are to be used The complete list of the telecommunications option pads be found in Table 2 1 By refering to this list the user should have no difficulty in strapping the telecommunications interface for his application PAD 15 14 15 16 17 18 19 20 21 22 25 24 25 26 27 28 29 50 51 52 55 54 35 36 57 38 39 40 41 42 43
19. COMMUNICATIONS Two independent communications ports are provided via a Zilog ZSIO USART Each port can be configured via software to operate in several different modes Two full sets of RS 232C modem control signal drivers are provided allowing modems to be attached to these ports Access to these I O ports is achieved through the FORTH words and P These words are described in Section 5 0 All port programming and I O is accomplished using these two words BASE ADDRESS Hex ZSIO PORT 0000 Channel A Data 0002 Channel A Control Registers 0004 Channel B Data 0006 Channel B Control Registers 5 7 SERIAL DATA CHANNEL CLOCKS SYNC WAITIREADY INTERNAL CHANNEL A CONTROL READ WRITE LOGIC REGISTERS dd i DISCRETE erem CONTROL amp MODEM OR STATUS OTHER CONTROLS CH A DATA BUS 1 0 CONTROL CONTROL amp STATUS MODEM OR DISCRETE OTHER CONTROLS CH B INTERRUPT CHANNEL B CONTROL READ WRITE LOGIC REGISTERS SERIAL DATA CHANNEL CLOCKS CHANNEL B lt gt SYNC INTERRUPT WAIT READY CONTROL i LINES Figure 3 3 USART INTERNAL STRUCTURE The USART s internal structure includes a CPU interface internal control and interrupt logic and two full duplex channels Each channel contains read and write registers and discrete control and status logic that provides the interface to modems or other external devices see Figure 3 3 The
20. address CECE Count of bytes to be moved The command SMOVE functions in the same way as MOVE except that the segment values must be explicitly specified 2 5 2 SMATCH FORMAT AAAA 5555 CCCC SMATCH AAAA First source address within source segment 5555 First source segment register address BBBB Second source address within segment DDDD Second source segment register address Count of bytes to be compared DISPLAY FORMAT 5555 7 BBBB VV Command terminates either completion of count or upon given number of mismatches see Section 5 4 5 5 4 MONITOR CONTROL COMMANDS 5 4 1 SEGMENT FORMAT 5555 SEGMENT 5555 Value to be loaded into the implied segment register The contents of the implied segment may be views by typing IMPLIED Note If the number appears negative type IMPLIED U 2 5 9 4 2 TIMES RUN FORMAT ININNN TIMES COMMAND NINININ Loop counter value COMMAND One or more of the monitor commands using either implied or explicit segment register The TIMES RUN command pair must be used as a pair and in the order given above The commands that go between TIMES and RUN will be executed at least once even if a zero is given for the count The maximum count is 32 767 number of commands that go in between has no practical limit and may extend over several lines Each command must be able to be found in controlF ORTH s dictionary or an error
21. commands P and WP write data to output ports P works with 8 bit ports and WP is for 16 bit output ports If the destination port address is within the local on board I O address space these commands will terminate normally even if there is no port at that address If the destination port is in the off board I O address space i e via the Multibus two conditions can occur If the destination port responds the commands will terminate normally If the destination port doesn t respond the deadman timer will expire and terminate the command the second case there will be a delay of at least 1 10th of a second Using a TIMES RUN command it is simple to detect a non responsive port 5 2 6 P and WP FORMAT DD and DD WP 3 DD Input port address The commands and WP read data from a given input port Again is for 8 bit ports and WP is for 16 bit ports These commands will exhibit exactly the same symptoms as the OUT command if the addressed port does not respond he data value displayed will be indeterminate if the port does not respond To see the value read from the port type the FORTH print command dot or U See glossary for more information about dot EXAMPLE to view the value from an I O device at Hex port 2E type 2E 5 2 7 GO FORMAT AAAA GO AAAA Address of first instruction to execute This command transfers control to the program whose first instruction is located at address AAAA and w
22. condition exists WORD CODE lt STACK NOTATION DEF INITION semi colon code Used in the form lt name gt CODE assembly code gt END CODE Stops compilation and terminates a new defining word name by compiling CODE The assembly code is put into place by putting bytes on the stack and using C and to emplace the opcodes in line Example 0 C 0 When lt name gt is later executed in the form lt name gt lt gt define the new lt namex gt the code field address of lt namex gt will contain the address of the code sequence following the CODE in lt name gt Exe cution of any lt namex gt will cause this machine code sequence to be executed semi colon S Stops interpretation of an input stream 5 is also the run time word compiled at the end of a colon definition which returns execution to the calling procedure nl n2 flag less than Leaves a true flag 1 if nl is less than n2 otherwise leaves a false flag f d d Jess than sharp Initializes the pictured numeric output format using the words lt 5 HOLD SIGN gt specifies the conversion of a double precision number into an ASCII character string stored in right to left order producing text at PAD GROUP ATTR DEFINING I COMPILER COMPARISON FORMAT 11 WORD STACK NOTATION DEF INITION lt BUILDS Used within a colon definition name
23. met PtP RO a 2 P 4 2 qu m 4 s d w 0 RES D LOPLI o B esspeppppponop as so 4 oo poo oso oo EL ELLE gt ELE o IIT POTUIT Iu Wn ED EE SEAR LEA I ard p d Mo p pP PP D PT o0 ame cm copes por RPM PPM MIS ate ae VU e ph PPAR S PICS We S E 3 9 P i SILL Te do 9 oO v do o Lo Peep PPP PRI Ia Ia n a PPS PEOPLE AIL le PAPAL w MERERI NINOS do ge i EE f Oe D 21327 44 4 aoe x LLL a7 alu o Cie 0 00 DODONAEA EM HK LPL PILL ta Ian We 5 z S Mm APIS ne PI EUR PPP IIIS EP ig A eerta da uu roooono sos 4 A Vei PP o da 2 p mee us AN 47
24. nl non zero question dup Reproduces nl only if it is non zero his is usually used to copy a value just before IF to eliminate the need for an ELSE clause to drop it f n question error Issues error message n if the Boolean flag is true question exec Issues an error message if not executing nl n2 question pairs Issues error message 19 CONDITIONALS PAIRED if nl does not equal n2 The message indicates that compiled conditionals do not match question stack Issues error message 7 FULL STACK if the stack is out of bounds flag question terminal Tests the terminal keyboard for actuation of any key Generates a Boolean value true flag 1 indicates actuation whereas a false flag f indi cates non actuation GROUP ATTR SECURITY STACK SECURITY SECURITY SECURITY SECURITY INPUT OUTPUT A 15 WORD ABORT ABS AGAIN ALLOT AND 14 STACK NOTATION DEF INITION addr n fetch Leaves the l6 bit contents of the address on top of the stack abort Clears the stacks and enters the execution state Returns control to the active I O port u absolute Leaves the absolute value of n u addr n compile time again Used in a colon definition in the form BEGIN AGAIN At run time AGAIN forces execution to return to the corresponding BEGIN There is no effect on the stack Execution cannot leav
25. plus minus Applies the sign of n2 to nl which is left as n5 nl run time addr n2 compile time plus loop Used in a colon definition in the form DO nl 4 OOP At run time LOOP selectively controls branching back to the corresponding DO based on nl the loop index and the loop limit The signed incre ment nl is added to the index and the total compared to the limit The branch back to DO occurs until the new index is equal to or greater than the limit nl gt 0 or until the new index is equal to or less than the limit nl lt Upon exiting the loop the parameters are discarded and execution continues Index and limit are signed integers in the range 32 68 to 22 767 At compile time LOOP compiles the run time word LOOP and computes the branch offset from HERE to the address left on the stack by n2 is used for compile time error checking n stores into the next available dictionary memory cell advancing the dictionary pointer GROUP ATTR ARITHMETIC MEMORY ARITHMETIC CONTROL IC DICTIONARY WORD FIND TRAILING STACK NOTATION DEFINITION nl n2 nj minus Substracts n2 from nl and leaves the difference n3 pfa byte tf found ff not found dash find Accepts the next text word delimited by blanks in the input stream to HERE and searches the CONTEXT and then CURRENT vocabularies for a matching entry If found t
26. read and write register group includes five 8 bit control registers two sync character registers and two status registers The ZSIO interrupt vector capability is not used All interrupt vectors are provided by the 8259A PIC The registers for both channels are designated in the text as follows WRO WR7 write registers 0 through 7 RRO RR2 read registers O through 2 The bit assignment and functional grouping of each register is configured to simplify and organize the programming process Paragraps 3 4 1 and 3 4 2 on the following page list the functions assigned to each read or write register 5 5 1 READ REGISTER FUNCTIONS RRO Transmit receive buffer status interrupt status and external status RRI Special receive condition status RR2 Modified interrupt vector Channel B only 5 4 2 WRITE REGISTER FUNCTIONS Register pointers CRC initialize initialization commands for the various modes etc WRI Transmit receive interrupt and data transfer mode definition WR2 Interrupt vector Channel B only WR3 Receive parameters and control WR4 Transmit receive miscellaneous parameters and modes Transmit parameters and controls WR6 Syne character or SDLC address field Sync character or SDLC flag The logic for both channels provides formats synchronization and validation for data transferred to and from the channel interface The modem control inputs Clear to Send CTS and Data Carrier Detect DCD are
27. stack task A no operation word which can mark the boundary between applications By forgetting TASK and re compiling an application can be discarded in its entirety Its definition is TASK then Used within a colon definition in the form IF ELSE THEN or IF THEN is the point where execution resumes after ELSE or IF when no ELSE is present GROUP ATTR STACK INPUT OUTPUT INPUT OUTPUT COMPILER U STACK DIC TIONARY CONTROL A 33 WORD TIB TOGGLE TYPE Un U U lt UABORT STACK NOTATION DEFINITION addr r D Leaves the address of user variable containing the starting address of the terminal input buffer addr b t oggle Complements the contents of addr by the 8 bit pattern byte addr n type Transmits n characters beginning at addr to the active output device action takes place for n less than one unl un2 ud t times Performs and unsigned multiplication of unl by un2 leaving the unsigned double number product of two unsigned numbers ud ul u ud u divide Performs the unsigned division of double number ud by ul leaving the unsigned remainder u2 and unsigned quotient n5 from the unsigned double dividend ud and unsigned divisor ul unl un2 flag u less than Leaves the flag representing the magnitude com parison of unl lt un2 where unl and un2 treated as 16 bit unsigned in
28. two according to or nl n2 two drop of the stack the operation the operation of the stack the operation the operation Drops the top double number on the stack GROUP ATTR PRIMITIVE C NUMERIC ARITHMETIC ARITHMETIC NUMERIC ARITHMETIC ARITHME STACK WORD 2DUP 36 A 10 STACK NOTATION DEF INITION GROUP ATTR d dd STACK or nl n2 n2 n2 two dup Duplicates the top double number on the stack NUMERIC three The number three is placed on top of the stack DEFINING eolon A defining word used in the form lt gt selects the CONTEXT vocabulary to be identical to CURRENT Creates a dictionary entry for name in CURRENT and sets the compile mode Words thus defined are called colon definitions The compilation addresses of subsequent words from the input stream which are not immediate words are stored into the dictionary to be exe cuted when name is later executed IMMEDIATE words are executed as encountered If a word is not found after a search of the CONTEXT and FORTH vocabularies conversion and compilation of a literal number is attempted with regard to the current BASE that failing an error condition exists DEFINING I semi colon Terminates a colon definition and stops further compilation If compiling from an external source and the input stream is exhausted before encoun tering an error
29. will result 5 4 3 TOLERATED To set the number of mismatches tolerated before termination of MATCH or SMATCH type n TOLERATED lt To view the number tolerated type TOLERATED lt APPENDIX CONTROLFORTH GLOSSARY This glossary contains the definition of all words in the controlFORTH vocabulary The definitions are presented ASCII sort order Stack Notation The first line of each entry shows a symbolic description of the action of the procedure on the parameter stack The symbols on the left indicate the order in which input parameters have been placed on the stack Three dashes indicate the execution point any parameters left on the stack after execution are listed on the right In this notation the top of the stack is to the right symbol Definition addr adrl Memory address b 8 bit with high eiaht bits zero C 7 bit ASCII character with high nine bits zero didi vos 32 bit signed double integer most significant portion with sign on top of stack flag Boolean flag false non zero true ff Boolean false flag value 9 OS Dos 16 bit signed integer number usos 16 bit unsigned integer number 32 bit unsigned number tf Boolean true flag value non zero Pronunciation The natural language pronunciation of control OR TH names is given in double quotes fb Integer F ormat Unless otherwise noted all references to numbers are for 16 bit si
30. 0 mA 35 mA 9 0 MHz 0 1 BUS 86 pin 0 156 center 0 4 Viking 3KH43 9AMK12 SERIAL I O 50 pin header type AUGAT 110 50001 102 P 796 Bus TTL compatible Interrupt request TTL compatible Serial I O RS 232C compatible 86 Intel 8086 equivalent Space for 8087 co processor provided Direct addressing to 1 Mbyte of memory Bit byte word and block operation PROCESSORS Cont PROCESSOR WORD SIZE INSTRUCTION CYCLE TIME SPECIFICATIONS Cont 24 operand addressing modes Fourteen 14 registers 8 and l6 bit signed and unsigned arithmetic FT 86C FP Intel IAPX 86 20 consisting of an Intel 8086 and an Intel 8087 co processing configuration Direct addressing of up to 1 Mbyte of memory Bit byte word and block operations 24 operand addressing modes Fourteen registers in the 8086 Eight 80 bit numeric data registers and six 16 bit registers in 8087 Single and double precision floating point arithmetic BCD arithmetic and transcendental functions FT 86C Instruction 8 16 24 52 40 or 48 bits Data 8 and 16 bits FT 86C FP Instruction 8 16 24 or 32 bits Data Internal up to 80 bits FT 86C Typical instruction cycle 1 0 microsecond FT 86C FP Typical instruction cycles Multiply double precision 27 microseconds Square root 56 microseconds Divide single precision 59 microseconds Tangent 90 microseconds SECTION 1 0 INTRODUCTION The 86 is a Mu
31. 117 118 01000 1000 115 116 02000 2000 115 114 03000 F 3000 111 112 04000 4000 109 110 05000 5000 107 108 06000 6000 103 104 07000 7000 105 106 98 8 sG 89 2 DAT WS 000005 000 lt Z 5 3 e 3 3 J TEN P SELECT iine 1 3 3 29131 udi Man Figure 4 4 EPRO AND CHIP SELECT LIMES 4 5 4 6 SECTION 5 0 FIRMWARE 9 1 CONTROLF ORTH ControlF ORTH is supplied in EPROM and is an implementation of FORTH derived from fig F ORTH and with certain extensions The extensions a general set of monitor commands to assist the user in adding debugging and testing LSI devices This Section explains the monitor enhancements of control ORTH in detail The glossary in Appendix A contains descriptions of the other FORTH words controlFORTH For further information on FORTH Appendix B is a bibliography of FORTH works In the following text underlines indicate or more spaces lt means the RETURN key With the exception of the substitute command all addresses counts and value fields may be entered in decimal octal or hexadecimal depending on the base selected prior to entering the command Commands may be strung togethe
32. 2 2 1 1 MULTIBUS OPTIONS Figure 2 2 The F T 86C is factory optioned to provide bus clock and common clock to the Multibus The clocks can be disabled by cutting the straps between pads 6 and 7 and 11 and 12 Refer to Figure 2 2 for pad locations The FT 86C will now draw its bus clock from the Multibus COMMUNICATIONS OPTIONS Most of the communications options for the FT 86C are software controlled The strapping options for the communications channels allow the user to select the communications clock source and speed for each channel user can also select local mode direct connection to a terminal or select modem operation through a combination of software and hardware strapping options 2 2 1 COMMUNICATIONS STRAPPING communications clock for the USART can come from either of two sources the on board clock generator used for asynchronous protocols or from an external clock source such as a modem used for synchronous protocols The user may select the clock source and speed by removing or installing jumpers The F T 86C is strapped at the factory for 300 baud operation on both communications channels Figure 2 1 is a pictorial representation of the T 86C PCB showing the jumper pad locations and numbers for option strapping Figure 2 3 shows the telecommunications clock generator and the associated pads for each clock frequency An example of how to strap Channel B for 9600 baud is given on page 2 6 Al
33. 70 147 149 M 55 171 174 148 150 18 Ds 168 170 13 169 171 Figure 2 5 EPROM STRAPPING 2 9 2 4 WAIT STATE TIMING Wait state timing is selected by straps at board location 10 Either one or two wait states may be inserted for RAM EPROM or I O The selection of the number of wait states is dependent on the speed of the slowest device in each category Refer to Figure 2 6 for strap locations To calculate the number of wait states required for a chip take the response time of the chip and subtract 400 ns Divide the result by 200 ns the period of each wait state and use the next highest multiple The factory settings are RAM 1 wait state Pad 185 to 185 l wait state Pad 182 to 185 I O 1 wait state Pad 184 to 185 o 00757 090000900000 WAIT STATE STRAPS PCB COORDINATE 1 C 1D 102 1615 O6 103 e D4 105 7 D6 1 WAIT STATE D7 2 WAIT STATES Figure 2 6 WAIT STATE STRAPPING 2 5 INTERRUPT STRAPPING Interrupts from the Multibus are available on the following pads INTERRUPT PAD ASSIGNMENTS PAD SIGNAL NAME SOURCE DESTINATION 67 IRA To PIC 68 IRA From Multibus Driver 69 70 IR7 From Multibus Driver 71 6 72 From Multibus Driver 73 IR5 To PIC 74 IR5 From Multibus Driver 75 IR3 To PIC 76 IR3 From Multibus Driver 77 78 IR2 Fro
34. BUILDS DOES 3 Each time lt name gt is executed BUILDS defines a new word with a high level execution procedure Executing lt name gt in the form lt name gt lt gt Uses lt BUILDS to create dictionary entry for lt namex gt with a call to the DOES gt part for lt namex gt When nnnn is later executed it has the address of its parameter area on the stack and executes the words after DOES gt in lt name gt lt BUILDS and DOES gt allows run time procedures to be written in high level rather than assembler code as required by CODE gt nl n2 flag greater than Leaves a true flag 1 if nl is greater than n2 otherwise a false flag ff gt R pr Removes number from the computation stack and places it as the most accessible number on the return stack Use should be balanced with R gt in the same definition addr question mark Displays the value contained at the address on the top of the stack in free format according to the current BASE Uses the format of question comp Issues error message if not compiling 12 GROUP ATTR DEF INING COMPARISON STACK STACK SECURITY WORD CSP PAIRS STACK TERMINAL STACK NOTATION DEF INITION question s Issues error message if stack position differs from value saved CSP nl nl if zero nl
35. ISTER 5 Tx CRC ENABLE RTS SDLCICRC 16 Tx ENABLE SEND BREAK 0 Tx 5 BITS OR LESS CHARACTER 1 Tx 7 BITS CHARACTER 0 Tx 6 BITS CHARACTER 1 Tx 8 BITS CHARACTER DTR WRITE REGISTER 6 or fos os oa oa oo SYNC BIT 0 SYNC BIT 1 SYNC BIT 2 SYNC BIT 3 SYNC BIT 4 SYNC BIT 5 SYNC BIT 6 SYNC BIT 7 eALSG SDLC ADDRESS FIELD WRITE REGISTER 7 oos va oz pr oo SYNC BIT 8 SYNC BIT 9 SYNC BIT 10 SYNC BIT 11 SYNC 12 SYNC BIT 13 SYNC BIT 14 SYNC BIT 15 FOR SDLC IT MUST BE PROGRAMMED TO 01111110 FOR FLAG RECOGNITION BIT FUNCTIONS 5 11 5 5 INTERRUPT CONTROL The 8259A programmable interrupt controller is in local I O space at Hex address 0008 It can be programmed using the P and P commands in the same manner as the serial communications ports When an interrupt request is generated and presented to one of the 8259A interrupt request lines the interrupt controller will evaluate the interrupt request and if appropriate generate an interrupt request to the 8086 If interrupts are enabled the processor will complete execution of the current instruction and enter the interrupt acknowledge machine cycle The processor status line 52 being low indicates either an I O operation or an interrupt machine cycle The I O bus will be enabled local 8288 bus controller generates an interrupt acknowledge signal INTA which is used to precondition the 8259A inter
36. LIO nom 44 LI LI J FERES RS as 00000 27 d 1510 RAM ADDRESS SELECT ze III 00000000 RoR RR Re 930 094 z 2 PROM TYPE wane dbi 0 0 00 06 6 A sd 15905 on 2 6 SR 1 30 i a UP UE lt 0 TIC P TIE o o o COEN 2 32 ee Figure 2 1 5 2 PPP A j MEMORY ie ADDRESS PADS v oG o BA o 9050 o o6 o B o d o L B 0 o E o o o RN o o B o o E o o p PADS o v 9 9 o 0 oo o o B o B o o p oG o o o
37. LOCATIONS MULTIBUS CONTROL STRAPPING CLOCK GENERATOR STRAPPING MODEM CONTROL AND COMMUNICATIONS STRAPPING EPROM STRAPPING WAIT STATE STRAPPING INTERRUPT STRAPPING BLOCK DIAGRAM FT 86C FP ADDRESS TIMING CONSTRAINTS USART INTERNAL STRUCTURE READ REGISTER BIT FUNCTIONS WRITE REGISTER BIT FUNCTIONS MEMORY ADDRESS AND DATA BUS S I O ADDRESS PADS SELECT PADS EPROM AND RAM CHIP SELECT LINES PAGE 2 3 2 5 2 6 2 7 2 9 2 10 2 12 5 3 5 7 5 8 5 10 5 11 4 2 4 3 4 4 4 5 111 5 TABLE NUMBER TITLE PAGE 2 1 TELECOMMUNICATION PAD ASSIGNMENTS 2 8 APPENDICES APPENDIX NUMBER TITLE PAGE A CONTROLFORTH GLOSSARY 1 RECOMMENDED READING B 1 FT 86C ASSIGNMENTS 1 Multibus is a registered trademark of Intel Corporation Portions of the copyrighted Zilog Microcomputer Components Data Book are reproduced within this manual with the written consent of Zilog Corporation PHYSICAL ENVIRONMENTAL FLECTRICAL CHARACTERISTICS FT 86C FT 86C FP SYSTEM CLOCK CONNECTORS ELECTRICAL INTERFACE PROCESSORS SPECIFICATIONS Width 12 0 30 48cm Height 6 75 17 15 Depth 2M 83cm Weight 15 0 oz approx 370 gm Shipping Weight 20 0 oz approx 570 gm Form Factor IEEE P 796 Operating Temperature 0 to 55 C Storage Temperature 10 70 Relative Humidity 90 non condensing 5V 4596 12V 10 12V 10 2 75 A 40 mA 35 mA 3 25 A 4
38. ON addr hold Leaves the address of user variable which holds the address of the latest character of text during numeric output conversion char hold Used between lt and gt to insert an ASCII character into a pictured numeric output string Used within a DO LOOP to copy the loop index from the return stack to the stack nfa i d dot Print a definition s name from its name field address See NFA flag run time addr n compile mf Used in a colon definition in form IF THEN IF ELSE THEN At run time IF selects execution based on a Boolean flag If flag is true the words following IF are executed and the words following ELSE are skipped The ELSE part is optional If flag is false the words between IF and ELSE or between IF and THEN when no ELSE is used are skipped IF ELSE THEN conditionals may nested At compile time IF compiles BRANCH reserves space for an offset at addr addr and n are used later for resolution of the offset and error testing GROUP ATTR FORMAT FORMAT CONTROL INPUT OUTPUT CONTROL A 25 WORD IMMEDIATE INTERPRET KEY LATEST A 26 STACK NOTATION DEFINITION immediate Marks the most recently made dictionary entry as a word which will be executed when encoun tered rather than being compiled addr Win leaves the address of user variable containing the byte offset within the cu
39. ORT SDLC RESET EXT STATUS INTERRUPTS CHARNEL RESET ENABLE INT ON NEXT Rx CHARACTER RESET TxINT PENDING ERROR RESET RETURN FROM INT ONLY gt OO gt O gt gt amp NULL CODE RESET Rx CRC CHECKER RESET Tx CRC GENERATOR RESET Tx UNDERRUN EOM LATCH coc gt gt WRITE REGISTER 1 EXT INT ENABLE Tx INT ENABLE STATUS AFFECTS VECTOR CH B ONLY O Rx INT DISABLE 1 Rx INT ON FIRST CHARACTER O INT ON ALL Rx CHARACTERS PARITY AFFECTS VECTOR 1 INT ON ALL Rx CHARACTERS PARITY DOES NOT AFFECT VECTOR WAITIREADY ON RIT gem WAITIREADY FUNCTION SONS EIN WAITIREADY ENABLE WRITE REGISTER 2 CHANNEL B ONLY o7 pa v3 02 on on vo vi v2 V INTERRUPT f VECTOR v5 V6 v7 WRITE REGISTER 3 ENABLE SYNC CHARACTER LOAD INHIBIT ADDRESS SEARCH MODE SDLC Rx CRC ENABLE ENTER HUNT PHASE AUTO ENABLES Rx 5 BITS CHARACTER Rx 7 BITS CHARACTER Rx 6 BITS CHARACTER Rx 8 BITS CHARACTER 0 0 0 1 8 1 1 Figure 3 5 WRITE REGISTER WRITE REGISTER 4 PARITY ENABLE PARITY EVEN ODD SYNC MODES ENABLE 1 STOP BIT CHARACTER 1 STOP BITS CHARACTER 2 STOP BITS CHARACTER gt gt gt gt gt 8 CHARACTER 16 SYNC CHARACTER SDLC MODE 01111110 FLAG EXTERNAL SYNC MODE O amp X1 CLOCK FAODE X16 CLOCK MODE X32 CLOCK MODE X64 CLOCK MODE 0 0 0 1 0 1 1 WRITE REG
40. TATION DEF INITION addr char addr n2 enclose The text scanning primitive used by WORD From the text address addr and an ASCII delimiting character is determined the byte offset to the first non delimiter character nl the offset to the first delimiter after the text n2 and the offset to the first character not included n5 This procedure will not process past an ASCII null treating it as an unconditional delimiter addr erase Clears a region of memory to zero from addr Over n addresses line in blk error Executes error notification and restart of system WARNING is first examined If WARNING 1 the text of line n relative to screen 4 of drive is printed This line number may be positive or negative and beyond just screen 4 If WARN ING f n is just printed as a message number non disk installation If WARNING 1 the definition ABORT is executed which executes the system ABORT The user may cautiously modify this execution by altering ABORT ControlF OR TH saves the contents of IN and to assist in determining the location of the error Final action is execution of QUIT addr execute Executes the definition whose code field address is on the stack The code field address is also called the compilation address addr count expect Transfers characters from the terminal beginning at addr upwards until a return or the count of n characters has
41. all go inactive 5 5 4 BUS TIMING Although the Multibus is an asynchronous bus two clock lines are present on the bus bus clock and constant clock The Multibus also has certain timing constraints regarding the relationship of the address data and command presentation Bus clock is used to synchronize bus arbitration Enabling of the Multibus address drivers AEN is synchronized with bus clock however the disabling of the Multibus address drivers is synchronized with T4 of the processor clock Bus clock can in theory be any frequency however the lower the frequency the longer the Multibus access arbitration time The F T 86C generates bus clock frequency of 9 85 MHz Constant clock is provided to the Multibus for general use It is not specifically related to the timing of bus clock or to the timing of other bus signals The FT 86C can provide 9 85 MHz constant clock ADRIn lt STABLE ADDRESS MRDC OR IORC ANE STABLE DATA 9 XACK D ADDRESS SETUP TIME 50 NANOSECONDS MINIMUM 2 TIME REQUIRED FOR SLAVE TO GET DATA ONTO BUS IN ACCORDANCE WITH SETUP TIME REQUIREMENT XACK CAN BE ASSERTED AS SOON AS DATA IS ON BUS 3 TIME REQUIRED FOR MASTER TO REMOVE COMMAND 4 ADDRESS AND DATA HOLD TIME 50 NANOSECONDS MINIMUM 5 XACK AND DATA MUST BE REMOVED FROM THE BUS A MAXIMUM OF 65 NANOSECONDS AFTER THE COMMAND IS REMOVED Figure 3 2 ADDRESS TIMING CONSTRAINTS 3 4
42. alter the current value HH and fetch the next byte location To change a value enter the required value VV and press carriage return The entered value VV will replace the original value HH To terminate the SUBSTITUTE command press the Q key and carriage return SUBSTITUTE operates in hexadecimal but it preserves and restores the base in use prior to using SUBSTITUTE 2 2 5 MOVE FORMAT AAAA BBBB CCCC MOVE AAAA Source address BBBB Destination address CECE Number of bytes to moved This command moves the specified number of bytes from locations starting at AAAA to locations starting at BBBB within the implied segment The move is always to higher memory locations 5 2 4 MATCH FORMAT AAAA BBBB CCCC MATCH AAAA Source address 1 BBBB Source address 2 ECC Byte count to compare DISPLAY FORMAT FOR MISMATCH AAAA HH BBBB VV Where is the implied segment value AAAA and are the addresses within the segment and HH and VV are the unequal values at those locations MATCH compares two given strings of bytes start addresses AAAA and BBBB This command will terminate either on completion of the count CCCC or after a given number of mismatches have been displayed The number of errors tolerated before termination can be altered see Section 5 4 3 This default is set to 10 mismatches 5 2 5 P and WP FORMAT VV DD P and VV DD WP VV Value to be output to the port DD Destination port address The
43. atting Compiler Text Interpreter Dictionary Control Defining Words Vocabularies Mass Storage Miscellaneous Security Error Detection Primitives Assembler Dictionary Parameter Used in ControlF ORTH WORD 5 ff gt 5 STACK NOTATION DEF INITION GROUP ATIR n addr MEMORY store Stores 16 bit number n into addr SECURITY store CSP Stores the stack position in CSP Used as part of the compiler security See CSP ud2 FORMAT sharp Generates the next ASCII character placed in an output string from udl Result ud2 is the quotient after division by BASE and is maintained for further processing Use between lt and gt See 5 d addr n FORMAT sharp greater Terminates numeric output conversion by dropping d leaving the text address and character count n suitable for TYPE ud FORMAT sharp s Converts all digits of a ud adding each to the pictured numeric output text until the remainder is zero single zero is added to the output string if the number was initially zero Use only between lt and gt addr DICTIONARY 1 tick Use in the form lt gt If executing leaves the parameter field address of the next word accepted from the input stream If compiling compiles this address as a literal later execution will place this value on the stack If the word is not found after a search of CONTEXT and FORTH vocabularies an error mes sage is d
44. been received Takes no action for n zero or less One or more nulls are added at the end of the text GROUP ATTR PRIMITIVE MEMORY SECURITY COMPILER INPUT OUTPUT A 25 WORD FENCE FORGET FORTH HERE HEX A 24 STACK NOTATION DEF INITION addr fence Leaves the address of a user variable containing an address below which FORGETting is trapped To forget below this point the user must alter the contents of FENCE forget Executes in the form FORGET lt name gt Delete from the dictionary lt name gt which is in the CURRENT vocabulary and all words added to the dictionary after lt name gt regardless of their vocabulary An error message will occur if the CURRENT and CONTEXT vocabularies are not currently the same Failure to fine lt name gt in CURRENT or FORTH is an error condition forth The name of the primary vocabulary Execution makes FORTH the CONTEXT vocabulary New definitions become a part of FORTH until a differing CURRENT vocabulary is established User vocabularies conclude by chaining to FORTH so it should be considered that FORTH is contained within each user s vocabulary addr here leaves the address of the next available dictionary location hex Sets the numeric conversion BASE to sixteen hex adecimal GROUP ATTR SECURITY U DICTIONARY VOCABULARY DICTIONARY NUMERIC WORD D HOLD STACK NOTATION DEF INITI
45. ce unit operates asynchronously to the execution unit The BIU controls an internal 6 byte long instruction queue The BIU will prefetch instructions from memory whenever there are 4 bytes or less in its internal queue and the executive unit doesn t require use of the bus The BIU has access to 5 of the 8086 s 16 bit registers The execution unit is not directly involved with bus management The execution unit executes instructions taken off the internal 6 byte instruction queue that were prefetched by the BIU When the EU requires immediate access to the bus it does so via the BIU The control and timing unit provides status information to external devices in addition to the EU and the BIU processor status lines 50 51 and 52 together with the processor clock are provided to the external bus control elements to enable demultiplexing of the address and data lines from the 8086 The bus control elements also decode the status lines into the appropriate operational commands The 8087 numerical data processor operates in a close coupled configuration with the 8086 The 8087 can execute instructions in parallel with the 8086 The 8087 provides trigonometric logarithmic and exponential functions in addition to its arithmetic processing capabilities 8087 conforms to the proposed IEEE Floating Point Standard Internally the 8087 consists of two units a control unit and a numeric execution unit The 8087 control unit maintains sync
46. dr to calculate an offset to DO is used for error testing nl n2 d m times A mixed magnitude math operation which leaves the double number signed product of two signed number d nl n2 n5 m divide A mixed magnitude math operator which leaves the signed remainder n2 and signed quotient n5 from a double number dividend d and divisor nl The remainder takes its sign from the dividend u2 u3 m divide mod An unsigned mixed magnitude math operation which leaves a double quotient ud4 and remainder 5 from a double dividend udl and single divisor u2 nl n2 max max Leaves the greater of two numbers GROUP ATTR CONTROL 1 ARITHME TIC ARITHMETIC ARITHMETIC ARITHME TIC WORD MESSAGE MIN MOD NEGATE NFA NOT NUMBER STACK NOTATION DEFINITION n lt a message If WARNING is positive executes the word whose CFA is in UWARN n may be positive or negative If WARNING is zero the message will simply be displayed as a number no mass storage nl n2 n5 min Leaves the smaller number n3 of two numbers nl and n2 nl n7 nj mod Leaves the remainder n5 of nl divided by n2 with the same sign as nl n n negate Leaves the two s complement of a number i e the difference of f less n pfa nfa Un f a3 Converts the parameter field address pfa of a definition to its name field address nfa flag
47. e number of wait states may be inserted between processor clock cycles T3 and T4 e g T2 3 Tw Tw 4 The FT 86C provides separately strappable wait states for on board I O RAM and EPROMs Multibus access being asynchronous will automatically result in 0 to wait states being inserted The number of wait states inserted depends on bus contention and arbitration and also on the access time of the specific device or memory type accessed 5 5 5 BUS CONTROL TIMING The three elements that make up the bus control section derive their timing from the processor clock and the processor status lines SQ Sl and S2 to 3 5 indicate what function is going to be performed during the current to T4 cycle This is done at T1 The 8086 also places the address on the multiplexed bus at this time Both bus controllers 8288s use the status lines and the processor clock to generate a pulse ALE to latch the address into both the local bus and the Multibus address drivers The Multibus address drivers do not at this stage have their outputs enabled The output of the local address drivers is decoded by the local PROM RAM and I O decoders to establish whether this address falls within the on board address range If it does a signal is generated and input to the bus arbiter to indicate a resident bus access only The Multibus address latches are not output enabled and the Multibus bus controller is held disabled If the address is
48. e this loop unless R gt DROP is executed one level below At compile time AGAIN compiles BRANCH with an offset from HERE to addr is used for compile time error checking n allot Adds the signed number to the dictionary pointer DP May be used to reserve dictionary space or re origin memory is the number of bytes nl n2 n5 Leaves the bitwise logical AND of nl and n2 as n5 GROUP ATTR MEMORY SECURITY ARITHMETIC CONTROL COMPILER ARITHMETIC WORD BASE BEGIN BL BLANKS BLK STACK NOTATION DEF INITION addr base Leaves the address of the variable containing the current number base used for input and output conversion The range of BASE is 2 through 70 addr n compile time begin Occurs in a colon definition in form BEGIN Flag UNTIL BEGIN AGAIN BEGIN flag WHILE REPEAT At run time BEGIN marks the start of a word sequence for repetitive execution A BEGIN UNTIL loop will be repeated until flag is true BEGIN WHILE REPEAT loop will be repeated until flag is false The words after UNTIL or REPEAT will be executed when either loope is finished flag is always dropped after being tested BEGIN AGAIN loop executes indefinitely At compile time BEGIN leaves its return address and n for compiler error checking char blank A constant that leaves the ASCII character value for blank i e Hex 20 addr n
49. gnal GND All reserved pins are reserved for future use and should not be used if upwards compatibility is desired 1 2 Pin Assignment of Bus Signals on 796 Bus Board Connector P1 GND 45V 45V 12V GND INIT BPRO BREQ MWIC IOWC INHI INH2 AD10 AD11 AD12 AD13 INT7 INT5 INT3 INT1 ADRF ADRD ADRB ADR9 ADR7 ADR5 ADR3 ADR1 DATF DATD DATB DAT9 DAT7 DAT5 DAT3 DAT1 GND 12V 45V 5V GND CIRCUIT SIDE MNEMONIC DESCRIPTION Signal GND 5 Vde 5 Vde 12 Vde Reserved Bussed Signal GND Initialize Bus Priority Out Bus Request Memory Write Command I O Write Command Inhibit 1 Disable RAM Inhibit 2 Disable PROM or ROM Address Bus Parallel Interrupt Request Address Bus Data Bus Signal GND Reserved Bussed 12 Vde 9 5 Signal GND PIN CO WN N NJ NM ND LE Fr L xL Ui amp Uu S SIGNAL Ground Ground Spare Fxternal Reset Spare Spare opare Spare Spare Spare Spare Spare Spare Spare Spare Spare Spare Spare Spare Spare Spare Spare Spare Spare Spare J1 CONNECTIONS PIN 26 21 28 29 50 21 32 52 54 56 21 58 29 40 4 42 45 44 45 46 47 48 49 20 SIGNAL Spare Spare Spare Spare Spare Spare Spare Transmit Data Channel B Spa
50. gned integers For 32 bit signed double numbers the most significant part with the sign is on top arithmetic is implicitly 16 bit signed integer math with error and underflow indication unspecified Capitalization Word names as used within the glossary are conventionally written in upper case characters Lower case is used when reference is made to the run time machine codes not directly accessible i e VARIABLE is the user word to create a varible Each use of that variable makes use of a code sequence variable which executes the function of the particular variable Attributes ATTR Capital letters show definition characteristics E I p U May only be used within a colon definition A digit indicates number of memory addresses used if other than one Intended for execution only Indicates that the word is IMMEDIATE and will execute during compilation unless special action is taken Has precedence bit set Will execute even when compiling A user variable Group Key Words GROUP The following key words identify the functional groups that each word is most related to STACK NUMERIC ARITHMETIC COMPARISON CONTROL MEMORY I O FORMAT COMPILER DICTIONARY DEF INING VOCABULARY MASS MISC SECURITY PRIMITIVE ASSEMBLER PARAMETER Stack Manipulation Numeric Representation Arithmetic and Logical Comparison Operators Control Structures Memory Input Output Output Form
51. he dictionary entry s parameter field address its length byte and a Boolean true is left Otherwise only a Boolean false is left addr nl addr n2 dash trailing Adjusts the character count nl of a text string beginning address to suppress the output of trailing blanks The characters at addr nl to addr n2 are blanks An error condition exists if nl is negative n Displays the number the top of stack number is converted from a signed 16 bit two s complement value according to the numberic BASE The sign is displayed only if the value is negative trailing blank is displayed after the number Also see dot quote Used in the form JU Accepts the following text from the input stream terminated by double quote If executing transmits this text to the selected output device If compiling compiles so that later execution will transmit the text to the selected output device At least 127 characters are allowed in the text If the input stream is exhausted before the termi nating double quote an error condition exists GROUP ATTR DICTIONARY FORMAT INPUT OUTPUT INPUT OUTPUT I WORD MOD lt A 8 STACK NOTATION DEF INITION nl n2 dot R Displays number nl right justified n2 places No trailing blank is printed dot S Displays the contents of the stack without altering the stack This word is very useful i
52. hich creates a user variable lt name gt The parameter field of lt name gt contains n as a fixed offset relative to the user pointer register UP for this user variable When lt name gt is later executed it places the sum of its offset and the user area base address on the stack as the storage address of that particular variable n lt name gt compute time lt name gt run time variable A defining word executed in the form n VARIABLE lt name gt to create a dictionary entry for lt name gt and allot two bytes for storage in the parameter field When lt name gt is later executed it will place the storage address on the stack addr voc link Leaves the address of user variable containing the address of a field in the definition of the most recently created vocabulary vocabulary names are linked by these fields to allow control for FORGETting through multiple vocabularies vocabulary A defining word used in the form VOCABULARY lt name gt to create in the CURRENT vocabulary a diction ary entry for lt name gt which specifies a new ordered list of word definitions Subsequent exe GROUP ATTR DEF INING DEF INING VOCABULARY U VOCABULARY WORD VOCABULARY Cont VLIST WARNING WHILE addrl nl addrl nl addr n2 compile time STACK NOTATION DEF INITION cution of name will make it the CONTEXT vocabulary When name becomes the CURRENT vocabulary
53. his buffer as the input stream by setting IN and BLK to zero quit Clears the return stack stops compilation and returns control to the entire input message is given GROUP ATTR ARITHMETIC STACK DICTIONARY DICTIONARY STACK INPUT OUTPUT MISC WORD R gt R REPEAT ROT RP STACK NOTATION DEFINITION n r fetch Copies the top of the return stack to the computa tion stack n r from Removes the top value from the return stack and leaves it on the computation stack See gt R and addr r zero leaves the address of user variable containing the initial value of the return stack pointer See RP addr n compiling repeat Used within a colon definition in the form BEGIN WHILE REPEAT At run time REPEAT forces an unconditional branch back to just after the corresponding BEGIN At compile time REPEAT compiles BRANCH and the offset from HERE to addr is used for error testing nl n2 n5 n2 nl rote Rotates the top three values on the stack bringing the third to the top r p store Initializes the return stack pointer from user variable Rf GROUP ATTR STACK STACK PRIMITIVE U CONTROL STACK PRIMITIVE 31 WORD RPG 5 gt 0 Sp SCR SIGN SMUDGE SP A 52 STACK NOTATION DEF INTION addr r p fetch Leaves the address of a variable containing the re
54. hronization with the 8086 by monitoring the 8086 status lines 50 51 52 and S6 8087 control unit moitors the data bus to obtain 8087 specific instructions The numeric execution unit has a register stack of 8 80 bit data registers which are used for computation Instructions can addres the data registers either implicitly or explicitly 5 1 BUS ELEMENTS There are four major elements within the FT 86C bus system bus control local bus I O bus and the Multibus Figure 3 1 is a block diagram of the 86 5 1 5 2 5 1 1 BUS CONTROL Bus control is implemented with three LSI chips The on board bus and the I O bus are controlled by an Intel 8288 bus controller The Multibus is controlled by a second 8288 Selection of which bus controller to use is made through an Intel 8289 bus arbiter The 8289 resolves access contention to the Multibus when operating in a multi master environment 5 1 2 LOCAL BUS The 20 bit memory addresses output by the 8086 8087 are always latched on board range test is then carried out by the memory decoding logic to determine if this is within the local on board address range the address is not within this range the bus arbiter contends for access to the Multibus The local bus controller is disabled and when access to the Multibus is granted the bus arbiter enables the Multibus bus controller If the address is a valid local address the local bus controller is enabled and issues the appro
55. ile time within the colon definition DO compiles DO and leaves the following addr and n for later error checking GROUP ATTR NUMERIC COMPILER ARITHMETIC CONTROL WORD DOES gt DP DPL STACK NOTATION DEF INITION does Defines the run time action within a high level defining word Used in the form lt name gt BUILDS DOES 3 and the lt name gt lt namex gt Marks the termination of the defining part of the defining word lt name gt and begins the definition of the run time action for words that will later be defined by lt name gt DOES alters the code field and first parameter of the new word to execute the sequence of compiled word addresses following DOES Used in combination with BUILDS The execution of the DOES gt part begins with the address of the first parameter of the new word lt namex gt on the stack Upon execution of lt name gt the sequence of words between DOES and will be executed with the address of lt namex gt s parameter field on the stack This allows interpretation using this area or its contents Typical uses include a FORTH assembler multi dimensional arrays and compiler generation addr 4 Leaves the address of user variable the dictionary pointer which points to address the next free memory address above the dictionary The value may be read by HERE and altered by ALLOT addr d p 1 Leaves the address of u
56. isplayed WORD CODE 1 ABORT DO A 4 STACK NOTATION DEF INITION paren Used in the form cccc Accepts and ignores comment characters from the input stream until the next right parenthesis As a word the left parenthesis must be followed by one blank It may be freely used while executing or compiling error condition exists if the input stream is exhausted before the right paren thesis The run time procedure compiled by which transmits the following in line text to the selected The run time procedure compiled by CODE that rewrites the code field of the most recently defined word to point to the following machine code sequence See CODE The run time procedure compiled by LOOP which increments the loop index by n and tests for loop completion See LOOP Executes after an error when WARNING is l This word normally executes ABORT but may be altered with care to a user s alternative procedure See ABORT limit l start The run time procedure compiled by DO which moves the loop control parameters to the return stack See DO GROUP ATTR MISC PRIMITIVE PRIMITIVE PRIMITIVE PRIMITIVE WORD FIND LOOP NUMBER MOD STACK NOTATION DEF INITION addrl addr2 pfa byte tf found addrl addr2 ff not found Searches the dictionary starting at the name field addres
57. ith the implied segment value 2 3 2 4 5 2 8 RECEIVE FORMAT AAAA DD RECEIVE AAAA Address where input data is to be loaded CCCC Count of bytes to be loaded DD Input port address 5 2 9 SEND FORMAT AAAA CCCC DD SEND AAAA Address where output data begins CCEC Number of memory bytes to be transferred DD Output port address TRANSMISSION FORMAT HHHHHHHH etc Where each H is an ASCI character containing 4 of the 8 bits in a byte To SEND n bytes requires transmission of 2 n characters The command pair RECEIVE and SEND receive and send binary data via a selected serial input output port The binary data is broken into 4 bit nibbles and converted to form the ASCI Hex characters 0 through 9F and 0 through F for transmission over a serial link The format for both commands is simply one of a long string of ASCII characters The command SEND assembles the ASCII from the data bytes and transmits it The RECEIVE command accepts an ASCII string strips the ASCII reassembles the original data bytes and places them in memory at the given address 5 2 10 DUMP FORMAT AAAA CCCC DUMP Starting address CCEC Byte count DISPLAY FORMAT AAAA nnnnnnnnnnnnnnnn 242 MONITOR COMMANDS WITH EXPLICIT SEGMENT ADDRESSES 5 5 1 SMOVE FORMAT AAAA 5555 BBBB DDDD CCCC SMOVE AAAA Source address within source segment 5555 Source segment address BBBB Destination address within destination segment DDDD Destination segment
58. l baud rates assume that the USART is initialized to 64 clock mode on the appropriate channel A 5 BETIS Im 3 a re a E J1 500000b6000000000000000000 4900000000000000000000000 o Ooo000000000000000000000090 00000000000000005900000000 0000000000000000000000000 0000000000000006000000000 00000000600000006000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 000000000000000000000000000000000000000000000000000 WAIT STATE STRAPPING 000000000000000000000000000000000000000000000000 0 000000 000000000000000000000000000000000000 MODEM CONTROL STRAPPING 000000 FE MA 009090005 gt f ADDRESS STRAPPING EDS ee LL ooo aT DIY eRe of D 9000 000000 56 600 661 620 430 2 OW oo 7 B o fo 25224 8288 CLOCK DISABLE PONES iC wwe A C R3 0200000 x So enm ae a E 1 7 0000000000000000 cor 69280 LE E gt Ta PT I
59. ltibus compatible single board 16 bit computer offering a customizing area processor is an Intel 8086 with the 8087 Numeric Data Processor available as an option The customizing area allows the user to add peripheral and memory chips to meet the user s specific needs The FT 86C and FT 86C FP provide ample drive current on local busses to support most types of peripheral or memory chips Spare select lines are provided for user added PROM RAM or I O devices All pads in the customizing area are drilled to take 0 025 square wire wrap pins The customizing area may be used for up to 27 16 chips and 5 40 pin chips or many combinations of 0 5 wide and 0 6 wide devices The optional controlF OR TH monitor is implementation of FORTH with monitor command extensions It provides the user with a real time programming language and also with a powerful testing and debugging tool The FORTH supplied with the 8087 numeric data processor option contains additional extensions to facilitate the use of the 8087 1 1 1 2 SECTION 2 0 INSTALLATION PROCEDURE AND OPTIONS 86 is shipped with the following options and straps Option straps and IC s can be located by using the x y coordinate system etched on the PCB Along the length of the PCB is a set of alphabetic coordinates B D etc Along the width of the PCB a set of numeric coordinates 1 2 3 etc can be found These coordinates form an x y grid so tha
60. m Multibus Driver 79 80 IR1 From Multibus Driver 81 IRQ To PIC 82 IRQ From Multibus Driver 83 INT From USART 84 INTN From Optional 8087 Refer to Figure 2 7 for interrupt pad locations INTERRUPT STRAPS PCB COORDINATE 8G NIA III IO OOO QU OV WM IMO 7 P 2 2424042 KA v t My We 7 WA Wi P T CO es 2 CAd PLEO ETE p 2 I I EFFETS by A 7 81 2 822 2 f 772 278 276 dci Z 1512150 73 22746 712 272 w SD h B N 2 VA 5 692 X 28 e lt lt INT FROM USART 17 TO CPU INTN Figure 2 7 INTERRUPT STRAPPING 2 12 5 0 THEORY OF OPERATION 86 The FT 86C processor is the Intel 8086 5 MHz 16 bit microprocessor The 8086 communicates to the outside world via a 20 bit wide multiplexed address and data bus 1 addresses and data exist on the same pins but at different times The separation of data and address values is achieved by using signals derived from the 8086 status lines Eleven additional 8086 lines provide the timing and control interfaces Internally the 8086 can be considered as three major elements the Bus Interface Unit BIU the Execution Unit EU and the timing and control unit The bus interfa
61. monitored by the discrete control logic under program control Strapping options permit on board emulation of the modem control signals The automatic interrupt vectoring capability of the ZSIO is not used An attempt to use the ZSIO generated interrupt vectors will cause an indeterminate result Both channels contain command registers that must be programmed prior to operation The controlFORTH monitor initializes Channel A and B of the 2510 5 4 5 PROGRAMMING THE WRITE REGISTERS The 780 510 contains eight registers WRO WR7 in each channel that are programmed separately by the system program to configure the functional personality of the channels With the exception of programming the write register requires two bytes The first byte contains three bits 00 02 that point to the selected register the second byte is the actual control word that is written into the register to configure the 780 510 See Figure 3 5 is a special case in that all the basic commands 0 2 be accessed with a single byte Reset internal or external initializes the pointer bits 0 2 to point to WRO 5 9 5 5 4 PROGRAMMING THE READ REGISTERS The 280 510 contains three registers RRO RR2 Figure 3 1 that can be read to obtain the status information for each channel except for RR2 Channel B only The status information includes error conditions interrupt vector and standard communications interface signals
62. n determining the stack contents during debugging programs and learning F ORTH nl n2 nj divide Divides nl by n2 and leave the quotient n5 n3 is rounded toward zero The remainder is lost nl n2 n5 n4 divide mod Divides nl by n2 and leaves the quotient n5 and remainder n4 n3 has the same sign as nl p zero The number zero is placed on top of the stack n flag zero less Leaves a true flag 1 if the number is less than zero negative otherwise leaves a false flag ff The number is lost n flag Zero equals Leaves a true flag 1 if the number is equal to zero otherwise leaves a false flag fl The number is lost GROUP ATTR FORMAT STACK ARITHMETIC ARITHMETIC NUMERIC COMPARISON COMPARISON WORD 1 2 2DROP STACK NOTATION DEF INITION flag zero branch The run time procedure to conditionally branch If the flag is false zero the following in line parameter is added to the interpretive pointer to branch ahead or back Compiled by IF UNTIL and WHILE number one Increments n by of Decrements n by of The number two Increments n by of Decrements n by of sel one is placed on top n n l one plus one according to n n l 3 89 one minus according to 2 two is placed on top n 2 two plus two according to n n 2 two minus
63. nected to the opposite pad in order to be within the on board address space Only the top 4 chip select lines may be used allowing the user to put a maximum of 32 Kbytes of EPROM on board 4 3 One chip select line is provided for 2764 EPROMs This is derived from OR ing the top two chip select lines on pads 119 and 121 If 27645 are to be used pads 119 and 121 must be strapped to 120 and 122 respectively Refer to Figure 4 4 for pad location BASE ADDRESS PAD TO PAD In Hex 0 000 or 00 121 122 0 000 000 119 120 000 or FAQOO 125 124 08000 F 8000 125 126 CHIP SELECT SELECTED ADDRESSES PAD NUMBER DEVICE In Hex 0000 0007 2510 0008 000F 8259A 0010 0017 91 SPARE 0018 001F 90 SPARE 0020 0027 89 SPARE 0028 002F 88 SPARE 0050 0027 87 SPARE 0038 003F 92 SPARE pub 87 8889 9091 D2 m uo SEE 277794722792 IO OU AKA KE RAN ARRA RAP Figure 4 3 1 0 SELECT PADS 4 5 2 RAM SELECT LINES The RAM select lines are decoded on 4 Kbyte boundaries One select line is used to select the 2 Kbit by 8 RAM chips at board locations 1A and 6A Seven select lines are avilable for use options To be included in the on board RAM space the user must connect the appropriate pad to the pad opposite it in addition to wiring the select signal to the RAM chip Refer to Figure 4 4 for pad location BASE ADDRESS OF CHIP SELECT CONNECT TO SELECT LINE Hex PAD NUMBER PAD NUMBER 00000 0000
64. not within the resident address space the signal to the 8289 bus arbiter is raised and the 8289 contends for the Multibus As soon as the 8289 has gained control of the Multibus the Multibus address drivers are enabled as is the Multibus bus controller At T2 time the 8086 floats its multiplexed address data lines preparatory to outputting or inputting data the resident bus controller is enabled it will now generate the appropriate command which has been decoded from the processor status lines If the Multibus bus controller is enabled the appropriate commands are issued to the Multibus and the resident bus controller is held disabled At T3 the appropriate control signals are issued from whichever bus controller is active to condition one of the sets of data bus transceivers The control signals will be held active through T5 and Twait where Twait may be 0 up to number of Twaits is dependent on the speed of the addressed device When addresses are within resident bus address space the FT 86C allows the user to strap select separate wait states for EPROM RAM and I O When addresses are not within the resident bus space Twait will be issued until the addressed Multibus device responds with an acknowledgement XACK At T4 time the 8086 floats its address data lines preparatory to issuing a new address at the following T1 The commands are terminated as are the control signals processor status lines S0 S1 and 52
65. of a user variable pointing to the vocabulary into which new word definitions are to be entered dl 92 d3 d plus Adds double precision numbers dl and d2 and leaves the double precision number sum d5 GROUP ATTR FORMAT INPUT OUTPUT DICTIONARY SECURITY 0 DICTIONARY ARITHMETIC WORD D D R DABS DECIMAL DEF INITIONS STACK NOTATION DEFINITION di n d2 d plus Applies the sign of n to the double precision number dl and leaves it as double precision number 2 Displays a signed double precision number from a 32 bit two s complement value The high order 16 bits are most accessable on the stack version is performed according to the current BASE A blank follows n d dot r Displays a signed double precision number d right aligned in a field n characters wide blank follows d ud d abs leaves the absolute value ud of a double number decimal Sets the numeric conversion BASE to decimal base 10 for input output definitions Used in the form cccc DEFINITIONS Sets CURRENT to the CONTEXT vocabulary so that subsequent definitions will be created in the vocabulary previously selected at CONTEXT In the example executing vocabulary name made it the CONTEXT vocabulary and executing DEF INITIONS made both specify vocabulary cccc GROUP ARITHMETIC FORMAT FORMAT ARITHME TIC NUMERIC VOCABULARY A 19 WORD
66. pare Spare Spare Spare Spare Spare Spare Spare Spare Spare Spare Spare Spare Spare Spare Spare Spare Spare Spare J1 CONNECTIONS PIN 26 2 28 29 50 5l 32 5 34 35 36 57 38 39 40 41 42 45 44 45 26 47 48 49 20 SIGNAL Spare Spare Spare Spare Spare Spare Spare Transmit Data Channel B Spare Data Terminal Ready Channel B Spare Data Terminal Ready Channel A Receive Data Channel B Request to Send Channel A Data Carrier Detect Channel B Transmit Data Channel A Clear to Send Channel B Request to Send Channel B Transmit Clock Channel B Clear to Send Channel A Receive Clock Channel B Data Carrier Detect Channel A Receive Data Channel A Receive Clock Channel A Transmit Clock Channel A
67. priate commands and enable signals 3 1 5 I O BUS The local I O bus consists of the low order 8 bits of both the data and address lines It is activated for an input or output operation The I O bus is only active for local I O addresses in the range 00 to 3F Hex MEMORY The on board memory resides in two overlapped 64 Kbyte address areas 0000 to FFFFF Hex 00000 to OFFFF Hex An address of Hex FFFFO will also address Hex This overlaid 64 Kbyte area is decoded into two sections of 32 Kbytes for EPROM and 52 Kbytes for RAM 5 2 5 2 1 RANDOM ACCESS MEMORY 86 comes with 4 Kbytes of RAM This is at addresses Hex 00000 to DOFFF and also Hex 0000 to FOFFF The RAM is configured with 2 x 8 Kbytes 200ns static RAMs Decoding is provided for up to seven additional pairs of RAMs up to a maximum of 52 Kbytes 5 2 2 PROGRAMMABLE READ ONLY MEMORY Four configuration pads are provided for EPROMs Each pad may be configured for 2252 2752 2764 parts Decoding is provided for four pairs of 32 Kbit EPROMs One chip select line is provided for one pair of 2764 EPROMs INTERRUPT REQUESTS 111 197 BPRN BREO BPR BUSY CBRO INIT BUS CO pou CPU CLK GER DRIVERS OPTIONAL 5087 b 4 ADO AD13 9J gt SYSO RESB MULTIBUS tock __ AEN 4 50 53 BUS ARBITER CEN BCLK lt gt 00 013 PROM
68. r separated with spaces on the same line with a carriage return lt at the end Once a base is selected it will remain in effect until another base command is entered Base commands HEX lt Sets hexadecimal base DECIMAL Sets decimal base OCTAL Sets octal base The base selected will affect the number of characters displayed in any numeric field All command formats shown use the hexadecimal base See the glossary for more information 5 2 MONITOR COMMANDS Implied Segment Value 5 2 1 STUFF FORMAT AAAA CCCC VV STUFF AAAA Source address CECE Byte count VV Value to be inserted The STUFF command executes using the implied segment value Memory will be filled with the specified value VV starting at address AAAA for the number of bytes specified in CCCC See 5 4 1 for information on setting or viewing the implied segment value The 16 bit implied segment value and 16 bit addresses are used together to generate the 20 bit addresses of the 8086 See the biblography in Appendix B for more information the 8086 9 1 EXAMPLE HEX 00 10 55 STUFF This example fills 16 decimal hexadecimal 10 memory locations starting at hexadecimal address COO with hexadecimal 55 5 2 2 SUBSTITUTE FORMAT AAAA SUBSTITUTE AAAA Starting address DISPLAY FORMAT 5555 AAAA HH This command executes on successive byte memory locations If the contents of a byte location do not need to be changed pressing carriage return will not
69. re Data Terminal Ready Channel A Spare Data Terminal Ready Channel B Receive Data Channel B Request to Send Channel A Data Carrier Detect Channel B Transmit Data Channel A Clear to Send Channel B Request to Send Channel B Transmit Clock Channel B Clear to Send Channel A Receive Clock Channel B Data Carrier Detect Channel A Receive Data Channel A Receive Clock Channel A Transmit Clock Channel A Pin Assignment of Bus Signals 796 Bus Board Connector 2 CIRCUIT SIDE PIN MNEMONIC DESCRIPTION 2 Reserved Not Bussed 4 Reserved Not Bussed 6 Reserved Not Bussed 8 Reserved Not Bussed 10 Reserved Not Bussed 12 Reserved Not Bussed 14 Reserved Not Bussed 16 Reserved Not Bussed 18 Reserved Not Bussed 20 Reserved Not Bussed 22 Reserved Not Bussed 24 Reserved Not Bussed 26 Reserved Not Bussed 28 Reserved Not Bussed 30 Reserved Not Bussed 52 Reserved Not Bussed 54 Reserved Not Bussed 56 Reserved Not Bussed 38 Reserved Not Bussed 40 Reserved Not Bussed 42 Reserved Bussed 44 Reserved Bussed 46 Reserved Bussed 48 Reserved Bussed 50 Reserved Bussed 52 Reserved Bussed 54 Reserved Bussed 56 ADR17 Address Bus 58 ADR15 60 Reserved Bussed ON ON WN N NN NY PM PN DN FH e BY Be Be Ye FW OO DON FW SIGNAL Ground Ground Spare External Reset Spare Spare S
70. rrent input text buffer terminal or disk from which the next text will be accepted WORD uses and moves the value of IN interpret The outer text interpreter which sequentially executes or compiles text from the input stream terminal or mass storage depending on STATE If the word name cannot be found after a search of CONTEXT and then CURRENT it is converted to a number according to the current BASE That also failing an error message echoing the lt name gt with a will be given Text input will be taken according to the con vention for WORD If a decimal point is found as part of a number a double number value will be left The decimal point has no other purpose than to force this action See NUMBER char key Leaves the ASCII value of the next avaiable character from the active input device addr latest Leave the name field address of the top most word in the CURRENT vocabulary GROUP ATTR COMPILER INPUT OUTPUT U COMPILER INPUT OUTPUT COMPILER WORD LEAVE LFA LIMIT LIT LITERAL STACK NOTATION DEF INITION leave Forces termination of a DO LOOP at the next opportunity by setting the loop limit equal to the current value of the index index itself remains unchanged and execution proceeds nor mally until LOOP or LOOP is encountered pfa fa Converts the parameter field address pfa of dictionary definition to its link field address
71. rupt controller other activity takes place during this processor cycle The second processor cycle duplicates the first up to issuing the The second INTA causes the 8259A to issue a vector byte to the 8086 via the I O data bus transceiver The vector byte is used to generate an address where the 8085 loads a new code segment and instruction pointer The base address of the interrupt controller is Hex 0008 Address line 1 is used to indicate the first word of either an initialized command word or an operational command word For full programming information see the Intel Component Data Catalog or the 8086 User s Guide SECTION 4 0 BREADBOARD INTERFACE 4 1 MEMORY ADDRESS BUS The memory address bus is available at two locations The full 20 bit address is available at pads through FA15 The lower 8 bits of the address lines are available on pads at board location AO also Refer to Figure 4 1 for pad location Memory addresses are always presented at these locations even when the address is not within the on board address range 4 2 ADDRESS BUS The I O address bus is the lower 8 bits of the address bus The I O address bus is always active when any address is output from the 8086 The addresses are available at board area G2 See Figure 4 2 for pad layout and numbering 4 5 DATA LINES Two separate sets of data transceivers are available One is active during memory references or memory mapped I O operation
72. ry entry for name leaving n in its parameter field When lt name gt is later executed it wil push the value of n to the stack addr context leaves the address of a user variable pointing to the vocabulary in which dictionary searches are made during interpretation of the input stream GROUP ATTR MEMORY MONITOR COMPILER DEF INING DICTIONARY 17 WORD COUNT CR CREATE CSP CURRENT D A 18 STACK NOTATION DEF INITION addr 1 count Leaves the addr l and the character count n of text beginning at addr The first byte at addr must contain the character count n actual text starts with the second byte The range of n is 255 Typically COUNT is followed by TYPE carriage return Transmits a carriage return CR and line feed LF to the active output device create A defining word used in the form CREATE lt name gt Creates a dictionary entry for lt name gt without allocating any parameter field memory When lt name gt is subsequently executed the address of the first byte of lt name gt s parameter field is left on the stack The code field contains the address of the word s parameter field The new word is created in the CURRENT vocabulary addr 5 Leaves the address of a user variable temporarily storing the check stack pointer CSP position for compilation error checking addr current leaves the address
73. s The other is only active during input output or interrupt acknowledge processor cycles 4 5 1 MEMORY DATA BUS Memory data lines are available to the user at pads FDO through FDF During an on board memory write cycle data will be valid on these pads during T5 Tw Tw Tw is governed by strap settings at board location D1 see Wait State Timing Section During an on board memory read data should be presented during T5 Tw Tw Tw See Intel 8086 product specification for exact timings During off board operations the on board transceivers will be tri stated allowing pads FDO through FDF to float The low order byte of the data bus is also available at board location Al Refer to Figure 4 1 for pad location 4 5 2 I O DATA BUS The data bus is the low order byte of the data bus It is only active during an input output or interrupt acknowledge processor cycle Timing is the same as the memory data bus Wait states are set by straps at D2 see Section on Wait State Timing 4 1 60002200000000000000000000 MEMORY ADDRESS BUS PADS oG P i Y N Fi x xs 4 4 i VEA 4 SU DII oP 2 9222 S CEE E EEEE E 209 ri x amp H gt 4 E amp 7777 r ae an er du lo
74. s addr2 matching to the text at addrl Returns parameter field address length of name field byte and Boolean true for good match If no match is found only a Boolean false is left See FIND The run time procedure compiled by LOOP which increments the loop index and tests for loop completion See LOOP d2 addr2 Converts the ASCII text beginning at addrl l with regard to BASE The new value is accumulated into dl being left as d2 addr2 is the address of the first unconvertable digit See NUMBER ni n2 nj times Multiples nl by n2 and leaves the product n5 nl n2 n5 n4 times divide Multiplies nl by n2 divides the result by n5 and leaves the quotient n4 n4 is rounded toward zero product of nl times n2 is maintained as in intermediate 32 bit value for a greater precision than the otherwise equivalent sequence nl n2 n3 nl n2 n5 n4 n5 times divide mod Multiplies nl by n2 divides the result by n3 and leaves the remainder n4 and quotient n5 A 32 bit intermediate product is used as for The remainder has the same sign as nl GROUP ATTR PRIMITIVE PRIMITIVE C PRIMITIVE ARITHME TIC ARITHMETIC ARITHMETIC WORD LOOP STACK NOTATION DEF INITION nl n2 n3 plus Adds nl to n2 and leaves the arithmetic sum n5 n addr plus store Adds n to the 16 bit value at the address by the convention given for nl n2 n5
75. ser variable containing the number of digits to the right of the decimal on double integer input It may also be used to hold the output column location of a decimal point in user generated formatting The default value on single number input is l GROUP ATTR DEF INING COMPILER U FORMAT U A 21 WORD DROP DUMP DUP ELSE EMIT A 22 STACK NOTATION DEF INITION n drop Drops the number on top of the stack from the stack addr n dump Displays the contents of n memory locations be ginning at addr Both addresses and contents are shown in the current numeric base n n n dup Duplicates the value on the stack addr nl addr n2 compiling else Occurs within a colon definition in the form IF ELSE THEN At run time ELSE executes after the true part following IF ELSE forces execution to skip over the following false part and resumes execution after the THEN It has no stack effect At compile time ELSE emplaces BRANCH serving a branch offset leaves the address addr2 and n2 for error testing ELSE also resolves the pending forward branch from IF by calculating the offset from addrl to HERE and storing at addrl See IF and THEN char emit Transmits an ASCII character to the active output device See KEY GROUP ATTR STACK INPUT OUTPUT STACK CONTROL I INPUT OUTPUT WORD ENCLOSE ERASE ERROR EXECUTE EXPECT STACK NO
76. t straps and IC s can be located rapidly 2 1 MULTIBUS CONTROL The F T 86C is optioned to act as bus master with the highest priority This is done by a strap pad 1 to pad 2 at board location 8J which holds pin 9 of the 8289 to ground Refer to Figure 2 1 for pad locations and Figure 2 2 for specific strapping information Cutting the ground strap allows the FT 86C to respond to the Multibus bus priority in BPRN signal The FT 86C can be used in either parallel or serial bus priority arbitration schemes For parallel priority arbitration external logic must be provided The 8289 bus arbiter has the signal ANYRQST option strapped to ground via pads 9 and 10 Refer to Figure 2 1 for pad locations and Figure 2 2 for specific strapping information In this mode the FT86C will not release the Multibus unless it has completed its immediate bus access requirements Cutting the ground trace between pads 9 and 10 and strapping ANYRQST to the adjacent option hole pad 8 will hold ANYRQST high The FT 86C will now relinquish the bus as soon as the current bus transfer cycle if any has been completed ANYRQST BPRN FUNCTION FACTORY Low Low Low 2 2 STANDARD t will not relinquish the bus Low Driven by pin 15 Low The F T 86C will relinquish on Multibus the bus only to a higher USER priority master OPTIONS Low Driven by pin 15 High The FT 86C relinquishes on Multibus the Multibus after each transfer cycle 2 1 2
77. tegers addr u abort Leaves the address of the user variable containing the code field address of the ABORT word GROUP ATTR INPUT OUTPUT U MEMORY INPUT OUTPUT ARITHME TIC ARITHMETIC ARITHMETIC PARAMETER 1 WORD UC L UKEY ULIMIT UNTIL STACK NOTATION DEFINITION addr u characters per line Leaves the address of the user variable containing the number of characters per line addr u emit Leaves the address of the user variable containing the code field address of the EMIT output word addr Leaves the address of the user variable containing code filed address of the KEY input word addr u limit Leaves the address of the user variable containing the last address plus one of the data or mass storage buffer flag run time addr n compile time until Occurs within a colon definition in the form BEGIN UNTIL At run time if flag is true the loop is terminated If flag is false execution returns to the first word after BEGIN BEGIN UNTIL structures may be nested At compile time UNTIL compiles BRANCH and an offset from HERE to addr n is used for error tests GROUP ATTR PARAMETER U PARAMETER U PARAMETER 0 PARAMETER U CONTROL WORD USER VARIABLE VOC LINK VOCABULARY A 56 STACK NOTATION DEF INITION n e as aw user A defining word used in the form n USER lt name gt W
78. turn stack pointer n d s to d Extends the sign of single number n to form double number d addr s zero Leaves the address user variable that contains the initial value for the parameter stack pointer See SP addr s c r Leaves the address of user variable containing the screen number most recently referenced n d d sign Inserts the ASCII minus sign into the pictured numeric output string if n is negative n is discarded but double number d is maintained Must be used between lt and gt smudge Used during word definition to toggle the smudge bit in a definitions name field This prevents an uncompleted definition from being found during dictionary searches until compiling is completed without error s p store Initializes the stack pointer from Sf GROUP ATTR STACK ARITHMETIC PRIMITIVE MASS FORMAT DICTIONARY STACK WORD sP SPACE SPACES STATE SWAP TASK THEN STACK NOTATION DEF INITION addr s p fetch Returns the address of the top of the stack as it was before 5 was executed spaces Transmits an ASCII blank to the active output device n c an o spaces Transmit n ASCII blanks to the active output device addr state Leaves the address of user variable containing the compilation state non zero value indicates compilation nl n2 n2 nl swap Exchanges the top two values on the

FT-86C and FT-86C/FP USER`S MANUAL FORWARD

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