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Z8 Encore! XP 8K and 4K Series

1. gt Receiver Control aan with Address Compare MM er Receive Shifter A icr Control Registers System Bus Y Transmit Data i Register Status Register Baud Rate Generator Transmit Shift TXD Register CTS Parity Generator Transmitter Control DE Operation Data Format Figure 10 UART Block Diagram Lis Zi LOG The UART always transmits and receives data in an 8 bit data format least significant bit first An even or odd parity bit can be added to the data stream Each character begins with an active Low START bit and ends with either 1 or 2 active High STOP bits Figure 11 and Figure 12 illustrate the asynchronous data format employed by the UART without parity and with parity respectively PS022820 0307 Universal Asynchronous Receiver Transmitter Idle State of Line q Data Field Is Z8 Encore XP 8K and 4K Series Product Specification ZI Zi LOG gt Stop Bit s b 1 A srt BitO Biti Bit2 y Bit3 y Bit4 0 Idle State of Line msb y Bit5 Bit6 y Bit7 l M i 2 Figure 11 UART Asynchronous Data Format without Parity q Data Field gt Stop Bit s Isb msb 1 T l V Start f Bito Biti y Bit2 y Bit3 yX Bit4 1 Bit5 y Bit6 Bit7 Jerem g i
2. 5 eo Ea G o o 2 2 S z pdo lerr t 4 2 oOo 3 Qux E go i gg 2 9Q 2525 53584 Z8 Encore XP 8K and 4K Series with 1 KB Flash Standard Temperature 0 C to 70 C Z8F011APBO20SC 1KB 256B 16B 6 13 2 0 1 1 0 PDIP 8 pin package Z8F011AQB020SC 1KB 256B 16B 6 13 2 0 1 1 0 QFN 8 pin package Z8F011ASBO20SC 1KB 256B 16B 6 13 2 0 1 1 0 SOIC 8 pin package Z8F011ASH020SC 1KB 256B 16B 17 19 2 0 1 1 0 SOIC 20 pin package Z8F011AHHO20SC 1KB 256B 16B 17 19 2 0 1 1 0 SSOP 20 pin package Z8F011APHO20SC 1KB 256B 16B 17 19 2 0 1 1 00 PDIP 20 pin package Z8F011ASJ020SC 1KB 256B 16B 25 19 2 0 1 1 0 SOIC 28 pin package Z8F011AHJO20SC 1KB 256B 16B 25 19 2 0 1 1 0 SSOP 28 pin package Z8F011APJ020SC 1KB 256B 16B 25 19 2 0 1 1 0 PDIP 28 pin package Extended Temperature 40 C to 105 C Z8F011APBO20EC 1KB 256B 16B 6 13 2 0 1 1 0 PDIP 8 pin package Z8F011AQB020EC 1KB 256B 16B 6 13 2 0 1 1 0 QFN 8 pin package Z8F011ASBO20EC 1KB 256B 16B 6 13 2 0 1 1 0 SOIC 8 pin package Z8F011ASHO20EC 1KB 256B 16B 17 19 2 0 1 1 0 SOIC 20 pin package Z8F011AHHO20EC 1KB 256B 16B 17 19 2 0 1 1 0 SSOP 20 pin package Z8F011APHO20EC 1KB 256B 16B 17 19 2 0 1 1 0 PDIP 20 pin package Z8F011ASJO20EC 1KB 256B 16B 25 19 2 0 1 1 0 SOIC 28 pin package Z8F011AHJO20EC 1KB 256B 16B 25 19 2 0 1 1 0 SSOP 28 pin package Z8F011APJO20EC 1KB 256B 16B 25 19 2 0 1 1 0 PDIP 28 pin package Replace C with G for Lead Free
3. BITS 7 6 5 4 3 2 1 0 FIELD Reserved RESET U U U U U U U U R W R W R W R W R W R W R W R W R W ADDR Information Page Memory 0020H Note U Unchanged by Reset R W Read Write PS022820 0307 Reserved Altering this register may result in incorrect device operation Flash Option Bits 158 Z8 Encore XP 8K and 4K Series Product Specification Ll i ZiLOG Trim Bit Address 0001H Table 89 Trim Option Bits at 0001H BITS 7 6 5 4 3 2 1 0 FIELD Reserved RESET U U U U U U U U R W R W R W R W R W R W R W R W R W ADDR Information Page Memory 0021H Note U Unchanged by Reset R W Read Write Reserved Altering this register may result in incorrect device operation Trim Bit Address 0002H Table 90 Trim Option Bits at 0002H TIPO BITS 7 6 5 4 3 2 1 0 FIELD IPO_TRIM RESET U R W R W ADDR Information Page Memory 0022H Note U Unchanged by Reset R W Read Write IPO TRIM Internal Precision Oscillator Trim Byte Contains trimming bits for Internal Precision Oscillator Trim Bit Address 0003H gt Note The LVD is available on 8 pin devices only Table 91 Trim Option Bits at Address 0003H TLVD BITS 7 6 5 4 3 2 1 0 FIELD Reserved LVD TRIM RESET U U U U U U U U R W R W R W R W R W R W R W R W R W ADDR Information Page Memory 0023H Note U Un
4. 38 Direct LED Drive 39 Shared Reset Pin 39 shared Debug PIN si iip a hber dU ber EU epa aa 39 Crystal Oscillator Override 40 5V Tolerance 40 ErkternalClockSetup 40 GPIO Interrupts 45 GPIO Control Register Definitions 45 Port A D Address Registers 46 Port A D Control Registers 47 Port A D Data Direction Sub Registers 47 Port A D Alternate Function Sub Registers 48 Table of Contents vi PS022820 0307 Z8 Encore XP 8K and 4K Series Product Specification ZiLOG Port A C Input Data Registers 52 Port A D Output Data Register 52 LED Drive Enable Register 53 LED Drive Level High Register 53 LED Drive Level Low Register 54 Interrupt Controller 55 Interrupt Vector Listing 55 ATE EWE RE RR CE 57 OpGratlOn eese ei
5. Table 137 Comparator Electrical Characteristics VDD 2 7 to 3 6 V TA 40 C to 105 C Symbol Parameter Minimum Typical Maximum Units Conditions Vos Input DC Offset 5 mV Vcngr Programmable Internal 5 20 28 pin devices Reference Voltage 3 8 pin devices Tprop Propagation Delay 200 ns Vuvs Input Hysteresis 4 mV Vin Input Voltage Range Vss Vpp 1 V PS022820 0307 Electrical Characteristics Z8 Encore XP 8K and 4K Series Product Specification Zi Zi LOG Table 138 Temperature Sensor Electrical Characteristics Vpp 2 7 to 3 6 V Symbol Parameter Minimum Typical Maximum Units Conditions Taerr Temperature Error 0 5 2 C Over the range 20 C to 30 C as measured by ADC 1 5 C Over the range 0 C to 70 C as measured by ADC 2 7 C Over the range 0 C to 105 C as measured by ADC 7 C Over the range 40 C to 105 C as measured by ADC TaeRR Temperature Error TBD C Over the range 40 C to 105 C as measured by comparator twake Wakeup Time 80 100 us Time required for Temperature Sensor to stabilize after enabling Devices are factory calibrated at for maximal accuracy between 20 C and 30 C so the sensor is maximally accurate in that range User re calibration for a different temperature range is possible and
6. ZiLOG Table 124 eZ8 CPU Instruction Summary Continued Assembly Symbolic Adress Mode Opcode s Fags Fetch Instr Mnemonic Operation dst src Hex C Z S V D H Cycles Cycles AND dst src dst lt dst AND src r r 52 0 2 3 r Ir 53 2 4 R R 54 3 3 R IR 55 3 4 R IM 56 3 3 IR IM 57 3 4 ANDX dst src dst dst AND src ER ER 58 Q 4 3 ER IM 59 4 3 ATM Block all interrupt and 2F 1 2 DMA requests during execution of the next 3 instructions BCLR bit dst dst bit 0 r E2 2 2 BIT p bit dst dst bit p r E2 2 2 BRK Debugger Break 00 1 1 BSET bit dst dst bit 1 r E2 2 2 BSWAP dst dst 7 0 lt dst 0 7 R D5 xX QO 2 2 BTJ p bit src dst if src bit p r F6 3 3 PC lt PC X ir F7 3 4 BTJNZ bit src dst if src bit 1 r F6 3 3 PC lt PC X Ir F7 3 4 BTJZ bit src dst if src bit 2 O r F6 3 3 PC lt PC X i F7 3 CALL dst SP SP 2 IRR D4 2 6 ere Da pe TE CCF C C EF K ee ei ka 1 2 CLR dst dst lt 00H R BO 2 2 IR B1 2 3 Flags Notation Value is a function of the result of the operation 0 Reset to 0 Unaffected 1 Set to 1 X Undefined PS022820 0307 eZ8 CPU Instruction Set Z8 Encore XP 8K and 4K Series Product Specification Z 211
7. 189 Oscillator Control Register Definitions 190 Crystal Oscillator 12i no Wa RD eS 193 Operating Modes 193 Crystal Oscillator Operation 193 Oscillator Operation with an External RC Network 195 Internal Precision Oscillator 199 ee cu Em 199 eZ8 CPU Instruction Set llllllllllllees s 201 Assembly Language Programming Introduction 201 Assembly Language Syntax 202 eZ8 CPU Instruction Notation 202 eZ8 CPU Instruction Classes 204 eZ8 CPU Instruction Summary 209 Opcode Maps 2 Rem Rr RR CERE RS RR eae E RR RR RUNS 218 Electrical Characteristics 223 Absolute Maximum Ratings 223 DC Characteristics 224 AC Characteristics 229 On Chip Peripheral AC and DC Electrical Characteristics 231 Table of Contents xi PS022820 0307 Z8 Encore XP 8K and 4K Series Product Specification ZiLOG General Purpose I O Port Input Data Sample Timing 236 General Purpose I O Port Outpu
8. BITS 7 6 5 4 3 2 1 0 FIELD RAND_LOT RESET U U U U U U U U R W R W R W R W R W R W R W R W R W ADDR Interspersed throughout Information Page Memory Note U Unchanged by Reset R W Read Write RAND LOT Randomized Lot ID The randomized lot ID is a 32 byte binary value that changes for each production lot Table 102 Randomized Lot ID Locations Info Page Memory Address Address Usage 3C FE3C Randomized Lot ID Byte 31 most significant 3D FE3D Randomized Lot ID Byte 30 3E FE3E Randomized Lot ID Byte 29 3F FE3F Randomized Lot ID Byte 28 58 FE58 Randomized Lot ID Byte 27 59 FE59 Randomized Lot ID Byte 26 5A FE5A Randomized Lot ID Byte 25 5B FE5B Randomized Lot ID Byte 24 5C FE5C Randomized Lot ID Byte 23 PS022820 0307 Flash Option Bits Z8 Encore XP 8K and 4K Series Product Specification A Zi LOG Table 102 Randomized Lot ID Locations Continued Info Page Memory Address Address Usage 5D FE5D Randomized Lot ID Byte 22 5E FE5E Randomized Lot ID Byte 21 5F FE5F Randomized Lot ID Byte 20 61 FE61 Randomized Lot ID Byte 19 62 FE62 Randomized Lot ID Byte 18 64 FE64 Randomized Lot ID Byte 17 65 FE65 Randomized Lot ID Byte 16 67 FE67 Randomized Lot ID Byte 15 68 FE68 Randomized Lot ID Byte 14 6A FE6A Randomized Lot ID Byte 13 6B FE6B Randomized Lot ID Byte 12 6D FE6D Randomized Lot I
9. ZiLOG Table 124 eZ8 CPU Instruction Summary Continued Assembly Symbolic madness Mode Opcode s Flags Fetch Instr Mnemonic Operation dst src Hex C Z S V D H Cycles Cycles SUBX dst src dst dst src ER ER 28 uS ML M S S 4 3 ER IM 29 4 3 SWAP dst dst 7 4 lt gt dst 3 0 R FO X KX 2 2 IR F1 2 3 TCM dst src NOT dst AND src r r 62 0 2 3 r Ir 63 2 4 R R 64 3 3 R IR 65 3 4 R IM 66 3 3 IR IM 67 3 4 TCMX dst src NOT dst AND src ER ER 68 0 4 3 ER IM 69 4 3 TM dst src dst AND src r r 72 0 2 3 r Ir 73 2 4 R R 74 3 3 R IR 75 3 4 R IM 76 3 3 IR IM 77 3 4 TMX dst src dst AND src ER ER 78 0 4 3 ER IM 79 4 3 TRAP Vector SP SP 2 Vector F2 2 6 SP PC SP SP 1 SP FLAGS PC Vector WDT 5F 1 2 Flags Notation Value is a function of the result of the operation 0 Reset to 0 Unaffected 1 Setto1 X Undefined PS022820 0307 eZ8 CPU Instruction Set Z8 Encore XP 8K and 4K Series Product Specification Z 217 ziLoc Table 124 eZ8 CPU Instruction Summary Continued Assembly Symbolic Address Mode Opcode s Flags Fetch Instr Mnemonic Operation dst src Hex C Z S V D H Cycles Cycles XOR dst src dst lt dst XOR src r r B2 0 2 3 r Ir B3 2 4 R R B4 3 3 R IR B5 3 4 R IM B6 3 3 IR IM B7 3 4 XORX dst src dst dst KOR src ER ER B8 Q 4 3 ER IM B9 4 3 Flags Notatio
10. 102 Clear To Send CTS Operation 103 MULTIPROCESSOR 9 bit Mode 103 External Driver Enable 104 UART Interr pts sese Rasa eie RC EORR RR RE Ue ee a 105 UART Baud Rate Generator 107 UART Control Register Definitions 108 UART Control 0 and Control 1 Registers 108 UART Status 0 Register 111 UART Status 1 Register issus vk in tele de RC RR CAL RR RC UR Bn 112 UART Transmit Data Register 113 UART Receive Data Register 113 UART Address Compare Register 113 UART Baud Rate High and Low Byte Registers 114 Infrared Encoder Decoder 117 uei AI enke e CTI 117 Operation zie xaO EGO EO EROR ARR ea UA C OR CR 117 Transmitting IrDA Data 118 Receiving IrDA Data 119 Infrared Encoder Decoder Control Register Definitions 120 Analog to Digital Converter 121 uei MT n 121 Operation AA AA KA AAA Ka AA 122 Table of Contents Z8 Encore XP 8K and 4K Series Product Specification ZiLOG Data Forma
11. Minimum Maximum Operation Latency Latency Read 16 byte array 875 9961 Read 64 byte array 876 8952 Read 128 byte array 883 7609 Write 16 byte array 4973 5009 Write 64 byte array 4971 5013 Write 128 byte array 4984 5023 Illegal Read 43 43 Illegal Write 31 31 If NVDS read performance is critical to your software architecture there are some things you can do to optimize your code for speed listed in order from most helpful to least helpful Periodically refresh all addresses that are used The optimal use of NVDS in terms of speed is to rotate the writes evenly among all addresses planned to use bringing all reads closer to the minimum read time Because the minimum read time is much less than the write time however actual speed benefits are not always realized Use as few unique addresses as possible this helps to optimize the impact of refreshing as well as minimize the requirement for it Non Volatile Data Storage Z8 Encore XP 8K and 4K Series Product Specification Li Zi LOG On Chip Debugger The Z8 Encore XP 8K and 4K Series devices contain an integrated On Chip Debugger OCD that provides advanced debugging features including Single pin interface Reading and writing of the register file Reading and writing of program and data memory Setting of breakpoints and watchpoints Executing eZ8 CPU instructions Debug pin sharing with general purpose input output function to
12. gt 2 Figure 12 UART Asynchronous Data Format with Parity Transmitting Data using the Polled Method PS022820 0307 Follow these steps to transmit data using the polled method of operation 1 Write to the UART Baud Rate High and rate Low Byte registers to set the required baud Enable the UART pin functions by configuring the associated GPIO Port pins for alternate function operation Write to the UART Control 1 register if MULTIPROCESSOR mode is appropriate to enable MULTIPROCESSOR 9 bit mode functions Set the Multiprocessor Mode Select MP1 EN bit to enable MULTIPROCESSOR mode Write to the UART Control 0 register to Set the transmit enable bit TEN to enable the UART for data transmission Set the parity enable bit PEN if pa rity is appropriate and MULTIPROCESSOR mode is not enabled and select either even or odd parity PSEL Set or clear the CTSE bit to enable or disable control from the remote receiver using the CTS pin Universal Asynchronous Receiver Transmitter Z8 Encore XP 8K and 4K Series Product Specification Zi LOG 6 Check the TDRE bit in the UART Status 0 register to determine if the Transmit Data register is empty indicated by a 1 If empty continue to Step 7 If the Transmit Data register is full indicated by a 0 continue to monitor the TDRE bit until the Transmit Data register becomes available to receive new data 7 Writ
13. On Chip Debugger initiated Reset System Reset except the On Chip Debugger OCDCTL 0 set to 1 is unaffected by the reset STOP mode Power on reset Voltage Brown Reset delay begins after supply voltage Out exceeds POR level RESET pin assertion All reset pulses less than the specified analog delay are ignored See Table 131 on page 231 DBG pin driven Low None Power On Reset Z8 Encore XP 8K and 4K Series devices contain an internal power on reset POR circuit The POR circuit monitors the supply voltage and holds the device in the Reset state until the supply voltage reaches a safe operating level After the supply voltage exceeds the POR voltage threshold Vpog the device is held in the Reset state until the POR Counter has timed out If the crystal oscillator is enabled by the option bits this timeout is longer After the Z8 Encore XP 8K and 4K Series device exits the power on reset state the eZ8 CPU fetches the Reset vector Following Power on reset the POR status bit in the Reset Status RSTSTAT register is set to 1 Figure 5 illustrates Power on reset operation See the Electrical Characteristics on page 223 for the POR threshold voltage Vpop PS022820 0307 Reset Stop Mode Recovery and Low Voltage Detection Z8 Encore XP 8K and 4K Series Product Specification Li Zi LOG Vec 0 0V Crystal Oscillator signal Program 4 Execution gt Internal Precision
14. In CONTINUOUS mode the system clock always provides the timer input The timer period is given by the following equation Reload Value x Prescale Continuous Mode Time Out Period s System Clock Frequency Hz If an initial starting value other than 0001H is loaded into the Timer High and Low Byte registers use the ONE SHOT mode equation to determine the first time out period COUNTER Mode In COUNTER mode the timer counts input transitions from a GPIO port pin The timer input is taken from the GPIO Port pin Timer Input alternate function The TPOL bit in the Timer Control Register selects whether the count occurs on the rising edge or the falling edge of the Timer Input signal n COUNTER mode the prescaler is disabled UN Caution The input frequency of the Timer Input signal must not exceed one fourth the system clock frequency Further the high or low state of the input signal pulse must be no less than twice the system clock period A shorter pulse may not be captured Upon reaching the Reload value stored in the Timer Reload High and Low Byte registers the timer generates an interrupt the count value in the Timer High and Low Byte registers is reset to 0001H and counting resumes Also if the Timer Output alternate function is enabled the Timer Output pin changes state from Low to High or from High to Low at timer Reload PS022820 0307 Timers Z8 Encore XP 8K and 4K Series Product Specification VAR ZiLOG The
15. Table 128 Power Consumption Continued Z8 Encore XP 8K and 4K Series Product Specification Z 227 ZiLOG Vpp 2 7 V to 3 6 V 1 Typical conditions are defined as Vpp 3 3 V and 30 C Maximum Maximum Symbol Parameter Typical Std Temp Ext Temp Units Conditions Ibp LPO Low Power Operational 3 5 5 HA Driving a high Amplifier Supply impedance load Current Ipp TS Temperature Sensor 60 pA See Note 4 Supply Current Ipp BG Band Gap Supply 320 480 500 pA For 20 28 pin devices Current For 8 pin devices Notes Standard temperature is defined as T4 0 C to 70 C these values not tested in production for worst case behavior but are derived from product characterization and provided for design guidance only 3 Extended temperature is defined as T4 40 C to 105 C these values not tested in production for worst case behavior but are derived from product characterization and provided for design guidance only For this block to operate the bandgap circuit is automatically turned on and must be added to the total supply current This bandgap current is only added once regardless of how many peripherals are using it PS022820 0307 Electrical Characteristics Z8 Encore XP 8K and 4K Series Product Specification Zi Zi LOG Figure 33 illustrates the typical current consumption while operating with all peripherals disabled at 30 C versus th
16. Z8 Encore XP 8K and 4K Series Product Specification ZI Zi LOG Address Hex Register Description Mnemonic Reset Hex Page No F91 FBF Reserved XX Interrupt Controller FCO Interrupt Request 0 IRQO 00 60 FC1 IRQO Enable High Bit IRQOENH 00 63 FC2 IRQO Enable Low Bit IRQOENL 00 63 FC3 Interrupt Request 1 IRQ1 00 61 FC4 IRQ1 Enable High Bit IRQ1ENH 00 64 FC5 IRQ1 Enable Low Bit IRQ1ENL 00 64 FC6 Interrupt Request 2 IRQ2 00 62 FC7 IRQ2 Enable High Bit IRQ2ENH 00 65 FC8 IRQ2 Enable Low Bit IRQ2ENL 00 65 FC9 FCC Reserved XX FCD Interrupt Edge Select IRQES 00 66 FCE Shared Interrupt Select IRQSS 00 66 FCF Interrupt Control IRQCTL 00 67 GPIO Port A FDO Port A Address PAADDR 00 45 FD1 Port A Control PACTL 00 47 FD2 Port A Input Data PAIN XX 47 FD3 Port A Output Data PAOUT 00 47 GPIO Port B FD4 Port B Address PBADDR 00 45 FD5 Port B Control PBCTL 00 47 FD6 Port B Input Data PBIN XX 47 FD7 Port B Output Data PBOUT 00 47 GPIO Port C FD8 Port C Address PCADDR 00 45 FD9 Port C Control PCCTL 00 47 FDA Port C Input Data PCIN XX 47 FDB Port C Output Data PCOUT 00 47 GPIO Port D FDC Port D Address PDADDR 00 45 FDD Port D Control PDCTL 00 47 FDE Reserved XX XX Undefined PS022820 0307 Register Map Z8 Encore XP 8K and 4K Series Product Specification ZI Zi LOG Table 7 Register File Address Map Contin
17. Alternate Function Set Port Pin Mnemonic Alternate Function Description Register AFS1 PCO Reserved AFS1 0 0 ANA4 CINP LED ADC or Comparator Input or LED drive AFS1 0 1 Drive PC1 Reserved AFS1 1 0 ANAS CINN LED ADC or Comparator Input or LED drive AFS1 1 1 Drive PC2 Reserved AFS1 2 0 ANAG LED ADC Analog Input or LED Drive AFS1 2 1 PC3 COUT Comparator Output AFS1 3 0 LED LED drive AFS1 3 1 PC4 Reserved AFS1 4 0 LED LED Drive AFS1 4 1 PC5 Reserved AFS1 5 0 LED LED Drive AFS1 5 1 PC6 Reserved AFS1 6 0 LED LED Drive AFS1 6 1 PC7 Reserved AFS1 7 0 Port C LED LED Drive AFS1 7 1 Note Because there are at most two choices of alternate function for any pin of Port C the Alternate Function Set register AFS2 is not used to select the function Also alternate function selection as described in Port A D Alternate Function Sub Registers on page 48 must also be enabled PS022820 0307 General Purpose Input Output Z8 Encore XP 8K and 4K Series Product Specification Table 15 Port Alternate Function Mapping 8 Pin Parts Zl Zi LOG Alternate Function Alternate Function Select Alternate Function Select Register Port Pin Mnemonic Description Register AFS1 Ars2 Port A PAO TOIN Timer 0 Input AFS1 0 0 AFS1 0 0 Reserved AFS1 0 0 AFS2 0 1 Reserved AFS1 0 1
18. External crystal oscillator operating up to 20 MHz Optional 8 channel 10 bit analog to digital converter ADC Optional on chip temperature sensor On chip analog comparator Optional on chip low power operational amplifier LPO Full duplex UART The UART baud rate generator BRG can be configured and used as a basic 16 bit timer Infrared Data Association IrDA compliant infrared encoder decoders integrated with UART Two enhanced 16 bit timers with capture compare and PWM capability Watchdog timer WDT with dedicated internal RC oscillator Up to 20 vectored interrupts 6 to 25 I O pins depending upon package Overview Z8 Encore XP 8K and 4K Series Product Specification Zi LOG Up to thirteen 5 V tolerant input pins Upto 8 ports capable of direct LED drive with no current limit resistor required On Chip Debugger OCD Voltage brownout protection VBO Programmable low battery detection LVD 8 pin devices only Bandgap generated precision voltage references available for the ADC comparator VBO and LVD Power on reset POR 2 7 V to 3 6 V operating voltage 8 20 and 28 pin packages 0 C to 70 C and 40 C to 105 C for operating temperature ranges Part Selection Guide Table 1 on page 3 identifies the basic features and package styles available for each device within the Z8 Encore XP 8K and 4K Series product line PS022820 0307 Overview Z8 En
19. PS022820 0307 General Purpose Input Output Z8 Encore XP 8K and 4K Series Product Specification Lla Zi LOG Table 16 GPIO Port Registers and Sub Registers Continued Port Register Mnemonic Port Register Name PxAF Alternate Function PxOC Output Control Open Drain PxHDE High Drive Enable PxSMRE Stop Mode Recovery Source Enable PxPUE Pull up Enable PxAFS1 Alternate Function Set 1 PxAFS2 Alternate Function Set 2 Port A D Address Registers The Port A D Address registers select the GPIO Port functionality accessible through the Port A D Control registers The Port A D Address and Control registers combine to pro vide access to all GPIO Port controls Table 17 Table 17 Port A D GPIO Address Registers PxADDR BITS 7 6 5 4 3 2 1 0 FIELD PADDR 7 0 RESET 00H R W R W R W R W R W R W R W R W R W ADDR FDOH FD4H FD8H FDCH PADDR 7 0 Port Address The Port Address selects one of the sub registers accessible through the Port Control reg Ister PADDR 7 0 Port Control sub register accessible using the Port A D Control Registers 00H No function Provides some protection against accidental Port reconfiguration 01H Data Direction 02H Alternate Function 03H Output Control Open Drain 04H High Drive Enable 05H Stop Mode Recovery Source Enable 06H Pull up Enable 07H Alternate Function Set 1 PS022820 0307
20. Port A Bit 7 or LVD Interrupt Request Enable Low Bit PA6CENL Port A Bit 6 or Comparator Interrupt Request Enable Low Bit PAxENL Port A Bit x Interrupt Request Enable Low Bit PS022820 0307 Interrupt Controller IRQ2 Enable High and Low Bit Registers Table 42 describes the priority control for IRQ2 The IRQ2 Enable High and Low Bit registers Table 43 and Table 44 form a priority encoded enabling for interrupts in the Interrupt Request 2 register Z8 Encore XP 8K and 4K Series Product Specification Lie Zi LOG Table 42 IRQ2 Enable and Priority Encoding IRQ2ENH x IRQ2ENL x Priority Description 0 0 Disabled Disabled 0 1 Level 1 Low 1 0 Level 2 Medium 1 1 Level 3 High where x indicates the register bits from 0 7 Table 43 IRQ2 Enable High Bit Register IRQ2ENH BITS 7 5 4 3 2 1 0 FIELD Reserved C3ENH C2bENH C1ENH COENH RESET 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W ADDR FC7H Reserved Must be 0 C3ENH Port C3 Interrupt Request Enable High Bit C2ENH Port C2 Interrupt Request Enable High Bit C1ENH Port C1 Interrupt Request Enable High Bit COENH Port CO Interrupt Request Enable High Bit Table 44 IRQ2 Enable Low Bit Register IRQ2ENL BITS 7 6 5 4 3 2 1 0 FIELD Reserved C3ENL C2ENL C1ENL COENL RESET 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W ADDR FC8H
21. Previous timer interrupt is not a result of Timer Input Capture Event 1 Previous timer interrupt is a result of Timer Input Capture Event Timer 0 1 Control Register 1 The Timer 0 1 Control TxCTL1 registers enable disable the timers set the prescaler value and determine the timer operating mode Table 49 Timer 0 1 Control Register 1 TxCTL1 BITS 7 6 5 4 3 2 1 0 FIELD TEN TPOL PRES TMODE RESET 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W ADDR FO7H FOFH PS022820 0307 TEN Timer Enable 0 Timer is disabled 1 Timer enabled to count TPOL Timer Input Output Polarity Operation of this bit is a function of the current operating mode of the timer ONE SHOT mode When the timer is disabled the Timer Output signal is set to the value of this bit When the timer is enabled the Timer Output signal is complemented upon timer Reload CONTINUOUS mode When the timer is disabled the Timer Output signal is set to the value of this bit When the timer is enabled the Timer Output signal is complemented upon timer Reload COUNTER mode If the timer is enabled the Timer Output signal is complemented after timer reload 0 Count occurs on the rising edge of the Timer Input signal 1 Count occurs on the falling edge of the Timer Input signal PWM SINGLE OUTPUT mode 0 Timer Output is forced Low 0 when the timer is disabled When enabled the Timer Output is forc
22. VBO warning signal The RESET pin is bi directional meaning it functions as reset source as well as a reset indicator PS022820 0307 Overview Z8 Encore XP 8K and 4K Series Product Specification Zi LOG Pin Description The Z8 Encore XP 8K and 4K Series products are available in a variety of packages styles and pin configurations This chapter describes the signals and available pin configu rations for each of the package styles For information regarding the physical package specifications see chapter Packaging on page 243 Available Packages The following package styles are available for each device in the Z8 Encore XP 8K and 4K Series product line SOIC 8 20 and 28 pin e PDIP 8 20 and 28 pin SSOP 20 and 28 pin QEN thisis an MLF S a QFN style package with an 8 pin SOIC footprint 8 pin In addition the Z8 Encore XP 8K and 4K Series devices are available both with and with out advanced analog capability ADC temperature sensor and op amp Devices Z8F082A Z8F042A Z8F022A and Z8F012A contain the advanced analog while devices Z8F081A Z8F041A Z8F021A and Z8F011A do not have the advanced analog capability Pin Configurations PS022820 0307 Figure 2 through Figure 4 illustrate the pin configurations for all of the packages available in the Z8 Encore XP 8K and 4K Series See Table 2 on page 11 for a description of the signals The analog input alternate functions ANAx are
23. Write Program Counter 06H Disabled Read Program Counter 07H Disabled Write Register 08H Only writes of the Flash Memory Control registers are allowed Additionally only the Mass Erase command is allowed to be written to the Flash Control register Read Register 09H Disabled Write Program Memory OAH Disabled Read Program Memory OBH Disabled PS022820 0307 On Chip Debugger Z8 Encore XP 8K and 4K Series Product Specification Zi Zi LOG Enabled when Command NOT in DEBUG Disabled by Debug Command Byte mode Flash Read Protect Option Bit Write Data Memory OCH Yes Read Data Memory ODH Read Program Memory CRC OEH Reserved OFH Step Instruction 10H Disabled Stuff Instruction 11H Disabled Execute Instruction 12H Disabled Reserved 13H FFH PS022820 0307 In the following bulleted list of OCD Commands data and commands sent from the host to the On Chip Debugger are identified by DBG lt Command Data Data sent from the On Chip Debugger back to the host is identified by DBG gt Data Read OCD Revision 00H The Read OCD Revision command determines the version of the On Chip Debugger If OCD commands are added removed or changed this revision number changes DBG 00H DBG OCDRev 15 8 Major revision number DBG OCDRev 7 0 Minor revision number Read OCD Status Register 02H The Read OCD Status Register comma
24. Z 117 Zi LOG Infrared Encoder Decoder The Z8 Encore XP 8K and 4K Series products contain a fully functional high performance UART to Infrared Encoder Decoder Endec The Infrared Endec is integrated with an on chip UART to allow easy communication between the Z8 Encore and IrDA Physical Layer Specification Version 1 3 compliant infrared transceivers Infrared communication provides secure reliable low cost point to point communication between PCs PDAs cell phones printers and other infrared enabled devices Architecture Figure 16 illustrates the architecture of the Infrared Endec System Clock Infrared Transceiver RxD RXD e et RXD TxD Infrared TXD UART m Encoder Decoder gt TXD Baud Rate Endec Clock NE Interrupt O Data Signal Address Figure 16 Infrared Data Communication System Block Diagram Operation When the Infrared Endec is enabled the transmit data from the associated on chip UART is encoded as digital signals in accordance with the IrDA standard and output to the infrared transceiver through the TXD pin Likewise data received from the infrared transceiver is passed to the Infrared Endec through the RXD pin decoded by the Infrared PS022820 0307 Infrared Encoder Decoder Z8 Encore XP 8K and 4K Series Product Specification Zi LOG Endec and passed to the UART Communication is half duplex which means simultaneous dat
25. od 102 receiving data using the polled method 101 transmitting data usin the interrupt driven method 100 transmitting data using the polled method 99 x baud rate high and low registers 114 x control 0 and control 1 registers 108 x status 0 and status 1 registers 111 112 UxBRH register 114 UxBRL register 114 UxCTLO register 108 114 UxCTL1 register 109 UxRXD register 113 UxSTATO register 111 UxSTAT1 register 112 UxTXD register 113 V vector 203 voltage brown out reset VBR 26 W watch dog timer approximate time out delay 92 approximate time out delays 135 CNTL 26 control register 94 136 190 electrical characteristics and timing 232 235 Index interrupt in normal operation 92 interrupt in stop mode 93 operation 135 refresh 92 207 reload unlock sequence 93 reload upper high and low registers 95 reset 27 reset in normal operation 93 reset in Stop mode 93 time out response 92 WDTCTL register 31 94 136 190 WDTH register 95 WDTL register 96 working register 203 working register pair 203 WTDU register 95 X X 203 XOR 208 XORX 208 Z Z8 Encore block diagram 4 features 1 part selection guide 2 PS022820 0307 Z8 Encore XP 8K and 4K Series Product Specification Zi Zi LOG Index Z8 Encore XP 8K and 4K Series Product Specification AR ZiLOG PS022820 0307 Index Z8 Encore XP 8K and 4K Series Product Specification Za Zi LOG Customer Support For answers to t
26. oue eee cee seven va iE wo ed rp ee wees 6 External Crystal Oscillator 6 Low Voltage Detector 6 On Chip Debugger 5 9 3 2 272 201 das RS Bede peewee xr ar mie e es 6 Universal Asynchronous Receiver Transmitter 7 ul rer 7 General Purpose I O 7 Direct LED Drive 00 000 ccc aa 7 Flash Controller 7 Non Volatile Data Storage 7 Interrupt Controller 8 Reset Controller 8 Pin Description AA KA ERROR NUNCA A CAU ROULEAU kaa 9 Available Packages uode vt eges pet e tea P ee Ce ee vee ees 9 Pin Configurations p sedea sd ura i appaia aes re oe Haale ac T doe dta Ad 9 Signal Descriptions 11 Pin Characteristics lll 13 Address Space enim Ge IAA 15 Register FIG uua ee u qb RE ACRI p EEN e RU A ob Maca d NR OE E ead 15 ProgramMemory 15 Data MEM wi ai aaa 17 Flash Information Area 17 Register Map a aeaaradecad 3 Ve OR ed er ea eon OU CO E d Wa c 19 PS022820 0307 Table of Contents PS022820 0307 Z8 Encore XP 8K and 4K Series Product Specification ZiLOG Reset
27. ADC Calibration Data Table 93 ADC Calibration Bits BITS 7 6 5 4 3 2 1 0 FIELD ADC_CAL RESET U U U U U U U U R W R W R W R W R W R W R W R W R W ADDR Information Page Memory 0060H 007DH Note U Unchanged by Reset R W Read Write ADC_CAL Analog to Digital Converter Calibration Values Contains factory calibrated values for ADC gain and offset compensation Each of the ten supported modes has one byte of offset calibration and two bytes of gain calibration These values are read by user software to compensate ADC measurements as detailed in Software Compensation Procedure Using Factory Calibration Data on page 126 The loca tion of each calibration byte is provided in Table 94 on page 162 PS022820 0307 Flash Option Bits 161 Z8 Encore XP 8K and 4K Series Table 94 ADC Calibration Data Location Product Specification Z Zi LOG Info Page Memory Compensation Reference Address Address Usage ADC Mode Type 60 FE60 Offset Single Ended Unbuffered Internal 2 0 V 08 FE08 Gain High Byte Single Ended Unbuffered Internal 2 0 V 09 FE09 Gain Low Byte Single Ended Unbuffered Internal 2 0 V 63 FE63 Offset Single Ended Unbuffered Internal 1 0 V 0A FEOA Gain High Byte Single Ended Unbuffered Internal 1 0 V OB FEOB Gain Low Byte Single Ended Unbuffered Internal 1 0 V 66 FE66 Offset Single Ended Unbuffered External 2 0 V 0C FEOC Gain High Byte Sing
28. DE signal is Active High 1 DE signal is Active Low BRGCTL Baud Rate Control This bit causes an alternate UART behavior depending on the value of the REN bit in the UART Control 0 Register When the UART receiver is not enabled REN 0 this bit determines whether the Baud Rate Generator issues interrupts 0 Reads from the Baud Rate High and Low Byte registers return the BRG Reload Value 1 The Baud Rate Generator generates a receive interrupt when it counts down to 0 Reads from the Baud Rate High and Low Byte registers return the current BRG count value When the UART receiver is enabled REN 1 this bit allows reads from the Baud Rate Registers to return the BRG count value instead of the Reload Value 0 Reads from the Baud Rate High and Low Byte registers return the BRG Reload Value 1 Reads from the Baud Rate High and Low Byte registers return the current BRG count value Unlike the Timers there is no mechanism to latch the Low Byte when the High Byte is read RDAIRQ Receive Data Interrupt Enable 0 Received data and receiver errors generates an interrupt request to the Interrupt Con troller Universal Asynchronous Receiver Transmitter Z8 Encore XP 8K and 4K Series Product Specification Zi LOG 1 Received data does not generate an interrupt request to the Interrupt Controller Only receiver errors generate an interrupt request IREN Infrared Encoder Decoder Enable 0 Infrared Encoder Decoder is dis
29. General Purpose Input Output Z8 Encore XP 8K and 4K Series Product Specification ZI Zi LOG 08H PADDR 7 0 Port Control sub register accessible using the Port A D Control Registers Alternate Function Set 2 09H FFH No function Port A D Control Registers The Port A D Control registers set the GPIO port operation The value in the correspond ing Port A D Address register determines which sub register is read from or written to by a Port A D Control register transaction Table 18 Table 18 Port A D Control Registers PxCTL BITS 7 6 5 4 3 2 1 0 FIELD PCTL RESET 00H R W R W R W R W R W R W R W R W R W ADDR FD1H FD5H FD9H FDDH PCTL 7 0 Port Control The Port Control register provides access to all sub registers that configure the GPIO Port operation Port A D Data Direction Sub Registers The Port A D Data Direction sub register is accessed through the Port A D Control register by writing 01H to the Port A D Address register Table 19 Table 19 Port A D Data Direction Sub Registers PxDD BITS 7 6 5 4 3 2 1 0 FIELD DD7 DD6 DD5 DD4 DD3 DD2 DD1 DDO RESET 1 1 1 1 1 1 1 1 R W R W R W R W R W R W R W R W R W ADDR If 01H in Port A D Address Register accessible through the Port A D Control Register DD 7 0 Data Direction These bits control the direction of the associated port pin
30. Register File Address Map Continued Address Hex Register Description Mnemonic Reset Hex Page No FOB Timer 1 Reload Low Byte T1IRL FF 88 FOC Timer 1 PWM High Byte T1PWMH 00 88 FOD Timer 1 PWM Low Byte T1PWML 00 89 FOE Timer 1 Control 0 T1CTLO 00 83 FOF Timer 1 Control 1 T1CTL1 00 84 F10 F6F Reserved XX UART F40 UART Transmit Receive Data Registers TXD RXD XX 113 F41 UART Status 0 Register UOSTATO 00 111 F42 UART Control 0 Register UOCTLO 00 108 F43 UART Control 1 Register UOCTL1 00 108 F44 UART Status 1 Register UOSTAT1 00 112 F45 UART Address Compare Register UOADDR 00 113 F46 UART Baud Rate High Byte Register UOBRH FF 114 F47 UART Baud Rate Low Byte Register UOBRL FF 114 Analog to Digital Converter ADC F70 ADC Control 0 ADCCTLO 00 130 F71 ADC Control 1 ADCCTL1 80 130 F72 ADC Data High Byte ADCD_H XX 133 F73 ADC Data Low Bits ADCD_L XX 133 F74 F7F Reserved XX Low Power Control F80 Power Control 0 PWRCTLO 80 35 F81 Reserved XX LED Controller F82 LED Drive Enable LEDEN 00 53 F83 LED Drive Level High Byte LEDLVLH 00 53 F84 LED Drive Level Low Byte LEDLVLL 00 54 F85 Reserved XX Oscillator Control F86 Oscillator Control OSCCTL AO 190 F87 F8F Reserved XX Comparator 0 F90 Comparator 0 Control CMPO 14 136 XX Undefined PS022820 0307 Register Map Table 7 Register File Address Map Continued
31. Stop Mode Recovery and Low Voltage Detection 23 Reset ypes Mc 23 Reset SOUIDBS uoces anin dea a da da dod Arbo a aa a e Go di dat ug 25 Power On Reset 25 Voltage Brownout Reset 26 Watchdog Timer Reset ww essa a d aea o aede b d bu E ayes 27 External Reset Input 27 External Reset Indicator 28 On Chip Debugger Initiated Reset 28 Stop Mode Recovery 28 Stop Mode Recovery Using Watchdog Timer Time Out 29 Stop Mode Recovery Using a GPIO Port Pin Transition 29 Stop Mode Recovery Using the External RESET Pin 30 Low Voltage Detection 30 Reset Register Definitions 30 Low PowerModes annunnann 33 SLOP MOUS AAA AAA AAA wes e AAA UE 33 HALI MOUSE wi Ai IA AA 34 Peripheral Level Power Control 34 Power Control Register Definitions 34 General Purpose Input Output 37 GPIO Port Availability By Device 37 Architecture 38 GPIO Alternate Functions
32. VO l N A Yes Programmable Yes Yes PA 7 2 Pull up Programmable unless pullups enabled PB 7 0 VO l N A Yes Programmable Yes Yes PB 7 6 Pull up Programmable unless pullups enabled PS022820 0307 Pin Description Z8 Encore XP 8K and 4K Series Table 3 Pin Characteristics 20 and 28 pin Devices Product Specification Lla Zi LOG Active Low or Internal Pull Schmitt Symbol Reset Active Tristate up Trigger Open Drain 5V Mnemonic Direction Direction High Output orPull down Input Output Tolerance PC 7 0 y o l N A Yes Programmable Yes Yes PC 7 3 Pull up Programmable unless pullups enabled RESET PDO VO I O defaults Low in Yes PDO programmable Yes programmable Yes unless to RESET Reset only for PDO always for PDO always pullups mode on for RESET on for RESET enabled VDD N A N A N A N A N A N A VSS N A N A N A N A N A N A gt Note X PB6 and PB7 are available only in those devices without ADC Table 4 Pin Characteristics 8 Pin Devices Active Low or Internal Pull Schmitt Symbol Reset Active Tristate up Trigger Open Drain 5V Mnemonic Direction Direction High Output or Pull down Input Output Tolerance PAO DBG I O but can N A Yes Programmable Yes Yes Yes unless change Pull up Programmable pull ups during reset enabled if key sequence detected PA1 I O l N A Yes Programmable Yes Yes Yes unless Pull up Programmable pull ups enabled RESET PA2 VO I O
33. WDT Reload Low Least significant byte LSB Bits 7 0 of the 24 bit WDT reload value PS022820 0307 Watchdog Timer Z8 Encore XP 8K and 4K Series Product Specification ZI Zi LOG Universal Asynchronous Receiver Transmitter The universal asynchronous receiver transmitter UART is a full duplez communication channel capable of handling asynchronous data transfers The UART uses a single 8 bit data mode with selectable parity Features of the UART include 8 bit asynchronous data transfer Selectable even and odd parity generation and checking Option of one or two STOP bits Separate transmit and receive interrupts Framing parity overrun and break detection Separate transmit and receive enables 16 bit baud rate generator BRG Selectable MULTIPROCESSOR 9 bit mode with three configurable interrupt schemes Baud rate generator BRG can be configured and used as a basic 16 bit timer Driver enable DE output for external bus transceivers Architecture The UART consists of three primary functional blocks transmitter receiver and baud rate generator The UART s transmitter and receiver function independently but employ the same baud rate and data format Figure 10 on page 98 illustrates the UART architecture PS022820 0307 Universal Asynchronous Receiver Transmitter Z8 Encore XP 8K and 4K Series Product Specification Parity Checker
34. Z8F041AHH Z8F041ASH Z8F021APH Z8F021AHH Z8F021ASH Z8F011APH Z8F011AHH Z8F011ASH Z8F082APJ Z8F082ASJ Z8F082AHJ 28 pin Yes 7 0 5 0 7 0 0 23 Z8F042APJ Z8F042ASJ Z8F042AHJ Z8F022APJ Z8F022ASJ Z8F022AHJ Z8F012APJ Z8F012ASJ Z8F012AHJ Z8F081APJ Z8F081ASJ ZaOF081AHJ 28 pn No 70 70 7 0 0 25 Z8F041APJ Z8F041ASJ Z8F041AHJ Z8F021APJ Z8F021ASJ Z8F021AHJ Z8F011APJ Z8F011ASJ Z8F011AHJ PS022820 0307 General Purpose Input Output Z8 Encore XP 8K and 4K Series Product Specification ZI Zi LOG Architecture Figure 7 illustrates a simplified block diagram of a GPIO port pin In this figure the ability to accommodate alternate functions and variable port current drive strength is not illustrated Port Input Schmitt Trigger Data Register lt lt System Clock VDD Port Output Control Port Output Data Register o DATA Bs ID Q Q Port Pin System Clock ep gt Port Data Direction zle GND Figure 7 GPIO Port Pin Block Diagram GPIO Alternate Functions Many of the GPIO port pins can be used for general purpose I O and access to on chip peripheral functions such as the timers and serial communication devices The Port A D Alternate Function sub registers configure these pins for either General Purpose I O or alternate function operation When a pin
35. count are as follows 1 Write to the Timer Control register to Disable the timer Configure the timer for CAPTURE COMPARE mode Set the prescale value Set the Capture edge rising or falling for the Timer Input 2 Write to the Timer High and Low Byte registers to set the starting count value typically 0001H 3 Wirite to the Timer Reload High and Low Byte registers to set the Compare value Timers 81 Z8 Encore XP 8K and 4K Series Product Specification 82 Zi LOG 4 Enable the timer interrupt if appropriate and set the timer interrupt priority by writing to the relevant interrupt registers By default the timer interrupt are generated for both input capture and reload events If appropriate configure the timer interrupt to be generated only at the input capture event or the reload event by setting TICONFIG field of the TxCTLO register 5 Configure the associated GPIO port pin for the Timer Input alternate function 6 Write to the Timer Control register to enable the timer 7 Counting begins on the first appropriate transition of the Timer Input signal No interrupt is generated by this first edge In CAPTURE COMPARE mode the elapsed time from timer start to Capture event can be calculated using the following equation _ Capture Value Start Value x Prescale Mre Elapsed mime 8 System Clock Frequency Hz Reading the Timer Count Values The current count value in the timers can be read while c
36. rA ee ae a el D Program Voltage Program Execution Brownout Execution wa gt System Clock l Internal RESET signal POR Note Not to Scale l l counter delay l Figure 6 Voltage Brownout Reset Operation The POR level is greater than the VBO level by the specified hysteresis value This ensures that the device undergoes a Power on reset after recovering from a VBO condition Watchdog Timer Reset If the device is in NORMAL or HALT mode the Watchdog Timer can initiate a System Reset at time out if the WDT_RES Flash Option Bit is programmed to 1 This is the unprogrammed state of the WDT RES Flash Option Bit If the bit is programmed to 0 it configures the Watchdog Timer to cause an interrupt not a System Reset at time out The WDT bit in the Reset Status RSTSTAT register 1s set to signify that the reset was initiated by the Watchdog Timer External Reset Input The RESET pin has a Schmitt triggered input and an internal pull up resistor Once the RESET pin is asserted for a minimum of four system clock cycles the device progresses through the System Reset sequence Because of the possible asynchronicity of the system clock and reset signals the required reset duration may be as short as three clock periods PS022820 0307 Reset Stop Mode Recovery and Low Voltage Detection Z8 Encore XP 8K and 4K Series Product Specification Zi LOG and as long as four A re
37. 0 0 0 0 R W R W R W R W R W R W R W R W R W ADDR F83H PS022820 0307 LEDLVLH 7 0 LED Level High Bit LEDLVLH LEDLVLL select one of four programmable current drive levels for each Port C pin 00 23 mA 01 7 mA 107 13 mA 11 20 mA General Purpose Input Output LED Drive Level Low Register Z8 Encore XP 8K and 4K Series Product Specification AP Zi LOG The LED Drive Level registers contain two control bits for each Port C pin Table 31 These two bits select between four programmable drive levels Each pin is individually programmable Table 31 LED Drive Level Low Register LEDLVLL BITS 7 6 5 4 3 2 1 0 FIELD LEDLVLL 7 0 RESET 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W ADDR F84H LEDLVLL 7 0 LED Level Low Bit LEDLVLH LEDLVLL select one of four programmable current drive levels for each Port C pin 00 3 mA 01 7mA 10 13mA 11 2 20 mA PS022820 0307 General Purpose Input Output Z8 Encore XP 8K and 4K Series Product Specification 55 Zi LOG Interrupt Controller The interrupt controller on the Z8 Encore XP 8K and 4K Series products prioritizes the interrupt requests from the on chip peripherals and the GPIO port pins The features of the interrupt controller include the following 20 possible interrupt sources with 18 unique interrupt vectors 12 GPIO port pin interrupt sources two inter
38. 0 Veit Output T2 end of stop bit s Figure 37 UART Timing With CTS Table 142 UART Timing With CTS Delay ns Parameter Abbreviation Minimum Maximum UART T4 CTS Fall to DE output delay 2 XIN 2 XIN period period 1 bit time To DE assertion to TXD falling edge start bit delay 5 T3 End of Stop Bit s to DE deassertion delay 5 PS022820 0307 Electrical Characteristics Z8 Encore XP 8K and 4K Series Product Specification 241 Zi LOG Figure 38 and Table 143 provide timing information for UART pins for the case where CTS is not used for flow control DE asserts after the transmit data register has been written DE remains asserted for multiple characters as long as the transmit data register is written with the nezt character before the current character has completed T2 Output o rs start J we bit 1 y str pariy stop utpu T1 end of stop bit s Figure 38 UART Timing Without CTS Table 143 UART Timing Without CTS Delay ns Parameter Abbreviation Minimum Maximum UART T4 DE assertion to TXD falling edge start bit delay 1 XIN 1 bit time period To End of Stop Bit s to DE deassertion delay Tx 5 data register is empty PS022820 0307 Electrical Characteristics Z8 Encore XP 8K and 4K Series Product Specification Z 242 Zi LOG PS022820 0307 Electrical Characteristics Z8 Encore
39. 0000 0 0 V 0001 0 2 V 0010 0 4 V 0011 70 6 V 0100 2 0 8 V 0101 1 0 V Default 0110 212 V 0111 2 14V Comparator Z8 Encore XP 8K and 4K Series Product Specification Z4 Zi LOG 1000 1 6 V 1001 1 8 V 1010 1111 Reserved For 8 pin devices 000000 0 00 V 000001 0 05 V 000010 0 10 V 000011 0 15 V 000100 0 20 V 000101 0 25 V 000110 0 30 V 000111 0 35 V 001000 0 40 V 001001 0 45 V 001010 0 50 V 001011 20 55 V 001100 0 60 V 001101 0 65 V 001110 0 70 V 001111 20 75 V 010000 0 80 V 010001 0 85 V 010010 0 90 V 010011 20 95 V 010100 1 00 V Default 010101 1 05 V 010110 1 10 V 010111 1 15 V 011000 1 20 V 011001 2 125 V 011010 1 30 V 011011 1 35 V 011100 1 40 V 011101 1 45 V 011110 1 50 V 011111 2 1 55 V 100000 1 60 V 100001 1 65 V 100010 1 70 V 100011 1 75 V 100100 1 80 V PS022820 0307 Comparator Z8 Encore XP 8K and 4K Series Product Specification 4 Zi LOG PS022820 0307 Comparator Z8 Encore XP 8K and 4K Series Product Specification 139 Zi LOG Temperature Sensor The on chip Temperature Sensor allows you to measure temperature on the die with either the on board ADC or on board comparator This block is factory calibrated for in circuit software correction Uncalibrated accuracy is significantly worse therefore the tempera ture sensor is not recommended for uncalibrated use Temperature Sensor Operati
40. 107 Zi LOG Receiver Ready Receiver Interrupt Read Status No Errors Yes Read Data which clears RDA bit and resets error bits Read Data Discard Data Figure 15 UART Receiver Interrupt Service Routine Flow Baud Rate Generator Interrupts If the baud rate generator BRG interrupt enable is set the UART Receiver interrupt asserts when the UART Baud Rate Generator reloads This condition allows the Baud Rate Generator to function as an additional counter if the UART functionality 1s not employed UART Baud Rate Generator The UART Baud Rate Generator creates a lower frequency baud rate clock for data transmission The input to the Baud Rate Generator is the system clock The UART Baud Rate High and Low Byte registers combine to create a 16 bit baud rate divisor value PS022820 0307 Universal Asynchronous Receiver Transmitter Z8 Encore XP 8K and 4K Series Product Specification Zi LOG BRG 15 0 that sets the data transmission rate baud rate of the UART The UART data rate is calculated using the following equation UART Data Rate bites 1em Ciock Frequency Me 16 x UART Baud Rate Divisor Value When the UART is disabled the Baud Rate Generator functions as a basic 16 bit timer with interrupt on time out To configure the Baud Rate Generator as a timer with interrupt on time out complete the following procedure 1 Disable the UART by clearing the REN and T
41. 125 135 a 142 165 056 065 S 152 165 060 065 E CONTROLLING DIMENSIONS INCH P a f m rv LLL d ar aaa OE Mu L al EL ea ____ S e B r Bi PS022820 0307 Figure 42 20 Pin Plastic Dual Inline Package PDIP Packaging Z8 Encore XP 8K and 4K Series Product Specification Z 247 ZiLOG Figure 43 illustrates the 20 pin Small Outline Integrated Circuit Package SOIC available for the Z8 Encore XP 8K and 4K Series devices j D c MILLIMETER INCH SYMBOL 20 11 MIN MAX MIN MAX ae ji A 2 40 2 65 094 104 M 0 10 0 30 004 012 A2 224 244 088 096 B 0 36 0 46 014 018 i 3 C 0 23 0 30 009 012 H E D 12 60 12 95 496 510 wo p E 740 7 60 291 299 O t LH G 1 27 BSC 050 BSC 7 H 10 00 10 65 394 419 h 0 30 0 40 012 016 0 60 ORO 1 10 L 1 00 024 039 P1 IDENTIFIER Q1 0 97 1 07 038 042 DETAIL A I 2 a f A2 F A CONTROLLING DIMENSIONS MM E LEADS ARE COPLANAR WITHIN 004 INCH L At Jy SEATING PLANE EE d E 0 8 DETAIL A Figure 43 20 Pin Small Outline Integrated Circuit Package SOIC PS022820 0307 Packaging Z8 Encore XP 8K and 4K Series Product Specification Z 248 Zi LOG Figure 44 illustrates t
42. 16 bit Reload value stored in the Timer Reload High and Low Byte registers The timer input is the system clock When reaching the Reload value the timer generates an interrupt the count value in the Timer High and Low Byte registers is reset to 0001H and counting resumes assuming the Timer Input signal remains asserted Also if the Timer Output alternate function 1s enabled the Timer Output pin changes state from Low to High or from High to Low at timer reset The steps for configuring a timer for GATED mode and initiating the count are as follows 1 Write to the Timer Control register to Disable the timer Configure the timer for GATED mode Set the prescale value PS022820 0307 Timers PS022820 0307 Z8 Encore XP 8K and 4K Series Product Specification Zi LOG 2 Write to the Timer High and Low Byte registers to set the starting count value Writing these registers only affects the first pass in GATED mode After the first timer reset in GATED mode counting always begins at the reset value of 0001H 3 Wirite to the Timer Reload High and Low Byte registers to set the Reload value 4 Enable the timer interrupt if appropriate and set the timer interrupt priority by writing to the relevant interrupt registers By default the timer interrupt is generated for both input deassertion and reload events If appropriate configure the timer interrupt to be generated only at the input deassertion event or the reload event b
43. 19 2 0 1 1 0 SSOP 28 pin package Z8F041APJO20SC 4KB 1KB 128B 25 19 2 0 1 1 0 PDIP 28 pin package Extended Temperature 40 C to 105 C Z8F041APBO20EC 4KB 1KB 128B 6 13 2 0 31 1 0 PDIP 8 pin package Z8F041AQBO20EC 4KB 1KB 128B 6 13 2 0 1 1 0 QFN 8 pin package Z8F041ASBO20EC 4KB 1KB 128B 6 13 2 0 1 1 0 SOIC 8 pin package Z8F041ASHO20EC 4KB 1KB 128B 17 19 2 0 1 1 0 SOIC 20 pin package Z8F041AHHO20EC 4KB 1KB 128B 17 19 2 0 1 1 0 SSOP 20 pin package Z8F041APHO20EC 4KB 1KB 128B 17 19 2 0 1 1 0 PDIP 20 pin package Z8F041ASJO20EC 4KB 1KB 128B 25 19 2 0 1 1 0 SOIC 28 pin package Z8F041AHJO20EC 4KB 1KB 128B 25 19 2 0 1 1 0 SSOP 28 pin package Z8F041APJO20EC 4KB 1KB 128B 25 19 2 0 1 1 0 PDIP 28 pin package Replace C with G for Lead Free Packaging PS022820 0307 Ordering Information Z8 Encore XP 8K and 4K Series Product Specification Zi Zi LOG Part Number Flash amp NVDS 1 0 Lines Interrupts 16 Bit Timers w PWM 10 Bit A D Channels UART with IrDA Comparator Temperature Sensor Description Z8 Encore XP 8K and 4K Series with 2 KB Flash 10 Bit analog to Digital Converter Standard Temperature 0 C to 70 C Z8F022APB020SC 2KB 512B 64B 6 14 2 4 1 1 1 PDIP 8 pin package Z8F022AQB020SC 2KB 512B 64B 6 14 2 4 1 1 1 QFN 8 pin package Z8F022ASB020SC 2KB 512B 64B 6 14 2 4 1 1 1 SOIC 8 pin package Z8F022ASH020SC 2KB 512B 64B 17 20 2 7 1 1 1 SOIC 20 pin
44. 250 0 1 345 6 38 24 115 2 5 125 0 8 51 115 2 3 115 2 0 00 57 6 11 56 8 1 36 57 6 6 57 6 0 00 38 4 16 39 1 1 73 38 4 9 38 4 0 00 19 2 33 18 9 0 16 19 2 18 19 2 0 00 9 60 65 9 62 0 16 9 60 36 9 60 0 00 4 80 130 4 81 0 16 4 80 72 4 80 0 00 2 40 260 2 40 0 03 2 40 144 2 40 0 00 1 20 521 1 20 0 03 1 20 288 1 20 0 00 0 60 1042 0 60 0 03 0 60 576 0 60 0 00 0 30 2083 0 30 0 2 0 30 1152 0 30 0 00 PS022820 0307 Universal Asynchronous Receiver Transmitter Table 70 UART Baud Rates Continued Z8 Encore XP 8K and 4K Series Product Specification Li n Zi LOG 3 579545 MHz System Clock 1 8432 MHz System Clock Acceptable BRGDivisor Actual Rate Error Acceptable BRGDivisor Actual Rate Error Rate kHz Decimal kHz Rate kHz Decimal kHz 1250 0 N A N A N A 1250 0 N A N A N A 625 0 N A N A N A 625 0 N A N A N A 250 0 1 223 72 10 51 250 0 N A N A N A 115 2 111 9 2 90 115 2 1 115 2 0 00 57 6 4 55 9 2 90 57 6 2 57 6 0 00 38 4 37 3 2 90 38 4 3 38 4 0 00 19 2 12 18 6 2 90 19 2 19 2 0 00 9 60 23 9 73 1 32 9 60 12 9 60 0 00 4 80 47 4 76 0 83 4 80 24 4 80 0 00 2 40 93 2 41 0 23 2 40 48 2 40 0 00 1 20 186 1 20 0 23 1 20 96 1 20 0 00 0 60 373 0 60 0 04 0 60 192 0 60 0 00 0 30 746 0 30 0 04 0 30 384 0 30 0 00 PS022820 0307 Universal Asynchronous Receiver Transmitter Z8 Encore XP 8K and 4K Series Product Specification
45. 86 3 4 IR IRR 87 3 5 r X rr 88 3 4 X rr r 89 3 4 ER r 94 3 2 ER Ir 95 3 3 IRR R 96 3 4 IRR IR 97 3 5 ER ER E8 4 2 ER IM E9 4 2 LEA dst X src dst lt src X r X r 98 3 3 rr X rr 99 3 5 MULT dst dst 15 0 RR F4 2 8 dst 15 8 dst 7 0 NOP No operation OF ee es ee ut 1 2 Flags Notation z Value is a function of the result of the operation 0 Reset to 0 Unaffected 1 Set to 1 X Undefined PS022820 0307 eZ8 CPU Instruction Set Z8 Encore XP 8K and 4K Series Product Specification Z4 ziLoc Table 124 eZ8 CPU Instruction Summary Continued Assembly Symbolic Adress Mode Opcode s Fags Fetch Instr Mnemonic Operation dst src Hex C Z S V D H Cycles Cycles OR dst src dst lt dst OR src r r 42 0 2 3 r Ir 43 2 4 R R 44 3 3 R IR 45 3 4 R IM 46 3 3 IR IM 47 3 4 ORX dst src dst dst OR src ER ER 48 Q 4 3 ER IM 49 4 3 POP dst dst lt SP R 50 2 2 SP lt SP 1 IR 51 2 3 POPX dst dst SP ER D8 3 2 SP lt SP 1 PUSH src SP SP 1 R 70 2 2 SP lt src IR 71 tu a 3 IM IF70 3 2 PUSHX src SP SP 1 ER C8 3 2 SP lt src RCF C lt 0 CF D ne SS 2 eS 1 2 RET PC SP AF 1 4 SP SP 2 RL dst R 90 2 2 De OS iR zm NC COE a dst RLC dst R 10 eR 2 2 E PPP P Ppp P lt 7 T gt dst Flags Notat
46. 8KB 1KB 0 17 19 2 0 1 1 0 SOIC 20 pin package Z8F081AHHO20EC 8KB 1KB 0 17 19 2 0 1 1 0 SSOP 20 pin package Z8F081APHO20EC 8KB 1KB 0 17 19 2 0 1 1 0 PDIP 20 pin package Z8F081ASJO20EC 8KB 1KB 0 25 19 2 0 1 1 0 SOIC 28 pin package Z8F081AHJO20EC 8KB 1KB 0 25 19 2 0 1 1 0 SSOP 28 pin package Z8F081APJO20EC 8KB 1KB 0 25 19 2 0 1 1 0 PDIP 28 pin package Replace C with G for Lead Free Packaging PS022820 0307 Ordering Information Z8 Encore XP 8K and 4K Series Product Specification Zi Zi LOG Part Number Flash amp NVDS 1 0 Lines Interrupts 16 Bit Timers w PWM 10 Bit A D Channels UART with IrDA Comparator Temperature Sensor Description Z8 Encore XP 8K and 4K Series with 4 KB Flash 10 Bit Analog to Digital Converter Standard Temperature 0 C to 70 C Z8F042APB020SC 4KB 1KB 128B 6 14 2 4 31 1 1 PDIP 8 pin package Z8F042AQB020SC 4KB 1KB 128B 6 14 2 4 1 1 31 QFN 8 pin package Z8F042ASB020SC 4KB 1KB 128B 6 14 2 4 31 1 1 SOIC 8 pin package Z8F042ASH020SC 4KB 1KB 128B 17 20 2 7 1 1 1 SOIC 20 pin package Z8F042AHHO20SC 4KB 1KB 128B 17 20 2 7 1 1 1 SSOP 20 pin package Z8F042APH020SC 4KB 1KB 128B 17 20 2 7 1 1 31 PDIP 20 pin package Z8F042ASJ020SC 4KB 1KB 128B 23 20 2 8 31 1 1 SOIC 28 pin package Z8F042AHJ020SC 4KB 1KB 128B 23 20 2 8 1 1 1 SSOP 28 pin package Z8F042APJ020SC 4KB 1KB 128B 23 20 2 8 1 1 31 PDIP 28 pin package Extended Temperature 4
47. ADDR If 07H in Port A D Address Register accessible through the Port A D Control Register gt Note PAFS1 7 0 Port Alternate Function Set 1 0 Port Alternate Function selected as defined in Table 14 and Table 15 in GPIO Alter nate Functions section 1 Port Alternate Function selected as defined in Table 14 and Table 15 in GPIO Alter nate Functions section Port A D Alternate Function Set 2 Sub Registers The Port A D Alternate Function Set 2 sub register Table 26 is accessed through the Port A D Control register by writing 08H to the Port A D Address register The Alternate Function Set 2 sub registers selects the alternate function available at a port pin Alternate Functions selected by setting or clearing bits of this register is defined in Table 15 in sec tion GPIO Alternate Functions on page 38 Alternate function selection on port pins must also be enabled as described in Port A D Alternate Function Sub Registers on page 48 Table 26 Port A D Alternate Function Set 2 Sub Registers PxAFS2 BITS 7 6 5 4 3 2 1 0 FIELD PAFS27 PAFS26 PAFS25 PAFS24 PAFS23 PAFS22 PAFS21 PAFS20 RESET OOH all ports of 20 28 pin devices 04H Port A of 8 pin device R W R W R W R W R W R W R W R W R W ADDR If O8H in Port A D Address Register accessible through the Port A D Control Register PS022820 0307 PAFS2 7 0 Port Alternate Function Set 2 0 Port Alternat
48. AFS2 0 0 TOOUT Timer 0 Output Complement AFS1 0 1 AFS2 0 1 PA1 TOOUT Timer 0 Output AFS1 1 0 AFS2 1 0 Reserved AFS1 1 0 AFS2 1 1 CLKIN External Clock Input AFS1 1 1 AFS2 1 0 Analog Functions ADC Analog Input VREF AFS1 1 1 AFS2 1 1 PA2 DEO UART 0 Driver Enable AFS1 2 0 AFS2 2 0 RESET External Reset AFS1 2 0 AFS2 2 1 T1OUT Timer 1 Output AFS1 2 1 AFS2 2 0 Reserved AFS1 2 1 AFS2 2 1 PA3 CTSO UART 0 Clear to Send AFS1 3 0 AFS2 3 0 COUT Comparator Output AFS1 3 0 AFS2 3 1 TAIN Timer 1 Input AFS1 3 1 AFS2 3 0 Analog Functions ADC Analog Input LPO Input AFS1 S3 1 AFS2 3 1 P PA4 RXDO UART 0 Receive Data AFS1 4 0 AFS2 4 0 Reserved AFS1 4 0 AFS2 4 1 Reserved AFS1 4 1 AFS2 4 0 Analog Functions ADC Comparator Input N LPO AFS1 4 1 AFS2 4 1 Input N PA5 TXDO UART 0 Transmit Data AFS1 5 0 AFS2 5 0 T1OUT Timer 1 Output Complement AFS1 5 0 AFS2 5 1 Analog Functions include ADC inputs ADC reference comparator inputs and LPO ports Note Also alternate function selection as described in Port A D Alternate Function Sub Registers on page 48 must be enabled PS022820 0307 General Purpose Input Output Z8 Encore XP 8K and 4K Series Product Specification Lia Zi LOG Table 15 Port Alternate Function Mapping 8 Pin Parts Continued Alternate Function Alternate Select Alternate Function Function Select Register Port Pin Mnemonic
49. Byte Programming Page Erase and Mass Erase of Flash memory The Flash Controller contains several protection mechanisms to prevent accidental pro gramming or erasure These mechanism operate on the page sector and full memory lev els The Flow Chart in Figure 22 illustrates basic Flash Controller operation The following subsections provide details about the various operations Lock Unlock Byte Program ming Page Protect Page Unprotect Page Select Page Erase and Mass Erase listed in Figure 22 Flash Memory Z8 Encore XP 8K and 4K Series Product Specification 144 Zi LOG Reset Y m gt Lock State 0 Write Page Select Register Writes to Page Select Register in Lock State 1 result in a return to Write FCTL Lock State 0 Write Page Select Register Page Select values match ge in Protected Sector Y Byte Program Write FCTL Page Unlocked I Program Erase Enabled Figure 22 Flash Controller Operation Flow Chart PS022820 0307 Flash Memory Z8 Encore XP 8K and 4K Series Product Specification Z 145 Zi LOG Flash Operation Timing Using the Flash Freguency Registers Before performing either a program or erase operation on Flash memory you must first configure the Flash Freguency High and Low Byte registers The Flash Freguency registers allow programming and erasing
50. Control register determines if the Capture occurs on a rising edge or a falling edge of the Timer Input signal When the Capture event occurs an interrupt is generated and the timer continues counting The INPCAP bit in TxCTLO register is set to indicate the timer interrupt is because of an input capture event The timer continues counting up to the 16 bit Reload value stored in the Timer Reload High and Low Byte registers Upon reaching the Reload value the timer generates an interrupt and continues counting The INPCAP bit in TxCTLO register clears indicating the timer interrupt is not because of an input capture event Timers PS022820 0307 Z8 Encore XP 8K and 4K Series Product Specification VAR ZiLOG The steps for configuring a timer for CAPTURE mode and initiating the count are as fol lows 1 Write to the Timer Control register to Disable the timer Configure the timer for CAPTURE mode Set the prescale value Set the Capture edge rising or falling for the Timer Input 2 Write to the Timer High and Low Byte registers to set the starting count value typically 0001H 3 Write to the Timer Reload High and Low Byte registers to set the Reload value 4 Clear the Timer PWM High and Low Byte registers to 0000H Clearing these registers allows user software to determine 1f interrupts were generated by either a capture event or a reload If the PWM High and Low Byte registers still contain 0000H after the inter
51. DEPOL BRGCTL RDAIRQ IREN RESET 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W ADDR F43H PS022820 0307 Universal Asynchronous Receiver Transmitter PS022820 0307 Z8 Encore XP 8K and 4K Series Product Specification AR ZiLOG MPMD 1 0 MULTIPROCESSOR Mode If MULTIPROCESSOR 9 bit mode is enabled 00 The UART generates an interrupt request on all received bytes data and address 01 The UART generates an interrupt request only on received address bytes 10 The UART generates an interrupt request when a received address byte matches the value stored in the Address Compare Register and on all successive data bytes until an address mismatch occurs 11 The UART generates an interrupt request on all received data bytes for which the most recent address byte matched the value in the Address Compare Register MPEN MULTIPROCESSOR 9 bit Enable This bit is used to enable MULTIPROCESSOR 9 bit mode 0 Disable MULTIPROCESSOR 9 bit mode 1 Enable MULTIPROCESSOR 9 bit mode MPBT Miultiprocessor Bit Transmit This bit is applicable only when MULTIPROCESSOR 9 bit mode is enabled The 9th bit is used by the receiving device to determine if the data byte contains address or data infor mation 0 Send a 0 in the multiprocessor bit location of the data stream data byte 1 Send a 1 in the multiprocessor bit location of the data stream address byte DEPOL Driver Enable Polarity 0
52. Enable Low Bit IRQ1 Enable High and Low Bit Registers PS022820 0307 Table 39 describes the priority control for IRQ1 The IRQ1 Enable High and Low Bit registers Table 40 and Table 41 form a priority encoded enabling for interrupts in the Interrupt Request 1 register Interrupt Controller Z8 Encore XP 8K and 4K Series Product Specification Lle Zi LOG Table 39 IRA1 Enable and Priority Encoding IRQ1ENH x IRQ1ENL x Priority Description 0 0 Disabled Disabled 0 1 Level 1 Low 1 0 Level 2 Medium 1 1 Level 3 High where x indicates the register bits from 0 7 Table 40 IRQ1 Enable High Bit Register IRQ1ENH BITS 7 6 5 4 3 2 1 0 FIELD PA7VENH PAGCENH PABSENH PA4ENH PA3ENH PA2ENH PA1ENH PAOENH RESET 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W ADDR FC4H PA7VENH Port A Bit 7 or LVD Interrupt Request Enable High Bit PA6CENH Port A Bit 7 or Comparator Interrupt Request Enable High Bit PAxENH Port A Bit x Interrupt Request Enable High Bit See Shared Interrupt Select IRQSS register for selection of either the LVD or the comparator as the interrupt source Table 41 IRQ1 Enable Low Bit Register IRQ1ENL BITS 7 6 5 4 3 2 1 0 FIELD PA7VENL PAGCENL PABSENL PA4ENL PA3ENL PA2ENL PA1ENL PAOENL RESET 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W ADDR FC5H PA7VENL
53. Encore XP 8K and 4K Series Product Specification A Zi LOG PS022820 0307 On Chip Debugger Z8 Encore XP 8K and 4K Series Product Specification AM Zi LOG Oscillator Control The Z8 Encore XP 8K and 4K Series devices uses five possible clocking schemes each user selectable Internal precision trimmed RC oscillator IPO On chip oscillator using off chip crystal or resonator On chip oscillator using external RC network External clock drive On chip low power Watchdog Timer oscillator Clock failure detection circuitry In addition Z8 Encore XP 8K and 4K Series devices contain clock failure detection and recovery circuitry allowing continued operation despite a failure of the system clock oscillator Operation This chapter discusses the logic used to select the system clock and handle primary oscillator failures A description of the specific operation of each oscillator is outlined elsewhere in this document The detailed description of the Watchdog Timer Oscillator starts on page 91 the Internal Precision Oscillator description begins on page 199 and the chapter outlining the Crystal Oscillator begins on page 193 of this document System Clock Selection The oscillator control block selects from the available clocks Table 108 details each clock source and its usage PS022820 0307 Oscillator Control Table 108 Oscillator Configuration and Selection Z8 Encore XP 8K and 4K Series Prod
54. If the device is not in DEBUG mode or if the Flash Read Protect Option bit is en abled the data is discarded DBG lt OCH DBG lt Data Memory Address 15 8 DBG lt Data Memory Address 7 0 DBG lt Size 15 8 DBG lt Size 7 0 DBG lt 1 65536 data bytes Read Data Memory 0DH The Read Data Memory command reads from Data Memory This command is equivalent to the LDE and LDEI instructions Data can be read 1 to 65536 bytes at a time 65536 bytes can be read by setting size to 0 If the device is not in DEBUG mode this command returns FFH for the data On Chip Debugger 182 Z8 Encore XP 8K and 4K Series Product Specification AR ZiLOG DBG lt ODH DBG lt Data Memory Address 15 8 DBG lt Data Memory Address 7 0 DBG Size 15 8 DBG lt Size 7 0 DBG 1 65536 data bytes Read Program Memory CRC 0EH The Read Program Memory CRC com mand computes and returns the Cyclic Redundancy Check CRC of Program Mem ory using the 16 bit CRC CCITT polynomial If the device is not in DEBUG mode this command returns FFFFH for the CRC value Unlike most other OCD Read com mands there is a delay from issuing of the command until the OCD returns the data The OCD reads the Program Memory calculates the CRC value and returns the re sult The delay is a function of the Program Memory size and is approximately equal to the system clock period multiplied by the number of bytes in the P
55. Interrupt Vector 0006 0007 Illegal Instruction Trap 0008 0037 Interrupt Vectors 0038 0039 Reserved 003A 003D Oscillator Fail Trap Vectors 003E OSFF Program Memory Note See Table 32 on page 56 for a list of the interrupt vectors Data Memory The Z8 Encore XP 8K and 4K Series does not use the eZ8 CPU s 64 KB Data Memory address space Flash Information Area Table 6 on page 18 describes the Z8 Encore XP 8K and 4K Series Flash Information Area This 128 B Information Area is accessed by setting bit 7 of the Flash Page Select Register to 1 When access is enabled the Flash Information Area is mapped into the Pro PS022820 0307 Address Space PS022820 0307 Z8 Encore XP 8K and 4K Series Product Specification 18 Zi LOG gram Memory and overlays the 128 bytes at addresses FEOOH to FF7FH When the Infor mation Area access is enabled all reads from these Program Memory addresses return the Information Area data rather than the Program Memory data Access to the Flash Informa tion Area is read only Table 6 Z8 Encore XP 8K and 4K Series Flash Memory Information Area Map Program Memory Address Hex Function FEO0 FESF ZiLOG Option Bits Calibration Data FE40 FE53 Part Number 20 character ASCII alphanumeric code Left justified and filled with FFH FE54 FE5F Reserved FE60 FE7F ZiLOG Calibration Data FE80 FFFF Reserved Address Space Z8 Encore XP 8K and 4K Series Product S
56. KB 8192 4 KB 4096 2 KB 2048 bytes or 1 KB 1024 with read write erase capability The Flash Memory can be programmed and erased in circuit by user code or through the On Chip Debugger Features include User controlled read and write protect capability Sector based write protection scheme Additional protection schemes against accidental program and erasure Architecture PS022820 0307 The Flash memory array is arranged in pages with 512 bytes per page The 512 byte page is the minimum Flash block size that can be erased Each page is divided into 8 rows of 64 bytes For program or data protection the Flash memory is also divided into sectors In the Z8 Encore XP 8K and 4K Series these sectors are either 1024 bytes in the 8kB devices or 512 bytes all other memory sizes in size Page and sector sizes are not generally equal The first 2 bytes of the Flash Program memory are used as Flash Option Bits See chapter Flash Option Bits on page 153 for more information about their operation Table 76 describes the Flash memory configuration for each device in the Z8 Encore XP 8K and 4K Series Figure 21 illustrates the Flash memory arrangement Table 76 Z8 Encore XP 8K and 4K Series Flash Memory Configurations Flash Size Flash Program Memory Flash Sector Part Number KB Bytes Pages Addresses Size bytes Z8F08xA 8 8192 16 0000H 1FFFH 1024 Z8F04xA 4 4096 8 OOOOH OFFFH 512 Z8F02xA 2 2048
57. Mode Recovery the eZ8 CPU responds to the interrupt request by fetching the Watchdog Timer interrupt vector and exe cuting code from the vector address WDT Reset in NORMAL Operation If configured to generate a Reset when a time out occurs the Watchdog Timer forces the device into the System Reset state The WDT status bit in the Reset Status RSTSTAT register is set to 1 See chapter Reset Stop Mode Recovery and Low Voltage Detection on page 23 for more information about system reset WDT Reset in STOP Mode If configured to generate a Reset when a time out occurs and the device is in STOP mode the Watchdog Timer initiates a Stop Mode Recovery Both the WDT status bit and the STOP bit in the Reset Status RSTSTAT register are set to 1 following WDT time out in STOP mode See chapter Reset Stop Mode Recovery and Low Voltage Detection on page 23 for more information Watchdog Timer Reload Unlock Sequence PS022820 0307 Writing the unlock sequence to the Watchdog Timer WDTCTL Control register address unlocks the three Watchdog Timer Reload Byte registers WDTU WDTH and WDTL to allow changes to the time out period These write operations to the WDTCTL register address produce no effect on the bits in the WDTCTL register The locking mechanism prevents spurious writes to the Reload registers The following sequence is required to unlock the Watchdog Timer Reload Byte registers WDTU WDTH and WDTL for write access 1 Write 55
58. Program Memory 0AH The Write Program Memory command writes data to Program Memory This command is equivalent to the LDC and LDCI instruc tions Data can be written 1 65536 bytes at a time 65536 bytes can be written by set ting size to 0 The on chip Flash Controller must be written to and unlocked for the programming operation to occur If the Flash Controller is not unlocked the data is discarded If the device is not in DEBUG mode or if the Flash Read Protect Option bit is enabled the data is discarded DBG lt OAH DBG lt Program Memory Address 15 8 DBG lt Program Memory Address 7 0 DBG lt Size 15 8 DBG lt Size 7 0 DBG lt 1 65536 data bytes Read Program Memory 0BH The Read Program Memory command reads data from Program Memory This command is equivalent to the LDC and LDCI instruc tions Data can be read 1 65536 bytes at a time 65536 bytes can be read by setting size to 0 If the device is not in DEBUG mode or if the Flash Read Protect Option bit is enabled this command returns FFH for the data DBG lt OBH DBG Program Memory Address 15 8 DBG lt Program Memory Address 7 0 DBG lt Size 15 8 DBG Size 7 0 DBG 1 65536 data bytes Write Data Memory 0CH The Write Data Memory command writes data to Data Memory This command is equivalent to the LDE and LDEI instructions Data can be written 1 65536 bytes at a time 65536 bytes can be written by setting size to 0
59. Reserved Must be 0 C3ENL Port C3 Interrupt Request Enable Low Bit C2ENL Port C2 Interrupt Request Enable Low Bit PS022820 0307 Interrupt Controller Z8 Encore XP 8K and 4K Series Product Specification CIENL Port C1 Interrupt Request Enable Low Bit COENL Port CO Interrupt Request Enable Low Bit Interrupt Edge Select Register The Interrupt Edge Select IRQES register Table 45 determines whether an interrupt is generated for the rising edge or falling edge on the selected GPIO Port A input pin Table 45 Interrupt Edge Select Register IRQES L e Zi LOG BITS 7 6 5 4 3 2 1 0 FIELD IES7 IES6 IES5 IES4 IES3 IES2 IES1 IESO RESET 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W ADDR FCDH IESx Interrupt Edge Select x 0 An interrupt request is generated on the falling edge of the PAx input 1 An interrupt request is generated on the rising edge of the PAx input where x indicates the specific GPIO Port pin number 0 through 7 Shared Interrupt Select Register The Shared Interrupt Select IRQSS register Table 46 determines the source of the PADXxS interrupts The Shared Interrupt Select register selects between Port A and alternate sources for the individual interrupts Because these shared interrupts are edge triggered it is possible to generate an interrupt just by switching from one shared source to another For this reason an interrupt must
60. The output sinks current at programmable levels of 3 mA 7 mA 13 mA and 20 mA This mode is enabled through the Alternate Function sub register AFSI and is programmable through the LED control registers The LED Drive Enable LEDEN register turns on the drivers The LED Drive Level LEDLVLH and LEDLVLL registers select the sink current For correct function the LED anode must be connected to Vpp and the cathode to the GPIO pin Using all Port C pins in LED drive mode with maximum current may result in excessive total current See Electrical Characteristics on page 223 for the maximum total current for the applicable package Shared Reset Pin On the 20 and 28 pin devices the PDO pin shares function with a bi directional reset pin Unlike all other I O pins this pin does not default to GPIO function on power up This pin acts as a bi directional reset until user software re configures it The PDO pin is output only when in GPIO mode On the 8 pin product versions the reset pin is shared with PA2 but the pin is not limited to output only when in GPIO mode AN Caution If PA2 on the 8 pin product is reconfigured as an input take care that no external stimulus drives the pin low during any reset sequence Since PA2 returns to its RESET alternate function during system resets driving it Low holds the chip in a reset state until the pin is released Shared Debug Pin On the 8 pin version of this device only the Debug pin shares fu
61. The value actually read is the ADC offset This value can be stored in non volatile memory Non Volatile Data Storage on page 169 and accessed by user code to compensate for the input offset error There is no provision for manual gain calibration Software Compensation Procedure Using Factory Calibration Data The value read from the ADC high and low byte registers is uncompensated The user mode software must apply gain and offset correction to this uncompensated value for maximum accuracy The following formula yields the compensated value ADComp ADCuncomp OFFCAL ADC yncomp OFFCAL GAINCAL 2 6 where GAINCAL is the gain calibration value OFFCAL is the offset calibration value and ADCyncomp is the uncompensated value read from the ADC All values are in two s complement format Analog to Digital Converter 126 gt Note Z8 Encore XP 8K and 4K Series Product Specification 127 Zi LOG The offset compensation is performed first followed by the gain compensation One bit of resolution is lost because of rounding on both the offset and gain computations As a result the ADC registers read back 13 bits 1 sign bit two calibration bits lost to rounding and 10 data bits Also note that in the second term the multiplication must be performed before the division by 2 6 Otherwise the second term incorrectly evaluates to zero AN Caution Althoughthe ADC can be used without the gain and offset compensation
62. Timer Output make a state change at a One Shot time out rather than a single cycle pulse first set the TPOL bit in the Timer Control Register to the start value before enabling ONE SHOT mode After starting the timer set TPOL to the opposite bit value The steps for configuring a timer for ONE SHOT mode and initiating the count are as follows 1 Write to the Timer Control register to Disable the timer Configure the timer for ONE SHOT mode Set the prescale value Set the initial output level High or Low if using the Timer Output alternate function 2 Write to the Timer High and Low Byte registers to set the starting count value 3 Wirite to the Timer Reload High and Low Byte registers to set the Reload value 4 Ifappropriate enable the timer interrupt and set the timer interrupt priority by writing to the relevant interrupt registers 5 Ifusing the Timer Output function configure the associated GPIO port pin for the Timer Output alternate function 6 Wirite to the Timer Control register to enable the timer and initiate counting In ONE SHOT mode the system clock always provides the timer input The timer period is given by the following equation Reload Value Start Value x Prescale Shot Mode Time Out Period M M M M scu orsa CU System Clock Frequency Hz CONTINUOUS Mode In CONTINUOUS mode the timer counts up to the 16 bit Reload value stored in the Timer R
63. Timer accuracy still degrades as temperature and supply voltage vary See Table 133 Watchdog Timer Electrical Characteristics and Timing on page 232 for details Watchdog Timer Control Register Definitions Watchdog Timer Control Register The Watchdog Timer Control WDTCTL register is a write only control register Writing the 55H AAH unlock sequence to the WDTCTL register address unlocks the three Watch dog Timer Reload Byte registers WDTU WDTH and WDTL to allow changes to the time out period These write operations to the WDTCTL register address produce no effect on the bits in the WDTCTL register The locking mechanism prevents spurious writes to the Reload registers This register address is shared with the read only Reset Status register Table 57 Watchdog Timer Control Register WDTCTL BITS 7 6 5 4 3 2 1 0 FIELD WDTUNLK RESET X X X X X X X X R W W W W W W ADDR FFOH X Undefined PS022820 0307 Watchdog Timer Z8 Encore XP 8K and 4K Series Product Specification WDTUNLK Watchdog Timer Unlock Lie Zi LOG The user software must write the correct unlocking sequence to this register before it is allowed to modify the contents of the Watchdog Timer reload registers Watchdog Timer Reload Upper High and Low Byte Registers The Watchdog Timer Reload Upper High and Low Byte WDTU WDTH WDTL regis ters Table 58 through Table 60 form the 24 bit reloa
64. UART Baud Rate High and Low Byte registers to set an acceptable baud rate for the incoming data stream Enable the UART pin functions by configuring the associated GPIO Port pins for alternate function operation Write to the UART Control 1 register to enable MULTIPROCESSOR mode functions if appropriate Write to the UART Control 0 register to Set the receive enable bit REN to enable the UART for data reception Enable parity if appropriate and if Multiprocessor mode is not enabled and select either even or odd parity Check the RDA bit in the UART Status 0 register to determine if the Receive Data register contains a valid data byte indicated by a 1 If RDA is set to 1 to indicate available data continue to Step 5 If the Receive Data register is empty indicated by a 0 continue to monitor the RDA bit awaiting reception of the valid data Read data from the UART Receive Data register If operating in MULTIPROCESSOR 9 bit mode further actions may be required depending on the MULTIPROCESSOR mode bits MPMD 1 0 Return to Step 4 to receive additional data Universal Asynchronous Receiver Transmitter Z8 Encore XP 8K and 4K Series Product Specification Zi LOG Receiving Data using the Interrupt Driven Method PS022820 0307 The UART Receiver interrupt indicates the availability of new data as well as error conditions Follow these steps to configure the UART receiver for interrupt driven opera tion
65. Unlock and write Oscillator Control Register OSCCTL to enable and select oscillator Unintentional accesses to the oscillator control register can actually stop the chip by switching to a non functioning oscillator To prevent this condition the oscillator con trol block employs a register unlocking locking scheme OSC Control Register Unlocking Locking To write the oscillator control register unlock it by making two writes to the OSCCTL register with the values 1 E7H followed by 18H A third write to the OSCCTL register changes the value of the actual register and returns the register to a locked state Any other sequence of oscillator control register writes has no effect The values written to unlock the register must be ordered correctly but are not necessarily consecutive It is possible to write to or read from other registers within the unlocking locking operation Oscillator Control Z8 Encore XP 8K and 4K Series Product Specification Z Zi LOG When selecting a new clock source the system clock oscillator failure detection circuitry and the Watchdog Timer oscillator failure circuitry must be disabled If SOFEN and WOFEN are not disabled prior to a clock switch over it is possible to generate an inter rupt for a failure of either oscillator The Failure detection circuitry can be enabled any time after a successful write of OSCSEL in the OSCCTL register The internal precision oscillator is enabled by defa
66. XP 8K and 4K Series Product Specification Z 243 CONTROLLING DIMENSIONS MM ZPL OG Packaging Figure 39 illustrates the 8 pin Plastic Dual Inline Package PDIP available for Z8 Encore XP 8K and 4K Series devices 8 5 MILLIMETER INCH SYMBOL MIN MAX MIN MAX M 0 38 0 81 0 015 0 032 El A2 325 3 81 0 128 0 150 B 0 38 0 53 0 015 0 021 B1 140 1 65 0 055 0 065 C 0 20 0 30 0 008 0 012 i fat D 9 02 9 78 0 355 0 385 i s E 7 62 8 26 0 300 0 325 E1 6 10 6 60 0 240 0 260 i E 5 2 54 BSC 0 100 BSC eA 787 9 14 0 310 0 360 B1 L 3 18 343 0 125 0 135 E i at 1 40 1 65 0 055 0 065 7 x5 S 0 64 0 89 0 025 0 035 Ka L Figure 39 8 Pin Plastic Dual Inline Package PDIP PS022820 0307 Packaging Z8 Encore XP 8K and 4K Series Product Specification Z 244 ZiLOG Figure 40 illustrates the 8 pin Small Outline Integrated Circuit package SOIC available for the Z8 Encore XP 8K and 4K Series devices ILLIMETER ICH a x f n A2 06 019 010 E 196 rane i E I al 1 i pO H 5 84 Figure 40 8 Pin Small Outline Integrated Circuit Package SOIC PS022820 0307 Packaging Z8 Encore XP 8K and 4K Series Product Specification Zi LOG Figure 41 illustrates the 8 pin Ouad Flat No Lead package OFN MLF S available for the Z8 Encore XP 8K and 4K Se
67. ZiLOG Table 124 eZ8 CPU Instruction Summary Continued Assembly Symbolic Adress Mode Opcode s Fags Fetch Instr Mnemonic Operation dst src Hex C Z S V D H Cycles Cycles COM dst dst lt dst R 60 0 2 2 IR 61 2 3 CP dst src dst src r r A2 uM ME MG 2 3 r Ir A3 2 4 R R A4 3 3 R IR A5 3 4 R IM A6 3 3 IR IM AT 3 4 CPC dst src dst src C r r 1F A2 e 9e ee 3 3 r Ir 1F A3 3 4 R R 1F A4 4 3 R IR 1F A5 4 4 R IM 1F A6 4 3 IR IM 1F A7 4 4 CPCX dst src dst src C ER ER 1F A8 m We uet V 5 3 ER IM 1F A9 5 3 CPX dst src dst src ER ER A8 GER ME ME 4 3 ER IM A9 4 3 DA dst dst lt DA dst R 40 X 2 2 IR 41 2 3 DEC dst dst dst 1 R 30 px OL UIS 2 2 IR 31 2 3 DECW dst dst dst 1 RR 80 o WU OUR 2 5 IRR 81 2 6 DI IRQCTL 7 0 8F 1 2 DJNZ dst RA dst dst 1 r OA FA 2 3 if dst 0 PC lt PC X EI IRQCTL 7 1 9F 1 2 Flags Notation Value is a function of the result of the operation 0 Reset to 0 Unaffected 1 Set to 1 X Undefined PS022820 0307 eZ8 CPU Instruction Set Z8 Encore XP 8K and 4K Series Product Specification Z 212 ziLoc Table 124 eZ8 CPU Instruction Summary Continued Assembly Symbolic Adress Mode Opcode s Flags Fetch Instr Mnemonic Operation dst src Hex C Z S V D H Cycles Cycles HALT Halt Mode 7F 1 2 INC dst dst dst 1 R 20 2 2 IR 2
68. and Z8F01xA in 20 Pin SOIC SSOP or PDIP Package PB2 ANA2 AMPINP PB4 ANA7 PB5 VREF PB3 CLKIN ANA3 PB6 AVDD VDD PAO TOIN TOOUT XIN PA1 TOOUT XOUT VSS PB7 AVSS PA2 DEO PA3 CTSO PA4 RXDO PA5 TXDO co 400 0 NN c c a c O AUONaO 28 27 26 25 24 23 22 21 20 19 18 17 16 15 I PB1 ANA1 AMPINN I PBO ANAO AMPOUT I PC3 COUT LED PC2 ANA6 LED L PC1 ANA5 CINN LED I PCO ANA4 CINP LED DBG RESET PDO PC7 LED PC6 LED PA7 T1OUT PC5 LED I PC4 LED I PA6 T1IN T1OUT Figure 4 Z8F08xA Z8F04xA Z8F02xA and Z8F01xA in 28 Pin SOIC SSOP or PDIP Package PS022820 0307 Pin Description Z8 Encore XP 8K and 4K Series Product Specification 11 Zi LOG Signal Descriptions Table 2 describes the Z8 Encore XP 8K and 4K Series signals See Pin Configurations on page 9 to determine the signals available for the specific package styles Table 2 Signal Descriptions Signal Mnemonic lO Description General Purpose I O Ports A D PA 7 0 O Port A These pins are used for general purpose 1 0 PB 7 0 I O Port B These pins are used for general purpose I O PB6 and PB7 are available only in those devices without an ADC PC 7 0 1 0 Port C These pins are used for general purpose 1 0 PD 0 O Port D This pin is used for general purpose output only Note PB6 and PB7 are
69. and a read routine Both of these routines are accessed with a CALL instruction to a pre defined address outside of the user accessible program memory Both the NVDS address and data are single byte values Because these routines disturb the working register set user code must ensure that any required working register values are preserved by pushing them onto the stack or by changing the working register pointer just prior to NVDS execution During both read and write accesses to the NVDS interrupt service is NOT disabled Any interrupts that occur during the NVDS execution must take care not to disturb the working register and existing stack contents or else the array may become corrupted Disabling interrupts before executing NVDS operations is recommended Use of the NVDS requires 15 bytes of available stack space Also the contents of the working register set are overwritten For correct NVDS operation the Flash Frequency Registers must be programmed based on the system clock frequency See Flash Operation Timing Using the Flash Frequency Registers on page 145 Byte Write To write a byte to the NVDS array the user code must first push the address then the data byte onto the stack The user code issues a CALL instruction to the address of the PS022820 0307 Non Volatile Data Storage Z8 Encore XP 8K and 4K Series Product Specification VAR ZiLOG byte write routine 0x10B3 At the return from the sub routine the write stat
70. and features an enabled internal pull up resistor PS022820 0307 Pin Description Z8 Encore XP 8K and 4K Series Product Specification 13 Zi LOG Table 2 Signal Descriptions Continued Signal Mnemonic I O Description Power Supply Vpp Digital Power Supply AVpp Analog Power Supply Vss Digital Ground AVss Analog Ground Note The AVpp and AVss signals are available only in 28 pin packages with ADC They are replaced by PB6 and PB7 on 28 pin packages without ADC Pin Characteristics Table 3 provides detailed information about the characteristics for each pin available on the Z8 Encore XP 8K and 4K Series 20 and 28 pin devices Data in Table 3 is sorted alphabetically by the pin symbol mnemonic Table 4 on page 14 provides detailed information about the characteristics for each pin available on the Z8 Encore XP 8K and 4K Series 8 pin devices gt Note All six I O pins on the 8 pin packages are 5 V tolerant unless the pull up devices are enabled The column in Table 3 below describes 5 V tolerance for the 20 and 28 pin packages only Table 3 Pin Characteristics 20 and 28 pin Devices Active Low or Internal Pull Schmitt Symbol Reset Active Tristate up Trigger Open Drain 5V Mnemonic Direction Direction High Output or Pull down Input Output Tolerance AVDD N A N A N A N A N A N A N A N A AVSS N A N A N A N A N A N A N A NA DBG O l N A Yes Yes Yes Yes No PA 7 0
71. and internal precision oscillator are stopped XIN and XOUT if previously enabled are disabled and PAO PAT revert to the states programmed by the GPIO registers System clock is stopped eZ8 CPU is stopped Program counter PC stops incrementing Watchdog Timer s internal RC oscillator continues to operate if enabled by the Oscillator Control register Ifenabled the Watchdog Timer logic continues to operate Ifenabled for operation in STOP mode by the associated Flash Option Bit the Voltage Brownout protection circuit continues to operate Low power operational amplifier continues to operate if enabled by the Power Control register to do so Allother on chip peripherals are idle To minimize current in STOP mode all GPIO pins that are configured as digital inputs must be driven to one of the supply rails Vcc or GND Additionally any GPIOs config ured as outputs must also be driven to one of the supply rails The device can be brought out of STOP mode using Stop Mode Recovery For more information about Stop Mode Recovery see Reset Stop Mode Recovery and Low Voltage Detection on page 23 Low Power Modes Z8 Encore XP 8K and 4K Series Product Specification VAR Zi LOG HALT Mode Executing the eZ8 CPU s HALT instruction places the device into HALT mode which powers down the CPU but leaves all other peripherals active In HALT mode the operating characteristics are Primary oscillator is
72. described in Timer Pin Signal Operation on page 82 PS022820 0307 General Purpose Input Output Z8 Encore XP 8K and 4K Series Product Specification ZI Zi LOG Table 14 Port Alternate Function Mapping Non 8 Pin Parts Continued Alternate Function Set Port Pin Mnemonic Alternate Function Description Register AFS1 PBO Reserved AFS1 0 0 ANAO AMPOUT ADC Analog Input LPO Output AFS1 0 1 PB1 Reserved AFS1 1 0 ANA1 AMPINN ADC Analog Input LPO Input N AFS1 1 1 PB2 Reserved AFS1 2 0 ANA2 AMPINP ADC Analog Input LPO Input P AFS1 2 1 PB3 CLKIN External Clock Input AFS1 3 0 ANA3 ADC Analog Input AFS1 3 1 PB4 Reserved AFS1 4 0 ANA7 ADC Analog Input AFS1 4 1 PB5 Reserved AFS1 5 0 VREF ADC Voltage Reference AFS1 5 1 PB6 Reserved AFS1 6 0 Reserved AFS1 6 1 PB7 Reserved AFS1 7 0 Port B Reserved AFS1 7 1 Note Because there are at most two choices of alternate function for any pin of Port B the Alternate Function Set register AFS2 is not used to select the function Also alternate function selection as described in Port A D Alternate Function Sub Registers on page 48 must also be enabled VREF is available on PB5 in 28 pin products only PS022820 0307 General Purpose Input Output Z8 Encore XP 8K and 4K Series Product Specification Zi Zi LOG Table 14 Port Alternate Function Mapping Non 8 Pin Parts Continued
73. enabled and continues to operate System clock is enabled and continues to operate eZ8 CPU is stopped Program counter PC stops incrementing Watchdog Timer s internal RC oscillator continues to operate Ifenabled the Watchdog Timer continues to operate All other on chip peripherals continue to operate if enabled The eZ8 CPU can be brought out of HALT mode by any ofthe following operations Interrupt Watchdog Timer time out interrupt or reset Power on reset Voltage Brownout reset External RESET pin assertion To minimize current in HALT mode all GPIO pins that are configured as inputs must be driven to one of the supply rails Vcc or GND Peripheral Level Power Control In addition to the STOP and Halt modes it is possible to disable each peripheral on each of the Z8 Encore XP 8K and 4K Series devices Disabling a given peripheral minimizes Its power consumption Power Control Register Definitions The following sections define the Power Control registers Power Control Register 0 Each bit of the following registers disables a peripheral block either by gating its system clock input or by removing power from the block PS022820 0307 Low Power Modes gt Note Z8 Encore XP 8K and 4K Series Product Specification Zi LOG The default state of the low power operational amplifier LPO is OFF To use the LPO clear the LPO bit turning it ON Clearing this bit might interfere wit
74. external crystal ceramic resonator or RC network Low Voltage Detector The low voltage detector LVD is able to generate an interrupt when the supply voltage drops below a user programmable level The LVD is available on 8 pin devices only On Chip Debugger The Z8 Encore XP 8K and 4K Series products feature an integrated on chip debugger OCD accessed via a single pin interface The OCD provides a rich set of debugging capabilities such as reading and writing registers programming Flash memory setting breakpoints and executing code PS022820 0307 Overview Z8 Encore XP 8K and 4K Series Product Specification Zi LOG Universal Asynchronous Receiver Transmitter The full duplex UART is included in all Z8 Encore XP package types The UART sup ports 8 and 9 bit data modes and selectable parity The UART also supports multi drop address processing in hardware The UART baud rate generator BRG can be configured and used as a basic 16 bit timer Timers Two enhanced 16 bit reloadable timers can be used for timing counting events or for motor control operations These timers provide a 16 bit programmable reload counter and operate in One Shot Continuous Gated Capture Capture Restart Compare Capture and Compare PWM Single Output and PWM Dual Output modes General Purpose I O The Z8 Encore XP 8K and 4K Series features 6 to 25 port pins Ports A D for general purpose I O GPIO The number of GPIO pins available is
75. for the minimum and maximum WDT reload values PS022820 0307 Watchdog Timer Z8 Encore XP 8K and 4K Series Product Specification Zi Zi LOG Table 56 Watchdog Timer Approximate Time Out Delays Approximate Time Out Delay with 10 kHz typical WDT oscillator frequency WDT Reload Value WDT Reload Value Hex Decimal Typical Description 000004 4 400 us Minimum time out delay FFFFFF 16 777 215 28 minutes Maximum time out delay Watchdog Timer Refresh When first enabled the Watchdog Timer is loaded with the value in the Watchdog Timer Reload registers The Watchdog Timer counts down to 000000H unless a WDT instruction is executed by the eZ8 CPU Execution of the WDT instruction causes the downcounter to be reloaded with the WDT Reload value stored in the Watchdog Timer Reload registers Counting resumes following the reload operation When the Z8 Encore XP 8K and 4K Series devices are operating in DEBUG mode using the on chip debugger the Watchdog Timer is continuously refreshed to prevent any Watchdog Timer time outs Watchdog Timer Time Out Response The Watchdog Timer times out when the counter reaches 000000H A time out of the Watchdog Timer generates either an interrupt or a system reset The WDT RES Flash Option Bit determines the time out response of the Watchdog Timer See chapter Flash Option Bits on page 153 for information regarding programming of the WDT RES Flash Option Bit WDT Interrupt i
76. identifier With this feature all devices in a given production lot are programmed with the same random number This random number is uniquely regenerated for each successive production lot and is not likely to be repeated The randomized lot identifier 1s a 32 byte binary value stored in the flash information page see Reading the Flash Information Page on page 155 and Randomized Lot Identifier on page 166 for more details and is unaffected by mass erasure of the device s flash memory Reading the Flash Information Page The following code example shows how to read data from the flash information area get value at info address 60 FE60h ldx FPS 80 enable access to flash info page ld RO SFE ld R1 60 ldc R2 RRO R2 now contains the calibration value Flash Option Bit Control Register Definitions Trim Bit Address Register The Trim Bit Address TRMADR register contains the target address for an access to the trim option bits Table 84 Trim Bit Address Register TRMADR BITS 7 6 5 4 3 2 1 0 FIELD TRMADR Trim Bit Address 00H to 1FH RESET 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W ADDR FF6H PS022820 0307 Flash Option Bits Z8 Encore XP 8K and 4K Series Product Specification 156 Zi LOG Trim Bit Data Register The Trim Bid Data TRMDR register contains the read or write data for access to the trim option bits Table 85 Tr
77. is available using the On Chip Debugger 1 Programming Page Erase and Mass Erase are enabled for all of Flash program memory Flash Program Memory Address 0001H Table 87 Flash Options Bits at Program Memory Address 0001H BITS 7 6 5 4 3 2 1 0 FIELD Reserved XTLDIS Reserved RESET U U U U U U U U R W R W R W R W R W R W R W R W R W ADDR Program Memory 0001H Note U Unchanged by Reset R W Read Write PS022820 0307 Flash Option Bits gt Note Z8 Encore XP 8K and 4K Series Product Specification Zi LOG Reserved Must be 1 XTLDIS State of Crystal Oscillator at Reset This bit only enables the crystal oscillator Its selection as system clock must be done man ually 0 2 Crystal oscillator is enabled during reset resulting in longer reset timing 1 Crystal oscillator is disabled during reset resulting in shorter reset timing AN Warning Programming the XTLDIS bit to zero on 8 pin versions of this device prevents any further communication via the debug pin This is due to the fact that the XIN and DBG functions are shared on pin 2 of this package Do not program this bit to zero on 8 pin devices unless no further debugging or flash programming is required Trim Bit Address Space All available Trim bit addresses and their functions are listed in Table 88 through Table 92 Trim Bit Address 0000H Table 88 Trim Options Bits at Address 0000H
78. is configured for alternate function control of the port pin direction input output is passed from the Port A D Data Direction registers to the alternate function assigned to this pin Table 14 on page 41 lists the alternate functions possible with each port pin For those pins with more one alternate function the alternate function is defined through Alternate Function Sets sub registers AFS1 and AFS2 The crystal oscillator functionality is not controlled by the GPIO block When the crystal oscillator is enabled in the oscillator control block the GPIO functionality of PAO and PA1 is overridden In that case those pins function as input and output for the crystal oscillator PS022820 0307 General Purpose Input Output PS022820 0307 Z8 Encore XP 8K and 4K Series Product Specification Zi LOG PAO and PA6 contain two different timer functions a timer input and a complementary timer output Both of these functions reguire the same GPIO configuration the selection between the two is based on the timer mode See Timers on page 69 for more details AA Caution For pin with multiple alternate functions it is recommended to write to the AFSI and AFS2 sub registers before enabling the alternate function via the AF sub register This prevents spurious transitions through unwanted alternate function modes Direct LED Drive The Port C pins provide a current sinked output capable of driving an LED without requiring an external resistor
79. l 9 Write to the UART Baud Rate High and Low Byte registers to set the acceptable baud rate Enable the UART pin functions by configuring the associated GPIO Port pins for alternate function operation Ezecute a DI instruction to disable interrupts Write to the Interrupt control registers to enable the UART Receiver interrupt and set the acceptable priority Clear the UART Receiver interrupt in the applicable Interrupt Request register Write to the UART Control 1 Register to enable Multiprocessor 9 bit mode functions if appropriate Set the Multiprocessor Mode Select MPEN to Enable MULTIPROCESSOR mode Set the Multiprocessor Mode Bits MPMD 1 0 to select the acceptable address matching scheme Configure the UART to interrupt on received data and errors or errors only interrupt on errors only is unlikely to be useful for Z8 Encore devices without a DMA block Write the device address to the Address Compare Register automatic MULTIPROCESSOR modes only Write to the UART Control 0 register to Set the receive enable bit REN to enable the UART for data reception Enable parity if appropriate and if multiprocessor mode is not enabled and select either even or odd parity Execute an EI instruction to enable interrupts The UART is now configured for interrupt driven data reception When the UART Receiver interrupt 1s detected the associated interrupt service routine ISR performs
80. mE JUI 7 UUL Oscillator Oscillator Start up Internal RESET POR optional XTAL Note Not to Scale 1 counter delay counterdelay Figure 5 Power On Reset Operation Voltage Brownout Reset PS022820 0307 The devices in the Z8 Encore XP 8K and 4K Series provide low voltage brownout VBO protection The VBO circuit senses when the supply voltage drops to an unsafe level below the VBO threshold voltage and forces the device into the Reset state While the supply voltage remains below the Power on reset voltage threshold Vpop the VBO block holds the device in the Reset After the supply voltage again exceeds the Power on reset voltage threshold the device progresses through a full System Reset sequence as described in the Power on reset section Following power on reset the POR status bit in the Reset Status RSTSTAT register 1s set to 1 Figure 6 illustrates Voltage Brown Out operation See chapter Electrical Characteristics on page 223 for the VBO and POR threshold voltages Vygo and Vpog The Voltage Brownout circuit can be either enabled or disabled during STOP mode Operation during STOP mode is set by the VBO AO Flash Option Bit See Flash Option Bits chapter for information about configuring VBO AO Reset Stop Mode Recovery and Low Voltage Detection Z8 Encore XP 8K and 4K Series Product Specification ZI Zi LOG l VCC 3 3V VCC 3 3V VPOR cks A S ll SI Vidoes m
81. maximize pins available to the user 8 pin product only Architecture The on chip debugger consists of four primary functional blocks transmitter receiver auto baud detector generator and debug controller Figure 23 illustrates the architecture of the on chip debugger Auto Baud System Clock Detector Generator eZ8 CPU Control Transmitter Debug Controller DBG Pin Receiver Figure 23 On Chip Debugger Block Diagram PS022820 0307 On Chip Debugger Z8 Encore XP 8K and 4K Series Product Specification Ll Zi LOG Operation OCD Interface The on chip debugger uses the DBG pin for communication with an external host This one pin interface is a bi directional open drain interface that transmits and receives data Data transmission is half duplex in that transmit and receive cannot occur simultaneously The serial data on the DBG pin is sent using the standard asynchronous data format defined in RS 232 This pin creates an interface from the Z8 Encore XP 8K and 4K Series products to the serial port of a host PC using minimal external hardware Two different methods for connecting the DBG pin to an RS 232 interface are depicted in Figure 24 and Figure 25 The recommended method is the buffered implementation depicted in Figure 25 The DBG pin has a internal pull up resistor which is sufficient for some appli cations for more details on the pull up current see Electrical Characteristi
82. memory and loaded into holding registers during Reset The features avail able for control through the Flash Option Bits are Watchdog Timer time out response selection interrupt or system reset Watchdog Timer always on enabled at Reset The ability to prevent unwanted read access to user code in Program Memory The ability to prevent accidental programming and erasure of all or a portion of the user code in Program Memory Voltage brownout configuration always enabled or disabled during STOP mode to re duce STOP mode power consumption Oscillator mode selection for high medium and low power crystal oscillators or external RC oscillator Factory trimming information for the internal precision oscillator and low voltage detection Factory calibration values for ADC temperature sensor and Watchdog Timer compensation Factory serialization and randomized lot identifier optional Option Bit Configuration By Reset PS022820 0307 Each time the Flash Option Bits are programmed or erased the device must be Reset for the change to take effect During any reset operation System Reset Power on Reset or Stop Mode Recovery the Flash Option Bits are automatically read from the Flash Program Memory and written to Option Configuration registers The Option Configuration registers control operation of the devices within the Z8 Encore XP 8K and 4K Series Option Bit control is established before the device exits Reset and
83. not available on the Z8FO81A Z8F041A Z8F021A and Z8F011A devices The analog supply pins AV pp and AV gs are also not available on these parts and are replaced by PB6 and PB7 At reset all Port A B and C pins default to an input state In addition any alternate functionality is not enabled so the pins function as general purpose input ports until programmed otherwise At powerup the PDO pin defaults to the RESET alternate function Pin Description Z8 Encore XP 8K and 4K Series Product Specification ZI Zi LOG The pin configurations listed are preliminary and subject to change based on manufacturing limitations VDD gt PAO TOIN TOOUT XIN DBG PA1 TOOUT XOUT ANA3 VREF CLKIN 1 PA2 RESET DEO T1OUT WORN ao N oo VSS PAS TXDO T1OUT ANAO CINP AMPOUT I PA4 RXD0 ANA1 CINN AMPINN PAS3 CTSO ANA2 COUT AMPINP T1IN Figure 2 ZaF08xA Z8F04xA Z8F02xA and Z8F01xA in 8 Pin SOIC QFN MLF S or PDIP Package PB1 ANA1 AMPINN PB2 ANA2 AMPINP PB3 CLKIN ANA3 VDD PAO TOIN TOOUT XIN PA1 TOOUT XOUT 4 vss 4 PA2 DEO PA3 CTSO PA4 RXDO OMAN DOA BRWBDHDY 20 19 18 17 16 15 14 13 12 11 L PBO ANAO AMPOUT LI PC3 COUT LED PC2 ANA6 LED L PC1 ANAS CINN LED L PCO ANA4 CINP LED DBG I RESET PDO PA7 T10UT PA6 T1IN TTOUT PAS TXDO Figure 3 Z8F08xA Z8F04xA Z8F02xA
84. only available in 28 pin packages without ADC In 28 pin packages with ADC they are replaced by AVpp and AVss UART Controllers TXDO Transmit Data This signal is the transmit output from the UART and IrDA RXDO Receive Data This signal is the receive input for the UART and IrDA CTSO Clear To Send This signal is the flow control input for the UART DE Driver Enable This signal allows automatic control of external RS 485 drivers This signal is approximately the inverse of the TXE Transmit Empty bit in the UART Status 0 register The DE signal may be used to ensure the external RS 485 driver is enabled when data is transmitted by the UART Timers TOOUT T1OUT Timer Output 0 1 These signals are outputs from the timers TOOUT T1OUT Timer Complement Output 0 1 These signals are output from the timers in PWM Dual Output mode TOIN T1IN Timer Input 0 1 These signals are used as the capture gating and counter inputs Comparator CINP CINN Comparator Inputs These signals are the positive and negative inputs to the comparator COUT Comparator Output PS022820 0307 Pin Description Z8 Encore XP 8K and 4K Series Product Specification 12 ZiLOG Table 2 Signal Descriptions Continued Signal Mnemonic VO Description Analog ANA T 0 Analog Port These signals are used as inputs to the analog to digital converter ADC VREF 1 0 Analog to digital converter reference
85. operation in progress 010xxx Page erase operation in progress 100xxx Mass erase operation in progress Flash Page Select Register PS022820 0307 The Flash Page Select FPS register shares address space with the Flash Sector Protect Register Unless the Flash controller is unlocked and written with SEH writes to this address target the Flash Page Select Register The register is used to select one of the available Flash memory pages to be programmed or erased Each Flash Page contains 512 bytes of Flash memory During a Page Erase operation all Flash memory having addresses with the most significant 7 bits given by FPS 6 0 are chosen for program erase operation Flash Memory Z8 Encore XP 8K and 4K Series Product Specification Lle ZiLOG Table 80 Flash Page Select Register FPS BITS 7 6 5 4 3 2 1 0 FIELD INFO EN PAGE RESET 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W ADDR FF9H INFO EN Information Area Enable 0 Information Area us not selected 1 Information Area is selected The Information Area is mapped into the Program Mem ory address space at addresses FEOOH through FFFFH PAGE Page Select This 7 bit field identifies the Flash memory page for Page Erase and page unlocking Program Memory Address 15 9 PAGE 6 0 For the Z8F08xx devices the upper 3 bits must be zero For the Z8F04xx devices the upper 4 bits must be zero For Z8F02xx de
86. out of Vss 120 mA 28 pin Packages Maximum Ratings at 0 C to 70 C Total power dissipation 450 mW Maximum current into Vpp or out of Vss 125 mA Operating temperature is specified in DC Characteristics 1 This voltage applies to all pins except the following Vpp AVpp pins supporting analog input Port B 5 0 Port C 2 0 and pins supporting the crystal oscillator PAO and PA1 On the 8 pin packages this applies to all pins but Vpp 2 This voltage applies to pins on the 20 28 pin packages supporting analog input Port B 5 0 Port C 2 0 and pins supporting the crystal oscillator PAO and PA1 DC Characteristics Table 127 lists the DC characteristics of the Z8 Encore XP 8K and 4K Series products All voltages are referenced to V ss the primary system ground Table 127 DC Characteristics TA 40 C to 105 C unless otherwise specified Symbol Parameter Minimum Typical Maximum Units Conditions VDD Supply Voltage 2 7 3 6 V Vina Low Level Input 0 3 0 3 Vpp V Voltage Viet High Level Input 0 7 Vpp 5 5 V Forall input pins without analog Voltage or oscillator function For all signal pins on the 8 pin devices Programmable pull ups must also be disabled Vin2 High Level Input 0 7 Vpp Vppt0 3 V For those pins with analog or Voltage oscillator function 20 28 pin devices only or when programmable pull ups are enabled PS022820 0307 Electrical Charact
87. pin package Z8F021ASB020SC 2KB 512B 64B 6 13 2 0 1 1 0 SOIC 8 pin package Z8F021ASH020SC 2KB 512B 64B 17 19 2 0 1 1 0 SOIC 20 pin package Z8F021AHHO20SC 2KB 512B 64B 17 19 2 0 1 1 0 SSOP 20 pin package Z8F021APH020SC 2KB 512B 64B 17 19 2 0 1 1 0 PDIP 20 pin package Z8F021ASJ020SC 2KB 512B 64B 25 19 2 0 1 1 0 SOIC 28 pin package Z8F021AHJ020SC 2KB 512B 64B 25 19 2 0 1 1 0 SSOP 28 pin package Z8F021APJO20SC 2KB 512B 64B 25 19 2 0 1 1 0 PDIP 28 pin package Extended Temperature 40 C to 105 C Z8F021APBO20EC 2KB 512B 64B 6 13 2 0 1 1 0 PDIP 8 pin package Z8F021AQB020EC 2KB 512B 64B 6 13 2 0 1 1 0 QFN 8 pin package Z8F021ASBO20EC 2KB 512B 64B 6 13 2 0 1 1 0 SOIC 8 pin package Z8F021ASH020EC 2KB 512B 64B 17 19 2 0 1 1 0 SOIC 20 pin package Z8F021AHHO20EC 2KB 512B 64B 17 19 2 0 1 1 0 SSOP 20 pin package Z8F021APHO20EC 2KB 512B 64B 17 19 2 0 1 1 0 PDIP 20 pin package Z8F021ASJO20EC 2KB 512B 64B 25 19 2 0 1 1 0 SOIC 28 pin package Z8F021AHJO20EC 2KB 512B 64B 25 19 2 0 1 1 0 SSOP 28 pin package Z8F021APJO20EC 2KB 512B 64B 25 19 2 0 1 1 0 PDIP 28 pin package Replace C with G for Lead Free Packaging PS022820 0307 Ordering Information Z8 Encore XP 8K and 4K Series Product Specification Ll z Zi LOG Part Number Flash amp NVDS 1 0 Lines Interrupts 16 Bit Timers w PWM 10 Bit A D Channels UART with IrDA Comparator Temperature Sensor Description Z8 Encore XP 8K and 4K Series with 1 KB Flash 10 Bit Anal
88. put is held in this register These bits are undefined after a Reset ADC Data Low Byte Register The ADC Data Low Byte ADCD_L register contains the lower bits of the ADC output as well as an overflow status bit The output is a 13 bit two s complement value During a single shot conversion this value is invalid Access to the ADC Data Low Byte register is read only Reading the ADC Data High Byte register latches data in the ADC Low Bits register Table 74 ADC Data Low Byte Register ADCD L BITS 7 6 5 4 3 2 1 0 FIELD ADCDL Reserved OVF RESET X X X X X X X X R W R R R R R R R R ADDR F73H X 7 Undefined PS022820 0307 ADCDL ADC Data Low Bits These bits are the least significant five bits of the 13 bits of the ADC output These bits are undefined after a Reset Reserved Must be undefined OVF Overflow Status 0 A hardware overflow did not occur in the ADC for the current sample 1 A hardware overflow did occur in the ADC for the current sample therefore the current sample is invalid Analog to Digital Converter Z8 Encore XP 8K and 4K Series Product Specification Z 134 ZiLOG Low Power Operational Amplifier Overview The LPO is a general purpose low power operational amplifier Each of the three ports of the amplifier is accessible from the package pins The LPO contains only one pin configu ration ANAO is the output feedback node ANA1 is the
89. r2 r1 X 3 2 POPX ER1 22 BIT p b r1 2 3 LD r1 Ir2 3 3 LD IR2 R1 3 2 LD 3 3 LD IR1 IM 4 2 LDX ER2 ER1 PS022820 0307 2 6 TRAP Vector 2 3 LD Ir1 r2 3 3 LD R2 IR1 Figure 31 First Opcode Map 3 3 3 4 BTJ p b Ir1 X Product Specification Zi LOG Opcode Maps 220 Z8 Encore XP 8K and 4K Series Product Specification Lower Nibble Hex Upper Nibble Hex 53 CPCX ER2 ER1 5 4 LDWX ER2 ER1 Figure 32 Second Opcode Map after 1FH PS022820 0307 Opcode Maps Z8 Encore XP 8K and 4K Series Product Specification Zi Zi LOG PS022820 0307 Opcode Maps Z8 Encore XP 8K and 4K Series Product Specification Electrical Characteristics VA Zi LOG The data in this chapter is pre gualification and pre characterization and is subject to change Additional electrical characteristics may be found in the individual chapters Absolute Maximum Ratings Stresses greater than those listed in Table 126 may cause permanent damage to the device These ratings are stress ratings only Operation of the device at any condition outside those indicated in the operational sections of these specifications 1s not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability For improved
90. reset value of 0001H 3 Wirite to the PWM High and Low Byte registers to set the PWM value 4 Write to the Timer Reload High and Low Byte registers to set the Reload value PWM period The Reload value must be greater than the PWM value 5 lfappropriate enable the timer interrupt and set the timer interrupt priority by writing to the relevant interrupt registers 6 Configure the associated GPIO port pin for the Timer Output alternate function 7 Write to the Timer Control register to enable the timer and initiate counting The PWM period is represented by the following equation Reload Value x Prescale PWMP mE TEE PEE E anaes System Clock Frequency Hz If an initial starting value other than 00014 is loaded into the Timer High and Low Byte registers use the ONE SHOT mode equation to determine the first PWM time out period If TPOL is set to 0 the ratio of the PWM output High time to the total period is repre sented by PWM Output High Time Ratio Reload Value PWM Value Reload Value 194 If TPOL is set to 1 the ratio of the PWM output High time to the total period is repre sented by PWM Value PWM Output High Time Ratio Yo Reload Value 100 Timers PS022820 0307 Z8 Encore XP 8K and 4K Series Product Specification Zi LOG PWM DUAL OUTPUT Mode In PWM DUAL OUTPUT mode the timer outputs a Pulse Width Modulated P WM output signal pair basic PWM signal and its complement through two GPI
91. setting up the ADC and initiating a single shot conversion are as follows 1 Enable the desired analog inputs by configuring the general purpose I O pins for alternate analog function This configuration disables the digital input and output drivers 2 Write the ADC Control Status Register 1 to configure the ADC Write to BUFMODI mode as well as Write the R EFSE H bit of the pair R EFS ELH R EFS E 2 0 to select SINGLE ENDED or DIFFERENTIAL unbuffered or buffered mode ELL to select the internal voltage reference level or to disable the internal reference The REFS is contained in the ADC Control Register 0 ELL bit 3 Write to the ADC Control Register 0 to configure the ADC and begin the conversion The bit fields in the ADC Control register can be written simultaneously the ADC can be configured and enabled with the same write instruction Analog to Digital Converter 4 Z8 Encore XP 8K and 4K Series Product Specification Zi LOG Write to the ANAIN 3 0 field to select from the available analog input sources different input pins available depending on the device Clear CONT to 0 to select a single shot conversion Ifthe internal voltage reference must be output to a pin set the REFEXT bit to 1 The internal voltage reference must be enabled in this case Write the REFSELL bit of the pair REFSELH REFSELL to select th
92. steps for configuring a timer for COUNTER mode and initiating the count are as follows 1 Write to the Timer Control register to Disable the timer Configure the timer for COUNTER mode Select either the rising edge or falling edge ofthe Timer Input signal for the count This selection also sets the initial logic level High or Low for the Timer Output alternate function However the Timer Output function is not required to be enabled 2 Write to the Timer High and Low Byte registers to set the starting count value This only affects the first pass in COUNTER mode After the first timer Reload in COUNTER mode counting always begins at the reset value of 0001H In COUNTER mode the Timer High and Low Byte registers must be written with the value 00018 3 Wirite to the Timer Reload High and Low Byte registers to set the Reload value 4 Ifappropriate enable the timer interrupt and set the timer interrupt priority by writing to the relevant interrupt registers 5 Configure the associated GPIO port pin for the Timer Input alternate function 6 Ifusing the Timer Output function configure the associated GPIO port pin for the Timer Output alternate function 7 Write to the Timer Control register to enable the timer In COUNTER mode the number of Timer Input transitions since the timer start is given by the following equation Counter Mode Timer Input Transitions Current Count Value Start Value COMPARATOR COUNTER M
93. the Interrupt Request 0 register Table 36 IRQO Enable and Priority Encoding IRQOENH x IRQOENL x Priority Description 0 0 Disabled Disabled 0 1 Level 1 Low 1 0 Level 2 Medium 1 1 Level 3 High where x indicates the register bits from 0 7 Interrupt Controller 62 Z8 Encore XP 8K and 4K Series Product Specification Zi Zi LOG Table 37 IRQO Enable High Bit Register IRQOENH BITS 7 6 5 4 3 2 1 0 FIELD Reserved TTENH TOENH UORENH UOTENH Reserved Reserved ADCENH RESET 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W ADDR FC1H Reserved Must be 0 TIENH Timer 1 Interrupt Request Enable High Bit TOENH Timer 0 Interrupt Request Enable High Bit UORENH UART 0 Receive Interrupt Request Enable High Bit UOTENH UART 0 Transmit Interrupt Request Enable High Bit ADCENH ADC Interrupt Request Enable High Bit Table 38 IRAO Enable Low Bit Register IRQOENL BITS 7 6 5 4 3 2 1 0 FIELD Reserved T1ENL TOENL UORENL UOTENL Reserved Reserved ADCENL RESET 0 0 0 0 0 0 0 0 R W R R W R W R W R W R R R W ADDR FC2H Reserved Must be 0 TIENL Timer 1 Interrupt Request Enable Low Bit TOENL Timer 0 Interrupt Request Enable Low Bit UORENL UART 0 Receive Interrupt Request Enable Low Bit UOTENL UART 0 Transmit Interrupt Request Enable Low Bit ADCENL ADC Interrupt Request
94. the interrupt requests for both vectored and polled interrupts When a request is presented to the interrupt controller the corresponding bit in the IRQO register becomes 1 If interrupts are globally enabled vec tored interrupts the interrupt controller passes an interrupt request to the eZ8 CPU If interrupts are globally disabled polled interrupts the eZ8 CPU can read the Interrupt Request 0 register to determine if any interrupt requests are pending Table 33 Interrupt Request 0 Register IRQO BITS 7 6 5 4 3 2 1 0 FIELD Reserved T1I TOl UORXI UOTXI Reserved Reserved ADCI RESET 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W ADDR FCOH Reserved Must be 0 T1I Timer 1 Interrupt Request 0 No interrupt request is pending for Timer 1 1 An interrupt request from Timer 1 is awaiting service TOI Timer 0 Interrupt Request 0 No interrupt request is pending for Timer 0 1 An interrupt request from Timer 0 is awaiting service PS022820 0307 Interrupt Controller Z8 Encore XP 8K and 4K Series Product Specification Zi Zi LOG UORKI UART 0 Receiver Interrupt Reguest 0 No interrupt request is pending for the UART 0 receiver 1 An interrupt request from the UART 0 receiver is awaiting service UOTXI UART 0 Transmitter Interrupt Request 0 No interrupt request is pending for the UART 0 transmitter 1 An interrupt request from the UART 0 trans
95. the next character is completely received gt Note In MULTIPROCESSOR mode MPEN 1 the receive data interrupts are dependent on the multiprocessor configuration and the most recent address byte A break is received An overrun is detected A data framing error is detected UART Overrun Errors When an overrun error condition occurs the UART prevents overwriting of the valid data currently in the Receive Data register The Break Detect and Overrun status bits are not displayed until after the valid data has been read After the valid data has been read the UART Status 0 register is updated to indicate the overrun condition and Break Detect if applicable The RDA bit is set to 1 to indicate that the Receive Data register contains a data byte However because the overrun error occurred this byte may not contain valid data and must be ignored The BRKD bit indi cates if the overrun was caused by a break condition on the line After reading the status byte indicating an overrun error the Receive Data register must be read again to clear the error bits is the UART Status 0 register Updates to the Receive Data register occur only when the next data word is received UART Data and Error Handling Procedure Figure 15 illustrates the recommended procedure for use in UART receiver interrupt service routines PS022820 0307 Universal Asynchronous Receiver Transmitter Z8 Encore XP 8K and 4K Series Product Specification Z
96. 0 Reset using RESET pin assertion Reset using Watchdog Timer time out Reset using the On Chip Debugger OCTCTL 1 set to 1 Reset from STOP Mode using DBG Pin driven Low Stop Mode Recovery using GPIO pin transition Stop Mode Recovery using Watchdog Timer time out oO oO o o O O ooo oo o o oO oO oO oO oo PS022820 0307 POR Power On Reset Indicator If this bit is set to 1 a Power on reset event occurs This bit is reset to 0 ifa WDT time out or Stop Mode Recovery occurs This bit is also reset to 0 when the register is read STOP Stop Mode Recovery Indicator If this bit is set to 1 a Stop Mode Recovery occurs If the STOP and WDT bits are both set to 1 the Stop Mode Recovery occurs because of a WDT time out If the STOP bit is 1 and the WDT bit is 0 the Stop Mode Recovery was not caused by a WDT time out This bit is reset by a Power on reset or a WDT time out that occurred while not in STOP mode Reading this register also resets this bit WDT Watchdog Timer Time Out Indicator If this bit is set to 1 a WDT time out occurs A POR resets this pin A Stop Mode Recov ery from a change in an input pin also resets this bit Reading this register resets this bit This read must occur before clearing the WDT interrupt EXT External Reset Indicator If this bit is set to 1 a Reset initiated by the external RESET pin occurs A Power on reset or a Stop Mode Recovery from a ch
97. 0 ANA4 0101 ANA5 0110 ANA6 0111 ANA7 1000 Reserved 1001 Reserved 1010 Reserved 1011 Reserved 1100 Hold transimpedance input nodes ANA1 and ANA2 to ground 1101 Reserved 1110 Temperature Sensor 1111 Reserved DIFFERENTIAL non inverting input and inverting input respectively 0000 ANAO and ANAI 0001 ANA2 and ANA3 0010 ANA4 and ANA5 0011 ANAI and ANAO 0100 ANA3 and ANA2 0101 ANAS and ANA4 0110 ANA6 and ANA5 0111 ANAO and ANA2 1000 ANAO and ANA3 1001 ANAO and ANA4 1010 ANAO and ANA5 1011 Reserved 1100 Reserved 1101 Reserved 1110 Reserved 1111 Manual Offset Calibration Mode Analog to Digital Converter Table 72 ADC Control Status Register 1 ADCCTL1 ADC Control Status Register 1 The ADC Control Status Register 1 ADCCTL1 configures the input buffer stage enables the threshold interrupts and contains the status of both threshold triggers It is also used to select the voltage reference configuration Z8 Encore XP 8K and 4K Series Product Specification Zi LOG BITS 7 6 5 4 3 2 1 0 FIELD REFSELH Reserved BUFMODE 2 0 RESET 1 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W ADDR F71H PS02282 REFSELH Voltage Reference Level Select High Bit in conjunction with the Low bit REFSELL in ADC Control Register 0 this determines the level of the internal voltage referenc
98. 0 C to 105 C Z8F042APBO20EC 4KB 1KB 128B 6 14 2 4 31 1 1 PDIP 8 pin package Z8F042AQBO20EC 4KB 1KB 128B 6 14 2 4 1 1 1 QFN 8 pin package Z8F042ASBO20EC 4KB 1KB 128B 6 14 2 4 1 1 1 SOIC 8 pin package Z8F042ASHO20EC 4KB 1KB 128B 17 20 2 7 31 1 1 SOIC 20 pin package Z8F042AHHO20EC 4KB 1KB 128B 17 20 2 7 1 1 1 SSOP 20 pin package Z8F042APHO20EC 4KB 1KB 128B 17 20 2 7 31 1 1 PDIP 20 pin package Z8F042ASJ020EC 4KB 1KB 128B 23 20 2 8 1 1 1 SOIC 28 pin package Z8F042AHJO20EC 4KB 1KB 128B 23 20 2 8 31 1 1 SSOP 28 pin package Z8F042APJO20EC 4KB 1KB 128B 23 20 2 8 1 1 31 PDIP 28 pin package Replace C with G for Lead Free Packaging PS022820 0307 Ordering Information Z8 Encore XP 8K and 4K Series Product Specification Zi Zi LOG 5 eo Ea G o o 2 2 S z cci t s Q 3 m E g o i y 2 9 E 92 S Ses Z8 Encore XP 8K and 4K Series with 4 KB Flash Standard Temperature 0 C to 70 C Z8F041APBO20SC 4KB 1KB 128B 6 13 2 0 1 1 0 PDIP 8 pin package Z8F041AQB020SC 4KB 1KB 128B 6 13 2 0 1 1 0 QFN 8 pin package Z8F041ASBO20SC 4KB 1KB 128B 6 13 2 0 31 1 0 SOIC 8 pin package Z8F041ASH020SC 4KB 1KB 128B 17 19 2 0 1 1 0 SOIC 20 pin package Z8F041AHHO20SC 4KB 1KB 128B 17 19 2 0 1 1 0 SSOP 20 pin package Z8F041APH020SC 4KB 1KB 128B 17 19 2 0 1 1 0 PDIP 20 pin package Z8F041ASJ020SC 4KB 1KB 128B 25 19 2 0 1 1 0 SOIC 28 pin package Z8F041AHJ020SC 4KB 1KB 128B 25
99. 07 stop mode recovery sources 28 30 using a GPIO port pin transition 29 30 using watch dog timer time out 29 SUB 205 subtract 205 subtract extended addressing 205 subtract with carry 205 subtract with carry extended addressing 205 SUBX 205 SWAP 209 swap nibbles 209 Index symbols additional 204 T TCM 206 TCMX 206 Technical Support 273 test complement under mask 206 test complement under mask extended ad dressing 206 test under mask 206 test under mask extended addressing 206 timer signals 11 timers 69 architecture 69 block diagram 70 capture mode 77 78 85 capture compare mode 81 85 compare mode 79 85 continuous mode 71 84 counter mode 72 73 counter modes 84 gated mode 80 85 one shot mode 70 84 operating mode 70 PWM mode 74 76 84 85 reading the timer count values 82 reload high and low byte registers 87 timer control register definitions 83 timer output signal operation 82 timers 0 3 control registers 83 84 high and low byte registers 87 88 TM 206 TMX 206 transmit IrDA data 118 transmitting UART data polled method 99 transmitting UART dat interrupt driven method 100 TRAP 208 PS022820 0307 Z8 Encore XP 8K and 4K Series Product Specification Zi Zi LOG U UART 7 architecture 97 baud rate generator 107 baud rates table 115 control register definitions 108 controller signals 11 data format 98 interrupts 105 multiprocessor mode 103 receiving data using interrupt driven meth
100. 1 2 3 r OE FE 1 2 INCW dst dst lt dst 1 RR AO mS 5 om gn 2 5 IRR A1 2 6 IRET FLAGS SP BF REL EN EE 1 5 SP SP 1 PC SP SP lt SP 2 IRQCTL 7 1 JP dst PC c dst DA 8D 3 2 IRR C4 2 3 JP cc dst if cc is true DA OD FD 3 2 PC lt dst JR dst PC lt PC X DA 8B 2 2 JR cc dst if cc is true DA OB FB 2 2 PC lt PC X LD dst rc dst lt src r IM OC FC 2 2 r X r C7 3 3 X r r D7 3 4 r Ir E3 2 3 R R E4 3 2 R IR E5 3 4 R IM E6 3 2 IR IM E7 3 3 Ir r F3 2 3 IR R F5 3 3 Flags Notation Value is a function of the result of the operation Unaffected X Undefined 0 Reset to 0 1 Setto 1 PS022820 0307 eZ8 CPU Instruction Set Z8 Encore XP 8K and 4K Series Product Specification Li z ZiLOG Table 124 eZ8 CPU Instruction Summary Continued Assembly Symbolic Addresa Mode Te pigs Fetch Instr Mnemonic Operation dst src Hex C Z S V D H Cycles Cycles LDC dst src dst src r Irr C2 SoS eS ux m 2 5 Ir Irr C5 2 9 Irr r D2 2 5 LDCI dst src dst src Ir Irr C3 Soe Se ke Ss d 2 9 od Ir dr D3 2 9 LDE dst src dst lt src r Irr 82 2 5 Irr r 92 2 5 LDEI dst src dst src Ir Irr 83 lOS 2 9 d Ir dr 93 2 9 LDWX dst src dst lt src ER ER 1FE8 See B a 5 4 LDX dst src dst lt src r ER 84 3 2 Ir ER 85 3 3 R IRR
101. 12 bit temperature sensor offset calibration value For usage details see Temperature Sensor Operation on page 139 Table 96 Temperature Sensor Calibration Low Byte at 003B TSCALL BITS 7 6 5 4 3 2 1 0 FIELD TSCALL RESET U U U U U U U U R W R W R W R W R W R W R W R W R W ADDR Information Page Memory 003B Note U Unchanged by Reset R W Read Write TSCALL Temperature Sensor Calibration Low Byte The TSCALH and TSCALL bytes combine to form the 12 bit temperature sensor offset calibration value For usage details see Temperature Sensor Operation on page 139 Watchdog Timer Calibration Data Table 97 Watchdog Calibration High Byte at 007EH WDTCALH BITS 7 6 5 4 3 2 1 0 FIELD WDTCALH RESET U U U U U U U U R W R W R W R W R W R W R W R W R W ADDR Information Page Memory 007EH Note U Unchanged by Reset R W Read Write PS022820 0307 Flash Option Bits Z8 Encore XP 8K and 4K Series Product Specification Zi LOG WDTCALH Watchdog Timer Calibration High Byte The WDTCALH and WDTCALL bytes when loaded into the watchdog timer reload reg Isters result in a one second timeout at room temperature and 3 3V supply voltage To use the Watchdog Timer calibration user code must load WDTU with 0x00 WDTH with WDTCALH and WDTL with WDTCALL Table 98 Watc
102. 2 8 kHz using the OSCSEL bits in the Oscillator Control on page 187 PS022820 0307 Internal Precision Oscillator Z8 Encore XP 8K and 4K Series Product Specification AR ZiLOG PS022820 0307 Internal Precision Oscillator Z8 Encore XP 8K and 4K Series Product Specification AE Zi LOG eZ8 CPU Instruction Set Assembly Language Programming Introduction The eZ8 CPU assembly language provides a means for writing an application program without concern for actual memory addresses or machine instruction formats A program written in assembly language is called a source program Assembly language allows the use of symbolic addresses to identify memory locations It also allows mnemonic codes opcodes and operands to represent the instructions themselves The opcodes identify the instruction while the operands represent memory locations registers or immediate data values Each assembly language program consists of a series of symbolic commands called statements Each statement can contain labels operations operands and comments Labels can be assigned to a particular instruction step in a source program The label identifies that step in the program as an entry point for use by other instructions The assembly language also includes assembler directives that supplement the machine instruction The assembler directives or pseudo ops are not translated into a machine instruction Rather the pseudo ops are interpreted as di
103. 203 immediate operand prefix 204 PS022820 0307 Z8 Encore XP 8K and 4K Series Product Specification Zi Zi LOG INC 205 increment 205 increment word 205 INCW 205 indexed 203 indirect address prefix 204 indirect register 203 indirect register pair 203 indirect working register 203 indirect working register pair 203 infrared encoder decoder IrDA 117 Instruction Set 201 instruction set ez8 CPU 201 instructions ADC 205 ADCX 205 ADD 205 ADDX 205 AND 207 ANDX 207 arithmetic 205 BCLR 206 BIT 206 bit manipulation 206 block transfer 206 BRK 208 BSET 206 BSWAP 206 208 BTJ 208 BTJNZ 208 BTJZ 208 CALL 208 CCF 206 CLR 207 COM 207 CP 205 CPC 205 CPCX 205 CPU control 206 CPX 205 DA 205 DEC 205 DECW 205 DI 206 Index DJNZ 208 EI 206 HALT 206 INC 205 INCW 205 IRET 208 JP 208 LD 207 LDC 207 LDCI 206 207 LDE 207 LDEI 206 LDX 207 LEA 207 logical 207 MULT 205 NOP 206 OR 207 ORX 207 POP 207 POPX 207 program control 208 PUSH 207 PUSHX 207 RCF 206 RET 208 RL 208 RLC 208 rotate and shift 208 RR 208 RRC 208 SBC 205 SCF 206 SRA 208 SRL 209 SRP 207 STOP 207 SUB 205 SUBX 205 SWAP 209 TCM 206 TCMX 206 TM 206 TMX 206 PS022820 0307 Z8 Encore XP 8K and 4K Series Product Specification Zi Zi LOG TRAP 208 watch dog timer refresh 207 XOR 208 XORX 208 instructions eZ8 classes of 204 interrupt control register 67 interrupt controller 55 architec
104. 4 0000H 07FFH 512 Z8F01xA 1 1024 2 0000H 03FFH 512 Flash Memory 8 KB Flash Program Memory Addresses hex Sector 5 Sector 4 Sector 2 Sector 1 Sector 0 1FFF Sector 7 1C00 1BFF Sector 6 1800 17FF 1400 13FF 1000 OFFF 0C00 OBFF 0800 O7FF 0400 O3FF 0000 Z8 Encore XP 8K and 4K Series Product Specification Z 142 Zi LOG 4 KB Flash Program Memory 2KB ian rogram Memory Pai hex Addresses hex O7FF Sector 7 Sector 3 NA 0E00 O5FF ODFF Sector 2 Sector 6 asus oe Sector 1 OBFF 0200 O1FF Sector 5 T Bastard O9FF 0000 Sector 4 0800 O7FF 1 KB Flash 0600 Program Memory Addresses hex E OSFF O3FF bind 0400 Sector 1 0200 O3FF O1FF Sector 1 Sector 0 O1FF Sector 0 0000 Figure 21 Flash Memory Arrangement Flash Information Area PS022820 0307 The Flash information area is separate from program memory and is mapped to the address range F EOOH to FFFFH This area is readable but cannot be erased or overwritten Factory trim values for the analog peripherals are stored here Factory calibration data for the ADC is also stored here Flash Memory Operation PS022820 0307 Z8 Encore XP 8K and 4K Series Product Specification Z 143 Zi LOG The Flash Controller programs and erases Flash memory The Flash Controller provides the proper Flash controls and timing for
105. 8 Encore MC Crimzon eZ80 and ZNEO are trademarks or registered trademarks of ZiLOG Inc All other products and or service names mentioned herein may be trademarks of the companies with which they are associated PS022820 0307 Z8 Encore XP 8K and 4K Series Product Specification ZiLOG Revision History Each instance in the following table reflects a change to this document from its previous revision For more details refer to the corresponding pages and appropriate links given in the table below Revision Date Level Description Page No March 20 Clarified the location of bits in the registers TXCTLO and TxCTL1 in 86 2007 Timers chapter Added the ISO logo in Document Disclaimer section Other style ii 273 updates in Document Disclaimer section and Customer Support chapter Added a warning for the XTLDIS bit description under Table 87 in 158 Flash Option Bits chapter December 19 Updated Step 3 in UART Baud Rate Generator section Changed the 108 140 2006 temperature sensor calibration value TSCAL to 12 bits in and 164 Temperature Sensor and Flash Option Bits chapters Removed the maximum values for the Ipp Stop current from Table 128 226 in the Electrical Characteristics chapter Included Green PSI number added Ethernet Smart Cable and 261 262 updated the number of interrupts in the Ordering Information chapter December 18 Removed the invalid sentence Resistor R1 is optional and limits tot
106. 85 capture compare 85 continuous 84 counter 84 gated 85 one shot 84 PWM 84 85 modes 85 PS022820 0307 Z8 Encore XP 8K and 4K Series Product Specification Zi Zi LOG MULT 205 multiply 205 multiprocessor mode UART 103 N NOP no operation 206 notation b 203 cc 203 DA 203 ER 203 IM 203 IR 203 Ir 203 IRR 203 Irr 203 p 203 R 203 r 203 RA 203 RR 203 rr 203 vector 203 X 203 notational shorthand 203 O OCD architecture 173 auto baud detector generator 176 baud rate limits 177 block diagram 173 breakpoints 178 commands 179 control register 184 data format 176 DBG pin to RS 232 Interface 174 debug mode 175 debugger break 208 interface 174 serial errors 177 status register 185 Index timing 239 OCD commands execute instruction 12H 183 read data memory 0DH 182 read OCD control register 05H 181 read OCD revision 00H 180 read OCD status register 02H 180 read program counter 07H 181 read program memory 0BH 182 read program memory CRC OEH 183 read register 09H 181 read runtime counter 03H 180 step instruction 10H 183 stuff instruction 11H 183 write data memory 0CH 182 write OCD control register 04H 180 write program counter 06H 181 write program memory 0AH 182 write register 08H 181 on chip debugger OCD 173 on chip debugger signals 12 on chip oscillator 193 one shot mode 84 opcode map abbreviations 219 cell description 218 first 220 sec
107. ADC The response of the ADC in all modes is limited by the input signal bandwidth and the latency Follow these steps for setting up the ADC and initiating continuous conversion 1 2 PS022820 0307 Enable the desired analog input by configuring the general purpose I O pins for alternate function This action disables the digital input and output driver Write the ADC Control Status Register 1 to configure the ADC Write to BUFMODE 2 0 to select SINGLE ENDED or DIFFERENTIAL mode as well as unbuffered or buffered mode Analog to Digital Converter 124 Z8 Encore XP 8K and 4K Series Product Specification 125 Zi LOG Write the REFSELH bit of the pair REFSELH REFSELL to select the internal voltage reference level or to disable the internal reference The REFSELL bit is contained in the ADC Control Register 0 3 Write to the ADC Control Register 0 to configure the ADC for continuous conversion The bit fields in the ADC Control register may be written simultaneously Write to the ANAIN 3 0 field to select from the available analog input sources different input pins available depending on the device Set CONT to 1 to select continuous conversion Ifthe internal VREF must be output to a pin set the REFEXT bit to 1 The internal voltage reference must be enabled in this case Write the REFSELL bit of the pair REFSELH REFSELL to select the internal voltage refere
108. Addressing TM dst src Test Under Mask TMX dst src Test Under Mask using Extended Addressing Table 118 Block Transfer Instructions Mnemonic Operands Instruction LDCI dst src Load Constant to from Program Memory and Auto Increment Addresses LDEI dst src PS022820 0307 Load External Data to from Data Memory and Auto Increment Addresses Table 119 CPU Control Instructions Mnemonic Operands Instruction ATM Atomic Execution CCF Complement Carry Flag DI Disable Interrupts EI Enable Interrupts HALT Halt Mode NOP No Operation RCF Reset Carry Flag SCF Set Carry Flag eZ8 CPU Instruction Set Z8 Encore XP 8K and 4K Series Product Specification Zi Zi LOG Table 119 CPU Control Instructions Continued Mnemonic Operands Instruction SRP src Set Register Pointer STOP STOP Mode WDT Watchdog Timer Refresh Table 120 Load Instructions Mnemonic Operands Instruction CLR dst Clear LD dst src Load LDC dst src Load Constant to from Program Memory LDCI dst src Load Constant to from Program Memory and Auto Increment Addresses LDE dst src Load External Data to from Data Memory LDEI dst src Load External Data to from Data Memory and Auto Increment Addresses LDWX dst src Load Word using Extended Addressing LDX dst src Load using Extended Addressing LEA dst X src Load Effectiv
109. Byte Register UOBRL BITS 7 6 5 4 3 2 1 0 FIELD BRL RESET 1 1 1 1 1 1 1 1 R W R W R W R W R W R W R W R W R W ADDR F47H The UART data rate is calculated using the following equation System Clock Frequency Hz ART Baud Rat it aut Rate bitsa 16 x UART Baud Rate Divisor Value For a given UART data rate calculate the integer baud rate divisor value using the follow ing equation Universal Asynchronous Receiver Transmitter Z8 Encore XP 8K and 4K Series Product Specification Li n Zi LOG System Clock Freguency 1 ART Baud Rate Divi Val BR y aud Rate Divisor Value BRG Round 16 x UART Data Rate bits s The baud rate error relative to the acceptable baud rate is calculated using the following equation Actual Data Rate Desired Data suo ART B R E 1 B aud Rate Error 8 a Desired Data Rate For reliable communication the UART baud rate error must never exceed 5 percent Table 70 provides information about data rate errors for popular baud rates and commonly used crystal oscillator frequencies Table 70 UART Baud Rates 10 0 MHz System Clock 5 5296 MHz System Clock Acceptable BRGDivisor Actual Rate Error Acceptable BRGDivisor Actual Rate Error Rate kHz Decimal kHz Rate kHz Decimal kHz 1250 0 N A N A N A 1250 0 N A N A N A 625 0 1 625 0 0 00 625 0 N A N A N A 250 0 3 208 33 16 67
110. C the parasitic capacitance of the oscillator XIN pin and the printed circuit board must be included in the estimation of the oscillator frequency It is possible to operate the RC oscillator using only the parasitic capacitance of the pack age and printed circuit board To minimize sensitivity to external parasitics external capacitance values in excess of 20 pF are recommended 4000 3750 3500 3250 3000 2750 2500 2250 2000 1750 Frequency kHz 1500 1250 1000 750 500 250 0 0 20 40 60 80 100 120 140 160 180 200 220 240 260 280 300 320 340 360 380 400 420 440 460 480 500 C pF Figure 29 Typical RC Oscillator Frequency as a Function of the External Capacitance with a 45 KOhm Resistor PS022820 0307 Crystal Oscillator PS022820 0307 Z8 Encore XP 8K and 4K Series Product Specification VAR ZiLOG When using the external RC oscillator mode the oscillator can stop oscillating if the power supply drops below 2 7 V but before the power supply drops to the voltage brownout threshold The oscillator resumes oscillation when the supply voltage exceeds 2 7 V Crystal Oscillator Z8 Encore XP 8K and 4K Series Product Specification Z Zi LOG PS022820 0307 Crystal Oscillator Z8 Encore XP 8K and 4K Series Product Specification Z Zi LOG Internal Precision Oscillator The internal precision oscillator IPO is designed
111. D Byte 11 6E FE6E Randomized Lot ID Byte 10 70 FE70 Randomized Lot ID Byte 9 71 FE71 Randomized Lot ID Byte 8 73 FE73 Randomized Lot ID Byte 7 74 FE74 Randomized Lot ID Byte 6 76 FE76 Randomized Lot ID Byte 5 77 FE77 Randomized Lot ID Byte 4 79 FE79 Randomized Lot ID Byte 3 TA FE7A Randomized Lot ID Byte 2 7C FE7C Randomized Lot ID Byte 1 7D FE7D Randomized Lot ID Byte 0 least significant PS022820 0307 Flash Option Bits Z8 Encore XP 8K and 4K Series Product Specification Z Zi LOG PS022820 0307 Flash Option Bits Z8 Encore XP 8K and 4K Series Product Specification Z Zi LOG Non Volatile Data Storage The Z8 Encore KP 4K Series devices contain a non volatile data storage NVDS element of up to 128 bytes This memory can perform over 100 000 write cycles Operation The NVDS is implemented by special purpose ZILOG software stored in areas of program memory which are not user accessible These special purpose routines use the Flash memory to store the data The routines incorporate a dynamic addressing scheme to maximize the write erase endurance of the Flash gt Note Different members of the Z8 Encore XP 4K Series feature multiple NVDS array sizes See Z8 Encore XP 8K and 4K Series Family Part Selection Guide on page 3 for details Also note that those members containing 8 KB of flash memory do not include the NVDS feature NVDS Code Interface Two routines are required to access the NVDS a write routine
112. D6 D7 STOP Figure 26 OCD Data Format gt Note When responding to a request for data the OCD may commence transmitting immediately after receiving the stop bit of an incoming frame Therefore when sending the stop bit the host must not actively drive the DBG pin High for more than 0 5 bit times It is recom mended that 1f possible the host drives the DBG pin using an open drain output to avoid this issue OCD Auto Baud Detector Generator To run over a range of baud rates data bits per second with various system clock frequencies the On Chip Debugger contains an Auto Baud Detector Generator After a reset the OCD is idle until it receives data The OCD requires that the first character sent from the host 1s the character 80H The character 80H has eight continuous bits Low one Start bit plus 7 data bits framed between High bits The Auto Baud Detector measures this period and sets the OCD Baud Rate Generator accordingly The Auto Baud Detector Generator is clocked by the system clock The minimum baud rate is the system clock frequency divided by 512 For optimal operation with PS022820 0307 On Chip Debugger Z8 Encore XP 8K and 4K Series Product Specification 177 Zi LOG asynchronous datastreams the maximum recommended baud rate is the system clock frequency divided by 8 The maximum possible baud rate for asynchronous datastreams is the system clock frequency divided by 4 but this theoretical maximum is possib
113. DC reference is buffered and driven out to the Vref pin AN Warning When the ADC is used with an external reference REFSELH REFSELL 00 the PS022820 0307 REFOUT bit must be set to 0 CONT 0 Single shot conversion ADC data is output once at completion of the 5129 system clock cycles measurements of the internal temperature sensor take twice as long 1 Continuous conversion ADC data updated every 256 system clock cycles after an initial 5129 clock conversion measurements of the internal temperature sensor take twice as long Analog to Digital Converter PS022820 0307 Z8 Encore XP 8K and 4K Series Product Specification 131 Zi LOG ANAIN 3 0 Analog Input Select These bits select the analog input for conversion Not all Port pins in this list are available in all packages for the Z8 Encore XP 8K and 4K Series See chapter Pin Description on page 9 for information regarding the port pins available with each package style Do not enable unavailable analog inputs Usage of these bits changes depending on the buffer mode selected in ADC Control Status Register 1 For the reserved values all input switches are disabled to avoid leakage or other undesir able operation ADC samples taken with reserved bit settings are undefined SINGLE ENDED 0000 ANAO transimpedance amp output when enabled 0001 ANA transimpedance amp inverting input 0010 ANA2 transimpedance amp non inverting input 0011 ANA3 010
114. Data register clears this bit 0 No framing error occurred 1 A framing error occurred Universal Asynchronous Receiver Transmitter 111 Z8 Encore XP 8K and 4K Series Product Specification Zi LOG BRKD Break Detect This bit indicates that a break occurred If the data bits parity multiprocessor bit and Stop bit s are all Os this bit is set to 1 Reading the UART Receive Data register clears this bit 0 No break occurred 1 A break occurred TDRE Transmitter Data Register Empty This bit indicates that the UART Transmit Data register is empty and ready for additional data Writing to the UART Transmit Data register resets this bit 0 Do not write to the UART Transmit Data register 1 The UART Transmit Data register is ready to receive an additional byte to be transmit ted TXE Transmitter Empty This bit indicates that the transmit shift register is empty and character transmission is fin ished 0 Data is currently transmitting 1 Transmission is complete CTS CTS signal When this bit is read it returns the level of the CTS signal This signal is active Low UART Status 1 Register This register contains multiprocessor control and status bits Table 64 UART Status 1 Register UOSTAT1 BITS 7 6 5 4 3 2 1 0 FIELD Reserved NEWFRM MPRX RESET 0 0 0 0 0 0 0 0 R W R R R R R W R W R R ADDR F44H PS022820 0307 Reserved Must be 0 NEWFR
115. Description Register AFS1 Ars2 Port A Reserved AFS2 5 1 AFS1 5 0 Cont Analog Functions ADC Comparator Input P LPO AFS2 5 1 AFS1 5 1 Output Analog Functions include ADC inputs ADC reference comparator inputs and LPO ports Note Also alternate function selection as described in Port A D Alternate Function Sub Registers on page 48 must be enabled GPIO Interrupts Many of the GPIO port pins can be used as interrupt sources Some port pins can be con figured to generate an interrupt request on either the rising edge or falling edge of the pin input signal Other port pin interrupt sources generate an interrupt when any edge occurs both rising and falling See chapter Interrupt Controller on page 55 for more information about interrupts using the GPIO pins GPIO Control Register Definitions Four registers for each Port provide access to GPIO control input data and output data Table 16 lists these Port registers Use the Port A D Address and Control registers together to provide access to sub registers for Port configuration and control Table 16 GPIO Port Registers and Sub Registers Port Register Mnemonic Port Register Name PxADDR Port A D Address Register Selects sub registers PxCTL Port A D Control Register Provides access to sub registers PxIN Port A D Input Data Register PxOUT Port A D Output Data Register Port Sub Register Mnemonic Port Register Name PxDD Data Direction
116. E bit If the CTS signal is low and the CTSE bitis 1 the transmitter is enabled 0 Transmitter disabled 1 Transmitter enabled REN Receive Enable This bit enables or disables the receiver 0 Receiver disabled 1 Receiver enabled CTSE CTS Enable 0 The CTS signal has no effect on the transmitter 1 The UART recognizes the CTS signal as an enable control from the transmitter PEN Parity Enable This bit enables or disables parity Even or odd is determined by the PSEL bit 0 Parity is disabled 1 The transmitter sends data with an additional parity bit and the receiver receives an additional parity bit PSEL Parity Select 0 Even parity is transmitted and expected on all received data 1 Odd parity is transmitted and expected on all received data SBRK Send Break This bit pauses or breaks data transmission Sending a break interrupts any transmission in progress so ensure that the transmitter has finished sending data before setting this bit 0 No break is sent 1 Forces a break condition by setting the output of the transmitter to zero STOP Stop Bit Select 0 The transmitter sends one stop bit 1 The transmitter sends two stop bits LBEN Loop Back Enable 0 Normal operation 1 All transmitted data is looped back to the receiver Table 62 UART Control 1 Register UOCTL1 BITS 7 6 5 4 3 2 1 0 FIELD MPMD 1 MPEN MPMD 0 MPBT
117. EN bits in the UART Control 0 register to 0 2 Load the acceptable 16 bit count value into the UART Baud Rate High and Low Byte registers 3 Enable the Baud Rate Generator timer function and associated interrupt by setting the BRGCTL bit in the UART Control 1 register to 1 When configured as a general purpose timer the interrupt interval is calculated using the following equation Interrupt Interval s System Clock Period s XBRG 15 0 UART Control Register Definitions The UART control registers support the UART and the associated Infrared Encoder Decoders For more information about the infrared operation refer to Infrared Encoder Decoder chapter on page 117 UART Control 0 and Control 1 Registers The UART Control 0 UxCTLO and Control 1 UxCTL 1 registers Table 61 and Table 62 configure the properties of the UART s transmit and receive operations The UART Control registers must not be written while the UART is enabled Table 61 UART Control 0 Register UOCTLO BITS 7 6 5 4 3 2 1 0 FIELD TEN REN CTSE PEN PSEL SBRK STOP LBEN RESET 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W ADDR F42H PS022820 0307 Universal Asynchronous Receiver Transmitter 108 Z8 Encore XP 8K and 4K Series Product Specification 109 Zi LOG TEN Transmit Enable This bit enables or disables the transmitter The enable is also controlled by the CTS signal and the CTS
118. F Flash Device Family Z8 ZiLOG s 8 Bit Microcontroller PS022820 0307 Ordering Information Index Symbols 204 204 204 Numerics 10 bit ADC 7 40 lead plastic dual inline package 250 251 A absolute maximum ratings 223 AC characteristics 229 ADC 205 architecture 121 automatic power down 122 block diagram 122 continuous conversion 124 control register 130 132 control register definitions 130 data high byte register 132 data low bits register 133 electrical characteristics and timing 233 operation 122 single shot conversion 123 ADCCTL register 130 132 ADCDH register 132 ADCDL register 133 ADCX 205 ADD 205 add extended addressing 205 add with carry 205 add with carry extended addressing 205 additional symbols 204 address space 15 ADDX 205 analog signals 12 analog to digital converter ADC 121 AND 207 PS022820 0307 Z8 Encore XP 8K and 4K Series Product Specification Zi Zi LOG ANDX 207 arithmetic instructions 205 assembly language programming 201 assembly language syntax 202 B B 204 b 203 baud rate generator UART 107 BCLR 206 binary number suffix 204 BIT 206 bit 203 clear 206 manipulation instructions 206 set 206 set or clear 206 swap 206 test and jump 208 test and jump if non zero 208 test and jump if zero 208 bit jump and test if non zero 208 bit swap 208 block diagram 4 block transfer instructions 206 BRK 208 BSET 206 BSWAP 206 208 BTJ 208 B
119. F6 AF5 AF4 AF3 AF2 AF 1 AFO RESET 00H Ports A C 01H Port D 04H Port A of 8 pin device R W RAW ADDR If 02H in Port A D Address Register accessible through the Port A D Control Register PS022820 0307 AF 7 0 Port Alternate Function enabled 0 The port pin is in normal mode and the DDx bit in the Port A D Data Direction sub register determines the direction of the pin 1 The alternate function selected through Alternate Function Set sub registers is enabled Port pin operation is controlled by the alternate function Port A D Output Control Sub Registers The Port A D Output Control sub register Table 21 is accessed through the Port A D Control register by writing 03H to the Port A D Address register Setting the bits in the Port A D Output Control sub registers to 1 configures the specified port pins for open drain operation These sub registers affect the pins directly and as a result alternate func tions are also affected General Purpose Input Output Z8 Encore XP 8K and 4K Series Product Specification ZI Zi LOG Table 21 Port A D Output Control Sub Registers PxOC BITS 7 6 5 4 3 2 1 0 FIELD POC7 POC6 POC5 POCA POC3 POC2 POC1 POCO RESET OOH Ports A C 01H Port D R W R W R W R W R W R W R W R W R W ADDR If O3H in Port A D Address Register accessible through the Port A D Control Register POC 7 0 Port Output Control These bits function i
120. H to the Watchdog Timer Control register WDTCTL 2 Write AAH to the Watchdog Timer Control register WDTCTL 3 Write the Watchdog Timer Reload Upper Byte register WDTU with the desired time out value 4 Write the Watchdog Timer Reload High Byte register WDTH with the desired time out value Watchdog Timer 93 Z8 Encore XP 8K and 4K Series Product Specification 94 Zi LOG 5 Write the Watchdog Timer Reload Low Byte register WDTL with the desired time out value All three Watchdog Timer Reload registers must be written in the order just listed There must be no other register writes between each of these operations If a register write occurs the lock state machine resets and no further writes can occur unless the sequence is restarted The value in the Watchdog Timer Reload registers is loaded into the counter when the Watchdog Timer is first enabled and every time a WDT instruction is executed Watchdog Timer Calibration Due to its extremely low operating current the Watchdog Timer oscillator is somewhat inaccurate This variation can be corrected using the calibration data stored in the Flash Information Page see Table 97 and Table 98 on page 165 Loading these values into the Watchdog Timer Reload Registers results in a one second timeout at room temperature and 3 3 V supply voltage Timeouts other than one second may be obtained by scaling the calibration values up or down as required Note that the Watchdog
121. Impedance 150 kQ In unbuffered mode at 20 MHz 10 MO In buffered modes Vin Input Voltage Range 0 Vbpp V Unbuffered Mode 0 3 Vpp 1 1 V Buffered Modes Note these values define the range over which the ADC performs within spec exceeding these values does not cause damage or instability see DC Characteristics on page 224 for absolute pin voltage limits Notes 1 Analog source impedance affects the ADC offset voltage because of pin leakage and input settling time Devices are factory calibrated at Vpp 3 3 V and TA 30 C so the ADC is maximally accurate under these conditions LSBs are defined assuming 10 bit resolution This is the maximum recommended resistance seen by the ADC input pin 5 The input impedance is inversely proportional to the system clock frequency PS022820 0307 Electrical Characteristics Z8 Encore XP 8K and 4K Series Product Specification Zi Zi LOG Table 136 Low Power Operational Amplifier Electrical Characteristics Vpp 2 7 to 3 6 V TA 40 C to 4105 C Symbol Parameter Minimum Typical Maximum Units Conditions Av Open loop voltage gain 80 dB GBW Gain Bandwidth product 500 kHz PM Phase Margin 50 deg jAssuming 13 pF load capacitance Vos ipo Input Offset Voltage 1 4 mV Vosa po Input Offset Voltage 1 10 uV C Temperature Drift VIN Input Voltage Range 0 3 Vdd 1 V Vout Output Voltage Range 0 3 Vdd 1 V lout 45 pA
122. KB 1KB 0 17 20 2 7 1 1 1 SSOP 20 pin package Z8F082APHO20EC 8KB 1KB 0 17 20 2 7 1 1 1 PDIP 20 pin package Z8F082ASJO20EC 8KB 1KB 0 23 20 2 8 31 1 1 SOIC 28 pin package Z8F082AHJ020EC 8KB 1KB 0 23 20 2 8 1 1 1 SSOP 28 pin package Z8F082APJO20EC 8KB 1KB 0 23 20 2 8 1 1 1 PDIP 28 pin package Replace C with G for Lead Free Packaging PS022820 0307 Ordering Information Z8 Encore XP 8K and 4K Series Product Specification Z 254 Zi LOG 5 eo Ea G o o 2 2 S z cci t g O 4 MO E E o i 2 2 9 E 92 S Ses Z8 Encore XP 8K and 4K Series with 8 KB Flash Standard Temperature 0 C to 70 C Z8F081APB020SC 8KB 1KB 0 6 13 2 0 1 1 0 PDIP 8 pin package Z8F081AQB020SC 8KB 1KB 0 6 13 2 0 1 1 0 QFN 8 pin package Z8F081ASB020SC 8KB 1KB 0 6 13 2 0 1 1 0 SOIC 8 pin package Z8F081ASH020SC 8KB 1KB 0 17 19 2 0 1 1 0 SOIC 20 pin package Z8F081AHH020SC 8KB 1KB 0 17 19 2 0 1 1 0 SSOP 20 pin package Z8F081APH020SC 8KB 1KB 0 17 19 2 0 1 1 0 PDIP 20 pin package Z8F081ASJ020SC 8KB 1KB 0 25 19 2 0 1 1 0 SOIC 28 pin package Z8F081AHJ020SC 8KB 1KB 0 25 19 2 0 1 1 0 SSOP 28 pin package Z8F081APJ020SC 8KB 1KB 0 25 19 2 0 1 1 0 PDIP 28 pin package Extended Temperature 40 C to 105 C Z8F081APBO20EC 8KB 1KB 0 6 13 2 0 1 1 0 PDIP 8 pin package Z8F081AQB020EC 8KB 1KB 0 6 13 2 0 1 1 0 QFN 8 pin package Z8F081ASBO20EC 8KB 1KB 0 6 13 2 0 1 1 0 SOIC 8 pin package Z8F081ASHO20EC
123. M Status bit denoting the start of a new frame Reading the UART Receive Data register resets this bit to 0 0 The current byte is not the first data byte of a new frame 1 The current byte is the first data byte of a new frame MPRX Multiprocessor Receive Returns the value of the most recent multiprocessor bit received Reading from the UART Receive Data register resets this bit to 0 Universal Asynchronous Receiver Transmitter 112 UART Transmit Data Register Z8 Encore XP 8K and 4K Series Product Specification Z4 Zi LOG Data bytes written to the UART Transmit Data UxTXD register Table 65 are shifted out on the TXDx pin The Write only UART Transmit Data register shares a Register File address with the read only UART Receive Data register Table 65 UART Transmit Data Register UOTXD BITS 7 6 5 4 2 1 0 FIELD TXD RESET X X X X X X X R W W W W W W W W ADDR F40H UART Receive Data Register TXD Transmit Data UART transmitter data byte to be shifted out through the TXDx pin Data bytes received through the RXDx pin are stored in the UART Receive Data UxRXD register Table 66 The read only UART Receive Data register shares a Regis ter File address with the Write only UART Transmit Data register Table 66 UART Receive Data Register UORXD BITS 7 6 5 4 2 1 0 FIELD RXD RESET X X X
124. O Port pins The timer input is the system clock The timer first counts up to the 16 bit PWM match value stored in the Timer PWM High and Low Byte registers When the timer count value matches the PWM value the Timer Output toggles The timer continues counting until it reaches the Reload value stored in the Timer Reload High and Low Byte registers Upon reaching the Reload value the timer generates an interrupt the count value in the Timer High and Low Byte registers is reset to 0001H and counting resumes If the TPOL bit in the Timer Control register is set to 1 the Timer Output signal begins as a High 1 and transitions to a Low 0 when the timer value matches the PWM value The Timer Output signal returns to a High 1 after the timer reaches the Reload value and is reset to 0001H If the TPOL bit in the Timer Control register is set to 0 the Timer Output signal begins as a Low 0 and transitions to a High 1 when the timer value matches the PWM value The Timer Output signal returns to a Low 0 after the timer reaches the Reload value and is reset to 0001H The timer also generates a second PWM output signal Timer Output Complement The Timer Output Complement is the complement of the Timer Output PWM signal A programmable deadband delay can be configured to time delay 0 to 128 system clock cycles PWM output transitions on these two pins from a low to a high inactive to active This ensures a time gap between the deassertion of on
125. Oscillator cycles TsMR Stop Mode Recovery 16 Hs 66 Internal Precision with crystal oscillator Oscillator cycles disabled TsMR Stop Mode Recovery 1 ms 5000 Internal Precision with crystal oscillator Oscillator cycles enabled Tygo Voltage Brown Out 10 us Period of time in which Vpp Pulse Rejection Period lt Vypo without generating a Reset Tramp Time for Vpp to 0 10 100 ms transition from Vas to Vpor to ensure valid Reset Tsmp Stop Mode Recovery 20 ns For any SMR pin or for the Reset pin when it is asserted in STOP mode 1 Data in the typical column is from characterization at 3 3 V and 30 C These values are provided for design guidance only and are not tested in production PS022820 0307 Electrical Characteristics Table 132 Flash Memory Electrical Characteristics and Timing Z8 Encore XP 8K and 4K Series Product Specification Zi Zi LOG Vpp 2 7 to 3 6 V TA 40 C to 105 C unless otherwise stated Parameter Minimum Typical Maximum Units Notes Flash Byte Read Time 100 ns Flash Byte Program Time 20 40 us Flash Page Erase Time 10 ms Flash Mass Erase Time 200 ms Writes to Single Address 2 Before Next Erase Flash Row Program Time 8 ms Cumulative program time for single row cannot exceed limit before next erase This parameter is only an issue when bypassing the Flash Controller Data Re
126. P 8K and 4K Series Product Specification Z4 Zi LOG OSC SEL 1 0 Oscillator Mode Selection 00 On chip oscillator configured for use with external RC networks 4 MHz 01 Minimum power for use with very low frequency crystals 32 kHz to 1 0 MHz 10 Medium power for use with medium frequency crystals or ceramic resonators 0 5MHz to 5 0MHz 11 Maximum power for use with high frequency crystals 5 0 MHz to 20 0 MHz This setting 1s the default for unprogrammed erased Flash VBO AO Voltage Brown Out Protection Always On 0 Voltage Brown Out Protection can be disabled in STOP mode to reduce total power consumption For the block to be disabled the power control register bit must also be writ ten See Power Control Register Definitions on page 34 1 Voltage Brown Out Protection is always enabled including during STOP mode This setting 1s the default for unprogrammed erased Flash FRP Flash Read Protect 0 User program code is inaccessible Limited control features are available through the On Chip Debugger 1 User program code is accessible All On Chip Debugger commands are enabled This setting 1s the default for unprogrammed erased Flash Reserved Must be 1 FWP Flash Write Protect This Option Bit provides Flash Program Memory protection 0 Programming and erasure disabled for all of Flash Program Memory Programming Page Erase and Mass Erase through User Code is disabled Mass Erase
127. Packaging PS022820 0307 Ordering Information Z8 Encore XP 8K and 4K Series Product Specification L z Zi LOG L o 2 2 3 lt y 3 2 a Ez 2 5 5 o 2 E k z 5 o 2 E 4 3 k E Z c o 5 g zz b 2 amp Fs E o o 5 gs 9 O t E E o amp t 2 9g E 99 Sse Z8 Encore XP 8K and 4K Series Development Kit Z8F08A28100KITG Z8 Encore XP 8K Series 28 Pin Development Kit Z8F04A28100KITG Z8 Encore XP 4K Series 28 Pin Development Kit Z8F04A08100KITG Z8 Encore XP 4K Series 8 Pin Development Kit ZUSBSC00100ZACG USB Smart Cable Accessory Kit ZUSBOPTSC01ZACG USB Opto Isolated Smart Cable Accessory Kit ZENETSC0100ZACG Ethernet Smart Cable Accessory Kit PS022820 0307 Ordering Information Z8 Encore XP 8K and 4K Series Product Specification Zi Zi LOG Part Number Suffix Designations Z8 F 04 2A S H 020 S C Environmental Flow C Standard Plastic Packaging Compound G Green Plastic Packaging Compound Temperature Range S Standard 0 to 70 C E Extended 40 to 105 C Speed 020 20 MHz Pin Count B 8 H 20 J 28 Package H SSOP P PDIP Q QFN S SOIC Device Type 2A Contains Advanced Analog Peripherals 1A Does Not Contain Advanced Analog Peripherals Memory Size 08 8 KB Flash 1 KB RAM 0 B NVDS 04 4 KB Flash 1 KB RAM 128 B NVDS 02 2 KB Flash 512 B RAM 64 B NVDS 01 1 KB Flash 256 B RAM 16 B NVDS Memory Type
128. Port Alternate Function operation overrides the Data Direction register setting 0 Output Data in the Port A D Output Data register is driven onto the port pin 1 Input The port pin is sampled and the value written into the Port A D Input Data Reg ister The output driver is tristated PS022820 0307 General Purpose Input Output UN Caution Z8 Encore XP 8K and 4K Series Product Specification 48 Zi LOG Port A D Alternate Function Sub Registers The Port A D Alternate Function sub register Table 20 is accessed through the Port A D Control register by writing 02H to the Port A D Address register The Port A D Alternate Function sub registers enable the alternate function selection on pins If dis abled pins functions as GPIO If enabled select one of four alternate functions using alternate function set subregisters 1 and 2 as described in the Port A D Alternate Function Set 1 Sub Registers on page 50 GPIO Alternate Functions on page 38 and Port A D Alternate Function Set 2 Sub Registers on page 51 See GPIO Alternate Functions on page 38 to determine the alternate function associated with each port pin Do not enable alternate functions for GPIO port pins for which there is no associated alternate function Failure to follow this guideline can result in unpredictable operation Table 20 Port A D Alternate Function Sub Registers PxAF BITS 7 6 5 4 3 2 1 0 FIELD AF7 A
129. R CAT NCC CR e RR 141 Architecture lessen 141 Flash Information Area n veas ie seed eve Reo Ue os DP OREL Deo d amare 142 Operation 143 Flash Operation Timing Using the Flash Frequency Registers 145 Flash Code Protection Against External Access 145 Flash Code Protection Against Accidental Program and Erasure 145 Byte Programming 147 Page Eraso CPP 147 Wass f C rc E E E AA E EE det EEE aoe 147 Flash Controller Bypass 148 Flash Controller Behavior in Debug Mode 148 Flash Control Register Definitions 149 Flash Control Register 149 Flash Status Register 150 Table of Contents PS022820 0307 Z8 Encore XP 8K and 4K Series Product Specification ZiLOG Flash Page Select Register 150 Flash Sector Protect Register 151 Flash Frequency High and Low Byte Registers 152 FlashOptionBits 153 Operaatio sereia ini AAA AAA ee AAA 153 Option Bit Configuration By Reset 153 Option Bit Types 154 Reading the Flash Information P
130. RT Interrupts PS022820 0307 The UART features separate interrupts for the transmitter and the receiver In addition when the UART primary functionality is disabled the Baud Rate Generator can also function as a basic timer with interrupt capability Transmitter Interrupts The transmitter generates a single interrupt when the Transmit Data Register Empty bit TDRE is set to 1 This indicates that the transmitter is ready to accept new data for trans mission The TDRE interrupt occurs after the Transmit shift register has shifted the first bit of data out The Transmit Data register can now be written with the next character to Universal Asynchronous Receiver Transmitter Z8 Encore XP 8K and 4K Series Product Specification Zi Zi LOG send This action provides 7 bit periods of latency to load the Transmit Data register before the Transmit shift register completes shifting the current character Writing to the UART Transmit Data register clears the TDRE bitto 0 Receiver Interrupts The receiver generates an interrupt when any ofthe following occurs A data byte is received and is available in the UART Receive Data register This interrupt can be disabled independently of the other receiver interrupt sources The received data interrupt occurs after the receive character has been received and placed in the Receive Data register To avoid an overrun error software must respond to this received data available condition before
131. Register The Oscillator Control Register OSCCTL enables disables the various oscillator circuits enables disables the failure detection recovery circuitry and selects the primary oscillator which becomes the system clock The Oscillator Control Register must be unlocked before writing Writing the two step sequence E7H followed by 18H to the Oscillator Control Register unlocks it The register is locked at successful completion of a register write to the OSCCTL Table 109 Oscillator Control Register OSCCTL BITS 7 6 5 4 3 D 1 0 FIELD INTEN XTLEN WDTEN SOFEN WDFEN SCKSEL RESET 1 0 1 0 0 0 0 0 R W R W R W R W R W R W R W R W R W ADDR F86H PS022820 0307 INTEN Internal Precision Oscillator Enable 1 Internal precision oscillator is enabled 0 Internal precision oscillator is disabled XTLEN Crystal Oscillator Enable this setting overrides the GPIO register control for PAO and PA1 1 Crystal oscillator is enabled 0 Crystal oscillator is disabled WDTEN Watchdog Timer Oscillator Enable 1 Watchdog Timer oscillator is enabled 0 Watchdog Timer oscillator is disabled SOFEN System Clock Oscillator Failure Detection Enable 1 Failure detection and recovery of system clock oscillator is enabled 0 Failure detection and recovery of system clock oscillator is disabled Oscillator Control PS022820 0307 Z8 Encore XP 8K and 4K Series Product Specifica
132. TJNZ 208 BTJZ 208 C CALL procedure 208 capture mode 85 capture compare mode 85 cc 203 CCF 206 characteristics electrical 223 clear 207 CLR 207 COM 207 Index compare 85 compare extended addressing 205 compare mode 85 compare with carry 205 compare with carry extended addressing 205 complement 207 complement carry flag 206 condition code 203 continuous conversion ADC 124 continuous mode 84 control register definition UART 108 Control Registers 15 19 counter modes 84 CP 205 CPC 205 CPCX 205 CPU and peripheral overview 5 CPU control instructions 206 CPX 205 Customer Feedback Form 273 D DA 203 205 data memory 17 DC characteristics 224 debugger on chip 173 DEC 205 decimal adjust 205 decrement 205 decrement and jump non zero 208 decrement word 205 DECW 205 destination operand 204 device port availability 37 DI 206 direct address 203 disable interrupts 206 DJNZ 208 dst 204 E EI 206 PS022820 0307 Z8 Encore XP 8K and 4K Series Product Specification ya Zi LOG electrical characteristics 223 ADC 233 flash memory and timing 232 GPIO input data sample timing 236 watch dog timer 232 235 enable interrupt 206 ER 203 extended addressing register 203 external pin reset 27 eZ8 CPU features 5 eZ8 CPU instruction classes 204 eZ8 CPU instruction notation 202 eZ8 CPU instruction set 201 eZ8 CPU instruction summary 209 F FCTL register 149 155 156 features Z8 Enco
133. Table 114 PS022820 0307 eZ8 CPU Instruction Set Table 114 Notational Shorthand Z8 Encore XP 8K and 4K Series Product Specification Zi Zi LOG Notation Description Operand Range b Bit b b represents a value from O to 7 000B to 111B CC Condition Code See Condition Codes overview in the eZ8 CPU User Manual DA Direct Address Addrs Addrs represents a number in the range of 0000H to FFFFH ER Extended Addressing Register Reg Reg represents a number in the range of 000H to FFFH IM Immediate Data Data Data is a number between 00H to FFH Ir Indirect Working Register Rn n 0 15 IR Indirect Register Reg Reg represents a number in the range of 00H to FFH Irr Indirect Working Register Pair RRp p 0 2 4 6 8 10 12 or 14 IRR Indirect Register Pair Reg Reg represents an even number in the range OOH to FEH p Polarity p Polarity is a single bit binary value of either OB or 1B r Working Register Rn n 0 15 R Register Reg Reg represents a number in the range of 00H to FFH RA Relative Address X X represents an index in the range of 127 to 128 which is an offset relative to the address of the next instruction rr Working Register Pair RRp p 7 0 2 4 6 8 10 12 or 14 RR Register Pair Reg Reg represents an even number in the range of 00H to FEH Vector Vector Address Vector Vector represents a number in the range of 00H to FFH X Indexed lndex The reg
134. Table 131 on page 231 When this happens the STOP bit in the Reset Status RSTSTAT register is set to 1 AN Caution In STOP mode the GPIO Port Input Data registers PxIN are disabled The Port Input PS022820 0307 Data registers record the Port transition only if the signal stays on the Port pin through the end of the Stop Mode Recovery delay As a result short pulses on the Port pin can initiate Stop Mode Recovery without being written to the Port Input Data register or without initiating an interrupt if enabled for that pin Reset Stop Mode Recovery and Low Voltage Detection 29 Z8 Encore XP 8K and 4K Series Product Specification 30 Zi LOG Stop Mode Recovery Using the External RESET Pin When the Z8 Encore XP 8K and 4K Series device is in STOP Mode and the external RESET pin is driven Low a system reset occurs Because ofa glitch filter operating on the RESET pin the Low pulse must be greater than the minimum width specified or it is ignored See Electrical Characteristics on page 223 for details Low Voltage Detection In addition to the Voltage Brownout VBO Reset described above it is also possible to generate an interrupt when the supply voltage drops below a user selected value For details about configuring the Low Voltage Detection LVD and the threshold levels avail able Trim Bit Address 0003H on page 159 The LVD function is available on the 8 pin product versions only When the supply voltag
135. WM count match and forced Low 0 upon Reload When enabled the Timer Output Complement is forced Low 0 upon PWM count match and forced High 1 upon Reload The PWMD field in TxCTLO register is a programmable delay to control the number of cycles time delay before the Timer Output and the Timer Output Complement is forced to High 1 1 Timer Output is forced High 1 and Timer Output Complement is forced Low 0 when the timer is disabled When enabled the Timer Output is forced Low 0 upon PWM count match and forced High 1 upon Reload When enabled the Timer Output Complement is forced High 1 upon PWM count match and forced Low 0 upon Reload The PWMD field in TxCTLO register is a programmable delay to control the number of cycles time delay before the Timer Output and the Timer Output Complement is forced to Low 0 CAPTURE RESTART mode 0 Count is captured on the rising edge of the Timer Input signal 1 Count is captured on the falling edge of the Timer Input signal COMPARATOR COUNTER mode When the timer is disabled the Timer Output signal is set to the value of this bit Timers Z8 Encore XP 8K and 4K Series Product Specification Z Zi LOG When the timer is enabled the Timer Output signal is complemented upon timer Reload Also 0 Count is captured on the rising edge of the comparator output 1 Count is captured on the falling edge of the comparator output AN Caution When the Timer Output alternate
136. X X X X R W R R R R R R R ADDR F40H X Undefined RXD Receive Data UART receiver data byte from the RXDx pin UART Address Compare Register The UART Address Compare UxADDR register stores the multi node network address of the UART see Table 67 When the MPMD 1 bit of UART Control Register 0 is set all incoming address bytes are compared to the value stored in the Address Compare register Receive interrupts and RDA assertions only occur in the event of a match PS022820 0307 Universal Asynchronous Receiver Transmitter Z8 Encore XP 8K and 4K Series Product Specification Ll iu Zi LOG Table 67 UART Address Compare Register UOADDR BITS 7 6 5 4 3 2 1 0 FIELD COMP ADDR RESET 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W ADDR F45H COMP ADDR Compare Address This 8 bit value is compared to incoming address bytes UART Baud Rate High and Low Byte Registers The UART Baud Rate High UxBRH and Low Byte UxBRL registers Table 68 and Table 69 combine to create a 16 bit baud rate divisor value BRG 15 0 that sets the data transmission rate baud rate of the UART Table 68 UART Baud Rate High Byte Register UOBRH PS022820 0307 BITS 7 6 5 4 3 2 1 0 FIELD BRH RESET 1 1 1 1 1 1 1 1 R W R W R W R W R W R W R W R W R W ADDR F46H Table 69 UART Baud Rate Low
137. XP 8K and 4K Series Product Specification 148 Zi LOG value 63H to the Flash Control register initiates the Mass Erase operation While the Flash Controller executes the Mass Erase operation the eZ8 CPU idles but the system clock and on chip peripherals continue to operate Using the On Chip Debugger poll the Flash Sta tus register to determine when the Mass Erase operation is complete When the Mass Erase is complete the Flash Controller returns to its locked state Flash Controller Bypass The Flash Controller can be bypassed and the control signals for the Flash memory brought out to the GPIO pins Bypassing the Flash Controller allows faster Row Program ming algorithms by controlling the Flash programming signals directly Row programming is recommended for gang programming applications and large volume customers who do not require in circuit initial programming of the Flash memory Page Erase operations are also supported when the Flash Controller is bypassed Refer to the document entitled Third Party Flash Programming Support for Z8 Encore for more information about bypassing the Flash Controller This document is available for download at www zilog com Flash Controller Behavior in Debug Mode The following changes in behavior of the Flash Controller occur when the Flash Control ler is accessed using the On Chip Debugger The Flash Write Protect option bit is ignored The Flash Sector Protect register is ignored
138. Z8 CPU Instruction Set Z8 Encore XP 8K and 4K Series Product Specification Table 123 Rotate and Shift Instructions Mnemonic Operands Instruction SRL dst Shift Right Logical SWAP dst Swap Nibbles eZ8 CPU Instruction Summary Table 124 eZ8 CPU Instruction Summary Zi Zi LOG Table 124 summarizes the eZ8 CPU instructions The table identifies the addressing modes employed by the instruction the effect upon the Flags register the number of CPU clock cycles required for the instruction fetch and the number of CPU clock cycles required for the instruction execution Assembly Symbolic Address Mode Opcode s Flags Fetch Instr Mnemonic Operation dst src Hex C Z S V D H Cycles Cycles ADC dst src dst dst src C r r 12 Woo wm m a 2 3 r Ir 13 2 4 R R 14 3 3 R IR 15 3 4 R IM 16 3 3 IR IM 17 3 4 ADCX dst src dst dst src C ER ER 18 t 79 COS oo 15 4 3 ER IM 19 4 3 ADD dst src dst lt dst src r r 02 oo Ow OW OS 2 3 r Ir 03 2 4 R R 04 3 3 R IR 05 3 4 R IM 06 3 3 IR IM 07 3 4 ADDX dst src dst lt dst src ER ER 08 m c e ur cs 4 3 ER IM 09 4 3 Flags Notation Value is a function of the result of the operation 0 Reset to 0 Unaffected 1 Set to 1 X Undefined PS022820 0307 eZ8 CPU Instruction Set Z8 Encore XP 8K and 4K Series Product Specification Zi
139. Zi LOG High Performance 8 Bit Microcontrollers Z8 Encore XP 8K and 4K Series Product Specification PS022820 0307 Copyright 2007 by ZiLOG Inc All rights reserved www zilog com Z ZiLOG This publication is subject to replacement by a later edition To determine whether a later edition exists or to request copies of publications please visit www zilog com BSI ZiLOG products are designed and manufactured under an ISO registered ANAB 9001 2000 Quality Management System ACCREDITED For more details please visit www zilog com quality ISO 9001 2000 FS 507510 Document Disclaimer 2007 by ZiLOG Inc All rights reserved Information in this publication concerning the devices applications or technology described is intended to suggest possible uses and may be superseded ZiLOG INC DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE INFORMATION DEVICES OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT ZiLOG ALSO DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION DEVICES OR TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE Except with the express written approval of ZiLOG use of information devices or technology as critical components of life support systems is not authorized No licenses or other rights are conveyed implicitly or otherwise by this document under any intellectual property rights Z8 Z8 Encore Z8 Encore XP Z
140. a corrupted value in the NVDS array at the location being read In this case the value returned in RO is the byte most recently written to the array that does not have a CRC error Power Failure Protection The NVDS routines employ error checking mechanisms to ensure a power failure endangers only the most recently written byte Bytes previously written to the array are not perturbed A system reset such as a pin reset or watchdog timer reset that occurs during a write operation also perturbs the byte currently being written All other bytes in the array are unperturbed Optimizing NVDS Memory Usage for Execution Speed PS022820 0307 As Table 104 lists the NVDS read time varies drastically this discrepancy being a trade off for minimizing the frequency of writes that require post write page erases The NVDS read time of address N is a function of the number of writes to addresses other than N since the most recent write to address N as well as the number of writes since the most recent page erase Neglecting effects caused by page erases and results caused by the ini tial condition in which the NVDS is blank a rule of thumb is that every write since the most recent page erase causes read times of unwritten addresses to increase by 1 us up to a maximum of 511 NVDS SIZE us Non Volatile Data Storage PS022820 0307 Table 104 NVDS Read Time Z8 Encore XP 8K and 4K Series Product Specification Z4 Zi LOG
141. a function of package and each pin is individually programmable 5 V tolerant input pins are available on all IOs on 8 pin devices and most IOs on other package types Direct LED Drive The 20 and 28 pin devices support controlled current sinking output pins capable of driving LEDs without the need for a current limiting resistor These LED drivers are independently programmable to four different intensity levels Flash Controller The Flash Controller programs and erases Flash memory The Flash Controller supports several protection mechanisms against accidental program and erasure as well as factory serialization and read protection Non Volatile Data Storage The non volatile data storage NVDS uses a hybrid hardware software scheme to implement a byte programmable data memory and is capable of over 100 000 write cycles gt Note Devices with 8 KB Flash memory do not include the NVDS feature PS022820 0307 Overview Z8 Encore XP 8K and 4K Series Product Specification Zi LOG Interrupt Controller The Z8 Encore XP 8K and 4K Series products support up to 20 interrupts These interrupts consist of 8 internal peripheral interrupts and 12 general purpose I O pin interrupt sources The interrupts have three levels of programmable interrupt priority Reset Controller The Z8 Encore XP 8K and 4K Series products can be reset using the RESET pin power on reset Watchdog Timer WDT time out STOP mode exit or Voltage Brownout
142. a transmission and reception is not allowed The baud rate is set by the UART s Baud Rate Generator and supports IrDA standard baud rates from 9600 baud to 115 2 Kbaud Higher baud rates are possible but do not meet IrDA specifications The UART must be enabled to use the Infrared Endec The Infrared Endec data rate is calculated using the following equation Infrared Data Rate bits s SAA Euch aes 16 x UART Baud Rate Divisor Value Transmitting IrDA Data Baud Rate Clock UART s TXD IR TXD PS022820 0307 F period a OOOO The data to be transmitted using the infrared transceiver is first sent to the UART The UART s transmit signal TXD and baud rate clock are used by the IrDA to generate the modulation signal IR TXD that drives the infrared transceiver Each UART Infrared data bit is 16 clocks wide If the data to be transmitted is 1 the IR TXD signal remains low for the full 16 clock period If the data to be transmitted is 0 the transmitter first out puts a 7 clock low period followed by a 3 clock high pulse Finally a 6 clock low pulse is output to complete the full 16 clock data period Figure 17 illustrates IrDA data transmis sion When the Infrared Endec is enabled the UART s TXD signal is internal to the Z8 Encore XP 8K and 4K Series products while the IR TXD signal is output through the TXD pin 16 clock Start Bit 0 Data Bit 0 1 Data Bit 1 2 0 Data Bit 2 1 Data Bit 3 1 3 clo
143. able Sub Registers PxPUE BITS 7 6 5 4 3 2 1 0 FIELD PPUE7 PPUE6 PPUE5 PPUE4 PPUE3 PPUE2 PPUE1 PPUEO RESET 00H Ports A C 01H Port D 04H Port A of 8 pin device R W R W R W R W R W R W R W R W R W ADDR If 06H in Port A D Address Register accessible through the Port A D Control Register PPUE 7 0 Port Pull up Enabled 0 The weak pull up on the Port pin is disabled 1 The weak pull up on the Port pin is enabled Port A D Alternate Function Set 1 Sub Registers The Port A D Alternate Function Set1 sub register Table 25 is accessed through the Port A D Control register by writing 07H to the Port A D Address register The Alternate Function Set 1 sub registers selects the alternate function available at a port pin Alternate Functions selected by setting or clearing bits of this register are defined in GPIO Alternate Functions on page 38 gt Note Alternate function selection on port pins must also be enabled as described in Port A D PS022820 0307 Alternate Function Sub Registers on page 48 General Purpose Input Output Z8 Encore XP 8K and 4K Series Product Specification ZI Zi LOG Table 25 Port A D Alternate Function Set 1 Sub Registers PxAFS1 BITS 7 6 5 4 3 2 1 0 FIELD PAFS17 PAFS16 PAFS15 PAFS14 PAFS13 PAFS12 PAFS11 PAFS10 RESET 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W
144. abled UART operates normally 1 Infrared Encoder Decoder is enabled The UART transmits and receives data through the Infrared Encoder Decoder UART Status 0 Register The UART Status 0 UxSTATO and Status 1 UxSTAT1 registers Table 63 and Table 64 identify the current UART operating configuration and status Table 63 UART Status 0 Register UOSTATO BITS 7 6 5 4 3 2 1 0 FIELD RDA PE OE FE BRKD TDRE TXE CTS RESET 0 0 0 0 0 1 1 X R W R R R R R R R R ADDR F41H PS022820 0307 RDA Receive Data Available This bit indicates that the UART Receive Data register has received data Reading the UART Receive Data register clears this bit 0 The UART Receive Data register is empty 1 There is a byte in the UART Receive Data register PE Parity Error This bit indicates that a parity error has occurred Reading the UART Receive Data regis ter clears this bit 0 No parity error has occurred 1 A parity error has occurred OE Overrun Error This bit indicates that an overrun error has occurred An overrun occurs when new data is received and the UART Receive Data register has not been read If the RDA bit is reset to 0 reading the UART Receive Data register clears this bit 0 No overrun error occurred 1 An overrun error occurred FE Framing Error This bit indicates that a framing error no Stop bit following data reception was detected Reading the UART Receive
145. age 155 Flash Option Bit Control Register Definitions 155 Trim Bit Address Register 155 Trim Bit Data Register 156 Flash Option Bit Address Space 156 Flash Program Memory Address OOOOH 156 Flash Program Memory Address 0001H 157 Trim Bit Address Space 158 Trim Bit Address OOOOH 158 Trim Bit Address 0001H 159 Trim Bit Address 0002H 159 Trim Bit Address 0003H 159 Trim Bit Address 0004H 161 ZiLOG Calibration Data 161 ADC Calibration Data 161 Temperature Sensor Calibration Data 164 Watchdog Timer Calibration Data 164 Serialization Data 165 Randomized Lot Identifier 166 Non Volatile Data Storage 169 Operation 169 NVDS Code Interface 169 Byte Writes ie
146. al 194 2006 power dissipation by the crystal from the Crystal Oscillator chapter since R1 is no longer required in the circuit September 17 Updated for minor changes in Overview General Purpose Input 1 23 37 2006 Output On Chip Debugger Reset Stop Mode Recovery and Low 55 141 Voltage Detection Flash Memory Interrupt Controller and Ordering 173 and Information chapters 253 August 16 Changes for improved readability Added data to Electrical All 2006 Characteristics chapter Added 8K features Updated Analog to Digital Converter Electrical Characteristics 121 223 chapters and Port Alternate Function Mapping Non 8 Pin Parts table and 41 PS022820 0307 Z8 Encore XP 8K and 4K Series Product Specification Z Zi LOG PS022820 0307 Z8 Encore XP 8K and 4K Series Product Specification ZiLOG Table of Contents OvervieW io eek Seed eke eae RA REA RR ee ee tae ed 1 Features aho aon a ai koa leen 1 Part Selection Guide 2 Block Diagrami MEME EMT 4 CPU and Peripheral Overview 5 eZ8 CPU Features 5 10 Bit Analog to Digital Converter 5 Low Power Operational Amplifier 6 Internal Precision Oscillator 6 Temperature Sensor 6 Analog Compearalor
147. amCounter 15 8 DBG lt ProgramCounter 7 0 Read Program Counter 07H The Read Program Counter command reads the value in the eZ8 CPU s Program Counter PC If the device is not in DEBUG mode or if the Flash Read Protect Option bit is enabled this command returns FFFFH DBG lt 07H DBG ProgramCounter 15 8 DBG ProgramCounter 7 0 Write Register 08H The Write Register command writes data to the Register File Data can be written 1 256 bytes at a time 256 bytes can be written by setting size to 0 If the device is not in DEBUG mode the address and data values are dis carded If the Flash Read Protect Option bit is enabled only writes to the Flash Con trol Registers are allowed and all other register write data values are discarded DBG lt 08H DBG 4 hO Register Address 11 8 DBG Register Address 7 0 DBG lt Size 7 0 DBG lt 1 256 data bytes Read Register 09H The Read Register command reads data from the Register File Data can be read 1 256 bytes at a time 256 bytes can be read by setting size to 0 If the device is not in DEBUG mode or if the Flash Read Protect Option bit is en abled this command returns FFH for all the data values DBG 09H DBG lt 4 hO Register Address 11 8 DBG Register Address 7 0 On Chip Debugger 181 PS022820 0307 Z8 Encore XP 8K and 4K Series Product Specification Zi LOG DBG Size 7 0 DBG 1 256 data bytes Write
148. ance only and are not tested in production PS022820 0307 Electrical Characteristics Table 128 Power Consumption Z8 Encore XP 8K and 4K Series Product Specification Zi Zi LOG Vpp 2 7 V to 3 6 V Current Maximum Maximum Symbol Parameter Typical Std Temp Ext Temp Units Conditions lpp Stop Supply Current in STOP 0 1 pA No peripherals enabled Mode All pins driven to Vpp or lpp Halt Supply Current in HALT 35 55 65 pA 32kHz Mode with all peripherals disabled D Ia MBE 2 1 2 3 24 mA 20 MHz IDD Supply Current in 2 8 mA 32 kHz BO EM OPRA aS 5 2 52 mA 5 5 MHz peripherals disabled 5 5 6 5 6 5 mA 10 MHz 7 9 9 3 9 3 mA 20 MHz Ipp WDT Watchdog Timer Supply 0 9 1 0 1 1 pA Current Ipp XTAL Crystal Oscillator 40 HA 32 kHz Supply Current 230 uA 4 MHz 760 pA 20 MHz Ipp IPO Internal Precision 350 500 550 pA Oscillator Supply Current IDD VBO Voltage Brown Out and 50 pA For 20 28 pin devices Low Voltage Detect VBO only See Note 4 Supply Current For 8 pin devices See Note 4 Ipp ADC Analog to Digital 2 8 3 1 3 2 mA 32 kHz Converter Supply Current with External 27 a wa mA Pp MH Reference 3 3 3 7 3 8 mA 10 MHz 3 7 4 2 4 3 mA 20 MHz IDD ADC Internal Reference 0 pA See Note 4 ADCRef Supply Current lbp CMP Comparator supply 150 180 190 pA See Note 4 PS022820 0307 Electrical Characteristics
149. ange in an input pin resets this bit Reading this regis ter resets this bit Reserved Must be 0 LVD Low Voltage Detection Indicator If this bit is set to 1 the current state of the supply voltage is below the low voltage detection threshold This value is not latched but is a real time indicator of the supply volt age level Reset Stop Mode Recovery and Low Voltage Detection 31 Z8 Encore XP 8K and 4K Series Product Specification Zi Zi LOG PS022820 0307 Reset Stop Mode Recovery and Low Voltage Detection Z8 Encore XP 8K and 4K Series Product Specification 33 Zi LOG Low Power Modes The Z8 Encore XP 8K and 4K Series products contain power saving features The highest level of power reduction is provided by the STOP mode in which nearly all device functions are powered down The next lower level of power reduction is provided by the HALT mode in which the CPU is powered down Further power savings can be implemented by disabling individual peripheral blocks while in Active mode defined as being in neither STOP nor HALT mode STOP Mode PS022820 0307 Executing the eZ8 CPU s STOP instruction places the device into STOP mode powering down all peripherals except the Voltage Brownout detector the Low power Operational Amplifier and the Watchdog Timer These three blocks may also be disabled for additional power savings Specifically the operating characteristics are Primary crystal oscillator
150. ations Low Gain 32 kHz 1 MHz Low Power Frequency 0 02 0 04 0 09 see Note Applications Medium Gain 0 5 MHz 10 MHz Medium Power Frequency 0 84 1 7 3 1 see Note Applications High Gain 8 MHz 20 MHz High Power Frequency 1 1 2 3 4 2 see Note Applications Note Printed circuit board layout must not add more than 4 pF of stray capacitance to either XIN or XOUT pins if no Oscillation occurs reduce the values of the capacitors C1 and C2 to decrease the loading Oscillator Operation with an External RC Network Figure 28 illustrates a recommended configuration for connection with an external resistor capacitor RC network VDD Figure 28 Connecting the On Chip Oscillator to an External RC Network PS022820 0307 Crystal Oscillator Z8 Encore XP 8K and 4K Series Product Specification 196 Zi LOG An external resistance value of 45 KO is recommended for oscillator operation with an external RC network The minimum resistance value to ensure operation is 40 KO The typical oscillator frequency can be estimated from the values of the resistor R in KO and capacitor C in pF elements using the following equation 1x108 Oscillator Frequency kHz VASE 0 4 x Rx C Ax C Figure 29 illustrates the typical 3 3 V and 25 C oscillator frequency as a function of the capacitor C in pF employed in the RC network assuming a 45 KQ external resistor For very small values of
151. be disabled before switching between sources Table 46 Shared Interrupt Select Register IRQSS BITS 7 6 5 4 3 2 1 0 FIELD PA7VS PA6CS Reserved RESET 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W ADDR FCEH PA7VS PA7 LVD Selection 0 PA7 is used for the interrupt for PA7VS interrupt request 1 The LVD is used for the interrupt for PA7VS interrupt request PS022820 0307 Interrupt Controller Z8 Encore XP 8K and 4K Series Product Specification Zi Zi LOG PA6CS PA6 Comparator Selection 0 PA6 is used for the interrupt for PA6CS interrupt request 1 The Comparator is used for the interrupt for PA6CS interrupt request Reserved Must be 0 Interrupt Control Register The Interrupt Control IRQCTL register Table 47 contains the master enable bit for all interrupts Table 47 Interrupt Control Register IRQCTL BITS 7 6 5 4 3 2 1 0 FIELD IRQE Reserved RESET 0 0 0 0 0 0 0 0 R W R W R R R R R R R ADDR FCFH PS022820 0307 IRQE Interrupt Request Enable This bit is set to 1 by executing an EI Enable Interrupts or IRET Interrupt Return instruction or by a direct register write of a 1 to this bit It is reset to 0 by executing a DI instruction eZ8 CPU acknowledgement of an interrupt request Reset or by a direct register write of a 0 to this bit 0 Interrupts are disabled 1 Interrupts ar
152. ble 55 control Pulse Width Modulator PWM operations These registers also store the Capture values for the CAPTURE and CAPTURE COMPARE modes Table 54 Timer 0 1 PWM High Byte Register TXPWMH BITS 7 6 5 4 3 2 1 0 FIELD PWMH RESET 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W ADDR F04H FOCH PS022820 0307 Timers Z8 Encore XP 8K and 4K Series Product Specification Zi Zi LOG Table 55 Timer 0 1 PWM Low Byte Register TkPWML BITS 7 6 5 4 3 2 1 0 FIELD PWML RESET 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W ADDR F05H FODH PWMH and PWML Pulse Width Modulator High and Low Bytes These two bytes PWMH 7 0 PWML 7 0 form a 16 bit value that is compared to the current 16 bit timer count When a match occurs the PWM output changes state The PWM output value is set by the TPOL bit in the Timer Control Register TxCTL 1 regis ter The TxPWMH and TxPWML registers also store the 16 bit captured timer value when operating in CAPTURE or CAPTURE COMPARE modes PS022820 0307 Timers Z8 Encore XP 8K and 4K Series Product Specification VAF ZiLOG PS022820 0307 Timers Z8 Encore XP 8K and 4K Series Product Specification 91 Zi LOG Watchdog Timer The Watchdog Timer WDT protects against corrupt or unreliable software power faults and other system level problems which may place the Z8 En
153. capture event If no Capture event occurs the timer counts up to the 16 bit Compare value stored in the Timer Reload High and Low Byte registers Upon reaching the Reload value the timer generates an interrupt the count value in the Timer High and Low Byte registers is reset to Timers Z8 Encore XP 8K and 4K Series Product Specification 79 Zi LOG 0001H and counting resumes The INPCAP bit in TxCTLO register is cleared to indicate the timer interrupt is not caused by an input capture event The steps for configuring a timer for CAPTURE RESTART mode and initiating the count are as follows 1 Write to the Timer Control register to Disable the timer Configure the timer for CAPTURE RESTART mode by writing the TMODE bits in the TxCTL 1 register and the TMODEHI bit in TxCTLO register Set the prescale value Set the Capture edge rising or falling for the Timer Input 2 Write to the Timer High and Low Byte registers to set the starting count value typically 00018H 3 Write to the Timer Reload High and Low Byte registers to set the Reload value 4 Clear the Timer PWM High and Low Byte registers to 0000H This allows user software to determine if interrupts were generated by either a capture event or a reload If the PWM High and Low Byte registers still contain 0000H after the interrupt the interrupt was generated by a Reload 5 Enable the timer interrupt 1f appropriate and set the timer interrupt priorit
154. capture event Table 48 Timer 0 1 Control Register 0 TxCTLO BITS 7 6 5 4 3 2 1 0 FIELD TMODEHI TICONFIG Reserved PWMD INPCAP RESET 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R ADDR FO6H FOEH PS022820 0307 TMODEHI Timer Mode High Bit This bit along with the TMODE field in TXCTL 1 register determines the operating mode of the timer This is the most significant bit of the Timer mode selection value See the TxCTL 1 register description for details of the full timer mode decoding TICONFIG Timer Interrupt Configuration This field configures timer interrupt definition Ox Timer Interrupt occurs on all defined Reload Compare and Input Events 10 Timer Interrupt only on defined Input Capture Deassertion Events 11 Timer Interrupt only on defined Reload Compare Events Reserved Must be 0 PWMD PWM Delay value This field is a programmable delay to control the number of system clock cycles delay before the Timer Output and the Timer Output Complement are forced to their active state 000 No delay 001 2 cycles delay 010 4 cycles delay 011 8 cycles delay 100 16 cycles delay 101 32 cycles delay 110 64 cycles delay 111 128 cycles delay Timers Z8 Encore XP 8K and 4K Series Product Specification L u Zi LOG INPCAP Input Capture Event This bit indicates 1f the most recent timer interrupt is caused by a Timer Input Capture Event 0
155. ccumulators address pointers index registers stack areas or scratch pad memory The upper 256 bytes of the 4 KB Register File address space are reserved for control of the eZ8 CPU the on chip peripherals and the I O ports These registers are located at addresses from F00H to FFFH Some of the addresses within the 256 B control register section are reserved unavailable Reading from a reserved Register File address returns an undefined value Writing to reserved Register File addresses is not recommended and can produce unpredictable results The on chip RAM always begins at address 000H in the Register File address space The Z8 Encore XP 8K and 4K Series devices contain 256 B to 1 KB of on chip RAM Reading from Register File addresses outside the available RAM addresses and not within the control register address space returns an undefined value Writing to these Register File addresses produces no effect Program Memory The eZ8 CPU supports 64 KB of Program Memory address space The Z8 Encore XP 8K and 4K Series devices contain KB to 8 KB of on chip Flash memory in the Program Memory address space depending on the device Reading from Program Memory PS022820 0307 Address Space Z8 Encore XP 8K and 4K Series Product Specification Lli Zi LOG addresses outside the available Flash memory addresses returns FFH Writing to these unimplemented Program Memory addresses produces no effect Table 5 describes the Program Mem
156. changed by Reset R W Read Write PS022820 0307 Flash Option Bits Z8 Encore XP 8K and 4K Series Product Specification Ll i Zi LOG Reserved Must be 1 LVD TRIM Low Voltage Detect Trim This trimming affects the low voltage detection threshold Each LSB represents a 50 mV change in the threshold level Alternatively the low voltage threshold may be computed from the options bit value by the following eguation LVD LVL 23 6 V LVD TRIM 0 05 V LVD Threshold V LVD TRIM Typical Description 00000 3 60 Maximum LVD threshold 00001 3 55 00010 3 50 00011 3 45 00100 3 40 00101 3 35 00110 3 30 00111 3 25 01000 3 20 01001 3 15 01010 3 10 Default on Reset 01011 3 05 01100 3 00 01101 2 95 01110 2 90 01111 2 85 10000 2 80 10001 2 75 10010 2 70 10011 2 70 to to 11111 1 65 Minimum LVD threshold PS022820 0307 Flash Option Bits Z8 Encore XP 8K and 4K Series Product Specification Zi LOG Trim Bit Address 0004H Table 92 Trim Option Bits at 0004H BITS 7 6 5 4 3 2 1 0 FIELD Reserved RESET U U U U U U U U R W R W R W R W R W R W R W R W R W ADDR Information Page Memory 0024H Note U Unchanged by Reset R W Read Write Reserved Altering this register may result in incorrect device operation ZiLOG Calibration Data
157. ck pulse T clock delay Figure 17 Infrared Data Transmission Infrared Encoder Decoder 118 Z8 Encore XP 8K and 4K Series Product Specification Zi LOG Receiving IrDA Data Data received from the infrared transceiver using the IR RXD signal through the RXD pin is decoded by the Infrared Endec and passed to the UART The UART s baud rate clock is used by the Infrared Endec to generate the demodulated signal RXD that drives the UART Each UART Infrared data bit is 16 clocks wide Figure 18 illustrates data recep tion When the Infrared Endec is enabled the UART s RXD signal is internal to the Z8 Encore XP 8K and 4K Series products while the IR RXD signal is received through the RXD pin 16 clock F period gt ssa LITT Clock Start Bit 0 Data Bit 0 1 Data Bit 1 0 Data Bit 2 1 Data Bit 3 1 IR RXD min 1 4 us 7 pulse UART EXD Start Bit 0 Data Bit 0 1 Data Bit 1 0 Data Bit 2 1 Data Bit 3 1 8 clock delay 16 clock 16 clock 16 clock 16 clock lt period period gt r period gt r period gt Figure 18 IrDA Data Reception Infrared Data Reception AN Caution The system clock frequency must be at least 1 0 MHz to ensure proper reception of the PS022820 0307 1 4 us minimum width pulses allowed by the IrDA standard Endec R
158. core XP 8K and 4K Series Product Specification Z Zi LOG Table 1 Z8 Encore XP 8K and 4K Series Family Part Selection Guide Part Flash RAM NVDS Advanced ADC Number KB B B lO Comparator Analog Inputs Packages Z8F082A 8 1024 0 6 23 Yes Yes 4 8 8 20 and 28 pin Z8F081A 8 1024 0 6 25 Yes No 0 8 20 and 28 pin Z8F042A 4 1024 128 6 23 Yes Yes 4 8 8 20 and 28 pin Z8F041A 4 1024 128 6 25 Yes No 0 8 20 and 28 pin Z8F022A 2 512 64 6 23 Yes Yes 4 8 8 20 and 28 pin Z8F021A 2 512 64 6 25 Yes No 0 8 20 and 28 pin Z8F012A 1 256 16 6 23 Yes Yes 4 8 8 20 and 28 pin Z8F011A 1 256 16 6 25 Yes No 0 8 20 and 28 pin Non volatile data storage Advanced Analog includes ADC temperature sensor and low power operational amplifier PS022820 0307 Overview Z8 Encore XP 8K and 4K Series Product Specification Z Zi LOG Block Diagram Figure 1 illustrates the block diagram of the architecture of the Z8 Encore XP 8K and 4K Series devices System Oscillator XTAL RC Clock Control s gt Oscillator Internal Precision Oscillator On Chip l e Low Power gt Debugger M RC Oscillator POR VBO eZ8 CPU Interrupt Es but WDT s gt Controller aid Y Memory Busses Re
159. core XP 8K and 4K Series devices into unsuitable operating states The Watchdog Timer includes the following features On chip RC oscillator A selectable time out response reset or interrupt 24 bit programmable time out value Operation The Watchdog Timer WDT is a one shot timer that resets or interrupts the Z8 Encore XP 8K and 4K Series devices when the WDT reaches its terminal count The Watchdog Timer uses a dedicated on chip RC oscillator as its clock source The Watchdog Timer operates in only two modes ON and OFF Once enabled it always counts and must be refreshed to prevent a time out Perform an enable by executing the WDT instruction or by setting the WDT_AO Flash Option Bit The WDT_AO bit forces the Watchdog Timer to operate immediately upon reset even if a WDT instruction has not been executed The Watchdog Timer is a 24 bit reloadable downcounter that uses three 8 bit registers in the eZ8 CPU register space to set the reload value The nominal WDT time out period is described by the following equation WDT Time out Period ms WOT Reload Value 10 where the WDT reload value is the decimal value of the 24 bit value given by WDTU 7 0 WDTH 7 0 WDTL 7 0 and the typical Watchdog Timer RC oscillator frequency is 10kHz The Watchdog Timer cannot be refreshed after it reaches 000002H The WDT Reload Value must not be set to values below 0000048 Table 56 provides information about approximate time out delays
160. cs on page 223 For OCD operation at higher data rates or in noisy systems an external pull up resistor is recommended UN Caution For operation of the on chip debugger all power pins Vpp and AVpp must be supplied with power and all ground pins Vss and AV ss must be properly grounded The DBG pin is open drain and may require an external pull up resistor to ensure proper operation VDD RS 232 Transceiver Schottky 10 KOhm Diode d DBG Pin RS 232 TX RS 232 RX ji Figure 24 Interfacing the On Chip Debugger s DBG Pin with an RS 232 Interface 1 PS022820 0307 On Chip Debugger Z8 Encore XP 8K and 4K Series Product Specification VA ZiLOG VDD RS 232 Transceiver Open Drain 10 KOhm Buffer RS 232 TX gt DBG Pin RS 232 RX Figure 25 Interfacing the On Chip Debugger s DBG Pin with an RS 232 Interface 2 DEBUG Mode The operating characteristics of the devices in DEBUG mode are The eZ8 CPU fetch unit stops idling the eZ8 CPU unless directed by the OCD to execute specific instructions The system clock operates unless in STOP mode All enabled on chip peripherals operate unless in STOP mode Automatically exits HALT mode Constantly refreshes the Watchdog Timer if enabled Entering DEBUG Mode The device enters DEBUG mode after the eZ8 CPU executes a BRK Breakpoint instruction Ifthe DBG pin is held Low during the final clock cycle of sys
161. d 4K Series Product Specification Z ZiLOG PS022820 0307 Low Power Modes Z8 Encore XP 8K and 4K Series Product Specification 37 Zi LOG General Purpose Input Output The Z8 Encore XP 8K and 4K Series products support a maximum of 25 port pins Ports A D for general purpose input output GPIO operations Each port contains control and data registers The GPIO control registers determine data direction open drain output drive current programmable pull ups Stop Mode Recovery functional ity and alternate pin functions Each port pin is individually programmable In addition the Port C pins are capable of direct LED drive at programmable drive strengths GPIO Port Availability By Device Table 13 lists the port pins available with each device and package type Table 13 Port Availability by Device and Package Type Devices Package ADC Port A Port B Port C Port D Total I O Z8F082ASB Z8F082APB Z8F082AQB 8 pin Yes 5 0 No No No 6 Z8F042ASB Z8F042APB Z8F042AQB Z8F022ASB Z8F022APB Z8F022AQB Z8F012ASB Z8F012APB Z8F012AQB Z8F081ASB Z8F081APB Z8F081AQB 8 pin No 5 0 No No No 6 Z8F041ASB Z8F041APB Z8F041AQB Z8F021ASB Z8F021APB Z8F021AQB Z8F011ASB Z8F011APB Z8F011AQB Z8F082APH Z8F082AHH Z8F082ASH 20 pin Yes 7 0 3 0 3 0 0 17 Z8F042APH Z8F042AHH Z8F042ASH Z8F022APH Z8F022AHH Z8F022ASH Z8F012APH Z8F012AHH Z8F012ASH Z8F081APH Z8FO81AHH Z8FO81ASH 20 pin No 70 3 0 3 0 0 17 Z8F041APH
162. d value that is loaded into the Watch dog Timer when a WDT instruction executes The 24 bit reload value is WDTU 7 0 WDTH 7 0 WDTL 7 0 Writing to these registers sets the appropriate Reload Value Reading from these registers returns the current Watchdog Timer count value AN Caution The 24 bit WDT Reload Value must not be set to a value less than 000004H Table 58 Watchdog Timer Reload Upper Byte Register WDTU BITS 7 6 5 4 3 2 1 FIELD WDTU RESET FFH R W R W ADDR FF1H R W Read returns the current WDT count value Write sets the appropriate Reload Value WDTU WDT Reload Upper Byte Most significant byte MSB Bits 23 16 of the 24 bit WDT reload value Table 59 Watchdog Timer Reload High Byte Register WDTH BITS 7 6 5 4 3 2 1 FIELD WDTH RESET FFH R W R W ADDR FF2H R W Read returns the current WDT count value Write sets the appropriate Reload Value WDTH WDT Reload High Byte Middle byte Bits 15 8 of the 24 bit WDT reload value PS022820 0307 Watchdog Timer Z8 Encore XP 8K and 4K Series Product Specification Le ZPL OG Table 60 Watchdog Timer Reload Low Byte Register WDTL BITS 7 6 5 4 3 2 1 0 FIELD WDTL RESET FFH R W R W ADDR FF3H R W Read returns the current WDT count value Write sets the appropriate Reload Value WDTL
163. defaults Low in Yes Programmable Yes programmable Yes unless to RESET Reset for PA2 always for PA2 always pull ups mode on for RESET on for RESET enabled PA 5 3 VO l N A Yes Programmable Yes Yes Yes unless Pull up Programmable pull ups enabled Vpp N A N A N A N A N A N A N A N A Vss N A N A N A N A N A N A N A N A PS022820 0307 Pin Description Z8 Encore XP 8K and 4K Series Product Specification Li ZiLOG Address Space The eZ8 CPU can access three distinct address spaces The Register File contains addresses for the general purpose registers and the eZ8 CPU peripheral and general purpose I O port control registers The Program Memory contains addresses for all memory locations having executable code and or data The Data Memory contains addresses for all memory locations that contain data only These three address spaces are covered briefly in the following subsections For more detailed information regarding the eZ8 CPU and its address space refer to the eZ8 CPU User Manual available for download at www zilog com Register File The Register File address space in the Z8 Encore MCU is 4 KB 4096 bytes The Register File is composed of two sections control registers and general purpose registers When instructions are executed registers defined as sources are read and registers defined as destinations are written The architecture of the eZ8 CPU allows all general purpose registers to function as a
164. dem ex Ba onde arde del Waa d Rr 57 Master Interrupt Enable 57 Interrupt Vectors and Priority 58 Interrupt Assertion 58 Software Interrupt Assertion 59 Watchdog Timer Interrupt Assertion 59 Interrupt Control Register Definitions 60 Interrupt Request 0 Register 60 Interrupt Request 1 Register 61 Interrupt Request 2 Register 62 IRQO Enable High and Low Bit Registers 62 IRQ1 Enable High and Low Bit Registers 63 IRQ2 Enable High and Low Bit Registers 65 Interrupt Edge Select Register 66 Shared Interrupt Select Register 66 Interrupt Control Register 67 TUMA IAEA 69 ues IA TUTUP 69 Operation 55a eed ed ER oh Rub AA Parade dur bap a eod E RU tech ek 70 Timer Operating Modes 70 Reading the Timer Count Values 82 Timer Pin Signal Operation 82 Timer Control Register Definitions 83 Timer 0 1 Control Register
165. digital value In DIFFERENTIAL mode the ADC PS022820 0307 Analog to Digital Converter Z8 Encore XP 8K and 4K Series Product Specification can output values across the entire 11 bit range from 1024 to 1023 In SINGLE ENDED mode the output generally ranges from 0 to 1023 but offset errors can cause small negative values 123 Zi LOG The ADC registers actually return 13 bits of data but the two LSBs are intended for com pensation use only When the software compensation routine is performed on the 13 bit raw ADC value two bits of resolution are lost because of a rounding error As a result the final value is an 11 bit number Hardware Overflow When the hardware overflow bit OVF is set in ADC Data Low Byte ADCD L register all other data bits are invalid The hardware overflow bit is set for values greater than Ver and less than V ef DIFFERENTIAL mode Automatic Powerdown If the ADC is idle no conversions in progress for 160 consecutive system clock cycles portions of the ADC are automatically powered down From this powerdown state the ADC requires 40 system clock cycles to power up The ADC powers up when a conversion is requested by the ADC Control register Single Shot Conversion PS022820 0307 When configured for single shot conversion the ADC performs a single analog to digital conversion on the selected analog input channel After completion of the conversion the ADC shuts down The steps for
166. dress Some port interrupts are not available on the 8 and 20 pin packages The ADC interrupt is unavailable on devices not containing an ADC Interrupt Controller Z8 Encore XP 8K and 4K Series Product Specification Zi Zi LOG Table 32 Trap and Interrupt Vectors in Order of Priority Program Memory Priority Vector Address Interrupt or Trap Source Highest 0002H Reset not an interrupt 0004H Watchdog Timer see chapter Watchdog Timer on page 91 003AH Primary Oscillator Fail Trap not an interrupt 003CH Watchdog Oscillator Fail Trap not an interrupt 0006H Illegal Instruction Trap not an interrupt 0008H Reserved 000AH Timer 1 000CH Timer 0 000EH UART 0 receiver 0010H UART 0 transmitter 0012H Reserved 0014H Reserved 0016H ADC 0018H Port A Pin 7 selectable rising or falling input edge or LVD see chapter Reset Stop Mode Recovery and Low Voltage Detection on page 23 001AH Port A Pin 6 selectable rising or falling input edge or Comparator Output 001CH Port A Pin 5 selectable rising or falling input edge 001EH Port A Pin 4 selectable rising or falling input edge 0020H Port A Pin 3 selectable rising or falling input edge 0022H Port A Pin 2 selectable rising or falling input edge 0024H Port A Pin 1 selectable rising or falling input edge 0026H Port A Pin 0 selectable rising or falling input edge 0028H Reserved 002AH Reserved 002CH Reserv
167. e enable the timer interrupt and set the timer interrupt priority by writing to the relevant interrupt registers 7 Configure the associated GPIO port pin for the Timer Output and Timer Output Complement alternate functions The Timer Output Complement function is shared with the Timer Input function for both timers Setting the timer mode to Dual PVM automatically switches the function from Timer In to Timer Out Complement 8 Write to the Timer Control register to enable the timer and initiate counting The PWM period is represented by the following equation Reload Value xPrescale PWM Period HUNE TPRIPE T GRPERRERU RET SOS System Clock Frequency Hz If an initial starting value other than 00014 is loaded into the Timer High and Low Byte registers the ONE SHOT mode equation determines the first PWM time out period If TPOL is set to O the ratio of the PWM output High time to the total period is repre sented by PWM Output High Time Ratio Reload Value PWM value Reload Value me If TPOL is set to 1 the ratio of the PWM output High time to the total period is repre sented by PWM Value PWM Output High Time Ratio Reload Value 100 CAPTURE Mode In CAPTURE mode the current timer count value is recorded when the appropriate exter nal Timer Input transition occurs The Capture count value is written to the Timer PWM High and Low Byte Registers The timer input is the system clock The TPOL bit in the Timer
168. e the following details the effects of REFSELH REFSELL this reference is independent of the Comparator reference 00 Internal Reference Disabled reference comes from external pin 01 Internal Reference set to 1 0 V 107 Internal Reference set to 2 0 V default 117 Reserved BUFMODE 2 0 Input Buffer Mode Select 000 Single ended unbuffered input 001 Single ended buffered input with unity gain 010 Reserved 011 Reserved 100 Differential unbuffered input 101 Differential buffered input with unity gain 110 Reserved 111 Reserved ADC Data High Byte Register The ADC Data High Byte ADCD_H register contains the upper eight bits of the ADC output The output is an 13 bit two s complement value During a single shot conversion this value is invalid Access to the ADC Data High Byte register is read only Reading the ADC Data High Byte register latches data in the ADC Low Bits register 0 0307 Analog to Digital Converter 132 Z8 Encore XP 8K and 4K Series Product Specification Liis Zi LOG Table 73 ADC Data High Byte Register ADCD H BITS 7 6 5 4 3 2 1 0 FIELD ADCDH RESET X X X X X X X X R W R R R R R R R R ADDR F72H X Undefined ADCDH ADC Data High Byte This byte contains the upper eight bits ofthe ADC output These bits are not valid during a single shot conversion During a continuous conversion the most recent conversion out
169. e Address POP dst Pop POPX dst Pop using Extended Addressing PUSH src Push PUSHX src Push using Extended Addressing Table 121 Logical Instructions Mnemonic Operands _ Instruction AND dst src Logical AND ANDX dst src Logical AND using Extended Addressing COM dst Complement OR dst src Logical OR ORX dst src Logical OR using Extended Addressing PS022820 0307 eZ8 CPU Instruction Set Z8 Encore XP 8K and 4K Series Product Specification Zi Zi LOG Table 121 Logical Instructions Mnemonic Operands Instruction KOR dst src Logical Exclusive OR XORX dst src Logical Exclusive OR using Extended Addressing Table 122 Program Control Instructions Mnemonic Operands Instruction BRK On Chip Debugger Break BTJ p bit src DA Bit Test and Jump BTJNZ bit src DA Bit Test and Jump if Non Zero BTJZ bit src DA Bit Test and Jump if Zero CALL dst Call Procedure DJNZ dst src RA Decrement and Jump Non Zero IRET Interrupt Return JP dst Jump JP cc dst Jump Conditional JR DA Jump Relative JR cc DA Jump Relative Conditional RET Return TRAP vector Software Trap Table 123 Rotate and Shift Instructions Mnemonic Operands Instruction BSWAP dst Bit Swap RL dst Rotate Left RLC dst Rotate Left through Carry RR dst Rotate Right RRC dst Rotate Right through Carry SRA dst Shift Right Arithmetic PS022820 0307 e
170. e DBGMODE bit of the OCDCTL register is automatically set to 1 0 Breakpoints are disabled 1 Breakpoints are enabled DBGACK Debug Acknowledge This bit enables the debug acknowledge feature If this bit is set to 1 the OCD sends a Debug Acknowledge character FFH to the host when a Breakpoint occurs 0 Debug Acknowledge is disabled 1 Debug Acknowledge is enabled Reserved Must be 0 RST Reset Setting this bit to 1 resets the Z8FO04xA Z8F04xA family device The device goes through On Chip Debugger Z8 Encore XP 8K and 4K Series Product Specification Ll Zi LOG a normal Power On Reset sequence with the exception that the On Chip Debugger is not reset This bit is automatically cleared to 0 at the end of reset 0 No effect 1 Reset the Flash Read Protect Option Bit device OCD Status Register The OCD Status register reports status information about the current state of the debugger and the system Table 107 OCD Status Register OCDSTAT BITS 7 6 5 2 1 0 FIELD DBG HALT FRPENB Reserved RESET 0 0 0 0 0 0 R W R R R R R R R DBG Debug Status 0 NORMAL mode 1 DEBUG mode HALT HALT Mode 0 Not in HALT mode 1 In HALT mode FRPENB Flash Read Protect Option Bit Enable 0 FRP bit enabled that allows disabling of many OCD commands 1 FRP bit has no effect Reserved Must be 0 PS022820 0307 On Chip Debugger Z8
171. e Function selected as defined in Table 15 in GPIO Alternate Functions section 1 Port Alternate Function selected as defined in Table 15 in GPIO Alternate Functions section General Purpose Input Output Port A C Input Data Registers Z8 Encore XP 8K and 4K Series Product Specification Zi Zi LOG Reading from the Port A C Input Data registers Table 27 returns the sampled values from the corresponding port pins The Port A C Input Data registers are read only The value returned for any unused ports is 0 Unused ports include those missing on the 8 and 28 pin packages as well as those missing on the ADC enabled 28 pin packages Table 27 Port A C Input Data Registers PxIN BITS 7 6 5 4 3 2 1 0 FIELD PIN7 PIN6 PIN5 PINA PIN3 PIN2 PIN1 PINO RESET X X X X X X X X R W R R R R R R R R ADDR FD2H FD6H FDAH X Undefined PIN 7 0 Port Input Data Sampled data from the corresponding port pin input 0 Input data is logical 0 Low 1 Input data is logical 1 High Port A D Output Data Register The Port A D Output Data register Table 28 controls the output data to the pins Table 28 Port A D Output Data Register PxOUT BITS 7 6 5 4 3 2 1 0 FIELD POUT7 POUT6 POUT5 POUT4 POUT3 POUT2 POUT POUTO RESET 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W ADDR FD3H FD7H FDBH FDFH POUTT 7 0 Port Output Data The
172. e PWM output to the assertion of its complement The steps for configuring a timer for PWM DUAL OUTPUT mode and initiating the PWM operation are as follows 1 Write to the Timer Control register to Disable the timer Configure the timer for PWM DUAL OUTPUT mode by writing the TMODE bits in the TxCTL 1 register and the TMODEHI bit in TxCTLO register Set the prescale value Set the initial logic level High or Low and PWM High Low transition for the Timer Output alternate function 2 Write to the Timer High and Low Byte registers to set the starting count value typically 0001H This only affects the first pass in PWM mode After the first timer reset in PWM mode counting always begins at the reset value of 00018 3 Wirite to the PWM High and Low Byte registers to set the PWM value 4 Write to the PWM Control register to set the PWM dead band delay value The deadband delay must be less than the duration of the positive phase of the PWM signal as defined by the PWM high and low byte registers It must also be less than the Timers 76 PS022820 0307 Z8 Encore XP 8K and 4K Series Product Specification 77 Zi LOG duration of the negative phase of the PWM signal as defined by the difference between the PWM registers and the Timer Reload registers 5 Write to the Timer Reload High and Low Byte registers to set the Reload value PWM period The Reload value must be greater than the PWM value 6 Ifappropriat
173. e Timer Reload High and Low Byte registers Upon reaching the Reload value the timer generates an interrupt the count value in the Timer High and Low Byte registers is reset to 0001H and counting resumes If the TPOL bit in the Timer Control register is set to 1 the Timer Output signal begins as a High 1 and transitions to a Low 0 when the timer value matches the PWM value The Timer Output signal returns to a High 1 after the timer reaches the Reload value and is reset to 0001H Timers 74 PS022820 0307 Z8 Encore XP 8K and 4K Series Product Specification 75 Zi LOG If the TPOL bit in the Timer Control register is set to 0 the Timer Output signal begins as a Low 0 and transitions to a High 1 when the timer value matches the PWM value The Timer Output signal returns to a Low 0 after the timer reaches the Reload value and is reset to 0001H The steps for configuring a timer for PWM SINGLE OUTPUT mode and initiating the PWM operation are as follows 1l Write to the Timer Control register to Disable the timer Configure the timer for PWM SINGLE OUTPUT mode Set the prescale value Set the initial logic level High or Low and PWM High Low transition for the Timer Output alternate function 2 Write to the Timer High and Low Byte registers to set the starting count value typically 0001H This only affects the first pass in PWM mode After the first timer reset in PWM mode counting always begins at the
174. e drops below the LVD threshold the LVD bit of the Reset Status RSTSTAT register is set to one This bit remains one until the low voltage condition goes away Reading or writing this bit does not clear it The LVD circuit can also generate an interrupt when so enabled Interrupt Vectors and Priority on page 58 The LVD bit is NOT latched so enabling the interrupt is the only way to guarantee detection of a transient low voltage event The LVD functionality depends on circuitry shared with the VBO block therefore disabling the VBO also disables the LVD Reset Register Definitions The following sections define the Reset registers Reset Status Register The Reset Status RSTSTAT register is a read only register that indicates the source of the most recent Reset event indicates a Stop Mode Recovery event and indicates a Watchdog Timer time out Reading this register resets the upper four bits to 0 This register shares its address with the Watchdog Timer control register which is write only Table 11 on page 31 PS022820 0307 Reset Stop Mode Recovery and Low Voltage Detection Z8 Encore XP 8K and 4K Series Product Specification ZiLOG Table 11 Reset Status Register RSTSTAT BITS 7 6 5 4 3 2 1 0 FIELD POR STOP WDT EXT Reserved LVD RESET See descriptions below 0 0 0 0 0 R W R R R R R R R R ADDR FFOH Reset or Stop Mode Recovery Event Power on reset 1 POR STOP WDT EXT
175. e enabled Reserved Must be 0 Interrupt Controller Z8 Encore XP 8K and 4K Series Product Specification Z Zi LOG PS022820 0307 Interrupt Controller Z8 Encore XP 8K and 4K Series Product Specification 69 Zi LOG Timers These Z8 Encore XP 8K and 4K Series products contain two 16 bit reloadable timers that can be used for timing event counting or generation of pulse width modulated PWM signals The timers feature include 16 bit reload counter Programmable prescaler with prescale values from 1 to 128 PWM output generation Capture and compare capability External input pin for timer input clock gating or capture signal External input pin signal frequency is limited to a maximum of one fourth the system clock frequency Timer output pin Timer interrupt In addition to the timers described in this chapter the Baud Rate Generator of the UART if unused may also provide basic timing functionality See chapter Universal Asynchro nous Receiver Transmitter on page 97 for information about using the Baud Rate Generator as an additional timer Architecture PS022820 0307 Figure 9 on page 70 illustrates the architecture of the timers Timers Z8 Encore XP 8K and 4K Series Product Specification ZiLOG a a ee ee EIE 1 Timer Block Data Timer Bus l Control Block Control 16 Bit Interrupt Timer gt l Reload Register PWM Interrup
176. e internal voltage reference level or to disable the internal reference The REFSELH bit is contained in the ADC Control Status Register 1 Set CEN to 1 to start the conversion CEN remains 1 while the conversion is in progress A single shot conversion requires 5129 system clock cycles to complete If a single shot conversion is requested from an ADC powered down state the ADC uses 40 additional clock cycles to power up before beginning the 5129 cycle conversion When the conversion is complete the ADC control logic performs the following operations 13 bit two s complement result written to ADCD H 7 0 ADCD L 7 3 Sends an interrupt request to the Interrupt Controller denoting conversion complete CEN resets to O to indicate the conversion is complete If the ADC remains idle for 160 consecutive system clock cycles it is automatically powered down Continuous Conversion When configured for continuous conversion the ADC continuously performs an analog to digital conversion on the selected analog input Each new data value over writes the previous value stored in the ADC Data registers An interrupt is generated after each conversion AN Caution In CONTINUOUS mode ADC updates are limited by the input signal bandwidth of the ADC and the latency of the ADC and its digital filter Step changes at the input are not immediately detected at the next output from the
177. e system clock freguency Typical Supply Current Active Mode 10 8 t 6 VDD 3 60V 30C a tbe a a 4 2 0 T T T 0 5 10 15 20 Freg MHz Figure 33 Typical Active Mode Ipp Versus System Clock Freguency PS022820 0307 Electrical Characteristics Z8 Encore XP 8K and 4K Series Product Specification 229 Zi LOG AC Characteristics The section provides information about the AC characteristics and timing All AC timing information assumes a standard load of 50 pF on all outputs Table 129 AC Characteristics Vpp 2 7 to 3 6 V TA 40 C to 105 C unless otherwise stated Symbol Parameter Minimum Maximum Units Conditions Fevscik System Clock Frequency 20 0 MHz Read only from Flash memory 0 032768 20 0 MHz Program or erasure of the Flash memory FxtaL Crystal Oscillator Frequency 20 0 MHz System clock frequencies below the crystal oscillator minimum require an external clock driver TxIN System Clock Period 50 ns Terk 1 Fsyscik TxinH System Clock High Time 20 30 ns TcLk 50 ns TXINL System Clock Low Time 20 30 ns TceLk 50 ns TxinR System Clock Rise Time 3 ns TeLk 50 ns TxiNp System Clock Fall Time 3 ns TcLk 50 ns PS022820 0307 Electrical Characteristics Z8 Encore XP 8K and 4K Series Product Specification Zi Zi LOG Table 130 Internal Precision Oscil
178. e the UART Control 1 register to select the outgoing address bit 8 Setthe Multiprocessor Bit Transmitter MPBT if sending an address byte clear it if sending a data byte 9 Wirite the data byte to the UART Transmit Data register The transmitter automatically transfers the data to the Transmit Shift register and transmits the data 10 Make any changes to the Multiprocessor Bit Transmitter MPBT value if appropriate and MULTIPROCESSOR mode is enabled 11 To transmit additional bytes return to Step 5 Transmitting Data using the Interrupt Driven Method PS022820 0307 The UART Transmitter interrupt indicates the availability of the Transmit Data register to accept new data for transmission Follow these steps to configure the UART for interrupt driven data transmission 1 Write to the UART Baud Rate High and Low Byte registers to set the appropriate baud rate 2 Enable the UART pin functions by configuring the associated GPIO Port pins for alternate function operation 3 Execute a DI instruction to disable interrupts 4 Wirite to the Interrupt control registers to enable the UART Transmitter interrupt and set the acceptable priority 5 Write to the UART Control 1 register to enable MULTIPROCESSOR 9 bit mode functions if MULTIPROCESSOR mode is appropriate 6 Setthe MULTIPROCESSOR Mode Select MPEN to Enable MULTIPROCESSOR mode 7 Wirite to the UART Control 0 register to Set the transmit enable b
179. eceiver Synchronization The IrDA receiver uses a local baud rate clock counter 0 to 15 clock periods to generate an input stream for the UART and to create a sampling window for detection of incoming pulses The generated UART input UART RXD is delayed by 8 baud rate clock periods with respect to the incoming IrDA data stream When a falling edge in the input data stream is detected the Endec counter is reset When the count reaches a value of 8 the UART RXD value is updated to reflect the value of the decoded data When the count reaches 12 baud clock periods the sampling window for the next incoming pulse opens The window remains open until the count again reaches 8 in other words 24 baud clock periods since the previous pulse was detected giving the Endec a sampling window of Infrared Encoder Decoder 119 Z8 Encore XP 8K and 4K Series Product Specification 120 Zi LOG minus four baud rate clocks to plus eight baud rate clocks around the expected time of an incoming pulse If an incoming pulse is detected inside this window this process is repeated If the incoming data is a logical 1 no pulse the Endec returns to the initial state and waits for the next falling edge As each falling edge is detected the Endec clock counter is reset resynchronizing the Endec to the incoming signal allowing the Endec to tolerate jitter and baud rate errors in the incoming datastream Resynchronizing the Endec does not alter the operation
180. echnical guestions about the product documentation or any other issues with ZiLOG s offerings please visit ZILOG s Knowledge Base at http www zilog com kb For any comments detail technical questions or reporting problems please visit ZiLOG s Technical Support at http support zilog com PS022820 0307 Customer Support Z8 Encore XP 8K and 4K Series Product Specification Za Zi LOG PS022820 0307 Customer Support
181. ed 002EH Reserved 0030H Port C Pin 3 both input edges 0032H Port C Pin 2 both input edges PS022820 0307 Interrupt Controller Z8 Encore XP 8K and 4K Series Product Specification Z 57 Zi LOG Table 32 Trap and Interrupt Vectors in Order of Priority Continued Program Memory Priority Vector Address Interrupt or Trap Source 0034H Port C Pin 1 both input edges Lowest 0036H Port C Pin 0 both input edges 0038H Reserved Architecture Figure 8 illustrates the interrupt controller block diagram High Port Interrupts Priority Vector Priority Mux IRQ Request Medium Priority Internal Interrupts Low JI Priority Interrupt Request Latches and Control Figure 8 Interrupt Controller Block Diagram Operation Master Interrupt Enable The master interrupt enable bit IRQE in the Interrupt Control register globally enables and disables interrupts PS022820 0307 Interrupt Controller Z8 Encore XP 8K and 4K Series Product Specification Z 58 ZiLOG Interrupts are globally enabled by any of the following actions Execution of an EI Enable Interrupt instruction Execution of an IRET Return from Interrupt instruction Writing a 1 to the IROE bit in the Interrupt Control register Interrupts are globally disabled by any of the following actions Execution of a DI Disable Interrupt instruction eZ8 CPU acknowledgement of an interrupt serv
182. ed High 1 upon PWM count match and forced Low 0 upon Reload Timers PS022820 0307 Z8 Encore XP 8K and 4K Series Product Specification Lla Zi LOG 1 Timer Output is forced High 1 when the timer is disabled When enabled the Timer Output is forced Low 0 upon PWM count match and forced High 1 upon Reload CAPTURE mode 0 Count is captured on the rising edge of the Timer Input signal 1 Count is captured on the falling edge of the Timer Input signal COMPARE mode When the timer is disabled the Timer Output signal is set to the value of this bit When the timer is enabled the Timer Output signal is complemented upon timer Reload GATED mode 0 Timer counts when the Timer Input signal is High 1 and interrupts are generated on the falling edge of the Timer Input 1 Timer counts when the Timer Input signal is Low 0 and interrupts are generated on the rising edge of the Timer Input CAPTURE COMPARE mode 0 Counting is started on the first rising edge of the Timer Input signal The current count is captured on subsequent rising edges of the Timer Input signal 1 Counting is started on the first falling edge of the Timer Input signal The current count is captured on subsequent falling edges of the Timer Input signal PWM DUAL OUTPUT mode 0 Timer Output is forced Low 0 and Timer Output Complement is forced High 1 when the timer is disabled When enabled the Timer Output is forced High 1 upon P
183. eload High and Low Byte registers The timer input is the system clock Upon reaching the Reload value the timer generates an interrupt the count value in the Timer High and Low Byte registers is reset to 0001H and counting resumes Also if the Timer Output alternate function is enabled the Timer Output pin changes state from Low to High or from High to Low at timer Reload The steps for configuring a timer for CONTINUOUS mode and initiating the count are as follows 1 Write to the Timer Control register to Disable the timer Configure the timer for CONTINUOUS mode Timers Z8 Encore XP 8K and 4K Series Product Specification 72 Zi LOG Set the prescale value Jfusing the Timer Output alternate function set the initial output level High or Low 2 Write to the Timer High and Low Byte registers to set the starting count value usually 0001H This action only affects the first pass in CONTINUOUS mode After the first timer Reload in CONTINUOUS mode counting always begins at the reset value of 0001H 3 Write to the Timer Reload High and Low Byte registers to set the Reload value 4 Enable the timer interrupt if appropriate and set the timer interrupt priority by writing to the relevant interrupt registers 5 Configure the associated GPIO port pin if using the Timer Output function for the Timer Output alternate function 6 Wirite to the Timer Control register to enable the timer and initiate counting
184. ena neti rer 169 Byte A eere E E es IA i a PA A 170 Power Failure Protection 171 Optimizing NVDS Memory Usage for Execution Speed 171 On ChipDebugger iius xk ox ORRRE ee ACER ERROR OR REACH ee el a 173 Architecture 173 Operation i dad tasmie a es RE PRU dur E ban roc a bu b oe as 174 OCD Interface 174 Table of Contents PS022820 0307 Z8 Encore XP 8K and 4K Series Product Specification ZiLOG DEBUG Mode 175 OCD Data Format 176 OCD Auto Baud Detector Generator 176 OCD Serial Errors 177 OCD Unlock Sequence 8 Pin Devices Only 178 Breakpoints 178 Runtime AAA es 179 On Chip Debugger Commands 179 On Chip Debugger Control Register Definitions 184 OCD Control Register 184 OCD Status Register e dor deos aac e cut dh Rn mmama Rit i SCR de ae 185 Oscillator Control 187 Operation AA AAA e RR AAA eR ERG AA 187 System Clock Selection 187 Clock Failure Detection and Recovery
185. eries ADC is factory calibrated for offset error and gain error with the compensation data stored in Flash memory Alternatively you can perform your own calibration storing the values into Flash themselves Thirdly the user code can perform a manual offset calibration during DIFFERENTIAL mode operation Factory Calibration Devices that have been factory calibrated contain 30 bytes of calibration data in the Flash option bit space This data consists of 3 bytes for each input mode one for offset and two for gain correction See ZiLOG Calibration Data on page 161 for a list of input modes for which calibration data exists User Calibration If you have precision references available its own external calibration can be performed using any input modes This calibration data takes into account buffer offset and non lin earity so it is recommended that this calibration be performed separately for each of the ADC input modes planned for use Manual Offset Calibration When uncalibrated the ADC has significant offset see Table 135 Analog to Digital Con verter Electrical Characteristics and Timing on page 233 for details Subsequently man ual offset calibration capability is built into the block When the ADC Control Register 0 sets the input mode ANAIN 2 0 to MANUAL OFFSET CALIBRATION mode the differential inputs to the ADC are shorted together by an internal switch Reading the ADC value at this point produces 0 in an ideal system
186. ering is opcode dependent The following instruction examples illustrate the format of some basic assembly instructions and the resulting object code produced by the assembler This binary format must be followed by users that prefer manual program coding or intend to implement their own assembler Example 1 If the contents of Registers 43H and 08H are added and the result is stored in 43H the assembly syntax and resulting object code is Table 112 Assembly Language Syntax Example 1 Assembly Language ADD 43H 08H ADD dst src Code Object Code 04 08 43 OPC src dst Example 2 In general when an instruction format requires an 8 bit register address that address can specify any register location in the range 0 255 or using Escaped Mode Addressing a Working Register RO R 15 If the contents of Register 43H and Working Register R8 are added and the result is stored in 43H the assembly syntax and resulting object code is Table 113 Assembly Language Syntax Example 2 Assembly Language ADD 43H R8 ADD dst src Code Object Code 04 E8 43 OPC src dst See the device specific Product Specification to determine the exact register file range available The register file size varies depending on the device type eZ8 CPU Instruction Notation In the eZ8 CPU Instruction Summary and Description sections the operands condition codes status flags and address modes are represented by a notational shorthand that is described in
187. eristics Table 127 DC Characteristics Continued Z8 Encore XP 8K and 4K Series Product Specification Zi Zi LOG TA 40 C to 105 C unless otherwise specified Symbol Parameter Minimum Typical Maximum Units Conditions Vout Low Level Output 0 4 V lg 2 mA Vpp 3 0 V Voltage High Output Drive disabled Vou High Level Output 2 4 V jlo 2 mA Vpp 3 0 V Voltage High Output Drive disabled VoL2 Low Level Output 0 6 V loL 20 mA Vpp 3 3 V Voltage High Output Drive enabled Vouo High Level Output 24 V lgu 20 mA Vpp 3 3 V Voltage High Output Drive enabled liu Input Leakage 30 002 5 HA Vin Vpp Current Vpp 3 3 V lu Input Leakage 30 007 5 HA ViN Vss Current Vpp 3 3 V lr Tristate Leakage 5 HA Current ILED Controlled Current 1 8 3 4 5 mA AFS2 AFS1 0 0 Dive 2 8 7 10 5 mA AFS2 AFS1 0 1 7 8 13 19 5 mA AFS2 AFS1 1 0 12 20 30 mA AFS2 AFS1 1 1 Cpap GPIO Port Pad 8 0 pF Capacitance Cyn XIN Pad 8 0 pF Capacitance Cxour XOUT Pad 9 5 pF Capacitance Ipu Weak Pull up 30 100 350 HA Vpp23 0V 3 6V Current Vram RAM Data TBD V Voltage at which RAM retains Retention Voltage static values no reading or writing is allowed Notes 1 This condition excludes all pins that have on chip pull ups when driven Low 2 These values are provided for design guid
188. et Reset as applicable Reset 66 Internal Precision Oscillator Cycles System Reset with Crystal Reset as applicable Reset 5000 Internal Precision Oscillator Cycles Oscillator Enabled Stop Mode Recovery Unaffected except Reset 66 Internal Precision Oscillator Cycles WDT CTL and IPO startup time OSC CTL registers Stop Mode Recovery with Unaffected except Reset 5000 Internal Precision Oscillator Cycles Crystal Oscillator Enabled WDT CTL and OSC CTL registers During a System Reset or Stop Mode Recovery the Internal Precision Oscillator requires 4 us to start up Then the Z8 Encore XP 8K and 4K Series device is held in Reset for 66 cycles of the Internal Precision Oscillator If the crystal oscillator is enabled in the Flash option bits this reset period is increased to 5000 IPO cycles When a reset occurs because of a low voltage condition or power on reset this delay is measured from the time that the supply voltage first exceeds the POR level discussed later in this chapter If the external pin reset remains asserted at the end of the reset period the device remains in reset until the pin is deasserted At the beginning of Reset all GPIO pins are configured as inputs with pull up resistor dis abled except PDO or PA2 on 8 pin devices which is shared with the reset pin On reset the PDO is configured as a bidirectional open drain reset The pin is internally driven low during port reset after which the user code may
189. etup For systems using an external TTL drive PB3 is the clock source for 20 and 28 pin devices In this case configure PB3 for alternate function CLKIN Write the Oscillator Control OSCCTL register page 190 such that the external oscillator is selected as the system clock For 8 pin devices use PA1 instead of PB3 PS022820 0307 General Purpose Input Output Z8 Encore XP 8K and 4K Series Product Specification ZI Zi LOG Table 14 Port Alternate Function Mapping Non 8 Pin Parts Alternate Function Set Port Pin Mnemonic Alternate Function Description Register AFS1 PAO TOIN TOOUT Timer 0 Input Timer 0 Output Complement N A Reserved PA1 TOOUT Timer 0 Output Reserved PA2 DEO UART 0 Driver Enable Reserved PA3 J CTSO UART 0 Clear to Send Reserved PA4 RXDO IRRXO UART 0 IrDA 0 Receive Data Reserved PA5 TXDO IRTXO UART 0 IrDA 0 Transmit Data Reserved PA6 TAIN T1OUT Timer 1 Input Timer 1 Output Complement Reserved PA7 T1OUT Timer 1 Output Port A Reserved Note Because there is only a single alternate function for each Port A pin the Alternate Function Set registers are not implemented for Port A Enabling alternate function selections as described in Port A D Alternate Function Sub Registers on page 48 automatically enables the associated alternate function Whether PAO PA6 take on the timer input or timer output complement function depends on the timer configuration as
190. ever the Timer Output function is not required to be enabled 2 Write to the Timer High and Low Byte registers to set the starting count value This action only affects the first pass in COMPARATOR COUNTER mode After the first timer Reload in COMPARATOR COUNTER mode counting always begins at the reset value of 0001H Generally in COMPARATOR COUNTER mode the Timer High and Low Byte registers must be written with the value 00018 3 Write to the Timer Reload High and Low Byte registers to set the Reload value 4 If appropriate enable the timer interrupt and set the timer interrupt priority by writing to the relevant interrupt registers 5 Ifusing the Timer Output function configure the associated GPIO port pin for the Timer Output alternate function 6 Write to the Timer Control register to enable the timer In COMPARATOR COUNTER mode the number of comparator output transitions since the timer start is given by the following equation Comparator Output Transitions Current Count Value Start Value PWM SINGLE OUTPUT Mode In PWM SINGLE OUTPUT mode the timer outputs a Pulse Width Modulator PWM output signal through a GPIO Port pin The timer input is the system clock The timer first counts up to the 16 bit PWM match value stored in the Timer PWM High and Low Byte registers When the timer count value matches the PWM value the Timer Output toggles The timer continues counting until it reaches the Reload value stored in th
191. ficient time such that the die and ambient temperatures converge this time is dependent on the thermal design of the system The temperature sensor measurement must then be made immediately after recovery from STOP mode The following equation defines the transfer function between the temperature sensor output voltage and the die temperature This is needed for comparator threshold measurements V 0 01 T 0 65 where T is the temperature in C V is the sensor output in Volts Temperature Sensor Z8 Encore XP 8K and 4K Series Product Specification 140 Zi LOG Assuming a compensated ADC measurement the following eguation defines the relation ship between the ADC reading and the die temperature T 25 128 ADC TSCAL 11 2 30 where T is the temperature in C ADC is the 10 bit compensated ADC value and TSCAL is the temperature sensor calibration value ignoring the two least significant bits of the 12 bit value See Temperature Sensor Calibration Data on page 164 for the location of TSCAL Calibration The temperature sensor undergoes calibration during the manufacturing process and is maximally accurate at 30 C Accuracy decreases as measured temperatures move further from the calibration point PS022820 0307 Temperature Sensor Flash Z8 Encore XP 8K and 4K Series Product Specification 141 Zi LOG Memory The products in the Z8 Encore KP 8K and 4K Series feature a non volatile Flash memory of 8
192. for programming and erase operations Programming operations are not limited to the page selected in the Page Select register Bits in the Flash Sector Protect register can be written to one or zero The second write of the Page Select register to unlock the Flash Controller is not necessary The Page Select register can be written when the Flash Controller is unlocked The Mass Erase command is enabled through the Flash Control register J Caution For security reasons the flash controller allows only a single page to be opened for write erase When writing multiple flash pages the flash controller must go through the unlock sequence again to select another page PS022820 0307 Flash Memory Z8 Encore XP 8K and 4K Series Product Specification Z 149 Zi LOG Flash Control Register Definitions Flash Control Register The Flash Controller must be unlocked using the Flash Control FCTL register before programming or erasing the Flash memory Writing the sequence 73H 8CH sequentially to the Flash Control register unlocks the Flash Controller When the Flash Controller is unlocked the Flash memory can be enabled for Mass Erase or Page Erase by writing the appropriate enable command to the FCTL Page Erase applies only to the active page selected in Flash Page Select register Mass Erase is enabled only through the On Chip Debugger Writing an invalid value or an invalid sequence returns the Flash Controller to Its loc
193. for use without external components You can either manually trim the oscillator for a non standard frequency or use the auto matic factory trimmed version to achieve a 5 53 MHz frequency IPO features include On chip RC oscillator that does not require external components Output frequency of either 5 53 MHz or 32 8 kHz contains both a fast and a slow mode Trimmed through Flash option bits with user override Elimination of crystals or ceramic resonators in applications where very high timing accuracy is not required Operation An 8 bit trimming register incorporated into the design compensates for absolute variation of oscillator frequency Once trimmed the oscillator frequency is stable and does not require subsequent calibration Trimming is performed during manufacturing and is not necessary for you to repeat unless a frequency other than 5 53 MHz fast mode or 32 8 kHz slow mode is required This trimming is done at 430 C and a supply voltage of 3 3 V so accuracy of this operating point is optimal If not used the IPO can be disabled by the Oscillator Control register see Oscillator Con trol Register Definitions on page 190 By default the oscillator frequency is set by the factory trim value stored in the write protected Flash information page However the user code can override these trim values as described in Trim Bit Address Space on page 158 Select one of two frequencies for the oscillator 5 53 MHz and 3
194. function TxOUT on a GPIO port pin is enabled PS022820 0307 TxOUT changes to whatever state the TPOL bit is in The timer does not need to be en abled for that to happen Also the Port data direction sub register is not needed to be set to output on TxOUT Changing the TPOL bit with the timer enabled and running does not immediately change the TxOUT PRES Prescale value The timer input clock is divided by 2PRES where PRES can be set from 0 to 7 The prescaler is reset each time the Timer is disabled This reset ensures proper clock division each time the Timer is restarted 000 Divide by 1 001 Divide by 2 010 Divide by 4 011 Divide by 8 100 Divide by 16 101 Divide by 32 110 Divide by 64 111 Divide by 128 TMODE Timer mode This field along with the TMODEHI bit in TxCTLO register determines the operating mode of the timer TMODEHI is the most significant bit of the Timer mode selection value The entire operating mode bits are expressed as TMODEHI TMODE 2 0 The TMODEHI is bit 7 of the TxCTLO register while TMODE 2 0 is the lower 3 bits of the TxCTLI register 0000 ONE SHOT mode 0001 CONTINUOUS mode 0010 COUNTER mode 0011 PWM SINGLE OUTPUT mode 0100 CAPTURE mode 0101 COMPARE mode 0110 GATED mode 0111 CAPTURE COMPARE mode 1000 PWM DUAL OUTPUT mode 1001 CAPTURE RESTART mode 1010 COMPARATOR COUNTER mode Timers Timer 0 1 High and Low Byte Registers The Timer 0 1 High and L
195. garding the eZ8 CPU refer to the eZ8 CPU User Manual avail able for download at www zilog com 10 Bit Analog to Digital Converter The optional analog to digital converter ADC converts an analog input signal to a 10 bit binary number The ADC accepts inputs from eight different analog input pins in both single ended and differential modes The ADC also features a unity gain buffer when high input impedance is required PS022820 0307 Overview Z8 Encore XP 8K and 4K Series Product Specification Zi LOG Low Power Operational Amplifier The optional low power operational amplifier LPO is a general purpose amplifier primarily targeted for current sense applications The LPO output may be routed internally to the ADC or externally to a pin Internal Precision Oscillator The internal precision oscillator IPO is a trimmable clock source that requires no external components Temperature Sensor The optional Temperature Sensor produces an analog output proportional to the device temperature This signal can be sent to either the ADC or the analog comparator Analog Comparator The analog comparator compares the signal at an input pin with either an internal pro grammable voltage reference or a second input pin The comparator output can be used to drive either an output pin or to generate an interrupt External Crystal Oscillator The crystal oscillator circuit provides highly accurate clock frequencies with the use of an
196. gister The next read from the Trim Bit Data register returns the work ing value of the target trim data byte The trim address range is from information address 20 3F only The remainder of the information page is not accessible through the trim bit address and data registers Calibration Option Bits The calibration option bits are also contained in the information page These bits are fac tory programmed values intended for use in software correcting the device s analog per formance To read these values the user code must employ the LDC instruction to access the information area of the address space as defined in See Flash Information Area on page 17 Serialization Bits As an optional feature ZiLOG is able to provide factory programmed serialization For serialized products the individual devices are programmed with unique serial numbers These serial numbers are binary values four bytes in length The numbers increase in size with each device but gaps in the serial sequence may exist These serial numbers are stored in the flash information page see Reading the Flash Infor mation Page on page 155 and Serialization Data on page 165 for more details and are unaffected by mass erasure of the device s flash memory Flash Option Bits 154 Z8 Encore XP 8K and 4K Series Product Specification 155 Zi LOG Randomized Lot Identification Bits As an optional feature ZILOG is able to provide a factory programmed random lot
197. gister Bus l l UART Timers ADC NVDS Flash RAM SAMBA Controller Controller Controller A A Y Low Temperature Power IrDA Sensor Op Amp Flash Memory RAM Y Y Y GPIO Figure 1 Z8 Encore XP 8K and 4K Series Block Diagram PS022820 0307 Overview Z8 Encore XP 8K and 4K Series Product Specification Zi LOG CPU and Peripheral Overview eZ8 CPU Features The eZ8 CPU ZiLOG s latest 8 bit Central Processing Unit CPU meets the continuing demand for faster and more code efficient microcontrollers The eZ8 CPU executes a superset of the original Z8 instruction set Its features include Direct register to register architecture allows each register to function as an accumulator improving execution time and decreasing the required program memory Software stack allows much greater depth in subroutine calls and interrupts than hardware stacks Compatible with existing Z8 code Expanded internal Register File allows access of up to 4 KB New instructions improve execution efficiency for code developed using higher level programming languages including C Pipelined instruction fetch and execution New instructions for improved performance including BIT BSWAP BTJ CPC LDC LDCI LEA MULT and SRL New instructions support 12 bit linear addressing of the Register File Up to 10 MIPS operation C Compiler friendly 2 to 9 clock cycles per instruction For more information re
198. h normal ADC mea surements on ANAO the LPO output This bit enables the amplifier even in STOP mode If the amplifier is not required in STOP mode disable it Failure to perform this results in STOP mode currents greater than specified This register is only reset during a POR sequence Other system reset events do not affect it Table 12 Power Control Register 0 PWRCTLO BITS 7 6 5 4 3 2 1 0 FIELD LPO Reserved VBO TEMP ADC COMP Reserved RESET 1 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W ADDR F80H gt Note PS022820 0307 LPO Low Power Operational Amplifier Disable 0 LPO is enabled this applies even in STOP mode 1 LPO is disabled Reserved Must be 0 VBO Voltage Brown Out Detector Disable This bit and the VBO_AO Flash option bit must both enable the VBO for the VBO to be active 0 VBO Enabled 1 VBO Disabled TEMP Temperature Sensor Disable 0 Temperature Sensor Enabled 1 Temperature Sensor Disabled ADC Analog to Digital Converter Disable 0 Analog to Digital Converter Enabled 1 Analog to Digital Converter Disabled COMP Comparator Disable 0 Comparator is Enabled 1 Comparator is Disabled Reserved Must be 0 Asserting any power control bit disables the targeted block regardless of any enable bits contained in the target block s control registers Low Power Modes 35 Z8 Encore XP 8K an
199. hard ware control interrupting only on frames that match the UART s address When an incoming address byte does not match the UART s address it is ignored All successive data bytes in this frame are also ignored When a matching address byte occurs an inter rupt is issued and further interrupts now occur on each successive data byte When the first data byte in the frame is read the NEWFRM bit of the UART Status 1 Register is asserted All successive data bytes have NEWFRM 0 When the next address byte occurs the hard ware compares it to the UART s address If there is a match the interrupts continues and the NEWFRM bit is set for the first byte of the new frame If there is no match the UART ignores all incoming bytes until the next address match The third scheme is enabled by setting MPMD 1 0 to 11 and by writing the UART s address into the UART Address Compare Register This mode is identical to the second scheme except that there are no interrupts on address bytes The first data byte of each frame remains accompanied by a NEWFRM assertion External Driver Enable The UART provides a Driver Enable DE signal for off chip bus transceivers This feature reduces the software overhead associated with using a GPIO pin to control the transceiver when communicating on a multi transceiver bus such as RS 485 PS022820 0307 Universal Asynchronous Receiver Transmitter 1 Z8 Encore XP 8K and 4K Series Product Specificat
200. hdog Calibration Low Byte at 007FH WDTCALL BITS 7 6 5 4 3 2 1 0 FIELD WDTCALL RESET U U U U U U U U R W R W R W R W R W R W R W R W R W ADDR Information Page Memory 007FH Note U Unchanged by Reset R W Read Write Serialization Data WDTCALL Watchdog Timer Calibration Low Byte The WDTCALH and WDTCALL bytes when loaded into the watchdog timer reload reg isters result in a one second timeout at room temperature and 3 3V supply voltage To use the watchdog timer calibration user code must load WDTU with 0x00 WDTH with WDTCALH and WDTL with WDTCALL Table 99 Serial Number at 001C 001F S NUM BITS 7 6 5 4 3 2 1 0 FIELD S_NUM RESET U U U U U U U U R W R W R W R W R W R W R W R W R W ADDR Information Page Memory 001C 001F Note U Unchanged by Reset R W Read Write S_NUM Serial Number Byte The serial number is a unique four byte binary value PS022820 0307 Flash Option Bits 165 Z8 Encore XP 8K and 4K Series Product Specification Zi Zi LOG Table 100 Serialization Data Locations Info Page Memory Address Address Usage 1C FE1C Serial Number Byte 3 most significant 1D FE1D Serial Number Byte 2 1E FE1E Serial Number Byte 1 1F FE1F Serial Number Byte 0 least significant Randomized Lot Identifier Table 101 Lot Identification Number RAND_LOT
201. he 20 pin Small Shrink Outline Package SSOP available for the Z8 Encore XP 8K and 4K Series devices DETAIL A 5 Fs a em ure rues un e d TERN A tio Ls SEATING PLANE 4 CONTROLLING OIMENSIONS MM LEADS ARE COPLANAR WITHIN 004 INCH L d DETAIL A Figure 44 20 Pin Small Shrink Outline Package SSOP PS022820 0307 Packaging Z8 Encore XP 8K and 4K Series Product Specification 249 Zi LOG Figure 45 illustrates the 28 pin Plastic Dual Inline Package PDIP available for the Z8 Encore XP 8K and 4K Series devices vugoL opr amp MILLIMETER INCH Liririririririririririririri MIN MAX MIN MAK A1 0 38 1 02 015 040 A2 3 18 4 19 125 165 B 0 38 0 53 015 021 D E1 Bl 01 1 40 1 65 055 065 02 1 14 1 40 045 055 C 0 23 0 38 009 015 P D 01 3658 37 34 1440 1470 1 44 02 3531 3594 1390 1415 D E 1524 1575 600 620 gp o 13 59 14 10 535 555 02 1283 13 08 505 515 E 2 54 TYP 100 BSC gi eA 1549 16 76 610 660 1 4 or L 3 05 3 81 120 150 NE A2 ar 0 140 1 91 055 075 rn 02 140 1 78 055 070 L f c 01 152 229 060 090 F B i 02 1 02 152 440 060 Ls La o H hH a 41 CONTROLLING DIMENSIONS INCH OPTION TABLE OPTION PACKAGE 01 STANDARD 02 IDF Note ZiLOG supplies both options for pr
202. he clock failure circuitry SOFEN must be deasserted in the OSCCTL register Watchdog Timer Failure In the event of a Watchdog Timer oscillator failure a similar non maskable interrupt like event is issued This event does not trigger an attendant clock switch over but alerts the CPU of the failure After a Watchdog Timer failure it is no longer possible to detect a pri mary oscillator failure The failure detection circuitry does not function if the Watchdog Timer is used as the system clock oscillator or if the Watchdog Timer oscillator has been disabled For either of these cases it 1s necessary to disable the detection circuitry by deasserting the WDFEN bit of the OSCCTL register The Watchdog Timer oscillator failure detection circuit counts system clocks while looking for a Watchdog Timer clock The logic counts 8004 system clock cycles before determining that a failure has occurred The system clock rate determines the speed at Oscillator Control Z8 Encore XP 8K and 4K Series Product Specification 190 Zi LOG which the Watchdog Timer failure can be detected A very slow system clock results in very slow detection times UN Caution It is possible to disable the clock failure detection circuitry as well as all functioning clock sources In this case the Z8 Encore XP 8K and 4K Series device ceases functioning and can only be recovered by power on reset Oscillator Control Register Definitions Oscillator Control
203. ice request from the interrupt controller Writing a 0 to the IROE bit in the Interrupt Control register Reset Execution of a Trap instruction Illegal Instruction Trap Primary Oscillator Fail Trap Watchdog Oscillator Fail Trap Interrupt Vectors and Priority The interrupt controller supports three levels of interrupt priority Level 3 is the highest priority Level 2 is the second highest priority and Level 1 is the lowest priority If all of the interrupts are enabled with identical interrupt priority all as Level 2 interrupts for example the interrupt priority 1s assigned from highest to lowest as specified in Table 32 on page 56 Level 3 interrupts are always assigned higher priority than Level 2 interrupts which in turn always are assigned higher priority than Level 1 interrupts Within each interrupt priority level Level 1 Level 2 or Level 3 priority is assigned as specified in Table 32 above Reset Watchdog Timer interrupt 1f enabled Primary Oscillator Fail Trap Watchdog Oscillator Fail Trap and Illegal Instruction Trap always have highest level 3 priority Interrupt Assertion PS022820 0307 Interrupt sources assert their interrupt requests for only a single system clock period sin gle pulse When the interrupt request is acknowledged by the eZ8 CPU the correspond ing bit in the Interrupt Request register is cleared until the next interrupt occurs Writing a 0 to the corresponding bi
204. igh and Low Byte TxRH and TxRL registers Table 52 and Table 53 store a 16 bit reload value TRH 7 0 TRL 7 0 Values written to the Timer Reload High Byte register are stored in a temporary holding register When a write to the Timer Reload Low Byte register occurs the temporary holding register value is written to the Timer High Byte register This operation allows simultaneous updates of the 16 bit Timer Reload value In COMPARE mode the Timer Reload High and Low Byte registers store the 16 bit Compare value PS022820 0307 Timers Z8 Encore XP 8K and 4K Series Product Specification ZI Zi LOG Table 52 Timer 0 1 Reload High Byte Register TxRH BITS 7 6 5 4 3 2 1 0 FIELD TRH RESET 1 1 1 1 1 1 1 1 R W R W R W R W R W R W R W R W R W ADDR F02H FOAH Table 53 Timer 0 1 Reload Low Byte Register TxRL BITS 7 6 5 4 3 2 1 0 FIELD TRL RESET 1 1 1 1 1 1 1 1 R W R W R W R W R W R W R W R W R W ADDR FO3H FOBH TRH and TRL Timer Reload Register High and Low These two bytes form the 16 bit Reload value TRH 7 0 TRL 7 0 This value sets the maximum count value which initiates a timer reload to 0001H In Compare mode these two bytes form the 16 bit Compare value Timer 0 1 PWM High and Low Byte Registers The Timer 0 1 PWM High and Low Byte TXPWMH and TxPWML registers Table 54 and Ta
205. im Bit Data Register TRMDR BITS 7 6 5 4 3 2 1 0 FIELD TRMDR Trim Bit Data RESET 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W ADDR FF7H Flash Option Bit Address Space The first two bytes of Flash program memory at addresses 0000H and 0001H are reserved for the user programmable Flash option bits Flash Program Memory Address 0000H Table 86 Flash Option Bits at Program Memory Address 0000H BITS 7 6 5 4 3 2 1 0 FIELD WDT RES WDT AO OSC SEL 1 0 VBO AO FRP Reserved FWP RESET U U U U U U U U R W R W R W R W R W R W R W R W R W ADDR Program Memory 0000H Note U Unchanged by Reset R W Read Write PS022820 0307 WDT_RES Watchdog Timer Reset 0 Watchdog Timer time out generates an interrupt request Interrupts must be globally enabled for the eZ8 CPU to acknowledge the interrupt request 1 Watchdog Timer time out causes a system reset This setting is the default for unpro grammed erased Flash WDT AO Watchdog Timer Always On 0 Watchdog Timer is automatically enabled upon application of system power Watch dog Timer can not be disabled 1 Watchdog Timer is enabled upon execution of the WDT instruction Once enabled the Watchdog Timer can only be disabled by a Reset or Stop Mode Recovery This setting is the default for unprogrammed erased Flash Flash Option Bits Z8 Encore X
206. increases accuracy near the new calibration point General Purpose I O Port Input Data Sample Timing Figure 34 illustrates timing of the GPIO Port input sampling The input value on a GPIO Port pin is sampled on the rising edge of the system clock The Port value is available to the eZ8 CPU on the second rising clock edge following the change of the Port value PS022820 0307 Electrical Characteristics System Clock Port Pin Input Value Port Input Data Register Latch Z8 Encore XP 8K and 4K Series Product Specification Zi Zi LOG TCLK Port Value Changes to 0 0 Latched Into Port Input Data Register Port Input Data Register Port Input Data Value 0 Read Read on Data Bus ae by eZ8 Figure 34 Port Input Sample Timing Table 139 GPIO Port Input Timing Delay ns Parameter Abbreviation Minimum Maximum Ts port Port Input Transition to XIN Rise Setup Time 5 Not pictured TH port XIN Rise to Port Input Transition Hold Time 0 Not pictured TSMR GPIO Port Pin Pulse Width to ensure Stop Mode Recovery 1us PS022820 0307 for GPIO Port Pins enabled as SMR sources Electrical Characteristics Z8 Encore XP 8K and 4K Series Product Specification Z 238 ZiLOG General Purpose I O Port Output Timing Figure 35 and Table 140 provide timing information for GPIO Port pins TCLK ma lt w f N Port Ou
207. ing the most recent attempted write to the NVDS array DWE Data Write Error A data byte failure occurred during the most recent attempted write to the NVDS array Byte Read PS022820 0307 To read a byte from the NVDS array user code must first push the address onto the stack User code issues a CALL instruction to the address of the byte read routine 0x1000 At Non Volatile Data Storage Z8 Encore XP 8K and 4K Series Product Specification 171 Zi LOG the return from the sub routine the read byte resides in working register RO and the read status byte resides in working register R1 The contents of the status byte are undefined for read operations to illegal addresses Also the user code must pop the address byte off the stack The read routine uses 9 bytes of stack space in addition to the one byte of address pushed by the user Sufficient memory must be available for this stack usage Because of the Flash memory architecture NVDS reads exhibit a non uniform execution time A read operation takes between 44 us and 489 us assuming a 20 MHz system clock Slower system clock speeds result in proportionally higher execution times NVDS byte reads from invalid addresses those exceeding the NVDS array size return Oxff Illegal read operations have a 2 us execution time The status byte returned by the NVDS read routine is zero for successful read as determined by a CRC check If the status byte is non zero there was
208. inverting input and ANA2 is the non inverting input Operation To use the LPO it must be enabled in the Power Control Register 0 PWRCTLO The default state of the LPO is OFF To use the LPO the LPO bit must be cleared turning it ON Power Control Register 0 PWRCTLO on page 35 When making normal ADC measurements on ANAO measurements not involving the LPO output the LPO bit must be OFF Turning the LPO bit ON interferes with normal ADC measurements n The LPO bit enables the amplifier even in STOP mode If the amplifier is not AN Warning required in STOP mode disable it Failing to perform this results in STOP mode currents higher than necessary As with other ADC measurements any pins used for analog purposes must be configured as such in the GPIO registers see Port A D Alternate Function Sub Registers on page 48 LPO output measurements are made on ANAO as selected by the ANAIN 3 0 bits of ADC Control Register 0 It is also possible to make single ended measurements on ANA1 and ANA2 while the amplifier is enabled which is often useful for determining offset con ditions Differential measurements between ANAO and ANA2 may be useful for noise cancellation purposes If the LPO output is routed to the ADC then the BUFFMODE 2 0 bits of ADC Control Sta tus Register 1 must also be configured for unity gain buffered operation Sampling the LPO m an unbuffered mode is not recommended When either input is overdriven the a
209. ion Value is a function of the result of the operation 0 Reset to 0 Unaffected 1 Set to 1 X Undefined PS022820 0307 eZ8 CPU Instruction Set Z8 Encore XP 8K and 4K Series Product Specification VAR ZiLOG Table 124 eZ8 CPU Instruction Summary Continued Assembly Symbolic Address Mode Opcode s Flags Fetch Instr Mnemonic Operation dst src Hex Cycles Cycles RR dst R EO soon o XU cg 2 2 PEPEPEPE R E1 2 3 dst Oo N o o I RRC dst R co UE EE M Te 2 2 aes oD a nac pm IR C1 2 3 SBC dst src dst dst src C r r 32 MD ae E E 2 3 r Ir 33 2 4 R R 34 3 3 R IR 35 3 4 R IM 36 3 3 IR IM 37 3 4 SBCX dst src dst dst src C ER ER 38 2o Er se um Vp 5 4 3 ER IM 39 4 3 SCF C 1 DF 1 1 2 SRA dst A R DO 0 2 2 PEEEEEEE IR Di 2 3 SRL dst o ppp 7 R 1F CO Tow WA mo 3 2 D IR 1F C1 3 3 SRP src RP lt src IM 01 2 2 STOP STOP Mode 6F 1 2 SUB dst src dst dst src r r 22 e eO e Uwe cd ow 2 3 r Ir 23 2 4 R R 24 3 3 R IR 25 3 4 R IM 26 3 3 IR IM 27 3 4 Flags Notation Value is a function of the result of the operation 0 Reset to 0 Unaffected 1 Set to 1 X Undefined PS022820 0307 eZ8 CPU Instruction Set Z8 Encore XP 8K and 4K Series Product Specification Zi
210. ion 105 Zi LOG Driver Enable is an active High signal that envelopes the entire transmitted data frame including parity and Stop bits as illustrated in Figure 14 The Driver Enable signal asserts when a byte is written to the UART Transmit Data register The Driver Enable signal asserts at least one UART bit period and no greater than two UART bit periods before the Start bit 1s transmitted This allows a setup time to enable the transceiver The Driver Enable signal deasserts one system clock period after the final Stop bit is transmitted This one system clock delay allows both time for data to clear the transceiver before disabling it as well as the ability to determine if another character follows the current character In the event of back to back characters new data must be written to the Transmit Data Regis ter before the previous character is completely transmitted the DE signal is not deasserted between characters The DEPOL bit in the UART Control Register 1 sets the polarity of DE 0 Idle State of Line Isb msb 1 T Start BitO X Biti X Bit2 y Bit3 Bit4 Bit5 Bit6 Bit7 Y Perv 0 gang the Driver Enable signal lt Data Field gt Stop Bit 1 1 Figure 14 UART Driver Enable Signal Timing shown with 1 Stop Bit and Parity Rate Hz mu The Driver Enable to Start bit setup time is calculated as follows 1 i i lt DE to Start Bit Setup Time s Baud Rate Hz UA
211. ister or register pair to be indexed is offset by the signed Index value Index in a 127 to 128 range Table 115 lists additional symbols that are used throughout the Instruction Summary and Instruction Set Description sections PS022820 0307 eZ8 CPU Instruction Set Z8 Encore XP 8K and 4K Series Product Specification Z 204 Zi LOG Table 115 Additional Symbols Symbol dst Definition Destination Operand src Source Operand Indirect Address Prefix SP Stack Pointer PC Program Counter FLAGS Flags Register RP Register Pointer Immediate Operand Prefix B Binary Number Suffix Hexadecimal Number Prefix H Hexadecimal Number Suffix Assignment of a value is indicated by an arrow For example dst dst src indicates the source data is added to the destination data and the result is stored in the des tination location eZ8 CPU Instruction Classes PS022820 0307 eZ8 CPU instructions can be divided functionally into the following groups Arithmetic Bit Manipulation Block Transfer CPU Control Load Logical Program Control Rotate and Shift eZ8 CPU Instruction Set Z8 Encore XP 8K and 4K Series Product Specification Zi Zi LOG Table 116 through Table 123 contain the instructions belonging to each group and the number of operands required for each instruction Some instructions appear in more than o
212. it TEN to enable the UART for data transmission Enable parity if appropriate and if MULTIPROCESSOR mode is not enabled and select either even or odd parity Setor clear CTSE to enable or disable control from the remote receiver using the CTS pin 8 Execute an EI instruction to enable interrupts Universal Asynchronous Receiver Transmitter 100 Z8 Encore XP 8K and 4K Series Product Specification L o ZiLOG The UART is now configured for interrupt driven data transmission Because the UART Transmit Data register is empty an interrupt is generated immediately When the UART Transmit interrupt is detected the associated interrupt service routine ISR performs the following 1 Write the UART Control 1 register to select the multiprocessor bit for the byte to be transmitted Set the Multiprocessor Bit Transmitter MPBT if sending an address byte clear it if sending a data byte Write the data byte to the UART Transmit Data register The transmitter automatically transfers the data to the Transmit Shift register and transmits the data Clear the UART Transmit interrupt bit in the applicable Interrupt Request register Execute the IRET instruction to return from the interrupt service routine and wait for the Transmit Data register to again become empty Receiving Data using the Polled Method Follow these steps to configure the UART for polled data reception 1 PS022820 0307 Write to the
213. it does exhibit non unity gain Designing the ADC with sub unity gain reduces noise across the ADC range but requires the ADC results to be scaled by a factor of 8 7 ADC Compensation Details PS022820 0307 High efficiency assembly code that performs this compensation is available for download on www zilog com The following is a bit specific description of the ADC compensation process used by this code The following data bit definitions are used 0 9 a f bit indices in hexadecimal s sign bit v overflow bit unused Input Data MSB LSB sba9 8765 4 210 S 5432 SSsss 765 4 2 10 0 sedcba 98g 7 5 43 2 ADC Offset Gain ADC Output Word if v 1 the data is invalid Offset Correction Byte Offset Byte shifted to align with ADC data Gain Correction Word Analog to Digital Converter Compensation Steps l Correct for Offset ADC MSB ADC LSB Offset MSB Offset LSB 1 MSB 1 LSB Z8 Encore XP 8K and 4K Series Product Specification Ll Zi LOG Take absolute value ofthe offset corrected ADC value if negative the gain correction factor is computed assuming positive numbers with sign restoration afterward 2 MSB 2 LSB AGain MSB AGain LSB Also take absolute value of the gain correction word if negative Multiply by Gain Correction Word If in DIFFERENTIAL mode
214. ked state The Write only Flash Control Register shares its Register File address with the read only Flash Status Register Table 78 Flash Control Register FCTL BITS 7 6 5 4 3 2 1 0 FIELD FCMD RESET 0 0 0 0 0 0 0 0 R W W W W W W W W W ADDR FF8H PS022820 0307 FCMD Flash Command 73H First unlock command 8CH Second unlock command 95H Page Erase command must be third command in sequence to initiate Page Erase 63H Mass Erase command must be third command in sequence to initiate Mass Erase SEH Enable Flash Sector Protect Register Access Flash Memory Z8 Encore XP 8K and 4K Series Product Specification 150 Zi LOG Flash Status Register The Flash Status FSTAT register indicates the current state of the Flash Controller This register can be read at any time The read only Flash Status register shares its Register File address with the Write only Flash Control register Table 79 Flash Status Register FSTAT BITS 7 6 5 4 3 2 1 0 FIELD Reserved FSTAT RESET 0 0 0 0 0 0 0 R W R R R R R R R R ADDR FF8H Reserved Must be 0 FSTAT Flash Controller Status 000000 Flash Controller locked 000001 First unlock command received 73H written 000010 Second unlock command received 8CH written 000011 Flash Controller unlocked 000100 Sector protect register selected 001xxx Program
215. l 2 0 V 17 FE17 Positive Gain Low Differential Unbuffered External 2 0 V Byte 34 FE34 Negative Gain Differential Unbuffered External 2 0 V High Byte 35 FE35 Negative Gain Low Differential Unbuffered External 2 0 V Byte 78 FE78 Offset Differential 1x Buffered Internal 2 0 V 18 FE18 Positive Gain High Differential 1x Buffered Internal 2 0 V Byte 19 FE19 Positive Gain Low Differential 1x Buffered Internal 2 0 V Byte 36 FE36 Negative Gain Differential 1x Buffered Internal 2 0 V High Byte 37 FE37 Negative Gain Low Differential 1x Buffered Internal 2 0 V Byte 7B FE7B Offset Differential 1x Buffered External 2 0 V 1A FE1A Positive Gain High Differential 1x Buffered External 2 0 V Byte 1B FE1B Positive Gain Low Differential 1x Buffered External 2 0 V Byte 38 FE38 Negative Gain Differential 1x Buffered External 2 0 V High Byte 39 FE39 Negative Gain Low Differential 1x Buffered External 2 0 V PS022820 0307 Byte Flash Option Bits Z8 Encore XP 8K and 4K Series Product Specification Z 164 Zi LOG Temperature Sensor Calibration Data Table 95 Temperature Sensor Calibration High Byte at 003A TSCALH BITS 7 6 5 4 3 2 1 0 FIELD TSCALH RESET U U U U U U U U R W R W R W R W R W R W R W R W R W ADDR Information Page Memory 003A Note U Unchanged by Reset R W Read Write TSCALH Temperature Sensor Calibration High Byte The TSCALH and TSCALL bytes combine to form the
216. lash status FSTAT 150 GPIO port A H address PXADDR 46 GPIO port A H alternate function sub regis ters 48 GPIO port A H control address PxCTL 47 GPIO port A H data direction sub registers 47 OCD control 184 OCD status 185 UARTx baud rate high byte UxBRH 114 UARTx baud rate low byte UxBRL 114 UARTx Control 0 UxCTLO 108 114 UARTx control 1 UxCTL1 109 UARTx receive data UxRXD 113 UARTx status 0 UxSTATO 111 UARTx status 1 UxSTAT1 112 UARTx transmit data UxTXD 113 watch dog timer control WDTCTL 31 94 136 190 watch dog timer reload high byte WDTH 95 watch dog timer reload low byte WDTL 96 watch dog timer reload upper byte WDTU 95 register file 15 register pair 203 register pointer 204 reset and stop mode characteristics 24 and stop mode recovery 23 carry flag 206 sources 25 RET 208 return 208 RL 208 PS022820 0307 Z8 Encore XP 8K and 4K Series Product Specification Zi Zi LOG RLC 208 rotate and shift instuctions 208 rotate left 208 rotate left through carry 208 rotate right 208 rotate right through carry 208 RP 204 RR 203 208 rr 203 RRC 208 S SBC 205 SCF 206 second opcode map after 1FH 221 set carry flag 206 set register pointer 207 shift right arithmatic 208 shift right logical 209 signal descriptions 11 single sho conversion ADC 123 software trap 208 source operand 204 SP 204 SRA 208 src 204 SRL 209 SRP 207 stack pointer 204 STOP 207 stop mode 33 2
217. lator Electrical Characteristics Vpp 2 7 to 3 6V TA 40 C to 105 C unless otherwise stated Symbol Parameter Minimum Typical Maximum Units Conditions Fipo Internal Precision Oscillator 5 53 MHz Vpp 3 3 V Frequency High Speed Ta 30 C Fipo Internal Precision Oscillator 32 7 kHz Vpp 3 3 V Frequency Low Speed Ta 30 C Fipo Internal Precision Oscillator 1 4 Error Tipost Internal Precision Oscillator 3 Hus Startup Time PS022820 0307 Electrical Characteristics Z8 Encore XP 8K and 4K Series Product Specification AR Zi LOG On Chip Peripheral AC and DC Electrical Characteristics Table 131 Power On Reset and Voltage Brown Out Electrical Characteristics and Timing TA 40 C to 105 C pin pulse rejection period Symbol Parameter Minimum Typical Maximum Units Conditions VPoR Power on reset Voltage 2 20 2 45 2 70 V VVpp Vpor Threshold VvBo Voltage Brown Out 2 15 2 40 2 65 V Vpp Vypo Reset Voltage Threshold Vpor to Vypo hysteresis 50 75 mv Starting Vpp voltage to Vss V ensure valid Power on reset TANA Power on reset Analog 70 HS Vpp gt Vpog Tpog Digital Delay Reset delay follows TANA TPoR Power on reset Digital 16 Hs 166 Internal Precision Delay Oscillator cycles IPO startup time Tipos Tpor Power on reset Digital 1 ms 5000 Internal Precision Delay
218. le Ended Unbuffered External 2 0 V 0D FEOD Gain Low Byte Single Ended Unbuffered External 2 0 V 69 FE69 Offset Single Ended 1x Buffered Internal 2 0 V OE FEOE Gain High Byte Single Ended 1x Buffered Internal 2 0 V OF FEOF Gain Low Byte Single Ended 1x Buffered Internal 2 0 V 6C FE6C Offset Single Ended 1x Buffered External 2 0 V 10 FE10 Gain High Byte Single Ended 1x Buffered External 2 0 V 11 FE11 Gain Low Byte Single Ended 1x Buffered External 2 0 V 6F FE6F Offset Differential Unbuffered Internal 2 0 V 12 FE12 a Gain High Differential Unbuffered Internal 2 0 V 13 FE13 En Gain Low Differential Unbuffered Internal 2 0 V Negative Gain 30 FE30 Differential Unbuffered Internal 2 0 V High Byte 31 FE31 ce Gain Low Differential Unbuffered Internal 2 0 V 72 FE72 Offset Differential Unbuffered Internal 1 0 V 14 FE14 a Gain High Differential Unbuffered Internal 1 0 V 15 FE15 and Gain Low Differential Unbuffered Internal 1 0 V Negative Gain 32 FE32 Differential Unbuffered Internal 1 0 V High Byte PS022820 0307 Flash Option Bits Z8 Encore XP 8K and 4K Series Product Specification Ll i ZiLOG Table 94 ADC Calibration Data Location Continued Info Page Memory Compensation Reference Address Address Usage ADC Mode Type 33 FE33 alld Gain LOW Ditterential Unbuffered Internal 1 0 V 75 FE75 Offset Differential Unbuffered External 2 0 V 16 FE16 eC Gain High pie rential Unbuffered Externa
219. le only for low noise designs with clean signals Table 105 lists minimum and recommended maximum baud rates for sample crystal frequencies Table 105 OCD Baud Rate Limits System Clock Recommended Recommended Frequency Maximum Baud Standard PC Minimum Baud MHz Rate Kbps Baud Rate bps Rate Kbps 20 0 2500 0 1 843 200 39 1 0 125 0 115 200 1 95 0 032768 32 kHz 4 096 2 400 0 064 If the OCD receives a Serial Break nine or more continuous bits Low the Auto Baud Detector Generator resets Reconfigure the Auto Baud Detector Generator by sending 80H OCD Serial Errors PS022820 0307 The On Chip Debugger can detect any of the following error conditions on the DBG pin Serial Break a minimum of nine continuous bits Low Framing Error received Stop bit is Low Transmit Collision OCD and host simultaneous transmission detected by the OCD When the OCD detects one of these errors it aborts any command currently in progress transmits a four character long Serial Break back to the host and resets the Auto Baud Detector Generator A Framing Error or Transmit Collision may be caused by the host sending a Serial Break to the OCD Because of the open drain nature of the interface returning a Serial Break break back to the host only extends the length of the Serial Break if the host releases the Serial Break early The host transmits a Serial Break on the DBG pin when first connecting to the Z8 Encore XP 8K and 4K Se
220. lowing provides more detailed information about each of the Stop Mode Recovery sources Table 10 Stop Mode Recovery Sources and Resulting Action Operating Mode Stop Mode Recovery Source Action STOP mode Watchdog Timer time out Stop Mode Recovery when configured for Reset Watchdog Timer time out Stop Mode Recovery followed by interrupt when configured for interrupt if interrupts are enabled Data transition on any GPIO Port pin Stop Mode Recovery enabled as a Stop Mode Recovery source Assertion of external RESET Pin System Reset Debug Pin driven Low System Reset Stop Mode Recovery Using Watchdog Timer Time Out If the Watchdog Timer times out during STOP mode the device undergoes a Stop Mode Recovery sequence In the Reset Status RSTSTAT register the WDT and STOP bits are set to 1 If the Watchdog Timer is configured to generate an interrupt upon time out and the Z8 Encore XP 8K and 4K Series device is configured to respond to interrupts the eZ8 CPU services the Watchdog Timer interrupt request following the normal Stop Mode Recovery sequence Stop Mode Recovery Using a GPIO Port Pin Transition Each of the GPIO Port pins may be configured as a Stop Mode Recovery input source On any GPIO pin enabled as a Stop Mode Recovery source a change in the input pin value from High to Low or from Low to High initiates Stop Mode Recovery Note that SMR pulses shorter than specified does not trigger a recovery See
221. maximum logical value 1023 or less than the minimum logical value 1024 Unlike the hardware overflow bit this is not a simple binary flag For a normal sample non overflow the sign and the overflow bit matches If the sign bit and overflow bit do not match a computational overflow has occurred Input Buffer Stage PS022820 0307 Many applications require the measurement of an input voltage source with a high output impedance This ADC provides a buffered input for such situations The drawback of the buffered input is a limitation of the input range When using unity gain buffered mode the input signal must be prevented from coming too close to either Vss or Vpp See Table 135 Analog to Digital Converter Electrical Characteristics and Timing on page 233 for details This condition applies only to the input voltage level with respect to ground of each dif ferential input signal The actual differential input voltage magnitude may be less than 300 mV The input range of the unbuffered ADC swings from Vss to Vpp Input signals smaller than 300 mV must use the unbuffered input mode If these signals do not contain low out put impedances they might require off chip buffering Signals outside the allowable input range can be used without instability or device dam age Any ADC readings made outside the input range are subject to greater inaccuracy than specified Analog to Digital Converter Z8 Encore XP 8K and 4K Series Pr
222. mitter is awaiting service ADCI ADC Interrupt Request 0 No interrupt request is pending for the analog to digital Converter 1 An interrupt request from the Analog to Digital Converter is awaiting service Interrupt Request 1 Register The Interrupt Request 1 IRQ1 register Table 34 stores interrupt requests for both vec tored and polled interrupts When a request is presented to the interrupt controller the cor responding bit in the IRQI register becomes 1 If interrupts are globally enabled vectored interrupts the interrupt controller passes an interrupt request to the eZ8 CPU If interrupts are globally disabled polled interrupts the eZ8 CPU can read the Interrupt Request 1 register to determine if any interrupt requests are pending Table 34 Interrupt Request 1 Register IRQ1 BITS 7 6 5 4 3 2 1 0 FIELD PA7VI PA6CI PASI PA4I PASI PAZI PA1I PAOI RESET 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W ADDR FC3H PS022820 0307 PA7VI Port A Pin 7 or LVD Interrupt Request 0 No interrupt request is pending for GPIO Port A or LVD 1 An interrupt request from GPIO Port A or LVD PA6CI Port A Pin 6 or Comparator Interrupt Request 0 No interrupt request is pending for GPIO Port A or Comparator 1 An interrupt request from GPIO Port A or Comparator PAxI Port A Pin x Interrupt Request 0 No interrupt request is pending for GPIO Port A pin x 1 An interrup
223. mode If a device has been erased or has not yet been programmed all program memory bytes contain FFH The CPU interprets this as an illegal instruction so some irregular behavior can occur before entering DEBUG mode and the register values after entering DEBUG mode differs from their specified reset values However none of these irregularities prevent programming the Flash memory Before beginning system debug it is recommended that some legal code be programmed into the 8 pin device and that a RESET occurs Breakpoints PS022820 0307 Execution Breakpoints are generated using the BRK instruction opcode 00H When the eZ8 CPU decodes a BRK instruction it signals the On Chip Debugger If Breakpoints are enabled the OCD enters DEBUG mode and idles the eZ8 CPU If Breakpoints are not enabled the OCD ignores the BRK signal and the BRK instruction operates as an NOP instruction Breakpoints in Flash Memory The BRK instruction is opcode 00H which corresponds to the fully programmed state of a byte in Flash memory To implement a Breakpoint write 00H to the required break address overwriting the current instruction To remove a Breakpoint the corresponding page of Flash memory must be erased and reprogrammed with the original data On Chip Debugger 178 Z8 Encore XP 8K and 4K Series Product Specification Z4 Zi LOG Runtime Counter The On Chip Debugger contains a 16 bit Runtime Counter It counts system clock cycles bet
224. mparator without first disabling interrupts and waiting for the comparator output to settle Doing so can result in spurious interrupts The following example describes how to safely enable the comparator Comparator 135 Z8 Encore XP 8K and 4K Series Product Specification Lis Zi LOG di ld cmp0 r0 load some new configutation nop nop wait for output to settle clr irq0 clear any spurious interrupts pending ei Comparator Control Register Definitions Comparator Control Register The Comparator Control Register CMPO configures the comparator inputs and sets the value of the internal voltage reference Table 75 Comparator Control Register CMPO0 BITS 7 6 5 4 3 2 1 0 INPSEL INNSEL REFLVL Reserved 20 28 pin FIELD REFLVL 8 pin RESET 0 0 0 1 0 1 0 0 R W R W R W R W R W R W R W R W R W ADDR F90H PS022820 0307 INPSEL Signal Select for Positive Input 0 GPIO pin used as positive comparator input 1 temperature sensor used as positive comparator input INNSEL Signal Select for Negative Input 0 internal reference disabled GPIO pin used as negative comparator input 1 internal reference enabled as negative comparator input REFLVL Internal Reference Voltage Level this reference is independent of the ADC voltage reference Note that the 8 pin devices contain two additional LSBs for increased resolution For 20 28 pin devices
225. mplifier output saturates at the positive or negative supply voltage No instability results PS022820 0307 Low Power Operational Amplifier Z8 Encore XP 8K and 4K Series Product Specification Zi LOG Comparator Operation The Z8 Encore KP 8K and 4K Series devices feature a general purpose comparator that compares two analog input signals These analog signals may be external stimulus from a pin CINP and or CINN or internally generated signals Both a programmable voltage reference and the temperature sensor output voltage are available internally The output is available as an interrupt source or can be routed to an external pin CINP Pi Temperature Sensor To COUT INPSEL p REFLVL INNSEL Comparator To Interrupt Internal Controller Reference Figure 20 Comparator Block Diagram When the positive comparator input exceeds the negative input by more than the specified hysteresis the output is a logic HIGH When the negative input exceeds the positive by more than the hysteresis the output is a logic LOW Otherwise the comparator output retains its present value See Table 137 Comparator Electrical Characteristics on page 235 for details The comparator may be powered down to reduce supply current See Power Control Reg ister 0 on page 34 for details AN Caution Because of the propagation delay of the comparator it is not recommended to enable or PS022820 0307 reconfigure the co
226. n Value is a function of the result of the operation 0 Reset to 0 Unaffected 1 Setto1 X Undefined PS022820 0307 eZ8 CPU Instruction Set Z8 Encore XP 8K and 4K Series Product Specification Z4 Zi LOG Opcode Maps A description of the opcode map data and the abbreviations are provided in Figure 30 Figure 31 and Figure 32 provide information about each of the eZ8 CPU instructions Table 125 lists Opcode Map abbreviations Opcode Lower Nibble Fetch Cycles Instruction Cycles 4 3 3 Opcode Upper Nibble A CP R2 R1 First Operand Second Operand After Assembly After Assembly Figure 30 Opcode Map Cell Description PS022820 0307 Opcode Maps Table 125 Opcode Map Abbreviations Z8 Encore XP 8K and 4K Series Product Specification Ll z Zi LOG Abbreviation Description Abbreviation Description b Bit position IRR Indirect Register Pair CC Condition code p Polarity 0 or 1 X 8 bit signed index or r 4 bit Working Register displacement DA Destination address R 8 bit register ER Extended Addressing register r1 R1 Ir1 Irr1 IR1 Destination address rr1 RR1 IRR1 ER1 IM Immediate data value r2 R2 Ir2 Irr2 IR2 Source address rr2 RR2 IRR2 ER2 Ir Indirect Working Register RA Relative IR Indirect register rr Working Register Pair Indirect Working Register Pair RR Register Pair PS022820 0307 Opcode Maps Z8 Encore XP 8K and 4K Serie
227. n Normal Operation If configured to generate an interrupt when a time out occurs the Watchdog Timer issues an interrupt request to the interrupt controller and sets the WDT status bit in the Reset Status RSTSTAT register see page 30 If interrupts are enabled the eZ8 CPU responds to the interrupt request by fetching the Watchdog Timer interrupt vector and executing code from the vector address After time out and interrupt generation the Watchdog Timer counter rolls over to its maximum value of FFFFFH and continues counting The Watch dog Timer counter is not automatically returned to its Reload Value The Reset Status RSTSTAT register must be read before clearing the WDT interrupt This read clears the WDT timeout flag and prevents further WDT interrupts from immediately occurring PS022820 0307 Watchdog Timer Z8 Encore XP 8K and 4K Series Product Specification Zi LOG WDT Interrupt in STOP Mode If configured to generate an interrupt when a time out occurs and the Z8 Encore XP 8K and 4K Series devices are in STOP mode the Watchdog Timer automatically initiates a Stop Mode Recovery and generates an interrupt request Both the WDT status bit and the STOP bit in the Reset Status RSTSTAT register are set to 1 following a WDT time out in STOP mode See chapter Reset Stop Mode Recovery and Low Voltage Detection on page 23 for more information about Stop Mode Recovery If interrupts are enabled following completion of the Stop
228. nce level or to disable the internal reference The REFSELH bit is contained in ADC Control Status Register 1 Set CEN to 1 to start the conversions 4 When the first conversion in continuous operation is complete after 5129 system clock cycles plus the 40 cycles for power up if necessary the ADC control logic performs the following operations CEN resets to 0 to indicate the first conversion is complete CEN remains 0 for all subsequent conversions in continuous operation An interrupt request is sent to the Interrupt Controller to indicate the conversion is complete 5 The ADC writes a new data result every 256 system clock cycles For each completed conversion the ADC control logic performs the following operations Writes the 13 bit two s complement result to ADCD H 7 0 ADCD_L 7 3 Sends an interrupt request to the Interrupt Controller denoting conversion complete 6 To disable continuous conversion clear the CONT bit in the ADC Control Register to 0 Interrupts The ADC is able to interrupt the CPU when a conversion has been completed When the ADC is disabled no new interrupts are asserted however an interrupt pending when the ADC is disabled is not cleared PS022820 0307 Analog to Digital Converter Z8 Encore XP 8K and 4K Series Product Specification Zi LOG Calibration and Compensation PS022820 0307 The Z8 Encore XP 8K and 4K S
229. nction with the PAO GPIO pin This pin performs as a general purpose input pin on power up but the debug logic General Purpose Input Output 39 Z8 Encore XP 8K and 4K Series Product Specification 40 Zi LOG monitors this pin during the reset sequence to determine if the unlock sequence occurs If the unlock sequence is present the debug function is unlocked and the pin no longer functions as a GPIO pin If it is not present the debug feature is disabled until unless another reset event occurs For more details see On Chip Debugger on page 173 Crystal Oscillator Override For systems using a crystal oscillator PAO and PAI are used to connect the crystal When the crystal oscillator is enabled see Oscillator Control Register Definitions on page 190 the GPIO settings are overridden and PAO and PA are disabled 5 V Tolerance All six I O pins on the 8 pin devices are 5 V tolerant unless the programmable pull ups are enabled If the pull ups are enabled and inputs higher than Vpp are applied to these parts excessive current flows through those pull up devices and can damage the chip gt Note In the 20 and 28 pin versions of this device any pin which shares functionality with an ADC crystal or comparator port is not 5 V tolerant including PA 1 0 PB 5 0 and PC 2 0 All other signal pins are 5 V tolerant and can safely handle inputs higher than Vpp except when the programmable pull ups are enabled External Clock S
230. nd reads the OCDSTAT register DBG lt 02H DBG OCDSTAT 7 0 Read Runtime Counter 03H The Runtime Counter counts system clock cycles in between Breakpoints The 16 bit Runtime Counter counts up from 0000H and stops at the maximum count of FFFFH The Runtime Counter is overwritten during the Write Memory Read Memory Write Register Read Register Read Memory CRC Step Instruction Stuff Instruction and Execute Instruction commands DBG 03H DBG RuntimeCounter 15 8 DBG RuntimeCounter 7 0 Write OCD Control Register 04H The Write OCD Control Register command writes the data that follows to the OCDCTL register When the Flash Read Protect Option Bit is enabled the DBGMODE bit OCDCTL 7 can only be set to 1 it cannot On Chip Debugger PS022820 0307 Z8 Encore XP 8K and 4K Series Product Specification Zi LOG be cleared to 0 and the only method ofreturning the device to normal operating mode is to reset the device DBG lt 04H DBG OCDCTL 7 0 Read OCD Control Register 05H The Read OCD Control Register command reads the value of the OCDCTL register DBG 05H DBG OCDCTL 7 0 Write Program Counter 06H The Write Program Counter command writes the data that follows to the eZ8 CPU s Program Counter PC If the device is not in DE BUG mode or if the Flash Read Protect Option bit is enabled the Program Counter PC values are discarded DBG lt 06H DBG lt Progr
231. nd 4K Series from ZiLOG using the following part numbers For more information on ordering please consult your local ZiLOG sales office The ZiLOG website www zilog com lists all regional offices and provides additional Z8 Encore xp product information 2 o 0 2 a c o p 5 E o E s 7 8 8 B 5 E 2 EO t RRB 5 o 2 pa 3 E z ya o t Eg z z be 2 amp 5 o D o3 297 amp 5E s G S o a E g 2 E 9250 aA Z8 Encore XP 8K and 4K Series with 8 KB Flash 10 Bit Analog to Digital Converter Standard Temperature 0 C to 70 C Z8F082APB020SC 8KB 1KB 0 6 14 2 4 1 1 1 PDIP 8 pin package Z8F082AQB020SC 8KB 1KB 0 6 14 2 4 1 1 1 QFN 8 pin package Z8F082ASB020SC 8KB 1KB 0 6 14 2 4 1 1 1 SOIC 8 pin package Z8F082ASHO20SC 8KB 1KB 0 17 20 2 7 41 1 1 SOIC 20 pin package Z8F082AHH020SC 8KB 1KB 0 17 20 2 7 1 1 1 SSOP 20 pin package Z8F082APHO20SC 8KB 1KB 0 17 20 2 7 1 1 1 PDIP 20 pin package Z8F082ASJ020SC 8KB 1KB 0 23 20 2 8 31 1 1 SOIC 28 pin package Z8F082AHJ020SC 8KB 1KB 0 23 20 2 8 1 1 1 SSOP 28 pin package Z8F082APJO20SC 8KB 1KB 0 23 20 2 8 31 1 1 PDIP 28 pin package Extended Temperature 40 C to 105 C Z8F082APBO20EC 8KB 1KB 0 6 14 2 4 1 1 1 PDIP 8 pin package Z8F082AQB020EC 8KB 1KB 0 6 14 2 4 31 1 1 QFN 8 pin package Z8F082ASB020EC 8KB 1KB 0 6 14 2 4 31 1 1 SOIC 8 pin package Z8F082ASHO20EC 8KB 1KB 0 17 20 2 7 1 1 1 SOIC 20 pin package Z8F082AHHO20EC 8
232. ndependently of the alternate function bit and always disable the drains if set to 1 0 The source current is enabled for any output mode unless overridden by the alternate function Push pull output 1 The source current for the associated pin is disabled open drain mode Port A D High Drive Enable Sub Registers The Port A D High Drive Enable sub register Table 22 1s accessed through the Port A D Control register by writing 04H to the Port A D Address register Setting the bits in the Port A D High Drive Enable sub registers to 1 configures the specified port pins for high current output drive operation The Port A D High Drive Enable sub register affects the pins directly and as a result alternate functions are also affected Table 22 Port A D High Drive Enable Sub Registers PxHDE BITS 7 6 5 4 3 2 1 0 FIELD PHDE7 PHDE6 PHDE5 PHDE4 PHDE3 PHDE2 PHDE1 PHDEO RESET 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W ADDR If 04H in Port A D Address Register accessible through the Port A D Control Register PS022820 0307 PHDE 7 0 Port High Drive Enabled 0 The Port pin is configured for standard output current drive 1 The Port pin is configured for high output current drive Port A D Stop Mode Recovery Source Enable Sub Registers The Port A D Stop Mode Recovery Source Enable sub register Table 23 is accessed through the Port A D Control register by writing 05H to the P
233. ne table as these instruction can be considered as a subset of more than one category Within these tables the source operand is identified as src the destination operand is dst and a condition code is cc Table 116 Arithmetic Instructions Mnemonic Operands Instruction ADC dst src Add with Carry ADCX dst src Add with Carry using Extended Addressing ADD dst src Add ADDX dst src Add using Extended Addressing CP dst src Compare CPC dst src Compare with Carry CPCX dst src Compare with Carry using Extended Addressing CPX dst src Compare using Extended Addressing DA dst Decimal Adjust DEC dst Decrement DECW dst Decrement Word INC dst Increment INCW dst Increment Word MULT dst Multiply SBC dst src Subtract with Carry SBCX dst src Subtract with Carry using Extended Addressing SUB dst src Subtract SUBX dst src Subtract using Extended Addressing PS022820 0307 eZ8 CPU Instruction Set Z8 Encore XP 8K and 4K Series Product Specification Zi Zi LOG Table 117 Bit Manipulation Instructions Mnemonic Operands Instruction BCLR bit dst Bit Clear BIT p bit dst Bit Set or Clear BSET bit dst Bit Set BSWAP dst Bit Swap CCF Complement Carry Flag RCF Reset Carry Flag SCF Set Carry Flag TCM dst src Test Complement Under Mask TCMX dst src Test Complement Under Mask using Extended
234. ng on the crystal or resonator used as well as on the feedback network See Table 111 for transconductance values to compute oscillator stabi lization times Crystal Oscillator Z8 Encore XP 8K and 4K Series Product Specification Z 194 Zi LOG Figure 27 illustrates a recommended configuration for connection with an external fundamental mode parallel resonant crystal operating at 20 MHz Recommended 20 MHz crystal specifications are provided in Table 110 Printed circuit board layout must add no more than 4 pF of stray capacitance to either the Xpy or Xoyr pins If oscillation does not occur reduce the values of capacitors C and C to decrease loading On Chip Oscillator XIN Crystal C1 15pF XOUT 2 15pF Figure 27 Recommended 20 MHz Crystal Oscillator Configuration Table 110 Recommended Crystal Oscillator Specifications Parameter Value Units Comments Frequency 20 MHz Resonance Parallel Mode Fundamental Series Resistance Rs 60 Q Maximum Load Capacitance CL 30 pF Maximum Shunt Capacitance Co 7 pF Maximum Drive Level 1 mW Maximum PS022820 0307 Crystal Oscillator Z8 Encore XP 8K and 4K Series Product Specification 195 Zi LOG Table 111 Transconductance Values for Low Medium and High Gain Operating Modes Transconductance mA V Crystal Frequency Use this range for Mode Range Function calcul
235. ode In COMPARATOR COUNTER mode the timer counts input transitions from the analog comparator output The TPOL bit in the Timer Control Register selects whether the count occurs on the rising edge or the falling edge of the comparator output signal In COMPAR ATOR COUNTER mode the prescaler is disabled UN Caution The frequency of the comparator output signal must not exceed one fourth the system PS022820 0307 clock frequency Further the high or low state of the comparator output signal pulse must be no less than twice the system clock period A shorter pulse may not be captured After reaching the Reload value stored in the Timer Reload High and Low Byte registers the timer generates an interrupt the count value in the Timer High and Low Byte registers is reset to 0001H and counting resumes Also if the Timer Output alternate function is enabled the Timer Output pin changes state from Low to High or from High to Low at timer Reload Timers PS022820 0307 Z8 Encore XP 8K and 4K Series Product Specification Zi LOG The steps for configuring a timer for COMPARATOR COUNTER mode and initiating the count are as follows 1 Write to the Timer Control register to Disable the timer Configure the timer for COMPARATOR COUNTER mode Select either the rising edge or falling edge of the comparator output signal for the count This also sets the initial logic level High or Low for the Timer Output alternate function How
236. oduct Specification Zi Zi LOG ADC Control Register Definitions ADC Control Register 0 The ADC Control Register 0 ADCCTLO selects the analog input channel and initiates the analog to digital conversion It also selects the voltage reference configuration Table 71 ADC Control Register 0 ADCCTLO BITS 7 6 5 4 3 2 1 0 FIELD CEN REFSELL REFOUT CONT ANAIN 3 0 RESET 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W ADDR F70H CEN Conversion Enable 0 Conversion is complete Writing a 0 produces no effect The ADC automatically clears this bit to 0 when a conversion is complete 1 Begin conversion Writing a 1 to this bit starts a conversion If a conversion is already in progress the conversion restarts This bit remains 1 until the conversion is complete REFSELL Voltage Reference Level Select Low Bit in conjunction with the High bit REFSELH in ADC Control Status Register 1 this determines the level of the internal voltage reference the following details the effects of REFSELH REFSELL note that this reference is independent of the Comparator reference 00 Internal Reference Disabled reference comes from external pin 017 Internal Reference set to 1 0 V 10 Internal Reference set to 2 0 V default 11 Reserved REFOUT Internal Reference Output Enable 0 Reference buffer is disabled Vref pin is available for GPIO or analog functions 1 The internal A
237. oduction Component layout PCB design should cover bigger option 01 Figure 45 28 Pin Plastic Dual Inline Package PDIP PS022820 0307 Packaging Z8 Encore XP 8K and 4K Series Product Specification 250 Zi LOG Figure 46 illustrates the 28 pin Small Outline Integrated Circuit package SOIC available in the Z8 Encore KP 8K and 4K Series devices C ee MILLIMETER j EI MAX AIN i 2 004 2 4 088 0 4 014 8 18 1 1 amp SC E LI 0 PERPPREPRRERE LCS SE x X 1 14 1 0 L3 bd EY HR Ht HH HH LI EET Wa i 1 CONTROLLING DIMENSIONS MM A EADS ARE COPLANAR WITHIN 004 INCH HB Seating plane E S Sr U i Figure 46 28 Pin Small Outline Integrated Circuit Package SOIC PS022820 0307 Packaging Z8 Encore XP 8K and 4K Series Product Specification Zi Zi LOG Figure 47 illustrates the 28 pin Small Shrink Outline Package SSOP available for the Z8 Encore XP 8K and 4K Series devices ae ae ae ae ae 0070 II pie meu 0 0256 TYP SEATING PLANE CONTROLLING DIMENSIONS MM LEADS ARE COPLANAR WITHIN 004 INCHES L y 0 8 La Figure 47 28 Pin Small Shrink Outline Package SSOP PS022820 0307 Packaging Z8 Encore XP 8K and 4K Series Product Specification Z Zi LOG PS022820 0307 Packaging Z8 Encore XP 8K and 4K Series Product Specification Li z Zi LOG Ordering Information Order the Z8 Encore XP 8K a
238. of the Flash with system clock freguencies ranging from 32 kHz 32768 Hz through 20 MHz The Flash Frequency High and Low Byte registers combine to form a 16 bit value FFREQ to control timing for Flash program and erase operations The 16 bit binary Flash Frequency value must contain the system clock frequency in kHz This value is calcu lated using the following equation ny System Clock Frequency Hz FFREQ 15 0 ODD UN Caution Flash programming and erasure are not supported for system clock frequencies below 32 kHz 32768 Hz or above 20 MHz The Flash Frequency High and Low Byte regis ters must be loaded with the correct value to ensure operation of the Z8 Encore XP 8K and 4K Series devices Flash Code Protection Against External Access The user code contained within the Flash memory can be protected against external access by the on chip debugger Programming the FRP Flash Option Bit prevents reading of the user code with the On Chip Debugger See chapter Flash Option Bits on page 153 and the chapter On Chip Debugger on page 173 for more information Flash Code Protection Against Accidental Program and Erasure The Z8 Encore XP 8K and 4K Series provides several levels of protection against accidental program and erasure of the Flash memory contents This protection is provided by a combination of the Flash Option bits the register locking mechanism the page select redundancy and the sector level protection contr
239. of the UART which ultimately receives the data The UART is only synchronized to the incoming data stream when a Start bit is received Infrared Encoder Decoder Control Register Definitions All Infrared Endec configuration and status information is set by the UART control registers as defined beginning on page 97 AN Caution To prevent spurious signals during IrDA data transmission set the IREN bit in the UART Control 1 register to 1 to enable the Infrared Encoder Decoder before enabling the GPIO Port alternate function for the corresponding pin PS022820 0307 Infrared Encoder Decoder Z8 Encore XP 8K and 4K Series Product Specification 121 Zi LOG Analog to Digital Converter The analog to digital converter ADC converts an analog input signal to its digital repre sentation The features of this sigma delta ADC include I bitresolution in DIFFERENTIAL mode O bitresolution in SINGLE ENDED mode Eight single ended analog input sources are multiplexed with general purpose I O ports 9th analog input obtained from temperature sensor peripheral 11 pairs of differential inputs also multiplexed with general purpose I O ports Low power operational amplifier LPO Interrupt on conversion complete Bandgap generated internal voltage reference with two selectable levels Manual in circuit calibration is possible employing user code offset calibration Factory calibrated for in circuit error com
240. og to Digital Converter Standard Temperature 0 C to 70 C Z8F012APB020SC 1KB 256B 16B 6 14 2 4 1 1 1 PDIP 8 pin package Z8F012AQB020SC 1KB 256B 16B 6 14 2 4 1 1 31 QFN 8 pin package Z8F012ASB020SC 1KB 256B 16B 6 14 2 4 1 1 1 SOIC 8 pin package Z8F012ASH020SC 1KB 256B 16B 17 20 2 7 1 1 1 SOIC 20 pin package Z8F012AHHO20SC 1KB 256B 16B 17 20 2 7 1 1 1 SSOP 20 pin package Z8F012APHO20SC 1KB 256B 16B 17 20 2 7 1 1 1 PDIP 20 pin package Z8F012ASJ020SC 1KB 256B 16B 23 20 2 8 31 1 1 SOIC 28 pin package Z8F012AHJ020SC 1KB 256B 16B 23 20 2 8 1 1 1 SSOP 28 pin package Z8F012APJ020SC 1KB 256B 16B 23 20 2 8 1 1 31 PDIP 28 pin package Extended Temperature 40 C to 105 C Z8F012APBO20EC 1KB 256B 16B 6 14 2 4 1 1 1 PDIP 8 pin package Z8F012AQBO20EC 1KB 256B 16B 6 14 2 4 1 1 1 QFN 8 pin package Z8F012ASBO20EC 1KB 256B 16B 6 14 2 4 1 1 1 SOIC 8 pin package Z8F012ASHO20EC 1KB 256B 16B 17 20 2 7 1 1 1 SOIC 20 pin package Z8F012AHHO20EC 1KB 256B 16B 17 20 2 7 1 1 1 SSOP 20 pin package Z8F012APHO20EC 1KB 256B 16B 17 20 2 7 1 1 1 PDIP 20 pin package Z8F012ASJ020EC 1KB 256B 16B 23 20 2 8 1 1 1 SOIC 28 pin package Z8F012AHJO20EC 1KB 256B 16B 23 20 2 8 31 1 1 SSOP 28 pin package Z8F012APJO20EC 1KB 256B 16B 23 20 2 8 1 1 31 PDIP 28 pin package Replace C with G for Lead Free Packaging PS022820 0307 Ordering Information Z8 Encore XP 8K and 4K Series Product Specification Zi Zi LOG
241. ol of the Flash Controller Flash Code Protection Using the Flash Option Bits The FRP and FWP Flash Option Bits combine to provide three levels of Flash Program Memory protection as listed in Table 77 See chapter Flash Option Bits on page 153 for more information PS022820 0307 Flash Memory PS022820 0307 Z8 Encore XP 8K and 4K Series Product Specification Z 146 Zi LOG Table 77 Flash Code Protection Using the Flash Option Bits FWP Flash Code Protection Description 0 Programming and erasing disabled for all of Flash Program Memory In user code programming Page Erase and Mass Erase are all disabled Mass Erase is available through the On Chip Debugger 1 Programming Page Erase and Mass Erase are enabled for all of Flash Program Memory Flash Code Protection Using the Flash Controller At Reset the Flash Controller locks to prevent accidental program or erasure of the Flash memory To program or erase the Flash memory first write the Page Select Register with the target page Unlock the Flash Controller by making two consecutive writes to the Flash Control register with the values 73H and 8CH sequentially The Page Select Register must be rewritten with the target page If the two Page Select writes do not match the con troller reverts to a locked state If the two writes match the selected page becomes active See Figure 22 on page 144 for details After unlocking a specific page you can enable eithe
242. on PS022820 0307 The on chip temperature sensor is a Proportional to Absolute Temperature PTAT topology A pair of Flash option bytes contain the calibration data The temperature sensor can be disabled by a bit in the Power Control Register 0 on page 34 to reduce power consumption The temperature sensor can be directly read by the ADC to determine the absolute value of its output The temperature sensor output is also available as an input to the comparator for threshold type measurement determination The accuracy of the sensor when used with the comparator is substantially less than when measured by the ADC If the temperature sensor is routed to the ADC the ADC must be configured in unity gain buffered mode See Input Buffer Stage on page 129 The value read back from the ADC is a signed number although it is always positive The sensor is factory trimmed through the ADC using the external 2 0V reference Unless the sensor is re trimmed for use with a different reference it is most accurate when used with the external 2 0V reference Because this sensor is an on chip sensor it is recommended that the user account for the difference between ambient and die temperature when inferring ambient temperature conditions During normal operation the die undergoes heating that causes a mismatch between the ambient temperature and that measured by the sensor For best results the Z8 Encore XP device must be placed into STOP mode for suf
243. on when a number of processors share a common UART bus In MULTI PROCESSOR mode also referred to as 9 Bit mode the multiprocessor bit MP is transmitted immediately following the 8 bits of data and immediately preceding the Stop bit s as illustrated in Figure 13 The character format is E Data Field gt Stop Bit s Is b msb 1 T A Sen BitO y Biti y Bit2 Bit3 Bit4 Bit5 y Bit6 h Bit7 y MP 1 1 i 2 Figure 13 UART Asynchronous MULTIPROCESSOR Mode Data Format PS022820 0307 In MULTIPROCESSOR 9 bit mode the Parity bit location 9th bit becomes the Multiprocessor control bit The UART Control 1 and Status 1 registers provide MULTI PROCESSOR 9 bit mode control and status information If an automatic address match ing scheme is enabled the UART Address Compare register holds the network address of the device MULTIPROCESSOR 9 bit Mode Receive Interrupts When MULTIPROCESSOR mode is enabled the UART only processes frames addressed to it The determination of whether a frame of data is addressed to the UART can be made in hardware software or some combination of the two depending on the multiprocessor Universal Asynchronous Receiver Transmitter Z8 Encore XP 8K and 4K Series Product Specification 104 Zi LOG configuration bits In general the address compare feature reduces the load on the CPU because it does not require access to the UART
244. ond after 1FH 221 Operational Description 23 33 37 55 69 91 97 117 121 134 135 139 141 153 169 173 187 193 199 OR 207 ordering information 253 ORX 207 oscillator signals 12 P p 203 packaging 20 pin PDIP 246 247 20 pin SSOP 248 251 28 pin PDIP 249 28 pin SOIC 250 PS022820 0307 Z8 Encore XP 8K and 4K Series Product Specification 268 Zi LOG 8 pin PDIP 243 8 pin SOIC 244 PDIP 250 251 part selection guide 2 PC 204 PDIP 250 251 peripheral AC and DC electrical characteristics 231 pin characteristics 13 Pin Descriptions 9 polarity 203 POP 207 pop using extended addressing 207 POPX 207 port availability device 37 port input timing GPIO 237 port output timing GPIO 238 power supply signals 13 power down automatic ADC 122 power on and voltage brown out electrical characteristics and timing 231 power on reset POR 25 program control instructions 208 program counter 204 program memory 15 PUSH 207 push using extended addressing 207 PUSHX 207 PWM mode 84 85 PxADDR register 46 PxCTL register 47 R R 203 r 203 RA register address 203 RCF 206 receive IrDA data 119 receiving UART data interrupt driven method 102 receiving UART data polled method 101 Index register 203 ADC control ADCCTL 130 132 ADC data high byte ADCDH 132 ADC data low bits ADCDL 133 flash control FCTL 149 155 156 flash high and low byte FFREQH and FREEQL 152 flash page select FPS 150 151 f
245. ontrol register except the Mass Erase or Page Erase commands UN Caution The byte at each address of the Flash memory cannot be programmed any bits written to 0 more than twice before an erase cycle occurs Doing so may result in corrupted data at the target byte Page Erase The Flash memory can be erased one page 512 bytes at a time Page Erasing the Flash memory sets all bytes in that page to the value FFH The Flash Page Select register identi fies the page to be erased Only a page residing in an unprotected sector can be erased With the Flash Controller unlocked and the active page set writing the value 95h to the Flash Control register initiates the Page Erase operation While the Flash Controller exe cutes the Page Erase operation the eZ8 CPU idles but the system clock and on chip peripherals continue to operate The eZ8 CPU resumes operation after the Page Erase operation completes If the Page Erase operation is performed using the On Chip Debug ger poll the Flash Status register to determine when the Page Erase operation 1s complete When the Page Erase is complete the Flash Controller returns to its locked state Mass Erase The Flash memory can also be Mass Erased using the Flash Controller but only by using the On Chip Debugger Mass Erasing the Flash memory sets all bytes to the value FFH With the Flash Controller unlocked and the Mass Erase successfully enabled writing the PS022820 0307 Flash Memory Z8 Encore
246. ort A D Address register Setting the bits in the Port A D Stop Mode Recovery Source Enable sub registers to 1 configures the specified Port pins as a Stop Mode Recovery source During STOP Mode any logic transition on a Port pin enabled as a Stop Mode Recovery source initiates Stop Mode Recovery General Purpose Input Output Z8 Encore XP 8K and 4K Series Product Specification Zi Zi LOG Table 23 Port A D Stop Mode Recovery Source Enable Sub Registers PXSMRE BITS 7 6 5 4 3 2 1 0 FIELD PSMRE7 PSMRE6 PSMRE5 PSMRE4 PSMRE3 PSMRE2 PSMRE1 PSMREO RESET 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W ADDR If 05H in Port A D Address Register accessible through the Port A D Control Register PSMRE 7 0 Port Stop Mode Recovery Source Enabled 0 The Port pin is not configured as a Stop Mode Recovery source Transitions on this pin during STOP mode do not initiate Stop Mode Recovery 1 The Port pin is configured as a Stop Mode Recovery source Any logic transition on this pin during STOP mode initiates Stop Mode Recovery Port A D Pull up Enable Sub Registers The Port A D Pull up Enable sub register Table 24 is accessed through the Port A D Control register by writing 06H to the Port A D Address register Setting the bits in the Port A D Pull up Enable sub registers enables a weak internal resistive pull up on the specified Port pins Table 24 Port A D Pull Up En
247. ory Maps for the Z8 Encore XP 8K and 4K Series products Table 5 Z8 Encore XP 8K and 4K Series Program Memory Maps Program Memory Address Hex Function Z8F082A and Z8F081A Products 0000 0001 Flash Option Bits 0002 0003 Reset Vector 0004 0005 WDT Interrupt Vector 0006 0007 Illegal Instruction Trap 0008 0037 Interrupt Vectors 0038 0039 Reserved 003A 003D Oscillator Fail Trap Vectors 003E 1FFF Program Memory Z8F042A and Z8F041A Products 0000 0001 Flash Option Bits 0002 0003 Reset Vector 0004 0005 WDT Interrupt Vector 0006 0007 Illegal Instruction Trap 0008 0037 Interrupt Vectors 0038 0039 Reserved 003A 003D Oscillator Fail Trap Vectors 003E OFFF Program Memory Note See Table 32 on page 56 for a list of the interrupt vectors PS022820 0307 Address Space Z8 Encore XP 8K and 4K Series Product Specification ZI Zi LOG Table 5 Z8 Encore XP 8K and 4K Series Program Memory Maps Continued Program Memory Address Hex Function Z8F022A and Z8F021A Products 0000 0001 Flash Option Bits 0002 0003 Reset Vector 0004 0005 WDT Interrupt Vector 0006 0007 Illegal Instruction Trap 0008 0037 Interrupt Vectors 0038 0039 Reserved 003A 003D Oscillator Fail Trap Vectors 003E 07FF Program Memory Z8F012A and Z8F011A Products 0000 0001 Flash Option Bits 0002 0003 Reset Vector 0004 0005 WDT
248. ounting enabled This capability has no effect on timer operation When the timer is enabled and the Timer High Byte register is read the contents of the Timer Low Byte register are placed in a holding regis ter A subsequent read from the Timer Low Byte register returns the value in the holding register This operation allows accurate reads of the full 16 bit timer count value while enabled When the timers are not enabled a read from the Timer Low Byte register returns the actual value in the counter Timer Pin Signal Operation Timer Output is a GPIO Port pin alternate function The Timer Output is toggled every time the counter is reloaded The Timer Input can be used as a selectable counting source It shares the same pin as the complementary timer output When selected by the GPIO Alternate Function Registers this pin functions as a timer input in all modes except for the DUAL PWM OUTPUT mode For this mode there is no timer input available PS022820 0307 Timers Timer Control Register Definitions Timer 0 1 Control Registers Time 0 1 Control Register 0 Z8 Encore XP 8K and 4K Series Product Specification Zi Zi LOG The Timer Control Register 0 TxCTLO and Timer Control Register 1 TxCTL 1 deter mine the timer operating mode It also includes a programmable PWM deadband delay two bits to configure timer interrupt definition and a status bit to identify if the most recent timer interrupt 1s caused by an input
249. ow Byte TxH and TxL registers Table 50 and Table 51 contain the current 16 bit timer count value When the timer is enabled a read from TxH causes the value in TxL to be stored in a temporary holding register read from TxL always returns this temporary register when the timers are enabled When the timer is disabled reads from TxL read the register directly Z8 Encore XP 8K and 4K Series Product Specification Zi Zi LOG Writing to the Timer High and Low Byte registers while the timer is enabled is not recom mended There are no temporary holding registers available for write operations so simul taneous 16 bit writes are not possible If either the Timer High or Low Byte registers are written during counting the 8 bit written value is placed in the counter High or Low Byte at the next clock edge The counter continues counting from the new value Table 50 Timer 0 1 High Byte Register TxH BITS 7 6 5 4 3 2 1 0 FIELD TH RESET 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W ADDR FOOH F08H Table 51 Timer 0 1 Low Byte Register TxL BITS 7 6 5 4 3 2 1 0 FIELD TL RESET 0 0 0 0 0 0 0 1 R W R W R W R W R W R W R W R W R W ADDR F01H FO9H TH and TL Timer High and Low Bytes These 2 bytes TH 7 0 TL 7 0 contain the current 16 bit timer count value Timer Reload High and Low Byte Registers The Timer 0 1 Reload H
250. oyr pin must be left unconnected The Z8 Encore XP 8K and 4K Series products do not contain an internal clock divider The frequency of the signal on the Kin input pin determines the frequency of the system clock Although the XIN pin can be used as an input for an external clock generator the CLKIN pin is better suited for such use See System Clock Selection on page 187 Operating Modes The Z8 Encore XP 8K and 4K Series products support four oscillator modes Minimum power for use with very low frequency crystals 32 kHz 1 MHZ Medium power for use with medium frequency crystals or ceramic resonators 0 5 MHz to 8 MHZ Maximum power for use with high frequency crystals 8 MHz to 20 MHz On chip oscillator configured for use with external RC networks 4 MHZ The oscillator mode is selected using user programmable Flash Option Bits See chapter Flash Option Bits on page 153 for information Crystal Oscillator Operation gt Note PS022820 0307 The Flash Option bit KTLDIS controls whether the crystal oscillator is enabled during reset The crystal may later be disabled after reset if a new oscillator has been selected as the system clock If the crystal is manually enabled after reset through the OSCCTL regis ter the user code must wait at least 1000 crystal oscillator cycles for the crystal to stabilize After this the crystal oscillator may be selected as the system clock The stabilization time varies dependi
251. package Z8F022AHHO20SC 2KB 512B 64B 17 20 2 7 1 1 1 SSOP 20 pin package Z8F022APH020SC 2KB 512B 64B 17 20 2 7 1 1 1 PDIP 20 pin package Z8F022ASJ020SC 2KB 512B 64B 23 20 2 8 1 1 1 SOIC 28 pin package Z8F022AHJ020SC 2KB 512B 64B 23 20 2 8 1 1 1 SSOP 28 pin package Z8F022APJ020SC 2KB 512B 64B 23 20 2 8 1 1 31 PDIP 28 pin package Extended Temperature 40 C to 105 C Z8F022APBO20EC 2KB 512B 64B 6 14 2 4 1 1 1 PDIP 8 pin package Z8F022AQBO20EC 2KB 512B 64B 6 14 2 4 1 1 1 QFN 8 pin package Z8F022ASBO20EC 2KB 512B 64B 6 14 2 4 1 1 1 SOIC 8 pin package Z8F022ASHO20EC 2KB 512B 64B 17 20 2 7 1 1 1 SOIC 20 pin package Z8F022AHHO20EC 2KB 512B 64B 17 20 2 7 1 1 1 SSOP 20 pin package Z8F022APHO20EC 2KB 512B 64B 17 20 2 7 1 1 1 PDIP 20 pin package Z8F022ASJ020EC 2KB 512B 64B 23 20 2 8 1 1 1 SOIC 28 pin package Z8F022AHJ020EC 2KB 512B 64B 23 20 2 8 1 1 1 SSOP 28 pin package Z8F022APJ020EC 2KB 512B 64B 23 20 2 8 1 1 1 PDIP 28 pin package Replace C with G for Lead Free Packaging PS022820 0307 Ordering Information Z8 Encore XP 8K and 4K Series Product Specification Ll z Zi LOG 5 eo Ea G o o 2 2 S z odo lerr t 4 2 oOo 3 MMH E Eg o zr 2 2 2eEFe es Ses Z8 Encore XP 8K and 4K Series with 2 KB Flash Standard Temperature 0 C to 70 C Z8F021APB020SC 2KB 512B 64B 6 13 2 0 1 1 0 PDIP 8 pin package Z8F021AQB020SC 2KB 512B 64B 6 13 2 0 1 1 0 QFN 8
252. pecification Zi LOG Register Map Table 7 provides the address map for the Register File of the Z8 Encore KP 8K and 4K Series devices Not all devices and package styles in the Z8 Encore XP 8K and 4K Series support the ADC or all of the GPIO Ports Consider registers for unimplemented periph erals as Reserved Table 7 Register File Address Map Address Hex Register Description Mnemonic Reset Hex Page No General Purpose RAM Z8F082A Z8F081A Devices 000 3FF General Purpose Register File RAM XX 400 EFF Reserved XX Z8F042A Z8F041A Devices 000 3FF General Purpose Register File RAM XX 400 EFF Reserved XX Z8F012A Z8F021A Devices 000 1FF General Purpose Register File RAM XX 200 EFF Reserved XX Z8F022A Z8F011A Devices 000 0FF General Purpose Register File RAM XX 100 EFF Reserved XX Timer 0 FOO Timer 0 High Byte TOH 00 87 F01 Timer 0 Low Byte TOL 01 87 F02 Timer 0 Reload High Byte TORH FF 88 F03 Timer 0 Reload Low Byte TORL FF 88 F04 Timer 0 PWM High Byte TOPWMH 00 88 F05 Timer 0 PWM Low Byte TOPWML 00 89 F06 Timer 0 Control 0 TOCTLO 00 83 F07 Timer 0 Control 1 TOCTL1 00 84 Timer 1 F08 Timer 1 High Byte T1H 00 87 F09 Timer 1 Low Byte T1L 01 87 FOA Timer 1 Reload High Byte T1RH FF 88 XX Undefined PS022820 0307 Register Map Z8 Encore XP 8K and 4K Series Product Specification Zi Zi LOG Table 7
253. pensation Architecture Figure 19 illustrates the major functional blocks of the ADC An analog multiplexer network selects the ADC input from the available analog pins ANAO through ANA7 The input stage of the ADC allows both differential gain and buffering The following input options are available Unbuffered input SINGLE ENDED and DIFFERENTIAL modes Buffered input with unity gain SINGLE ENDED and DIFFERENTIAL modes LPO output with full pin access to the feedback path PS022820 0307 Analog to Digital Converter Z8 Encore XP 8K and 4K Series Product Specification Z 122 ZiLOG Vrefsel Internal Voltage 7 Reference Generator VREF pin Analog Input VREFEKT Multiplexer ANAO ANA1 ANA2 ANA3 Ref Input j oe 13 ADC Data 7 7 ME ERE Si k i l v igma Delta ya ADC Buffer Amplifier 4 ANAIN gg Analog In SES Analog In Analog Input of Multiplexer ANAO ADC lt _ A e ANA1 IRQ BUFFMODE T fini ANA4 ANA5 ANA6 ANA Amplifier tristates when disabled Y T Low Power Operational Temp Amplifier Sensor Figure 19 Analog to Digital Converter Block Diagram Operation Data Format In both SINGLE ENDED and DIFFERENTIAL modes the effective output of the ADC is an 11 bit signed two s complement
254. r Page Program or Erase Writing the value 95H causes a Page Erase only if the active page resides in a sector that is not pro tected Any other value written to the Flash Control register locks the Flash Controller Mass Erase is not allowed in the user code but only in through the Debug Port After unlocking a specific page you can also write to any byte on that page After a byte is written the page remains unlocked allowing for subsequent writes to other bytes on the same page Further writes to the Flash Control Register cause the active page to revert to a locked state Sector Based Flash Protection The final protection mechanism is implemented on a per sector basis The Flash memories of Z8 Encore devices are divided into at most 8 sectors A sector is 1 8 of the total size of the Flash memory unless this value is smaller than the page size in which case the sec tor and page sizes are equal The Sector Protect register controls the protection state of each Flash sector This register is shared with the Page Select Register It is accessed by writing 73H followed by 5EH to the Flash controller The next write to the Flash Control Register targets the Sector Protect Register The Sector Protect Register is initialized to 0 on reset putting each sector into an unprotected state When a bit in the Sector Protect Register is written to 1 the correspond ing sector is no longer written or erased by the CPU External flash programming
255. r controls the state of the On Chip Debugger This register is used to enter or exit DEBUG mode and to enable the BRK instruction It can also reset the Z8 Encore XP 8K and 4K Series device A reset and stop function can be achieved by writing 81H to this register A reset and go function can be achieved by writing 41H to this register If the device is in DEBUG mode a run function can be implemented by writing 40H to this register Table 106 OCD Control Register OCDCTL BITS 7 6 5 4 3 2 1 0 FIELD DBGMODE BRKEN DBGACK Reserved RST RESET 0 0 0 0 0 0 0 0 R W R W R W R W R R R R R W PS022820 0307 DBGMODE Debug Mode The device enters DEBUG mode when this bit is 1 When in DEBUG mode the eZ8 CPU stops fetching new instructions Clearing this bit causes the eZ8 CPU to restart This bit is automatically set when a BRK instruction is decoded and Breakpoints are enabled If the Flash Read Protect Option Bit is enabled this bit can only be cleared by resetting the device It cannot be written to 0 0 The Z8 Encore XP 8K and 4K Series device is operating in NORMAL mode 1 The Z8 Encore XP 8K and 4K Series device is in DEBUG mode BRKEN Breakpoint Enable This bit controls the behavior of the BRK instruction opcode 00H By default Break points are disabled and the BRK instruction behaves similar to an NOP instruction If this bit is 1 when a BRK instruction is decoded th
256. re 1 first opcode map 220 FLAGS 204 flags register 204 flash controller 7 option bit address space 156 option bit configuration reset 153 program memory address 0000H 156 program memory address 0001H 157 flash memory 141 arrangement 142 byte programming 147 code protection 145 configurations 141 control register definitions 149 155 controller bypass 148 electrical characteristics and timing 232 flash control register 149 155 156 flash option bits 146 flash status register 150 flow chart 144 frequency high and low byte registers 152 mass erase 147 operation 143 operation timing 145 Index page erase 147 page select register 150 151 FPS register 150 151 FSTAT register 150 G gated mode 85 general purpose I O 37 GPIO 7 37 alternate functions 38 architecture 38 control register definitions 45 input data sample timing 236 interrupts 45 port A C pull up enable sub registers 50 51 port A H address registers 46 port A H alternate function sub registers 48 port A H control registers 47 port A H data direction sub registers 47 port A H high drive enable sub registers 49 port A H input data registers 52 port A H output control sub registers 48 port A H output data registers 52 53 port A H stop mode recovery sub registers 49 port availability by device 37 port input timing 237 port output timing 238 H H 204 HALT 206 halt mode 34 206 hexadecimal number prefix suffix 204 I2C 7 IM 203 immediate data
257. reconfigure this pin as a general purpose output During Reset the eZ8 CPU and on chip peripherals are idle however the on chip crystal oscillator and Watchdog Timer oscillator continue to run Upon Reset control registers within the Register File that have a defined Reset value are loaded with their reset values Other control registers including the Stack Pointer Register Pointer and Flags and general purpose RAM are undefined following Reset The eZ8 CPU fetches the Reset vector at Program Memory addresses 0002H and 0003H and loads that value into the Program Counter Program execution begins at the Reset vector address As the control registers are re initialized by a system reset the system clock after reset is always the IPO User software must reconfigure the oscillator control block such that the correct system clock source is enabled and selected PS022820 0307 Reset Stop Mode Recovery and Low Voltage Detection Z8 Encore XP 8K and 4K Series Product Specification Liz Zi LOG Reset Sources Table 9 lists the possible sources of a system reset Table 9 Reset Sources and Resulting Reset Type Operating Mode Reset Source Special Conditions NORMAL or HALT Power on reset Voltage Brownout Reset delay begins after supply voltage modes exceeds POR level Watchdog Timer time out None when configured for Reset RESET pin assertion All reset pulses less than three system clocks in width are ignored
258. rectives that control or assist the assembly process The source program is processed assembled by the assembler to obtain a machine language program called the object code The object code is executed by the eZ8 CPU An example segment of an assembly language program is detailed in the following example Assembly Language Source Program Example JP START Everything after the semicolon is a comment START A label called START The first instruction JP START in this example causes program execution to jump to the point within the program where the START label occurs LD R4 R7 A Load LD instruction with two operands The first operand Working Register R4 is the destination The second operand Working Register R7 is the source The contents of R7 is written into R4 LD 234H 4 01 Another Load LD instruction with two operands The first operand Extended Mode Register Address 2344 identifies the destination The second operand Immediate Data value 01H is the source The value 01H is written into the Register at address 234H PS022820 0307 eZ8 CPU Instruction Set Z8 Encore XP 8K and 4K Series Product Specification Zi Zi LOG Assembly Language Syntax For proper instruction execution eZ8 CPU assembly language syntax requires that the operands be written as destination source After assembly the object code usually has the operands in the order source destination but ord
259. reliability tie unused inputs to one of the supply voltages Vpp or Vgs Table 126 Absolute Maximum Ratings Parameter Minimum Maximum Units Notes Ambient temperature under bias 40 105 C Storage temperature 65 150 C Voltage on any pin with respect to Vss 0 3 5 5 V 1 0 3 3 9 V 2 Voltage on Vpp pin with respect to Vss 0 3 3 6 V Maximum current on input and or inactive output pin 5 5 pA Maximum output current from active output pin 25 25 mA 8 pin Packages Maximum Ratings at 0 C to 70 C Total power dissipation 220 mW Maximum current into Vpp or out of Vss 60 mA Operating temperature is specified in DC Characteristics 1 This voltage applies to all pins except the following Vpp AVpp pins supporting analog input Port B 5 0 Port C 2 0 and pins supporting the crystal oscillator PAO and PA1 On the 8 pin packages this applies to all pins but Vpp 2 This voltage applies to pins on the 20 28 pin packages supporting analog input Port B 5 0 Port C 2 0 and pins supporting the crystal oscillator PAO and PA1 PS022820 0307 Electrical Characteristics Z8 Encore XP 8K and 4K Series Table 126 Absolute Maximum Ratings Continued Product Specification Zi Zi LOG Parameter Minimum Maximum Units Notes 20 pin Packages Maximum Ratings at 0 C to 70 C Total power dissipation 430 mW Maximum current into Vpp or
260. ries devices This package has a footprint identical to that of the 8 pin SOIC but with a lower profile Dra de E PS022820 0307 A1 5 8 TOT Notch or chamfer HERD Lr Figure 41 8 Pin Quad Flat No Lead Package QFN MLF S J Ta SvMBGL MILLIMETER INCH MIN MAX MIN MAX 0 80 1 00 0 032 0 039 M 0 0 05 0 0 002 b 0 35 0 45 0 014 0 018 AD 4 95 5 05 0 195 0 199 AE 5 95 6 05 0 234 0 238 1 27 BSC 0 050 BSC L 0 50 0 70 0 020 0 028 1 CONTROLLING DIMENSIONS mm 2 MAX COPLANARITY 0 08 mm 0 003 Packaging 245 Z8 Encore XP 8K and 4K Series Product Specification Z 246 ZiLOG Figure 42 illustrates the 20 pin Plastic Dual Inline Package PDIP available for the Z8 Encore XP 8K and 4K Series devices me MILLIMETER INCH MIN MAX MIN MAX Al 038 0 81 015 032 20 11 A2 3 25 3 68 128 145 B 041 051 016 020 B1 147 157 058 062 C 020 0 30 008 012 E D 2565 26 16 1010 1 030 E 749 826 295 325 E1 610 665 240 282 r T E 2 54 BSC 100 BSC eA 787 9 14 310 360 p a L 318 343
261. ries devices or when recovering from an error A Serial Break from the host resets the Auto Baud Generator Detector but does not reset the OCD Control register A Serial Break leaves the device in DEBUG mode if that is the current mode The OCD is held in Reset until the end of the Serial Break when the DBG pin returns High Because of the open drain nature of the DBG pin the host can send a Serial Break to the OCD even if the OCD is transmitting a character On Chip Debugger Z8 Encore XP 8K and 4K Series Product Specification Zi LOG OCD Unlock Seguence 8 Pin Devices Only Because of pin sharing on the 8 pin device an unlock seguence must be performed to access the DBG pin If this sequence is not completed during a system reset then the PAO DBG pin functions only as a GPIO pin The following sequence unlocks the DBG pin 1 Hold PA2 RESET Low 2 Wait 5ms for the internal reset sequence to complete 3 Send the following bytes serially to the debug pin DBG 80H autobaud DBG lt EBH DBG 5AH DBG 70H DBG CDH 32 bit unlock key 4 Release PA2 RESET The PAO DBG pin is now identical in function to that of the DBG pin on the 20 28 pin device To enter DEBUG mode re autobaud and write 80H to the OCD control register See On Chip Debugger Commands on page 179 UN Caution Between steps 3 and 4 above there is an interval during which the 8 pin device is neither in RESET nor DEBUG
262. rogram Memory DBG lt OEH DBG CRC 15 8 DBG CRC 7 0 Step Instruction 10H The Step Instruction command steps one assembly in struction at the current Program Counter PC location If the device is not in DEBUG mode or the Flash Read Protect Option bit is enabled the OCD ignores this command DBG lt 10H Stuff Instruction 11H The Stuff Instruction command steps one assembly in struction and allows specification of the first byte of the instruction The remaining 0 4 bytes of the instruction are read from Program Memory This command is useful for stepping over instructions where the first byte of the instruction has been overwritten by a Breakpoint Ifthe device is not in DEBUG mode or the Flash Read Protect Option bit is enabled the OCD ignores this command DBG lt 11H DBG opcode 7 0 Execute Instruction 12H The Execute Instruction command allows sending an entire instruction to be executed to the eZ8 CPU This command can also step over Breakpoints The number of bytes to send for the instruction depends on the opcode If the device is not in DEBUG mode or the Flash Read Protect Option bit is enabled this command reads and discards one byte DBG lt 12H DBG lt 1 5 byte opcode PS022820 0307 On Chip Debugger Z8 Encore XP 8K and 4K Series Product Specification Z 184 Zi LOG On Chip Debugger Control Register Definitions OCD Control Register The OCD Control registe
263. rupt the interrupt was generated by a Reload 5 Enable the timer interrupt 1f appropriate and set the timer interrupt priority by writing to the relevant interrupt registers By default the timer interrupt is generated for both input capture and reload events If appropriate configure the timer interrupt to be generated only at the input capture event or the reload event by setting TICONFIG field of the TxCTLO register 6 Configure the associated GPIO port pin for the Timer Input alternate function 7 Write to the Timer Control register to enable the timer and initiate counting In CAPTURE mode the elapsed time from timer start to Capture event can be calculated using the following equation Capture Elapsed Time s Capture Value Start Value x Prescale System Clock Frequency Hz CAPTURE RESTART Mode In CAPTURE RESTART mode the current timer count value is recorded when the accept able external Timer Input transition occurs The Capture count value is written to the Timer PWM High and Low Byte Registers The timer input is the system clock The TPOL bit in the Timer Control register determines if the Capture occurs on a rising edge or a falling edge of the Timer Input signal When the Capture event occurs an interrupt is generated and the count value in the Timer High and Low Byte registers is reset to 0001H and counting resumes The INPCAP bit in TxCTLO register is set to indicate the timer interrupt is because of an input
264. rupt vectors are shared 8 on chip peripheral interrupt sources two interrupt vectors are shared Flexible GPIO interrupts Eight selectable rising and falling edge GPIO interrupts Four dual edge interrupts Three levels of individually programmable interrupt priority Watchdog Timer and LVD can be configured to generate an interrupt Supports vectored as well as polled interrupts Interrupt requests IRQs allow peripheral devices to suspend CPU operation in an orderly manner and force the CPU to start an interrupt service routine ISR Usually this interrupt service routine is involved with the exchange of data status information or control infor mation between the CPU and the interrupting peripheral When the service routine is completed the CPU returns to the operation from which it was interrupted The eZ8 CPU supports both vectored and polled interrupt handling For polled interrupts the interrupt controller has no effect on operation Refer to the eZ8 CPU User Manual for more information regarding interrupt servicing by the eZ8 CPU The eZ8 CPU User Manual is available for download at www zilog com Interrupt Vector Listing gt Note PS022820 0307 Table 32 on page 56 lists all of the interrupts available in order of priority The interrupt vector is stored with the most significant byte MSB at the even Program Memory address and the least significant byte LSB at the following odd Program Memory ad
265. s 83 Timer 0 1 High and Low Byte Registers 87 Timer Reload High and Low Byte Registers 87 Timer 0 1 PWM High and Low Byte Registers 88 Watchdog Timer anunnanunannnn 91 Operation 91 Watchdog Timer Refresh 92 Table of Contents vii PS022820 0307 Z8 Encore XP 8K and 4K Series Product Specification ZiLOG Watchdog Timer Time Out Response 92 Watchdog Timer Reload Unlock Sequence 93 Watchdog Timer Calibration 94 Watchdog Timer Control Register Definitions 94 Watchdog Timer Control Register 94 Watchdog Timer Reload Upper High and Low Byte Registers 95 Universal Asynchronous Receiver Transmitter 97 PICINCCING aa AA AA AA aN AA aa 97 Operation 98 Dale Bi aa ep AA WA AAA AE WAA eee tee 98 Transmitting Data using the Polled Method 99 Transmitting Data using the Interrupt Driven Method 100 Receiving Data using the Polled Method 101 Receiving Data using the Interrupt Driven Method
266. s Lower Nibble Hex 4 3 ADDX ER2 ER1 4 3 ADDX IM ER1 43 ADCX ER2 ER1 4 3 ADCX IM ER1 4 3 SUBX ER2 ER1 4 3 SUBX IM ER1 2 3 SBC 3 3 SBC 43 SBCX ER2 ER1 4 3 SBCX IM ER1 2 3 OR 2 4 OR r1 Ir2 3 3 OR 34 OR 4 3 ORX ER2 ER1 4 3 ORX IM ER1 2 3 AND r1 r2 24 AND r1 Ir2 3 3 AND R1 IM 3 4 AND IR1 IM 4 3 ANDX ER2 ER1 4 3 ANDX IM ER1 2 3 TCM r1 r2 24 TCM r1 Ir2 3 3 TCM R1 IM 3 4 TCM IR1 IM 43 TCMX ER2 ER1 4 3 TCMX IM ER1 2 3 TM r1 r2 24 TM r1 Ir2 3 3 TM R1 IM 3 4 TM IR1 IM 4 3 TMX ER2 ER1 4 3 TMX IM ER1 2 5 LDE r1 lrr2 2 9 LDEI Ir1 Irr2 3 3 LDX Ir1 ER2 34 LDX IRR2 R1 3 5 LDX IRR2 IR1 3 4 LDX r1 m2 X 3 4 LDX rr r2 X Upper Nibble Hex 2 5 LDE r2 lrri 2 9 LDEI Ir2 Irr1 3 3 LDX 1r2 ER1 3 4 LDX R2 IRR1 3 5 LDX IR2 IRR1 3 3 LEA r1 r2 X 3 5 LEA rr1 r2 X 2 3 CP r1 r2 24 CP r1 Ir2 34 CP IR2 R1 3 3 CP R1 IM 34 CP IR1 IM 4 3 CPX ER2 ER1 4 3 CPX IM ER1 2 3 XOR 1 12 2 4 XOR r1 Ir2 34 XOR IR2 R1 3 3 XOR R1 IM 3 4 XOR IR1 IM 43 XORX ER2 ER1 4 3 XORX IM ER1 2 5 LDC r1 Irr2 2 9 LDCI Ir1 Irr2 2 9 LDC Ir1 Irr2 3 4 LD r1 r2 X 32 PUSHX ER2 2 5 LDC r2 lrri 2 9 LDCI Ir2 Irr1 2 2 BSWAP R1 3 3 CALL DA 3 4 LD
267. sable the timer Configure the timer for COMPARE mode Set the prescale value Set the initial logic level High or Low for the Timer Output alternate function if appropriate 2 Write to the Timer High and Low Byte registers to set the starting count value 3 Wirite to the Timer Reload High and Low Byte registers to set the Compare value 4 Enable the timer interrupt if appropriate and set the timer interrupt priority by writing to the relevant interrupt registers 5 Ifusing the Timer Output function configure the associated GPIO port pin for the Timer Output alternate function 6 Write to the Timer Control register to enable the timer and initiate counting In Compare mode the system clock always provides the timer input The Compare time can be calculated by the following equation Compare Value Start Value x Prescale Mode T Compare Value Slat value 12 Erescsie wa KA Ve NS System Clock Freguency Hz GATED Mode In GATED mode the timer counts only when the Timer Input signal is in its active state asserted as determined by the TPOL bit in the Timer Control register When the Timer Input signal is asserted counting begins A timer interrupt is generated when the Timer Input signal is deasserted or a timer reload occurs To determine if a Timer Input signal deassertion generated the interrupt read the associated GPIO input value and compare to the value stored in the T POL bit The timer counts up to the
268. se bits contain the data to be driven to the port pins The values are only driven if the corresponding pin is configured as an output and the pin 1s not configured for alternate function operation 0 Drive a logical 0 Low 17 Drive a logical 1 High High value is not driven if the drain has been disabled by setting the corresponding Port Output Control register bit to 1 PS022820 0307 General Purpose Input Output Z8 Encore XP 8K and 4K Series Product Specification Zi Zi LOG LED Drive Enable Register The LED Drive Enable register Table 29 activates the controlled current drive The Port C pin must first be enabled by setting the Alternate Function register to select the LED function Table 29 LED Drive Enable LEDEN BITS 7 6 5 4 3 2 1 0 FIELD LEDEN 7 0 RESET 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W ADDR F82H LEDEN 7 0 LED Drive Enable These bits determine which Port C pins are connected to an internal current sink 0 Tristate the Port C pin 1 Enable controlled current sink on the Port C pin LED Drive Level High Register The LED Drive Level registers contain two control bits for each Port C pin Table 30 These two bits select between four programmable drive levels Each pin is individually programmable Table 30 LED Drive Level High Register LEDLVLH BITS 7 6 5 4 3 2 1 0 FIELD LEDLVLH 7 0 RESET 0 0 0 0
269. set pulse three clock cycles in duration might trigger a reset a pulse four cycles in duration always triggers a reset While the RESET input pin is asserted Low the Z8 Encore XP 8K and 4K Series devices remain in the Reset state If the RESET pin is held Low beyond the System Reset time out the device exits the Reset state on the system clock rising edge following RESET pin deassertion Following a System Reset initiated by the external RESET pin the EXT sta tus bit in the Reset Status RSTSTAT register is set to 1 External Reset Indicator During System Reset or when enabled by the GPIO logic see Port A D Control Registers on page 47 the RESET pin functions as an open drain active low reset mode indicator in addition to the input functionality This reset output feature allows a Z8 Encore XP 8K and 4K Series device to reset other components to which it is con nected even if that reset is caused by internal sources such as POR VBO or WDT events After an internal reset event occurs the internal circuitry begins driving the RESET pin Low The RESET pin is held Low by the internal circuitry until the appropriate delay listed in Table 8 has elapsed On Chip Debugger Initiated Reset A Power on reset can be initiated using the On Chip Debugger by setting the RST bit in the OCD Control register The On Chip Debugger block is not reset but the rest of the chip goes through a normal system reset The RST bit automa
270. sh Frequency High FFREQH and Low Byte FFREQL registers combine to form a 16 bit value FFREQ to control timing for Flash program and erase operations The 16 bit binary Flash Frequency value must contain the system clock frequency in kHz and is calculated using the following equation FFREQ 15 0 FFREQH 7 0 FFREQL 7 0 System Sock Erequenc UN Caution The Flash Frequency High and Low Byte registers must be loaded with the correct value to ensure proper operation of the device Also Flash programming and erasure is not supported for system clock frequencies below 20 kHz or above 20 MHz Table 82 Flash Frequency High Byte Register FFREQH BITS 7 6 5 4 3 2 1 0 FIELD FFREQH RESET 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W ADDR FFAH FFREQH Flash Frequency High Byte High byte ofthe 16 bit Flash Frequency value Table 83 Flash Frequency Low Byte Register FFREQL BITS 7 6 5 4 3 2 1 0 FIELD FFREQL RESET 0 R W R W ADDR FFBH FFREQL Flash Frequency Low Byte Low byte of the 16 bit Flash Frequency value PS022820 0307 Flash Memory Z8 Encore XP 8K and 4K Series Product Specification Zi LOG Flash Option Bits Operation Programmable Flash option bits allow user configuration of certain aspects of Z8 Encore KP 8K and 4K Series operation The feature configuration data is stored in the Flash program
271. t e Timer imer Outpu System Control Supe Clock 16 Bit Counter Timer Timer with Prescaler Output Complement nput Gate Game ad 16 Bit PWM Compare gt Capture Input ia ee e EU wa se e Ua mE 4 Figure 9 Timer Block Diagram Operation The timers are 16 bit up counters Minimum time out delay is set by loading the value 0001H into the Timer Reload High and Low Byte registers and setting the prescale value to 1 Maximum time out delay is set by loading the value 00008 into the Timer Reload High and Low Byte registers and setting the prescale value to 128 If the Timer reaches FFFFH the timer rolls over to 0000H and continues counting Timer Operating Modes PS022820 0307 The timers can be configured to operate in the following modes ONE SHOT Mode In ONE SHOT mode the timer counts up to the 16 bit Reload value stored in the Timer Reload High and Low Byte registers The timer input is the system clock Upon reaching the Reload value the timer generates an interrupt and the count value in the Timer High and Low Byte registers is reset to 0001H The timer is automatically disabled and stops counting Timers PS022820 0307 Z8 Encore XP 8K and 4K Series Product Specification 71 Zi LOG Also if the Timer Output alternate function is enabled the Timer Output pin changes state for one system clock cycle from Low to High or from High to Low upon timer Reload If it is appropriate to have the
272. t AA AA Ka UA E AS 122 Hardware Overflow 123 Automatic Powerdown 123 Single Shot Conversion 123 Continuous Conversion 124 Interrupts 125 Calibration and Compensation 126 ADC Compensation Details 127 Input Buffer Stage 129 ADC Control Register Definitions 130 ADC Control Register 0 130 ADC Control Status Register 1 132 ADC Data High Byte Register 132 ADC Data Low Byte Register 133 Low Power Operational Amplifier 134 OVEIVIOW is cou aces obe Eu Rud AAA AA PAE wi 134 Operation ane a e aa a i ia aSo a EA KAA RE E AIBA aAa EA MILI EU KUU A 134 Comparator erossa i eee wis eon ee E RU RD EORR oa a AUC R RUE NUR RR aa 135 Operatlon is m RR Ae EEEE AA aa AER 135 Comparator Control Register Definitions 136 Temperature Sensor annunnannnn 139 Temperature Sensor Operation 139 Flash Memory ia ko ko a a ee ae a RACE XU CORTO ct e QC C
273. t Timing 238 On Chip Debugger Timing 239 UART TIPOIDO 2 0 oscar ct RO Re CR ORE RR DAC RAO RR em CR RC e T eae acs 240 Packaging rre eaten f RC lr C ee le i 243 Ordering Information 253 Ndek remiamas ET 263 Customer Support snanazunsanzunznanansnwa 273 Table of Contents xii Overview Features PS022820 0307 Z8 Encore XP 8K and 4K Series Product Specification Zi LOG ZiLOG s Z8 Encore MCU family of products are the first in a line of ZILOG micro controller products based upon the 8 bit eZ8 CPU ZiLOG s Z8 Encore XP 8K and 4K Series products expand upon ZiLOG s extensive line of 8 bit microcontrollers The Flash in circuit programming capability allows for faster development time and program changes in the field The new eZ8 CPU is upward compatible with existing Z8 instruc tions The rich peripheral set of the Z8 Encore XP 8K and 4K Series makes it suitable for a variety of applications including motor control security systems home appliances per sonal electronic devices and sensors The key features of Z8 Encore XP 8K and 4K Series products include 20 MHz eZ8 CPU 1 KB 2 KB 4 KB or 8 KB Flash memory with in circuit programming capability 256 B 512 B or 1 KB register RAM Up to 128 B non volatile data storage NVDS Internal precision oscillator trimmed to 1 accuracy
274. t in the Interrupt Request register likewise clears the interrupt request Interrupt Controller Z8 Encore XP 8K and 4K Series Product Specification 59 Zi LOG The following coding style that clears bits in the Interrupt Request registers is not Caution i dud recommended All incoming interrupts received between execution of the first LDX command and the final LDX command are lost Poor coding style that can result in lost interrupt requests LDX r0 IRQO AND r0 MASK LDX IRQO r0 AA Caution To avoid missing interrupts use the following coding style to clear bits in the Interrupt Request 0 register Good coding style that avoids lost interrupt requests ANDX IRQO MASK Software Interrupt Assertion Program code can generate interrupts directly Writing a 1 to the correct bit in the Interrupt Request register triggers an interrupt assuming that interrupt is enabled When the inter rupt request is acknowledged by the eZ8 CPU the bit in the Interrupt Request register is automatically cleared to 0 AN Caution The following coding style used to generate software interrupts by setting bits in the Interrupt Request registers is not recommended All incoming interrupts received be tween execution of the first LDX command and the final LDX command are lost Poor coding style that can result in lost interrupt requests LDX r0 IRQO OR r0 MASK LDX IRQO r0 AN Caution To avoid missing interrupts use the follo
275. t request from GPIO Port A pin x is awaiting service where x indicates the specific GPIO Port pin number 0 5 Interrupt Controller Z8 Encore XP 8K and 4K Series Product Specification Zi LOG Interrupt Reguest 2 Register The Interrupt Request 2 IRQ2 register Table 35 stores interrupt requests for both vec tored and polled interrupts When a request 1s presented to the interrupt controller the cor responding bit in the IRQ2 register becomes 1 If interrupts are globally enabled vectored interrupts the interrupt controller passes an interrupt request to the eZ8 CPU If interrupts are globally disabled polled interrupts the eZ8 CPU can read the Interrupt Request 2 register to determine if any interrupt requests are pending Table 35 Interrupt Request 2 Register IRQ2 BITS 7 6 5 4 3 2 1 0 FIELD Reserved PC3l PC2l PC1I PCOI RESET 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W ADDR FC6H PS022820 0307 Reserved Must be 0 PCxI Port C Pin x Interrupt Request 0 No interrupt request is pending for GPIO Port C pin x 1 An interrupt request from GPIO Port C pin x is awaiting service where x indicates the specific GPIO Port C pin number 0 3 IRQO Enable High and Low Bit Registers Table 36 describes the priority control for IROO The IRQO Enable High and Low Bit registers Table 37 and Table 38 form a priority encoded enabling for interrupts in
276. tchdog Timer time out when configured by the WDT RES Flash Option Bit to initiate a reset External RESET pin assertion when the alternate RESET function is enabled by the GPIO register On chip debugger initiated Reset OCDCTL 0 set to 1 When the device is in STOP mode a Stop Mode Recovery is initiated by either of the following Watchdog Timer time out GPIO Port input pin transition on an enabled Stop Mode Recovery source The low voltage detection circuitry on the device available on the 8 pin product versions only performs the following functions Generates the VBO reset when the supply voltage drops below a minimum safe level Generates an interrupt when the supply voltage drops below a user defined level 8 pin devices only Reset Types The Z8 Encore XP 8K and 4K Series provides several different types of Reset operation Stop Mode Recovery is considered as a form of Reset Table 8 lists the types of Reset and their operating characteristics The System Reset is longer if the external crystal oscillator is enabled by the Flash option bits allowing additional time for oscillator start up PS022820 0307 Reset Stop Mode Recovery and Low Voltage Detection Z8 Encore XP 8K and 4K Series Product Specification Zi Zi LOG Table 8 Reset and Stop Mode Recovery Characteristics and Latency Reset Characteristics and Latency eZ8 Reset Type Control Registers CPU Reset Latency Delay System Res
277. tem reset the part enters DEBUG mode immediately 20 28 pin products only gt Note Holding the DBG pin Low for an additional 5000 minimum clock cycles after reset making sure to account for any specified frequency error if using an internal oscillator prevents a false interpretation of an Autobaud sequence see OCD Auto Baud Detector Generator on page 176 Ifthe PA2 RESET pin is held Low while a 32 bit key sequence is issued to the PAO DBG pin the DBG feature is unlocked After releasing PA2 RESET itis pulled High PS022820 0307 On Chip Debugger Z8 Encore XP 8K and 4K Series Product Specification 176 Zi LOG At this point the PAO DBG pin may be used to autobaud and cause the device to enter DEBUG mode See OCD Unlock Sequence 8 Pin Devices Only on page 178 Exiting DEBUG Mode The device exits DEBUG mode following any of these operations Clearing the DBGMODE bit in the OCD Control Register to 0 Power on reset Voltage Brownout reset Watchdog Timer reset Asserting the RESET pin Low to initiate a Reset Driving the DBG pin Low while the device is in STOP mode initiates a System Reset OCD Data Format The OCD interface uses the asynchronous data format defined for RS 232 Each character transmitted and received by the OCD consists of 1 Start bit 8 data bits least significant bit first and 1 Stop bit as displayed in Figure 26 START DO D1 D2 D3 D4 D5
278. tention 100 years 25 C Endurance 10 000 cycles Program erase cycles Table 133 Watchdog Timer Electrical Characteristics and Timing Vpp 22 7 3 6V TA 40 C to 105 C unless otherwise stated Symbol Parameter Minimum Typical Maximum Units Conditions Fwpt WDT Oscillator Frequency 10 kHz FwpT WDT Oscillator Error 50 TwprcAL WDT Calibrated Timeout 0 98 1 1 02 S Vpp 3 3 V Ta 30 C 0 70 1 1 30 S Vpp 2 7 V to 3 6 V TA 0 C to 70 C 0 50 1 1 50 S Vpp 2 7 V to 3 6 V TA 40 C to 105 C PS022820 0307 Electrical Characteristics Table 134 Non Volatile Data Storage Z8 Encore XP 8K and 4K Series Product Specification Zi LOG Vpp 2 7 3 6V TA 40 C to 105 C Parameter Minimum Typical Maximum Units Notes NVDS Byte Read Time 34 519 us With system clock at 20 MHz NVDS Byte Program Time 0 171 39 7 ms With system clock at 20 MHz Data Retention 100 years 25 C Endurance 160 000 cycles Cumulative write cycles for entire memory Table 135 Analog to Digital Converter Electrical Characteristics and Timing Vpp z3 0 3 6V Ta 0 C to 70 C unless otherwise stated Symbol Parameter Minimum Typical Maximum Units Conditions Resolution 10 bits Differential Nonlinearity 1 0 1 0 LSB E
279. the following l Checks the UART Status 0 register to determine the source of the interrupt error break or received data Reads the data from the UART Receive Data register if the interrupt was because of data available If operating in MULTIPROCESSOR 9 bit mode further actions may be required depending on the MULTIPROCESSOR mode bits MPMD 1 0 Universal Asynchronous Receiver Transmitter 102 Z8 Encore XP 8K and 4K Series Product Specification Z 0 Zi LOG 3 Clears the UART Receiver interrupt in the applicable Interrupt Request register 4 Executes the IRET instruction to return from the interrupt service routine and await more data Clear To Send CTS Operation The CTS pin if enabled by the CTSE bit of the UART Control 0 register performs flow control on the outgoing transmit datastream The Clear To Send CTS input pin is sam pled one system clock before beginning any new character transmission To delay trans mission of the next data character an external receiver must deassert CTS at least one system clock cycle before a new data transmission begins For multiple character trans missions this action is typically performed during Stop Bit transmission If CTS deasserts in the middle of a character transmission the current character is sent completely MULTIPROCESSOR 9 bit Mode Idle State of Line The UART has a MULTIPROCESSOR 9 bit mode that uses an extra 9th bit for selec tive communicati
280. the eZ8 CPU begins code execution The Option Configuration registers are not part of the Register File and are not accessible for read or write access Flash Option Bits 153 Z8 Encore XP 8K and 4K Series Product Specification Zi LOG Option Bit Types gt Note PS022820 0307 User Option Bits The user option bits are contained in the first two bytes of program memory User access to these bits has been provided because these locations contain application specific device configurations The information contained here is lost when page 0 of the program mem ory is erased Trim Option Bits The trim option bits are contained in the information page of the Flash memory These bits are factory programmed values required to optimize the operation of onboard analog cir cuitry and cannot be permanently altered by the user Program memory may be erased without endangering these values It is possible to alter working values of these bits by accessing the Trim Bit Address and Data Registers but these working values are lost after a power loss or any other reset event There are 32 bytes of trim data To modify one of these values the user code must first write a value between 00H and 1FH into the Trim Bit Address Register The next write to the Trim Bit Data register changes the working value of the target trim data byte Reading the trim data requires the user code to write a value between 00H and 1FH into the Trim Bit Address Re
281. there are two gain correction values one for positive ADC values another for negative ADC values Based on the sign of 2 use the appropriate Gain Correction Word 2 MSB 2 LSB AGain MSB AGain LSB 3 3 3 3 4 Round the result and discard the least significant two bytes this is equivalent to dividing by 2 3 3 3 3 0x00 0x00 0x80 0x00 4 MSB 4 LSB 5 Determine sign of the gain correction factor using the sign bits from step 2 If the offset corrected ADC value AND the gain correction word have the same sign then the factor is positive and is left unchanged If they have differing signs then the factor is negative and must be multiplied by 1 5 MSB 5 LSB PS022820 0307 Analog to Digital Converter Z8 Encore XP 8K and 4K Series Product Specification Z ZiLOG 6 Add the gain correction factor to the original offset corrected value 5 MSB 5 LSB 1 MSB 1 LSB 6 MSB 6 LSB 7 Shift the result to the right using the sign bit determined in step 1 above This allows for the detection of computational overflow S gt 6 MSB 6 LSB Output Data The following is the output format of the corrected ADC value MSB LSB svba9Q987 6 543210 The overflow bit in the corrected output indicates that the computed value was greater than the
282. through Flash Memory Z8 Encore XP 8K and 4K Series Product Specification 147 Zi LOG the OCD or via the Flash Controller Bypass mode are unaffected After a bit of the Sector Protect Register has been set it cannot be cleared except by powering down the device Byte Programming The Flash Memory is enabled for byte programming after unlocking the Flash Controller and successfully enabling either Mass Erase or Page Erase When the Flash Controller is unlocked and Mass Erase is successfully completed all Program Memory locations are available for byte programming In contrast when the Flash Controller is unlocked and Page Erase is successfully completed only the locations of the selected page are available for byte programming An erased Flash byte contains all 1 s FFH The programming operation can only be used to change bits from 1 to 0 To change a Flash bit or multiple bits from 0 to 1 requires execution of either the Page Erase or Mass Erase commands Byte Programming can be accomplished using the On Chip Debugger s Write Memory command or eZ8 CPU execution of the LDC or LDCI instructions Refer to the eZ8 CPU User Manual available for download at www zilog com for a description of the LDC and LDCI instructions While the Flash Controller programs the Flash memory the eZ8 CPU idles but the system clock and on chip peripherals continue to operate To exit program ming mode and lock the Flash write any value to the Flash C
283. tically clears during the system reset Following the system reset the POR bit in the Reset Status RSTSTAT register is set Stop Mode Recovery PS022820 0307 STOP mode is entered by execution of a STOP instruction by the eZ8 CPU See chapter Low Power Modes on page 33 for detailed STOP mode information During Stop Mode Recovery SMR the CPU is held in reset for 66 IPO cycles if the crystal oscillator is dis abled or 5000 cycles if it is enabled The SMR delay see Table 131 on page 231 Top also includes the time required to start up the IPO Stop Mode Recovery does not affect on chip registers other than the Watchdog Timer Control register WDTCTL and the Oscillator Control register OSCCTL After any Stop Mode Recovery the IPO is enabled and selected as the system clock If another system clock source is required the Stop Mode Recovery code must reconfigure the oscil lator control block such that the correct system clock source is enabled and selected The eZ8 CPU fetches the Reset vector at Program Memory addresses 0002H and 0003H and loads that value into the Program Counter Program execution begins at the Reset Reset Stop Mode Recovery and Low Voltage Detection 28 Z8 Encore XP 8K and 4K Series Product Specification Zi LOG vector address Following Stop Mode Recovery the STOP bit in the Reset Status RSTSTAT Register is set to 1 Table 10 lists the Stop Mode Recovery sources and result ing actions The text fol
284. tion L io ZiLOG WDFEN Watchdog Timer Oscillator Failure Detection Enable 1 Failure detection of Watchdog Timer oscillator is enabled 0 Failure detection of Watchdog Timer oscillator is disabled SCKSEL System Clock Oscillator Select 000 Internal precision oscillator functions as system clock at 5 53 MHz 001 Internal precision oscillator functions as system clock at 32 kHz 010 Crystal oscillator or external RC oscillator functions as system clock 011 Watchdog Timer oscillator functions as system 100 External clock signal on PB3 functions as system clock 101 Reserved 110 Reserved 111 Reserved Oscillator Control Z8 Encore XP 8K and 4K Series Product Specification AR ZiLOG PS022820 0307 Oscillator Control Z8 Encore XP 8K and 4K Series Product Specification Z Zi LOG Crystal Oscillator gt Note The products in the Z8 Encore KP 8K and 4K Series contain an on chip crystal oscillator for use with external crystals with 32 kHz to 20 MHz frequencies In addition the oscillator supports external RC networks with oscillation frequencies up to 4 MHz or ceramic resonators with frequencies up to 8 MHz The on chip crystal oscillator can be used to generate the primary system clock for the internal eZ8 CPU and the majority of the on chip peripherals Alternatively the Kin input pin can also accept a CMOS level clock input signal 32 kHz 20 MHZ If an external clock generator is used the X
285. tput Figure 35 GPIO Port Output Timing Table 140 GPIO Port Output Timing Delay ns Parameter Abbreviation Minimum Maximum GPIO Port pins T4 XIN Rise to Port Output Valid Delay 15 T2 XIN Rise to Port Output Hold Time 2 PS022820 0307 Electrical Characteristics Z8 Encore XP 8K and 4K Series Product Specification Z 239 ZiLOG On Chip Debugger Timing Figure 36 and Table 141 provide timing information for the DBG pin The DBG pin timing specifications assume a 4 ns maximum rise and fall time TCLK lt XIN N T T1 T2 Zo lt gt Output l j T3 T4 X gt lt gt Input Figure 36 On Chip Debugger Timing Table 141 On Chip Debugger Timing Delay ns Parameter Abbreviation Minimum Maximum DBG T4 XIN Rise to DBG Valid Delay E 15 To XIN Rise to DBG Output Hold Time 2 T3 DBG to XIN Rise Input Setup Time 5 T4 DBG to XIN Rise Input Hold Time 5 PS022820 0307 Electrical Characteristics Z8 Encore XP 8K and 4K Series Product Specification Z 240 Zi LOG UART Timing Figure 37 and Table 142 provide timing information for UART pins for the case where CTS is used for flow control The CTS to DE assertion delay T1 assumes the transmit data register has been loaded with data prior to CTS assertion CTS Input DE pi Output T1 TXD str Y pariy stop start bit
286. ture 55 interrupt assertion types 58 interrupt vectors and priority 58 operation 57 register definitions 60 software interrupt assertion 59 interrupt edge select register 66 interrupt request 0 register 60 interrupt request 1 register 61 interrupt request 2 register 62 interrupt return 208 interrupt vector listing 55 interrupts UART 105 IR 203 Ir 203 IrDA architecture 117 block diagram 117 control register definitions 120 operation 117 receiving data 119 transmitting data 118 IRET 208 IRQO enable high and low bit registers 62 IRQ1 enable high and low bit registers 63 IRQ2 enable high and low bit registers 65 IRR 203 Irr 203 J JP 208 jump conditional relative and relative condi tional 208 Index L LD 207 LDC 207 LDCI 206 207 LDE 207 LDEI 206 207 LDX 207 LEA 207 load 207 load constant 206 load constant to from program memory 207 load constant with auto increment addresses 207 load effective address 207 load external data 207 load external data to from data memory and auto increment addresses 206 load external to from data memory and auto in crement addresses 207 load using extended addressing 207 logical AND 207 logical AND extended addressing 207 logical exclusive OR 208 logical exclusive OR extended addressing 208 logical instructions 207 logical OR 207 logical OR extended addressing 207 low power modes 33 master interrupt enable 57 memory data 17 program 15 mode capture
287. uct Specification Ll ZiLOG Clock Source Internal Precision RC Oscillator Characteristics 32 8 kHz or 5 53 MHz High accuracy No external components required Required Setup Unlock and write Oscillator Control Register OSCCTL to enable and select oscillator at either 5 53 MHz or 32 8 kHz External Crystal 32 kHz to 20 MHz Configure Flash option bits for correct Resonator Very high accuracy dependent on external oscillator mode crystal or resonator used Unlock and write OSCCTL to enable Requires external components crystal oscillator wait for it to stabilize and select as system clock if the XTLDIS option bit has been de asserted no waiting is required External RC 32 kHz to 4 MHz Configure Flash option bits for correct Oscillator Accuracy dependent on external external oscillator mode components Unlock and write OSCCTL to enable crystal oscillator and select as system clock External Clock 0to 20 MHz Write GPIO registers to configure PB3 Drive e Accuracy dependent on external clock pin for external clock function source Unlock and write OSCCTL to select external system clock Apply external clock signal to GPIO Internal Watchd Timer Oscillator AN Caution PS022820 0307 10 kHz nominal Low accuracy no external components required Very low power consumption og Enable WDT if not enabled and wait until WDT Oscillator is operating
288. ued Address Hex Register Description Mnemonic Reset Hex Page No FDF Port D Output Data PDOUT 00 47 FEO FEF Reserved XX Watchdog Timer WDT FFO Reset Status Read only RSTSTAT X0 30 Watchdog Timer Control Write only WDTCTL N A 94 FF1 Watchdog Timer Reload Upper Byte WDTU 00 95 FF2 Watchdog Timer Reload High Byte WDTH 04 95 FF3 Watchdog Timer Reload Low Byte WDTL 00 96 FF4 FF5 Reserved XX Trim Bit Control FF6 Trim Bit Address TRMADR 00 155 FF7 Trim Bit Data TRMDR 00 156 Flash Memory Controller FF8 Flash Control FCTL 00 149 FF8 Flash Status FSTAT 00 150 FF9 Flash Page Select FPS 00 151 Flash Sector Protect FPROT 00 151 FFA Flash Programming Frequency High Byte FFREQH 00 152 FFB Flash Programming Frequency Low Byte FFREQL 00 152 eZ8 CPU FFC Flags XX Refer to the FFD Register Pointer RP XX eZ8 CPU User FFE Stack Pointer High Byte SPH XX Manual FFF Stack Pointer Low Byte SPL XX XX Undefined PS022820 0307 Register Map Z8 Encore XP 8K and 4K Series Product Specification ZI Zi LOG Reset Stop Mode Recovery and Low Voltage Detection The Reset Controller within the Z8 Encore KP 8K and 4K Series controls Reset and Stop Mode Recovery operation and provides indication of low supply voltage conditions In typical operation the following events cause a Reset Power on reset POR Voltage Brownout VBO Wa
289. ult If the user code changes to a differ ent oscillator it may be appropriate to disable the IPO for power savings Disabling the IPO does not occur automatically Clock Failure Detection and Recovery PS022820 0307 System Clock Oscillator Failure The Z8FO8xA Z8F04xA family devices can generate non maskable interrupt like events when the primary oscillator fails To maintain system function in this situation the clock failure recovery circuitry automatically forces the Watchdog Timer oscillator to drive the system clock The Watchdog Timer oscillator must be enabled to allow the recovery Although this oscillator runs at a much slower speed than the original system clock the CPU continues to operate allowing execution of a clock failure vector and software rou tines that either remedy the oscillator failure or issue a failure alert This automatic switch over is not available if the Watchdog Timer is selected as the system clock oscillator It is also unavailable if the Watchdog Timer oscillator is disabled though it is not necessary to enable the Watchdog Timer reset function outlined in the Watchdog Timer chapter of this document on page 91 The primary oscillator failure detection circuitry asserts if the system clock frequency drops below 1 kHz 50 If an external signal is selected as the system oscillator it is possible that a very slow but non failing clock can generate a failure condition Under these conditions do not enable t
290. us byte resides in working register RO The bit fields of this status byte are defined in Table 103 The contents of the status byte are undefined for write operations to illegal addresses Also user code must pop the address and data bytes off the stack The write routine uses 13 bytes of stack space in addition to the two bytes of address and data pushed by the user Sufficient memory must be available for this stack usage Because of the flash memory architecture NVDS writes exhibit a non uniform execution time In general a write takes 251 us assuming a 20 MHz system clock Every 400 to 500 writes however a maintenance operation is necessary In this rare occurrence the write takes up to 61ms to complete Slower system clock speeds result in proportionally higher execution times NVDS byte writes to invalid addresses those exceeding the NVDS array size have no effect Illegal write operations have a 2 us execution time Table 103 Write Status Byte BITS 7 6 5 4 3 2 1 0 FIELD Reserved RCPY PF AWE DWE DEFAULT 0 0 0 0 0 0 0 0 VALUE Reserved Must be 0 RCPY Recopy Subroutine Ezecuted A recopy subroutine was executed These operations take significantly longer than a normal write operation PF Power Failure Indicator A power failure or system reset occurred during the most recent attempted write to the NVDS array AW Address Write Error An address byte failure occurred dur
291. vices the upper 5 bits must always be 0 For the Z8F01xx devices the upper 6 bits must always be 0 Flash Sector Protect Register The Flash Sector Protect FPROT register is shared with the Flash Page Select Register When the Flash Control Register is written with 73H followed by 5EH the next write to this address targets the Flash Sector Protect Register In all other cases it targets the Flash Page Select Register This register selects one of the 8 available Flash memory sectors to be protected The reset state of each Sector Protect bit is an unprotected state After a sector is protected by setting Its corresponding register bit it cannot be unprotected the register bit cannot be cleared without powering down the device Table 81 Flash Sector Protect Register FPROT BITS 7 6 5 4 3 2 1 0 FIELD SPROT7 SPROT6 SPROT5 SPROT4 SPROT3 SPROT2 SPROT1 SPROTO RESET 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W ADDR FF9H PS022820 0307 Flash Memory Z8 Encore XP 8K and 4K Series Product Specification Zi Zi LOG SPROT7 SPROTO Sector Protection Each bit corresponds to a 512 byte Flash sector For the Z8F08xx devices the upper 3 bits must be zero For the Z8F04xx devices all bits are used For the Z8F02xx devices the upper 4 bits are unused For the Z8F01xx devices the upper 6 bits are unused Flash Frequency High and Low Byte Registers The Fla
292. voltage input or buffered output for internal reference Low Power Operational Amplifier LPO AMPINP AMPINN LPO inputs If enabled these pins drive the positive and negative amplifier inputs respectively AMPOUT O LPO output If enabled this pin is driven by the on chip LPO Oscillators XIN External Crystal Input This is the input pin to the crystal oscillator A crystal can be connected between it and the XOUT pin to form the oscillator In addition this pin is used with external RC networks or external clock drivers to provide the system clock XOUT O External Crystal Output This pin is the output of the crystal oscillator A crystal can be connected between it and the XIN pin to form the oscillator Clock Input CLKIN Clock Input Signal This pin may be used to input a TTL level signal to be used as the system clock LED Drivers LED O Direct LED drive capability All port C pins have the capability to drive an LED without any other external components These pins have programmable drive strengths set by the GPIO block On Chip Debugger DBG 1 0 Debug This signal is the control and data input and output to and from the On Chip Debugger UN Caution The DBG pin is open drain and requires a pull up resistor to ensure proper operation Reset RESET I O RESET Generates a Reset when asserted driven Low Also serves as a reset indicator the Z8 Encore XP forces this pin low when in reset This pin is open drain
293. ween Breakpoints The counter starts counting when the On Chip Debugger leaves DEBUG mode and stops counting when it enters DEBUG mode again or when it reaches the maximum count of FFFFH On Chip Debugger Commands The host communicates to the on chip debugger by sending OCD commands using the DBG interface During normal operation only a subset of the OCD commands are avail able In DEBUG mode all OCD commands become available unless the user code and control registers are protected by programming the Flash Read Protect Option bit FRP The Flash Read Protect Option bit prevents the code in memory from being read out of the Z8 Encore XP 8K and 4K Series products When this option is enabled several of the OCD commands are disabled Table 106 on page 184 1s a summary of the On chip debug ger commands Each OCD command is described in further detail in the bulleted list fol lowing this table Table 106 on page 184 also indicates those commands that operate when the device is not in DEBUG mode normal operation and those commands that are dis abled by programming the Flash Read Protect Option bit Enabled when Command NOT in DEBUG Disabled by Debug Command Byte mode Flash Read Protect Option Bit Read OCD Revision 00H Yes Reserved 01H Read OCD Status Register 02H Yes Read Runtime Counter 03H Write OCD Control Register 04H Yes Cannot clear DBGMODE bit Read OCD Control Register 05H Yes
294. when it receives data directed to other devices on the multi node network The following three MULTIPROCESSOR modes are available in hardware Interrupt on all address bytes Interrupt on matched address bytes and correctly framed data bytes Interrupt only on correctly framed data bytes These modes are selected with MPMD 1 0 in the UART Control 1 Register For all mul tiprocessor modes bit MPEN of the UART Control 1 Register must be set to 1 The first scheme is enabled by writing 01b to MPMD 1 0 In this mode all incoming address bytes cause an interrupt while data bytes never cause an interrupt The interrupt service routine must manually check the address byte that caused triggered the interrupt If it matches the UART address the software clears MPMD 0 Each new incoming byte interrupts the CPU The software is responsible for determining the end of the frame It checks for the end of frame by reading the MPRX bit of the UART Status 1 Register for each incoming byte If MPRX 1 a new frame has begun If the address of this new frame is different from the UART s address MPMD 0 must be set to 1 causing the UART inter rupts to go inactive until the next address byte If the new frame s address matches the UART s the data in the new frame is processed as well The second scheme requires the following set MPMD 1 0 to 10B and write the UART s address into the UART Address Compare Register This mode introduces additional
295. wing coding style to set bits in the Interrupt Request registers Good coding style that avoids lost interrupt requests ORX IRQ0 MASK Watchdog Timer Interrupt Assertion The watchdog timer interrupt behavior is different from interrupts generated by other sources The watchdog timer continues to assert an interrupt as long as the timeout condition continues As it operates on a different and usually slower clock domain than the rest of the device the watchdog timer continues to assert this interrupt for many system clocks until the counter rolls over PS022820 0307 Interrupt Controller Z8 Encore XP 8K and 4K Series Product Specification 60 Zi LOG To avoid re triggerings of the watchdog timer interrupt after exiting the associated interrupt service routine it is recommended that the service routine continues to read from the RSTSTAT register until the WDT bit is cleared as given in the following coding sample CLEARWDT LDX r0 RSTSTAT read reset status register to clear wdt bit BTJNZ 5 r0 CLEARWDT loop until bit is cleared Interrupt Control Register Definitions For all interrupts other than the Watchdog Timer interrupt the Primary Oscillator Fail Trap and the Watchdog Oscillator Fail Trap the interrupt control registers enable individual interrupts set interrupt priorities and indicate interrupt requests Interrupt Request 0 Register The Interrupt Request 0 IRQO register Table 33 stores
296. xternal Vrer 2 0 V DNL Rs 3 0 KO Integral Nonlinearity INL 3 0 30 LSB External Veer 2 0 V Rs 3 0 KO Offset Error with Calibration 1 LSB Absolute Accuracy with 3 LSB Calibration VREF Internal Reference Voltage 1 0 1 1 1 2 V REFSEL 01 2 0 2 2 2 4 REFSEL 10 VREF Internal Reference 1 0 Temperature variation Variation with Temperature with Vpp 3 0 VREF Internal Reference Voltage 0 5 Supply voltage variation Variation with Vpp with T4 30 C Rrerout Reference Buffer Output 850 Q When the internal Impedance reference is buffered and driven out to the VREF pin REFOUT 1 PS022820 0307 Electrical Characteristics 233 Z8 Encore XP 8K and 4K Series Product Specification Z 234 Zi LOG Table 135 Analog to Digital Converter Electrical Characteristics and Timing Continued Vpp 3 0 3 6V Ta 0 C to 70 C unless otherwise stated Symbol Parameter Minimum Typical Maximum Units Conditions Single Shot Conversion 5129 System All measurements but Time clock temperature sensor cycles 10258 Temperature sensor measurement Continuous Conversion 256 System All measurements but Time clock temperature sensor cycles 512 Temperature sensor measurement Signal Input Bandwidth 10 kHz As defined by 3 dB point Rs Analog Source Impedance 10 kQ In unbuffered mode 500 kQ In buffered modes Zin Input
297. y by writing to the relevant interrupt registers By default the timer interrupt is generated for both input capture and reload events If appropriate configure the timer interrupt to be generated only at the input capture event or the reload event by setting TICONFIG field of the TxCTLO register 6 Configure the associated GPIO port pin for the Timer Input alternate function 7 Write to the Timer Control register to enable the timer and initiate counting In CAPTURE mode the elapsed time from timer start to Capture event can be calculated using the following equation Capture Value Start Value x Prescale ture Elapsed T REGAL MCN eee Sepe Md e System Clock Frequency Hz COMPARE Mode In COMPARE mode the timer counts up to the 16 bit maximum Compare value stored in the Timer Reload High and Low Byte registers The timer input is the system clock Upon reaching the Compare value the timer generates an interrupt and counting continues the timer value is not reset to 0001H Also if the Timer Output alternate function is enabled the Timer Output pin changes state from Low to High or from High to Low upon Compare If the Timer reaches FFFFH the timer rolls over to 0000H and continue counting PS022820 0307 Timers Z8 Encore XP 8K and 4K Series Product Specification 80 Zi LOG The steps for configuring a timer for COMPARE mode and initiating the count are as fol lows 1 Write to the Timer Control register to Di
298. y setting TICONFIG field of the TxCTLO register 5 Configure the associated GPIO port pin for the Timer Input alternate function 6 Wirite to the Timer Control register to enable the timer 7 Assert the Timer Input signal to initiate the counting CAPTURE COMPARE Mode In CAPTURE COMPARE mode the timer begins counting on the first external Timer Input transition The acceptable transition rising edge or falling edge 1s set by the TPOL bit in the Timer Control Register The timer input is the system clock Every subsequent acceptable transition after the first of the Timer Input signal captures the current count value The Capture value is written to the Timer PWM High and Low Byte Registers When the Capture event occurs an interrupt is generated the count value in the Timer High and Low Byte registers is reset to 0001H and counting resumes The INPCAP bit in TXCTLO register is set to indicate the timer interrupt is caused by an input capture event If no Capture event occurs the timer counts up to the 16 bit Compare value stored in the Timer Reload High and Low Byte registers Upon reaching the Compare value the timer generates an interrupt the count value in the Timer High and Low Byte registers is reset to 0001H and counting resumes The INPCAP bit in TxCTLO register is cleared to indicate the timer interrupt is not because of an input capture event The steps for configuring a timer for CAPTURE COMPARE mode and initiating the

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