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1. Suffix Description Usage notes Ke C source file Implies c90 ac C source file Implies c90 arm tc C source file Implies c90 thumb cpp C source file Implies cpp C The compiler uses the suffixes cc and CC to identify files CXX for implicit inclusion See Implicit inclusion on page 5 15 c in the Compiler Reference Guide for more information CC acpp C source file Implies cpp arm tcpp C source file Implies cpp thumb d Dependency list d is the default output filename suffix for files output file using the md option ch CorC header cpp arm file 0 ARM object file obj in ELF format Ss ARM or Thumb For files in the input file list suffixed with s the compiler assembly invokes the assembler armasm to assemble the file language source s is the default output filename suffix for files output file using either the option S or asm Ist Error and 1st is the default output filename suffix for files output warning list file using the list option pch Precompiled pch is the default output filename suffix for files output header file using the pch option txt Text file txt is the default output filename suffix for files output using the S or asm option in combination with the interleave option ARM DUI 0205H Copyright 2002 2007 ARM Limited All rights reserved 2 11 Non Confidential Getting started with the ARM Compiler Note Instruction set switching base
2. long long int j 25902068371200 length of light day meters unsigned long long int i 94607304725808Q00ULL length of light year meters See long long on page 3 8 in the Compiler Reference Guide for more information Macros with a variable number of arguments You can declare a macro in C99 that accepts a variable number of arguments The syntax for defining such a macro is similar to that of a function For example define debug format fprintf stderr format void Variadic_Macros_ VA_ARGS__ debug a test string is printed out along with x x x n 12 14 20 Mixed declarations and code C99 enables you to mix declarations and code within compound statements just as in C For example Copyright 2002 2007 ARM Limited All rights reserved ARM DUI 0205H Non Confidential ARM DUI 0205H Introduction void foo float i i i gt 0 i 7 float j sqrt i illegal in C90 New block scopes for selection and iteration statements In a for loop the first expression may be a declaration just as in C The scope of the declaration extends to the body of the loop only For example extern int max for int n max 1 n gt Q n body of loop is equivalent to extern int max int n max 1 for n gt Q n body of loop Note Unlike in C you cannot introduce new declarations in a for test if test or switch expressio
3. result is 0x7f000000 MOV r __cpp 33554432 2 result is Oxff000000 Assembler numbers with leading zeros are still decimal For example MOV rO 0700 decimal 700 MOV rO __cpp 0700 octal 0700 decimal 448 Assembler operator precedence differs from C and C For example Copyright 2002 2007 ARM Limited All rights reserved 6 19 Non Confidential Using the Inline and Embedded Assemblers 6 2 4 6 20 MOV rO 0x23 AND Oxf 1 0x23 amp Oxf 1 gt 4 MOV rO __cpp x23 amp Oxf 1 0x23 amp Oxf 1 gt 0 Assembler strings are not null terminated DCB Hello world 12 bytes no trailing null DCB __cpp Hello world 13 bytes trailing null Note The assembler rules apply outside __cpp and the C or C rules apply inside __cpp See The __cpp keyword on page 6 21 for more information Generation of embedded assembly functions The bodies of all the __asm functions in a translation unit are assembled as if they are concatenated into a single file that is then passed to the ARM assembler The order of __asm functions in the assembly file that is passed to the assembler is guaranteed to be the same order as in the source file except for functions that are generated using a template instantiation Note This means that it is possible for control to pass from one __asm function to another by falling off the end of the first function into the next __asm function in
4. 2002 2007 ARM Limited All rights reserved 3 3 Non Confidential Compiler Features 3 4 __nop on page 4 78 in the Compiler Reference Guide __return_address on page 4 83 in the Compiler Reference Guide __semihost on page 4 85 in the Compiler Reference Guide Implementations of these intrinsics are available across all architectures Intrinsics for controlling IRQ and FIQ interrupts The following intrinsics enable you to control IRQ and FIQ interrupts e __disable_irg on page 4 72 in the Compiler Reference Guide __enable_irg on page 4 73 in the Compiler Reference Guide __disable_fiq on page 4 71 in the Compiler Reference Guide __enable_fig on page 4 73 in the Compiler Reference Guide You cannot use these intrinsics to change any other CPSR bits including the mode state and imprecise data abort setting This means that the intrinsics can be used only if the processor is already in a privileged mode because the control bits of the CPSR and SPSR cannot be changed in User mode These intrinsics are available for all processor architectures in both ARM and Thumb state If you are compiling for processors that support ARMvV6 or later a CPS instruction is generated inline for these functions for example CPSID i If you are compiling for processors that support ARMv4 or ARMv5 in ARM state the compiler inlines a sequence of MRS and MSR instructions for example MRS r CPSR ORR r0 rO 0x80 MSR
5. If an expression used as an operand creates a temporary that requires destruction then the destruction occurs after the inline assembly instruction is executed This is analogous to the C rules for destruction of temporaries A simple expression operand is one of the following e a variable value the address of a variable e the dereferencing of a pointer variable a compile time constant Any expression containing one of the following is not a simple expression operand an implicit function call such as for division or explicit function call the construction of a C temporary e an arithmetic or logical operation Register lists A register list can contain a maximum of 16 operands These operands can be virtual registers or expression register operands Copyright 2002 2007 ARM Limited All rights reserved 6 11 Non Confidential Using the Inline and Embedded Assemblers 6 1 8 The order in which virtual registers and expression operands are specified in a register list is significant The register list operands are read or written in left to right order The first operand uses the lowest address and subsequent operands use addresses formed by incrementing the previous address by four This new behavior is in contrast to the usual operation of the LDM or STM instructions where the lowest numbered physical register is always stored to the lowest memory address This difference in behavior is a consequence of th
6. To see how the compiler has processed the command line use the show_cmdline option The commands are shown normalized and the contents of any via files are expanded 2 1 3 Specifying command line options with an environment variable You can specify command line options by setting the value of the RVCT31_CCOPT environment variable The syntax is identical to the command line syntax The compiler reads the value of RVCT31_CCOPT and inserts it at the front of the command string This means that options specified in RVCT31_CCOPT can be overridden by arguments on the command line 2 1 4 Autocompleting command line options ARM DUI 0205H You can optionally request the autocompletion of command line options To do this place a dot after the characters to be autocompleted Autocompletion only applies to keyword options Arguments must be separated from the dot by an equals character or space character You cannot use autocompletion for the arguments to an option You must include sufficient characters to make the autocompleted option unique For example use diag_su 223 to specify diag_suppress 223 on the command line See Using command line options on page 2 2 for more information Copyright 2002 2007 ARM Limited All rights reserved 2 9 Non Confidential Getting started with the ARM Compiler 2 1 5 2 1 6 2 10 Reading compiler options from a file When the operating system restricts the command line lengt
7. 2 1 Non Confidential Getting started with the ARM Compiler 2 1 2 1 1 2 2 Using command line options You can control many aspects of compiler operation with command line options The ARM compiler uses the Edison Design Group EDG front end See the Edison Design Group web site at http www edg com for more information on the EDG front end The following rules apply depending on the type of option Single letter options All single letter options or single letter options with arguments are preceded by a single dash You can use a space between the option and the argument or the argument can immediately follow the option For example J directory Jdirectory Keyword options All keyword options or keyword options with arguments are preceded by a double dash An or space character is required between the option and the argument For example depend file d depend file d Compiler options that contain non leading or _ can use either of these characters For example force_new_nothrow is the same as force new nothrow To compile files with names starting with a dash use the POSIX option to specify that all subsequent arguments are treated as filenames not as command switches For example to compile a file named ifile_1 use armcc c ifile 1 Invoking the ARM compiler The command for invoking the ARM compiler is armcc help options source language search paths project temp
8. 3 int z int 3 1 Designated initializers In C90 there is no way to initialize specific members of arrays structures or unions C99 supports the initialization of specific members of an array structure or union by either name or subscript through the use of designated initializers For example typedef struct char name int rank data name foo rank 1 name bar 1 rank 2 name baz name gazonk data vars 10 0 1 2 3 Members of an aggregate that are not explicitly initialized are initialized to zero by default Hex floats C99 supports floating point numbers that can be written in hexadecimal format For example float hex_floats void In hexadecimal format the exponent is a decimal number that indicates the power of two by which the significant part is multiplied Therefore 0x1 fp3 1 9375 8 1 55e1 return x1 fp3 1 15 16 243 Flexible array members In a struct with more than one member the last member of the struct can have incomplete array type Such a member is called a flexible array member of the struct Copyright 2002 2007 ARM Limited All rights reserved ARM DUI 0205H Non Confidential ARM DUI 0205H Introduction Note When a struct has a flexible array member the entire struct itself has incomplete type Flexible array members enable you to mimic dynamic type specification in C in the sense that you
9. By default when the compiler creates a PCH file it takes the name of the primary source file and replaces the suffix with pch creates the file in the same directory as the primary source file Note Support for PCH processing is not available when you specify multiple source files in a single compilation If you request PCH processing and specify more than one primary source file the compiler issues an error message and aborts the compilation The ARM compiler can precompile header files automatically or enable you to control the precompilation For more information see Automatic PCH processing Manual PCH processing on page 2 19 Controlling the output of messages during PCH processing on page 2 20 Performance issues on page 2 20 Automatic PCH processing When you use the pch command line option automatic PCH processing is enabled This means that the compiler automatically looks for a qualifying PCH file and reads it if found Otherwise the compiler creates one for use on a subsequent compilation When the compiler creates a PCH file it takes the name of the primary source file and replaces the suffix with pch The PCH file is created in the directory of the primary source file unless you specify the pch_dir option See Ordering command line options on page 2 9 for more information The header stop point The PCH file contains a snapshot of all the code that precedes a header stop point T
10. In some circumstances the compiler might intentionally generate unaligned LDR instructions In particular the compiler can do this to load halfwords from memory even where the architecture supports dedicated halfword load instructions For example to access an unaligned short within a __packed structure the compiler might load the required halfword into the top half of a register and then shift it down to the bottom half This operation requires only one memory access whereas performing the same operation using LDRB instructions requires two memory accesses plus instructions to merge the two bytes 4 5 3 __ packed structures versus individually packed fields 4 26 When optimizing a struct that is packed the compiler tries to deduce the alignment of each field to improve access However it is not always possible for the compiler to deduce the alignment of each field in a __packed struct In contrast when individual fields in a struct are declared as __packed fast access is guaranteed to naturally aligned members within the struct Therefore when the use of a packed structure is required it is recommended that you always pack individual fields of the structure rather than the entire structure itself Copyright 2002 2007 ARM Limited All rights reserved ARM DUI 0205H Non Confidential Coding Practices Note Declaring individual non aligned fields of a struct as __packed also has the advantage of making it clearer to the
11. and other C or C expressions can be specified as register operands in an inline assembly instruction Copyright 2002 2007 ARM Limited All rights reserved ARM DUI 0205H Non Confidential ARM DUI 0205H Using the Inline and Embedded Assemblers The type of an expression used in place of an ARM integer register must be either an integral type that is char short int or long excluding long long or a pointer type No sign extension is performed on char or short types You must perform sign extension explicitly for these types The compiler might add code to evaluate these expressions and allocate them to registers When an operand is used as a destination the expression must be a modifiable lvalue if used as an operand where the register is modified For example a destination register or a base register with a base register update For an instruction containing more than one expression operand the order that expression operands are evaluated is unspecified Note No exceptions are thrown during expression evaluation An expression operand of a conditional instruction is only evaluated if the conditions for the instruction are met A C or C expression that is used as an inline assembler operand might result in the instruction being expanded into several instructions This happens if the value of the expression does not meet the constraints set out for the instruction operands in the ARM Architecture Reference Manual
12. e measure code and data sizes generate static callgraphs measure stack use reduce debug information in objects and libraries 4 2 1 Measuring code and data sizes You can measure the code and data sizes of your application using a range of options For more information see info totals on page 2 48 in the Compiler Reference Guide e info and callgraph in the section on Generating image related information on page 2 29 of the Linker Guide 4 2 2 Measuring stack use ARM DUI 0205H C and C both use the stack intensively For example the stack is used to hold the return address of functions registers that must be preserved as determined by the AAPCS local variables including local arrays structures and in C classes In general there is no way to automatically measure stack use However it is possible to manually estimate the extent of stack utilization This can be done in several ways Link with callgraph to produce a static callgraph This shows information on all functions including stack use Use your debugger to set a watchpoint on the last available location in the stack and see if the watchpoint is ever hit Use your debugger to 1 Allocate space for the stack that is much larger than you expect you need 2 Fill the stack with a known value for example zero or OxDEADDEAD 3 Run your application or a fixed portion of it Aim to use as much of the stack as poss
13. r15 from inline assembly code see Inline assembler on page 6 2 Example 6 8 shows how legacy inline assembly code might use 1r Example 6 8 Legacy inline assembly code using Ir void func int var __asm mov var Ir get the return address of func There is no guarantee that 1r contains the return address of a function if your legacy code uses it in inline assembly For example there are certain build options or optimizations that might use 1r for another purpose The compiler in RVCT v2 0 and above reports an error similar to the following if Ir sp or pc is used in this way If you have to access these registers from within a C or C source file you can use embedded assembly see Embedded assembler on page 6 17 use the following intrinsics in inline assembly __current_pc To access the pc register __current_sp To access the sp register __return_address To access the Ir register For more information see also Accessing sp r13 lr r14 and pc r15 in legacy code Instruction intrinsics on page 4 63 in the Compiler Reference Guide 6 3 1 Accessing sp r13 Ir r14 and pc r15 in legacy code The following methods enable you to access the sp 1r and pc registers correctly in your source code Method 1 Use the compiler intrinsics in inline assembly for example ARM DUI 0205H Copyright 2002 2007 ARM Limited All rights reserved 6 27 Non Confidential Using the Inl
14. 2 1 2 Source language modes eeeeeeeeeeseeeteeteaeeeaeeeseeseaeeeseeeeaeeteeeeaeeteeeeaeeeaees 1 3 1 3 Th C and G 1libraries 24 488 abet hand unit frere died Asie 1 4 1 4 Ne features of C99 vise nn nn ne AR ends 1 5 Getting started with the ARM Compiler 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 Using command line options ss 2 2 File NAMING conventions eeseeeeeeeeeseeeeeeneeeeeaeeeeeneeeeenaeeteeaeeeeneeeeseaeeeeaes 2 11 Include file stands Re aa aar A TE DES Re TELERS 2 13 Precompiled header files 2 16 Specifying the target processor or architecture eceeceeeeeseeeeteeeeeetees 2 22 Specifying the procedure call standard AAPCS ccescceeeseeeeeseeeeees 2 23 Using linker feedback eceseecceseseeeeseceeeeceeeeeeeesesenenesaeenenenenseeeeneneneeeses 2 25 Adding symbol versions cc eeeeeeeeseeeeenneeteseeeeeeeeeeaeeteneeeeeneeeeeeneereneeees 2 26 Thread local storage Aiinicssan neonne a AE ivan eieites 2 27 Copyright 2002 2007 ARM Limited All rights reserved v Non Confidential Contents vi Chapter 3 Chapter 4 Chapter 5 Chapter 6 Appendix A 2 10 Eight byte alignment features 2 0 0 eeeeeeeeeeeeneeeeeeeeeeneeeeeneeeseneeeeeneeeeee 2 28 Compiler Features 3 1 WHMIS ICS EE PR RS RAR ET Sn net are i ated aed 3 2 3 2 Pragmas ss aenea nieve ee a hie ee Ans 3 13 Coding Practices 4 1 Optimizin
15. CPSR_c r e If you are compiling for processors that support ARMv4 or ARMv5 in Thumb state the compiler calls a helper function for example BL __ARM_disable_irq For more information on these instructions see the Assembler Guide Intrinsics for inserting optimization barriers The ARM compiler can perform a range of optimizations including re ordering instructions and merging some operations In some cases such as system level programming where memory is being accessed concurrently by multiple processes it might be necessary to disable instruction re ordering and force memory to be updated Copyright 2002 2007 ARM Limited All rights reserved ARM DUI 0205H Non Confidential ARM DUI 0205H Compiler Features The following optimization barrier intrinsics do not generate code but they can result in slightly increased code size and additional memory accesses __schedule_barrier on page 4 85 in the Compiler Reference Guide __force_stores on page 4 74 in the Compiler Reference Guide __memory_changed on page 4 78 in the Compiler Reference Guide Note On some systems the memory barrier intrinsics might not be sufficient to ensure memory consistency For example the __memory_changed intrinsic forces values held in registers to be written out to memory However if the destination for the data is held in a region that can be buffered it might wait in a write buffer In this case you might also have to write
16. On completion the compiler returns a value greater than zero if an error is detected See Severity of diagnostic messages on page 5 3 for more information on how the compiler handles the different levels of diagnostic messages ARM DUI 0205H Copyright 2002 2007 ARM Limited All rights reserved 5 9 Non Confidential Diagnostic Messages 5 9 Data flow warnings 5 10 The compiler performs data flow analysis as part of its optimization process This information can be used to identify potential problems in your code for example to issue warnings about the use of uninitialized variables The data flow analysis can only warn about local variables that are held in processor registers not global variables held in memory or variables or structures that are placed on the stack Be aware that Data flow warnings are issued by default in RVCT v2 0 and earlier data flow warnings are issued only if the fa option is specified Data flow analysis is disabled at 00 even if the fa option is specified The results of this analysis vary with the level of optimization used This means that higher optimization levels might produce a number of warnings that do not appear at lower levels For example int f void int i return i produces a following warning at 02 The data flow analysis cannot reliably identify faulty code and any C3017W warnings issued by the compiler are intended only as an indication of possi
17. The standard is available from national standards bodies for example AFNOR in France ANSI in the USA Kernighan B W and Ritchie D M The C Programming Language 2nd edition 1988 Prentice Hall Englewood Cliffs NJ USA ISBN 0 13 110362 8 This is the original C bible updated to cover the essentials of ANSI C Harbison S P and Steele G L A C Reference Manual Sth edition 2002 Prentice Hall Englewood Cliffs NJ USA ISBN 0 13 089592 X This is a very thorough reference guide to C including useful information on ANSI C Plauger P The Standard C Library 1991 Prentice Hall Englewood Cliffs NJ USA ISBN 0 13 131509 9 This is a comprehensive treatment of ANSI and ISO standards for the C Library Koenig A C Traps and Pitfalls Addison Wesley 1989 Reading Mass ISBN 0 201 17928 8 This explains how to avoid the most common traps in C programming It provides informative reading at all levels of competence in C See http refspecs freestandards org for the latest information about the DWARF debug table standards and ELF specifications Copyright 2002 2007 ARM Limited All rights reserved xi Non Confidential Preface xii The following publications provide information about the ETSI basic operations They are all available from the telecommunications bureau of the International Telecommunications Union ITU at http www itu int ETSI Recommendation G 191 Software tools for speech and audio co
18. To intercept divide by zero therefore you can re implement __rt_raise This function has prototype void __rt_raise int signal int type When a divide by zero error occurs __aeabi_idiv calls __rt_raise 2 2 Therefore in your implementation of __rt_raise you must check signal 2 amp amp type 2 to determine if division by zero has occurred For more information see Integer and FP helper functions on page 2 24 in the Libraries Guide Exploiting the C library on page 2 25 in the Libraries Guide 4 38 Copyright 2002 2007 ARM Limited All rights reserved ARM DUI 0205H Non Confidential ARM DUI 0205H Coding Practices Tailoring error signaling error handling and program exit on page 2 76 in the Libraries Guide __rt_raise on page 2 79 in the Libraries Guide Identifying division by zero errors in code On entry into __aeabi_idiv the link register LR contains the address of the instruction after the call to the __aeabi_uidiv division routine in your application code To identify the offending line in your source code you can simply look up the line of C code in the debugger at the address given by LR Examining parameters To save parameters for post mortem debugging you must intercept __aeabi_idivd Use the Super and Sub mechanism to intervene in all calls to __aeabi_idivQ Super Prefix __aeabi_idiv with Super to identify the original unpatched function __aeabi_idivd Use this
19. You can link legacy objects with v6 objects for running on ARMV6 if you wish However in this case the linker switches the byte order of the legacy object code into BE8 mode The resulting image is BE8 Compiling for ARMv6 legacy endian mode BE32 To use the pre ARMV6 or legacy BE32 mode you must tie the BIGENDINIT input into the core HIGH or set the B bit bit 7 of CP15 register 1 in your initialization code Note You must link BE32 compatible code using the linker option be32 Otherwise the v6 attribute of the objects causes a BE8 image to be produced For more information see Alignment support on page 4 43 bigend on page 2 10 in the Compiler Reference Guide littleend on page 2 57 in the Compiler Reference Guide no_ unaligned_access on page 2 88 in the Compiler Reference Guide be amp in Specifying Byte Addressing mode on page 2 27 in the Linker Guide be32 in Specifying Byte Addressing mode on page 2 27 in the Linker Guide Copyright 2002 2007 ARM Limited All rights reserved 4 45 Non Confidential Coding Practices 4 46 Copyright 2002 2007 ARM Limited All rights reserved ARM DUI 0205H Non Confidential Chapter 5 Diagnostic Messages ARM DUI 0205H The ARM compiler issues messages about potential portability problems and other hazards This section describes compiler options that you can use to Turn off specific messages For example you can turn off warnings if you ar
20. accessing subarchitecture functionality of VFP coprocessors These files are located in the vfpsupport subdirectory of the Examples directory of your RVDS distribution at install_directory RVDS Examples vfpsupport When the VFP coprocessor bounces an instruction an Undefined Instruction exception is signaled to the processor and the VFP support code is entered via the Undefined Instruction vector The top level and second level interrupt handlers perform some initial processing of the signal for example ensuring that the exception is not caused by an illegal instruction The user level interrupt handler then calls the appropriate library function in the library vfpsupport 1 or vfpsupport b to emulate the VFP operation in software Note You do not need to use VFP support code when no trapping of uncommon or exceptional cases is required when the VFP coprocessor is operating in RunFast mode when the hardware coprocessor is a VFPv3 based system For more information on using the VFP support code supplied with your installation of RVCT see ARM Application Note 133 Using VFP with RVDS You can find this application note in the vfpsupport subdirectory of the Examples directory of your RVDS distribution at install_directory RVDS Examples vfpsupport Copyright 2002 2007 ARM Limited All rights reserved 4 37 Non Confidential Coding Practices 4 7 Trapping and identifying division by zero errors It is
21. application domain there is usually a range of domain specific operations that need to be performed frequently Often however these operations cannot be efficiently implemented in C or C A typical example is the saturated add of two 32 bit signed two s complement integers commonly used in DSP programming Example 3 1 shows its implementation in C Example 3 1 C implementation of saturated add operation include lt limits h gt int L_add const int a const int b int C c a b if a A b amp INT_MIN 0 if c A a amp INT_MIN c a lt Q INT MIN INT_MAX return C Copyright 2002 2007 ARM Limited All rights reserved Non Confidential ARM DUI 0205H Compiler Features Intrinsic functions provide a way of easily incorporating domain specific operations in C and C source code without resorting to complex implementations for example in embedded assembler or inline assembler An intrinsic function has the appearance of a function call in C or C but is replaced during compilation by a specific sequence of low level instructions When implemented using an intrinsic for example the saturated add function of Example 3 1 on page 3 2 has the form include lt dspfns h gt Include ETSI intrinsics int a b result result L_add a b Saturated add of a and b The use of intrinsics offers several performance benefits The low level instructions substituted for an intri
22. as extract_1 extract_h and round For example round L_v1 rounds the lower 16 bits of the 32 bit input L_v1 into the most significant 16 bits with saturation Note Beware that both the dspfns h header file and the ISO C99 header file math h both define different versions of the function round Take care to avoid this potential conflict See the header file dspfns h for a complete list of the ETSI basic operations supported in RVCT For more information see ETSI Recommendation G 191 Software tools for speech and audio coding standardization ITU T Software Tool Library 2005 User s manual included as part of ETSI Recommendation G 191 ETSI Recommendation G723 1 Dual rate speech coder for multimedia communications transmitting at 5 3 and 6 3 kbit s ETSI Recommendation G 729 Coding of speech at 8 kbit s using conjugate structure algebraic code excited linear prediction CS ACELP Copyright 2002 2007 ARM Limited All rights reserved 3 7 Non Confidential Compiler Features These documents are available from ITU T the telecommunications bureau of the ITU athttp www itu int Overflow and carry The implementation of the ETSI basic operations in dspfns h exposes the status flags Overflow and Carry These flags are available as global variables for use in your own C or C programs For example include lt dspfns h gt include ETSI intrinsics include lt stdio h gt const int BUFLEN 255 int
23. can defer the specification of the array size to runtime For example extern const int n typedef struct int len char pl str void foo void size_t str_size sizeof str equivalent to offsetoff str p str s malloc str_size sizeof char n The object s can be considered as having the declaration extern const int n struct int len char p n s __func__ predefined identifier The __func__ predefined identifier provides a means of obtaining the name of the current function For example the function void foo void printf This function is called s n __func__ prints This function is called foo Copyright 2002 2007 ARM Limited All rights reserved 1 7 Non Confidential Introduction 1 8 inline functions The C99 keyword inline hints to the compiler that invocations of a function qualified with inline are to be expanded inline For example inline int max int a int b return a gt b a b The compiler inlines a function qualified with inline only if it is reasonable to do so It is free to ignore the hint if inlining the function adversely affects performance See Inlining on page 4 19 for more information Note The semantics of inline in C99 are different to the semantics of inline in Standard C long long data type C99 supports the integral data type long long This type is exactly 64 bits wide in RVCT For example
24. code When the VFP hardware is unable to deal with a situation directly it bounces the case to VFP support code for further processing For example VFP support code might be called to process any of the following floating point operations involving NaNs floating point operations involving denormals floating point overflow floating point underflow e inexact results division by zero errors invalid operations Copyright 2002 2007 ARM Limited All rights reserved ARM DUI 0205H Non Confidential ARM DUI 0205H Coding Practices When support code is in place the VFP supports a fully IEEE 754 compliant floating point model Using VFP support For convenience an implementation of VFP support code that can be used in your system is provided with your installation of RVCT The support code comprises The libraries vfpsupport 1 and vfpsupport b for emulating VFP operations bounced by the hardware These files are located in the lib armlib subdirectory of your RVCT installation C source code and assembly language source code implementing top level second level and user level interrupt handlers These files can be found in the vfpsupport subdirectory of the Examples directory of your RVDS distribution at insta11_directory RVDS Examples vfpsupport These files may require modification in order to integrate VFP support with your operating system C source code and assembly language source code for
25. from the other state To provide linker feedback to the compiler you must link your code as a separate step and use the armlink option feedback fi lename to create a feedback file You can then use this file as an input to the compiler using the compiler option feedback fi lename Note To get the maximum benefit from linker feedback you have to do a full compile and link at least twice A single compile and link using feedback from a previous build is normally sufficient to obtain some benefit You can specify the feedback fi lename option even when no feedback file exists This enables you to use the same build or make file regardless of whether a feedback file exists for example armcc c feedback unused txt test c o test o armlink feedback unused txt test o o test axf The first time you build the application it compiles normally but the compiler warns you that it cannot read the specified feedback file because it does not exist The link command then creates the feedback file and builds the image Each subsequent compile step uses the feedback file from the previous link step to remove any unused functions that are identified For more information see feedback filename on page 2 37 in the Compiler Reference Guide The Linker Guide Copyright 2002 2007 ARM Limited All rights reserved 2 25 Non Confidential Getting started with the ARM Compiler 2 8 2 26 Adding symbol versions The comp
26. function inline unless doing so causes problems For example a recursive function is inlined into itself only once To force the compiler to attempt to inline all functions compile your code with the forceinline command line option At the highest levels of optimization 02 and 03 the compiler is able to automatically inline functions if it is sensible to do so even if the user does not explicitly give a hint See Marking functions as static on page 4 21 for more information You can control the automatic inlining of functions at the highest optimization levels using the no_ autoinline command line option In general when automatic inlining is enabled the compiler inlines anything that it is sensible to inline When automatic inlining is disabled only functions marked as __inline are candidates for inlining You can control whether inlining is performed at all using the no_ inline keyword By default inlining of functions is enabled If you disable inlining of functions using the no_inline command line option then the compiler attempts to inline only those functions that are explicitly qualified with __forceinline For more information see no_ autoinline on page 2 9 in the Compiler Reference Guide forceinline on page 2 39 in the Compiler Reference Guide no_ inline on page 2 49 in the Compiler Reference Guide e __forceinline on page 4 6 in the Compiler Reference Guide e __inline on page 4 9 in the Compile
27. greater than the number of available hardware breakpoints the debugger might not be able to set the additional breakpoints In this case the debugger reports an error For more information see no_ autoinline on page 2 9 of the Compiler Reference Guide forceinline on page 2 39 of the Compiler Reference Guide no_ inline on page 2 49 of the Compiler Reference Guide __forceinline on page 4 6 of the Compiler Reference Guide Copyright 2002 2007 ARM Limited All rights reserved ARM DUI 0205H Non Confidential Coding Practices __inline on page 4 9 of the Compiler Reference Guide ARM DUI 0205H Copyright 2002 2007 ARM Limited All rights reserved 4 23 Non Confidential Coding Practices 4 5 Aligning data It is sometimes necessary to access unaligned data in memory for example when porting legacy code from a CISC architecture where instructions are available to directly access unaligned data in memory Like other RISC architectures ARM and Thumb processors are designed to efficiently access aligned data that is words which lie on addresses that are multiples of four and halfwords which lie on addresses that are multiples of two Such data is located on its natural size boundary Care needs to be taken when accessing unaligned data in memory lest unexpected results are returned For example when a conventional pointer is used to read a word in C or C source code the ARM compiler generates assembly
28. gt f where f is a virtual function all arguments other than the this pointer are already setup assumes f does not return a struct if __mcall_is_in_vbase D f LDR r12 rp fetch vtable pointer Copyright 2002 2007 ARM Limited All rights reserved 6 25 Non Confidential Using the Inline and Embedded Assemblers ldr ADD else MOV LDR ADD endif MOV LDR r0 r12 __mcall_offsetof_vbase D f fetch the base offset r0 r0 rp r0 rp r12 rp r0 rO __mcall_this_offset D f lr pc pc r12 __vcall_offsetof_vfunc D f do this adjustment set up this pointer for D fetch vtable pointer do this adjustment prepare Ir calls rp gt f 6 2 10 Differences from previous versions of the ARM C C compilers This section describes the main areas of difference between the embedded assembler in the ARM compiler and the embedded assembler in previous versions of the ARM C and C compilers For more information on using existing assembly code for the embedded assembler see the RealView Compilation Tools Developer Guide ARMv6 instructions The embedded assembler supports all ARMv6 instructions 6 26 Copyright 2002 2007 ARM Limited All rights reserved Non Confidential ARM DUI 0205H Using the Inline and Embedded Assemblers 6 3 Legacy inline assembler that accesses sp Ir or pc The compilers in RVCT v1 2 and earlier enabled accesses to sp r13 Ir r14 and pc
29. include lt stdio h gt include lt fenv h gt int main void float a b c Trap the Invalid Operation exception and untrap all other exceptions __ieee_status FE_IEEE_MASK_ALL_EXCEPT FE_IEEE_MASK_DIVBYZERO c 0 a b c printf b c f a trap division by zero error return Q Identifying division by zero errors in code The C library helper function _fp_trapveneer is called whenever an exception occurs On entry into this function the state of the registers is unchanged from when the exception occurred Therefore to find the address of the function in your application code that contains the arithmetic operation which resulted in the exception simply place a breakpoint on the function _fp_trapveneer and look at LR For example suppose the C code of Example 4 5 is compiled from the command line using the string armcc fpmode ieee_full Copyright 2002 2007 ARM Limited All rights reserved ARM DUI 0205H Non Confidential ARM DUI 0205H Coding Practices When the assembly language code produced by the compiler is disassembled Real View Debugger produces the output shown in Example 4 6 main 00008080 E92D4010 00008084 E3A01C02 00008088 E3A00C9F 0000808C EBQQQF1A 00008090 E59F0020 00008094 E3A01000 00008098 EBQQQDEA 0000809C EBQQQDBD 000080A0 E1A02000 000080A4 E1A03001 000080A8 E28F000C 000080AC EB000006 000080B0 E3A00000 000080B4 E8BD8010 000080B8 40A00000 000080BC 202F2062 000080C0 2
30. language code that reads the word using an LDR instruction This works as expected when the address is a multiple of four for example if it lies on a word boundary However if the address is not a multiple of four then the LDR returns a rotated result rather than performing a true unaligned word load Generally this rotation is not what the programmer expects 4 5 1 About data alignment All accesses to data in memory can be classified into the following categories Natural alignment for example on a word boundary at 0x1000 The ARM compiler normally aligns variables and pads structures so that these items are accessed efficiently using LDR and STR instructions Known but non natural alignment for example a word at address 0x1001 This type of alignment commonly occurs when structures are packed to remove unnecessary padding In C and C the __packed qualifier is used to signify that a structure is packed Unknown alignment for example a word at an arbitrary address This type of alignment commonly occurs when defining a pointer that can point to a word at any address In C and C the __packed qualifier is used to signify that a pointer that can access a word on a non natural alignment boundary See The __packed qualifier and unaligned accesses to data for more information about the __packed qualifier packed structures and unaligned pointers 4 5 2 The __packed qualifier and unaligned accesses to data The __packed quali
31. of the link time is consumed by reading in all the debug sections and eliminating the duplicates Minimizes the size of the final image This facilitates the fast loading and processing of debug symbols by a debugger There are several ways in which you can reduce the amount of debug information being generated per source file For example you can Avoid conditional use of define in header files The linker is unable to remove common debug sections unless these sections are identical Modify your C or C source files so that header files are included in the same order Partition header information into smaller blocks That is use a larger number of smaller header files rather than a smaller number of larger header files This helps the linker to eliminate more of the common blocks Only include a header file in a C or C source file if it is really needed Copyright 2002 2007 ARM Limited All rights reserved ARM DUI 0205H Non Confidential ARM DUI 0205H Coding Practices Guard against the multiple inclusion of header files For example if you have a header file foo h then add ifndef foo_h define foo_h rest of header file as before endif foo_h You can use the compiler option remarks to warn about unguarded header files Compile your code with the no_debug_macros command line option to discard preprocessor macro definitions from debug tables For more information see no_ debug
32. on page 2 68 Otime on page 2 69 2 6 Copyright 2002 2007 ARM Limited All rights reserved ARM DUI 0205H Non Confidential ARM DUI 0205H diagnostic options Getting started with the ARM Compiler Note Optimization criteria can limit the debug information generated by the compiler Controls the diagnostic messages output by the compiler no_ brief_diagnostics on page 2 10 diag_error tag tag on page 2 26 diag_remark tag tag on page 2 27 e diag_style armlidelgnu on page 2 27 diag_suppress tag tag on page 2 28 diag_suppress optimizations on page 2 29 diag_warning tag tag on page 2 30 diag_warning optimizations on page 2 31 e errors filename on page 2 34 remarks on page 2 78 W on page 2 94 no_ wrap_diagnostics on page 2 96 See Chapter 5 Diagnostic Messages for more information multiple compilations PCS options pass thru options Specifies the feedback file that contains information about a previous build feedback filename on page 2 37 Specifies the procedure call standard to use apcs qualifer qualifier on page 2 4 See Specifying the procedure call standard AAPCS on page 2 23 for more information Instructs the compiler to pass options to other RVCT tools Aopt on page 2 2 e Lopt on page 2 52 source Provides the filenames of one or more text files containing C or C source code By def
33. performed by the compiler depend both on the level of optimization chosen and whether you are optimizing for performance or code size The compiler supports the following optimization levels 00 Minimum optimization The compiler performs simple optimizations that do not impair the debug view Copyright 2002 2007 ARM Limited All rights reserved ARM DUI 0205H Non Confidential Coding Practices When debugging is enabled this option gives the best possible debug view 01 Restricted optimization When debugging is enabled this option gives a generally satisfactory debug view with good code density 02 High optimization This is the default optimization level When debugging is enabled this option might give a less satisfactory debug view 03 Maximum optimization This is the most aggressive form of optimization available It is weighted towards your choice of Ospace or Otime Specifying this option enables multifile compilation by default where multiple files are specified on the command line When debugging is enabled this option typically gives a poor debug view Because optimization affects the mapping of object code to source code the choice of optimization level and Ospace Otime generally impacts the debug view When debugging is enabled using debug explicitly specify the most appropriate optimization level using the Onum command line option The option 00 is the best option to use if a simple debug vie
34. processor or architecture imply the selection of a particular floating point unit For example the option cpu ARM1136JF S implies the option fpu vfpv2 Any FPU explicitly selected using the fpu option always overrides any FPU implicitly selected using the cpu option For example the option cpu ARM1136JF S fpu softvfp generates code that uses the software floating point library fplib even though the choice of CPU implies the use of architecture VFPv2 If you specify an FPU implicitly using the cpu option that is incompatible with an FPU chosen explicitly using fpu then the compiler generates an error 4 32 Copyright 2002 2007 ARM Limited All rights reserved ARM DUI 0205H Non Confidential Coding Practices Note The compiler only generates scalar floating point operations If you want to use VFP vector operations then you must do this using assembly code For more information about which compiler option to use in a particular set of circumstances see Using the fpu option on page 4 34 fpu name on page 2 42 in the Compiler Reference Guide 4 6 4 Floating point linkage ARM DUI 0205H The fpu option sets the type of floating point linkage In particular each of the options fpu softvfp fpu softvfp vfpv2 and fpu softvfp vfpv3 selects software floating point linkage When software floating point linkage is used either the calling function and the called function must be compiled
35. the arm or thumb option For more information see E NEON technology Selecting the target CPU on page 4 3 arm on page 2 7 in the Compiler Reference Guide cpu list on page 2 15 in the Compiler Reference Guide cpu name on page 2 15 in the Compiler Reference Guide fpu list on page 2 41 in the Compiler Reference Guide fpu name on page 2 42 in the Compiler Reference Guide thumb on page 2 86 in the Compiler Reference Guide Chapter 4 Interworking ARM and Thumb in the Developer Guide NEON technology The ARM Advanced Single Instruction Multiple Data SIMD Extension also known as NEON technology is a 64 128 bit hybrid SIMD architecture developed by ARM to accelerate the performance of multimedia and signal processing applications NEON is implemented as part of the processor but has its own execution pipelines and a register bank that is distinct from the ARM register bank Key features include aligned and unaligned data access support for integer fixed point and single precision floating point data types tight coupling to the ARM core and a large register file with multiple views NEON instructions are available in both ARM and Thumb 2 The ARM compiler provides support for Cortex processors equipped with a NEON unit To generate NEON instructions you must specify a Cortex processor that includes NEON technology on the command line for example cpu Cortex A8 There is no NEON support for arch
36. the file if the return instruction is omitted When you invoke armcc the object file produced by the assembler is combined with the object file of the compiler by a partial link that produces a single object file The compiler generates an AREA directive for each __asm function as in Example 6 2 Example 6 2 __asm function include lt cstddef gt struct X int x y void addto_y int __asm void X addto_y int LDR r2 r __cpp offsetof X y ADD r1 r2 r1 Copyright 2002 2007 ARM Limited All rights reserved ARM DUI 0205H Non Confidential Using the Inline and Embedded Assemblers STR ri r __cpp offsetof X y BX Ir For this function the compiler generates AREA emb_text CODE READONLY EXPORT _ZN1X7addto_yEi line num file _ZN1X7addto_yEi PROC LDR r2 r0 4 ADD r1 r2 rl STR r1 r0 4 BX Ir ENDP END The use of of fsetof must be inside the __cpp because it is the normal offsetof macro from the cstddef header file Ordinary __asm functions are put in an ELF section with the name emb_text That is embedded assembly functions are never inlined However implicitly instantiated template functions and out of line copies of inline functions are placed in an area with a name that is derived from the name of the function and an extra attribute that marks them as common This ensures that the special semantics of these kinds of functions is maintained No
37. the search rule originally described by Kernighan and Ritchie in The C Programming Language Under this rule each nonrooted user include is searched for relative to the directory containing the source file that is being compiled See kandr_include on page 2 52 in the Compiler Reference Guide for more information Copyright 2002 2007 ARM Limited All rights reserved 2 13 Non Confidential Getting started with the ARM Compiler 2 3 2 The RVCT31INC environment variable The RVCT31INC environment variable points to the location of the included header and source files provided with RVCT Do not change this environment variable If you want to include files from other locations use the I and J command line options as required When compiling directories specified with RVCT31INC are searched immediately after directories specified by the I option have been searched If you use the J option RVCT31INC is ignored 2 3 3 The search path Table 2 2 shows how the command line options affect the search path used by the compiler when it searches for included header and source files Table 2 2 Include file search paths lt include gt search Compiler option rder include search order Neither I nor J RVCT31INCdirs CP RVCT31INCdirs I RVCT31INCdirs Idirs CP Idirs RVCT31INCdirs J Jdirs CP and Jdirs Both I and J Jdirs Idirs CP Idirs Jdirs sys_include No effect Removes CP from the search pa
38. to call the original function directly Sub Prefix __aeabi_idiv with Sub to identify the new function to be called in place of the original version of __aeabi_idiv Use this to add processing before or after the original function __aeabi_idiva Example 4 4 illustrates the use of the Super and Sub mechanism to intercept __aeabi_div See Using Super and Sub to override symbol definitions on page 4 21 in the Linker Guide for more information on using Super and Sub Example 4 4 Intercepting __aeabi_div0 using Super and Sub extern void Super __aeabi_idiv void this function is called instead of the original __aeabi_idiv void Sub __aeabi_idivQ insert code to process a divide by zero call the original __aeabi_idiv function Super __aeabi_idivQ Copyright 2002 2007 ARM Limited All rights reserved 4 39 Non Confidential Coding Practices 4 7 2 Software Floating point division 4 40 Floating point division by zero errors in software can be trapped and identified using a combination of intrinsics and C library helper functions Trapping division by zero errors in code To trap floating point division by zero errors in your code use the intrinsic __ieee_status FE_IEEE_MASK_ALL_EXCEPT FE_IEEE_MASK_DIVBYZERO This traps any division by zero errors in code and untraps all other exceptions as illustrated in Example 4 5 Example 4 5 Division by zero error
39. using one of the options softvfp fpu softvfp vfpv2 or fpu softvfp vfpv3 the calling function and the called function must be declared using the __softfp keyword Each of the options fpu softvfp fpu softvfp vfpv2 and fpu softvfp vfpv3 specify software floating point linkage across the whole file In contrast the __softfp keyword enables software floating point linkage to be specified on a function by function basis For more information see fpu name on page 2 42 in the Compiler Reference Guide e __softfp on page 4 15 in the Compiler Reference Guide pragma no_ softfp_linkage on page 4 59 in the Compiler Reference Guide Copyright 2002 2007 ARM Limited All rights reserved 4 33 Non Confidential Coding Practices 4 6 5 The fpmode option You can specify the floating point conformance and floating point optimization using the fpmode option Different libraries are selected depending on the model chosen Table 4 12 Floating point models supported in RVCT Option Description fpmode ieee_ful1 All facilities operations and representations guaranteed by the IEEE standard are available in single and double precision Modes of operation can be selected dynamically at run time fpmode ieee_fixed IEEE standard with round to nearest and no inexact exceptions fpmode ieee_no_fenv IEEE standard with round to nearest and no exceptions This mode is compatible with the Java floating point
40. value of x imaxdiv_t imaxdiv intmax_t x intmax_t y returns the quotient and remainder of x y Floating point environment access in lt fenv h gt The C99 standard header file lt fenv h gt provides access to an IEEE 754 compliant floating point environment for numerical programming The library introduces two types and numerous macros and functions for managing and controlling floating point state The new types supported are fenv_t representing the entire floating point environment fexcept_t representing the floating point state New macros supported include FE_DIVBYZERO FE_INEXACT FE_INVALID FE_OVERFLOW and FE_UNDERFLOW for managing floating point exceptions FE_DOWNWARD FE_TONEAREST FE_TOWARDZERO FE_UPWARD for managing rounding in the represented rounding direction FE_DFL_ENV representing the default floating point environment New functions include int feclearexcept int ex clear floating point exceptions selected by ex int feraiseexcept int ex raise floating point exceptions selected by ex int fetestexcept int ex test floating point exceptions selected by x int fegetround void return the current rounding mode Copyright 2002 2007 ARM Limited All rights reserved ARM DUI 0205H Non Confidential ARM DUI 0205H Introduction int fesetround int mode set the current rounding mode given by mode int fegetenv fenv_t penv return the floating point environment in pe
41. 03D2063 000080C4 202C6625 000080C8 00000000 PUSH OV OV BL LDR OV BL BL OV OV ADR BL OV POP lt Data gt lt Data gt lt Data gt lt Data gt lt Data gt r4 1r r1 0x200 r0 0x9F00 __ieee_status r0 0x80b8 r1 0 _fdiv _f2d r2 rQ r3 r1 rO pc 0x14 0x80bc __Oprintf rQ 0 r4 pc 0x00 0x00 OxAQ Q LD Li Li E Li 1 ves Li Li LE Li 1 ro IF PA Li 1 0x00 0x00 0x00 0x00 Example 4 6 Disassembly of division by zero error lt 0xbcfc gt lt 0xb848 gt lt 0xb798 gt lt x80cc gt Placing a breakpoint on _fp_trapveneer and executing the disassembly in the debug monitor produces gt go Stopped at O x 000BF6C due to SW Instruction Breakpoint Stopped at x QQBF6C TRAPV_S _fp_trapveneer Then inspection of the registers shows ra Qx40A00000 r4 O x0090C1DC r8 0x00000000 r12 0x08000004 CPSR nzcvIFtSVC rl 0x00000000 r2 r5 Q x00 0C1CC r6 r9 Ox00000000 r10 0x00000000 0x00000000 0x0000COD4 SP Ox07FFFFF8 LR 0x0000809C r3 0x00000000 r7 0x00000000 r11 0x00000000 PC Ox0QQQBF6C The address contained in the link register LR is set to 0x809c the address of the instruction after the instruction BL _fdiv that resulted in the exception Copyright 2002 2007 ARM Limited All rights reserved Non Confidential 4 44 Coding Practices 4 42 Examining parameters To save parameters for post mortem debugging you must intercept _fp_trapveneer
42. 4 C casts void g int void g long struct T int mf int int mf int int __asm void f Tx int int BL __cpp static_cast lt int T int int gt amp T mf calls T mf int int BL __cpp static_cast lt void int gt g calls g int BX Ir 6 2 7 Keywords for related base classes The following keyword enables you to determine the offset from the beginning of an object to a base class sub object within it __offsetof_base D B B must be an unambiguous non virtual base class of D 6 22 Copyright 2002 2007 ARM Limited All rights reserved ARM DUI 0205H Non Confidential Using the Inline and Embedded Assemblers Returns the offset from the beginning of a D object to the start of the B base subobject within it The result might be zero Example 6 5 shows the offset in bytes that must be added to a D p to implement the equivalent of static_cast lt B gt p Example 6 5 static_cast lt B gt p __asm Bx my_static_base_cast D xp if __offsetof_base D B lt gt optimize zero offset case ADD r rO __offsetof_base D B endif BX Ir These keywords are converted into integer or logical constants in the assembler source You can only use them in __asm functions but not in a __cpp expression 6 2 8 Keywords for member function classes ARM DUI 0205H The following keywords facilitate the calling of virtual and non virtual member functions from an __asm fun
43. BITINIT input to the core HIGH Note Code compiled using the default options for ARMv6 only runs correctly if unaligned support is enabled on the ARM core U 1 A 1 in CP15 register 1 Enables modulo four alignment checking on an ARMV6 target without unaligned accesses When modulo four alignment checking is enabled your must compile your code using the appropriate option memaccess UL41 for RVCT 2 x no_unaligned_access for RVCT 3 0 and later Note The memaccess option is deprecated and will be removed in a future release For more information see Aligning data on page 4 24 4 44 Copyright 2002 2007 ARM Limited All rights reserved ARM DUI 0205H Non Confidential Coding Practices no_ unaligned_access on page 2 88 in the Compiler Reference Guide 4 8 3 Endian support ARM DUI 0205H You can produce either little endian objects or big endian objects using the compiler command line options littleend and bigend respectively ARMv6 introduces two different endian modes for big endian objects the ARMv6 endian mode BE8 the pre ARMv6 or legacy endian mode BE32 Compiling for ARMv6 endian mode BE8 By default the compiler generates BE8 big endian objects when compiling for ARMv6 big endian The compiler sets a flag in the object code object code that labels the code as BE8 Therefore to enable BE8 support in the ARM core you normally need to set the E bit in the CPSR
44. Compiler Reference Guide e kandr_include on page 2 52 in the Compiler Reference Guide sys_include on page 2 86 in the Compiler Reference Guide Command line options on page 2 2 in the Compiler Reference Guide 2 3 1 The current place ARM DUI 0205H By default the ARM compiler uses Berkeley UNIX search rules so source files and include header files are searched for relative to the current place This is the directory containing the source or header file currently being processed by the compiler When a file is found relative to an element of the search path the directory containing that file becomes the new current place When the compiler has finished processing that file it restores the previous current place At each instant there is a stack of current places corresponding to the stack of nested include directives For example if the current place is the include directory include and the compiler is seeking the include file sys defs h it locates include sys defs h if it exists When the compiler begins to process defs h the current place becomes include sys Any file included by defs h that is not specified with an absolute path name is searched for relative to include sys The original current place include is restored only when the compiler has finished processing defs h You can disable the stacking of current places by using the compiler option kandr_include This option makes the compiler use
45. M in good faith However all warranties implied or expressed including but not limited to implied warranties of merchantability or fitness for purpose are excluded This document is intended only to assist the reader in the use of the product ARM Limited shall not be liable for any loss or damage arising from the use of any information in this document or any error or omission in such information or any incorrect use of the product Where the term ARM is used it means ARM or any of its subsidiaries as appropriate Confidentiality Status This document is Non Confidential The right to use copy and disclose this document may be subject to license restrictions in accordance with the terms of the agreement entered into by ARM and the party that ARM delivered this document to Copyright 2002 2007 ARM Limited All rights reserved ARM DUI 0205H Non Confidential ARM DUI 0205H Product Status The information in this document is final that is for a developed product Web Address http ww arm com Copyright 2002 2007 ARM Limited All rights reserved Non Confidential Copyright 2002 2007 ARM Limited All rights reserved Non Confidential ARM DUI 0205H Contents RealView Compilation Tools Compiler User Guide Chapter 1 Chapter 2 ARM DUI 0205H Preface ABDOUB THIS book strass tree tte aa caveats Maveage viii Feedback oarn a r a oda ekana il ten iaieiiea xiii Introduction 1 1 About the ARM compiler sn 1
46. P instructions However you can specify them using the generic coprocessor instructions Inline assembly code must not be used to change VFP vector mode Inline assembly can contain floating point expression operands that can be evaluated using compiler generated VFP code Therefore it is important that only the compiler modifies the state of the VFP Unsupported instructions The following instructions are not supported in the inline assembler BKPT BX BXJ and BLX instructions Note You can insert a BKPT instruction in C and C code by using the __breakpoint intrinsic SVC instruction LDR Rn expression pseudo instruction Use MOV Rn expression instead this can generate a load from a literal pool LDRT LDRBT STRT and STRBT instructions MUL MLA UMULL UMLAL SMULL and SMLAL flag setting instructions Copyright 2002 2007 ARM Limited All rights reserved 6 7 Non Confidential Using the Inline and Embedded Assemblers 6 1 3 6 8 MOV or MVN flag setting instructions where the second operand is a constant e user mode LDM instructions ADR and ADRL pseudo instructions See __breakpoint on page 4 63 in the Compiler Reference Guide for more information Virtual registers The inline assembler provides no direct access to the physical registers of an ARM processor If an ARM register name is used as an operand in an inline assembler instruction it becomes a reference to a virtual reg
47. RealView Compilation Tools Version 3 1 Compiler User Guide ARM Copyright 2002 2007 ARM Limited All rights reserved ARM DUI 0205H RealView Compilation Tools Compiler User Guide Copyright 2002 2007 ARM Limited All rights reserved Release Information The following changes have been made to this book Change History Date Issue Confidentiality Change August 2002 A Non Confidential Release 1 2 January 2003 B Non Confidential Release 2 0 September 2003 C Non Confidential Release 2 0 1 for RVDS v2 0 January 2004 D Non Confidential Release 2 1 for RVDS v2 1 December 2004 E Non Confidential Release 2 2 for RVDS v2 2 May 2005 F Non Confidential Release 2 2 for RVDS v2 2 SP1 March 2006 G Non Confidential Release 3 0 for RVDS v3 0 March 2007 H Non Confidential Release 3 1 for RVDS v3 1 Proprietary Notice Words and logos marked with or are registered trademarks or trademarks owned by ARM Limited Other brands and names mentioned herein may be the trademarks of their respective owners Neither the whole nor any part of the information contained in or the product described in this document may be adapted or reproduced in any material form except with the prior written permission of the copyright holder The product described in this document is subject to continuous developments and improvements All particulars of the product and its use contained in this document are given by AR
48. To intervene in all calls to _fp_trapveneer use the Super and Sub mechanism For example AREA foo CODE IMPORT Super _fp_trapveneer EXPORT Sub _fp_trapveneer Sub _fp_trapveneer Add code to save whatever registers you need here Take care not to corrupt any needed registers B Super _fp_trapveneer END For more information see Integer division on page 4 38 Using Super and Sub to override symbol definitions on page 4 21 in the Linker Guide Copyright 2002 2007 ARM Limited All rights reserved ARM DUI 0205H Non Confidential Coding Practices 4 8 Support for ARM architecture v6 All components of RVDS 3 1 support ARM architecture v6 In particular the compiler can generate some ARMV6 instructions the inline assembler supports some ARMv6 instructions the embedded assembler supports all ARMve6 instructions 4 8 1 Instruction generation When compiling code for ARMv6 the compiler Generates explicit sign extend and zero extend instructions where appropriate For example consider the C function unpack signed char unpack int i Compiling this code with the option cpu 5 produces unpack PROC return signed char i LSL r0 r0 24 ASR r0 r0 24 BX Ir ENDP Compiling the function unpack with the option cpu 6 produces unpack PROC SXTB r0 r0 BX Ir ENDP Performs code scheduling for ARM11 cores Generates the endian reversal instruct
49. View Compilation Tools Essentials Guide for the latest information See Chapter 2 Getting started with the ARM Compiler for more information on the ARM compiler 1 2 Copyright 2002 2007 ARM Limited All rights reserved ARM DUI 0205H Non Confidential Introduction 1 2 Source language modes ARM DUI 0205H The ARM compiler has three distinct source language modes that you can use to compile different varieties of C and C source code ISO C90 ISO C99 ISO C The ARM compiler compiles C as defined by the 1990 C standard and addenda excepting wide I O Use the compiler option c9 to compile C90 code This is the default The ARM compiler compiles C as defined by the 1999 C standard and addenda excepting complex numbers and wide I O Use the compiler option c99 to compile C99 code The ARM compiler compiles C as defined by the 2003 standard excepting wide streams and export templates Use the compiler option cpp to compile C code The compiler provides support for numerous extensions to the C and C languages For example some GNU compiler extensions are supported The compiler has several modes in which compliance to a source language is either enforced or relaxed Strict mode In strict mode the compiler enforces compliance with the language GNU mode standard relevant to the source language To compile in strict mode use the command line option strict In GNU mode all the GNU compiler extensions t
50. __asm and asm keywords If you include multiple instructions on the same line you must separate them with a semicolon If you use double quotes you must enclose all the instructions within a single set of double quotes If an instruction requires more than one line you must specify the line continuation with the backslash character For the multiple line format you can use C or C comments anywhere in the inline assembly language block However you cannot embed comments in a line that contains multiple instructions The comma is used as a separator in assembly language so C expressions with the comma operator must be enclosed in parentheses to distinguish them asm ADD x y f z An asm statement must be inside a C function An asm statement can be used anywhere a C statement is expected Register names in the inline assembler are treated as C or C variables They do not necessarily relate to the physical register of the same name see Virtual registers on page 6 8 If you do not declare the register as a C or C variable then the compiler generates a warning Do not save and restore registers in inline assembler The compiler does this for you Also the inline assembler does not provide direct access to the physical registers See Virtual registers on page 6 8 for more information If registers other than CPSR and SPSR are read without being written to an error message is issued For ex
51. _macros on page 2 21 in the Compiler Reference Guide remarks on page 2 78 in the Compiler Reference Guide Copyright 2002 2007 ARM Limited All rights reserved 4 13 Non Confidential Coding Practices 4 3 4 3 1 4 3 2 Functions To enable the compiler to perform optimizations more efficiently it is a good idea in general to keep functions small and simple There are several ways of achieving this goal For example you can minimize the number of parameters passed to and from functions return multiple values from a function through the registers using __value_in_regs where possible qualify functions as __pure Minimizing parameter passing overhead There are several ways in which you can minimize the overhead of passing parameters to functions For example __value_in_regs Ensure that functions take four or fewer arguments each a word or less in size Registers RQ R3 can then be used in place of the stack for passing the parameters Note In C non static member functions have an implicit this pointer argument which is usually passed in RO Therefore only three more registers are available for passing additional arguments in this case Ensure that a function does a significant amount of work if it requires more than four arguments so that the cost of passing the stacked arguments is outweighed Put related arguments in a structure and pass a pointer to the structure in any function call This re
52. a BUFLEN b BUFLEN c BUFLEN Overflow Q Clear overflow flag for i 0 i lt BUFLEN i c i L_add ali b i saturated add of a i and b i if Overflow fprintf stderr Overflow on saturated addition n Generally saturating functions have a sticky effect on overflow That is the overflow flag remains set until it is explicitly cleared For more information see the header file dspfns h 3 1 4 TI C55x intrinsics 3 8 The Texas Instruments TI C55x compiler recognizes a number of intrinsics for the optimization of C code RVCT supports the emulation of selected TI C55x intrinsics through the header file c55x h TI C55x intrinsics that are emulated in c55x h include Intrinsics for addition subtraction negation and absolute value such as _sadd and _ssub For example _sadd v1 v2 returns the 16 bit saturated sum of v1 and v2 Intrinsics for multiplication and shifting such as _smpy and _ssh1 For example _smpy v1 v2 returns the saturated fractional mode product of v1 and v2 Intrinsics for rounding saturation bitcount and extremum such as _round and _count For example _round v1 returns the value v1 rounded by adding 215 using unsaturated arithmetic clearing the lower 16 bits Copyright 2002 2007 ARM Limited All rights reserved ARM DUI 0205H Non Confidential Compiler Features The following TI C55x intrinsics are not supported in c55x h Associativ
53. aders changed littleend littleend MD md memaccess no_unaligned_access no_inlinemax forceinline O no_ autoinline no_Jautoinline 0data_reorder data_reorder O no inline no_Jinline O no_ drd None Selected automatically since RVCT 2 1 based on selected CPU or architecture variant Ono_autoinline no_autoinline Ono_data_reorder no_data_reorder Ono_inline no_inline S fs S interleave split_ldm split_ldm strict strict unix_depend_format depend_format unix Wletter diag_suppress tag Use tag to identify the number of the warning message to suppress See Table A 3 on page A 6 zasnumber __align keyword ARM DUI 0205H Copyright 2002 2007 ARM Limited All rights reserved A 5 Non Confidential Using Old Command line Options Table A 2 Mapping of ADS 1 2 compiler options continued Equivalent RVCT ADS compiler option compiler option Usage notes zat min_array_alignment or __align keyword ZC signed_chars Z0 split_sections A 2 2 Controlling ADS 1 2 diagnostic messages in the new release Table A 3 describes options to control diagnostic messages used by the ARM compiler in ADS 1 2 and the equivalent options to control diagnostic messages in the current release of RVCT All the old compiler options listed in Table A 3 are obsolete in the latest
54. ag_suppress 1295 Deprecated declaration format no arg types We Suppresses C2564W diag_suppress 1296 Use of extended initializer Wf Suppresses C2207W diag_suppress 223 Missing function prototype W g Enables C2819W remarks or Warns of unguarded header Enables C2820W diag_warning 1297 1298 files since RVCT v2 0 1 default is suppressed W i Enables C2887W remarks or Implicit constructor default is suppressed diag_warning 367 Wk Suppresses C2621W diag_suppress 1466 double constant automatically converted to float W 1 Enables C2915W None Lower precision in wider default is suppressed context Wm Suppresses C2203W None Multiple character char constants W n Enables C2921W None Implicit narrow cast default is suppressed Wo Suppresses C2201W diag_suppress 1134 Implicit conversion to signed long long constants W p Enables C2812W None Non ANSI header files default is suppressed being included with include lt gt Wq Suppresses C2252W diag_suppress 1299 C constructor Suppresses C2253W initialization order ARM DUI 0205H Copyright 2002 2007 ARM Limited All rights reserved Non Confidential A 7 Using Old Command line Options Table A 3 Controlling ADS 1 2 diagnostic messages continued Old ADS compiler option Old ADS compiler behavior Equivalent RVCT compiler option Usage notes Wr Suppresses C2997W diag_suppress 1300 Implicit virtual w
55. alue_in_regs A pure function is a function that always returns the same result if it is called with the same arguments By default it is sufficient to evaluate any particular call to a pure function only once Because the result of a call to the function is guaranteed to be the same for any identical call each subsequent call to the function in code can be replaced with the result of the original call This is an instance of the compiler optimization known as Common Subexpression Elimination CSE To instruct the compiler that a function is pure declare the function as __pure The use of the __pure keyword is illustrated in the two sample routines of Table 4 7 on page 4 16 Both routines call a function fact to calculate the sum of n and n The fact function depends only on its input argument n to compute n Therefore fact is a pure function Copyright 2002 2007 ARM Limited All rights reserved 4 15 Non Confidential Coding Practices 4 16 The first routine shows a naive implementation of the function fact where fact is not declared __pure In the second implementation the function fact is qualified as __pure to indicate to the compiler that it is a pure function Table 4 7 C code for pure and impure functions A pure function not declared __ pure A pure function declared __pure int fact int n int fact int n __pure int f 1 int f 1 while n gt 0 while n gt 0 f x n f x n return f r
56. ample int f int x asm Copyright 2002 2007 ARM Limited All rights reserved ARM DUI 0205H Non Confidential Using the Inline and Embedded Assemblers STMFD sp rQ save r illegal read before write ADD r x 1 EOR x rQ x LDMFD sp r0 restore r not needed return x The function must be written as int f int x int rQ __asm ADD r x 1 EOR x rQ x return x See Restrictions on inline assembly operations for more information 6 1 2 Restrictions on inline assembly operations ARM DUI 0205H There are a number of restrictions on the operations that can be performed in inline assembly code These restrictions provide a measure of safety and ensure that the assumptions in compiled C and C code are not violated in the assembled assembly code Miscellaneous restrictions The inline assembler has the following restrictions The inline assembler is a high level assembler and the code it generates might not always be exactly what you write Do not use it to generate more efficient code than the compiler generates Use embedded assembler or the ARM assembler armasm for this purpose Some low level features that are available in the ARM assembler armasm such as branching and writing to PC are not supported Label expressions are not supported You cannot get the address of the current instruction using dot notation or PC The amp operator cannot be used t
57. and data marked __declspec dllexport If you use apcs fpic and no_hide_all on the same command line the compiler ignores __declspec d11 and exports all extern variables and functions The compiler disables auto inlining for exported functions For example use no_hide_all and apcs fpic together when building a System V or ARM Linux shared library See __declspec attributes on page 4 24 in the Compiler Reference Guide for more information on the __declspec keyword 2 24 Copyright 2002 2007 ARM Limited All rights reserved ARM DUI 0205H Non Confidential Getting started with the ARM Compiler 2 7 Using linker feedback ARM DUI 0205H Linker feedback enables the efficient elimination of unused functions Unused function code might occur in the following situations Where you have legacy functions that are no longer used in your sources Rather than manually remove the unused function code from your sources you can use linker feedback to remove the unused object code automatically from the final image When a function is inlined If an inlined function is not declared as static the out of line function code is still present in the object file but there is no longer a call to that code Where your image contains both ARM and Thumb code functions that are called from the other state must be built for interworking You can use linker feedback to avoid compiling for interworking those functions that are never called
58. arithmetic model fpmode std IEEE finite values with denormals flushed to zero round to nearest and no exceptions This is the default option and is C and C compatible fpmode fast Perform more aggressive floating point optimizations that might cause a small loss of accuracy to provide a significant performance increase This option results in behavior that is not fully compliant with the ISO C and ISO C standards However numerically robust floating point programs behave correctly Note Initialization code might be required to enable the VFP See VFP support on page 4 36 for more information For more information on specifying floating point conformance see fpmode model on page 2 39 in the Compiler Reference Guide 4 6 6 Using the fpu option The following guidelines can be used to help you select the most suitable floating point build options to use for your application 4 34 Copyright 2002 2007 ARM Limited All rights reserved ARM DUI 0205H Non Confidential ARM DUI 0205H Coding Practices ARM and Thumb floating point ARMV6 and earlier There are several choices for compiling code that carries out floating point operations in ARM state code and Thumb state code ARM only Choose the option fpu vfpv2 to have the compiler generate ARM code only for functions containing floating point operations When the option fpu vfpv2 is selected the compiler generates ARM code for any function
59. arning W s Enables C2221W remarks or Padding inserted in default is suppressed diag_warning 1301 structures diag_warning 2530 Padding added to end of structures W t Enables C2924W None Unused this warning default is suppressed Wu Enables C2204W remarks or Future compatibility with Enables C2920W diag_warning 40 C default is suppressed W v Enables C2218W remarks or Implicit int return type from diag_warning 260 old style C function Wx Suppresses C2866W diag_suppress 177 Variable declared but never Suppresses C2871W referenced Wy Suppresses C20671 diag_suppress 1362 Deprecated features A 8 Copyright 2002 2007 ARM Limited All rights reserved ARM DUI 0205H Non Confidential Using Old Command line Options A3 Migrating command line options from RVCT 2 2 and RVCT 3 0 This section describes migrating RVCT 2 2 and RVCT 3 0 compiler options to the latest release of the compiler A 3 1 Mapping RVCT 2 2 compiler options to the new release Table A 4 describes options used by the ARM compiler in RVCT 2 2 and the equivalent compiler options in the current release of RVCT All the old compiler options listed in Table A 4 are obsolete in the latest release of RVCT and no longer supported If you are upgrading from RVCT 2 2 use Table A 4 to identify options that are no longer supported in the RVCT compiler and to find new names for these flags in the latest release You must migrate any use of old compiler o
60. ary fplib fplib is available as part of the standard distribution of the RealView Development Suite C libraries 4 6 2 VFP architectures VFP is a floating point architecture that provides both single and double precision operations Many operations can take place in either scalar form or in vector form Several versions of the architecture are currently supported including VFPv2 VFPv2 is implemented in the VFP10 revision 1 as provided by the ARM10200E the VFP9 S available as a separately licensable option for ARM926 946 966 the VFP11 as provided in the ARM1136JF S and ARM1176JZF S VFPv3 This architecture is implemented on ARM architecture v7 and later for example the Cortex A8 VFPv3 is backwards compatible with VFPv2 except that it cannot trap floating point exceptions It requires no software support code VFPv3U is an implementation of VFPv3 that can trap floating point exceptions It requires software support code Note Particular implementations of the VFP architecture might provide additional implementation specific functionality For example the VFP coprocessor hardware might include extra registers for describing exceptional conditions This extra functionality is known as sub architecture functionality For more information about sub architecture functionality see ARM Application Note 133 Using VFP with RVDS You can find this application note in the vfpsupport sub directory of the Examp
61. at takes advantage of the NEON architecture when compared to writing assembler directly The NEON intrinsics are defined in the header file arm_neon h The header file defines both the intrinsics and a set of vector types See Appendix E Using NEON Support in the Compiler Reference Guide for more information about NEON intrinsics Example 3 3 shows a short example using NEON intrinsics To build the example 1 Compile the C file neon_example c with the following options armcc c debug cpu Cortex A8 neon_example c 2 Link the image using the command armlink neon_example o o neon_example axf 3 Use a compatible debugger for example RealView Debugger to load and run the image Example 3 3 NEON intrinsics neon_example c Neon intrinsics example program include lt stdint h gt include lt stdio h gt include lt assert h gt include lt arm_neon h gt fill array with increasing integers beginning with Q void fill_array int16_t array int size int i for i 0 i lt size i array i i return the sum of all elements in an array This works by calculating 4 Copyright 2002 2007 ARM Limited All rights reserved 3 11 Non Confidential Compiler Features totals one for each lane and adding those at the end to get the final total int sum_array int16_t sarray int size initialize the accumulator vector to zero int16x4_t acc vdup_n_s16 i
62. ault the compiler looks for source files and creates output files in the current directory Copyright 2002 2007 ARM Limited All rights reserved 2 7 Non Confidential Getting started with the ARM Compiler If a source file is an assembly file that is one with an extension of s the compiler activates the ARM assembler to process the source file The ARM compiler accepts one or more input files for example armcc c options ifile 1 ifile_n Specifying a dash for an input file causes the compiler to read from stdin To specify that all subsequent arguments are treated as filenames not as command switches use the POSIX option See Using command line options on page 2 2 for more information Default behavior The compiler startup configuration is determined by the compiler according to the specified command line options and the filename extensions Command line options override the default configuration determined by the filename extension The compiler startup language can be C or C and the instruction set can be ARM or Thumb When you compile multiple files with a single command all files must be of the same type either C or C The compiler cannot switch the language based on the file extension The following example produces an error because the specified source files have different languages armcc c testl c test2 cpp If you specify files with conflicting file extensions you can force the compiler to com
63. ble problems For a full analysis of your code suppress this warning with diag_suppress C3017 and then use any appropriate third party analysis tool for example Lint Copyright 2002 2007 ARM Limited All rights reserved ARM DUI 0205H Non Confidential Chapter 6 Using the Inline and Embedded Assemblers This chapter describes the optimizing inline assembler and non optimizing embedded assembler of the ARM compiler armcc It contains the following sections ARM DUI 0205H Inline assembler on page 6 2 Embedded assembler on page 6 17 Legacy inline assembler that accesses sp lr or pc on page 6 27 Differences between inline and embedded assembly code on page 6 29 Copyright 2002 2007 ARM Limited All rights reserved 6 1 Non Confidential Using the Inline and Embedded Assemblers 6 1 6 1 1 6 2 Inline assembler The ARM compiler provides an inline assembler that enables you to write optimized assembly language routines and access features of the target processor not available from C or C Note The inline assembler supports ARM assembly language only It does not support Thumb or Thumb 2 assembly language Use the embedded assembler for Thumb and Thumb 2 support The following subsections are included Inline assembler syntax Restrictions on inline assembly operations on page 6 5 Virtual registers on page 6 8 Constants on page 6 9 Instruction expansion on page 6 9 Condition
64. bly of the machine code produced by the compiler for each of the sample implementations of Table 4 1 where the C code for both implementations has been compiled using the options 02 Otime Table 4 2 C Disassembly for incrementing and decrementing loops Incrementing loop Decrementing loop fact1 PROC fact2 PROC MOV r2 r MOVS rl r0 MOV r0 1 MOV r0 1 CMP r2 1 BXEQ lr MOV rl r0 L1 12 BXLT Ir MUL r0 r1 r0 L1 20 SUBS rl r1 1 MUL rd rl r0 BNE L1 12 ADD rl rl 1 BX lr CMP rl r2 ENDP BLE L1 20 BX Ir ENDP Comparing the disassemblies of Table 4 2 shows that the ADD CMP instruction pair in the incrementing loop disassembly has been replaced with a single SUBS instruction in the decrementing loop disassembly This is because a compare with zero can be optimized away In addition to saving an instruction in the loop the variable n does not need to be saved across the loop so the use of a register is also saved in the decrementing loop disassembly This eases register allocation ARM DUI 0205H Copyright 2002 2007 ARM Limited All rights reserved 4 5 Non Confidential Coding Practices 4 6 The technique of initializing the loop counter to the number of iterations required and then decrementing down to zero also applies to while and do statements Loop unrolling Small loops can be unrolled for higher performance with the disadvantage of increased code size When a loop is unrolled a loo
65. cify the filename and location of the PCH file using the following command line options create_pch fi Jename use_pch fi ename pch_dir directory If you use either create_pch or use_pch with the pch_dir option the indicated filename is appended to the directory name unless the filename is an absolute path name Ordering PCH command line options The compiler cannot use these three options together on the same command line If more than one of these options is specified the following rule applies use_pch takes precedence over pch create_pch takes precedence over all other PCH options Most of the features of automatic PCH processing apply to one or other of these modes For example header stop points and PCH file applicability are determined in the same way Controlling PCH processing You can specify that parts of a header file are subject to PCH processing using the following pragmas Insert a manual header stop point using the pragma hdrstop directive in the primary source file before the first token that does not belong to a preprocessing directive Copyright 2002 2007 ARM Limited All rights reserved 2 19 Non Confidential Getting started with the ARM Compiler 2 4 3 2 4 4 2 20 This enables you to specify where the set of header files that is subject to precompilation ends For example include xxx h include yyy h pragma hdrstop include zzz h In this exam
66. ckwards compatibility with existing inline assembler code For example the instruction BL foo r expressionl rl expression2 r2 generates the following pseudocode MOV physical r expression1 MOV physical r1 expression MOV physical r2 virtual r2 BL foo Copyright 2002 2007 ARM Limited All rights reserved 6 13 Non Confidential Using the Inline and Embedded Assemblers 6 1 9 Labels Output value list This list specifies the physical registers that contain the output values from the BL or SWI and where they must be stored The output values are specified as assignments from physical registers to modifiable Ivalue expressions or as single physical register names The inline assembler takes the values from the specified physical registers and assigns them into the specified expressions physical register name specified without assignment causes the virtual register of the same name to be updated with the value from the physical register For example the instruction BL foo resultl r0 r1 generates the following pseudocode BL foo MOV result1 physical r MOV virtual r1 physical r1 Corrupted register list This list specifies the physical registers that are corrupted by the called function If the condition flags are modified by the called function then you must specify the PSR in the corrupted register list The BL and SWI instructions always corrupt Ir If this list is omi
67. containing floating point operations regardless of whether the compiler is compiling for ARM or compiling for Thumb Functions containing floating point operations and that are complied for Thumb are compiled to ARM code because Thumb code cannot contain VFP instructions or access VFP registers Mixed ARM Thumb Choose the option fpu softvfp vfpv2 to have the compiler generate mixed ARM Thumb code When the option fpu softvfp vfpv2 is selected all functions are compiled using software floating point linkage This means that floating point arguments are passed to and returned from functions in integer registers library functions containing ARM code are called to carry out floating point operations from Thumb code Thumb code cannot contain VFP instructions or access VFP registers Software floating point linkage enables functions containing floating point operations and that are compiled for Thumb to be compiled to Thumb code However library functions are called to carry out the floating point operations in ARM code The option that provides the best code size or performance depends upon the code being compiled When compiling for ARM it is best to experiment with the options fpu softvfp vfpv2 and fpu vfpv2 to determine which provides the required code size and performance attributes ARM and Thumb 2 floating point ARMv7 RVDS 3 0 and later Mixed ARM Thumb 2 Choose the option fpu softvfp vfpv3 to have the c
68. cpp files but still generates ARM code for ac and acpp files If you use armcc thumb all files are compiled to produce Thumb code regardless of file suffix Note The following tool names are deprecated and will be removed in the next release e tcc e armcpp e tcpp A 2 Copyright 2002 2007 ARM Limited All rights reserved ARM DUI 0205H Non Confidential Using Old Command line Options A2 Migrating command line options from ADS 1 2 This section describes migrating ADS 1 2 compiler options to the latest release of the compiler Mapping ADS 1 2 compiler options to the new release Table A 2 describes options used by the ARM compiler in ADS 1 2 and the equivalent compiler options in the current release of RVCT All the old compiler options listed in Table A 2 are obsolete in the latest release of RVCT and no longer supported If you are upgrading from ADS 1 2 use Table A 2 and Table A 3 on page A 6 to identify options that are no longer supported in the RVCT compiler and to find new names for these flags in the latest release You must migrate any use of old compiler options to the equivalent options in the latest release of the compiler Table A 2 Mapping of ADS 1 2 compiler options ADS compiler option Equivalent RVCT compiler option Usage notes ansi c90 ansic c90 apcs apcs 3 apcs no swstackcheck None Software stack checking is obsolete in RVCT 3 0 asm a
69. ction The keywords beginning with __mcal1 can be used for both virtual and non virtual functions The keywords beginning with __vcall can be used only with virtual functions The keywords do not particularly help in calling static member functions For examples of how to use these keywords see Calling non static member functions on page 6 25 __mcall_is_virtual D f Results in TRUE if f is a virtual member function found in D or a base class of D otherwise FALSE If it returns TRUE the call can be done using virtual dispatch otherwise the call must be done directly __mcall_is_in_vbase D f Results in TRUE if f is a non static member function found in a virtual base class of D otherwise FALSE If it returns TRUE the this adjustment must be done using __mcall_offsetof_vbase D f otherwise it must be done with __mcall_this_offset D f Copyright 2002 2007 ARM Limited All rights reserved 6 23 Non Confidential Using the Inline and Embedded Assemblers __mcall_offsetof_vbase D f __mcall_this_ __vcall_offse Where D class type and f is a non static member function defined in a virtual base class of D in other words __mcall_is_in_vbase D f returns true This returns at which negative offset in the vtable of the vtable slot that holds the base offset from the beginning of a D object to the start of the base in which f is defined This is the this adjustment necessary when making a call to f witha po
70. d above double and long long data types are eight byte aligned This enables efficient use of the LDRD and STRD instructions in ARMVSTE and above The default implementations of malloc realloc and calloc maintain an eight byte aligned heap The default implementation of alloca returns an eight byte aligned block of memory See alloca on page 2 84 in the Libraries Guide for more information on this C library extension Copyright 2002 2007 ARM Limited All rights reserved ARM DUI 0205H Non Confidential Chapter 3 Compiler Features This chapter gives an overview of ARM specific features of the compiler It includes the following sections Intrinsics on page 3 2 Pragmas on page 3 13 ARM DUI 0205H Copyright 2002 2007 ARM Limited All rights reserved 3 1 Non Confidential Compiler Features 3 1 3 1 1 3 2 Intrinsics The compiler supports several families of intrinsics including Instruction intrinsics for realizing ARM assembly language instructions from your C or C code Intrinsics realizing the ETSI basic operations Intrinsics emulating intrinsics found on the TI C55x compiler NEON intrinsics for use with the NEON vectorizing compiler This section describes these families of intrinsics About intrinsics C and C are suited to a wide variety of tasks but do not provide inbuilt support for specific areas of application for example Digital Signal Processing DSP Within a given
71. d email to errata arm com giving the document title the document number the page number s to which your comments apply a concise explanation of the problem General suggestions for additions and improvements are also welcome ARM DUI 0205H Copyright 2002 2007 ARM Limited All rights reserved xiii Non Confidential Preface xiv Copyright 2002 2007 ARM Limited All rights reserved ARM DUI 0205H Non Confidential Chapter 1 Introduction This chapter introduces the ARM compiler provided with RealView Compilation Tools RVCT It describes the standards of conformance and gives an overview of the runtime libraries provided with RVCT It contains the following sections About the ARM compiler on page 1 2 Source language modes on page 1 3 The C and C libraries on page 1 4 New features of C99 on page 1 5 ARM DUI 0205H Copyright 2002 2007 ARM Limited All rights reserved 1 1 Non Confidential Introduction 1 1 About the ARM compiler The ARM compiler armcc is a mature industrial strength optimizing C and C compiler that compiles Standard C and Standard C source code into machine code for ARM architecture based processors It complies with the Base Standard Application Binary Interface for the ARM Architecture BSABI and generates output objects in ELF format with support for DWARF 3 debug tables If you are upgrading to RVCT from a previous release or are new to RVCT ensure that you read Real
72. d on the ac acpp tc and tcpp file name suffixes is deprecated and will be removed in the next release 2 2 1 Portability To assist portability between hosts use the following guidelines Ensure that filenames do not contain spaces If you have to use path names or filenames containing spaces enclose the path and filename in double or single quotes e Make embedded path names relative rather than absolute Use forward slashes in embedded path names not backslashes 2 2 2 Output files By default the output files created by an ARM compiler are located in the current directory Object files are written in ARM Executable and Linkable Format ELF The ELF documentation is available in install_directory Documentation Specifications 2 12 Copyright 2002 2007 ARM Limited All rights reserved ARM DUI 0205H Non Confidential Getting started with the ARM Compiler 2 3 Include files Several factors affect the way the ARM compiler searches for include header files and source files These include the value of the environment variable RVCT31INC the I and J compiler options the kandr_include and sys_include compiler options whether the filename is an absolute filename or a relative filename whether the filename is between angle brackets or double quotes For more information see Idir dir on page 2 46 in the Compiler Reference Guide Jdir dir on page 2 51 in the
73. dates and corrections to its documentation See http www arm com for current errata sheets and addenda and the ARM Frequently Asked Questions FAQs Copyright 2002 2007 ARM Limited All rights reserved ix Non Confidential Preface ARM publications This book contains reference information that is specific to development tools supplied with RVCT Other publications included in the suite are RVCT Essentials Guide ARM DUI 0202 RVCT Compiler Reference Guide ARM DUI 0348 RVCT Libraries and Floating Point Support Guide ARM DUI 0349 RVCT Linker and Utilities Guide ARM DUI 0206 RVCT Assembler Guide ARM DUI 0204 RVCT Developer Guide ARM DUI 0203 RealView Development Suite Glossary ARM DUI 0324 NEON Vectorizing Compiler Guide ARM DUI 0350 For full information about the base standard software interfaces and standards supported by ARM see install_directory Documentation Specifications In addition see the following documentation for specific information relating to ARM products ARM6 M Architecture Reference Manual ARM DDI 0419 e ARM7 M Architecture Reference Manual ARM DDI 0403 ARM Architecture Reference Manual ARMv7 A and ARMV7 R edition ARM DDI 0406 ARM Architecture Reference Manual Advanced SIMD Extension and VFPv3 Supplement ARM DDI 0268 ARM datasheet or technical reference manual for your hardware device Other publications This book is not inten
74. ded to be an introduction to the C or C programming languages It does not try to teach programming in C or C and it is not a reference manual for the C or C standards Other books provide general information about programming The following publications describe the C language e ISO IEC 14882 2003 C Standard Stroustrup B The C Programming Language 3rd edition 1997 Addison Wesley Publishing Company Reading Massachusetts ISBN 0 201 88954 4 Copyright 2002 2007 ARM Limited All rights reserved ARM DUI 0205H Non Confidential ARM DUI 0205H Preface The following books provide general C programming information Stroustrup B The Design and Evolution of C 1994 Addison Wesley Publishing Company Reading Massachusetts ISBN 0 201 54330 3 This book explains how C evolved from its first design to the language in use today Vandevoorde D and Josuttis N M C Templates The Complete Guide 2003 Addison Wesley Publishing Company Reading Massachusetts ISBN 0 201 73484 2 Meyers S Effective C 1992 Addison Wesley Publishing Company Reading Massachusetts ISBN 0 201 56364 9 This provides short specific guidelines for effective C development Meyers S More Effective C 2nd edition 1997 Addison Wesley Publishing Company Reading Massachusetts ISBN 0 201 92488 9 The following publications provide general C programming information ISO IEC 9899 1999 C Standard
75. ding standardization ITU T Software Tool Library 2005 User s manual included as part of ETSI Recommendation G 191 ETSI Recommendation G723 1 Dual rate speech coder for multimedia communications transmitting at 5 3 and 6 3 kbit s ETSI Recommendation G 729 Coding of speech at 8 kbit s using conjugate structure algebraic code excited linear prediction CS ACELP Publications providing information about TI compiler intrinsics are available from Texas Instruments at http www ti com Copyright 2002 2007 ARM Limited All rights reserved ARM DUI 0205H Non Confidential Feedback Preface ARM Limited welcomes feedback on both RealView Compilation Tools and the documentation Feedback on RealView Compilation Tools If you have any problems with RVCT contact your supplier To help them provide a rapid and useful response give Feedback on this book your name and company the serial number of the product details of the release you are using details of the platform you are running on such as the hardware platform operating system type and version a small standalone sample of code that reproduces the problem a clear explanation of what you expected to happen and what actually happened the commands you used including any command line options sample output illustrating the problem the version string of the tools including the version number and build numbers If you notice any errors or omissions in this book sen
76. duces the number of parameters and increases readability Minimize the number of long long parameters as these take two argument words Minimize the number of double parameters if software floating point is enabled Avoid functions with a variable number of parameters Functions taking a variable number of arguments effectively pass all their arguments on the stack In C and C one way of returning multiple values from a function is to use a structure Normally structures are returned on the stack with all the associated expense this entails Copyright 2002 2007 ARM Limited All rights reserved ARM DUI 0205H Non Confidential 4 3 3 __pure ARM DUI 0205H Coding Practices To reduce memory traffic and reduce code size the compiler enables you to return multiple values from a function through the registers Up to four words can be returned from a function in a struct by qualifying the function with __value_in_regs For example typedef struct s_coord int x int y coord coord reflect int x1 int y1 __value_in_regs You can use __value_in_regs anywhere where you need to return multiple values from a function Examples include returning multiple values from C and C functions returning multiple values from embedded assembly language functions d making supervisor calls re implementing __user_initial_stackheap See __value_in_regs on page 4 19 in the Compiler Reference Guide for more information about __v
77. e is generated when these registers are accessed The initial values of virtual registers are undefined Therefore you must write to virtual registers before reading them The compiler warns you if code reads a virtual register before writing to it The compiler also generates these warnings for legacy code that relies on particular values in physical registers at the beginning of inline assembly code for example int add int i int j int res __asm ADD res r0 r1 relies on i passed in r and j passed in r1 return res This code generates warning and error messages The errors are generated because virtual registers r and r1 are read before writing to them The warnings are generated because rQ and r1 must be defined as C or C variables The corrected code is Copyright 2002 2007 ARM Limited All rights reserved 6 15 Non Confidential Using the Inline and Embedded Assemblers int add int i int j int res __asm ADD res i j return res Instruction expansion The inline assembler in the compiler expands the instructions LDM STM LDRD and STRD into a sequence of single register memory operations that perform the equivalent functionality It is possible that the compiler optimizes the sequence of single register memory operation instructions back into a multiple register memory operation Register lists The order of operands in a register list for an LDM or STM instruction is signi
78. e for the ARM processors 6 2 1 Embedded assembler syntax ARM DUI 0205H An embedded assembly function definition is marked by the __asm C and C or asm C function qualifiers and can be used on member functions non member functions template functions template class member functions Functions declared with __asm or asm can have arguments and return a type They are called from C and C in the same way as normal C and C functions The syntax of an embedded assembly function is __asm return type function name parameter list ARM Thumb Thumb 2 assembler code instruction instruction instruction The initial state of the embedded assembler ARM or Thumb is determined by the initial state of the compiler as specified on the command line This means that if the compiler starts in ARM state the embedded assembler uses arm if the compiler starts in Thumb state the embedded assembler uses thumb The embedded assembler state at the start of each function is as set by the invocation of the compiler as modified by pragma arm and pragma thumb pragmas You can change the state of the embedded assembler within a function by using explicit ARM THUMB or CODE16 directives in the embedded assembler function Such a directive within an __asm function does not affect the ARM or Thumb state of subsequent __asm functions If you are compiling for a Thumb 2 capable processor you can use Thu
79. e in the early stages of porting a program written in old style C In general however it is better to check the code than to switch off messages Change the severity of specific messages This section includes the following subsections Redirecting diagnostics on page 5 2 Severity of diagnostic messages on page 5 3 Controlling the output of diagnostic messages on page 5 4 Changing the severity of diagnostic messages on page 5 5 Suppressing diagnostic messages on page 5 6 Prefix letters in diagnostic messages on page 5 7 Suppressing warning messages with W on page 5 8 Exit status codes and termination messages on page 5 9 Data flow warnings on page 5 10 Copyright 2002 2007 ARM Limited All rights reserved 5 1 Non Confidential Diagnostic Messages 5 1 Redirecting diagnostics Use the errors filename option to redirect compiler diagnostic output to a file Diagnostics that relate to the command options are not redirected See Controlling the output of diagnostic messages on page 5 4 for more information 5 2 Copyright 2002 2007 ARM Limited All rights reserved ARM DUI 0205H Non Confidential Diagnostic Messages 5 2 Severity of diagnostic messages ARM DUI 0205H Diagnostic messages have an associated severity as described in Table 5 1 Table 5 1 Severity of diagnostic messages Severity Description Internal fault Internal faults indicate an internal problem with the compiler Contact your su
80. e message number pragma diag_default tag tag on page 4 51 pragma diag_error tag tag on page 4 52 pragma diag_remark tag tag on page 4 53 pragma diag_suppress tag tag on page 4 54 pragma diag_warning tag tag on page 4 54 Copyright 2002 2007 ARM Limited All rights reserved ARM DUI 0205H Non Confidential Chapter 4 Coding Practices ARM DUI 0205H The ARM compiler armcc is a mature industrial strength ISO C and C compiler capable of producing highly optimized high quality machine code By using programming practices and techniques that work well on RISC processors such as ARM cores however you can increase the portability efficiency and robustness of your C and C source code This chapter describes some of these programming practices together with some programming techniques that are specific to ARM processors This chapter includes the following sections Optimizing code on page 4 2 Code metrics on page 4 11 Functions on page 4 14 Inlining on page 4 19 Aligning data on page 4 24 Using floating point arithmetic on page 4 29 Trapping and identifying division by zero errors on page 4 38 Support for ARM architecture v6 on page 4 43 Copyright 2002 2007 ARM Limited All rights reserved 4 1 Non Confidential Coding Practices 4 1 Optimizing code The ARM compiler is highly optimizing for small code size and high performance The compiler performs optimizations common to
81. e the program Having already read the value of buffer_full into r0 the compiler omits reloading the variable when optimizations are enabled because its value cannot change The result is the infinite loop labeled L1 8 In contrast in the disassembly of the volatile version of the buffer loop the compiler assumes the value of buffer_full can change outside the program and performs no optimizations Consequently the value of buffer_full is loaded into register r inside the loop labeled L1 4 As a result the loop L1 4 is implemented correctly in assembly code To avoid optimization problems caused by changes to program state external to the implementation you must declare variables as volatile whenever their values can change unexpectedly in ways unknown to the implementation In practice you must declare a variable as volatile whenever you are accessing memory mapped peripherals sharing global variables between multiple threads Copyright 2002 2007 ARM Limited All rights reserved 4 9 Non Confidential Coding Practices 4 10 accessing global variables in an interrupt routine Copyright 2002 2007 ARM Limited All rights reserved Non Confidential ARM DUI 0205H Coding Practices 4 2 Code metrics Code metrics provide a means of objectively evaluating code quality The ARM compiler and linker provide several facilities for generating simple code metrics and improving code quality In particular you can
82. e variants of intrinsics for addition and multiply and accumulate This includes all TI C55x intrinsics prefixed with _a_ for example _a_sadd and _a_smac e Rounding variants of intrinsics for multiplication and shifting for example _smacr and _smasr All long long variants of intrinsics This includes all TI C55x intrinsics prefixed with _11 for example _11sadd and _11sh1 long long variants of intrinsics are not supported in RVCT because they operate on 40 bit data All arithmetic intrinsics with side effects For example the TI C55x intrinsics firs and _Ims are not defined in c55x h Intrinsics for ETSI support functions such as L_add_c and L_sub_c Note An exception is the ETSI support function for saturating division divs This intrinsic is supported in c55x h See the header file c55x h for a complete list of the TI C55x intrinsics emulated in RVCT For more information on TI compiler intrinsics see http uww ti com 3 1 5 Named register variables The compiler enables you to access registers of an ARM architecture based processor using named register variables Named register variables are declared by combining the register keyword with the __asm keyword The __asm keyword takes one parameter a character string that names the register For example the declaration register int foo __asm rQ declares foo as a named register variable for the register r0 See Named register variables on pa
83. e virtualization of registers An expression operand or virtual register can appear more than once in a register list and is used each time it is specified The base register is updated if specified The update overwrites any value loaded into the base register during a memory load operation Operating on User mode registers when in a privileged mode by specifying 4 after a register list is not supported by the inline assembler Intermediate operands A C or C constant expression of an integral type might be used as an immediate value in an inline assembly instruction A constant expression that is used to specify an immediate shift must have a value that lies in the range defined in the ARM Architecture Reference Manual as appropriate for the shift operation A constant expression that is used to specify an immediate offset for a memory or coprocessor data transfer instruction must have a value with suitable alignment Function calls and branches The BL and SWI instructions of the inline assembler enable you to specify three optional lists following the normal instruction fields These instructions have the following format SWI cond swi_num input_param_list output_value_list corrupt_reg_list BL cond function input_param_list output_value_list corrupt_reg_list Note You cannot use the SVC instruction in the inline assembler You can only use the SWI instruction The lists are described in the follo
84. embler 2 252288 nevis oi device nineteen edna 6 2 6 2 Embedded assembler ccccccccsccceeeeeceeeeeeeeeeneeeeeeseceaeeeeesesenneeeeeeseaaees 6 17 6 3 Legacy inline assembler that accesses sp Ir OF PC ou seeseeeeesteeeereeeeneees 6 27 6 4 Differences between inline and embedded assembly code 6 29 Using Old Command line Options A 1 Invoking the ARM compiler using older tool names A 2 A 2 Migrating command line options from ADS 1 2 ceeeeceeeseeeesteeeeneeeneetaes A 3 A 3 Migrating command line options from RVCT 2 2 and RVCT 3 0 aaaeeeaa A 9 A4 Warning messages for old options in RVCT e eeceeeeeeeeeeeteeteeeeeeeteeeees A 11 A 5 Getting more information eceeeceeceeeeeeeeeeeeeeteeeeeaeeseeeeaeeeeeseaeeseeteeeend A 12 Copyright 2002 2007 ARM Limited All rights reserved ARM DUI 0205H Non Confidential Preface This preface introduces the RealView Compilation Tools Compiler User Guide It contains the following sections About this book on page viii Feedback on page xiii ARM DUI 0205H Copyright 2002 2007 ARM Limited All rights reserved vii Non Confidential Preface About this book Intended audience Using this book viii This book provides user information for Real View Compilation Tools RVCT and gives an overview of the command line options and compiler specific features that are supported by the ARM compiler This book is written fo
85. emp When the C code of Example 4 1 on page 4 29 is compiled with the command line option softvfp the compiler produces machine code with the disassembly of Example 4 2 In this example floating point arithmetic is performed in software through calls to library routines such as __aeabi_fmul Example 4 2 Support for floating point operations in software foo PROC PUSH r4 r6 Ir MOV r4 rl BL __aeabi_fadd MOV r5 r MOV rl r4 MOV rd r4 BL __aeabi_fmul MOV rl r5 POP r4 r6 Ir B __aeabi_fsub ENDP When the C code of Example 4 1 on page 4 29 is compiled with the command line option vfp the compiler produces machine code with the disassembly of Example 4 3 In this example floating point arithmetic is performed in hardware through floating point arithmetic instructions such as VMUL F32 Example 4 3 Support for floating point operations in hardware foo PROC VADD F32 s2 s s1 VMUL F32 s s1 sl VSUB F32 sQ s0 s2 BX Ir ENDP Copyright 2002 2007 ARM Limited All rights reserved ARM DUI 0205H Non Confidential Coding Practices In practice code that makes use of hardware support for floating point arithmetic is more compact and offers better performance than code that performs floating point arithmetic in software However hardware support for floating point arithmetic requires a VFP coprocessor The default option is to support floating point arithmetic using the software floating point libr
86. er the AAPCS registers fp and sb or modify coprocessor states but the compiler does not recognize these changes If you change processor mode you must not use C or C expressions until you change back to the original mode otherwise the compiler corrupts the registers for the new processor mode Similarly if you change the state of a floating point coprocessor by executing floating point instructions you must not use floating point expressions until the original state has been restored Thumb instruction set The inline assembler is not available when compiling C or C for Thumb state and the inline assembler does not assemble Thumb instructions Instead the compiler switches to ARM state automatically If you want to include inline assembly in code to be compiled for Thumb enclose the functions containing inline assembler code between pragma arm and pragma thumb statements For example Copyright 2002 2007 ARM Limited All rights reserved ARM DUI 0205H Non Confidential ARM DUI 0205H Using the Inline and Embedded Assemblers pragma arm int add int i int j int res __asm ADD res i j add here return res pragma thumb You must also compile your code using the apcs interwork compiler option For more information see Interworking qualifiers on page 2 23 Pragmas on page 4 49 in the Compiler Reference Guide VFP coprocessor The inline assembler does not provide direct support for VF
87. eturn f int foo int n int foo int n return fact n fact n return fact n fact n Table 4 8 shows the corresponding disassembly of the machine code produced by the compiler for each of the sample implementations of Table 4 7 where the C code for each implementation has been compiled using the option 02 Table 4 8 Disassembly for pure and impure functions A pure function not declared __pure A pure function declared __pure fact PROC fact PROC foo PROC foo PROC MOV r3 rO PUSH lr PUSH lr BL fact BL fact LSL rQ r0 1 MOV r2 r POP pc MOV r0 r3 ENDP BL fact ADD r0 r0 r2 POP pc ENDP In the disassembly of the function foo in Table 4 8 where fact is not qualified as __pure the function fact is called twice because the compiler does not know the function is a candidate for CSE In contrast in the disassembly of foo in Table 4 8 where fact is qualified as __pure fact is called only once instead of twice because the compiler has been able to perform CSE when adding fact n fact n Copyright 2002 2007 ARM Limited All rights reserved ARM DUI 0205H Non Confidential Coding Practices By definition pure functions cannot have side effects For example a pure function cannot read or write global state by using global variables or indirecting through pointers because accessing global state can violate the rule that the function must return the same value each time when called twice with t
88. ficant They are used in the order given that is left to right and the first operand references the lowest generated memory address This is in contrast to the behavior in previous compilers where the lowest numbered register always referenced the lowest memory address generated by the instruction This has changed because you can now use expression operands in register lists alongside virtual registers The compiler gives a warning message if it encounters a register list that contains only virtual registers and where the result of the new ordering is different to that from previous ARM C and C compilers Thumb instructions The inline assembler in the compiler does not support the Thumb instruction set It does not assemble Thumb instructions and cannot be used at all when compiling C or C for Thumb state unless you use the pragma arm and pragma thumb pragmas see Thumb instruction set on page 6 6 6 16 Copyright 2002 2007 ARM Limited All rights reserved ARM DUI 0205H Non Confidential Using the Inline and Embedded Assemblers 6 2 Embedded assembler The ARM compiler enables you to include assembly code out of line in one or more C or C function definitions Embedded assembler provides unrestricted low level access to the target processor enables you to use the C and C preprocessor directives and gives easy access to structure member offsets See the Assembler Guide for more information on writing assembly languag
89. fier sets the alignment of any valid type to one This enables objects of packed type to be read or written using unaligned accesses 4 24 Copyright 2002 2007 ARM Limited All rights reserved ARM DUI 0205H Non Confidential ARM DUI 0205H Coding Practices Examples of objects that can be packed include structures unions pointers See __packed on page 4 11 in the Compiler Reference Guide for more information on the __packed qualifier Unaligned fields in structures For efficiency fields in a structure are located on their natural size boundary This means that the compiler often inserts padding between fields to ensure they are aligned When space is at a premium the __packed qualifier can be used to create structures without padding between fields Structures can be packed in two ways The entire struct can be declared as __packed For example __packed struct mystruct char c short s not recommended Each field of the structure inherits the __packed qualifier Declaring an entire struct as __packed typically incurs a penalty both in code size and performance See __ packed structures versus individually __packed fields on page 4 26 for more information Individual non aligned fields within the struct can be declared as __packed For example struct mystruct char c __packed short s recommended This is the recommended approach to packing structures See __packed structure
90. flags on page 6 10 Operands on page 6 10 Function calls and branches on page 6 12 Labels on page 6 14 Differences from previous versions of the ARM C C compilers on page 6 15 For more information see also the chapter on mixing C C and assembly language in the Developer Guide for information on how to use the inline assembler and restrictions on inline assembly language the Assembler Guide for more information on writing assembly language for the ARM processors Inline assembler syntax The ARM compiler supports an extended inline assembler syntax introduced by the asm keyword C or the __asm keyword C and C The syntax for these keywords is described in the following sections Inline assembly with the __asm keyword on page 6 3 Inline assembly with the asm keyword on page 6 3 Rules for using __asm and asm on page 6 4 You can use an asm or __asm statement anywhere a statement is expected Copyright 2002 2007 ARM Limited All rights reserved ARM DUI 0205H Non Confidential ARM DUI 0205H Using the Inline and Embedded Assemblers The inline assembler supports the majority of the ARM instruction set including generic coprocessor instructions The BX BLX and BXJ instructions are not supported The inline assembler supports a subset of ARMvV6 instructions This subset comprises the ARMv6 media instructions only See Restrictions on inline assembly operations on page 6 5 for more
91. g Codes ans ant me ane an AR nn tte 4 2 4 2 Code Metrics sintirina en unten mt ren eee entame 4 11 4 3 FUNCIIONS tierce eta LAN APR SANS TAN eh ae Mae A eee 4 14 4 4 WMI esd hissed eee eet e etl vn eel ee ete 4 19 4 5 AliQning data cect vec dees dates es tan avin ee nt aaa nel A 4 24 4 6 Using floating point arithmetic eee eeeeeeeneeeeneeeeeneeeseneeeeeneeeeeneeeeeneeees 4 29 4 7 Trapping and identifying division by zero errors eeeeeeseeeteneeeeneeeeeaes 4 38 4 8 Support for ARM architecture v6 eeeeeeceeseeeeeeeeeeseeeeeaeeeaeeteaeeeaeeeseeees 4 43 Diagnostic Messages 5 1 Redirecting diagnostics 0 02 ecsceeseececseeceeeseeeeseneeeeseeeeseeeeneeneeseseeeeeeseenenes 5 2 5 2 Severity of diagnostic MESSAGES eeceeceeeeeeeeeeeeeeeeeeeeeeeeeeeeeettaeeeaeeeeeee 5 3 5 3 Controlling the output of diagnostic MESSAGES 0 0 eeeeeeeeteteteeeteeteeeeteees 5 4 5 4 Changing the severity of diagnostic MESSAGES eeeeeeeeeeeteeeteeeeeeeteees 5 5 5 5 Suppressing diagnostic MESSAGES eeceeeceeeeeeeeeeeeeeeeeeeeeeeeeeeeaeeteeeeeaeens 5 6 5 6 Prefix letters in diagnostic MESSAGES 0 00 eee eeeeeeeeseeeeeeneeeeeeeeteneeeeenaeereaes 5 7 5 7 Suppressing warning messages With W uo eeeeeeeeeeeeeeeneeeeeeeeeeteeeteaeee 5 8 5 8 Exit status codes and termination MESSAGES eeeeeeseeeeeeneeteeeeteneeeeees 5 9 5 9 Data flow warnings eisi nnn ikea hie ais 5 10 Using the Inline and Embedded Assemblers 6 1 Inline ass
92. g occur when several source files can share the same PCH file The more sharing the less disk space is consumed Sharing minimizes the disadvantage of large PCH files without giving up the advantage of a significant decrease in compilation times Copyright 2002 2007 ARM Limited All rights reserved ARM DUI 0205H Non Confidential ARM DUI 0205H Getting started with the ARM Compiler Therefore to take full advantage of header file precompilation you might have to re order the include sections of your source files or group include directives within a commonly used header file Different environments and different projects might have differing requirements Be aware however that making the best use of PCH support might require some experimentation and probably some minor changes to source code Copyright 2002 2007 ARM Limited All rights reserved 2 21 Non Confidential Getting started with the ARM Compiler 2 5 2 5 1 2 22 Specifying the target processor or architecture RVCT includes support for all ARM architectures from ARMv4 onwards including ARM NEON technology All architecture names prior to ARMv4 are now obsolete and no longer supported Specifying a target processor or architecture enables the compiler to take advantage of extra features specific to the selected processor or architecture Use the cpu and fpu options to enable these features You can also specify the startup instruction set by using
93. ge 4 101 in the Compiler Reference Guide for more information on the registers of ARM architecture based processors that can be accessed using named register variables A typical use of named register variables is to access bits in the Application Program Status Register APSR Example 3 3 shows the use of named register variables to set the saturation flag Qin the APSR ARM DUI 0205H Copyright 2002 2007 ARM Limited All rights reserved 3 9 Non Confidential Compiler Features 3 10 Example 3 2 Setting bits in the APSR using a named register variable ifndef __BIG_ENDIAN bitfield layout of APSR is sensitive to endianness typedef union struct int int int int int int int int int int oO uw Hamas Qa 5 19 SNO lt A PRPPPPSPHPHPSG b unsigned int word PSR else __BIG_ENDIAN typedef union struct int N int Z int C int V int Q int _d int I int F intT int mo b unsigned int word PSR m 19 e 5 endif __BIG_ENDIAN register PSR apsr __asm apsr void set_Q void Copyright 2002 2007 ARM Limited All rights reserved Non Confidential ARM DUI 0205H Compiler Features apsr b Q 1 3 1 6 NEON Intrinsics ARM DUI 0205H The ARM compiler provides NEON intrinsics to provide an intermediate step for SIMD code generation between a vectorizing compiler and writing assembler code This feature makes it easier to write code th
94. h you can include additional command line options in a file with the compiler option via filename The compiler opens the specified file and reads additional command line options from it See Appendix A Via File Syntax in the Compiler Reference Guide for more information Specifying keyboard input Use minus as the source filename to instruct the compiler to take input from the keyboard The default compiler mode is C To terminate input enter Ctrl Z then Return on Microsoft Windows systems Ctrl D on Red Hat Linux systems An assembly listing for the keyboard input is sent to the output stream after input has been terminated if both the following are true no output file is specified no preprocessor only option is specified for example E If you specify an output file with the o option an object file is written If you specify the E option the preprocessor output is sent to the output stream If you specify the o option the output is sent to the console Copyright 2002 2007 ARM Limited All rights reserved ARM DUI 0205H Non Confidential 2 2 File naming conventions Getting started with the ARM Compiler The ARM compiler uses filename suffixes to identify the classes of file involved in compilation and in the link stage The filename suffixes recognized by the compiler are described in Table 2 1 Table 2 1 Filename suffixes recognized by the ARM compiler
95. he same parameters Therefore you must use __pure carefully in your programs Where functions can be declared __pure however the compiler can often perform powerful optimizations such as CSEs See __ pure on page 4 13 in the Compiler Reference Guide for more information about pure functions 4 3 4 Placing ARM function qualifiers ARM DUI 0205H Many ARM keyword extension modify the behavior or calling sequence of a function For example __pure __irq __swi __swi_indirect __softfp and __value_in_regs all behave in this way gt jas These function modifiers all have a common syntax A function modifier such as __pure can qualify a function declaration either Before the function declaration For example __pure int foo int After the closing parenthesis on the parameter list For example int foo int __pure For simple function declarations each syntax is unambiguous However for a function whose return type or arguments are function pointers the prefix syntax is imprecise For example the following function returns a function pointer but it is not clear whether __pure modifies the function itself or its returned pointer type __pure int foo int int declares foo as a pure function that returns a pointer to a pure function It is ambiguous which of the two function types is pure In fact the single __pure keyword at the front of the declaration of foo modifies both foo itself a
96. header files meet the following requirements The header stop point must appear at file scope It must not be within an unclosed scope established by a header file For example a PCH file is not created in this case xxx h class A XXX C include xxx h int i Copyright 2002 2007 ARM Limited All rights reserved 2 17 Non Confidential Getting started with the ARM Compiler The header stop point must not be inside a declaration that is started within a header file Also in C it must not be part of a declaration list of a linkage specification For example in the following case the header stop point is int but because it is not the start of a new declaration no PCH file is created yyy h static yyy c include yyy h int i e The header stop point must not be inside a if block or a define that is started within a header file e The processing that precedes the header stop point must not have produced any errors Note Warnings and other diagnostics are not reproduced when the PCH file is reused No references to predefined macros __DATE__ or __TIME__ must appear No instances the line preprocessing directive must appear pragma no_pch must not appear The code preceding the header stop point must have introduced a sufficient number of declarations to justify the overhead associated with precompiled headers More than one PCH file might apply to a given compilati
97. ible in the test run For example be sure to execute as many branches of your code as possible and to generate interrupts where appropriate so that they are included in the stack trace Copyright 2002 2007 ARM Limited All rights reserved 4 11 Non Confidential Coding Practices 4 2 3 4 12 4 Examine after your application has finished executing the stack area of memory to see how many of the known values zeros or OxDEADDEAD have been overwritten The stack shows garbage in the part of the stack that has been used and zeros or OXxDEADDEAD values in the remainder 5 Count the number of known entries and multiply by eight This shows how far the stack has grown in memory in bytes For RVISS use a map file to define a region of memory where access is not allowed Place this region directly below your stack in memory If the stack overflows into the forbidden region a data abort occurs which can be trapped by your debugger For more information see Measuring code and data sizes on page 4 11 no_ callgraph in Generating image related information on page 2 29 in the Linker Guide Reducing debug information in objects and libraries It is often useful to reduce the amount of debug information in objects and libraries Reducing the level of debug information Reduces the size of objects and libraries thereby reducing the amount of disk space needed to store them Speeds up link time In the compilation cycle most
98. ies offered in UNIX standard libraries for example the snprintf family of functions Some entirely new library features for example the standardized floating point environment offered in lt fenv h gt A selection of new library features of C99 that might be of particular interest are discussed in the following sections Additional math library functions in lt math h gt C99 supports additional macros types and functions in the standard header lt math h gt that are not found in the corresponding C90 standard header New macros found in C99 that are not found in C90 include Copyright 2002 2007 ARM Limited All rights reserved ARM DUI 0205H Non Confidential Introduction INFINITY positive infinity NAN IEEE not a number New generic function macros found in C99 that are not found in C90 include define isinf x non zero only if x is positive or negative infinity define isnan x non zero only if x is NaN define isless x y 1 only if x lt y and x and y are not NaN and 0 otherwise define isunordered x y 1 only if either x or y is NaN and otherwise New mathematical functions found in C99 that are not found in C90 include double acosh double x hyperbolic arccosine of x double asinh double x hyperbolic arcsine of x double atanh double x hyperbolic arctangent of x double erf double x returns the error function of x double round double x returns x rounded to the neare
99. ile tells the compiler that the variable can be modified at any time externally to the implementation for example by the operating system or by hardware Because the value of a volatile qualified variable can change at any time the physical address of the variable in memory must always be accessed whenever the variable is referenced in code This means the compiler cannot perform optimizations on the variable for example caching it in a local register to avoid memory accesses Copyright 2002 2007 ARM Limited All rights reserved 4 7 Non Confidential Coding Practices 4 8 In contrast when a variable is not declared as volatile the compiler can assume its value cannot be modified outside the implementation Therefore the compiler can perform optimizations on the variable The use of the volatile keyword is illustrated in the two sample routines of Table 4 5 both of which loop reading a buffer until a status flag buffer_full is set to true Both routines assume that the state of buffer_full can change asynchronously with program flow The first routine shows a naive implementation of the loop Notice that the variable buffer_full is not qualified as volatile in this implementation In contrast the second routine shows the same loop where buffer_fu11 is correctly qualified as volatile in the implementation Table 4 5 C code for nonvolatile and volatile buffer loops Nonvolatile version of buffer loop Volatile version of buffer l
100. iler and linker support the GNU extended symbol versioning model To create a function with a symbol version in C or C code you must use the assembler label GNU extension to rename the function symbol into a symbol that has the name function ver for a default ver of function or function ver for a non default ver of function For example to define a default version int new_function void __asm__ versioned_fun ver2 int new_function void return 2 To define a non default version int old_function void __asm__ versioned_fun ver1 int old_function void return 1 For more information see Assembler labels on page 3 21 in the Compiler Reference Guide Symbol versioning on page 4 22 in the Linker Guide Copyright 2002 2007 ARM Limited All rights reserved ARM DUI 0205H Non Confidential Getting started with the ARM Compiler 2 9 Thread local storage ARM DUI 0205H Thread Local Storage TLS is a class of static storage that like the stack exists only once for each thread of execution Each thread in a process is given a location where it can store thread specific data Variables are allocated such that there is one instance of the variable for each existing thread A global index is used to provide unique data for each thread that the process can access One thread allocates the index when the process starts This is then used by the other threads to retrieve the unique data associated with
101. important to eliminate any division by zero errors in code particularly for embedded systems which might not be able to recover easily For ARM processor cores division by zero errors fall into two categories integer division by zero errors software floating point division by zero errors Different techniques are required in both cases for trapping and identifying these errors 4 7 1 Integer division Integer division by zero errors can be trapped and identified by re implementing the appropriate C library helper functions Trapping division by zero errors in code There are two ways you can trap integer division by zero errors Either Re implement the C library helper function __aeabi_idiv so that division by zero returns some standard result for example zero Integer division is implemented in code through the C library helper functions __aeabi_idiv and __aeabi_uidiv Both functions check for division by zero When integer division by zero is detected a branch to __aeabi_idiv is made To trap the division by zero therefore you need only to place a breakpoint on __aeabi_idiv See the Run time ABI for the ARM Architecture for more information on the AEABI functions __aeabi_idiv __aeabi_uidiv and __aeabi_idiv This can be found at http ww arm com products DevTools ABI htm1 Re implement the C library helper function __rt_raise to deal with the signal By default integer division by zero raises a signal
102. ine and Embedded Assemblers void printReg unsigned int spReg IrReg pcReg __asm MOV spReg __current_sp MOV pcReg __current_pc MOV IrReg __return_address printf SP Qx X n spReg printf PC x X n pcReg printf LR x X n 1rReg Method 2 Use embedded assembly to access physical ARM registers from within a C or C source file for example __asm void func MOV r Ir BX Tr This enables the return address of a function to be captured and displayed for example for debugging purposes to show the call tree See Embedded assembler on page 6 17 Note The compiler might also inline a function into its caller function If a function is inlined then the return address is the return address of the function that calls the inlined function Also a function might be tail called See __return_address on page 4 83 in the Compiler Reference Guide for more information 6 28 Copyright 2002 2007 ARM Limited All rights reserved ARM DUI 0205H Non Confidential Using the Inline and Embedded Assemblers 6 4 Differences between inline and embedded assembly code There are differences between the way inline and embedded assembly is compiled Inline assembly code uses a high level of processor abstraction and is integrated with the C and C code during code generation Therefore the compiler optimizes the C and C code and the assembly code together Unlike inli
103. information See the chapter on mixing C C and assembly language in the Developer Guide for more information on inline assembly language in C and C sources Inline assembly with the _asm keyword The inline assembler is invoked with the assembler specifier and is followed by a list of assembler instructions inside braces You can specify inline assembler code using the following formats On a single line for example __asm instruction instruction Must be a single string __asm instruction instruction You cannot include comments On multiple lines for example asm instruction You can use C or C comments anywhere in an inline assembly language block Also see Rules for using __asm and asm on page 6 4 Inline assembly with the asm keyword When compiling C the ARM compiler supports the asm syntax proposed in the ISO C Standard You can specify inline assembler code using the following formats On a single line for example asm instruction instruction Must be a single string asm instruction instruction You cannot include comments On multiple lines for example Copyright 2002 2007 ARM Limited All rights reserved 6 3 Non Confidential Using the Inline and Embedded Assemblers 6 4 asm instruction You can use C or C comments anywhere in an inline assembly language block Rules for using __asm and asm Follow these rules when using the
104. inter to a D Note The offset returns a positive number that then has to be subtracted from the vtable pointer offset D f Where D class type and f is a non static member function defined in D or a non virtual base class of D This returns the offset from the beginning of a D object to the start of the base in which f is defined This is the this adjustment necessary when making a call to f with a pointer to a D It is either zero if f is found in D or the same as __offsetof_base D B where B is a non virtual base class of D that contains f If __mcall_this_offset D f is used when f is found in a virtual base class of D it returns an arbitrary value designed to cause an assembly error if used This is so that such invalid uses of __mcall_this_offset can occur in sections of assembly code that are to be skipped tof_vfunc D f Where D is a class and f is a virtual function defined in D or a base class of D The function returns the negative offset of the slot in the vtable that holds the base offset The base offset is calculated as the distance between a D object to the start of the base in which f is defined If __vcall_offsetof_vfunc D f is used when f is not a virtual member function it returns an arbitrary value designed to cause an assembly error if used 6 24 Copyright 2002 2007 ARM Limited All rights reserved ARM DUI 0205H Non Confidential Using the Inline and Embedded Assemblers 6 2 9 Calling no
105. ions REV REV16 and REVSH if it can deduce that a C expression performs an endian reversal Might make use of some architecture v6 specific implementations of C library functions for example memcpy The compiler cannot generate SIMD instructions because these do not map well onto C expressions 4 8 2 Alignment support By default the compiler uses ARMv6 unaligned access support to speed up access to packed structures by allowing LDR and STR instructions to load from and store to words that are not aligned on natural word boundaries ARM DUI 0205H Copyright 2002 2007 ARM Limited All rights reserved 4 43 Non Confidential Coding Practices You can control alignment support in ARMv6 directly from the processor core using the U and A bits in CP15 register 1 Four combinations are possible U 0 A 0 in CP15 register 1 Enables legacy or pre ARMv6 alignment mode where unaligned loads rotate loaded values This mode of operation is supported in RVCT only when compiling with the cpu 5TE command line option Note When compiling with the cpu 5TE command line option be aware that ARMvV6 instructions cannot be used U 0 A 1 in CP15 register 1 Enables modulo eight alignment checking without unaligned accesses This mode of operation is not supported by the RVCT toolset U 1 A 0 in CP15 register 1 Enables unaligned support on the ARM core Alternatively you can enable unaligned accesses from reset by tying the U
106. ister with the same name and not the physical ARM register The compiler allocates physical registers to each virtual register as appropriate during optimization and code generation However the physical register used in the assembled code might be different to that specified in the instruction You can explicitly define these virtual registers as normal C or C variables If they are not defined then the compiler supplies implicit definitions for the virtual registers The compiler defined virtual registers have function local scope that is within a single function multiple asm statements or declarations that refer to the same virtual register name access the same virtual register No virtual registers are created for the sp r13 1r r14 and pc r15 registers and they cannot be read or directly modified in inline assembly code See Legacy inline assembler that accesses sp lr or pc on page 6 27 for information on how you can modify your source code There is no virtual Processor Status Register PSR Any references to the PSR are always to the physical PSR Existing inline assembler code that conforms to previously documented guidelines continues to perform the same function as in previous versions of the compiler although the actual registers used in each instruction might be different The initial value in each virtual register is unpredictable You must write to virtual registers before reading them The compiler generates a
107. itectures before ARMv7 See Appendix E Using NEON Support in the Compiler Reference Guide for more information Copyright 2002 2007 ARM Limited All rights reserved ARM DUI 0205H Non Confidential Getting started with the ARM Compiler 2 6 Specifying the procedure call standard AAPCS The Procedure Call Standard for the ARM Architecture AAPCS forms part of the Base Standard Application Binary Interface for the ARM Architecture BSABI specification By writing code that adheres to the AAPCS you can ensure that separately compiled and assembled modules can work together For more information see Interworking qualifiers Position independence qualifiers Specifying the target processor or architecture on page 2 22 Procedure Call Standard for the ARM Architecture specification aapcs pdf in install_directory Documentation Specifications 2 6 1 Interworking qualifiers These apcs qualifiers control interworking For more information see apcs qualifer qualifier on page 2 4 in the Compiler Reference Guide Chapter 4 Interworking ARM and Thumb in the Developer Guide Chapter 3 Using the Basic Linker Functionality in the Linker Guide 2 6 2 Position independence qualifiers These apcs qualifiers control position independence They also affect the creation of reentrant and thread safe code For more information see ARM DUI 0205H apcs qualifer qualifier on page 2 4 in the Compiler Reference Guide Restric
108. ize This is because code size for embedded systems is a major issue In most circumstances the decision to inline a particular function is best left to the compiler However you can give the compiler a hint that an inline function is required by using the __inline keyword in C or inline keyword in C It also offers a range of other facilities for modifying its behavior with respect to inlining There are several factors you must take into account when deciding whether to use these facilities or more generally whether to inline a function at all 4 4 1 How the compiler decides to inline When inlining is enabled the compiler uses a complex decision tree to decide when a function is inlined The compiler uses the following simplified algorithm to determine if a function is to be inlined 1 Ifthe function is qualified with __forceinline then the function is inlined if it is possible to do so 2 Ifthe function is qualified with __inline and the option forceinline is selected then the function is inlined if it is possible to do so If the function is qualified with __inline and the option forceinline is not selected then the function is inlined if it is sensible to do so 3 Ifthe optimization level is 02 or higher or autoinline is selected then the function is inlined if it is sensible to inline the function and it is possible to do so When deciding if it is practical to inline a function the compiler takes into accou
109. late options PCH options preprocessor options C language output format target options debug options code generation options optimization options diagnostic options additional checks PCS options pass thru options source Copyright 2002 2007 ARM Limited All rights reserved ARM DUI 0205H Non Confidential Getting started with the ARM Compiler See Chapter 2 Compiler Command line Options in the Compiler Reference Guide for more information on each of the following options help options Shows the main command line options the version number of the compiler and how the compiler has processed the command line help on page 2 45 show_cmdline on page 2 81 vsn on page 2 94 source language Specifies the source language variants accepted by the compiler c90 on page 2 13 c99 on page 2 13 no_ compile_all_input on page 2 14 cpp on page 2 14 gnu on page 2 44 no_ strict on page 2 84 e strict_warnings on page 2 85 These language options can be combined For example armcc c90 gnu search paths Specifies the directories to search for included files Idir dir on page 2 46 Jdir dir on page 2 51 kandr_include on page 2 52 preinclude filename on page 2 75 no_ reduce_paths on page 2 76 sys_include on page 2 86 See Include files on page 2 13 for more information on how these options work together project template optio
110. le 4 4 shows the corresponding disassembly of the machine code produced by the compiler for each of the sample implementations of Table 4 3 on page 4 6 where the C code for each implementation has been compiled using the option 02 Table 4 4 Disassembly for rolled and unrolled bit counting loops Bit counting loop Unrolled bit counting loop countbit1 PROC countbit2 PROC MOV rl 0 MOV rl r0 B L1 20 MOV r0 0 L1 8 B L1 48 TST r0 1 L1 12 ADDNE rl rl 1 TST rl 1 LSR r0 rQ 1 ADDNE rQ r0 1 L1 20 TST rl 2 CMP r0 0 ADDNE rQ r0 1 BNE L1 8 TST rl 4 MOV r0 rl ADDNE rQ r0 1 BX Ir TST r1 8 ENDP ADDNE rQ r0 1 LSR rl rl 4 L1 48 CMP rl 0 BNE L1 12 BX lr ENDP On the ARMY checking a single bit takes six cycles in the disassembly of the bit counting loop shown in the leftmost column The code size is only nine instructions The unrolled version of the bit counting loop checks four bits at a time taking on average only three cycles per bit However the cost is the larger code size of fifteen instructions 41 5 Using volatile ARM DUI 0205H Occasionally you might encounter problems when compiling code at the higher optimization levels 02 and 03 For example you might get stuck in a loop when polling hardware or multi threaded code might exhibit strange behavior In such cases it is likely that you need to declare some of your variables as volatile Declaring a variable as volat
111. les directory of your RVDS distribution at install_directory RVDS Examples vfpsupport ARM DUI 0205H Copyright 2002 2007 ARM Limited All rights reserved 4 31 Non Confidential Coding Practices 4 6 3 The fpu option By default the compiler generates code that makes calls to the software floating point library fplib in order to carry out floating point operations To make use of VFP instructions you must use appropriate compiler options to modify the code generated as described in Table 4 11 Table 4 11 VFP compiler options Option Description Usage notes fpu vfp This is a synonym for fpu vfpv2 fpu vfpv2 Selects hardware vector floating point unit conforming to architecture VFPv2 fpu vfpv3 Selects hardware vector floating point unit conforming Available in to architecture VFPv3 RVDS 3 0 and VFPv3 is backwards compatible with VFPv2 except that later only VFPv3 cannot trap floating point exceptions fpu softvfp Selects the software floating point library fplib This is the default if you do not specify a fpu option or if you select a CPU that does not have an FPU fpu Selects a floating point library with software softvfp vfpv2 floating point linkage that can use VFPv2 instructions fpu Selects a floating point library with software Available in softvfp vfpv3 floating point linkage that uses VFPv3 instructions RVDS 3 0 and later only Note By default some choices of
112. mb 2 instructions when in Thumb state Copyright 2002 2007 ARM Limited All rights reserved 6 17 Non Confidential Using the Inline and Embedded Assemblers 6 18 Note Argument names are permitted in the parameter list but they cannot be used in the body of the embedded assembly function For example the following function uses integer i in the body of the function but this is not valid in assembly __asm int f int 7 ADD i i 1 error You can use for example r instead of i See the chapter on mixing C C and assembly language in Developer Guide for more information on embedded assembly language in C and C sources Embedded assembler example Example 6 1 shows a string copy routine as an embedded assembler routine Example 6 1 String copy with embedded assembler include lt stdio h gt __asm void my_strcpy const char src char dst loop LDRB r2 r0 1 STRB r2 ri 1 CMP r2 0 BNE loop BX Ir int main void const char a Hello world char b 20 my_strcpy a b printf Original string s n a printf Copied string s n b return Q Copyright 2002 2007 ARM Limited All rights reserved ARM DUI 0205H Non Confidential Using the Inline and Embedded Assemblers 6 2 2 Restrictions on embedded assembly The following restrictions apply to embedded assembly functions After preprocessing __asm functions can only contain assembly code
113. mpiler calls the AEABI runtime routine __aeabi_uread4 for reading an unsigned word at an unknown alignment to access the field four because it is not able to determine that the field lies on its natural size boundary In the disassembly of the struct with individually packed fields in Table 4 10 the fields one two and three are accessed just as they are in the case where the entire struct is qualified as __packed In contrast to the situation where the entire struct is packed however the compiler makes a word aligned access to the field four because the presence of the __packed short within the structure helps the compiler to determine that the field four lies on its natural size boundary Copyright 2002 2007 ARM Limited All rights reserved ARM DUI 0205H Non Confidential Coding Practices 4 6 Using floating point arithmetic The ARM compiler provides many features for managing floating point arithmetic both in software and in hardware For example you can specify software or hardware support for floating point particular hardware architectures and the level of conformance to IEEE floating point standards The selection of floating point options determines various trade offs between floating point performance system cost and system flexibility To obtain the best trade off between performance cost and flexibility you need to make sensible choices in your selection of floating point options 4 6 1 Support for floating point
114. n _Pragma preprocessing operator C90 does not permit a pragma directive to be produced as the result of a macro expansion The C99 _Pragma operator enables you to embed a preprocessor macro in a pragma directive For example define RWDATA X PRAGMA arm section rwdata X define PRAGMA X _Pragma X RWDATA foo same as pragma arm section rwdata foo int y 1 y is placed in section foo Copyright 2002 2007 ARM Limited All rights reserved 1 9 Non Confidential Introduction Restricted pointers The C99 keyword restrict enables you to ensure that different object pointer types and function parameter arrays do not point to overlapping regions of memory This enables the compiler to perform optimizations that might otherwise be prevented because of possible aliasing In the following example pointer a does not and cannot point to the same region of memory as pointer b void copy_array int n int restrict a int xrestrict b while n gt xa xb void test void extern int array 100 copy_array 5 array 50 array valid copy_array 5 array 1 array undefined behavior Pointers qualified with restrict can however point to different arrays or to different regions Within an array 14 2 Library features The C99 standard introduces several new library features of interest to programmers including Some features similar to extensions to the C90 standard librar
115. n be used with diag_error diag_remark and diag_warning or when suppressing messages for example armcc diag_suppress C1287 C3017 Use the prefix letters to control options that are passed from the compiler to other tools for example include the prefix letter L to specify linker message numbers ARM DUI 0205H Copyright 2002 2007 ARM Limited All rights reserved 5 7 Non Confidential Diagnostic Messages 5 7 Suppressing warning messages with W The W option suppresses all warnings 5 8 Copyright 2002 2007 ARM Limited All rights reserved ARM DUI 0205H Non Confidential Diagnostic Messages 5 8 Exit status codes and termination messages If the compiler detects any warnings or errors during compilation the compiler writes the messages to stderr At the end of the messages a summary message is displayed that gives the total number of each type of message of the form filename n warnings n errors where n indicates the number of warnings or errors detected Note Remarks are not displayed by default To display remarks use the remarks compiler option No summary message is displayed if only remark messages are generated This section also includes Response to signals e Exit status 5 8 1 Response to signals The signals SIGINT caused by a user interrupt like AC and SIGTERM caused by a UNIX kil command are trapped by the compiler and cause abnormal termination 5 8 2 Exit status
116. n error if you attempt to read a virtual register before writing to it for example if you attempt to read the virtual register associated with the variable r1 You must also explicitly declare the names of the variables in your C or C code It is better to use C or C variables as instruction operands The compiler generates a warning the first time a virtual or physical register name is used and only once for each translation unit For example if you specify register r3 a warning is displayed Copyright 2002 2007 ARM Limited All rights reserved ARM DUI 0205H Non Confidential 6 1 4 Constants Using the Inline and Embedded Assemblers The constant expression specifier is optional If it is used the expression following it must be a constant 6 1 5 Instruction expansion ARM DUI 0205H An ARM instruction in inline assembly code might be expanded into several instructions in the compiled object The expansion depends on the instruction the number of operands specified in the instruction and the type and value of each operand Instructions using constants The constant in an instruction with a constant operand is not limited to the values permitted by the instruction Instead the compiler translates the instruction into a sequence of instructions with the same effect For example ADD r r0 1023 might be translated into ADD r0 rQ 1024 SUB r0 r0 1 With the exception of coprocessor instructions all ARM instructi
117. n static member functions ARM DUI 0205H You can use keywords beginning with __mcal1 and __veall to call non virtual and virtual functions from __asm functions See Keywords for member function classes on page 6 23 for more information There is no __mcall_is_static to detect static member functions because static member functions have different parameters that is no this and therefore call sites are likely to already be specific to calling a static member function Calling a non virtual member function Example 6 6 shows the following code can be used to call a non virtual function in either a virtual or non virtual base Example 6 6 Calling a non virtual function rp contains a D and we wish to do the equivalent of rp gt f where f is a non virtual function all arguments other than the this pointer are already setup assumes f does not return a struct if __mcall_is_in_vbase D f LDR r12 rp fetch vtable pointer LDR r r12 __mcall_offsetof_vbase D f fetch the vbase offset ADD r r rp do this adjustment else MOV r rp set up this pointer for D ADD r rO __mcall_this_offset D f do this adjustment endif BL __cpp amp D f call Di f Calling a virtual member function Example 6 7 shows code that can be used to call a virtual function in either a virtual or non virtual base Example 6 7 Calling a virtual function rp contains a Dx and we wish to do the equivalent of rp
118. nd armcc diag_remark 1293 Note These options also have pragma equivalents See Pragmas on page 3 13 for more information The following diagnostic messages can be changed Messages with the number format nnnn D Warning messages with the number format Cnnnnw ARM DUI 0205H Copyright 2002 2007 ARM Limited All rights reserved 5 5 Non Confidential Diagnostic Messages 5 5 5 6 Suppressing diagnostic messages To suppress all diagnostic messages that have the specified tag s use the following option diag_suppress fagl tag See also Pragmas on page 3 13 diag_suppress tag tag on page 2 28 in the Compiler Reference Guide Copyright 2002 2007 ARM Limited All rights reserved ARM DUI 0205H Non Confidential Diagnostic Messages 5 6 Prefix letters in diagnostic messages The RVCT tools automatically insert an identification letter to diagnostic messages as described in Table 5 2 Using these prefix letters enables the RVCT tools to use overlapping message ranges Table 5 2 Identifying diagnostic messages Prefix letter RVCT tool C armcc A armasm L armlink or armar Q fromelf The following rules apply All the RVCT tools act on a message number without a prefix A message number with a prefix is only acted on by the tool with the matching prefix A tool does not act on a message with a non matching prefix Thus the compiler prefix C ca
119. nd the function pointer type returned by foo In contrast the postfix syntax because it enables a clear distinction between whether __pure applies to the argument the return type or the base function when declaring a function whose argument and return types are function pointers For example int fool int __pure int fool is a pure function returning a pointer to a normal function Copyright 2002 2007 ARM Limited All rights reserved 4 17 Non Confidential Coding Practices int foo2 int int __pure foo2 is a function returning a pointer to a pure function int foo3 int __pure int __pure foo3 is a pure function returning a pointer to a pure function In this example fool and foo3 are modified themselves foo2 and foo3 return a pointer to a modified function the functions foo3 and foo are identical Because the postfix syntax is more precise than the prefix syntax it is recommended that where possible you make use of the postfix syntax when qualifying functions with ARM function modifiers 4 18 Copyright 2002 2007 ARM Limited All rights reserved ARM DUI 0205H Non Confidential 4 4 Inlining Coding Practices Inlining of functions offers a trade off between code size and performance By default the compiler decides for itself whether to inline code or not As a general rule the compiler makes sensible decisions about inlining with a view to producing code of a minimal s
120. ne assembly code embedded assembly code is assembled separately from the C and C code to produce a compiled object that is then combined with the object from the compilation of the C or C source e Inline assembly code can be inlined by the compiler but embedded assembly code cannot be inlined either implicitly or explicitly Table 6 1 summarizes the main differences between inline assembler and embedded assembler Table 6 1 Differences between inline and embedded assembler Feature Embedded assembler Inline assembler Instruction set ARM and Thumb ARM only ARM assembler directives All supported None supported ARMv6 instructions All supported Supports only the media instructions C C expressions Constant expressions only Full C C expressions Optimization of assembly code No optimization Full optimization Inlining Never Possible Register access Specified physical registers are used You can also use PC LR and SP Uses virtual registers see Virtual registers on page 6 8 Using sp r13 1r r14 and pc r15 gives an error See Legacy inline assembler that accesses sp lr or pc on page 6 27 Return instructions You must add them in your code Generated automatically The BX BXJ and BLX instructions are not supported BKPT instruction Supported directly Not supported See also Differences between expres
121. ne instead of just __inline is a good coding style because it serves as a reminder to the programmer that __inline functions are implicitly static See Common group or section elimination on page 3 11 in the Linker Guide for more information 4 4 5 Debugging data and the no _inline keyword Inlined functions can appear in multiple places in compiled code Therefore it is quite complex to provide full debug information for inline functions In practice it is useful to avoid generating debug information for inline functions You can enable or disable the inlining of functions using the no_ inline command line option See no_Jinline on page 2 49 in the Compiler Reference Guide for more information 4 4 6 Marking functions as static ARM DUI 0205H At the optimization levels 02 and 03 the compiler is able to automatically inline a function if it is sensible to do so even when the function is not declared as __inline or inline Copyright 2002 2007 ARM Limited All rights reserved 4 21 Non Confidential Coding Practices Note To control the automatic inlining of functions at higher optimization levels use the no_ Jautoinline command line option Unless a function is explicitly declared as static or __inline the compiler has to retain the out of line version of it in the object file in case it is called from some other module The linker is unable to remove unused out of line functions from an object unless un
122. ns Controls the behavior of project templates no_ project filename on page 2 74 reinitialize_workdir on page 2 77 workdir directory on page 2 95 PCH options Controls the processing of PCH files create_pch filename on page 2 18 pch on page 2 70 pch_dir dir on page 2 71 ARM DUI 0205H Copyright 2002 2007 ARM Limited All rights reserved 2 3 Non Confidential Getting started with the ARM Compiler preprocessor options no_ pch_messages on page 2 72 no_ pch_verbose on page 2 72 use_pch filename on page 2 89 Specifies preprocessor behavior including preprocessor output and macro definitions C language output format C on page 2 13 no_ code_gen on page 2 14 Dname parm list def on page 2 19 E on page 2 33 M on page 2 60 Uname on page 2 87 Specifies options specific to C compilation no_Janachronisms on page 2 3 no_ dep_name on page 2 22 no_ export_all_vtbl on page 2 35 no_ force_new_nothrow on page 2 38 no_ friend_injection on page 2 43 no_ guiding_decls on page 2 44 no_Jimplicit_include on page 2 47 no_Jimplicit_include_searches on page 2 47 no_Jimplicit_typename on page 2 48 no_ nonstd_qualifier_deduction on page 2 64 no_Jold_specializations on page 2 68 no_ parse_templates on page 2 70 pending_instantiations n on page 2 73 no_ rtti on page 2 79 no_ using_std on page 2 90 no_ vfe on page 2 92 S
123. nsic might be more efficient than corresponding implementations in C or C resulting in both reduced instruction and cycle counts To implement the intrinsic the compiler automatically generates the best sequence of instructions for the specified target architecture For example the L_add intrinsic maps directly to the ARM v5TE assembly language instruction qadd QADD r0 r rl Assuming r0 a rl b on entry An intrinsic never makes unnecessary function calls so function call overhead is minimized These performance benefits can be significant for real time processing applications Care needs to be taken when using intrinsics however because their use can decrease code portability 3 1 2 Instruction intrinsics ARM DUI 0205H The ARM compiler provides a range of instruction intrinsics for realizing ARM assembly language instructions from within your C or C code Collectively these intrinsics enable you to emulate inline assembly code using a combination of C code and instruction intrinsics Generic intrinsics The following generic intrinsics are ARM language extensions to the ISO C and C standards __ breakpoint on page 4 63 in the Compiler Reference Guide __builtin_clz on page 4 64 in the Compiler Reference Guide __builtin_expect on page 4 65 in the Compiler Reference Guide __current_pc on page 4 70 in the Compiler Reference Guide __current_sp on page 4 70 in the Compiler Reference Guide Copyright
124. nt several other criteria including whether you select Ospace or Otime Select Otime to increase the likelihood that a function is inlined See When is it practical for the compiler to inline for more information You cannot override any decision made by the compiler about when it is practical to inline a function For example you cannot force a function to be inlined if the compiler thinks it is not sensible 442 When is it practical for the compiler to inline ARM DUI 0205H The compiler decides for itself when it is practical to inline a function or not depending on a number of conditions including the size of the function and how many times it is called Copyright 2002 2007 ARM Limited All rights reserved 4 19 Non Confidential Coding Practices the current optimization level whether it is optimizing for speed Otime or size Ospace whether the function has external or static linkage Ultimately the compiler can decide not to inline a function even if the function is qualified with __forceinline As a general rule smaller functions stand a better chance of being inlined compiling with Otime increases the likelihood that a function is inlined large functions are not normally inlined because this can adversely affect code density and performance 4 4 3 Managing inlining You can force the compiler to attempt to inline a function using the __forceinline keyword The compiler places the
125. nt32x2_t accl int64x1_t acc2 this implementation assumes the size of the array is a multiple of 4 assert size 4 0 counting backwards gives better code for size 0 size 4 int16x4_t vec load 4 values in parallel from the array vec vldi_s16 array increment the array pointer to the next element array 4 add the vector to the accumulator vector acc vadd_sl6 acc vec calculate the total accl vpaddl_s16 acc acc2 vpaddl_s32 accl return the total as an integer return int vget_lane_s64 acc2 0 main function int main int16_t my_array 100 fill_array my_array 100 printf Sum was d n sum_array my_array 100 return Q For more information about NEON see NEON technology on page 2 22 ARM DAI 0156A Using Neon Intrinsics with RVDS in instal _directory Documentation Speci fications The Assembler Guide Copyright 2002 2007 ARM Limited All rights reserved Non Confidential ARM DUI 0205H Compiler Features 3 2 Pragmas The ARM compiler recognizes pragmas of the following form pragma no_ feature name Note Pragmas override related command line options For example pragma arm overrides the thumb command line option For more information see the relevant section in the Compiler Reference Guide Pragmas for saving and restoring the pragma state The following pragmas enable
126. nv int fesetenv const fenv_t penv set the floating point environment to penv snprintf family of functions in lt stdio h gt Using the sprintf family of functions found in the C90 standard header lt stdio h gt can be dangerous In the statement sprintf buffer size Error d Cannot open file s errno filename the variable size specifies the minimum number of characters to be inserted into buffer Consequently more characters can be output than might fit in the memory allocated to the string The snprintf functions found in the C99 version of lt stdio h gt are safe versions of the sprintf functions that prevent buffer overrun In the statement snprintf buffer size Error d Cannot open file s errno filename the variable size specifies the maximum number of characters that can be inserted into buffer The buffer can never be overrun provided its size is always greater than the size specified by size Type generic math macros in lt tgmath h gt The new standard header lt tgmath h gt defines several families of mathematical functions that are type generic in the sense that they are overloaded on floating point types For example the trigonometric function cos works as if it has the overloaded declaration extern float cos float x extern double cos double x extern long double cos long double x A statement such as p cos 0 78539f p cos pi 4 calls the single precision version of
127. o denote hexadecimal constants Use the 0x prefix instead For example Copyright 2002 2007 ARM Limited All rights reserved 6 5 Non Confidential Using the Inline and Embedded Assemblers 6 6 __asm AND x y xF00 The notation to specify the actual rotate of an 8 bit constant is not available in inline assembly language This means that where an 8 bit shifted constant is used the C flag must be regarded as corrupted if the NZCV flags are updated You must not modify the stack This is not necessary because the compiler automatically stacks and restores any working registers as required The compiler does not permit you to explicitly stack and restore work registers Registers Registers such as rQ r3 sp Ir and the NZCV flags in the CPSR must be used with caution If you use C or C expressions these might be used as temporary registers and NZCV flags might be corrupted by the compiler when evaluating the expression See Virtual registers on page 6 8 The pc Ir and sp registers cannot be explicitly read or modified using inline assembly code because there is no direct access to any physical registers However you can use the following intrinsics to access these registers __current_pc on page 4 70 in the Compiler Reference Guide __current_sp on page 4 70 in the Compiler Reference Guide __return_address on page 4 83 in the Compiler Reference Guide Processor modes You can change processor modes alt
128. o the relevant source language are available To compile in GNU mode use the compiler option gnu For more information on source language modes and language compliance see New features of C99 on page 1 5 Source language modes on page 1 3 in the Compiler Reference Guide Language extensions and language compliance on page 1 5 in the Compiler Reference Guide c90 on page 2 13 in the Compiler Reference Guide c99 on page 2 13 in the Compiler Reference Guide cpp on page 2 14 in the Compiler Reference Guide e gnu on page 2 44 in the Compiler Reference Guide e no_ strict on page 2 84 in the Compiler Reference Guide Copyright 2002 2007 ARM Limited All rights reserved 1 3 Non Confidential Introduction 13 The C and C libraries RVCT provides the following runtime C and C libraries The ARM C libraries The ARM C libraries provide standard C functions and helper functions used by the C and C libraries The ARM libraries comply with the C Library ABI for the ARM Architecture CLIBABI the C ABI for the ARM Architecture CPPABI For more information see The C and C libraries on page 1 8 in the Compiler Reference Guide ABI for the ARM Architecture compliance on page 1 3 in the Libraries Guide Rogue Wave Standard C Library version 2 02 03 The Rogue Wave Standard C Library as supplied by Rogue Wave Software Inc provides standard C functions and objects such as c
129. ompiler generate mixed ARM Thumb code Copyright 2002 2007 ARM Limited All rights reserved 4 35 Non Confidential Coding Practices 4 6 7 4 36 ARM only When the option fpu softvfp vfpv3 is selected all functions are compiled using software floating point linkage This means that floating point arguments are passed to and returned from functions in ARM integer registers Software floating point linkage enables you to link with generic libraries and legacy code that are themselves built with software floating point linkage Choose the options arm fpu vfpv3 to have the compiler generate ARM code only Thumb 2 only VFP support Choose the options thumb fpu vfpv3 to have the compiler generate Thumb 2 code only for your entire program without needing to switch to ARM state to perform VFP operations Note This option is available only for ARMv7 processors with VFPv3 for example the Cortex A8 where VFP is directly accessible from both the ARM and Thumb 2 instruction set ARM VFP coprocessors are optimized to process well defined floating point code in hardware Arithmetic operations that occur too rarely or that are too complex are not handled in hardware Instead processing of these cases must be handled in software This approach minimizes the amount of coprocessor hardware required and reduces costs Code provided to handle cases the VFP hardware is unable to process is known as VFP support
130. on If so the largest is used that is the one representing the most preprocessing directives from the primary source file For instance a primary source file might begin with include xxx h include yyy h include zzz h If there is one PCH file for xxx h and a second for xxx h and yyy h the latter PCH file is selected assuming that both apply to the current compilation Additionally after the PCH file for the first two headers is read in and the third is compiled a new PCH file for all three headers might be created In automatic PCH processing mode the compiler indicates that a PCH file is obsolete and deletes it under the following circumstances if the PCH file is based on at least one out of date header file but is otherwise applicable for the current compilation 2 18 Copyright 2002 2007 ARM Limited All rights reserved ARM DUI 0205H Non Confidential Getting started with the ARM Compiler if the PCH file has the same base name as the source file being compiled for example xxx pch and xxx c but is not applicable for the current compilation for example because you have used different command line options These describe some common cases You must delete other PCH files as required 2 4 2 Manual PCH processing ARM DUI 0205H You can specify the filename and location of PCH files and the parts of a header file that are subject to PCH processing Specifying a PCH filename and location You can spe
131. ondition flags Operands An inline assembly instruction might explicitly or implicitly attempt to update the processor condition flags Inline assembly instructions that involve only virtual register operands or simple expression operands see Operands have predictable behavior The condition flags are set by the instruction if either an implicit or an explicit update is specified The condition flags are unchanged if no update is specified If any of the instruction operands are not simple operands then the condition flags might be corrupted unless the instruction updates them In general the compiler cannot easily diagnose potential corruption of the condition flags However for operands that require the construction and subsequent destruction of C temporaries the compiler gives a warning if the instruction attempts to update the condition flags This is because the destruction might corrupt the condition flags Operands can be one of several types Virtual registers Registers specified in inline assembly instructions always denote virtual registers and not the physical ARM integer registers Virtual registers require no declaration and the size of the virtual registers is the same as the physical registers However the physical register used in the assembled code might be different to that specified in the instruction See Virtual registers on page 6 8 for more information Expression operands Function arguments C or C variables
132. ons A4 Warning messages for old options in RVCT ARM DUI 0205H If you are using the latest release of RVCT and you specify an obsolete command line option the compiler might issue either an error or a warning depending on whether an equivalent option exists in the current release of the compiler For example specifying armcc cpp on the command line results in a warning about old syntax because the old ADS 1 2 option cpp has the equivalent RVCT option cpp In contrast specifying armcc fh results in a fatal error because the old ADS 1 2 option fh has no equivalent in the current release of the compiler Old style command line options that are currently accepted by the compiler with a warning are not guaranteed to be recognized in future releases of the RVCT toolset Therefore you must migrate any use of old compiler options to the equivalent options in the latest release of the compiler Copyright 2002 2007 ARM Limited All rights reserved A 11 Non Confidential Using Old Command line Options A5 Getting more information See the RealView Compilation Tools Essentials Guide for a full list of the command line options that are deprecated and obsolete in the latest release For information about previous releases of RVCT see Appendix A in the RealView Compilation Tools Essentials Guide A 12 Copyright 2002 2007 ARM Limited All rights reserved ARM DUI 0205H Non Confidential
133. ons are not currently supported in RVCT The ETSI basic operations serve as a set of primitives for developers publishing codec algorithms rather than as a library for use by developers implementing codecs in C or C RVCT provides support for the ETSI basic operations through the header file dspfns h 3 6 Copyright 2002 2007 ARM Limited All rights reserved ARM DUI 0205H Non Confidential ARM DUI 0205H Compiler Features ETSI operations in RVCT The dspfns h header file contains definitions of the ETSI basic operations as a combination of C code and intrinsics RVCT supports the original ETSI family of basic operations described in the ETSI G 729 recommendation Coding of speech at 8 kbit s using conjugate structure algebraic code excited linear prediction CS ACELP including 16 bit and 32 bit saturated arithmetic operations such as add and sub For example add v1 v2 adds two 16 bit numbers v1 and v2 together with overflow control and saturation returning a 16 bit result 16 bit and 32 bit multiplication operations such as mult and L_mult For example mult v1 v2 multiplies two 16 bit numbers v1 and v2 together returning a scaled 16 bit result 16 bit arithmetic shift operations such as sh and shr For example the saturating left shift operation sh1 v1 v2 arithmetically shifts the 16 bit input v1 left v2 positions A negative shift count shifts v1 right v2 positions 16 bit data conversion operations such
134. ons with a constant operand support instruction expansion In addition the MUL instruction can be expanded into a sequence of adds and shifts when the third operand is a constant The effect of updating the CPSR by an expanded instruction is arithmetic instructions set the NZCV flags correctly e logical instructions setthe NZ flags correctly do not change the V flag corrupt the C flag Load and store instructions The LDM STM LDRD and STRD instructions might be replaced by equivalent ARM instructions In this case the compiler outputs a warning message informing you that it might expand instructions Inline assembly code must be written in such a way that it does not depend on the number of expected instructions or on the expected execution time for each specified instruction Copyright 2002 2007 ARM Limited All rights reserved 6 9 Non Confidential Using the Inline and Embedded Assemblers 6 1 6 6 1 7 6 10 Instructions that normally place constraints on pairs of operand registers such as LDRD and STRD are replaced by a sequence of instructions with equivalent functionality and without the constraints However these might be recombined into LDRD and STRD instructions All LDM and STM instructions are expanded into a sequence of LDR and STR instructions with equivalent effect However the compiler might subsequently recombine the separate instructions into an LDM or STM during optimization C
135. oop int buffer_full volatile int buffer_full int read_stream void int read_stream void int count 0 int count Q while buffer_ful1 while buffer_full count count return count return count Copyright 2002 2007 ARM Limited All rights reserved ARM DUI 0205H Non Confidential ARM DUI 0205H Coding Practices Table 4 6 shows the corresponding disassembly of the machine code produced by the compiler for each of the sample implementations of Table 4 1 on page 4 5 where the C code for each implementation has been compiled using the option 02 Table 4 6 Disassembly for nonvolatile and volatile buffer loop Nonvolatile version of buffer loop Volatile version of buffer loop read_stream PROC read_stream PROC LDR ri L1 28 LDR r1 L1 28 MOV r0 0 MOV r0 0 LDR ri r1 0 IL1 8 IL1 12 LDR r2 r1 0 buffer _full CMP rl 0 CMP r2 0 ADDEQ rQ rQ 1 ADDEQ rQ r0 1 BEQ IL1 12 infinite loop BEQ IL1 8 BX Ir BX lr ENDP ENDP L1 28 IL1 28 DCD data DCD data AREA data DATA ALIGN 2 AREA data DATA ALIGN 2 buffer_full buffer_full DCD 0x00000000 DCD 0x00000000 In the disassembly of the nonvolatile version of the buffer loop in Table 4 6 the statement LDR r r 0 loads the value of buffer_full into register r outside the loop labeled L1 8 Because buffer_full is not declared as volatile the compiler assumes that its value cannot be modified outsid
136. operations ARM DUI 0205H The ARM processor core does not contain floating point hardware Floating point arithmetic must be supported separately either In software through the floating point library fplib This library provides functions that can be called to implement floating point operations using no additional hardware See The software floating point library fplib on page 4 2 in the Libraries Guide for more information In hardware using a hardware VFP coprocessor attached to the ARM processor core to provide the required floating point operations VFP is a coprocessor architecture that implements IEEE floating point and supports single and double precision but not extended precision Note In practice floating point arithmetic in the VFP is actually implemented using a combination of hardware which executes the common cases and software which deals with the uncommon cases and cases causing exceptions See VFP support on page 4 36 for more information The differences between software and hardware support for floating point arithmetic are illustrated with Example 4 1 which shows a function implementing floating point arithmetic operations in C Example 4 1 Floating point operations float foo float numl float num2 float temp temp2 Copyright 2002 2007 ARM Limited All rights reserved 4 29 Non Confidential Coding Practices 4 30 temp numl num temp2 num2 num2 return temp2 t
137. ostic messages errors fi lename Redirects the output of diagnostic messages from stderr to the specified errors file filename This option is useful on systems where output redirection of files is not well supported remarks Causes the compiler to issue remark messages such as warning of padding in structures Remarks are not issued by default no_ wrap_diagnostics Enables or disables the wrapping of error message text when it is too long to fit on a single line See Command line options on page 2 2 in the Compiler Reference Guide for more information Copyright 2002 2007 ARM Limited All rights reserved ARM DUI 0205H Non Confidential Diagnostic Messages 5 4 Changing the severity of diagnostic messages These options enable you to change the diagnostic severity of all remarks and warnings and a limited number of errors diag_error tag tag Sets the diagnostic messages that have the specified tag s to Error severity diag_remark tag tag Sets the diagnostic messages that have the specified tag s to Remark severity diag_warning tag tag Sets the diagnostic messages that have the specified tag s to Warning severity These options require a comma separated list of the error messages that you want to change For example you might want to change a warning message with the number 1293 to Remark severity because remarks are not displayed by default To do this use the following comma
138. other optimizing compilers for example data flow optimizations such as common sub expression elimination and loop optimizations such as loop combining and distribution In addition the compiler performs a range of optimizations specific to ARM architecture based processors Even though the compiler is highly optimizing you can often significantly improve the performance of your C or C code by selecting correct optimization criteria target processor and architecture inlining options and by adopting good RISC programming practices 4 1 1 Optimizing for size versus speed The compiler provides two options for optimizing code size and performance Ospace This option causes the compiler to optimize mainly for code size This is the default option Otime This option causes the compiler to optimize mainly for speed For best results you must build your application using the most appropriate command line option Note For small functions it is not guaranteed that Otime always generates faster code or that Ospace always generates smaller code The exact outcome of a particular optimization cannot be determined until all optimizations have been applied at which point it is too late to undo any optimizations For more information see Ospace on page 2 68 in the Compiler Reference Guide Otime on page 2 69 in the Compiler Reference Guide 4 1 2 Optimization levels and the debug view 4 2 The precise optimizations
139. out It also includes data structures and algorithms known as the Standard Template Library STL For more information on the Rogue Wave libraries see the Rogue Wave HTML documentation and the Rogue Wave web site at http www roguewave com Support libraries The ARM C libraries provide additional components to enable support for C and to compile code for different architectures and processors The C and C libraries are provided as binaries only There is a variant of the 1990 ISO Standard C library for each combination of major build options such as the byte order of the target system whether interworking is selected and whether floating point support is selected See Chapter 2 The C and C Libraries in the Libraries Guide for more information 1 4 Copyright 2002 2007 ARM Limited All rights reserved ARM DUI 0205H Non Confidential Introduction 1 4 New features of C99 The 1999 C standard introduces a range of new features into C including New language features including new keywords and identifiers together with extended syntax for the existing C90 language New library features including new libraries and new macros and functions for existing C90 libraries A selection of new features in C99 that are of interest to developers using them for the first time are discussed in the following sections Note C90 is compatible with Standard C in the sense that the language specified by the standa
140. p counter needs to be updated less often and fewer branches are executed If the loop iterates only a few times it can be fully unrolled so that the loop overhead completely disappears The ARM compiler unrolls loops automatically at 03 Otime Otherwise any unrolling must be done in source code Note Manual unrolling of loops might hinder the automatic re rolling of loops and other loop optimizations by the compiler The advantages and disadvantages of loop unrolling can be illustrated using the two sample routines shown in Table 4 3 Both routines efficiently test a single bit by extracting the lowest bit and counting it after which the bit is shifted out The first implementation uses a loop to count bits The second routine is the first unrolled four times with an optimization applied by combining the four shifts of n into one Unrolling frequently provides new opportunities for optimization Table 4 3 C code for rolled and unrolled bit counting loops Bit counting loop Unrolled bit counting loop int countbit1l unsigned int n int countbit2 unsigned int n int bits Q int bits Q while n Q while n Q if n amp 1 bits if n amp 1 bits n gt gt 1 if n amp 2 bits if n amp 4 bits if n amp 8 bits return bits n gt gt 4 return bits Copyright 2002 2007 ARM Limited All rights reserved ARM DUI 0205H Non Confidential Coding Practices Tab
141. page 4 73 in the Compiler Reference Guide _ fabsf on page 4 74 in the Compiler Reference Guide __gadd on page 4 80 in the Compiler Reference Guide ___qdbl on page 4 81 in the Compiler Reference Guide __qsub on page 4 81 in the Compiler Reference Guide sqrt on page 4 87 in the Compiler Reference Guide __sqrtf on page 4 88 in the Compiler Reference Guide These intrinsics introduce the appropriate target instructions for e ARM architectures from ARM v5TE onwards Thumb 2 architectures except M variants For example the ARMSTE QDADD instruction is realized by a combination of __qadd and __qdb1 3 1 3 ETSI basic operations The European Telecommunications Standard Institute ETSI has produced several recommendations for the coding of speech for example the G 723 1 and G 729 recommendations These recommendations include source code and test sequences for reference implementations of the codecs Model implementations of speech codecs supplied by the ETSI are based on a collection of C functions known as the ETSI basic operations The ETSI basic operations include 16 bit 32 bit and 40 bit operations for saturated arithmetic 16 bit and 32 bit logical operations and 16 bit and 32 bit operations for data type conversion Note Version 2 0 of the ETSI collection of basic operations as described in the ITU T Software Tool Library 2005 User s manual introduces new 16 bit 32 bit and 40 bit operations These operati
142. pecifies the format for the compiler output You can use these options to generate object files assembly language output listing files and make file dependency files 2 4 Copyright 2002 2007 ARM Limited All rights reserved Non Confidential asm on page 2 8 c on page 2 12 default_extension ext on page 2 22 depend filename on page 2 23 ARM DUI 0205H Getting started with the ARM Compiler depend_format string on page 2 24 no_ depend_system_headers on page 2 25 info totals on page 2 48 interleave on page 2 50 e list on page 2 55 e md on page 2 60 o filename on page 2 65 e S on page 2 80 split_sections on page 2 83 target options Specifies the target processor or architecture and the target instruction set in use at startup arm on page 2 7 cpu list on page 2 15 cpu name on page 2 15 fpu list on page 2 41 fpu name on page 2 42 thumb on page 2 86 See Specifying the target processor or architecture on page 2 22 for more information debug options Controls the format and generation of debug tables no_ debug on page 2 21 no_ debug_macros on page 2 21 s dwarf2 on page 2 33 dwarf3 on page 2 33 code generation options Specifies the code generation options for the ARM compiler including endianness symbol visibility and alignment criteria no_ alternative_tokens on page 2 3 bigend on page 2 10 bss_th
143. pile either for C or for C regardless of file extension For example armcc c cpp testl c test2 cpp Where an unrecognized extension begins with c for example fi lename cmd a warning is given Support for processing PreCompiled Header PCH files is not available when you specify multiple source files in a single compilation If you request PCH processing and specify more than one primary source file the compiler issues an error message and aborts the compilation See Precompiled header files on page 2 16 for more information 2 8 Copyright 2002 2007 ARM Limited All rights reserved ARM DUI 0205H Non Confidential Getting started with the ARM Compiler 2 1 2 Ordering command line options In general command line options can appear in any order in a single compiler invocation However the effects of some options depend on the order they appear in the command line and how they are combined with other related options for example optimization options prefixed by 0 or PCH options See Precompiled header files on page 2 16 The compiler enables you to use multiple options even where these might conflict This means that you can append new options to an existing command line for example in a make file or via file Where options override previous options on the same command line the last one found always takes precedence For example armcc 01 02 Ospace Otime is executed by the compiler as armcc 02 Otime
144. ple the PCH file includes the processing state for xxx h and yyy h but not for zzz h This is useful if you decide that the information following the pragma hdrstop does not justify the creation of another PCH file Use the pragma no_pch directive to suppress PCH processing for a source file Note You can use these pragmas even if you are using automatic PCH processing See Pragmas on page 3 13 for more information Controlling the output of messages during PCH processing When the compiler creates or uses a PCH file it displays the following message test c creating precompiled header file test pch You can suppress this message by using the command line option no_pch_messages When you use the pch_verbose option the compiler displays a message for each PCH file that is considered but cannot be used giving the reason why it cannot be used Performance issues Typically the overhead of creating and reading a PCH file is small even for reasonably large header files and even if the created PCH file is not used If the file is used there is typically a significant decrease in compilation time However PCH files can range in size from about 250KB to several megabytes or more so you might not want to create many PCH files PCH processing might not always be appropriate for example where you have an arbitrary set of files with non uniform initial sequences of preprocessing directives The benefits of PCH processin
145. pplier with the information listed in Feedback on RealView Compilation Tools on page xiii Error Errors indicate problems that cause the compilation to stop These errors include command line errors internal errors missing include files and violations in the syntactic or semantic rules of the C or C language If multiple source files are specified then no further source files are compiled Warning Warnings indicate unusual conditions in your code that might indicate a problem Compilation continues and object code is generated unless any further problems with an Error severity are detected Remark Remarks indicate common but sometimes unconventional use of C or C These diagnostics are not displayed by default Compilation continues and object code is generated unless any further problems with an Error severity are detected Copyright 2002 2007 ARM Limited All rights reserved 5 3 Non Confidential Diagnostic Messages 5 3 Controlling the output of diagnostic messages These options enable you to control the output of diagnostic messages no_ brief_ diagnostics Enables or disables a mode where a shorter form of the diagnostic output is used When enabled the original source line is not displayed and the error message text is not wrapped when it is too long to fit on a single line The default is no_brief_diagnostics diag_style arm ide gnu Specifies the style used to display diagn
146. programmer which fields of the struct are non aligned The differences between not packing a struct packing an entire struct and packing individual fields of a struct are illustrated by the three implementations of a struct shown in Table 4 9 In the first implementation the struct is not packed In the second implementation the entire structure mystruct is qualified as __packed In the third implementation the __packed attribute is removed from the mystruct structure and individual non aligned fields are declared as __packed Table 4 9 C code for an unpacked struct a packed struct and a struct with individually packed fields Unpacked struct __packed struct __ packed fields struct foo __packed struct foo struct foo char one char one char one short two short two __packed short two char three char three char three int four int four int four c c bc Table 4 10 on page 4 28 shows the corresponding disassembly of the machine code produced by the compiler for each of the sample implementations of Table 4 9 where the C code for each implementation has been compiled using the option 02 Note The Ospace and O0time compiler options control whether accesses to unaligned elements are made inline or through a function call Using Otime results in inline unaligned accesses while using Ospace results in unaligned accesses made through function calls ARM DUI 0205H Copyright 2002 2007 ARM Limited All
147. ptions to the equivalent options in the latest release of the compiler Table A 4 Mapping of RVCT 2 2 compiler options RVCT 2 2 compiler Equivalent RVCT Usage notes option compiler option apcs no swstackcheck None memaccess UL41 no_unaligned_access A 3 2 Mapping RVCT 3 0 compiler options to the new release Table A 5 on page A 10 describes options used by the ARM compiler in RVCT 3 0 and the equivalent compiler options in the current release of RVCT All the old compiler options listed in Table A 5 on page A 10 are obsolete in the latest release of RVCT and no longer supported ARM DUI 0205H Copyright 2002 2007 ARM Limited All rights reserved A 9 Non Confidential Using Old Command line Options If you are upgrading from RVCT 3 0 use Table A 5 to identify options that are no longer supported in the RVCT compiler and to find new names for these flags in the latest release You must migrate any use of old compiler options to the equivalent options in the latest release of the compiler Table A 5 Mapping of RVCT 3 0 compiler options Equivalent compiler option Usage notes Old compiler option apcs adsabi None Support for the ADS ABI is obsolete in the latest release of RVCT Your code might require small modifications to be compatible with the new ABI A 10 Copyright 2002 2007 ARM Limited All rights reserved ARM DUI 0205H Non Confidential Using Old Command line Opti
148. r Reference Guide 4 20 Copyright 2002 2007 ARM Limited All rights reserved ARM DUI 0205H Non Confidential Coding Practices 44 4 inlining functions across multiple files The __inline keyword in C has the semantics of the standard C keyword inline According to the C standard an inline function is required to be identically defined in each translation unit in which it is used Therefore only objects with internal linkage can be inlined It is not possible to link to an inline function in another file In particular extern functions are not inlined Because __inline has C semantics declaring a function as __inline means that it cannot be called from another compilation unit Therefore a function declared extern __inline might not behave as you expect To make a function available for inlining across multiple files you must place the function in a common header file for example foo h mark the function as extern __inline include the header file in each file where the inline function is needed If the compiler decides not to inline the function in one or more cases the function is compiled so that only one copy of it remains after linking Functions declared as __inline that are only called locally within a translation unit must never be placed in a header file These functions cannot be shared so multiple copies might exist after linking Marking an inline function local to a compilation unit as static __inli
149. r all developers who are producing applications using RVCT It assumes that you are an experienced software developer See the Real View Compilation Tools Essentials Guide for an overview of the ARM development tools provided with RVCT This book is organized into the following chapters and appendixes Chapter 1 Introduction Read this chapter for an overview of the ARM compiler the conformance standards and the C and C Libraries Chapter 2 Getting started with the ARM Compiler Read this chapter for an overview of the command line options and compiler specific features It describes how to invoke the compiler how to pass options to other RVCT tools and how to control diagnostic messages Chapter 3 Compiler Features Read this chapter for an overview of the intrinsics supported by the ARM compiler Chapter 4 Coding Practices Read this chapter for an overview of good programming practice in RVCT Chapter 5 Diagnostic Messages Read this chapter for an overview of the diagnostic messages produced by the RVCT tools Chapter 6 Using the Inline and Embedded Assemblers Read this chapter for a description of the inline and embedded assemblers provided by the ARM compiler Copyright 2002 2007 ARM Limited All rights reserved ARM DUI 0205H Non Confidential Preface Appendix A Using Old Command line Options Read this appendix for information on changes to compiler option names This appendix describes changes in this release and in p
150. rd is a subset of C except for a few special cases New features in the C99 standard mean that C99 is no longer compatible with C in this sense 1 4 1 Language features ARM DUI 0205H The C99 standard introduces several new language features of interest to programmers including Some features similar to extensions to C90 offered in the GNU compiler for example macros with a variable number of arguments Note The implementations of extensions to C90 in the GNU compiler are not always compatible with the implementations of similar features in C99 Some features available in C such as comments and the ability to mix declarations and code Some entirely new features for example restricted pointers and designated initializers A selection of new language features of C99 that might be of particular interest are discussed in the following sections comments You can use to indicate the start of a one line comment just as in C See comments on page 3 5 in the Compiler Reference Guide for more information Copyright 2002 2007 ARM Limited All rights reserved 1 5 Non Confidential Introduction 1 6 Compound literals ISO C99 supports compound literals compound literal looks like a cast followed by an initializer Its value is an object of the type specified in the cast containing the elements specified in the initializer It is an lvalue For example I int y int 1 2
151. release of RVCT and no longer supported If you are upgrading from ADS v1 2 use Table A 3 and Table A 2 on page A 3 to identify options that are no longer supported in the RVCT compiler and to find new names for these flags in the latest release You must migrate any use of old compiler options to the equivalent options in the latest release of the compiler Table A 3 Controlling ADS 1 2 diagnostic messages Old ADS compiler Old ADS compiler Equivalent RVCT z Usage notes option behavior compiler option Ea Downgrades access control None errors to warnings in C Ec Suppresses C3029E None Ef Suppresses errors for None unclean casts Ei Suppresses C225W diag_suppress 260 Use of implicit ints in constructs E Suppresses C2991E None Ep Suppresses errors arising None from extra characters Ez Suppresses C3017E None A 6 Copyright 2002 2007 ARM Limited All rights reserved ARM DUI 0205H Non Confidential Using Old Command line Options Table A 3 Controlling ADS 1 2 diagnostic messages continued Old ADS compiler option Old ADS compiler behavior Equivalent RVCT compiler option Usage notes Wa Suppresses C2916W diag_suppress 187 Use of the assignment operator in a condition context Wb Suppresses C2901E diag_suppress 66 230 Extensions to the ANSI Suppresses C2485W Standard Wd Suppresses C2215W di
152. reshold num on page 2 11 no_ dllexport_all on page 2 31 no_ dllimport_runtime on page 2 32 no_ dollar on page 2 32 enum_is_int on page 2 34 no_ exceptions on page 2 35 ARM DUI 0205H Copyright 2002 2007 ARM Limited All rights reserved 2 5 Non Confidential Getting started with the ARM Compiler optimization options no_Jexceptions_unwind on page 2 35 no_ export_all_vtbl on page 2 35 no_Jexport_defs_implicitly on page 2 36 no_ extended_initializers on page 2 36 no_ hide_all on page 2 46 littleend on page 2 57 loose_implicit_cast on page 2 58 locale lang_country on page 2 57 message_locale lang_country codepage on page 2 61 min_array_alignment opt on page 2 62 no_ multibyte_chars on page 2 62 no_Jrestrict on page 2 79 pointer_alignment num on page 2 73 un signed_bitfields on page 2 80 un signed_chars on page 2 81 split_ldm on page 2 82 no_Junaligned_access on page 2 88 no_ vla on page 2 93 no_ vectorize on page 2 91 wchar16 on page 2 94 wchar32 on page 2 94 Controls the level and type of code optimization no_Jautoinline on page 2 9 no_ data_reorder on page 2 20 forceinline on page 2 39 fpmode model on page 2 39 no_Jinline on page 2 49 library_interface lib on page 2 53 library_type lib on page 2 54 no_ Jlower_ropi on page 2 59 no_ Jlower_rwpi on page 2 59 no_ multifile on page 2 63 Onum on page 2 66 Ospace
153. revious releases of RVCT This book assumes that the ARM software is installed in the default location For example on Windows this might be volume Program Files ARM This is assumed to be the location of install_directory when referring to path names for example install_directory Documentation You might have to change this if you have installed your ARM software in a different location Typographical conventions Further reading ARM DUI 0205H The following typographical conventions are used in this book monospace Denotes text that can be entered at the keyboard such as commands file and program names and source code monospace Denotes a permitted abbreviation for a command or option The underlined text can be entered instead of the full command or option name monospace italic Denotes arguments to commands and functions where the argument is to be replaced by a specific value monospace bold Denotes language keywords when used outside example code italic Highlights important notes introduces special terminology denotes internal cross references and citations bold Highlights interface elements such as menu names Also used for emphasis in descriptive lists where appropriate and for ARM processor signal names This section lists publications from both ARM Limited and third parties that provide additional information on developing code for the ARM family of processors ARM Limited periodically provides up
154. rights reserved 4 27 Non Confidential Coding Practices 4 28 Table 4 10 Disassembly for an unpacked struct a packed struct and a struct with individually packed fields Unpacked struct __ packed struct __ packed fields r contains address of c rQ contains address of c r0 contains address of c LDRB ri r0 0 char one char one LDRSH r2 r0 2 LDRB ri rQ 0 LDRB ri rQ 0 LDRB r3 r0 4 LDR r12 r0 8 short two short two LDRB r2 rQ 1 LDRB r2 r 1 LDRSB r12 r 2 LDRSB r12 r 2 ORR r2 r12 r2 LSL 8 ORR r2 r12 r2 LSL 8 char three char three LDRB r3 rQ 3 LDRB r3 rQ 3 int four int four ADD r0 rO 4 LDR r12 r0 4 BL __aeabi_uread4 In the disassembly of the unpacked struct in Table 4 10 the compiler always accesses data on aligned word or halfword addresses The compiler is able to do this because the struct is padded so that every member of the struct lies on its natural size boundary In the disassembly of the __packed struct in Table 4 10 the fields one and three are aligned on their natural size boundaries by default and so the compiler makes aligned accesses The compiler always carries out aligned word or halfword accesses for fields it can identify are aligned For the unaligned field two the compiler uses multiple aligned memory accesses LDR STR LDM STM combined with fixed shifting and masking to access the correct bytes in memory The co
155. s versus individually __packed fields on page 4 26 for more information Note The same principles apply to unions You can declare either an entire union as __packed or use the __packed attribute to identify components of the union that are unaligned in memory Copyright 2002 2007 ARM Limited All rights reserved 4 25 Non Confidential Coding Practices Reading from and writing to structures qualified with __packed requires unaligned accesses and can therefore incur a performance penalty See __packed structures versus individually __packed fields for more information Unaligned pointers By default the ARM compiler expects conventional C pointers to point to an aligned word in memory as this enables the compiler to generate more efficient code If you wish to define a pointer that can point to a word at any address then you must specify this using the __packed qualifier when defining the pointer For example __packed int pi pointer to unaligned int When a pointer is declared as __packed the ARM compiler generates code that correctly accesses the dereferenced value of the pointer regardless of its alignment The generated code consists of a sequence of byte accesses or variable alignment dependent shifting and masking instructions rather than a simple LDR instruction Consequently declaring a pointer as __packed incurs a performance and code size penalty Unaligned LDR instructions for accessing halfwords
156. sions in embedded assembly and C or C on page 6 19 ARM DUI 0205H Non Confidential Copyright 2002 2007 ARM Limited All rights reserved 6 29 Using the Inline and Embedded Assemblers 6 30 Copyright 2002 2007 ARM Limited All rights reserved ARM DUI 0205H Non Confidential Appendix A Using Old Command line Options This appendix describes command line options that have changed between previous releases of RealView Compilation Tools RVCT This appendix contains the following sections Invoking the ARM compiler using older tool names on page A 2 Migrating command line options from ADS 1 2 on page A 3 Migrating command line options from RVCT 2 2 and RVCT 3 0 on page A 9 Warning messages for old options in RVCT on page A 11 Getting more information on page A 12 ARM DUI 0205H Copyright 2002 2007 ARM Limited All rights reserved A 1 Non Confidential Using Old Command line Options A 1 Invoking the ARM compiler using older tool names For backwards compatibility you can still invoke the ARM compiler using one of the tool names supported in earlier compilation tools The startup configuration associated with each of the older tool names is shown in Table A 1 Table A 1 Startup configuration based on old tool names Tool Instruction Source name set language armcc ARM C tcc Thumb C armcpp ARM C tcpp Thumb C If you use tcc the compiler generates Thumb code for c and
157. sm asm fs asm interleave auto_float_constants fpmode std fpmode std is the default bigend bigend cpu name cpu name CPP cpp E depend filename depend fi ename ARM DUI 0205H d11_vtbl export_all_vtbl dwarf2 dwarf2 Ec loose_implicit_cast Copyright 2002 2007 ARM Limited All rights reserved Non Confidential Using Old Command line Options Table A 2 Mapping of ADS 1 2 compiler options continued ADS compiler option Equivalent RVCT compiler option Usage notes embeddedcplusplus None fa None Data flow analysis feature on by default since RVCT 2T fd sys_include fh None fi None fj None fk kandr_include fp None fpu name fpu name fs interleave fu None fv None fx remarks or strict_warnings fy enum_is_int 2 g no_debug g debug z g gtp no_debug_macros E gt p gt p debug_macros jdir_list Jdir_list list list Option behavior has no_depend_system_headers changed A 4 Copyright 2002 2007 ARM Limited All rights reserved ARM DUI 0205H Non Confidential Using Old Command line Options Table A 2 Mapping of ADS 1 2 compiler options continued ADS compiler option Equivalent RVCT compiler option Usage notes list fi fj list Option behavior has depend_system_he
158. st integer double tgamma double x returns the gamma function of x C99 supports the new mathematical functions for all real floating point types Single precision versions of all existing lt math h gt functions are also supported Boolean type and lt stdbool h gt C99 introduces the native type _Bool The associated standard header lt stdboo1 h gt introduces the macros bool true and false for Boolean tests For example include lt stdbool h gt bool foo FILE str bool err false if 1fflush str err true return err Note The C99 semantics for bool are intended to match those of C ARM DUI 0205H Copyright 2002 2007 ARM Limited All rights reserved 1 11 Non Confidential Introduction Extended integer types and functions in lt inttypes h gt and lt stdint h gt In C90 the Tong data type can serve both as the largest integral type and as a 32 bit container C99 removes this ambiguity through the new standard library header files lt inttypes h gt and lt stdint h gt The header file lt stdint h gt introduces the new types intmax_t and uintmax_t which are maximum width signed and unsigned integer types intptr_t and unintptr_t which are integer types capable of holding signed and unsigned object pointers The header file lt inttypes h gt provides library functions for manipulating values of type intmax_t including intmax_t imaxabs intmax_t x absolute
159. te Due to the special naming of the area for out of line copies of inline functions and template functions these functions are not in the order of definition but in an arbitrary order Therefore you cannot assume that a code execution falls out of an inline or template function and into another __asm function 6 2 5 The__cpp keyword ARM DUI 0205H You can use the __cpp keyword to access C or C compile time constant expressions including the addresses of data or functions with external linkage from the assembly code The expression inside the __cpp must be a constant expression suitable for use as a C static initialization See 3 6 2 Initialization of non local objects and 5 19 Constant expressions in ISO IEC 14882 2003 Example 6 3 on page 6 22 shows a constant replacing the use of __cpp expr Copyright 2002 2007 ARM Limited All rights reserved 6 21 Non Confidential Using the Inline and Embedded Assemblers Example 6 3 __cpp expr LDR r __cpp amp some_variable LDR r1 __cpp some_ function BL __cpp some_ function MOV r __cpp some_constant_expr Names in the __cpp expression are looked up in the C context of the __asm function Any names in the result of a __cpp expression are mangled as required and automatically have IMPORT statements generated for them 6 2 6 Manual overload resolution Example 6 4 shows the use of C casts to do overload resolution for non virtual function calls Example 6
160. ted by the compiler using the command line option cpu list For more information see Specifying the target processor or architecture on page 2 22 cpu list on page 2 15 in the Compiler Reference Guide cpu name on page 2 15 in the Compiler Reference Guide 4 1 4 Optimizing loops Loops are a common construct in most programs Because a significant amount of execution time is often spent in loops it is worthwhile paying attention to time critical loops Loop termination The loop termination condition can cause significant overhead if written without caution Where possible e always write count down to zero loops and use simple termination conditions e always use a counter of type unsigned int and test for not equal to zero 4 4 Copyright 2002 2007 ARM Limited All rights reserved ARM DUI 0205H Non Confidential Coding Practices Table 4 1 shows two sample implementations of a routine to calculate n that together illustrate loop termination overhead The first implementation calculates n using an incrementing loop while the second routine calculates n using a decrementing loop Table 4 1 C code for incrementing and decrementing loops Incrementing loop Decrementing loop int factl int n int fact2 int n int i fact 1 unsigned int i fact 1 for i 1 i lt n i for i n i 0 i fact i fact i return fact return fact Table 4 2 shows the corresponding disassem
161. th kandr_include No effect Uses Kernighan and Ritchie search rules In Table 2 2 RVCT31INCdirs List of directories specified by the RVCT31INC environment variable if set cP The current place Idirs and Jdirs Directories specified by the Idirs and Jdirs compiler options 2 34 The TMP and TMPDIR environment variables On Windows platforms the environment variable TMP is used to specify the directory to be used for temporary files 2 14 Copyright 2002 2007 ARM Limited All rights reserved ARM DUI 0205H Non Confidential ARM DUI 0205H Getting started with the ARM Compiler On Red Hat Linux platforms the environment variable TMPDIR is used to specify the directory to be used for temporary files If TMPDIR is not set a default temporary directory usually tmp or var tmp is used Copyright 2002 2007 ARM Limited All rights reserved 2 15 Non Confidential Getting started with the ARM Compiler 2 4 2 4 1 2 16 Precompiled header files When you compile your source files the included header files are also compiled If a header file is included in more than one source file it is recompiled when each source file is compiled Also you might include header files that introduce many lines of code but the primary source files that include them are relatively small Therefore it is often desirable to avoid recompiling a set of header files by precompiling them These are referred to as PreCompiled Header PCH files
162. the cos function as determined by the type of the literal 0 78539f Note Type generic families of mathematical functions can be defined in C using the operator overloading mechanism The semantics of type generic families of functions defined using operator overloading in C are different from the semantics of the corresponding families of type generic functions defined in lt tgmath h gt Copyright 2002 2007 ARM Limited All rights reserved 1 13 Non Confidential Introduction 1 14 Copyright 2002 2007 ARM Limited All rights reserved ARM DUI 0205H Non Confidential Chapter 2 Getting started with the ARM Compiler This chapter outlines the command line options accepted by the ARM compiler armcc It describes how to invoke the compiler how to pass options to other RVCT tools and how to control diagnostic messages It contains the following sections Using command line options on page 2 2 File naming conventions on page 2 11 Include files on page 2 13 Precompiled header files on page 2 16 Specifying the target processor or architecture on page 2 22 Specifying the procedure call standard AAPCS on page 2 23 Using linker feedback on page 2 25 Adding symbol versions on page 2 26 Thread local storage on page 2 27 Eight byte alignment features on page 2 28 See the Compiler Reference Guide for more information ARM DUI 0205H Copyright 2002 2007 ARM Limited All rights reserved
163. the index When a thread starts it allocates a block of dynamic memory and stores a TLS pointer to this memory In general TLS pointers point to a specific memory location returned by a library function This is a CP15 register on ARM MPCore Before each thread terminates it releases its dynamic memory and any pointers to thread local variables in that thread become invalid Before the process terminates it releases the index See __declspec thread on page 4 27 in the Compiler Reference Guide for more information Copyright 2002 2007 ARM Limited All rights reserved 2 27 Non Confidential Getting started with the ARM Compiler 2 10 2 28 Eight byte alignment features The ARM compiler has the following eight byte alignment features The Procedure Call Standard for the ARM Architecture AAPCS requires that the stack is eight byte aligned at all external interfaces The ARM compiler and C libraries preserve the eight byte alignment of the stack In addition the default C library memory model maintains eight byte alignment of the heap In RealView Compilation Tools RVCT v2 0 and above all code is compiled with the REQUIRE8 and PRESERVES directives If you have assembly files or legacy objects or libraries in your project it is your responsibility to check that they preserve eight byte stack alignment and correct them if required For more information see the Assembler Guide and the Linker Guide In RVCT v2 0 an
164. tions on position independent code and data on page 2 24 Writing reentrant and thread safe code on page 2 4 in the Libraries Guide Chapter 6 BPABI and System V Shared Libraries and Executables in the Linker Guide Copyright 2002 2007 ARM Limited All rights reserved 2 23 Non Confidential Getting started with the ARM Compiler Restrictions on position independent code and data There are restrictions when you compile code with ropi or rwpi or fpic The main restrictions are The use of apcs ropi is not supported when compiling C You can compile only the C subset of C with ropi Some constructs that are legal C do not work when compiled for apcs ropi or apcs rwpi for example int i rw int pl amp i this static initialization does not work with apcs rwpi no_lower_rwpi extern const int ci ro const int p2 amp ci this static initialization does not work with apcs ropi However to enable these static initializations to work use the 1ower_rwpi and lower_ropi options To compile this code type armcc apcs rwpi ropi lower_ropi You do not have to specify lower_rwpi because this is the default The use of apcs fpic is supported when compiling C Here virtual table functions and typeinfo are placed in read write areas so that they can be accessed relative to the location of the PC If you use apcs fpic the compiler exports only functions
165. to CP15 to drain the write buffer Refer to the Technical Reference Manual for your ARM processor for more information Intrinsics for inserting native instructions The following intrinsics enable you to insert ARM processor instructions into the instruction stream generated by the compiler __cdp on page 4 68 in the Compiler Reference Guide __clrex on page 4 69 in the Compiler Reference Guide __Idrex on page 4 75 in the Compiler Reference Guide e __Idrt on page 4 76 in the Compiler Reference Guide __pld on page 4 79 in the Compiler Reference Guide __pli on page 4 80 in the Compiler Reference Guide __rbit on page 4 82 in the Compiler Reference Guide __rev on page 4 82 in the Compiler Reference Guide __ror on page 4 84 in the Compiler Reference Guide sev on page 4 87 in the Compiler Reference Guide __strex on page 4 89 in the Compiler Reference Guide __strt on page 4 90 in the Compiler Reference Guide __swp on page 4 92 in the Compiler Reference Guide __wfe on page 4 94 in the Compiler Reference Guide __wfi on page 4 94 in the Compiler Reference Guide _ yield on page 4 95 in the Compiler Reference Guide Intrinsics for digital systems processing The following intrinsics assist in the implementation of DSP algorithms __clz on page 4 69 in the Compiler Reference Guide Copyright 2002 2007 ARM Limited All rights reserved 3 5 Non Confidential Compiler Features _ fabs on
166. tted then for BL and SWI the registers r r3 pc 1r and the PSR are corrupted The branch instruction B must only be used to jump to labels within a single C or C function Labels defined in inline assembly code can be used as targets for branches or C and C goto statements Labels defined in C and C can be used as targets by branch instructions in inline assembly code in the form BL cond label Copyright 2002 2007 ARM Limited All rights reserved ARM DUI 0205H Non Confidential Using the Inline and Embedded Assemblers 6 1 10 Differences from previous versions of the ARM C C compilers ARM DUI 0205H There are significant differences between the inline assembler in the ARM compiler and the inline assembler in previous versions of the ARM C and C compilers This section highlights the main differences For more information on using existing assembly code for the inline assembler see the RealView Compilation Tools Developer Guide ARMV6 instructions Of all the ARMv6 instructions the inline assembler supports the ARMv6 media instructions only Virtual registers Inline assembly code for the compiler always specifies virtual registers The compiler chooses the physical registers to be used for each instruction during code generation and enables the compiler to optimize fully the assembly code and surrounding C or C code The pc r15 1r r14 and sp r13 registers cannot be accessed at all An error messag
167. used out of line functions are placed into their own sections using linker feedback If you fail to declare functions that are never called from outside a module as static your code can be adversely affected In particular you might have A larger code size because out of line versions of functions are retained in the image When a function is inlined both the in line version and an out of line version of the function might end up in the final image unless the function is declared as static This might possibly increase code size An unnecessarily complicated debug view because there are both inline versions and out of line versions of functions to display Retaining both inline and out of line copies of a function in code can sometimes be confusing when setting breakpoints or single stepping in a debug view The debugger has to display both in line and out of line versions in its interleaved source view so that you can see what is happening when stepping through either the in line or out of line version Because of these problems declare functions as static when you are sure that they can never be called from another module 4 4 7 Setting breakpoints on inlined functions in ROM images 4 22 When you set a breakpoint on an inline function the RealView Debugger attempts to set a breakpoint on each inlined instance of the function If you are using Real View ICE to debug an image in ROM and the number of inline instances is
168. w is needed Selecting 00 typically increases the size of the ELF image by 7 15 To reduce the size of your debug tables use the no_debug_macros option For more information see no_ debug on page 2 21 in the Compiler Reference Guide no_ debug_macros on page 2 21 in the Compiler Reference Guide dwarf2 on page 2 33 in the Compiler Reference Guide dwarf3 on page 2 33 in the Compiler Reference Guide Onum on page 2 66 in the Compiler Reference Guide 41 3 Selecting the target CPU ARM DUI 0205H Each new version of the ARM architecture typically supports extra instructions and modes of operation Where a compiled program is to run on a specific ARM architecture based processor it is best to select the target processor using the cpu command line option This enables the compiler to make full use of instructions that are supported by the processor and also to perform processor specific optimizations such as instruction scheduling Copyright 2002 2007 ARM Limited All rights reserved 4 3 Non Confidential Coding Practices Where a compiled program is to run on different ARM processors you must choose the lowest common denominator architecture appropriate for your application using the cpu command line option For example to compile code for processors supporting the ARM v6 architecture use the command line option cpu 6 Note You can list all the processors and architectures suppor
169. wing sections No lists specified on page 6 13 Input parameter list on page 6 13 Copyright 2002 2007 ARM Limited All rights reserved ARM DUI 0205H Non Confidential ARM DUI 0205H Using the Inline and Embedded Assemblers Output value list on page 6 14 Corrupted register list on page 6 14 Note The BX BLX and BXJ instructions are not supported in the inline assembler It is not possible to specify the 1r sp or pc registers in any of the input output or corrupted register lists The sp register must not be changed by any SWI instruction or function call No lists specified If you do not specify any lists then r0 r3 are used as input parameters rQ is used for the output value r12 and r14 are corrupted Input parameter list This list specifies the expressions or variables that are the input parameters to the function call or SWI instruction and the physical registers that contain the expressions or variables They are specified as assignments to physical registers or as physical register names A single list can contain both types of input register specification The inline assembler ensures that the correct values are present in the specified physical registers before the BL or SWI instruction is entered A physical register name that is specified without assignment ensures that the value in the virtual register of the same name is present in the physical register This ensures ba
170. with the exception of the following identifiers see Keywords for related base classes on page 6 22 and Keywords for member function classes on page 6 23 _ cpp expr __offsetof_base D B __mcall_is_virtual D f __mcall_is_in_vbase D f __mcall_offsetof_base D f __mcall_this_offset D f __vcall_offsetof_vfunc D f No return instructions are generated by the compiler for an __asm function If you want to return from an __asm function then you must include the return instructions in assembly code in the body of the function Note This makes it possible to fall through to the next function because the embedded assembler guarantees to emit the __asm functions in the order you have defined them However inlined and template functions behave differently see Generation of embedded assembly functions on page 6 20 __asm functions do not change the AAPCS rules that apply This means that all calls between an __asm function and a normal C or C function must adhere to the AAPCS even though there are no restrictions on the assembly code that an __asm function can use for example change state 6 2 3 Differences between expressions in embedded assembly and C or C ARM DUI 0205H Be aware of the following differences between embedded assembly and C or C Assembler expressions are always unsigned The same expression might have different values between assembler and C or C For example MOV rO 33554432 2
171. you to save and restore the pragma state pragma pop on page 4 58 pragma push on page 4 58 Pragmas controlling multiple optimizations These pragmas enable you to assign multiple optimizations on individual functions The pragmas must be placed outside of a function and you cannot apply more than one of these optimizations on a function The following pragmas control these optimizations pragma Onum on page 4 57 e pragma Ospace on page 4 58 pragma Otime on page 4 58 Pragmas controlling code generation The following pragmas control how code is generated pragma arm on page 4 50 pragma thumb on page 4 62 pragma no_ exceptions_unwind on page 4 55 e pragma once on page 4 57 pragma no_ softfp_linkage on page 4 59 pragma import symbol_name on page 4 56 pragma arm section section_sort_list on page 4 50 Pragmas controlling PreCompiled Header PCH processing The following pragmas control PCH processing pragma hdrstop on page 4 55 pragma no_pch on page 4 57 ARM DUI 0205H Copyright 2002 2007 ARM Limited All rights reserved 3 13 Non Confidential Compiler Features Pragmas controlling anonymous structures and unions The following pragma controls the use of anonymous structures and unions pragma no_Janon_unions on page 4 49 Pragmas controlling diagnostic messages The following pragmas control the output of the diagnostic messages that have a D postfix in th
172. ypically the header stop point is the first token in the primary source file that does not belong to a preprocessing directive In the following example the header stop point is int and the PCH file contains a snapshot that reflects the inclusion of xxx h and yyy h Copyright 2002 2007 ARM Limited All rights reserved ARM DUI 0205H Non Confidential ARM DUI 0205H Getting started with the ARM Compiler include xxx h include yyy h int i Note You can manually specify the header stop point with pragma hdrstop You must place this before the first token that does not belong to a preprocessing directive In this example place it before int See Controlling PCH processing on page 2 19 for more information Conditions that affect PCH file generation If the first non preprocessor token or a pragma hdrstop appears within a if block the header stop point is the outermost enclosing if For example include xxx h ifndef YYY_H define YYY_H 1 include yyy h endif if TEST int i endif In this example the first token that does not belong to a preprocessing directive is int but the header stop point is the start of the if block containing it The PCH file reflects the inclusion of xxx h and conditionally the definition of YYY_H and inclusion of yyy h It does not contain the state produced by if TEST A PCH file is produced only if the header stop point and the code preceding it mainly the

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