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MCF5282 User`s Manual Errata

1. Low analog reference l Debug and JTAG Test Port Control R9 JTAG_EN JTAG Enable P9 DSCLK TRST Debug clock TAP reset l Yes T9 TCLK TAP clock l Yes P10 BKPT TMS Breakpoint TAP test mode l Yes select R10 DSI TDI Debug data in TAP data in l Yes T10 DSO TDO Debug data out TAP data out O C12 D12 A13 B13 DDATAJ3 0 PDD 7 4 Debug data VO C13 A14 B14 A15 PST 3 0 PDD 3 0 Processor status data VO Test N10 TEST Test mode pin l Power Supplies R5 VDDA Analog positive supply l P5 T1 VSSA Analog ground l P2 VDDH ESD positive supply l N8 VDDPLL PLL positive supply l P8 VSSPLL PLL ground l A6 C11 VPP Flash stress programming l voltage A12 C5 D5 D11 VDDF Flash positive supply l B5 B12 VSSF Flash module ground l N11 VSTBY Standby power l MCF5282 User s Manual Errata Rev 13 14 Freescale Semiconductor Revision History Table 14 3 MCF5282 Signals and Pin Numbers Sorted by Function continued MAPBGA Pin Pin Functions Primary Secondary Tertiary Description Primary Internal O Pull up E6 E11 F5 F7 F10 F12 G5 G6 G11 G12 H5 H6 H11 H12 J5 J6 J11 J12 K5 K6 K11 K12 L5 L7 L10 L12 M6 M11 VDD Positive supply A1 A16 E5 E12 F6 F11 G7 G10 H7 H10 J7 J10 K7 K10 L6
2. Data bus VO M1 M2 M3 M4 N1 N2 N3 P1 D 7 0 PD 7 0 Data bus VO N5 T6 R6 P6 P14 T15 R15 R16 BS 3 0 PJ 7 4 Byte strobe VO Yes N16 OE PE7 Output enable VO P16 TA PE6 Transfer acknowledge VO Yes P15 TEA PES Transfer error acknowledge VO Yes N15 R W PE4 Read write VO Yes N14 SIZ1 PE3 SYNCA Transfer size VO Yes MCF5282 User s Manual Errata Rev 13 10 Freescale Semiconductor Table 14 3 MCF5282 Signals and Pin Numbers Sorted by Function continued Errata for Revision 1 0 Pin Functions ve Primary Internal MAPBGA Pin Description Pull up Primary Secondary Tertiary 2 M16 SIZO PE2 SYNCB Transfer size VO Yes M15 TS PE1 SYNCA _ Transfer start VO Yes M14 TIP PEO SYNCB Transfer in progress VO Yes Chip Selects L16 L15 L14 L13 CS 3 0 PJ 3 0 Chip selects 3 0 VO Yes C6 B6 A5 A 23 21 PF 7 5 CS 6 4 Chip selects 6 4 O Yes SDRAM Controller H15 SRAS PSD5 SDRAM row address strobe VO H16 SCAS PSD4 SDRAM column I O address strobe G15 DRAMW PSD3 SDRAM write enable 0 H13 G16 SDRAM_CS 1 0 PSD 2 1 SDRAM chip selects VO H14 SCKE PSDO SDRAM clock enable VO External Interrupts Port B15 B16 C14 C15 IRQ 7 1 PNQ 7 1 External interrupt request VO C16 D14 D15 Ethernet C10 EMDIO PAS5 URXD2 M
3. For Literature Requests Only Freescale Semiconductor Literature Distribution Center P O Box 5405 Denver Colorado 80217 1 800 441 2447 or 303 675 2140 Fax 303 675 2150 LDCForFreescaleSemiconductor hibbertgroup com Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document Freescale Semiconductor reserves the right to make changes without further notice to any products herein Freescale Semiconductor makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters that may be provided in Freescale Semiconductor data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts Freescale Semiconductor does not convey any license under its patent rights nor the rights of others Freescale Semiconduct
4. to IPSBAR 0x1188 Figure 23 18 Page 23 18 Remove the two 16 bit divider blocks from timer input as the divider is not available using external clock sources Section 23 5 1 2 2 Page 23 19 Remove 16 bit divider from equation as the divider is not available using external clock sources Section 25 5 8 Page 25 25 Change end of last sentence from and can be written by the host to 0 to and can be written by the host to 1 Table 25 17 Page 25 29 Remove the following information from the BITERR and ACKERR descriptions as these fields are read only To clear this bit first read it as a one then write it as a one Writing zero has no effect This is a rescindment of a previous documentation errata Change last sentence in ERRINT description from To clear this bit first read it as a one then write as a zero Writing a one has no effect to To clear this bit first read it as a one then write a one Writing a zero has no effect Add the following information to the BOFFINT and WAKEINT descriptions To clear this bit first read it as a one then write it as a one Writing zero has no effect MCF5282 User s Manual Errata Rev 13 Freescale Semiconductor Errata for Revision 2 3 Table 1 MCF5282UM Rev 2 3 Errata continued Location Description Table 25 17 Page 25 27 Definition of bits ERRINT and BOFFINT are incorrect for register ES
5. 66MHz 80MHz PLL Reference Frequency Range MHz Crystal reference fref_crystal 2 8 33 10 0 External reference fref ext 2 8 33 10 0 1 1 Mode fret 1 1 33 33 66 66 80 System Frequency fsys fsystmax fsys max MHz External Clock Mode 0 66 66 On Chip PLL Frequency fret 32 66 66 80 3 Errata for Revision 2 0 Table 3 MCF5282UM Rev 2 0 Errata Location Description Table 33 8 33 9 Reference to TA TL to TH was not deleted Delete 4 Errata for Revision 1 0 Table 4 MCF5282UM Rev 1 0 Errata Location Description 1 1 1 1 Change Real time debug support with two user visible hardware breakpoint registers To Real time debug support with one user visible hardware breakpoint register Table 2 2 2 7 Change the field description to read Interrupt level mask Defines the current interrupt level Interrupt requests are inhibited for all priority levels less than or equal to the current level except the edge sensitive level 7 request which cannot be masked MCF5282 User s Manual Errata Rev 13 Freescale Semiconductor 5 Errata for Revision 1 0 Table 4 MCF5282UM Rev 1 0 Errata continued Location Description Table 5 1 5 2 Replace the description of PRI1 and PRI2 with the following Description Priority bit PRI1 determines if DMA or CPU has priority in upper 32K bank of memory PRI2 determines if DMA or CPU has priority i
6. MCF5282UM Rev 1 0 Errata continued Location Description Table 17 13 17 26 Change encodings for bits 31 9 to OThe corresponding interrupt source is masked 1The corresponding interrupt source is not masked Chapter 19 Change PIT1 PIT4 to PITO PIT3 throughout chapter When a timer is referenced individually PIT1 should be PITO PIT2 should be PIT1 PIT3 should be PIT2 and PIT4 should be PIT3 Other chapters in the user s manual use the correct nomenclature PITO PIT3 19 6 3 19 7 Change timeout period equation to the equation below Timeout period PREIB O x PM 15 0 1 x 2 system clock Figure 23 11 Change UISR bits 5 3 to reserved bits 24 6 1 24 11 Change I2CR OxA to I2CR 0xA0 27 2 1 27 2 Change When interfacing to 16 bit ports the port C and D pins and PJ 7 6 BS 3 2 can be configured as general purpose input output I O To When interfacing to 16 bit ports the port C and D pins and PJ 5 4 BS 1 0 can be configured as general purpose input output I O 32 2 32 7 Added additional device number order information to Table 32 2 Table 32 2 Orderable Part Numbers Motorola Part Number Description Speed Temperature MCF5280CVF66 MCF5280 RISC Microprocessor 256 MAPBGA 66 67 MHz 40 to 85 C MCF5280CVF80 MCF5280 RISC Microprocessor 256 MAPBGA 80 MHz 40 to 85 C MCF5281CVF66 MCF5281 RISC Microprocessor 256 MAPBGA 66 67 MHz 40 to
7. VSS Ground L11 M5 M12 T16 NOTES Pull ups are not active when GPIO functions are selected for the pins default to GPIO inputs N On FR WwW Pull up is active only with the SYNCA function Pull up is active only with the SYNCB function Pull up is active only with the SDA function Pull up is active only with SCL function Pull up is active when JTAG_EN is driven high 5 Revision History Table 5 provides a revision history for this document Rev Number Table 5 Revision History Table Substantive Changes The primary functionality of a pin is not necessarily its default functionality Pins that have GPIO functionality will Date of Release Initial release 07 2003 Added page erase verify errata for Chapter 6 ColdFire Flash Module CFM 09 2003 Added errata for UART interrupt status register Added errata for PIT timer timeout equation Added I2CR write errata Added errata for Internal Pull Up column in MCF5282 Signals and Pin Numbers Sorted by Function table Added errata for SDRAM Read Cycle figure 11 2003 Added errata for Chapter 19 PIT1 PIT4 should be PITO PIT3 01 2004 Added errata for spurious interrupt Added errata for Table 33 8 Single instance of T T to Ty was overlooked in revision 2 0 of the manual This instance has now been removed Added errata for Section 25 4 10 change CANICR to ICRn Added er
8. should read frep X 2 MFD 2 oe fret x 2 MFD 2 lt f Where fsys max IS the maximum system frequency for the particular MCF5282 device 66MHz or 80MHz Tas sys sys max f sys sys max gt Include the following text in the section description and as a note in Figure 10 9 It is the responsibility of the software to program the ICRnx registers with unique and non overlapping level and priority definitions Failure to program the ICRnx registers in this manner can result in undefined behavior If a specific interrupt request is completely unused the ICRnx value can remain in its reset and disabled state Interrupt Force Register Low INTFRCLn is illustrated as read only in the figure However this register should be read write Change flag clearing mechanism for sources 24 26 They should read as follows Write ERR_INT 1 after reading ERR_INT 1 Write BOFF_INT 1 after reading BOFF_INT 1 Write WAKE_INT 1 after reading WAKE_INT 1 BAM bit field description the first example should read So if CSARO 0x0000 and CSMRO BAN 0x0001 instead of So if CSARO 0x0000 and CSMRO BAM 0x0008 NOP command entry Replace SRAS asserted with SDRAM_CS 1 0 asserted Chapter 17 The maximum buffer size of the FEC is 2032 bytes Replace any mention of the max size being 2047 bytes with 2032 bytes Figure 17 26 Page 17 41 Change EMRBR register address from IPSBAR 0x11B8
9. 32 bytes Replace any mention of the max size being 2047 bytes with 2032 bytes In PALR PAUR entry delete only needed for full duplex flow control Figure 17 23 17 39 Change FRSR to read write instead of read only 25 4 10 25 16 Change CANICR to ICRn Table 25 17 25 29 Add the following information to BITERR and ACKERR descriptions To clear this bit first read it as a one then write it as a one Writing zero has no effect Table 25 17 25 30 Table 25 19 25 32 Change bit ordering ERRINT should be bit 2 and BOFFINT should be bit 1 Change BUF nl field description from To clear an interrupt flag first read the flag as a one then write it as a zero to To clear an interrupt flag first read the flag as a one then write it as a one MCF5282 User s Manual Errata Rev 13 Freescale Semiconductor Errata for Revision 2 0 Table 2 MCF5282UM Rev 2 1 amp 2 2 Errata continued Location Description Chapter 33 It is crucial during power up that VDD never exceeds VDDH by more that 0 3V There are diode devices between the two voltage domains and violating this rule can lead to a latch up condition Table 33 8 33 7 In the PLL Electrical Specifications table only specs for the 80 MHz MCF5282 device were listed Insert specs for the 66MHz device in the first 2 rows and also declare symbol fsys max aS shown below Max Characteristic Symbol Min Unit
10. 6 80 On Chip PLL Frequency fret 32 66 66 80 Section 33 13 1 Page 33 21 Remove second sentence There is no minimum frequency requirement Section 33 13 2 Page 33 22 Remove second sentence There is no minimum frequency requirement Remove second paragraph as this feature is not supported on this device The transmit outputs ETXD 3 0 ETXEN ETXER can be programmed to transition from either the rising or falling edge of ETXCLK and the timing is the same in either case This options allows the use of non compliant MII PHYs Refer to the Ethernet chapter for details of this option and how to enable it Table A 3 Page A 4 The CSMR1 and CSCR1 register addresses are incorrect They should be IPSBAR 0x090 and IPSBAR 0x096 respectively MCF5282 User s Manual Errata Rev 13 Freescale Semiconductor 3 Errata for Revision 2 1 amp 2 2 2 Errata for Revision 2 1 amp 2 2 Table 2 MCF5282UM Rev 2 1 amp 2 2 Errata Location Figure 4 2 4 6 Table 4 6 4 9 Table 4 6 4 9 Figure 6 3 6 6 Table 6 10 6 15 Table 9 4 9 7 10 3 2 10 8 Description Changed bit 23 from DIDI to DISI Under Configuration for Instruction Cache the Operation entry changed to Invalidate 2 KByte data cache Under Configuration for Data Cache the Operation entry changed to Invalidate 2 KByte instruction cache Changed bit 8 t
11. 85 C MCF5281CVF80 MCF5281 RISC Microprocessor 256 MAPBGA 80 MHz 40 to 85 C MCF5282CVF66 MCF5282 RISC Microprocessor 256 MAPBGA 66 67 MHz 40 to 85 C MCF5282CVF80 MCF5282 RISC Microprocessor 256 MAPBGA 80 MHz 40 to 85 C Chapter 33 Delete references to TA TL to TH Table 33 1 33 1 The Digital Input Voltage Vin absolute maximum rating should be 0 3 to 6 0 V Table 33 6 33 8 The normal operation analog supply current Ippa maximum value has been changed to 5 0 mA MCF5282 User s Manual Errata Rev 13 8 Freescale Semiconductor Errata for Revision 1 0 Table 4 MCF5282UM Rev 1 0 Errata continued Location Description Figure 33 5 33 16 Replace Figure 33 5 SDRAM Read Cycle with the figure below Gn 2 a 9 10 11 12 13 ciKouT A 7 Nag Ne N Er A 23 0 x Row OK Column X _ Om F er h SCAS E gt DRAMW Fo D 31 0 SDRAM_CS 1 0 0s Ar BS 3 0 x ACTV NOP READ NOP PRE 1 DACRICASL 2 Figure 33 5 SDRAM Read Cycle Table 14 3 14 11 Change Internal Pull Up column to pull up indications in the table below 5 6 7 8 Table 14 3 MCF5282 Signals and Pin Numbers Sorted by Function Pin Functions Prima Internal MAPBGA Pin Description IO y Pull up Pri
12. Freescale Semiconductor MCF5282UMAD User s Manual Addendum Rev 13 08 2006 MCF5282 User s Manual Errata by Microcontroller Division This errata document describes corrections to the Table of Contents MCF5282 ColdFire Microcontroller User 5 Manual z EEPE PERELE ATT EE EPO F rrata for Revision 2 AS AER T PAE order number MCF5282UM For convenience the 3 Errata for Revision 20 5 addenda items are grouped by revision Please check our 4 Errata for Revision 1 0 5 website at http www freescale com for the latest 5 Revision Hilary anne 15 updates u P gt i i sr TM Freescale Semiconductor Inc 2006 All rights reserved os freesca le semiconductor Errata for Revision 2 3 1 Errata for Revision 2 3 Table 1 MCF5282UM Rev 2 3 Errata Location Description Table 5 1 Page 5 2 The PRI1 PRI2 text description does not match the table below it It should be If a bit is set CPU has priority If a bit is cleared DMA has priority Chapter 8 Table 9 4 Page 9 7 Section 10 3 6 Page 10 11 Figure 10 6 Page 10 9 Table 10 14 Page 10 15 Table 12 7 Page 12 7 Table 15 1 Page 15 3 Remove any references to the core watchdog timer being able to reset the device It is only able to interrupt the processor Use the peripheral watchdog timer described in Chapter 18 if needing a watchdog timer to reset the device In the table for MFD bit definition footnote 1 equation
13. TAT ERRINT should be bit 1 BOFFINT should be bit 2 They should be cleared by writing a one instead of a zero Table 26 1 Page 26 5 Change description field for DTOUT1 from DMA timer 1 output Port TD 3 to DMA timer 1 output Port TD 2 Change description field for DTINO from DMA timer 0 input Port TD 3 to DMA timer 1 output Port TD 1 Change description field for DTOUTO from DMA timer 0 output Port TD 3 to DMA timer 1 output Port TD 0 Chapter 33 Add the following note It is crucial during power up that VDD never exceeds VDDH by more that 0 3V There are diode devices between the two voltage domains and violating this rule can lead to a latch up condition Table 33 3 Page 33 3 In the Voy and Vo entries change the respective lop and Io specs from lop 2 0mA to lop 5 0mA and lo 2 0mA to Io 5 0mA Table 33 8 Page 33 7 In the PLL Electrical Specifications table only specs for the 80 MHz MCF5282 device were listed Insert specs for the 66MHz device in the first 2 rows and also declare symbol fsys max aS shown below Max Characteristic Symbol Min Unit 66MHz 80MHz PLL Reference Frequency Range MHz Crystal reference fref_crystal 2 8 33 10 0 External reference fref ext 2 8 33 10 0 1 1 Mode tat jet 33 33 66 66 80 System Frequency igs fsys max fsys max MHz External Clock Mode 0 66 6
14. UTXD1 PUA2 U1 transmit data VO N6 URXDO PUA1 UO receive data 1 0 T7 UTXDO PUAO UO transmit data VO EEE C10 EMDIO PAS5 URXD2 U2 receive data 1 0 B10 EMDC PAS4 UTXD2 U2 transmit data VO D16 CANRX PAS3 URXD2 U2 receive data VO E13 CANTX PAS2 UTXD2 U2 transmit data VO E14 SDA PAS1 URXD2 U2 receive data VO Yes E15 SCL PASO UTXD2 U2 transmit data VO Yes K16 DTIN3 PTC3 URTS1 U1 U0 Request to Send 1 0 URTSO K15 DTOUT3 PTC2 URTS1 U1 U0 Request to Send 1 0 URTSO K14 DTIN2 PTC1 UCTS1 U1 U0 Clear to Send 1 0 UCTSO K13 DTOUT2 PTCO UCTS1 U1 UO Clear to Send O UCTSO J16 DTIN1 PTD3 URTS1 U1 U0 Request to Send O _ URTSO MCF5282 User s Manual Errata Rev 13 12 Freescale Semiconductor Errata for Revision 1 0 Table 14 3 MCF5282 Signals and Pin Numbers Sorted by Function continued Pin Functions Prima Internal MAPBGA Pin Description 0 y Pull up Primary Secondary Tertiary 1 J15 DTOUT1 PTD2 URTS1 U1 U0 Request to Send VO URTSO J14 DTINO PTD1 UCTS1 U1 U0 Clear to Send VO UCTSO J13 DTOUTO PTDO UCTS1 U1 U0 Clear to Send VO UCTSO General Purpose Timers T13 R13 P13 N13 GPTA 3 0 PTA 3 0 Timer A IC OC PAI VO Yes T12 R12 P12 N12 GPTBI 3 0 PTB 3 0 Timer B IC OC PAI VO Yes N14 SIZ1 PE3 SYNCA Timer A synchronization input VO Yes M16 SI
15. ZO PE2 SYNCB Timer B synchronization input VO Yes M15 TS PE1 SYNCA Timer A synchronization input VO Yes M14 TIP PEO SYNCB Timer B synchronization input WO Yes DMA Timers K16 DTIN3 PTC3 URTS1 Timer 3 in VO URTSO K15 DTOUT3 PTC2 URTS1 Timer 3 out VO URTSO K14 DTIN2 PTC1 UCTS1 Timer 2 in VO UCTSO K13 DTOUT2 PTCO UCTS1 Timer 2 out VO UCTSO J16 DTIN1 PTD3 URTS1 Timer 1 in 1 0 URTSO J15 DTOUT1 PTD2 URTS1 Timer 1 out VO URTSO J14 DTINO PTD1 UCTS1 Timer 0 in 1 0 UCTSO J13 DTOUTO PTDO UCTS1 Timer 0 out VO UCTSO Queued Analog to Digital Converter QADC T3 ANO PQBO ANW Analog channel 0 VO R2 AN1 PQB1 ANX Analog channel 1 VO T2 AN2 PQB2 ANY Analog channel 2 VO R1 AN3 PQB3 ANZ Analog channel 3 VO MCF5282 User s Manual Errata Rev 13 Freescale Semiconductor 13 Errata for Revision 1 0 Table 14 3 MCF5282 Signals and Pin Numbers Sorted by Function continued Pin Functions u Primary Internal MAPBGA Pin Description Pull up Primary Secondary Tertiary 1O R4 AN52 PQAO MAO Analog channel 52 VO T4 AN53 PQA1 MA1 Analog channel 53 VO P3 AN55 PQA3 ETRIG1 Analog channel 55 VO R3 AN56 PQA4 ETRIG2 Analog channel 56 VO P4 VRH High analog reference l T5 VRL
16. anagement channel VO serial data B10 EMDC PAS4 UTXD2 Management channel clock VO A8 ETXCLK PEH7 MAC Transmit clock VO D6 ETXEN PEH6 MAC Transmit enable VO D7 ETXDO PEH5 MAC Transmit data VO B11 ECOL PEH4 MAC Collision VO A10 ERXCLK PEH3 MAC Receive clock VO C8 ERXDV PEH2 MAC Receive enable VO D9 ERXDO PEH1 MAC Receive data VO A11 ECRS PEHO MAC Carrier sense VO A7 B7 C7 ETXD 3 1 PEL 7 5 MAC Transmit data VO D10 ETXER PEL4 MAC Transmit error VO A9 B9 C9 ERXD 3 1 PEL 3 1 MAC Receive data VO B8 ERXER PELO MAC Receive error VO MCF5282 User s Manual Errata Rev 13 Freescale Semiconductor 11 Errata for Revision 1 0 Table 14 3 MCF5282 Signals and Pin Numbers Sorted by Function continued Pin Functions u Primary Internal MAPBGA Pin Description Pull up Primary Secondary Tertiary 2 1 FlexCAN D16 CANRX PAS3 URXD2 FlexCAN Receive data VO E13 CANTX PAS2 UTXD2 FlexCAN Transmit data VO FC E14 SDA PAS1 URXD2 I2C Serial data VO Yes E15 SCL PASO UTXD2 I C Serial clock VO Yes QSPI F13 QSPI_DOUT PQSO QSPI data out VO E16 QSPI_DIN PQS1 QSPI data in VO F14 QSPI_CLK PQS2 QSPI clock VO G14 G13 F16 F15 QSPI_CS 3 0 PQS 6 3 QSPI chip select VO UARTs R7 URXD1 PUA3 U1 receive data VO P7
17. errupt controller 08 2006 Added FlexCAN ESTAT register description errata for various bits Added ICRnx note regarding unique and non overlapping level and priority definitions Added DTOUT1 DTINO DTOUTO description field errata in GPIO chapter Added FEC MIl transmit and receive specification section errata MCF5282 User s Manual Errata Rev 13 16 Freescale Semiconductor Revision History MCF5282 User s Manual Errata Rev 13 Freescale Semiconductor 17 How to Reach Us Home Page www freescale com E mail support freescale com USA Europe or Locations Not Listed Freescale Semiconductor Technical Information Center CH370 1300 N Alma School Road Chandler Arizona 85224 1 800 521 6274 or 1 480 768 2130 support freescale com Europe Middle East and Africa Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen Germany 44 1296 380 456 English 46 8 52200080 English 49 89 92103 559 German 33 1 69 35 48 48 French support freescale com Japan Freescale Semiconductor Japan Ltd Headquarters ARCO Tower 15F 1 8 1 Shimo Meguro Meguro ku Tokyo 153 0064 Japan 0120 191014 or 81 3 5437 9125 support japan freescale com Asia Pacific Freescale Semiconductor Hong Kong Ltd Technical Information Center 2 Dai King Street Tai Po Industrial Estate Tai Po N T Hong Kong 800 2666 8080 support asia freescale com
18. mary Secondary Tertiary 1 Reset R11 RSTI Reset in l Yes P11 RSTO Reset out O Clock T8 EXTAL External clock crystal in l MCF5282 User s Manual Errata Rev 13 Freescale Semiconductor 9 Errata for Revision 1 0 Table 14 3 MCF5282 Signals and Pin Numbers Sorted by Function continued Pin Functions ve Primary Internal MAPBGA Pin Description Pull up Primary Secondary Tertiary 2 1 R8 XTAL Crystal drive O N7 CLKOUT Clock out Chip Configuration Mode Selection R14 CLKMODO Clock mode select l Yes T14 CLKMOD1 Clock mode select l Yes T11 RCON Reset configuration enable l Yes H1 D26 PA2 Chip mode VO K2 D17 PB1 Chip mode VO K3 D16 PBO Chip mode VO J4 D19 PB3 Boot device data port size VO K1 D18 PB2 Boot device data port size VO J2 D21 PB5 Output pad drive strength VO External Memory Interface and Ports C6 B6 A5 A 23 21 PF 7 5 CSI 6 4 Address bus O Yes C4 B4 A4 B3 A3 A 20 16 PF 4 0 Address bus Yes A2 B1 B2 C1 A 15 8 PG 7 0 Address bus Yes C2 C3 D1 D2 D3 D4 E1 E2 A 7 0 PH 7 0 Address bus O Yes E3 E4 F1 F2 F3 G1 G2 G3 D 31 24 PA 7 0 Data bus VO G4 H1 H2 H3 H4 J1 J2 J3 D 23 16 PB 7 0 Data bus VO J4 K1 K2 K3 L1 L2 L3 L4 D 15 8 PC 7 0
19. n lower 32K bank of memory If bit is set DMA has priority If bit is reset CPU has priority Priority is determined according to the following table Upper Bank Lower Bank PRI 1 2 Priority Priority 00 DMA Accesses DMA Accesses 01 DMA Accesses CPU Accesses 10 CPU Accesses DMA Accesses 11 CPU Accesses CPU Accesses NOTE The Motorola recommended setting for the priority bits is 00 Table 5 1 5 3 Add the following note to the SPV bit description The BDE bit in the second RAMBAR register must also be set to allow dual port access to the SRAM For more information see Section 8 4 2 Memory Base Address Register RAMBAR MCF5282 User s Manual Errata Rev 13 6 Freescale Semiconductor Errata for Revision 1 0 Table 4 MCF5282UM Rev 1 0 Errata continued Location Description Figure 6 2 6 4 Replace Figure 6 2 CFM 512K Array Memory Map with the figure below 0x0007 FFFF Logical Block 1 256 Kbytes Flash Physical Block 2 Flash Physical Block 3 er Paar Par an l l Memory Memory Memory Array 2H Array 2L Array 3H Array 3L 0x0004 000C 3H 1 3L 1 0x0004 0008 2H 1 2L 1 0x0004 0004 3H 0 340 2H 0 2L 0 0x0004 0000 2Hfo 2LIo 2 0x0003 FFFF E A Flash Physical Block 0 Configuration Field 1H 31 1L 31 0x0000_0400 0x0000_0417 Memory Memory Memory Memory Array OH Array OL Array 1H Ar
20. o write only instead of read write Removed selected by BKSL 1 0 as these are internal signal names not necessary for end user In the table for MFD bit definition footnote 1 equation should read f Tae SA sys sys max fret x 2 MFD 2 sys RD fiet x 2 MFD a 2 lt f sys max gt Where fsys max IS the maximum system frequency for the particular MCF5282 device 66MHz or 80MHz Add the following note If an interrupt source is being masked in the interrupt controller mask register IMR or a module s interrupt mask register while the interrupt mask in the status register SR I is set to a value lower than the interrupt s level a spurious interrupt may occur This is because by the time the status register acknowledges this interrupt the interrupt has been masked A spurious interrupt is generated because the CPU cannot determine the interrupt source To avoid this situation for interrupts sources with levels 1 6 first write a higher level interrupt mask to the status register before setting the mask in the IMR or the module s interrupt mask register After the mask is set return the interrupt mask in the status register to its previous value Since level seven interrupts cannot be disabled in the status register prior to masking use of the IMR or module interrupt mask registers to disable level seven interrupts is not recommended Chapter 17 Table 17 2 17 5 The maximum buffer size of the FEC is 20
21. or products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application Buyer shall indemnify and hold Freescale Semiconductor and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part e a oe 2 freescale semiconductor Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc All other product or service names are the property of their respective owners Freescale Semiconductor Inc 2006 All rights reserved MCF5282UMAD Rev 13 08 2006
22. rata for BITERR and ACKERR field descriptions Added errata for BOFFINT and ERRINT bit sequence Added errata for BUF nl field description 03 2004 03 2004 MCF5282 User s Manual Errata Rev 13 Freescale Semiconductor 15 Revision History Table 5 Revision History Table continued Rev Number Substantive Changes Date of Release 6 Added errata for Table 17 2 11 2004 Added errata for FRSR register diagram 7 Added errata for Figure 4 2 Table 4 6 Figure 6 3 and Table 6 10 11 2004 Added the below errata for MCF5282UM Rev 2 3 8 Added FEC max buffer size errata 01 2005 Added VDD VDDH power up requirement Added MFD bit definition footnote errata Added PLL spec table entries for 66MHz device 9 Added INTFRCL n figure errata 03 2005 Added BAM bit field example errata 10 Added SDRAM NOP command errata 07 2005 Added UART clock source errata 11 Added PRI1 PRI2 text description errata 08 2005 Added CSMR1 CSCR1 register address errata Removed Table 23 5 errata that was added in revision 10 of this document as it was incorrect Only the internal UART clock source is prescaled by the 16 bit divider Added 2 UART external clock source errata removing the 16 bit divider from a figure and equation 12 Added core watchdog unable to reset the device errata 12 2005 Added EMRBR register address errata Added lop and lo errata 13 Added FlexCAN flag clearing mechanism errata in int
23. ray IL 0x0000 000C 1H 1 1L 1 x 2 4 4 0x0000 0008 OH 1 OL 1 l 0x0000 0004 1L 1 RE 0x0000 0000 OHIO OL O 7 Each memory array 64 Kbytes 16 bits wide x 32K Each physical block 128 Kbytes 32 bits wide x 32K Figure 6 2 CFM 512K Array Memory Map Table 6 12 6 16 Change value for page erase verify command to 0x06 Table 6 13 6 20 Change value for page erase verify command to 0x06 Table 8 3 8 5 Add the following note the BDE bit description The SPV bit in the CPU s RAMBAR must also be set to allow dual port access to the SRAM For more information see Section 5 3 1 SRAM Base Address Register RAMBAR Figure 9 1 9 3 Remove 2 from CLKGEN block 10 3 6 10 11 Add this text to the end of the first paragraph If a specific interrupt request is completely unused the ICRnx value can remain in its reset and disabled state 10 5 10 17 Add the following note The wakeup mask level taken from LPICR 6 4 is adjusted by hardware to allow a level 7 IRQ to generate a wakeup That is the wakeup mask value used by the interrupt controller must be in the range of 0 6 Figure 12 4 12 8 Change CSCRn to reflect that AA is set to 1 at reset 13 5 13 15 Remove final paragraph The paragraph incorrectly states that the MCF5282 does not have a bus monitor MCF5282 User s Manual Errata Rev 13 Freescale Semiconductor 7 Errata for Revision 1 0 Table 4

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