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PK2600

1. U3 Flash EPROM Figure 4 4 CM7200 Core Module There is no need to disconnect any cables connected to either the controller board or to the display board 38 Hardware Configurations PK2600 4 Remove the four 4 x 3 4 screws holding the I O conversion module to the PK2600 assembly These screws are labeled 2 in Figure 4 3 5 The I O conversion module plugs into headers 118 111 1 7 10 6 H9 J5 H12 H14 and H15 on the controller board Carefully unplug the I O conversion from these headers Figure 4 5 shows the header locations on the controller board Remove to access Standoffs Display Board s u19 ut RTC Tr o 2 U12 IULII ug Controller CM7200 Board Core Module Figure 4 5 Attachment of Controller Board to Display Board and I O Conversion Module Remove to access Display Board The CM7200 core module is attached to the controller board There is need to remove the core module to access either the controller board or the display board
2. Connecting the PK2600 display to a PC using the SIB2 1 Make sure that Dynamic C is installed on your PC as described in the Dynamic C Technical Reference manual Unplug the power supply 2 Connect an RJ 12 cable between the RJ 12 DE9 adapter attached to the PC and the SIB2 The cable and adapter are supplied with the SIB2 3 Plug the SIB2 s 8 pin connector onto the DISPLAY header located on the back of the PK2600 as shown in Figure 2 5 Make sure that pin 1 on the ribbon cable connector on the striped side matches up with pin 1 on the DISPLAY header indicated by a small black dot next to the header 4 Plug the power supply transformer into a wall socket Running Dynamic C With the SIB2 connected to the DISPLAY header double click the Dynamic C icon to start the software Note that the PC attempts to communicate with the PK2600 each time Dynamic C is started No error messages are displayed once communication is established The communication rate port and protocol are all selected by choosing Serial Options from Dynamic C s OPTIONS menu The SIB2 and the PK2600 both set their baud rate automatically to match the communication rate set on the host PC using Dynamic C 9600 bps 19 200 bps 28 800 bps or 57 600 bps To begin adjust the communications rate to 19 200 bps Make sure that the PC serial port used to connect the serial cable COM1 or COM2 is the one selected in the D
3. Figure 4 2 shows an exploded view of these five boards s gt lt oe 9 Trans 5555 B SI former pp ps mon Co pros pres B B 024 ces U10 5 pi Bp E moomo au mmm i P bonu diurnum 27 furs ae 02 SRAM RTC i SRAM TUNIS ni Us L Bd a Ut B cage y Lop B 4 Flash 3 E Flash B Control Eos 8 POA 5 2180 emma Pi E Display Bb ee CU com 528 3 8l V Board v2 SERA 282954 eg ps Um a ET AH p 254854 TULI PL titia sez V 1 His Hig n MVA MV iine veo d 5 OE un un cy IN 3 q u18 8 U16 8 OOO 1 nnn i Us U4 miim Controller H Board E U10 3 an 5 OT m 1 US O Pene AREE 0 Power Program Conversion CM7200 Module Module Core Module Figure 4 2 E
4. Replacing Soldered Lithium Battery Battery Cautions 5 Index viii Table of Contents Asout THis MANUAL This manual provides instructions for installing testing configuring and interconnecting the Z World PK2600 integrated touchscreen control system Instructions are also provided for using Dynamic C functions Assumptions Assumptions are made regarding the user s knowledge and experience in the following areas e Ability to design and engineer the target system that interfaces with the PK2600 Understanding of the basics of operating a software program and editing files under Windows on a PC Knowledge ofthe basics of C programming e For a full treatment of C refer to the following texts The C Programming Language by Kernighan and Ritchie C A Reference Manual by Harbison and Steel Knowledge of basic Z80 assembly language and architecture For documentation from Zilog refer to the following texts Z180 MPU User s Manual Z180 Serial Communication Controllers Z80 Microprocessor Family User s Manual PK2600 About This Manual ix Acronyms Table 1 lists and defines the acronyms that may be used in this manual Table 1 Acronyms Acronym Meaning EPROM Erasable Programmable Read Only Memory EEPROM Electronically Erasable Programmable Read Only Memory LCD Liquid Crystal Display LED Light Emitting D
5. 79 SYS LIB g 109 sysChk2ndFlash 109 sysRoot2FXmem 109 system clock frequency 80 86 87 88 system 222222 79 T TOR 81 85 5 83 81 85 83 time date clock 108 T6g SteTs oc sentes 138 timer watchdog 77 78 79 108 tn 108 touchscreen initialization 106 reading sss 106 107 transmitter data register 83 83 transmitter enable 85 transmitter interrupt 81 transmitter interrupt enable 83 TRAP i vehe eee 142 troubleshooting 121 board resets 123 cables duse 122 COM port esee 123 PK2600 serial channels continued RS 485 65 100 101 serial communication 76 80 83 85 86 88 136 external connections 65 sample program 101 signals inea 65 serial communication controller 32 62 Serial Interface Board 2 See SIB2 serial interrupts 142 serial ports 18 81 82 asynchronous 80 multiprocessor communications Tea
6. RS 232 Ch 0 2543 Analog Inputs RS 232 Ch 1 2180 9 to Display Board watcha ADC 8 AIN 0 7 atchdog RS 232 or RS 485 Ch A Supervisor RS 232 or RS 485 Ch SCC ADREF Flash EPROM Ref 25V RAM Battery PLCBus RTC CM7200 5 V oo0 GND Code iN Rs Bank A 16 00 15 16 3 00545 as Input or output PR T but not both K 2803 Sinking Driver standard m 2985 Sourcing Driver optional Digital Inputs Digital Outputs TTL or CMOS output optional 5 V 000 GND Bank 5 HVB 00 15 16 1 00 15 ae Input or output Y but not both K Figure 5 1 Controller Board Block Diagram Only the subsystems associated with the CM7200 core module GY are included in this chapter See Chapter 4 Hardware Config urations for a description of the configurable subsystems Microprocessor Core Module The controller board is built around a Z World CM7200 Series microproces sor core module The core module consists of a Zilog Z180 microproces sor 32K of battery backed static RAM 128K of flash EPROM a real time clock and a watchdog timer microprocessor supervisor The Z180 CPU runs at 18 432 MHz Internal to the Z180 are two asynchro nous serial ports two DMA channels two programmable reload timers PRTs and three interrupt lines Six chip select lines CS1 CS6 enable one of six groups of 64 I O ad
7. 101 117 kpDefStChgEn 107 kpInit dp 106 kpScanState 106 117 L 7 15 28 3 background color 69 contrast adjustment 28 contrast control jumper configu TatiODS 69 manual contrast adjustment 28 matrix coordinates 29 software contrast adjustment 28 LCD BUS ect terit edes 163 LCD controller 74 ets 163 libraries 90 function 7097 164 liquid crystal display See LCD PK2600 26 pin 6 pin assignments 162 4 bit operations 163 165 8 bit operations 163 165 addresses 164 165 configuration 68 memory mapped I O register 164 operating modes 68 reading 1808 164 relays DIP istis thi 162 cesis 167 writing data 164 plot a circle 115 plota Ime 115 14 plot a polygon 115 ports 18 81 82 asynchronous sses 80 multiprocessor communication 10 esee 80 POWOE eerte 79 142 7 154 power failure 222 TI detection circuit 178 interrupts 142 179 77 7 179 sample program
8. sssse 147 CSI O clocked serial I O 84 CDS aan e Mio 84 CTS enabl s i Res 84 84 customization 222 22 16 D D0OX D7X gt 163 data carrier detect 83 data format mode bits 85 Ib GE 79 default jumper settings 154 158 demonstration screen displays 21 Developer s Kit 18 packing list sss 20 digital inputs 22222222 4 addtesses i uses 92 Bank A eee 41 Bank 4 connecting to 41 61 67 frequency response 129 input current 129 logic threshold 42 low pass filter 4 operating 16 4 operating voltage 129 opto isolation 41 67 pull down resistors 42 pull up resistors 42 0 91 sample program 92 software 91 Specifications 129 digital outputs sss 45 addresses sss 9 Bank ees 45 Bank tiers 45 2600 expansion register 166 2 17 11 90 EZIOLGPL LIB 1 167 EZIOMGPL LIB 167 EZIOOP71 LIB 102 117 EZIOPL2 LIB 167 EZIOPLC 18 167 2
9. Computing Module sse Power Regulation esse Serial Communication System Reset cese eter e Levate e Haze dU 7180 Serial Ports 2 Use of the Serial Ports iv Table of Contents Asynchronous Serial Communication Interface ASCI Status DCDO Data Carrier 22 TIE Transmitter Interrupt Enable Transmitter Data Register Empty CTSIE CTS Enable Channel 1 RIE Receiver Interrupt Enable sss FE Framing Error eee PE Parity oe erdt 7 Receiver Data Register Full 44424442 MODO0 MOD2 Data Format Mode Bits MPBR EFR Multiprocessor Bit Receive Error Flag Reset RTSO Request to Send Channel 0 CKAID CKAI Disable enne RE Receiver Enable eene MPE Multiprocessor Enable sss SS Source Speed Select 2 2 PEO Parity Even Odd sse CTS PS Clear to Send Prescaler MPBT Multiprocessor Bit Transmit
10. SIB2 is needed to program the display board See the Dynamic Technical Reference manual for more information on use and other libraries 90 Software Development PK2600 Digital I O Digital Inputs The PK2600 controller board is equipped with protected digital inputs designed as logical data inputs that return a 1 when the input is high or 0 when the input is low A low pass filter on each input channel has a time constant of Tyo 220 us 4 5 kHz If the signals present on the digital inputs change states faster than this the readings on the inputs may not be accurate How to Read the Input This section provides information on using the Dynamic C software drivers for the controller board s protected digital inputs The following software drivers read the status of the protected digital inputs unsigned BankA unsigned eioAddr unsigned BankB unsigned eioAddr BankA converts eioAddr to a value of 16 31 for addressing the correct input or output assignments BankB converts eioAddr to a value of 0 15 PARAMETER eioAddr specifies channel number from 0 15 RETURN VALUE the formatted I O assignment or 1 if the parameter eioAddr is out of range int eioBrdDI unsigned eioAddr Reads the state from one of the 32 physical digital inputs Sets eioErrorCode ifeioAddr is out of range PARAMETER eioAddr specifies the input to be read Valid numbers
11. ASCI Control Register B Chapter 6 Software Development Supplied Software esses Digital IQ eae een REN ah T Digital Inputs eec REP Reine How to Read Digital Outputs Sample Program sees How to Use the PWM Feature PWM Software Pulse Width Modulated PWM Outputs Analog Inputs Using the Analog Inputs eee Sample Progr m evi is Table of Contents v PK2600 Serial Channelsz 6 ertet 100 RS 232 Communication essere 100 RS 485 Communication essere 100 Software ede ee 50 ERR 101 Sample Program 101 Display Board Functions 102 Display Hardware Control sse 102 Display Images EROR 05 00 102 Touchscreen Functions 106 Additional Software eo a ee 108 Real Time 108 Flash EPROM Rete Badenian 108 Other Software P eer rep DEP 110 Sample Programs ORE OE OTt 110 Chapter 7 Graphics Programming 113 n nete osito edente 114 5 Drawing Primitiv s cete ere tient HI seen 114 Plota Pixel cioe t en HY e ed 114 Plot Eine enne e REP AR EU TT 115 22 dd i eonim 115 Plot a Polygone eee ciae emere e erede 115 Pilla Circle
12. oy N 14 154 Circuit Board Reference Table 0 5 Controller Board Jumper Settings concluded Factory Default Connected Connected Connected Connected Connected Connected Connected Description Connect to enable RS 485 termination resistors for Channel A Connect to enable RS 485 termination resistors for Channel B Connect to enable 5 wire RS 232 on Channel B Connect to enable 2 wire RS 485 for Channel B Connect to allow DREQO to be used for Channel A Connect to allow DREQO to be used for PWM disconnect for user application Disconnected DREQO available for user application Connect for 3 wire RS 232 on Channel 1 Connect for 2 wire RS 485 on Channel 1 Connect to allow DREQ I to be used for Channel B Connect to allow user application for Channel B Circuit Board Reference 155 Pins 1 2 3 4 5 6 8 1 3 3 5 BEES 0 24 4 6 2 4 6 7 9 9 11 10 12 Header PK2600 Table D 6 lists the jumper settings for optional controller board configura tions These optional configurations involve adding or removing input interface or high voltage driver ICs which are surface mounted This work is most easily done in the factory in response to customer needs Table D 6 Controller Board Jumper Setting for Optional Inputs Outputs Header Pins Description Bank A Digital Outputs T
13. Programming Port SIB Display Board Programming Port 4 Figure 1 1 PK2600 Block Diagram 14 Overview Features The PK2600 is equipped with a gas tight bezel conforming to a NEMA Type 4 enclosure rating The PK2600 features an 18 432 MHz clock with the Z180 microprocessor and the display uses a 9 216 MHz clock The PK2600 includes the following features Controller The controller uses a core module Z World part number 129 0099 designed for easy in system programming The core module includes the CPU 32K SRAM 128K flash EPROM real time clock and microprocessor watchdog circuitry The following I O are available on the PK2600 Serial channels Three full duplex serial channels interface directly with serial I O devices RS 232 and RS 485 signals are supported e Digital I O The 32 I O lines can be ordered as inputs or outputs in banks of eight The PK2600 comes standard with 16 protected digital inputs and 16 high voltage high current sinking outputs capable of driving resistive and inductive loads The sinking outputs can be converted to sourcing outputs with an optional sourcing driver kit e Pulse width modulated outputs Up to 7 digital outputs can provide pulse width modulation Analog inputs Eight conditioned 12 bit analog inputs each with user configurable bias and gain interface directly with many sensors Two unconditioned analog inputs are also available Expansion bus
14. 78 sequence of events 178 software 108 110 124 power supply backlight 75 CONNECTIONS sss 20 high voltage 75 E E E 75 07 75 power program module dimensions 147 dew 87 PK2600 outport 82 93 114 134 136 168 169 171 outputs CMOS niti itin 50 50 ques 84 OVEITUN eese 84 OVETVICW 14 84 85 parity na 87 parity 84 parity 87 PE I atiam 84 85 PEO 87 peripheral addresses 139 77 79 2 pinouts analog inputs 31 152 sassssitess 152 tet 152 digital T O 30 151 Bank A 151 Bank 151 HIO 151 nasse 151 em 151 151 PLCBUS esas 162 RS 232 serial ports 32 RS 232 RS 485 serial ports 67 serial communication headers eec 153 153 X 153 HID eee erm 153 PK2600 11111415 dense 16 PK26CONT C 111 PK26DISP C neon 111 200 Index ite keine 174 RS 232 serial communication 32 62 76 RS 485
15. Plots the outline of a polygon PARAMETERS is the number of vertices x1 is the x coordinate of the first vertex y1 is the y coordinate of the first vertex x2 is the x coordinate of the second vertex y2 is the y coordinate of the second vertex void glFillVPolygon int n int pFirstCoord Fills in a polygon PARAMETERS is the number of vertices pFirstCoord is an array of vertex coordinates x y X y void glFillPolygon int n int x1 int yl int x2 int y2 Fills in a polygon PARAMETERS nis the number of vertices x1 is the x coordinate of the first vertex y1 is the y coordinate of the first vertex x2 is the x coordinate of the second vertex y2 is the y coordinate of the second vertex void glPutBitmap int x int y int bmWidth int bmHeight char bm Displays a bitmap stored in root memory on the LCD For bitmaps defined in xmem memory use g1XPutBitmap PARAMETERS x is the x coordinate of the bitmap left edge y is the y coordinate of the bitmap top edge bmWidth is the width of the bitmap bmHeight is the height of the bitmap bm is a pointer to the bitmap The bitmap format is a column with the major byte aligned for each column PK2600 Software Development 105 e void glXPutBitmap int x int y int bmWidth int bmHeight unsigned long bmPtr Displays a bitmap stored in xmem on the LCD For bitmaps stored in root memory use g1PutBitmap PARAMETERS x is the
16. 61 148 H12 controller board 65 148 controller board 65 148 14 controller 65 148 H15 controller board 65 148 H2 controller board 45 H3 controller board 45 H4 controller board 148 H6 controller board 41 49 61 67 148 H7 controller board 41 49 61 67 148 PK2600 12 controller board 42 63 display board 157 J3 controller board 42 display board 28 157 JA controller board 63 65 68 display board 157 5 controller board 148 display board 157 J6 display board 157 J7 controller board 65 J8 controller board 51 63 display board 157 JUMP vectors 142 jumper settings sees 51 51 INT1 Wares esie 68 Bank A digital inputs 43 digital outputs 47 reer More 47 pp 43 Bank digital inputs 44 a 44 contrast control 69 controller board default settings 154 155 TD rc Meer 156 jor 154 p ER 154 A E ons aS 156 JA nes ud 154 Jh sehe 155 VR tthe oiu ect 155 P
17. 94 Software Development Pulse Width Modulated PWM Outputs Digital outputs 0 6 on Bank B can produce fixed frequency pulse width modulated PWM signals When these outputs are being used for PWM operation Channel 7 is used by software to support PWM and cannot be used for your application The periods of the PWM signals are fixed at 13 3 ms 75 Hz witha resolution of 256 divisions per period 8 bit resolution Using the supplied software generating PWM signals consumes about 8 of controller s processing power When PWM functions are used serial communication baud rates may be affected because of an overloading of the microprocessor s resources Contact Z World Technical Support at 530 757 3737 for furthe assistance with PWM functions How to Use the PWM Feature The PK2600 controller board can produce fixed frequency fixed phase variable duty cycle square waves from up to seven of its outputs Figures 6 1 and 6 2 show PWM transition and DMA timing Composite Edge 52 08 us i E Single Edge 13 02 us Output 0 Output 1 Output 2 Output 3 Figure 6 1 Transition Timing PK2600 Software Development 95 ii Wave Period 13 33 ms i i Next Possible Transisition ii 256 no 52 08 us No x 52 08 us Output 0 Output 1 Output 2 Output 3 no number of divisions per period 0 256 52 08 us Figure 6 2 DMA Timing Notice that each s
18. All headers and jumpers necessary to configure the controller board are now accessible Once the controller board has been reconfigured repeat the above steps in reverse order or remove the controller board to gain access to the display board PK2600 Hardware Configurations 9 Accessing the Display Board 1 Follow Steps 1 5 in the section on Accessing the Controller Board on the previous two pages 2 Remove the two 4 x 1 2 screws holding the controller board to the mounting bracket as shown in Figure 4 5 3 A ribbon cable connects header 18 on the display board to header 3 on the controller board A wire assembly carries the supply voltage from power header J1 on the controller board to power header J11 on the display board There is need to disconnect the cables connected to either the controller board or to the display board There is no need to removed the display board to access the LCD The controller board may now be lifted off the bracket leaving the headers and jumpers on the display board accessible Once the display board has been reconfigured repeat the above steps in reverse order to replace the boards that were removed Figure 4 6 shows the board layout for the display board Trans former u7 us
19. Connecting the PK2600 controller to a PC using the SIB2 1 Make sure that Dynamic C is installed on your PC as described in the Dynamic C Technical Reference manual Unplug the power supply 2 Connect an RJ 12 cable between the RJ 12 DE9 adapter attached to the PC and the SIB2 The cable and adapter are supplied with the SIB2 3 Plug the SIB2 s 8 pin connector onto the CONTROLLER header located on the back of the PK2600 as shown in Figure 2 5 Make sure that pin 1 on the ribbon cable connector on the striped side matches up with pin 1 on the CONTROLLER header indicated by a small black dot next to the header Ca H 0 AX CAUTION High Voltage H Transformer Only qualified v persons may open this case ANALOG INPUTS SERIAL PORT 1 Beros Marked Conductor j HRUN DC 41 to Pin 1 CONTROLLI DIGITAL GROUP 2 SERIAL PORT 2 DIGITAL GROUP 1 PLCBUS EXPANSION PORT 2900 SPAFFORD ST DAVIS CA 95616 N 1 530 757 3737 WWW ZWORLD COM Serial Interface Board 2 Figure 2 5 PK2600 SIB2 Programming Connections 4 Plug the power supply transformer into a wall socket The Run Program switches must remain in the RUN position when using the 5132 to program the PK2600 The SIB2 takes care of setting the PK2600 to program mode while it is con nected to the PK2600 PK2600 Getting Started 23
20. from 0 to 31 0 15 represents Bank 16 31 represents Bank A RETURN VALUE 0 if input reads low 1 if input reads high unsigned inport unsigned port Reads a value from an I O port PARAMETER 1 port is the PK2600 controller board port address to read When used to read the digital inputs port is one of four groups of eight inputs There are two groups of eight inputs for each bank RETURN VALUE The value read from the port PK2600 Software Development 91 Table 6 2 lists the addresses and corresponding headers of the digital input ports on the controller board Table 6 2 Digital Input Addresses Header H10 H7 H6 H9 Channels 00 07 08 15 HVA08 HVAIS HVA00 HV A07 Physical Channels 0 7 8 15 24 31 16 23 Address 0x4040 0x4041 0x4042 0x4043 The factory default is for Bank A to be configured for digital inputs The lower eight bits of the value read back by the inport function repre sent the status of the inputs Bit 0 represents inputs 0 8 16 or 24 depending on which address is read Bit 1 represents inputs 1 9 17 or 25 and so forth Sample Program The sample program BL17DIO C shows how to use the digital I O It can be found in the Dynamic C SAMPLES BL17XxX subdirectory 92 Software Development PK2600 Digital Outputs The PK2600 controller board provides up to 32 high voltage high current driver outputs Some outputs can also function as pulse width modu
21. Q 0 7 8 gt BONUS Keypad Buzzer drive vec RNA To J5 or to J6 keypad U10 47 connectors COL 0 7 D 0 7 YI0 71 0 71 o O7 ed _ Keypad sense 014 021 ICOLUMN 74HC244 4 021 L WV Figure D 9 Block Diagram of PK2600 Keypad Interface PK2600 Circuit Board Reference 159 Blank 160 Circuit Board Reference PK2600 E PLCBus Appendix E provides the pin assignments for the PLCBus describes the registers and lists the software drivers PK2600 PLCBus 1 PLCBus Overview The PLCBus is a general purpose expansion bus for Z World controllers The PLCBus is available on the BL1200 BL1600 BL1700 PK2100 PK2200 and PK2600 controllers The BL1000 BL1100 BL1300 BL1400 and BL1500 controllers support the XP8300 XP8400 XP8600 and XP8900 expansion boards using the controller s parallel input output port The BL1400 and BL1500 also support the XP8200 and XP8500 expansion boards The ZB4100 s PLCBus supports most expansion boards except for the XP8700 and the XP8800 The SE1100 adds expansion capability to boards with or without a PLCBus interface Table E 1 lists Z World s expansion devices that are supported on the PLCBus Table E 1 Z World PLCBus Expansion Devices Device Device Description EXP ADI2 EXP A D12 Eight channels of 12 bit A D converters SE1100 Four SPDT relays for use with all Z World controllers XP8100 Series 32 d
22. Subsystems PK2600 The assumption is that if the program fails to hit the watchdog the program must be stuck in a loop or halted The Dynamic C function for hitting the watchdog timer is hitwd To hold the watchdog timer at bay make a call to hitwd in a routine that runs periodically at the lowest software priority level A program can read the state of the WDO line with a call to wderror This makes it possible to determine whether a watchdog timeout occurred The following sample program shows how to do this when a program starts or restarts main 15 wderror 1 hitwd Power Shutdown and Reset When VCC 5 V drops below V n between 4 5 V and 4 75 V the 691 supervisor asserts RESET and holds it until VCC goes above V m and stays that way for at least 50 ms This delay allows the system s devices to power up and stabilize before the CPU starts PFI Early Warning When PFI drops below 1 3 V 0 05 V 1 DCIN drops below 7 9 V for the controller board or 10 V for the display board the supervisor asserts NMI nonmaskable interrupt and allows the program to clean up and get ready for shutdown The underlying assumption here is that PFI will cause the interrupt during a power failure before the 691 asserts RESET Memory Protection When RESET is active the 691 supervisor disables the RAM chip select line preventing accidental writes Battery Backup The backup
23. 1 11 167 BEARS e erts 84 85 15 circle 115 fill a polygon 115 flash EPROM 72 180 flexibility odo ens 16 float USC Seiten ative Maange 124 fntcvtr exe 118 Entstrip exe 118 font and bitmap conversion 118 sample program 118 using in program 119 framing 2 84 frequency LCD controller 74 system 01006 86 87 88 7 74 function libraries 164 G eoo 102 glFillCircle 104 115 glFillPolygon 105 115 1 111 1 105 glFontInit 102 116 glinrt sew 104 114 glPlotCircle 104 115 glPlotDot 104 114 glPlotLine 104 115 glPlotPolygon 105 115 glPlotVPolygon 105 glPrintf 104 116 glPutBitmap 105 115 PK2600 E doe 180 _ 180 EEPROM simulated 73 74 addresses 180 constants 141 reserved addresses 74 simulated in flash EPROM 73 4 software 1
24. 4 1 expresses an amplifier s gain in terms of its input voltage range 2 5 V Ee 4 1 Vin 7 Vin where g is the gain Vy is the maximum input voltage and is the minimum input voltage The ratio of the user specified gain resistor to its associated fixed input resistor determines an amplifier s gain For the amplifier in Fig ure 4 14 with its input resistor fixed at 10 kQ the gain is R ain E END LE 4 2 10 000 Q Given an input voltage range of 10 V this gain equation fixes the amplifier s gain at 0 25 This gain scales the input signal s range properly down to the op amp s 2 5 V maximum output range R must therefore be 2500 Q gain 5 3 Determine bias resistor If the op amp is to servo its output properly around the desired center voltage you must establish the appropriate bias voltage at the op amp s noninverting input You must select the bias or offset resistor tO position the input voltage range correctly with respect to ground For this example let us use 5 V to 5 V 54 Hardware Configurations PK2600 Because the value for R pain has already been selected the maximum input voltage Nmap determines the maximum voltage seen at the amplifier s summing junction inverting input circuit nodes through VR7 Compute VRO through VR7 using Equation 4 3 g VRO Va x 4 3 IN max g For each op amp the bias voltage must equal its corresponding VRn A
25. Feedback capacitors roll off the high frequency response of the amplifiers to attenuate noise Figure 4 14 shows a schematic diagram of the condi tioned input amplifier circuit ANAO ANA7 10 Figure 4 14 Analog Conditioning Circuit Table 4 6 lists the gain and bias resistors for each of the eight conditioned analog input channels Table 4 6 Gain and Bias Resistors Hm Rgain ANAO R20 R21 ANAI R19 R34 ANA2 R6 R22 ANA3 R18 R35 ANA4 R51 R36 ANAS R52 R49 ANA6 R53 R37 ANAT R50 R38 PK2600 Hardware Configurations 53 Strip sockets spaced 0 400 inches 10 2 mm apart accommodate the gain and bias resistors Z World can install surface mounted gain and bias resistors for your exact configuration in production quantities For more information call your Z World Sales Representative at 530 757 3737 2 Select gain resistor The gain and bias resistors determine the input signal s voltage relative to ground as well as its range For example assume your circuit must handle an input signal voltage range of 10 V spanning 5 V to 5 V You should first select the gain feedback resistor to suit an input signal voltage range of 10 V The gain ofthe amplifier is the ratio of its maximum output voltage swing to your application s maximum input voltage swing The 2 5 V input voltage range of the A D chip limits the op amp s output swing to 2 5 V Therefore Equation
26. HVA SiS 3 6 6 4 3 6 6 4 Channels 5 6 5 T 6 S EM 8 7 8 U15 ULN2803 U15 UDN2985 46 Hardware Configurations 2600 The digital interface chips must be removed from Bank A and high voltage driver chips must be installed before the Bank A inputs can be used as outputs Figure 4 8 shows the location of the driver chips and the headers whose jumpers need to be changed Battery Figure 4 8 Locations of Headers and Sinking Drivers Pay particular attention to the orientation of the jumpers when changing the driver output from sinking to sourcing Exercise caution when install ing sourcing drivers in the field 1 Besure power is removed from the controller 2 Remove the ULN2803 sinking drivers from the IC sockets Note that regular PK2600 controller boards have two ULN2803 chips at U7 and U17 and only PK2600s that have been customized for more than 16 outputs will have chips at 115 and 15 3 Install the jumpers on header H3 for the sourcing configuration as shown in Tables 4 3 and 4 4 Note the location of pin number 1 in Figure 4 8 4 Install UDN2985 sourcing driver chips into the IC sockets Be sure the jumper settings conform to what 1s specified Failure to install jumpers correctly may damage your
27. The PK2600 must be in this mode to compile a program to the PK2600 or to debug a program The PK2600 will run a program without polling when the PK2600 is in Program mode The Dynamic C manuals provide a complete description of program polling Program mode the 2600 matches the baud rate of the PC COM port up to 57 600 bps RunMode In Run mode the PK2600 runs standalone At power up the PK2600 checks to see if its onboard memory contains a program If a program exists the PK2600 executes the program immediately after power up In Run mode the PK2600 does not respond to Dynamic C running on the A program cannot be compiled or de bugged when the PK2600 is in Run mode The PK2600 has two DIP switches to set the Run or Program modes 8 PROG one for the controller C and one for RUN the display D Dc Although the controller and the display are pro 1 grammed separately Tip both DIP switches CONTROLLER should be set to RUN for the PK2600 to run stand DISPLAY alone Figure 3 1 shows the location of the Figure 3 1 Location of Run DIP switches used to set the Run or Pr ogram DIP Switches Program modes 26 Hardware Features PK2600 Changing the Operating Mode 1 Locate the Run Program DIP switch see Figure 3 1 2 Select whether the display or the controller is to have its operating mode changed and set the corresponding DIP switch to the
28. the PK2600 can be customized to better meet the needs of your application The options include the following configurations Core module configuration CM7100 and CM7200 core modules can be used on the PK2600 Customization options include RAM size flash EPROM size flash EPROM or regular EPROM and clock speed CM7100 and CM7200 core modules must have a 5 pin header installed at H1 and the BIOS must be customized for these core modules to be used on the PK2600 Digital I O configuration optional TTL level I O Analog input configuration gain and offset configuration Serial channel configuration RS 485 3 wire RS 232 or 5 wire RS 232 serial ports Background positive blue images on white background or negative white images on blue background The following accessories are available for the PK2600 Sourcing driver kit SIB2toallow programming through the SIB ports leaving all the serial ports available for the application being developed SIB2 is required to program the display board 16 Overview PK2600 Table 1 2 lists the various configuration options and the factory default configurations for the PK2600 Table 1 2 PK2600 Configuration Options Configuration Factory Default Alternatives Controller SERIAL 1 2 N A SERIAL 2 5 232 with DCDand ps Ags DTR SERIAL PORT3 85 232 85 485 8 digital inputs amp 8 digital outputs OR 16 digital
29. via SIB2 23 power supply 20 connectors 26 pin PLCBus pin assignments 162 contrast control 15 28 PK2600 B background negative blue with white characters 69 positive white with blue characters 69 background routine 166 backlight 3 ems 15 backup battery TI 79 011101186 190 Bank 91 93 91 93 battery replacing assets 190 baud rates 76 87 88 bidirectional data lines 163 bitmap conversion 118 BLl7AIN C eee 99 17510 92 4 17 187 17 2 185 BL17PWMA C 97 block diagram internal power regulators 75 keypad interface 159 28 serial channels 76 Z180 Serial Channel 0 80 bus control registers 167 digital inputs 167 EXPANSION 162 167 4 bit drivers 168 8 bit drivers 170 addresses 166 1 166 167 functions 168 171 rules for devices 166 software driv
30. Clocked Serial Control Register 5 TRDR Clocked Serial Data Register 0 0 TMDROL Timer Data Register Channel 0 least 0x0D TMDROH Timer Data Register Channel 0 most OxOE RLDROL Timer Reload Register Channel 0 least OxOF RLDROH Timer Reload Register Channel 0 most 0x10 TCR Timer Control Register 13 11 0 0 Reserved 0 14 TMDRIL Timer Data Register Channel 1 least 0x15 TMDRIH Timer Data Register Channel 1 most 0x16 RLDRIL Timer Reload Register Channel 1 least Ox17 RLDRIH Timer Reload Register Channel 1 most continued 136 Memory I O Map and Interrupt Vectors PK2600 Table 6 2 2180 Internal I O Registers Addresses 0x00 0x3F concluded Address Name Description 0 18 FRC Free running counter Ox19 0xIF Reserved 0 20 SAROL source address Channel 0 least 0 21 SAROH source address Channel 0 most 0x22 SAROB DMA source address Channel 0 extra bits 0x23 DAROL DMA destination address Channel 0 least 0x24 DAROH DMA destination address Channel 0 most 0x25 DAROB DMA destination address Channel 0 extra bits 0 26 BCROL DMA Byte Count Register Channel 0 least 0 27 BCROH DMA Byte Count Register Channel 0 most 0x28 MARIL DMA Memory Address Register Channel 1 least 0x29 MARIH DMA Memory Address Register Channel 1 most Ox2A MARIB Memory Address Register Channel
31. Connect for HV A00 HV A07 sinking output 1 3 dca Connect for HV A00 HV 07 sourcing output 5 6 a Connect for 08 15 sinking output 5 7 6 8 Connect for 08 15 sourcing output Bank B Digital Inputs 1 3 Connect for inputs pulled up 3 5 Connect for HVB00 HVBO3 inputs pulled down 2 4 Connect for HVB04 HVBO7 inputs pulled up 4 6 Connect for HVB04 HVBO7 inputs pulled down 7 9 Connect for 08 15 inputs pulled up 9 11 Connect for HVB08 HVBI5 inputs pulled down For ordering information or for more details about the various options and prices call your Z World Sales Representative at 530 757 3737 156 Circuit Board Reference PK2600 Display Board Table D 7 lists the header functions for the headers on the display board Figure D 8 shows the header locations and the dimensions of the display board Table D 7 Display Board Header Functions Header Description LCD hard wired 12 Backlight 8 LCD Gibbon cable J4 Programming port 5 Touchscreen interface J6 Keypad interface J8 RS 232 port header Jil DC power supply RS 485 port 112 4 390 typ 6 4 6 400 163 Figure D 8 Display Board Headers and Dimensions PK2600 Circuit Board Reference 157 Table D 8 lists the jumper configurations for the configurable heade
32. Control Register B Control Register B configures the multiprocessor mode parity and baud rate for each channel CNTLBO 02H and CNTLB1 03H 3 2 1 0 i PEO DR SS2 SS sso R W R W R W R R W SS Source Speed Select Coupled with the prescaler PS and the divide ratio DR the Ss bits select the source internal or external clock and the baud rate divider as shown in Table 5 3 Table 5 3 Baud Rate Divide Ratios for Source Speed Select Bits 552 551 sso Divide Ratio 0 0 0 1 0 0 1 2 0 1 0 4 0 1 1 28 1 0 0 16 1 0 1 32 1 1 0 64 1 1 1 external clock not exceed system clock 0 86 Subsystems 0 The prescaler PS the divide ratio DR and the SS bits form a 6 generator as shown in Figure 5 7 Prescaler Divider Processor PS 1 Clock 10 2 External or gs Clock 30 64 Figure 5 7 Z180 Baud Rate Generator DR Divide Ratio This bit controls one stage of frequency division in the baud rate genera tor If 1 then divide by 64 If 0 then divide by 16 This is the only control bit that affects the external clock frequency PEO Parity Even Odd This bit affects parity 0 even parity 1 odd parity It is effective only if MODI is set in CNTLA parity enabled ICTS PS Clear to Send Prescaler When read this bit gives the state of external pin CTS 0 low 1 high When CTS is high RDRF is inhibited so that incoming r
33. Intetr pt VeCtOES s eoe eet t EO RE URGE RETRATOS Nonmaskable Interrupts sse JUMP VECLOLS Inteft pt Priorities 73 3 e HDI NOR tees Appendix D Circuit Board Reference Powet Program Module ne roe REIR Gore Module 2 ech ner HE HE e MES I O Conversion Module sse 11 2 2020 0440 02 Headers e ratem vae m ERE CE E RARE Display ied Ne i Keypad Interface c ee e edente Appendix E PLCBus PLCB s 5 5 dre adeb e RE Allocation of Devices on the 4 Bit Deviees ua one den tee RE E UNTERE TRE Expansion Bus Software 0 0 PK2600 Table of Contents vii 0 Appendix Serial Interface Board 2 External Dimensions 2 Appendix G Advanced Topics Power Power Failure Detection Circuitry Power Failure Sequence of Events Simulated EEPROM sese Pulse Width Modulation PWM Software PWM Addressing Detail PWM Software Sample Program cies Appendix Battery Battery Life and Storage Conditions
34. LANDSCAPE 0 0 0 7 7 7 0 7 PORTRAIT 7 0 0 0 Figure 3 4 LCD Coordinate System row column PK2600 Hardware Features 29 Digital Inputs Outputs Digital Group 1 The factory default is for the controller digital inputs to be pulled up Figure 3 5 shows the pinout DIGITAL GROUP 1 5 8 Ze 222 2222959227 XD 00 E 13 12 131 009 8 7 6 54 3 2 1 0000000000000 0 0 0 0 0 0 0 0 0 0 0 0 25 24 23 22 21 20 19 18 17 16 15 4 x v 10 x r zz X 0000 55 22222522 Figure 3 5 Digital Group 1 Pinout Digital Group 2 The factory default is for sinking controller digital outputs Figure 3 6 shows the pinout 5 8 aaa 8 2 2 2 gt gt gt lt lt lt lt gt OOO rE LET 2 13 1211 109 8 7 6 5 43 2 1 6 6 0 0 6 6 0 60 6 0 6 6 0 0 0 0 0 0 0 0 0 0 0 0 0 25 24 23 22 21 20 19 18 17 16 15 4 0 9 5 SEE 2 2 gt 2 lt SSS SS gt ee Figure 3 6 Digital Group 2 Pinout Chapter 4 Hardware Configurations provides instructions GY to reconfigure these two groups of digital I O in groups of eight 30 Hardware Features PK2600 Analog Inputs The eight conditioned analog inputs on the controller are connected directly to the ANALOG INPUTS DB25 connector on the PK2600 Th
35. ON at 60 C The absolute maximum power that the driver IC can dissipate depends on several factors The sinking IC s saturation voltage 18 1 6 V DC max per channel The sinking driver s source voltage must range from 2 V to 48 V DC Specifications 131 PK2600 Sourcing Driver The sourcing driver IC can handle a maximum of 1 38 A 250 mA for any channel or 75 mA per channel on average if all channels are ON at 60 C The sourcing IC can dissipate a maximum of 2 2 W The saturation voltage is 1 6 V DC max per channel The sourcing driver s source voltage must range from 3 V to 30 V DC The minimum output sustaining voltage is 15 V DC Operating the driver at more than 15 V without providing for energy dissipation may destroy the driver when an inductive load is connected For more information on sinking and sourcing high voltage GY drivers referto the Motorola DL128 or Allegro AMS 5022 linear data books 132 Specifications 0 1 i KJ ArPENDIX MEMORY IO AND INTERRUPT VECTORS Appendix C provides detailed information on memory and an I O map The interrupt vectors are also listed PK2600 Memory I O Map and Interrupt Vectors 133 Memory The controller board and the display board each have a Z180 microproces sor Figure C 1 shows the memory map of the 1M address space 1024K Socket U8 RAM 0x80000 512K Socket U7 EPROM 0x00000 Figure C 1 Memo
36. PK2600 controller board PK2600 Hardware Configurations 47 Figure 4 9 shows a typical sinking driver output configuration DC External lt 500 mA channel 6 Load Sc 6 m 8 gt Freewheel 1 Diode gt ULN2803 Figure 4 9 Sinking Driver Output Figure 4 10 shows a typical sourcing driver output DC Ko a o 5 External Freewheel Load Diode L UDN2985 Figure 4 10 Sourcing Driver Output Z World also offers all PK2600 integrated control systems for quantity orders with factory installed sourcing drivers For ordering information call your Z World Sales Representative at 530 757 3737 48 Hardware Configurations PK2600 Connections to Bank A are made on headers 116 and 119 Connections to Bank B are made on headers H7 and H10 The pinouts for headers H6 H7 H9 and H10 are shown in Figure 4 7 See Appendix B Specifications for detailed specifications ev on the high voltage drivers Using Output Drivers The common supply for all eight channels supplied by a driver chip is called K and is labeled as such on the PK2600 pinouts K must be powered up to allow proper operation The K connection performs two vital functions to the high voltage driver circuitry on the PK2600 1 supplies
37. _flashInfo initial ized by sysChk2ndF lash src points to the beginning of the block in root memory to be copied to the second flash EPROM dest a physical address points to the beginning of the block in the second flash EPROM mapped to memory space len is the length of the block to be copied Flash EPROM is rated for 10 000 writes In practice flash EPROM has performed for up to 100 000 writes Z World recommends that any writes to the flash EPROM be made by the programmer rather than automatically by the software to maximize the life of the flash EPROM PK2600 Software Development 109 Other Software For watchdog information refer to descriptions of the function hitwd in your Dynamic C manuals e For simulated EEPROM information refer to descriptions of the functions ee_rd and ee wr in Appendix For power failure flag information refer to the descriptions of the function _sysIsPwrFail and sysIsPwrFail in your Dynamic C manuals For resetting the board information refer to descriptions of the func tions sysForceSupRst sysIsSuperReset sysIsSuperReset sysForceReset _sysIsWDTO and sysIsWDTO in your Dynamic manuals Sample Programs Two sample programs have been written to illustrate the use of the display board and the controller board These sample programs are available from Z World Web site http www zworld com in the Products and Services section for the PK2600 With a power supply c
38. are connected directly to the A D converter Operating Modes and Configuration User selected gain and bias resistors determine voltage ranges for the conditioned input signals Standard PK2600 integrated control systems come with 2370 Q gain resistors and 39 2 kQ bias resistors These resistors provide a gain of 0 25 for a unipolar input signal range of 0 V to 10 Table 4 5 lists the gain and bias resistors for other selected input voltage ranges A step by step procedure follows to explain how to calculate the values for the gain and bias resistors for a particular input voltage range Rbias Q PK2600 Table 4 5 Hepresentative Analog Input Setups 8060 6650 4990 4530 2870 1690 931 392 39 200 20 000 10 000 4020 Rgain Gain Q 0125 1180 0250 2370 0 500 4750 0 625 5900 1 250 11 800 2 500 23 700 5 000 47 500 12 500 118 000 0 250 2370 0 500 4750 1 000 9530 2 500 23 200 Input Voltage Range V 10 0 to 0 5 0 to 45 0 2 5 to 42 5 2 0 to 42 0 1 0 to 1 0 0 5 to 40 5 0 25 to 40 25 0 10 to 40 10 0 to 10 0 0 to 0 0 to 5 0 to 41 0 52 Hardware Configurations 1 Set up the analog inputs The first eight analog input signals are routed to the inverting input of one of the eight op amps in U9 and U12 The op amps in U9 and U12 operate in an inverting configuration User selectable resistors set the gain and bias voltages of the amplifiers The 10 input resistors are fixed
39. desired operating mode 3 Cycle the power off and back on to switch the PK2600 to the selected mode Using Run and Program Modes Example 1 Place the PK2600 display in Program mode and cycle the unit s power 2 Select a sample program from the Dynamic C SAMPLES QVGA directory and open the program 3 Select the Compile command from the Compile menu or press on the PC keyboard 4 Ifno errors are detected Dynamic C compiles the program and auto matically downloads it into the display s flash memory 5 Return the DIP switch setting to Run mode and cycle the power off and on to reset the PK2600 The downloaded program begins to run immediately The program is now loaded in the PK2600 display s flash EPROM This program runs automatically every time the PK2600 powers up in Run mode until you load another program Similar steps can be followed to download a program into the controller s flash memory The downloaded program begins to run as soon as the power is applied Pay close attention after downloading programs to the controller so that any electronic or mechanical devices connected to the PK2600 do not cause any damage PK2600 Hardware Features 27 Liquid Crystal Display LCD The 240 x 320 LCD supports both graphics and text Automatic contrast control is built in so that the contrast once set does not drift as the PK2600 warms up or is moved Figure 3 2 provides a block diagram o
40. ersetzen Entsorgung der gebrauchten Batterien gem b den Anweisungen des Herstellers Attention French Il y a danger d explosion si la remplacement de la batterie est incorrect Remplacez uniquement avec une batterie du m me type ou d un type quivalent recommand par le fabricant Mettez au rebut les batteries usag es conform ment aux instructions du fabricant Cuidado Spanish Peligro de explosi n si la pila es instalada incorrectamente Reemplace solamente con una similar o de tipo equivalente a la que el fabricante recomienda Deshagase de las pilas usadas de acuerdo con las instrucciones del fabricante Waarschuwing Dutch Explosiegevaar indien de batterij niet goed wordt vervagen Vervanging alleen door een zelfde of equivalent type als aanbevolen door de fabrikant Gebruikte batterijen afvoeren als door de fabrikant wordt aangegeven Varning Swedish Explosionsfara vid felaktigt batteribyte Anv nd samma batterityp eller en likvardigt typ som rekommenderas av fabrikanten Kassera anvant batteri enligt fabrikantens instruktion PK2600 Battery 191 Blank 192 Battery PK2600 AdcMode 200 addresses EEPROM simulated 180 00 165 MOLES oett 165 other controller board registers 7 139 164 5 analog inputs 52 8 bias resistors 54 calibrating 58 calibration constants 99 condi
41. mapping from DIGITAL GROUP 2 to the headers on the controller board Table 0 3 PK2600 Digital Group 2 Pin Mapping Controller Digital Signal Controller Pin No PK2600 DB25 Pin No HVB00 1 1 3 14 HVB02 5 2 HVB03 7 15 GND T 9 11 12 13 4 E 2 3 05 T 4 16 HVB06 6 4 HVB07 8 17 10 9 10 1 5 09 3 18 10 5 6 HVB11 0 7 19 9 24 25 HVBI2 2 7 m 4 20 HVB14 6 8 15 8 21 K 10 22 23 150 Circuit Board Reference PK2600 Figure D 5 shows the pinouts for controller board headers 116 117 H9 and H10 which are connected to DIGITAL GROUP 1 and to DIGITAL GROUP 2 on the PK2600 Bank A Bank B H6 H7 HVAO8 1 2 HVA12 08 1 M 2 HVB12 HVAO9 3 4 HVA13 09 3 4 HVA10 5 6 HVA14 10 5 6 HVB14 HVA11 7 e 8 5 HVB11 7 86 8 HVB15 GND 9 GND 9 9 10 00 HVA04 00 1 M 2 4 HVA01 3 4 5 HVB01 4 5 34 02 5 6 6 02 5 6 6 HVAO3 7 7 HVBO3 7 e 8 7 GND 9 10K GND 9 6 ok Figure D 5 Pinouts for PK2600 Controller Board Digital I O PK2600 Circuit Board Reference 151 Table D 4 provides a pin mapping from the ANALOG INPUTS to the h
42. out puts outputs can be sink ing or sourcing DIGITAL GROUP 1 16 digital inputs Outputs can be sinking 2 sourcing 16 digital outputs DIGITAL GROUP 2 sinking 8 digital inputs amp 8 digital outputs OR 16 digital in puts Conditioned inputs can be reconfigured for different voltage ranges 8 conditioned inputs over ANALOG INPUTS range 010 V to 10 V 2 unconditioned inputs Core module may be re placed with one having 256K flash EPROM and or 9 216 MHz clock 32K SRAM 128K flash Memory Clock EPROM 18 432 MHz clock Display PK2600 software ad justable LCD Contrast J Software or manually ad PK2610 manually ad justable justable LCD Background White Blue See Chapter 4 Hardware Configurations for information on how to change the jumper settings for alternative configurations For ordering information or for more details about the various options and prices call your Z World Sales Representative at 530 757 3737 PK2600 Overview 17 Development and Evaluation Tools Developer s Kit The PK2600 is supported by a Developer s Kit that includes everything needed to start development with the PK2600 Software Dynamic C Z World s Windows based real time C language development system is used to develop software for the PK2600 The host PC down loads the executable code through the SIB2 or one of the serial ports to flash EPROM Lib
43. period If necessary call Z World Technical Support at 530 757 3737 for assistance PK2600 Advanced Topics 187 Blank 188 Advanced Topics PK2600 NS EN _ iw APPENDIX BATTERY Appendix H provides information about the onboard lithium backup batteries PK2600 Battery 189 Battery Life and Storage Conditions The batteries on the PK2600 controller board and display board will provide approximately 9 000 h of backup time for the onboard real time clock and static RAM However backup time longevity is affected by many factors including the amount of time the PK2600 is unpowered and the static RAM size Most systems are operated on a continuous basis with the battery supplying power to the real time clock and the static RAM during power outages and or during routine maintenance The time estimate reflects the shelf life of a lithium ion battery with occasional use rather than the ability of the battery to power the circuitry full time The battery on the controller board has a capacity of 190 mA h At 25 C the real time clock draws 3 uA when idle and the 32K SRAM draws 2 uA Ifthe PK2600 were unpowered 100 percent of the time the battery would last 38 000 hours 4 3 years The battery on the display board has a capacity of 165 mA h At 25 C the real time clock draws 3 uA when idle and the 128K SRAM draws 4 uA If the PK2600 were unpowered 100 percent of the time the battery would last 23 570 hour
44. serial communication 32 62 76 100 0 7 101 terminating resistors 65 84 RIS etes Ren 85 Run mode sess 26 running sample program 24 RNS hot 84 5 sample programs analog 1 99 digital inputs 92 digital outputs 94 font and bitmap conversion 118 97 187 serial communication 101 use of display and controller boards 110 use of controller board PK26CONT C 111 use of display board 26 111 SOG 32 62 5 485 101 5 1100 162 select PLCBus 80017658 168 Serial Channel 0 block diagram 80 Serial Channel 1 80 serial 6180618 32 62 Channel 0 32 62 Channel 1 32 62 Channel 32 62 Channel 32 62 configuration 63 dflVers 101 networking 2 2222 sss 65 operating modes 63 Index 201 printing 116 Program mode 26 programming 18 51 95 addressing 181 advanced programming 1
45. using input functions Follow the suggested protocol The software drivers are easier to use but are less efficient in some cases Table E 5 lists the libraries Table E 5 Dynamic C PLCBus Libraries Library Needed Controller DRIVERS LIB All controllers EZIOTGPL LIB BL1000 EZIOLGPL LIB BL1100 EZIOMGPL LIB BL1400 BL1500 EZIOPLC LIB BL1200 BL1600 PK2100 PK2200 ZB4100 EZIOPLC2 LIB BL1700 PK2600 PBUS_TG LIB BL1000 PBUS_LG LIB BL1100 BL1300 PLC EXP LIB BL1200 BL1600 PK2100 PK2200 PK2600 PLCBus 167 There are 4 bit and 8 bit drivers The 4 bit drivers employ the following calls void eioResetPlcBus Resets all expansion boards on the PLCBus When using this call make sure there is sufficient delay between this call and the first access to an expansion board LIBRARY EZIOPLC LIB EZIOPLC2 LIB EZIOMGPL LIB void eioPlcAdr12 unsigned addr Specifies the address to be written to the PLCBus using cycles BUSADRO BUSADRI and BUSADR2 PARAMETER addr is broken into three nibbles and one nibble is written in each BUSADRx cycle LIBRARY EZIOPLC LIB EZIOPLC2 LIB EZIOMGPL LIB void setl6adr int adr Sets the current address for the PLCBus All read and write operations access this address until a new address is set PARAMETER adr is a 16 bit physical address The high order nibble contains the value for the expansion register and the remaining three 4 bit nibbles form
46. voltages between 48 V DC and 48 V DC The inputs can detect logic level signals and have a nominal logic threshold of 2 5 V DC This means an input returns a 0 if the input voltage is below 2 5 V DC and a 1 if the input voltage is above 2 5 V DC The inputs can be pulled up to 5 V or down to ground A low pass filter on each input channel has a time constant of us 4 5 kHz 220 The digital inputs may be configured as pull up or pull down in groups of fours and eights The configuration of each input should be determined by normal operating conditions power down mode and possible failure modes including open or shorted conditions These factors will influence your decision about configuring the inputs as pull up or pull down Operating Modes and Configuration Inputs may be pulled up to 5 V or pulled down to ground by configuring the jumpers on the PK2600 controller board headers J2 and J3 J2 jumpers select pull up pull down resistors for Bank A Jumpers on J3 select pull up pull down resistors for inputs for Bank B To change an input from the factory default of pull up simply place a jumper across the appropriate two pins of J2 and or J3 Tables 4 1 and 4 2 illustrate the jumper settings for pull up and pull down configurations for the controller board s Bank A and Bank B inputs m The factory default is for the digital inputs to be pulled up to 5V 42 Hardware Configurations PK2600 Table 4 1 PK2600 Co
47. x coordinate of the bitmap left edge y is the y coordinate of the bitmap top edge bmWidth is the width of the bitmap bmHeight is the height of the bitmap bmPtr is a pointer to the bitmap The bitmap format is a column with the major byte aligned for each column Touchscreen Functions The following functions from the Dynamic C KP LIB library are used to control the touchscreen void kpInit int changeFn Initializes the kp module Call this function before calling other functions in this library If the default keypad scanning routine will be used use kpDefInit instead of this function PARAMETER changeFn is a pointer to a function that will be called when the driver detects a change when kpScanState 15 called Two arguments are passed to the callback function The first argument is a pointer to an array that indicates the current state of the keypad The second is a pointer to an array that indicates what keypad positions are changed and detected by kpScanState The byte offset in the array represents the line pulled high row number and the bits in a byte represents the positions column number read back int kpScanState Scans the keypad and detects any changes to the keypad status If kpInitis called with a non NULL function pointer that function will be called with the state of the keypad This function should be called periodically to scan for keypad activities RETURN VALUE 0 if there is no change t
48. 0 to 0 25 we change the waveform from 0x01 0x03 OxOE OxOE OxOE OxOE 0x00 OxOE OxOE OxOE OxOE OxOE OxOE 0x02 OxOE OxOE to 0x01 0x03 OxOE OxOE 0x00 OxOE OxOE OxOE OxOE OxOE OxOE OxOE OxOE 0x02 OxOE OxOE The underlined edges are the only ones affected Of course the waveform pattern buffer may have the pattern repeated many times Each occurrence of the pattern in the buffer must be modified in the same manner However although the use of no op edges seems to be compute time inexpensive it does require the application to maintain the location of the non no op edges In other words besides the waveform pattern buffer the application program must maintain a duty cycle variable for each channel Recall that the second problem of changing the duty cycle is the require ment for the change to be phase synchronized to the current waveform Many of the involved issues are similar to those of refreshing the DMA counter and pointer The driver software library provides the function dmapwmSwBuf to switch waveform pattern buffers PWM Software The functions shown below are second level functions that allow more PWM outputs They are also more complex and require a more in depth understanding of PWM and DMA generation These functions are located in EZIODPWM LIB void dmapwmSetBuf char pBufStart char bufLength256 unsigned step char outChar Formats part of the waveform pattern buffer fo
49. 00 ArPENDIX ADVANCED TOPICS Appendix G provides more advanced information to help the user needing to implement special applications The following topics are included Power Management Simulated EEPROM e Pulse Width Modulation Software PK2600 Advanced Topics 177 Power Management Power Failure Detection Circuitry Figure G 1 shows the power fail detection circuitry of the PK2600 controller board 1 581 UC ON crest n 51kQ 1 pe CM7200 1N5230 4 99 kQ 196 Figure G 1 Controller Board Power Failure Detection Circuit Power Failure Sequence of Events Figure G 2 shows the events that occur as the input power fails Power Fails 15 0 14 0 13 0 Unregulated 12 0 DC 11 0 Regulated 5 10 0 9 0 8 0 7 0 Dropout Voltage 6 0 5 0 Input Voltage V 4 0 3 0 2 0 1 0 691 691 691 Asserts Asserts Ceases RESET Operation Time Figure G 2 Power Failure Sequence 178 Advanced Topics PK2600 1 The power management IC triggers a power fail NMI nonmaskable interrupt when the DC input voltage falls within the range of 14 44 V to 14 72 VDC 2 At some point the raw input voltage will not be sufficient for the regulator to provide 5 V DC to the controller board due to dropout voltage At that point the regulated output begins to drop The power management IC triggers a reset when the regulated 5 V DC output falls withi
50. 00 Subsystems 75 Serial Communication The display board has two serial channels that support asynchronous communication at baud rates from 300 bps to 57 600 bps The serial chan nels are factory configured as two 3 wire RS 232 channels Figure 5 5 illustrates the configuration of these serial channels U24 TXA1 4 D A RXA1 R 485 EN485 DE RE B TXAO E gt TOUT RTSO T2IN gt 2 RXAO RXAO R10UT lt RIIN 04 CTS0 oo RX1 R20UT lt R2IN 232A Figure 5 5 Display Board Serial Channels Although the display board may be configured for RS 485 serial communication the factory default RS 232 configuration is required for the connection to the controller board Neither the second RS 232 channel nor the RS 485 channel is acces sible when the display board is used with the PK2600 Serial channel z1 of the display board is connected by a ribbon cable from display board header 18 to serial channel 21 on the controller board through header H13 on the controller board 76 Subsystems 0 691 Supervisor Chip Both the display board and the controller board have an onboard 691 supervisor A voltage divider across the DC input provides a PFI signal to the 691 watchdog supervisor The 691 chip performs the following services e Watchdog timer resets the microprocessor if software hangs e Power failure shutdown and reset e Generates an ea
51. 08 110 124 HPR 84 EFR bit 84 eioBeep 102 61036081 31 99 98 eioBrdAO 97 eioBrdAOR f 97 184 91 eioBrdDO 93 eioBrdInit 98 6102104612 168 169 eioReadDl 169 eioReadD2 169 eioResetPlcBus 168 eioSetupAO1st 97 183 eioWriteWR 170 electrical specifications 126 environmental specifications 126 EPROM 72 180 execution times 135 Exp A DI2 essere 162 expansion boards reset 168 expansion bus 162 167 4 bit drivers sss 168 8 bit drivers sinn tais 170 addresses 166 10068 166 7 digital inputs 167 functions 168 171 rules for devices 166 software drivers 167 196 Index H8 controller board 61 148 H9 controller board 41 49 61 67 148 headers controller board 148 H10 41 49 61 6
52. 1 extra Ox2B IARIL DMA I O Address Register Channel 1 least 0 2 IARIH DMA I O Address Register Channel 1 most 0 2 Reserved Ox2E BCRIL DMA Byte Count Register Channel 1 least Ox2F BCRIH DMA Byte Count Register Channel 1 most 0x30 DSTAT DMA Status Register 0x31 DMODE DMA Mode Register 0x32 DCNTL DMA WAIT Control Register 0x33 IL Interrupt Vector Low Register 0x34 ITC Interrupt Trap Control Register 0x35 Reserved 0x36 RCR Refresh Control Register 0x37 Reserved 0x38 CBR MMU Common Base Register 0x39 BBR MMU Bank Base Register Ox3A CBAR MMU Common Bank Area Register Ox3B 0x3D Reserved Ox3E OMCR Operation Mode Control Register Ox3F ICR I O Control Register PK2600 Memory I O Map and Interrupt Vectors 137 Real Time Clock Registers 0x4180 0x418F Table C 3 lists the real time clock registers Table C 3 Real Time Clock Registers 0x4180 0x418F Address Name Data Bits Description 4180 SECI D0 D7 seconds units il 4181 sECIO D0 D7 seconds tens 4182 MINI D0 D7 minutes units 4183 MINIO D0 D7 minutes tens 4184 HOURI D0 D7 hours units 4185 HOURIO D0 D7 hours tens 4186 DAYI D0 D7 days units 4187 DAY10 D0 D7 days tens 4188 1 D0 D7 months units 4189 MONTHIO D0 D7 months tens 4 YEARI D0 D7 years units 4188 YE
53. 12 DU DDnnnnrn UUTUUU n DIUI d l nnnnnnn bg U18 016 WEE 010 U12 08 06 4 nnmnnn U4 U3 Hi E 9 UUTUUU Bank B Bank A Figure 4 7 PK2600 Controller Board Banks A and B External Connections Bank signals appear on controller board headers H6 and H9 Bank B signals appear on headers H7 and H10 The Bank A digital inputs outputs are brought out to the PK2600 DIGITAL GROUP 1 DB25 connector and Bank B digital inputs outputs are brought out to the DIGITAL GROUP 2 DB25 connector through the I O conversion module PK2600 Hardware Configurations 41 Digital Inputs The PK2600 can provide up to 32 protected digital inputs designed as logical data inputs returning a or 0 Their normal operating range is 20 V DC to 24 V DC and they are protected from
54. 136 Serial Port 1 141 215 4865 101 Index 203 troubleshooting continued communication mode 123 grounding sss 122 operating mode 123 PC COM ports 122 TTL outputs eese 50 U 2985 2 0 45 ULEN2808 5 45 V M 79 7 5 VMIN 79 VRAM 79 watchdog timer 72 77 78 79 software 108 110 124 79 writel2data 171 170 PK2600 Blank 204 Index PK2600 24 Z World Inc 2900 Spafford Street Davis California 95616 6800 USA Telephone 530 757 3737 Facsimile 530 753 5141 WebSite http www zworld com E Mail zworld Zzworld com Part No 019 0061 Revision C Printed in U S A
55. 180 memory cycles execution timing 135 memory map 134 MODO ence Rep 85 iphone 86 87 MOD ertet Rete eet 85 modes addressing 165 changing 222 27 operating sess 26 26 26 standalone 27 86 87 MPBR ERR eene 85 5 e eese 87 edu 86 multiprocessor bit receive error flag esi Recte ies 85 multiprocessor bit transmit 87 multiprocessor enable 86 multiprocessor mode 85 87 N 77 2 power failure TI NMI VEC 142 0 op71BackLight 102 op71SetContrast 102 operating modes 26 Index 199 jumper settings continued display board default settings 158 IO aser 158 7 158 07 158 158 7 158 LCD background 69 serial channel configuration 63 64 Jor seit tite 63 G 64 eee 63 64 K 49 keypad interface 159 keypad programming 117 reading keypad 117 scanning keypad 117 KP OP71 LIB 106 117 kpDefGetKey 107 117 kpDefInit
56. 2 lists the specifications for the protected digital inputs Table B 2 Protected Digital Input Specifications Protected Digital Inputs Absolute Maximum Rating Input Voltage 20 V DC to 24 V DC protected against spikes to 48 V Logic Threshold 2 5 Input Current 15 mA 10 15 mA Leakage Current 5uA Noise Spike Filter 220 us Faster than 656 Hz Not slower than 1 52 ms input at 5 V DC Low pass filter RC time constant Frequency Response worst case PK2600 Specifications 129 Frequency Response for the Protected Inputs The protection network comprises a low pass filter with a corner frequency of 724 Hz For example if the driving source of a protected input is a step function that step becomes available 1 38 ms later as a valid 5 V DC CMOS input to the PK2600 controller board s data bus Equation B 1 shows how R and C affect the frequency response of the protected inputs 00 through 15 J 276 CT 222 10 10 1 724 Hz f 1 38 ms at 0 707 of full input value Figure B 2 shows the protected input circuitry for protected inputs HVAOO to HVA15 on the controller board in the factory default pulled up configu ration 5 V 5V e High 10 ko Impedance 1 Rn Digital Input 9 Data 22 kQ CMOS Bus C z10nF Input Figure B 2 Protected Input Circuitry HVAOO through HVA15 If a fa
57. 2600 Memory I O Map and Interrupt Vectors 139 Display Board Table C 5 lists the other registers Table C 5 Other Display Board I O Addresses PK2600 Description Chip Select 1 Chip Select 2 Chip Select 3 Chip Select 4 Chip Select 5 Chip Select 6 Watchdog Flash EPROM write enable Bit 0 is the power failure NMI state Watchdog output Data Bits Address 4000 403F 4040 407F 4080 40 40C0 40FF 4100 413 4140 417 41 0 41 8000 C000 000 140 Memory I O and Interrupt Vectors Interrupt Vectors Table C 6 presents a suggested interrupt vector map Most of these interrupt vectors can be altered under program control The addresses are given here in hex relative to the start of the interrupt vector page as determined by the contents of the I register These are the default interrupt vectors set by the boot code Table C 6 Interrupt Vectors for 2180 Internal Devices Address Name Description NMI VEC Used for power failure detection INTO Available for use 0x00 VEC Available for use as expansion bus attention INTI vector 0x02 INT2 VEC Not available 0x04 PRTO_VEC PRT Timer Channel 0 0x06 PRT1 VEC PRT Timer Channel 1 DMAO VEC DMA Channel 0 0x08 Ox0A DMA1_VEC DMA Channel 1 0 0 5 Avail
58. 2600 controller board is fairly compli cated This is because it uses the clock output from communication port 1 CKA1 to drive the request line DMA Channel 0 in edge detection mode The simple interface previously described in Chapter 4 provides PWM support for output 0 to output 3 If the application requires more PWM channels or require specific frequencies or precision the application engineer may need to make trade offs This section describes how PWM channels are driven as well as how to customize PWM resource allocation to compromise number of modulated channels frequency and resolution 1 Determine the number of channels frequency and resolution A pulse width modulated waveform has a frequency and a resolution The frequency states how many times the pattern repeats itself in a second Hz The resolution states how many divisions within one waveform can be resolved distinguished As a collection the PWM driver also needs to know the total number of channels to be pulse width modulated The calculations in this section are made with the assumption that all channels have the same frequency and resolution The clock output from communication port 1 CKA1 must have a fre quency f B 2 where which f is the frequency of CKA1 is the number of channels PW modulated f is the frequency of each channel and is the resolu tion in number of divisions per wave For example the driver interface eioSetu
59. 3 D2 and D1 determine which output in a group is selected Data bit DO determines the state of the output Data bits D7 through D4 are unused PK2600 Software Development 93 Table 6 3 shows the address and data values used with the outport function for writing to the digital outputs 2 data data ala N CA N w 5 gt 514 l ele AJN ele Mm Table 6 3 Digital Output Addresses Address 0x4110 0x4110 0x4110 0x4110 0x4110 0x4110 0x4110 0x4110 0x4118 0x4118 0x4118 0x4118 0x4118 0x4118 0x4118 0x4118 Bank A 00 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 9 H6 ON data 1 3 5 7 9 11 13 15 3 0 OFF data 0 10 12 14 10 Address 0x4100 0x4100 0x4100 0x4100 0 4100 0 4100 0 4100 0 4100 0 4108 0 4108 0 4108 0 4108 0 4108 0 4108 0 4108 0 4108 00 15 i 10 6 11 The factory default is for Bank B to be configured for digital PK2600 outputs Sample Program The sample program BL17DIO C shows how to use the digital I O It can be found in the Dynamic C SAMPLES BL17XxX subdirectory
60. 4 4 bit bus operations 163 164 166 5 x 3 addressing mode 165 691 supervisor 77 79 142 system reset 79 8 bit bus operations 163 165 167 A A D converter internal test voltages 60 power down mode 61 7 13 1 2 163 164 16 7 16 sourcing driver kit 16 PK2600 BUSADRO 163 165 BUSADRI 164 165 02 164 5 170 171 BUSRD 167 168 169 171 BUSRDI 167 168 BUSWR 2 168 circuit board assembly 37 5 CKAT disable es 85 CKAI TEND 85 ttis 85 Clear to Send prescaler 87 clock 1 79 108 time date 79 108 clock frequency 7 86 88 7200 72 73 CMOS 2222 2 50 CNTLA sect acce 84 CNIEB teen 86 common problems programming errors 124 communication Dynamic 2 22 222 4 142 RS232 eee 76 RS 485 odo e 76 serial 76 80 83 85 86 88 136 computing 110016 74 connections PC via SERIAL PORT 1 22
61. 7 148 61 148 65 148 EI fos costes tects ih 65 148 HIA ai eile ees 65 148 15 65 148 7 45 156 PR 45 154 148 41 49 61 67 148 7 41 49 61 67 148 PSone eee HS 61 148 H9 41 49 61 67 148 eden 148 p 42 63 154 42 156 Mess 63 65 68 154 Josue 148 65 155 JS entes 51 63 155 display board MER 28 157 157 lp 157 28 157 157 Ios A tiem d 157 157 157 Jo tee 158 IP lis b es 69 158 JP2 nie eve 69 158 158 7 158 Index 197 glSetBrushType 103 114 103 114 Q1XFontInit 103 116 glXPutBitmap 106 115 graphics programming drawing primitives 114 draw a 01111185 ee 115 fillacircle 115 fill a polygon 115 plot a 115 plot a line 115 plota 1 114 plot a polygon 115 font and bitmap conversion 118 initialization 114 keypad programming 117 printing text eese 116 H controller board 148 10 controller board 41 49 61 67 148 HII controller board
62. 81 PWM continued buffers ie eek 186 DMA refresh 97 duty cycle atte 97 initialization 97 186 sample program 97 sample programs 187 software COMPIEX sese 185 waveform pattern buffer 185 R RAM ete eue 72 StatlC acre t sees 77 79 ROR good ERREUR 84 81 84 86 07 86 read data register full 84 readi2data sonde 169 171 read4data 170 readBdata uec 171 reading data on the PLCBus 164 169 real time clock RTC 72 79 108 software 108 110 124 receiver data register 84 receiver data register full 84 receiver 08016 86 receiver interrupt enable 84 receiver interrupts 81 83 84 receiver shift register 84 registers VA EA E 136 request to send 85 nici eels 77 79 179 expansion boards 168 software 108 110 124 PK2600 specifications 125 145 electtical as s 126 environmental 126 mechanical 126 SSO siena ie RR 86 86 SS2 5o id Qe 86 standalone mode 27 STATO 7 83 subsystems sess 72 supervisor 691 77 79 142 System
63. A 232RXB 6 232RTSB RS485A 7 6 8 RS485B 8 GND 9 10 RS485A GND 10 RS485B Channel A to Serial Port 2 Channel B to Serial Port 3 Figure D 7 Pinouts of PK2600 Controller Board Serial Ports PK2600 Circuit Board Reference 3 Table 0 5 Controller Board Jumper Settings Factory Default Connected Connected Connected Connected Connected Connected Connected Connected Connected continued PK2600 Jumper Settings Table D 5 lists the jumper configurations for the configurable headers on Description Connect for HVB00 HVBO7 sinking output Connect for HVB00 HVBO7 sourcing output Connect for 08 15 sinking output Connect for HVB08 HVBI5 sourcing output Connect for HV A0 HV A03 inputs pulled up Connect for HV A00 HV A03 inputs pulled down Connect for HV A04 HV A07 inputs pulled up Connect for HV A04 HV 07 inputs pulled down Connect for HVA08 HVAI5 inputs pulled up Connect for HVA08 HVAI5 inputs pulled down Connect for 5 wire RS 232 DCD and DTR on Channel A Connect for 2 wire RS 485 on Channel A Connect to enable RS 485 termination resistors for Channel 1 Connect for INTO serial communication on Channel A and Channel B disconnect to allow INTO for user application Connect to allow INT1 to be used as AT on PLCBus disconnect for INT1 external use only Pins 10 12 1 2 3 4 7 8 a the controller board Header
64. AR10 D0 D7 years tens 41800 WEEK D0 D7 weeks 482 TREGD D0 D7 Register D 48E D0 D7 Register E 418 D0 D7 Register F 138 Memory I O and Interrupt Vectors PK2600 Other Registers Controller Board Table C 4 lists the addresses that control I O devices external to the Z180 processor Table C 4 Controller Board External I O Device Registers Address Name R W Function 0x4000 EN485A W DO RS 485 Channel 1 Enable 0x4040 ENDII DO D7 Digital Input 00 15 0 4040 485 W DO 88 485 Channel B Transmit Enable 0x4042 ENDI2 R DO D7 Digital Input 16 31 0 4042 TE485A W DO RS 485 Channel A Transmit Enable 0 40 0 ADEOC R DO ADC end of conversion 0 4000 ADOUT R D0 ADC output Ox40DO ADIN W D2 ADC instruction 0x40D0 ADCS D1 ADC chip select 0x40D0 ADCLK W DO ADC clock 0x40E0 LCD R W PLCBus LCD line 0 40 0 STB R W PLCBus strobe 0x4100 ENHV1 W Digital Output 00 07 0 4108 ENHV2 W Digital Output 08 15 0 4110 ENHV3 W Digital Output 16 23 0408 ENHV4 W Digital Output 24 31 ox4120 6 R W Serial Channel B Control 1 R W Serial Channel A Control 2 R W Serial Channel B Data 3 R W Serial Channel A Data 04142 LED W DO LED status 0x417F R D7 Run Program Mode 26 00 ID PK
65. Board Reference 147 PK2600 Headers Table D 1 lists the input output and serial communication headers Table D 1 Controller Board Headers Header Function H4 Not used H6 Digital input output Bank A H7 Digital input output Bank B H8 Analog input H9 Digital input output Bank A H10 Digital input output Bank B H11 Analog input H12 Channel 0 RS 232 serial communication port H13 Channel 1 RS 232 connected to display board H14 Channel A RS 232 RS 485 serial communication port 15 Channel RS 232 RS 485 serial communication port Power input 5 PLCBus 148 Circuit Board Reference PK2600 Table D 2 provides a pin mapping from DIGITAL GROUP 1 to the headers on the controller board Table D 2 PK2600 Digital Group 1 Pin Mapping Controller Digital Signal Controller Pin No PK2600 DB25 Pin No 00 1 1 HVAOI 3 14 HVA02 5 2 3 5 7 15 GND F 9 11 12 13 HVA04 3 2 3 HVA05 T 4 16 HVA06 6 4 HVA07 8 17 K 10 9 10 HVAOS 1 5 09 3 18 HVA10 5 6 7 19 GND E 9 24 25 12 E 2 7 HVA13 T 4 20 14 6 8 HVAIS 8 21 10 22 23 PK2600 Circuit Board Reference 149 Table D 3 provides a pin
66. Digital Outputs Up to 32 high voltage high current digital outputs are possible on the PK2600 The digital outputs can be configured in groups of eight for either sinking or sourcing operation by setting jumpers and installing the appropriate driver ICs Sinking drivers can sink up to 500 mA at voltages up to 48 V DC Sourcing drivers can source up to 250 mA at voltages up to 30 V DC All outputs are diode protected against inductive spikes TTL CMOS level outputs are also possible by bypassing the driver ICs This option is for quantity orders only and should be performed at Z World s manufacturing facility High voltage outputs are diode protected against inductive spikes All outputs are individually addressable Operating Modes and Configuration The digital inputs and outputs are divided into two banks Bank A and Bank B In the factory default digital outputs occupy Bank B and digital inputs are located on Bank A In order for a bank to be configured as an output the appropriate interface ICs must be installed Z World recom mends that this be done only at Z World s manufacturing facility High Voltage Drivers Outputs may be configured for either sinking or sourcing current The configuration is determined by the type of driver ICs installed and the jumper settings For Bank A U5 drives outputs 8 15 and U15 drives outputs 0 7 For Bank B U7 drives outputs 8 15 and U17 drives outputs 0 7 The jumpers placed on H3 configu
67. FERENCE Appendix D provides comprehensive information about the individual boards in the PK2600 assembly PK2600 Circuit Board Reference 145 Power Program Module Figure D 1 shows the dimensions of the power program module Core Module Figure D 2 shows the dimensions of the CM7200 core module _ zx 84 5g 2g c9 Fu Y v LY 4 096 25 _ 2 05 52 Figure 0 1 Power Program Figure D 2 CM7200 Core Mdule Module Dimensions Dimensions Conversion Module Figure D 3 shows the dimensions of the power program module 107 3 768 Ea 1 452 95 7 36 9 0 600 2 15 2 1 921 0 761 48 8 19 6 450 5 164 Figure D 3 I O Conversion Module Dimensions 146 Circuit Board Reference PK2600 Controller Board Figure D 4 shows the locations of the headers and the dimensions of the IH 14r 13 T PERSE FERES 12 gt Swi dh J5 jE as o e e 58 J4 1 1 035 26 3 2 775 70 5 05 77 5 controller board Q H8 H10 me 4X Fot N H11 H7 uu 23 Poe F1 6 Figure D 4 Controller Board Headers and Dimensions Circuit
68. I O expansion via built in PLCBus The PLCBus uses inexpensive off the shelf Z World expansion boards Display The display offers the following features e LCD 240 320 4 VGA LCD with touchscreen on PK2600 e Contrast control software controlled contrast is enabled disabled with jumper settings automatic temperature compensation for LCD contrast changes There is also an opening to access the contrast adjustment manually Backlight software controlled cold cathode fluorescent backlighting e Memory 128K SRAM 256K flash EPROM for program 256K flash EPROM for screen bitmaps GY Appendix provides detailed specifications for the PK2600 PK2600 Overview 15 Options The PK2600 has two versions Table 1 1 lists their standard features Table 1 1 PK2600 Series Features Features PK2600 Standard integrated system with serial graphic display touchscreen blue and white screen LCD bezel mount software contrast control 2610 PK2600 with no touchscreen manual contrast control The PK2600 may be used in either a portrait or a landscape orientation Flexibility and Customization The PK2600 was designed with customization in mind The design was optimized for cost effective quick turn custom manufacturing Surface mount technology is used extensively in order to reduce both size and cost while providing the flexibility to meet individual design needs For quantity orders
69. K2600 high voltage drivers iver 49 specifications 131 high voltage outputs 45 78 79 I O conversion module dimensions sssse 146 expansion 68 rne Ires TI 77 inport 82 91 134 142 168 171 169 input voltage 179 inputs outputs 136 MAP 136 SPACE 136 int type specifier 186 124 interface asynchronous serial ports 80 serial communications 88 interrupts 81 83 84 141 142 166 163 interrupt service routines 142 interrupt vectors 81 141 142 default 2 22 141 nonmaskable 142 power failure 142 179 priorities 143 166 0 7 Serials didt t RR 142 ISR See interrupt service routines J Jl controller board 148 display board 28 157 display board 157 198 Index literal C term USO A Porcine Madan 124 lithium battery 0 0 0 190 M mechanical dimensions 128 mechanical specifications 126 memory random 800688 n 77 79 read only suse
70. NFIGURATIONS Analog inputs Serial Channels PLCBus Liquid Crystal Display PK2600 Hardware Configurations 35 The configurations described in Chapter 3 are the factory default configu rations The configurations are available without having to open the PK2600 enclosure Other configurations are possible and are described in this chapter Z World offers the PK2600 for quantity orders with these other configurations set at the factory For ordering information call your Z World Sales Representative at 530 757 3737 PK2600 Assembly The PK2600 assembly is contained in an enclosure Remove the back cover from the enclosure by removing the two 4 x 1 3 8 screws shown in Figure 4 1 All power to the PK2600 must be disconnected e AN CAUTION High Voltage H Transformer Only qualified persons may open this case ANALOG INPUTS SERIAL PORT 1 PROG ERUN DC CONTROLLER 5 a 5 DISPLAY 2 amp DIGITAL GROUP 1 SERIAL PORT 3 2292 8 2 Q 0 a POWER Gum 2900 SPAFFORD ST DAVIS CA 95616 SIN 9 1 530 757 3737 WWW ZWORLD COM i Figure 4 1 PK2600 Back Cover Attachment The PK2600 assembly has the following five layers from top to bottom 1 Power program module 2 I O conversion module and CM7200 core module 3 Controller board 4 Display board 5 LCD 36 Hardware Configurations PK2600
71. RS 232 port supplies a large current most commonly on portable and industrial PCs some RS 232 level converter ICs go into a nondestructive latch up Connect the RS 232 cable after power up to eliminate this problem PK2600 Repeatedly Resets Ifthe program fails to hit the watchdog timer periodically the watchdog timer causes a reset every 1 0 seconds When you debug a program using the Dynamic C debugger Dynamic C hits the watchdog timer If your program does not hit the watchdog timer then you will have trouble running your program in standalone mode To hit the watchdog make a call to the Dynamic C library function hi twd Dynamic C Loses Serial Link If your program disables interrupts for a more than 50 ms Dynamic C may lose its link with the PK2600 PK2600 Troubleshooting 123 Common Programming Errors Values for constants or variables out of range Table A 1 lists accept able ranges for variables and constants Table A 1 Ranges of Dynamic C Function Types Type Range int 32 768 25 to 432 767 25 1 long int 2 147 483 648 2 to 42147483647 2 1 float 1 18 x 107 to 3 40 x 10 char 0 to 255 Mismatched types For example the literal constant 3293 is of type int 16 bit integer However the literal constant 3293 0 is of type float Although Dynamic C can handle some type mismatches avoiding type mismatches is the best practice Counting up from or down to one i
72. The function kpScanState must be called periodically to scan the keypad for changes In a cooperative multitasking big loop style this function should be called every 25 ms or so If you are using a real time kernel you can also attach this function to one of the tasks and have it invoked approximately every 25 ms Note that this function scans for changes but it does not report what was changed Reading Keypad Activities The function kpDefGetKey returns the interpretation of the state change detected by kpScanState into key activities The means that the kpDefGetKey function must be called no less frequently than kpScanState to ensure no key activity is lost The function kpDefGetKey returns an integer If the integer is 1 no key activity was detected Otherwise bits 0 2 indicates the index of the sense line of the key column and bits 3 5 indicate the index of the drive line of the key 7 row Bit 8 indicates whether the key has been pressed the key was pressed 11 bit 8 is a 1 Note that if two key activities occur between two calls to kpScanState only one key activity is interpreted by the kpDefGetKey function even though both activities may be registered by the kpScanState function The priority of key interpretation is from drive line 0 highest priority to drive line 7 On the same drive line the priority is from sense line 0 highest priority to sense line 7 Once a key activity is detec
73. When the function returns CKA1 of communication port 1 generates clock pulses at cka1rate 19 2 kHz to DREQO DMA Channel 0 would then perform memory to I O transfer for each clock pulse falling edge PARAMETERS phyBuffer256 is the 256 byte aligned physical address of the buffer in 256 byte units In general if the buffer is defined as an array in root memory that is oftype char the following expression should be passed to this parameter unsigned xmadr buffer 255 lt lt 8 in which buffer is a pointer oftype char to the array bufsize256 is the size of the buffer in 256 byte units This size should not include the overflow area 2688126256 is the size of the overflow area in 256 byte units ioAddr is the port to which the DMA should transfer memory content ckalrate is the clock rate generated by CKA1 in 19 2 kHz units Allowed numbers are 2 4 and 8 186 Advanced Topics PK2600 Sample Program BL17PWM1 C and BL17PWM2 C are sample programs which show how to use the pulse width modulation feature using the functions listed above They can be found in the Dynamic C SAMPLES BL17Xx directory The PWM functions use the Z180 s built in DMA hardware Using this DMA driven PWM limits the communication speed of the Z180 s Serial Port 1 to 4800 bps and the Z180 runs effectively at least 8 slower In addition you must ensure your application calls __eioBrdAORE at least every 25 ms to refresh the drivers
74. a 12 bit address the first and last nibbles must be swapped LIBRARY DRIVERS LIB void setl2adr int adr Sets the current address for the PLCBus All read and write operations access this address until a new address is set PARAMETER adr is a 12 bit physical address three 4 bit nibbles with the first and third nibbles swapped LIBRARY DRIVERS LIB void eioPlcAdr4 unsigned addr Specifies the address to be written to the PLCBus using only cycle BUSADR2 PARAMETER addr is the nibble corresponding to BUSADR2 LIBRARY EZIOPLC LIB EZIOPLC2 LIB EZIOMGPL LIB 168 PLCBus PK2600 void set4adr int adr Sets the current address for the PLCBus All read and write operations access this address until a new address is set A 12 bit address may be passed to this function but only the last four bits will be set Call this function only if the first eight bits of the address are the same as the address in the previous call to set12adr PARAMETER adr contains the last four bits bits 8 11 of the physical address LIBRARY DRIVERS LIB e char _eioReadDO Reads the data on the PLCBus in the BUSADRO cycle RETURN VALUE the byte read on the PLCBus in the BUSADRO cycle LIBRARY EZIOPLC LIB EZIOPLC2 LIB EZIOMGPL LIB e char _eioReadD1 Reads the data on the PLCBus in the BUSADRI cycle RETURN VALUE the byte read on the PLCBus in the BUSADRI cycle LIBRARY EZIOPLC LIB EZIOPLC2 LIB EZIOMGPL LIB e
75. able for programming CM7200 not available for use on CM7100 OxOE SERO VEC Asynchronous Serial Port Channel 0 0x10 SER1_VEC Asynchronous Serial Port Channel 1 To an interrupt to a user function in Dynamic use a directive such as the following INT_VEC 0x10 myfunction The above example causes the interrupt at offset 10H Serial Port 1 the Z180 to invoke the function myfunction The function must be declared with the interrupt keyword as shown below interrupt myfunction Refer to the Dynamic C manuals for further details on interrupt functions eo PK2600 Memory I O Map and Interrupt Vectors 141 Nonmaskable Interrupts The NMI line normally connects to the power failure output of the 691 supervisor Anonmaskable interrupt NMI occurs when PFI falls to 1 25 V 0 05 V This advanced warning allows the program to perform some emergency processing before an unwanted power down occurs The NMI is edge sensitive and cannot be masked by software When activated the NMI disables all other interrupts except TRAP and begins execution from logical address 0x66 The following example shows how to handle a power failure interrupt JUMP_VEC NMI_VEC myint interrupt retn myint body of interrupt routine while IBIT WDO 0 input voltage is still below the threshold that triggered the NMI return if just a power glitch return Jump Vectors These specia
76. able for user application PK2600 Channel SCC Option Channel A e DREQO used for SCC Channel A J8 1 6 2 4 5 6 6 Channel B 7 e els 10 11 12 1 used for SCC Channel B Channel A and Channel B INTO used for serial communication on Channel A and Channel B 64 Hardware Configurations Configuring a Multidrop Network Configure the serial channels that you wish to use for RS 485 communi cation e networked controllers connect RS 485 to RS 485 and RS 485 to RS 485 using single twisted pair wires nonstranded tinned A Refer to the Dynamic C manuals for more details on master slave networking RS 485 Termination Termination and bias resistors are required in a multidrop network to minimize reflections echoing and to keep the network line active in an idle state Typically termination resistors are installed at the master node and the physical end node of an RS 485 network A bias resistor is installed only at the master node Termination resistors are provided on the PK2600 controller board for the RS 485 configuration for Channels A and B When configuring a multidrop network be sure to enable the 220 termination resistors on both the master network controller and the end slave controller Figure 4 18 illustrates a multidrop network and Table 4 11 provides
77. ace to a controller PLCBus Yellow wire on top PLCBus Header Note position of connector relative to pin 1 From OP6000 KLB Interface Card Header J2 Pin 1 Figure E 2 OP6000 Connection to PLCBus Port The PLCBus consists of the following lines STBX negative going strobe e AIX A3X three control lines for selecting bus operation e DOX D3X four bidirectional data lines used for 4 bit operations D4X D7X four additional data lines for 8 bit operations e AT attention line open drain that may be pulled low by any device causing an interrupt PLCBus be used as a 4 bit bus DOX D3X or as an 8 bit bus DOX D7X Whether it is used as a 4 bit bus or an 8 bit bus depends on the encoding of the address placed on the bus Some PLCBus expansion cards require 4 bit addressing and others such as the XP8700 require 8 bit addressing These devices may be mixed on a single bus PK2600 PLCBus 163 There are eight registers corresponding to the modes determined by bus lines 2 and A3X The registers are listed in Table E 2 Table E 2 PLCBus Registers Register Address A3 A2 A1 Meaning BUSRDO CO 0 0 0 Read data one way BUSRDI C2 0 0 1 Read data another way BUSRD2 0 1 0 Spare or read data Read this register to BUSRESET d I reset the PLCBus BUSADRO C8 1 0 0 First address nibble or byte Second address BUSADRI CA 1 0 1 1 b
78. ages In addition to the external input channels of the A D converter chip three additional internal channels exist to measure reference points within the A D converter chip Unfortunately the A D converter compares its internal nodes to REF and REF so the conversions yield either all 1s or all Os You may access these channels using ordinary library routines by specifying the appropriate channel address when calling the functions Table 4 7 Internal Test Voltages Internal Voltage Read Channel 11 VREF VREF 2 Channel 12 VREF Channel 13 VREF 60 Hardware Configurations PK2600 Power Down Mode If you select Channel 14 the A D converter chip enters a power down mode in which all circuitry within the chip goes into a low current standby mode Upon power up and before the first conversion the chip also goes into the power down mode The chip remains in the power down mode until you select a channel other than 14 The normal operating current of the A D converter chip is 1 mA to 2 5 mA In power down mode this consumption is reduced to 4 uA to 25 uA External Connections The analog inputs on headers H8 and H11 are brought out to the PK2600 ANALOG INPUTS DB25 connector throught the I O conversion module PK2600 Hardware Configurations 61 Serial Channels There are four serial channels on the PK2600 controller board One chan nel Channel 1 is a dedicated RS 232 communication channel a
79. annel unsigned state Enables or disables the RS 485 drivers for Channel A or Channel B on the SCC PARAMETERS channel is SCC Aor SCC B state is to enable the driver 0 to disable it RETURN VALUE 0 if channel is valid 1 if not int z1Sw485 unsigned state Enables or disables the RS 485 driver for Channel 1 PARAMETER state is 1 to enable the driver 0 to disable it RETURN VALUE 0 if channel is valid Sample Program BL17SCC C is a serial communication sample program found in the Dynamic C SAMPLES BL17Xx directory PK2600 Software Development 101 Display Board Functions Display Hardware Control The following functions from the Dynamic C EZIOOP71 LIB library are used to control the hardware aspects of the display including the back light the contrast and the beeper void op71BackLight int onOff Turns the backlight of the PK2600 on or off PARAMETER onoff is non zero to turn the backlight on zero to turn the backlight off void op71SetContrast unsigned contrast Controls the contrast of the LCD PARAMETER contrast values range from 0 to 127 0 for the least contrast minimum V EE 127 for the most contrast maximum VEE void eioBeep int onOff Turns the buzzer on or off PARAMETER onoff is non zero to turn the buzzer on zero to turn the buzzer off Display Images The following functions from the Dynamic C GLCD LIB library are used to control the appearance of the fonts
80. ar pixWidth char pixHeight unsigned startChar unsigned endChar unsigned long xmemBuffer to initialize a font information structure if the font is stored in xmem This is similar to g1FontInit but xmemBuf fer is a physical address pointing to the font table stored in xmem Z World supplies five font sizes for the PK2600 The smallest font engFont6x8 compiles to xmem and each character is 6 pixels wide by 8 pixels high The largest font engFont17x35 also compiles to xmem and each character is 17 pixels wide by 35 pixels high When you need to print text to the LCD call void glPrintf int x int y struct fontInfo pInfo char fmt where x y is the upper left corner of the text pInfo points to a font information structure fmt points to a format string much like print and the rest of the parameters specify what to print for each field in the format string same as printf 116 Graphics Programming PK2600 Keypad Programming The sample program KPDEFLT C in the Dynamic C SAMPLES QVGA subdirec tory demonstrates how to read the keypad Add the following directives at the top of the program to make it possible to use the keypad routines fuse lqvga 1ib landscape orientation OR fuse pqvga lib portrait orientation duse ezioop71 1lib duse kp op71 1lib Initialization To initialize the keypad driver call kpbe Init This must be performed before other keypad operations Scanning the Keypad
81. ate of the pixel to be drawn y is the y coordinate of the pixel to be drawn RETURN VALUE Status ofthe LCD after the operation void glPlotLine int x1 int yl int x2 int 12 Plots a line on the LCD PARAMETERS x1 is the x coordinate of the first endpoint y1 is the y coordinate of the first endpoint x2 is the x coordinate of the second endpoint y2 is the y coordinate of the second endpoint void glPrintf int x int y struct fontInfo pInfo char fmt Prints a formatted string much like print on the LCD screen PARAMETERS x is the x coordinate ofthe text left edge y is the y coordinate of the text top edge pInfo is the pointer to the font descriptor used for printing on the LCD screen mt 15 the pointer to the format string void glPlotCircle int xc int yc int rad Draws a circle on the LCD PARAMETERS xc is the x coordinate ofthe center is the y coordinate of the center radis the radius of the circle void glFillCircle int xc int yc int rad Draws a filled in circle on the LCD PARAMETERS xc is the x coordinate ofthe center is the y coordinate of the center radis the radius of the circle 104 Software Development PK2600 void glPlotVPolygon int n int pFirstCoord Plots a filled in polygon PARAMETERS nis the number of vertices pFirstCoord is an array of vertex coordinates x y void glPlotPolygon int n int xl int yl int x2 int y2
82. battery protects data in the RAM and the real time clock RTC VRAM the voltage supplied to the RAM and RTC can also protect other devices attached to the system against power failures The 691 supervisor switches VRAM to VBAT or VCC whichever is greater To prevent hunt ing the switchover actually occurs when Vcc is 50 mV higher than VBAT The circuit draws no current from the battery once regular power is applied System Reset The 691 chip drives the RESET line The RESET line is not pulled up internally PK2600 Subsystems 79 2180 Serial Ports The Z180 s two independent full duplex asynchronous serial channels have a separate baud rate generator for each channel The baud rate can be divided down from the microprocessor clock or from an external clock for either or both channels The serial ports have a multiprocessor communications feature When enabled this feature adds an extra bit to the transmitted character where the parity bit would normally go Receiving Z180s can be programmed to ignore all received characters except those with the extra multiprocessing bits enabled This provides a 1 byte attention message that can be used to wake up a processor without the processor having to intelligently monitor all traffic on a shared communications link The block diagram in Figure 5 6 shows Serial Channel 0 Serial Channel 1 is similar but control lines for RTS and DCD do not exist The five unshaded registe
83. bus uses only the lower five bits of the three address bytes PK2600 PLCBus 5 Z World provides software drivers that access the PLCBus To allow access to bus devices in a multiprocessing environment the expansion register and the address registers are shadowed with memory locations known as shadow registers The 4 byte shadow registers which are saved at predefined memory addresses are as follows SHBUSI SHBUS1 1 SHBUSO SHBUSO 1 SHBUS0 2 SHBUS0 3 BUSADRO BUSADRI BUSADR2 Before the new addresses or expansion register values are output to the bus their values are stored in the shadow registers All interrupts that use the bus save the four shadow registers on the stack Then when exiting the interrupt routine they restore the shadow registers and output the three address registers and the expansion registers to the bus This allows an interrupt routine to access the bus without disturbing the activity of a background routine that also accesses the bus To work reliably bus devices must be designed according to the following rules 1 The device must not rely on critical timing such as a minimum delay between two successive register accesses 2 The device must be capable of being selected and deselected without adversely affecting the internal operation of the controller Allocation of Devices on the Bus 4 Bit Devices Table E 4 provides the address allocations for the registers of 4 bit de
84. cal address bits 8 11 dat bits 0 3 specifies the data to write to the PLCBus LIBRARY DRIVERS LIB The 8 bit drivers employ the following calls void set24adr long address Sets a 24 bit address three 8 bit nibbles on the PLCBus All read and write operations will access this address until a new address is set PARAMETER address is a 24 bit physical address for 8 bit bus with the first and third bytes swapped low byte most significant LIBRARY DRIVERS LIB 170 PLCBus PK2600 void set8adr long address Sets the current address on the PLCBus All read and write operations will access this address until a new address is set PARAMETER address contains the last eight bits of the physical address in bits 16 23 A 24 bit address may be passed to this function but only the last eight bits will be set Call this function only if the first 16 bits of the address are the same as the address in the previous call to set24adr LIBRARY DRIVERS LIB int read24data0 long address Sets the current PLCBus address using the 24 bit address then reads eight bits of data from the PLCBus with a BUSRDO cycle RETURN VALUE PLCBus data in lower eight bits upper bits 0 LIBRARY DRIVERS LIB int read8data0 long address Sets the last eight bits of the current PLCBus address using address bits 16 23 then reads eight bits of data from the PLCBus with a BUSRDO cycle PARAMETER address bits 16 23 are rea
85. char 6102080602 Reads the data on the PLCBus in the BUSADR2 cycle RETURN VALUE the byte read on the PLCBus in the BUSADR2 cycle LIBRARY EZIOPLC LIB EZIOPLC2 LIB EZIOMGPL LIB char readl2data int adr Sets the current PLCBus address using the 12 bit adr then reads four bits of data from the PLCBus with BUSADRO cycle RETURN VALUE PLCBus data in the lower four bits the upper bits are undefined LIBRARY DRIVERS LIB PK2600 PLCBus 169 char read4data int adr Sets the last four bits of the current PLCBus address using adr bits 8 11 then reads four bits of data from the bus with BUSADRO cycle PARAMETER adr bits 8 11 specifies the address to read RETURN VALUE PLCBus data in the lower four bits the upper bits are undefined LIBRARY DRIVERS LIB e void _eioWriteWR char ch Writes information to the PLCBus during the BUSWR cycle PARAMETER ch is the character to be written to the PLCBus LIBRARY EZIOPLC LIB EZIOPLC2 LIB EZIOMGPL LIB void writel2data int adr char dat Sets the current PLCBus address then writes four bits of data to the PLCBus PARAMETER adr is the 12 bit address to which the PLCBus is set dat bits 0 3 specifies the data to write to the PL CBus LIBRARY DRIVERS LIB void write4data int address char data Sets the last four bits of the current PLCBus address then writes four bits of data to the PLCBus PARAMETER adr contains the last four bits of the physi
86. communication is possible on this channel but is not supported by Dynamic C drivers at this time Channel B Channel B is a general purpose serial channel Along with Channel A it is controlled by the Serial Communication Controller chip Channel B can be configured as two wire RS 485 or five wire RS 232 Synchronous commu nication is possible on this channel but is not supported by Dynamic C drivers at this time 62 Hardware Configurations PK2600 Operating Modes and Configuration Tables 4 9 and 4 10 show the operating modes and jumper configurations for the serial channels on the PK2600 controller board Table 4 9 Serial Channel Configuration Jumper Settings Jumper Settings Channel 7 RS 232 Communication RS 485 Communication Channel 0 No jumper settings J2 J2 e 2 e 2 1 4 6 06 6 5 6 6 6 Channel A e e H 10 9 0 n 10 e 9 17 11 6 12 5 wire RS 232 2 wire RS 485 DCD DTR J8 1 H 6 2 6 4 5 0 6 Channel B els 9 6 0 11 6 2 5 wire RS 232 2 wire RS 485 PK2600 Hardware Configurations 63 Table 4 10 Serial Channel Configuration Jumper Settings Jumper Settings User Application Option DREQO available for user application J8 2 4 6 8 10 12 1 available for user application on INTO avail
87. d RETURN VALUE PLCBus data in lower eight bits upper bits 0 LIBRARY DRIVERS LIB void write24data long address char data Sets the current PLCBus address using the 24 bit address then writes eight bits of data to the PLCBus PARAMETERS address is 24 bit address to write to data is data to write to the PLCBus LIBRARY DRIVERS LIB void write8data long address char data Sets the last eight bits of the current PLCBus address using address bits 16 23 then writes eight bits of data to the PLCBus PARAMETERS address bits 16 23 are the address ofthe PLCBus to write data is data to write to the PLCBus LIBRARY DRIVERS LIB PK2600 PLCBus 1 Blank 172 PLCBus PK2600 APPENDIX F SERIAL INTERFACE BoARD 2 Appendix F provides technical details and baud rate configuration data for Z World s SIB2 The following sections are included e Introduction Dimensions PK2600 Serial Interface Board 2 173 Introduction The SIB2 is an interface adapter used to program the PK2600 The SIB2 is contained in an ABS plastic enclosure making it rugged and reliable The SIB2 enables both the controller board and the display board to communi cate with Dynamic C via the Z180 s clocked serial I O CSI O port freeing the serial ports for use by the application during programming and debugging The SIB2 s 8 pin cable plugs into the target PK2600 s processor through an aperture in the backplate and a 6 c
88. de 1 m Floating square root sqrt q Floating exponent exp q Floating cosine cos The execution times can be adjusted proportionally for clock speeds other than 9 216 MHz Operations involving one wait state will slow the execu tion speed about 25 PK2600 Memory I O Map and Interrupt Vectors 5 Memory Map Input Output Select Map The Dynamic C library functions IBIT ISET and IRES in the BIOS LIB library allow bits in the I O registers to be tested set and cleared Both 16 bit and 8 bit I O addresses can be used 2180 Internal Input Output Registers Addresses 00 3F The internal registers for the I O devices built into to the Z180 processor occupy the first 40 hex addresses of the I O space These addresses are listed in Table C 2 Table 2 2180 Internal I O Registers Addresses 0x00 0x3F Address Name Description 0x00 CNTLAO Serial Channel 0 Control Register A 0x01 CNTLAI Serial Channel 1 Control Register A 0 02 CNTLBO Serial Channel 0 Control Register B 0x03 CNTLB1 Serial Channel 1 Control Register B 0x04 STATO Serial Channel 0 Status Register 0 05 STATI Serial Channel 1 Status Register 0 06 TDRO Serial Channel 0 Transmit Data Register 0x07 TDRI Serial Channel 1 Transmit Data Register 0x08 RDRO Serial Channel 0 Receive Data Register 0x09 RDRI Serial Channel 1 Receive Data Register 0x0A CNTR
89. dr unsigned state Specifies the duty cycle for a particular output channel Set eioErrorCode ifeioAddr is out of range PARAMETERS eioAddr is a number ranging from 0 to 3 state is a placeholder for a number ranging from 0 to turn off the channel to 256 to turn on the channel 10096 duty cycle The duty cycle is state 256 e g 128 for 50 duty cycle 64 for 25 duty cycle RETURN VALUE 0 ifsuccessful 1 if not The PWM functions use the Z180 s built in DMA hardware The use of DMA driven PWM effectively makes the Z180 run at least 8 more slowly Be sure your application calls 610202082 at least every 25 ms to refresh the drivers period Contact Z World Technical Support at 530 757 3737 for further assistance with PWM functions void _eioSetupAOlst Initializes the PWM hardware eioSetupAO1st must be called before using e3oBrdAO e int eioBrdAORf Refreshes the DMA counter and address pointer Your program must call it every 25 ms or more frequently after eioSetupAOI1st is called RETURN VALUE The function returns 1 ifthe DMA count is zero PWM has stopped and returns 0 otherwise If the function returns 1 the driver is either not initialized by calling eioSetupAO1st or _eioBrdAORE is not called at least every 25 ms Sample Program BL17PWM4 is a sample program that shows how to use the pulse width modulation feature using the functions listed above It can be found in the Dy
90. dresses These lines are used to access peripherals on the controller board The power supervisor IC performs several functions It provides a watchdog timer function performs power failure detection RAM protec tion and battery backup when the CM7200 is unpowered 72 Subsystems 0 Your program can obtain the time and the date from the real time clock Figure 5 2 shows a block diagram of the CM7200 microprocessor core module A6 A8 Decoder CS1 CS6 0 19 0100660 Serial O lt J 200 0 5 2 PRTs 00 07 DMA Request gt DMA End 2 Serial Ports 2 DMA Channels SRAM EPROM Interrupt MMU 32K 512K 32K 512K 45V GND Supervisor VRAM Watchdog Timer RTC VBAT gt Power Failure Warning Reset Control cs Battery Backup Control gt VRAM Figure 5 2 CM7200 Block Diagram The core module also provides connections to the Clock Serial I O CSIO port on the Z180 This port can be used to program the controller board using Z World s SIB2 This allows programming and debugging of the PK2600 while providing access to all the onboard serial channels The EEPROM is simulated in flash EPROM for consistency with Z World controllers whose software libraries rely on exchanging information with the EEPROM See Appendix G Advanced Topics for more in
91. e two unconditioned inputs A8 and A9 are also available Figure 3 7 shows the pinout ANALOG INPUTS GND ADREF 5 8 oa 0 A7 Oo A6 On A5 A4 Oo A3 on A2 Oo A1 wo N Bo eo SO A9 No So 20 50 50 2 2 2 2 2 2 22 oooooooooooo Figure 3 7 Analog Inputs Pinout The PK2600 comes with gain and bias resistors installed for an input range of 0 V to 10 V for A0 A7 The two unconditioned inputs A8 and A9 have an input range of 0 V to 2 5 V Chapter 4 Hardware Configurations provides instructions to reconfigure the conditioned analog inputs for different input voltage ranges PK2600 Hardware Features 31 Serial Channels Three serial channels are available on the PK2600 One channel SERIAL PORT 1 is a dedicated RS 232 channel The other two channels may be configured as either RS 232 or RS 485 SERIAL PORT 1 is connected to the controller Z180 s Serial Channel 0 SERIAL PORT 2 and SERIAL PORT 3 are controlled by the Serial Communications Controller SCC chip on the PK2600 controller board these two ports also have hardware support for synchronous communication Baud rates up to 57 600 bps are supported The factory default configuration for SERIAL PORT 2 and SERIAL PORT 3 is five wire RS 232 SERIAL PORT 2 also provides DCD and DTR signals Synchronous communication is possible on these chan
92. eaders on the controller board Table D 4 PK2600 Analog Inputs Pin Mapping Controller Digital Signal Controller Pin No PK2600 DB25 Pin No AO 1 1 Al A2 A3 5 ADREF 5 3 1 4 9 1 11 12 A8 13 9 GND 2 4 6 8 10 12 14 15 16 17 18 19 Header 1 A4 1 5 A5 A6 7 3 6 2 7 7 8 5 9 11 ADREF 1 12 A9 13 10 GND 2 4 6 8 10 12 14 20 21 22 23 24 25 Header H8 Figure D 6 shows the pinouts for controller board headers H8 and H11 which are connected to the ANALOG INPUTS on the PK2600 H8 H11 ANA4 1 2 GND ANAO 1 M 2 GND ANA5 3 4 GND 3 4 GND ANA6 5 6 GND ANA2 5 6 GND ANA7 7 GND ANA3 7 8 GND 5ANA 9 10 GND 5ANA 9 6 10 GND ADREF 1 12 GND ADREF 11 12 GND ANAAQ 13 14 GND ANA8 13 14 GND Figure D 6 Pinouts for PK2600 Controller Board Analog Inputs 152 Circuit Board Reference PK2600 Figure D 7 shows the pinouts for controller board headers H12 H15 which are connected to the three serial ports on the PK2600 H12 H13 2 4 0 232TX1 6 0 232RX1 232 0 232 0 GND 10 GND Channel 0 to Serial Port 1 Channel 1 to Display H14 H15 232DTRA 2 232DCDA 2 232TXA 3 4 232CTSA 232TXB 4 232CTSB 232RXA 5 6 6 232RTS
93. eceive characters are ignored When written this bit has an entirely different function If a 0 is written the baud rate prescaler is set to divide by 10 118 1 1s written it is set to divide by 30 MP Multiprocessor Mode When this bit is set to 1 the multiprocessor mode is enabled The multi processor bit MPB is included in transmitted data as shown here start bit data bits MPB stop bits The MPB is 1 when MPBT is 1 and 0 when MPBT is 0 MPBT Multiprocessor Bit Transmit This bit controls the multiprocessor bit MPB When MPB is 1 transmit ted bytes will get the attention of other units listening only for bytes with MPB set PK2600 Subsystems 87 Table 5 4 relates the Z180 s ASCI Control Register B to the baud rate Table 5 4 Baud Rates for ASCI Control Register B Baud Rate at 18 432 MHz bps 38 400 19 200 9600 4800 1200 600 300 2400 Baud Rate at 9 216 MHz bps 19 200 9600 4800 2400 1200 600 300 150 ASCI B Value 20 21 22 or 28 23 or 29 24 or 2A 25 or 2B 26 or 2C Baud Rate at 18 432 MHz bps 115 200 57 600 28 800 14 400 7200 3600 1800 it bps 00 57 600 01 28 800 020 08 14400 03 or 09 7200 04 or OA 3600 05 or OB 1800 06 or oC 900 450 225 PK2600 88 Subsystems CHAPTER 6 S OFTWARE DEVELOPMENT Chapter 6 describes the software function calls used to develop applica tion
94. edge triggered Set this bit to 0 to stop sending Otherwise interrupts will be requested continu ously as soon as the transmitter data register is empty TDRE Transmitter Data Register Empty A 1 means that the channel is ready to accept another character A high level on the CTS pin forces this bit to 0 even though the transmitter is ready PK2600 Subsystems 83 CTS1E CTS Enable Channel 1 The signals RXS and CTS1 are multiplexed on the same pin 1 stored in this bit makes the pin serve the CTS1 function A 0 selects the RXS function The pin RXS is the CSI O data receive pin When RXS is selected the CTS line has no effect RIE Receiver Interrupt Enable A 1 enables receiver interrupts and 0 disables them A receiver interrupt is requested under any of the following conditions DCDO Channel 0 only read data register full OVRN overrun PE parity error and FE framing error The condition causing the interrupt must be removed before the interrupts are re enabled or another interrupt will occur Read ing the receiver data register RDR clears the RDRF flag The EFR bit in CNTLA is used to clear the other error flags FE Framing Error A stop bit was missing indicating scrambled data This bit is cleared by the EFR bitin CNTLA PE Parity Error Parity is tested only if MODI in CNTLA is set This bit is cleared by the EFR bitin CNTLA OVRN Overrun Error Overrun occurs when bytes ar
95. ents through the input resistor and the feedback resistor are essentially identical the ratio of the voltages across the resistors is equivalent to the ratio of the resistors Therefore the gain is _ VOUT VRO VRO e gain Again using Channel 0 as an example measure the voltage of VREF and the voltage at VRO Because the current into the op amp input is negli gible the resistance ratio of the two resistors in the voltage divider alone determines VRO You can then compute the value of the fixed resistor in the divider once you know both the value of the resistor you installed and the value of VRO 8 Calibrate the PK2600 A D converter Mathematically derived values provide good baseline gain values Calibration is necessary because the inherent component to component variations of resistors can completely swamp the 0 25 resolution of the A D converter To achieve the highest accuracy possible calibrate the PK2600 controller board 58 Hardware Configurations PK2600 Dynamic C provides a routine to compute calibration coefficients and store the coefficients in nonvolatile memory The routine uses two reference points to compute the coefficients Each reference point comprises a pair of values the actual applied test voltage and raw converted A D value a 12 bit integer The supplied Z World A D software will automatically use these calibration coefficients to correct all subsequent A D readings The factory installed
96. ers 167 163 operations 4 bit 163 164 166 8 163 167 194 Index digital outputs continued connecting 0 49 high voltage driver specifications 131 PME 95 sample program 9 Software eios e A ene 93 93 dimensions controller board 147 core 147 display board 157 conversion module 146 PK2600 128 power program module 147 SIB2 erent i 175 DIP relays 162 display liquid crystal See LCD display board dimensions 157 87 DMA and 97 dmapwmBufBeg 186 dmapwmInit 183 186 dmapwmSetBuf 185 dmapwmSwBuf 186 DR enr te 87 draw a 1111180 115 inis eI 90 expansion bus 167 168 170 relay 167 DRIVERS LIB 108 167 Dynamic 18 24 COMMUNICATION 142 sample programs 24 serial options seses 24 will not 123 Index 195 controller board dimensions 2222 4 147 subsystems 72 core module ss sseeseeess000 72 3 dimensions
97. f ORLD 2600 Integrated Control System User s Manual Revision C PK2600 User s Manual Part Number 019 0061 Revision C Last revised on July 20 2000 Printed in U S A Copyright 1999 Z World Inc All rights reserved Z World reserves the right to make changes and improvements to its products without providing notice Trademarks Dynamic C isa registered trademark of Z World Inc Windows isa registered trademark of Microsoft Corporation PLCBus is a trademark of Z World Inc Hayes Smart Modem isa registered trademark of Hayes Microcomputer Products Inc Notice to Users When a system failure may cause serious consequences protecting life and property against such consequences with a backup system or safety device is essential The buyer agrees that protection against conse quences resulting from system failure is the buyer s responsibility This device is not approved for life support or medical systems All Z World products are 100 percent functionally tested Additional testing may include visual quality control inspections or mechanical defects analyzer inspections Specifications are based on characterization of tested sample units rather than testing over temperature and voltage of each unit Z World may qualify components to operate within a range of parameters that is different from the manufacturer s recommended range This strategy is believed to be more economical and ef
98. f the LCD control and RAM circuits U3 0 VA 0 14 D 0 7 VD 0 7 FRAME INTO ON OFF RESET XD 0 3 SED1335F LCD Control VRAMCS1 VRAMCS2 VCC VCC VCC R26 R31 10 0 25 Manual Adjustment Figure 3 2 Block Diagram LCD Control and Memory The LCD is connected to the PK2600 display circuit board through header J1 AAT or J3 on the display circuit board 2 2 4 2 we Contrast Adjustment 2 Figure 3 3 shows the location of the manual contrast adjustment access Insert a small screwdriver to adjust the MANUAL variable resistor inside the enclosure CONTRAST ADJUSTMENT This contrast adjustment is the factory default for the PK2610 The PK2600 is configured with software contrast con trol as the factory default With soft ware contrast control the contrast level may be set via a software func tion call Since it is hard to guess the correct level in software buttons de 0 fined on the touchscreen and in soft ware can be used to adjust the con trast PLCBUS EXPANSION PORT NSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSNQSS SSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSS SSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSNSSSSS Figure 3 3 Location of PK2600 Manual Contrast Adjustment 28 Hardware Features PK2600 Coordinate Systems Figure 3 4 shows the coordinate systems for the 8 x 8 LCD matrix 7 0
99. f you remove the power cable abruptly from the controller board side then only the capacitors on the board provide power reducing computing time to a few microseconds These times can vary considerably depending on system configuration and loads on the controller board power supplies The interval between the power failure detection and entry to the power failure interrupt routine is approximately 100 us or less if Dynamic C NMI communication is not in use PK2600 Advanced Topics 179 Simulated EEPROM The PK2600 uses a section of the flash EPROM on the controller board to simulate EEPROM The size of the simulated EEPROM is 512 bytes not Kbytes Locations 0x02 through 0x3D are used to store the analog input calibration constants The rest of the simulated EEPROM is free for use by the application These functions are used to read write from to the simulated EEPROM int ee rd int address Reads and returns data from flash EPROM storage location address The function returns 1 if it is unable to read data LIBRARY BIOS LIB int ee wr int address int data Writes data to flash EPROM storage location address The function returns 1 if it is unable to write data LIBRARY BIOS LIB Locations 0x02 through 0x3D on the display board are reserved for a simulated EEPROM but are not presently used 180 Advanced Topics PK2600 Pulse Width Modulation PWM Software PWM Addressing Detail The driver of the PWM on the PK
100. fective Additional testing or burn in of an individual unit is available by special arrangement Company Address gt Z WOrRLD Y Z World Inc Telephone 530 7 2900 Spafford Street Facsimile 530 753 5141 Davis California 95616 6800 WebSite http www zworld com USA E Mail zworld gzworld com TABLE OF CONTENTS About This Manual ix Chapter 1 Overview 13 1 eiue ects ake RU EID 15 16 Flexibility and Customization esee 16 Development and Evaluation Tools 2 18 Developer s Kit sedet aae eee pte 18 SION 18 Chapter 2 Getting Started 19 Initial PK2600 Setup 20 Parts Required cede eee bep eer dg 20 Setting Up the 2600 0 20 Connecting the PK2600 to a Host PC 22 Running Dytiainic C i eere i e qb eins 24 Chapter 3 Hardware Features 25 Modes 26 Changing the Operating Mode sse 27 Using Run and Program Modes Example 27 Liquid Crystal Display LCD eere 28 Contrast Adjustment 28 Coordinat Systems 5 eee aHa 29 Digital Inputs Outputs eese 30 Digital GrOUD leno CREER aia 30 Digital 30 Analog Inputs 3l Serial Channels 32 PEGBUS rra ESE 33 Chap
101. fixed resistors have a 1 tolerance Calibration constants for the factory installed resistors are stored in simulated EEPROM during testing 9 Recalibrate the PK2600 To recalibrate a PK2600 apply two known test voltages to each channel you plan to use Get the converted reading for each test voltage and pass them along with the test voltages to the function e3oBrdACalib to calculate the conversion coefficients for that channel eioBrdACalib will automatically store the coefficients in the flash EPROM Sample program BL17AIN C in the Dynamic C SAMPLES directory shows how to calibrate the conditioned analog input channels of a PK2600 manu ally assuming test voltages of 1 00 V and 9 00 V Drift The AD680JT voltage reference displays a voltage drift of 10 ppm C typ to 30 ppm C max This drift corresponds to 25 mV C to 75 mV C or 1 75 mV to 5 25 mV over the temperature range of 0 C to 70 C The LMC660C operational amplifier exhibits an offset voltage drift of 1 3 V C typ or 91 mV over the operating temperature range Low Pass Filter The 0 01 mF feedback capacitors in the amplifier s feedback path transform the amplifiers into low pass filters These filters attenuate any high frequency noise that may be present in your signal These filters charac teristics depend on the resistors your select The 3 dB corner frequency of a filter is 1 4 6 2z xR x0 01 uF f db For the case above wi
102. formation ev about the simulated EEPROM PK2600 Subsystems 73 Display Board Subsystems The PK2600 display board consists of several subsystems including a com puting module serial communication channels LCD a buzzer and a keypad interface Figure 5 3 provides a block diagram of the PK2600 display board Z180 SRAM Flasht Flash2 Batt 691 super LCD Control To Controller R5292 Board 7 4 1 8 Drive 4 4 Keypad Sense 2 Interface Optional Software Touchscreen Contrast Adjustment Figure 5 3 Display Board Block Diagram VRAM1 VRAM2 LCD 320 x 240 A Contrast Adjustment Computing Module The computing module consists of a Zilog Z180 microprocessor 128K of battery backed static RAM and 512K of flash EPROM The computing module operates in tandem with a real time clock and a watchdog timer microprocessor supervisor The Z180 CPU runs at 18 432 MHz and the LCD controller runs at 9 216 MHz The watchdog timer microprocessor chip provides a watchdog timer function power failure detection RAM protection and battery backup The real time clock provides time and date information to applications running on the display board The EEPROM is simulated in flash EPROM for consistency with Z World controllers whose software libraries rely on exchanging informat
103. ge function to inter pret key presses when kpScanState is called Use kpDefGetKey to get the code of the last key pressed PK2600 Software Development 107 Additional Software Real Time Clock RTC The controller board and the display board each have an RTC The RTC stores time and date information and accounts for the number of days in a month and for leap year A backup battery allows the values in the RTC to be preserved if a power failure occurs The Dynamic C function library DRIVERS LIB provides the following RTC functions tm_rd Reads time and date values from the RTC tm_wr Writes time and date values into the RTC The Dynamic C Function Reference manual describes these functions and the associated data structure tm The following points apply when using the RTC 1 The AM PM bit is 0 for AM 1 for PM The RTC also has a 24 hour mode 2 Set the year to 96 for 1996 97 for 1997 and so on Constantly reading the RTC in a tight loop will result in loss of accuracy Flash EPROM The controller board has one flash EPROM and the display board has two flash EPROM The following function from the Dynamic C DRIVERS LIB library is used to write to the controller flash EPROM and to the program flash EPROM on the display board int WriteFlash unsigned long physical_addr char buf int count Writes count number of bytes pointed to by buf to the program flash EPROM absolute data location phys
104. ge load See Figures 4 11 and 4 12 TTL CMOS Outputs Z World also offers TTL or CMOS compatible outputs for the PK2600 Input and output channels may be configured independently in any combi nation However the functionality of each input is not independent the inputs are still characterized in groups of four or eight Z World offers all PK2600 integrated control systems in quantity with factory installed TTL or CMOS compatible outputs For ordering information call your Z World Sales Representative at 530 757 3737 50 Hardware Configurations PK2600 Pulse Width Modulation PWM Configuration In order to use the PWM feature of the digital outputs header 18 on the controller board must be jumpered from pin 4 to pin 6 See Figure 4 13 J8 11 12 DREQO available for user application J8 N 10 12 DREQO used for SCC DREQO Jumper Settings Hardware Configurations 51 J8 9 4 6 e e 1 12 a DREQO used for PWM Figure 4 13 PK2600 Analog Inputs The PK2600 provides 10 single ended analog to digital conversion chan nels with 12 bit resolution Eight channels are conditioned and two are unconditioned The eight conditioned inputs can measure bipolar or uni polar signals User installable resistors determine the signal conditioning for your application Two inputs
105. gt u9 UI WOOO 6 IDDnnnnm T RE PALE 691 B R unus 26 8 8 2 cio 8 013 U14 SRAM RTC SRAM 3 AN Ud 2 DUI n OTT m 1 nm H 8 a usb LCD E Flash 8 B B EB Dis la D 8 5 play vi 8 EO RE p Ui E U18 B Board c ms 65 mT 28 2954 e Reg 8 11103 E oe sin 9 Figure 4 6 Display Board Layout 40 Hardware Configurations PK2600 Digital Inputs and Outputs The digital inputs and outputs are divided into two banks A and B as shown in Figure 4 7 The 16 factory default digital inputs on the PK2600 controller board occupy Bank A and 16 digital outputs are located on Bank B Future and or custom versions of the PK2600 may have both or no banks configured as digital inputs In order for a bank to be configured as an input the appropriate interface ICs must be installed In order for a bank to be configured as an output the appropriate high voltage driver ICs must be installed These modifications should only be performed at Z World s manufacturing facility 4 Moooo MV6 MV5 MV4 MV3 MV2 MV1 CU OQ 00 0
106. gure 2 1 DCIN S 3 Plugthe connector back into the power connection at the back of the PK2600 Watch the polarity Figure 2 1 Wiring PK2600 Power Supply Connector of the connection so that the banded wire from the power supply goes to DCIN as shown in Figure 2 2 2 DIGITAL GROUP 1 SERIAL PORT 3 0222 0009 K PLCBUS EXP pm 2900 SPAFFORD ST DAVIS CA 95616 IN 0 1 530 757 3737 WWW ZWORLD COM Figure 2 2 PK2600 Power Supply Connections 4 Plugthe power supply into a wall outlet The display should now light up with the demonstration screens shown in Figure 2 3 20 Getting Started PK2600 Zorro PK2600 SERIES CONTROLLER SUPPORT Z WORLD TECHNICAL SUPPORT 1 580 757 8737 www zworld com Control Features Runs at 18 432 MHz 16 protected inputs 16 high current outputs Ten 12 bit analog inputs 3 full duplex serial channels PLCBus interface Also a really neat display Clock Ctrst Bkit Beep Figure 2 3 PK2600 Demo Screens PK2600 Getting Started 21 Connecting the PK2600 to a Host PC The PK2600 can be programmed using a PC through an RS 232 serial port with the DE9 to DE9 programming cable provided in the Developer s Kit You can also use Z World s SIB2 to program the PK2600 Using the SIB2 frees all the serial channels for the application d
107. h routine restores must be phase synchronized with the PWM waveforms at the moment The driver library provides a refresh routine 610226035 to refresh the DMA counter and source address registers eioBrdAORf can be called from a preemptive task or from the main program The refresh routine must be called frequently enough so that the DMA counter never reaches 0 The following inequality states the requirement A244 in which f is the refresh frequency f is the frequency of CKA1 and Zp is the total length of the waveform pattern buffer For example eioSetupAO1st sets up f Hz and ls 4096 As a result the application engineer must ensure gt 37 5 Hz 6 Changing duty cycles Once the PWM waveforms are up and running the application may need to change the duty cycles for the channel s This poses two problems First the change should only be done to the channel that needs a change of duty cycle all other channels should remain the same Second the change must become effective phase synchronized with the current waveform The solution to the first problem depends on how the edges are repre sented In particular it depends on whether the no op edges are used If the no op edges are used changing duty cycle is a matter of moving the edges that are not no op For example in our example in the set up the 184 Advanced Topics PK2600 waveform section if we wish to change the duty cycle of output
108. hannel 0 09 RDRI Receive Data Register Serial Channel 1 82 Subsystems PK2600 Asynchronous Serial Communication Interface The Z180 incorporates an asynchronous serial communication interface ACSI that supports two independent full duplex channels ASCI Status Registers A status register for each channel provides information about the state of each channel and allows interrupts to be enabled and disabled STATO 04H 7 2 6 5 4 3 1 0 RDRF OVRN PE FE RIE mcno TDRE TIE twHs CB R R R W R W STATI 05H _ MEE SENE VEM RDRF OVRN PE FE RIE 01516 TDRE TIE R RIW R R R W 8 DCDO Data Carrier Detect This bit echoes the state of the 26 0 input pin for Channel 0 However when the input to the pin switches from high to low the data bit switches low only after STATO has been read The receiver is held to reset as long as the input pin is held high This function is not generally useful because an interrupt is requested as long as DCDO is a 1 This forces the program mer to disable the receiver interrupts to avoid endless interrupts A better design would cause an interrupt only when the state of the pin changes This pin is tied to ground in the CM7200 TIE Transmitter Interrupt Enable This bit masks the transmitter interrupt If set to 1 an interrupt 1s re quested whenever TDRE is 1 The interrupt is not
109. he number of fluctuations of the DC input and hence the number of stacked NMIs the processor s stack can overflow possibly into your program s code or data PK2600 Subsystems 77 The following sample program shows how to handle an NMI main char dummy 24 define NMI_BIT 0 sit 0 JUMP_VEC NMI VEC myint asm myint ld sp dummy 24 force stack pointer to top of dummy vector to prevent overwriting code or data do whatever service within allowable execution time loop call hitwd make sure no watchdog reset while low voltage ld bc NMI load the read NMI register to bc in a c read the read NMI register for PFO bit NMI BIT a check for status of PFO jr z loop wait until the brownout Clears timeout then a tight loop to force a watchdog timeout timeout resetting the 2180 endasm Of course if the DC input voltage continues to decrease then the PK2600 will just power down Call the Dynamic C function hitwd during the power failure service routine to make sure that the watchdog timer does not time out and thereby reset the processor The controller can continue to run at low voltages and so it might not be able to detect the low voltage condition after the watchdog timer resets the processor Watchdog Timer To increase reliability the 691 s watchdog timer forces a system reset if a program does not notify the supervisor nominally at least every second 78
110. he raw data corresponding to v1 d2 is the raw data corresponding to v2 v1 is the known voltage used to obtain d1 v2 is the known voltage used to obtain 2 RETURN VALUE 0 if successful 1 if eioAddr is out of range Since the PK2600 is calibrated at the factory it is only neces sary to use this function to recalibrate the 2600 controller board Sample Program BL17AIN C is a sample program that shows how to use the analog inputs It can be found in the Dynamic C directory under SAMPLESNBL17XX PK2600 Software Development 99 Serial Channels The PK2600 provides three serial communication channels Two ports can be configured as RS 232 or RS 485 the remaining port SERIAL PORT 1 is RS 232 only This section provides information on RS 232 and RS 485 communications Chapter 4 Hardware Configurations provides information on configuring the serial channels RS 232 Communication The RS 232 channels and the supplied Dynamic C software allow the PK2600 to communicate with other computers or controllers By adding a modem remote communications can be achieved including remote down loading using the X modem protocol Examples of RS 232 software drivers can be found in the Dynamic C SAMPLES AASC directory Refer to your Dynamic C manuals for additional information on remote downloading Use the SIB2 if you need to make all the serial channels Ti p available to your application during sof
111. her the LQVGA LIB landscape image or the PQVGA LIB portrait image library in your program Using the Font Bitmap In Your Program The array does not store the dimensions of the font or the bitmap This information is contained in the comments The following lines in the comments indicate the dimensions of the font horizontal size is 6 pixels vertical size is 8 pixels For fonts the comments also indicate the starting character and the ending character code with the following line make call to glFontInit amp fi 6 8 32 127 fontBitMap The fourth argument is the first character code mapped to the font and the fifth argument is the last character code mapped to the font PK2600 Graphics Programming 119 To initialize a font information structure of type struct _fontInfo you can call g1FontInit for a font stored in root memory or g1XFontInit for a font stored in xmem To display a bitmap call g1PutBitmap to display a bitmap stored in root memory and call g1XPutBitmap to display a bitmap stored in xmem 120 Graphics Programming PK2600 ArPENDIXx A TROUBLESHOOTING Appendix A provides procedures for troubleshooting system hardware and software The following sections are included Out of the Box Dynamic C Will Not Start Finding the Correct COM Port and Baud Rate PK2600 Repeatedly Resets Troubleshooting Software PK2600 Troubleshooting 121 Out of the Box Check the items listed below bef
112. her vertices in the x first order Fill a Circle void glFillCircle int xc int yc int r Similar to g1PlotCircle but paints the circle solid Fill a Polygon void glFillPolygon int n int xl int yl Similar to g1P1otPolygon but paints the polygon solid Note that this function works for polygons with concave angles Draw a Bitmap void glPutBitmap int x int y int w int h char bm Or void glXPutBitmap int x int y int w int h unsigned long xBm x y 15 the location of the upper left corner of the bitmap w is the width h is the height of the bitmap bm points to the first byte of the bitmap xBm is the physical address of the bitmap 11 the bitmap is stored in xmem instead of root memory PK2600 Graphics Programming 115 Printing Text Printing text involves setting the font information structures Call void glFontInit struct _fontInfo pInfo char pixWidth char pixHeight unsigned startChar unsigned endChar char bitmapBuffer to initialize a font information structure if the font is stored in root memory pInfo points to a font information structure pixWidth is the width of each character fixed pitch pixHeight is the height of each character startChar is the ASCII code of the first character in the font endChar is the ASCII code of the last character in the font and bitmapBuffer points to the font table stored in root memory Call void glXFontInit struct _fontInfo pInfo ch
113. ical_addr Allocate data location by declaring the byte arrays as initialized arrays or declare an initialized xdata array If byte array is declared convert logical memory to physical memory with phy_adr array For initialized xdata you can pass the array name directly 108 Software Development PK2600 PARAMETERS physical addr is the absolute data location in the flash EPROM buf is a pointer to the bytes to write count is the number of bytes to write RETURN VALUES 0 ifWriteFlash is okay 1 if the program flash EPROM is not in used 2 if physical_addr is inside the BIOS area 3 if physical_addr is within the symbol area or the simulated EEPROM area 4ifWriteFlash times out The following functions from the Dynamic C SYS LIB library are associ ated with the second flash EPROM on the display board e int sysChk2ndFlash struct flashInfo pInfo Checks for the existence and configuration of the second flash EPROM mapped to memory space PARAMETER pInfo is a pointer to struct _flashInfo which stores the configuration of the flash RETURN VALUE 01s returned if the second flash EPROM exists and the configuration is valid otherwise a negative number is returned void sysRoot2FXmem struct flashInfo pInfo void src unsigned long int dest unsigned integer len Copies memory content from the root memory space to the second flash EPROM mapped to memory space PARAMETERS pInfo isa pointer to struct
114. igital inputs outputs XP8200 Universal Input Output Board 16 universal inputs 6 high current digital outputs XP8300 Two high power SPDT and four high power SPST relays XP8400 Eight low power SPST DIP relays 8500 11 channels of 12 bit A D converters XP8600 Two channels of 12 bit D A converters XP8700 One full duplex asynchronous RS 232 port XP8800 One axis stepper motor control XP8900 Eight channels of 12 bit D A converters GND 25 VCC 5 V Multiple expansion boards may AOX 23 RE be linked together and connected LCDX 21 WRX D1X 19 DOX to a Z World controller to form Dax 17 D2X an extended system D5X 15 DAX Figure E 1 shows the pin layout END 1 for the PLCBus connector GND 9 2 GND 7 GND 5 strobe STBX 24 V 3 attention AT 5 V VCC 1 GND Figure E 1 PLCBus Pin Diagram PK2600 162 PLCBus Two independent buses the LCD bus and the PLCBus exist on the single connector The LCD bus consists of the following lines LCDX positive going strobe RDX negative going strobe for read WRX negative going strobe for write A0X address line for LCD register selection DO0OX D7X bidirectional data lines shared with expansion bus The LCD bus is used to connect Z World s OP6000 series interfaces or to drive certain small liquid crystal displays directly Figure E 2 illustrates the connection of an OP6000 interf
115. in gain and an A D converter excursion approaching 10 The same caveat applies to the bias network Using 1 resistors allows a more precise choice of values 56 Hardware Configurations PK2600 Figure 4 16 illustrates the result of adjusting the resistor values so that the input signal to the A D converter stays within its specified 2 5 V range A D converter s input voltage S limit E e Op amp output voltage Oo deviation arising from resistor variations E 5 5 lt 0 10 Analog Input V Figure 4 16 Proper Input Range 7 Confirm performance If your measurements are critical check setups after installing resistors by measuring test signals at and near the input voltage limits See if the voltages fall within the A D converter s input range or if accuracy is lost due to over excursions at the A D converter s input Another method 18 to measure the resistance of the factory installed fixed resistors before selecting your own resistors You can indirectly measure the fixed resistors after installation by measur ing the voltages at the amplifiers inputs and outputs See Figure 4 17 PK2600 Hardware Configurations 57 VRn VOUT ANAO ANA7 TL 4 Rn Figure 4 17 Signal Conditioning Test Points Using Channel 0 as an example ground the input AO at pin 1 011111 Then measure the voltages at VRO and the amplifier s output Because the curr
116. iode NMI Nonmaskable Interrupt PIO Parallel Input Output Circuit Individually Programmable Input Output PRT Programmable Reload Timer RAM Random Access Memory RTC Real Time Clock SIB Serial Interface Board SRAM Static Random Access Memory UART Universal Asynchronous Receiver Transmitter Icons Table 2 displays and defines icons that may be used in this manual Table 2 Icons Icon Meaning Icon Meaning oy Refer to or see Note I ER Please contact Ti A Caution A High Voltage Factory Default x About This Manual PK2600 Conventions Table 3 lists and defines the typographic conventions that may be used in this manual Table 3 Typographic Conventions Example Description while Courier font bold indicates a program a fragment of a program or a Dynamic C keyword or phrase IN 01 Program comments are written in Courier font plain face Italics Indicates that something should be typed instead of the italicized words e g in place of filename type a file s name Edit Sans serif font bold signifies a menu or menu selection An ellipsis indicates that 1 irrelevant program text is omitted for brevity or that 2 preceding program text may be repeated indefinitely Brackets in a C function s definition or program segment indicate that the enclosed directive is optional gt lt Angle brackets occasionall
117. ion channel 1 determines how frequently the DMA device transfer memory to I O Each transfer corresponds to one edge in the previous section Refer to the Zilog user s manual for more information on how GY to setup the CKA1 frequency for the Z80180 Z180 or to the Hitachi user s manual for the 64180 MPU The driver does include a function dmapwmInit that sets up the fre quency of CKA1 The function is described later in this appendix The PWM interface sets up CKAI to clock at 76 800 Hz in the call _eioSetupAOlst PK2600 Advanced Topics 183 5 Refresh the DMA counter and source address The DMA device does not automatically reload the counter and source address registers when the specified amount of bytes is transferred When the DMA device finishes transferring the specified amount of bytes it stops and optionally causes an interrupt In other words the PWM waveform is abruptly ended when the DMA finishes To overcome this limitation the application program must periodically refresh the counter and source address registers of the DMA device The refresh should check whether the counter is less than a critical number If so both the counter and the source address registers must be wound to a previous state a larger counter value and a corresponding lower source address Note that the PWM waveforms cannot be disrupted while it is refreshing the registers In other words the previous state to which the refres
118. ion with the EEPROM simulated EEPROM in the display board is unused at the present time but addresses 0 and 1 are reserved for future use Do not use these addresses in your application 74 Subsystems PK2600 Power Regulation The display board was designed to operate from a 12 V to 30 V DC source and consumes about 4 5 W with the backlight on 1 5 W with the backlight off To allow for a surge current when the PK2600 is first turned on the power supply used must be able to handle at least four times this power for example 800 mA at 24 V The display board power is converted internally to supply three voltages 1 Aswitching regulator outputs VCC 5 V 2 A linear regulator outputs VEE approximately 20 V 3 A high voltage section supplies 300 V rms to drive the cold cathode fluorescent backlight The backlight can be turned on or off under software control whereby a high on the gate of Q3 enables Q1 and Q2 to oscillate and a low turns off Q3 stopping the oscillation of Q1 and Q2 Figure 5 4 shows these internal power supplies in a block diagram VCC 12 30 V DC gt mE J10 9 2575 Sw Reg F 1 U27 2951 Lin Power VEE J11 5 025 023 12 30 V DC gt gt 7662 7662 Sw Reg Sw Reg voc Backlight 300 V rms 32 7 kHz Power to CCFL backlight Q3 from EPLD V Figure 5 4 Block Diagram of Display Board Internal Power Regulators PK26
119. ize 203 mm x 137 mm x 4 0 mm with gasket Operating Temperature 0 C to 50 C may be stored at 20 C to 70 C Humidity 25 to 65 noncondensing 15 V DC to 30 V DC 8 7 W with backlight on 5 7 W with backlight off Replaceable dual cold cathode fluorescent tube rated at 20 000 h to 30 000 h with software on off control FSTN 320 x 240 pixels blue on white back ground Pixel matrix is 115 2 mm x 86 4 mm 0 36 mm pitch Viewing area is 121 mm x 91mm Adjustable contrast with temperature compensation Power Backlight LCD 8 x 8 matrix 225 touch switches rated 10 con Touchscreen tacts 16 standard continuous operation from 20 V to 24 V logic threshold at 2 5 V protected against spikes 48 V 10 kQ pull up or pull down resis tors Digital Inputs 16 standard at 25 C one channel can sink up to Digital Outputs 500 mA continuously load limit is 48 V Ten 12 bit channels 8 conditioned factory configured 0 V to 10 V e 2 unconditioned 0 V to 2 5 V Analog Inputs Pulse width modulated on digital output lines up to 7 channels 7180 at 18 432 MHz controller Z180 at 18 432 MHz display Analog Outputs Processor continued 126 Specifications PK2600 PK2600 General Specifications concluded Table B 1 Specification 32K standard supports up to 512K controller 128K standard supports up to 512K display 128K standard supports up
120. l interrupts occur in a different manner Instead of loading the address of the interrupt routine from the interrupt vector these interrupts cause a jump directly to the address of the vector which contains a jump instruction to the interrupt routine The following example illustrates a jump vector 0x66 nonmaskable power failure interrupt Since nonmaskable interrupts NMI can be used for Dynamic C communi cations an interrupt vector for power failure is normally stored just in front ofthe Dynamic C program Use the command JUMP_VEC NMI name to store the vector here The Dynamic C communication routines relay to the jump vector when the NMI is caused by a power failure rather than by a serial interrupt 142 Memory I O Map and Interrupt Vectors PK2600 Interrupt Priorities Table C 7 lists the interrupt priorities Table C 7 Interrupt Priorities Interrupt Priorities Highest Priority Trap illegal instruction NMI nonmaskable interrupt INT 0 maskable interrupts Level 0 three modes INT 1 maskable interrupts Level 1 PLCBus attention line interrupt INT 2 maskable interrupts Level 2 PRT Timer Channel 0 PRT Timer Channel 1 DMA Channel 0 DMA Channel 1 2180 Serial Port 0 Lowest Priority Z180 Serial Port 1 2600 Memory I O and Interrupt Vectors 143 Blank 144 Memory I O Map and Interrupt Vectors PK2600 APPENDIX D Circuir BoARD RE
121. lated PWM outputs This section provides information on the Dynamic C software drivers for the controller board s high voltage driver outputs The following software function turns a specified high voltage driver ON or OFF unsigned BankA unsigned eioAddr unsigned BankB unsigned eioAddr BankaA converts eioAddr to a value of 16 31 for addressing the correct input or output assignments BankB converts eioAddr to a value of 0 15 PARAMETER eioAddr specifies channel number from 0 15 RETURN VALUE the formatted I O assignment or 1 if the parameter eioAddr is out of range int eioBrdDO unsigned eioAddr char state Sets the state of a digital output Sets eioErrorCode if parameter eioAddr is out of range PARAMETERS eioAddr specifies the output to be set Valid numbers are from 0 to 31 0 15 represents Bank B 16 31 represents BankA state is the desired output state for the specified output A non zero value turns the output on A zero turns the output off RETURN VALUE Returns 0 if successful 1 if eioAddr is out of range void outport unsigned port unsigned value Writes data to an I O port PARAMETERS port is the PK2600 controller board port address to be written When used to write to the digital outputs port is one of four groups of eight outputs There are two groups of eight outputs for each bank value is the data to be written to the port When used to write to the digital outputs data bits D
122. le if output 0 is to have a 0 375 duty cycle output 1 is to be at 0 75 duty cycle and the resolution is 8 divisions per cycle a simple wave form would be as follows CT1 turn on output 0 turn on output 1 CT2 do nothing CT3 do nothing CT4 turn off output 0 CTS do nothing CT6 do nothing CT7 turn off output 1 8 do nothing Go back to CTI 182 Advanced Topics PK2600 Outputting the byte 0x01 turns on output 0 0x00 turns off output 0 0x03 turns on output 1 and 0x02 turns off output 1 The byte OxOE is an no op and it does nothing The composite transitions with no ops can be translated into the following byte sequence to be sent to the I O address 0x4100 CT1 0x01 0x03 CT2 0x0E OxOE 0x0E OxOE CT4 0x00 OxOE 5 0x0E OxOE CT6 0x0E OxOE CT7 OxOE 0x02 8 0x0E OxOE Go back to CT1 The equivalent byte stream contents in the waveform pattern buffer is a repeating pattern of the following 0x01 0x03 OxOE OxOE OxOE OxOE 0x00 OxOE OxOE OxOE OxOE OxOE OxOE 0x02 OxOE OxOE The driver library provides a function dmapwmSetBuf that allows the application engineer to modify the content of the waveform pattern buffer 4 Setup the clock The DMA device transfer from memory to I O port address 0x4100 is driven by falling edges on signal DREQO Since DREQO is connected to 1 the clock output of communication channel 1 the communication speed of communicat
123. lines and bitmaps on the LCD void glFontInit struct fontInfo pInfo char pixWidth char pixHeight unsigned startChar unsigned endChar char bitmapBuffer Initializes a font descriptor with the bitmap defined in the root memory For fonts with bitmaps defined in xmem use g1XFontInit PARAMETERS pInf o is a pointer to the font descriptor to be initialized pixWidth is the width of each font item pixWidth must be uniform for all items pixHeight is the height of each font item pixHeight must be uniform for all items startChar is the offset to the first useable item useful for fonts for ASCII or other fonts with an offset endChar is the index of the last useable font item bitmapBuffer is a pointer to a linear array of the font bitmap The bitmap is a column with the major byte aligned 102 Software Development PK2600 glXFontInit struct fontInfo pInfo char pixWidth char pixHeight unsigned startChar unsigned endChar unsigned long xmemBuffer Initializes a font descriptor that has the bitmap defined in xmem For bitmaps defined in root memory use g1FontInit PARAMETERS pInfo is a pointer to the font descriptor to be initialized pixWidth is the width of each font item pixWidth must be uniform for all items pixHeight is the height of each font item pixHeight must be uniform for all items startChar is the offset to the first useable item useful for fonts for ASCII or other fonts with a
124. n offset endChar is the index of the last useable font item xmemBuffer is a pointer to a linear array ofthe font bitmap The bitmap is a column with the major byte aligned void glSetBrushType int type Sets the type of brush type and controls how pixels are drawn on the screen until the next call to g1SetBrushType PARAMETER type is the type ofthe brush The four macros described below have been defined for valid values to pass to the function Macro Description Effect Pixels specified by subsequent g1 LCDPix LCDPix newPix pixels Pixels specified by subsequent g1 LCDPix i LCDPix amp newPix pixels Pixels specified by subsequent g1 LCDPix functions will toggle the LCD pixels LCDPix newPix Pixels specified by subsequent g1 GL_BLOCK functions will be displayed on the LCDPix newPix LCD as is All four brush types can be used to display text or bitmaps Do not use GL BLOCK for g1Plot or g1Fill graphics primitive functions PK2600 Software Development 103 GL_SET functions will turn on the LCD GL_CLEAR functions will turn off the LCD e int glInit Initializes the LCD module software and hardware RETURN VALUE the status ofthe LCD Ifthe initialization was successful this function returns 0 Otherwise the returned value indicates the LCD status e int glPlotDot int x int Plots one pixel on the screen at coordinate x y PARAMETERS xis the x coordin
125. n on the backlight If you have a PK2600 equipped with software contrast control call op71SetContrast unsigned level to change contrast The range of level is from 0 to 127 A level of 63 usually yields reasonable contrast at room temperature Drawing Primitives You can draw various objects on the LCD Before doing any drawing specify the type of the brush by calling glSetBrushType int flag Four brush macros are supported GL SET sets the pixels as specified by the plot commands but leaves other pixels alone GL CLEAR clears the pixels as specified by the plot commands but leaves other pixels alone GL toggles the pixels as specified by the plot command but leaves other pixels alone GL BLOCK forces the value of pixels in groups of eight vertical pixels GL BLOCK is useful when speed is important the current pixels need to be overwritten and the overwriting pixels are aligned in eight pixel rows Plot a Pixel int glPlotDot int x int y x and y are the coordinates the upper left corner is 0 0 114 Graphics Programming PK2600 Plot a Line e void glPlotLine int xl int yl int x2 int y2 x1 y1 and x2 y2 are the endpoints of the line Plot a Circle void glPlotCircle int xc int yc int xc yc is the center of the circle is the radius Plot a Polygon void glPlotPolygon int n int xl int yl nis the number of vertices x1 y1 is the first vertex followed by the ot
126. n the range of 4 50 V to 4 75 V DC This causes the power fail routine to be invoked The power fail routine can be used to store important state data Use a power supply with large capacitance if you need to D increase the holdup time This will provide additional time for the controller board to execute a safe shutdown 3 The power management IC switches power for the time date clock and SRAM to the lithium backup battery when the regulated voltage falls below the battery voltage of approximately 3 V DC 4 The 691 power management IC keeps the system in reset until the regulated voltage drops below 1 V DC At this point the power management IC ceases operating By this time the portion of the circuitry not battery backed has already ceased functioning The ratio of your power supply s output capacitor s value to your circuits current draw determines the actual holdup time A situation similar to a continuous low input brownout can occur if the power supply is overloaded For example when a high current device such as a relay turns ON the raw voltage supplied to the PK2600 may dip below 14 44 V DC The interrupt routine performs a shutdown This shutdown turns off the relay clearing the problem However if the cause of the overload persists the system oscillates alternately experiencing an overload and then resetting Using a power supply with a sufficiently large current capacity will correct this problem I
127. namic C directory under SAMPLES BL17XX PK2600 Software Development 97 Analog Inputs The PK2600 s analog inputs provide an easy to use interface to a wide variety of sensors and transducers The PK2600 provides 10 single ended A D conversion channels with 12 bit resolution Using the Analog Inputs The factory calibrates each PK2600 storing each unit s individual zero offset and actual gain for its eight primary channels in simulated EEPROM Your application can use library functions to access the simulated EEPROM s calibration constants to correct measurements for offset and gain error void eioBrdInit int flags Initializes the analog to digital converter to the default output mode The default mode is unipolar input 12 bit data length most significant bit first PARAMETER flags is not used at this level and should be set to 0 Call e oBrdInit before calling eioBrdAI int eioBrdAI unsigned eioAddr Reads one of the 10 voltage inputs and performs analog to digital conversion Sets e3oErrorCode if eioAddr is out of range PARAMETER eioAddr specifies an input number of 0 to 9 or 16 to 25 to be read eioAddr values 0 through 9 represent analog inputs 0 through 9 and will cause the function to return the voltage read on an input eioAddr values 16 through 25 also represent analog inputs 0 through 9 but cause the function to return a 12 bit raw data value for the analog input RETURN VALUE The function re
128. nd 8 bit addressing modes must coexist the lower four bits of the first address byte written to BUSADRO identify addressing categories and distinguish 4 bit and 8 bit modes from each other There are 16 address categories as listed in Table E 3 An x indicates that the address bit may be a 1 or a 0 Table E 3 First Level PLCBus Address Coding First Byte Mode Addresses Full Address Encoding 0000 206 4bitsx3 0 0 0 0 xxxx xxxx 0001 206 1 0 xxxx xxxx 0010 256 0010 0011 256 0011 Sbitsx3 2 048 x0100 0 0 1 0 0101 xxxxx 2 048 1 1 0 0110 xxxxx 2 048 0 1 1 0 0111 2 048 1 1 0 1000 16 384 63 0 100 01 16 384 1001 xxxxxx xx1010 4 61 1010 4bitsx1 1 1011 expansion register 1011 1100 4 096 2 1100 8 bits x bits x 3 1M 1101 xxxxxxxx 8 1101 8bitsx1 16 xxxx1110 1110 1111 8 bits x 1 16 xxxx1111 This scheme uses less than the full addressing space The mode notation indicates how many bus address cycles must take place and how many bits are placed on the bus during each cycle For example the 5 x 3 mode means three bus cycles with five address bits each time to yield 15 bit addresses not 24 bit addresses since the
129. nd is con nected to the display board Channel 0 is a dedicated RS 232 communica tion channel The remaining two channels may be either RS 232 or RS 485 Channel 0 and Channel 1 are connected to the Z180 s Serial Channel 0 and Serial Channel 1 respectively Channel A and Channel B are controlled by the Serial Communications Controller SCC chip on the controller board these two ports also have hardware support for synchronous communica tion Serial channel signals are routed to either RS 232 or RS 485 convert ers via configuration jumpers Baud rates up to 57 600 bps are supported Table 4 8 summarizes the operating modes for the four channels Table 4 8 Serial Channel Configuration Options Configurations Channel 0 Three wire or five wire RS 232 only Channel 1 Three wire RS 232 connection to display board Channel A Two wire RS 485 or five wire RS 232 plus DCD and DTR Channel B Two wire RS 485 or five wire RS 232 0 Channel 0 may be used as the controller board s RS 232 programming port and is configured as three wire or five wire RS 232 Channel 0 cannot be reconfigured Channel A Channel A is a general purpose serial channel controlled by a Zilog Serial Communication Controller SCC chip on the controller board Channel A can be configured as two wire RS 485 or five wire RS 232 When config ured as RS 232 Channel A also provides DCD and DTR signals Synchro nous
130. nels but is not supported by Dynamic C drivers at this time Figure 3 8 provides the factory default pinouts for the three serial ports SERIAL PORT 1 SERIAL PORT 3 gg 2g 2 BS 2 A N NN 2 2 0 0 Of Ow oo o2 0 Of Ow 2320150 O 232RTSB 0 2323150 oo 232CTSB 0 SERIAL PORT 2 232RXA GND On 232TXA O 2320 Ow 232RTSA oo 232CTSA xo 232DCDA oo Figure 3 8 Serial Port Pinouts Chapter 4 Hardware Configurations provides instructions Gv toreconfigure SERIAL PORT 2 and SERIAL PORT 3 for RS 485 serial communication 32 Hardware Features PK2600 PLCBus The PLCBus connector on the PK2600 allows expansion boards to be connected to the PK2600 Expansion boards allow additional I O A D converters D A converters relay boards and stepper motor controllers to be connected to the PK2600 Refer to Appendix E PLCBus for more detailed information the PLCBus and Z World s expansion boards PK2600 Hardware Features 33 Blank 34 Hardware Features PK2600 4 Chapter 4 describes alternative hardware configurations for the PK2600 The back cover of the PK2600 must be removed and some boards need to be taken apart to access the appropriate configuration jumpers The following sections are included PK2600 Assembly Digital Inputs and Outputs CHAPTER 4 HARDWARE CO
131. nnel 1 Used for LCD and display board J7 J7 1 1 2 Channel A 3 3 4 5 5 6 7 7 8 J7 1 1 2 Channel B 3 3 4 5 5 6 7 7 8 Serial channels 0 A and B are brought out to the 62600 SERIAL PORT DE connectors through the I O conversion module The pinouts for SERIAL PORT 2 and SERIAL PORT 3 are shown in Figure 4 19 SERIAL PORT 2 SERIAL PORT 3 5 8 55 5 x 5 5 ZNAN OCNNN 543 21 543 2 1 9 8 7 6 9 8 7 6 gt gt lt INNA 0 0 9 Oo DIAJ 5 8 8 Figure 4 19 PK2600 09 Pinouts for Serial Channels A and B PK2600 Hardware Configurations 67 PLCBus Some PLCBus expansion boards use the AT line on the PLCBus Jumpers on the PK2600 controller board s header J4 determine whether the INT1 signal is connected to the PLCBus AT line as shown in Table 4 12 If you intend to use a PLCBus expansion board that uses the AT signal make sure that a jumper is installed in the JP4 7 8 position If you want to use the INTI signal for another external signal and it is not needed for the PLCBus then remove the jumper from the J4 7 8 position Table 4 12 PK2600 PLCBus Jumper Settings INT1 used as AT on PLCBus INT1 external use only o NW OQ 68 Hardware Config
132. nstead of zero In software ordinal series often begin or terminate with zero not one e Confusing a function s definition with an instance of its use in a listing Not ending statements with semicolons Not inserting commas as required in functions parameter lists Leaving out ASCII space character between characters forming a different legal but unwanted operator Confusing similar looking operators such as amp amp with amp with and with nadvertently inserting ASCII nonprinting characters into a source code file Ifthe DMA driven PWM correctly drives the output for a while then suddenly some channels remain ON others remain off most likely the function _eioBrdAORE is not called frequently enough There are three possible solutions 1 Increase the frequency of calling 610202094 2 Increase the size of the waveform pattern buffer 3 Slow down the clock CKA1 124 Troubleshooting PK2600 B SPECIFICATIONS Appendix B provides comprehensive PK2600 physical electronic and environmental specifications PK2600 Specifications 125 Electronic and Mechanical Specifications Table B 1 lists the electronic mechanical and environmental specifications for the PK2600 Table B 1 PK2600 General Specifications Parameter Specification Enclosure Back 4 511 x 6 930 x 2 500 Cover Size 115 mm x 175 mm x 63 5 mm 8 00 x 5 4 x 0 156 Front Bezel S
133. ntroller Board Bank Digital Input Jumper Configurations Jumper Settings Channe Inputs Pulled Up Inputs Pulled Down wo Physical Channels 24 27 Occ zx o HVA 4 7 Bank A 1 Channels 3 12 15 5 7 9 Physical Channels 28 31 2 2 8 15 Bank A 1 Channels 3 0 7 5 Physical 7 Channels 9 16 23 Lh HVA 0 3 2 2 Bank A Channels 4 i 8 11 6 6 8 e 8 e e PK2600 Hardware Configurations 43 Table 4 2 62600 Controller Board Bank B Digital Input Jumper Configurations Jumper Settings Inputs Pulled Up Inputs Pulled Down J3 c HVB 0 3 Bank B Channels 0 3 N Physical Channels 0 3 on aw gt on aw e e e Ex 12 HVB 4 7 Bank B Channels 4 7 Physical Channels 4 7 J3 J3 HVB 8 15 emm 1 Bank B Channels 3 8 15 5 7 9 Physical Channels 8 15 x N The high voltage driver chips must be removed from Bank B 54 and interface chips must be installed before the Bank inputs can be used as digital inputs 44 Hardware Configurations PK2600
134. o store the result text file of the conversion Click OK when the file is specified 5 The title bar displays inactive when the conversion is done Close the window Dynamic C may be used to edit the text file that was generated The generated file typically looks as follows Automatic output from Font Converter font file is U TEST DC5X SAMPLES QVGA 6X8 OUT dfVersion 0x300 dfSize 5148 dfCopyright c Copyright 1997 1998 Z World All rights reserved dfType 0x0 horizontal size is 6 pixels vertical size is 8 pixels first character is for code 0x20 118 Graphics Programming PK2600 last character is for code Oxff make call to glFontInit amp fi 6 8 32 127 fontBitMap to initialize table char fontBitMap char 0x20 of width 6 at Ox5da x0 x0 x0 x0 x0 x0 0 x0 0 The first task is to rename the array so that it is unique Then you decide whether the font bitmap should be stored in root memory or in extended memory Because bitmaps can be large and root memory space is precious Z World recommends you to use xmem to store the font bitmap To store the font bitmap in xmem you need to change the following line char fontBitMap to xdata fontBitMap Once these changes are made you can copy and paste the font as an initialized character array or as an initialized xdata item into your program or library Remember to tuse eit
135. o the keypad non zero if there is any change to the keypad 106 Software Development PK2600 int kpDefStChgFn char curState char changed This 18 the default state change function for the default get key func tion kpDefGetKey This function is called back by kpscanstate when there is a change in the keypad state If the current key 1s not read by kpDefGetKey the new key pressed will not be registered PARAMETERS curState points to an array that reflects the current state of the keypad bitmapped 1 indicates key is not currently pressed changed points to an array that reflects the CHANGE of keypad state from the previous scan bitmapped 1 indicates there was a change RETURN VALUE 1 ifno key is pressed Otherwise kpScanState returns the normalized key number The normalized key number is 8 rowtcoltedge 256 edge is if the key is released and 0 the key is pressed int kpDefGetKey This 18 the default get key function It returns the key previously pressed 1 e from the one keypress buffer The key pressed is actually interpreted by kpDe StChgFn which is called back by kpScanState kpDefInit should be used to initialize the module RETURN VALUE 1 if no key is pressed Otherwise kpDefGetKey returns the normalized key number The normalized key number is 8 rowtcoltedge 256 edge is if the key is released and 0 the key is pressed void kpDefInit Initializes the library to use the default state chan
136. onductor RJ 12 phone cable connects the SIB2 to the host PC The SIB2 automatically selects its baud rate to match the communication rates established by the host PC 9600 19 200 or 57 600 bps However the SIB2 determines the host s communication baud rate only on the first communication after reset To change baud rates change the COM baud rate reset the target PK2600 board which also resets the SIB2 then select Reset Target from Dynamic C Chapter 2 provides detailed information on connecting the SIB2tothe PK2600 The SIB2 receives power and resets from the target board on the PK2600 via the 8 pin connector J1 Therefore do not unplug the SIB2 from the PK2600 while power is applied To do so could damage both the PK2600 and the SIB2 additionally the target may reset Never connect or disconnect the SIB2 with power applied to the controller The SIB2 consumes approximately 60 mA from the 5 V supply The target system current consumption therefore increases by this amount while the SIB2 is connected to the PK 2600 174 Serial Interface Board 2 PK2600 External Dimensions Figure F 1 illustrates the external dimensions for the SIB2 Serial Interface Borro Board 2 Top View 12 0 3 60 305 91 4 0 8 20 1 525 i l G87 1625 41 3 Side View Figure F 1 SIB2 External Dimensions PK2600 Serial Interface Board 2 175 Blank 176 Serial Interface Board 2 PK26
137. onnected to the PK2600 as described in Chapter 2 Getting Started in the user s manual connect the SIB2 to the DISPLAY or the CONTROLLER port on the back ofthe PK2600 as shown in Figure 1 A CAUTION High Voltage H Transformer Only qualified persons may open this case ANALOG INPUTS SERIAL PORT 1 6 4 Bonon Marked WRUN Conductor i Dc toPin1 DIGITAL GROUP 2 SERIAL PORT 2 000 CONTROLLI 7 5 o 2 5 DIGITAL GROUP 1 SERIAL PORT 3 J 5 e Je ee 5 2900 SPAFFORD ST DAVIS 95616 1 530 757 3737 WWW ZWORLD COM To 120 v Serial Interface 9 amp Board 2 CN Figure 6 3 PK2600 SIB2 and Power Supply Connections 110 Software Development PK2600 With Dynamic C installed on your PC download the PK26CONT 6 and the PK26DISP C sample programs from the Z World Web site e PK26CONT C illustrates the use of the controller board Use 26 with the SIB2 connected to the CONTROLLER header on the back ofthe PK2600 e PK26DISP C illustrates the use of the display board Use PK26DISP C with the SIB2 connected to the DISPLAY header on the back of the PK2600 The communication rate port and protocol are all selected by choosing Serial Options from Dynamic C s OPTIONS menu The SIB2 and the PK2600 both set their baud ra
138. ore starting development Rechecking may help to solve problems found during development Do not connect any boards with PLCBus RS 485 or any other I O devices until you verify that the PK2600 runs standalone Verify that your entire system has a good low impedance ground The PK2600 is often connected between the PC and some other device Any differences in ground potential from unit to unit can cause serious hard to diagnose problems Double check the connecting cables Do not connect analog ground to digital ground anywhere Verify that your PC s COM port actually works Try connecting a known good serial device to your COM port Remember that on a PC COM1 COM3 and COM2 COMA share interrupts User shells and mouse software particularly often interfere with proper COM port operation For example a mouse running on COMI can preclude your running Dynamic C on COM3 unless the interrupt is changed Use the supplied Z World power supply If you must use your own power supply verify that it has enough capacity and filtering to support the PK2600 Use the supplied Z World cables The most common fault of home made cables is their failure to properly assert CTS at the RS 232 port of the PK2600 Without CTS s being asserted the PK2600 s RS 232 port will not transmit You can assert CTS by either connecting the RTS signal ofthe PC s COM port or looping back the PK2600 s RTS Experiment with each peripheral device you connect to y
139. our PK2600 to determine how it appears to the PK2600 when it is powered up pow ered down when its connecting wiring is open and when its connect ing wiring is shorted 122 Troubleshooting PK2600 Dynamic 6 Will Not Start If Dynamic C will not start an error message on the Dynamic C screen for example Target Not Responding or Communication Error announces a communication failure The following list describes situations causing an error message and possible resolutions Wrong Communication Mode Both sides must be talking RS 232 Wrong COM Port A PC generally has two serial ports COMI and COM2 Specify the one being used in the Dynamic C Target Setup menu Use trial and error if necessary Some PCs have special programs to reconfigure their port assignments You may need to run such a program to make a given COM port appear at an external back panel D connector Wrong Operating Mode Communication with Dynamic C will be lost when the PK2600 is configured for standalone operation Make sure the DIP switch on the back of the PK2600 is set to PROGRAM mode as described in Chapter 2 Getting Started for the controller board or the display depending on which board is to be programmed You need to reset the PK2600 by unplugging the transformer from the wall waiting a moment then plugging the transformer back If all else fails connect the serial cable to the PK2600 after power up If the PC s
140. pAO1st makes the following assumptions N 4 J 76 800 Hz R 256 Consequently f 76 800 Hz 4 x 256 75 Hz 2 Declarestorage for the WPB waveform pattern buffer Memory must be allocated to store the waveform pattern PK2600 Advanced Topics 181 3 Setup the waveform The PWM functions use the Z180 s built in DMA mechanism to transfer PWM edges from memory to the high current ports at specific time intervals Each edge is a byte whose least significant four bits select one of the high current outputs output 0 through output 6 The least signifi cant bit is a 1 to turn the specified port on rising PWM edge or a 0 to turn the specified port off falling PWM edge Edges for the channels being pulse width modulated are then grouped into composite transitions Each composite transition is a series of edges each representing one possible transition for an individual channel For example if output 0 and output 1 are the only pulse width modulated channels a composite transition consists of two bytes The first byte specifies a possible transition for channel output 0 The second byte specifies a possible transition for channel output 1 Let us assume the first byte in the composite transition corresponds to output 0 and the second byte corresponds to output 1 The composite PWM waveform is a series of composite transitions CTs that specify the duty cycle of the pulse width modulated channels For examp
141. power to driver circuitry inside the driver chip 2 also allows a diode internal to the driver chip to snub voltage transients produced during the inductive kick associated with switch ing inductive loads Relays solenoids and speakers are examples of inductive loads Long leads may present enough induction to also produce large potentially damaging voltage transients The anodes of the protection diodes for each channel are common and so only one voltage supply can be used for all high voltage driver loads The following points summarize the functions of K provides power to the driver chip circuitry Kprovides clamping for all high voltage driver loads tis mandatory to connect K regardless of whether sourcing or sinking Theload s supply must have a common ground with all other supplies in your system All loads must use same supply voltage Refer to Figures 4 11 and 4 12 when connecting K PK2600 Hardware Configurations 49 To PK2600 Controller Board K Connection To Load Power DC source K Connection LOAD Sinking Configuration To BL1700 High Voltage Output Figure 4 11 K Connections Sinking Configuration To PK2600 Controller Board K Connection To Load Power DC source To BL1700 High Current Output K Connection POD Sourcing Configuration Figure 4 12 K Connections Sourcing Configuration K must be connected to the power supply used for the high volta
142. quare wave s period is exactly 1024 divisions One division equals 120 clock cycles 120 9 216 MHz 13 02 us for the PWM function Consequently the period of each square wave 1s 1024 x 13 02 us 13 33 ms Notice also that the square waves are displaced slightly from each other in phase That is output 1 s output starts and ends one division after output 0 s output 2 s one division after output 1 s and output 3 s one division after output 2 s As a result although the period of each wave is 1024 divisions a change to one particular channel is possibly only every 4 divisions Therefore the resolution of the transition edge in the wave is 1 256 PWM Software The supplied software provides two levels of support The first level provides easy to use fixed PWM functions for only four of the outputs outputs 0 3 The periods of the PWM signals are fixed at 13 3 ms 75 Hz with a resolution of 256 division per period 8 bit resolution Using the supplied software generating PWM signals consumes about 8 of the controller s processing power The second PWM support level allows you to create custom PWM functions for seven of the outputs outputs 0 6 96 Software Development PK2600 The following three functions are the first level functions They are designed for ease of use These functions are located in EZIODPWM LIB that is automatically included when EZIOBL17 LIB is included e int eioBrdAO unsigned eioAd
143. r DMA driven PWM In other words dmapwmSetBuf does the following starting at the address pointed to by pBufStart for bufLength256 many 256 byte pages change every step bytes to outChar PARAMETERS pBu Start points to the first byte to be formatted Note that pBu Start does not always have to point to a 256 byte aligned address bufLength256 is the length of the buffer including the overflow area step is the number of bytes to skip between outputting outChar outChar is the actual bytes to send to the I O address PK2600 Advanced Topics 185 void dmapwmSwBuf unsigned newBuf256 In order to facilitate all or none duty cycle transitions you should use two buffers While one buffer is being used by the DMA mechanism to generate the PWM output modify the other buffer for the new PWM pattern When the new buffer is ready this function should be called to switch to use the buffer at the address pointed to by newBu 256 in 256 byte units char dmapwmBufBeg char bufPtr The buffer used by the PWM mechanism starts at 256 byte boundaries Normal data definition declarations such as char buffer 0x2000 start at byte boundaries dmapwmBufBeg returns a character pointer that points to the first 256 byte aligned root address larger than or equal to the parameter bu Ptr void dmapwmInit unsigned phyBuffer256 unsigned bufSize256 unsigned resSize256 unsigned ioAddr char ckalrate Initializes the DMA PWM mechanism
144. rary functions provide an easy and robust interface to the PK2600 Dynamic C Deluxe must be used when developing applications for the 2600 The standard version of Dynamic does not allow sufficient access to extended memory Z World s Dynamic C reference manuals provide complete software descriptions and programming instructions 18 Overview PK2600 2 Chapter 2 provides instructions for connecting the PK2600 to a host PC and running a sample program The following sections are included Initial PK2600 Setup Connecting the PK2600 to a Host PC Establishing Communication with the PK2600 2 GETTING STARTED e Running a Sample Program PK2600 Getting Started 19 Initial PK2600 Setup Parts Required 24 V unregulated DC power supply capable of delivering up to 1 1 A included only in Developer s Kits for North America DE9to DE serial cable The necessary parts are supplied with the Developer s Kit The PK2600 Developer s Kit also includes the following items Three DB25 male plugs and covers to allow custom I O cable assem blies to be made Extended PLCBus ribbon cable PK2600 User s Manual with schematics this document Setting Up the PK2600 1 Remove the green power con nector shown in Figure 2 1 from n 9 the back of the PK2600 GND 2 Attach the bare leads from the GND D to i Duis power supply to the power con GND nector as shown in Fi
145. re sourcing sinking modes for the outputs on Bank B Jumpers on H2 configure sourcing sinking modes for the outputs on Bank A if it is configured for output Tables 4 3 and 4 4 show the jumper settings for sinking and sourcing configurations The sinking driver chips used on the PK2600 controller board are ULN2803 or equivalent The sourcing driver chips are UDN2985 or equivalent To configure drivers for sinking outputs default for Bank B install the ULN2803 driver chips in the appropriate socket locations For sourcing outputs install UDN2985 driver chips PK2600 Hardware Configurations 45 Table 4 3 62600 Controller Board Bank Digital Output Jumper Configurations pem Jumper Settings an oe Sinking Outputs Sourcing Outputs H3 H3 1 2 0 7 88 4 4 Channels 5 lee e PD 0 7 7 6 6 8 7 6 6 8 U17 ULN2803 U17 UDN2985 H3 e HVB 8 15 6 4 Channels 5 6 RO ERA 8 U7 ULN2803 U7 UDN2985 Table 4 4 PK2600 Controller Board Bank A Digital Output Jumper Configurations Jumper Settings an _ Sinking Outputs Sourcing Outputs H2 H2 1 2 1 n 2 HVA 0 7 3 4 3 4 Channels sle 6 6 sle 6 6 1 aem 7 6 6 8 8 U5 ULN2803 05 UDN2985 H2 H2 1 62 6 2
146. rive faster than they can be read from the receiver data register The receiver shift register RSR and receiver data register RDR are both full This bit is cleared by the EFR bit in CNTLA RDRF Receiver Data Register Full This bit is set when data is transferred from the receiver shift register to the receiver data register It is set even when one of the error flags is set in which case defective data is still loaded to RDR The bit is cleared when the receiver data register is read when the DCDO input pin is high and by RESET and IOSTOP 84 Subsystems PK2600 ASCI Control Register A Control Register A affects various aspects of the asynchronous channel operation CNTLAO 00H 202700226 5 4 XS 0 MPE RE TE RTSO MOD1 MODO 7 R W RW R W R W R W R W RW R W CNTLAI 01H 7 6 5 4 3 1 0 MPE RE Karo Mo R W R W R W R W R W R W R W R W MODO MOD2 Data Format Mode Bits MODO controls stop bits 0 1 stop bit 1 2 stop bits If 2 stop bits are expected then 2 stop bits must be supplied MODI controls parity 0 parity disabled 1 parity enabled See PEO in ASCI Control Register B for even odd parity control MOD2 controls data bits 0 7 data bits 1 8 data bits MPBR EFR Multiprocessor Bit Receive Error Flag Reset Reads and writes on this bit are unrelated Storing a byte when this bit 1s 0 clears all
147. rly warning power failure interrupt that lets the system know when power is about to fail Memory protection feature prevents writes to RAM when power is low Supports battery backup Handling Power Fluctuations During a normal power down an interrupt service routine is used in response to a nonmaskable interrupt NMI to save vital state information for the application for when power recovers The amount of code that the interrupt service routine can execute depends on how fast the voltage drops Theoretically a power failure would cause a single NMI Then the inter rupt service routine would restore data from the previous state when the voltage recovers However fluctuations in the DC input line could cause the 691 to see multi ple crossings of the 1 3 V input power reset threshold These multiple negative edge transitions would in turn cause the Z180 to see multiple NMIs When the Z180 generates an NMI it saves the program counter PC on the processor s stack It next copies maskable interrupt flag IEF 1 to IEF2 and zeroes IEF1 The Z180 will restore saved state information when it executes a RETN return from nonmaskable interrupt instruction Ideally the Z180 should be able to pop the stack and return to the location where the program was first interrupted But the original flag is not recoverable because the second and subsequent NMIs will have saved to IEF2 Also depending on t
148. rs on the display board Table D 8 Display Board Jumper Settings Pins Factory header Connected pueden Default 1 2 js Positive LCD background 5 6 4 blue characters on white 19 background 11 12 fes Negative LCD background 4 6 white characters on blue T background 10 12 5 P 1 2 Software contrast adjustment PK2600 2 3 Manual contrast adjustment PK2610 1 2 5 6 One 5 wire RS 232 9 10 one RS 485 11 12 JP3 1 2 One 3 wire RS 232 5 6 one RS 485 Two 3 wire RS 232 7 8 3 4 5 6 RS 485 on J11 2 3 Not JP4 available on RS 232 3 PER 7 8 12 Connect to enable termination Not J9 34 resistors disconnect to disable available on termination resistors PK2600 Headers JP3 JP4 J4 and 19 are provided for the display board to be used outside the PK2600 Do not change the factory default settings on these headers when using the display board as part of the PK2600 158 Circuit Board Reference PK2600 Keypad Interface The PK2600 has a touchscreen which is connected to the display board at header J5 Table D 9 lists the pinouts for header 15 Table D 9 PK2600 Keypad Header Pinout Signal Header J5 J6 Pin Signal Header J5 J6 Pin Rowo 1 COLO 9 Rowi 2 COL1 10 Row2 3 COL2 11 ROW3 4 COL3 12 ROW4 5 COL4 13 ROWS 6 COL5 14 ROWS6 7 COL6 15 Row7 8 COL7 16 Figure D 9 shows a simplified diagram of the keypad interface U8 U9
149. rs shown in Figure 5 6 are directly accessible as internal registers Microprocessor Internal Bus TXAO Shift Register Out Shift Register In Baud Rate Generator Figure 5 6 7180 Serial Channel 0 RTSO CTSO CNTLAO CNTLBO STATO 80 Subsystems 0 The serial ports can be polled or interrupt driven A polling driver tests the ready flags TDRE and RDRF until a ready condition appears transmitter data register empty or receiver data register full If an error condition occurs on receive the routine must clear the error flags and take appropriate action if any If the CTS line is used for flow control transmission of data is automatically stopped when CTS goes high because the TDRE flag 1s disabled This prevents the driver from transmitting more characters because it thinks the transmitter 1s not ready The transmitter will still function with CTS high but exercise care because TDRE is not available to synchronize loading the data register TDR properly An interrupt driven port works as follows The program enables the receiver interrupt as long as it wants to receive characters The transmitter interrupt is enabled only while characters are waiting in the output buffer When an interrupt occurs the interrupt routine must determine the cause receiver data register full transmitter data register empty receiver error or DCDO pin high channel 0 only None of these interrupts i
150. ry Map of 1M Address Space Figure C 2 shows the memory map within the 64K virtual space 64K XMEM XMEM UNITIALIZED UNITIALIZED DATA DATA STACK RAM STACK RAM UNUSED UNUSED USER CODE USER CODE ROM LIBRARY ROM LIBRARY 0 RAM Based ROM Based Figure C 2 Memory Map of 64K Virtual Space The various registers in the input output I O space can be accessed in Dynamic C by the symbolic names listed below These names are treated as unsigned integer constants The Dynamic C library functions inport and outport access the I O registers directly data value inport CNTLAO outport CNTLAO data value 134 Memory I O Map and Interrupt Vectors PK2600 Execution Timing The times reported in Table C 1 were measured using Dynamic C and they reflect the use of Dynamic C libraries The time required to fetch the arguments from memory but not to store the result is included in the timings The times are for a 9 216 MHz clock with 0 wait states Table C 1 CM7000 Execution Times for Dynamic C Execution Time us Operation per byte 0 73 3 4 4 4 18 90 85 113 320 28 97 415 849 2503 3049 Integer assignment i j Integer add j k Integer multiply j k Integer divide j k Floating add p q typical Floating multiply p q Floating divide p q Long add 1 m Long multiply 1 m Long divi
151. s 2 7 years To maximize the battery life the PK2600 should be stored at room tempera ture in the factory packaging until field installation Take care that the PK2600 is not exposed to extreme temperature humidity and or contami nants such as dust and chemicals To ensure maximum battery shelf life follow proper storage procedures Replacement batteries should be kept sealed in the factory packaging at room temperature until installation Protection against environmental extremes will help maximize battery life Replacing Soldered Lithium Battery Use the following steps to replace the battery 1 Locate the three pins on the bottom side of the printed circuit board that secure the battery to the board 2 Carefully de solder the pins and remove the battery Use a solder sucker to clean up the holes 3 Install the new battery and solder it to the board Use only a Panasonic BR2325 1HG or its equivalent for the controller board and a Renata CR2325RH or its equivalent for the display board 190 Battery PK2600 Battery Cautions Caution English There is a danger of explosion if the battery is incorrectly replaced Replace only with the same or equivalent type recommended by the manufacturer Dispose of used batteries according to the manufactur er s instructions Warnung German Explosionsgefahr durch falsches Einsetzen oder Behandein der Batterie Nur durch gleichen Typ oder vom Hersteller empfohlenen Ersatztyp
152. s edge trig gered Another interrupt will occur immediately if interrupts are re enabled without disabling the condition causing the interrupt The signal DCDO is grounded on the display board Table 3 3 lists the interrupt vectors Table 5 1 Serial Port Interrupt Vectors Address Name Description SERO_VEC Z180 Serial Port 0 higher priority SER1_VEC 7180 Serial Port 1 PK2600 Subsystems 81 Use of the Serial Ports If you plan to use the serial ports extensively or if you intend to use syn chronous communications Z World recommends that you obtain copies of the following Zilog technical manuals available from Zilog Inc in Camp bell California Z180 MPU User s Manual Z180 SIO Microprocessor Family User s Manual Each serial port appears to the CPU as a set of registers Each port can be accessed directly with the inport and outport library functions using the symbolic constants shown in Table 5 2 Table 5 2 2180 Serial Port Registers Address Name Description 00 CNTLAO Control Register A Serial Channel 0 01 CNTLAI Control Register A Serial Channel 1 02 CNTLBO Control Register B Serial Channel 0 03 CNTLB1 Control Register B Serial Channel 1 04 STATO Status Register Serial Channel 0 05 STATI Status Register Serial Channel 1 06 TDRO Transmit Data Register Serial Channel 0 07 TDRI Transmit Data Register Serial Channel 1 08 RDRO Receive Data Register Serial C
153. s with the PK2600 The following major sections are included Supplied Software Digital 0 Analog Inputs Serial Channels Display Board Functions Additional Software PK2600 Software Development 89 Supplied Software Software drivers for controlling the PK2600 s inputs outputs and serial ports are provided with Dynamic C In order to use these drivers it is necessary to include the appropriate Dynamic C libraries These libraries are listed in Table 6 1 Table 6 1 PK2600 Software Libraries Library Description General Libraries AASC LIB All serial communication applications DRIVERS LIB General drivers SYS LIB General drivers Controller Board Libraries AASCURT2 LIB XP8700 applications only EZIOBL17 LIB All controller board applications EZIOPBDV LIB All expansion board applications EZIOPLC2 LIB All expansion board applications Display Board Libraries EZIOOP71 LIB All OP7100 applications GLCD 8 LCD applications KP_OP71 LIB Touchscreen read applications LOVGA LIB Landscape image VGA drivers 1 Portrait image VGA drivers Your application program can use these libraries by including them in your program To include these libraries use the use directive as shown below duse drivers lib Since the controller and the display boards are programmed separately remember to use the corresponding libraries from Table 6 1 depending on which board is being programmed
154. slightly higher than its nominal value the actual input to the A D converter would be greater than 2 5 V A loss of accuracy then results because the A D converter input would reach its maximum input value before the true signal input reaches the minimum expected input level as shown in Figure 4 15 PK2600 Hardware Configurations 55 Out of range PASA i A D converter s input voltage limit Op amp output voltage deviation arising from resistor variations Op Amp Output A D IC Input V Out of range 10 Analog Input V Figure 4 15 Input Out of Range A deviation from nominal values in the bias network could skew the A D converter s input voltage away from the theoretically computed value For example a small positive or negative deviation of the bias voltage arising from variances in the resistive divider would offset the A D converter s input voltage This offset would be positive or negative tracking the deviation s sign and would be equal to the bias deviation multiplied by the amplifier s gain plus one Both of these effects could occur in the same circuit 6 Pick proper tolerance Use care when compensating for any discrepancies discovered For example if you use standard 5 resistors the values are spaced approxi mately 10 apart If your gain is too high by just a small amount then going to the next smallest standard 5 value could result in a drop
155. ster frequency response is needed it is possible to replace with a smaller value For example ifthe digital input is being driven by 8 5 V DC CMOS compatible driver can be replaced with a zero ohm 0805 resistor Replacing R with a zero ohm resistor will adversely affect the noise immunity of the PK2600 s digital inputs 130 Specifications PK2600 High Voltage Drivers Table B 3 lists the high voltage driver characteristics when sinking drivers or sourcing drivers are used Table B 3 High Voltage Driver Characteristics Sourcing Driver 2985 8 75 mA 60 C 125 mA 50 C 3 V to 30 V DC 2 2 W 1 6V 18 mW C 55 C W Yes 1 38 Sinking Driver 2803 8 75 mA 60 C 125 mA 50 C 2 V to 48 V DC 2 2 W 1 38 1 6V 18 mW C 55 C W Yes Characteristic Number of Channels Max Current per Channel all channels ON Voltage Source Range Package Power Dissipation Max Current all channels ON Max Collector Emitter Voltage VCE Derating Output Flyback Diode K Max Diode Drop Voltage K For additional information on maximum operating conditions for the PK2600 high voltage drivers call Z World Technical Support at 530 757 3737 Sinking Driver The sinking driver IC can handle a maximum of 1 38 A 500 mA for any channel or 75 mA per channel on average if all channels
156. t te ies e dnte hte 80 setl2adr 168 setl 6adr 168 set24adr 170 set4adr 169 set8adr uio 171 shadow registers 166 16 23 baud rate 174 dimensions 175 cate vecors 174 sinking drivers sssse 45 specifications 131 0 18 0 backlight 0 0 102 buzzer on off 102 contrast control 102 102 109 libraries 164 read write flash EPROM 108 109 real time clock 108 touchscreen 106 source C term lS tutus 124 source speed select 86 sourcing drivers 45 specifications 131 202 Index write4data 170 write8data 171 WriteFlash 108 writing data on the PLCBus 164 170 X XPS8I00 cere 162 XP8200 sese 162 162 XP8400 sese 162 XPRS OO eee 162 8600 sese 162 XP8700 162 163 167 8800 162 167 XP8900 162 Z Z180 internal I O registers
157. te automatically to match the communication rate set on the host PC using Dynamic C 9600 bps 19 200 bps 28 800 bps or 57 600 bps To begin use the default communication rate of 19 200 bps Make sure that the PC serial port used to connect the serial cable COMI or COM2 is the one selected in the Dynamic C OPTIONS menu Select the 1 stop bit protocol Depending on whether the SIB2 is connected to the CONTROLLER or to the DISPLAY header select PK26CONT C or PK26DISP C and compile and run the program by pressing F9 or by selecting Run from the Run menu PK2600 Graphics Programming 111 Blank 112 Graphics Programming PK2600 CHAPTER f GRAPHICS PROGRAMMING Chapter 5 provides helpful guidelines for drawing graphics on the PK2600 PK2600 Graphics Programming 113 Initialization The PK2600 unlike most other Z World controllers uses the maximum I O and memory wait states when main gets control The wait states can be reduced to improve performance The following statement sets up the proper wait states for the standard using a 90 ns flash memory PK2600 display board outport DCNTL inport DCNTL amp 0 0x60 The graphic LCD can be set up by a simple function call to glInit This function initializes and starts the LCD controller before supplying voltage to the LCD screen The backlight is controlled by op71BackLight int onOff Pass zero to turn off the backlight default or a non zero value to tur
158. ted by kpScanState no further key activities will be detected by further calls to kpScanState unless kpDefGetKey is called PK2600 Graphics Programming 117 Font and Bitmap Conversion Customers are encouraged to design their own fonts and bitmaps These restrictions must be followed Save bitmaps as Windows bitmaps bmp not OS 2 bitmaps The bitmap can only have two colors Color 0 is the background and color 1 is the foreground This is the reverse of most bitmap editors Fonts must be bitmapped not true type and must be of fixed pitch Save font files as nt version 3 The PK2600 uses a vertical stripe display logic format The conversion utility programs ntstrip exe landscape image and fntevtr exe portrait image convert the fnt and bmp file format to the Z World vertical stripe format Follow these instructions to use these utilities 1 Create the nt or bmp file that conforms to the restrictions listed above 2 Start fntstrip or fntcvtr Specify the file to convert select the file from the menu List files of type and choose either fnt or bmp Entering fnt or bmp in the File name window will not TI work The file must be selected after clicking on Font files or Bitmap files in the List files of type window 4 Click the OK button or double click on the file to convert At this point the software asks the destination of the conversion Specify a file t
159. ter 4 Hardware Configurations 35 PK2600 Assembly en det ROI 36 Accessing the Controller Board 38 Accessing the Display Board serere 40 PK2600 Table of Contents iii 0 Digital Inputs and Outputs esse External 22 Digital Inputs ete eaten Operating Modes and Configuration Digital Outputs Operating Modes and Configuration High Voltage Drivers ess TTL CMOS Outputs Pulse Width Modulation PWM Configuration Analog Operating Modes and Configuration Low Pass Filter 20 Excitation Resistors eee Using the Unconditioned Converter Channels Internal Test Voltages sess Power Down 2 External Connections 2 Serial Channels 0 Operating Modes and Configuration Configuring a Multidrop Network RS 485 Termination sse External Connections eene Liquid Crystal Display 1 0222 sss Contrast Adjustments esses Background essere Chapter 5 Subsystems Controller Board Subsystems Microprocessor Core Module Display Board Subsystems
160. th a gain of 0 25 using a 1 feedback resistor of 2490 Q the 3 dB corner frequency is 6392 Hz PK2600 Hardware Configurations 59 Excitation Resistors Some transducers require an excitation voltage For example a thermistor serving as one leg of a voltage divider having a fixed resistor in the other leg measures temperature The voltage at the divider s junction will vary with temperature 10 kQ excitation resistors are installed on the inputs of the eight conditioned analog channels The excitation resistors are tied to the 5 V analog supply Using the Unconditioned Converter Channels The eight conditioned channels use the first eight channels AINO AIN7 of the A D converter chip Two additional channels are also available You can access these channels with software by inserting your desired channel number in the library functions These signals are available on headers H8 and H11 For optimum results drive these channels with low output impedance voltage sources less than 50 Op amps are ideal for this purpose High output impedance sources on the other hand are susceptible to coupled noise In addition only a low impedance source can quickly charge the sampling capacitors within the A D converter When designing the signal sources to drive the extra channels be sure to consider whether the amplifiers you choose can handle the capacitance of the cable that connects to the analog input connectors Internal Test Volt
161. the jumper settings to enable disable the termination resistors External Connections Each serial channel has its own individual header for external connections Both Channel and Channel B RS 232 and RS 485 signal lines are brought out to the serial channel s 10 pin header Only one set of signals RS 232 or RS 485 is active The three wire RS 232 interface provides the following signals RX TX GND The five wire RS 232 interface provides the following signals RX TX RIS CIS GND The two wire RS 485 interface provides the following signals e RS485 e RS485 PK2600 Hardware Configurations 65 Enable termination PK2600 resistors on the SERIAL PORT2 3 gt master controller and end controller only Ground recommended PK2600 SERIAL PORT2 3 PK2600 SERIAL PORT2 3 PK2600 SERIAL PORT2 3 Figure 4 18 Multidrop Network The RS 485 drivers supplied on the PK2600 controller board support up to 32 nodes The transmission bandwidth may be reduced as additional nodes over the benchmark quantity of 32 are added to the network Contact Z World Technical Support for assistance with large scale network design 66 Hardware Configurations PK2600 Table 4 11 Termination Resistor Jumper Settings Jumper Settings Channel Termination Resistors Termination Resistors Enabled Disabled Channel 0 No RS 485 available Cha
162. the error flags OVRN FE PE Reading this bit obtains the value of the MPB bit for the last read operation when the multiprocessor mode is enabled IRTSO Request to Send Channel 0 Store a 1 in this bit to set the RTSO line from the Z180 high This bit is essentially a 1 bit output port without other side effects 1 CKA Disable This bit controls the function assigned to the multiplexed pin CKA1 TENDO 1 TENDO a DMA function and 0 CKA1 external clock I O for Channel 1 serial port TE Transmitter Enable This bit controls the transmitter 1 transmitter enabled 0 transmitter disabled When this bit 1s cleared the processor aborts the operation in progress but does not disturb TDR or TDRE PK2600 Subsystems 85 RE Receiver Enable This bit controls the receiver 1 enabled 0 disabled When this bit is cleared the processor aborts the operation in progress but does not disturb RDRF or the error flags MPE Multiprocessor Enable This bit 1 enabled 0 disabled controls multiprocessor communica tion mode which uses an extra bit for selective communication when a number of processors share a common serial bus This bit has effect only when MP in Control Register B is set to 1 When this bit is 1 only bytes with the MP bit on will be detected Others are ignored If this bit is 0 all bytes received are processed Ignored bytes do not affect the error flags or RDRF ASCI
163. tioned channels 52 54 data 10 98 nip nS 59 drivers 2 98 excitation resistors 60 gain bias resistors 52 53 component tolerance 56 59 deviation sss 55 gain resistors 54 initializing esse 98 input range 52 55 low pass filter 59 Op amps 53 54 performance 57 reading sees 98 sample program 99 setting 53 54 SOMWALE oce res 98 unconditioned 52 60 ASCI 85 86 88 Control Register 85 Control Register B 86 status registers 83 asynchronous channel operation 85 attention line sss 163 Index 193 Symbols _ 1 VEC eee 142 163 ICS1 CS6 140 ICTS unnustan 81 83 87 ICTSIPS 87 7 80 84 line to ground 8 IDREQO ne 186 INT1 configuration 68 142 IRDX 163 RESET enta nanl 79 90 0 85 RTS l eann 80 163 ITENDO 85 INDO 79 IWRX tecta 163 assignment Dc 12
164. to 256K controller Two 256K display Simulated in flash EPROM e 1 full duplex RS 232 2 configurable as full duplex RS 232 or as RS 485 Up to 57 600 bps Yes 32K standard supports up to 64K display Yes controller and display e Panasonic BR2325 1HG 3 V DC lithium ion rated life 190 mA h controller Renata CR2325RH 3 V DC lithium ion rated life 165 mA h display Specifications 127 Parameter SRAM VRAM Flash EPROM EEPROM Serial Ports Serial Rate Watchdog Time Date Clock Backup Battery PK2600 2000 61 4 800 122 91 5 400 137 3 583 PK2600 Mechanical Dimensions Figure B 1 shows the mechanical dimensions for the PK2600 LCD aperture is 122 x 92 mm Pixel matrix 320 x 240 is 115 17 x 86 37 mm 4 40 8 studs 8x 0 125R typ 4 3 18 4 763 87 121 6 800 99 203 4 152 00000000000000 00000000000000 nnnnnnnnnnnnnnn 0000000000000 0000000000000 6 930 176 0125 typ 48 SS ae f 0 320 typl 8 1 1 619 typ 41 2 120 typ 54 Display Controller Figure 8 1 PK2600 Dimensions PK2600 128 Specifications Protected Digital Inputs Table B
165. turns the voltage read as a real number in a floating point representation for e3oAddr values 0 9 if the read is successful For eioAddr values 16 25 if the read is successful the function returns a floating point representation of an unsigned integer value 0 4095 for the 12 bit raw data value read from the A D converter int eioBrdAdcMode int datalen int dataformat int polarformat Sets the analog to digital conversion data length data format and polarity format other than default Call this function after eioBrdInit and before eioBrdAI RETURN VALUE returns 1 if successful 1 if an invalid parameter is passed to the function 98 Software Development PK2600 Call e3oBrdAdcMode after calling e3oBrdInit and before calling eioBrdAI Table 6 4 shows the parameters datalen dataformat and polarformat Table 6 4 Analog to Digital Converter Modes Parameter Value datalen 0 12 bit data length 1 8 bit data length 2 12 bit data length 3 16 bit data length dataformat 0 most significant bit first least significant bit first polarformat 0 unipolar 1 bipolar e int eioBrdACalib int eioAddr unsigned dl unsigned d2 float v1 float v2 Calculates the calibration constants for an analog input channel using two known voltages and two corresponding raw data readings Stores the calibration constants in EEPROM PARAMETERS eioAddr is the analog input channel 41 is t
166. tware development See Chapter 2 Getting Started and Appendix D Serial Interface Board 2 for more information RS 485 Communication The PK2600 controller board can be configured to provide up to three channels of RS 485 communications RS 485 is an asynchronous multidrop half duplex standard that provides multidrop networking with maximum cable lengths up to 4000 feet Dynamic C provides library functions for master slave two wire half duplex RS 485 9th bit binary communications This RS 485 hardware standard supports up to 32 controllers on one network The supplied software supports 1 master unit plus up to 255 slave units which may consist of any combination of Z World controllers that support the RS 485 protocol 100 Software Development PK2600 Software Serial channel 0 is supported by Dynamic C library functions Serial channels A and B are driven by U13 a Zilog Serial Communication Controller on the controller board Serial channels A and B have addi tional capabilities beyond those supported by the Dynamic C libraries If you would like to use these additional capabilities refer to the Zilog Serial Communication Controllers Manual Comprehensive information on the serial channel software and RY programming can be found in the Dynamic C Function Reference manual and the Dynamic C Application Frame works manual The following functions are used with the RS 485 serial channels int sccSw485 unsigned ch
167. uei pP te di eit MOERS 115 Filla Poly 115 Draw a Bitmap 115 Printing Text sic isset anit HER RSEN CHI ERREUR 116 Keypad Programming essere 117 Initialization 117 Scanning the Keypad essere 117 Reading Keypad Activities esee 117 Font and Bitmap Conversion 118 Using the Font Bitmap In Your Program 119 Appendix A Troubleshooting 121 Out of the BOX etie c ede e e e 122 Dynamic C Will Not Start 123 PK2600 Repeatedly Resets essere 123 123 Common Programming Errors eese 124 vi Table of Contents PK2600 133 134 Appendix B Specifications Electronic and Mechanical PK2600 Mechanical Dimensions eee Protected Digital Inputs sess Frequency Response for the Protected Inputs High Voltage Drivers iii cathe ees eate EHE Sinking Drivers Sourcing Driver eee eth Appendix C Memory I O Map and Interrupt Vectors Memory ETE Input Output Select 7180 Internal Input Output Registers Addresses 00 3F Real Time Clock Registers 0x4180 0x418F Other Registers ee ete EN E Controller Boarder aeu Display 30 RD reg
168. urations PK2600 Liquid Crystal Display LCD The contrast adjustments and the background of the LCD can be config ured using jumpers on selected headers on the display board Contrast Adjustments Figure 4 20 shows the jumper settings for the contrast control options Software Manual Contrast Contrast Adjustment Adjustment LS1 3 2 2 Battery 1 i JP2 021 z 022 OP7100 OP7110 OP7130 OP7120 Figure 4 20 Display Board Contrast Control Jumper Configurations Background The LCD on the PK2600 comes factory configured to display blue charac ters on a white positive background The jumpers on header JP1 on the display board may be rearranged as shown in Figure 4 21 to display white characters on a blue negative background Positive Background white with blue graphics U4 0000 2 4 6 8 10 2 je Ilo El o 135 7911 JP1 NOOOOO Negative Background blue with white graphics Figure 4 21 LCD Background Jumper Settings PK2600 Hardware Configurations 69 Blank 70 Hardware Configurations PK2600 CHAPTER 5 SUBSYSTEMS PK2600 Subsystems 71 Controller Board Subsystems The PK2600 controller board consists of several subsystems including a microprocessor core module serial communications channels digital I O analog inputs and PLCBus expansion port Figure 5 1 illustrates these subsystems
169. uring development The SIB2 is not part of the standard Developer s Kit Both programming methods are described below 51 2 ordering information call your Z World Sales Representative at 530 757 3737 Connecting the PK2600 to a PC using the serial port 1 Make sure that Dynamic C is installed on your PC as described in the Dynamic C Technical Reference manual Unplug the power supply 2 Connect the DE to DE9 programming cable from SERIAL PORT 1 on the PK2600 to the appropriate COM port of your computer as shown in Figure 2 4 0 A CAUTION High Voltage Transformer Only qualified v persons may open this case ANALOG INPUTS SERIAL PORT 1 B PROG RUN DC CONTROLLER 5 a z 9 DISPLAY 2 5 DIGITAL GROUP 1 SERIAL 3 5999 86066 e a Ji E a OWER gm 2900 SPAFFORD ST DAVIS CA 95616 IN 0 1 530 757 3737 WWW ZWORLD COM Programming Cable To PC Figure 2 4 PK2600 Serial Port 1 Programming Connections Use only the transformer and programming cable supplied by Z World 22 Getting Started PK2600 3 Set the C Run Program switch on the back of the 2600 to PROG 4 Plug the power supply transformer into a wall socket Only the controller may be programmed at this time through SERIAL PORT 1 The SIB2 is required to program the display
170. vices Table E 4 Allocation of Registers Al A2 A3 Meaning 000 000 digital output registers 64 registers 64 x 8 512 registers 000j 001 analog output modules 64 registers digital input registers 128 registers 128 x 4 512 input bits 000 10xj xxxj analog input modules 128 registers 000j 11xj xxxj 128 spare registers customer 001j 512 spare registers Z World 000 01 xxxj j controlled by board jumper X controlled by PAL 166 PLCBus PK2600 Digital output devices such as relay drivers should be addressed with three 4 bit addresses followed by a 4 bit data write to the control register The control registers are configured as follows bit 3 bit 2 bit 1 bit 0 A2 Al AO D The three address lines determine which output bit is to be written The output is set as either 1 or 0 according to D If the device exists on the bus reading the register drives bit 0 low Otherwise bit 0 18 8 1 For digital input each register BUSRDO returns four bits The read register BUSRDI drives bit 0 low if the device exists on the bus 8 Bit Devices Z World s XP8700 and XP8800 expansion boards use 8 bit addressing Refer to the XP8700 and XP8800 manual Expansion Bus Software The expansion bus provides a convenient way to interface Z World s controllers with expansion boards or other specially designed boards The expansion bus may be accessed by
171. voltage divider comprising a bias resistor and a fixed 10 resistor derive the bias voltage from VREF Note that VREF is not necessarily the same as REF REF is the positive reference voltage the A D chip uses VREF is 2 5 V and R is 10 000 Q R bias bias 4 4 2 5 V Vias Continuing the example for an input voltage range that necessitates a gain 010 25 and for which Ax is 5 V is then 1 0 Therefore is 6667 Q in absolute mode Now suppose that the input range is 0 V to 10 V instead of 5 V to 5 V snow 10 Vand V becomes 2 0 V 1s then 40 kQ 4 Choose resistor values bias The calculated values of course will not always be available as standard resistor values In these cases use the nearest standard resistor value For example rather than 6667 Q use 6650 Q if you are using 1 resistors or use 6800 if you are using 5 resistors 5 Bracket input range To be sure of accurately measuring signals at the extremes of an input range you must be aware of the interaction between the 10 kQ fixed resistors and the resistors you install In the ideal case if you were to measure a signal at the minimum input level the A D converter s input would be at the maximum expected value of 2 5 V However in the real world resistor values vary within their rated tolerance bands Thus if the fixed input resistor is lower than its nominal value and the installed resistor is
172. xploded View of PK2600 Boards Top View Case Removed PK2600 Hardware Configurations 37 Accessing the Controller Board 1 Remove the two 3 8 screws holding the power program module to the I O conversion module These screws are labeled 1 in Figure 4 3 CM7200 Core Module o 15 Conversion 2 1 Module Power Program Module Figure 4 3 Attachment of Power Program Module and I O Conversion Module 2 The bottom side of the CONTROLLER SIB port on the power program module 14 15 plugs into header JP1 of the CM7200 core module see Figure 4 4 The bottom side of the DISPLAY SIB port on the power program module J3 J6 5 90 U1 plugs into header 119 on the 0 conversion module J19 is 10 cated just above the core mod ule cutout Carefully unplug JP4 J5 and 13 16 from JP1 core module and J19 I O conversion module 3 A wire assembly connects the H1 power header J2 on the power program module to the power header J1 on the controller board Move the power pro gram module to the side with out disconnecting these cables
173. y enclose classes of terms alblc A vertical bar indicates that a choice should be made from among the items listed Pin Number 1 A black square indicates pin 1 of all headers J1 Measurements All diagram and graphic measurements are in inches followed by millime ters enclosed in parenthesis PK2600 About This Manual xi Blank xii About This Manual PK2600 CHAPTER 1 OVERVIEW Chapter provides a comprehensive overview and description of the PK2600 The following sections are included Features Flexibility and Customization Development and Evaluation Tools PK2600 Overview 13 The PK2600 Integrated Control System is designed as an off the shelf system that integrates an established Z World controller with a 4VGA LCD The PK2600 is ideal for systems that require an integrated graphic interface The feature rich controller has modular digital and analog I O that allows easy custom modification The display has a large storage area for bitmaps display lists and screens Both the controller and the display are programmed using Dynamic C PLCBus DIGITAL GROUP 1 DIGITAL ANALOG INPUTS POWER PK2600 Z World s version of the C programming language Figure 1 1 shows a block diagram of the PK2600 SERIAL SERIAL SERIAL PORT3 PORT2 PORT 1 Dynamic C programming RS 232 RS 232 RS 232 RS 485 RS 485 SIB2 PLCBus Controller Board Digital a SIB e
174. ynamic C OPTIONS menu Select the 1 stop bit protocol 5 See Appendix A Troubleshooting if an error message such as Target Not Responding or Communication Error appears Once the necessary changes have been made to establish communication between the host and the display board use the Dynamic C shortcut lt Ctrl Y gt to reset the controller and initiate communication At this point the LCD should be blank and the backlight should be off Once communication is established load the sample program DEFDEMOL C in the Dynamic C SAMPLES QVGA subdirectory Compile and run the program by pressing F9 or by selecting Run from the Run menu The PK2600 should now alternately display the large font 17x 35h and the small font 6w 8h The fonts should scroll across the display Compiling and running this sample program will overwrite the Z World demonstration program shown in Figure 2 3 24 Getting Started PK2600 3 HARDWARE FEATURES Chapter 3 describes the PK2600 hardware The following sections are included Operating Modes Liquid Crystal Display Keypad Interface Digital Inputs Outputs Serial Channels PLCBus PK2600 Hardware Features 25 Operating Modes The PK2600 has two mutually exclusive operating modes Run Mode and Program Mode Each mode is explained in detail below Program Mode In Program mode the PK2600 runs under the control of the PC that is running Dynamic C
175. yte BUSADR cc 1 1 0 Third address nibble or byte BUSWR CE 1 1 1 Write data Writing or reading one of these registers takes care of all the bus details Functions are available in Z World s software libraries to read from or write to expansion bus devices To communicate with a device on the expansion bus first select a register associated with the device Then read or write from to the register The register is selected by placing its address on the bus Each device recognizes its own address and latches itself internally A typical device has three internal latches corresponding to the three address bytes The first is latched when a matching BUSADRO is detected The second is latched when the first is latched and a matching BUSADRI is detected The third is latched if the first two are latched and a matching BUSADR2 is detected If 4 bit addressing is used then there are three 4 bit address nibbles giving 12 bit addresses In addition a special register address is reserved for address expansion This address if ever used would provide an additional four bits of addressing when using the 4 bit convention If eight data lines are used then the addressing possibilities of the bus become much greater more than 256 million addresses according to the conventions established for the bus 164 PLCBus PK2600 Place an address on the bus by writing bytes to BUSADRO BUSADRI and BUSADR2 in succession Since 4 bit a

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