ODMB user`s manual
Contents
1. 23th January 2014 O DMB user s manual Optical DAQ MotherBoard for the ME1 1 stations of the CMS muon endcap detector Firmware tag V02 04 ODMB V2 and ODMB V3 compatible Manuel Franco Sevilla Frank Golf Guido Magazzu Tom Danielson Adam Dishaw Jack Bradmiiller Feld UC Santa Barbara Table of Contents Front panel General Firmware version VME access through the board discrete emergency logic Jumpers and test points Device 1 DCFEB JTAG Example Read DCFEB UserCode Device 2 ODMB JTAG Example Read ODMB UserCode Device 3 ODMB DCFEB control Bit specification of ODMB_CTRL and DCFEB_CTRL Information accessible via command R 3YZC Device 4 Configuration registers Notes Device 5 Test FIFOs Notes Device 6 BPI Interface PROM Device 7 ODMB monitoring Translation into temperatures and voltages Device 8 Low voltage monitoring Device 9 System tests Firmware block diagram ODMB user s manual OO ANN ODO AM RAO N ok O O m ND _ ke a RR OQ ront panel 5 0V 1 0V 1 2V LVMB FPGA FPGA 1 8V 2 5Vv 3 3V FPGA FPGA FPGA 0 amp 3 3V 3 3V 3 3V OTX ORX ORXI 5 0V 3 3V 3 3V VME VME PPIB Firmware tag V02 04 EDA 02415 ODMB user s manual Push buttons HRST Reloads firmware in PROM onto FPGA SRST Resets registers FIFOs in FW LEDs 1 12 blink at different speeds for 3s PB1 Sends L1A and L1A M2. 56 se DI 0 Ro C CORN ro Jr eryserte ru2 LL SH16 A sT16 MO Ti MI R121 Sme y2 1634 cis T pi R123 Ten 1C35 a mm Bam gt Firmware tag V02 04 4 DMB user s manual Device 1 DOFEB JIAG Y refers to the number of bits to be shifted Instruction Description Shift Data no TMS header no TMS tailer W 1Y04 Shift Data with TMS header only W 1Y08 Shift Data with TMS tailer only W 1YOC Shift Data with TMS header amp TMS tailer R 1014 Read TDO register W 1018 Resets JTAG protocol to IDLE state data sent with this command is disregarded Shift Instruction register w 1020 Select DCFEB one bit per DCFEB R 1024 Read which DCFEB is selected Example Read DCFEB UserCode DCFEB registers are set and read via JTAG The following procedure reads the 32 bit USERID of DCFEB 3 W 1020 4 Select DCFEB 3 one bit per DCFEB W 191c 3C8 Set instruction register to 3C8 read UserCode W 1F04 0 Shift 16 lower bits R 1014 0 Read last 16 shifted bits DBDB W 1F08 0 Shift 16 upper bits R 1014 0 Read last 16 shifted bits XYZK Firmware tag V02 04 5 ODMB user s manual Device 2 ODMB JIAG Y refers to the number of bits to be shifted Instruction Description TT E R 2014 Read TDO register W 2018 Resets JTAG protocol to IDLE state data sent with this command is disregarded Shift Instruction register W 2020 Change polarity of V6 JTAG SEL Example Read
3. 61 67 Number of data packets received with good CRC for given DCFEB YZ 71 77 Number of LCTs for given DCFEB YZ 78 Number of available OTMB packets YZ 79 Number of available ALCT packets YZ BA Read last CCB_CMD 5 0 EVTRST BXRST strobed YZ 5B Read last CCB_DATA 7 0 strobed YZ 5C Read toggled CCB_CAL 2 0 CCB_BXO CCB_BXRST CCB_L1ARST CCB_L1A CCB_CLKEN CCB_EVTRST CCB_CMD_STROBE CCB_DATA_STROBE YZ 5D Read toggled CCB RSV signals Firmware tag V02 04 8 ODMB user s manual Device 4 Configuration registers Instruction Description W R 4000 LCT_L1A_DLY 5 0 gt Set to LCT L1A gap 100 W R 4004 OTMB_DLY 5 0 gt Set to L1A OTMBDAV gap read with R 338C W R 400C ALCT_DLY 5 0 gt Set to L1A ALCTDAV gap read with R 3390 W R 4010 INJ_DLY 4 0 Delay 12 5 INJ_DLY ns W R 4014 EXT_DLY 4 0 Delay 12 5 EXT_DLY ns W R 4018 CALLCT_DLY 3 0 Delay 25 CALLCT_DLY ns W R 401C KILL 9 1 ALCT TMB 7 DCFEBs W R 4020 CRATEID 6 0 W R 4028 Number of words generated by dummy DCFEBs OTMB and ALCT Notes 1 If unique ID not set request UCSB to write it Firmware tag V02 04 9 DMB user s manual Device 5 Test FIFOs Z refers to FIFO 1 gt PC TX 2 gt PC RX 3 gt DDU TX 4 gt DDU RX 5 gt OTMB 6 gt ALCT Instruction Description R 5000 Read one word of selected DCFEB FIFO R 500C Read numbers of words stored in selected DCFEB FIFO
4. ATCH to all DCFEBs Turns on LED 12 LEDs set in firmware 1 4 Hz signal from clock for data gt DDU 3 2 Hz signal from clock for data gt PC 5 1 Hz signal from internal ODMB clock 7 Data taking ON normal OFF pedestal 9 Triggers ON external OFF internal 11 Data ON real OFF simulated 2 Bit 0 of LIA COUNTER 4 Bit 1 of LIA COUNTER 6 Bit 2 of LIA COUNTER 8 Bit 3 of LIA COUNTER 10 Bit 4 of LIA COUNTER 12 Briefly ON when a VME command is received Also ON when PB1 is pressed LEDs set in hardware DDU Signal Detected on DDU RX PC Signal Detected on PC RX ETD DTACK enable for discrete logic active low EJD JTAG enable for discrete logic active low DON DONE signal from FPGA ON when pro grammed INIT INIT_B signal from FPGA active low LOCK QPLL is locked ERR Error with QPLL Bottom 12 Voltage monitoring Genera Firmware version For a given firmware tag VXY ZK Usercode is XYZKdbdb Firmware version read via R 4200 is XYZK VME access through the board discrete emergency logic The FPGA may be accessed via JTAG through the discrete logic as follows The VME address is OxFFFC The bit O of the data sent is TMS The bit 1 of the data sent is TDI ODMB user s manual For example to read the Usercode starting from JTAG idle five TMS 1 amp one TMS 0 the commands are FFFC FFFC FFFC FFFC FFFC FFFC FFFC FFFC FFFC FFFC FFFC EFEC FFFC
5. FFFC 23333 FFFC FFFC FFFC FFFC EFEC FFFC DI VW DN DN O on OC OO CE i oe ao EG RR 5 To Select To Select IR Scan To Capture IR To Shift I Shif Shif Shif Shif Shif Shif Shif Shif Shif Shif ting ting ting ting ting ting ting ting ting ting I I I I I I I I I I DR Scan R Read UserCode IR 3C8 R R R R R R R R R R and to To Update IR To Ri un Tes To Select To Capture DR Shifting D Shifting D t Idle DR Scan R Exitl IR R Read bit 0 of UserCode Since the Usercode register is 32 bits the last two commands should be repeated 31 more times Firmware tag V02 04 DMB user s manual Jumpers and test points Place the jumpers marked in red in the diagram The signals sent to the test points marked in blue are MATCH _MATCH 2 _MATCH 8 _MATCH 4 _MATCH 5 _MATCH 6 L1A_MATCH 7 DDU_DATA_VALID ALCTDAV TP30 Defined by TP SEL TP31 2 R34 G c4 OPLL FOS1 st7 T g me opt Foso ETL 0 0 woos EE 25 c5 OPLL FOS3 NI OPLL FOS2 sti le CLK WP FEE zz ce 2 H11 BET 5 gt gt le t13 1C33 a Oo le OPLL ExT MEOE S L Ornan mm 1C28 R90 ao SS CI CI Corio Ba L R58 RI Rica R92 7 ao 2 XILINX cel R93 DL LR104 7632 me Sm VIRTEX 6 R95 1 r106 mg Cage XC6VLX130T a EG LL FFG11
6. ODMB UserCode Read FPGA UserCode W 291c 3C8 Set instruction register to 3C8 read UserCode W 2F04 0 Shift 16 lower bits R 2014 0 Read last 16 shifted bits DBDB W 2F08 0 Shift 16 upper bits R 2014 0 Read last 16 shifted bits XYZK Firmware tag V02 04 6 ODMB user s manual Device 3 ODMB DCFEB control Instruction Description W R 3000 ODMB_CTRL register W R 3010 DCFEB_CTRL register W R 3020 TP_SEL register selects which signals are sent to TP27 TP28 TP41 TP42 W R 3100 LOOPBACK 0 gt no loopback 1 or 2 internal loopback W R 3110 DIFFCTRL TX voltage swing 0 gt minimum 100 mV F gt maximum 1100mV R 3120 Read DONE bits from DCFEBs 7 bits R 3124 Read if QPLL is locked Read ODMB_DATA corresponding to selection Z See below Bit specification of ODMB CTRL and DCFEB_CTRL ODMB CTRL 3 0 Selects CAL_TRGEN calibration mode ODMB CTRL 4 Selects CAL MODE calibration mode gt ODMB CTRLJ 5 Selects CAL TRGSEL calibration mode ODMB CTRL 7 Selects DCFEB data path O gt real data 1 gt dummy data gt ODMB CTRL 8 Resets FPGA registers FIFOs and LEDs 1 12 blink for 3s Bit is auto reset ODMB CTRL 9 Selects L1A and LCTs O gt from CCB 1 gt internally generated ODMB CTRL 10 Selects LVMB O gt real LVMB 1 gt dummy LVMB ODMB_CTRL 11 Kills L1A ODMB CTRL 12 Kills L1A_MATCH ODMB CTRL 13 O gt normal 1 gt pedestal L1A MA
7. TCHes sent to DCFEBs for each L1A ODMB CTRL 14 0 gt normal 1 gt pedestal OTMB data requested for each L1A needs spec OTMB FW gt DCFEB CTRL 0 Reprograms the DCFEBs Bit is auto reset DCFEB CTRL 1 Resynchronizes the L1IA COUNTER of ODMB and DCFEBs Bit is auto reset DCFEB CTRL 2 Sends INJPLS signal to DCFEBs Bit is auto reset DCFEB_CTRL 3 Sends EXTPLS signal to DCFEBs Bit is auto reset DCFEB CTRL 4 Sends test L1A and L1A_MATCH to all DCFEBs Bit is auto reset DCFEB CTRL 5 Sends LCT request to OTMB Bit is auto reset DCFEB CTRL 6 Sends external trigger request to OTMB Bit is auto reset DCFEB CTRL 7 Resets the optical transceivers Bit is auto reset Firmware tag V02 04 7 ODMB user s manual Information accessible via command R 3YZC gt YZ 3F Least significant 16 bits of LIA COUNTER YZ 21 29 Number of L1A_MATCHes for given DCFEB OTMB ALCT YZ 31 37 Gap in number of bunch crossings between the last LCT and L1A for given DCFEB YZ 38 Gap in number of bunch crossings between the last L1A and OTMBDAV YZ 39 Gap in number of bunch crossings between the last L1A and ALCTDAV YZ 41 49 Number of packets stored for given DCFEB TMB or ALCT YZ 4A Number of packets sent to the DDU YZ 4B Number of packets sent to the PC YZ 51 59 Number of packets shipped to DDU and PC for given DCFEB TMB or ALCT YZ
8. W R 5010 Select DCFEB FIFO W 5020 Reset DCFEB FIFOs 7 bits one per FIFO which are auto reset R 5200 Read one word of FIFO Read numbers of words stored in FIFO Notes 1 All these FIFOs can hold a maximum of 2 000 18 bit words 36 kb 2 The OTMB ALCT and 7 DCFEB FIFOs store the data as it arrives in parallel to the standard data path e They can hold a maximum of 3 OTMB 4 ALCT and 2 DCFEB data packets 3 The DDU TX FIFO stores DDU packets just before being transmitted e They include the DDU header 4 words starting with 9 4 starting with A ALCT data TMB data DCFEB data and trailer 4 words starting with F 4 starting with E 4 The PC TX FIFO stores DDU packets wrapped in ethernet frames just before being transmitted e They include the ethernet header 4 words and trailer 4 words e They need to be at least 32 words long 5 The DDU and PC RX FIFOs can be used for loopback tests Firmware tag V02 04 10 DMB user s manual Device 6 BPI Interface PROM Important Instruction 6000 takes 1 second during which Device 4 and 6 write commands are ignored Instruction Description W 6000 Write configuration registers to PROM W 6004 Set configuration registers to retrieved values from PROM W 6020 Reset BPI interface state machines W 6024 Disable parsing commands in command FIFO while filling FIFO with commands no data W 6028 Enable parsing commands in the command FIFO no data W 602C Write one word to comma
9. nd FIFO R 6030 Read one word from read back FIFO R 6034 Read number of words in read back FIFO R 6038 Read BPI Interface Status Register R 603C Read Timer 16 LSBs R 6040 Read Timer 16 MSBs Firmware tag V02 04 11 DMB user s manual Device 7 ODMB monitoring Reads output of the ADC inside the FPGA Instruction Description Translation into temperatures and voltages The output of the 7YZO commands is a 12 bit number that we call Ryz The measurement is R 503 975 e The FPGA temperature is Tppaa 273 15 C e The temperature of the thermistors THERM1 THERM2 is given by PI cr ses sa co 700 os as eee E Dis o fs pao fs ols 0 7 z Ryz STE Vyz Nom V where Vyz nom is the nominal voltage level for that register That is V10 Nom 3 3V V13 Nom 3 6V V11 Nom V17 Nom DV V14 Nom 2 5V and V46 Nom 1V e The voltage levels are Vyz Firmware tag V02 04 12 ODMB user s manual Device 8 Low voltage monitoring Instruction Description w 8000 Send control byte to ADC R 8004 Read ADC W 8010 Select DCFEBs ALCT to be powered on 8 bits ALCT 7 DCFEBs R 8018 Read which DCFEBs ALCT are powered on W 8020 Select ADC to be read 0 to 6 R 8024 Read which ADC is to be read Table 1 Control Byte Format PD1 MODE 0 Normal operation always on internal clock mode 0 Normal operation always on external clock INPUT RANGE RNG BIP mode S
10. tandby power down mode STBYPD clock mode unaffected O to 5V O to 10V 5V Full power down mode FULLPD clock mode unaffected 10V O 0 Firmware tag V02 04 13 ODMB user s manual Device 9 System tests Instruction Description EEE AEE EN De 820 check GOO sone PRES pate sano peer CS Firmware tag V02 04 14 ODMB user s manual Firmware block diagram The firmware can be downloaded from http github com odmb odmb ucsb v2 ODMB_UCSB_V2 Top of the design FPGA Control Data ODMB VME MBV LVDBMON Device 8 SYSTEM MON Device 7 BPI PORT Device 6 TESTFIFOS Device 5 VMECONFREGS Device 4 VMEMON Device 3 ODMBJTAG Device 2 CFEBJTAG Device 1 ODMB CTRL MBC CALIBTRG Calibration ccna Trigger conor contor onu packets COMMAND VME protocol Firmware tag V02 04 15
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