SMT310Q User Manual - Sundance Multiprocessor Technology Ltd.
Contents
1. USERDEF 1 Table 12 SDB Pin out 12 2 Comports 12 2 1 FMS Cabling The cables used with FMS connectors are not supplied with the SMT310Q You can order them separately from Sundance with part number SMT500 FMSxx where xx is the cable length in centimetres When fitting FMS cables make sure they have a twist one end must have the blue side facing out and the other must have the silver side facing out Important Note If using FMS cables between two SMT310Qs the reset headers must be connected to ensure that all comports reset at the same time See Reset and Config headers 4 This is not recommended as long FMS cables can introduce communication problems Version 2 1 Page 39 of 55 SMT310Q User Manual Pin N Signal Pin N Signal 1 GND 2 DATAO 3 DATA 4 DATA2 5 DATA3 6 DATA4 7 DATAS 8 DATA6 9 DATA7 10 ICREQ 11 ICACK 12 ICSTRB 13 ICRDY 14 GND Figure 13 FMS connector pin out 12 2 2 Buffered Comport Cabling Connecting between buffered comports requires a 1 to 1 cable the SMT502 Buffer is the recommended cable assembly and can be purchased separately Cable plugs 3M Scotchflex 10126 6000EL FES part 038740A Plug shells 3M Scotchflex 10326 A200 00 FES part 038760D Cable type 3M Scotchflex KUCKMPVVSB28 13PAIR FES part 038781E This cable has 13 individual pairs with an overall shield and an outer diameter of 7mm Cable length should be as short as possibl2. 19 4 4 Comport Directions Santander inner 19 5 Sundance Digital Bus GDPl een 20 6 JTAG GOmMEON GF eege EES 21 6 1 Using the SMT310Q External Internal JTAG with TI Tools 22 7 Global Local Bus Transfers DSP lt gt PCI 23 cht len DE AE SSL RE cia addin seach cans evs GR ca a cia SEE 23 7 1 1 Doorbell Interrupts Ae 24 1 2 DSPintEer pt Control seen sonne eine 24 7 3 DSP To Local Aperture 0 control and Accessing 25 TA DSP SIGS eege 26 Version 2 1 Page 4 of 55 SMT310Q User Manual Ire EUREN tent eek cutee 29 8 1 SMT310Q To PCI Interrupts EE 29 8 2 PCI To SMT310Q Interrupts nsnnesnneeennnnnnnenensnennrttnnrrrnrrnrrrrtrrrrnnnenrn rrene 30 9 9 Interrupt E 30 8 3 1 INTREG Register BAR1 Offset 4045 31 9 Memory lagen 32 9 1 PCI Bus leschen eieiei deed ee ee e 32 9 1 1 PCI Bridge Chip Internal Register BARO 32 9 1 2 WO Space Register Assignments DAT 32 9 1 3 Memory Space Assignments BAH 33 9 1 4 DMA ne ane ener ere A ese ere ere ere ree 33 9 2 Local Bus Memory Map 2 ccc cccccceceneeeet cence eete ence teteeneeneteentetedeeneetetennenene 34 10 Stand Al n MONG E 35 11 Specifications E 36 11 1 Performance Figures ses een eos en ee en een 36 11 2 Relative J TAC SDC Es ec cc cs ce ct ts 37 11 3 Mechanical Dimensions mn din de de de 37 bh E EE POWET ONSUMPION ES manne nr dada
3. If it doesn t detect the SMT310Q then it means the EPROM file hasn t been loaded Version 2 1 Page 52 of 55 SMT310Q User Manual 16 Checking for hardware resource conflicts For 2000 and XP users Check for any resource conflicts by right clicking on the My Computer icon and selecting Manage from the menu Select the Device manager in the left pane and the Sundance carrier board in the right D Computer Management FOX WB Fie Action View Window Help 5 x DR Se A Sa Computer Management A gt Keyboards System Tools 7 Mice and other pointing devices fg Event Viewer Monitors 9 Shared Folders 9 Network adapters Local Users and Gro a Ports COM amp LPT Si Performance Logs SBR Processors A Device Manager Sound video and game controllers Sy Storage J S Sundance amp Removable Storage Sa BS Disk Defragmenter re System devices aix gt H Universal Serial Bus controllers Ensure that there are no resource conflicts by right clicking on the carrier board and selecting Properties from the menu Version 2 1 Page 53 of 55 SMT310Q User Manual SMT3100 Properties General Driver Resources Hg mn Resource settings Resource type Setting WH Memory Range FFDFFFOO FFDFFFFF Wu Ronge FE00 FEFF Memory Range FD000000 FDFFFFFF Conflicting device list No conflicts If there are conflicts
4. T1C1 T2C4 A T1C4 T4C3 C Table 1 COM SWITCH Register B T1C5 T4C1 A SMT310Q User Manual T3C3 T4C0O T3C2 T4C5 T3C1 T4C4 T2C2 T3C5 T2C1 T3C4 T1C3 T2C0 Bit Clear 0 Set 1 Bit Clear 0 Set 1 T4C1 T1C4 T1C3 FMS DO T4C1 FMS D8 T1C3 T2C0 Requires D3 set T2CO FMS T4C2 T1C5 T2C1 FMS D1 T4C2 FMS D9 T2C1 T3C4 Requires D4 set T3C4 FMS T4C3 T1C0 T2C2 FMS D2 T4C3 FMS D10 T2C2 T3C5 Requires D5 set T3C5 FMS T1C4 T4C1 T2C3 FMS D3 T1C4 FMS D11 T2C3 T3C0 Requires DO set T3CO FMS T1C5 T4C2 T3C1 FMS D4 T1C5 FMS D12 T3C1 T4C4 Requires D1 set T4C4 FMS T1CO T4C3 T3C2 FMS D5 T1CO FMS D13 T3C2 T4C5 Requires D2 set T4C5 FMS T1C1 FMS D6 T1C1 T2C4 D14 T3C3 FMS T3C3 T4C0 T2C4 FMS T1C2 FMS PCI T1C3 PCI External D7 T1C2 T2C5 DIS C BUF Extemar BUlered Gomport 1202 ENS Buffered Comport 11C3 C_BUF Version 2 1 Page 16 of 55 SMT310Q User Manual 4 2 Buffered External Comport The buffer consists of an FCT245AT type device with 64mA pull down ability All signals are pulled up to 3 3 volts with 100 ohm resistors and the active devices are mounted as closely as possible to the connector they serve The back panel connector is a 26 pin 3M type 3M part number 10226 5212JL As well as ground signals and the 12 C4x comport signals there are 6 additional signals These
5. JTAG connector J21 To access the EPLDs you will need both the Xilinx parallel programming cable and a copy of the ISE version 6 3 or later The earlier versions of impact don t support the type of EPLDS on board the SMT310Q Version 2 1 Page 50 of 55 SMT310Q User Manual 3 After the JTAG cable has been connected the user should run impact Once the connection has been detected and setup Impact will show that there are two different CPLDs G untitled Configuration Mode iMPACT DI x File Edit View Mode Operations Output Help CECI A Halang Boundary Scan Slave Serial SelectMAP Desktop Configuration Right click device to select operations 0951 44x xc95288xl pciarb2_3 jed comv4_3 jed Ve BATCH CMD Identify PROGRESS_START Starting Operation Identifying chain contents TU Manufacturers ID Xilinx xc95288xl Version 3 INFO MPACT 1777 ing C Xilin2 xc9500xldata zc95288x bed INFOAMPACT 1777 Reading CXilio2 xc9500xldata xc95 1 44xl bsd INFOAMPACT 501 1 Added Device xc95144x successfully For Help press F1 Configuration Mode Boundary Scan Parallel 111 lipti Fz The first EPLD XC95144XL in the chain needs to be loaded with the file pciarb jed For the second EPLD XC95288XL the user will want to load the file comm jed After the CPLDs have been programmed you have to run the SetCpld exe utility contained in the package This utility is run f
6. Register Read Width 0016 0416 COMPORT_ OUT COMPORT_IN DURS METE O ge ne D l duc CR RS Table 8 1 0 address space map Version 2 1 Page 33 of 55 SMT310Q User Manual 9 1 3 Memory Space Assignments BAR2 age Description We 000000006 000FFFFF 46 Shared Memory Bank 1MB SRAM Mirror of COMPORT OUT 0020009046 Comport Data Mirror COMPORT_IN See Note 2 Mirror of Control Status 0020009446 Comport Status Mirror See Note 2 f Mirror of Int_Control 0020009816 Comport Int_Control Mirror See Note 2 002000005 0020007F16 Global Bus See Note 1 Input Output 16 bit SDB 002002606 0020027F 16 SDB Control Register SDB Control Status Table 9 Memory space map Note 1 In order for the TIM to respond to accesses for this area address line GADD30 and GADD19 of the TIM site connector must be decoded as high and GADD7 and GADD5 must be decoded as low Note 2 These mirrors of addresses in the I O Space BAR1 allow increased transfer speeds across the host comport link in excess of x10 increase 9 1 4 DMA Engine The PCI Bridge DMA processor sees the shared memory at a different address from that used for normal accesses For normal memory access the memory base address register offset is 0000000016 For DMA access address line A28 On hardware interface must be high therefore DMA memory access starts at 40000000 not 10000000 as addressing is in bytes Version 2 1 Page 34 of 55 SMT310Q Use
7. Ta ae TN dd Ta 37 12 Cables and Connectors ss ESS iana aaas anaip iaup sanp Ea iaaii Sapas 38 EN E B E E E E E E AE EEE E iar E ak ears te tn le in 38 12 1 1 2S BB COMMOCION ox cenccesecesccesecenccesecencoeserentc esecesecevecentceuecencoeseceneceseceneces 38 122 ENEE geed etes at GR nt ne taire ter 38 122 1 FMS CAIN n tet ok ai in Sot ee O bed oe hn oe So be So hoe do 38 12 2 2 Buffered Comport Cabling EE 39 123 STNG Cabling EE 40 12 4 Reset and Config headers 44 13 Expansion Fleege 45 14 JTAG Interface circuits cess EE a 46 E a RRE Ee 46 15 Firmware Upgrades ANE 48 15 1 CPLD and EPROM reprogramming AAA 49 te Fa CP DS HAINE ss sr ns ss se 49 15 12 EPROM Updating sante e eee ess 51 Version 2 1 Page 5 of 55 SMT310Q User Manual 16 Checking for hardware resource conflicts 52 17 Where s that Jumper ennemie 54 18 LED description Version 2 1 Page 6 of 55 SMT310Q User Manual 1 Introduction The SMT310Q is a full length PCI board that can carry up to four industry standard TIM format processor modules Sundance provides a large range of these TIMs Features e Processor interconnection using comports Direct comport and SDB access to the host is also provided e A software configurable routing matrix to allow certain comport connectivity without needing external cables e 1MB of shared SRAM between the host and TIM site 1 the Master TIM site e On b
8. e Try inserting the carrier board into another PCI slot e Try removing other PCI devices Version 2 1 Page 54 of 55 SMT310Q User Manual 17 Where s that Jumper J10 Reset Out 12 Config Out J11 XDS 510 JTAG Out 317 Config In 3 Sa CCC dures E rares 2 2 2 Seeeeeaeseses WER e ee ee ee KKKA elei KN 36 Buffered Comport Connector J18 5D8 Rx Tx Select J7 High Low Comport Select J5 Buffered JTAG Connector Figure 17 Jumper Finder Diagram Version 2 1 Page 55 of 55 18 LED description On the SMT310Q carrier board LED1 indicates the direction of the transfer for the host comport LED2 indicates the reset of the board SMT310Q User Manual
9. jumpers J3 J5 J11 and J14 can be found in Figure 17 Important Note There must only ever be one jumper fitted in J3 Multiple SMT310Qs can be cascaded in a JTAG chain but the master device must drive out through either the buffered JTAG or the XDS 510 header not both If you require all modules to be reset when using multiple SMT310Qs the Reset In and Reset Out headers must be chained together See Reset and Config headers There are three cable options for the SMT310Q e SMT501 JTAG is designed to connect two SMTxxx carrier boards for example an SMT310Q controlling an SMT328 VME carrier The length of SMT501 JTAG is 1 meter e SMT510 XDS is a variant of the SMT501 JTAG providing an XDS 510 14 way connector to interface to non Sundance products e SMT503 JTAG INT is used to connect to the un buffered XDS 510 compatible JTAG in and out headers 6 1 Using the SMT310Q External Internal JTAG with TI Tools For details on using the SMT310Q with Texas Instruments Code Composer see the SMT6012 documentation The SMT6012 is Sundance s driver for Code Composer and can be obtained separately The Texas Instruments Evaluation Module EVM kits can be used as stand alone devices with an SMT310Q as the JTAG master When running with the EVM kits ensure that the EVM jumper is set up correctly External JTAG must be selected and the DSP boot location must be set for internal memory space Version 2 1 Page 23 of 55 SMT310Q User Man
10. 1 IIOF2 DSP Interrupt signals These are open collector signals on the SMT310Q that can be driven by the DSP interrupt the host or driven by the host to interrupt the DSP Version 2 1 Page 27 of 55 SMT310Q User Manual In the timing diagram below all signals change relative to the rising LCLK signal This signal is the H1 clock signal of the DSP when using the DSP global bus in synchronous mode TIMReq FIFO Full cm ee ee ee Se STRB1 RD STATO TT DS AE DE We an Eb Ge Ey a Ct al Et ED Sanat Rue i SS gt Ey Figure 8 Timing diagram for DSP local bus access LCLK Period 30ns frequency is 33MHz The DSP initiates a global bus R W by asserting the STRB1 low and STAT 1 3 change see the TIM Spec for details of STAT 1 3 Once the arbitration unit detects this it waits for the last cycle of the Local bus to be completed by the PCI bridge before allowing the DSP to become Bus Master Once the DSP is Master the arbitration unit drives AE and DE low to enable the DSP s address and data lines RDY1 is driven low by the arbiter to indicate to the DSP on the next rising LCLK that the data packet has been transferred If the input FIFO 256 words deep becomes full the arbitration logic de asserts the RDY1 signal to indicate a hold off state Once the data have been transferred from the FIFO to the PCI bus RDY1 is re asserted to continue the transfer Asserting STATO low indicates the end of the
11. Allows a programmed interrupt to be generated by the C40 when set CLEAR OBE INT Write a one to this bit to clear the interrupt resulting from a comport output event CLEAR IBF INT Write a one to this bit to clear the interrupt event resulting from comport input CLEAR C40 INT Write a one to this bit to clear down the C40 INT event Table 5 Interrupt Control Register 4 4 Comport Direction Comports will automatically switch direction during the execution of a program but when they come out of reset they will be set to an initial direction input or output You should always ensure that you only ever connect pairs of comports that reset to opposite initial directions Comports resetting as inputs 3 4 5 Comports resetting as outputs 0 1 2 Version 2 1 Page 20 of 55 SMT310Q User Manual 5 Sundance Digital Bus SDB A growing number of Sundance s Modules have an on board SDB A description of the SDB interface may be found on the Sundance web site at www sundance com html pdf_info htm The following register controls the carrier s SDB RE EE EE Table 6 SDB Control Register The SDB control and status register is located at BAR2 offset 0020026016 The bit definitions are shown below RXNTX SDB Direction The SDB direction is set using Jumper J18 Figure 17 on the SMT310Q When the jumper is removed the SDB is set for receive mode when the jumper is present the SDB is set for transmit mode Thi
12. C Figure 9 SMT310Q to PCI Interrupts Interrupts can also be generated by the SMT310Q writing or reading the mailbox registers in the PCI Bridge Version 2 1 Page 30 of 55 SMT310Q User Manual 8 2 PCI To SMT310Q Interrupts 8 3 CONTROL CPLD CONTROL REGISTER PCI Bridae gt IIOFO gt TIMI OFO g _IIOF1 gt TIMIIOF1 IIOF2 gt TIMIIOF2 LINTcan o be caused INTREG by any PCI REGISTER interrupt e g Mailbox IMIIOFO IE LINT e UNI muer IE e gt TIMIIOF2 IE Figure 10 PCI to SMT310Q Interrupts Interrupt Registers The following registers are used to control PCI DSP and DSP PCI interrupts PCI bridge internal register PCI Interrupt Configuration BAR 0 4C 6 PCI Interrupt Status BAR 0 48 16 Local Bus Interrupt Mask BAR 0 7716 Local Bus Interrupt Status BAR 0 7616 PCI Mailbox Write Interrupt Control BAR 0 D046 PCI Mailbox Read Interrupt Control BAR 0 D216 Local Bus Mailbox Write Interrupt Control BAR 0 D446 Local Bus Mailbox Read Interrupt Control BAR 0 D6416 Mailbox Write Interrupt Status BAR 0 D816 Mailbox Read Interrupt Status BAR 0 DAi6 Version 2 1 Page 31 of 55 SMT310Q User Manual Details of these registers can be found in the V363EPC Local Bus PCI Bridge User Manual http www quicklogic com home asp Pagel
13. CK1 of each of the four TIM sites The pin out for the header is shown below IIMOFO GND IIMOF 1 GND TIM SITE 1 IIMOF2 GND TCKO GND TCK1 GND IIMOFO GND IIMOF1 GND TIM SITE 2 IIMOF2 GND TCKO GND TCK1 GND IIMOFO GND IIMOF1 GND TIM SITE 3 IIMOF2 GND TCKO GND TCK1 GND IIMOFO GND IIMOF 1 GND TIM SITE 4 IIMOF2 GND TCKO GND TCK1 GND Figure 14 Expansion Header Pin Out Diagram Version 2 1 Page 46 of 55 SMT310Q User Manual 14 JTAG Interface circuits The buffered JTAG circuit on the SMT310Q allows connection between SMT310Q cards and other compatible carrier modules This section describes the JTAG interfacing circuitry to customers custom built slave devices 14 1 Signal Description Signal Description TDI JTAG Test Data In The master device drives this signal TDO JTAG Test Data Out The slave device drives this signal TMS Test Mode Select Driven by the master device TCK JTAG Clock Driven by the master TCK_RET JTAG Clock Return driven by the slave ITRST JTAG Reset driven by the master RESET Board Reset Driven my master Unused on SMT310Q PD Pod Detect signal This signal should be connected 3 3V or 5V on the slave device to indicate to the master that an external device is present DETECT A master pulls this signal to GND If connecting two SMT310Q together a jumper is used on one of the carriers switching it to slave mode to prevent two masters being con
14. D 223 amp sMenulD 114 Docs Other Registers Control Register BAR1 Offset 1416 WRITE ONLY Interrupt Control Register BAR1 Offset 1816 INTREG Register BAR1 Offset 4016 8 3 1 INTREG Register BAR1 Offset 4016 Bits Name Description 15 Reserved 14 Reserved 13 Reserved 12 Reserved 11 Reserved 10 Reserved 9 Reserved 8 Reserved 7 Reserved 6 Reserved 5 Reserved 4 Reserved 3 S Reserved 2 IIOF2EN PC to DSP TIMIIOF2 interrupt enable 1 IIOF1EN PC to DSP TIMIIOF1 interrupt enable 0 IIOFOEN PC to DSP TIMIIOFO interrupt enable Table 7 INTREG Register Version 2 1 Page 32 of 55 SMT310Q User Manual 9 Memory Maps All address information is given in bytes 9 1 PCI Bus Memory Map 9 1 1 PCI Bridge Chip Internal Register BARO Please see the User Manual for the V363EPC Local Bus PCI Bridge chip http www quicklogic com home asp PagelD 223 amp sMenulD 114 Docs for details of internal registers 9 1 2 UO Space Register Assignments BAR1 In target mode a host device accesses the SMT310Q across the PCI bus which gives access to the target mode registers The operating system or BIOS will normally allocate a base address for the target mode registers of each SMT310Q Access to each register within the SMT310Q is then made at offsets from this base address as shown in the table below Offset Register Write
15. S will reset as an output See Figure 17 D15 1 C_BUF FMS is connected to T1C3 this resets to an input D15 J7 fitted J7 removed 0 Connect C_BUF to an output comport Connect C_BUF to an input comport 1 Connect C_BUF to an output comport Not to be used Some TIMs do not implement all six possible comports Version 2 1 Page 13 of 55 SMT310Q User Manual A B C Host Link Exe mal Buffered Comport FMS Connector Quick Switch A B C Figure 4 Comport Switching Matrix Version 2 1 Page 14 of 55 SMT310Q User Manual The Quick Switches are controlled by the COM SWITCH register BAR1 offset 2416 The Quick Switch controlled by bit D15 of the COM SWITCH register has the following effect External External T1C3 Buffered T1C3 Buffered Comport Comport Em se E je C BUF Host Link C CBUF Fu Host Link S 3 C PR Pe S kA essais Lo Quick Switch off 0 pus us off 0 Jumper J7 fitted umper J remove External T1C3 Buffered Comport Quick Switch on 1 The switches controlled by all other bits of the COM SWITCH register have the following effect FMS A FMS B Quick Switch off 0 Quick Switch on 1 Figure 5 Operation of quick switches Version 2 1 Page 15 of 55 PCI External T1C3 C_BUF T2C3 T3C0 D7 T102 T2C5 C T1C0 T4C2 B
16. SMT310Q User Manual Certificate Number FM 55022 User Manual QCF42 Version 3 1 31 03 03 Sundance Multiprocessor Technology Ltd 2003 Version 2 1 Page 2 of 55 SMT310Q User Manual Revision History CCC rr 31 10 01 Original Document SP 08 20 11 01 Global Bus Accessing AJP 09 0 1 20 12 05 Version 2 1 Page 3 of 55 SMT310Q User Manual Table of Contents T Introduction SES ne 6 2 Installing the SMT S10 NEE 7 2 1 Software installation ntt rtrtennnen rnnr enee 7 2 2 Hardware Installation ssinmistinminaetnamidtneitentietienees 7 2 3 Testing the hardware scsi en en EES 7 3 Hardware Overview 5 55 Eed EEGENEN 9 OA Eeer 9 3 2 V363EPC PCI Bridge Chip EE 10 3 3 TAG controler eee KEE EEN E E E E EEEE 10 E KE EE 10 3 9 TEE ee Ee ee tre Et Pa ire 10 3 6 Onboard TESOUI CE Six EE 11 3 6 1 SDB EE 11 3 6 2 Lu CO LS M 90 48 816 4 EI LL LR eee r nant te Rene Stier kre r ero 11 Be e e Teen occas ee aca seco es veep eck Se Le 12 ae ce ee Pe oe erat ee PcPro PCO te RS UL VCO nt ee ne 1 172 12 4 2 Buffered External Gompor EEN 16 ka AGOmMpOrtt0 PCI Interface esenee e E Ea 16 4 3 1 Comport Registers BAR1 Offset 1016 VV 16 4 3 2 Control Register BAR1 Offset 1416 WRITE ONLY 17 4 3 3 Status Register BAR1 Offset 1416 Read Only 18 4 3 4 Interrupt Control Register BAR1 Offset 1846
17. The connectors are marked TxCy where x indicates the TIM site 1 4 and y the comport number 0 5 You can connect pairs of comports by plugging cables into these FMS connectors Details of the connections can be found in FMS Cabling As an alternative to cables you can use on board connections that allow for a subset of the possible topologies These on board connections are selected by means of Quick Switches programmed from the Host Figure 4 shows the possible connections When the SMT310Q comes out of reset all the quick switches will be in the 0 state There is a connection from the PCI interface to T1C3 This is enabled by default and is intended for booting the system The connection can be changed with the quick switch controlled by bit D15 in the COM SWITCH register The two settings are 0 Connect the Host Link to T1C3 and connect the C_BUF FMS connector to the external buffered comport This allows any of the remaining comports on sites 1 4 to be connected to the external buffered comport with an FMS cable In this state the FMS connector for T1C3 must not be used 1 Connect the Host Link to the external buffered comport and connect T1C3 to the C_BUF FMS connector 4 1 C BUF Bit D15 in the COM SWITCH register determines the connection of the C_BUF FMS connector J15 D15 0 C_BUF FMS is connected to the buffered comport With jumper J7 fitted C_BUF FMS will reset as an input With J7 removed C_BUF FM
18. be routed to INTA INTB or INTC using the PCI Interrupt Configuration Register BARO offset 4C 16 Set when a word has been written to the comport output register Cleared when the word has been transmitted to the DSP INTD The logical OR of bits 7 4 in this register gated with each one s enable bit Version 2 1 Page 19 of 55 SMT310Q User Manual 4 3 4 Interrupt Control Register BAR1 Offset 1816 This write only register controls the generation of interrupts on the PCI bus Each interrupt source has an associated enable and clear flag This register can be written with the contents of bits 7 0 of the Status Register The JTAG controller generates TBC INT and must be cleared of all interrupt sources in order to clear the interrupt ee ae nn ee Sea EE DSP PC CLEAR CLEAR CLEAR OBE C40IE TBC IE IBF IE OBE IE IIOF0 En C40 INT IBF INT INT DSP PC IIOF2 En Enables DSP PC interrupts on IIOF2 DSP PC IIOF1 En Enables DSP PC interrupts on IIOF 1 DSP PC IIOFO En Enables DSP PC interrupts on IIOFO IBF IE Comport Input Buffer Full Interrupt Enable Allows an interrupt to be generated when the host comport input register is loaded with data from the C40 OBE IE Comport Output Buffer Empty Interrupt Allows an interrupt to be generated when the host comport register has transmitted its contents TBC IE Test Bus Controller Interrupt Enable Interrupts from the Texas JTAG controller are enabled when set C40 IE C40 Interrupt Enable
19. burst access If RDY1 is not active then STATO should remain asserted until ready is asserted and the final data transaction has been completed It is possible for a deadlock condition to arise if the PCI bus is trying to read from the SMT310Q resources while the DSP is reading from the PCI Bus If this happens the arbitration unit gives the PCI bridge device priority and services the HOST PCI access before giving bus ownership back to the DSP Version 2 1 Page 28 of 55 SMT310Q User Manual When running code composer applications to debug the DSP a reduction in the speed of the debugger may be noticed The DSP has priority when accessing the local bus and any other accesses will only occur under the following conditions e Burst access finishes e A deadlock condition occurs which forces the DSP to release ownership of the Bus For multi threaded applications the length of the DSP burst can be reduced to allow PCI bus R W cycles snatch cycles from the DSP Version 2 1 8 Interrupts 8 1 Page 29 of 55 SMT310Q To PCI Interrupts SMT310Q User Manual CONTROL EPLD D REGISTER REGISTER Wi Name MDSPINT Ca01E oan DEZ wm ven MIMIOFZ dea OBE INT OBE E UTAG INT CIN sec E INTA INTB INT
20. e The maximum tested cable length is 1 meter On reset each comport initialises to being either an input or an output Do not connect Reset to Input comports together Do not connect Reset to Output comports together However if this should occur no damage will result because comport direction signals disable relevant comports Version 2 1 Page 40 of 55 SMT310Q User Manual The following table shows connector pin out and cable pair connections This is important as the critical signals must be paired with a ground as shown The allocation to twisted pairs is based on grouping the data signals because they change at the same time so that crosstalk is not an issue Each control signal has its own ground Twisted RTI RTO Twisted RTI Signal RTO Signal Pair Signal Signal Pair s se 2 2 E CE so EUR SE AOE ET ET Lie 6 opte ee 2 a a s 9 ps Css esr sre Eee eee cnND enD FETAN AN mE ICRDY ICRDY VCC par 11 7 RTS Case es 23 12 stout stn all ag op 2 r SRE RES Law sw als fo RCE RST_IN RST_OUT SHIELD SHIELD Table 13 Buffered Comport connector pinout The overall shield is attached to the body of the metal plug shell The signal VCC is fused on the board at 1 amp the fuse automatically resets when the load is removed When the buffered comport is reset to input pins 1 and 23 are always driven and pins 3 and 25 are always receivers When t
21. e units a write access over the global bus to 1C000000 C0 will write to the first 4 mailbox registers in the PCI bridge device The mailbox registers are accessed from the PCI bus through the PCl to Internal Register PCI_IO_BASE aperture This is accessed via the PCI Bridge Chip Internal Register BARO byte offset CO16 CF 16 7 1 1 Doorbell Interrupts Each of the 16 mailbox registers can generate four different interrupt requests called doorbell interrupts Each of these requests can be independently masked for each mailbox register The four doorbell interrupt types are e DSP interrupt request on read from PCI side e DSP interrupt request on write from PCI side e PCI interrupt request on read from DSP side e PCI interrupt request on write from DSP side The PCI read and DSP read interrupts are ORed together and latched in the mailbox read interrupt status register MAIL_RD_STAT Similarly the PCI write and DSP write interrupts are ORed together and latched in the mailbox write interrupt status register MAIL_WR_STAT All of the interrupt request outputs from the status registers are ORed together to form a single mailbox unit interrupt request and routed to both the Local and PCI Interrupt Control Units When several mailbox registers are accessed simultaneously for example when 4 mailbox registers are read as a word quantity then each register affected will request a separate interrupt if programmed to do so See sectio
22. he buffered comport is reset to output pins 3 and 25 are always driven and pins 1 and 23 are always receivers 12 3 JTAG cabling The 20 way JTAG connectors require the following cabling components Cable plugs 3M Scotchflex 10120 6000EL FES part 038739R Plug shells 3M Scotchflex 10320 A200 00 FES part 038759A Cable type 3M Scotchflex KUCKMPVVSB28 10PAIR FES part 038780G Version 2 1 Page 41 of 55 SMT310Q User Manual When the SMT310Q is configured as a Slave using the Buffered JTAG connector as a JTAG source the buffered connector pins are used as follows EE ER re ol m s meomn PC RS BE AC ff CSCS pee ca BC CS AE ss CSCS Co rocret or mem Pol oo SCS else II ol eo Lan Pommeau else II afse LT Table 14 Buffered JTAG connector pin functionality as JTAG source Version 2 1 Page 42 of 55 SMT310Q User Manual When the SMT310Q is configured as a Master using the Buffered JTAG connector to connect to a JTAG slave the buffered connector pins are used as follows Fu Sat onn rm Tee S eet D PS 9 TCK_RET JTAG clock return eet S ett a IRESET Board Reset out 14 PD N Presence detect when pulled high IDETECT Detect external JTAG controller when grounded CONFIG OPEN COLL Global open collector C4x CONFIG EMUO Buffered EMUO output EMU Buffered EMU1 output Table 15 Buffered JTAG connector pin functionality as JTAG master Version 2 1 Page 43 of 55 SMT310Q User Manual Direct
23. ion Description JTAG Test mode select JTAG Reset JTAG data out oa SE DN Ee PET e key fonte oooO S ES Pe ES CE e PE ES ITRST 5 PD 5 i EE w SSCS D Table 16 Internal JTAG out XDS 510 pin descriptions Fin Signal i DEER sf SCH o rox CE ES CS 0 1 1 1 1 1 fs rox _ nf 3 4 JTAG clock return 1 JTAG clock 10MHz EMUO Buffered EMUO Out EMU Buffered EMU Out Table 17 Internal JTAG in XDS 510 pin descriptions Version 2 1 Page 44 of 55 SMT310Q User Manual 12 4 Reset and Config headers There are pairs of headers for TIMRESET and TIMCONFIG to allow several SMT310Qs to be chained together The TIMRESET headers are J10 Reset Out and J9 Reset In and the TIMCONFIG headers are J12 Config Out and J17 Config In Below is the pin out for each header Pin Signal 1 TIMRESET 2 GND Table 18 Reset header pin out IN OUT Pin Signal 1 ITIMCONFIG 2 GND Table 19 Config header pin out IN OUT Pin 1 of header is the lower pin These headers should be chained together for all boards in the system Out to In Version 2 1 Page 45 of 55 SMT310Q User Manual 13 Expansion Header J2 The expansion header at the opposite end of the board to the end plate is a 40 pin interleaved ground header which provides access to the three interrupt lines IIMOFO IIMOF01 IIMOF2 and two clock lines TCKO T
24. ld be set to select the local bus clock in preference to its own oscillator to allow it to synchronise accesses across the PCI Bridge Details of this can usually be found in the TIM documentation under Global Bus Control Register The Local Bus is not shown explicitly in the SMT310Q block diagram Version 2 1 Page 10 of 55 SMT310Q User Manual 3 2 V363EPC PCI Bridge Chip The PCI Bridge connects the host PCI bus to various devices on the local bus e Quick Logic EPC363 bridge chip This has a 32 bit 33MHz PCI interface that supports 1 C control mailbox register access and direct memory reads and writes e Input and output FIFO This is capable of transferring 256 32 bit words of data to and from the DSP at 33MHz bursting at a maximum local bus transfer rate of 132MB s e Address apertures These provide access to the V363EPC bridge chip configuration registers or bridging functions The apertures respond to addresses on both the PCI and Local buses The following apertures are available on the SMT310Q o Four data transfer apertures to transfer data across the bridge Two apertures are for PCI to local transfers BAR1 and BAR2 and two are for local to PCI transfers Local to PCI Aperture 0 and Local to PCI Aperture 1 o Two apertures to access the bridge chip s internal registers one aperture for Local Bus PCI Bridge Register accesses and one for PCI bus BARO accesses 3 3 JTAG controller The JTAG controller i
25. ligned value e Write Read data using Local to PCI Aperture 0 Version 2 1 Page 26 of 55 SMT310Q User Manual 7 4 DSP Signals AE DE active low address data enable signals driven by the SMT310Q When the DSP has ownership of the bus these signals are driven low by the SMT310Q allowing the DSP to drive the address and data pins GEO the tri state control for the DSP s global bus control pins This is permanently tied low by the SMT310Q as the control signals are always enabled STRB1 the data strobe signal from the DSP s global bus It is driven low when the DSP is carrying out an access cycle The DSP waits for RDY1 to be driven low by the SMT310Q to indicate transfer has been completed This transfer is carried out in synchronous burst mode The DSP pulls STATO low to signal when the burst transfer has completed RDY 1 an active low transfer acknowledgement driven by the SMT310Q to indicate that the current transfer has been completed STATO STAT1 STAT2 STAT3 the DSP Status line When all of the signals are logic 1 then the DSP Global bus interface is in an idle state When any of these signals is driven low the DSP is requesting ownership of the SMT310Q s local bus STATO has a special meaning and is driven low by the DSP to indicate the last data packet transfer A0 A30 the DSP s global Bus address lines DO D31 the DSP s global Bus data lines IIOFO IIOF
26. meters e The transfer size e Frequency of transfer e The layout of the target memory Scatter Gather or contiguous e Availability of the PCI bus e Other devices on the PCI bus e Debugging traffic on the bus e Comport traffic Transfer MIN MAX AVERAGE Comments type Mb s Mb s Mb s C60 Burst Will Vary depending Memory C60 Burst i j Will Vary depending Memory Table 11 Performance Figures Version 2 1 Page 37 of 55 SMT310Q User Manual 11 2 Relative JTAG speed Relative Emulator Speeds 2 50 2 00 1 62 1 50 1 67 ee 1 25 1 20 1 00 4 e 0 85 0 60 0 50 a io 0 00 i Speed relative to XDS510 XDS510 FleXDS SP1525 XDS510PP SPI515 XDS510PP Tiger SMT106 SMT310Q Plus Emulator Figure 12 JTAG speed Comparison chart 11 3 Mechanical Dimensions The board size is 312mm x 120mm 11 4 Power consumption The SMT310Q takes 3 3V and DV power from the PC s internal power supply The following current consumption figures were measured using a LEM current clamp during a quiescent period Current drawn from 3 3v supply 440mA Current drawn from 5v supply 100mA Version 2 1 Page 38 of 55 SMT310Q User Manual 12 Cables and Connectors 12 1 SDB No SDB cables are supplied with the SMT310Q You can order them separately from Sundance with part number SMT510 SDBxx where xx is the cable length in centimetres 12 1 1 SDB Connector Function Function USERDEFO
27. n 8 for further information on Interrupts 7 2 DSP Interrupt Control Interrupts can be enabled from a number of different sources i e DSP Host and Host DSP See section 8 fora description of these functions Version 2 1 Page 25 of 55 SMT310Q User Manual 7 3 DSP To Local Aperture 0 control and Accessing The quickest way to transfer information between the DSP and PCI Bus is to use the Local to PCI Aperture 0 in the PCI bridge device DSP may need to transfer large amounts of acquired data to the PC host for data storage or post processing Allowing the DSP to take control of the PCI bus means that the HOST only needs to be involved once the data have been transferred by the DSP to PC memory Alerting the Host that data have been transferred can be accomplished in a number of ways for example by writing to a mailbox register to generate an interrupt The Local to PCI Aperture 0 is mapped as a region of addressable space from 18000000 6 183FFFFF46 words as shown in Table 4 section 5 There are several registers to initialise before data can be read or written via this address space e Unlock the PCI Bridge System register This requires a write to the LB _CFG SYSTEM offset 7816 BAR 0 with the value AO5F 46 e Write the upper 8 bits of your destination address in bytes to the upper 8 bits of the 32 bit Local Bus to PCI Map O register LB MAPO RES offset in bytes 5c4 e Convert you lower 24 bit address to a word a
28. nected together CONFIG This signal is unused and should be left unconnected EMUO EMU1 These are open collector JTAG emulation pins and should be connected to the DSP Pull up resistors are required Table 20 JTAG signals Version 2 1 Page 47 of 55 SMT310Q User Manual The JTAG circuit for a slave target board is shown in Figure 15 Using the correct buffers and connectivity is essential to achieving a working JTAG interface VCC Slave Connector TDI TDO TCLK TCLK_RET TMS TRST IRESET JTAG Device PD DETECT CONFIG Figure 15 JTAG Slave circuit All buffers are of type 74FCT244 5V 74LV244 3 3V or equivalent N B When the JTAG device is NON 5v tolerant ensure that 3 3v buffers are used Version 2 1 Page 48 of 55 SMT310Q User Manual 15 Firmware Upgrades The SMT310Q series carrier boards are populated with two Xilinx CPLDs XC95144XL and XC95288XL that act as an on board arbitration unit that control which device has access to the Local Bus resources These devices are very important on the carrier board and it is necessary to keep these devices up to date From time to time Sundance might issue a CPLD update The Sundance wizard will alert you when you need to update your CPLD To upgrade the firmware Xilinx JTAG programming software is required together with a lead to connect to the SMT310Q s header The image below shows the location of pin 1 of the JTAG connector J21 This connec
29. oard JTAG controller to allow debugging using Code Composer The board can also be used as a JTAG master for debugging remote systems e On board PCI bridge chip to provide DMA mailbox events and interrupts e PCI access between the host and the Master TIM site at burst speeds in the range 60 100MB s Version 2 1 Page 7 of 55 SMT310Q User Manual 2 installing the SMT310Q 2 1 Software installation You should install the SMT6300 software package before plugging the hardware into your PC The SMT6300 sets up device drivers and test utilities for the Sundance range of carrier boards 2 2 Hardware installation 1 Plug your TIMs into the SMT310Q slots You should normally always have a TIM in the Master TIM site nearest the board s end plate Note that many TIMs require a 3 3V supply This is taken from the mounting pillars so it is important you bolt down the modules securely 2 Power down the PC 3 Insert the SMT310Q into a spare PCI slot 4 Power up your PC If you are using Windows 2000 or Windows XP the hardware wizard should appear Figure 1 5 Click Next gt The wizard should indicate that the SMT310Q has been installed successfully Figure 2 6 Click Finish 2 3 Testing the hardware The SMT6300 comes with a utility called SmtBoardinfo exe You should start this and run its confidence test found under Tools 1 Windows NT users No hardware wizard will appear but you should ensure
30. ol Register BAR1 Offset 1416 WRITE ONLY The CONTROL register contains various control flags A EE os D Leo tore reser RESET Write a 1 to this bit to assert the reset signal to all the TIM modules on the SMT310Q These bits connect to the corresponding pins on the TIM in module site 1 Writing 0 causes the corresponding IIOF line to go low Table 3 Control Register Note On PCI system reset RESET is asserted to all TIM sites Version 2 1 Page 18 of 55 SMT310Q User Manual 4 3 3 Status Register BAR1 Offset 1416 Read Only EE ee eee ee a IMO INTD Come Dees o master er o8 En m1 CR RS ee OBE INT Set if the comport output buffer becomes empty Cleared by writing a 1 to the corresponding bit in the interrupt control register IBF INT Set if the comport input buffer receives a word Cleared by writing a ito the corresponding bit in the interrupt control register TBC INT Set when the TBC asserts its interrupt Cleared by removing the source of the interrupt in the TBC C40 INT Set when the TIM DSP sets its host interrupt bit Cleared by writing a 1 to the corresponding bit in the interrupt control register TBC RDY Reflects the current state of the TBC RDY pin This bit is active high and therefore is an inversion of the TBC pin CONFIG_L Reflects the state of the TIMs CONFIG signal Active low Table 4 Status Register INTD is the input interrupt into the PCI Bridge from the SMT310Q this can
31. or all the sites are not populated with a TIM then the module s SENSE signal is used to enable a tri state buffer connecting TDI and TDO JTAG Data In and Data Out on the specific site maintaining the integrity of the JTAG data path This switching is automatic The Buffered External JTAG Connector J5 is intended to connect to a JTAG device external to the system chassis When the SMT310Q is in master mode the buffered JTAG connector acts as a master and is to be connected to JTAG slaves The un buffered JTAG out XDS 510 Header J11 is for use with JTAG slaves within the system chassis When either of these connectors is connected to a JTAG slave device the SMT310Q automatically detects the device and routes the test data accordingly Master mode is selected with a jumper in location A on J3 When the SMT310Q is configured in Slave mode the TBC on the SMT310Q is disabled as the TBC is assumed to be on another device connected to the SMT310Q If using a TBC device within the same system chassis the connection can be made using the XDS 510 compatible connector J14 Version 2 1 Page 22 of 55 SMT310Q User Manual In this case the XDS 510 compatible connector must be selected as the JTAG source by fitting a jumper on J3 in location B If the TBC device is out side the system chassis then the External Buffered JTAG connector J5 should be used Again this connector must be selected as the JTAG source by fitting a jumper on J3 in location C The
32. r Manual 9 2 Local Bus Memory Map The table below illustrates the resources and their corresponding address regions when accessed by the Master module 1800000046 183FFFFF 46 Local to PCI Aperture 0 PCI Bridge Aperture 0 Space 1400000046 17FFFFFF 16 Local to PCI Aperture 1 PCI Bridge Aperture 1 Space 1C000000 6 1C0000FF 16 PCI Bridge Registers PCI Bridge Internal resisters D000000046 D00FFFFF 46 Shared Memory Bank 1MB SRAM Table 10 Memory space map Version 2 1 Page 35 of 55 SMT310Q User Manual 10 Stand Alone Mode For the SMT310Q to operate in stand alone mode Jumper J8 Figure 17 Jumper Finder Diagram must be installed and the Auxiliary power header J1 connected The plug for power connector is AMP part N 640440 8 The connector requires wiring as shown in the pin diagram below Wire of 0 3 mm core 22 AWG should be used 1 12V 2 12V 3 5V 4 5V 5 3 3V 6 3 3V 7 GND 8 GND Figure 11 Auxiliary Power Connector Version 2 1 Page 36 of 55 SMT310Q User Manual 11 Specifications 11 1 Performance Figures The following performance figures are for the SMT310Q with the Rev A1 V PCI bridging device fitted and using a SMT335 Further performance figures will be issued as faster V PCI bridging devices become available and are fitted to the SMT310Q The figures shown below may vary greatly depending on the application Some of the issues are e PC Architecture and performance e Transfer para
33. rom a command line and will change the CPLD version number stored on the carrier board This version information is Version 2 1 Page 51 of 55 SMT310Q User Manual used by the Sundance wizard and other Sundance software to know the features of the carrier board At this point you should reboot the PC and run the SMTBoardinfo utility tool SMT6300 Place a Sundance DSP module on the first TIM site of the carrier board and run the confidence test which is part of SMTBoardinfo program If this test passes the CPLDs update has been successful 15 1 2 EPROM updating Usually the EPROM file doesn t get changed because it contains PCI interface data but without this the SMT310Q won t be detected If the EPROM becomes corrupt there is a simple way to update it The best way to change the EPROM file is to use the EPROM programming utility which is part of SMT6300 When the program starts it will show the user what type of board is being used what I O address it s at and what version the stored EPROM file is The next thing is to choose the update tab and select the prm file to be used x 1 0 Address EEPROM Ver Update SMT3100 0x1400 Ver 4 03 Ea Save Verify OK Since the EPROM holds the PCI interface data you will not be able to detect the SMT310Q if the correct EPROM is not loaded Therefore after updating the EPROM be sure to run SMTBoardinfo In the board info it should show the user what address the SMT310Q is at
34. s based on the TI 8990 device Code Composer Studio drivers are available from Sundance Part Number SMT6012 The presence of a TIM in a module site causes its SENSE pin to switch the module into the JTAG chain 3 4 Shared SRAM The Master TIM can access the SRAM over the Local Bus at transfer rates up to 100MB s The number of wait states required by the Master TIM varies depending on the speed of the module Maximum access rates use a 20ns strobe cycle 3 5 Control EPLD The EPLD acts as an on board arbitration unit that controls which device has access to the Local Bus resources Version 2 1 Page 11 of 55 SMT310Q User Manual 3 6 Onboard resources 3 6 1 SDB The on board SDB connector is accessible via the Host PCI interface It can be configured with a jumper J18 to be either an input port or an output port It is not intended as a high speed link as it only has a single 16 bit data register You can join this connector with an SDB cable to one of the SDB connectors on any TIM plugged into the board 3 6 2 Host comport link The normal means of communication between the host PC and the Master TIM on an SMT310Q is through the host comport A programmable switch selects how this comport is connected Version 2 1 Page 12 of 55 SMT310Q User Manual 4 Comports The SMT310Q gives access to all six comports on each of the four TIM sites All of these comports can be presented at an FMS connector on the rear of the carrier card
35. s bit indicates the direction set 0O Receive 1 Transmit RW General scratch bits IPFF Input FIFO full When set a 16 bit value has been latched in the data register ready for reading This bit is automatically cleared on a read from the data register OPFF Output FIFO full This bit is set when a 16 bit value is written to the FIFO and is automatically cleared when it has been sent out of the SDB The SDB data register is located at BAR2 offset 0020024016 You can write 16 bit values to this location to transfer them over the SDB interface as long as the OPFF flag in the status register is clear and the J18 jumper is present Version 2 1 Page 21 of 55 SMT310Q User Manual 6 JTAG Controller The SMT310Q has an on board Test Bus Controller TBC an SN74ACT8990 from Texas Instruments The TBC is controlled from the PCI bus giving access to the on site TIMs and any number of external TIMs Please refer to the Texas Instruments data sheet for details of this controller The TBC is accessed in I O space BAR1 offset 8046 XDS 510 XDS 510 compatible compatible JTAG in JTAG out Buffered JTAG Connector Test Bus Switching Matrix Test Bus Controller PCI bridge Figure 6 TBC Data Routing Buffers The SMT310Q can operate in two TBC modes Master mode and Slave mode In Master mode the Test Bus Controller on the SMT310Q drives the JTAG scan chain through the TIM sites on the SMT310Q If any
36. signals are NOT essential for communications Name Description RST_IN Active low board reset input pulled up to 3 3V by 100 ohms VCC 1 AMP 5 Volt supply with resetable 1 Amp fuse to power a remote buffer if required SHIELD Overall cable shield connected to plug shells and chassis Table 2 Buffered Comport Additional Signals You can synchronise resetting a number of boards by chaining them together with RST_OUT of one driving RST_IN of the next The SMT502 Buffer is the recommended cable assembly for the buffered comport and can be purchased separately 4 3 Comport to PCI Interface The comport interface is memory mapped to the PCI bridge as illustrated in Table 8 The comport uses the control and data registers to detect the state of the input and output FIFOs The following section describes the bit definitions for these registers 4 3 1 Comport Registers BAR1 Offset 1046 The host can be connected to TIM site 1 using comport 3 T1C3 This port is bi directional and will automatically switch direction to meet a request from either the host or the DSP Both input and output registers are 32 bits wide Data can only be written to COMPORT_OUT when STATUS OBF is 0 When a word is received from the DSP it is stored in COMPORT_IN and STATUS IBF is set to 1 Reading COMPORT_IN will clear STATUS IBF and allow another word to be received from the DSP Version 2 1 Page 17 of 55 SMT310Q User Manual 4 3 2 Contr
37. there are no resource conflicts See Checking for hardware resource conflicts Version 2 1 Page 8 of 55 SMT310Q User Manual Found New Hardware Wizard Welcome to the Found New Hardware Wizard This wizard helps you install software for SMT310Q 9 If your hardware came with an installation CD or floppy disk insert it now What do you want the wizard to do Q Install from a list or specific location Advanced Click Next to continue Figure 1 Hardware wizard Found New Hardware Wizard Completing the Found New Hardware Wizard The wizard has finished installing the software for Hg SMT310Q Click Finish to close the wizard lt Back l Finish i Cancel Figure 2 Hardware wizard detected the Sundance hardware Version 2 1 Page 9 of 55 SMT310Q User Manual 3 Hardware Overview Buffered External JTAG connector JTAG In Internal JTAG Out Internal HOST Se comport N 6 ports 6 ports 6 ports 6 ports oes COMPORT CONNECTION MATRIX control 8 bit 8 bit 8 bit 8 bit A ES ES CBuf FMS FMS p 4 FMS Buffered Comport Figure 3 SMT310Q Block Diagram 3 1 Local Bus The SMT310Q uses a Local Bus to control transfers amongst the various resources The bus has a 33MHz clock that is available on the CLKIN pin of the Master TIM site The TIM in this site shou
38. tor is a 2x3 2mm pin header 1S A8 Figure 16 JTAG header pin numbers Table 21 JTAG Header pin function There are 4 things you require to update the CPLDs on a SMT310Q e The Xilinx IMPACT software tool If you do not have IMPACT you need to download the software package from Xilinx called_Xilinx Webpack It is free and it includes the Xilinx IMPACT tool that will allow you to reprogram the CPLDs on the SMT310Q carrier board e The JTAG programming cable Parallel Cable IV The Parallel Cable IV can be order on Xilinx Website Version 2 1 Page 49 of 55 SMT310Q User Manual e The adaptor to connect the Parallel Cable IV to the header J21 of the SMT310Q as shown in the table above e The files needed for the update configuration files and an executable 15 1 CPLD and EPROM reprogramming It is possible for the CPLDs or EPROM s data files on the SMT310Q to become corrupt This section helps to solve such issues Users may also want to change the CPLDs code to implement their own protocol For this the use must fully understand how the JTAG connection works and what steps are needed to program the CPLD The EPROM generally only uses the code supplied by Sundance but as it can become corrupted therefore the user must have a way to update its content The files and the instructions for the update of the CPLDs are described in the Sundance support forum 15 1 1 CPLDs updating The EPLDs can be accessed through the
39. ual 7 Global Local Bus Transfers DSP lt PCI The traditional global bus interface on C6x DSP modules interfaces to the SMT310Q via a local bus This allows Global bus transfers on the DSP to be converted into local bus accesses giving direct DSP accesses to the PCI bridge chip The resources in the PCI bridge chip are illustrated in the figure below PCI Bridge Device MailBox Read Write Interrupt Control DSP Global Bus Access Local Bus Local To PCI Bus Apperture Control LOCAL lt gt PCI Apperture 0 d 16MB Address a gt Arbitration Unit Space Figure 7 Local Bus to DSP Connectivity 7 1 Mailbox Accesses The mailbox registers can be used to transfer commands or small amounts of data between the PCI bus and the DSP via the local bus The PCI bridge device provides 16 8 bit mailbox registers which may be used to communicate data between the DSP and Host The mailbox registers are accessed from the DSP through the Local to Internal Register LB_IO_BASE aperture As illustrated in section 5 table 4 of this document this region is accessed by the DSP via a global bus access to the PCI Bridge Registers Address 1C000000 6 Version 2 1 Page 24 of 55 SMT310Q User Manual The mailbox registers are on byte boundaries with offsets CO465 CF16 from LB IO BAGE As all DSP global bus accesses are carried out in aligned 4 byt
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