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EXC-1553VME-VXI/MCH: User`s Manual, Rev A

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1. by the card Note that all bits in this register ar set to 0 after assertion of VME bus line SYSRESET A24 A32 ENABLE Memory enable ROSEL2 ROSELI ROSELO reserved reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SYSFAIL INH RESET Bit_Name Description RESET Writing a 1 to this bit forces the card into the RESET state The user must not write a 0 into this bit for at least 100 usec after writing a 1 into it That is once in the RESET state the card must remain in this state for at least 100 usec While in the RESET state the card is completely inactive and will not respond to any commands Upon releasing the card from the RESET state write 0 to this bit the card will perform its self test routines The board may also be reset via the Software Reset Registers defined within the main body of this manual This second method is the preferred mechanism for resetting the card SYSFAIL This bit has no effect NHIBIT ROSEL 2 0 Writing to these bits selects which one of the VME bus Interrupt Request lines IRQ1 IRQ7 will be driven active when the card generates an interrupt Refer to section Using Interrupts on VME in following The following table shows the relationsh
2. MODID ROSEL2 ROSELI ROSELO reserved reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 iL 0 READY PASSED SYSFAIL INH RESET Note The MODID READY PASSED SYSFAIL NHIBIT and RESET functions are included to maintain compliance with the VXI specification It is recommended that VME users make use of the software reset described in the main body of this manual Bit_Name Description RESET Indicates the state of the RESET bit in the Control Register SYSFAIL Indicates the state of the SYSFAIL INHIBIT bit in the NHIBIT Control Register PASSED This bit is always set to 1 READY A 1 indicates that the power up sequence has completed and that the card is ready to accept commands This bit is a logical AND of all installed channels s READY bit ROSEL Indicates the state of the IRQSEL2 0 bits in the Control 2 0 Register MODID Indicates the inverted value of the VXI bus MODID line A24 A32 Indicates the state of the A24 A32 ENABLE bit in the ACTIVE Control Register VME VXI Interface 3 1 5Control Register VXI amp VME Writing to this E BASE 04 WR E TE ONLY 16 bit register causes the actions listed below to be executed
3. o KATI BET WOrd RE sie da a aa id 74 643 518 Time La i ROGUS TOD it eed ayaa vehi taa 74 6234 19 Initial Monitor Block Pointer Register 74 6 53 0 Initial Monitor Data Pointer Register 75 6 3 1 onitor Block Counter RegisteTl ooooooooooo o o 75 64 3 2 onttor Filter Hi REIS ES Recs a Ta ASES onitor Filter Lo REegISEEB si toi ia 75 Ou 3 LBS MONTE OL Arehite ctute i a Sy Bt is da B 76 63821 essage Information Wotd ooooooooooooooooo oo 77 6 3223 l l Message Information BitS ooooooooooo o o A 62322 COMMANG Word Sisi adn ta ss a 3 ce 78 63233 Data POINT A a Gale td ce aus a dite Sits 78 6 3 2 4 status WOC AS Lan So Go Sse saan shee 78 o AD RD A A E RAN 79 6 3 2 6 Reserved a Ss A ta 79 6 363 Monitor Block CMa AG a da 79 6 344 Memory AtEeh itb6 EUTE ila cece rca L aa ee 80 64 35 09 MESSAGE Pro ess UNG ii A e bia in 80 62356 RT Concurrent BM Opetation si iia a aaa 81 GS MIL SIDLS5SSA Operati ti iaaea ie i a Se Ge Soe ee hw ales 82 6 4 CHANNEL INTERRUPT ARCHITECTURE oooooooooooooo o 83 6 4 1 Interrupt Identification Word IIW 84 6 4 2 Interrupt Address Word IAW 38 lolis ala aw amp 84 6 43 INte rupt Log List Address i sj a B 85 B
4. Opcode Definition 15 12 0000 End Of List This opcode instructs the EXC 1553VME MCH that the end of the command block has been encountered Command processing stops and the interrupt is generated if the interrupt is enabled No command processing takes place i e no 1553 0001 Skip This opcode instructs the EXC 1553VME MCH to load the message to message timer with the value stored in the timer value location The EXC 1553VME MCH will then wait the specific time before proceeding to the next command block This opcode allows for scheduling a specific time between messag xecution No command processing takes place i e no 1553 0010 Go To This opcode instructs the EXC 1553VME MCH to go to the command block as specified in the branch address location No command process takes place i e no 1553 0011 Built in Test This opcode instructs the channel to perform an internal built in test If the channel passes the built in test then processing of the next command block will continue However if the channel fails the built in test then processing stops No command processing takes place i e no 1553 0100 Execute Block Continue This opcode instructs the EXC 1553VME MCH to xecut th current command block and proceed to the next command block This opcode allows for continuous opera
5. Note If Start B I T SBIT and Start Execution STEX are both set on one register write SBIT has prioritv Should be set to O BUAENBus A Enable Setting this bit enables Bus A operation If negated the EXC 1553VME MCH does not recognize commands received over Bus A BUBEN Bus B Enable Setting this bit enables Bus B operation If negated the EXC 1553VME MCH does not recognize commands received over Bus B PTCE Programmable Timer Clock Enable Assertion of this bit enables a programmable clock used with an internal time tag counter Refer to Programmable Timer Clock Register section described above E Note The user can only change the clock frequency source before starting the EXC 1553VME MCH i e setting STEX bit to 1 PPACK Ping Pong Acknowledge This read only bit acknowledges the Ping Pong operation The Ping Pong Enable is acknowledged by transitioning from a logical zero to a logical one while the Ping Pong Disable is acknowledged by transitioning from a logical one to a logical zero 32 Bit Name Description 8 7 RIM 1 0 Remote Terminal Mode bits These two bits determine th RT mode of operation RIM 1 0 RT Mode 0 0 Mode 0 Index or Ping Pong Operation O 1 X reserv
6. Registers Board Configuration Registers Block TEFFFE On Board PROG TIMER CLK REG 30H Memory and Registers VECTOR 7 REG 2EH gt 00000 VECTOR 0 REG 2 0H OFFSET REGISTER 06H A24 A32 ADDRESS STATUS CNTRL REGISTER 04H SPACE DEVICE TYPE REG 02H gt D REGISTER 00H A16 ADDRESS SPACE I O Logical Address Dip Switch SW1 Figure 4 Memory Registers Address Mapping Diagram A16 ADDRESSING EXAMPLE Given Required configuration registers base address E000 H Then Set dip switch SWI to LOGICAL ADDRESS 80 H OFF ON ON ON ON ON ON ON SWI l 2 3 4 5 6 i 8 VME VXI Interface 11 4 0 GENERAL MEMORY MAP The board occupies 512Kx8 of the VME A24 or A32 address mapped via the Offset Register within the VM 256K words of memory space occupied by the EXC 1553VM eight blocks of 32K words one for each channel CHANNEL 0 REGISTERS amp MEMORY 7FFFFH 70000 OFFFF LH 60000 SFFFF H A 50000 4FFFF oo 40000 3FFFF LH 30000 2FFFF ao 20000 LEFFF UA 10000 OFFFF LH 00000H E MCH Figure 5 EXC 1553VME MCH Memory Map Note In case of a partially occupied board ignore rela
7. og List as separate entities Figure 23 shows that the first block of memory is allocated for the Monitor Blocks Notice that Initial Monitor Block Pointer Register points to the initial Monitor Block location Initial Monitor Data Pointer Register points to the initial Data location Interrupt Log List Pointer Register points to the Interrupt Log and Monitor Block Counter Register contains the Monitor Block count After execution begins the EXC 1553VME MCH will build command blocks and store data words until the count reaches zero When the count reaches zero the EXC 1553VME MCH will simply wrap back to the initial values and start again Register onitor Register Data Register Interrupt Blocks Storage Log List Init Mon gt Msg Info Wd Init Mon gt Memory Int Log gt nt Info Wd Blk Ptr CMD Words Data Ptr List Ptr Monitor Block Data Ptr Sts Words Time Tag Reserved sg Info Wd CMD Words Data Ptr Sts Words Time Tag Reserved sg Info Wd CMD Words Data Ptr Sts Words Time Tag Reserved Figure 23 BM Memory Architecture 6 3 5Message Processing To process messages the Bus Monitor uses data supplied in the control registers along with RAM memory The Bus Monitor uses seven memory locations for each message Called a monitor block The following paragraphs discuss the command block end of command processing in detail The user allocates memory spaces monitor blocks can reside at any ad
8. is to monitor terminal address 12 Example 1 Bus A CMD TA 12 Bus B CMD TA 1 In this example the realiz the messag is for terminal address 12 message However as soon as the EXC 1553VM on bus B is to terminal address 1 message processing BM Mode 88 E MCH realizes th the RT will take prioritv and begin RT and RT precludes the RT has commands to the RT will alwavs The examples below describe Bus Monitor Bus Monitor will decode the first command on bus A start monitoring the second command Example 2 Bus A CMD TA 1 Bus B CMD TA 12 In example 2 the RT will decode the first command on bus A realize the message is for terminal address 1 and start message processing As the message on bus B is received the EXC 1553VME MCH will realize it is to terminal address 12 But since the RT has priority the Bus Monitor will not switch to the monitor mode The above examples also apply to an RT RT message For example if the first command in an RI RT transfer matches the terminal address of the RI the ntire message will be stored Message 1 However if the first command in an RT RT transfer matches the terminal address of the Bus Monitor and the second command matches the terminal address of the RT the RT will take priority and only the RT message is stored Message 2 Below is a
9. 10 PTCE Programmable Timer Clock Enable Assertion of this bit enables a programmable clock used with an internal counter for variable minor frame timing Refer to Programmable Timer Clock Register section described above Note The user can only change the clock frequency source before starting the EXC 1553VME MCH i e setting STEX bit to 1 9 ERTO Extended Response Time Out Assertion of this bit enables the xtended response time out option and forces the BC Mode to look for an RTs response time in 30 usec or generate time out errors Negation of this bit enables for the standard time out in 14 usec 8 5 reserved Should be set to O 4 BCEN Broadcast Enable Assertion of this bit enables the broadcast option for BC Mode Negation of this bit enables the remot terminal address 31 as a unique RT address When enabled the EXC 1553VME MCH does not expect a status word response from the remote terminal 3 reserved Should be set to O BC Mode 15 Bit Name 1 Description 2 PPENPing Pong Zero dictates that all retries will be perf A logic one al Enable This bit controls the method by which the EXC 553VME MCH will retry messages 553VME MCH to ping pong between buses during retries llows the EXC A logic formed on the programmed bus as defined in the Retry Number field
10. REGISTER BASED Note This register contains the same value whether set up for VME or VXI installation The VXI specification requires all VXI devices to identify themselves via an ID register This location is not defined under the VME specification 3 1 3Device Type Register VXI only BASE 02 READ ONLY This 16 bit register contains a fixed Device Type Identifier as well as a four bit field which reflects the Required Memory usage of the card 1 1 0 0 REQUIRED MEMORY m A32 SPACE JP33 not installed 0 1 0 0 REQUIRED MEMORY m A24 SPACE JP33 installed 15 14 13 12 11 10 9 8 7 6 5 4 3 2 l 0 MODEL CODE 553 Hex 1363 Dec Note This register contains the same value whether set up for VME or VXI installation The VXI specifications requires the user to let the system know how much memory the device requires This is known as the m value in VXI parlance This location is not defined under the VME specification VME VXI Interface 3 1 4Status Register VXI amp VME A read of this 16 bit register provides BASE 04 READ ONLY A24 A32 ACTIVE information as defined below
11. two buses the Bus B on which of the Bus A Logic 0 bit defines Logic 1 Bus A B This command was received RT RT Transfer This bit defines whether or not the message associated with this Monitor whether th This bit will be set only if t Block was an RI RT transfer and EXC 1553VME MCH saved the second command word EXC 1553VME MCH is ne instructed to monitor the Receive RT Message Information These bits define the conditions of the messag received by the EXC 1553VMI E MCH for that particular nformation bits is defined Monitor Block Each of the message 1 in the fol Llowing section 6 3 2 1 1 Message Information Bits Message information bits are provided as a means to supply more data on the message In an RT RT transfer the information applies to the complete message Each message information bit is defined below Bit Number Description 7 Message Error This bit will be set if the monitor detects an error in either the command word data words or the RT s status BM Mode 83 Bit Number Description 6 Mode Code without Data This bit will be set if the monitor detects that the command being processed is a mode code without data words 5 Broadcast This bit will be set if the monitor detects that the command being processed is a
12. Figure 24 Interrupt Ring Buffer Interrupt Architecture 92 7 0 BOARD LAYOUT LD LD LD LD LD LD LD LD LD LD 10 9 8 T 6 5 4 3 2 1 J8 JI J6 J5 J4 J3 J2 J1 JP JP JP JP JP JP JP JP 29 32 25 28 21 24 17 20 13 16 9 12 5 8 1 4 JP33 JP34 1 SW1 P2 P1 Note B size card shown Figure 25 Board Layout 8 0 LEDS The individual functions of the front panel leds are listed below MODID LD1 Reflects the state of the MODID pin on the VXI bus JP34 must be installed This LED has no function in a VME system READY LD2 Indicates that the card is ready to receive commands Reflects the state of the bit of the same name in the Configuration Status Register CH 0 LD3 Channel 0 Active Indicates that a 1553 message is processed by the channel Reflects the state of the TERACT bit in the channel 0 Operational Status Register CH 1 LD4 Channel 1 Active Indicates that a 1553 message is processed by the channel Reflects the state of the TERACT bit in the channel 1 Operational Status Register Hardware 93 CH CH CH CH CH CH 9 0 The 2 LDS 3 LD6 4 LD7 5 LD8 6 LD9 7 LD10 Channel 2 Active by the channel Reflects the state of the TERACT channel 2 Operational Status Register Channel 3 Active by the
13. A Reset Remot Terminal mode code Mode Code 01000 T R 1 clears the ncoder decoders resets the time tag nables the busses to the programmed host state and r nables the Terminal Flag for assertion This reset is performed after the transmission of the 1553 Status word RT Mode 73 MIL STD 1553A Operation exibility the 6 2 10 To maximize fl systems which the EXC To meet these protocols Table 5 defines th Register A B_ ST When bits D XMTSW configured use various protocols 1553VME MCH mav b EXC 1553VME MCH can operate in manv dif two of the protocols interfaced to Specifically are MI EXC 15 the 53VME thr Table 5 RESULT 553B response 1553A response 1553A response LAST STATUS WORI a remote te RT MI protocol selected 553B Standard 1553A Standard Auto execute the TRANSMI D mode code rminal to meet MIL ST 1553VME MCH will operate as follows responds with a status word within 7 usec ignores the T R bit for all a mode codes ar all mode codes use mode cod mode code 00000 is defined as D mode codes defined without data transmit control and information words DBC ynamic Bus Control subaddress 00000 defines a mode code ME E all other status word bits are programmable
14. Figure 12 6 1 5Message Processing To process messages registers along with data stored in memory the EXC 1553VM Log List Pointer Reg The words stored in memorv called a command block at the beginning and end of Note n Block on a retrv The user allocates memorv spaces for the minor frame blocks can reside at a the user Command Word Command Word 1 2 BC mod the th EXC T 553VMI situation control nv address location command processing ake Block Pointer Branch Address registers Register contents Command Word 2 and Timer Value complete description of each location BC Mode 29 Data Pointer Refer to the previous BC Memory Architecture List Pointer Register will Interrupt Log List t Info Wd D Block t Info Wd D Block nfo Wd Oc Block nfo Wd Od Block n CM t Info Wd D Block E MCH uses data supplied in the control EXC 1553VME MCH accesses eight The command block is accessed sections E MCH does not need to re read the Command The top of the command Defined and entered into memory by linked to the Command Each command block contains a Control Status Word 1 Block via the Status Word for a Control word information allows the EXC 1553VM
15. This register selects the programmable timers clock value for the channel timers Each channel can be individually programmed to use an internal fixed clock or to use this programmable clock see PTCE bit within channel s Control Register This clock is derived from the VME SYSCLK signal 16MHz There are two reasons to use the programmable clock First a desired timer resolution different from the fixed on 64 usec Second a request for the timers synchronization to the VME clock and or synchronization to other boards residing in the VME system Only the least significant 8 bits are used Writing a value of 0 to this register will stop the programmable timer clock The highest possible clock resolution that can be achieved is 0 25 usec 4MHz The lowest possible resolution is 32 usec 31 250KHz X X X X X X X X Timer Clock Value X don t care The formula for calculating the Timer Clock Value TCV is 16 000 000 TEV S 2 x freq Hz Example Desired Programmable Timer Clock frequency is 31 250KHz 32 usec resolution 16 000 000 TCV 1 256 1 255 Dec FFH 2 x 31250 Write OOFFH to this register VME VXI Interface 10 3 1 10 Memory Registers Address Mapping Diagram 1553 Data Storage Area and Control
16. For MIL STD 1553B applications the register is as follows Bit Name Description 15 MCLR Immediate Clear Function Assertion of this bit nables th Immediate Clear Function IMF of the EXC 1553VME MCH Enabling the IMF results in the clearing of the INS BUSY TF SRQ and or SUBF bit immediately after a message is completed This function is enabled by asserting this bit when asserting bit s NS BUSY TF SRO and or SSYSF This bit should be used consistently since once set it will remain set and once cleared it will remain cleared 14 10 reserved Should be set to O 9 INS Instrumentation Bit This bit asserts the Instrumentation bit of the MIL STD 1553B status word Bit time 10 of the Status Word 8 SRO Servic Request Bit This bit asserts the Service Request bit of the MIL STD 1553B status word Bit time 11 of the Status Word l 4 reserved Should be set to O 3 BUSX Busy Bit Assertion of this bit is reflected in the outgoing MIL STD 1553B status word Assertion of this bit prevents memorv accesses Bit time 16 of the Status Word 2 SSYSF Subsystem Flag Bit This bit asserts the Subsystem Flag bit of the MIL STD 1553B status word Bit time 17 of the Status Word
17. B 7 0 The lower 8 bits of this register are user defined Description DMA Fail Assertion of this bit indicates that all channel s internal DMA activity had not been completed within 7 usec Fail The EXC 1553VME MCH automatically compares the transmitted word encoder word to the reflected decoder word via the continuous loop back feature If the encoder word and reflected word do not match the WRAPF bit is asserts The loop back path is via the MIL STD 1553 bus transceiver Terminal Address Parity Fail This bit reflects the outcome of the remote terminal address parity check A logic one indicates a parity failure When a parity error occurs the EXC 1553VME MCH does not begin operation STEX bit forced to a logic zero and bus A and B do not enable BIT Fail Assertion of this bit indicates a B I T failure Bits 1 and 10 should be interrogated to determine the specific bus that failed 1553 status word bit time 19 Terminal Flag is automatically set to a logic one when a B I T failure occurs Bus A Fail Assertion of this bit indicates a B I T failure in Bus A Bus B Fail Assertion of this bit indicates a B l T failure in Bus B emory Test Fail Most significant memory byte failure emory Test Fail Least significant memory byte
18. NEXT COMMANI STATUS WORD NEXT COMMAND w o DATA po BROADCAST MODE DATA NEXT MODE COMMAND WORD COMMAND w DATA Note Response time Intermessag gap Figure 27 MIL STD 1553B Message Formats Appendix B 104 The information contained in this document is believed to be accurate However no responsibility is assumed by Excalibur Systems Inc for its use a E nd no license or rights are granted by implication or otherwise in connection herewith Specifications are subject to change without notice July 1996 Rev A 2 105
19. Word bits and generate interrupts or branch to a new message frame depending of course on the specific conditions which arise 6 1 2 0 BC Mode Command Block Figure 8 shows the BC s Command Block architecture while next sections describe each location associated with the Command Block Timer Value eighth location Branch Address Status Word 2 Status Word 1 Data Pointer Command Word 2 Command Word 1 second location Control Word first location Figure 8 BC Command Block Architecture BC Mode 21 6 1 2 1 Control Word The first memory location of each BC Mode Command Block contains the control word Each control word contains the opcode retry number bus definition RT RT instruction condition codes and the block access messag rror The control word is as follows 15 12 11 Opcode Bit Number is 12 il 10 I BC Mode Retrv f BUSA B RT RT Conditions Codes BAME 10 9 8 7 l 0 Description Opcode These bits define the opcode to be used by the EXC 1553VME MCH for that particular Command Block If the opcode does not perform any 1553 function all other bits are ignored Each of the available opcodes is defined in the next section Retry Number These bits define the number of retries for each individual Command Block and if a retry opcode is used If the Ping Pong Enable Bit bit 2 of
20. NTE 2 DATA PO 0 CONTROL RT Mode R NTER WORI Figure 14 RT 45 SS 03F8 H TRANSM BLOCK TRANSM BLOCK TRANSM BLOCK ESS 0300 H TRANSM BLOCK ESS 02F8 H RECEIVE BLOCK RECEIVE BLOCK RECEIVE BLOCK ESS 0200 H RECEIVE BLOCK ESS 01F8 H TRANSM BLOCK TRANSM BLOCK TRANSM BLOCK ESS 0100 H TRANSM BLOCK ESS 00F8 H RECEIVE BLOCK RECEIVE BLOCK ESS 0008 H RECEIVE BLOCK ESS 0000 H RECEIVE BLOCK MOI MOI MOI MOI SU SU SU SU Descriptor Table CO 31 CO CO 30 1 CO i CO 0 31 CO DE SO 1 DE BAI ESS BAI ESS BAI ESS 0 31 30 1 BAI ESS BAI ESS BAI ESS BAI ESS 0 31 30 1 BAI ESS 0 6 2 2 0 6 2 2 1 Descriptor Block Control Words Receive Control Word The following bits describe the receive subaddress descriptor Control word Information contained in this word assists the EXC 1553VME MCH in message processing by the Bit Name 15 8 INDX 7 INTX 6 IWA 5 BRD 4 BAC 3 reserved RT Mode The descriptor control word is initialized by the host and updated EXC 1553VME MCH during command post
21. 1 reserved Should be set to O 0 TF Terminal Flag Assertion of this bit is reflected in the outgoing MIL STD 1553B status word The EXC 1553VME MCH automatically asserts this bit if a B I T failure occurs Inhibit Terminal Flag mod cod prevents the assertion by the host Override Inhibit Terminal Flag Mode Code r stablishes the Terminal Flag option Bit time 19 of the Status Word RT Mode 39 For MIL ST Bit 15 Name MCLR D 1553A applications the register is as follows Description mmediate Clear Function Assertion of this bit nables th 14 10 reserved RT Mode SB10 Immediate Clear Function IMF of the EXC 1553VME MCH Enabling the IMF results in the clearing of the bit times 10 19 immediately after a 1553 status word is transmitted This function is enabled by asserting this bit when asserting bit times 10 19 This bit should be used consistently since once set it will remain set and once cleared it will remain cleared Should be set to O Status bit time 10 Status bit time 11 Status bit time 12 Status bit time 13 Status bit time 14 Status bit time 15 Status bit time 16 Status bit time 17 Status bit time 18 Status bit time 19 40 E 6 2 1 11 Illegalization Registers 0020 H 003E H These 16 registers are divided into 8 blocks 2 registe
22. 6 Interrupt Log List Pointer Registel o o o oooooo L 6 21 BIE Word Register a e a Rua Boe aa emo L 6 8 i or Frame Tamer REGVS dt ns A ia al a e o aa a 20 Ga ES Command Block Pointer Reglstel ooooooooooooo o 20 OZ BC ABCALE SCOUT AN e A 21 ade 2 0 BE Mode Command BIl Eekui ss pe a 21 Gel Za Control WOT Cisse Gs tee re do 22 Gs Taa Bed BE Opcode DeFINTETON ie Wide ace eee erate a E Ea 23 Oda iZ BE Condition COJE SM pi Ries Sos Sesh Sed ta da 25 GaTe 252 1553 Command WOT AS saz din a a Re ds te 25 ISS D tia BOTAS dato a a eae are ee tl oe 26 Oe 234 ar Stat US WO Sn NO NP e Ada ap erate 26 Gal 2555 Branch AddHeS 2 4 jix ei e Di gneve 26 6 1 2 6 Tamer Val Ucs iii a sie hane auu a e E if te ls Art a B alee sh te 26 6 l SCommatna Block CRAINING Li sidi dd hg eee ina 27 OL A Memory ATOCOATESO CUT A ey eye a 28 6 ol so Message POESIA A a oo 29 Ou OMbESTD 15532 Oper at VOM ei iii ni ta dee 30 TABLE OF CONTENTS OV OY OV OV OV OD OV OD OD OD OD OD OV OD OD OD OD OD OD OD OD OD OD OD OD OD OD OD OD OD OD OD OD OD OD OV OD OD OF OV 0D 0D OD OV OV OV OV OV OV OV OY OV 2 REMOTE TERMINAL MODE RT MODE 31 2 Cont
23. Br de lo sp Co en No No 6 2 3Data Structures E MCH automatically increments this data pointer during if the ping pong operation is disabled scription oadcast Data Pointer The fourth word of the scriptor block contains the broadcast data buffer cation This pointer can reside anywhere in memory ace The EXC 1553VME MCH accesses this pointer when ntrol Word bit 0 is a logic one and broadcast is abled te 1 If ping pong is enabled this pointer does not update te 2 When the broadcast command is followed by a Transmit Last Command or Last Status Word mode code the EXC 1553VME MCH transmits a status word with bit time 15 of the 1553 status word set to a logic one The broadcast bit is cleared by reception of the next valid non broadcast command The following sections discuss the data structures that result from command processing For each complete message processed the EXC 1553VME MCH generates a Message Information word and Time Tag word These words aid the host in further message processing The Message Information word contains word count message type and message error information The Time Tag word is a 16 bit word containing the command validity tim The Time Tag word data comes from the EXC 1553VME MCH s internal Time Tag counter 6 2 3 1 Subaddress Receive Data For receive commands the EXC 1553VME MCH stores data words
24. RI Mode 42 3 XX Automatically illegalized by EXC 1553VME MCH Automatically illegalized by EXC 1553VME MCH in 1553B only 5 ZZ Automatically illegalized by EXC 1553VME MCH in 1553B and 1553A if XMTSW is enabled Hs lt Ke 6 WW Automatically illegalized in 1553A 7 UU Automatically illegalized in 1553A if XMTSW enabled RT Mode 43 6 2 2Descriptor Block To process messages the EXC with data stored in the RAM descriptor block stored in RAM beginning and end of Th The command processing sequentially entered into memory to form a descriptor table 553VME MCH uses data from the control e EXC 1553VME MCH descriptor registers accesses a four word block is accessed at the Multiple descriptor blocks are The following paragraphs discuss the descriptor block in detail The host controlling the top of the descriptor table can reside at any descriptor Each descriptor block contains a Control Word Data Pointer is assigned a descriptor for receive and transmit commands registers are linked to the Register contents A Data Pointer B and Broadcast zero or one Control word buffer messages information allows the and control message processing Data List Pointer is read to determin EXC 1553VME MCH all spaces for the subaddress and mode code
25. Table 7 oodonoaao WOIDTRWNHHO AAAAANQAA NMNNNNNNNN I O U e W ay e OO C28 Connector Pl Pinout 98 DD be p p D D oorererererRRRRA 00 0 O HN ms 0100010 5V ESE RD 11 3 Connector P2 Pinout Pin Sig Name Pin Sig Name Pink Sig Name Al B1 5V C1 A2 B2 GND EZ A3 B3 C3 A4 B4 A24 C4 A5 B5 A25 CS A6 B6 A26 C6 A7 B7 A27 C7 A8 B8 A28 C8 A9 B9 A29 C9 A10 B10 A30 C10 All B11 A31 c11 A12 B12 GND ELZ A13 B13 5V C13 A14 B14 C14 A15 B15 C15 A16 B16 C16 A17 B17 C17 A18 B18 c18 A19 B19 C19 A20 B20 C20 A21 B21 c21 A22 B22 GND C22 A23 B23 623 A24 B24 C24 A25 B25 C25 A26 B26 C26 A27 B27 c27 A28 B28 C28 A29 B29 C29 A30 MODID x B30 C30 A31 B31 GND C31 A32 B32 5V 632 Table 8 Connector P2 Pinout Notes x VXI signals each of them is unconnected unless the specific jumper is shorted See Jumpers section Hardware 99 12 0 POWER REQUIREMENTS The board s maximum power supply requirements are defined below EXC 1553VME MCH with no channels installed 5V 1 0 Amps Each installed channel requires 5V B 150mA 0 duty cycle non transmitting on 1553 bus 5V 395mA 25 duty cycle transmitting on 1553 bus 5V 595mA 50 duty cycle transmitting on 1553 bus 5V B 895mA 80 duty cycle transmitting on 1553 bus 5V 895mA 100
26. A6 Switch ON or Closed logic 0 at bit position Switch OFF or OPEN logic 1 at bit position Note Address lines A15 A14 are always decoded as 1 Example for a Logical Address of CO H A16 address FOOOH set positions l and 2 to OFF or OPEN and ALL other positions to ON or CLOSED Hardware 94 9 2 Factory Default Dip Switch Settings SWI is set to Logical Address 80H 1 off 2 8 on Al6 address E000 H 10 0 JUMPERS Groups of Jumper Headers are provided on the board for various user selectable functions default board setup These headers are mounted with shorting blocks according to the see Factory Default Jumper Settings section below In high vibration environments these jumpers can be soldered or Wire Wrapped Jumpers not appearing on the Board Layout are factory set and should not be used 10 1 Channel fix 1553 Coupling Mode Select Jumpers JP1 32 Groups of four jumpers select the coupling mode to the channel fx 1553 bus The EXC 1553VMI bus E MCH can be either DIRECT or TRANSFORMER coupled to the 1553 Refer to this diagram for all 32 jumpers Q hannel hannel 00000004 hannel hannel hannel hannel hannel hannel hannel 0 1 2 3 4 5 6 7 EE 4 Er Es Short pins 2 3 for Direct Coupled mode Short pins 1 amp 2 for Transformer Coupled mode Jumper Group P4 P8 P12
27. Dia tat ui is qe Bajja ka bre ara eve ini a ea in B 76 FIGUES 227 BM MONITO Block SECrUCCUPLNG Ll iii iba see bears see ea DS ee 79 Figure 23 BM Memory Ar lhite ttite caidas eu a a aaneen ida Specs ey See area ss 80 Fi ure 245 jJnterrupt Ring Butt Sr dos lia eel eek a e a a E E 85 Ergun 20 Board La YOUE eaa E A A enS 86 Figure 26 LE STD L9039B Word Normativa a a g ee ae soe 94 Figure 27 LI SIB 1T553B Message Formats es lidia taa Seas ae dee 95 TABLES LIST Table 1 RI le alizationiRe istet BLOCKS 28 bini aa 41 Table 2 RT legalization Register Maps esis less A 42 Table 3 RT Mode 2 Control Word and MIB Pointer Structure 63 Table 4 RT Mode Code Des riptlot oid Mod Mode a eri bite an bute Bad Wahl 64 Table 5 RT MESS TD TOS IA Operat On ie a a wets 68 Table 6 CONNE SLOT IZ PINOUT S de safe etapa Soke de Daley JA Baat arch Sh S oo ads 90 Table 7 Connector TPL 4 Pr NOUE L A Dal Table 8 CONNEC OTR BL PTO Ue A a AS i ena AA a Rar aT ET SF 92 iv 1 0 The systems this n TSIMMI req INTRODUCTION TPESTA uired per xibl test The name channel applications test simulation The EXC 1553VME MCH x and the multi channel Mil Std 1553 test and EXC 1553VME MCH nanual and denotes both boards 1553 protocol controller EXC 1553VM capable EXC 1553VME MCH environment modular the nvironment wil EXC 1553VXI MCH
28. Log List Pointer indicates the starting address of the Interrupt Log List The Interrupt Log List is a 32 word ring buffer that contains information pertinent to the service of interrupts The EXC 1553VME MCH architecture requires th location of the Interrupt Log List on a 32 word boundary The most significant 11 bits of this register designate the location of the Interrupt Log List within a 64K memory space Initialize the lower five bits of this register to a logic zero The EXC 1553VME MCH controls the lower five bits to implement the ring buffer architecture This register is read to determine the location and number of interrupts within the Interrupt Log List least significant five bits Bit Name Description 15 0 ILLP 15 0 Interrupt Log List Pointer Bits Note Bits 5 5 indicate the starting Base address while bits 4 0 indicate the ring location of the Interrupt Log List 6 1 1 7 BIT Word Register 000C H Read Write This register contains information on the current health of the channel hardware The lower 8 bits of this register are user defined Bit Name Description 15 DMAF DMA Fail Assertion of this bit indicates that all channel s internal DMA activity had not been completed within 16 usec 14 WRAPFWrap Fail The EXC 1553VME MCH automatically compares the transmitted word encoder wo
29. broadcast of all mod Code 00010 Transmit Status word if enabled to illegalize a Mode Code and TF bits are defined in the 1553 status word Tes codes th receive and transmit versions illegalization of row 1F H is RT Mode user f not automatic 74 L STD 1553A Operation NO xcept Mode Code 00000 is allowed ds to illegalize both the D L STD 1553A and MI CH may be configured through Control ways to program the EXC ferent that 553B L STD 553VME MCH D 1553A EXC the BUSX mode etc BC and Mode 6 3 BUS MONITOR MODE BM MODE 6 3 1Control Registers for BM Mode The control registers are read write unless otherwise stated All control registers must be accessed in word mode high and are reset to 0 unless otherwise stated BM Mode reserved MONITOR FILTER LO RE MONITOR FILTER HI RE G G MONITOR BLOCK COUNTE R RE All control NITIAL MONITOR CMD reserved TIME TAG REG BIT WORD REG NITIAL MONITOR DATA PO NT BLK PI R REG NTERRUPT LOG LIST P PENDING INTERRUPT RE NTERRUPT MASK REG CURRENT COMMAND BLOCK RI O
30. descri locates 512 consecutive memory th 1553VME MCH stores data locations e g 0100H 0102H 0104H 0106H command the Data List Pointer is read to determin retrieved The EXC 1553VME MCH retrieves address the The Broadcast from broadcast data per MIL STD 1553B Notice EXC 1553VM ptor table see figure 14 The address location The control table via the Descriptor Address Data Pointer Each subaddress and mode code T R bit equals top of the data buffer E MCH to generat For a receive command The interrupts the EXC sequentiallv from the top of data buffer plus two ECC When processing a transmit wher data words are data words Data List Pointer designates plus two 16 bit address sequentially from the locations Data Pointer allows for separate storage of non broadcast data this feature via the Control Word s transmit commands the Broadcast does not transmit anv information command The EXC 1553VME MCH reads the descriptor on the after assertion of TERACT Data Pointers The 1607 and three EXC 1553VM The data words for either transmission or storage After transmission or reception The Descriptor Block is updated An after a descriptor update modifies the Control Word index field and bits 4 Data Pointer A
31. error condition exists The EXC 1553VME MCH can detect manchester errors sync field word count errors too many or too few MIL STD 1553 word parity errors bit count errors too many or too few and protocol errors If not masked this bit is always set and an interrupt generated when th EXC 1553VME MCH asserts bit time 9 Message Error of the 1553 status word e g illegal commands invalid data word etc 10 SUBAD Subaddress Accessed Interrupt Assertion of this bit indicates a pre selected subaddress has transacted a message To determine the exact subaddress the host interrogates the interrupt log IAW 9 BDRCV Broadcast Command Received Interrupt This bit is set to a logic one to indicate the EXC 1553VME MCH s receipt of a valid broadcast command The EXC 1553VME MCH suppresses status word transmission 8 XEQO Index Equal Zero Interrupt The EXC 1553VME MCH asserts this bit to indicate the completion of a pre defined number of commands by the RT Upon assertion of this interrupt the host updates the subaddress descriptor to prevent the potential loss of data 7 LCMD Illegal Command Interrupt This bit is set to a logic one to indicate the reception of an illegal command by the EXC 1553VME MCH Upon receipt of this command the EXC 1553VME MCH responds with a status word only Bit time 9 Message Error of the 1553 status word is set to a logic one 6 0 reserved Ignore on read 6 2 1 6 Interrupt Log List Pointer Register
32. if no message errors occurred during Reception of a broadcast command Broadcast 553VME MCH has the ping pong mode of EXC 1553VME MCH updates the message transaction errors results in the update of Pointer A or B is updated if the operation enabled RT Mode the optional least significant bit non broadcast and broadcast data is stored via Data Pointer is not used receipt of a broadcast transmit block during EXC 1553VME MCH reads the control word E MCH then begins the acquisition of The user enables or disables When disabled the Data List Pointer A or B For The EXC 1553VME MCH command processing EXC 1553VME MCH begins post processing interrupt log entrv is performed During the descriptor update the EXC 44 th EXC 1553VME MCH 1 if required The 2 and with no message Neither Data Data Pointer RELATIVE ADDRE SINGLE DESCR PTOR BLOCK 6 BRDCST DA TA PO 4 DATA PO
33. indicates the reception of a broadcast command Should be set to O Mode Code Receive Control Word The following bits describe the receive mode code descriptor Control word processing by the Note ignored Bit Name 15 8 INDX 7 INTX 6 IWA 5 BRD RT Mode Information contained in this word assists the EXC 1553VME MCH in message The descriptor control word is initialized by the host and updated EXC 1553VME MCH during command post processing n MIL STD 1553A all mode codes are without data and the T R bit is Description Index Field These bits define a multiple message buffer length The host uses this field to instruct the EXC 1553VME MCH to buffer N messages N can range from 0 00 H to 256 FF H If buffer ping ponging is enabled the INDX field is don t care i e does not contain applicable information The EXC 1553VME MCH does not perform message buffering in the ping pong mode of operation Th index decrements ach time a complete message is transacted no message errors The index does not decrement if the mode code is illegalized The EXC 1553VME MCH can generate an interrupt when the index field transitions from one to zero see bit 7 Interrupt Index Equals Zero Assertion of this bit nables the generation of an interrupt when the index field transitio
34. internally increments the CA pointer to store the receive data word s After message processing completes the EXC 1553VME MCH stores the message information word and time tag word into the circular buffer preceding the message data At the end of message processing the EXC 1553VME MCH updates CA if no errors detected For CA larger than BA storage of next message begins at the address location pointed to by the TA pointer and CA is made equal to TA If CA is less than BA CA points to the next available memory location in the buffer i e CA 1 For transmit commands the EXC 1553VME MCH begins transmission of data from memory location CA 2 Reserv th first two locations for the message information word and time tag word After message processing completes the EXC 1553VME MCH enters the message information word and time tag word into the circular buffer At the end of message processing the EXC 1553VME MCH updates CA if no errors detected For CA larger than BA storage of the next messag begins at the address location pointed to by the TA pointer and CA is made to equal TA If CA is less than BA CA points to the next available memory location in the buffer i e CA 1 Note In this mode the Message Information word bit 5 reflects the reception of broadcast message via the BRD bit The EXC 1553
35. minor frames The minimum BC intermessage gap is 28 0 usec MINOR FRAME N RETRIES CONDITIONAL FAIL BRANCH lt gt ERROR SERVICE FRAME FRAME RETURN RETURN gt lt Figure 9 BC Minor Frame Branching gt gt gt MINOR MINOR MINOR FRAME FRAME FRAME 1 2 N 100Hz 50Hz o e o f 25Hz EOL EOL EOL Figure 10 BC Minor Frame Sequencing BC Mode 2T MINOR FRAME CONDITIONAL BRANCH 1 gt SERVICE RETURN FRAME lt gt MINOR FRAME CONDITIONAL BRANCH 2 gt SERVICE FRAME RETURN lt lt MINOR FRAME CONDITIONAL BRANCH N gt SERVICE FRAME Figure 11 BC Major Frame Sequencing 6 1 4Memory Architecture After reviewing the control registers it may be advantageous to look at how the user sets up memory to configure the EXC 1553VME MCH in bus controller mode The intent of this section is to show one method for defining the memory configuration The configuration shows the Command Log List as separate entities is allocated for the Command Register initially points to the control Blocks Blocks data locations and the Interrupt Figure 12 shows that the first block of memory Notice that the Command Block Pointer word of the first Command Block After completing execution for th
36. plus two additional words The EXC 1553VME MCH adds a Receive Information word and Time Tag word to each receive command data packe Information the Receive associated with a receive com occur Time Tag word Onc considered errors the EXC t The word and Time Tag word ahead of the mand see figures 5 16 and 17 When message 1553VME MCH enters the Receive Information word and EXC 1553VME MCH places data words invalid two 16 bit locations RT Mode a messag rror condition is observed all data words are Data storage occurs at the memory location pointed to by the data pointer plus 53 6 2 3 1 1 Receive Information Info Word The following bits describe the Receive Information Word contents Bit Name Description 15 11 WC 4 0 Word Count Bits These five bits contain word count information extracted from the receive command word bit times 15 to 19 10 reserved Ignore on read 9 BUA BBus A B Assertion of this bit indicates that the message was received on bus A Conversely if this bit is set to logic zero the message was received on bus B 8 RTRT Remote Terminal to Remote Terminal Transfer The command processed was an RT to RT transfer q ME Message Error Assertion of this bit indicates a message error condition was observed during processing See bits O to 4 for det
37. ponging is not enabled Broadcast Received Assertion of this bit indicates the reception of a valid broadcast command Notice Asserting this bit nables the us of the Broadcast Data Pointer as a buffer for broadcast command information When negated broadcast information is stored in the same buffer as non broadcast information 6 2 2 4 Mode Code Transmit Control Word The following bits describe the transmit mode code descriptor Control word processing Information contained in this word assists the EXC 1553VME MCH in message The descriptor control word is initialized by the user and updated by the EXC 1553VME MCH during command post processing Note nM ignored Bit Name 15 7 reserved 6 IWA 5 BRD RT Mode L STD 1553A all mode codes are without data and the T R bit is Description Should be set to O Interrupt When Accessed Assertion of this bit enables the generation of an interrupt when a mode code command is received The interrupt is entered into the Pending Interrupt Register if not masked in the Mask Register An interrupt is generated after message processing Interrupt Broadcast Received Assertion of this bit nables the generation of an interrupt when a broadcast mode code is received The interrupt is entered into the Pending Interrupt Re
38. processing Description Index Field These bits define multiple message buffer length The host uses this field to instruct the EXC 1553VME MCH to buffer N messages N can range from 0 00 H to 256 FF H If buffer ping ponging is enabled the INDX field is don t care i e does not contain applicable information During ping pong mode operation initialize the index field to 00 H The RT does not perform multiple message buffering in the ping pong mode of operation The index decrements each time a complete message is transacted no message errors The index does not decrement if the subaddress is illegalized The EXC 1553VME MCH can generate an interrupt when the index field transitions from one to zero see bit 7 Interrupt Index Equals Zero Assertion of this bit nables the generation of an interrupt when the index ield transitions from one to zero The interrupt is entered into the Pending Interrupt Register if not masked in the Mask Register An interrupt is generated after message processing F Interrupt When Accessed Assertion of this bit enables the generation of an interrupt when the subaddress receives a valid command The interrupt is entered into the Pending Interrupt Register if not masked in the Mask Register An interrupt is generated after messag processing Interrupt Broadcast Recei
39. read LL MERR Message Error Interrupt Assertion of this bit indicates the occurrence of a message error The EXC 1553VME MCH can detect Manchester sync field word count 1553 word parity bit count and protocol errors This bit will be set and an interrupt generated if not masked after message processing is complete 10 6 reserved Ignore on read 5 EOL End Of List Interrupt Assertion of this bit indicates that the EXC 1553VME MCH is at the end of the command block 4 ILLCMD llogical Command Interrupt Assertion of this bit indicates that an illogical command Lo y Transmit Broadcast or improperly formatted RT RT message has been written into the Command Block The EXC 1553VME MCH checks for RI RT Terminal address field match RT RT transmit receive bit mismatch and correct order and broadcast transmit commands If illogical commands occur the EXC 1553VME MCH will halt execution 3 LLOP Illogical Opcode Interrupt Assertion of this bit indicates an illogical opcode i e any reserved opcode was used in the command block The EXC 1553VME MCH halts operation if this condition occurs 2 RTF Retry Fail Interrupt Assertion of this bit indicates all programmed retries failed 1 CBA Command Block Accessed Interrupt Assertion of this bit indicates a command block was accessed Opcode 1010 if enabled 0 reserved Ignore on read BC Mode 18 6 1 1 6 Interrupt Log List Pointer Register 000A H Read Write The Interrupt
40. the Control Register is not enabled all retries will occur on the programmed bus However if bit 2 is enabled the first retry will always occur on the alternate bus the second retry will occur on the primary bus the third retry will occur on the alternate bus and the fourth retry will occur on the primary bus BIT 11 BIT 10 of Retries 0 1 1 0 2 1 1 3 0 0 4 Bus A B This bit defines on which of the two buses the command will be transmitted i e primary bus Logic 1 Bus A Logic 0 Bus B RI RT Transfer This bit defines whether or not the present Command Block is an RI RT transfer and if the EXC 1553VME MCH should transmit the second command word Data associated with an RT RT is always stored by the EXC 1553VME MCH Condition Codes These bits define the condition code the EXC 1553VME MCH uses for that particular Command Block Each of the available condition codes ar defined in the following sections Block Access Message Error Assertion of this bit indicates a protocol message error occurred in the RT s response For this occurrence the EXC 1553VME MCH will overwrite this bit prior to storing the Control Word into memory Noise on the 1553 bus may be one example of such an error 22 6 1 2 1 1 BC Opcode Definition
41. the generation of the Full Emptv interrupt Figure 19 describes the relationship between TA CA and MIB RT Mode 64 Control Word Bits 15 8 FF TE 3F 1F OF 07 03 01 Figure 19 RT Mode Data Circular Buffer MIB CA TA B Length RT Mode 2 8 7 Descriptor Descriptor 65 Length of MIB Pointer Structure MIB Base and CAF messages 128 8 Bit Base Address 8 Bit Current Address Field 64 9 Bit Base Address 7 Bit Current Address Field 32 O Bit Base Address 6 Bit Current Address Field 16 1 Bit Base Address 5 Bit Current Address Field 8 2 Bit Base Address 4 Bit Current Address Field 4 3 Bit Base Address 43 Bit Current Address Field 2 4 Bit Base Address 42 Bit Current Address Field 1 5 Bit Base Address 1 Bit Current Address Field Table 3 RT Mode 2 Control Word and MIB Pointer Structure Time Tag Message Info Word Time Tag Message Info Word lt Information Buffer Message Circular CONTROL WORD Block Block and Circular Buffers 6 2 5Mode Code and Subaddress The EXC 1553VM MIL STD 155 internal il 4 shows the T R I RT Mode E MCH provides subaddress and mode 3B requirements In addition the EXC 1553VME MCH h
42. to the top of this memory space The EXC 1553VME MCH uses the T R bit subaddress mod cod field and mode code to select one block within the descriptor table for message processing The RT Descriptor Pointer Register is static during message processing Bit Name Description 15 0 RTDA 15 0 RT Descriptor Address Bits 6 2 1 10 1553 Status Word Bits Register 0012 H Read Write This register controls the outgoing MIL STD 1553 status word The host controls the Instrumentation Busy Terminal Flag Servic Request and Subsystem Flag by writing to bits 9 through 0 of this register The EXC 1553VME MCH s status word response reflects assertion of these bit s until negated by the host unless th Immediat Clear Function is enabled The Immediat Clear Function automatically clears these bits after being transmitted in a status word The Immediate Clear Function does not affect the operation of the Transmit Last Status word and Transmit Last Command word Mode Codes Transaction of a legal valid command with the INS bit set to a logic one and the Immediat Clear Function enabled results in the transmission of a 1553 status word with Bit time 10 asserted If the ensuing command is a Transmit Last Status word or Last Command mode code Bit time 10 of the outgoing 1553 status word remains a logic one RT Mode 38
43. user defined Bit Name Description 15 DMAF DMA Fail This bit is set if all channel s internal DMA activity had not been completed within 7 usec 14 13 reserved Should be set to O 12 BITE BIT Fail Assertion of this bit indicates a B I T failure Interrogate bits 11 and 10 to determin th specific bus that failed 11 BUAF Bus A Fail Assertion of this bit indicates a B I T failure in Bus A 10 BUBE Bus B Fail Assertion of this bit indicates a B I T failure in Bus B 9 SBF emory Test Fail Most significant memory byte failure 8 LSBF emory Test Fail Least significant memory byte failure 7 0 UDB 7 0 User Defined Bits 6 3 1 8 Time Tag Register OOOE H READ ONLY This register reflects the state of a 16 bit free running ring counter in the RT and BM modes This counter will remain a free running counter as long as the channel is not in a reset mode This counter may be driven by the Programmable Timer Clock see PTCE bit within Control Register If not driven by the Programmable Timer Clock this counter is clocked by a fixed 15 625 KHz 64 usec clock The Time Tag counter begins operation immediately after reset or within 64 usec Bit Name Description 15 0 TT 15 01 Time Tag Counter Bit
44. x family of products provide a simulation environment on VME and VXI l be used as a generic name throughout Based on the latest ASIC technology UTMC which substantially reduces the area in a E MCH provides a very powerful and most sophisticated tO design the providing complete F the user while handling nables the manner flexibility in choosing the data processing power required The EXC 1553VME MCH provides Bus Controller Remot Terminal Bus Monitor Remote Terminal Concurrent Bus Monitor operation on each channel enabling Concurrent operation on multiple independant Mil Std 1553 dual redundant buses As card operation is set by parameters stored in Ram test setups may be altered in real time as dictated by the application For harsh environments in flight applications the EXC 1553VME MCH is available in a ruggedized extended temperature 40 to 85 C version See Ordering Information for specifying available options 1 VME BUS 5 J1 lt gt XFRMR A lt gt CH 0 9 lt gt XFRMR B lt gt ASIC MODULE 3 C J2 lt gt XFRMR A lt gt CH 1 O lt gt XFRMR B lt gt ASIC MODULE N lt ADDR N VME E lt gt NTER lt gt DATA FACE T lt gt CTRL O J8 lt gt XFRMR A lt gt CH 7 N lt gt X
45. 000A H Read Write The Interrupt Log List Pointer indicates the starting address of the Interrupt Log List The Interrupt Log List is a 32 word ring buffer that contains information pertinent to the service of interrupts The EXC 1553VME MCH architecture requires th location of the Interrupt Log List on a 32 word boundary The most significant 11 bits of this register designate the location of the Interrupt Log List within a 64K memorv space The lower 5 bits of this register should be initialized to a logic zero The EXC 1553VME MCH controls the lower 5 bits to implement the ring buffer architecture This register is read to determine the location and number of interrupts within the Interrupt Log List least significant 5 bits RT Mode 36 Bit 15 0 6 2 1 7 Name Description ILLP 15 0 Interrupt Log List Pointer Bits Note Bits 5 5 indicate the starting Base address while bits 4 0 indicate the ring location of the Interrupt Log List BIT Word Register 000C H Read Write This register contains information on the channel s hardware current health The RT transmits the contents of this register upon reception of a Transmit Bit 15 14 13 12 RT Mode BIT Word Mode Cod WRAPF Wrap Name DMAF TAPF TE BUAF BU BE LS BF
46. 1553A Operation The F EXC 1553VME MCH may be configured to meet the MIL STD 1553A protocol When configured as a MIL STD 1553A bus controller the EXC 1553VME MCH will operate as follows Looks for the RT response within 9 usec Defines all mode codes without data Defines subaddress 00000 as a mode code A B_STD ERTO RESULT 0 0 553B standard 1553B response in 14 usec 0 1 553B standard extended response in 30 usec 0 1553A standard 1553A response in 9 usec 1 1553A standard extended response in 21 usec BC_Mode 30 6 2 REMOTE TERMINAL MODE RT MODE 6 2 1Control Registers for RT Mode The control registers are registers must be accessed in word mode 0 unless otherwise stated high and are reset to RT Mode read write unless otherwise stated All control All control I Ey EGALIZATION R EGIST ERS 1553 STATUS WORD 16 registers reserved RT DESCRIPTOR PO NTER TIME BIT WORD REG TAG REGISTER INT LOG LIST POINTER REG PENDING INTERRUP NT T RRUPT MASK RI CURRENT COMMAND T REG EG E OPERAT ONAL STAT CONTROL REGISTER Figure 13 RT Control R
47. 8 O ROAK FEATURES PER CHANNEL OPERATES AS BC RT BM s BC MODE RT CONCURRENT BM MAJOR MINOR FRAMES PROGRAMMABLE INTERMESSAGE GAP MULTIPLE PROTOCOL CAPABILITY AUTOMATIC RETRY MIL STD 1553A MIL STD 1553B e RT MODE AUTONOMOUS OPERATION IN ALL SINGLE RT SIMULATION MODES SUBADDRESS DOUBLE BUFFERING CIRCULAR BUFFER MODE 32K WORD MEMORV MAPPED RAM MESSAGE ILLEGALIZATION 16 BIT TIME TAG 32 CONTROL REGISTERS PROGRAMMABLE BROADCAST MODE POLLING OR INTERRUPT DRIVEN BM MODE 16 BIT TIME TAG REAL TIME OPERATION FILTERING PER RI INTERRUPT HISTORY LIST BUILT IN TEST CAPABILITY PROGRAMMABLE MONITOR BLOCK COUNT The EXC 1553VME MCH x a Std 1553 interface cards for VME and VXI svstems Each channel is Dual Redundant and supports Bus Controller Remot nd EXC 1553VXI MCH x are multi channel up to 8 LES both 1553A and 1553B protocols Each channel provides Bus onitor operation Terminal Bus Monitor and Remote Terminal Concurrent The user controls the operation of each channel by accessing dedicated memory mapped control registers and 32Kx16 RAM TABLE OF CONTENTS INTRODUCTION 2 ia i aa ti A ltd
48. E MCH to control the commands transmitted over the 1553 bus The Control word allows the EXC 1553VME MCH to transmit commands on a specific bus perform retries initiate RT RT transi word first spec al E fers and interrupt on certain conditions The host defines each command associated with each command block For normal 1553 commands only the command word location will contain valid data For RI RT commands as fied in the Control word the host must define the first command word as a receive and the second command word as a transmit For a receive command the Data Pointer is read to determine where data words are retrieved The EXC 1553VME MCH retrieves data words sequentiallv from the address specified by the Data Pointer For a transmit command the Data Pointer is read to determine the top memory location The EXC 1553VME MCH stores data words sequentiallv from this top memory location The EXC 1553VME MCH reads the command block during minor frame processing The EXC 1553VME MCH then begins the acquisition of data words for either transmission or storage After transmission or reception the EXC 1553VME MCH begins post processing The command block is updated The EXC 1553VME MCH modifies the Control word as required An optional interrupt log entry is performed after the command block update 6 1 6MIL STD
49. EG US RE register bits are active 003E H 0020 H 001E H 0014 H 0012 H 0010 H OOOE H 000 H 000A H 0008 H 0006 H 0004 H 0002 H 0000 H Registers Map 31 6 2 1 0 6 2 1 1 The Control Bit 15 14 11 10 RT Mode Description of RT Mode Control Registers Control Register 0000 H Read Write Name STEX reserved Register controls RT Mode configuration To make changes to the RT Mode and this register the STEX bit Bit 15 must be logic zero Description Start Channel Execution Assertion of this bit initiates operation of the EXC 1553VME MCH channel A Control Register write negating this bit inhibits channel operation A remote terminal address parity error prevents RT Mode operation regardless of the logical state of this bit If an RT address paritv error exists bit 3 of the Operational Status Register will be set low and bit 2 of the Operational Status Register will be set high Start Channel B I T Assertion of this bit places the channel into the Built In Test routine The BIT test takes 1 ms to execute and has a fault coverage of 93 4 If the channel has been started the host must halt the channel in order to place the channel into the Built In Test routine STEX 0
50. EXC 1553VME MCH EXC 1553VXI MCH User s Manual Zp XALI EXCALIBUR SYSTEMS 311 Meacham Avenue Elmont NY 11003 Tel 516 327 0000 Fax 516 327 4645 e mail excalibur mil 1553 com website www mil 1553 com EXC 1553VME MCH x EXC 1553VXI MCH x MULTI CHANNEL MIL STD 1553 TEST AND SIMULATION BOARDS GENERAL FEATURES UP TO 8 MIL STD 1553 FOR VME AND VXI SYSTEMS DUAL REDUNDANT CHANNEL NDEPENDENT e COMPATIBLE WITH VME amp VXI SYSTEMS S c B AND C SIZE CARDS EASY TO INSTALL AND OPERATE 16 BIT DATA TRANSFERS c SOFTWARE LIBRARY INCLUDED e SINGLE SUPPLY 5V OPERATION RUGGEDIZED EXTENDED TEMPERATURE RANGE AVAILABLE VME VXI COMPLIANCE SLAVE ADDRESS A16 A24 A32 DATA D16 NTERRUPT DO
51. FRMR B lt gt ASIC MODULE S Figure 1 EXC 1553VME MCH x Block Diagram 2 0 INSTALLATION amp CONNECTIONS Before installing the card it is very important to determine which 64 byte section of Al6 address space is available for the cards VME VXI Configuration Registers When this is determined the SWI dipswitch should be set accordinglv see Dip Switch Settings section The user should also decide if A24 or A32 address space is to be used and set the appropriate jumper JP33 see Jumpers section 1553 devices may be connected to the 1553 bus either directly Direct Coupled or via a bus coupling stub Transformer Coupled Jumpers JP1 to JP32 must be set to inform the card which coupling method is being used for each bus the card is connected to see Jumpers section 2 1 1553 Bus Connections For short distances direct coupling may be used to connect the EXC 1553VME MCH directly to another 1553 device The user must make certain that the cable connecting the two devices is properly terminated with 78 ohm resistors to insure data integrity Figure 2a shows how two 1553 devices may be connected in Direct mode Hi EXC 1553VME MCH Termination Resistors 1553 Device Direct Coupled 78 ohm Direct Coupled Lo Figure 2a Direct Coupled Connection One Bus Shown For users wishing to operate in the more standard Transformer Coupling mode stub cou
52. OARD LAYOUT peed ono e ae Set ese Sew area a e a 86 LEDS pi ir too 86 DIP SWITCH SETTINGS enanas co eee eee sica sia ye e a aa 87 9 1 Card Logical Address Dip Switch Setting 87 9 2 Factory Default Dip Switch SettinQS ooooooooooooooooo 88 JUMPERS sign cio ete pl as a ad OS a l ite a ad 88 10 1 Channel x 1553 Coupling Mode Select Jumpers JP1 32 88 0 2 VME Address Space Select Jumper JP33 ooooooooooo 88 10 3 VXI MODID Connect Jumper JP34 se ee aeae be el es eee ew ee eee 89 1004 Factory Default Jumper SSPEINGS 6 wie init a ae Oo eared ee a 89 CONNECTORS op e a a E E EE A E E E N E E E E AE a aa 90 Le CONNECE OR JX PINOUT AA je A AS y AAA na 90 g2 Connector PI Pa NOU yen Ses Sie erste E g a a a 91 3 Connector P2 Pa OUT A gia ered sere a ve Neen Eee taa Bie whee sel 92 POWER REQUIREMENTS oo ooooooo ee eet eee eee eee 93 ORDERING INFORMATION 00 cece ence eee ee eee eee oonooao 93 APPEND TE XESS cui a dl a ds 94 A MEE STD 15909B Word Formats e einean A A A SI Wola d 94 B MIL SID 1553B Message Formats sceo d e e Laa ee 95 E FIGURES LIST Figure 1 EXC 1553VME MCH x Block DiaglaM o
53. ODE WORD MESSAGE ERROR INSTRUMENTATION SERVICE REQUEST BROADCADST COMMAND RCV D BUSY SUBSYSTEM FLAG DYNAMIC BUS CONTROL ACCEPTANCE TERMINAL FLAG Note T R transmit receive MODCOD mode cod P paritv Figure 26 MIL STD 1553B Word Formats Appendix A 102 APPENDIX B MIL STD 1553B MESSAGE FORMATS BC to RT RT to BC RT to RT NEXT COMMAND MODE w o DATA MODE w DATA TRANSMT MODE w DATA RECEIVE BROADCAST BC to RTs BROADCAST RT to RTs BROADCAST MODE Appendix RECEIVE DATA DATA DATA STATUS COMMAND WORD WORD WORD WORD TRANSMIT STATUS DATA DATA e e DATA COMMAND WORD WORD WORD WORD RECEIVE TRANSMIT STATUS DATA DATA DATA COMMAND COMMAND WORD WORD WORD WORD MODE STATUS NEXT COMMAND WORD COMMAND MODE STATUS DATA NEXT COMMAND WORD WORD COMMAND MODE DATA STATUS NEXT COMMAND WORD WORD COMMAND RECEIVE DATA DATA e DATA f NEXT COMMAND WORD WORD WORD COMMAND RECEIVE TRANSMIT STATUS DATA DATA DATA COMMAND COMMAND WORD WORD WORD WORD SSS MODE NEXT COMMAND COMMAND 103 CO
54. P16 G P20 P24 P28 P32 10 2 VME Address Space Select Jumper JP33 This jumper selects the VME Address Space that the board s memory will be located at Jumper shorted Jumper open Hardware A24 address space A32 address space 9 5 10 3 VXI MODID Connect Jumper JP34 This jumper connects the card to the VXI MODID signal located at P2 A30 Jumper shorted MODID connected ready for VXI environment Jumper open MODID disconnected pin P2 A30 free for VME user defined 10 4 Factory Default Jumper Settings my The factory jumpers setup for VME is as follows JPl JP32 set to Transformer Coupled mode pins 1 amp 2 Shorted JP33 set to A24 Address Space Shorted JP34 set to MODID disconnected Open The factorv jumpers setup for VXI is as follows JPl JP32 set to Transformer Coupled mode pins 1 amp 2 Shorted JP33 set to A24 Address Space Shorted JP34 set to MODID connected Shorted Hardware 96 11 0 CONNECTORS The EXC 1553VME MCH contains ten connectors a eight 6 pin Molex micro fit connectors J1 to J8 one per channel b two DIN type 96 pin VME VXI connectors P1 and P2 11 1 Connector Jx Pinout These 6 pin MOLEX 43045 0600 connectors contain all signals relevant to a specific channel Mating connectors 43025 0600 with crimp terminals 43030 are include
55. PERATIONAL STATUS RI CONTROL REGISTER Figure 20 BM Control O NT ER RE 75 register bits are active 003E H 0020 H 001E H 001C H 001A H 0018 H 0016 H 0014 H 0010 H OOOE H 000 H 000A H 0008 H 0006 H 0004 H 0002 H 0000 H Registers Map 6 3 1 0 Description of BM Mode Control Registers 6 3 1 1 Control Register 0000 H Read Write To operate the EXC 1553VME MCH as a bus monitor use the following bits To make changes to the Bus Monitor and to this register the STEX bit Bit 15 must be logic zero Note The user has 5 usec after TERACT OPERATIONAL STATUS REGISTER bit 0 active to stop execution Bit Name Description 15 STEX Start Execution Assertion of this bit commences operation of the EXC 1553VME MCH A Control Register write negating this bit inhibits operation of the EXC 1553VME MCH After execution has begun a write of a logic Zero will halt the EXC 1553VME MCH after completing the current 1553 message 14 SBIT Start B I T Assertion of this bit places the channel into the Built In Test routine The BIT test takes 1 ms to execute and has a 93 4 fault coverage If the chann
56. REG 0004 H OPERATIONAL STATUS REG 0002 H CONTROL REGISTER 0000 H Figure 7 BC Control Registers Map I BC Mode 14 6 1 1 0 Description Of BC Mode Control Registers 6 1 1 1 Control Register 0000 H Read Write The Control Register s function is to configure the EXC 1553VME MCH for operation To make changes to the BC and this register the STEX bit Bit 15 must be logic zero To operate the EXC 1553VME MCH as a bus controller use the following bits Bit Name Description 15 STEX Start Channel Execution Assertion of this bit commences operation of the EXC 1553VME MCH channel A Control Register write negating this bit inhibits operation of the channel After execution begins a write of logic zero will halt the EXC 1553VME MCH channel after completing the current 1553 message 14 SBIT Start Channel B I T Assertion of this bit places the channel into the Built In Test routine The BIT test takes 1 ms to execute and has a fault coverage of 93 4 Once the channel has been started the host must halt the channel in order to place the channel into the Built In Test routine STEX 0 Note If Start BIT SBIT and Start Execution STEX are both set on one register write BIT has prioritv 13 11 reserved Should be set to O
57. VME MCH generates a circular buffer empty full interrupt when the buffer reaches th nd i e CA greater than BA and begins a new message at the top of the buffer Bit 8 of the Mask Register and bit 7 of the Descriptor Control Word mask enables the generation of the Full Empty interrupt Figure 18 describes the relationship between TA BA and CA RT Mode 61 RT Mode Figure 18 gt RT Mode fl Time Tag Data Words Message Info Word CIRCULAR BUFFE Time Tag Data Words Message Info Word BA CA TA CONTROL WO Descriptor Descriptor B 62 lock ock and Circular Buffer 6 2 4 2 Mode 2 Operation In this mode the EXC 1553VME MCH separates messag data and message information into unique circular buffers The separation of data from message information simplifies the software that loads and unloads data from the buffers The message information buffer contains Time Tag and Mesage Information words for each message trasnacted on the bus while the data buffer contains the message data words Both buffers wrap around after processing a pre determined number of messages 6 2 4 2 1 Mode 2 Descriptor Block Each subaddress and mode code both trasmit and receive has a unique pair of circular buffers The EXC 1553VME MCH decodes the command word T R bit subaddres
58. a S41 Share a Bs ji INSTALLATION CONNECTIONS ooooocoooooocoocnooooocoo oo ooo 2 Zo 1003 BUS CONMECELON Si A neater a aan VME VXI INTERFACE ree ie a aa a a Be 3 3 VME VXE Configuration Register Size lala a 3 1 1 Configuration Register Memory MaP ooooooooooo oo 4 Sea 2 ED PREG ASST ia ts la A ds a is ia S 5 33 La Device TYPE REGi Ste e menena A o a ts 5 Sisa Status Register ri erete i i a Ea a aa 6 8 6 CONDE OW REGUS et i 5 55 b AS A A a a aan s 7 Bal G USING TAESECUPES on MM A A er sa 8 SL OBESCE REG SETI A A aang Set We 9 3 LAS WeECEOREN Reg Usera A e a ba LO 3 1 9Programmable Timer Clock Register LO did LO Memory Registers Address Mapping Diagram TI GENERAL MEMORY MAP oere rreka ia a tos a ale da ate ale 2 CHANNEL GENERAL OPERATION oooooooooooooooonononocoooo ee eee el 13 Soi Channel Reset Register iia a as aie A 13 OPERATIONAL MODES oooooococcococooooooooo ooo a l L4 6 1 BUS CONTROLLER MODE BC MODE o o oooocoococoooooo oo 14 6 Control Registers for BC Models snesena eme aa 14 6 0 Description of BC Mode Control Registers 1 L 6 lt Control REgLStO E sic sd aaa de ai Sel case L 6 IL Operational Status RegisStel oooooooooooooooooo L 6 3 Current Command Registe esea Ce ea EE al L 6 4 Interrupt Mask Reglistel ooooooooooooooooooooooo L 6 20 Pending Interrupt Registel ooooooooooooooooooo L 6
59. a in the transfer 6 3 2 4 Status Words The next two locations in the Monitor Block are for status words As the RT responds to the BC s command the corresponding status word will be stored in Status Word 1 However in an RI RT transfer the first status word will be the status of the Transmitting RT while the second status word will be the status of the Receiving RT BM Mode 84 6 3 2 5 Time Tag The seventh location in the Monitor Block is the time tag associated with the message The time tag is stored into this location at the end of message processing i e captured after the command is validated 6 3 2 6 Reserved The last location in the Monitor Block is reserved 6 3 3Monitor Block Chaining The host determines the first Monitor Block bv setting the start address in the Initial Monitor Block Pointer Register Figure 22 shows the Monitor Block as the blocks execute in a contiguous fashion lt Monitor gt Monitor Block Block 1 4 gt Monitor gt Monitor Block Block 2 5 gt Monitor gt Monitor Block Block 3 6 Figure 22 BM Monitor Block Structuring BM Mode 85 6 3 4Memory Architecture The configuration shows the Monitor Blocks and the data locations Interrupt
60. ace i e no 1553 Return to Branch This opcode instructs the EXC 1553VME MCH to return to the command block address saved during a Branch opcode No command processing takes place i e no 1553 Note For retries with interrupts enabled all interrupts are logged after message processing is complete BC Mode 24 6 1 2 1 2 BC Condition Codes Condition codes have been provided as a means for the EXC 1553VME MCH to perform certain functions based on the RT s status word In an RT RT transfer the conditions apply to both of the status words Each bit of the condition codes is defined below Bit Number 7 6 1 2 2 Description Message Error This condition will be met if the EXC 553VME MCH detects an error in the RT s response or if it detects no response The EXC 1553VME MCH will wait 15 usec in 553B mode and 11 usec in 1553A mode before declaring an RT no response Status Word Response with the Message Error bit set Bit time 9 in 1553A mode This condition is met if the EXC 1553VME MCH detects that the RT s status word has the Message Error bit set Status 1553A Word Response with the Busy bit set Bit time 16 in mode This condition is met if the EXC 1553VME MCH detects that the RT s status word has the Busv bit set Status 19 in 553VMI Word Response with the Te
61. ails 6 5 reserved Ignore on read 4 ILL Illegal Command Received Assertion of this bit indicates the command received was an illegal command 3 TO Time 0ut Error Assertion of this bit indicates the EXC 1553VME MCH did not receive the proper number of data words i e the number of data words received was less than the word count specified in the command word 2 OVR Overrun Error Assertion of this bit indicates the EXC 1553VME MCH received a word when none was expected or the number of data words received was greater then expected 1 PRTY Parity Error Assertion of this bit indicates the EXC 1553VME MCH observed a parity error in the incoming data words 0 MAN anchester Error Assertion of this bit indicates the EXC 1553VME MCH observed a Manchester error in the incoming data words RT Mode 56 6 2 3 2 The user is words Subaddress Transmit Data into memorv and establishing the applicable data pointer responsible for organization of the data packet i e M data The user allocates two memorv locations at the top of the data packet for the storage e of the Transmit Information word and Time Tag word An example transmit data structure for three words is shown below Data Pointer A gt equals 0100 H 0202 00200 H XXXX reserved for Transmit Info word H XXXX reserved for Time Tag
62. as automatic legal command decoding for reserved MIL STI EXC 1553VME MCH s response to all possibl code decoding that meets D 1553B mode codes Table mode code combinations Table 4 RT Mode Code Description Mode Code Function 00000 01111 Undefined w o data 10000 Undefined with data 10001 Synchronize with data 10010 Undefined 10011 Undefined 10100 Selected Transmitter 66 Operation 1 Command word stored 2 Status word transmitted 1 Command word stored 2 Data word stored 3 Status word transmitted 1 Command Word stored 2 Data word stored 3 Time Tag counter loaded with data word value 4 Status word transmitted 1 Command word stored 2 Data word stored 3 Status word transmitted 1 Command word stored 2 Data word stored 3 Status word transmitted 1 Command word stored 0 10101 0 10110 11111 1 00000 bit word Control 1 00001 to ili 00010 transmitted after updates RT Mode Shutdown Override Selected Transmitted Shutdown Reserved Dvnamic Bus Control Svnchronize Transmit Status Word 67 ls Data word stored Status word transmitted Command word stored Data word stored Status word transmitted Command word stored Data word stored Status word transmitted Command word stored Dynamic Bus Acceptance set in outgoing status if enabled in the Register Status word transmitted Command word st
63. at first Command Block the Command Block Pointer Register will next Command Following the Command Block locations words In BC applications Block known In figure 12 for example automatically be updated to show the address is the memory required for all the number of data words for each Command the first Command Block has with the the data Block is allocated several memory locations for expected data Conversely the second Command words associated with efficiently BC Mode each Command 28 Block has only allocated a few memory locations Since the number of data Block is known memory may be used Also shown as a separate memory area is the description Pointer Register points to the top of the of the Interrupt Log List that first BC Command Block automatically be updated Register Command Command Blocks gt CTL Word gt the initial Interrupt Data Storage Memory Log Register Interrupt Interrupt Log List Notice that the Interrupt refer to the Log List Log List After execution of Block Pointer Reg CMD Words Data Ptr Sts Words Brnch Add sg Timer CTL Word CMD Words Data Ptr Sts Words Brnch Add sg Timer CTL Word CMD Words Data Ptr Sts Words Brnch Add sg Timer
64. broadcast message 4 Reserved 3 Time out Error This bit will be set if the BM did not receive the proper number of data words e g the number of data words received was less than the word count specified in the command word 2 Overrun Error This bit will be set if the BM received a word when none wer xpected or the number of data words received was greater than expected 1 Parity Error This bit will be set if a parity error has occurred on one of the message words 0 Manchester Error This bit will be set if a Manchester error has occurred on one of the data words 6 3 2 2 Command Words The next two locations in the EXC 1553VME MCH Monitor Block are for command words In non RT RT 1553 messages only the first command word will be stored However in an RT RT transfer the first command word is the Receive Command and the second command word is the Transmit Command 6 3 2 3 Data Pointer The fourth location in the Monitor Block is the data pointer This pointer points to the first memory location to store the data words associated with the message for this block Note that the data associated with each individual message will be stored contiguously This data structure allows the EXC 1553VME MCH to store the specified number of data words Note In an RT RT transfer the Bus Monitor uses the data pointer as the location in memory to store the transmitting dat
65. ccessing Data Storage Area and Control Registers XX XXXX H A24 mode with ADDRESS MODIFIER CODES 39 or XXXX XXXX H A32 mode with ADDRESS MODIFIER CODES 09 The memory map is divided into two distinct blocks 1 VME VXI Configuration Registers 2 1553 Message Storage Area and Control Registers F 2D 3A OA 3 01 that all accesses accesses will be form The VME VXI Configuration Registers are used for setting up the board within the user s VME or VXI system The 1553 Message Storage Area and Control Registers are used to control the operation of the board on the 1553 bus Interface VME VXI 3 1 VME VXI Configuration Registers The VME VXI Configuration registers are located within a 64 byte block in the Al6 address spac between th addresses 49152 dec COOOH and 65472 dec FFCOH The base address of the Configuration registers is determined by the following equation Base Address dec V 64 49152 dec V the Logical Address of the card is an integer which varies between 0 and 255 and is defined by the user via the 8 pole dipswitch SWI see Dip Switch Settings section In order to ensure correct operation of the board within the user s VME or VXI system the Configuration registers must be re initialized after power up or after assertion of SYSRESET For a full e
66. ch the exact specified number of data ords thus saving memory space and providing efficient space allocation Note In an RT RT transfer the EXC 1553VME MCH uses the data pointer as the ocation in memory to store the transmitted data in the transfer One common pplication for the data pointer occurs when the EXC 1553VME MCH needs to send he same data words to several RTs Here each Command Block associated with hose messages would contain the same data pointer value and therefore fetch and transmit the same data Note that the Data Pointer is never updated i e the EXC 1553VME MCH reads and writes the pointer but never changes its value tturas toot H 6 1 2 4 1553 Status Words The next two locations in the BC Mode Command Block are for status words As the RT responds to the BC s command the corresponding status word will be stored in Status Word 1 In an RT RT transfer the first status word will be the status of the Transmitting RT while the second status word will be the status of the Receiving RT 6 1 2 5 Branch Address The seventh location in the BC Mode Command Block contains the starting location of the branch This location simply allows the EXC 1553VME MCH to branch to another location in memory when certain opcodes are used 6 1 2 6 Timer Value The last location in the BC Mode Command Block is the Timer Value This timer is use
67. channel channel 3 Operational Status Register Channel 4 Active by the channel channel 4 Operational Status Register Channel 5 Active by the channel channel 5 Operational Status Register Channel 6 Active by the channel channel 6 Operational Status Register Channel 7 Active by the channel channel 7 Operational Status Register DIP SWITCH SETTINGS Address of board 9 1 Card Logical Address Dip Switch Setting EXC 1553VME MCH board contains 1 SW1 Indicates that a 1553 message is processed bit in the Indicates that a 1553 message is processed Reflects the state of the TERACT bit in the Indicates that a 1553 message is processed Reflects the state of the TERACT bit in the Indicates that a 1553 message is processed Reflects the state of the TERACT bit in the Indicates that a 1553 message is processed Reflects the state of the TERACT bit in the Indicates that a 1553 message is processed Reflects the state of the TERACT bit in the Dip Switch which controls the Logical Dip switch SW1 is used to select the card s Logical Address as described in the section VME VXI Configuration Registers The Logical Address is set as shown below Logical Address Switch SW1 MSB LSB ELS ETA 2 3 4 5 6 7 8 gt numbers indicate switch positions A15 A14 A13 A12 All A10 A9 A8 A7
68. contain the latest 1553 command that was transmitted by the bus controller 6 1 1 4 Interrupt Mask Register 0006 H Read Write The BC Mode interrupt architecture allows the host to mask or temporarily disable the service of interrupts While masked interrupt activity does not occur The unmasking of an interrupt after the event occurs does not generate an interrupt for that event An interrupt is masked only if the corresponding bit of this register is set to a logic zero Bit Name Description 15 12 reserved Should be set to O 11 MERR Message Error Interrupt 10 6 reserved Should be set to O 5 EOL End Of List Interrupt 4 ILLCMD Illogical Command Interrupt 3 LLOP Illogical Opcode Interrupt 2 RTF Retry Fail Interrupt 1 CBA Command Block Accessed Interrupt 0 reserved Should be set to O BC Mode 17 6 1 1 5 Pending Interrupt Register 0008 H READ ONLY This register is used to identify which of the interrupts occurred during operation The assertion of anv bit in this register generates an interrupt Note that all register bits are cleared on a host read Bit Name Description 15 12 reserved Ignore on
69. d EXC The E MCH automaticallv updates the CA pointer After messag CAF receiving the information word At the end of message processing B Current Address Field If B CAF correct the EXC CAF equals is reset to CA and M length in each buffer Control specify the MIB length For transmit commands the memory location CA of message processing the equals the specified MIB to zero EXC 1553V After message processing completes enters the message information word and time tag word into the M EXC 1553VME MCH updates CA and the CA is updated to TA and the M If CAF is less than the specified M length Word bits B CAF point to 15 to 8 the B E MCH begins transmission of data from EXC 1553VME MCH At the end B CAF f CAF B CAF is reset B length CA and M the next available memorv location in each buffer Note In this mode the The MIB reaches th BRD bit is added to the Message EXC 1553VME MCH generates a circular buffer emptv full nd and begins a new message at the top of the buffer B CAF point to Information word bit 5 interrupt when the Bit 8 of the Mask Register and bit 7 of the descriptor Control Word mask and enable
70. d 1 Receive 3 words Message Info Word 0200 H Index equals 3 BROADCAST DATA POINTER Broadcast Data Pointer XXXX H DATA POINTER B Data Pointer B XXXX H DATA POINTER A Data Pointer A 0100 H Receive Subaddr 1 Descriptor Block CONTROL WORD Index field contents 03XX H Figure 15 RT Non Broadcast Receive Message Indexing RT Mode 52 Note X RT Mode don t care 58 BROADCAST BUFFER DATA UFFER UU RT Mode DATA BUFF ER BROADCAST DATA POINTER DATA POINTER B gt M Data Words DATA POINTER A Time Tag of J CONTROL WO gt Message Info Word DATA BUFFER Message N Figure 16 RT Descriptor Block Receive XXXX H DATA POINTER B gt M Data Words DATA POINTER A Time Tag CONTROL WORD gt Message Info Word DATA BUFFER Message N Figure 17 RT Descriptor Block Transmit 54 6 2 2 6 The Broadcast command Bit L5 0 following bits Pointer Information word Time The command post processing Broadcast Data Pointer Mode 0 Data EXC 1553VM describ th receiv subaddress mode code descriptor This word contains the address for the Message Tag word and data words associated with a broadcast Name De BP 15 0
71. d Each connector is associated with a specific channel Channel Connector channel 0 J1 channel 1 J2 channel 2 J3 channel 3 JA channel 4 J5 channel 5 J6 channel 6 J7 channel 7 J8 Connector Jx Layout and Pin Assignments Front View Pin Signal Name Pin Signal Name 5 BUS_B_H 6 BUS_B_LO 3 SHIELD case 4 SHIELD case 1 BUS_A_HI 2 BUS_A_LO Table 6 Connector Jx Pinout Signals description BUS_A HI Channel x Bus A connection BUS_A_LO BUS_B_H Channel x Bus B connection BUS_B_LO SHIELD case Provided for 1553 cables shield connection This signal is connected to the VME system s case trough the front panel Hardware 97 11 2 Connector Pi Pinout PREPARE OOJGUSWONIO Hardware Ot Oob oosdoodu a n azjnonmi D IACK ACK AM4 A07 A06 A05 A04 A03 A02 A01 12V 5V N IACKOUT opt Pin Sig Name B1 B2 B3 B4 BGOIN B5 BGOOUT B6 BG1IN B7 BG1OUT B8 BG2IN B9 BG20UT B10 BG3IN B11 BG30UT B12 B13 B14 B15 B16 AMO B17 AM1 B18 AM2 B19 AM3 B20 GND B21 B22 B23 GND B24 RQ7 B25 RQ6 B26 RQ5 B27 RQ4 B28 RO3 B29 RQ2 B30 RQ1 B31 B32 5V
72. d for one of two purposes First the value may be used to set up minor frame schedules when using the Load Minor Frame Timer opcode 1110 The MFT counter may be driven by the Programmable Timer Clock If not driven by the Programmable Timer Clock the MFT counter is clocked by a fixed 15 625 KHz 64 usec clock The MFT counter runs continuously during message processing and must decrement to zero prior to loading the next Minor Frame time value Second the value may be used as a message to message timer MMT when using the Skip opcode 0001 The MMT timer is clocked at a 24 0 MHz 41 666 nsec rate and allows for scheduling a specific time between messag xecution BC_Mode 26 6 1 3Command Block Chaining Th user determines th address in the Command B first Command ock Pointer Register Block as long as h the e Figures in a contiguous fashion opcodes are used Wit configuration is possibl use no of 9 go to 10 these and setting the initial start Blocks will execute branch call or return opcodes almost any memory 11 show how several Command frame and how branch opcodes by The Command LA Blocks may be linked together to form a command f mav be used to link
73. d ping pong operation disabled 6 2 2 5 1 Ping Pong Handshake Mode 0 The EXC 1553VME MCH provides a software handshake which indicates th nabl and disable of buffer ping pong operation During remote terminal operation the EXC 1553VME MCH asynchronous ping pongs between two subaddress or mode code data buffers To perform buffer service the application software must freeze the remote terminal s access to a single buffer The EXC 1553VME MCH s ping pong enable disable handshake allows the application software to asynchronously freeze i e disable ping pong operation the remote terminal F to a single buffer The handshake mechanism functions as follows Prior to starting remote terminal operation enable the buffer ping pong feature by writing a logical 1 to bit 2 of the Control Register During ping pong operation the remote terminal ping pongs between the two data buffers for each subaddress or mode code on a message by message basis Each unique IL STD 1553 subaddress and mode code is assigned two data buffer locations A and B The remote terminal retrieves data from a buffer or stores data into a buffer depending on the message typ i e transmit or receive command During ping pong operation th remot terminal determines the active subaddress or mode code buffer at the beginning of message processing the
74. d will be set rmines where to store data words The from the top memorv location The Bus associated with the message into the commands commands EXC 1553VME MCH begins monitoring after Control onlv the first status word assertion of TERACT and STEX After post processing optional interrupt log entrv Time Out MIL STD 1553A 11 usec MIL STD 1553B 15 usec 6 3 6RT Concurrent BM Operation uire simultan For applications that operations the and monitor This feature specific address and the addresses Configuration req as both Bus reception cous Monitor a the second status word Register bit 15 1 i e the EXC 1553VME MCH begins Command post processing involves storing data to memorv is performed after a monitor is entered Monitor Remote Terminal and EXC 1553VME MCH should be configured as both a remote terminal allows the RT to communicate on the bus Bus Monitor to monitor the bus for other specific nd An Bus Monitor for one th EXC 1553VME MCH from monitoring its own remote terminal address When th prioritv over the Bus Monitor take prioritv over commands for the EXC 1553VME MCH is configured as both RT and For example Bus Monitor is defined for terminal address Bus Monitor 1 and the what happens if the RT
75. dress the control The monitor block for each monitor block location linked to the Monitor registers are BM Mode Block Pointer Register and the Monitor monitor block contains a Message 86 Information Word Block via the Initial is updated at the The top of the Initialized by the host Monitor Block Counter Register contents Command Command Word 1 Each Word 2 Data Pointer Status Word 1 Status Word 2 and Time Tag Refer to section Bus Monitor Architecture for a full description of each location BM Mode 87 The Message Information word allows the EXC 1553VM E MCH to inform which bus the command was received whether th Th messag EXC 1553VME was an CH and conditions associated with the mes each command word associated with the message into the appropriate only the first command word the second command word location will For normal 1553 commands data For RI RT commands and bit 8 in the Message Data Pointer det sag RT RT the user on transfer also stores location location wi 11 contain For each command the Bus Monitor stores data sequentially onitor also stores each status word appropriate location For normal 1553 location will contain data For location will contain data The RT RT contain data Information wor
76. duty cycle transmitting on 1553 bus Example 8 channel board 25 duty cycle per channel maximum power requirements will be 5V B 4 16A 1 0A 8 x 0 395A 4 16A 13 0 ORDERING INFORMATION Part Number Description Note EXC 1553VME MCH x Multi Channel 1553 VME VXI B size 6 x9 board Supports BC RT RT BM and BM Modes EXC 1553VME MCH x E Same as above with Ruggedization and Extended 1 Temperature 40 to 4850 C operation EXC 1553VXI MCH x Multi Channel 1553 VXI C size 13 x9 board Supports BC RT RT BM and BM Modes Supplied with RFI EMI shield EXC 1553VXI MCH x E Same as above with Ruggedization and Extended dE Temperature 40 to 4850 C operation x number of channels required up to 8 EXC 1553UPG MCH Additional Channel upgrade 2 Note 1 Products with E suffix come with a board stiffener and all components are soldered onto the printed circuit board sockets are not used enabling use in high vibration environments 2 Factory installed upgrades for additional channels to a maximum of 8 may be ordered 100 APPENDIXES APPENDIX A MIL STD 1553B WORD FORMATS REGISTER 15 14 13 12 11 10 9 8 7 6 5 0 BITS 1553 BIT 1 2 3 4 5 6 T 8 9 10 11 12 13 LS 19 20 TIMES CMD WORD 5 l 5 SYNC RT IT RI COUNT MODCOD P ADDRESS WORD 16 DATA RT ADDRESS RESERVED Appendix A SUBADDRESS M
77. e EXC 1553VME MCH will look for the RT s response in 7 usec MIL STD 1553A or in 12 usec MIL STD 1553B Assertion of this bit forces the Bus Monitor to declare a time out error condition if the RT has not responded in 9 usec Negation of this bit allows the Bus Monitor to declare a time out error condition if the RT has not responded in 14 usec 6 5 reserved These read only bits should be ignored on read BM Mode 77 Bit Name Description 4 reserved Should be set to O 3 EX EXC 1553VME MCH Channel Executing This read oniv bit indicates whether the channel is presentlv executing or whether it is idle A logic one indicates that the channel is executing a logic zero indicates idle 2 reserved Should be set to O 1 RI E ADV Channel Ready This read only bit indicates that the channel has completed initialization or B I T This bit is cleared on reset 0 TERACT Channel Terminal Active This read only bit indicates that the channel is presently processing a 1553 message This bit is cleared on reset 6 3 1 3 Current Command Register 0004 H READ ONLY This register contains the last valid command that was transmitted over th 1553 bus In an RT RT transfer this register will update as each of the two commands are received by the Bus Monitor Bit Name Description 15 0 ccr15 0 Current Command These bits contain the la
78. e mode codes Table 2 shows the illegalization register map For each block the numbers shown in the column under each bit number identifies the specific subaddress or mode code in hex that the register bit illegalizes Logical 0 legal Logical 1 illegal RT Mode 41 Name Register Address Hex BitNumber 15 14 13 12 11 109876543210 Receive 0020 OF OE OD OC 0B 0A 09 08 07 06 05 04 03 02 01 00 0022 1F 1E 1D 1C 1B 1A 19 18 17 16 15 14 13 12 11 10 Transmit 0024 OF OE OD OC OB 0A 09 08 07 06 05 04 03 02 01 00 0026 1F IE ID IC 1B 1A 19 18 17 16 15 14 13 12 11 10 Brd Receive 0028 OF OE OD OC 0B 0A 09 08 07 06 05 04 03 02 01 00 002A IF IE ID IC 1B 1A 19 18 17 16 15 14 13 12 11 10 Brd Transmit 002C XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX 002E XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX Mode Receive 0030 OF OE 0D OC 0B 0A 09 08 07 06 05 04 03 02 01 00 0032 1F IE ID IC 1B 1A 19 18 17 16 15 14 13 12 11 10 Mode Transmit 0034 OF 0E OD OC 0B 0A 09 08 07 06 05 04 03 02 01 00 0036 1F IE ID IC 1B 1A 19 18 17 16 15 14 13 12 11 10 Mode Brd Receive 0038 OF OE OD OC 0B 0A 09 08 07 06 05 04 03 UU 01 WW 003A IF IE ID IC 1B 1A 19 18 17 16 15 14 13 12 11 10 Mode Brd Transmit003C OF OE OD OC 0B 0A 09 08 07 06 05 04 03 ZZ 01 XX 003E YY YY YY YY YY YY YY YY YY YY YY YY YY YY YY YY Table 2 RT Illegalization Register Map Notes 1 Brda Broadcast 2 Mode Mode cod
79. ed 0 Mode 1 Circular Buffer 1 Operation Mode 2 Circular Buffer 2 Operation 5 reserved Should be set to O 4 BCEN Broadcast Enable Assertion of this bit enables the broadcast option for RT Mode Negation of this bit nables remote terminal address 31 as a unique remote 3 DYNBC Dynamic Bus Control Acceptance This bit controls the EXC 1553VME MCH s ability to accept the dynamic bus control mode code Assertion of this bit allows the EXC 1553VME MCH to respond to a dvnamic bus control mode code with status word bit 18 set to a logic one Negation of this bit prevents the assertion of status word bit 18 upon reception of the dvnamic mode code 2 PPEN Ping Pong Enable Assertion of this bit enables the ping pong buffer featur of the EXC 1553VME MCH and disables the message indexing feature Negation of this bit disables the ping pong feature and enables the message indexing feature 1 NTEN Interrupt Log Enable Assertion of this bit enables the interrupt logging feature Negation of this bit prevents the logging of interrupts 0 XMTSW Transmit Last Status Word Assertion of this bit allows the EXC 1553VME MCH to automaticallv xecut th TRANSMIT LAST STATUS WORD mode code when configured for MIL STD 1553A mode operation 6 2 1 2 Operational Status Register 0002 H Read Write This reg
80. edge skew correct number of bits and parity If the command is a receive command the EXC 1553VME MCH processes each incoming data word for correct format word count and contiguous data If a message error is detected the EXC 1553VME MCH stops processing the remainder if any of the message suppresses status word transmission and asserts bit time 9 ME bit of the status word The EXC 1553VME MCH automatically compares the transmitted word encoder word to the reflected decoder word by way of the continuous loop back feature If the encoder word and reflected word do not match the WRAPF bit is asserted in the BIT Word Register In addition to the loop back compare test a timer precludes a transmission greater than 800 usec by the assertion of Fail Safe Timer This timer is reset upon receipt of another command Remote Terminal Response Time MIL STD 1553A 7 usec MIL STD 1553B 10 usec Data Contiguity Time Out 1 0 usec RT Mode 72 6 2 7RT RT Transfer Compare The RI to RT Terminal Address compare logic ensures that the incoming status word s Terminal Address matches the Terminal Address of the transmitting RT specified in the command word An incorrect match results in setting the message error bit and suppressing transmission of the status word RT to RT transfer time out 55 to 59 usec The EXC 1553VME MCH does n
81. el has been started the host must halt the channel in order to place the channel into the Built In Test routine STEX 0 Note If Start B I T SBIT and Start Execution STEX are both set on one register write BIT has 13 11 reserved Should be set to priority UT 10 PTCE Programmable Timer Clock Enable Assertion of this bit enables a programmable clock used with an internal time tag counter Refer to Programmable Timer Clock Register section described above If set to logic zero the EXC 1553VME MCH will use an internal fixed clock Refer to Time Tag Register Note The user can only change the clock frequency source before starting the EXC 1553VME MCH i e setting STEX bit to 1 9 ERTO Extended Response Time Out Assertion of this bit nables th xtended response time out option and forces the BM Mode to look for an RTs response time in 30 usec or generate time out errors Negation of this bit enables for the standard time out in 14 usec 8 6 reserved Should be set to O BM Mode 76 Bit Name Description 5 BMTC Bus Monitor Control This bit d
82. eration takes 5 usec to execute 5 2 Reserved FFFC H This location is reserved General L3 status general The user has direct access to The user controls the softwar reset s figure TMC S MMIT XT 1553 message protocol The EXC B as well as Mil std performs a software reset of the had been switched off then on ncoder decoder all control registers and associated Note that assertion of reset terminates immediately command processing The logic will be reset 6 0 OPERATIONAL MODES The following describes the operation of a single channel of the EXC 1553VME MCH in each of its operational modes Note that the operation and addressing of the next channels is identical to that of the first with the appropriate base address 6 1 BUS CONTROLLER MODE BC MODE 6 1 1Control Registers For BC Mode The control registers are read write unless otherwise stated All control registers must be accessed in word mode All control register bits are active high and are reset to 0 unless otherwise stated 003E H reserved 0012 H COMMAND BLOCK POINTER REG 0010 H INOR FRAME TIMER 000E H BIT WORD REG 000C H INT LOG LIST POINTER REG 000A H PENDING INTERRUPT REG 0008 H NTERRUPT MASK REG 0006 H CURRENT COMMAND BLOCK
83. etermines whether th EXC 1553VME MCH will monitor all RTs or selected RTs If this bit is set to logic zero the EXC 1553VME MCH will monitor all RTs If this bit is set to logic one the EXC 1553VME MCH will monitor only the RTs as specified in the Monitor Filter Hi Lo Registers 4 BCEN Broadcast Enable This bit if set to logic one allows RT address 31 to be used as a Broadcast message If set to logic zero then address 31 is a normal address 3 2 reserved Should be set to O 1 NTEN Interrupt Log List Enable Assertion of this bit enables th Interrupt Log List Negation of this bit prevents the logging of interrupts as they occur 0 reserved Should be set to O 6 3 1 2 Operational Status Register 0002 H Read Write This register provides pertinent status information for BM Mode and is not reset to 0000H on reset Instead the bit A B_STD is set to l Note To make changes to the BM and to this register the STEX bit Control Register bit 15 must be logic zero Bit Name Description 15 10 reserved Should be set to O 9 MSELI Mode Select 1 In conjunction with Mode Select 0 this bit determines the EXC 1553VME MCH mode of operation 8 MSELO Mode Select 0 In conjunction with Mode Select 1 this bit determines the EXC 1553VME MCH mode of operation MSEL1 MSELO Mode of Operation 0 0 BC Mode 0 1 RT Mode 0 BM Mode RT Concurrent BM Mode 7 A B_STD Military Standard 1553A or 1553B Standard This bit determines whether th
84. failure User Defined Bits 37 6 2 1 8 Time Tag Register OOOE H READ ONLY The Time Tag Register reflects the state of a 16 bit free running counter This counter may be driven by the Programmable Timer Clock see PTCE bit within Control Register If not driven by the Programmable Timer Clock this counter is clocked by a fixed 15 625 KHz 64 usec clock The Time Tag counter is automatically reset when the EXC 1553VME MCH receives a valid synchronize without data mode code The EXC 1553VME MCH automatically loads the Time Tag counter with the data associated with reception of a valid synchronize with data mode code The Time Tag counter begins operation immediately after reset or within 64 usec after th receipt of a valid mode code reset remot terminal or synchronize with without data When the RT is halted STEX 0 the Time Tag continues to run Bit Name Description 15 0 TT 15 0 Time Tag Counter Bits These bits indicate the state of the 16 bit internal counter 6 2 1 9 RT Descriptor Pointer Register 0010 H Read Write Each subaddress and mode code has a reserved block of memory containing information on how to process a valid command to that subaddress or mode code Located contiguously in memory these reserved memory locations are called a descriptor space The RT Descriptor Pointer Register contains an address that points
85. gister if not masked in the Mask Register An interrupt is generated after messag processing 49 Bit Name Description 4 BAC Block Accessed The user initializes this bit to zero the EXC 1553VME MCH overwrites the zero with a logic one upon completion of message processing After interrogating this bit the host resets this bit to zero to observe further accesses 3 reserved Should be set to O 2 A B Buffer A B This bit indicates the last buffer accessed when buffer ping ponging is enabled During initialization the user designates the first buffer used bv asserting or negating this bit A logic one indicates buffer A a logic zero indicates buffer B This bit is a don t care if buffer ping ponging is not enabled 1 BRD Broadcast Received Assertion of this bit indicates the reception of a broadcast command 0 reserved Should be set to O 6 2 2 5 Data Pointer A and B Mode 0 Data List Pointer A and B contain address information for the retrieval and storage of message data words In the index mode of operation the EXC 1553VME MCH reads Data Pointer A to determin th location of data for retrieval or storage The EXC 1553VME MCH uses the Data Pointer to initialize an internal counter the counter increments after each data word For a receive command the EXC 1553VME MCH stores the incoming data word sequentially into memory As part of comma
86. h number of interrupts that have occurred By extracting the least significant five bits from the Interrupt Log List Register and logical shifting the data once to the right the user determines the number of interrupt events Ring Buffer Pointer Base Address 00 H W Base Address 20 H W 9 Base Address 02 H IAW Base Address 22 H IAW 9 Base Address 04 H W 2 Base Address 4 24 H w 10 Base Address 06 H IAW 2 Base Address 26 H IAW 10 Base Address 08 H W 3 Base Address 28 H W Base Address OA H IAW 3 Base Address 2A H IAW Base Address OC H W 4 Base Address 2C H W 12 Base Address OE H IAW 4 Base Address 2E H IAW 12 Base Address 10 H W 5 Base Address 30 H W 13 Base Address 12 H IAW 5 Base Address 32 H IAW 13 Base Address 14 H W 6 Base Address 34 H W 14 Base Address 16 H IAW 6 Base Address 36 H IAW 14 Base Address 18 H W 7 Base Address 38 H W 15 Base Address 1A H IAW 7 Base Address 3A H IAW 15 Base Address 1C H W 8 Base Address 3C H W 16 Base Address 1E H IAW 8 Base Address 3E H IAW 16 Interrupt Log List Interrupt Log List Address Register Contents Address Register Contents
87. h was generated by Channel n will result in the interrupt routine whose vector resides in VECTOR n register to be executed If case of multiple pending interrupt requests the highest priority request STATUS ID will appear first After the user services this interrupt a second interrupt will be generated for the next pending interrupt The priorities are defined as follows Request name Priority hannel 0 Request Highest hannel 1 Request hannel 2 Request hannel 3 Request hannel 4 Request hannel 5 Request hannel 6 Request hannel 7 Request Lowest C2002 6 1 20 For all interrupts the serviced interrupt request is cleared automatically at the end of the interrupt acknowledge cycle This method is referred to within the VME specification as ROAK Release on AcKnowledge VME VXI Interface 3 1 70ffset Register VXI amp VME This A32 memory and registers 16 bit read write register defines the bas 06 Read Write BASE address of the card s A24 or If A24 addressing is used the 5 most significant E bits of the Offset register are the values of the 5 most significant bits of the card s memory and register addresses and the 8 least significant bits of not used th register ar represents the 13 most the Offset lines A23 through A19 for the A24 Address Space 15 trough 3 map to address
88. ion word Time Tag word and message data word All receive mode codes with data have one associated data word Data storage occurs at the memory location pointed to by the data pointer plus two locations Reception of the synchronize with data mode code automatically loads the Time Tag counter and stores the data word at the address defined by the data pointer plus two locations The transmit mode code data structure contains an Information word Time Tag word and associated data word The host is responsible for linking the EXC 1553VME MCH Data Pointer to the data e g Transmit Vector word For mode codes with internally generated data words e g Transmit BIT word Transmit Last Command the transmitted data word is added to the data structure For MIL STD 1553A mode of operation all mode codes are defined without data words For mode codes without data the data structure contains the Message Information word and Time Tag word only Note In MIL STD 1553A all mode codes are without data and the T R bit is ignored See section MIL STD 1553A Operation in following 6 2 3 3 1 Mode Code Receive Information Info Word The following bits describe the Mode Code Receive Information word contents Bit Name Description 15 11 MC 4 0 Mode Code Thes five bits contain the mode code information extracted from the receive c
89. ip between IRQSEL 2 0 and IRQ7 1 SELECTED IRQ LINE IRQSEL2 IRQSEL1 IRQSELO NONE 0 0 0 TRQ1 0 0 1 TRQ2 0 0 TRQ3 0 1 1 TRO4 0 0 TRQ5 0 1 TRQ6 0 IRQ7 VME VXI Interface Bit_Name Description A24 A32 ENABLE Writing a 1 to this bit enables access to the card s Memory Enable 1553 essage Storage Area and Control Registers residing in A24 or A32 VME address space If this bit is set to 0 none of the on card registers and memory which are resident in the A24 or A32 address space may be accessed The Configuration registers of course remain accessible regardless of the state of this bit as they reside in the A16 address space of the card 3 1 6Using Interrupts on VME The Interrupt generated on the selected IRQ line is the logical OR of all interrupt generating sources on the card An interrupt which was generated by Channel 0 will result in the interrupt routine whose vector resides in VECTOR 0 register to be executed The card will place the value in the V E d ECTOR 0 register called the STATUS ID onto the VME data lines when issuing he interrupt acknowledge cycle The user s processor will use this value to etermine which entry in the user s interrupt vector table to jump to Within this interrupt routine the actual source of the interrupt can be determined by polling the Pending Interrupt Register Likewise an interrupt whic
90. ister Note It is recommended that this register not be changed while the Bus Monitor is active i e Operational Status Register bit EX 1 Bit Name Description 15 0 MBC 15 0 Monitor Block Count These bits indicate the number of onitor Blocks to log 6 3 1 12 Monitor Filter Hi Register 001C H Read Write This register determines which RTs RT 31 through RT 16 the EXC 1553VME MCH will monitor Bit Name Description 15 0 MFH 31 16 Monitor Filter Hi These bits determine which RT to monitor 6 3 1 13 Monitor Filter Lo Register OO1E H Read Write This register determines which RTs RT 15 through RT 0 the EXC 1553VME MCH will monitor Bit Name Description 15 0 MFL 15 0 Monitor Filter Lo These bits determine which RT to monitor BM Mode 81 6 3 2Bus Monitor Architecture To meet the MIL STD 1553 monitor requirements the EXC 1553VME MCH utilizes a Monitor Block architecture that takes advantage of both control registers and RAM The Monitor Block which is located in contiguous memory requires eight locations for each message These eight locations include a message information word two command word locations a data pointer two status word locations a time tag location and a reserved location The user must initialize the starting locations of the Monitor Bl
91. ister provides pertinent status information for RT Mode and is not reset to 0000H on reset Instead the bits A B STD and RTA 4 0 are set to kai ii A Note To make changes to the RT and to this register the STEX bit Control Register bit 15 must be logic zero Bit Name Description 15 11 RTA 4 0 Remote Terminal Address Bits These five bits contain the remote terminal address The RTA4 bit is the MSB bit while the RTAO bit is the LSB bit RT Mode 33 Bit Name Description 10 RTAPTY Terminal Address Paritv Bit This bit is appended to the remote terminal address bus RTA 4 0 to supply odd parity The EXC 1553VME MCH requires odd parity for proper operation 9 MSEL1 Mode Select 1 In conjunction with Mode Select 0 this bit determines the channel s mode of operation 8 MSELO Mode Select 0 In conjunction with Mode Select 1 this bit determines the channel s mode of operation MSEL1 MSELO Mode of Operation 0 0 BC Mode 0 1 RT Mode 0 BM Mode RT Concurrent BM Mode 7 A B_STD Military Standard 1553A or 1553B This bit determines whether the EXC 1553VME MCH will operate under MIL STD 1553A or 1553B protocol Assertion of this bit enables the XMTSW bit Bit 0 of
92. l word Information contained in this word assists the EXC 1553VME MCH in message processing by the Bit Name 15 7 reserved 6 IWA 5 reserved 4 BAC 3 reserved 2 A B RT Mode The descriptor control word is initialized bv the host and updated EXC 1553VME MCH during command post processing Description Should be set to O Interrupt When Accessed Assertion of this bit enables the generation of an interrupt when the subaddress receives a valid command The interrupt is entered into the Pending Interrupt Register if not masked in the Mask Register An interrupt is generated after messag processing Should be set to O Block Accessed The host initializes this bit to zero and the EXC 1553VME MCH overwrites the zero with a logic one upon completion of message processing After interrogation the user should reset this bit to zero to F observe further accesses Should be set to O Buffer A B ndicates the data pointer to access when buffer ping pong is enabled During initialization the host designates the first buffer used by asserting or negating this bit A logic one indicates buffer A a logic zero indicates buffer B This bit is a don t care if buffer ping ponging is not enabled 47 Bit Name 1 BRD 0 reserved 6 2 2 3 Description Broadcast Received Assertion of this bit
93. lines A31 through A19 for the A32 Address Space addresses Thus A24 ADDRESSING EXAMPLE OFFSET 0 0 0 1 1 15 14 13 12 1 If A32 addressing is used the Offset register of the card s memory and register 15 through 11 map to the address significant bits register bits and the Offset register bits required base address 18 0000 H write 18XX H to Offset register X don t care 10 9 8 7 6 5 4 3 2 1 0 A23 A22 A21 A20 A A32 ADDRESSING EXAMPLE required base address FF38 0000 H write FF38 H to Offset register OFFSET 10 9 8 7 6 5 4 3 2 1 0 A31 A30 A29 A28 A27 A26 A25 A24 A23 A22 A21 A20 A19 Interface VME VXI 3 1 8 Vectorin Register VXI amp VME BASE 20 H 2n Read Write In the case of an interrupt generated by Channel fn the 8 least significant bits of this 16 bit register known as the STATUS ID are used as the interrupt vector during the ensuing interrupt acknowledge cycle The card is a DO8 0 NTERRUPTER and as a result will place these 8 bits on lines DOO DO7 of the VME bus during the interrupt acknowledge cycle Refer to section Using Interrupts on VME The 8 most significant bits of this register are don t care X X X X X X X X STATUS ID X don t care 3 1 9Programmable Timer Clock Register VXI amp VME BASE 30 H Read Write
94. mmand Blocks After execution begins this register is automatically updated with the address of the next block Bit Name Description 15 0 CBA 15 0 Command Block Address These bits indicate the starting location of the Command Block BC_Mode 20 6 1 2BC Architecture As defined in MIL STD 1553 the bus controller initiates all communications on the bus To meet MIL STD 1553 bus controller requirements the EXC 1553VME MCH utilizes a Command Block architecture that takes advantage of both control registers and RAM Each command word transmitted over the bus must be associated with a Command Block The Command Block requires eight contiguous 16 bit memory locations for each message Thes ight locations include a control word two command word locations a data pointer which indicates where data is to be written to or read from two status word locations a branch address location and a timer value used in the scheduling of messages The host must initialize each of the locations associated with each Command Block the exception being is f for the two status locations which will be updated as command words are transmitted and corresponding status words are received Command Blocks mav be linked together in such a manner as to allow the generation of Major and Minor message frames In addition the BC can detect the assertion of Status
95. mode field and word count mode code field to select a unique descriptor block which contains Control Word TA CA and MIB see figure 19 To implement Circular Buffer 2 s architecture th descriptor block and Control Register are different than in Mode 0 Bits 15 through 8 of the Control Word specify the Message Information Buffer MIB length the maximum MIB size is 256 Table 3 shows how the Control Word s most significant bits select the depth of the MIB The Control Words eight most significant bits remain static during message processing The second word of the description block defines the top address TA of the data circular buffer The TA pointer remains static during message processing The third descriptor word identifies the current address i e CA of the data circular buffer The application software reads the dynamic CA pointer to determin th current address of the data buffer The EXC 1553VME MCH increments the CA pointer at the end of message processing until the MIB buffer is full When the MIB wraps around the SuMMIT loads the CA pointer with the TA pointer The fourth word in the descriptor block defines the top or base address of the Message Information Buffer i e MIB and the current MIB address i e offset from base address The SuMMIT enters the message informa
96. n RT RT messag xample Message 1 CMD TA 1 CMD TA 12 Message 2 CMD TA 12 CMD TA 1 6 3 7 MIL STD 1553A Operation The EXC 1553VME MCH may be configured to meet the MIL STD 1553A protocol A B_STD ERTO RESULT 0 0 553B standard 1553B response in 14 usec 0 1 553B standard extended response in 30 usec 0 1553A standard 1553A response in 9 usec 1 1553A standard extended response in 21 usec When configured as a MIL STD 1553A monitor the EXC 1553VME MCH will operate as follows looks for the RT response within 9 usec ignores the T R bit for all mode codes defines all mode codes without data defines subaddress 00000 as a mode code BM Mode 89 6 4 CHANNEL INTERRUPT ARCHITECTURE The EXC 1553VME MCH channel registers an Interrupt Log registers interrupt include a Pending Interrupt List Log List Register information that identifies Interrupt Mask Register allows the user to mask or disable the generation of the and the Interrupt Register The Pending events genera architecture involves three control interrupt line The thr control Interrupt Mask Register and Interrupt Register contains ting the interrupts The interrupts The Interrupt Log List Register contains the base address of a 32 word interrupt ring buf Th lower t
97. nd post processing the EXC 1553VME MCH writes a new data pointer into the descriptor block The EXC 1553VME MCH continues to update the data pointer until the Control Word index E field decrements to zero An example is shown in figure 15 Note The index feature is not applicable for transmit commands i e T R bit 1 For ping pong buffer operation the host uses either Data Pointer A or Data Pointer B The EXC 1553VME MCH determines which pointer to access via the state of Control Word bit 2 The EXC 1553VME MCH retrieves or stores data words from the address contained in the data pointer automaticallv incrementing the data pointer as data words are received The data pointer is never updated as part of command post processing in the ping pong mode of operation See figures 16 and 17 RT Mode 50 Bit Name Description 15 0 DP 15 0 Data Pointer Bits The second and third words of the descriptor block contain the data buffer location The EXC 1553VME MCH accesses either Data Pointer A or Data Pointer B depending on the state of Control Word Bit 2 during ping pong operation For index operation the EXC 1553VME MCH accesses onlv Data Pointer A The EXC 1553VME MCH updates data pointer A after messag processing is complete and th index field is not equal to zero an
98. nformation Info Word 55 DES Mode Code Dalai e ao ee hay ead aye T 56 243433 ode Code Receive Information Info Word 56 LID ode Code Transmit Information Info Word 57 2 4RT Circular Buffer Modes 1 and 2 o oooooooo oo 58 2 4 Mode 1 Opetatii Ot a i B a a hel gate ace See a Scarce 58 Les As My ode 1 Descriptor BOCK is ia wes a ee are eae 58 2A MN ode Fl Circular Butte a daa 59 2 4 2 Mode 2 Operation a o mes Oy A 61 DL ode 2 Des riptot Blocks daa das 61 2 4 2 2 vde 42 Circular Butter ieda acidos la 62 2 9Mode Code ana subaddte 8 Divina a rias is 64 26 Encoder and Decoder eenaa e Sree ee 66 2 RTORT TEanster Conpa Give niece ccs b aa as 67 2 59 Termina L AQdALESS U oct ied a e A la e aa 67 DARRO SO Es Sir 0 a a esate Me Aa AN AA wig A A E is 67 2 10 MIL STDSESSSA Opetatioti iii a a ra ele eb le ee aes 68 3 BUS MONITOR MODE BM Mode oo o ooo 69 31 Control Registers for BM Modes eei 66 aa canicas 69 Dn O Description of BM Mode Control Registers 70 ALLE CONE ROM RE SEE H a ai A ta ia a ear oon Sieh da 70 Bid eZ Operational Status Regilstel ooooooooooooooooo 71 34113 Current Command Registel o oooooooooooooooo ooo 72 3 1 4 Ehterrupt Mask REgIST mit EEEE a 72 SxS Pending Interrupt Registel o oooooooooooooooo o 73 3 416 Interrupt Log List Pointer Register 73 aa 10 11 12 13 0 0 TABLE OF CONTENTS
99. ns from one to zero The interrupt is entered into the Pending Interrupt Register if not masked in the Mask Register An interrupt is generated after message processing Interrupt When Accessed Assertion of this bit enables the generation of an interrupt when a mode code command is received The interrupt is entered into the Pending Interrupt Register if not masked in the Mask Register An interrupt is generated after message processing Interrupt Broadcast Received Assertion of this bit nables th generation of an interrupt when a valid broadcast mode code command is received The interrupt is entered into the Pending Interrupt Register if not masked in the Mask Register An interrupt is generated after message processing 48 Bit Name BAC reserved A B BRD Description Block Accessed The user initializes this bit to zero the EXC 1553VME MCH overwrites the zero with a logic one upon completion of message processing After interrogating this bit the user resets this bit to zero to observe further accesses Should be set to O BE Buffer A B ndicates the last buffer accessed when buffer ping ponging is enabled During initialization the user designates the first buffer used bv asserting or negating this bit A logic one indicates buffer A a logic zero indicates buffer B This bit is a don t care if buffer ping
100. nterrupt architecture allows for the masking of all interrupts An interrupt is masked if the corresponding bit of this register is set to logic zero This feature allows the host to temporarily disable the service of interrupts While masked interrupt activity does not occur The unmasking of an interrupt after the event occurs does not generate an interrupt for that event Bit Name Description 15 12 resereved Should be set to O 11 MERR Message Error Interrupt 10 SUBAD Subaddress Accessed Interrupt 9 BDRCV Broadcast Command Received Interrupt 8 XEQO Index Equal Zero Interrupt 7 ILLCMD Illegal Command Interrupt 6 0 reserved Should be set to O 6 2 1 5 Pending Interrupt Register 0008 H READ ONLV The Pending Interrupt Register contains information that identifies events which generate interrupts The assertion of anv bit in this register generates an interrupt A register read of the Pending Interrupt Register will clear all bits Bit Name Description 15 12 reserved Ignore on read RT Mode 85 Bit Name Description 11 MERR Message Error Interrupt Assertion of this bit indicates that a message
101. o ooooooooooooooo o 1 Figure 2a Direct Coupled Connection One Bus Shown 2 Figure 2b Transformer Coupled Connection One Bus Shown 2 Fi ure 38 Contrigurdat Lon Register ss May f ib bia A ie Mee ee Ne 4 Figure 4 emory Registers Address Mapping Diagram 1 L1 Figure 5 FXCc 1553VME MCH Memory Mapu 12 Figure Channel Memory Map ii dl il dl L3 Fi ure fi BC Control Registers Ma Pie testes o a ds a eee Se ele al 4 Rurgure 8 BC Command Block Atr chitettutei lb bet ene a 21 Figure 7957 BO Minor Frame Branch ra a a 27 Figure 105 BC Minor Frame seguenciti iui alia ee day ee arid Bos Seg eee dea eee eG 27 Figure dilo BE Major Frame Sequencing id a sta Sha bch se Sis aes Sue Bole Gls eae 28 Figure 425 BE Memory rAtelite itik e ss ive int NI clan es 29 Figure 13s RI Control Registers Mapes sa la wa ear oi ote ata otal oes eee fale ele ave beens ee 31 Figure Las ORT Descriptor Tabla face aa o a wie bye a Masse Leyes ds 44 Figure 15 RT Non Broadcast Receive Message Indexing 51 Figure 16 RT Descriptor Block Recelve oooooooooooooooooo ooo 52 ki ure Dye RI Descriptor Block Transmit ssia a xb 8 eS 52 Figure 18 RT Mode 1 Descriptor Block and Circular Buffer 60 Figure 19 RT Mode 2 Descriptor Block and Circular Buffers 63 Figure 202 BM Control Registers Map sib data ia a ia ese a bw le eee 69 Fi ure 2d BM M nttor Block
102. ock the Data Pointer Block Counter and the Interrupt Log Pointer From then on the EXC 1553VME MCH will build a Monitor Block for each message it receives over th 1553 bus Figure 21 shows a diagram of the Monitor Block followed by a description of each location associated with the Monitor Block reserved TIME TAG STATUS WORD 2 STATUS WORD 1 DATA POINTER COMMAND WORD 2 COMMAND WORD 1 NFORMATION WORD MESSAG T Figure 21 BM Monitor Block Diagram BM Mode 82 6 3 2 1 The first information word bus definition number 15 O1 00 Bit Number 15 12 LEO Message Information Word location of each Monitor Block contains the Each message information word contains the opcode RT RT messages and the message information memory message retry 12 11 10 8 7 0 0 0 Information BUSA RT RT Message Description Default With the Monitor Block architectur Command Block architecture thes bits state which is the Execute and Continue opcode monitor must switch to the BC mode of operation resembling the BC default to a 0100 in case the Default With the Monitor Block architectur resembling the BC these bits default to a 00 state If the monitor must switch to the BC the retries will be set at four per message
103. of the Assertion of this bit nables th st Negation of this bit prevents the logging Command Block control word 1 NTEN Interrupt Log List Enable Interrupt Log Li of interrupts as they occur 0 reserved Should be set to 0 6 1 1 2 Operational Status Register This register provides pertinent status information for reset to 0000H on reset Instead Bit 15 10 reserved 9 BC_Mode Note To make changes to the Register 0002 H Read Write the bit A B ST bit 15 must be logic zero BC Mode and is not Dis set to 1 BC and to this register the STEX bit Control Name Description Should be set to 0 MSELI Mode Select 1 In conjunction with Mode Select 0 this bit determines the channel s mode of operation MSELO Mode Select 0 In conjunction with Mode Select 1 this bit determines the channel s mode of operation MSEL1 MSELO Mode of Operation 0 0 BC Mode 0 HE RT Mode 0 BM Mode RT Concurrent BM Mode A B_STD Military Standard 1553A or 1553B This bit determines whether the EXC 1553VME MCH will operate under MIL STD 1553A or 1553B protocol Assertion of this bit forces the EXC 1553VME MCH to look for all responses in 9 usec or generate time out errors Negation of thi
104. ollowing paragraphs 6 2 4 1 Mode 1 Operation In this mod th EXC 1553VME MCH merges transmit or receive data into a circular buffer along with message information For each valid receiv message the EXC 1553VME MCH enters a message information word time tag word and data word s into a unique receive circular buffer For each valid transmit message the EXC 1553VME MCH enters a message information word and time tag word into reserved memory locations within the transmit circular buffer The EXC 1553VME MCH automatically controls the wrap around of circular buffers 6 2 4 1 1 Mode 1 Descriptor Block Each subaddress and mode code both transmit and receive has a unique circular buffer assignment The EXC 1553VME MCH decodes the command word T R bit subaddres mode code field and word_count mode_code field to select a unique descriptor block which contains Control Word TA CA and BA see figure 18 To implement Circular Buffer 1 s architecture the four word descriptor block and Control Register are different than in the Mode 0 Bits 15 through 8 of the Control Word are don t care The second word of the descriptor block defines the buffer s starting or top address TA The TA pointer remains static during message processing The fourth entry into the descriptor block identifies the buffer s bottom address i e BA and al
105. ommand word bit times 15 to il 9 10 reserved Ignore on read 9 BUA BBus A B Assertion of this bit indicates that the message was received on bus A Converselv if this bit is set to logic zero the message was received on bus B 8 RTRT Remote Terminal to Remote Terminal Transfer Assertion of this bit indicates the command processed was an RT to RT transfer 7 ME Message Error Assertion of this bit indicates a message error condition was observed during processing See bits O to 4 for details 6 5 reserved Ignore on read 4 ILL Illegal Command Received Assertion of this bit indicates the command received was an illegal command RT Mode 58 Bit Name 3 TO 2 OVR 1 PRTY 0 MAN Description Time out Error Assertion of this bit indicates the EXC 1553VME MCH did not receive the proper number of data words i e the number of data words received was less than the word count specified in the command word Overrun Error Assertion of this bit indicates the EXC 1553VME MCH received a word when none was expected or the number of data words received was greater than expected Parity Error Assertion of this bit indicates the EXC 1553VME MCH observed a parity error in the incoming data words the the indicates error in anchester Error Assertion of this bit EXC 1553VME MCH observed a Manchester incoming data wo
106. on as specified in the branch address location If no conditions are met the opcode appears as an execute and continue Interrupt Continue This opcode instructs the EXC 1553VME MCH to interrupt and continue processing on the next command block When using this opcode no 1553 processing occurs Call This opcode instructs the EXC 1553VME MCH to go to the command block as specified in the branch address location without processing this block The next command block address is saved in an internal register so that the EXC 1553VME MCH may remember on address and return to the next command block No command processing takes place i e no 1553 Return to Call This opcode instructs the EXC 1553VME MCH to return to the command block address saved during the Call opcode No command processing takes place i e no 1553 Reserved The EXC 1553VME MCH will generate an illegal opcode interrupt if interrupt enabled and automatically stop execution if a reserved opcode is used Load Minor Frame Timer This opcode instructs the EXC 1553VME MCH to load the minor frame timer MET with the value stored in the eighth location of the current command block The timer will be loaded after the previous MFT has decremented to zero After the MFT timer is loaded with the new value th EXC 1553VME MCH will proceed to the next command block No command processing takes pl
107. ong operation is acknowledged by bit 9 of the Control Register Bit 9 of the Control Register acknowledges the ping pong disable by transitioning from a logical one to a logical zero The application software interrogates bit 2 of each Descriptor Control Word to determin th active buffer on a subaddress or mode code basis If bit 2 is a logical zero the remote terminal uses Buffer A and the application software off loads or loads Buffer A The application software enables ping pong operation by writing a logical one to Control Register bit 2 The enable of ping pong operation is acknowledged by bit 9 of the Control Register Bit 9 of the Control Register acknowledges the ping pong enable by transitioning from a logical zero to a logical one Data Word 3 021A H Index decrements to 0 Data Pointer A updated Data Word 2 0218 H to 010E H interrupt generated if enabled Data Word 1 0216 H Time Tag 0214 H Command 3 Receive 3 words Message Info Word 0212 H Index equals 1 Data Word 2 0210 H Index decrements to 1 Data Word 1 020E H Time Tag 020C H Command 2 Receive 2 words Message Info Word 020A H Index equals 2 Data Word 3 0208 H Index decrements to 2 Data Word 2 0206 H Data Word 1 0204 H Time Tag 0202 H Comman
108. ored Time Tag counter reset 0000 H Status word transmitted Command word stored 2 Last status word 3 Status word cleared master reset Note EXC 1553VME MCH status word if illegalized RT Mode 68 T R Mode Code Function 1 00011 Initiate Self Test I 00100 Transmitter Shutdown 1 00101 Override Transmitter Shutdown override mode a ena Reg ter clears shutdown 1 00110 Inhibit Terminal Flag Bit to disabled RT Mode 69 Operation 1 Command word stored 2 Status word transmitted 3 B I T initiated 4 TF bit set if BITF bit asserted 1 Command word stored 2 Status word transmitted 3 Alternate bus disabled 1 Command word stored 2 Status word transmitted 3 Alternate bus enabled Note Reception of the transmitter shutdown code does not enable bus not previously bled in the Control ister Reset remot minal mode code the transmitter shutdown function 1 Command word stored 2 Terminal flag bit set zero and assertion 1 00111 enabled 1 01000 section information 1 01001 01111 1 10000 to outgoing the 1 10001 RT Mode Override Inhibit Terminal Flag Reset Remote Terminal Reserved Transmit Vector Word Reserved 70 Status word transmitted Command Word stored 2 Terminal flag bit for assertion Status word transmitted Command word stored Status word transmit
109. ot check ME or SSYSF of the transmitting remote terminal when receiving 6 2 8 Terminal Address The EXC 1553VME MCH Terminal Address is programmed via the most significant six bits in the Operational Status Register RTA 4 0 and RTAPTY The Terminal Address parity is odd RTAPTY is set to a logic state to satisfy this requirement Assertion of Operational Status Register bit 2 TPARF indicates incorrect Terminal Address parity For example RTA 4 0 05 H 00101 RTAPTY 1 H 1 Sum of 1s 3 odd Operational Status Reg Bit 2 0 RTA 4 0 04 H 00100 RTAPTY 0 H 0 Sum of 1s 1 odd Operational Status Reg Bit 2 0 RTA 4 0 04 H 00100 RTAPTY 1 H 1 Sum of 1s 2 even Operational Status Reg Bit 2 1 Notes The EXC 1553VME MCH checks the Terminal Address and parity after RT mode operation has been started With Broadcast disabled RTA 4 0 11111 operates as a normal RT address The BIT Word Register parity fail bit is valid after RT mode has been started 6 2 9Reset The softwar reset s Channel Reset Register is also equivalent to a F hardware power on reset and takes 5 usec to complete Assertion of reset results in th immediat reset of the channel and termination of command processing The user is responsible for the re initialization of the RT Mode for operation
110. pler devices are available from a number of manufacturers North Hills Electronics Inc supplies a three stub coupler PN DB30010 as well as 78 ohm terminators PN RT500078 Two terminators are required for each coupler which services a single bus e g BUS A Figure 2b shows how 1553 devices may be connected in Transformer Stub mode to other 1553 device Hi Hi EXC 1553VME MCH 1553 Device Transformer Coupled Transformer Coupled Lo Lo s A s B s 6 Terminator Terminator 78 ohm Three Stub Coupler 78 ohm Figure 2b Transformer Coupled Connection One Bus Shown 3 0 VME VXI INTERFACE The EXC 1553VME MCH complies with the following VME VXI parameters VME parameters Board type SLAVE Addressing A16 and A24 A32 Data D16 Interrupts IRQ1 7 DO8 0 ROAK VXI parameters Device Class Register Based Manufacturer ID 3924dec F54H Address Space A16 A24 or A16 A32 Required Memorv 512K m 0100 A24 1100 A32 Model Code 1363dec 553H The board interfaces to the VME via a 16 bit data bus Note to the card must be Word accesses 16 bits All bvte ignored The board mav be accessed bv using addresses in the For accessing VME VXI Configuration registers XXXX H A16 mode with ADDRESS MODIFIER CODES 29 For a
111. processing is complete 10 1 reserved Ignore on read 0 MBC Bus Monitor Block Counter Interrupt This bit is set if the EXC 1553VME MCH s monitor block counter reaches zero transition from 1 to 0 It should be noted that the Bus Monitor does not discriminat between rror Er messages and those messages with errors 6 3 1 6 Interrupt Log List Pointer Register 000A H Read Write This register indicates the starting address of the Interrupt Log List The Interrupt Log List is a 32 word ring buffer that contains information pertinent to the service of interrupts The EXC 1553VME MCH architecture requires the location of the Interrupt Log List on a 32 word boundary The most significant 11 bits of this register designate the location of the Interrupt Log List within a 64K memory space Initialize the lower five bits of this register to a logic zero The EXC 1553VME MCH controls the lower five bits to implement the ring buffer architecture This register is read to determine the location and number of interrupts within the Interrupt Log List least significant five bits Bit Name Description 15 0 ILLP 15 0 Interrupt Log List Pointer Bits Note Bits 5 5 indicate the starting Base address while bits 4 0 indicate the ring location of the Interrupt Log List BM Mode 79 6 3 1 7 BIT Word Register 000C H Read Write This register contains information on the current health of the channel s hardware The lower 8 bits of this register are
112. rd to the reflected decoder word by way of the continuous loop back feature If the encoder word and reflected word do not match the WRAPF bit asserts The loop back path is via the MIL STD 1553 bus transceiver 13 reserved Ignore on read 12 BITE BIT Fail Assertion of this bit indicates a B I T failure Interrogate bit 11 and 10 to determin th specific bus that failed 11 BUAF Bus A Fail Assertion of this bit indicates a B I T failure in Bus A 10 BUBE Bus B Fail Assertion of this bit indicates a B I T failure in Bus B BC Mode 19 Bit Name Description 9 MSBF Memory Test Fail Most significant memory byte failure 8 LSBF Memory Test Fail Least significant memory byte failure 7 0 UDB 7 0 User Defined Bits 6 1 1 8 Minor Frame Timer Register 000E H READ ONLY The Minor Fram Timer Register MFT reflects the state of the 16 bit MET counter This counter is loaded via the Load Minor Frame Timer opcode Opcode 1110 For user defined counter resolution use PTCE bit Control Register bit 10 Bit Name Description 15 0 MFT 15 0 Minor Frame Timer These bits indicate the value of the timer 6 1 1 9 Command Block Pointer Register 0010 H Read Write This register contains the location to start the Co
113. rds 6 2 3 3 2 Mode Code Transmit Information Info Word The following bits describ Bit Name 15 11 MC 4 0 Mod 10 reserved 9 BUA B Bus 8 reserved il ME 6 5 reserved 4 ILL 3 reserved 2 OVR 1 0 reserved RT Mode the Mode Cod Transmit Information word contents A B Description Cod Thes five bits contain the mode code information extracted from the command word bit times 15 to 19 Ignore on read Assertion of this bit indicates that the message was received on bus A Conversely if this bit is set to logic zero the message was received on bus B Ignore on read Message Error Assertion of this bit indicates a message error condition was observed during processing See bits O to 4 for details Ignore on read Illegal Command Received Assertion of this bit indicates the command received was an illegal command Ignore on read Overrun Error Assertion of this bit indicates th EXC 1553VME MCH received a data word with a Transmit Command Ignore on read 59 6 2 4RT Circular Buffer Modes fl and 2 The RT circular buffer modes simplify the software service of remote terminals implementing bulk or periodic data transfers The user selects the preferred mode at start up by writing to Control Register bits 7 and 8 see Control Register above The two modes Mode fl and Mode 2 are discussed in f
114. remote terminal complements bit 2 of the Descriptor Control Word to access the alternate buffer on the following message i e ping pong To off load or load the subaddress and mode code buffers without collisions e g remote terminal writing and application software reading the same buffer the application software must disable ping pong operation i e freez th remot terminal access to a single buffer either A or B Disabling ping pong operation allows the application software to off load or load the alternat buffer whil th remot terminal continues to use the active buffer To implement this architecture ping pong operation must enable and disable asynchronously via software with feedback to indicate that buffer ping ponging is truly disabled Second unique subaddress and mode code flags indicate which buffer is active Each unique subaddress and mode code is assigned a flag which indicates the active buffer To begin the process of off loading or loading th remot terminal s subaddress and or mode code buffers when using the ping pong feature th application software performs the following sequences disables ping pong operation determines the active buffer service the alternate buffer enables ping pong operation RT Mode 51 The application software disables ping pong operation by writing a logical zero to Control Register bit 2 The disable of ping p
115. ress with the descriptor base address subaddress or mode code information IAW contains made by comparing the identifier 91 Interrupt If a match If no 6 4 3 Interrupt Log List Address The interrupt log list resides in a 32 word ring buffer The host defines the location buffer within the memory space via the Interrupt Log List Register Restrict the ring buffer address to a 32 word boundary During initialization the user writes a value to the Interrupt Log List Pointer Register Initialize the least significant five bits to a logic zero The most significant 11 bits determine the base address of the buffer The EXC 1553VME MCH increments the ring buffer pointer on the occurrence of the first interrupt storing the W and IAW at buffer locations 00H and 02H respectively The EXC 1553VME MCH logs ensuing interrupts sequentiallv into the ring buffer until interrupt number 16 occurs The EXC 1553VME MCH enters interrupt 16 s W in buffer location 3CH and the IAW at location 3EH The EXC 1553VME MCH increments the ring buffer pointer as interrupts occur The least significant five bits of the Interrupt Log List Pointer Register reflect the ring buffer pointer value Figure 24 shows the ring buffer architecture The user reads the ring buffer pointer value to determin t
116. rminal Flag bit set Bit time 1553A mode This condition is met if the EXC E MCH detects that the RT s status word has the Terminal Flag bit set Status 17 in 553VMI Word Response with the Subsvstem Fail bit set Bit time 1553A mode This condition is met if the EXC E MCH detects that the RT s status word has the Subsystem Fail bit set Status time 1 Word Response with the Instrumentation bit set Bit O in 1553A mode This condition is met if the EXC 553VMI E MCH detects that the RT s status word has the Status time 1 Instrumentation bit set Word Response with the Service Request bit set Bit 1553VMI l in 553A mode This condition is met if the EXC E MCH detects that the RT s status word has the Service Request bit set 1553 Command Words The next two locations of the BC Mode Command Block are for 1553 command words In most 1553 initialized However Receive Command and the second command word is the Transmit Command BC Mode messages only the first command word needs to be in an RI RT transfer the first command word is the 25 6 1 2 3 Data Pointer he fourth location of the BC Mode Command Block is the data pointer that oints to the first memory location to store or fetch the data words ssociated with the message for that command block This data structure allows he EXC 1553VME MCH to store or fet
117. rol Registers for RT MOde iss i sa 31 AO Description of RT Mode Control Registers 32 sa Coftit il REGUS ters ii td ls je cot eld Md tr drajt aw ew age 32 2 1 2 Operational Status RegliStel oooooooooooooooo o 33 FO rLbe3 Current Command REGIS Bee aristides eee 35 2 1 4 ihtertupt Mask Register vori ei ee aia 35 DAL Pending Interrupt Registel o oooooooooooooooo o 35 2 1 6 Interrupt Log List Pointer Register 36 DO g al BLT Word Registradas bs sia ada sess le l das diia 37 22148 Time Tag Register as li 38 Le be 9 RT Descriptor Pointer Registel ooooooooooooo o 38 23 0 1553 Status Word Bats REGESCEC aces bir e aja 38 Dl llle alization Re istltS 1220 io i b oe soda krin e 41 2 2 Descr Ip ptor BLOCK A BT a ior 43 2 2 0 Descriptor Block Control WO AS is ea aaa 45 DIED Receive Control Wordenia ea n e E tia 45 2 2 2 Transmit Control Words sisitan E wa IIS pat e a La at 46 2 2 3 ode Code Receive Control Word oooooooooooo 47 2 2 4 ode Code Transmit Control Word 48 DADA Data Pointer A and B Mode 0 49 DD Ping Pong Handshake Mode 0 50 2 2 6 Broadcast Data Pointer Mode 0 53 2 DATA SEKU EJTTE Si a ae se wl l telat eta 53 LB Subaddress Receive Data o oooooooooooooooooo oo 53 PENE PAR Receive Information Info Word 54 Jee Subaddress Transmit Dates esses cee cee a are Se oe ee 55 PANE Transmit I
118. ror Interrupt All modes 10 SUBAD Subaddress Accessed Interrupt RT Mode 9 BDRCV Broadcast Command Received Interrupt RT Mode 8 XEQO Index Equal Zero Interrupt RT Mode 7 LCMD Illegal Command Interrupt RT Mode 6 reserved Set to 0 5 EOL End of List BC Mode 4 LCMD Illogical Command BC Mode 3 LOP Illogical Opcode BC Mode 2 RTF Retry Fail BC Mode 1 CBA Command Block Accessed BC Mode 0 MBC Monitor Block Count Equal Zero BM Mode 6 4 2Interrupt Address Word IAW The Interrupt Address Word IAW is a 16 bit word that identifies the interrupt source Depending on the mode of operation i e RT BC or BM the IAW has different meanings In the RT mode operation the IAW identifies the subaddress or mode code descriptor that generated the interrupt For the counter count wh Initial Monitor command block tha When in RT Concurrent information for contents of the occurs then the match occurs the Architecture BC mode of operation interrupt occurred the IAW points to the command block addressed when th In the BM mode of operation the IAW marks the monitor n the interrupt occurred The user uses th IAW with the Command Block Pointer Register to determin th monitor t generates the interrupt BM mode BM the RT or the user must determine if the The determination is IAW contains a IAW contains monitor counter IAW base add
119. rs per block see table L Block Name Address H Receive 0020 and 0022 Transmit 0024 and 0026 Broadcast Receive 0028 and 002A Broadcast Transmit Automatically Illegalized 002C and 002E Mode Code Receiv 0030 and 0032 ode Code Transmit 0034 and 0036 Broadcast Mode Code Receiv 0038 and 003A Broadcast Mode Code Transmit 003C and 003E Table 1 RT Illegalization Register Blocks F The blocks correspond to the following types of commands Register address 0020 H and 0022 H illegalize receive commands to 32 subaddresses The most significant bit of register 0020 H controls the illegalization of subaddress 01111 The least significant bit controls subaddress 00000 Register 0022 H controls illegalization of subaddresses 10000 through 11111 The least significant bit relates to subaddress 10000 the most significant bit relates to subaddress 11111 Transmit commands and broadcast commands both receive and transmit us th sam ncoding scheme as the receive subaddress illegalization Register 0030 H through 003E H control the illegalization of mode codes Register 0030 H governs the illegalization of receive mode codes T R bit 0 00000 through 01111 and register 0032 H mode codes 10000 through 11111 Register blocks Transmit Mode Code T R bit 1 Broadcast Receive Mod Codes and Broadcast Transmit Mode Codes us th same decod scheme as the receiv
120. s These bits indicate the state of the 16 bit internal counter 6 3 1 9 Initial Monitor Block Pointer Register 0016 H Read Write This register contains the starting location of the Monitor Blocks Note It is recommended that this register not be changed while the Bus Monitor mode is active i e Operational Status Register bit EX 1 Bit Name Description 15 0 MBA 15 0 Initial Monitor Block Address These bits indicate the starting location of the Monitor Block BM Mode 80 6 3 1 10 Initial Monitor Data Pointer Register 0018 H Read Write This register contains the starting location of the Monitor Data Note It is recommended that this register not be changed while the Bus Monitor mode active i e Operational Status Register bit EX 1 Bit Name Description 15 0 MDA 15 0 Initial Monitor Data Address These bits indicate the starting location of the Monitor Data 6 3 1 11 Monitor Block Counter Register 001A H Read Write This register contains the number of Monitor Blocks the user wishes to log After execution begins this register automatically decrements as commands are logged When this register is decremented from one to zero an interrupt will be generated if enabled The Bus Monitor will start over at the initial pointers as identified in the Initial Monitor Block Pointer Register and the Initial Monitor Data Pointer Reg
121. s bit automatically allows the EXC 1553VME MCH to operate under the MIL STD 1553B protocol See MIL STD 1553A Operation for further information reserved These read only bits are not applicable EX EXC 1553VME MCH Channel Executing This read only bit indicates whether the channel is presently executing or is idle A logic one indicates that the channel is executing logic zero indicates the channel is idle reserved This read only bit is not applicable 16 Bit Name Description 1 RI E ADV Channel Ready This read only bit indicates that the channel has completed initialization or B I T This bit is cleared on reset 0 TERACT Channel Terminal Active This read only bit indicates that the channel is presently processing a 1553 message This bit is cleared on reset Note When STEX transitions from 1 to 0 EX and TERACT stay active until command processing is complete 6 1 1 3 Current Command Register 0004 H READ ONLY This register contains the last 1553 command that was transmitted by the EXC 1553VME MCH Upon the execution of each Command Block this register will automatically be updated This register is updated when transmission of the Command Word begins In an RI RT transfer the register will reflect the latest Command Word as it is transmitted Bit Name Description 15 0 CCI15 0 Current Command These bits
122. so remaines static during message processing The third descriptor block words represent the current address 1 e CA in the buffer and is dynamic If the EXC 1553VME MCH observes no message error conditions the CA pointer updates at the end of message processing The application software reads the dvnamic CA pointer to determine the current bottom of the buffer T b he TA top of buffer and BA bottom of buffer pointers define the circular uffer s length The CA pointer identifies the current address i e last accessed address plus one The circular buffer wraps to the top address after completing a message that results in CA being greater than or equal to BA If CA increments past BA during intra message processing the EXC 1553VME MCH will access memory read or write address locations past BA Delimit all circular buffer boundaries with at least 34 address locations Note In this mode of operation bits INDX N and A B of the descriptor Control Word and the PPEN bit of the Control Register are don t care RT Mode 60 6 2 4 1 2 Mode 1 Circular Buffer First a review of receive message processing The EXC 1553VME MCH begins all message processing by reading a unique descriptor block after reception and validation of a subaddress or mode code command word The EXC 1553VME MCH
123. ted 3 RT Mode reset s Reset for more on software reset Command word stored Status word transmitted Command word stored Service request bit set a logic zero in status Status word transmitted Data word transmitted Clears the SRQ bit in 1553 Status Word Bits Register Command word stored Status word transmitted Data word transmitted T R Mode Code 1 10010 transmitted transmi is all the Command illegalized word 1 10011 from 1 10100 10101 1 10110 11111 RT Mode Function Operation Transmit Last Command 1 Command word not stored 2 Last status word 3 Last command word tted 4 Data word stored Transmit Last Command 5 Transmitted data word zero after reset Note The RT Mode stores Transmit Last mode code if and updates status Transmit BIT Word 1 Command word stored 2 Status word transmitted 3 BIT word transmitted BIT Word Register 4 Data word stored Transmit BIT Word Undefined with data 1 Command word stored 2 Status word transmitted 3 Data word transmitted Reserved 1 Command word stored 2 Status word transmitted 71 3 Data word transmitted 6 2 6Encoder and Decoder The EXC 1553VME MCH receives the command word from the MIL STD 1553 bus and processes it either by the primary or secondary decoder Each decoder checks for the proper sync pulse and Manchester waveform
124. ted to the non occupied channels General 12 the space which are E VXI Configuration Registers The is divided into memory locations 5 0 CHANNEL GENERAL OPERATION The description of operation of the EXC 1553VME MCH which follows each available 1553 channel This area is shared between th Channel used for message control Channel Register Block used for various control and the Channel Reset Register used for Channel 6 A powerful RISC processing unit U controller provides automatic message handling operational status and interrupt information all control registers and data blocks in Real Time and control il Std 1558 operation of the card bv accessing the Ram 1553VME MCH mav be configured to support 1553A protocol applies to Each channel occupies a 32K words area of the board s Memorv Address Space emorv Block data and registers registers CHANNEL RESET REGISTER FREE reserved FFFC FFFA CHANNEL MEMORY BLOCK 1553 Message Storage Control Data Storage 0040 003 ti CHANNEL REGISTERS BLOCK Control Registers 32 registers 0000 Figure 6 Channel Memory Map 5 1 Channel Reset Register FFF E H Writing to this register data don t care channel The channel will act as if POWER reset op
125. test 1553 command word that was received by the Bus Monitor 6 3 1 4 Interrupt Mask Register 0006 H Read Write The EXC 1553VME MCH interrupt architecture allows the host to mask or temporarily disabl th servic of interrupts While masked interrupt activity does not occur The unmasking of an interrupt after the event occurs does not generate an interrupt for that event An interrupt is masked if the corresponding bit of this register is set to logic zero Bit Name Description 15 12 reserved Should be set to O 11 MERR Message Error Interrupt 10 1 reserved Should be set to O 0 MBC Monitor Block Counter Interrupt BM Mode 78 6 3 1 5 The pending Pending Interrupt Register interrupt 0008 H R EAD ONLY register is used to identify which of the interrupts occurred during operation read Bit 15 12 reserved Name Note that all register bits are cleared on a host Description Ignore on read 11 MERR Message Error Interrupt This bit is set if a message error occurs The Bus Monitor can detect Manchester sync field word count 1553 word parity bit count and protocol errors This bit will be set and an interrupt generated after message
126. the Control Register Negation of this bit automatically allows the EXC 1553VME MCH to operate under the MIL STD 1553B protocol 6 4 reserved These read only bits are not applicable 3 EX EXC 1553VME MCH Channel Executing This read only bit indicates whether the channel is presently executing or is idle A logic one indicates that the channel is executing logic zero indicates the channel is idle 2 TPARF Terminal Parity Fail This bit indicates the observance of a terminal address parity error The EXC 1553VME MCH checks for odd parity This read only bit reflects the parity of Operational Status Register bits 15 10 1 READY Channel Ready This read only bit indicates that the channel has completed initialization or B I T This bit is cleared on reset 0 TERACT Channel Terminal Active This read only bit indicates that the channel is presently processing a 1553 message This bit is cleared on reset Note Remote Terminal Address and Parity are checked on start of execution RT Mode 34 6 2 1 3 Current Command Register 0004 H READ ONLY This register contains the last valid 1553 command processed by the EXC 1553VME MCH Bit Name Description 15 0 ccr15 0 Current Command These bits contain the latest valid 1553 command that was received by the EXC 1553VME MCH This register is valid 13 usec after TERACT is negated 6 2 1 4 Interrupt Mask Register 0006 H Read Write The EXC 1553VME MCH i
127. tion word and time tag word into the MIB for each message until the end of the MIB is reached When the MIB reaches th nd the next message s message information word and time tag word is entered at the top of the MIB The MIB pointer is a semi static pointer The EXC 1553VME MCH updates the current address field at the end of message processing The base address field remains static Note In this mode of operation bits INDX N and A B of the descriptor Control Word and the PPEN bit of the Control Register are don t care RT Mode 63 6 2 4 2 2 Mode 2 Circular Buffer First is a review of recelv The messag processing all message processing by reading the descriptor block of the mode code command received in the CA pointer The internally as message number of data words the the specified MIB zero If CAF is the next available memory length Toe 1553VME MCH begins storage of data word s EXC 1553VMI processing progresses EXC 1553VME MCH stores th and time tag word into the MIB 1553VME MCH updates CA and the M CA is updated to TA and the M less than the specified MIB location Control Word TA CA EXC 1553VM E MCH begins subaddress or and MIB starting at the location containe
128. tions 0101 Execute Block Branch This opcode instructs the EXC 1553VME MCH to xecute the current command block and unconditionally branch to the location as specified in the branch address location 0110 Execute Block Branch on Condition This opcode instructs the EXC 1553VME MCH to execute the current command block and branch only if the condition is met If no conditions are met the opcode appears as an execute and continue 0111 Retry on Condition This opcode instructs the EXC 1553VME MCH to perform automatic retries as specified in the control word if particular conditions occur If no conditions are met the opcode appears as an execute and continue 1000 Retry on Condition Branch This opcode instructs the EXC 1553VME MCH to perform automatic retries as specified in the control word if particular conditions occur If the conditions are met the EXC 1553VME MCH retries Once all retries have executed the EXC 1553VME MCH branches to the location specified in the branch address location If no conditions are met the opcode appears as an execute and branch BC Mode 23 Opcode 1001 1010 1011 1100 1101 1110 LLEL Definition Retry on Condition Branch if all Retries Fail This opcode instructs the EXC 1553VME MCH to perform automatic retries as specified in the control word if particular conditions occur If the conditions are met and all the retries fail the EXC 1553VME MCH branches to the locati
129. ved Assertion of this bit enables the generation of an interrupt when the subaddress receives a valid broadcast command The interrupt is entered into the Pending Interrupt Register if not masked in the Mask Register An interrupt is generated after message processing Block Accessed The host initializes this bit to zero the EXC 1553VME MCH overwrites the zero with a logic one upon completion of message processing After interrogating this bit the host resets this bit to zero to observe further accesses Should be set to O 46 Bit 6 2 2 2 Name A B BRD Description FE Buffer A B ndicates the last buffer accessed when buffer ping pong is enabled During initialization the host designates the first buffer used bv asserting or negating this bit A logic one indicates buffer A a logic zero indicates buffer B This bit is a don t care if buffer ping ponging is not enabled Broadcast Received Assertion of this bit indicates the F reception of a valid broadcast command Notice Assertion of this bit nables the us of the Broadcast Data Pointer as a buffer for broadcast command information When negated broadcast information is stored in the same buffer as non broadcast information Transmit Control Word The following bits describe the transmit subaddress descriptor Contro
130. welve interr into the Interrupt Log F Lets upt bits of the Pending Int List if the errupt Register ar ntered Interrupt Log List is enabled The interrupt architecture allows for t word ring buffer see figure 24 The handles the interrupt logging overhead information to assist interrupt occurred e g subaddress or command block the Identification Word host EXC 1553VMI he entry of 16 interrupts into a 32 E MCH channel automatically Each inter in performing W identifies th rupt generates two words of interrupt processing The tvpe s of interrupt that The Interrupt Address Word Interrupt Architecture 90 IAW ident via a 16 bit address ifies th interrupt source 6 4 1 Interrupt Identification Word IIW The Interrupt Identification Word IIW is a 16 bit word identifying the interrupt type The format is similar to the Pending Interrupt Register The host reads the W to determine which interrupt event occurred The bit description for the W is provided below Bit Name Description 5 12 reserved Set to O 11 MERR Message Er
131. word 0204 H FFFF data word 1 0206 H FFFF data word 2 0208 H FFFF data word 3 Note Data Pointer A points to the top of the data structure not to the top of the data words 6 2 3 2 1 Transmit Information Info Word The following bits describe the Transmit Bit 15 11 9wWC 4 0 10 RT Mode Name reserved BUA B Bus reserved ME E reserved ILL reserved OVR reserved Word Information word contents Description Count Bits These five bits contain word count information extracted from the receive command word bit times 15 to 19 Ignore on read A B Assertion of this bit indicates that the message was received on the A bus Conversely if this bit is set to logic zero the message was received on the B bus Ignore on read Message Error Assertion of this bit indicates a message error condition was observed during processing See bits O to 4 for more detail Ignore on read Illegal Command Received Assertion of this bit indicates the command received was an illegal command Ignore on read Overrun Error Assertion of this bit indicates the EXC 1553VME MCH received a data word with a Transmit Command Ignore on read 57 6 2 3 3 Mode Code Data The transmit and receive data structures for mode codes are similar to those for subaddress The receive data structure contains an Informat
132. xplanation of the VXI Configuration registers and other topics relating to F operation of the VXI bus refer to the VXI Bus System Specification 3 1 1Configuration Register Memory Map PROGRAMMABLE TIMER CLOCK REG BASE 30 H VECTOR 7 REGISTER BASE 2E H VECTOR 6 REGISTER BASE 2C H VECTOR 5 REGISTER BASE 2A H VECTOR 4 REGISTER BASE 28 H VECTOR 3 REGISTER BASE 26 H VECTOR 2 REGISTER BASE 24 H VECTOR I REGISTER BASE 22 H VECTOR 0 REGISTER BASE 20 H OFFSET REGISTER BASE 06 H STATUS CONTROL REGISTER BASE 04 H DEVICE TYPE REGISTER BASE 02 H D REGISTER BASE 00 H Figure 3 Configuration Registers Map VME VXI Interface 3 1 2ID Register VXI only BASE 00 READ ONLY The contents of this 16 bit register provides the following information about the board s configuration 0 il A32 ADDRESS SPACE JP33 not installed 0 0 A24 ADDRESS SPACE JP33 installed 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 0 1 0 1 0 1 0 0 DEVICE CLASS MANUFACTURER ID F54 Hex 3924 Dec

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