MAXVME-6400TM User Manual
Contents
1. Technologies Figure 1 1 6400 Block diagram IP0 VME P2 IP1 Back Plane IP2 Rear UO VME P0 IP3 IRIG Circuit optionnal IRIG Signal Sync In Out FLASH SDRAM 5 optionnal optionnal VCXO Page 9 MAXVME 6400 User Manual Rev 1 2 CHAPTER 2 ON BOARD HARDWARE SPECIFICATION 2 1 Timer and Synchronization The MAXVME 6400 has a 1 us resolution 64 bit free running counter as main timer This free running counter is accessible via the 64BIT COUNTER registers 2 1 1 System synchronization Many or a single MAXVME 6400 and the IPs on them can have their timer synchronized in phase and frequency with or without an external reference To do so the MAXVME 6400 cards must be daisy chained using their input and output synchronization ports SYNC IN SYNC OUT The resulting daisy chained scheme is used to propagate the reference and synchronization symbols from the first card of the chain to the last one This important feature gives the opportunity to have the same time base over a complete system with a simple coax or twisted pair wire from a MAXVME 6400 to another 2 1 1 1 Slave card The slave state is reached when the card detects reference symbols from a master card on its SYNC IN port The selected reference source must be the SYNC IN port The reference source 18 selected with REF SRC bit of the GENERAL CTRL register see section 4 2 12. when selected by BASE EN Not NotUsed Those bits give the base address for A32 mapping when selected by BASE EN 0 Disabled OxXX 0 Disabled 0x0 Technologies Rev 1 2 MAXVME 6400 User Manual 4 2 1 9 Temperature sensor data 0x0028 0x002C The MAXVME 6400 is equipped with 4 temperature sensors The values of the sensors are continuously read by the FPGA and the result is presented in the following registers Reset Value 12 0 R IPA_TMP Temperature 0x0000 This value gives the temperature with a precision of 0 5 from 55 to 128 C 127 5 C 0111 1111 1111 0 5 0000 0000 0001 0 C 0000 0000 0000 0 5 C 1111 1111 1111 128 1000 0000 0000 14 13 15 Error flag Occurs when the sensor is not responding 31 16 IPB_TMP 0x0000 47 32 IPC TMP 0 0000 63 48 TMP 0 0000 4 2 1 10 IRIG B correlation timer 0x0030 0x0034 This register presents the correlation between the optional IRIG B time and IMHz card counter When the IRIG B data register below is accessed the timer register is latched and presented in this register This will give to the user the correlation between the IRIG B time and the lus precision counter 63 32 IRIG CORR 32 bit High correlation counter 0x00000000 IRIG CORR 32 bit Low correlation counter 0x00000000 4 2 1 11 IRIG B data 0x0038 This register shows the last set of information the IRIG B decoder has captured If
3. 08 cycles 1 byte VME64 0 84 048 CR CSR Space Specification ID 1 byte VME64 Ox1F 0x43 ASCII C 1 byte VME64 4 0x23 0x52 ASCII R byte VMEG4 0x27 0 2 Ox2F Manufacturer s ID IEEE OUI 3 bytes VME64 0x00 0x00 0x00 Ed Mises eoneopenpe Ox3F Board ID supplied by manufacturer 4 bytes VME64 0 09 0 00 0 00 0 00 Rai NEQNE RR Ox4F Revision ID supplied by manufacturer bytes VME64 0x01 0x00 0x00 0x00 Pointer to a null terminated ASCII 0x53 0x57 0x5B printable string or 0x000000 WEN IVME64 kp 0x00 0x00 0x5F to 0x7B 8 bytes tes Al Al oao 9 Ox9F 0xA3__ OffsettoBEG_CRAM B bytes VME64x Slave Characteristics Parameter NN implements P2 connector and uses ETL 77577 TS GE OxFF CRAM ACCESS WIDTH bye MME64x 0x103 Accepts D32 D16 or DO8 E0 cycles 1 byte 4 0x84 0x107 D32 D16 or 08 cycles 1 byte VMEG4x 0 84 la 22002231 2 Data Access Width Gu as mi Ox10B D32 D16 or 08 cycles 1 byte VMEG4x 0 84 Table 4 4 VME6400 CR Page 22 MAX Technologies Rev 1 2 MAXVME 6400 User Manual Address Relevant 6400 LSB Content Size Standard VALUE em 0 AM Code Mask D supervisory and non privileged access 0x00 0x00 0x22 0x00 0x123 OX13F supported 8 bytes jVME64x 0 00 0 00 0 00 0 00 Function 1 AM Code Mask all access type supported in A24 64 bit 0XEE 0x00 0
4. 6 3 ENVIRONEMENTAL Technologies 5 MAXVME 6400 User Manual Rev 1 2 List of Figures Figure 1 1 MAXVME 6400 Block diagram eee 9 Figure 3 1 and Switch positiOn up per udis pp telis For HR dodaci eet te n re ied 14 Figure 3 2 GA base address circuit a eene enne u nennen nein trennen 17 Figure 3 35 SW 1to SW CIECUIL oe Eri ot eter EENS co m deinen EE EE 18 Page 6 MAX Technologies Rev 1 2 MAXVME 6400 User Manual List of Tables Table 2 1 MAXVME 6400 Synchronization configuration and states n n 11 Table 3 1 VME 64x back plane IO 2 15 Table 3 2 VME 64x back plane IO OPO 16 Table 3 3 local base address settings esee eee et e Pe eR Tec ER TEC Pe RH ERE Pe ous 17 Table 3 4 SW1 to SWT d scriptioni 22 DEG e ee te Ra ea huie di di evi 18 Table 3 5 LED Deftrttitions re cer He etg eee o He He pb t ei e rU o etc Eee ah 19 Table 4 1 VME6400 IPack amp Control register Memory Map 20 Table 4 2 VME6400 IPack memory A32 Memory Map 21 Table 4 3 VME6400 IPack memory A24 Memory Map 21 Table 4 4a VME6400 CR e A TOV ge EIN REB RR i oro 22 Tablet PRISE 23 Table 4 5 VME6400 CSR Uu a s us rre p AH ELI E ERU EO EUER E EFIE 24 Table 5 1 Interrupts routing to the VME bus i
5. IPA 1O36 1 35 IPB IO29 P2 24 IPB 1O31 IPA 1O38 IPA IO37 GND P2 25 IPB 1O33 IPA IO40 IPA IO39 IPB IO32 P2 26 IPB 1034 IPA 1O42 IPA IO41 GND P2 27 IPB 1O36 IPA IO44 IPA IO43 IPB IO35 P2 28 IPB 1O37 1046 IPA IO45 GND P2 29 IPB 1O39 IPA IO48 IPA IO47 IPB IO38 P2 30 IPB IO40 IPA IO50 IPA lIO49 GND P2 31 GND 3 3V 3 3V 3 3V P2 32 VPC 5V 5V GND Table 3 1 VME 64x back plane IO P2 MAX Technologies Page 15 MAXVME 6400 User Manual Rev 1 2 Row VME Connector Position f e d b a P0 1 GND IPD IO5 IPD IO4 IPD IO3 IPD IO2 IPD IO1 P0 2 GND IPD IO10 IPD IO9 IPD IO8 IPD IO7 IPD IO6 P0 3 GND IPD IO15 IPD IO14 IPD IO13 IPD IO12 IPD IO11 P0 4 GND IPD IO20 IPD IO19 IPD IO18 IPD IO17 IPD IO16 P0 5 GND IPD IO25 IPD IO24 IPD IO23 IPD IO22 IPD IO21 P0 6 GND IPD IO30 IPD IO29 IPD IO28 IPD IO27 IPD IO26 P0 7 GND IPD IO35 IPD IO34 IPD IO33 IPD IO32 IPD IO31 P0 8 GND IPD IO40 IPD IO39 IPD IO38 IPD IO37 IPD IO36 P0 9 GND IPD IO45 IPD IO44 IPD IO43 IPD IO42 IPD IO41 P0 10 GND IPD IO50 IPD IO49 IPD IO48 IPD IO47 IPD IO46 P0 11 GND IPC IO5 IPC IO4 IPC IO3 IPC IO2 IPC IO1 P0 12 GND IPC IO10 IPC IO9 IPC IO8 IPC IO7 IPC IO6 P0 13 GND IPC IO15 IPC IO14 IPC IO13 IPC IO12 IPC IO11 P0 14 GND IPC IO2
6. sticky bit cleared when 0 Disabled written with a 1 IPXF2 IPC exception flag sticky bit cleared when 0 Disabled written with a 1 IPXF3 IPD exception flag sticky bit cleared when 0 Disabled written with a 1 Page 26 MAX Technologies Rev 1 2 MAXVME 6400 User Manual 4 2 1 3 IP configuration register 0x0008 R W RW R W R W Rw Bit 20 22 24 MAX Technologies 0 Disabled IPA bus width bit 0 IPA bus width bit 1 Bits effect 00 gt 8bit 01 gt 16bit IX gt 32bit fo IPB buswidth bitO LD IPB bus widthbitt LD IPC buswidth bitO LD IPC bus widthbitt do i IPDbuswidthbitO LD i fo e o fo s 0 E Name Reserved IPAWIDTHO IPAWIDTHI IPBWIDTHO IPBWIDTHI IPCWIDTHO IPCWIDTHI IPDWIDTHO IPDWIDTHI IPSPEEDO IPA clock set 0 8 MHz 1 32 MHz Counter value at interrupt enable IPSPEEDI IPSPEED2 IPSPEED3 N U INTCNT enable Page 27 MAXVME 6400 User Manual Rev 1 2 4 2 1 4 General control Register 0x000C Reset Value ee ee 984 pin of the IPA pin of the IPB pin of the IPC pin of the IPD 4 R W 1 0 Writing a 1 to this bitdeactivatesledQ Ju 5 RW LEDI Writing a 1 to this bit deactivatesled1 0 6 R W LED2 Writing a 1 to this bit deactivates led2 7 R W__ LED3 R W REG LED EN Enables the LED control with the register bit 4 to 7
7. DOCUMENT REVISION Logic Embedded Code PCB Details Revision 1 0 Rev 90001 Rev 1 0 First Release Revision 1 1 Rev 90002 Rev 1 0 Added new LED functionality Revision 1 2 Rev 90002 Rev 1 0 Minor syntax corrections MAX Technologies Page 3 MAXVME 6400 User Manual Rev 1 2 Table of Contents Table of eases 4 IS EH RRE 8 GENERAL INTRODUCTION de etti ee teet paiay 8 GE A s a eto arie rp arid e 8 CHAPTER 2 a a uq u e ee e d EUR E ee P I A e TELE e Per Dr ER ER c E dE 10 ON BOARD HARDWARE SPECIFICATION nnne nennen 10 2 1 Timer and Synchronization sc a Ae ene E 10 2 Asli System sytichronization sce eR Has Eek A ae 10 2 1 1 Slave Card asa cde ee I ete cnp dere cred ure u a etai kaa qa k h 10 2 1 1 2 Master with internal reference card n 10 2 1 1 3 Master with external reference Card 10 2 1 1 4 Master with SYSCLK reference car 11 2 1 1 5 Optional IRIG B synchronization 12 21 16 Timer synchronization ee EE E O a 12 2 2 Interrupt Time Tag EEE aS Re e e e eee ere EE sees 13 2 3 Optional t 15VDCDQ i eee pee EU RIEN END ep Ene Pero P e 13 2 4 l emperature SensSoE er
8. The default led signification is explained in section 3 2 10 13 9 1 U Not Used IRIG TTL EN IRIG B TTL input enable 15 R W IRIG TTL 1 5 IRIG B TTL configuration When set to 0 the IRIG B source is the TTL input when set to 1 the TTL input is a IPPS signal used in conjunction with the IRIG B AM input 23 16 R W XO CAL Calibration value for the VCXO Reset value is in the middle of the frequency range When the card PLL is not referenced to any source so that it is in the master mode 2 When 0 External reference or SYSCLK IRIGB ENABLE When 1 VME SYSCLK is selected SYNC_DONE Card synchronization done status sticky bit 0 Disabled cleared when written with a 17 MSTR SLA When 1 card is master When 0 card is slave Master means that the board generates clock and reset for other boards d z E 2 Z ci IN Ni 4 2 1 5 64 bit timer register 0x0010 and 0x0014 Name Reset Value 63 32 R COUNT High 32 bits of the 64BIT COUNTER at 1 MHz 0x00000000 This is the main timer of the carrier board 31 0 R COUNT Low 32 bits of the 64BIT COUNTER at 1 MHz 0x00000000 This is the main timer of the carrier board Page 28 MAX Technologies Rev 1 2 MAXVME 6400 User Manual 4 2 1 6 64 bit counter value at last IP interrupt 0x0018 and 0x001C Reset Value 63 32 R INT_COUNT This register gives the High value of the 0x00000000 64BIT COUNTER stored in the FIFO at the
9. 4 In this state INT REF of the GENERAL CTRL register is set to 0 because the clock reference is external 2 1 1 2 Master with internal reference card This master state is reached when the card does not detect an external reference or reference symbols and when the selected reference source is the SYNC_IN port Then the card uses its own VCXO for reference symbol generation on its SYNC_OUT port Consequently the slave card attached to the master SYNC_OUT port locks its VCXO to the master VCXO In this state INT_REF of the GENERAL CTRL register is set to 1 because the clock reference is internal The VCXO of the master card can be calibrated for a specific operating temperature Note that the MAXVME 6400 VCXO has a temperature stability of 25 PPM over all the specified operating temperature range The VCXO has a pulling range of 100 PPM The XO CAL 8 bit value of the GENERAL CTRL register section 4 4 8 is used to calibrate the VCXO frequency Writing a value to those bits will pull the VCXO to a corresponding frequency 0x00 is pulling the VCXO down to the slowest frequency and OxFF is pulling the VCXO up to the highest frequency 2 1 1 3 Master with external reference card Page 10 This master state is reached when the card detects an external IMhz clock on its SYNC IN port but no reference symbols The reference source is selected with the REF SRC bit of the GENERAL CTRL register see section 4 4 8 When a master card de
10. Interrupt mask register 0 0000 nnne nennen 26 4 2 1 2 Interrupt flag register OXO004 enne nnne 26 4 2 1 3 IP configuration register 0x0008 27 4 2 1 4 General control Register 0x000C u an ua usa aD huahana a 28 4 2 1 5 64 bit timer register 0 0010 and 0x0014 n nuansa 28 4 2 1 6 64 bit counter value at last IP interrupt 0x0018 and 0x0010C sse 29 4 2 1 7 VME control OS0020 nennen nennen NN nnne I U u 30 4 2 1 8 A32 A24 IPMEMCONTROL control register 0x0024 sss 30 4 2 1 9 Temperature sensor data 0x0028 0x002C n enne nnne 31 4 Technologies Rev 1 2 MAXVME 6400 User Manual 4 2 1 10 IRIG B correlation timer 0 0030 0 0034 31 4 2 VAL IRIG B data x0038 l au G sO maa anqa Ite ttt aa umawa EE asa 31 4 2 1 12 Model and Revision register SOUCHE 32 4 2 1 13 User defined register 0 0070 0 7 32 4 2 1 14 User 128 bytes 0x0080 0x00FC essere enne nnne enne 32 CHAPTER Su bs cic eve usd ede e e e eo ed e ee Rn Re Ede ee dene ede re ee e Ros 33 INTERESSE A et EE ver aite e eb i ds 33 SM eR reta eere e u u eee tad e ua a aes 33 CHIA NEE 34 SIN DEI LLN RER 34 61 M 34 ee EC 34
11. be changed through the CSR Note also that if you can modify the A32 and A24 base address access by the CSR the system most stil enable it in the A32 A24 IPMEMCONTROL CSR Address Content Size Relevant 6400 Standard Value CR CSR BAR Base Address Ox7FFFF Register set by GA 1 byte VME64 DxGA Ox7FFFB Bit Set Register 1 byte VME64 All 0x00 Ox7FFF7 Bit Clear Register H byte VME64 All 0x00 7 CRAM_OWNER Register 1 buts VME64x All 0x00 Ox7FFEF User Defined Bit Set Register MEE All 0x00 Ox7FFEB User Defined Bit Clear Register 1 byte 64 All 0x00 Ox7FFES Ox7FFE7 me e besen nn jme Ox7FF93 0x7FF9F Function 3 ADER 4 bytes VME64x en come e 17 Dien rn Ox7FF83 OX7FF8F 4 bytes 4 0x00 0x00 0x00 0x00 EE Ox7FF73 OXYFF7F address 4 bytes VME64x 0x00 0x00 0x00 0x00 en ze Milia er US Ox7FF63 OXYFF6F address 4 bytes VME64x 0 00 0 00 0 0x00 Ox7FCOO Ox7FF5F RESERVED 16 bytes VMEGAx 1 0 Geographical address reed 2 ADER Address Decoder compare register The default is that A16 ADER will be set by the GA but it may be modified by the user Only the byte marked with an asterisk are relevant and can be modified See also ADEM in CR AM mask is not supported yet all access mode type are supported by default Table 4 5 VME6400 CSR Page 24 MAX Technologies Rev 1 2 MAXVME 640
12. the TTL output corresponds exactly to the Pr point When using an AM IRIG B signal the decoder circuitry and logic will synchronize on the zero crossing of the beginning of the Pr point of the AM modulated signal This zero crossing of the low frequency AM modulated signal is not as accurate as the TTL 1 5 signal So the user may use a 1PPS signal on the TTL input to improve synchronicity when using the IRIG B AM signal or compensate Note that when the card is in the SLAVE state the IRIGB ENABLE is ignored and the card 18 synchronized with the MASTER card Note that the IRIG B signal should be standard amplitude modulated IRIG B signals in the range of 0 1 to 10 Vpp Both signal and ground IRIG B pins must be connected for correct decoding The decoded IRIG B data and the registered value of the 64 bit timer are available for correlation between the two timing methods See register section for detail 2 1 1 6 Timer synchronization The timer present on some IP modules as well as the 64 bit free running counter of the MAXVME 6400 can all be synchronized in phase The RST CNT bit of the INTERRUPT MASKS register section 4 2 1 1 resets the free running counter and also sends a 0 125 us low pulse on the IP STROBE lines that may be used to reset IP modules timers When writing 1 to the RST CNT bit of the master card a reset symbol is generated to the SYNC OUT port and consequently all over the cards chain The detection of this rese
13. 0 IPC IO19 IPC IO18 IPC IO17 IPC IO16 P0 15 GND IPC IO25 IPC IO24 IPC IO23 IPC IO22 IPC IO21 P0 16 GND IPC IO30 IPC IO29 IPC IO28 IPC IO27 IPC IO26 P0 17 GND IPC IO35 IPC IO34 IPC IO33 IPC IO32 IPC IO31 P0 18 GND IPC IO40 IPC IO39 IPC IO38 IPC IO37 IPC IO36 P0 19 GND IPC IO45 IPC IO44 IPC IO43 IPC IO42 IPC IO41 Table 3 2 VME 64x back plane IO P0 3 2 3 J1 J2 15V select The 6400 offers the possibility to change the regular 12V supplied by the VME chassis to the IP modules by an optional 15V from DC DC converters The jumper J1 and J2 are used to select between the two values The default configuration is that the board comes without the DC DC converter and jumper are replaced by a shut wire on the 12V side If the DC DC are in place the jumper are set on position 12V by default Note that every IP modules are linked to the same power source therefore the user must be very careful when using 15V 3 2 4 JP1 Reserved for internal use 3 2 5 JP2 Used for backward compatibility with older MAXT Ipack carrier card synchronization Connect pin 7 amp 8 for referential SYNC IN in correlation with SW4 The rest of JP2 is reserved for internal use 3 2 6 JP3 Reserved for internal future use 3 2 7 JP4 This jumper is used to supply the 3 3V from the 5V power source when using the MAXVME 6400 in a legacy standard VME card cage This jumper sh
14. 0 User Manual 4 2 CONTROL REGISTERS DEFINITION 4 2 1 Register Summary Address Offset Register name 0x0000 INTERRUPT_MASKS 0x0004 INTERRUPT FLAGS 0x0008 IP_ CONFIGURATION 0x000C GENERAL CTRL 0 0010 0x0014 0 0018 0x001C 0 0020 0x0024 0x0028 0x002C 0x0030 0 0034 0x0038 0x003C 0x0040 0x068 0x006C 0 0070 0 007 0 0080 0 00 Technologies 25 MAXVME 6400 User Manual Rev 1 2 4 2 1 1 Interrupt mask register 0x0000 BEER R W IPVMEMI TREQI to VME interrupt enable 3 IPB INTREQI to VME interrupt enable 6 Iw IPVMEM6 IPDINTREQ0to interrupt enable 0 Disabled E m ua IPD INTREQI to VME interrupt enable 8815 18 NU Notussd 10 R W IPEMO IPA ERROR interrupt enable 0 Disabled 2s UW IPEMT PR ERROR 0 Disabled 26 27 R W IPEM3 IPD ERROR interrupt enable 0 Disabled 28 50 8 NU T re 31 RST_CNT Writing a one to this bit resets the main timer and 0 Disabled the timer of all the IP modules as well as the timer present on other slave carriers Used by the master carrier only See SYNC_DONE bit of the GENERAL CTRL register 4 2 1 2 Interrupt flag register 0x0004 8 JR Pro IPAINTREQOinterruptflag 0 9 JR JJI IPAINTREQI interrupt flag Disabled R 26 IPA exception flag sticky bit cleared when 0 Disabled written with a 1 IPXF1 IPB exception flag
15. 12V to the IP modules Those DCDC can provide up to 260mA per output and are powered by the VME bus 5V The user can choose 15V by setting the and J2 jumpers 2 4 Temperature Sensor The 6400 is equipped with 4 temperatures sensor which are place near each IP module sites and give the possibility to monitor the temperature of the board during operation The temperature is available with a 0 5 C precision See register section for detail MAX Technologies Page 13 MAXVME 6400 User Manual Rev 1 2 CHAPTER 3 PHYSICAL CONFIGURATION amp INSTALLATION 3 1 INTRODUCTION This section covers the physical configuration of the MAXVME 6400 board Page 14 IP position and IO connectors pin out Serial port pin out VME address range setting dipswitches Board to board synchronization port connector Reset button and status LEDs Dip n IPD e di IPB e IPA en J10 21111 5 3 swi 5801 swa swa sws swe sw JP2h TIS VME PO lt 5 2 Figure 3 1 IP and Switch position MAX Technologies Rev 1 2 MAXVME 6400 User Manual 3 2 Connector switch and jumper 3 2 1 IP position Figure 3 1 above shows the position of the 4 IP modules that can support a MAXVME 6400 board Single size IPs may use any of the four slots shown Double size IPs ma
16. ME 64x card 6 3 ENVIRONEMENTAL Operation Temperature 0 55 C Relative Humidity 0 95 non condensing Storage Temperature 55 to 125 C Table 6 2 MAXVME 6400 Environmental Specifications Page 34 MAX Technologies
17. VME64x IP carrier board Document N MANH402 51 6400 User Manual Version 1 2 technologies MAXVME 6400 User Manual Rev 1 2 Copyright 2007 MAX Technologies Inc All rights reserved including those to reproduce this publication or parts thereof in any form without prior written permission from MAX Technologies Inc Printed in Canada MAX Technologies MAXVME 6400 and the MAX Technologies logo are all trademarks of MAX Technologies Inc All other trademarks and registered trademarks are the property of their respective owners Changes are periodically made to the information in this document These changes will be incorporated into new editions of this document MAX Technologies may make improvements and or changes in the products and or programs described in this document at any time MAX Technologies Inc makes no warranties as to the contents of this manual or the accompanying software Although every effort has been made to ensure that the manual is accurate and that the software is reliable MAX Technologies Inc cannot be held responsible for any damages suffered from the use of this product How to reach MAX Technologies for Product Support 7005 Taschereau Blvd Suite 350 Brossard Quebec Canada J4Z 1A7 Tel 450 443 3332 Fax 450 443 1618 Toll free 800 361 1629 www maxt com Page 2 MAX Technologies Rev 1 2 MAXVME 6400 User Manual MAXVME 6400 USER S MANUAL HISTORY
18. et RE i OP eerie dedere ee Rin entra 13 CHAPTER S dad deque do tes 14 PHYSICAL CONFIGURATION amp INSTALLATION 14 SR IR BIER LE EE 14 32 Connector switch and Jumpet deter ae uwa E ERE TG WI 15 ERMNIGIUNCM 15 3 2 2 VME connector IO assignment nn eene nennen ener tnn entere nennen 15 3 2 3 71 52 554 IS V selecti ceo eee Street tUe e MEER Ge eR e REGERE 16 EE 16 BD SIP 2 ss GE Aii e NS kanaa Aes a k a eate 16 3 22 06 ee E ea stn 16 92 aaa E u Ee huu kun E E u td dat 16 3 2 8 Switch S2 A24 CR CSR and A16 Address range sese 17 3 2 9 SW1 SW7 Multi board synchronization port connectors 18 EMISIT 19 CHAPTER EE 20 MEMORY amp IO MAPD 5525 u Sus teo oce e tape e eei bae ee e oer u iie ee s e 20 4 1 6400 MEMORY MAP teet tette ree Re E 20 4 1 1 VME6400 IPack amp Control register Memory Man 20 4 1 2 VME6400 IPack Memory Access 21 4 1 3 VME6400 Geographical Addressing A16 and CR CSR A24 memory access 21 4 2 CONTROL REGISTERS DEFINITION UU ull l l teen tne teen tnt toto tnt to tne tn to ente A tno rot 25 4 2 1 Register Summary c E HR eA e 25 4 2 1 1
19. hing when the IP modules are accessed READ This LED 18 flashing when the IP modules are accessed WRITE Table 3 5 LED Definitions Note that it is possible to control the LED through the General Control Register 0x0C by setting the bit LED EN to one See section 4 2 1 4 MAX Technologies Page 19 MAXVME 6400 User Manual Rev 1 2 CHAPTER 4 MEMORY amp IO MAP 4 1 VME 6400 MEMORY MAP 4 1 1 VME6400 Pack amp Control register Memory Map The VME6400 board uses 32 bit 24 bit and 16 bit address range A32 A24 A16 depending on the resource that is accessed The A32 and A24 base address gives access to the same region only the available range differs The following table presents the different access with their corresponding base address Address Access Range A16 Base 0x0000 IPA I O Space 128 bytes 16 Base 0x007F 16 Base 0x0080 IPA ID Space 32 bytes 16 Base 0x009F Reserved 96 bytes A16 Base 0x0100 IPB I O Space 128 bytes 16 Base 0x017F 16 Base 0x0180 IPB ID Space 32 bytes 16 Base 0x019F Reserved 96 bytes A16 Base 0x0200 IPC I O Space 128 bytes 16 Base 0x027F 16 Base 0x0280 IPC ID Space 32 bytes 16 Base 0x029F Reserved 96 bytes 16 Base 0x0300 IPD I O Space 128 bytes 16 Base 0x037F 16 Base 0x0380 IPD ID Space 32 bytes 16 Base 0x039F Reserved 96 bytes A16 Base 0x0400 VME6400 Register
20. last interrupt edge 31 0 R INT_COUNT This register gives the Low value of the 0x00000000 64BIT COUNTER stored in the FIFO at the last interrupt edge MAX Technologies Page 29 MAXVME 6400 User Manual 4 2 1 7 VME control 0x0020 Function 00000000 Rev 1 2 Reset Value Value Ere MM bus interrupts generation 108 VILEV VME interruptlevel to7 0 O 1 RW VIARM__ VME interrupt armed bit See section 5 1 0 Disabled 12 R W VITYPE VME interrupt type 0 every IP interrupt and error are directly sent to the same VME interrupt level 1 each one of the IP interrupt are sent to a single interrupt level The same VIVECT 15 issued for all IRQ Note that when set to 1 bit 10 8 are ignored IPD INTZ1 is ignored and IP errors are ignored see section 5 1 3123 NU NotUsed Je 4 2 1 8 A32 A24 IPMEMCONTROL control register 0x0024 Reset Value we BASE SEL This register gives to the user the choice between A24 mapping and A32 mapping It has to be used in conjunction with the BASE EN A32 BASE and A24 BASE DE GE Reserved future 28 r pee 19 16 R W 23 20 24 BASE A 25 BASE Page 30 This register enables the access to the A32 or A24 EE space Not U NotUsed Those bits give the base address for A16 access GA if not changed through the CSR Not Used Those bits give the base address for A24
21. no IRIG B signal is fed to the decoder circuitry these registers will remain at their reset value These registers are read only Note IRIG B signals often give Greenwich Mean Time GMT 00 00 Bit Access Function Reset value 3 0 R W Units of seconds 0000 6 4 R W Tens of seconds 000 10 7 R W Units of minutes 0000 13 11 R W Tens of minutes 000 17 14 R W Units of hours 0000 19 18 R W Tens of hours 00 23 20 R W Units of days 0000 27 24 R W Tens of days 0000 29 28 R W Hundreds of days 00 MAX Technologies Page 31 MAXVME 6400 User Manual Rev 1 2 4 2 1 12 Model and Revision register 0x003C REVISION This register gives the revision number 0x0001 31 16 MODEL This register gives the model number 0x0009 4 2 1 13 User defined register 0x0070 0x7C These are general purpose user define registers with no effect They will be reseted to 0 upon a software or hardware reset 4 2 1 14 User RAM 128 bytes 0x0080 0x00FC This is a RAM region for general purpose use Set to 0 on power up it will remain as is on a software or hardware reset Page 32 MAX Technologies Rev 1 2 5 1 INTERRUPTS MAXVME 6400 User Manual CHAPTER 5 INTERRUPTS The MAXVME 6400 card may generate interrupts to the VMEBUS The VME interrupt level generated by the MAXVME 6400 is dynamically selectable and two modes are available In the multiple interrupt mode every IP interru
22. nt plate connector back plane connector and IP IO signals Switch Number Synchronization Signal Front Plate VME Back Correspondin BNC Plane g IP IO Connector Connector SWI IRIGB 1 1 VME P2 C5 IPB 1050 SW2 IRIGB DIGITAL P2 1 VME P2 C30 IPA 1050 SW3 SYNC INL P3 2 VME P2 Z3 1049 SW5 SYNC_IN P3 1 VME P2 D3 IPC 1050 SW6 SYNC OUT L P4 2 VME_P0 D10 IPD_1049 SW7 SYNC_OUT P4 1 VME 10 IPD 1050 Table 3 4 SW1 to SW7 description The remaining switch SW4 is used to select between differential POSO or referential POS1 SYNC_IN and SYNC_OUT signals This is done so that the MAXVME 6400 card can be compatible with old MAX Technologies carrier boards which were referential see also JP2 pin 7 amp 8 Note that when using only MAXVME 6400 cards the users should select differential POSO because of the improved resistance to noise that it offers Page 18 MAX Technologies Rev 1 2 3 2 10 Status LED MAXVME 6400 User Manual When used in a conventional VME card cage the MAXVME 6400 is equipped with four LEDs on the front plate which gives the user the status of the card The following table presents the default signification of each LED LEDI LED2 LED3 LED4 This LED 18 flashing when the card is on This LED is on when ERROR L is received from one of the 4 IP modules This LED 18 flas
23. nterrupt system n sns 33 Table 6 1 VME6400 power requirement enne en rennen inneren nennen 34 Table 6 2 MAXVME 6400 Environmental Specifications essere 34 MAX Technologies Page 7 MAXVME 6400 User Manual Rev 1 2 CHAPTER 1 GENERAL INTRODUCTION 1 1 INTRODUCTION The MAXVME 6400 is an Industry Pack IP carrier board designed to be compliant with the VME 64x and supports the A32 A24 A16 D32 D16 D08 single and block access It supports up to four single width IP modules or 2 double width IP modules where every IP bus has its independent 8MHz or 32 MHz clock Features e 4single 8 or 16 bit or 2 double 32 bit IP sites e Per IP selectable operating frequency 8 or 32Mhz and width 16 or 32 bit no hold cycle e 64 bit timer that can be frequency and phase synchronized between multiple VME 64 carriers and others MAX Technologies carrier boards Temperature sensor IRIG B circuitry Optional 15V instead of regular 12V on IP modules Four status LEDs Page 8 MAX Technologies Rev 1 2 The following figure presents the block diagram of the 6400 board MAXVME 6400 User Manual VME bus VME64 1 2 N AUN Transceiver amp FPGA Quick Switch
24. ould not be placed when used on a standard VME64 card cage default Page 16 MAX Technologies Rev 1 2 MAXVME 6400 User Manual 3 2 8 Switch S2 A24 CR CSR and A16 Address range The MAXVME 6400 support multiple addressing access 16 24 or A32 On power up the board 18 accessible through A16 or 24 CR CSR mode a standard 64 frame system the A16 and CR CSR A24 base address will be defined by the Geographical Address But it is possible to disable the Geographical Address and use a local base address configured by dipswitch The following figure represents the schematics related to the dipswitch bypass and GA settings Switch 52 Mux Demux Bus Switch to FPGA Figure 3 2 GA base address circuit NOTE Each GA lines must be connected to a pull up See VME64x specification On power up the FPGA will access the VME system Geographical Address GA compute the parity and compare the result with the GA Parity read on VME system If valid the VME GA will be kept as the A16 and CR CSR A24 base address If not the local dipswitch settings will be taken even if an invalid address is found a valid GA must have a value between 1 and 21 inclusively Note that it is possible to force the local A16 and CR CSR A24 base address by switching the EN switch to The following table summarizes the definition of the different switches of S2 Switch Number Definition 1 4 Reser
25. pt is routed directly to a VME IRQ line The single interrupt mode will send every IP interrupt lines to the same VME IRQ line selectable through the VME CONTROL 0x0020 register Note that every IP interrupt line must be individually enabled through the INTERUPT MASK 0x0000 register Interrupt mode Interrupt Source VME Interrupt Multiple INTREQO L IRQI L IPA INTREQI L IRQ2 L IPB INTREQO L IRQ3 L IPB INTREQI L IRQ4 L IPC INTREQ0 L IRQ5 L IPC INTREQI L IRQ6 L INTREQO L IRQ7 L INTREQI L unconnected Single Every INTREQx L and One of the L IPx ERROR L Table 5 1 Interrupts routing to the VME bus interrupt system Interrupts to the VME bus are enabled when writing 17 to the VIARM bit in register This bit is automatically cleared during the interrupt acknowledge cycle from the VME interrupt handler At the end of the software interrupt service routine this bit should be written to 1 in order to re arm the card interrupt system to the VME bus MAX Technologies Page 33 MAXVME 6400 User Manual Rev 1 2 CHAPTER 6 SPECIFICATION 6 1 ELECTRICAL Power consumption his established as the carrier board power only It does not include installed IP module power consumption Voltage Current Typical 5V 200 ma 12V 0 ma 12V 0 ma Table 6 1 VME6400 power requirement 6 2 MECHANICAL 6U X 4 HP V
26. s 1024 bytes A16 Base 0 07 and others Table 4 1 VME6400 IPack amp Control register Memory Map Page 20 MAX Technologies Rev 1 2 MAXVME 6400 User Manual 4 1 2 VME6400 IPack Memory Access You may configure the VME 6400 to access the Ipack memory region in A24 or A32 Depending on your need it will give you the possibility to access the totality of the Ipack memory region or use less VME memory space Address Access Range A32 Base 0x01FFFFFF IP D Memory Space 8 Mbytes A32 Base 0x01800000 A32 Base 0x017FFFFF IP C Memory Space 8 Mbytes A32 Base 0x01000000 A32 Base 0x00FFFFFF IP B Memory Space 8 Mbytes A32 Base 0x00800000 A32 Base 0x007FFFFF IP A Memory Space 8 Mbytes A32 Base 0x00000000 Table 4 2 VME6400 IPack memory A32 Memory Map Address Access Range A24 Base 0x07FFFF IP D Memory Space 128kbytes A24 Base 0x060000 A24 Base OxOSFFFF IP C Memory Space 128kbytes A24 Base 0x040000 A24 Base 0x03FFFF IP B Memory Space 128kbytes A24 Base 0x020000 A24 Base 0x01FFFF IP A Memory Space 128kbytes A24 Base 0x000000 Table 4 3 VME6400 IPack memory A24 Memory Map 4 1 3 VME6400 Geographical Addressing A16 and CR CSR A24 memory access Through Geographical Addressing GA capability as stated in the VME64x specification the VME 6400 Ipack carrier give direct access to the CR CSR A24 address space to inform the sy
27. stem of the card capacity and configuration The CR CSR Base Address and also the default 16 base address register value are derived from the geographical address upon system initialization This will permit the system to automatically identify into which VME64x back plane slot the VME6400 is inserted The geographical address pins are set by the system backplane with unique slot addresses and are routed via the P1 connector If the VME6400 is to be utilized into a standard VME frame it is possible to bypass the VME64 back plane GA addressing See 3 7 switch 52 The CR CSR base address will remain link to the GA setting while the A16 base address may be configured change through the CSR function 0 ADER address decode compare register The Ipack memory space base address access may also be configured directly in the CSR ADER or through the A16 configuration register see A32 A24 IPMEMCONTROL The following tables are a brief description of the VME64x specification with values for the VME 6400 Ipack carrier card For more details consult the vita 1 1994 VME64 and Vita 1 1 1997 VME64x standard Note that all unused or unimplemented locations in the defined CR and CSR area will be mark as 0x00 MAX Technologies Page 21 MAXVME 6400 User Manual Rev 1 2 Standard VALUE Configuration ROM data access width Accepts D32 D16 or DO8 EO cycles 1 byte 4 0x84 CSR Data access width Accepts D32 0x17 D16 or
28. ster card should have the VME system clock as its external reference source SYNCHRONIZATION REF SRC bit SYNC IN port INT REF bit MSTR SLA bit 3 STATUS Slave 0 SYNC IN port SYNC OUT port of External Reference 0 SLAVE another MAXT card Master with internal reference 0 5 INpot No external VCXO with 1 MASTER reference detected XO CAL Master with external reference 0 SYNC INport External Reference 0 External Reference MASTER Master with VME SYSCLK 1 VME SYSCLK Do not care 0 External Reference MASTER reference 2 3 See section 4 2 1 4 GENERAL CTRL Register bit 29 See section 4 2 1 4 GENERAL CTRL Register bit 24 See section 4 2 1 4 GENERAL CTRL Register bit 31 Table 2 1 MAXVME 6400 Synchronization configuration and states MAX Technologies Page 11 MAXVME 6400 User Manual Rev 1 2 2 1 1 5 Optional IRIG B synchronization The MAXVME 6400 can also optionally be synchronized on an external IRIG B signal if your carrier comes with the IRIG B decoder circuitry If so when the IRIGB_ENABLE bit is activated and the IRIG B signal is connected to IRIG B_IN the MAXVME 6400 will synchronies its internal clock and timer on the incoming signal by automatically adjusting the VCXO The decoder logic accepts both TTL and standard amplitude modulated AM IRIG B signal When using the TTL input the lus synchronicity is exact since the rising edge of
29. t symbol by the slave cards resets their free running counter and also sends a 0 125 us low pulse on their IP STROBE signal On a master or a slave card the SYNC DONE bit of the GENERAL CTRL register indicates when such a timer counter reset occurred see section 4 2 1 4 IMPORTANT When writing a 1 to the RST CNT bit of the INTERRUPT MASKS of a slave card no synchronization symbol is generated to the SYNC OUT port of this card but it resets the counters of this card only 1 All MAX Technologies IP modules support this feature however it is not specified in the IP specification Other manufacturers may not support this feature Page 12 MAX Technologies Rev 1 2 MAXVME 6400 User Manual 2 2 Interrupt Time Tag Fifo It is possible for the user to obtain the value of the 64BIT COUNTER register at the time of all the incoming IP interrupt sources Activating the INTCNT enable bit in IP Configuration register enables this feature By doing so the IP interrupts will only be presented one at a time The associated counter timer value is available in the INT COUNT register If more then one interrupt 18 received from the IP modules the associated counter values are memorized and will be presented once the first interrupt 1s cleared There is no obligation to read the INT COUNT even if the option 15 enabled 2 3 Optional 15V DCDC The MAXVME 6400 is optionally equipped with two DCDC converters which can provide 15V instead of
30. tects this reference it automatically locks its on board VCXO to this external reference Then the card generates reference symbols on its SYNC_OUT port Consequently the slave card attached to the master card SYNC_OUT port locks its VCXO to the reference too An external reference connected to the SYNC_IN port of the master card must meet the following l 1 MHz square wave 100 PPM 2 TTL level compatible 3 40 60 duty cycle The difference between reference symbols and an external clock reference is the clock duty cycle MAX Technologies Rev 1 2 2 1 1 4 Master with VME SYSCLK reference card MAXVME 6400 User Manual This master state 1s reached when the external reference source is the VME SYSCLK The reference source is selected with the REF SRC bit of the GENERAL CTRL register see section 4 4 8 The card locks its on board VCXO to this external reference Then the card generates reference symbols on its SYNC OUT port Consequently the slave card attached to the master card SYNC OUT port locks its VCXO to that VME SYSCLK too In this state INT REF of the GENERAL CTRL register is set to 0 because the clock reference is external When used the VME system clock must meet the following 1 16 Mhz 100 PPM accuracy IMPORTANT Slave state 18 not possible when the VME system clock is selected as the external reference because the card will never detect reference symbols generated by a master card Only a desired ma
31. ved future use default OFF 5 9 Local base address selector Equivalent to the GA4 to GA0 10 Local base address Enable When set to on 1t will force the base address to the local dipswitch setting MAX Technologies Table 3 3 local base address settings Page 17 MAXVME 6400 User Manual Rev 1 2 3 2 9 SW1 SW7 Multi board synchronization port connectors As mentioned previously the MAXVME 6400 has input output synchronization ports identified as SYNC_IN and SYNC_OUT that are used to synchronize multiple boards together The boards are also optionally equipped with an IRIG B circuitry which can be used to synchronize a master board to an IRIG B signal The MAXVME 6400 can use those synchronization devices through the back plane bypassing parallel IP IO or through the front BNC connector only available on convection cooled board Since back plane IO are already assigned to IP modules IO using the back plane setting will imply disconnecting the corresponding IP IO The selection is made with SW1 to SW7 the following figure represents the schematics of those switches Switch Front Plate BNC QUIE POSO Sync Signal 277 HrK On Back Plane e IPx Switch No Connect POS1 Figure 3 3 5 1 to SW7 circuit Note that POS0 on the switches are represented by a DOT This table gives the connection between the switches synchronization signals fro
32. x00 0x00 0x143 0x15F MBLT mode 8bytes 4 0 00 0 00 0 00 0 00 Function 2 Se Code Mask all access type supported in A32 0 64 01 0 00 0 00 0 00 0 00 0x163 0x17F MBLT mode 8 s VME64x aer F 0x00 0xEE 0x00 0x183 0x19F Function 3 AM Code Mask 8 bytes 64 All Alo 0x1A3 1 Function 4 AM Code Mask VME64x All 0x00 0x1C3 0x1DF_ Function 5 AM Code Mask bytes VME64x All 0x00 Ox1E3 OXTFF Function 6 AM Code Mask bytes VME64x All 0x00 0 203 0x21F Function 7 AM Code Mask VME64x WI 0x00 PU Mala 0 0x223 0x61F XAMCAP 256 bytes VME64x WI 0x00 Function 0 Address Decoder Mask ADEM A16 memory access use address bit A15 0x623 Ox62F A11 2KB boundary 4 bytes 4 0 00 0 00 0 8 0 00 Function 1 ADEM A24 memory access use address bit to A19 512KB 0 633 0x63F boundar 4 bytes VME64x 0x00 0xF8 0x00 0x00 Function 2 ADEM A32 memory access use address bit A31 to 25 32 0x64F ZE bytes 4 Bes 0 00 0 00 0 00 JE _ 0x6A3 0x6AB Reserved readaszero MME Table 4 4b VME6400 CR MAX Technologies Page 23 MAXVME 6400 User Manual Rev 1 2 The Configuration status register CSR will be use in order to provide Address Space Relocation Note that A24 and A32 base address definition may also be configured through the A32 A24 IPMEMCONTROL register while A16 base address definition may only
33. y use slot A amp B or C amp D 3 2 2 VME connector IO assignment The two following table present the IP modules IO connection to the VME connector and P2 Note that the IOs are connected as indicated in specification VITA 4 1 1996 IP I O Mapping to VME64x Row VME Connector Position d 2 2 1 IPC 1047 IPB IO42 IPB IO41 1046 2 2 IPC 1048 1044 4 43 GND 2 3 1 50 IPB IO46 1045 1049 2 4 4 1 1048 IPB 1047 GND 2 5 IPB IO3 IPB IO50 IPB IO49 IPB IO2 2 6 4 4 IPA IO2 IPA IO1 GND P2 7 IPB IO6 IPA IOA IPA IO3 IPB IO5 P2 8 4 7 6 IPA IO5 GND P2 9 4 9 IPA IO8 IPA IO7 IPB IO8 P2 10 IPB IO10 IPA IO10 IPA IO9 GND P2 11 4 12 IPA IO12 IPA IO11 IPB IO11 P2 12 IPB 1O13 IPA IO14 IPA lI013 GND P2 13 15 IPA IO16 IPA IO15 IPB IO14 2 14 IPB IO16 IPA 1O18 IPA IO17 GND P2 15 IPB 1018 IPA IO20 IPA IO19 IPB IO17 P2 16 4 19 IPA 1O22 IPA IO21 GND P2 17 IPB IO21 IPA IO24 IPA IO23 IPB IO20 P2 18 22 IPA 1O26 IPA IO25 GND P2 19 IPB 1024 IPA 1O28 IPA IO27 IPB IO23 P2 20 25 IPA IO30 29 GND P2 21 IPB 1O27 IPA 1O32 IPA IO31 IPB IO26 P2 22 28 034 IPA IO33 GND P2 23 IPB 1O30
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