User Manual EVA-X4300
Contents
1. 000000 16000000 15 14 000000 0000 ol 0 0 0 O 9 O 0 0 02 OQ OQ O 0000000000 O COO 0O10 000 0 O O O O 00 0000 0000000000 13000000 12000000 11000000 100000000 9000000 8000000 70000000 60000000000000 50000000000000 40000000000000 30000000000000 20000000000000 0000000000000 1 em Pin 1 Corner EVA X4300 System Design Guide 26 NC AD24 TRDY PCIRST_ AD13 AD10 AD5 AD3 AD1 TXP RXP DP1 EI 25 AD25 CBE 3 IRDY STOP AD14 AD9 AD7 AD4 AD2 TXN RXN DM1 DMO 24 AD26 CBE 2 FRAME DEVSEL AD15 CBE 0 PAR ADO ISET VCCAO VCCA1 VSSA1 AVSSO 23 AD27 AD16 AD17 TESTO TESTA VCC SPI AD11 INTA VCCAPLL VSSAPLL VSSA0 VCCABG AVBDELL 0 22 AD28 AD18 AD19 TEST2 TESTI ATSTP CBE 1 AD12 ADE Duplex Link Active VSSABG AVDDO 21 AD29 AD20 AD21 GND SPI TEST3 ATSTN ROM cs AD8 TXCO TXENO RXDVO RXCO or 20 PCICLK 2 AD30 AD31 AD23 AD22 INTC_ 19 PCICLK 0 PREQ2 PGNTO PGNT2 INTD INTB_ 18 PCICLK 1 1 PREQO PGNT1 VCC3V VCC3V TXD0 3 TXD0 0 RXD0 0 RXD0 3 Vad io 17 MD4 MDO 11014 DQM1 GNDK GND R3 TXD0 2 TXDO 1 RXDO 1 RXD0 2 Vad io 16 MD3 MD1 MD9 MD15 MD15 GND R3 MDC MDIO COLO VCC3V GND R3 15 MD2 MD7 MD11 MD12 MD8 GND R3 VCC3V VCC3V VCC3V VCC3V GND R3 14 MD5 ES MD13 Daso MD10 VCCK VCCK VCCK VCCK VCCK GND R3 13 MD62. Au PLATING PIN 1 CORNER 13 5 7 9 1113 1517 19 2123 1 00 3 REF U li 0000000000 0000000000 0000000000 222000 _ 2000000000 _ 000000 000000 3993988883 0 re om o gt EXEC Sa lt lt DE REN Om 0000000000 0000000000 0000000000 0000000000 0000000000 0000000000 0000000000000000 0000000000000000 0000000000004604 AF 00000000 A B c D ES F G H J K L M N P R T Y Y AA Mo AE AF TOP_VIEW EVA X4300 System Design Guide Symbol Common Dimensions Body Size Ball Pitch Total Thickness A 2 23 0 13 s Mold Area Chamfer e E EHE n ao Ball Count Edge Ball Center to Center 7 EVA X4300 System Design Guide 2 3 Signal Arrangement Top View 2B Oo OOOO OD OUO 0 Q0 OO 0 9 2 99029 coo 25 OOOO HOO 000000 000000 000000 000000 000000 00000 OO Oe OO 000000 000000 000000 000000 000000 O Qi 68 O O 0000000000000 0000000000000 0000000000000 OO OQ OO 0 O 0000000000000 0000000000000 o 0 0000 o 000 o 00000 000 060000 00 0 2400000000000000000000000000 23 0 00000 0000 00 010 0006000 0 00 0000 22 0 00000 0 0 0 0 00 00 0 6 1060 0600000000000 22 0 0000 0 0 0 0 0000 000 000 000 000 20000000 19000000 18000000 17 00000 00000 00000 00000 0000000000 000 0 0
3. Bridge those grounds with only one connection Only those signals required for operation or interconnect can run into the isolated area Analog GND I O connectors Chasis GND Note the interconnects between GNDs were not shown 13 EVA X4300 System Design Guide 18 19 20 Ensure that any signal passing between those sections runs ONLY through the bridge and run the signals on a layer adjacent to the bridge to maintain RF return path If analog or digital power is not required in the isolated area the unused power plane can be redefined as a second ground plane referenced to the main ground plane by stitches of vias within the isolated area Connect system Power on and H W Reset to Power good input of EVA X4300 then use PCI RST output of EVA X4300 to reset ALL peripherals 21 The power on strap pins are combined with the memory address bus which belong to DRAM power category So the pull high resistors should connect to the same supply VCCO of DRAM interface That is DRAM type Supply V Note SDR 3 3 DDR2 1 8 For detail of power on straps function please refer to the EVA X4300 data sheet 22 Do follow the power on sequence to prevent excessive current from the power supplies during power up and power down periods m Power up core supply VDD CORE and then power up the I O supply DVDD m Power down I O supply
4. EVA X4300 System Design Guide Trusted ePlatform Services AD ANTECH Copyright Advantech reserves the right to make changes without further notice to any products or data herein to improve reliability function or design Information furnished by Advantech is believed to be accurate and reliable However Advantech does not assure any liability arising out of the application or use of this information nor the application or use of any product or circuit described herein neither does it convey any license under its patent rights nor the rights of others Copyright O 2008 Advantech Co Ltd All rights reserved Part No 2006X43020 Edition 1 Printed in Taiwan August 2008 EVA X4300 System Design Guide ii Contents Chapter 1 1 1 Chapter 2 2 13 Appendix A A 1 Overview 7 _ 1 eM p M 2 Layout GUIS BGA Layout Guidellne itii itte innen eu ana 4 Package Outline 4 2 ro sc bro veo e la 6 Signal dearer 8 EVA X4300 Power 8 11 General Layout Rule deerit daa elds 11 Crystal External Oscillator seen 15 DDRZ Interface Em 16 Switching Power urn rare 19 POI Interface nunmal T nd anaad dads 20 USB 2 0 dte m da rae adi iaia
5. DVDD and then power down the core supply VDD CORE 23 Recommend Termination sign 2 Termination Q Trace impedance Q Clocks 24M 26 22 86 PCI clock 7 2 22 PCI signal 13 2 51 086 DDR Clocks 19 33 90 Differential DDR signal 19 33 086 24 Recommended PCB stack up a 4 layers Layer Type Description Material Thickness 1 Signal Top Routing Copper 0 5 102 FR4 5mil 2 Plane Ground Copper 1oz FR4 40mil 3 Plane Power Copper 1oz FR4 5mil 4 Signal Bottom Routing Copper 0 5 10z EVA X4300 System Design Guide 14 2 6 b 6 layers Layer Type Description Material Thickness 1 Signal Top Routing Copper 0 5 102 FR4 5mil 2 Plane Ground Copper 1oz FR4 5mil 3 Plane Power Copper 1oz FR4 40mil 4 Signal Internal Routing Copper 1oz FR4 5mil 5 Plane Ground Copper 1oz FR4 5mil EN Signal Bottom Routing Copper 0 5 102 Crystal External Oscillator The EVA X4300 requires a 14 318 MHz clock to generate all the internal and external clocks Connect an external 14 318 MHz crystal Parallel resonant between Xtal and Xtal o pins to operate as a Pierce oscillator The EVA X4300 specification requires a frequency tolerance of 30 parts pre million PPM The other way is to use an external 14 318MHz oscillator and directly route the oscil lator is output into XTALi pin of EVA X4300 A s
6. PR ES PIS USBI PWMICLK TF GPIO 40 DTR1 CTS1 DSR1 Fi 7 23 AVSS1 AVDD2 LADO LAD1 LAD2 LAD3 SPEAKER Vdd_core Vss io Vdd_io GPIO 45 GPIO 47 GPIO 46 RTC RD RTC IRO8 prc pg SYSFAILOJExt Switch m vd E SPLDI corel vss jo vadio RUY SOUTH RTS1 GPIO 36 GPIO 34 N ut fail GPIOP 33 GPIO 43 GPIO 41 GPIO 42 8 USO ta lePIoP 31 c E SPI CS E SPI DO VBat VBatGnd AT C WR ExiSysFaill EXT GP Vad core Vss io vad TxD_EN1 SIN GPIO_P2_ 24 GPIO 35 Mi S GPIO 44 1 SA25 GPIOP 30 GPIOP 32 GPIO P2 GPIO P2 GPIO GPIO P2 GPIO P2 7ISA31 6 SA30 Vss_io 5 SA29 4 SA28 2 SA26 GPIO P1 GPIO P2 GPIO P1 GPIO P1 GPIO P1 GPIO P1 49 7 0 SA24 6 5 4 0 GPIO PO GPIO P1 GPIO P1 GPIO P2 GPIO PO GPIO PO 4 g Vss io Vss io Vss core LFRAME LDRQ 7 3 2 3 SA27 5 3 P velo veo ve GPIO PO GPIO P1 GPIO PO GPIO PO GPIO PO GPIO PO 47 6 1 1 0 4 2 Vdd io Vss io Vss core Vss core Pescante SD3 ES GPCSO GPCS1_ SD15 5014 16 Vdd io Vss io Vss io Vss core MSDATA LA20 LA18 LA23 LA19 DRA7 SD12 15 VCC3V Vad io Vss io Vss core MSCLK 504 nm SD2 SD6 LA21 SD11 14 VCC3V Vad io Vss io Vss core ARES IOCHCK_ SA2 SBHE_ LA22 SAS DACK 2 13 VCC3V Vss io Vdd core Vss core Vss core SA3 DRQO Vss core 508 MEMW_ SAI 12 VCC3V Vss_io Vdd core Vss core Vss core DRQ5
7. 21 e 23 LPC Interface ui nn iii 24 10 400 LAN Pe 25 References 29 R lerenee8 nce m 30 iii EVA X4300 System Design Guide EVA X4300 System Design Guide Chapter 1 Overview 1 1 Overview The EVA X4300 is a fully static 32 bit x86 based processor that is compatible with a wide range of PC peripherals applications and operating systems such as DOS WinCE Linux and most popular 32 bit RTOSs Real Time OS It enables maximum software re use based on its feature of legacy compatibility The EVA X4300 inte grates 32 KB write through direct map L1 cache a PCI bus interface at 33 MHz an 8 16 bit ISA bus interface SDR SDRAM DDR2 SDRAM a ROM controller IPC Inter nal Peripheral Controller with DMA and interrupt timer counter included FIFO UART SPI Serial Peripheral Interface LPC low pin count a USB 1 1 2 0 host controller LoC LAN on Chip an IDE controller and 256 KB flash within a single 581 pin BGA package to form a an SoC System on Chip processor The EVA X4300 integrates comprehensive features and rich I O flexibility within a single System on Chip to reduce board design complexity and shorten product development schedules Taking advantage of ultra low power consumption the EVA X4300 is able to operate in a wide range of temperatures without additional thermal design With the commitment of long term supply guaranteed for the EVA X4300 customers can extend product life cycle and receive a maximum
8. Do not run any high speed signal close to the external resistor of ISET to keep from interference and coupling EVA X4300 System Design Guide 26 21 Avoid over damping which affects LAN stability It is recommend to place 51 ohm and 22 pF from PCI ADO AD3 27 EVA X4300 System Design Guide EVA X4300 System Design Guide 28 Appendix A References A 1 References EVA X4300 Technical Manual PCI Local Bus Specification rev 2 2 EMC and the Printed Circuit Board Mark I Montrose High speed Digital Design Howard W Johnson PH D Noise reduction Techniques in the Electronic System Henry W Ott Printed Circuit Board design Techniques for EMC Compliance Mark 1 Mon trose gt EVA X4300 System Design Guide 30 31 EVA X4300 System Design Guide Trusted ePlatform Services AD ANTECH Www advantech com Please verify specifications before guoting This guide is intended for reference purposes only All product specifications are subject to change without notice No part of this publication may be reproduced in any form or by any means electronic photocopying recording or otherwise without prior written permis sion of the publisher All brand and product names are trademarks or registered trademarks of their respective companies Advantech Co Ltd 2008
9. SA4 Vss core DACK 6 SD10 6 11 VCC3V Vdd_io Vss io Vdd core Vdd core SMEMR DACK 5 Vss core SD13 SD9 SYSCLK 10 VCCK Vdd io Vss io Vss io Vss io SA19 SA17 DRQ2 DACK 0 LA17 MEMR 9 SMEMW AEN IRQ12 OWS_ sii OSC14M 8 SDO SA10 SA8 IRQ5 IRQ7 DACK 7 7 un ren pus js ue 5 Vss io 507 Vdd io Vss core Vdd core SA7 IRQ10 pem 6 PDD12 PDD2 PDD1 PDD11 RI4 SA1 Vss io DRQ3 Vdd io Vss core Vdd core SA18 SA9 TC 5 PDD10 PDD5 PDD6 PDD7 Vss core Vdd io SD5 Vdd io Vss core Vdd core DRO1 BALE IRQ15 4 PIORDY PIOW PDDO PDD8 Vdd io Vdd io DACK 3 SA16 DACK 1 SAO SA11 IOCS16 17 11 3 PA1 PAO PCS0 PDD4 PDD15 7 14 IOW SA12 SA14 SA6 SA13 IRQ3 IRQ14 2 13 PDACK PCBLID_ EN PCS1 SD1 SA15 EE di m Ios MEMES Ne 1 P R T U V W Y AA AB AC AD AE AF EVA X4300 System Design Guide 10 2 4 EVA X4300 Power Requirement 2 5 DC Volt Tolerance Ripple amp Noise Max Current 3 3V for VCCP 0 30 V lt 100 mV 185 mA 3 3V for VCCO 0 15 V 1 8V for VCCO 0 09 V SD IUS i DC Volt Min Volt Max Volt Ripple amp Noise Max Current 1 3V for VCCK 1 30 V 1 40 V lt 50 mA 240 mA Note CPU clock 300 MHz DDR2 clock 133 MHz and PCI clock 33 MHz Il General Layout Rule 10 Keep all traces as SHORT as possible Decoupling is to remove the RF energy injected into
10. be less than 70 mil These values may vary depending on the actual PCB parameters The maximum trace length of USB differential pairs should be less than 2 21 EVA X4300 System Design Guide 10 11 12 13 14 15 The common mode choke used if really necessary on the DP and DM lines must be placed as close as possible to the USB connector and must have Zcom 8 2 100 MHz and Z gif lt 300 O 100 MHz The analog power pins of EVA X4300 AVDDO 1 2 3 and AVDDPLLO 1 need to be properly filtered for USB performance aW RUE AVDDO 7 EE AVDDPLLO 4 5 ka s T ja GNDB GNDB NDB GNDB It is recommended to connect the analog ground pins of EVA X4300 AVSS0 1 2 3 and AVSSPLLO 1 to an isolated quiet analog ground plane which is con nected to the digital ground plane with a single Bridge or Ferrite Bead Please refer to section 2 4 for more details Place the external resistors of REXTO 1 pin U26 amp P26 as close to the EVA 4300 as possible And connect another ends of these external resistors to the isolated analog ground plane described above Do not run any high speed signal close to the external resistors of REXTO 1 to keep from interference and coupling Provide a good path from the USB connector shell to the chassis ground Maintain the maximum possible distance between Hi Speed USB differential pairs high speed or lows peed clock and non periodic signals The minimum recommended
11. return on investment The EVA X4300 provides an ideal solution for embedded systems and communica tion products such as the thin client NAT router home gateway access point and tablet PC producing optimal performance This system design guide provides detailed usage information of the highly inte grated EVA X4300 SoC processor EVA X4300 System Design Guide 2 Chapter 2 Layout Guide 2 4 BGA Layout Guideline The package of EVA X4300 is 581 ball PBGA The ball diameter is 0 6 mm 24 mil ball pitch is 1 mm 40 mil There are 6 rows of balls arranged along the edge of the package For 6 layer Ball pad diameter 24 mil Traces width spacing for Signals 5 5 5 mil Trace width for Power and Ground 20 mils Vias PAD Drill diameter for all Signals 14 8 mil Via to via spacing center to center 40 mil Via to pad spacing center to center 30 mil EVA X4300 System Design Guide 4 For 4 layer Ball pad diameter 14 mil Traces width spacing for Signals 5 5 mil Trace width for Power and Ground 20 mils Vias PAD Drill diameter for all Signals 22 12 mil Via to via spacing center to center 40 mil Via to pad spacing center to center 30 mil Note All the Vias must be covered by solder mask To minimize inductance E power vias should be as large as possible and take good care of the inadvertently cut of the ground and power planes 5 EVA X4300 System Design Guide 2 2 Package Outline
12. the power distribution net work from high speed switching devices Bypassing is to divert unwanted common mode RF noise from components or cables coupling from one area to another Place 0 01 uF 0 1 uF decoupling capacitors across each pair of VCC and GND pins Use the shortest and thickest trace between decoupling capacitor and the VCC GND pins Bulk capacitors ensure that a sufficient amount of DC voltage and current is available for digital components At least one bulk capacitor should be located m Every VLSI device m Power connector s m Daughter card slots Furthest location from the power connector m Clock generation circuitry The voltage rating of the bulk capacitors should be 50 higher than the actual voltage level to prevent self destruction and or voltage surge For decoupling of DDR2 interface please check the DDR2 section for more details In digital circuits conductors may be treated as transmission lines if the propa gation time 1689 is equal to or greater than the pulse transition time Tie or Tran The propagation speed on typical PCB is about 170 pS inch 50 Q Stripline 150pS inch 50 Q Microstrip There are 4 properties affect the performance of the transmission line m Impedance reflection distortion Time delay m High Freguency Loss limit signal bandwidth and transmission distance m Crosstalk coupling 11 EVA X4300 System Design Guide 11 12 13 14 15 1
13. 6 It is recommended to add serial damping resistors to all high speed signals especially the clock signals to reduce high frequency energy and EMI These resistors should be placed as close to the driving source as possible The clock signals should be the first routed trace in any PCB design Adjacently routed guard ground traces provide shielding and signal return path These ground shielding traces should be connect to the ground plane by vias at both ends It is best to run all clock signals on the signal plane above a solid ground plane on a multi layer board If clock high speed signals must make a layer jump route ground trace adja cent to the signals and connect both ends of the ground trace to the GND plane to form a RF return path of the signals The split power planes may cause serious EMI and signal integrity problems for high speed signals which run adjacent to the power planes To minimize these problems some decoupling capacitors should be placed between these split power planes to enhance RF return current path Any unused area of the top and bottom signal layers of the PCB can be filled with copper that is connected to the ground plane through stitches of vias Example for BGA Power Ground routing EVA X4300 System Design Guide 12 17 Every I O connector must be isolated from the digital ground and power planes A clean or quiet ground must be located at the point where interconnects leave the system Connect
14. CS 1 WE RAS cso VCCK GND R3 GND R3 GND R3 GND R3 GND R3 12 MA10 MAG BA2 BAO CAS_ BAI GNDK GNDK GNDK GND R3 GND R3 11 Mat MAS MA7 MA9 MA11 MA13 GNDK GNDK GNDK GNDK GND R3 10 MAO MA3 MA4 VDLLO GNDDLLO MA12 GNDK GNDK GNDK GNDK GND R3 g SDRAM SDRAM mao VpLL1 GNDDLL1 mas TMS GNDK GNDK GNDK VCCK CLKN CLKP 8 NC NC NC VCCO GNDK VCCK ES NC NC VCCO VCCO GNDK GNDO TCK 6 NC NC VCCO GNDO GNDO GNDO TDO TDI SOUT9 SIN9 PE SDD9 SOUT4 SIN4 5 NC NC VCCO GNDO GNDO GNDO GNDO GNDPLLO GNDPLL1 PD6 SDD6 PD5 SDD5 ied si 4 NC NC VCCO VCCO VCCO GNDO VCCK VPLLO VPLL1 PD7 SDD7 pur 4 5004 SUD 3 NC NC NC NC TESTS TEST6 SIN3 ee TESTCLK PD3 SDD3 mid ar PDD9 2 NC NC NC NC TEST TEST8 50073 m poi PDO SDDO PD1 SDD1 PD2 SDD2 PINT i ne ne mo SIE must A B E F G H J K L M N 9 EVA X4300 System Design Guide P R T U V W Y AA AB AC AD AE AF CTS2 DSR2 PWM1GATPPWMOGAT Nc 126 AVDD33 0 DP3 DP2 AVDD33 1 RTC Xin AVDD3 XOUT_14 POWER CLK25MO DCD2 318 GOOD UT PWMOCLK E DTR2 RTS2 TXD EN2 AVSSPLLo DM3 om2 lavssPLLiRTC Xou avssa MTBF 0 pwm20u Pwm10u PWM2GAT ONZ 25 8 ut 3 i g PWM2CLK SOUT2 pe REXTO AVDD1 AVSS2 REXT1 AVDDPLL SERIRO Vss pii 1 Vad pii 1 vad pii 0 Vss pii 0 FIZ pwmoou OCP 24
15. between these two pair of traces We recommend the trace Width Spacing Isolation of TX TD and RX RD pairs to be 8 mil 10 mil gt 20 mil And the mismatch of the differential pairs should be less than 100 mil Do NOT run any digital trace close to and parallel to the differential pairs The RJ 45 and output side of transformer should reference to guiet ground plane chassis ground which is isolated from the ground plane of the input side of transformer and EVA X4300 Connect this guiet ground plane to system ground with only one connection bridge Do NOT run any signal into this iso lated area The moat to isolate the guiet ground should be at least 100 mil Avoid laying power and ground planes underneath the magnetic to enhance EMI Provide a good path from the RJ 45 connector shell to the chassis ground The analog power pins of EVA X4300 VCCAPLL VCCABG VCCA0 1 and AVDD33 0 1 need to be properly filtered for LAN performance LE FL Er GIDA GNDA GIDA GNDA GIDA GNDA It is recommended to connect the analog ground pins of EVA X4300 VSSAPLL VSSABG and VSSA0 1 to an isolated quiet analog ground plane which is connected to the digital ground plane with a single Bridge or Ferrite Bead Please refer to section 2 4 for more details Place the external resistor of ISET pin J24 as close to the EVA X4300 as possible And connect another end of the external resistor to the isolated analog ground plane described above
16. ced close to the VIN pins Shortening the traces of the SW node reduces the parasitic trace inductance at these nodes This not only reduces EMI but also decreases switching voltage spikes at these nodes Some switching devices have exposed pad which should be soldered to a large analog ground plane as the analog ground copper acts as a heat sink To ensure proper adhesion to the ground plane avoid using vias directly under the device For more detailed design information please refer to the switching regulator s data sheet 2 9 PCI Interface 1 We highly recommend reserve terminations for ALL PCI signals It is much easier to remove terminations than adding them after the PCB has been found to fail EMI The trace length for all PCI signals must be limited to 7 inches The trace length for PCI Clocks must be short for on board PCI devices to mini mize the clock skew The PCI clock traces should be parallel to their reference plane usually ground planes That means the clock traces should be right beneath or on top of their reference plane There is NO board impedance specified in the PCI bus specification We recom mend the trace impedance to be 60 Q 10 with a trace width spacing design of 5 mil 10 mil Add serial termination resistor and bypassing capacitor tens of pF to PCI clock signals to match the trace impedance and enhance EMI Buffer e 1 lt gt 2 ET OS EVA X4300 System Design Guide 20 Avoid r
17. distances are as follows m 20 mils between the DP and DM traces and low speed non periodic signal traces m 50 mils between the DP and DM traces and clock high speed periodic signal traces m 20 mils between two pairs of the DP and DM traces USB data lines must be routed as critical signals Locate the USB connector close to EVA X4300 The DP and DM signals in a pair must be routed in parallel to each other Do not route these traces near high frequency signals Guard ground traces on each side of the signal pair can minimize the induced common mode noise Ferrite beads and decoupling capacitor placed on VBUS are for EMI purposes thus these components should be placed close to the USB connectors A value of about 150 uF 10 V for the decoupling capacitor is recommended on each port EVA X4300 System Design Guide 22 F1 LP ISM110 0805 LUSBD1 LUSBD1 USBl 2 SF2012900YSB 2 11 IDE The trace length and impedance match must be considered for IDE signals to enhance the EMI and signal integrity 1 2 The pull up resistors on open collector signals such as IORDY should be more than 1 KO All IDE signals need to be serial terminated Place the termination resistors for A 0 2 CS 0 1 IOR IOW and DACK near EVA X4300 Place the termina tion resistors for D 0 15 DRQ IORDY and IRQ near IDE connector The termination value should be optimized to compensate for transceiver and trace impedance to match t
18. erial damping resistor and a bypass capacitor are recommended for EMI reduction The XTALo pin should leave uncon nected The requirement of the clock is duty cycle should be between 40 60 TM TE F y a XIN 14318 65 Yi 1M 14 318MHz 124 22 XX2 YI XOUT 14318 Recommended Layout m Route the signal traces of the crystal to EVA X4300 as SHORT as possible W Whenuse external crystal with EVA X4300 internal oscillation circuitry to work as clock oscillator be sure to put all the related components close to EVA X4300 chip The ground area under the crystal circuitry should be physically insolated from system ground plane with only a small bridge between them for signals crossing This isolation prevents noise located elsewhere on the PCB from corrupting the oscillator circuitry m The power plane under the crystal oscillator area should be void when no use or insolated with exactly the same pattern of ground plane m Do NOT run any signals under this area for EMI and interference enhance ment 15 EVA X4300 System Design Guide 2 7 DDR2 Interface 1 Itis assumed that the reader is familiar with the specification and the basic elec trical operation of the DDR2 interface 2 EVA X4300 DDR2 interface substrate conductors length for signal integrality EVA X4300 Substrate Conductor Length Net Name Length
19. he characteristic cable impedance The 28th pin of IDE connectors CSEL should be pulled low Signals in the same channel should have the same length the mismatch must be less than 1 Reference circuitry IDE 44PIN DOM DED b_____ipeDs DE D6 DEDS DE DS Cuun DED10 DE DS P DED DED DED IDED1 IDED14 IDEDO P IbEDIS IDEREQ b an a DEKOR Di dej DE ACI SET IDESA1 Px IDECBLID IDESAO IDESA2 IDE Kl IDECSI DELED oon vcc px 23 EVA X4300 System Design Guide R232 PDD RN23 2 334 IDEDI 47K DCBUD 3 egi DECBLIC DICH 9 DECS PDD3 RN24 pl 2 3314 DI PDD13 E IDED13 vees H QUO ly ty 5 D Ja 8 X DD 25 iens x4 DED DD DED R231 05 hy 1 OS DUI O hie A D DIU PDSA1 RN28 1 pl 2 33x4 DESAI 47K PDRDY IDERDY POSA WE IDESAZ CIT R233 PDCS1 RN27 33x4 IDECSI PDD DE D1 DDI hil A DED 1K DIOR A DE PODO RN28 2242 33x4 IDEDO PDREG e IDEREG POON MA TT IDE W PDSAD gl 8 IDESAO R27 PDD ww M DED1 DD DE D4 DD fil DE D 1K DLE gh A DE DL DRS KAA x DEN EO Og R258 1K 2 12 LPC Interface A Low Pin Count LPC controller is integrated in EVA X4300 The LPC interface is to replace ISA interface serving as a bus interface between the system processor and peripherals e g LPC super I O chip Many of the signals are the same as signals found on the PCI
20. in microns MAIO 13283 31 MA 1 12989 16 MA 2 8745 03 MA 3 10321 07 MA 4 10173 85 MA 5 11728 8 MA 6 12466 29 MA 7 11480 64 MA 8 7638 44 MA 9 10753 84 MA 10 13659 62 MA 11 9367 04 MA 12 7999 4 MA 13 8948 06 MD 0 12939 2 MD 1 12379 26 MD 2 12218 38 MD 3 12868 28 MD 4 13327 88 MD 5 11731 55 MDI 6 11817 28 MDIT 11681 94 MDI 8 11494 07 MDI9 10379 54 MD 10 10577 86 MD 11 11902 14 MD 12 11610 42 MD 13 10048 32 MD 14 10981 68 MD 15 12062 12 BAO 10484 24 BA1 9914 61 BA2 9542 11 CAS 9668 98 1050 10088 02 1051 10430 52 DQMO 12436 31 DQM1 10402 02 DQSO 10560 44 DQS1 9752 32 EVA X4300 System Design Guide 16 MCLK 6700 98 RAS 11307 98 3 IWE 10909 61 Supported DDR2 Devices Vendor Part Number Note Hynix HY5PS121621C 84 ball Hynix HY5PS12821C 60 ball SiS DDRII6408 5C 60 ball Elpida EDE1108ABSE 68 ball 10 13 12 13 14 15 In order to meet the maximum interface speed 200 MHz 400 Mbps memory device drive strength should be set 10096 strength This requires the series ter minations to avoid excessive Under Over shoot We highly recommend reserve terminations for ALL high speed signals It is much easier to remove terminations than adding them after the PCB has been found to fail EMI It is critical that all signal routing layers have a ground reference plane meaning that there is a full contiguous ground pla
21. interface Data transfer on the LPC bus is serialized over a 4 bit bus Route the LPC signals with the PCI design rule EVA X4300 System Design Guide 24 2 13 10 100 LAN 1 Recommended Schematics E T fi 102 3KV 2 Magnetics Specification Specification Note Parameters Tx Turns Ratio 1CT 1 CT 1CT 1CT Inductance HH 350 350 Capacitance pF 15 15 DC Resistance 0 09 09 3 Magnetics Selection Guide Manufacturer Part Number Note Mingtek HN16005CG 4 Keep the distance between the EVA X4300 and the RJ 45 connector short under 4 5 Route the differential traces TX RX TD 8 RD for 100 Q differential impedance 25 EVA X4300 System Design Guide 6 VA 10 11 12 13 14 15 16 17 cali T oa 1 BEA VCCAO ig e VCCAPLL als VCCABG o gt MA vcc3 3 1 2 7 17 18 m de 18 19 20 Keep the differential traces lengths equal to reduce signal skew Keep the differential traces close and symmetric to reduce noise The parallel termination resistors of TD should be placed near the magnetic The parallel termination series resistors of RD should be placed near the EVA X4300 It is recommended that route the differential traces turn with arcs and avoid any vias and corners The traces of TX TD pair should be kept away from RX RD pair It is best to place ground guard traces
22. ne next to every DDR2 routing layers The purpose is to provide a path for return currents to minimize crosstalk and EMI The DDR2 devices should be placed as close to EVA X4300 as possible The distance between DDR2 devices and EVA X4300 should less than 3 inches Other devices should be kept away to ensure other signals do not interfere with the DDR2 interface The 1 8V power partial plane island should encompass at least the entire DDR2 region All signals avoid crossing over an unrelated plane or different power plane Six or more layers of PCB could eliminate these problems by routing DDR2 signals in the layer that is adjacent to the ground plane s Rout traces with minimal layer transitions and minimize the total number of turns and vias Decoupling capacitors are critical to the reliable operation of the DDR2 inter face The decoupling capacitors should be 0402 size or smaller Bulk capacitors ensure that a sufficient amount of DC voltage and current is available for DDR2 devices At least one bulk capacitor should be located for each DDR2 device DO NOT share the vias for decoupling capacitors due to the inductance of the vias To minimize inductance power vias should be as large as possible but take good care of the inadvertently cut of the ground and power planes The PLL and DLL power supply pins draw small currents but they are noise sensitive Each supply should be filtered by Tr filter networks Use Ferrite Bead NOT ind
23. t route near by in the same plane Group 1 LDOS LDQS LDOM DO 0 7 Group 2 UDOS UDOS UDOM DO 8 15 Group 3 MA 0 13 BA 0 2 RAS CAS WE MCLK MCLK i The intra signals trace length in each group better keeps the same other wise keeps the mismatch less than 250 mils ii The mismatch trace length between the inter groups must be less than 400 mils b All signals avoid crossing over an unrelated plane or different power plane c Route traces with minimal layer transitions and minimize the total number of turns amp vias Width Spacing Maximum Length Isolation Data Strobe 5 mil gt 20 mil 20 mil Data Mask 5 mil gt 5 mil 15 mil 2 inches Data Bus 5 mil gt 5 mil 5 mil Clock 5 mil 20 mil 20 mil Tie MMA VOD ferential pair is 10 mil Address 3 inches 5 mil gt 5 mil 5 mil Command VREF Power Width gt 20 mil Kept to a minimum GND Switching Power 1 ments of the DDR2 system 2 Please check section 2 3 and DDR2 data sheet for the detailed power require In a step down switching regulator the input bypass capacitor the main power switch and the freewheeling diode carry discontinuous currents with high dt di For jitter free operation the size of the loop formed by these components should be minimized 19 EVA X4300 System Design Guide aur VOUT The input bypass capacitors should be pla
24. uctor 17 EVA X4300 System Design Guide 16 i EVA X4300 vaa pi o AB VDDPLLO jo Vss pll 0 Pi N Vdd pll 1 pou GNDPLLO EAD L18 Ves pli 1 ied 7 VPLLO EAD L19 VPLLO D usos 4 GNDPLLO E m ca 4 03 04 VPLLI Fs GNDVPLLO HEAD L20 GNDPLL1 PE Da VDLLO BEAD VDLL1 121 5 vcc12 2 ca GNDDLL1 ES PI 03 04 VDLLO PA GNDDLLO HEAD 22 L GNDDLLO ii DDR2 SDRAM Fai 336 K XVRE 104 257 337 K VREF is not a high current supply but it is important to keep it as quiet as possi ble with minimum inductance For VREF the minimum trace width is 20 mil and keeps overall trace length as short as possible 17 The VREF divider resistors can be placed close to the DDR2 devices 18 The decoupling capacitors for VREF are intended to reduce AC noise Place one each at the divider and every VREF input of the DDR2 s 19 Recommended Terminations for DDR2 interface Signal Impedance Value Q Note O Clock Near EVA X4300 Differential 90 DQS Near DDR2 A 0 13 BA 0 2 Controls 33 Near EVA X4300 BM EN DQ 0 15 Near DDR2 MD 0 15 Near EVA X4300 Note Termination value may have to be adjusted according to manufacturing IE condition B EVA X4300 System Design Guide 18 2 8 20 Recommended layout A Trace length include the substrate amp PCB trace length routing a The following signals of DDR2 SDRAM in each group mus
25. unning PCI clocks in parallel with other signals for a long distance for interference and coupling The user may need to drive two or more source terminated clock lines with sin gle output However the following condition must be achieved i The clock traces length must be as equal as possible to guarantee the arriv ing time of the reflected pulses ii The loads must be balanced to guarantee the same shape of the reflected pulses Damping p na Clock Load Clock Source Clock Load In equal engl 17 equal lengt lii The termination value must be calculated according to Ri Z 9 R N R termination resistor Q Rs output impedance of the driver Z line impedance N number of lines Transmission line 20 2 10 USB 2 0 1 Route the Hi Speed USB differential pairs over continuous ground or power planes Avoid crossing anti etch areas and any breaks in the inter nal planes plane splits Avoid placing a series of vias near the DP and DM lines as these will create break areas in the ground plane below Avoid routing the USB differential pairs near I O connectors signal headers crystals oscillators magnetic and power connectors Maintain parallelism between USB differential signals with the trace spacing needed to achieve 90 O differential impedance We recommend the trace Width Spacing Isolation of USB differential pairs to be 8 mil 8 mil gt 20 mil And the mismatch of the differential pairs should
Download Pdf Manuals
Related Search