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BSP User Guide

1. 63 M5000 Series BSP User Guide Issued June 20 2007 1 49 vmernoll innovation deployed uniVmeSlavelmageSetup 65 unilmageShow 67 5 2 Configuring PCI Slave Images in the Universe 68 Procedure 68 Viewing PCI Slave Image Configuration 68 Changing PCI Slave Image Configuration 68 Option 1 68 Option 2 69 Option 3 70 523 VME Interrupts eee ex eR a an seats dunes 74 VME Interrupt Handling 74 VME Interrupt Generation 75 VxWorks Target Shell Example 76 5 4 Universe DMA Functionality 77 Universe DMA Driver issus esc de exer re hr PE HERE 77 Universe DMA Interface Functions 77 nDmaLabInit seses eee eh Mek DUE EROR Red dos 77 uniDmaDirect yi ois eee eie RER at Gi ec bum ce gs 78 uniDmaChainCmdPktCreate 79 uniDmaChain 1 cnet ne 80 uniDmaChainStop 80 uniDmaNotifyFneSet 81 RACEway PCI Interface X viso serrer HERBS PEOR UE A 83 6 1 RACEway PCI Interface 84 OVERVIEW Es dns dark Raa a dod Tink ea ee rhone a 64 PXB Iniialization iere ik i treo dr dain Mi Se
2. sourceBuffer is the local address of the data to be DMA ed destinationBuffer is the local address of where to place the data bufferSizeBytes is the size of the buffer to transfer f int ppc440DmaXferBlocking uint32 t sourceBuffer uint32 t destinationBuffer int bufferSizeBytes int status OK ppc440DmaTransaction t trans ppc440DmaStatus t dmaStatus char funcName ppc440DmaXferBlocking Set up the transfer data structure trans Alignment DMA ALIGNED SELECT Driver selected alignment trans Callback NULL trans UserContext NULL trans Channel 0 trans Status 1234 trans DetailedStatus 4321 trans TransferByteCount bufferSizeBytes Issued June 20 2007 M5000 Series BSP User Guide 115 DMA drivers vmernoU innovation deployed ppc440LocalAdrsToPlbAdrs sourceBuffer amp trans SourceAddressLow amp trans SourceAddressHigh ppc440LocalAdrsToPlbAdrs destinationBuffer amp trans DestinationAddressLow amp trans DestinationAddressHigh status ppc440DmaXfer amp trans 1 amp dmaStatus if status OK logMsg s xfer FAILED Status 0x x Text s n funcName dmaStatus status_code dmaStatus status_text 0 0 0 else if trans Status OK logMsg s transaction FAILED Status d DetailedStatus OxSx n funcName trans Status trans DetailedStatus 0 0
3. 74 M5000 Series BSP User Guide Issued June 20 2007 vmernoB VME Interrupts innovation deployed 5 3 VME Interrupts The Universe chip provides the means to Handle VME interrupts on a selected set of levels i e act as interrupt controller and notify the PPC440GX processor with a PCI interrupt and the vector from the interrupt source Generate VME interrupts on all levels and automatically communicate a user specified interrupt vector to the interrupt controller The Universe driver in the M5xxx BSP implements functions that support both VME interrupt handling and generation VME Interrupt Handling on page 74 describes how to setup and handle VME interrupts VME Interrupt Generation on page 75 describes how to generate VME interrupts VME Interrupt Handling All boards may generate interrupts on all lines in contrast to that there may only be one interrupt controller destination for a given interrupt line I e there may be several interrupt sources and only one interrupt destination for a given VME interrupt line Therefore as board configuration and selection of interrupt controllers is user system specific VME interrupt handling is not enabled by default in the M5xxx BSP You should determine which boards should handle which interrupt levels and activate the hardware Universe on each board accordingly The uniPciIntEnable function is used to activate and route interrupts from a user specified
4. 35 muMessageDisable 36 muMessageWrite 37 Example Inbound Message Register 37 Example Remote Use of the Message Registers 40 4 4 Inbound Message Queue 41 Common Definitions 41 imuCarcularQueuelInit esu nov nb WON BE OHS ENS EVA 42 mulnPostQueueConnect 42 niuQueueCorinect creser retter assa nome see cae dees 43 mulnPostQueueDisconnect 43 muCircularQueueFree 43 mulsInPostQueueConnected 44 mulnPostQueueWrite 45 Example Inbound Message Queue 45 Example Remote Use of the Inbound Post Queue Register 48 VME BUS Operation isse kae Re ORES EAB RR OH ESSE ES SA 49 5 1 VME Master amp Slave Access Configuration 50 QVOPVI W a Larsen dons dre Bonus RIE a rods 50 VME Address Modifier AM Codes 56 VME Master PCI Slave Access Windows 58 VME Slave PCI Master Access Windows 59 FUNCOMS zies en ax Des COEM 61 uniPciSlavelmageSet 61 uniVmeSlavelmageSet
5. UNI DMA EVENT P ERR DMA protocol error event nc points to the entry point of the function to be called on DMA event Description arg is the first argument to be passed to nc AI K Returns ways The function declaration for nc is of the form void uniDmaNotifyFnc int arg int event The second argument passed to nc is the DMA event that caused the call to nc This argument is one of UNI DMA EVENT DONE DMA completion event UNI DMA EVENT LERR DMA engine caused PCI bus error UNI DMA EVENT VERR DMA engine caused VME bus error Notes UNI DMA EVENT P ERR DMA protocol error event 82 M5000 Series BSP User Guide Issued June 20 2007 vmernoll innovation deploued RACEway PCI Interface Issued June 20 2007 M5000 Series BSP User Guide 83 RACEway PCI Interface VMETRO 5 innovation deployed 6 1 RACEway PCI Interface Overview An M5xxx board with the R option MSXXX R has an on board RACEway PCI interface ASIC chip the PXB The MIDAS BSP initializes the PXB if present to a known non conflicting state in order to guarantee proper operation See also chapter 9 for information about the bundled PXB DMA Driver PXB Initialization The PXB interface chip operates in either bridge mode or endpoint mode In bridge mode the PXB chip operates like a PCI P2P bridge In endpoint mode the PXB
6. VMETRO 5 The Midas File System MFS innovation deployed mfs gets Synopsis char mfs fgets int buf int len int fd buf buffer the put the read line into len the maximum length of the line to be read fd the file number that was previously returned from mfs_open Description This function reads data from file fd until the next 0x0a character or until the next 0x0a character is found whichever comes first The data is stored into buf This function is similar to the C library function fgets Returns This function returns buf if OK or NULL if there is an error or EOF Example Read up to an 80 byte line from the given file in mfs char buf 80 if mfs gets buf 80 fd ERROR printf The line read is s n buf else printf Error reading a line n Issued June 20 2007 M5000 Series BSP User Guide 129 MIDAS File System VMETRO E innovation deployed mfs_read Synopsis int mfs_read int fd int buf int len fd the file number that was previously returned from mfs_open buf buffer to put the read data into len the maximum amount of data to be read Description This function reads up to len bytes of data from file fd and stores the data into buf This function is similar to the read C library function Returns This function returns the length read if OK otherwise ERROR Example Read up to 80 bytes from the given file in mfs char buf 80 int va
7. lt vmeAmCode gt is the VME Address Modifier code to be used when transferring the DMA block If lt pci64 gt is TRUE then PCI Dual Address Cycles are enabled lt direction gt is either UNI DMA_V2L 0 meaning VME to PCI or UNI DMA L2V 1 meaning PCI to VME If the newly created command packet is to be part of an already existing chain of DMA command packets lt prev gt should point to the UNI DMA CHAIN CMDPT NODE gt structure representing the packet in front of the new one and lt next gt should point to the lt UNI DMA CHAIN CMDPKT NODE gt structure representing the next packet in the chain Both lt prev gt and lt next gt may point to NULL Pointer to newly created UNI DMA CHAIN CMDPKT NODE structure on success or NULL on failure The chain of DMA command packets is stored internally as a singly linked list Please see the uniDmaLib h file for the complete structure definition Internally this function calls cacheDmaMal loc to allocate memory for the new node Therefore the memory for the node can be freed by calling cacheDmaFree with the returned value of uniDmaChainCmdPktCreate as the parameter Note that freeing a node in this manner invalidates the chain of DMA command packets unless the user manually re attaches the previous and next links ofthe chain Please see the Notes section of the uniDmaDirect function in regard to vmeAdrs pciAdrs byteCount and vmeAmCode These notes apply to the par
8. 1 PCI base address of the VME A32 window is configured automatically The base address is stored in the global variable VmeA32MasterPciBase 2 VME A32 MASTER BASE VME A32 base of window M5xxx BSP default is 0x0 3 VME A32 MASTER SIZE size of the window into A32 space M5xxx BSP default value is 256MB The following macros define an optional window disabled by default onto VME A32 address space from the PPC440GX 1 PCI base address of the optional VME A32 window is configured automatically The base address is stored in the global variable VmeA32Master2PciBase 2 VME A32 MASTER 2 BASE VME A22 base of the optional window M5xxx BSP default is 0x0 3 VME A32 MASTER 2 SIZE size of the optional window M5xxx BSP default is 64KB The PCI addresses and hence the local addresses corresponding to the VME windows are determined as part of the PCI autoconfiguration process In order to access the VME windows from local address space the local address must be determined The function sysBusToLocalAdrs can be used to translate a VME address to a local address The unilmageShow function can also be used to view the configuration of Universe windows VME Slave PCI Master Access Windows A VME slave access window is a window on the VME bus that allows other VME bus masters to access the M5xxx board as a VME bus slave device A VME slave window usually makes main memory RAM available This is frequently called Dual Porting M
9. mfs_eof Synopsis int mfs_eof int fd fd the file number that was previously returned from mfs_open Description This function tests the given stream for an end of file indicator Once the indicator is set read operations on the file return the indicator until rewind is called or the file is closed The end of file indicator is reset with each input operation Returns This function returns nonzero if an end of file indicator was detected on the last input operation on the named stream and 0 if end of file has not been reached Example Determine if the given file is at its end of file marker if mfs_eof fd printf This file is positioned at its end of file mark n else printf This file is not positioned at its end of file location n mfs_ftrunc mU EE LSS aes Synopsis int mfs ftrunc int fd int length d the file number that was previously returned from m s open length the length to which the file will be truncated Description This function truncates a file to the specified length If the file is already shorter than this length the length of the file is not changed Returns This function returns OK if the file was truncated or if the file is already shorter than the specified length The function returns ERROR if an error condition is detected Example Truncate the given file to 100 bytes mfs ftrunc fd 100 128 M5000 Series BSP User Guide Issued June 20 2007
10. BSP User Guide MIDAS M5000 Series Single Board Computer VxWorks 5 5 Version 1 2 Release 1 5 VMETRO innovation deployed Notice The information in this document is subject to change without notice and should not be construed as a commitment by VMETRO While reasonable precautions have been taken VMETRO assumes no responsibility for any errors that may appear in this document Trademarks Trademarked names appear throughout this document Rather than list the names and entities that own the trademarks or insert a trademark symbol with each mention of the trademarked name we hereby state that the names are used only for editorial purposes and to the benefit of the trademark owner with no intention of improperly using the trademark The mention of any trademarked name is not intended to imply that VMETRO products are affiliated endorsed or sponsored by such trademark owner Software and Firmware Licensing Any Software and Firmware code provided by VMETRO described herein is proprietary to VMETRO or its licensors The use of this Software and Firmware is governed by a licensing agreement included on the media on which the Software and Firmware was supplied Use of the Software or Firmware assumes that the user has agreed to the terms of the licensing agreement VMETRO retains all rights to the Software and Firmware under the copyright laws of the United States of America and other countries This Software or Firmware may not in contraven
11. Example This example sets up a VME slave image at PCI address 0xb0000000 and VME address 0x50000000 VME address space is A24 both Supervisory and Non priviledged transactions are supported as well as both Data and Program operations The size of the window is 0x400000 4 MB uniVmeSlavelmageSetup 7 0x50000000 0xb0000000 0x400000 UNI PCI MEMORY SPACE UNI AMCODE A24 TRUE TRUE TR Ul Is TRUI Ut Fi TRUI Ut Is TRUE TRUE TRUE Issued June 20 2007 M5000 Series BSP User Guide 67 VME Bus Operation vmernoU innovation deployed unilmageShow Synopsis Description Returns Example void unilmageShow This function is used to obtain a summary of the configuration of the Universe windows It is very useful for determining the current status of VME connectivity The information reported by this function is extracted directly from the UCSR in PCI Configuration Space Nothing is returned other than the textual output printed by the function The following text is typical of the output of unilmageShow Universe PCI slave images VME master windows Image Type Local PCI Base VME Base Size 0 MEM d2000000 d2000000 00000000 00010000 1 MEM d0000000 d0000000 00000000 01000000 2 MEM c0000000 c0000000 00000000 10000000 Universe VME slave images PCI master windows Image Type Local PCI VME
12. RACEdrv while the section parameter to this function should not have brackets i e RACEdrv Returns OK or ERROR Example Set the VmeAl6SlaveBase flag to 16384 int val 16384 mfs ini setlong vxbsp ini VMEInterface Vmel6SlaveBase amp val Issued June 20 2007 M5000 Series BSP User Guide 133 MIDAS File System VMETRO E innovation deployed mfs_ini_setlongh Synopsis STATUS mfs ini setlongh char filename char section char item long value Description This function sets the value of the item item in section section of file filename to the value value The value is written as a hex value with a prefix of 0x Note the actual section name in the file has brackets around it i e RACEdrv while the section parameter to this function should not have brackets i e RACEdrv Returns OK or ERROR Example Set the VmeAl6SlaveBase flag to 0x10000 int val 0x10000 mfs ini setlongh vxbsp ini VMEInterface Vmel6SlaveBase amp val mfs ini getlong Synopsis STATUS mfs ini getlong char filename char section char item long value Description This function sets the value of the item item in section section of file filename The value is read as a 32 bit unsigned integer and it can appear in the file in either decimal or hex format The hex format has a prefix of Ox Note the actual section name in the file has
13. BSP User Guide Issued June 20 2007 vmernoll innovation deployed VME Interrupts level is VME interrupt level to generate vector is a value in the range 0 255 that will be communicated to the interrupt controller in order for the interrupt controller to identify the interrupt source and call the correct interrupt service routine VxWorks Target Shell Example You need two boards for this example BOARDI board that is to act as VME interrupt controller handler BOARD2 board that is to act as VME interrupt source device Register an interrupt service routine on BOARDI gt intConnect 0x30 logMsg n n nhello n ngoodbye n n Tell the Universe to handle VME interrupt level 3 and signal to the 440GX on PCI interrupt line 0 uniPciIntEnable 0 3 Generate the interrupt on BOARD2 uniVmeIntGenerate 3 0x30 The following messages should appear on the console of BOARD interrupt hello goodbye Issued June 20 2007 M5000 Series BSP User Guide 77 VME Bus Operation VMETRO E innovation deployed 5 4 Universe DMA Functionality The Universe includes a built in DMA controller that enables high speed block transfers between PCI and VME This enables high throughput block transfers without the involvement of the CPU The BSP includes a module called uniDmaLib which provides functions for interfacing with the Universe DMA controlle
14. Factors that affect the PCI bus numbers chosen by the autoconfigurator include the number and configuration of all P2P bridges present in the system whether the MEZZ500 is present and whether the PXBs are being used The functions MidasBusNoToPciBusNo and MidasBusNoFromPciBusNo are available for translating between the MidasBusId parameter and PCI bus number Issued June 20 2007 M5000 Series BSP User Guide 21 PCI Bus Operation VMETRO 5 innovation deployed PMC slot The M5xxx board can accommodate up to five 5 PCI Mezzanine Card PMC modules Typically these PMCs provide I O memory or even DSP functions Typically in order to access the registers of a PMC in PCI Configuration Space the programmer has to provide information such as the device number and MidasBusId which can be obtained with the function MidasPmcSlotInfoGet The function MidasPmcSlotTblShow is useful for reviewing these attributes Following is a list of functions documented in this chapter MidasBusIdFromPciBusNo MidasBusIdToPciBusNo MidasGetPmcBridgeBusNumbers MidasPciSlotInfoGet MidasPmcSlotInfoGet sysBusToLocalAdrs and sysLocalToBusAdrs MidasBusIdFromPciBusNo Synopsis int MidasBusIdFromPciBusNo UINT8 MidasBusId UINT8 PciBusNo idasBusId pointer to the returned Midas Bus ID Returned value is either IDAS PRIMARY BUS 0 IDAS SECONDARY BUS 1 MIDAS TERTIARY BUS 2 MIDAS QUATERNARY BUS 3 or MIDAS MEZZ500
15. RACEdrv while the section parameter to this function should not have brackets i e RACEdrv Returns OK or ERROR Example Find whether PXB initialization is enabled char init flag 40 if mfs ini gettext vxbsp ini RACEdrv PxbInit init flag sizeof init flag OK printf Value of init flag is s n init flag else printf Value of init flag not found n 132 M5000 Series BSP User Guide Issued June 20 2007 VMETRO 5 The Midas File System MFS innovation deployed mfs ini settext Synopsis STATUS mfs ini settext char filename char section char item char text Description This function sets the value of the item item in section section of file filename to text Note the actual section name in the file has brackets around it i e RACEdrv while the section parameter to this function should not have brackets i e RACEdrv Setting the text parameter to a null string i e will remove the item from the section Returns OK or ERROR Example Set the PXB initialization flag to be enabled mfs ini gettext vxbsp ini RACEdrv PxbInit TRUE mfs ini setlong Synopsis STATUS mfs ini SELON char filename char section char item long value Description This function sets the value of the item item in section section of file filename to the value value Note the actual section name in the file has brackets around it i e
16. U TLB Entry MMU TLBEntry a The cached and non cached regions access the same physical SDRAM b Userconfigurable through NONCACHEABLE MEMORY SIZE c User configurable through PCT MASTER PREFETCHABLE POOL SIZI trj with prefetch without prefetch Regions marked Not mapped available can provide addressing to PCIbus resources To enable access to these regions the PPCA40GX MMU must be initialized appropriately This is done by adding entries to the sysStaticTlbDesc array found in sysLib c See the sysStaticTlbDesc array in sysLib c for more details Figure 1 2 shows a graphic representation of Table 1 2 Issued June 20 2007 M5000 Series BSP User Guide vmernoUl Overview innovation deploued 36 bit PLB 32 bit virtual PCI memory Space Processor Local Address Map Address Map Bus Address Map by bsp F FFFF FFFF Flash Memory FFFF FFFF FF00 0000 PCI X bridge FEO00 0000 Not Mapped unused FCO00 0000 32 bit PCI 1 0 outbound F880 0000 Not mapped unused F801 0000 16 bit PCI I O outbound Not Mapped unused F800 0000 Flash Memory F400 0000 PLD F300 0000 SRAM F200 0000 120 F100 0000 Internal CPU Peripherals F000 0000 PCI Memory outbound non prefetch pool for Not Used window without prefetch autoconfiguration C000 0000 3 7000 0000 PCI Memory PCI Memory outbound prefetch pool for 2 9000 0000 window with prefetch aut
17. VME interrupt lline to a user specified PCI interrupt PIN This function is declared as follows STATUS uniPciIntEnable int lint PCI interrupt pin int source Universe interrupt source lt source gt is one of the following UNI INT ACFAIL AC fail signal UNI INT SYSFAIL Sys Fail signal UNI INT SW INT Software interrupt UNI INT SW IACK Software interrupt Acknowledged UNI INT VERR VME bus error UNI INT LERR PCI bus error UNI INT DMA DMA controller interrupt UNI INT VIRQ7 VME interrupt level 7 UNI INT VIRO6 VME interrupt level 6 UNI INT VIRO5 VME interrupt level 5 UNI INT VIRO4 VME interrupt level 4 UNI INT VIRO3 VME interrupt level 3 UNI INT VIRO2 VME interrupt level 2 UNI INT VIRQ1 VME interrupt level 1 UNI INT VOWN VME ownership interrupt Issued June 20 2007 M5000 Series BSP User Guide 75 VME Bus Operation VMETRO E innovation deployed lt lint gt is one of the following Zz LINT7 PCI interrupt pin 7 _LINT6 PCI interrupt pin 6 LINT5 PCI interrupt pin 5 LINT4 PCI interrupt pin 4 Zz z Z UNI INT LINT3 PCI interrupt pin 3 UNI INT LINT2 PCI interrupt pin 2 U NT LINT1 PCI interrupt pin 1 HAH AAA H H Hi H HH HH H H Z C 2 24 24 2 2 2 2 2Z _LINTO PCI interrupt pin 0 It is also required to implement and register a function that can act as th
18. be liable for direct indirect special incidental or consequential damages including but not limited to lost profits penalties or damages payable to third parties suffered or incurred whether based on contract tort or any other legal theory even if VMETRO has been informed of the possibility of such damages This limitation of liability may not be enforceable in certain jurisdictions therefore the limitations may not apply This warranty gives you specific rights You may have other rights that vary from jurisdiction to jurisdiction VMETRO s warranty is limited to the repair or replacement policy described above and neither VMETRO nor its agent shall be responsible for consequential or special damages related to the use of their products Limited Liability VMETRO does not assume any liability arising out of the application or use of any product described herein neither does it convey any license under its patent rights nor the rights of others VMETRO products are not designed intended or authorized for use as components in systems intended to support or sustain life or for any application in which failure of the VMETRO product could create a situation where personal injury or death may occur Should Buyer purchase or use VMETRO products for any such unintended or unauthorized application Buyer shall indemnify and hold VMETRO and its officers employees subsidiaries affiliates and distributors harmless against all claims costs dam
19. 0 status ERROR return status Chained DMA transfer example The following source code is an example of a chained DMA transfer The code starts in the doChain function include vxWorks h include stdio h include cacheLib h finclude taskLib h include ppc440DmaLib h void setPattern uint32 t buf int size 116 M5000 Series BSP User Guide Issued June 20 2007 vmernoll innovation deployed PPC440GX DMA Driver for size gt 0 size buf buf size int checkPattern uint32 t buf int size for size gt 0 size buf if buf size return ERROR return OK void erasePattern uint32 t buf int size for size gt 0 size buf buf Oxffffffff static int doXferChained totalIntr static int doXferChained status int doXferChainedIsr int Status int DetailedStatus void UserContext doXferChained totalIntr if doXferChained status Already set donit overwrite Issued June 20 2007 M5000 Series BSP User Guide 117 DMA drivers VMETRO E innovation deployed return OK if Status doXferChained status DetailedStatus if UserContext NULL doXferChained status ERROR return OK static int doXferChained int width int bufferSize uint32_t sourceBuffer uint32_t destinationBuffer int descs int status OK Int ent ppc440DmaTransacti
20. DetailedStatus Pointer to callback routine int Callback int Status int DetailedStatus void UserContext User applied callback parameter void UserContext ppc440DmaTransaction t The fields are used as follows Channel DMA channel to use Must be set to 0 110 M5000 Series BSP User Guide Issued June 20 2007 VMETRO PPC440GX DMA Driver innovation deployed Alignment Alignment of user buffers The alignment affects the transfer line width used by the DMA engine to transfer data and thus the performance The user application can either force this field to an alignment or leave it up to the driver to decide If forced then the driver will return with an error if the user buffers are not correctly aligned Values used for this field are as follows DMA ALIGNED SELECT 0 Alignment selected by driver DMA ALIGNED 1 1 1 byte aligned DMA ALIGNED 2 2 2 bytes aligned DMA ALIGNED 4 4 4 bytes aligned DMA ALIGNED 8 8 8 bytes aligned DMA ALIGNED 16 16 16 bytes aligned TransferByteCount Size of transaction in bytes The DMA engine supports transferring 1024k transfer lines The transfer line width is dependent on the alignment and thus the maximum value of this field is 1024k times the alignment Buffer addresses Addresses of the source and destination buffers as seen from the processor local bus PLB Translation function
21. Gigabit Ethernet Channel EMAC3 MTU 8000 Gigabit Ethernet Channel For most users the default configuration should work fine Issued June 20 2007 M5000 Series BSP User Guide 89 Network vmernoU innovation deployed 7 2 Shared Memory sm Backplane Network Interface 1 MSxxxboards If the M5xxx boards are attached then the problem is more likely to be with the gateway or with the host system configuration 2 You can use host system utilities such as arp netstat etherfind and ping to study the state of the network from the host side 90 M5000 Series BSP User Guide Issued June 20 2007 VMETRO i Gigabit Ethernet Throughput Performance innovation deployed 7 3 Gigabit Ethernet Throughput Performance Most Ethernet transfer protocols use the IP stack when transferring data across Ethernet The IP stack is processor demanding and therefore it is important to configure and use the stack optimally in order to get high throughput In order to improve Gigabit Ethernet throughput the BSP has implemented support for JUMBO packets This feature enhances the Ethernet throughput performance significantly The maximum size of the JUMBO packets for the PPC440GX is 9000 bytes By default the size is set to 8000 since this gives better alignment with the internal buffer sizes in the PPC440GX It is important that Gigabit Ethernet switches that are used together with JUMBO packets have support for JUMBO packet
22. MES WE eode ador Poor RR Ls whee PU haan HORS 131 mfs pwd 131 Infs ibi gettext esee ence heehee e 132 xii M5000 Series BSP User Guide Issued June 20 2007 1 49 vmernoll innovation deployed infs ani settext L o2conbheD ep EX lacie GR RUE e 133 mfs ini setlong 133 mfs mi selong 48e wwe woe es EN Ie 134 mfs ini getlong 134 mfs ust load files ces sue p ces ke Vee eae neue 135 11 2 The vxbsp ami File vetet toe tp a ne ptt enr 136 The RACEdrv Section 136 The Vmelnterface Section 136 11 3 The trimon anr File deor o e ER e E re t s 137 The BoardInfo Section 137 The AutoStart Section 137 Fibre Channel Support ix esum ee Elantra whee des ERA 139 12 1 Fibre Channel Information 140 OVERVIEW us sud vede ee inner QR Bale Aa hae Rae iet date R 140 APFENDIXE rmm 141 Troubleshooting seas Ohne SN Deer OEE RAE GUERRE NO ERED 143 Hello World Example Using WorkBench 144 Deprecated PUHOONSS oso eene oai Rw RN A RRR ADR EEA 145 pciToLocalAdrs replaced with sysBusToLocalAdrs 146 peiLocalToPciAdrs replaced with sysLocalToBusAdrs 147 Built In Self Test BIST APL
23. PWEN VDW 0 MEM d2000000 d2000000 00000000 00010000 2d Y 32 1 MEM d1000000 d1000000 00000000 01000000 3d Y 32 2 MEM c0000000 c0000000 00000000 11000000 0d Y 32 Universe VME slave images PCI master windows Size VMEAM codes PWEN PREN LD64 LRMW Fl Image Type Local PCL VMI 5 MEM 00000000 00000000 00000000 10000000 09 Oa Od Oe Y Y N N This default configuration covers the VMEbus interface requirements of many applications but not all Changing PCI Slave Image Configuration There are several ways to change the PCI slave image configuration to customize to application requirements Option 1 The simplest approach is to modify the constants in the BSP that determine the VME base addresses sizes and AM codes of the default PCI slave images The BSP can then be recompiled and reloaded into the M5xxx This is appropriate when only one or two VME regions are required which may be the case when interfacing to one or two external VME resources Issued June 20 2007 M5000 Series BSP User Guide 69 VME Bus Operation VMETRO E innovation deployed For example suppose the M5xxx needs to interface with a VME based digitizer board that uses 16 MiB of VME A32 space specifically AM code 0x09 starting at 0x60000000 in VME A32 space If there are no other VME interface requirements the existing A32 window can be modified This is done by modifying the code in sysVme c that sets up the PCI slave
24. SLV BUS using VME A32 SLV SIZE and the processor number 3 VME A32 SLV LOCAL Local bus base of window Do not change this value Issued June 20 2007 M5000 Series BSP User Guide 61 VME Bus Operation VMETRO 5 innovation deployed Functions uniPciSlaveImageSet Synopsis Description STATUS uniPciSlaveImageSet int image UINT32 pciBase UINT32 vmeBase UINT32 size UINT32 pciAddrSpace UINT32 vmeAmCode UINT32 vmeDataWidth BOOL postedWrites image the Universe PCI slave image number from 0 7 pciBase the PCI base address of the window vmeBase the VME base address of the window size the size of the window in bytes pciAddrSpace the PCI address space The value can be either UNI PCI MEMORY SPACE 0 UNI PCI IO SPACE 1 or UNI PCI CFG SPACE 2 vmeAmCode the VME AM code specifying a block type AM code also implies that the similar AM code corresponding to single cycles will also be supported by the window vmeDataWidth the data width supported by the window The value can be either UNI VMEBUS DATAWIDTH 8 0 UNI VMEBUS DATAWIDTH 16 1 UNI VMEBUS DATAWIDTH 32 2 or UNI VMEBUS DATAWIDTH 64 3 postedWrites whether the window allows posted cached writes The value should be either TRUE 1 or FALSE 0 This function is used to configure a Universe PCI slave image This allows the M5xxx to act as a VME master and read write to
25. Size 5 MEM 00000000 00000000 00000000 11000000 value 0 0x0 unilmageShow VMEAM codes PWEN PREN LD64 LRMW 09 0a 0d 0e Y Y N N M5000 Series BSP User Guide Issued June 20 2007 VMETRO uj Configuring PCI Slave Images in the Universe innovation deployed 5 2 Configuring PCI Slave Images in the Universe Procedure PCI slave images are used whenever the M5xxx needs to access external VME resources The Universe supports up to 8 PCI slave images By default the M5xxx BSP uses 3 of the 8 PCI slave images These PCI slave images support 256 MiB 16 MiB in VME A32 space starting at 0x00000000 16 MiB in VME A24 space starting at 0x000000 and 64 KiB in VME A16 space starting at 0x0000 A fourth PCI slave image optionally used by the BSP is disabled by default It can be enabled by using the VmeA32Master2Base flag in the VmelInterface section of the vxbsp ini file If this parameter is present the fourth PCI slave image will support 64 KiB in VME A32 space starting at the value of the VmeA32Master2Base parameter Viewing PCI Slave Image Configuration A convenient way to view how the Universe PCI and VME slave images are configured is to use the uni ImageShow function In the default BSP configuration the uni ImageShow function gives the following information unilmageShow Universe PCI slave images VME master windows Image Type Local PCI Base VME Base Size VMEAM
26. User defined User defined User defined User defined Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved A16 non priv 32 bit access Reserved Reserved A16 LOCK command A16 supervisory 32 bit access Reserved Config ROM Control Status Register Reserved Reserved A24 LOCK command No No No No No No No No No No No No No No No No No No Yes No No No Yes No No No No 58 M5000 Series BSP User Guide Issued June 20 2007 VMETRO i VME Master amp Slave Access Configuration innovation deployed TABLE 5 2 M5xxx Supported VME AM Codes Continued 0x33 110011 Reserved No 0x34 110100 A40 access No 0x35 110101 A40 LOCK command No 0x36 110110 Reserved No 0x37 110111 A40 block transfer No 0x38 111000 A24 non priv 64 bit block transfer Yes 0x39 111001 A24 non priv 32 bit data transfer Yes 0x3a 111010 A24 non priv 32 bit program access Yes Ox3b 111011 A24 non priv 32 bit block Yes Ox3c 111100 A24 supervisory 64 bit block transfer Yes Ox3d 111101 A24 supervisory 32 bit data transfer Yes Ox3e 111110 A24 supervisory 32 bit program access Yes Ox3f 111111 A24 supervisory 32 bit block Yes VME Master PCI Slave Access Windows A VME master access window is a window from the M5xxx onto the VME bus A master access window enables the M5xxx board to become a VME bus master The PPC
27. buffer is now inconsistent with the cache To handle cache coherency problem on the M5xxx board the user has three options use cache safe buffers Cache safe buffer is the best approach since data integrity is assured on a per buffer basis and the performance penalty of calling cacheInvalidate is avoided The MSxxx BSP supports the VxWorks routine cacheDmaMalloc whenever MMU support is included the default case call cacheInvalidate before reading from the local buffer and call cacheFlush after writing to the local buffer disable the data cache This is not recommended except during device driver debugging Default Memory Configuration 1000 0000 34 SysPhysMemTop Non Cached 0E00 0000 NONCACHEABLE MEMORY SIZE SysPhysMemTop NONCACHEABLE MEMORY SIZE Cache Unused 0200 0000 SysMemTop Cached 0000 0000 LOCAL MEM LOCAL ADRS FIGURE 2 1 Default Memory Configuration Issued June 20 2007 M5000 Series BSP User Guide 11 System Memory vmernoB innovation deployed 2 3 Error Checking and Correction ECC The MIDAS M5xxx BSP supports Error Checking and Correction ECC Switch 6 2 on the MIDAS board is used to switch ECC on and off When sw6 2 is ON ECC is Enabled The ECC feature automatically corrects 1 bit errors 2 bit and multiple bit errors are not corrected and will result in the suspension of the t
28. csh script depending on which platform and shell is used In Solaris the torVars script is run using source torVars sh or source torVars csh Running torVars csh or torVars sh without using the source command won t work Having installed Tornado 2 2 1 with patch 90451 and run the torVars script in the current shell the BSP should be able to compile using commands such as make make vxWorks make vxWorks st_rom bin or make bootrom bin ADDED CFLAGS DBOOT ROM from the BSP directory The bootrom bin should be compiled with the ADDED CFLAGS DBOOT ROM option in order to not include Flash and Built In Self Test functionality in the bootrom image 144 M5000 Series BSP User Guide Issued June 20 2007 vmernoll innovation deployed If you encounter problems compiling the BSP after having installed Tornado 2 2 1 with Patch 90451 and run the torvars script check that the WIND BASE environment variable correctly points to the Tornado 2 2 1 90451 installation Issued June 20 2007 M5000 Series BSP User Guide 145 Troubleshooting vmcernol innovation deployed 146 M5000 Series BSP User Guide Issued June 20 2007 VMETRO ation deployed DeprecatedFunctions Issued June 20 2007 M5000 Series BSP User Guide 145 Deprecated Functions VMETRO E innovation deployed pciToLocalAdrs replaced with sysBusToLocalAdrs Synopsis int pciToLoc
29. known as PCI auto configuration In the rare cases in which the user wishes to perform manual configuration of P2P bridges the functions to do so are available in the BSP However the user is cautioned that improperly changing the configuration of onboard P2Ps can have unexpected results particularly if the P2P bridges are configured with inconsistent PCI bus numbers See the section on PCIbus operations for more information There are many switches on the M5xxx that are fully documented in the M5xxxUser Guide 2 Only a few of the switches affect the operation of the BSP and these are shown in the table below Default positions are noted in bold TABLE 1 1 M5xxx switch settings affecting BSP Switch sw10 3 sw10 4 sw10 1 sw3 4 sw6 2 Controls CPU FLASH write enable CPU FLASH Monitor write enable CPU Serial EEPROM write enable Controls board Reset to VME Reset propagation This affects the function systemReset ECC Closed Write disabled Write enabled Write enabled Enabled Disabled Open Write enabled Write disabled Write disabled Disabled Enabled Default position Write enabled Write disabled Write enabled Enabled Disabled Issued June 20 2007 M5000 Series BSP User Guide bent VIMETRO innovation deployed 1 2 M5xxx Model Numbering The MSxxx is offered with a number of optional components leading to many different possible hardware configurations Th
30. oso AZIS UALSVIN TEV ANA aM 9D AZIS WHISVIN tCV ANA gr v9 AZIS UALSVW 9IV ANA azig mepa OZI XDOrPOdd 01 siurod 00000000X0 esegrodz4eiseWztVv9euA ep qerreA eqo o esegriodaej3sewzteVeuA e qeLreA eqo o esegioga943seyWp ZVOUA epqerreA eqo o esegroga493seqwo LV9uA ep qerreA eqo o 9seg 19d 00001x0 x umNoo1ds s 00000080X0 ST oseg os 0 sr oseg 0 ndO H AO Iurdsqxa ut esegeAeTSz veuA Iur dsqxA Ul oSegza49 3s enc EV9uA 00000000X0 HSVH ANA ZEY AWA OL DOT SVGIIN 00000000X0 HSVH ANA tcV ANA OL DOT SVGIIN 00000000X0 HSVH ANA 9IV ANA OL DOT SVGIIN 9seg ANA SAIS TNA cv SAIS Od TEV 98 DALIS Od TEV PAS Od vCV DALIS Od 9Iv uondrbsoq Issued June 20 2007 M5000 Series BSP User Guide 32 vmernoll innovation deployed VME Master amp Slave Access Configuration FIGURE 5 1 Default Usage of Outbound VME A32 Address Space Issued June 20 2007 M5000 Series BSP User Guide 53 VME Bus Operation vmernoU innovation deployed 32 bit virtual Address Outbound VMEbus Map by bsp A24 Address Map FFFF FFFF Flash Memory FE00 0000 PCI X bridge FD00 0000 Not Mapped unused FCO00 0000 32 bit PCI 1 0 outbound F880 0000 Not mapped unused F801 0000 16 bit PCI 1 O outbound F800 0000 PLD F500 0000 Flash Memory F300 0000 SRAM F200 0000 120
31. other VMEbus devices configured as VME slaves 62 M5000 Series BSP User Guide Issued June 20 2007 VMETRO i VME Master amp Slave Access Configuration innovation deployed uniPciSlaveImageSet Continued Returns OK Or ERROR Example This example sets up a PCI slave image at PCI address 0xb0000000 and VME address 0x50000000 The VME address space is A24 the size of the window is 0x400000 4 MB The AM code is 0x3c A24 supervisory 64 bit block transfer Using this AM code implies that AM code 0x3d A24 supervisory data access is also supported Also note that even though the AM code specifies 64 bit only 32 bit data width will be supported because UNI_VMEBUS DATAWIDTH 32 is specified uniPciSlavelmageset 7 0xb0000000 0x50000000 0x400000 UNI PCI MEMORY SPACE 0x3c UNI VMEBUS DATAWIDTH 32 TRUE Issued June 20 2007 M5000 Series BSP User Guide 63 VME Bus Operation VMETRO E innovation deployed uniVmeSlavelmageSet Synopsis STATUS uniVmeSlaveImageSet int image UINT32 vmeBase UINT32 pciBase UINT32 size UINT32 pciAddrSpace UINT32 vmeAmCode BOOL postedWrites BOOL prefetchReads BOOL pci64 BOOL pciLockOnRMWs image the Universe VME slave image number from 0 7 vmeBase the VME base address of the window pciBase the PCI base address of the window size the size of the window in bytes pciAddrSpace the PCI ad
32. possible to change but it must be within the Flash address area If the Flash is locked by switch settings the 1ash Load command will inform the you about this The M5000 User Guide explain how the locking unlocking of Flash through DIP switches is performed The default address 0xf4000000 is not locked by fabric switch settings Issued June 20 2007 M5000 Series BSP User Guide 105 Burning VxWorks Boot Code VMETRO E innovation deployed 9 3 Burning VxWorks Boot Code from U Boot Ethernet The M5000 board is shipped with a U Boot image programmed in Flash memory U Boot is a bootloader with an ethernet driver which is used to load and boot Linux on the M5000 board Additionally U Boot can load and flash VxWorks images across Ethernet which is the preferred method Serial loading with the MIDAS Monitor is the only alternative In order to download a VxWorks binary image to the M5000 U Boot supports two communication protocols TFTP client and NFS client The VxWorks image must be available on a networked TFTP server or NFS server in order to load the image The U Boot command sequence in order to download a VxWorks image is described below Setting Network Parameters The following command sequence is required to setup the network parameters for both TFTP and NFS download methods 1 Specify which ethernet port to use ppc 440x eth0 ppc 440x ethl ppc 440x eth2 or ppc_440x_eth3 gt setenv ethact ppc 440x et
33. that an adrsSpace value of PCI SPACE CFG PRI is not supported In other words sysLocalToBusAdrs cannot be used to determine the PCI Config Space equivalent of local address space because there is no such direct address mapping between local and PCI configuration space Returns OK Or ERROR Example This example allocates a cacheable buffer and determines the PCI address of the buffer char bufLocal bufPci bufLocal char malloc 1000 if sysLocalToBus PCI SPACE MEM PRI bufLocal amp bufPci return ERROR printf The PCI address of the buffer is Ox xWMn bufPci 18 M5000 Series BSP User Guide Issued June 20 2007 VMETRO 5 PCI Interrupt Handling innovation deployed 3 4 PCI Interrupt Handling This chapter documents interrupt routing and handling in the M5xxx implementation The PCI autoconfigurator automatically configures the PCI configuration space registers known as Interrupt Line offset 0x3c and Interrupt Pin offset 0x3d for each PCI device However the PCI autoconfigurator does not install any Interrupt Service Routines ISRs Setting up the ISRs is typically performed by device drivers In general device drivers are specific to the operating system i e VxWorks 5 5 as well as the type of CPU 1 e PPC440GX They are often supplied by the manufacturer of PCI devices The M5xxx BSP includes the device drivers for all PCI devices mounted on the M5xxx itself ex
34. 0 Description A64 64 bit block transfer A64 32 bit single transfer Reserved A64 32 bit block transfer A64 LOCK command A32 LOCK command Reserved Reserved A32 non priv 64 bit block transfer A32 non priv 32 bit data access A32 non priv 32 bit program access A32 non priv 32 bit block transfer A32 supervisory 64 bit block transfer A32 supervisory 32 bit data access A32 supervisory 32 bit program access A32 supervisory 32 bit block transfer User defined User defined User defined User defined User defined User defined User defined Supported Yes Yes No Yes No No No No Yes Yes Yes Yes Yes Yes Yes Yes No No No No No No No Issued June 20 2007 M5000 Series BSP User Guide 57 VME Bus Operation vmernoU innovation deployed TABLE 5 2 M5xxx Supported VME AM Codes Continued 0x17 0x18 0x19 Oxla Ox1b Oxic Oxld Oxle Oxif 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2a 0x2b 0x2c 0x2d 0x2e 0x2f 0x30 0x31 0x32 01 0111 01 1000 01 1001 01 1010 01 1011 01 1100 01 1101 01 1110 01 1111 10 0000 10 0001 10 0010 10 0011 10 0100 10 0101 10 0110 10 0111 10 1000 10 1001 10 1010 10 1011 10 1100 10 1101 10 1110 10 1111 11 0000 11 0001 11 0010 User defined User defined User defined User defined User defined
35. 000 to match the size of the requirement for Board 1 define VME A32 MASTER SIZE 0x20000000 Three more PCI slave images must still be configured to meet the interface requirements In this example the optional fourth PCI slave image may be used for the one of these three PCI slave images To properly configure the P2P bridges change the value of VME A32 MASTER 2 SIZEin sysVme h to 0x30000000 The value of VmeA32Master2Base should also be set in vxbsp ini for example to 0x40000000 This can be done from the Midas monitor with the line miset VmeInterface VmeA32Master2Base 0x40000000 vxbsp ini 72 M5000 Series BSP User Guide Issued June 20 2007 vmernoll innovation deployed Configuring PCI Slave Images in the Universe After rebooting uniImageShow shows EN LD64 LRMW unilmageShow Universe PCI slave images VME master windows Image Type Local PCI Base VME Base Size VMEAM PWEN VDW 0 MEM e1000000 e1000000 00000000 00010000 2d Y 32 1 MEM 50000000 50000000 00000000 01000000 3d ng 32 2 MEM 90000000 90000000 10000000 20000000 Od Y 32 3 MEM 11000000 b1000000 40000000 30000000 0d Y 32 Universe VME slave images PCI master windows Image Type Local PCI VME Size VMEAM codes PW 5 MEM 00000000 00000000 00000000 10000000 09 Oa Od Oe Y The following command reconfigures the optional PCI slave image window uniPciSlave
36. 107 Burning VxWorks Boot Code VMETRO E innovation deployed 108 M5000 Series BSP User Guide Issued June 20 2007 vmernoll innovation deployed DMA drivers The MSxxx has several on board DMA controllers including the PPC440GX Universe and PXB which move data between DRAM PCI memory VME and RACEway DMA drivers are included in the M5xxx BSP for the PPC440GX Issued June 20 2007 M5000 Series BSP User Guide 109 DMA drivers VMETRO m innovation deployed 10 1 PPC440GX DMA Driver The PPC440GX DMA Driver is capable of moving data to from any memory reachable from the PPC440GX However for performance reasons this driver is mostly applicable for data transfers involving system DRAM Once the DMA transfer is initiated data is moved without any need for processor intervention The driver supports one channel transfers where the transfers can be single DMA transactions or chained scather gather DMA transactions To use the PPC440GX DMA driver include the ppe440DmaLib h header file from the BSP distribution Setting up a DMA transaction A DMA transaction is set up by using a DMA transaction structure The structure is defined as follows typedef struct ppc440DmaTransactionInfo int Channel Always 0 int Alignment uint32 t TransferByteCount uint32 t SourceAddressLow uint32 t SourceAddressHigh uint32 t DestinationAddressLow uint32 t DestinationAddressHigh int Status int
37. 440GX access to a local address within the window generates a VME bus transaction This is what referred to as address translation mapping The M5xxx BSP defines three VME master access windows VME A32 A24 and A16 and optionally one additional A32 window referred to as the secondary VME master access window Each window is defined by a set of three macros the PCI base VME bus base and window size See Table 4 for a summary of the default windows and their sizes The following macro defines a window onto VME A16 address space from the PPC440GX 1 PCI base address of the VME A16 window is configured automatically The base address is stored in the global variable VmeA 16MasterPciBase 2 VME A16 MASTER BASE VME A16 base of window M5xxx BSP default is 0x0 3 VME A16 MASTER SIZE size of the window into A16 space M5xxx BSP default value is 64KB The following macro defines a window onto VME A24 address space from the PPC440GX 1 PCI base address of the VME A24 window is configured automatically The base address is stored in the global variable VmeA24MasterPciBase 2 VME A24 MASTER BASE VME A24 base of window M5xxx BSP default is 0x0 3 VME A24 MASTER SIZE size of the window into A24 space M5xxx BSP default value is 16MB The following macros define a window onto VME A32 address space from the PPC440GX Issued June 20 2007 M5000 Series BSP User Guide 59 VME Bus Operation VMETRO 5 innovation deployed
38. 8180 Montigny le Bretonneux Contact Alain D Aux Phone 33 1 30 07 00 60 Fax 33 1 30 07 00 69 info vsystems fr Italy VSYSTEMS srl via Cavour 123 10091 Alpignano TO Contact Luca Ravera Phone 39 11 9661319 Fax 39 11 9662368 info vsystems it vmernoll innovation deployed Preface Introduction The VMETRO MIDAS M5000 is a single board computer SBC built in a GU VMEbusform factor based on the AMCC PPC440GX PowerPC processor This document describes the Vx Works Board Support Package BSP for the PPCA40GX processor on the VMETRO MIDAS 5000 series products This User s Guide provides important information on all aspects of the MIDAS M5xxx VxWorks Board Support Package BSP Answers to questions such as How do I install the BSP How do I boot the MIDAS board How do I burn VxWorks boot code How do I configure the MIDAS board to be VME bus master slave at certain base addresses How do I connect a PCI interrupt How do I read write the registers of a PCI device Etc can be found in this document The chapters are summarized below Overview provides a brief description of the PPCA40GX processor and its surroundings Model Numbering describes the model numbering approach used Address Maps and Address Space Mapping describes the address space layout for both PPC440GX local and PCIbus perspectives System Memory describes the SDRAM memory system used and describes how to access additional memory Cache safe Buffers
39. 9 Not Used X SDRAM mapped by PIMO 0 1000 0000 Was i 0 0000 0400 SERAM Sa 120 Msg Unit 000000000 LL 0 0000 0000 FIGURE 1 3 nbound Address Mapping from PCI Memory Space with PCI Auto Configuration TABLE 1 4 Effective virtual address space of PPC440GX to PCI I O Space Local Memory Range PCI I O Address range Resource Mapped Mapped by 0xf 8800000 0xfbffffff 0x800000 0x4000000 32 bit PCI I O Space MMU 0x 8000000 0xf800ffff 0x0 0x1000 16 bit PCI I O Space MMU The figure below shows how the Effective virtual address space of PPC440GX memory maps to PCII O Space Issued June 20 2007 M5000 Series BSP User Guide 7 Overview vmernoUl innovation deployed FFFF FFFF FE00 0000 FD00 0000 FC00 0000 F880 0000 F801 0000 F800 0000 F400 0000 F300 0000 F200 0000 F100 0000 F000 0000 C000 0000 1 0000 0000 0 0000 0000 32 bit virtual Address Map by bsp Flash Memory PCI X bridge Not Mapped unused 32 bit PCI I O outbound Not mapped unused 16 bit PCI 1 0 outbound Flash Memory PLD SRAM 120 Internal CPU Peripherals PCI Memory outbound window without prefetch PCI Memory outbound window with prefetch local PPC 440 SDRAM PCI memory Space FFFF FFFF 400 0000 0080 0000 0001 0000 Address Map Not Used 32 bit PCI I O Not Used 16 bit PCI 1 0 FIGURE 1 4 Address Mapping from Loc
40. BUS 4 5 PciBusNo The PCI bus number Description This function translates a PCI bus number to its corresponding Midas bus ID The MIDAS bus ID is a software reference to one of the possible PCI X PCI buses on the M5xxx board The PCI bus number is the actual PCI bus number stored in the bus number registers of the P2P bridges on a particular segment If any PMC cards or any other interconnect bridge implements a PCI bus which is physically off board the M5xxx the corresponding PCI bus number cannot be mapped to a MidasBusId because only onboard busses have been assigned a MidasBusld value MidasBusIdFromPciBusNo will return ERROR for off board PCI bus numbers Returns OK or ERROR 22 M5000 Series BSP User Guide Issued June 20 2007 vmernoll innovation deployed PCI Bus Operations MidasBusIdFromPciBusNo Continued Example UINT8 MidasBusId UINT8 PciBusNo for PciBusNo 0 PciBusNo lt 255 PciBusNo if MidasBusIdFromPciBusNo amp MidasBusId PciBusNo ERROR switch MidasBusId case MIDAS PRIMARY BUS printf Midas primary PCI bus corresponds to PCI bus number x n PciBusNo break case MIDAS SECONDARY BUS printf Midas secondary PCI bus corresponds to PCI bus number x n PciBusNo break case MIDAS TERTIARY BUS printf Midas tertiary PCI bus corresponds to PCI bus number x n PciBusNo break case MIDAS QUATERNARY BUS prin
41. DMA transaction on page 110 for a description timeout Driver timeout for execution The PPC440GX DMA engine does not support timeouts Thus this timeout is only used in software when waiting for control over the engine dmaStatus Pointer to a status structure See Common status structure on page 114 for a description This structure is only used on ERROR The return value for the ppc440Dmaxfer functions only reflects whether the driver was able to initiate the transfer or not To find the status of the actual transfer the relevant fields in the DMA transaction structure must be checked Chained DMA transactions Transfers involving one or more DMA transactions are executed through the ppc440DmaChainXfer function DMA chains can only be executed in a non blocking mode Before a chain can be executed a DMA descriptor must be created through the ppc440DmaChainDescCreate function This function is defined as follows ppc440DmaChainDesc t ppc440DmaChainDescCreate ppc440DmaTransaction t trans ppc440DmaChainDesc t prev ppc440DmaChainDesc t next ppc440DmaStatus t dmaStatus The fields are used as follows trans Pointer to a DMA transaction structure See Setting up a DMA transaction on page 110 for a description Since DMA chains can only be executed in non blocking mode the user application must fill in the callback fields The user application may choose not to have a callback on every transacti
42. E00 0000 PCI X bridge FDOO 0000 Not Mapped unused FCO00 0000 32 bit PCI I O outbound F880 0000 Not mapped unused F801 0000 16 bit PCI 1 O outbound F800 0000 PLD F500 0000 Flash Memory F300 0000 SRAM F200 0000 120 F100 0000 Internal CPU Peripherals F000 0000 PCI Memory outbound window without prefetch C000 0000 PCI Memory outbound window with prefetch 1 0000 0000 Ee local PPC440 SDRAM 0 1000 0006 0 0000 0400 p Im PPC440GX 120 ce 0 0000 0000 0 0000 0000 FIGURE 5 4 Default Usage of Inbound VME A32 Address Space 56 M5000 Series BSP User Guide Issued June 20 2007 vmernoll innovation deployed VME Master amp Slave Access Configuration VME Address Modifier AM Codes VME Address Modifier AM codes are a standard part of the VMEbus Specification 6 In this section the VME AM codes will be reviewed along with an indication of whether each is supported by the address translation functions sysBusToLocalAdrs and sysLocalToBusAdrs in the BSP The Universe driver can be setup to support all AM codes except A64 codes TABLE 5 2 M5xxx Supported VME AM Codes HEX Binary 0x00 00 0000 0x01 000001 0x02 00 0010 0x03 00 0011 0x04 00 0100 0x05 000101 0x06 00 0110 0x07 000111 0x08 00 1000 0x09 001001 0x0a 00 1010 Ox0b 001011 Ox0c 00 1100 Ox0d 00 1101 Ox0e 001110 Ox0f 00 1111 0x10 01 0000 0x11 01 0001 0x12 010010 0x13 010011 0x14 010100 0x15 010101 0x16 01 011
43. F100 0000 Internal CPU Peripherals P0000000 PCI Memory outbound window without prefetch VmeA32MasterPciBase POMI C000 0000 PCI Memory outbound window with prefetch 1 0000 0000 FF FFF local PPC440 SDRAM 0 0000 0000 0 0000 0000 FIGURE 5 2 Default Usage of Outbound VME A24 Address Space 54 M5000 Series BSP User Guide Issued June 20 2007 VMETRO VME Master amp Slave Access Configuration innovation deployed 32 bit virtual Address Outbound VMEbus Map by bsp A16 Address Map FFFF FFFF Flash Memory FEO00 0000 PCI X bridge FD00 0000 Not Mapped unused FCO00 0000 32 bit PCI I O outbound F880 0000 Not mapped unused F801 0000 16 bit PCI 1 0 outbound F800 0000 PLD F500 0000 Flash Memory F300 0000 SRAM F200 0000 120 F100 0000 Internal CPU Peripherals T000 0900 PCI Memory outbound window without prefetch VmeA32MasterPciBase PO ai n C000 0000 PCI Memory outbound window with prefetch POMO 1 0000 0000 FFFF local PPC440 SDRAM 0 0000 0000 0000 FIGURE 5 3 Default Usage of Outbound VME A16 Address Space Issued June 20 2007 M5000 Series BSP User Guide 55 VME Bus Operation VMETRO E innovation deployed 32 bit virtual Address Inbound VMEbus Map by bsp A32 Address Map FFFF FFFF Flash Memory FFFF FFFF Not Used F
44. In combination with other PCI related functions this information can be used to read write the configuration registers of the device Note that when the PMC contains a P2P bridge this function returns the PCI device number for the P2P bridge The PCI device numbers for any devices behind the PMC s bridge are set by the PMC itself Returns OK Or ERROR Example struct MIDAS PCI SLOT INFO slot info if MidasPmcSlotInfoGet 1 amp slot info ERROR return ERROR printf For the PMC in slot 1 Win printf The device name is s Mn slot info Name printf The device number is d Mn slot info PciDeviceNo switch slot info MidasBusId case PRIMARY PCI BUS printf PRIMARY PCI bus break case SECONDARY PCI BUS printf SECONDARY PCI bus break case TERTIARY PCI BUS printf TERTIARY PCI bus break case QUATERNARY PCI BUS printf QUATERNARY PCI bus break case MEZZ500 PCI BUS printf MEZZ500 PCI bus break default printf Unknown PCI bus break 26 M5000 Series BSP User Guide Issued June 20 2007 VMETRO 5 PCI Bus Operations innovation deployed MidasPciSlotInfoGet Synopsis int MidasPciSlotInfoGet int iPciSlotTblIdx MIDAS PCI SLOT INFO pMidasPciSlot iPciSlotTblIdx The PCI slot table index Must be one of the MPSLOT X constants defined in MidasPciLib h PMidasPciSlot pointer to structure defined as follows struct MIDAS PCI SLOT INFO c
45. JUMBO packets is not needed in order to maximize the throughput potential of Fast Ethernet By default the fast Ethernet channels are configured to use 1500 bytes Ethernet frame sizes MTU while the Gigabit Ethernet channels are configured to use 8000 bytes Ethernet frame sizes When the Ethernet Network Interface communicates with other Ethernet network devices the network devices will negotiate and use the smallest of the maximum frame sizes of both of the devices The configuration of MTU sizes should therefore not break communication between network devices The PPC440GX supports MTU sizes up to 9000 bytes The default MTU size is set to 8000 this is because 8000 is better aligned with the MAL buffer sizes than the maximum MTU 9000 and therefore gives higher performance MTU size can be configured in config h EMAC uA define define define define MTU Size is the maximum packet size the EMAC is configured to use when communicating with other Ethernet devices Maximum MTU size for the PPC440GX is 9000 The Fast Ethernet EMACS have a default value of 1500 The Gigabit Ethernet EMACS have a default value of 8000 The default value of 8000 for the Gigabit Ethernet EMACS gives an optimal performance due to alignment with the MAL buffer size MTU Size EMACO MTU 1500 Fast Ethernet Channel EMAC1 MTU 1500 Fast Ethernet Channel EMAC2 MTU 8000
46. NTA The Interrupt Pin register can be read to determine which of the four pins each device uses see the PCI Specification 3 Interrupt Routing and Sharing The M5xxx implements sixteen interrupt inputs to the PPCA40GX See M5xxx User Guide 2 for a description of how interrupts from the various devices are routed to the Universal Interrupt Controller UIC of the PPC440GX Some of the PPC440GX interrupt inputs are shared between PCI devices Additionally some PCI devices implement more than one interrupt output and may have multiple interrupt outputs routed to the same PPC440GX interrupt input For example PMC 2 s INTA and INTC are both connected to interrupt input 1 of the PPCA40GX If a multifunction device is installed on PMC 2 and two of its functions asserted INTA and INTC respectively an interrupt on either of those lines would be sent to interrupt input 1 of the PPC440GX Issued June 20 2007 M5000 Series BSP User Guide 19 PCI Bus Operation VMETRO E innovation deployed Interrupt Connection and Enabling The pciIntConnect routine will install an interrupt handler for any vector in the table regardless of whether that vector is associated with an input to the UIC The PowerPC architecture also defines the functions intEnable and intDisable Following connection with pcilntConnect an interrupt must be enabled by calling intEnable In the M5xxx BSP implementation these functions operate only on interrup
47. O0 printf ERROR setsockopt failed for SO SNDBUF n if setsockopt fd SOL SOCKET SO RCVBUF char amp soRcvBufSize sizeof soRcvBufSize 0 printf ERROR setsockopt failed for SO RCVBUF n 92 M5000 Series BSP User Guide Issued June 20 2007 innovation deploye BSP Installation Issued June 20 2007 M5000 Series BSP User Guide 99 BSP Installation VMETRO E innovation deployed 8 1 BSP Installation amp Distribution Installation The M5xxx BSP is distributed on CD ROM media Refer to the CD ROM for installation procedure This BSP is only compatible with Tornado 2 2 1 which includes VxWorks 5 5 1 with Patch 90451 applied The patch can be obtained from Wind River Systems technical support Files amp Directories The following is a summary of M5xxx PPC440GX BSP software distribution This distribution contains all the BSP specific files that allows VxWorks to run on the M5xxx doc this directory contains all of the documentation for the BSP mdrv this directory contains all MSxxx specific drivers and associated header files mdrv include this directory contains all the BSP user include header files mdrv include Common h numerous common definitions used by the BSP mdrv include flash h flash memory driver header file mdrv include flashlib h flash storage device interface library header file mdrv include i20_mu h 120 message unit header file mdrv incl
48. PSLOT UNIVERSE amp slot info ERROR return ERROR if MidasBusIdToPciBusNo slot info MidasBusId amp PciBusNo ERROR return ERROR pciConfigInLong PciBusNo slot info PciDeviceNo 0 0x10 amp bar0 if sysBusToLocal PCI SPACE MEMIO PRI char bar0 char amp localAdrs return ERROR printf The UCSR is at 0x x in local address space n localAdrs Issued June 20 2007 M5000 Series BSP User Guide 17 PCI Bus Operation VMETRO E innovation deployed sysLocalToBusAdrs Synopsis STATUS sysLocalToBusAdrs int adrsSpace char localAdrs char pBusAdrs adrsSpace Represents the bus address space in which pBusAdrs resides The value can be one of the following PCI SPACE IO PRI 0x40 32 bit PCI I O Space PCI SPACE MEMIO PRI 0x41 Non cacheable PCI Memory Space PCI SPACE MEM PRI 0x42 Cacheable PCI Memory Space PCI SPACE IO16 PRI 0x43 16 bit PCI I O Space A supported VMEbus AM code see section on VMEbus localAdrs the local address to be converted to a bus address pBusAdrs holds the returned bus address equivalent of localAdrs if it exists Description This function converts a local address to a bus address The bus address can be in either a PCI and VME address space If the given local address can be converted to a bus address the bus address is placed in pBusAdrs and the function returns OK Otherwise ERROR is returned Note
49. S sysBusToLocalAdrs int adrsSpace char busAdrs char pLocalAdrs adrsSpace Represents the bus address space in which busAdrs resides The value can be one of the following PCI SPACE IO PRI 0x40 32 bit PCI I O Space PCI SPACE MEMIO PRI 0x41 Non cacheable PCI Memory Space PCI SPACE MEM PRI 0x42 Cacheable PCI Memory Space PCI SPACE IO16 PRI 0x43 16 bit PCI I O Space A supported VMEbus AM code see section on VMEbus busAdrs the bus address to be converted to a local address pLocalAdrs holds the returned local address equivalent of the busAdrs if it exists Description This function converts a bus address to a local address The function can be used with both PCI and VME address spaces If the given bus address can be converted to a local address the local address is placed in pLocalAdrs and the function returns OK Otherwise ERROR is returned Note that an adrsSpace value of PCI SPACE CFG PRI is not supported In other words sysBusToLocalAdrs cannot be used to determine the local address space equivalent for PCI Config Space because there is no such direct address mapping between local and PCI configuration space Returns OK or ERROR Example This example finds the Universe UCSR held in BARO of the Universe in local address space struct MIDAS PCI SLOT INFO slot info UINT32 PciBusNo bar0 localAdrs Get slot info for the Universe if MidasPciSlotInfoGet M
50. S5xxx SBC Complete details on the CPU itself may be found in the PPC440GX Embedded Processor User s Manual 1 available from AMCC See Related Documentation on page vii Note The BSP requires Tornado 2 2 1 with patch 90451 available from Wind River Issued June 20 2007 M5000 Series BSP User Guide bent vmernoUl innovation deployed 1 1 Overview The AMCC PPC440GX Embedded Processor hereafter referred to simply as PPC440GX or 440 combines a PowerPC 440 processor core and various on board peripheral components including L2 cache controller SRAM controller DDR SDRAM controller PCI X controller DMA controller Ethernet controllers including support for Gigabit Ethernet timers serial ports and others The MIDAS M5xxx implementation incorporates the PPC440GX operating at a core speed of 500 667 MHz 256 MBof SDRAM on a 166 MHz memory bus and 16 MiB of FLASH ROM The M xxx interfaces the 440 to the PCI X bus and provides access to all other PCI X devices The M5xxx includes a Qlogic ISP2312 dual channel Fibre Channel interface The M5xxx also includes a Universe IID controller for interfacing with VME The M5xxx may optionally include a RACEway interface PXB The M5xxx has two PCI X compatible PMC sites where optional or user supplied modules may be mounted shows a simplified block diagram of the MSxxx As shows the MIDAS M xxx board architecture implements a total of three separate PCI X busses an
51. Series BSP User Guide Issued June 20 2007 VMETRO i Universe DMA Functionality innovation deployed uniDmaDirect STATUS uniDmaDirect UINT32 vmeAdrs UINT32 pciAdrs UINT32 byteCount UINT32 vmeAmCode BOOL pci64 int direction Synopsis This function commands the Universe DMA engine to transfer a single DMA block lt vmeAdrs gt is the VME bus address of the DMA block lt pciAdrs gt is the PCI bus address of the DMA block lt byteCount gt is the number of bytes in the DMA block lt vmeAmCode gt is the VME Address Modifier code to be used when transferring the DMA block If lt pci64 gt is TRUE then PCI dual address cycles are enabled lt direction gt is either UNL DMA_V2L 0 meaning VME to PCI or Description UNI DMA L2V 1 meaning PCI to VME OK or ERROR Returns The vmeAdrs and pciAdrs parameters are not required to have any particular byte alignment in memory For example a PCI or VME address of 0x00200001 can be used However the vmeAdrs and pciAdrs must be aligned to an 8 byte boundary with each other For example if a PCI address of 0x00200001 is used some valid VME addresses are 0x10001001 0x10001009 0x10001011 etc If vmeAdrs and pciAdrs are not aligned to an 8 byte boundary with each other no DMA transfer is performed even though uniDmaDirect returns with no error The DMA transfer will only succeed if the VME target device accepts the specified AM code Ifno VME target accept
52. ages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that VMETRO was negligent regarding the design or manufacture of the part Worldwide HQ VMETRO asa stensj veien 32 0667 OSLO Norway Phone 47 22 10 60 90 Fax 47 22 10 62 02 info vmetro no United Kingdom VMETRO Ltd Manor Courtyard Hughenden Avenue High Wycombe HP13 SRE United Kingdom Phone 44 0 1494 476000 Fax 44 0 1494 464472 sales vmetro co uk North American HQ VMETRO Inc 1880 Dairy Ashford Suite 400 Houston TX 77077 U S A Phone 281 584 0728 Fax 281 584 9034 info vmetro com VMETRO Inc Suite 275 171 E State St Box 120 Ithaca New York 14850 Phone 607 272 5494 Fax 607 272 5498 info vmetro com Asia Pacific VMETRO Pte Ltd 175A Bencoolen Street 06 09 Burlington Square Singapore 189650 Phone 65 6238 6010 Fax 65 6238 6020 info vmetro com sg Contact Us www vmetro com Nordic amp Baltic Countries VSYSTEMS AB Drottninggatan 104 SE 111 60 Stockholm Contact Bengt Olof Larsson Phone 46 8 444 15 50 Fax 46 8 444 15 60 info vsystems se Germany VSYSTEMS Electronic GmbH Elisabethstrasse 30 80796 Miinchen Contact Ralf Streicher Phone 49 89 273 763 0 Fax 49 89 273 763 10 info vsystems de France VSYSTEMS SAS P A du Pas du Lac 5 rue Micha l Faraday 7
53. al Address Space to PCI I O Space M5000 Series BSP User Guide Issued June 20 2007 VMETRO ation deployed System Memory Issued June 20 2007 M5000 Series BSP User Guide System Memory VMETRO E innovation deployed 2 1 System Memory The MIDAS M5xxx implementation includes 256 MBof 166 MHz Double Data Rate DDR SDRAM Memory is mapped by MMU Translation Lookaside Buffer TLB entries which permits the SDRAM memory to be accessed as either cacheable or non cacheable The malloc or calloc functions can be used to allocate cacheable memory while cacheDmaMal11oc can be used to allocate non cacheable memory By default the M5xxx BSP implementation makes only 32 MiB available to the operating system This is because the PowerPC compiler uses the single instruction branch direct calls to subroutines by default Single branch instruction allow only 25 effective address displacement bits plus a signed bit resulting in possible jumps to subroutines within 32 MiB offset from the current branch instruction 1 e at the current program counter Object code compiled with single branch instructions cannot call subroutines if they are loaded more than 32 MiB from the VxWorks libraries object modules are loaded into the heap which starts at sysMemTop and grows toward address 0 If the compiler is instructed to use dual instruction indirect calls the same as used when calling function pointers the resulti
54. alAdrs int adrsSpace char busAdrs char localAdrs int busId adrsSpace specifies which PCI address space Must be one of the following defined constants PCI MEMORY SPACE 1 or PCI IO SPACE 2 busAdrs PCI bus address to convert localAdrs where the converted address is returned busId This parameter is not used Descrip The PPC440GX accesses the PCI buses via address translation mappings set up by the BSP Say you have a PCI tion device that maps its registers to certain PCI addresses In order for the PPCA40GX to read write those registers the PCI address must be converted to a local address This function converts a PCI bus address to its equivalent local address Returns OK or ERROR if the translation is not valid in which case localAdrs will be NULL Example struct my device regs devRegs int value The device registers start at memory address 0xC0000000 on the Primary bus if pciToLocalAdrs PCI MEMORY SPACE char 0xC0000000 char amp devRegs 0 ERROR return ERROR Read a 32 bit value from the device s status register g value devRegs status 146 M5000 Series BSP User Guide Issued June 20 2007 vmernoll innovation deployed pciLocalToPciAdrs replaced with sysLocalToBusAdrs Synopsis Descrip tion Returns Example int pciLocalToPciAdrs int adrsSpace char localAdrs char busAdrs int busId adrsSpace spec
55. ameters of the uniDmaChainCmdPktCreate function when the created command packet is used in a chained DMA transfer 80 M5000 Series BSP User Guide Issued June 20 2007 vmernoll innovation deployed Universe DMA Functionality uniDmaChain STATUS uniDmaChain UNI DMA CHAIN CMDPKT NODE cpp Synopsis This function commands the Universe DMA engine to run a chained DMA block transfer lt cpp gt points to the first command packet node in the chain of DMA command Description packets to be executed OK or ERROR Returns none Notes uniDmaChainStop STATUS unidDmaChainStop UNI UCSR ucsr Synopsis This function commands the Universe DMA engine to stop after the current DMA command packet node transfer is complete If the DMA engine is not active an error is returned This function does not return until after the current command packet node Description DMA transfer is complete OK or ERROR Returns none Notes Issued June 20 2007 M5000 Series BSP User Guide 81 VME Bus Operation VMETRO 5 innovation deployed uniDmaNotifyFncSet STATUS uniDmaNotifyFncSet FUNCPTR fnc int arg Synopsis This function may be used to specify a function to be called when a DMA event occurs A DMA event may be one of UNI DMA EVENT DONE DMA completion event UNI DMA EVENT LERR DMA engine caused PCI bus error UNI DMA EVENT VERR DMA engine caused VME bus error
56. an pass a message and interrupt the PPC440GX by writing to the appropriate VME A32 address where the Inbound Message Register 0 is mapped see the file mdrv include mu h for the address byte offset of all the IMU s registers The IMU has three messaging mechanisms e 4 Message Registers two inbound and two outbound writing a 32 bit value to one of the two Inbound Message Registers interrupts the PPC440GX e 2 Doorbell Registers e 2 Circular Queues Note The M5xxx BSP only supports the Message Register mechanism Doorbell Registers and Circular Queues are not currently supported by the BSP 30 M5000 Series BSP User Guide Issued June 20 2007 VMETRO 5 Message Register Support innovation deployed 4 2 Message Register Support This section documents the following functions muMessageConnect muIsMessageConnected muMessageDisconnect and muMessageEnable These functions let the user connect ISRs to the IMU in particular the Inbound Message Registers An additional function supported by the BSP related to the message unit is sysMailboxConnect which internally calls muMessageConnect muMessageConnect Synopsis Description Returns Example int muMessageConnect int regNum int isr int int isrArg regNum Inbound Message Register number 0 or 1 int isr int routine called at each message interrupt isrArg one argument to be passed to the ISR This function connec
57. as mmon ini and pci ini Detailed description of all symptoms observed including serial port output and PCI or VME analyzer trace files if applicable Online Support http www vmetro com support North and South America Telephone Support 281 584 0728 Fax 281 584 9034 United Kingdom Telephone Support 44 0 1494 476000 Fax 44 0 1494 464472 Singapore Telephone Support 65 6238 6010 Fax 65 6238 6020 Europe and the rest of the world Telephone Support 47 23 17 28 00 Fax 47 23 17 28 01 Issued June 20 2007 M5000 Series BSP User Guide 151 vmernoU innovation deployed References The Fibre Channel Industry Association FCIA http www fibrechannel org American National Standards Institute http www ansi org 152 M5000 Series BSP User Guide Issued June 20 2007
58. ask that initiated the memory transaction 12 M5000 Series BSP User Guide Issued June 20 2007 vmernoll innovation deployed PCI Bus Operation This chapter covers the PCI bus operation associated with the M5xxx BSP You should already be familiar with basic PCI bus operating principles First the PCI bus layout of the M5xxx is discussed Then methods for accessing the PCI bus are presented All of the BSP functions that provide access to the PCI bus are documented in this chapter Issued June 20 2007 M5000 Series BSP User Guide 13 PCI Bus Operation VMETRO E innovation deployed 3 1 PCI Bus Layout PCI IDSEL numbers and configuration addresses are given in the M5xxx User Guide 2 The device number to use in calls to PCI configuration functions see section on PCIbus Operations below is the IDSEL number minus 16 Therefore PMC 1 with IDSEL pAD 16 is device number 0 Device numbers for devices behind P2P bridges on PMCs are set by the PMC hardware according to the PCI Specification 3 The standard VxWorks PCI related query functions pciDeviceShow and pciHeaderShow are very useful for reviewing device numbers as well as a great deal of other information about each of the PCI devices in PCI configuration space The PCI auto configuration process takes care of assigning all PCI Memory and I O space resources The regions of PCI Memory Space are summarized as follows 0x10000000 OxBFFFFFFF 2 75 GB for PCI p
59. at will help you get the best performance IEC Prefixes for binary multiples Symbol Name Origin Derivation Size Ki Kibi Kilo binary kilo 1024 bytes Mi Mebi Mega binary mega 1 048 576 bytes Gi Gibi Gig binary giga 1 073 741 824 bytes Quality Assurance VMETRO is dedicated to supplying our customers with products and services of the highest quality We therefore continually review and assess our products and services with the aim to improve the processes involved in the development of our world class products If you have any comments or feedback with respect to our products and services please feel free to contact us through the support channels listed here or email us at comments vmetro no Technical Support Please see the section Technical Support at the end of this guide Related Documentation We recommend reading the documentation in the order shown Release Notes e M5000 User Guide Hardware References Used in this document 1 PPC440GX Embedded Processor User s Manual AMCC 2 M5xxx User Guide VMETRO Inc 3 The PCI Specification v2 2 PCI Special Interest Group 4 VxWorks 5 5 Drivers API Reference Manual Wind River Systems Inc 5 VMEbus Interface Components Manual Tundra 6 The VMEbus Specification VMEbus International Trade Association VITA Issued June 20 2007 M5000 Series BSP User Guide vii vmernoUl innovation deployed 7 VxWorks 5 5 Programmer s Guide Wind River Sy
60. ations because the additional serial output causes the M5xxx to take longer to boot up On M55xx boards the MEZZ500 daughter board allows for three additional PCI compatible PMC sites The MEZZ500 has an on board P2P that bridges between the Quaternary Bus and the three PMC sites on the MEZZ500 The PCI autoconfigurator configures the MEZZ500 P2P bridge and all devices installed on MEZZ500 PMC sites in the same way as all other P2P bridges and PCI PCI X devices in the system Thus the user need not take any special action to allocate or reserve PCI resources for the MEZZ500 or PMC devices mounted on the MEZZ500 14 M5000 Series BSP User Guide Issued June 20 2007 VMETRO i PCI Configuration Space Access innovation deployed 3 2 PCI Configuration Space Access Access to M5xxx PCI configuration space is provided through functions defined in target h drv pci pciConfigLib h which is part of the standard VxWorks Tornado installation See the aforementioned file for details The following definitions in config h can be used to access these resources M5000 PPC440GX VENDOR M5000_PPC440GX_ DEVICE M5000 PPC440GX I20 BAR M5000 PPC440GX SDRAM BAR Issued June 20 2007 M5000 Series BSP User Guide 15 PCI Bus Operation vmernoU innovation deployed 3 3 PCI Memory and I O Space Access PCI Memory and I O accesses are made through memory mapped references to the regions designated in the CPU Relative address map shown
61. ator reserves a secondary bus number to each PXB device but it does not scan for PCI devices behind the PXB device as it would normally do for other P2P bridges The BSP provides a special mechanism that allows the PCI auto configurator to reserve PCI memory and I O address space for PXB related applications This mechanism is available through a set of parameters in the RACEdrv section of the vxbsp ini file The PXB related parameters are shown in Table 6 1 84 M5000 Series BSP User Guide Issued June 20 2007 vmernoll innovation deployed RACEway PCI Interface TABLE 6 1 PXB related flags used by M5xxx BSP Parameter name Meaning Values PxbInit Initialize PXB TRUE FALSE PxbPrefMemSize Size of prefetch memory pool for PXB Power of 2 1 MiB 512MiB PxbMemloSize Size of non prefetch memory pool for PXB Power of 2 1 MiB 64 MiB PxbloSize Size of PCI I O pool for PXB Power of 2 16 bytes 256 KiB Default FALSE 256 MiB 0 disabled 0 disabled Note If a M5xxx R board hangs during VxWorks boot first check to see if the VME slot is a RACEway slot If the slot is a non RACEway slot reset the board enter the M5xxx monitor disable PXB initialization then reset the board and allow it to boot Vx Works PXB DMA Driver The PXB DMA driver is sold as part of a separate product called RACE driver for Vx Works RACE DRV VXWORKS and is documented in the PXB DMA Driver Software Reference Manual Iss
62. ault values edit the VME Master Slave Access Window Macros in sysVme h 50 M5000 Series BSP User Guide Issued June 20 2007 VMETRO VME Master amp Slave Access Configuration innovation deployed 32 bit virtual Address Outbound VMEbus Map by bsp A32 Address Map FFFF FFFF Flash Memory FFFF FFFF Not Used FE00 0000 PCI X bridge FD00 0000 Not Mapped unused FCOO 0000 32 bit PCI I O outbound F880 0000 Not mapped unused F801 0000 16 bit PCI I O outbound F800 0000 PLD F500 0000 Flash Memory F300 0000 SRAM F200 0000 120 F100 0000 Internal CPU Peripherals F000 0000 PCI Memory outbound window without prefetch VmeA32MasterPciBase C000 0000 N b PCI Memory outbound window with prefetch k A 1 0000 0000 0 1000 0000 local PPC440 SDRAM 0 0000 0000 0 0000 0000 Issued June 20 2007 M5000 Series BSP User Guide 51 innovation deployed vmernoUl VME Bus Operation TABLE 5 1 M5xxx Default Universe VME and PCI Slave Images Tur dsqxa ur o qesiqoA ISCe vourA PPV NO HTIHVSId HAVIS TEVAWA ourjop q 3uoo Uy e qeue oj rurdsqxa 0 osegcIoise ACE V9ULA PPV pnegop q payqesiq Q 0 O1OBUT AZIS JoS Q 0 01oeUI AZIS JoS Q 01 OLOBUI OZIS 19S 9 QUSIp 0 MOH 00001X0 SI 9ZIS 9spd AUN 8TI SE 9ZIS O NdOH AZIS OOT OL TEVANA ANA a 79 AZIS WHISVIN OFS TEV ANA E EN
63. boot parameters for the emac interface may be done using the c command in the VxWorks bootrom or through the bootChange command of a running VxWorks system An example of boot parameters for the emac interface is shown in Figure 7 1 boot device emac0 processor number i 0 host name file name usr wind target config bspname vxWorks inet on ethernet e 192 168 100 10 inet on backplane b host inet h 192 168 100 1 gateway inet g user u fred ftp password pw blank use rsh flags f 0 FIGURE 7 1 Example Boot paramneters for the emac interface Configuring JUMBO packets The Ethernet Network Interface driver supports JUMBO packets for both the fast Ethernet and Gigabit Ethernet channels JUMBO packets is a feature of gigabit Ethernet controllers which basically increases the Ethernet frame size also referred to as MTU Maximal Transmission Unit from 1500 bytes typically to several kilobytes The maximum Ethernet frame size depends on the Ethernet controller Ethernet communication with JUMBO packet MTU sizes gives better performance than smaller packets because the number of interrupts and CPU overhead is reduced per byte transmitted This is of benefit where it is necessary to maximize Gigabit Ethernet throughput potential as much as possible 88 M5000 Series BSP User Guide Issued June 20 2007 VMETRO i Ethernet emac Network Interface innovation deployed The use of
64. brackets around it i e RACEdrv while the section parameter to this function should not have brackets i e RACEdrv Returns OK or ERROR Example Get the value of the VmeAl6SlaveBase flag int val mfs ini getlong vxbsp ini VMEInterface Vmel6SlaveBase amp val 134 M5000 Series BSP User Guide Issued June 20 2007 vmernoll innovation deployed The Midas File System MFS mfs usr load file Synopsis STATUS mfs usr load file char networkFilename char mfsFilename Description This function loads the specified file networkFilename from the network and saves it in MFS with the specified filename mfsFilename Returns Returns OK or ERROR Example status mfs usr load file home WindRiver c5000 bsp1 2 r1 1 pci ini pci ini Issued June 20 2007 M5000 Series BSP User Guide 135 MIDAS File System vmernoU innovation deployed 11 2 The vxbsp ini File The RACEdrv Section Flag name Meaning PxblInit Initialize PXB PxbPrefMemSize Size of prefetch memory pool for PXB PxbMemloSize Size of non prefetch memory pool for PXB PxbloSize Size of PCI I O pool for PXB The Vmelnterface Section Flag name Meaning VmeA32Master2Base VME A32 base address of secondary PCI slave base image no such space if not present VmeAl6SlaveBase 32 bit VME base address of A16 VME slave image used for booting other boards over VME VmeA32SlaveBase VME A32 base addres
65. cept for the Fibre Channel controllers and RACEway These devices are supported through separate products available from VMETRO In PCI systems interrupts may be shared by multiple PCI devices In order to support interrupt sharing each ISR must determine whether its associated device caused an interrupt and if so it must clear the condition that caused the interrupt The device driver application programmer should use the pciIntConnect function to install an ISR for a particular PCI device on the M5xxx board or mounted in a PMC slot Using the VxWorks library function intConnect is not guaranteed to work because intConnect does not support interrupt chaining whereas pcilntConnect does To disassociate an ISR from an interrupt use the pcilntDisconnect 2 function The pciIntConnect and pciIntDisconnect2 functions are documented in 4 The application code needs to include the header files listed below e intLib h VxWorks interrupt related function declarations e drv pci pcilntLib h declarations for pciIntConnect pciIntDisconnect mdrv include MidasPciLib h Midas PCI related functions e mdrv include midasppc440 h PPC440GX primarily interrupt related declarations Interrupt Pin Each PCI device may implement up to four interrupt pins INTA INTB INTC and INTD on a physical package of a multi function PCI device If a package implements one pin it must be INTA If a package is single function it must use I
66. chip operates like a PCI device The M5xxx BSP only supports the PXB operating in bridge mode When an M5xxx R board boots VxWorks the BSP will attempt to initialize the PXB and this includes placing the PXB in bridge mode However if the MSxxx R is not installed in a RACEway VME slot i e the slot s P2 is not overlaid with an ILK device the PXB initialization process will cause the board to hang The M5xxx monitor allows the user to switch the PXB initialization on or off thus enabling an M5xxx R board to be used in either a RACEway or non RACEway VME slot e To enable PXB initialization enter the following command at the VxWorks target shell prompt gt mfs ini settext vxbsp ini RACEdrv PxbInit TRUE e To disable PXB initialization enter the following command at the Vx Works target shell prompt gt mfs ini settext vxbsp ini RACEdrv PxbInit FALSE Or omit this item altogether However the ability to inhibit PXB initialization is potentially quite dangerous especially in boards deployed in production system because if the PXB chip is not initialized RACEway PCI data transfer will work with undefined result or not at all In other words RACEway PCI communication requires PXB initialization To insure that the BSP always initializes the PXB see the function sys pxb init in sysLib c and follow the instructions there When using PCI auto configuration and PXB initialization is enabled the auto configur
67. d one PCI bus PCI 33 645 FIGURE 1 1 PCI busses mm PCLX 133 64 3 3V The PCI X bus segment attached directly to the PPC440GX is referred to as the Primary Bus The Primary Bus attaches to the Qlogic ISP2312 and the first on board PLX P2P bridge hereafter called a P2P The secondary side of the first P2P is referred to as the Secondary Bus which attaches PMC site 1 and the second on board P2P The secondary side of the second on board P2P is referred to as the Tertiary Bus which attaches PMC site 2 and the third onboard P2P The secondary side of the third onboard P2P is referred to as the Quaternary Bus which attaches the Universe PCI VME bridge and the PXB bridge if present For M55xx series products an optional mezzanine daughter card provides three additional PCI compatible PMC sites The mezzanine daughter card has a P2P which is attached to the Quaternary Bus The three additional PMC slots on the mezzanine are attached to the mezzanine s P2P 2 M5000 Series BSP User Guide Issued June 20 2007 vmernoll innovation deployed Overview In general P2P bridges may be enabled or disabled Note that all three onboard P2Ps must be enabled in order for the PPC440GX to have visibility of the Universe and other components on the Quaternary Bus Typically users will not need to worry about enabling or disabling the onboard P2Ps because the BSP properly configures the bridges through a process
68. dress space The value can be either UNI PCI MEMORY SPACE 0 UNI PCI IO SPACE 1 or UNI PCI CFG SPACE 2 vmeAmCode the VME AM code specifying a block type AM code also implies that the similar AM code corresponding to single cycles will also be supported by the window postedWrites specifies whether the window will support posted write operations With posted write write operations may return before the data has been written to its final destination on the PCI bus prefetchReads specifies whether the window will support prefetch read operations With prefetch read read operations may actually read more than the amount of data requested so that surrounding data may more quickly be returned on the next operation pci64 specifies whether the window will support 64 bit operation If this is enabled the window supports a data width of up to 64 bits postedWrites whether the window allows posted cached writes The value should be either TRUE 1 or FALSE 0 pciLockOnRMWs tells whether the window will use PCI Lock signal on Read Modiy Write cycles from VME to PCI bus 64 M5000 Series BSP User Guide Issued June 20 2007 VMETRO i VME Master amp Slave Access Configuration innovation deployed uniVmeSlavelmageSet Continued Description This function is used to configure a Universe VME slave image This allows the M5xxx to act as a VME slave and support reading writing to the local PCI bus from other VMEb
69. e 4 The fourth method involves simply addressing the extra memory directly independent of VxWorks In this case the user is responsible for managing the extra memory since the VxWorks memory management functions such as malloc calloc free etc will not work for this method 10 M5000 Series BSP User Guide Issued June 20 2007 VMETRO Cache safe Buffers innovation deployed 2 2 Cache safe Buffers Any time there is asynchronous access to DRAM there is a potential cache coherency problem 1 e data in the cache is different from data in DRAM The PPC440GX data cache may be write through cache i e data is always written to both cache and memory when the CPU performs a write or copyback i e data is flushed to main memory only when a pending read must reuse the previously written cache line By default the data cache is copyback If write through caching is used there is no cache coherency problem whenever data is transferred from local memory to remote memory Copyback caching the default case improves processor throughput but the local memory does not immediately reflect the value written Read access by an external agent e g a DMA controller may pick up the old or uninitialized value if the dirty cache line has not yet been flushed when the external read access commences Regardless of the cache mode used when data is written by another master typically a DMA controller to local memory the local
70. e sourceBuffer destinationBuffer descs cacheDmaFree sMallocPtr cacheDmaFree dMallocPtr return status Issued June 20 2007 M5000 Series BSP User Guide 121 DMA drivers VMETRO E innovation deployed 122 M5000 Series BSP User Guide Issued June 20 2007 vmernoll innovation deploued MIDAS File System Issued June 20 2007 M5000 Series BSP User Guide 123 MIDAS File System VMETRO E innovation deployed 11 1 The Midas File System MFS Overview The M5xxx contains a serial EEPROM that is accessible as a file system referred to as the Midas File System MFS The MFS can be accessed from the BSP or from the Midas Monitor Please see the M5xxx BSP Monitor User s Guide 10 for information on how to access MFS files from the Midas Monitor The functions used for interfacing with MFS from the BSP are documented in this section along with the default files that are placed in MFS and their contents The MFS Functions This section documents the MFS access functions available in the BSP The include files mfs h and mfs_ini h should be included when using these functions mfs_open Synopsis int mfs_open char filename int flags filename the name of the file to open in MFS flags 0 or MFS_CREATE 1 Description This function opens a file in MFS or creates it if it does not exist and the MFS_CREATE option is set Returns File number of opened file
71. e configuration of each M5xxx is encoded in the model number for the board This section reviews the available M5xxx options and how the model number can be used to identify which options are present The general format for model numbers is MS5ABCRP XYZ rr where M is for Midas 5 represents this generation of Midas product A is for the number of PMC positions typically 2 or 5 for mezzanine B is for the number of PPCs 0 pure carrier l intelligent C is reserved for future options R is used when RACE PXB is available P denotes that there is a mounted PO connector XYZ gives front panel options present on the board from top to bottom XYZ can consist of Fisfor Fibre channel SFF connector optical e Eis for Fast Ethernet 10 100 RJ45 connector copper e Gis for Gigabit Ethernet 10 100 1000 SFF optical e Jis for Gigabit Ethernet 10 100 1000 RJ45 copper is for serial interface options which can be lt no number gt is for RS232 2 ports e 4 is for RS232 1 port and RS422 1 port rr is for the ruggedized version of the product Additional restrictions apply to the usage of the three front panel In particular X can be E emac0 G emac2 or J emac2 X cannot be F Y can be E emacl or F Z can be F G emac3 or J emac3 Z can only be F if Y is also F The names in parentheses above refer to the name of each port within VxWorks These names are
72. e interrupt service routine ISR for a given interrupt source When generating the VME interrupt the interrupt source communicates a vector that will be used by the main interrupt service routine of the Universe driver implemented internally in the M5xxx BSP in order to lookup the ISR registered for the interrupt source The ISR must be registered with the VxWorks function called intConnect which is declared in S WIND_BASE target h intLib h as follows STATUS intConnect VOIDFUNCPTR vector VOIDFUNCPTR routine int parameter lt vector gt is the vector communicated by the interrupt source routine is a function pointer to the interrupt service routine for the interrupt source device lt parameter gt is a user defined value that will be sent as the one and only parameter to the ISR when called VME Interrupt Generation All boards may generate interrupts on all lines in contrast to that there may only be one interrupt controller destination for a given interrupt line I e there may be several interrupt sources and only one interrupt destination for a given VME interrupt line In order to generate a VME interrupt the uniVmeIntGenerate function is called as follows STATUS uniVmeIntGenerate int level int vector interrupt vector to return 0 255 Note The Universe II only supports even vector numbers The least significant bit is always 0 76 M5000 Series
73. ed by this warranty and will if possible be repaired for time and material charges in effect at the time of repair Any customer modification to VMETRO products including conformal coating voids the warranty unless agreed to in writing by VMETRO If boards that have been modified are returned for repair this modification should be removed prior to the board being shipped back to VMETRO for the best possibility of repair Boards received without the modification removed will be reviewed for reparability If it is determined that the board is not repairable the board will be returned to the customer All review and repair time will be billed to the customer at the current time and materials rates for repair actions This product has been designed to operate with modules carriers or compatible user provided equipment Connection of incompatible hardware is likely to cause serious damage VMETRO assumes no liability for any damages caused by such incompatibility For products that have failed or malfunctioned due to abuse miss use or accident or for products that have failed or malfunctioned after the expiry of the warranty the costs of repair or replacement will not be covered by VMETRO VMETRO specifically disclaims any implied warranty of merchantability and fitness for a particular purpose The warranty provided herein for electronic equipment products is the user s sole and exclusive remedy In no event shall VMETRO or its distributors and agents
74. emory Any VME bus access that addresses the VME slave window generates an access into the PPC440 local bus Each window is defined by a set of three macros the local base VME bus base and window size Please see Table 4 for the default VME windows and sizes defined by the BSP The following macros define a window from VME A16 address space into M5xxx memory Note The M5xxx board uses A16 slave window to support BusNet These macros are not defined by default if define INCLUDE BUSNET is not in config h 1 VME AI6 SLV SIZE window size in A16 space BSP default value is 4KB 2 VME A16 SLV BUS VME A106 bus base BSP default value is 0x0 3 VME A16 SLV LOCAL Not applicable The following macros define a window from VME A32 address space into M5xxx memory 1 VME A32 SLV SIZE size of window in A32 space Window size depends on whether the entire DRAM is dual ported By default only the sm master processor number 0 dual ports its DRAM For an M5xxx board which is not sm master only 64KB is made visible not the entire DRAM in order to limit VME A32 bus space consumed The user can easily dual port the entire DRAM by enabling the define MIDAS MAP DRAM TO VME statement in sysVme h 60 M5000 Series BSP User Guide Issued June 20 2007 vmernoll innovation deployed VME Master amp Slave Access Configuration 2 VME A32 SLV BUS VME A32 base of window Each M5xxx board is mapped to a unique VME A32
75. ertiary PCI bus corresponds to PCI bus number x Mn PciBusNo if MidasBusIdToPciBusNo MIDAS QUATERNARY BUS amp PciBusNo ERROR printf Midas quaternary PCI bus corresponds to PCI bus number x n PciBusNo if MidasBusIdToPciBusNo MIDAS MEZZ500 BUS amp PciBusNo ERROR printf Midas MEZZ500 PCI bus corresponds to PCI bus number x n PciBusNo 24 M5000 Series BSP User Guide Issued June 20 2007 VMETRO 5 PCI Bus Operations innovation deployed MidasGetPmcBridgeBusNumbers Synopsis int MidasGetPmcBridgeBusNumbers UINT8 PmcSlotNo UINT8 primary UINT8 secondary UINT8 subordinate PmcSlotNo The PMC slot number Must be one of 1 2 3 4 or 5 primary pointer to the returned value of the primary PCI bus number associated with a P2P bridge mounted in a PMC slot secondary pointer to the returned value of the secondary PCI bus number associated with a P2P bridge mounted in a PMC slot subordinate pointer to the returned value of the subordinate PCI bus number associated with a P2P bridge mounted in a PMC slot Description This function can be used to determine whether a given PMC has a P2P bridge mounted on it and if so which PCI bus number s has been allocated for it If a P2P bridge is present on a PMC slot the function returns OK The primary secondary and subordinate PCI bus numbers associated with the P2P bridge are returned through parameters If no P2P br
76. g the status status text Symbolic string describing the status Usually this structure is used to describe an error condition See the relevant function call for use Address translation functions The PPC440GX DMA driver expects processor local bus PLB addresses as input The driver provides functions to translate both local addresses and PCI addresses to PLB addresses These are int ppc440LocalAdrsToPlbAdrs uint32 t localAdrs uint32 t plbAdrsLo uint32 t plbAdrsHi int ppc440PciAdrsToPlbAdrs int adrsSpace uint32 t pciAdrsLo uint32 t pciAdrsHi uint32 t plbAdrsLo uint32 t plbAdrsHi Each function will return OK or ERROR depending on if the translation succeeded or not The ppc440PciAdrsToPlbAdrs function currently supports PCI MEMORY address space and 32 bits addresses 114 M5000 Series BSP User Guide Issued June 20 2007 VMETRO PPC440GX DMA Driver innovation deployed Single blocking DMA transfer example The following source code is an example of a single blocking DMA transfer The code starts in the doSingle function include vxWorks h include ppc440DmaLib h extern int logMsg char fmt ppc440DmaXferBlocking is a simple interface to the ppc440DmaLib BSP module THE ALIGNMENT WILL B Is oO ETERMINED BY THE DMA DRIVER MAX TRANSFER SIZE T DEPENDENT ON THE ALIGNMENT
77. gabit Ethernet peers support Ethernet packets larger than the MTU Maximum Transmission Unit being used and that this feature jumbo packets is enabled for all switches in the network Note Many Gigabit Ethernet switches that support jumbo packets are shipped with this feature disabled by default If you are not using a Gigabit Ethernet switch that supports jumbo packets a work around for this problem is to configure EMAC2_MTU and EMAC3 MTU to 1500 in config h This turns off jumbo packet usage in software New bootrom vxWorks or vxWorks st rom images must be compiled and used with these new configurations For Fast Ethernet Switches 100 Mbps Fast Ethernet switches will work with the M5000 regardless of whether jumbo packets are configured or not Command line compilation of the BSP fails In order to compile the BSP from a shell there are two steps that must be completed 1 Installation of Tornado 2 2 1 with patch 90451 2 Set up the compilation environment using the torVars script Wind River has installation files for installing Tornado 2 2 1 for PowerPC directly It is also acceptable to install Tornado 2 2 for PowerPC followed by installing the Tornado 2 2 Cumulative Patch 1 Patch 90451 must be installed on top of Tornado 2 2 1 or Tornado 2 2 with Tornado 2 2 Cumulative Patch applied Before compiling the BSP it is also necessary to run the torVars script Run torVars bat torVars sh or torVars
78. h0 2 Set the IP address of the M5000 board gt setenv ipaddr 192 168 168 175 3 Set the hostname of the M5000 board gt setenv hostname c5000 4 Set the IP address of the NFS or TFTP server gt setenv serverip 192 168 168 4 TFTP 1 Put the vx Works image in the tfipboot directory on the TFTP server 2 Download the VxWorks image bootrom bin or vx Works st rom bin into SDRAM at address 01000000 gt tftpboot 1000000 bootrom bin NFS 1 Put the vx Works image in the exported directory on the NFS server for instance export images bootrom bin 2 Download the VxWorks image bootrom bin or vx Works st rom bin into SDRAM at address 01000000 nfs 1000000 export images bootrom bin 106 M5000 Series BSP User Guide Issued June 20 2007 VMETRO i Burning VxWorks Boot Code from U Boot Ethernet innovation deployed Flash VxWorks image The following command sequence is required in order to flash the vx Works image for both TFTP and NFS download methods 1 1 Unlock the flash blocks where the VxWorks image should be written gt protect off 4000000 f41fffff 2 2 Erase the flash blocks where the VxWorks image should be written gt erase f4000000 f41fffff 3 3 Copy the VxWorks image from SDRAM to flash the filesize parameter is updated automatically by U boot when the file is downloaded gt cp b 1000000 4000000 filesize Issued June 20 2007 M5000 Series BSP User Guide
79. har Name 16 UINT8 PciDeviceNo UINT8 MidasBusId UINT8 PcilntLine PCI INT LIN Fl uv Description This function can be used to get information such as the PCI device number see PCI spec the MIDAS bus ID the name of the device or the PCI interrupt line s associated with the PCI device This information can then be used to read write the configuration registers of the device Returns OK Or ERROR Example struct MIDAS PCI SLOT INFO slot info if MidasPciSlotInfoGet MPSLOT UNIVERSE amp slot info ERROR return ERROR printf Universe PCI device info Mn printf The device name is s Mn slot info Name printf The device number is d Mn slot info PciDeviceNo Issued June 20 2007 M5000 Series BSP User Guide 27 PCI Bus Operation vmernoll innovation deployed 3 6 PCI Optimizations During PCI autoconfiguration the M5000 BSP sets the Latency Timer register of all PCI devices including any PMCs that may have mounted to the maximum allowed value FF which corresponds to 255 PCI cycles The Latency Timer register specifies in units of PCI bus clocks the minimum guaranteed number of clocks allocated to the PCI master after which it must surrender tenure as soon as possible after its GNT is deasserted The reason for maximizing the latency timers in the M5000 BSP is because many MIDAS applications require a maximum throughput performance If your app
80. idge is found in the given PMC slot the function returns ERROR The meaning of these PCI bus numbers are fully described in the PCI specification 3 Basically the primary PCI bus number is the bus number for the side of the bridge closest to the 440 The secondary PCI bus number is the bus number for the side of the bridge furthest from the 440 The subordinate PCI bus number is the highest numbered bus that exists behind the bridge Returns OK Or ERROR Example UINT8 primary secondary subordinate INT8 i for i 1 i lt 5 i if MidasGetPmcBridgeBusNumbers i amp primary amp secondary amp subordinate OK printf PMC with P2P bridge found in PMC d primary d secondary d subordinate d n i primary secondary subordinate Issued June 20 2007 M5000 Series BSP User Guide 25 PCI Bus Operation VMETRO 5 innovation deployed MidasPmcSlotInfoGet Synopsis int MidasPmcSlotInfoGet int iPmcSlotNo MIDAS PCI SLOT INFO pMidasPciSlot iPmcSlotNo The PMC slot number Must be one of 1 2 3 4 or 5 MidasPciSlot pointer to structure defined as follows struct MIDAS PCI SLOT INFO char Name 16 UINT8 PciDeviceNo UINT8 MidasBusId UINT8 PciIntLine PCI INT LINES Description This function can be used to get information such as the PCI device number the MIDAS bus ID of a particular PMC slot the name of the device or the PCI interrupt line s associated with the slot
81. if OK else ERROR Example int fd if fd mfs open filename 0 ERROR return ERROR 124 M5000 Series BSP User Guide Issued June 20 2007 VMETRO 5 The Midas File System MFS innovation deployed mfs close Synopsis STATUS mfs close int fd d the file number that was previously returned from mfs open Description This function close a file in MFS that was previously opened with mfs open Returns OK or ERROR Example Close a previously opened file in MFS mfs close fd mfs remove Synopsis STATUS mfs remove char filename filename the name of the MFS file to remove Description This function removes a file in MFS Returns ERROR if file doesn t exist else OK Example Remove the file in MFS named test txt mfs remove test txt Issued June 20 2007 M5000 Series BSP User Guide 125 MIDAS File System VMETRO E innovation deployed mfs_dir Synopsis STATUS mfs dir Description This function lists the files in the MFS Returns Nothing Example List the files in MFS mfs dir mfs_seek eee Synopsis STATUS mfs_seek int fd int offset int refpos fd the file number that was previously returned from mfs_open offset the position in the file to read write next in bytes re fpos The position from which to seek The value can be either MFS START 0 MFS END 1 oran offset in bytes Description This f
82. ifies which PCI address space Must be one of the following defined constants PCI MEMORY SPACE 1 or PCI IO SPACE 2 localAdrs local address to convert busAdrs where the converted address is returned busId This parameter is not used Say the application code allocates a buffer in the PPC440 DRAM In order for other PCI masters to access this buffer the buffer s PCI address must be obtained from its corresponding local address OK Or ERROR char localAdrs busAdrs Allocate a 1KB buffer in MPC8240 DRAM localAdrs malloc 1024 if localAdrs NULL return ERROR Find PCI address of buffer if pciLocalToPciAdrs PCI MEMORY SPACE localAdrs amp busAdrs 0 ERROR return ERROR printf buffer local addr 0x x buffer PCI bus address 0x x n localAdrs busAdrs Issued June 20 2007 M5000 Series BSP User Guide 147 Deprecated Functions VMETRO E innovation deployed 148 M5000 Series BSP User Guide Issued June 20 2007 vmernoll innovation deploued Built In Self Test BIST API Issued June 20 2007 M5000 Series BSP User Guide 149 Built In Self Test BIST API VMETRO E innovation deployed C 1 Built In Self Test API Contents The Built In Self Test API BIST APT is a set of functions that tests the M5000 hardware and not any external IO The tests are grouped as follows Processor device tests Tests SDRAM Flash SPROM PLD and te
83. image The original code Set Universe window to VME A32 space uniPciSlavelmageSet MIDAS UNI A32 WIN NUM VmeA32MasterPciBase IDAS LOC TO VME A32 VME BASE VME A32 MASTER SIZE UNI PCI MEMORY SPACE 0x0d UNI VMEBUS DATAWIDTH 32 TRUE may be modified to Set Universe window to VME A32 space uniPciSlavelmageSet MIDAS UNI A32 WIN NUM VmeA32MasterPciBase 0x60000000 0x01000000 UNI PCI MEMORY SPACE 0x09 UNI VMEBUS DATAWIDTH 32 TRUE If the single region is larger than VME A32 MASTER SIZE then the value of VME A32 MASTER SIZE would need to be changed Option 2 Another approach to configuring the PCI slave image in this example is to modify the existing VME slave images in the application prior to usage instead of modifying the BSP Because the default value of VME A32 MASTER SIZE is 256 MiB this approach will only work if the region size needed is less than or equal to 256 MiB In the case for the example above simply call the following from the application prior to using the PCI slave image 70 M5000 Series BSP User Guide Issued June 20 2007 VMETRO w Configuring PCI Slave Images in the Universe innovation deployed Set Universe window to VME A32 space uniPciSlavelmageSet MIDAS UNI A32 WIN NUM VmeA32MasterPciBase 0x60000000 0x01000000 UNI PCI MEMORY SPACE 0
84. in the section on address maps Because PClIbus is inherently little endian least significant byte resides at the lowest address and the PPC440GX is inherently big endian most significant byte at lowest address care must be exercised when accessing device registers or other non memory devices so that data values are read and written properly An object and any pointer to it must agree in size or the data read or written will be wrong or be in the wrong place Data read from a multi byte entity must be byte swapped before being used or returned Data must be byte swapped before being written to a multi byte entity The M5xxx BSP provides functions for accessing PCI resident resources which take care of byte swapping and guaranteeing in order access to system resources They are IMPORT VOID sysOutWord ULONG address UINT16 data sysALib s IMPORT VOID sysOutLong ULONG address ULONG data sysALib s IMPORT VOID sysOutByte ULONG UCHAR sysALib s IMPORT USHORT sysInWord ULONG address sysALib s IMPORT ULONG sysInLong ULONG address sysALib s IMPORT UCHAR sysInByte ULONG sysALib s PCI to CPU and CPU to PCI address translations are provided by the functions sysBusToLocalAdrs and sysLocalToBusAdrs respectively 16 M5000 Series BSP User Guide Issued June 20 2007 VMETRO PCI Memory and I O Space Access innovation deployed sysBusToLocalAdrs Synopsis STATU
85. ion deployed midas ppc440 h MIDAS PPC440GX board M5xxx header file pciAutoConfigLib c modified version of the VxWorks PCI autoconfigurator that supports the M5xxx phyLib c h MIT physical network configuration code and header ppc440gx h IBM PPC440GX specific header file ppc440Timer c PPC440GX timer function library romlnit s Assembly source code supporting power up reset sdramDcr h IBM SDRAM controller DCR access assembly routines sdrDcr h IBM system DCR register definitions sysALib s this is the assembly source code supporting sysLib c sysBusPci c Support routines for PCI auto configuration sysCpcr c h IBM PPC440GX clocking amp power and system device access header sysDcr h s DCR access header and assembly routines sysLib c this is the primary BSP source file sysNet c Ethernet hardware initialization sysSerial c Serial hardware initialization sysVme c h Functions for VMEbus support uicDcr h IBM Universal Interrupt Controller UIC DCR access definitions and assembly routines uicIntr c PPC440GX IBM Universal Interrupt Controller UIC library usrExtra c VxWorks support for optionally included modules zmiiLib h ZMII macro header 102 M5000 Series BSP User Guide Issued June 20 2007 vmernoll innovation deployed Burning VxWorks Boot Code There are two methods of burning VxWorks boot code Ethernet This is the preferred method and should be used where Ether
86. issus ded chee e pO RR ERA 149 Built In Self Test API Contents 150 Issued June 20 2007 1 49 M5000 Series BSP User Guide xiii vmernoU innovation deployed XIV M5000 Series BSP User Guide Issued June 20 2007 1 49 VMETRO ation deploued Figures Issued June 20 2007 1 49 M5000 Series BSP User Guide XV vmernoU innovation deployed Xvi M5000 Series BSP User Guide Issued June 20 2007 1 49 vmernoll innovation deployed Tables TABLE 1 1 M5xxx switch settings affecting BSP 3 TABLE 1 2 M5xxx BSP 32 bit Effective Virtual Address Map with PCI Auto config default 5 TABLE 1 3 M5xxx Inbound PCIbus Memory Space Relative Address Map 6 TABLE 1 4 Effective virtual address space of PPC440GX to PCI I O Space 7 TABLE 5 1 M5xxx Default Universe VME and PCI Slave Images 51 TABLE 5 2 M5xxx Supported VME AM Codes 56 TABLE 6 1 PXB related flags used by M5xxx BSP 85 Issued June 20 2007 1 49 M5000 Series BSP User Guide xvii vmernoU innovation deployed xviii M5000 Series BSP User Guide Issued June 20 2007 1 49 vmernoll innovation deployed Overview This section briefly describes the features and architecture of the PPCA40GX and its incorporation in the VMETRO M
87. ite eod sg 84 PABDMA Drivel s bis uu Le e qoe PR EE NT EE erate bbe 85 non D 87 7 1 Ethernet emac Network Interface 88 Configuring JUMBO packets 88 7 2 Shared Memory sm Backplane Network Interface 90 Modifying the kernel configuration 90 Configuring The Development Host UNIX 91 Specifying IP Addresses And Host Names For VxWorks Nodes 91 Specifying the Internet Gateway for VxWorks Nodes 91 Configuring The SM Network 92 Configuring the SM Network Master 92 BSP Configuration for the SM Network 92 VxWorks Boot Parameters for the SM Network Master 92 Configuring M5000 as an SM Network Participant 93 Shared Memory Network Synchronization 94 Testing And Troubleshooting 95 7 3 Gigabit Ethernet Throughput Performance 96 Issued June 20 2007 1 49 M5000 Series BSP User Guide xi vmernoU innovation deployed BSP Installation 99 8 1 BSP Installation amp Distribution 100 Installations bes od ite a d ede E te na Mee ae toda ae desc 100 Files amp Directories 100 Burning VxWorks Boot Code 103 9 1 Burning VxWorks Boot Code from Rom Monitor Serial 104 9 2 Burning VxWorks Boot C
88. l val mfs read fd buf 80 if val ERROR printf Read d bytes Ss n val buf else printf Error reading dataNin 130 M5000 Series BSP User Guide Issued June 20 2007 VMETRO 5 The Midas File System MFS innovation deployed mfs write Synopsis STATUS mfs write int fd int buf int len d the file number that was previously returned from mfs open buf buffer to put the read data into len the amount of data to be written Description This function writes up to len bytes of data from buf into the file fd This function is similar to the write C library function Returns OK or ERROR Example Write some data to the given file in mfs char buf 80 abcdefg int val mfs write fd buf 7 mfs pwd Synopsis STATUS mfs pwd Description This function prints the current working directory in MFS Returns Nothing Example Print the current working directory in MFS mfs pwd Issued June 20 2007 M5000 Series BSP User Guide 131 MIDAS File System VMETRO E innovation deployed mfs_ini gettext Synopsis STATUS mfs ini gettext char filename char section char item char buf int buflen Description This function reads the value of the item item in section section from file filename and puts it into buf up to the length buflen Note the actual section name in the file has brackets around it i e
89. lication must minimize the latency of each PCI transaction please refer to section 3 5 4 Arbitration Latency in the PCI Local Bus Specification revision 2 2 2 3 or 3 0 Note Some PCI devices limit the maximum value of their Latency Timer to a value that is optimized for their maximum burst size This is allowed according to the PCI Local Bus Specification and should not be mistaken as an error in the M5000 BSP 28 M5000 Series BSP User Guide Issued June 20 2007 vmernoll innovation deploued 120 Messaging Unit Support Issued June 20 2007 M5000 Series BSP User Guide 29 120 Messaging Unit Support VMETRO E innovation deployed 4 1 Overview The M5xxx BSP uses the PPC440GX 120 Messaging Unit IMU to implement mailbox interrupts The IMU allows external host processors and the PPC440GX to communicate via message passing and interrupt notification see Chapter 21 of the PPC440GX User s Manual 1 for a highly detailed description of the IMU On theM5xxx the BSP makes the IMU visible on PCI VME and RACEway so that it is possible for another processor to communicate interrupt the PPC440GX via those buses The IMU registers are accessible in local memory space at 0OxF1FF0000 The IMU registers are located in PCI space at 0x00000000 By default this region is mapped to VME A32 AM code 0x0d at a location dependent on CPU number see section on VME bus for more information An external VME master c
90. lmageSet 3 VmeA32Master2PciBase 0x40000000 0x10000000 UNI PCI MEMORY SPACE 0x0d UNI VMI TRUE EBUS DATAWIDTH 32 The following two commands configure the additional PCI slave image windows uniPciSlavelmageSet 4 VmeA32Master2PciBase 0x10000000 0x60000000 0x10000000 UNI PCI MEMORY SPACE 0x0d UNI VMEBUS DATAWIDT TRUE B32 Issued June 20 2007 M5000 Series BSP User Guide 73 VME Bus Operation VMETRO 5 innovation deployed uniPciSlaveImageSet 5 VmeA32Master2PciBase 0x20000000 0x80000000 0x10000000 UNI PCI MEMORY SPACE 0x0d UNI VMEBUS DATAWIDTH 32 TRUE At this point all VME interface requirements are met This is confirmed with uni ImageShow gt unilmageShow Universe PCI slave images VME master windows Image Type Local PCI Base VME Base Size VMEAM PWEN VDW 0 EM e1000000 e1000000 00000000 00010000 2d Y 32 1 EM 050000000 500000000 00000000 01000000 3d Y 32 2 E 90000000 90000000 18000000 20000000 0d X 32 3 E b1000000 b1000000 40000000 10000000 Od Y 32 4 EM c1000000 c1000000 60000000 10000000 Od Y 32 5 EM d1000000 d1000000 80000000 10000000 Od Y 32 Universe VME slave images PCI master windows Image Type Local PCI VME Size VMEAM codes PWEN PREN LD64 LRMW 5 MEM 00000000 00000000 00000000 10000000 09 Oa Od Oe Y Y N N
91. lmageSetup int image UINT32 vmeBase UINT32 pciBase UINT32 size UINT32 pciAddrSpace BOOL amCodeAdrsSpace BOOL amCodeUser BOOL amCodeSuper BOOL amCodeData BOOL amCodeProgram BOOL postedWrites BOOL prefetchReads BOOL pci64 BOOL pciLockOnRMWs image the Universe VME slave image number from 0 7 vmeBase the VME base address of the window pciBase the PCI base address of the window size the size of the window in bytes pciAddrSpace the PCI address space The value can be either UNI PCI MEMORY SPACE 0 UNI PCI IO SPACE 1 or UNI PCI CFG SPACE 2 amCodeAdrsSpace specifies the VME address portion of the AM codes supported by the window It should be one of UNI AMCODE A16 0 UNI AMCODE A24 1 0rUNI AMCODE A32 2 amCodeUser specifies whether the window will respond to VME transactions with AM codes indicating Non privilidged access amCodeSuper specifies whether the window will respond to VME transactions with AM codes indicating Supervisory access amCodeData specifies whether the window will respond to VME transactions with AM codes indicating Data access amCodeProgram specifies whether the window will respond to VME transactions with AM codes indicating Program access 66 M5000 Series BSP User Guide Issued June 20 2007 VMETRO i VME Master amp Slave Access Configuration innovation deployed uniVmeSlavelmageSetup Continued Sy
92. mperature sensors bist proc P2P tests Tests the three P2P bridges on the M5000 board bist p2p Fibre Channel tests Tests the Fibre Channel interface on the M5000 board bist p2fc VME tests Tests the VME interface on the M5000 board bist p2vme Raceway tests Tests the RaceWay interface on the M5000 board bist p2race I O Spacer tests Tests Gigabit Ethernet extension modules mounted on some M5000 boards bist iospacer Mezzanine tests Tests the Mezzanine connection that is present on some M5000 boards the M55xx boards bist mezz Base board tests Tests other items on the board primarily the Ethernet interrupt bist baseboard Each group has an all function LE bist proc all that runs all the tests for that groups There are also two functions bist all and bist all show that run all the tests appropriate for the board on which they are being run A full list and explanation of the BIST API functions can be found in the BIST API Reference Guide A link directly to the API Reference Guide can be found on the main documentation webpage located in the documentation directory 150 M5000 Series BSP User Guide Issued June 20 2007 vmernoll innovation deployed Technical Support In order for us to provide fast technical support please provide the following information e Any modifications made to the default BSP e Any changes to the default versions of the FLASH files such
93. mple if muMessageEnable 1 ERROR printf Message Register 1 was successfully enabled n 32 M5000 Series BSP User Guide Issued June 20 2007 vmernoUl innovation deployed Message Register Support Issued June 20 2007 M5000 Series BSP User Guide 33 120 Messaging Unit Support vmernoUl innovation deployed 34 M5000 Series BSP User Guide Issued June 20 2007 innovation deploye VME Bus Operation Issued June 20 2007 M5000 Series BSP User Guide 49 VME Bus Operation VMETRO E innovation deployed 5 1 VME Master amp Slave Access Configuration Overview This chapter defines terminology and configuration macros that together provide a guideline for how VME master slave windows can be configured in the M5xxx BSP The standard frame of reference shall be the perceived view by the user and the local CPU i e the PPC440GX A master transaction is one where the M5xxx board takes control of the VME bus and initiates a VME transaction A slave transaction is one where the M5xxx board responds as a VME bus slave device to a transaction initiated by some other board acting as VME bus master On the M5xxx the VME interface is controlled with the Tundra Universe IID chip hereafter called the Universe The Universe databook 5 describes all the registers in the Universe and is a very useful resource to have handy when working with the Universe In the terminology
94. mples are Courier font and at least one size less than context Text that represents user input is bold Courier font Directory path names are italicized File names are in bold Absolute path file names are italicized and in bold Pressing of individual keys will be indicated as lt key gt For example lt Enter gt Press the key marked Return or Enter Pressing a key combination will be indicated as Mod n where Mod refers to any of the Control Cut Alt Alt or Shift Shift and n is any key For example Ctrl z Hold the Control key and press z Alt s Hold the Alt key and press s Simulated interaction with a computer will be shown in Courier type Required keywords in computer interaction examples are shown in bold Courier type and placeholders for items that vary or must be supplied by the user are indicated with italic Courier type Output from the computer is shown in one of these three preceding styles Input from the user is also displayed in one of these styles but with the addition of underlining Finally comments that are not actually displayed or typed but are provided in the text as aids to understanding are shown in italic Arial type Warning Indicates important information that can affect the operation of your M5xxx vi M5000 Series BSP User Guide Issued June 20 2007 vmernoll innovation deployed Note This is information th
95. net connection is available Serial Port If no Ethernet access is available or VxWorks does not boot then the Rom Monitor serial load must be used to burn Vx Works boot code Issued June 20 2007 M5000 Series BSP User Guide 103 Burning VxWorks Boot Code VMETRO E innovation deployed 9 1 Burning VxWorks Boot Code from Rom Monitor Serial On the M5xxx board VxWorks boot code is stored in non removable FLASH The board is always first booted by the M5xxx low level monitor program which will then boot VxWorks automatically The M5xxx monitor is used to download VxWorks boot code into FLASH via the serial port and file transfer with the KERMIT protocol The M5xxx monitor prompt is the symbol Follow the steps below to burn VxWorks boot code into FLASH 1 Make the VxWorks boot file if one does not exist This is typically bootrom bin but other targets that produce binary may be used as appropriate for the application Use the set baudrate command to configure the baudrate for the download operation Baud rates up to 115200 bps are supported Connect to the M5xxx board s serial port with any terminal emulator program such as HyperTerminal in Windows using the configured baudrate The terminal emulator program must be able to send files with the KERMIT protocol At the M5xxx monitor prompt download the boot file This procedure automatically erases the appropriate region of FLASH so it is not necessary to ex
96. ng object module can call subroutines anywhere within the 32 bit effective address space This can be done by using the compiler option mlongcall However dual instruction calls are slightly more expensive in both code space and execution time Therefore it is often better to keep sysMemTop at 32 MiB in order to provide the best possible efficiency By default the sysMemTop function returns a value close to the 32 MiB effective address range The sysPhysMemTop function can be used to determine the total amount of memory present on the board There are at present four ways an application can make use of the memory beyond the first 32 MiB 1 The first method is to create a separate memory pool for the extra memory 1 e not part of the system memory pool Refer to memPartLib memPartCreate in the Vx Works Reference Manual 2 The second method of getting around this restriction for downloadable applications is to use the mlongcall compiler option in the GNU compiler However this option may introduce an unacceptable amount of performance penalty and extra code size for some applications It is for this reason that the VxWorks kernel is not compiled using m1ongcall 3 The third method uses the standard Vx Works distribution but relies on loading all code modules first while only 32 MiB of memory is available then adding the extra memory to the system memory pool by a call to memAddToPool LOCAL MEM LOCAL ADRS 0x02000000 siz
97. nopsis postedWrites specifies whether the window will support posted write operations With posted write write continued operations may return before the data has been written to its final destination on the PCI bus prefetchReads specifies whether the window will support prefetch read operations With prefetch read read operations may actually read more than the amount of data requested so that surrounding data may more quickly be returned on the next operation pci 4 specifies whether the window will support 64 bit operation If this is enabled the window supports a data width of up to 64 bits postedWrites whether the window allows posted cached writes Either TRUE 1 or FALSE 0 pciLockOnRMWs tells whether the window will use PCI Lock signal on Read Modify Write cycles from VME to PCI bus Description This function is used to configure a Universe VME slave image This allows the M5xxx to act as a VME slave and support reading writing to the local PCI bus from other VMEbus devices configured as VME masters The difference between this function and uniVmeSlavelmageSet is that uniVmeSlaveImageSetup allows the window to simultaneously support multiple AM codes while uniVmeSlavelmageSet only allows a single AM code to be specified Note that the Universe VME slave images always support both single and block operation the VME master controls whether transfers are single cycle or block transfers Returns OK Or ERROR
98. nterrupt Routing and Sharing 19 Interrupt Connection and Enabling 20 3 5 PCI Bus Operations 21 OVERVIEW han Len Sams acid een Gants fedele De hylan Bs fan cede die a dee e 21 Issued June 20 2007 1 49 M5000 Series BSP User Guide ix vmernoUl innovation deployed PCI buses and MidasBusID 21 PMC slot 22 MidasBusIdFromPciBusNo 22 MidasBusIdToPciBusNo 24 MidasGetPmcBridgeBusNumbers 25 MidasPmcSlotInfoGet 26 MidasPciSlotInfoGet 27 3 6 PCI Optimizations 28 I20 Messaging Unit Support cesse eee oh n 29 AV OVERVIEW 36 cc bep oe Ede beetle i RER a 30 4 2 Doorbell register support 31 muOutDoorbell Write 31 muOutDoorbellRead 31 ee a A DS SD D DS NS e A eee A etes de 31 4 3 Message Register support 32 Common Definitions 32 muMessageConnect 33 mulsMessageConnected 34 muMessageDisconnect 34 muMessageEnable
99. oconfiguration Not Used 2 1260 0000 Extra PCI I O 2 0880 0000 Not Used 2 0801 0000 PCI I O 2 0800 0000 TN Not Used 10000000 0 1000 0000 Cacheable access to local PPC440 SDRAM 440GX slave PPC440 SDRAM 120 mapped by POMO 0 0000 0000 0000 0000 0660 6006 FIGURE 1 2 Outbound Address Mapping to PCI Memory Space with PCI Auto Configuration TABLE 1 3 M5xxx Inbound PCIbus Memory Space Relative Address Map Resource PCI Address range Mapped Mapped by 0x00000000 0x00000fff PPC440GX 120 PIMO PIM1 0x00001000 0xOfffffff SDRAM PIMO M5000 Series BSP User Guide Issued June 20 2007 VMETRO i M5xxx Address Maps and Address Space Mapping innovation deployed The I2O is the PPC440GX Message Unit which facilitates the transfer of messages between the PPC440GX and a device on PCI Please see the PPC440GX Embedded Processor User s Manual 1 for more information on the 120 Figure 1 3 shows how the inbound PCI memory maps to local PPC440GX memory 36 bit PLB Processor Local PCI memory Space Bus Address Map Address Map F FFFF FFFF FFFF FFFF Not used Not mapped unused 3 7000 0000 PCI Memory 2 9000 0000 Not Used 2 1260 0000 Extra I O 2 0880 0000 Not Used 2 0800 1000 Vo 2 0800 0000 Not Used 1 0000 0000 1 0000 0000 120 Msg Unit La d O ERE 009
100. ode from VxWorks Ethemet 105 9 3 Burning VxWorks Boot Code from U Boot Ethernet 106 Setting Network Parameters 106 TFTP 106 NFS 106 Flash VxWorks image 107 DMA RER eee SHAR OA der aedes AR CO 109 10 1 PPC440GX DMA Driver 110 Setting up a DMA transaction 110 Single DMA transactions 111 Chained DMA transactions 112 Common status structure 114 Address translation functions 114 Single blocking DMA transfer example 115 Chained DMA transfer example 116 MIDAS File System ed du CREER AREE REESE 123 11 1 The Midas File System MES 124 QYvePVIeW oie de rade eta eerte ecd bcd de ove rcge diede 124 The MFS Functions 124 UE NE TC 124 i fs ClOSe sus ae e o Ree drei ed UR ein 125 MES TEMO Ecen bim eet ee re ue 125 Infs dif uns eS Gere hod a Rae AE vigens 126 inis Seek iil eua e Ir eee E be ae ee 126 EIL ELI 127 mits tell zb be Rex e epu Rep ERR rete e Rt 127 no E 128 IDs MURS an cn tit esce NA 128 D S SB 1 m 129 PUES TOA ios etr Em etuer m t 130
101. of the Universe VME master windows are called PCI slaves Sometimes VME slaves are referred to as PCI masters In other words VME slaves are the same as PCI masters and PCI slaves are the same as VME masters The Universe supports a maximum of 8 PCI slave images and 8 VME slave images An image in Universe terminology is essentially just a window in address space through which one bus can access the other There are functions available in the BSP to configure both PCI and VME slave images and all of these functions are reviewed in this section These functions are uniPciSlaveImageSet uniVmeSlaveImageSet and uniVmeSlaveImageSetup One useful function for reviewing Universe slave images is uni ImageShow This function provides information about all of the currently defined Universe slave images both PCI and VME and their attributes Other useful functions are sysBusToLocalAdrs and sysLocalToBusAdrs which are documented in the PCI section above By default the PPC440GX BSP uses 3 PCI slave images and 1 VME slave image The sections below review the default slave image configurations Using parameters in the vmbsp ini file one additional PCI slave image and one additional VME slave image may be defined Please see the section of the manual on the vmbsp ini file for more details Note The VME slave bases of the M5xxx board are set in software see below not by hardware jumpers To change the bases from the def
102. on in the chain This is however not advised since there is no way to find out if the given transaction failed or not prev Pointer to a DMA descriptor Ifthis field is not NULL then the new descriptor is added in the chain after the previous descriptor next Pointer to a DMA descriptor If this field is not NULL then the new descriptor is added in the chain before the next descriptor dmaStatus Pointer to a status structure See Common status structure on page 114 for a description of this structure This structure is only used if the create function for some reason failed i e returned NULL 112 M5000 Series BSP User Guide Issued June 20 2007 VMETRO PPC440GX DMA Driver innovation deployed If the ppc440DmaChainDescCreate function succeeded in creating a new descriptor then a pointer to this descriptor is returned If not the return value is NULL To remove a descriptor the ppc440DmaChainDescRemove function is used This function is defined as follows int ppc440DmaChainDescRemove ppc440DmaChainDesc t desc ppc440DmaStatus t dmaStatus The fields are used as follows desc Pointer to the descriptor to be removed from the chain dmaStatus Pointer to a status structure See Common status structure on page 114 fora description This field is only used on ERROR This field may be set to NULL if status is not wanted This function will return OK or ERROR depending on if the remove s
103. on t trans ppc440DmaStatus_t dmaStatus ppc440DmaChainDesc t desc 10 0 0 0 0 0 0 0 0 0 0 ppc440DmaChainDesc t prev NULL if descs gt 10 printf Number of descs larger than 10 return ERROR setPattern uint32 t sourceBuffer bufferSize 4 erasePattern uint32 t destinationBuffer bufferSize 4 118 M5000 Series BSP User Guide Issued June 20 2007 VMETRO PPC440GX DMA Driver innovation deployed trans Alignment width trans Callback doXferChainedIsr trans UserContext NULL trans Channel 0 ppc440LocalAdrsToPlbAdrs sourceBuf fer amp trans SourceAddressLow amp trans SourceAddressHigh ppc440LocalAdrsToPlbAdrs destinationBuffer amp trans DestinationAddressLow amp trans DestinationAddressHigh trans TransferByteCount bufferSize trans Status 1234 trans DetailedStatus 4321 for cnt 0 cnt descs cnt desc cnt ppc440DmaChainDescCreate amp trans prev NULL amp dmaStatus if desc cnt status ERROR for cnt gt 0 cnt ppc440DmaChainDescRemove desc cnt 1 NULL break prev desc cnt if status OK doXferChained totalIntr 0 doXferChained status OK Issued June 20 2007 M5000 Series BSP User Guide 119 DMA drivers vmernoUl innovation deployed status ppc440DmaChainXfer desc 0 sysClkRateGet 30 amp dmaStatus if s
104. or must be changed to make this possible Issued June 20 2007 M5000 Series BSP User Guide 71 VME Bus Operation VMETRO E innovation deployed The PCI autoconfigurator reserves all PCI memory space associated with VME spaces from non prefetchable memory space By default the M5xxx BSP has a maximum of 768 MiB available for all non prefetchable PCI resources This can be increased by decreasing the value of PCI MASTER PREFETCH POOL SIZE in config h For this example the constant can be set in config h as follows define PCI MASTER PREFETCH POOL SIZE 0x80000000 Since a total of 0xE0000000 memory space is available for both prefetchable and non prefetchable resources the above line increases the amount of non prefetchable space used by the PCI autoconfigurator to 0x60000000 0xE0000000 0x80000000 In this example the default A32 PCI slave image may be used for the first board since there are no additional VME interface requirements The first slave image is configured as follows by modifying the sysV me c file in the location described above Set Universe window to VME A32 space uniPciSlavelmageSet MIDAS UNI A32 WIN NUM VmeA32MasterPciBase 0x18000000 VME A32 MASTER SIZE UNI PCI MEMORY SPACE Ox0Od UNI VMEBUS DATAWIDTH 32 TRUE For this example the value of VME A32 MASTER SIZE should be changed in sysVme h to 0x20000
105. plicitly erase the FLASH serial load 0xf4000000 0x lt filesize gt Where the optional parameter lt filesize gt is the length of the file in Bytes Escape back to the host and send the boot file with the KERMIT protocol Wait for file transfer to finish There will be a number of progress messages displayed as the M5xxx monitor writes the bootcode to FLASH Note after the serial load command is given the board waits to receive the boot file accepting no further input until file transfer is done or time out exception 104 M5000 Series BSP User Guide Issued June 20 2007 VMETRO i Burning VxWorks Boot Code from VxWorks Ethernet innovation deployed 9 2 Burning VxWorks Boot Code from VxWorks Ethernet In order to program a boot image from VxWorks Ethernet must be configured properly Details about how this is done are described in Ethernet emac Network Interface on page 88 Burning boot code into Flash from VxWorks is done as follows 1 Make sure that the Ethernet connection is working For example use the command ping or Jg 2 Program the boot image through flashLoad lt path gt lt filename gt lt address gt Example flashLoad tornado 2 2 1 90451 ppc target config midas ppc440 bsp1 2 rl 3 1 bootrom bin 0xf4000000 The address 0xf4000000 is the default address to program boot images This address has to match ROM TEXT ADRS in config h and Makefile ROM TEXT ADRS is
106. provides a guideline to allocate a buffer that is noncacheable BSP users with questions such as What is a cache safe buffer How do I get a buffer on the M5000 that can be used as shared memory between another board and the M5000 can find the answers here PClbus Operations provides an overview of the PCI bus architecture of the M5xxx board and a description of the routines used to generate PCI bus cycles BSP users with questions such as What is a PMC slot How do I read write the configuration registers of a PMC in slot 1 How do I read write PCI addresses How do I convert a local address to a PCI address Etc can find the answers here This chapter assumes that the reader has some knowledge of PCI terminologies and bus specifications PCI Interrupt Handling provides a guideline for connecting an Interrupt Service Routine ISR for a PCI device BSP users with question such as How do I connect an interrupt handler for my PMC board can find the answer here Message Unit Interrupt provides a guideline for using mailbox interrupt via the PPCA40GX Message Unit BSP users with questions such as What is a Message Unit Where is the MIDAS M5000 s mailbox address How can I interrupt the M5000 board from another board across PCI VME and or RACEway can find the answers here VME Master amp Slave Access Configuration provides a guideline to configure the M5xxx board to be master slave at certain VME addresses BSP users with question s
107. r Both direct DMA transfers and chained DMA transfers are supported by this module Universe DMA Driver In order to use the Universe DMA controller module of the BSP include the following line at the top of the application source file include uniDmaLib h The object module lt bsp directory gt mdrv lib uniDmaLib o must be loaded prior to loading the application The uniDmaLib o module may also be directly linked with the application The Universe DMA controller supports 2 modes of operation 1 Direct mode transfers a single block of data between the PCI bus and the VME bus Use uniDmaDirect function to initiate a direct DMA transfer 2 Linked list chained mode transfers one or multiple blocks of data between the PCI bus and the VME bus The DMA engine uses DMA command packets to describe how to transfer each block of data Use uniDmaChainCmdPkCreate to create DMA command packets Use the uniDmaChain function to initiate a chained DMA transfer Use uniDmaChainStop to stop a chained DMA transfer Use the uniDmaNotifyFncSet to specify a function to be called when the DMA engine is done or halts due to an error situation Universe DMA Interface Functions uniDmaLibInit STATUS uniDmaLibInit int show_release Synopsis This function initializes the Universe DMA library If the parameter show_release is Description TRUE the driver release info is printed to the console OK or ERROR Returns none Notes 78 M5000
108. refetchable memory space 0xC0000000 OXEFFFFFFF 768 MB for PCI non prefetchable memory space These should be sufficient for almost all real world applications In rare instances when more PCI memory space is needed there are several possible approaches to obtaining larger amounts of PCI Memory Space If the VME outbound windows are not required the non prefetchable memory pool can be effectively made larger by disabling the VME outbound windows See the section on VMEbus operation for more information on how to do this If even larger amounts of PCI Memory Space are required please contact Vmetro technical support for assistance The regions of PCI I O Space are summarized as follows OxF8800000 OXFBFFFFFF 56 MiB for 32 bit PCI I O space OxF8000000 OxF800FFFF 64 KB for 16 bit PCI I O space These should be sufficient for almost all real world applications The sizes of the 16 bit and 32 bit PCI I O space are as large as the PPC440GX allow them to be In order to gain a better understanding of what the PCI autoconfigurator is doing and to determine how much PCI Memory and I O Space is being used by the PCI autoconfigurator the PCI AUTO DEBUG constant found in pciAutoConfigLib c can be define d This constant is undef ed by default By define ing this constant a large amount of serial output will be generated by the PCI autoconfigurator It is recommended that the PCI AUTO DEBUG variable be left undef ed for distributable applic
109. ries BSP User Guide Issued June 20 2007 vmernoll innovation deploued Fibre Channel Support Issued June 20 2007 M5000 Series BSP User Guide 139 Fibre Channel Support VMMETRO innovation deployed 12 1 Fibre Channel Information Overview The M5xxx models with F in the model name contain an onboard Qlogic ISP2312 dual Fibre Channel controller Models with a single F have front panel access to one Fibre Channel port and models with two F s in the model name have front panel access to both Fibre Channel ports The Fibre Channel driver is sold as part of a separate product called VMFC driver for VxWorks VMFC DRV VXWORKS and is documented in the VMFC Driver Software Reference Manual 12 140 M5000 Series BSP User Guide Issued June 20 2007 vmernoll innovation deploued APPENDIXES Issued June 20 2007 M5000 Series BSP User Guide 141 vmernoU innovation deployed 142 M5000 Series BSP User Guide Issued June 20 2007 vmernoll innovation deployed Troubleshooting This section covers common problems encountered with the M5000 Issued June 20 2007 M5000 Series BSP User Guide 143 Troubleshooting VMMETRO innovation deployed Gigabit Ethernet network communication does not work For Gigabit Ethernet Switches The default configuration of the M5000 BSP requires that all Gigabit Ethernet switches in the data path between the M5000 and other Gi
110. s and that this feature is enabled Otherwise communication will fail It is also important that both of the devices that communicate with Gigabit Ethernet have support for JUMBO packets and that this feature is enabled Otherwise the standard MTU size of 1500 will be used which will slow down the throughput significantly In order to get maximum throughput performance on Gigabit Ethernet the JUMBO packets should be enabled and set to size 8000 as they are by default look for EMAC2 MTU and EMAC3 MTU in config h Optimizations of the IP stack are also configured by default in config h It is important to increase the TCP and or UDP socket buffer sizes in order to get the maximum throughput This can be done for test purposes by setting global variables from the VxWorks shell prompt as follows tcp sendspace 0x38000 tcp recvspace 0x38000 udp sendspace 0x38000 udp recvspace 0x38000 Issued June 20 2007 M5000 Series BSP User Guide 91 Network vmernoUl innovation deployed A better approach however is to use the command setsockopt to set the buffer sizes to the same values as above on socket level This is to avoid that all TCP and UDP sockets use such large buffer sizes Set SO SNDBUF and SO RCVBUF for TCP and UDP int soSndBufSize 0x38000 int soRcvBufSize 0x38000 if setsockopt fd SOL SOCKET SO SNDBUF char amp soSndBufSize sizeof soSndBufSize
111. s from local and PCI addresses are provided by the driver See Address translation functions on page 114 for a description The buffers must be aligned as implied by the alignment field Status Status of operation where applicable Always set OK or ERROR DetailedStatus Detailed status of operation where applicable See header file for values Callback Pointer to callback function If this field is set to NULL then blocking mode is implied UserContext Pointer to user context used in non blocking mode The callback function will be called with this field as a parameter Some fields in the structure are only applicable to the given user mode For single transactions the driver supports both blocking and non blocking modes Chained transactions only support non blocking mode Single DMA transactions Transfers involving only one transaction structure are most efficiently executed through the ppc440Dmaxfer function This function supports both blocking and non blocking mode Blocking mode is chosen by setting the callback field in the transaction structure to NULL The ppc440DmaXfer function is defined as follows int ppc440DmaXfer ppc440DmaTransaction t trans int timeout ppc440DmaStatus t dmaStatus Issued June 20 2007 M5000 Series BSP User Guide 111 DMA drivers vmernoU innovation deployed The fields are used as follows trans Pointer to a DMA transaction structure See Setting up a
112. s of secondary VME slave base image VmeA32SlaveDisable If present secondary VME slave base image is disabled Values TRUE FALSE Power of 2 1MiB 512 MiB Power of 2 1 MiB 64 MiB Power of 2 16 bytes 256 KiB Values Default VME A32 Not present base address 32 bit VME Not present base address VME A32 Not present base address 0 1 Not present Default FALSE 0 disabled 0 disabled 0 disabled The Universe DMA driver is part of the BSP and is documented in the Universe DMA Driver Software Reference Manual 136 M5000 Series BSP User Guide Issued June 20 2007 vmernoll The mmon ini File innovation deployed 11 3 The mmon ini File Normally the mmon ini file does not need to be modified by the user The BoardInfo Section Flag name Meaning Values Default Model The model number of the Set by factory Depends on board config board SerialNo The serial number of the Set by factory Assigned by manufacturer board ECO level The ECO level of the board Set by factory Assigned by manufacturer TotalDramSize The size ofthe SDRAM Set by factory Assigned by manufacturer memory The AutoStart Section Flag name Meaning Values Default StartAddr The addres from which to start Oxf400 0000 0x fAfffFfF Oxf400 0000 booting an application VxWorks Issued June 20 2007 M5000 Series BSP User Guide 137 MIDAS File System VMETRO E innovation deployed 138 M5000 Se
113. s the AM code a VME bus error will occur There must be only one VME target device in the system accepting the specified AM code and VME address Otherwise the results of this function are unpredictable The size of the DMA transfer can be as small as one byte and as large as 16 MB Ifa block AM code is specified such as 0x8 Oxb Oxc or Oxf and the size of the transfer is less than 8 bytes the Universe generates single cycle accesses i e using a non block data AM code such as 0x9 or Oxd The Universe also generates single cycle accesses when vmeAdrs and pciAdrs are not aligned to 8 byte boundaries See the Universe Notes Reference Manual from Tundra Semiconductor Corp for more information Issued June 20 2007 M5000 Series BSP User Guide 79 VME Bus Operation vmernoUl innovation deployed uniDmaChainCmdPktCreate Synopsis Description Returns Notes UNI DMA CHAIN CMDPKT NODE uniDmaChainCmdPktCreate UINT32 vmeAdrs UINT32 pciAdrs UINT32 byteCount UINT32 vmeAmCode BOOL pci64 int direction UNI DMA CHAIN CMDPKT NODI UNI DMA CHAIN CMDPKT NODI prev next E Lui uniDmaChainCmdPktCreate allocates a new DMA chain command packet and initializes it according to the arguments given lt vmeAdrs gt is the VME bus address of the DMA block pciAdrs is the PCI bus address of the DMA block lt byteCount gt is the number of bytes in the DMA block
114. sLib functionality added to the M5xxx BSP mdrv include uniDmaLib h header file for Universe DMA engine mdrv include uniLib h header file for Universe library mdrv lib contains all the BSP archive libraries md rv lib libmdrvs a this is an archive library that contains all the BSP drivers The object modules in this library are linked in on demand as part of VxWorks 440gxBusErr s PPC440GX dependent bus error reporting 440gxBusErrOriginShow c used for decoding the bus error value from sysBusErrRegsGet config h this file contains configuration parameters for VxWorks This file may be edited directly Usually BSP development from the command prompt is the desired approach However the BSP may be developed from within Tornado itself in which case the configuration parameters may be changed from within Tornado configNet h Platform independent network configuration cprDcr h IBM chip clocking and PDR DCR definitions dmaDcr h PPCA40GP DMA controller DCR access assembly routines ebcDcr h IBM external bus controller DCR definitions emacEnd c h EMAC Ethernet driver with patch 90835 L2Lib c Level 2 cache controller support Makefile this file performs the compilation and linking steps to build various Vx Works images as requested by the user maDcr h IBM Memory Access Layer MAL DCR access assembly routines Issued June 20 2007 M5000 Series BSP User Guide 101 BSP Installation VIMETRO innovat
115. stems Inc 8 WindRiver Platforms Getting Started Wind River Systems Inc 9 VxWorks 5 5 Network Programmer s Guide Wind River Systems Inc 10 VxWorks 5 5 Reference Manual Wind River Systems Inc 11 MIDAS Monitor User Guide VMETRO Inc 12 MIDAS PXB DMA Driver Software Reference Manual VMETRO Inc 13 VMFC Driver Software Reference Manual VMETRO Inc viii M5000 Series BSP User Guide Issued June 20 2007 vmernoll innovation deployed Contents CERO Et iw ERES ge SR MR REY Pa EP qr It d eae 1 TDi QV GEVICW Lives ado teetrep Rene ne detente tdt 2 1 2 M5xxx Model Numbering 4 1 3 M5xxx Address Maps and Address Space Mapping 5 System Memory ci crt oes wen cS Ado an eh nee ey BER Reese 9 2 1 System Memoty eoa E Lio parecia RR lc each each a 10 2 2 Cache safe Buffers issue eee ot axis e ean 11 2 3 Error Checking and Correction ECC 12 PCI Bus UB FIIO Cue g sou xata gt Ru CROCE areae e er pt a 13 S L PCI Bus Layout esee ret pk ER race pande ei cidem 14 3 2 PCI Configuration Space Access 15 3 3 PCI Memory and I O Space Access 16 sysBusToLocalAdrs 17 sysEocalToB sAdr i ver Ryu diese dut menteur ER 18 3 4 PCI Interrupt Handling 19 Interrupt PIWi o eso esed oe nee es Rent EU nd en nee 19 I
116. t levels vectors associated with interrupt inputs to the UIC See mdrv include midasppc440 h for the interrupt levels and vectors defined for the M5xxx implementation The functions sysIntEnable and sysIntDisable in sysLib c applies only to VMEbus interrupt request levels See the 7 for details 20 M5000 Series BSP User Guide Issued June 20 2007 VMETRO 5 PCI Bus Operations innovation deployed 3 5 PCI Bus Operations Overview The functions documented here are used to access the PCI buses on the M5xxx board The application code needs to include the header files listed below all BSP provided header files can be found in the BSP directory midasppc440 or in midasppc440 mdrv include e MidasPciLib h WIND BASE target h drv pci pciConfigLib h PCI buses and MidasBusID All M5xxx boards have three 3 PCI X buses which are referred to as the Primary Secondary and Tertiary PCI X buses All M5xxx boards also have one 1 PCI bus referred to as the Quaternary PCI bus In addition M55xx boards have a fifth PCI bus referred to as the MEZZ500 PCI bus To differentiate between the five buses some of the functions use a MidasBusId parameter The MidasBusld is an identifier used to specify which of the physical PCI X PCI buses are being referenced There is no MidasBusld associated with additional P2P bridges that may be present for example P2P bridges installed on PMCs The MidasBusld can only be one of the follo
117. tatus OK printf ppc440DmaChainxfer FAILED Status Ox x text s dmaStatus status_code else Wait for all descs whil taskDelay sysClkRateGet status doXferChained status doXferChained totalIntr lt descs dmaStatus status text amp dmaStatus OK if status OK Check buffer if checkPattern uint32 t destinationBuffer bufferSize 4 OK printf checkPattern FAILED status ERROR for cnt 0 cnt lt descs cnt if ppc440DmaChainDescRemove desc cnt status ERROR return status int doChain void 120 M5000 Series BSP User Guide Issued June 20 2007 VMETRO PPC440GX DMA Driver innovation deployed int width 16 int bufferSize 1024 int descs 2 int status OK void sMallocPtr void dMallocPtr uint32 t sourceBuffer uint32 t destinationBuffer sMallocPtr cacheDmaMalloc bufferSize width if sMallocPtr NULL printf cacheDmaMalloc FAILED return ERROR dMallocPtr cacheDmaMalloc bufferSize width if dMallocPtr NULL printf cacheDmaMalloc FAILED cacheDmaFree sMallocPtr return ERROR sourceBuffer uint32 t sMallocPtr width uint32 t sMallocPtr width destinationBuffer uint32 t dMallocPtr width uint32 t dMallocPtr width status doXferChained width bufferSiz
118. tf Midas quaternary PCI bus corresponds to PCI bus number x n PciBusNo break case MIDAS MEZZ500 BUS printf Midas MEZZ500 PCI bus corresponds to PCI bus number x n PciBusNo Issued June 20 2007 M5000 Series BSP User Guide 23 PCI Bus Operation VMETRO E innovation deployed MidasBusIdToPciBusNo Synopsis int MidasBusIdToPciBusNo UINT8 MidasBusId NT8 PciBusNo I MidasBusId The Midas Bus ID Must be one of IDAS PRIMARY BUS 0 IDAS SECONDARY BUS 1 I HE I z mox DAS TERTIARY BUS 2 DAS QUATERNARY BUS 3 DAS MEZZ500 BUS 4 z M PciBusNo pointer to a UINT8 that holds the returned PCI bus number Description This function translates a Midas bus ID to its corresponding PCI bus number The MIDAS bus ID is a software reference to one of the buses on the M5xxx board The PCI bus number is the actual PCI bus number stored in the bus number registers of the P2P bridges on a particular segment Returns OK Or ERROR Example UINT8 PciBusNo if MidasBusIdToPciBusNo MIDAS PRIMARY BUS amp PciBusNo ERROR printf Midas primary PCI bus corresponds to PCI bus number x Mn PciBusNo if MidasBusIdToPciBusNo MIDAS SECONDARY BUS amp PciBusNo ERROR printf Midas secondary PCI bus corresponds to PCI bus number x Mn PciBusNo if MidasBusIdToPciBusNo MIDAS TERTIARY BUS amp PciBusNo ERROR printf Midas t
119. tion of the licensing agreement be furnished or disclosed to any third party and may not be copied or reproduced by any means electronic mechanical or otherwise in whole or in part without specific authorization in writing from VMETRO Copyright 2007 VMETRO This document may not be furnished or disclosed to any third party and may not be copied or reproduced in any form electronic mechanical or otherwise in whole or in part without the prior written consent of VMETRO vmernoU innovation deployed Warranty VMETRO products are warranted against defective materials and workmanship within the warranty period of one year from date of invoice Within the warranty period VMETRO will free of charge repair or replace any defective unit covered by this warranty A Return to Manufacturer Authorization RMA number should be obtained from VMETRO prior to return of any defective product With any returned product a written description of the nature of malfunction should be enclosed The product must be shipped in its original shipping container or similar packaging with sufficient mechanical and electrical protection in order to maintain warranty The product should be returned at the user s expense including insurance for the full product value This warranty assumes normal use Products subjected to unreasonably rough handling negligence abnormal voltages abrasion unauthorized parts replacement and repairs or theft are not cover
120. ts an ISR to the Inbound Message register specified by the regNum argument OK or ERROR int isr int arg logMsg This is my ISR arg d n arg return ERROR int isrInstall int arg 4 Connect ISR to the Inbound Message Register 0 if muMessageConnect 0 isr arg ERROR return ERROR Issued June 20 2007 M5000 Series BSP User Guide 31 120 Messaging Unit Support VMETRO E innovation deployed mulsMessageConnected Synopsis int muIsMessageConnected int regNum regNum Inbound Message Register 0 or 1 Description Test to see if there is an ISR connected to the Inbound Message Register specified by the regNum argument Returns TRUE if there is an installed ISR or FALSE Example If mulsMessageConnected 1 printf There is an ISR installed for Inbound Message Register 1 n muMessageDisconnect Synopsis int muMessageDisconnect int regNum regNum which Inbound Message Register 0 or 1 Description This function disconnects an ISR from the Inbound Message Register specified by the regNum argument Returns OK Or ERROR Example if muMessageDisconnect 1 ERROR return ERROR muMessageEnable Synopsis int muMessageEnable int regNum regNum which Inbound Message Register 0 or 1 Description This function enables the message interrupt Returns OK Or ERROR Exa
121. ucceeded or not Further status may be retrieved through the status structure When a descriptor is removed the rest of the chain is modified to keep the chain consistent The DMA chain is executed through the ppc440DmaChainXfer function This function is defined as follows int ppc440DmaChainXfer ppc440DmaChainDesc t desc int timeout ppc440DmaStatus t dmaStatus The fields are used as follows desc Pointer to a DMA descriptor The user application may choose which descriptor in the chain to start at If the chain 1s to be started from the beginning then the user application must make sure that this field is a pointer to the first descriptor timeout Driver timeout for execution The PPC440GX DMA engine does not support timeouts Thus this timeout is only used in software when waiting for control over the engine dmaStatus Pointer to a status structure See Common status structure on page 114 fora description of this structure This structure is only used on ERROR Issued June 20 2007 M5000 Series BSP User Guide 113 DMA drivers VMETRO m innovation deployed Common status structure Several of the function calls in the PPC440GX DMA driver interface use a common status structure This structure is defined as follows typedef struct ppc440DmaStatus int status_code char status text 256 ppc440DmaStatus t The fields are used as follows status code Integer value representin
122. uch as How can I get the M5xxx board to read write a VME slave at sextets address How can a VME master read write the M5xxx memory Etc can find the answers here RACEway PCI Interface provides important information on how to handle M5000 board with the RACEway interface R option BSP users with question such as How can I use a M5000 R board in a non RACEway VME slot I boot a M5xxx R board with VxWorks and it hangs what happens Etc can find the answers here Issued June 20 2007 M5000 Series BSP User Guide y vmernoU innovation deployed Network Interfaces provides a guideline for using various network interfaces BSP users with questions such as How do I boot the M5000 board with sm How do I boot the M5000 board with an ethernet interface can find the answers here BSP Installation and Distribution provides information on BSP installation and software distribution Burning VxWorks Boot Code provides a guide on how to burn VxWorks boot code on the M5000 board DMA Drivers provides information on DMA drivers associated with the M5000 The Midas File System provides information on the Midas File System implemented in FLASH memory of the M5000 board Fibre Channel Information provides information about the Fibre Channel interface built into the M5000 board Appendixes Troubleshooting e Deprecated Functions e BIST Built In Self Test Technical Support Style Conventions Used Code sa
123. ude iospacer h header file supporting io spacer mdrv include mfs h header file supporting the Midas File System in Flash mdrv include mfs_ini h ini file support for Midas File System mdrv include mfs_usr h header file for support of Midas File System mfs user functions mdrv include midas h header file containing many M5xxx board specific addresses and other hardware defines mdrv include MidasIntLib h header file with MIDAS interrupt routing support mdrv include MidasPciLib h M5xxx specific PCI usage header file mdrv include midasppc440 h header file with PPC440GX specific I O addresses and constants mdrv include model h header file associated with identifying model number of Midas products mdrv include mu h message unit definition header file mdrv include p2pLib h header file for PCI to PCI P2P bridge library 100 M5000 Series BSP User Guide Issued June 20 2007 VMETRO uj BSP Installation amp Distribution innovation deployed mdrv include pcicfg h PCI configuration header file mdrv include pciLib h PCI library header file mdrv include ppc440DmaLib h header file for the PPCA40 DMA mdrv include pxb h header file with PXB driver definitions mdrv include pxb bsp midas h header file with Midas BSP specific PXB driver definitions mdrv include sprom h header file supporting sprom c mdrv include sprom_ppc440 h PPC440 specific SPROM definitions mdrv include sysLibMidas h header file for extra sy
124. ued June 20 2007 M5000 Series BSP User Guide 85 RACEway PCI Interface vmernoUl innovation deployed 86 M5000 Series BSP User Guide Issued June 20 2007 vmernoll innovation deployed Network This chapter documents various network interfaces supported by the M5xxx BSP The conditional define INCLUDE N ETWORK in config h controls the inclusion of network protocol and device driver support by the M5xxx BSP Issued June 20 2007 M5000 Series BSP User Guide 87 Network vmernoU innovation deployed 7 1 Ethernet emac Network Interface The PPC440GX CPU includes four Ethernet interfaces generally referred to as emac The M xxx BSP includes support for the emac interface using the Wind River Enhanced Network Device END driver model which is enabled when INCLUDE END is defined in config h The M5xxx may support up to 3 simultaneous Ethernet connections depending on the specific configuration of the board In all configurations at least one Ethernet connection will always be available Either emacO or emac2 will be available in all configurations The other ports that may be available are emac or emac3 e emac0 is the onboard fast Ethernet port 10 100 Mbps emacl is an IOSpacer fast Ethernet port 10 100 Mbps emac2 is an IOSpacer gigabit Ethernet port 10 100 1000 Mbps e emac3 is an IOSpacer gigabit Ethernet port 10 100 1000 Mbps Configuring the
125. unction seeks to a specified point in an MFS file so that future reads writes to the file occur from the given point Returns If the seek cannot be performed ERROR is returned Otherwise OK is returned Example Seek to the end of a file in MFS mfs seek fd 0 MFS END 126 M5000 Series BSP User Guide Issued June 20 2007 VMETRO 5 The Midas File System MFS innovation deployed mfs stat Synopsis STATUS mfs stat int fd MFS STAT stat d the file number that was previously returned from mfs open stat pointer to an MFS STAT structure which contains offset and size of the file Description This function queries the status of a file in sprom Returns If the stat cannot be performed ERROR is returned Otherwise OK is returned Example Get the status of a previously opened file in MFS MVS STAT mfs stat mfs stat fd amp mfs stat mfs tell Synopsis int mfs tell int fd d the file number that was previously returned from mfs open Description This function returns the current offset location for reading writing from to a file in SPROM Returns If the operation cannot be performed ERROR is returned Otherwise the offset is returned Example Get the current read write location of a previously opened file in MFS int offset offset mfs tell fd Issued June 20 2007 M5000 Series BSP User Guide 127 MIDAS File System VMETRO E innovation deployed
126. us devices configured as VME masters Note that the AM code parameter specifies the size of VMEbus address space 1 e A16 A24 or A32 whether the window will support either Data or Program transactions not both and whether the window will support either Supervisor or Non priviledged operation not both The Universe VME slave image itself can simultaneously support both Data and Program transactions and both Supervisor and Non priviledged operation In order to open a window with support for such combinations use the uniVmeSlavelmageSetup function instead Also note that AM code does not specify whether VME slave images always support single and or block operation The Universe VME slave images always support both single and block operation the VME master controls whether transfers are single cycle or block transfers Returns OK Or ERROR Example This example sets up a VME slave image at PCI address 0xb0000000 and VME address 0x50000000 The AM code is 0x3d therefore VME address space is A24 and 32 bit Supervisory Data transactions are supported the size of th window is 0x400000 4 MB uniVmeSlavelmageset 7 0x50000000 0xb0000000 0x400000 UNI PCI MEMORY SPACE Ox3d TRUE TRUE TRUE TRUE Issued June 20 2007 M5000 Series BSP User Guide 65 VME Bus Operation VMETRO E innovation deployed uniV meSlavelmageSetup Synopsis STATUS uniVmeSlave
127. used when specifying a device used to boot VxWorks 4 M5000 Series BSP User Guide Issued June 20 2007 vmernoll innovation deployed M5xxx Address Maps and Address Space Mapping 1 3 M5xxx Address Maps and Address Space Mapping The address map layouts CPU and PCI for the M5xxx BSP implementation are as follows These maps are shown as supported with the default PCI auto configuration Manual PCI configuration is not currently supported by the M5xxx BSP A detailed look at PCI address space assignment is given in the section of PCI bus layout TABLE 1 2 M5xxx BSP 32 bit Effective Virtual Address Map with PCI Auto config default Address range 0x00000000 0x0dffffffh 0x0e000000 0x0fffffff b 0x10000000 0xbffffffffT 0xc0000000 0xefffffffT 0xf0000000 OxfOffffff 0xf1000000 Oxflffffff 0xf2000000 0xf2ffffff 0xf 3000000 Oxf4ffffff 0xf5000000 0xf5ffffff 0xf8000000 0xfbffffff Oxfc000000 Oxfdffffff 0xfd000000 0Oxfdffffff Oxfe000000 Oxffffffff Resource Mapped Cached System SDRAM access Non cached System SDRAM access PCI outbound translation window PCI outbound translation window Internal CPU Peripherals I20 SRAM FLASH memory cached PLD PCI I O outbound Not mapped available PCI X bridge FLASH memory non cached Mapped by MMU TLB Entry MMU TLB Entry MMU TLB Entry U TLB Entry U TLB Entry MMU TLB Entry MMU TLB Entry U TLB Entry MMU TLB Entry MMU TLB Entry
128. wing values e MIDAS PRIMARY BUS 0 MidasBusld for primary PCI X bus MIDAS SECONDARY BUS 1 MidasBusld for secondary PCI X bus e MIDAS TERTIARY BUS 2 MidasBusld for tertiary PCI X bus e MIDAS QUATERNARY BUS 3 MidasBusld for quaternary PCI bus e MIDAS MEZZ500 BUS 4 MidasBusld for MEZZ500 PCI bus The MidasBusld is useful for identifying a PCI device typically a PMC card by its physical bus location This need typically arises in applications where multiple PMC slots carry the same type of PMC card and the user needs to associate each PMC card with different roles in the system The function MidasPmcSlotInfoGet is used to retrieve the physical parameter associated with a given PMC slot When there is only one PMC card of a certain type the standard VxWorks library function pciFindDevice is preferred in order to retrieve PCI bus and device numbers for the PMC card Note that the MidasBusld is not necessarily the same value as the actual secondary bus numbers stored in the P2P bus number registers The actual secondary bus number for a particular PCI device is referred to in the PCI Specification 3 documentation the BSP itself and this documentation as the PCI bus number When PCI auto configuration is enabled PCI bus numbers are automatically determined by the PCI auto configurator The PCI bus numbers assigned by the PCI auto configurator may change from one bootup to the next depending on the hardware and options being used
129. x09 UNI VMEBUS DATAWIDTH 32 TRUE This second approach has the disadvantage of keeping 240 MiB 256 MiB 16 MiB of PCI space MMU mapped reserved and unused although this shouldn t be a problem in most applications since there is usually more than enough PCI memory space available to the PCI autoconfigurator Option 3 The most flexible approach to configuring PCI slave images is a little more sophisticated In this approach the total amount of extra space required for all additional VME interface regions is reserved by the PCI autoconfigurator Then the application can use uniPciSlavelmageSet to reconfigure existing PCI slave images and to configure up to four additional PCI slave images This sequence is necessary because the PCI autoconfigurator must consistently configure the three P2P bridges between the CPU and the Universe chip to handle all of the PCI slave images that will be used For example suppose the M5xxx needs to interface with four VMEbus digitizer boards with the following specifications AM Board VME base Size code 1 0x 18000000 0x20000000 0x0d 2 0x40000000 0x10000000 0x0d 3 0x60000000 0x10000000 0x0d 4 0x80000000 0x10000000 0x0d Also assume that these four boards are the only VME interfacing requirement for the M5xxx The total amount of VME space required to interface to these boards is 1 GiB 256 MiB Due to the large amount of space needed a default setting in the PCI autoconfigurat

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