EVBUM2300 - NB3H5150MNG Evaluation Board User`s Manual
Contents
1. MM_ICN COMP DEVICE TYPE COMP_VALUE SOURCE SOURCE _PN QTY REFPDES 13 80 112 00108 Connector Header hdr_1x03_ 100 Samtec TSW 150 14 G S 440 J42 444 446 J48 50 Pos 0 100 J50 J61 J62 J63 J64 J75 J OSC FSEL J OSC OE 80 112 00249 CONN HEADER FMAL 26 pis conn Digi Key S7116 ND 2 CN2 CN3 26PS 1 DL GOLD 80 112 00108 HDR S5PIN CROSS 100 HDR 1x01 5 pin Samtec TSW 150 14 G S 4 J71 J72 J73 J74 _HEADER MAL 80 112 00108 Connector Header hdr 1 x02 100 Samtec TSW 150 14 G S 5 J58 J OSC VDD 50 Pos 0 100 J_SCL1 J SDA1 J USB PWR DUT OSC ON NBXDBAQ14 DN U3 CLCC 7X5 254 D TP TP Y DNI OSC_ECS_SUBMINIATU DNI RE_OSC_MINI_6 80 112 00199 TEST POINT PC MULTI TP RED Digi Key JA J5 420 421 J22 J23 PURPOSE RED EXT_OSC_VDD 80 112 00148 TEST POINT PC MULTI TP BLK Digi Key ES PURPOSE BLK 3 3 1 5010K ND 5011K ND 5011K ND 5011K ND 80 112 00148 TEST POINT PC MULTI TP BLK Digi Key PURPOSE BLK 80 113 00905 Crystal CTS 25 MHz TH 25 MHz Digi Key ABL 25 000MHZ B2F NCP4586DSN33T1G ND 80 116 00527 IC REG LDO 3 3 V 0 15 A 3 3 V Digi Key SOT23 5 80 116 00526 IC REG LDO 2 5 V 0 15 A 2 5 V Digi Key SOT23 5 80 116 00528 IC REG LDO 1 8 V 0 15 A BV Digi Key SOT23 5 FM NCP4688DSN25T1GOSCT N U402 U403 U U MIC5247 1 8YM5TR 80 112 00148 TEST POINT PC MULTI TP BLK Digi Key PURPOSE BLK U401 NCV1117STAT3G 1 80 116 00549 IC REG LDO ADJ 1 A Digi Key SOT223 CSP ON2. R1A1 CLK1A gt 33 VDDO1 A gt RIAS R1B3 127 R1A2 CLK1 A amp B 0 OUTPUTS BO 0 RIAA R4B4 835 835 R1B1 CLK1B gt 33 Vo wd f J69 LVPECL Differential CLK4AB LVCMOS CLK2A CLK2B LVCMOS CLK3A CLK3B LVPECL ONLY o LK4AB LVCMOS CLK4A CLK4B LVPECL Differential CLK3AB VDDO1 DNI R1A5 A LVCMOS OUTPUT DN TsopF R1 NZ A GND GND LVPECL OUTPUTS Through 2 1 Balun GND VDDO1 DNI R1B5 A LVCMOS OUTPUT DNI 5 0 pF R1B6 CLK1B S A GND GND Figure 12 Output Selection Capabilities CAUTION CLK1 CLK2 CLK3 8 CLK4 pairs are configured as both LVCMOS and LVPECL outputs www onsemi com NB3H5150MNGEVB The user must determine each output type and configure the outputs accordingly by removing the appropriate components to establish one signal output path R1A1 CLK1A gt e 33 VDDO1 A R1B3 127 e CLKn A amp B j OUTPUTS sj e gt RIM 9 R4B4 1UF 83 5 R1B1 an CLK1B gt 33 LVCMOS Output Configuration Remove RIA2 and R1B2 RIAI and RIBI remain installed The LVCMOS outputs have provisions for a series Rs and a Cl oad Rs 33 02 and Ci bad 5 pF are installed VDDOT DNI RIA5 A LVCMOS OUTPUT LVCMOS OUTPUT GND GND Figure 13 LVCMOS Output Configuration LVPECL Output Configuration Remove RIAI and RIBI RIA2 and RIB2 remain installed RIA3 amp RIA4 and CLK1A gt gt VDDO1 A R1B3 127
3. A J_OSC_FSEL ud Fu 1j E GND a 2 1513 3 s DNI x GND RTO Reg DNI CLK_XT1 CLKB_XT2 Figure 7 Crystal or External Clock Input Configuration Schematic External Crystal Oscillator The NB3H5150MNGEVB has features to use a 4 or 6 pin XO U3 in either a 5 x 7 mm or 3 2 x 5 mm package 1 The XO can be powered separately by a VDD of the demo board connect J OSC_VDD HEADER 2 b An external VDD power supply connect EXT_OSC_VDD at OSC_VDD 2 Connect jumper at J75 for the XO GND pin 3 In either option install R73 0 4 to power the XO 4 C91 amp C92 are bypass capacitors for the XO VDD power pin and are installed 5 If using an XO J OSC OE jumper header will control the OE function of the XO and J_OSC_FSEL will control the frequency select option of the XO if needed Also a crystal in a 4 pin package can be installed over the XO footprint Signal Generator 1 Select Clock Input a Differential Input pu 0 Connect a signal generator to the J59 amp J60 SMA connectors for the CLK XTALI amp CLKb XTAL inputs H Set appropriate input signal levels 111 Install 50 62 termination resistors at R31 amp R32 for a signal generator termination iv Remove C31 amp C32 Install R69 amp R70 b Single Ended Input 1 Connect a signal generator to the J59 SMA connectors for the CLK XTALI input li Ground CLKb_XTAL2 111 Set appropriate input signal levels iv Install 50 62 t
4. Copper 7 60000 0000 Pra 5 foam 0002 Comer f 50000 0000 eea e Boom 00012 Copper 50 100 0010 0 012 Figure 18 NB3H5150MNG Evaluation Board Layer Stack Up 0 0012 0 100 0 010 0 012 GND www onsemi com 14 NB3H5150MNGEVB SCHEMATICS davod ONHU OSISHEAN nro Lo OUT yee lt 100 60904 eca Quad TOQQA 0 CAAYASAY gt Ore asa UU U U O O gt lt y y GI ly Lad rOqqA A QQ FIC 223 BZZ IND SEG b 8011 je y El U GND UND Ko SAP OSTSHEEN INASNO OQQA a gt gt Ind TOUAA LAG 6007 Ind 1007 IND 98 ING UNO _ tin OSISHEAN IWASNO UNO T 0011 60 Jpu Ho H e V f dda qdOWsaa i UND ZN PRE 5 A I a OLA L FARANE ZUDE X UNO N GSS PITI aw ju I Mg 69A ES H N O b ING GND _ UND cdo Wi 001 ING u H ET E o ddA OSO OXI 104 F TASA OSO f HO OSO f I O V 38073 _ddA_OSO QQAQQA OSO f ddA SO IXA ELA www onsemi com 15 NB3H5150MNGEVB 10 00006 davod OWAQ OSTSHE AN oul sonTepeds Ilo JA op ee lava ee IVrI ce Taca te IVA 47472 rx ENTOD YENTO 8 ogra L ad o g ING e a 182 de 1 IND a sara INA nq roada S ES gt SER dND ant PEPA 410
5. 33 790 2910 i Fax 303 675 2176 or 800 344 3867 Toll Free USA Canada Japan Customer Focus Center For additional information please contact your local Email orderlit onsemi com Phone 81 3 5817 1050 Sales Representative EVBUM2300 D
6. levels for CLK1 Jumper Levels For a HIGH Level Put Jumper to VDD For a LOW Level Put Jumper to GND For a Mid Level No Jumper or left open This will enable internal pull up and pull down circuits to default to mid level logic FSn pins can also be controlled through the I2C and GUI When controlling FSn pins via EC do not install jumpers on J65 J66 J67 J68 J69 J70 Two Level Input Pins REFMODE SDA SCL PD and MMC The two level input pins can also be controlled with H L jumpers J40 hdr_1x03_ 100 O FS1 Figure 11 FS1 Jumper Setting www onsemi com 9 NB3H5150MNGEVB STEP 4 OUTPUT LEVEL SELECTION FOR EVB The NB3HSISOMNGEVB has the flexibility of two output types LVPECL amp LVCMOS across four output banks Each output channel has the abilitv to drive LVCMOS and LVPECL levels When evaluating LVCMOS CLKnA amp CLKnB are to be used When LVPECL Differential CLK1AB Q aypa O 200 ec Ba e TA 306 0000 00 O evaluating LVPECL the NB3H5ISOMNGEVB has the ability to view signal differentially and single ended The user must determine the output level and the respective CLKnA CLKnB and CLKnAB interface in order to configure the board correctly LVPECL Differential CLK2AB LVCMOS CLK1A CLK1B CLK1AB CLK2AB LVPECL ONLY 91 ON Semiconductor NB3H5150 DEMO BOARD sesasoss 2 B 1 TS
7. rights nor the rights of others SCILLC products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application Buyer shall indemnify and hold SCILLC and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part SCILLC is an Equal Opportunity Affirmative Action Employer This literature is subject to all applicable copyright laws and 16 not for resale in any manner PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT N American Technical Support 800 282 9855 Toll Free ON Semiconductor Website www onsemi com Literature Distribution Center for ON Semiconductor USA Canada 19521 E 32nd Pkwy Aurora Colorado 80011 USA Europe Middle East and Africa Technical Support Order Literature http www onsemi com orderlit Phone 303 675 2175 or 800 344 3860 Toll Free USA Canada Phone 421
8. such as Crystal mounted J64 amp J61 that allows for appropriate configuration on board Crystal Oscillator Sienal Generator or separate Table 3 INPUT CLOCK REFERENCE SETTINGS Signal Generator Position 2 amp 3 Jumpered NOTES To use Crystal Install R71 R72 C31 amp C32 Ci oan Capacitors Remove R69 R70 R31 amp R32 To use XO Install R69 amp R70 Remove R71 R72 R31 amp R32 To use Signal Generator Install R69 R70 R31 8 R32 Remove R71 amp R72 K Bef 08 CLK1AB CLK2AB LVPECk ONLY i ihe 91 an JC ON Semiconductor gt NB3H5150 DEMO BOARD Jumper Position 2 amp 3 LVPECL ONLY L Figure 6 J61 amp J64 Board Location Crystal Input Default Set Up External Clock Source 1 Set REFMODE Low 1 Set REFMODE High 2 Y1 25 MHz crystal is installed 2 Remove R71 amp R72 and C31 amp C32 3 R31 amp R32 are removed R69 amp R70 are not 3 R31 amp R32 must be installed and R69 amp R70 installed must be installed 4 R71 amp R72 and C31 amp C32 are installed crystal 4 R31 amp R32 are 50 Q to GND and are used to load capacitors terminate an external signal generator 5 MCLK XTALI and CLKb_XTAL2 pins are driven by another IC device remove R31 amp R32 www onsemi com 5 NB3H5150MNGEVB EXT_OSC_VDD J OSC VDD VDD OSC VDD HEADER A O R73 DNI J_OSC_OE OE VDD 1 FSEL CLK 3 liem ax OU i B o I C
9. the two separate options C1B2 must be removed as the cap coupled balun Components will either need to be added or removed for will affect the signal at this node Observe the two appropriate configuration The following describes the two single ended LVPECL outputs with Hi Z probe at options to view LVPECL as complementary single ended the nodes below with a high Z probe waveforms ae DNI R1A5 AT CLKIA TX 1 a a a 5 0 pF Gii U100 m 5 CLK1 A amp B 0 OUTPUTS PP ski A 3 0000 l L gt Ls CLK1AB N LVPECL Output CLKnB 835 Use High Z Probe Here VDDO1 DNI RIBS s A IB GND Q 1 4 e CLK1B gt ES 3 DNI 5 0 pF R1B6 CLK1B N ER GND GND Figure 15 LVPECL Outputs Optional Set Up Option 2 The LVPECL outputs can also be monitored by modifying RIAI amp RIBI with 0 42 resistors remove 5 pF install a few board components remove R1A2 amp R1B2 Replace Thevenin resistors RIA5 amp RIA6 and RIBS amp RIB6 VDDOT DNI R1A5 A R1A1 CLK1A gt e WA 1 penal ri se High Z Probe Here yoo TIT s R1B3 83 Q ka 127 RJA2 CLK1 A amp B i OUTPUTS s 144 R4B4 1UF GND 83 5 VDDO1 DNI R1B5 R1B1 GND LVPECL Output CLKnB Use High Z Probe Here CLK1B gt Ti 1270 0 pF CLK1B GND Figure 16 LVPECL Outputs Optional Set Up www onsemi com 12 NB3H5150MNGEVB STEP 5 POWER SEQUENCE FOR EVB The NB3H5150 EVB has the flexibility of being powered by two different metho
10. 0 1 uF Digi Key 445 5942 1 ND C1A2 C1B2 C2A2 10 X5R 0402 C2B2 C3A2 C3B2 C4A2 C4B2 80 111 00219 Cap Chip 18 pF 0402 18 pF Digi Key 478 4435 1 ND 2 031 032 10 V 2 80 111 00031 Cap Chip 1 uF 0603 1 uF SMEC MCCB105KINRT 10 04 06 08 C10 0403 10V 10 X7R C404 C406 C407 C409 CAP CER 0 1 uF 50 V 0 1 Digi Key 490 1519 1 ND 17 C410 10 X7R 0603 Digi Key 80 111 00147 C12 038 039 040 C63 065 C67 C69 C82 C83 C84 C85 C86 C92 C405 C408 C411 GRM1885C1H5ROCZ01D 80 111 00536 5 0 pF C1A1 C1B1 C2A1 C2B1 0341 C3B1 C4A1 0481 Digi Key MOUSER 581 05055C104J 1 IE AW Digi Kev 478 1556 1 ND 3 05 07 09 Digi Key 587 1370 1 ND C64 C66 068 070 071 072 073 074 Cap Chip 5 0 pF 0603 50 V 80 111 00255 Cap Chip 0 1 uF 0805 0 1 uF 50 V 5 X7R 80 111 00796 Cap Cer 1206 50 V 0 1 uF 0 1 uF X7R 10 80 111 00074 Cap Chip 10 uF 1210 10 uF 10 V 10 X5R DNI CAP_DNI_TANTB DN 80 111 00197 Cap Chip 22 uF 22 uF Tant D 25 V 10 NI 1 C3 R39 0805N RES DNI 0805 DN DNI D 1 DNI Res Chip 49 9 2 0402 49 9 62 Digi Kev P49 9LCT ND 2 R31 R32 1 16 W 1 80 114 00163 80 114 01607 Res SMD 3 3 kQ 1 3 3 kQ 1 16 W 0402 Digi Key RHM3 3KCDTR ND 1 Digi Key 311 0 0JRTR ND R40 R71 R72 R2A2 R2B2 R3A2 R3B2 R4A2 R4B2 80 114 00052 Res Chip 0 8 0402 1 16 W 5 o o J DNI Res Chip 0 2 0402 Digi Key 311 0 0JRTR ND
11. 2 R1A2 R1B2 1 16 W 5 0402N RES 0 1 16W_5 _ DNI DNI DNI 2 R69 R70 0402 80 114 00473 Res Chip 33 2 0402 33 Q SMEC RC73L2Z330JT 2 R1A1 R1B1 1 16 W 5 DNI Res Chip 33 Q 0402 33 Q SMEC RC73L2Z330JT R2A1 R2B1 R3A1 1 16 W 5 R3B1 R4A1 R4B1 80 114 01612 127 Q Res SMD 127 Q 1 1 16 W 0402 R1A3 R1B3 R2A3 R2B3 R3A3 R3B3 R4A3 R4B3 Digi Key 541 127LDKR ND l l R1A5 R1A6 R1B5 R1B6 R2A5 R2A6 R2B5 R2B6 R3A5 R3A6 R3B5 R3B6 R4A5 R4A6 R4B5 R4B6 0402S1 RES DNI 0402 DN 80 114 01460 Res 10 kQ 1 10 W 1 10 kQ 0603 SMD Digi Key P10 0OKHCT ND 2 R67 R68 ERA 6AEB820V P82DACT ND Res SMD 82 Q 0 1 0 15 W 0805 80 114 01628 82 5 60 0603 R1A4 R1B4 R2A4 R2B4 R3A4 R3B4 R4A4 R4B4 80 118 00259 IND_FERRITE BEAD_60 600 Q 100 MHz Digi Key 587 1846 1 ND L1 L2 L3 L4 L5 L6 L7 OOHM 100MHZ L8 80 118 00260 TRANSFORMER MABA 007159 Digi Key 1465 1302 1 ND 4 U100 U200 U300 U400 80 080 00330 CONN SMA JACK 50 2 SMA 142 0761 861 Digi Key J805 ND 14 CLK1A CLK1AB CLK1B Digi Key o o EDGE MNT CLK2A CLK2AB CLK2B CLK3A CLK3AB CLK3B CLK4A CLK4AB CLKAB 459 J60 Samtec TSW 150 14 G S 3 J76 J77 J78 80 112 00108 Connector Header HDR 1x01 50 Pos 0 100 DNI Connector Header hdr_1x02_ 100 50 Pos 0 100 Samtec TSW 150 14 G S J65 J66 J67 J68 J69 J70 www onsemi com 19 NB3H5150MNGEVB Table 5 NB3H5150MNGEVB BILL OF MATERIALS continued
12. 58 d aNd 6STL00 VEVIN avexo ra ao Taro S 3 HAT de gt 3 o ZVrO O LO UNO LTI LTI UND N EIVA EVVA e Z vex IVA ad o s ING y e 3 viS Lad rOqqA V gt SVA ING LOG 17000 UNO NO N 99EN ad 06 ING e 2 1862 do T e v sadd INA LAG 6000 SE8 D S ES UNO gnr 7868 41764 e UNO 6STLOO VIVIA N L a de 2 38 LUI LUI GND N CHCA EVEN e Z vero N L V S Lad oqqA do gt 38 S ogra dd o s ING e 1823 I IND 3 Lu KON Saza INGA tad ZOddA S ES S ES qND ant 7808 bvza e UND 6S1 00 V8VIN i e a de EN S 3 UND LTI ZN EITA 4 S f 9VZA S aios B A i i e ada a TYTO i V e svcd INGA Land ZOAAA A ZS ode b ad og ING 18123 I IND 3 2 Sara ING LAC 1oddaA S E8 S ES UND ant FAN ervii UNO 6SILO0 VAVIN E i L mel S do 2 5 3 LTI GND ZN cara 4 ZA wisp 9708 3 aios A N a IVIO E V N Taza EE Ivca tt Tara te IVII 7170 4472 4DITO Y INTO www onsemi com 16 NB3H5150MNGEVB QAVOA ONHU OSTSHE HAN ni oul sonte pods JA lt HAGVAH 8sf END lt AYHUAVHAH LINA AMA asa f OWN O I GONWHda 698 O I 2994 O I ISI O I ano AAQVAH TIOS
13. LVPECK ONLY Qan y L gt gt Se eee D o 14209 REV C e A SPECIALTIES je 1543 4 kao 858 0393 www mms 184 RITA M amp M SPECIALTIES INC Deis WA E MADE IN U S A Cr ie lt Teri e Y gt a S e ISA KOM ma J68 He 9 8 ALA S e s X SY ASIF mis ji i A ver vi E ji 9 ES J Ki gt e u e O r Bottom View Figure 1 NB3H5150MNGEVB Evaluation Board Publication Order Number EVBUM2300 D NB3H5150MNGEVB NB3H5150MNG EVALUATION BOARD BOARD LAYOUT MAP Figures 2 amp 3 illustrate the locations of major features and information in this manual will guide the user how to components of the NB3HS5ISOMNGEVB The proceeding properly configure the NB3H5150 for lab testing LVPECL Differential LVPECL Differential CLK1AB CLK2AB External CLK External CLKb GND VDD LVCMOS CLK1A CLK1B G6 2 08 CLKIAB CLK2AB LVPECL ONLY Com L wi 91 ORAR ON Semiconductor fel NB3H5150 e DEMO BOARD onoi x L LVCMOS CLK2A CLK2B uo in gt e 02 fl Coal b B 76604 R342 ed 00008 ig LVCMOS Hs AN CLK3A CLK3B AS 0044 232H Mini Module mit 0_MMC LVPECL ONLY CLK 3AB lt LVCMOS CLK4A CLK4B USB 12C LVPECL Differential LVPECL Differential Module CLK4AB CLK3AB Figure 2 NB3H5150MNGEVB Top View VDD 40655 5 FI SAUEN E E 2 LT fado SR
14. NB3H5150MNGEVB NB3H5150MNG Evaluation Board User s Manual Introduction The NB3H5150MNGEVB evaluation board was developed to provide a flexible and conventent platform to quickly evaluate and verify the operation of the NB3H5150 This evaluation board manual contains e Information on the NB3H5150 Evaluation Board e Assembly Instructions e Test and Measurement Setup Procedures e Board Schematic and Bill of Materials Board Features e Accommodates the Electrical Evaluation of the NB3H5150 e Incorporates On Board I2C SMBus Interface Module Powered via a USB Connection Minimizing Cabling 25 MHz Crystal is Installed Default Input e Differential Inputs Outputs Signals are Accessed via SMA Connectors or High Impedance Probes LVPECL Outputs are DC Loaded and Terminated Signals then Go through 2 1 Baluns for Direct Connection into Phase Noise Analyzer or High Z Scope LVCMOS Outputs are Series Terminated and Cap Loaded Flexible Power Supply Combinations for Device Operation Pin Strap Mode Frequency Select Jumpers Convenient and Compact Board Layout Board must be configured before powering up This manual should be used in conjunction with the device data sheet which contains full technical details on the device specifications and operation Semiconductor Components Industries LLC 2015 1 November 2015 Rev 1 ON Semiconductor www onsemi com EVAL BOARD USER S MANUAL a L yd 006 o CLKIAB CLK2AB
15. R1A2 0 CLKnA amp B 0 OUTPUTS o 0 6144 9 Rima lUF 835 Y 835 18 GND CLK1B gt gt RIB3 amp R1B4 are Thevenin equivalent DC load and AC termination resistors VDDO1 DNI RIA5 A A C1A1 DNI T50pF GND LVPECL OUTPUTS Through 2 1 Balun GND CLK1B GND GND Figure 14 LVPECL Output Configuration The differential LVPECL outputs are DC loaded and AC terminated with Thevenin resistors capacitor coupled 1010 U100 a 2 1 balun which creates a true differential signal This signal connects directly into a test Instrument primarily a phase noise analyzer an oscilloscope with a high Z probe frequency counter etc NOTES In pin strap mode the NB3H5150 CLK1 defaults to LVCMOS only and CLK2 defaults to LVPECL only Therefore on the EVB remove the appropriate resistors such that CLK1A amp CLK1B defaults to LVCMOS output configuration and the CLK1AB SMA connector is open Figure 13 Use a high Z probe on the two single ended outputs CLK2 defaults to differential LVPECL output configuration Remove the appropriate resistors such that the CLK2AB SMA connector is used and CLK2A amp CLK2B SMA connectors are open Figure 14 www onsemi com 11 NB3H5150MNGEVB LVPECL Complementary Single Ended Output Option 7 Configuration 1 The LVPECL outputs can be observed at the The NB3H5150 EVB has the ability to observe LVPECL Thevenin termination resistors but C1A2 and waveforms single ended using
16. REV af SS fin PECJALTIES pe Hat Crvstal E H so 858 0393 www mmspec co MO SPECIALTIES INC 2015 o MADE IN U S A gt AI o gt gt o o SD JTI J72 a CIA B amp 61 SN don s lt pn s gt A er KU a fi 3 es a ES Y AN r GERA EA gt 0 2 1 Balun x 4 i I i f i A Y TIM n Jn 8 Re l la 120 gt 3 3 V 2 5 V 1 8 V Voltage Regulators Selectable for VDDOn Figure 3 NB3H5150MNGEVB Bottom View www onsemi com 2 NB3H5150MNGEVB STEP 1 POWER SUPPLY FOR EVB The NB3H5150MNGEVB has the flexibilitv to be J USB POWERS DUT that allows for either powered either with an external power supplv or USB configuration module Table 1 describes Jumper Setting When USB Powers DUT VDD 3 3 V Table 1 NB3H5150MNGEVB DUT POWER JUMPER SETTINGS DUT Power J_USB_POWERS_DUT USB I C Module Install Jumper VDDOn J USB POWERS DUT A taj 11 R Rev ESA O 088 Figure 4 J USB POWERS DUT Board Location Power Supplies VDD AVDDI AVDD2 and AVDD3 Power Pins 2 VDD of the demo board using jumpers J71 J72 A single VDD test point connector is connected to the J73 and J74 VDDOn VDD positive power supply and powers each of the VDD and 3 Three selectable regulators 3 3 V U401 2 5 V AVDDn power supply pins U402 and 1 8 V U403 using jumpers J71 J72 J73 and J74 VDDOn VREGULATOR VDDOn Pow
17. SEMI_NB3H5150_SK Q ON Semiconductor T MM 50 000 0 80 080 00337 USB Cable USB A DNI Mini B 1 8M Frost White 80 113 00906 USB Hi Speed FT2232H DNI Evaluation Module NB3H5150 9341 ND 2 88732 8800 1 1 1 1 1 1 1 1 1 1 1 8 1 1 FT2232H Mini Module U U ON Semiconductor and the ON are registered trademarks of Semiconductor Components Industries LLC SCILLC or its subsidiaries in the United States and or other countries SCILLC owns the rights to a number of patents trademarks copyrights trade secrets and other intellectual property A listing of SCILLC s product patent coverage may be accessed at www onsemi com site pdf Patent Marking pdf SCILLC reserves the right to make changes without further notice to any products herein SCILLC makes no warranty representation or guarantee regarding the suitability of 116 products for any particular purpose nor does SCILLC assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation special consequential or incidental damages Typical parameters which may be provided in SCILLC data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts SCILLC does not convey any license under its patent
18. ds external power supply or via USB module connection External Power Supply 1 Connect power supply cables to VCC and GND connectors 2 Configure board according to Steps 1 through 4 3 Turn on VDD power supplv 4 Monitor CLKnA amp CLKnB outputs on oscilloscope or other test instrument Signal Generator OUT OUTb ko iy finta 92 SSA At ON Semiconductor r NB3H5150 USB Power Supply 1 Configure board according to Steps 1 through 4 2 Connect USB cable to I C Module 3 Monitor CLKnA amp CLKnB outputs on oscilloscope or other test instrument When using an external clock source board must be powered first Phase Noise Analvzer LVPECL IN Oscilloscope LVCMOS IN tt Ba CLK1AB CLK2AB LVPECL ONLY DEMO BOARD E amp ME f E E amp 1 ge gt a x LVPECL ONLY 040 paros Figure 17 Power Sequence Diagram Graphical User Interface GUI There is a stand alone Graphical User Interface software package and GUI user s manual that will interface with the DUT via the USB connector USB amp I2C SMBus Interface The NB3H5150 EVB has an on board I C SMBus interface module located in the lower left section of the board This circuitry will interface the device with the GUI software via the SDA and SCL PD input pins The GUI can control the Frequency Select pins output types output enable and PLL ByPass Mode SCL PD amp SDA The SMBus Clock SCL PD and Data SDA pin
19. er Pins VDDOn pins can be powered individually NOTE Figure 5 illustrates VDDOn jumper selection options 1 An external power supply connected through J20 J21 J22 and J23 Remove jumpers J71 J72 J73 and J74 J 1 VDDOI Example VDDO1 Jumper to VDD DDOI REG_V2V5 REG V1Vv8 VDD REG_V3V3 Figure 5 VDDOn Power Supply Options www onsemi com 3 NB3H5150MNGEVB The NB3H5ISOMNGEVB provides three Voltage Regulators which can be used to power each VDDOn separately To power these regulators follow Table 2 for J58 configuration J58 enables the optional on board VDDOn regulators when the device board is powered by an external power supply Table 2 VDDO VOLTAGE REGULATOR POWER e When J58 is open the 3 3 V 2 5 V and 1 8 V regulators for VDDOn are powered by the USB e When J58 is jumpered the 3 3 V 2 5 V and 1 8 V regulators are powered by the external VDD power supply e When VDD 2 5 V VDDOn can not be 3 3 V only 2 5 V or 1 8 V J58 VDDO Voltage Regulator Power VDDOn Voltage Regulator Power USB I2C Module NOTE All four VDDOn pins must be connected to a power supply before power up CAUTION Neglecting Table 2 configurations may cause damage to USB I C module www onsemi com 4 NB3H5150MNGEVB STEP 2 INPUT CLOCK REFERENCE FOR EVB The NB3HSISOMNGEVB has the flexibility to accept clock Integrated circuit Table 3 describes Jumper Settings multiple Input clock references
20. ermination resistor at R31 for a signal generator termination v Remove C31 amp C32 Install R69 amp R70 2 Set REFMODE High 3 Connect Jumpers to J SDAI and J SCLI a This will connect SDA amp SCL PD to GND and set the NB3H5150 in Pin Strap mode 4 Connect the CLKnA and CLKnB outputs to the appropriate test instrument a LE Oscilloscope Phase Noise Analyzer Frequency Counter etc www onsemi com NB3H5150MNGEVB REFMODE When the REFMODE pin is Low it selects a crystal for the Input When the REFMODE pin is High it selects an external differential or single ended clock source for the input For manual control 1 164 a Jumper across pins 2 amp 3 to select manual control of REFMODE and then use J61 2 J61 a 1 amp 2 High VDD For External Clock Source Input b 2 amp 3 Low GND For Crystal Input JE4 REFMODE REFMODE DUT 2 REFMODE DUT_GND Figure 8 REFMODE Jumper Settings www onsemi com 7 NB3H5150MNGEVB STEP 3 PIN STRAP OR I C MODE FOR EVB The NB3HSISOMNGEVB has the flexibility of two module and Software GUI various frequency and level methods of selecting output frequencies and level types types combinations can be generated Table 4 describes Pin Strap selections are limited to those described in data Jumper Settings J_SDA1 JSCLI that allow for appropriate sheet Refer to Tables 3 amp 4 of data sheet for selectable configuration frequencies and levels W
21. f lt THIVHH UNO 001 0XT Py srt A n B Y Lot VrSd gt dda 001 0XT Py Ort v IOGCI E m A so 7 Qoa 001 601 py OST T n ESA ddA 001 0XT py Lagi 00T OXT py crt H x sor ISH dda 001 OXT py Ort CA ID www onsemi com 17 NB3H5150MNGEVB 10 pns 6007 Joquiny Ju umoo LINA 7000 400 7000 2414001 YO 009 ST roads davod OWA OSTSHE AN oul sone pods op 8L LAG EOQQA 400 EOQQA ZUWIO0 1 YO 009 vI OUUA 400 TOQQA 400 TOQQA 2414001 WO 009 I TOQQA 400 IOQQA 400 IOQQA ZuIN001 utuO 009 TI IOQQA ANO SHT Idd 1S diHHMOd NO 602 001 SSO D NIdS AQH 001 SSOAD NIdS zH 001 SSO OD NIdS AQH 001 SSO O NIdS ACH A A DAY A A DAY A A DAY A A DAA 8ATA DAA 8AIA DAA 8AIA DAY 8ATA OTA SATA DAA SATA DAN SATA Dia SATA DAA YLI 400 roada 400 odda 400 TOQQA 400 IOQQA CNO GND GND CNO Or Lad 600 gt LAG AdAV ZUWO01 Wyo 009 2414001 WO 009 2414001 YO 0092014001 utuO 009 81 dda www onsemi com 18 NB3H5150MNGEVB BILL OF MATERIALS Table 5 NB3H5150MNGEVB BILL OF MATERIALS MMJGNA COMP DEVICE TYPE COMP VALUE SOURCE souncr PNA ary REDES 80 111 00666 CAP CER 0 1 uF 50 V
22. hile using IC with provided USB Table 4 PIN STRAP OR EC SETTINGS Pin Strap or I C Mode J PS SDAA SCL amp J_SCL1 Pin Strap Install KA f ee NOTE For I2C Mode Install the USB I C module and power up with cable from PC when VDD 3 3 V YD 00 oo CLKIAB CLKZAB LVPECL ONLY Cae ih EL hhh 91 o N g G VOD AVODIA OSM ON Semiconductor fp NB3H5150 DEMO BOARD 0 MMC LVPECL ONI Y a LK4AB CLK3AB ge b noe 9 ie g A e G 4 gt 169 paros PR IV 3s J50 l e UT a pa l l K Figure 9 J_SDA J_SCL Board Location Pin Strap Operation 1 Connect a jumper across J SDAI and J SCLI a This will connect both SDA and SCL PD pins to GND J_SDA1 SDA I C Operation 1 Remove jumpers from J_SDA 1 and J SCLI a The powered I2C module will then connect both SDA and SCL PD pins to VDD via pull up resistors DUT_GND HEADER 2 Figure 10 SDA and SCL PD Jumper www onsemi com 8 NB3H5150MNGEVB Control Pins Each control pin can be managed manually with H L Jumper header H VDD L GND Tri Level Input Pins FSn Frequency Select pins for CLKn The five tri level input pins FS1 FS2 FS3 FS4A and FS4B have selectable levels Reference Tables 3 amp 4 of NB3H5150 data sheet for pin strap frequency settings The logic levels for the FSn pins can be selected manually by using respective Jumpers Figure 11 is an example of control pin FSI controlling logic
23. s are exercised through the on board EC interface In order to enable the IC control of the DUT see Step 3 The I2C SMBus interface circuitry is powered separately from the USB type B connection and is isolated from the device VDD and VDDOn The SDA and SCL PD pins can also be externally accessed by an off board programmer allowing other SMBus emulators to be used to program the DUT Test point anvils TPS amp TP6 are available for external control of the device with the use with mini grabber cables www onsemi com 13 NB3H5150MNGEVB Graphical User Interface Set Up 1 Connect the USB port on the evaluation board to Alllayers are constructed with FR4 dielectric material a USB port via PC cable Layer Stack 2 See the stand alone GUI Instructions document e LI Top Signal 3 Allow Windows to install the necessary drivers for e 12 Ground the evaluation board USB interface hardware e Ta Powe 4 Start the GUI program e LA Power Board Layout e L5 Ground The NB3H5150 QFN 32 Evaluation Board provides e L6 Bottom Signal a high bandwidth 50 2 controlled trace impedance environment 100 92 line to line differential and is implemented in six layers STACKUP 6 LAYERS IMPEDANCE Layer Layer Thickness Q Line Number Name Inches Material 5 Width 50 0 0080 rec Cf 1 2 60000 0000 rra ma Pw 0002 Cope 2 60000 aoust FRA a Pw 0002
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