processor overview
Contents
1. Nios Processing Unit e Pipelined RISC architecture e Single issue 5 stage pipeline e Harvard architecture e Instruction set contains arithmetic and logical operations bit operations byte extraction data movement control flow modification conditionally executed instructions e Registers gt 128 256 or 512 registers gt Register width width of CPU data path gt 32 register sliding window with granularity gt Register file behaves like a stack gt CWP Current Window Pointer Manager routine handles details of manipulating register file during subroutine calls Several machine control registers Program counter K register used for instruction prefixing VVVVVV 16 register VV V 8 13 32 bit softcore CPU Multiplier e 3 types of multipliers gt software implementation gt MSTEP hardware implementation gt full 16x16bit hardware Option Additional LEs Used Clock Cycles 16x16 gt 32 Clock Cycles 32x32 gt 32 e Floating point unit gt software implementation gt full implementation in the future Custom Instructions e Custom instruction logic extends Nios instruction set e Accelerates software algorithms reduces number of operations for inner loop tasks to a single cycle e Single cycle combinatorial or multi cycle sequential Interrupt Service Routine Handler e Up to 64 prioritized vectored interrupts e 16 interrupt are reserved for system services2. Area lt 0 5 mm 0 18u 6LM cache memories not included Target Applications e Internet networking and telecom applications e Embedded applications e Portable and wireless applications e Home entertainment consumer electronics e Automotive applications Utilization Synthesis results for Xilinx devices with Synplify MODEL Speed Compilation Grade time Virtex 1000E 6 2819 SLICES 21 MHz 95s 7m30s Virtex 1000E 8 2900 SLICES 22 MHz 129s 6m03s VirtexII Pro 7 5 2387 SLICES 38 MHz 125s 4m43s VirtexII Pro 7 7 2460 SLICES 47 MHz 117s 34m34s Spartan 2E 600 6 2960 SLICES 19 MHz 109s 4m3s Spartan 2E 600 7 2960 SLICES 24 MHz 113s 6m48s Virtex II 1000 4 2382 SLICES 32 MHz 89s 7m49s Virtex II 1000 6 2387 SLICES 43 MHz 112s 9m10s Size Speed References e Original overview by OpenRISC Team e Synthesis results by Tom Tierens amp Dries Driessens De Nayer Instituut 11 13 Xilinx Virtex II PRO Introduction The Virtex II Pro architecture uses the PowerPC 405D5 processor core which is a 32 bit high performance low power scalar RISC architecture using separate data and instruction Harvard architecture cache It is a 0 13 micron hard implementation of the area optimized 0 18 micron IBM PowerPC 405D4 core used in the IBM Blue Logic core library Integration of the PowerPC core into the Virtex II Pro device is accomplished b
3. the GDB Tcl debuggers e Allows debugging on a cycle accurate MicroBlaze instruction set simulator ISS e Allows debugging of a MicroBlaze running XMDstub on a hardware board 6 13 32 bit softcore CPU External memory controller EMC Supports up to 8 memory flash SRAM banks Separate control register for each bank Supports 8 16 32 and 64 bits bus interface Supports memory width of 8 16 32 and 64 bits Memory width is independent of OPB bus width Configurable wait states for read write read in page read recovery before write and write recovery before read e Optional faster access for in page read accesses page size 8 bytes Timer counter e Two 32 bit programmable interval timers with interrupt compare and capture capabilities e One Pulse Width Modulation PWM output e Watch Dog Timer WDT with selectable timeout period and interrupt e Supports 8 16 and 32 bit bus interfaces Interrupt controller e Number of interrupts inputs is configurable up to the width of the data bus e can be easily cascaded to provide additional interrupt inputs e Programmer interface similar to Virtex II Pro interrupt controller IP IntC e Master Enable Register for disabling the interrupt request output e Supports data bus widths of 8 16 and 32 bits UART Lite e 1 Transmit and 1 Receive channel full duplex e 16 character transmit FIFO and 16 character receive FIFO e Number of databits baud rate is configu
4. 160 OPB DDR Controller 370 OPB SDRAM Controller 250 OPB 10 100M Ethernet w DMA amp SG 3760 OPB 10 100M Ethernet Lite Full Duplex 530 OPB 10 100M Ethernet Lite Half Duplex 567 OPB to PCI Full Bridge 32 33 w IDMA amp SG 2900 OPB ATM Utopia Level 2 Slave w DMA amp SC 3120 OPB ATM Utopia Level 2 Master wDMA amp SC 3210 OPB Single Channel HDLC w DMA amp SG 2614 OPB 12C M amp S 440 OPB SPI M amp S w Rx amp Tx FIFOs 350 IPIF Interrupt Control 16 Interrupt MAX impl 92 OPB Interrupt Controller 32 Interrupts MAX impl 332 OPB UART Lite or JTAG 110 OPB Timebase WDT 63 OPB Timer Counter 255 OPB GPIO 11 0 8 OPB GPIO 8 I Os 16 OPB GPIO 16 I Os 32 OPB GPIO 32 I Os 48 Performance Device Family Speed Performance Logic Cells Virtex ll Pro 6 150 MHz 102 D MIPS 900 Virtex Il 5 125 MHz 82 D MIPS 900 Virtex E 7 75 MHz 49 D MIPS 1050 Spartan llE 7 75 MHz 49 D MIPS 1050 Spartan ll 6 65 MHz 43 D MIPS 1050 Technology Area Timing Spartan 2300 6 684 slices 66MHz Spartan 2 amp 300 7 684 slices 72MHz Virtex 1000 4 685 slices 54MHz Virtex 1000 6 685 slices 64MHz Virtex 2 1000 4 627 106MHz Virtex 2 1000 6 627 135MHz Virtex 2 Pro 7 5 626 slices 124MHz Virtex 2 Pro 7 7 626 slices 154MHz 7 13 without off chip memory Links References http www xilinx com http ucos ii com contents products ucos ii p
5. C 405 processor e soft bus comprising gt high speed PLB processor local bus gt general purpose OPB on chip peripheral bus gt control oriented DCR device control register e IBM CoreConnect bus is available as a no fee no royalty license Timer e 64 bit time base e contains 3 timers gt programmable interval timer PIT gt fixed interval timer FIT gt watchdog timer WDT Expandability e growing library of basic peripheral IP is available UART memory controllers Fast Ethernet MAC Gigabit Ethernet MAC Utopia Level 2 C SPI master some free most of them not e All peripheral IP cores interface to the high speed PLB or general purpose OPB of the CoreConnect bus OPB peripherals are also compatible with the Xilinx MicroBlaze soft processor Xilinx Platform Studio XPS e Peripherals may be selected and integrated e Integrates synthesis simulation and debugging into one tool Synthesis e Netlist in 2 ways Flat or Hierarchical e Hierarchical 2 Implementation Tool Flows e XPS 4 synthesis tools available XST Leonardo FPGA Compiler II and Synplify e Xilinx ISE e Flat only XPS Debugging e external debug mode by JTAG debuggers e Internal debug mode for use by ROM monitors and software debuggers e debug wait mode which allows the servicing of interrupts while the processor appears to be stopped e real time trace mode which supports event triggering for real time tracing e X
6. HOGESCHOOL VOOR WETENSCHAP amp KUNST DE NAYER INSTITUUT DE NAYER Instituut J De Nayerlaan 5 B 2860 Sint Katelijne Waver Tel 015 31 69 44 Fax 015 31 74 53 e mail ppe denayer wenk be ddr denayer wenk be tti denayer wenk be website emsys denayer wenk be OVERVIEW EXCALIBUR LEON MICROBLAZE NIOS OPENRISC VIRTEX II PRO Version 1 1 HOBU Fonds Project IWT 020079 Titel f Embedded Systeemontwerp op basis van Soft en Hardcore FPGA s Projectleider Ing Patrick Pelgrims Auteur Ing Dries Driessens Ing Tom Tierens Copyright c 2003 by Patrick Pelgrims Tom Tierens and Dries Driessens This material may be distributed only subject to the terms and conditions set forth in the Open Publication License v1 0 or later the latest version is presently available at http www opencontent org openpub ARM922T Altera EXCALIBUR Introduction Excalibur devices integrate a 200 MHz 32 bit ARM922T processor on chip SRAM SDRAM controller and several other peripherals with the APEX 20KE FPGA architecture balancing the price performance and system integration requirements of system on a programmable chip SOPC designs The microprocessor subsystem is implemented as an embedded stripe next to the FPGA stripe Specifications BA PLD to Stripe Bridge t Peripherals AHB 2 PLO AHB 1 OEA Caches MMU SRAM Soran Control PLD to Stripe B
7. PGA 2 SDRAM controllers for in total 128MB Synthesis tool Speed Area Power consumption SOPC Builder Quartus 40MHz 4663 LE 551mA 5V Leonardo Spectrum 40MHz 4580 LE 420mA 5V Synplify 40MHz 4123 LE 450mA 5V gt Remark the difference in power 100mA gt Low level architecture specific stuff had to be left out gt Is probably the cause of this huge difference 2 Target Comparison e Full featured Nios e Simple UART e 1kB GERMS monitor on chip ROM e 8kB on chip RAM Target Grade Tool Size Speed Time Apex20KE 2X Quartus 3804LE 58MHz 9m14s 1000 Synplify 83634LE 55MHz 94s 7m19s 1X Synplify 3632LE 60MHz 104s 7m11 s Apex Il 25 7 Quartus 2420LE 100 MHz 5m31s Synplify 2389LE 98MHz 74s 5m36s 9 Synplify 2400LE 71MHz 90s 4m50s Cyclone 12 6 Synplify 3472LE 120MHz 72s 4m42s 8 Synplify 3697LE 94MHz 65s 5m00s Stratix 10 5 Synplify 3339LE 123MHz_ 72s 4m12s 7 Synplify 3115LE 97MHz 65s 4m12s License e Free evaluation version for Quartus subscribers e OpenCore Plus license one hour time limit e Full Nios in Nios development kit e No fees or royalties for your shipped products Nios 3 0 Enhanced debugging possibilities 1 bit DAC PWM Links Input capture event counter Floating point unit High performance revision SDRAM memory contro
8. Spartan 2E 600 6 4824 SLICES 33 MHz Xilinx Spartan 2E 600 7 4824 SLICES 40 MHz The area in the table reflects the complete leon 2 1 0 10 cache internal PROM with 8KB on chip AHB RAM DSU and SRAM controller Performance Using 4k 4k caches and a 16x16 multiplier the Dhrystone 2 1 benchmark reports 1550 iterations s MHz this translates to roughly 0 85 dhrystone MIPS MHz using the VAX 11 780 value Configurations with mul div and larger caches usually perform somewhat better Implementation results Technology Timing Dhryst MIPS RAM Cache kB Isec i d Xilinx VirtexE 1000E 6 25MHz 35600 21 SRAM 16 8 Altera APEX20k200 2X oe MHz 11000 7 SRAM 2 2 8 bit memory bus Altera APEX20k200 2X oe MHz 37151 21 SRAM 2 2 16 bit memory bus Altera APEX20k200 2X 6 MHz 37267 21 SRAM 2 2 32 bit memory bus Altera APEX20k1000E 2X 20MHz 5165 4 SDRAM 6 8 Xilinx Virtex 116000 5 40MHz 45977 27 SRAM 4 4 using the dhrystone 2 1 benchmark Links References http www gaisler com http www leox org http groups yahoo com group leon_sparc http groups yahoo com group leon_dev http www sun com processors communitysource LEON 2 Processor User s Manual Version 1 0 10 Xilinx MicroBlaze Introduction The MicroBlaze is a 32 bit soft processor developed by Xilinx It features a RISC architecture with Harva
9. The timer unit implements gt two 24 bit timers gt one 24 bit watchdog timer e Shared 10 bit prescaler value Interrupt controller e 15 maskable interrupt sources e two interrupt priorities e optional chained interrupt controller providing 32 additional interrupts System interface e Full implementation of AMBA AHB and APB buses V2 0 e All provided peripherals use the AMBA AHB APB interface making it easy to implement more of them or using them as an example Parallel I O port e 32 bit I O port gt 16 bit shared with memory bus gt 16 bit individually programmable Synthesis e the VHDL model is fully synthesisable e synthesis scripts available for gt Exemplar Leonardo gt Synopsys FPGA compiler gt Synopsys DC gt Synplify Simulation e a generic testbench and test program is available including support files for gt Synopsys VSS gt Modelsim Operating system support e eCos port available e uCLinux port under developement Development tools support e LECCS cross compiler system free GNU C C compiler gcc 2 95 2 Linker assembler archiver etc binutils 2 11 Standalone C library Cygnus newlib 1 8 2 RTEMS real time kernel rtems 4 5 0 Boot prom utility mkprom GNU debugger with Tk front end DDD graphical user interace for gdb Remote target monitor rdbmon DSU monitor dsumon e TSIM architectural simulator licensed VVVVVVVV V License e Leon model available un
10. ache D Cache j j Low Speed Peripherals PLB OPB Bridge CoreConnect Processor Local Bus PLB _ PLB Atbiter User Logic Memory Controller High Speed Peripherals Xilinx Soft IP External Memory Copyright c 2003 by Patrick Pelgrims Tom Tierens and Dries Driessens This material may be distributed only subject to the terms and conditions set forth in the Open Publication License v1 0 or later the latest version is presently available at http Awww opencontent org openpub 13 13
11. duction The LEON VHDL model implements a fully synthesisable 32 bit processor with an instruction set according to the IEEE 1754 SPARC V8 standard The processor was initially developed by Jiri Gaisler while working for the European Space agency ESA Gaisler Research is now maintaining and further enhancing the model under ESA contract The LEON is designed for embedded applications the implementation is focused on portability and low complexity Specifications The LEON SPARC consists of several modular units Debug a seria Link 7 LEON processor Integer unit Debug Support Unit H l Cache D Cache AHB interface AMBA AHB AHB Controller Timers InqCte Memory AHBIAPB Controller UARTS 1 0 port Bridge AMBA APB I 8 16 22 bits memory bus PROM vo SRAM SDRAM Integer unit IU e 32 bit RISC architecture implementing the IEEE 1754 standard SPARC V8 instruction set including all multiply and divide instructions 5 stage instruction pipeline 8 global registers 2 32 register windows of 16 registers each configurable multiplier 32 bit instructions 16x16 bit MAC with 40 bit accumulator non restoring Radix 2 divider Custom and optional units e direct interface to the MEIKO FPU which is part of SUN s Micro Sparc availab
12. e 48 interrupt vectors for user applications Memory e 8 16 or 32 bit on and off chip memory e On chip memory embedded system blocks ESBs e Off chip memory active serial memory interface SDRAM SSRAM flash and SRAM controllers e Any user defined interface may be created to connect other off chip memory devices Avalon Bus e Simultaneous access to memory resources for the Nios embedded CPU together with high bandwidth peripherals e Nios only traffic management tasks e Slave side arbritation Simulation e Simulation with Modelsim e SOPC Builder creates project files for Modelsim GERMS e Mnemonic for minimal command set of monitor program gt Go run a program gt Erase flash gt Relocate next download gt Memory set and dump gt Send S records e Also contains software routines for writing to and erasing Advanced Micro Devices AMD flash devices e Connection via UART GNU Debugger GDB e Requires special hardware components e Starts programs and specifies anything that might affect its behavior Stops programs based on a set of specific conditions Examines what happened once programs stop Changes programs to fix bugs and continue testing Supports programs written in assembly C or C Especially commercial operating systems Nucleus Plus real time OS from Accelerated Tech NORTIi CE uITRON compliant real time OS The wClinux kit from Microtronix uC OS II a real time multita
13. errupt sources e two interrupt priorities Custom and Optional Units e Additional units such as a floating point unit can be added as standard units e 8 custom units can be added and controlled through special purpose registers or customer instructions Development Tools Support e GNU ANSIC C Java and Fortran compilers e GNU debugger linker assembler and utilities e Architectural simulator Operating System Support e Linux e uClinux e OAR RTEMS real time OS e Leading 3rd party products such as Windows CE and VxWorks are planned to be available License OpenRISC is available under the GNU LGPL license Specifications 250 MHz in worst case 0 18u 6LM System Interface e System interface optimized for system on chip applications e Low latency open standard dual WISHBONE interface e Dual interface simultaneous flow of instructions and data e Variety of peripheral cores optimized for transparent interconnection with the OpenRISC 1200 Support e OpenCores community e OpenRISC forum General Description The OpenRISC 1200 Processor Core is ideally suited for applications that require 32 bit performance compared to performance of 16 bit processors and need low cost and low power consumption advantage compared to 64 bit processors e 250 MIPS Dhrystone 2 1 250MHz we e 250 MMAC operations 250MHz we lt 1W 250MHz 0 18u full throttle est e lt 500mW 250MHz 0 18u half throttle est e
14. ic internal interrupt response Thirty two 32 bit general purpose registers DSP MAC 32x32 Custom user instructions L1 Caches e Harvard model with split instruction and data cache e Instruction data cache size scalable from 1KB to 64KB e Physically tagged and addressed e Cache management special purpose registers Memory Management Unit Harvard model with split instruction and data MMU Instruction data TLB size scalable from 16 to 256 entries Direct mapped hash based TLB Linear address space with 32 bit virtual address and physical address from 24 to 32 bits e Page size 8KB with per page attributes 10 13 32 bit softcore CPU Sophisticated Power Management Unit e Software controlled clock frequency in slow and idle modes power reduction from 2x to 100x e Interrupt wake up in doze and sleep modes e Dynamic clock gating for individual units Advanced Debug Unit e Conventional target debug agent with a debug exception handler e Non intrusive debug trace for both RISC and system e Real time trace of RISC and system e Access and control of debug unit from RISC or via development interface e Complex chained watchpoint and breakpoint conditions Integrated Tick Timer e Task scheduling and precise time measuring Maximum timer range of 2432 clock cycles Maskable tick timer interrupt Single run restartable or continuous mode Programmable Interrupt Controller e 2non maskable interrupt sources e 30 maskable int
15. ilinx ChipScope Pro provides powerful in system logic analyzer ILA and in system bus analyzer IBA capabilities e Wind River Xilinx edition Embedded Tools gt Singlestep Debugger gt Diab C C Compiler gt VisionPROBE II target connection Simulation Operating Systems e 2 simulation methods e NetBSD from Wasabi gt CPU SMART model for complete simulation with e VxWorks realtime OS from Wind River Systems accurate execution of binary images of the software e Linux embedded OS from MontaVista gt Bus Functional Models BFM to verify each of the peripherals attached to the bus individually or as a Performance whole without executing software code requires e system frequency of at least 300 MHz Coreconnect software e more than 420 Dhrystone MIPS e 3rd party tools gt Riviera Elite multiplatform design and verification References solution and Active HDL from Aldec e Virtex II Pro The Platform for Programmable systems gt CoSimple hardware software co simulation from PowerPC Processor Reference Guide e Endeavor i e PowerPC 405 Block Reference Guide gt Seamless hardware software co verification fae www xilinx com solution from Mentor Graphics FPGA FPGA Block RAM Block RAM t 4 OCM Controllers Peripherals with t t Device Registers A CoreConnect Device Control Register Bus DCR PowerPC 3 Blin CoreConnect On Chip Peripheral Bus OPB gt _ 0PB Arbiter I C
16. le under the Sun s Community licensing SCSL e An open source IEEE 754 FPU exists but is still incomplete e general interface to connect to other floating point units custom units allowing parallel or sequential execution with the IU Cache e Harvard model with split instruction and data e Instruction data cache size scalable from 1KB to 64KB e Direct mapped or multi set cache with set associativity of 2 4 e Cache lines with 8 32 bytes of data e Supporting 3 replacement policies least recently used least recently replaced and pseudo random e Data cache can perform bus snooping on AHB bus 4 13 32 bit softcore CPU Debug support unit DSU e Optional no impact on performance e Non intrusive debugging on target hardware us e Seamless connection to gdb allowing on chip debugging e Allows insertion of data and instruction watchpoints and access to all on chip registers from a remote debugger e Trace buffer to trace executed instruction flow and or AHB bus traffic e Communication to DSU using a dedicated UART Memory controller e Direct interface to gt PROM gt SRAM gt memory mapped I O devices gt SDRAM supports up to two banks of PC100 PC133 compatible devices e 2 Gbyte address space e memory areas can be programmed to 8 16 32 bit data width SDRAM supports only 32 bit Power management e Power down mode supported effective halt of integer unit wake up on interrupt Timer unit e
17. ller Streaming parallel output http www altera com products devices nios nio index html http www altera com literature lit nio html References e Nios Soft Core Embedded Processor datasheet e Nios Software Development Reference Manual e Nios 32 Bit Programmer s Reference Manual e News amp Views 2Q 2000 4Q 2001 1Q 3Q 2000 OpenRISC 1200 RISC DSP Core Introduction The OpenRISC 1000 architecture is the latest in the development of modern open architectures and the base for a family of 32 and 64 bit RISC DSP processors Open architecture allows a spectrum of chip and system implementations at a variety of price performance points for a range of applications Designed with emphasis on performance simplicity low power consumption scalability and versatility it targets medium and high performance networking portable embedded and automotive applications Specifications The OpenRISC 1200 RISC DSP Core consists of several modular units System VF System VF PM POWERM IMMU DB eal DEBUG eal DCache 8KB TICK TIMER CPU DSP INT ommu High Performance 32 Bit CPU DSP e 32 bit architecture implementing ORBIS32 instruction set e Scalar single issue 5 stage pipeline delivering sustained throughput Single cycle instruction execution on most instructions 250 MIPS performance 250MHz worstcase conditions Predictable execution rate for hard real time applications Fast and determinist
18. nder GNU LGPL e Files and testbenches under GNU GPL Support e good updated manual e Gaisler research e e group Area used FPGA APEX20K1000E 1X module size Leon cache DSU 8186 LE HW mul Div Scycle 1635 LE SDRAM ctrlr 594 LE MEIKO FPU 6151 LE Facts amp figures Technology Area Timing Atmel 0 18 CMOS std cell_ 35K gates RAM 165 MHz pre layout Atmel 0 25 CMOS std cell_ 33K gates RAM 140 MHz pre layout UMC 0 25 CMOS std cell 35K gates RAM 130 MHz pre layout Atmel 0 35 CMOS std cell_ 2mm2 RAM 65 MHz pre layout Xilinx XC2V500 6 4800 LUT block RAM 65 MHz post layout Altera 20K200C 7 5700 LCELLs EAB RAM 49 MHz post layout Actel AX1000 3 7600 cells RAM 48 MHz post layout 5 13 The area in the table reflects the complete LEON 1 2 3 3 with on chip peripherals and memory controller Technology Area Timing Altera APEX20K1000E 1X 8186 LE 36 MHz Altera APEX20K1000E 2X 8189 LE 32 MHz Altera APEX II 25 7 8219 LE 51 MHz Altera APEX II 25 9 8234 LE 36 MHz Altera Cyclone 20 6 14669 LE 43 MHz Altera Cyclone 20 9 14669 LE 42 MHz Altera Stratix 20 5 15708 LE 65 MHz Altera Stratix 20 7 15708 LE 49 MHz Xilinx Virtex 1000 4 4177 SLICES 19 MHz Xilinx Virtex 1000 6 4166 SLICES 24 MHz Xilinx Virtex 2 PRO 7 5 4081 SLICES 59 MHz Xilinx Virtex 2 PRO 7 7 4092 SLICES 69 MHz Xilinx
19. ngle port SRAM up to 256 KB internal dual port SRAM up to 128 KB internal SDRAM controller gt supports single data rate SDR and double data rate DDR gt upto512 MB gt Data rates to 133 266 MHz Expansion Bus Interface EBI gt Compatible with industry standard flash memory SRAM and peripheral devices gt Four devices each up to 32 MB Bus architecture uses 2 AMBA V2 0 processor busses AHB1 and AHB2 each bus has 32 bit address read and write buses ARM designed high performance bus standard that is optimized for high speed cache interfaces AHB1 runs at the processor speed up to 200 MHz single master bus AHB2 serves as the peripheral bus runs at one half of the AHB frequency multi master bus Timer e general purpose dual channel timer gt 32 bit timer register gt 32 bit clock pre scaler gt 3 operating modes free running interrupt interval timer one shot interrupt watchdog timer Interrupt controller e provides a simple flexible interrupt system e upto 17 interrupt sources gt 10 interrupts from modules within the embedded stripe gt 1 external interrupt source gt 6 interrupts from the PLD stripe can be treated as a bus Extended programmable on chip peripherals embedded stripe PLLS universal asynchronous receiver transmitter UART general purpose I O port e ETM9 embedded trace module to assist software debugging Debugging e SignalTap embedded logic analy
20. orts html Altera NIOS Introduction The Nios embedded processor is a soft core CPU introduced in 2000 optimized for Altera programmable logic devices and system on a programmable chip SOPC integration It is a configurable 16 or 32 bit general purpose RISC processor with a single issued 5 stage pipelined Harvard architecture and a compiler friendly instruction set The principal features of this instruction set architecture are a large windowed register file 16bit instructions for both versions powerful addressing modes and easy extensibility The Nios can easily be configured using the Altera s SOPC Builder which automatically generates arbiters for all include peripherals and user logic The SOPC Builder includes also several peripherals including a UART timer PIO SPI S SRAM SDRAM Flash DMA PWM and IDE All these peripherals connect to the Avalon bus of the Nios The Nios kit also comes shipped together with Redhat s GNUPro toolkit It includes a compiler an assembler a debugger and several utilities Additional development kits support pClinux Ethernet and on chip debugging with tracing Specifications System Module User PCI_ctrl e H logic lt PCiaddr RR 3 PIO H area Signals PCI_dala ki a Signals to s to off chip Nios a Custom on chip devices CPU S peripherall vser g logic off chip x memory stom peripheral Altera PLD
21. rable e Supports 8 bit bus interfaces System interface e OPB V2 0 bus interface with byte enable support e OPB Arbitration gt arbitrates between 1 16 OPB Masters gt arbitration priorities among masters programmable via register write gt priority arbitration mode configurable via a design parameter Fixed priority arbitration with processor access to read write Priority Registers Dynamic priority arbitration implementing a true least recent used LRU algorithm gt Two bus parking modes selectable via Control Register write park on selected OPB master park on last OPB master which was granted OPB access gt Watchdog timer which asserts the OPB time out signal if a slave response is not detected with 16 cycles GPIO e Each GPIO bit dynamically programmable as input or output e Number of GPIO bits configurable up to size of data bus interface e Can be configured as inputs only to reduce resource utilisation e Supports 8 16 and 32 bit bus interfaces Synthesis e Xilinx Platform Studio XPS e Netlist in 2 ways Flat or Hierarchical e Hierarchical 2 Implementation Tool Flows e XPS 4 synthesis tools available XST Leonardo FPGA Compiler II and Synplify e Xilinx ISE Best area and speed results more than 300 faster and more than 30 smaller designs e Flat only XPS Simulation e XMD includes SimGen Simulation Generator e Generates automatically simulation models for MicroBlaze and IP
22. rd model separate data and instruction busses The MicroBlaze is designed for building complex systems for networking telecommunication data communication embedded and consumer applications Specifications The MicroBlaze consists of several modular units All peripherals mentioned below come with a OPB V2 0 bus interface with byte enable support a TY ns Machine Status Reg g r31 SS On Chip Rogister Filo Data 32 x 32bit On Chip instruction Memory 0 256KB Program Counter pm x Momory ri 0 256KB Control Unit g ag rO p a E instruction Buffer car y Subtract Muttpiy so onUSD sng uogonasuj JOORUCD sng seg Watohdog General Timer Timer Purpose I O Counters Processor e True 32 bit RISC architecture implementing the MicroBlaze instruction set architecture ISA 32 x 32 bit general purpose registers 1 instruction per cycle 3 stage pipeline Uses hardware multiplier if available 32 bit instruction words gt type A two source and one destination operand gt type B 1 source and one immediate operand e Harvard architecture implementing separate instruction and data bus e Memory access possible trough gt local memory bus LMB for fast on chip BRAM maximum 2 x 256kB gt on chip peripheral bus OPB e No support for custom instructions e No interface for co processors e g FPU e No cache Xilinx Microprocessor debugger XMD e Program that facilitates a unified interface to
23. ridge PLD Slave EBI l SDRAM Flash Memory Processor e ARM9TDMI processor core with 32 bit Harvard architecture ARM V4T instruction set 32 bit load and store instruction set Instruction set supports 16 and 8 bit memories 5 stage pipeline supports little amp big endian modes task identifier register for real time operating system RTOS support PLD re configuration possible via the embedded processor software 32x8bit hardware multiplier no hardware divider no FPU Cache 8 KB instruction cache 8 KB data cache 8 word line length one valid bit two dirty bits allowing half word write backs selectable pseudo random or round robin replacement independently lockable caches with granularity of 1 64 of cache four word write buffer with 4 addresses virtually addressed 64 way set associative cache write trough and write back cache operation supported Master DPRAM Interface 2 13 32 bit hardcore CPU MMU standard ARMv4 MMU mapping sizes domains and access protection scheme provides translation and access permission checks for instruction and data addresses fully configurable memory map mapping sizes are 1MB sections 64KB large pages 4KB small pages and 1KB tiny pages 16 domains implemented in hardware 64 entry instruction Transfer Look aside Buffer TLB and 64 entry data TLB hardware page table walks round robin replacement algorithm cyclic Memory support internal si
24. s e Generates ModelSim DO file e Behavioral Structural or Timing simulation models Platform Tailoring Utilities e Platform Generator gt tailors each bus component gt generates a custom e Library Generator gt customised device drivers gt software function libraries for the given user defined hardware processor system generated by Platform Generator Operating system support e uC OS II RTOS port under development Development tools support e Xilinx software integrated development environment which creates software like device drivers standard C libraries that matches the selected hardware e GNU C compiler tools including compiler assembler debugger Facts amp figures The following synthesis results were obtained with Xilinx ISE and its integrated XST synthesis The Microblaze system is a simple system with 4kB on chip RAM a jtag uart and some GPIO pins Area Following estimated Logic Cells were calculated with the Field Programmable Controller Calculator This is an online tool that calculates MicroBlaze IP core size usage in Spartan IIE devices module Logic Cells IPIF DMA 1 Channel 463 IPIF DMA 2 Channel 875 OPB EMC Flash SRAM and ZBT 1 Mem Device 200 OPB EMC Flash SRAM and ZBT 2 Mem Device 240 OPB EMC Flash SRAM and ZBT 8 Mem Device 280 OPB BRAM Controller
25. sking kernel from Micrium KROS a POSIX compliant OS from Shuygo Design o e Expandability e SOPC Builder has interface to user logic wizard e Free AMBA bridges SOPC Builder ready cores can be evaluated Component Type LE ESB Nios 32 bit Minimum 1290 5 Standard 1500 9 Maximum 2025 16 Nios 16 bit Minimum 950 3 Standard 1140 5 Maximum 1270 8 Debug HW breakpoint 530 0 ext Trace buffer 300 0 UART No Par 8bit 170 J0 PIO input 2 bit 0 output 1 bit 0 input output 3 bit 0 bidir Tri state 3 bit 0 TIMER full 232 0 simple 100 JO watchdog 103 0 LE Logic Element ESB Embedded System Block ramblock SOPC Builder e From concept to system in minutes e Automatic bus connections interrupt numbering and memory ranges e Changes to any memory interrupt number or clock frequency automatically reconfigures all other necessary settings Synthesis e In Quartus as a block e VHDL Nios system with any synthesis tool Performance e Full 16x16bit hardware multiplier and SDRAM e 0 2 dhrystone MIPS MHz Speed 1 Dhrystones 2 1 Dhyrstones 20MHz 8300 6300 40MHz 17000 13000 9 13 Facts amp Figures 1 Synthesis Comparison On chip ROM 2 simple UARTS 2 simple timers Some GPIO pins Full featured Nios 1kB GERMS monitor 16kB on chip RAM APEX20KE1000 2X F
26. y taking advantage of the IP Immersion architecture which allows hard IP cores to be diffused at any coordinate within the Platform FPGA fabric while maintaining unprecedented connectivity with the surrounding Configurable Logic Block CLB array Specifications Processing unit e embedded 400 MHz 600 D MIPS RISC core e implements PowerPC User Instruction Set architecture UISA e 5 stage data path pipeline with single cycle execution of most instructions including loads and stores 32 x 32 bit general purpose registers 32 bit Harvard architecture 8x32bit hardware multiplier hardware divider 35 cycle no FPU Cache e 16 KB 2 way set associative instruction cache e 16 KB 2 way set associative data cache write back write through e separate processor local bus PLB master interface for instruction and data cache e non blocking caches e least recently used LRU replacement policy e 32 byte cachelines MMU e 4GB of flat non segmented address space e 64 entry unified address Translation Look aside Buffers TLB e variable page sizes 1KB 16 KB e protection functions using zones e supports demand paged virtual memory Memory e dedicated On Chip Memory OCM interface no peripheral bus required e external memory can be accessed using peripheral IP cores 12 13 32 bit hardcore CPU Bus architecture e supports IBM CoreConnect bus architecture e 64 bit 133 MHz bus used with the PowerP
27. ze e ARM JTAG processor debug support e real time data instruction processor trace e background debug monitoring via JTAG interface SOPC builder synthesis e intuitive GUI simplifying system definition and customization e wizard interface for customization of each component e automatically generated logic integrates processor memories peripherals IP cores on chip buses and bus arbiters e creates VHDL Verilog HDL code for system connection e software development environment generated to match the target hardware Simulation support for e Quartus II simulator e Cadence NC Verilog and NC VHDL simulators e ModelSim simulator e Synopsys VCS simulator Software e Quartus II development environment includes gt Integrated hardware and software development environment gt C C compiler source level debugger RTOS support Operating Systems Accelerated Technology Nucleus PLUS RTOS Micrium uC OS II the Real Time Kernel Microtronix Linux MiSPO NORTi RTOS MontaVista Software Linux OSE Systems OSE RTOS Shugyo Design Technologies KROS Performance e performance ratio of 1 05 MIPS per MHz e processor running 200 MHz References e www altera com products devices arm e Excalibur Devices Hardware Reference Manual e ARM922T Technical Reference Manual e ARM9TDMI Technical Reference Manual 3 13 HOGESCHOOL VOOR WETENSCHAP amp KUNST DIE NAYER INSTITUUT LEON 2 1 0 10 Intro
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