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C167 Derivatives

1. SSCCON FFB2 D94 SFR Reset Value 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SSC SSC SSC SSC SSC SSC SSC rw rw rw rw rw rw rw r Bit Function Operating Mode SSCEN 1 SSCBC SSC Bit Count Field Shift counter is updated with every shifted bit Do not write to SSCTE SSC Transmit Error Flag T4 Transfer starts with the slave s transmit buffer not being updated SSCRE SSC Receive Error Flag 1 Reception completed before the receive buffer was read SSCPE SSC Phase Error Flag 1 Received data changes around sampling clock edge SSCBE SSC Baudrate Error Flag 14 More than factor 2 or 0 5 between Slave s actual and expected baudrate SSCBSY SSC Busy Flag Set while a transfer is in progress Do not write to SSCMS SSC Master Select Bit 0 Slave Mode Operate on shift clock received via SCLK 1 Master Mode Generate shift clock and output it via SCLK SSCEN SSC Enable Bit 1 Transmission and reception enabled Access to status flags and M S control Note The target of an access to SSCCON control bits or flags is determined by the state of SSCEN prior to the access ie writing C0574 to SSCCON in programming mode SSCEN 0 will initialize the SSC SSCEN was 0 and then turn it on SSCEN 1 When writing to SSCCON make sure that reserved locations receive zeros The shift register of the SSC is connected to both the transmit pin and the receive pin via the pin
2. 4 o lt T6l gt cpU MHz D imt TxOTL s TxOUT TxOE MCB02028 Figure 9 13 Block Diagram of Core Timer T6 in Timer Mode The timer input frequencies resolution and periods which result from the selected prescaler option when using a 20 MHz CPU clock are listed in the table below This table also applies to the Gated Timer Mode of T6 and to the auxiliary timer T5 in timer and gated timer mode Note that some numbers may be rounded to 3 significant digits GPT2 Timer Input Frequencies Resolution and Periods fopy 20MHz Timer Input Selection T5I T6l 000p 001g 010g 011g 100g 101g 110g 111g Prescaler factor 4 8 16 32 64 128 256 512 Input Frequency 5 2 5 1 25 625 312 5 1156 25 78 125 39 06 MHz MHz MHz kHz kHz kHz kHz kHz Resolution 200ns 400ns 800ns 1 6us 3 2us 6 4us 12 8 us 25 6 us Period 13ms 26ms 52 5ms 105ms 210 ms 420 ms 840 ms 1 68 s Semiconductor Group 9 20 SIEMENS The General Purpose Timer Units C167 Timer 6 in Gated Timer Mode Gated timer mode for the core timer T6 is selected by setting bit field T6M in register TECON to 010g or 0115 Bit TeM 0 T6CON 3 selects the active level of the gate input In gated timer mode the same options for the input frequency as for the timer mode are available However the input clock to the timer in this mode is gated by the external input pin T6IN Timer T6 External Input which is an alter
3. Bit Function Programming Mode SSCEN 0 SSCBM SSC Data Width Selection 0 Reserved Do not use this combination 1 15 Transfer Data Width is 2 16 bit lt SSCBM gt 1 SSCHB SSC Heading Control Bit 0 Transmit Receive LSB First 1 3 Transmit Receive MSB First SSCPH SSC Clock Phase Control Bit 0 Shift transmit data on the leading clock edge latch on trailing edge du Latch receive data on leading clock edge shift on trailing edge SSCPO SSC Clock Polarity Control Bit 0 Idle clock line is low leading clock edge is low to high transition ic Idle clock line is high leading clock edge is high to low transition SSCTEN SSC Transmit Error Enable Bit 0 Ignore transmit errors 1 Check transmit errors SSCREN SSC Receive Error Enable Bit 0 Ignore receive errors 1 Check receive errors SSCPEN SSC Phase Error Enable Bit 0 Ignore phase errors 1 Check phase errors SSCBEN SSC Baudrate Error Enable Bit 0 Ignore baudrate errors 1 Check baudrate errors SSCAREN SSC Automatic Reset Enable Bit 0 No additional action upon a baudrate error 1 The SSC is automatically reset upon a baudrate error SSCMS SSC Master Select Bit 0 Slave Mode Operate on shift clock received via SCLK Ws Master Mode Generate shift clock and output it via SCLK SSCEN SSC Enable Bit 0 Transmission and reception disabled Access to control bits Semiconductor Group 11 3 SIEM ENS The High Speed Synchronous Serial Interface C167
4. CAN TxD CAN Interface CAN RxD Physical Layer NY MCB02574 Connection to the CAN Bus More information about the on chip CAN interface is provided in the separate document The On Chip CAN Module Advance Information 05 93 Future versions of this manual will also provide more detailled information Semiconductor Group 23 20 SIEMENS Keyword Index C167 1 Keyword Index This section lists a number of keywords which refer to specific details of the C167 in terms of its architecture its functional units or functions This helps to quickly find the answer to specific questions about the C1670 A Acronyms 1 7 Adapt Mode 17 8 ADC 2 16 16 1 ADCIC ADEIC 16 11 ADCON 16 3 ADDAT ADDAT2 16 4 Address Arbitration 8 22 Area Definition 8 21 Boundaries 3 12 Segment 8 8 17 10 ADDRSELx 8 20 8 22 ALE length 8 11 ALU 4 14 Analog Digital Converter 2 16 16 1 Arbitration Address 8 22 External Bus 8 25 ASCO Error Detection 10 10 Interrupts 10 12 ASCO Asynchronous Serial Interface 10 1 Auto Scan conversion 16 5 Semiconductor Group 1 1 B Baudrate ASCO 10 10 Bootstrap Loader 13 4 CAN 23 10 SSC 11 11 BHE 6 19 8 7 Bit addressable memory 3 4 Handling 4 9 Manipulation Instructions 21 2 protected 2 17 4 9 Bootstrap Loader 13 1 17 8 Boundaries 3 12 Burst mode PWM 15 5 Bus Arbitration 8 25 CAN 2 13 23 1 23 20 Demultiplexed 8 4 Mode Configuration 8 2 17 9 Multiplexed 8 3 B
5. and also accessible via the ESFR mode EXTR is not required for this access i i MMee el The scope of the EXTR 4 instruction ends here MOV T8REL R1 T8REL uses 16 bit address R1 is duplicated and does not require switching In order to minimize the use of the EXTR instructions the ESFR area mostly holds registers which are mainly required for initialization and mode selection Registers that need to be accessed frequently are allocated to the standard SFR area wherever possible Note The tools are equipped to monitor accesses to the ESFR area and will automatically insert EXTR instructions or issue a warning in case of missing or excessive EXTR instructions Semiconductor Group 3 8 SIEMENS Memory Organization C167 3 3 The On Chip XRAM The XRAM area is located within data page 3 and provides access to 2 KByte of on chip RAM organized as 1K 16 As the XRAM is connected to the internal XBUS it is accessed like external memory however no external bus cycles are executed for these accesses XRAM accesses are globally enabled or disabled via bit XPEN in register SYSCON This bit is cleared after reset and may be set via software during the initialization to allow accesses to the on chip XRAM When the XRAM is disabled default after reset all accesses to the XRAM area are mapped to external locations The XRAM may be used for both code instructions and data variables user stack tables etc storage
6. Count Direction Control The count direction of the core timer can be controlled either by software or by the external input pin T6EUD Timer T6 External Up Down Control Input which is the alternate input function of port pin P5 10 These options are selected by bits T6UD and T6UDE in control register TeCON When the up down control is done by software bit TEUDE 0 the count direction can be altered by setting or clearing bit TEUD When TeUDE 1 pin T6EUD is selected to be the controlling source of the count direction However bit T6UD can still be used to reverse the actual count direction as shown in the table below If TEUDz 0 and pin T6EUD shows a low level the timer is counting up With a high level at T6EUD the timer is counting down If T6UD 1 a high level at pin T6EUD specifies counting up and a low level specifies counting down The count direction can be changed regardless of whether the timer is running or not GPT2 Core Timer T6 Count Direction Control Pin TXEUD Bit TXUDE Bit TXUD Count Direction X 0 0 Count Up X 0 1 Count Down 0 1 0 Count Up 1 1 0 Count Down 0 1 1 Count Down 1 1 1 Count Up Note The direction control works the same for core timer T6 and for auxiliary timer T5 Therefore the pins and bits are named Tx Timer 6 Output Toggle Latch An overflow or underflow of timer T6 will clock the toggle bit T6OTL in control register T6CON T6OTL can also be set or reset
7. MCTC 3 0 Synchronous READY ie the READY signal must meet setup and hold times MCTC 3 1 Asynchronous READY ie the READY signal is synchronized internally The Synchronous READY provides the fastest bus cycles but requires setup and hold times to be met The CLKOUT signal should be enabled and may be used by the peripheral logic to control the READY timing in this case The Asynchronous READY is less restrictive but requires additional waitstates caused by the internal synchronization As the asynchronous READY is sampled earlier see figure above programmed waitstates may be necessary to provide proper bus cycles see also notes on normally ready peripherals below Semiconductor Group 8 15 SIEMENS The External Bus Interface C167 A READY signal especially asynchronous READY that has been activated by an external device may be deactivated in response to the trailing rising edge of the respective command RD or WR Note When the READY function is enabled for a specific address window each bus cycle within this window must be terminated with an active READY signal Otherwise the controller hangs until the next reset A timeout function is only provided by the watchdog timer Combining the READY function with predefined waitstates is advantageous in two cases Memory components with a fixed access time and peripherals operating with READY may be grouped into the same address window The external w
8. Note The content of SSCBR must be gt 0 Semiconductor Group 11 11 SIEM ENS The High Speed Synchronous Serial Interface C167 11 4 Error Detection Mechanisms The SSC is able to detect four different error conditions Receive Error and Phase Error are detected in all modes while Transmit Error and Baudrate Error only apply to slave mode When an error is detected the respective error flag is set When the corresponding Error Enable Bit is set also an error interrupt request will be generated by setting SSCEIR see figure below The error interrupt handler may then check the error flags to determine the cause of the error interrupt The error flags are not reset automatically like SSCEIR but rather must be cleared by software after servicing This allows servicing of some error conditions via interrupt while the others may be polled by software Note The error interrupt handler must clear the associated enabled errorflag s to prevent repeated interrupt requests A Receive Error Master or Slave mode is detected when a new data frame is completely received but the previous data was not read out of the receive buffer register SSCRB This condition sets the error flag SSCRE and when enabled via SSCREN the error interrupt request flag SSCEIR The old data in the receive buffer SSCRB will be overwritten with the new value and is unretrievably lost A Phase Error Master or Slave mode is detected when the incoming data at
9. Semiconductor Group 6 5 SIEMENS Parallel Ports C167 Alternate Functions of PORTO When an external bus is enabled PORTO is used as data bus or address data bus Note that an external 8 bit demultiplexed bus only uses POL while POH is free for IO provided that no other bus mode is enabled PORTO is also used to select the system startup configuration During reset PORTO is configured to input and each line is held high through an internal pullup device Each line can now be individually pulled to a low level see DC level specifications in the respective Data Sheets through an external pulldown device A default configuration is selected when the respective PORTO lines are at a high level Through pulling individual lines to a low level this default can be changed according to the needs of the applications The internal pullup devices are designed such that an external pulldown resistors see Data Sheet specification can be used to apply a correct low level These external pulldown resistors can remain connected to the PORTO pins also during normal operation however care has to be taken such that they do not disturb the normal function of PORTO this might be the case for example if the external resistor is too strong With the end of reset the selected bus configuration will be written to the BUSCONO register The configuration of the high byte of PORTO will be copied into the special register RPOH This read only registe
10. The instruction cycle time has been dramatically reduced through the use of instruction pipelining This technique allows the core CPU to process portions of multiple sequential instruction stages in parallel The following four stage pipeline provides the optimum balancing for the CPU core FETCH In this stage an instruction is fetched from the internal ROM or RAM or from the external memory based on the current IP value DECODE In this stage the previously fetched instruction is decoded and the required operands are fetched EXECUTE In this stage the specified operation is performed on the previously fetched operands WRITE BACK In this stage the result is written to the specified location If this technique were not used each instruction would require four machine cycles This increased performance allows a greater number of tasks and interrupts to be processed Instruction Decoder Instruction decoding is primarily generated from PLA outputs based on the selected opcode No microcode is used and each pipeline stage receives control signals staged in control registers from the decode stage PLAs Pipeline holds are primarily caused by wait states for external memory accesses and cause the holding of signals in the control registers Multiple cycle instructions are performed through instruction injection and simple internal state machines which modify required control signals High Function 8 bit and 16 bit Arithmetic and Logic U
11. To meet the demand for greater performance and flexibility a number of areas has been optimized in the processor core Functional blocks in the CPU core are controlled by signals from the instruction decode logic These are summarized below and described in detail in the following sections 1 High Instruction Bandwidth Fast Execution 2 High Function 8 bit and 16 bit Arithmetic and Logic Unit 3 Extended Bit Processing and Peripheral Control 4 High Performance Branch Call and Loop Processing 5 Consistent and Optimized Instruction Formats 6 Programmable Multiple Priority Interrupt Structure Semiconductor Group 2 2 SIEMENS Architectural Overview C167 High Instruction Bandwidth Fast Execution Based on the hardware provisions most of the C167 s instructions can be executed in just one machine cycle which requires 100 ns at 20 MHz CPU clock For example shift and rotate instructions are always processed within one machine cycle independent of the number of bits to be shifted Branch multiply and divide instructions normally take more than one machine cycle These instructions however have also been optimized For example branch instructions only require an additional machine cycle when a branch is taken and most branches taken in loops require no additional machine cycles at all due to the so called Jump Cache A 32 bit 16 bit division takes 1us a 16 bit 16 bit multiplication takes 0 5 us
12. Write ODP2 y Open Drain Latch Read ODP2 y Write DP2 y Y Direction Latch Read DP2 y Y I n 1 e r n a lt UJ oc Data Output Write Port P2 y n Compare Trigger gt Read P2 y Figure 6 9 Block Diagram of a Port 2 Pin Semiconductor Group s Mn Output Alternate Latch 0 v v Alternate Data Input d Output Buffer Xzln MCB02070 SIEMENS Parallel Ports C167 6 4 Port 3 If this 15 bit port is used for general purpose IO the direction of each line can be configured via the corresponding direction register DP3 Most port lines can be switched into push pull or open drain mode via the open drain control register ODP2 pins P3 15 P3 14 and P3 12 do not support open drain mode Due to pin limitations register bit P3 14 is not connected to an output pin P3 FFC4 E21 SFR Reset Value 0000 15 14 13 12 1i 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bit Function P3 y Port data register P3 bit y Note Register bit P3 14 is not connected to an IO pin DP3 FFC6 E31 SFR Reset Value 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 eo t e oe oe e ep oe v ee ee v t 15 11 10 8 7 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bit Function DP3 y Port direction register DP3 bit y DP3 y 0 Port line P3 y is an input high impedance
13. C167 code Segment 15 CSP Register 0 15 IP Register FF FFFFj 7 255 254 FE 0000 V A J 0100004 24 20 18 Bit Physical Code Address 000000 MCA02265 Figure 4 5 Addressing via the Code Segment Pointer Note When segmentation is disabled the IP value is used directly as the 16 bit address Semiconductor Group 4 19 SIEMENS The Central Processing Unit CPU C167 The Data Page Pointers DPPO DPP1 DPP2 DPP3 These four non bit addressable registers select up to four different data pages being active simultaneously at run time The lower 10 bits of each DPP register select one of the 1024 possible 16 Kbyte data pages while the upper 6 bits are reserved for future use The DPP registers allow to access the entire memory space in pages of 16 Kbytes each The DPP registers are implicitly used whenever data accesses to any memory location are made via indirect or direct long 16 bit addressing modes except for override accesses via EXTended instructions and PEC data transfers After reset the Data Page Pointers are initialized in a way that all indirect or direct long 16 bit addresses result in identical 18 bit addresses This allows to access data pages 3 0 within segment 0 as shown in the figure below If the user does not want to use any data paging no further action is required DPPO FE00 004 SFR Reset Value 0000 15 9 8
14. Disable Enable Control for Pin BHE BYTDIS Bit BYTDIS is provided for controlling the active low Byte High Enable BHE pin The function of the BHE pin is enabled if the BYTDIS bit contains a 0 Otherwise it is disabled and the pin can be used as standard IO pin The BHE pin is implicitly used by the External Bus Controller to select one of two byte organized memory chips which are connected to the C167 via a word wide external data bus After reset the BHE function is automatically enabled BYTDIS 0 if a 16 bit data bus is selected during reset otherwise it is disabled BYTDIS 1 It may be disabled if byte access to 16 bit memory is not required and the BHE signal is not used Semiconductor Group 8 7 SIEMENS The External Bus Interface C167 Segment Address Generation During external accesses the EBC generates a programmable number of address lines on Port 4 which extend the 16 bit address output on PORTO or PORT1 and so increase the accessible address space The number of segment address lines is selected during reset and coded in bit field SALSEL in register RPOH see table below SALSEL Segment Address Lines Directly accessible Address Space 11 Two A17 A16 256 KByte Default without pull downs 10 Eight A23 A16 16 MByte Maximum 0 1 None 64 KByte Minimum 00 Four A19 A16 1 MByte Note The total accessible address space may be increased by accessing several banks whi
15. Power Supply for Analog Digital Converter VPP Reserved for Flash Programming Voltage VCC VSS Digital Power Supply and Ground 10 pins each The Address Latch Enable signal ALE controls external address latches that provide a stable address in multiplexed bus modes ALE is activated for every external bus cycle independent of the selected bus mode ie it is also activated for bus cycles with a demultiplexed address bus When an external bus is enabled one or more of the BUSACT bits set also X Peripheral accesses will generate an active ALE signal ALE is not activated for internal accesses ie accesses to ROM Flash if provided the internal RAM and the special function registers In single chip mode ie when no external bus is enabled no BUSACT bit set ALE will also remain inactive for X Peripheral accesses The External Read Strobe RD controls the output drivers of external memory or peripherals when the C167 reads data from these external devices During reset and during Hold mode an internal pullup ensures an inactive high level on the RD output During accesses to on chip X Peripherals RD remains inactive high The External Write Strobe WR WRL controls the data transfer from the C167 to an external memory or peripheral device This pin may either provide an general WR signal activated for both byte and word write accesses or specifically control the low byte of an external 16 bit device WRL together with
16. SIEMENS Device Specification C167 2 CC24l0 4 3 2 0 5 CC2710 4 CC2610 3 CC2510 0 H 7 A H 6 A H 4 A H 2 A H 1 A9 H 0 A8 POH 0 AD8 POL 7 AD7 POL 6 AD6 POL 5 AD5 POL 4 AD4 POL 3 AD3 P6 0 CS0 P6 1 CS1 P6 2 CS2 P6 3 CS3 P6 4 CS4 P6 5 HOLD P6 6 HLDA POL 2 AD2 P6 7 BREQ POL 1 AD1 P8 0 CC16 POL 0 ADO P8 1 CC17 EA P8 2 CC18 ALE PB 3 CC19 READY P8 4 CC20 WR WRL P8 5 CC21 RD P8 6 CC22 P8 7 CC23 Voc Vos P4 6 A22CAN TxD P7 0 POUTO P4 5 A21CAN RxD P7 1 POUT1 P4 4 A20 P7 2 POUT2 P4 3 A19 P7 3 POUT3 P4 2 A18 P7 4 CC2810 P4 1 A17 P7 5 CC2910 P4 0 A16 P7 6 CC30I0 Vep P7 7 CC3110 Vss P5 0 ANO Kc P5 1 AN1 P3 15 CLKOUT P5 2 AN2 P3 13 SCLK P5 3 AN3 P3 12 BHE WRH P5 4 AN4 P3 11 RXDO P5 5 AN5 P3 10 TXDO P5 6 AN6 P3 9 MTSR P5 7 AN7 P3 8 MRST P5 8 AN8 P3 7 T2IN P5 9 AN9 P3 6 T3IN oNN ANN 0 1 49 0 1 50 0 1151 0 1 52 MCP01991 P5 10 AN10 TGEUD r zo P5 11 AN11 T5EUD r 40 P5 12 AN12 T6IN r 41 P5 13 AN13 T5IN r 42 P5 14 AN14 TA4EUD r 43 P5 15 AN15 T2EUD r 44 P2 0 CCO P2 1 CC1 P2 2 CC2 P2 5 CC3 P2 4 CC4 P2 5 CC5 P2 6 CC6 P2 7 CC7 Figure 22 1 Pin Description for C167 P MQFP 144 Package Semiconductor Group 22 2 SIEMENS The On Chip CAN Interface C167 23 The On Chip CAN Interface The Controller Area Network CAN bus with its associated protocol allows communication between a number of stations which are connected to this bus with high efficiency Efficiency
17. The functions of the CAPCOM timers are controlled via the bitaddressable 16 bit control registers T01CON and T78CON The high byte of TO1CON controls T1 the low byte of TO1 CON controls TO the high byte of T78CON controls T8 the low byte of T78CON controls T7 The control options are identical for all four timers except for external input TO1CON FF50 A8 SFR Reset Value 00004 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw s zi rw rw 3 rw rw rw T78CON FF20 904 SFR Reset Value 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw Bit Function Txl Timer Counter x Input Selection Timer Mode TxM 0 Input Frequency fopy p lt Txl gt 3 See also table below for examples Counter Mode TxM 1 X00 Overflow Underflow of GPT2 Timer 6 X01 Positive rising edge on pin TxIN X10 Negative falling edge on pin TxIN X11 Any edge rising and falling on pin TxIN TxM Timer Counter x Mode Selection 0 Timer Mode Input derived from internal clock 1 Counter Mode Input from External Input or T6 TxR Timer Counter x Run Control 0 Timer Counter x is disabled 1 Timer Counter x is enabled This selection is available for timers TO and T7 Timers T1 and T8 will stop at this selection The timer run flags TOR T1R T7R and T8R allow for enabling and disabling the timers The following description of the timer modes and operation always applies to the
18. 00004 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw Bit Function mdh Specifies the high order 16 bits of the 32 bit multiply and divide register MD Whenever this register is updated via software the Multiply Divide Register In Use MDRIU flag in the Multiply Divide Control register MDC is set to 1 When a multiplication or division is interrupted before its completion and when a new multiply or divide operation is to be performed within the interrupt service routine register MDH must be saved along with registers MDL and MDC to avoid erroneous results A detailed description of how to use the MDH register for programming multiply and divide algorithms can be found in chapter System Programming The Multiply Divide Low Register MDL This register is a part of the 32 bit multiply divide register which is implicitly used by the CPU when it performs a multiplication or a division After a multiplication this non bit addressable register represents the low order 16 bits of the 32 bit result For long divisions the MDL register must be loaded with the low order 16 bits of the 32 bit dividend before the division is started After any division register MDL represents the 16 bit quotient MDL FEOE 074 SFR Reset Value 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Function mdl Specifies the low order 16 bits of the 32 bit multiply and divide register MD Semiconductor Group 4 27 SIEMENS The Ce
19. 14 ACC CCMOD15 al CCMOD14 EL CCMOD13 Gl CCMOD12 icd Semiconductor Group 14 9 SIEMENS The Capture Compare Units C167 Capture Compare Mode Registers for the CAPCOM2 Unit CC16 CC32 CCM4 gis 91 A SFR Reset Value pe 14 w ee e eme e mms up ul CCM5 ie oai SFR Reset Value pU 14 CCM6 pgs s SFR Reset Value Id 14 LENSES GEN CCM7 P E SFR Reset Value octane 14 Bit Function CCMODx Mode Selection for Capture Compare Register CCx The available capture compare modes are listed in the table below ACCx Allocation Bit for Capture Compare Register CCx 0 CCx allocated to Timer TO CAPCOM 1 Timer T7 CAPCOM2 1 CCx allocated to Timer T1 CAPCOM1 Timer T8 CAPCOM2 Semiconductor Group 14 10 SIEMENS The Capture Compare Units C167 Selection of Capture Modes and Compare Modes CCMODx Selected Operating Mode 000 Disable Capture and Compare Modes The respective CAPCOM register may be used for general variable storage 001 Capture on Positive Transition Rising Edge at Pin CCxlO 010 Capture on Negative Transition Falling Edge at Pin CCxlO 0 1 1 Capture on Positive and Negative Transition Both Edges at Pin CCxlO 100 Compare Mode 0 Interrupt Only Several interrupts per timer period Enables double register compare mode for registers CC8 CC15 and CC24 CC31 101 Compare Mode 1 Toggle Output Pin on each Match Several compare events per timer peri
20. 2 CCx cv2 CCx cv1 MCT02021 Output pin CCxIO only effected in mode 3 No changes in mode 2 B i v 8 Figure 14 9 Timing Example for Compare Modes 2 and 3 Semiconductor Group 14 16 SIEMENS The Capture Compare Units C167 Compare Mode 3 Compare mode 3 is selected for register CCx by setting bit field CCMODx of the corresponding mode control register to 1115 In compare mode 3 only one compare event will be generated per timer period When the first match within the timer period is detected the interrupt request flag CCxIR is set to 1 and also the output pin CCxIO alternate port function will be set to 1 The pin will be reset to 0 when the allocated timer overflows If a match was found for register CCx in this mode all further compare events during the current timer period are disabled for CCx until the corresponding timer overflows If after a match was detected the compare register is reloaded with a new value this value will not become effective until the next timer period In order to use the respective port pin as compare signal output pin CCxlO for compare register CCx in compare mode 3 this port pin must be configured as output ie the corresponding direction control bit must be set to 1 With this configuration the initial state of the output signal can be programmed or its state can be modified at any time by writing to the port output latch In compare mode 3 the port latc
21. BASE Move table base into RO LOOP CMP R1 RO Compare target to table entry JMPR cc SGT LOOP Test whether target has not been found Note The last entry in the table must be greater than the largest possible target MOV RO BASE Move table base into RO LOOP CMP R1 RO Compare target to table entry JMPR cc NET LOOP Test whether target is not found AND the end of table has not been reached Note The last entry in the table must be equal to the lowest signed integer 8000p 19 5 Peripheral Control and Interface All communication between peripherals and the CPU is performed either by PEC transfers to and from internal memory or by explicitly addressing the SFRs associated with the specific peripherals After resetting the C167 all peripherals except the watchdog timer are disabled and initialized to default values A desired configuration of a specific peripheral is programmed using MOV instructions of either constants or memory values to specific SFRs Specific control flags may also be altered via bit instructions Once in operation the peripheral operates autonomously until an end condition is reached at which time it requests a PEC transfer or requests CPU servicing through an interrupt routine Information may also be polled from peripherals through read accesses to SFRs or bit operations including branch tests on specific control bits in SFRs To ensure proper allocation of peripherals among multiple tasks a port
22. C167 Note The channel injection request bit ADCRQ will be set on any interrupt request of CAPCOM2 channel CC31 regardless whether the channel injection mode is enabled or not It is recommended to always clear bit ADCRQ before enabling the channel injection mode Note While an injected conversion is in progress no further channel injection request can be triggered The Channel Injection Request flag ADCRQ remains set until the result of the injected conversion is written to the ADDAT2 register Note If the converter was idle before the channel injection and during the injected conversion the converter is started by software for normal conversions the channel injection is aborted and the converter starts in the selected mode as described above This can be avoided by checking the busy bit ADBSY before starting a new operation After the completion of the current conversion if any is in progress the converter will start inject the conversion of the specified channel When the conversion of this channel is complete the result will be placed into the alternate result register ADDAT2 and a Channel Injection Complete Interrupt request will be generated which uses the interrupt request flag ADEIR for this reason the Wait for ADDAT Read Mode is required Note If the temporary data register used in Wait for ADDAT Read Mode is full the respective next conversion standard or injected will be suspended The temporary register can hol
23. Corruption of the data on the receive line sent by the selected slave is avoided when all slaves which are not selected for transmission to the master only send ones 1 Since this high level is not actively driven onto the line but only held through the pullup device the selected slave can pull this line actively to a low level when transmitting a zero bit The master selects the slave device from which it expects data either by separate select lines or by sending a special command to this slave After performing all necessary initializations of the SSC the serial interfaces can be enabled For a master device the alternate clock line will now go to its programmed polarity The alternate data line will go to either 0 or 1 until the first transfer will start After a transfer the alternate data line will always remain at the logic level of the last transmitted data bit When the serial interfaces are enabled the master device can initiate the first data transfer by writing the transmit data into register SSCTB This value is copied into the shift register which is assumed to be empty at this time and the selected first bit of the transmit data will be placed onto the MTSR line on the next clock from the baudrate generator transmission only starts if SSCEN 1 Depending on the selected clock phase also a clock pulse will be generated on the SCLK line With the opposite clock edge the master at the same time latches and shifts
24. D0 SOM 100p of 8 data bits D7 DO plus an automatically generated parity bit SOMz 111g or of 8 data bits D7 DO plus wake up bit S0Mz 101g Parity may be odd or even depending on bit SOODD in register SOCON An even parity bit will be set if the modulo 2 sum of the 8 data bits is 1 An odd parity bit will be cleared in this case Parity checking is enabled via bit SOPEN always OFF in 9 bit data and wake up mode The parity error flag SOPE will be set along with the error interrupt request flag if a wrong parity bit is received The parity bit itself will be stored in bit SORBUF 8 In wake up mode received frames are only transferred to the receive buffer register if the 9th bit the wake up bit is 1 If this bit is 0 no receive interrupt request will be activated and no data will be transferred This feature may be used to control communication in multi processor system When the master processor wants to transmit a block of data to one of several slaves it first sends out an address byte which identifies the target slave An address byte differs from a data byte in that the additional 9th bit is a 1 for an address byte and a 0 for a data byte so no slave will be interrupted by a data byte An address byte will interrupt all slaves operating in 8 bit data wake up bit mode so each slave can examine the 8 LSBs of the received character the address The addressed slave will switch to 9 bit data mode
25. FF06 834 SFR Reset Value 00 8 7 6 5 4 3 2 1 rw rw rw rw rw rw rw rw Bit Function P1X y Port data register P1H or P1L bit y DP1L F104 82 ESFR Reset Value 00 ic E 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 E TE s TE DP1H F106 831 ESFR Reset Value 00 le ee 9 8 7 6 5 4 3 2 1 0 DP1H 7 E amp rw rw rw rw rw rw rw rw Bit Function DP1X y Port direction register DP1H or DP1L bit y DP1X y 0 Port line P1X y is an input high impedance DP1X y 1 Port line P1X y is an output Semiconductor Group 6 8 SIEMENS Parallel Ports C167 Alternate Functions of PORT1 When a demultiplexed external bus is enabled PORT1 is used as address bus Note that demultiplexed bus modes use PORT1 as a 16 bit port Otherwise all 16 port lines can be used for general purpose IO The upper four pins of PORT1 P1H 7 P1H 4 also serve as capture input lines for the CAPCOM2 unit CC2710O CC241O As all other capture inputs the capture input function of pins P1H 7 P1H 4 can also be used as external interrupt inputs 400 ns sample rate 20 MHz CPU clock As a side effect the capture input capability of these lines can also be used in the address bus mode Hereby changes of the upper address lines could be detected and trigger an interrupt request in order to perform some special service routines External capture signals can only be applied if no
26. I n t e r n a MCB02073 Figure 6 12 Block Diagram of Pins P3 15 CLKOUT and P3 12 BHE WRH Note Enabling the BHE or WRH function automatically enables the P3 12 output driver Setting bit DP3 122 1 is not required During bus hold pin P3 12 is switched back to its standard function and is then controlled by DP3 12 and P3 12 Keep DP3 12 0 in this case to ensure floating in hold mode Semiconductor Group 6 19 SIEMENS Parallel Ports C167 6 5 Port4 If this 8 bit port is used for general purpose IO the direction of each line can be configured via the corresponding direction register DP4 P4 FFC8 E44 SFR Reset Value 00 UNE 13 12 ull RES 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw Bit Function P4 y Port data register P4 bit y DP4 FFCA E5y SFR Reset Value 00 zm i 6 5 4 3 2 1 0 orar ora oras ora ora ea zoe ooa E a z a a DP4 y Port direction register DP4 bit y DP4 y 0 Port line P4 y is an input high impedance DP4 y 1 Port line P4 y is an output Bit Function Alternate Functions of Port 4 During external bus cycles that use segmentation ie an address space above 64 KByte a number of Port 4 pins may output the segment address lines The number of pins that is used for segment address output determines the external address space which is directly accessible The other pins of Port 4 if
27. If the alternate output function of a port pin is used by a peripheral the state of the pin is determined by the operation of the peripheral Port pins which are used for bus control functions go into that state which represents the inactive state of the respective function eg WR or to a defined state which is based on the last bus access eg BHE Port pins which are used as external address data bus hold the address data which was output during the last external memory access before entry into Idle mode under the following conditions POH outputs the high byte of the last address if a multiplexed bus mode with 8 bit data bus is used otherwise POH is floating POL is always floating in Idle mode PORT outputs the lower 16 bits of the last address if a demultiplexed bus mode is used otherwise the output pins of PORT1 represent the port latch data Port 4 outputs the segment address for the last access on those pins that were selected during reset otherwise the output pins of Port 4 represent the port latch data During Power Down mode the oscillator and the clocks to the CPU and to the peripherals are turned off Like in Idle mode all port pins which are configured as general purpose output pins output the last data value which was written to their port output latches When the alternate output function of a port pin is used by a peripheral the state of this pin is determined by the last action of the peripheral before the clocks wer
28. Increment DSTPx by 1 or 2 BWT 1 0 Increment SRCPx by 1 or 2 BWT 1 1 Reserved Do not use this combination changed to 10 by hardware PEC Control Register Addresses Register Address Reg Space Register Address Reg Space PECCO FECO 604 SFR PECC4 FEC8 644 SFR PECC1 FEC2 61 SFR PECC5 FECA 65 SFR PECC2 FEC4 62 SFR PECC6 FECC 664 SFR PECC3 FEC6 63 SFR PECC7 FECE 67 SFR Byte Word Transfer bit BWT controls if a byte or a word is moved during a PEC service cycle This selection controls the transferred data size and the increment step for the modified pointer Semiconductor Group Interrupt and Trap Functions C167 SIEMENS Increment Control Field INC controls if one of the PEC pointers is incremented after the PEC transfer It is not possible to increment both pointers however If the pointers are not modified INC 00 the respective channel will always move data from the same source to the same destination Note The reserved combination 11 is changed to 10 by hardware However it is not recommended to use this combination The PEC Transfer Count Field COUNT controls the action of a respective PEC channel where the content of bit field COUNT at the time the request is activated selects the action COUNT may allow a specified number of PEC transfers unlimited transfers or no PEC service at all The table below summarizes
29. LT z x x m a T DP7 y Port direction register DP7 bit y DP7 y 0 Port line P7 y is an input high impedance DP7 y 1 Port line P7 y is an output Bit Function ODP7 F1D2 E9 ESFR Reset Value 00j 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ODP7 ODP7 ODP7 ODP7 ODP7 ODP7 ODP7 ODP7 T4 6 5 4 3 2 x 0 mes a me TF s m ODP7 y Port 7 Open Drain control register bit y ODP7 y 0 Port line P7 y output driver in push pull mode ODP7 y 1 Port line P7 y output driver in open drain mode Bit Function Semiconductor Group 6 30 SIEMENS Parallel Ports C167 Alternate Functions of Port 7 The upper 4 lines of Port 7 P7 7 P7 4 serve as capture inputs or compare outputs CC3110 C C2810 for the CAPCOM2 unit The usage of the port lines by the CAPCOM unit its accessibility via software and the precautions are the same as described for the Port 2 lines As all other capture inputs the capture input function of pins P7 7 P7 4 can also be used as external interrupt inputs 400 ns sample rate 20 MHz CPU clock The lower 4 lines of Port 7 P7 3 P7 0 serve as outputs from the PWM module POUTS POUTO At these pins the value of the respective port output latch is XORed with the value of the PWM output rather than ANDed as the other pins do This allows to use the alternate output value either as it is port latch holds a 0 or invert its level at the pin port latch holds
30. N and N 1 are executed out of external memory instructions N 1 and N require external operand read accesses and instructions N 3 N 2 and N 1 write back external operands In this case the PEC response time is the time to perform 7 word bus accesses When instructions N and N 1 are executed out of external memory but all operands for instructions N 3 through N 1 are in internal memory then the PEC response time is the time to perform 1 word bus access plus 2 state times Once a request for PEC service has been acknowledged by the CPU the execution of the next instruction is delayed by 2 state times plus the additional time it might take to fetch the source operand from internal ROM or external memory and to write the destination operand over the external bus in an external program environment Note A bus access in this context also includes delays caused by an external READY signal or by bus arbitration HOLD mode Semiconductor Group 5 20 SIEMENS Interrupt and Trap Functions C167 5 6 External Interrupts Although the C167 has no dedicated INTR input pins it provides many possibilities to react on external asynchronous events by using a number of IO lines for interrupt input The interrupt function may either be combined with the pin s main function or may be used instead of it ie if the main pin function is not required Interrupt signals may be connected to CC311O CCO0IO the capture input compare output lines of
31. When writing a value to register CP with bits CP 11 CP 9 000 bits CP 11 CP 10 are set to 11 by hardware in all other cases all bits of bit field cp receive the written value Note It is the user s responsibility that the physical GPR address specified via CP register plus short GPR address must always be an internal RAM location If this condition is not met unexpected results may occur Do not set CP below 00 F600j or above 00 FDFE Be careful using the upper GPRs with CP above 00 FDE0 The CP register can be updated via any instruction which is capable of modifying an SFR Note Due to the internal instruction pipeline a new CP value is not yet usable for GPR address calculations of the instruction immediately following the instruction updating the CP register The Switch Context instruction SCXT allows to save the content of register CP on the stack and updating it with a new value in just one machine cycle Semiconductor Group 4 22 SIEMENS The Central Processing Unit CPU C167 Internal RAM pas rw d pas pas Context Pointer 7 7 MCA02003 Figure 4 7 Register Bank Selection via Register CP Several addressing modes use register CP implicitly for address calculations The addressing modes mentioned below are described in chapter Instruction Set Summary Short 4 Bit GPR Addresses mnemonic Rw or Rb specify an address relative to the memory location s
32. aca se Send NERA SONG OR OR aL Se E E VES 1 7 2 Architectural Overview 00 cece eee eee eee 2 1 2 1 Basic CPU Concepts and Optimizations 0000 eee 2 2 2 1 1 High Instruction Bandwidth Fast Execution 2 200 2 3 2 1 2 Programmable Multiple Priority Interrupt System 2 6 2 2 The On chip System Resources 00 cc eee eens 2 7 2 3 The On chip Peripheral Blocks ice oid eek eee taiwan s EE Ir ae els 2 11 2 4 Protected BITS MR rr Ct 2 17 3 Memory Organization 0 00 cee eee eee 3 1 3 1 Internal HOM ss stock ot Ste Pa CREXELame LEE eed afe dee ees 3 3 3 2 Internal RAM and SFR Area 0 ees 3 4 3 3 The On Chip XRHAM 4 sees iter de eee Nea Rs ee ARI AERERRSRER de 3 9 3 4 External Memory SpaCes cose ey oto aya wide RO AG CAE DEA e RS e 3 11 3 5 Crossing Memory Boundaries 0 00 e cence eee eee 3 12 4 The Central Processing Unit CPU 4 1 4 1 Instr ction Pipelining cesce ova nae Ae ae eae Eee RR OR EG 4 3 4 1 1 Particular Pipeline Effects eccdsaexe veu tees Oe xe REX E ERO d 4 6 4 2 Bit Haridling and Bit Protectlolt uve easier CR ERE xuEECPCCO E VES 4 9 4 3 Instruction State Times ansa ice CP ace s dre b o CR e acea 4 10 4 4 CPU Special Function Registers 0 00 cc cece eee eee 4 11 5 Interrupt and Trap Functions 00 0c eee eee 5 1 5 1 Interrupt System Structure 0 0 eee 5 2 5 1 1
33. control logic see block diagram Transmission and reception of serial data is synchronized and takes place at the same time ie the same number of transmitted bits is also received Transmit data is written into the Transmit Buffer SSCTB It is moved to the shift register as soon as this is empty An SSC master SSCMS 1 immediately begins transmitting while an SSC slave SSCMS 0 will wait for an active shift clock When the transfer starts the busy flag SSCBSY is set and a transmit interrupt request SSCTIR will be generated to indicate that SSCTB may be reloaded again When the programmed number of bits 2 16 has been transferred the contents of the shift register are moved to the Receive Buffer SSCRB and a receive interrupt request SSCRIR will be generated If no further transfer is to take place SSCTB is empty SSCBSY will be cleared at the same time Software should not modify SSCBSY as this flag is hardware controlled Note Only one SSC etc can be master at a given time Semiconductor Group 11 4 SIEM ENS The High Speed Synchronous Serial Interface C167 The transfer of serial data bits can be programmed in many respects the data width can be chosen from 2 bits to 16 bits transfer may start with the LSB or the MSB the shift clock may be idle low or idle high data bits may be shifted with the leading or trailing edge of the clock signal the baudrate may be set from 152 Bd up to 5 MBd 20 MHz CPU clo
34. control the selected address windows are completely under software control while register BUSCONQO which eg is also used for the very first code access after reset is partly controlled by hardware ie it is initialized via PORTO during the reset sequence This hardware control allows to define an appropriate external bus for systems where no internal program memory is provided BUSCONO ossa rm SFR Reset Value OXX0 14 11 1 0 CSW CSR RDY BUS ALE MTT RWD rw BUSCON1 ilu zn SFR Reset Value 0000 14 11 1 0 CSW CSR RDY ED ALE MTT RWD rw BUSCON2 i 64 zn SFR Reset Value 00004 14 11 1 0 CSW CSR RDY BUS ALE MTT RWD rw BUSCON3 8H as SFR Reset Value 00004 14 11 1 0 CSW CSR RDY BUS ALE MTT RWD rw BUSCONA uh Au o SFR Reset Value 00004 14 11 1 0 CSW CSR RDY BUS ALE MTT RWD rw Note BUSCONDO is initialized with 0000 if pin EA is high during reset If pin EA is low during reset bits BUSACTO and ALECTLO are set 1 and bit field BTYP is loaded with the bus configuration selected via PORTO Semiconductor Group 8 18 SIEMENS The External Bus Interface C167 Bit Function MCTC Memory Cycle Time Control Number of memory cycle time wait states 0000 15 waitstates Number 15 lt MCTC gt 111 1 No waitstates RWDCx Read Write Delay Control for BUSCONx 0 With read write delay activate command 1 TCL after falling edge of ALE 1 No read write delay activate
35. data has been transferred 3 When the CPU requests the transmission of a receive object a remote frame will be sent instead of a data frame to request a remote node to send the corresponding data frame This bit will be cleared by the CAN controller along with bit RMTPND when the message has been successfully transmitted if bit NEWDAT has not been set If there are several valid message objects with pending transmission request the message with the lowest message number is transmitted first Semiconductor Group 23 15 SIEMENS The On Chip CAN Interface C167 Arbitration Registers The Arbitration Registers are used for acceptance filtering of incoming messages and to define the identifier of outgoing messages A received message is stored into the valid message object with a matching identifier and DIR 0 data frame or DIR 1 remote frame Extended frames can be stored only in message objects with XTD 1 standard frames only in message objects with XTD 2 0 For matching the corresponding global mask has to be considered in case of message object 15 also the Mask of Last Message If a received message data frame or remote frame matches with more than one valid message object it is stored into that with the lowest message number When the CAN controller stores a data frame not only the data bytes but the whole identifier and the data length code are stored into the corresponding message object standard identifiers
36. external bus cycles accessing the respective address window will have their ALE signal prolonged by half a CPU clock 25 ns at fep 20 MHz Also the address hold time after the falling edge of ALE on a multiplexed bus will be prolonged by half a CPU clock so the data transfer within a bus cycle refers to the same CLKOUT edges as usual ie the data transfer is delayed by one CPU clock This allows more time for the address to be latched Note ALECTLO is 1 after reset to select the slowest possible bus cycle the other ALECTLx are 0 after reset Normal Multiplexed Lengthened Multiplexed Bus Cycle Bus Cycle l W RS NN l N M E e 1 1 I NW Y NV N Hold S NS NS Set ups E RWG SS S Address y i MCT02235 Figure 8 6 ALE Length Control Semiconductor Group 8 11 SIEMENS The External Bus Interface C167 Programmable Memory Cycle Time The C167 allows the user to adjust the controller s external bus cycles to the access time of the respective memory or peripheral This access time is the total time required to move the data to the destination It represents the period of time during which the controller s signals do not change Bus Cycle e Segment X Address MCTC Wait States 1 MCTO2063 Figure 8 7 Memory Cycle Time The external bus cycles of the C167 can be extended for a me
37. how the COUNT field itself the interrupt requests flag IR and the PEC channel action depends on the previous content of COUNT Previous Modified IR after Action of PEC Channel COUNT COUNT PEC service and Comments FF FF 0 Move a Byte Word Continuous transfer mode ie COUNT is not modified FEy 024 FDy 01y 0 Move a Byte Word and decrement COUNT Olh 004 T Move a Byte Word Leave request flag set which triggers another request 004 004 1 No action Activate interrupt service routine rather than PEC channel The PEC transfer counter allows to service a specified number of requests by the respective PEC channel and then when COUNT reaches 00 activate the interrupt service routine which is associated with the priority level After each PEC transfer the COUNT field is decremented and the request flag is cleared to indicate that the request has been serviced Continuous transfers are selected by the value FF in bit field COUNT In this case COUNT is not modified and the respective PEC channel services any request until it is disabled again When COUNT is decremented from 01 to 00 after a transfer the request flag is not cleared which generates another request from the same source When COUNT already contains the value 004 the respective PEC channel remains idle and the associated interrupt service routine is activated instead This allows to choose if a level 15 or 14 reque
38. in Txl when using a 20 MHz CPU clock are listed in the table below The numbers for the timer periods are based on a reload value of 0000 Note that some numbers may be rounded to 3 significant digits fcpy 20 MHz Timer Input Selection Txl 000g 001g 010g 011g 100g 101g 110g 111g Prescaler for fopy 8 16 32 64 128 256 512 1024 Input Frequency 2 5 1 25 625 312 5 156 25 78 125 39 06 19 53 MHz MHz kHz kHz kHz kHz kHz kHz Resolution 400 ns 800ns 1 6us 3 2us 6 4us 12 8us 25 6 us 51 2 us Period 26ms 52 5ms 105ms 210 ms 420 ms 840 ms 1 68s 3 36 s After a timer has been started by setting its run flag TxR to 1 the first increment will occur within the time interval which is defined by the selected timer resolution All further increments occur exactly after the time defined by the timer resolution When both timers of a CAPCOM unit are to be incremented or reloaded at the same time TO is always serviced one CPU clock before T1 T7 before T8 respectively Semiconductor Group 14 6 SIEMENS The Capture Compare Units C167 Counter Mode The bits TxM in SFRs TO1CON and T78CON select between timer or counter mode for the respective timer In Counter mode TxMz 1 the input clock for a timer can be derived from the overflows underflows of timer T6 in block GPT2 In addition timers TO and T7 can be clocked by external events Either a positive a negative or both a positi
39. interrupts by the CPU When IEN is cleared no interrupt requests are accepted by the CPU When IEN is set to 1 all interrupt sources which have been individually enabled by the interrupt enable bits in their associated control registers are globally enabled Note Traps are non maskable and are therefore not affected by the IEN bit Semiconductor Group 5 10 Interrupt and Trap Functions C167 SIEMENS 5 2 Operation of the PEC Channels The C167 s Peripheral Event Controller PEC provides 8 PEC service channels which move a single byte or word between two locations in segment 0 data pages 3 0 This is the fastest possible interrupt response and in many cases is sufficient to service the respective peripheral request eg serial channels A D converter etc Each channel is controlled by a dedicated PEC Channel Counter Control register PECCx and a pair of pointers for source SRCPx and destination DSTPx of the data transfer The PECC registers control the action that is performed by the respective PEC channel PECCx FECy 624 see table SFR Reset Value 0000 15 14 11 7 6 5 4 3 2 1 0 13 12 10 9 8 rw rw rw Bit Function COUNT PEC Transfer Count Counts PEC transfers and influences the channel s action see table below BWT Byte Word Transfer Selection 0 Transfer a Word 1 Transfer a Byte INC Increment Control Modification of SRCPx or DSTPx 0 0 Pointers are not modified 0 1
40. vector associated with the requesting source the CSP is cleared in case of segmentation and the first instruction of the service routine is fetched from the respective vector location which is expected to branch to the service routine itself The data page pointers and the context pointer are not affected When the interrupt service routine is left RETI is executed the status information is popped from the system stack in the reverse order taking into account the value of bit SGTDIS Context Switching An interrupt service routine usually saves all the registers it uses on the stack and restores them before returning The more registers a routine uses the more time is wasted with saving and restoring The C167 allows to switch the complete bank of CPU registers GPRs with a single instruction so the service routine executes within its own separate context The instruction SCXT CP New Bank pushes the content of the context pointer CP on the system stack and loads CP with the immediate value New Bank which selects a new register bank The service routine may now use its own registers This register bank is preserved when the service routine terminates ie its contents are available on the next call Before returning RETI the previous CP is simply POPped from the system stack which returns the registers to the original bank Note The first instruction following the SCXT instruction must not use a GPR Resources that a
41. 0000 WDT FEAE 574 Watchdog Timer Register read only 0000 SOTBUF FEBO 584 Serial Channel 0 Transmit Buffer Register 0000 SORBUF FEB2y 594 Serial Channel 0 Receive Buffer Register XXXXy read only SOBG FEB4y SAY Serial Channel 0 Baud Rate Generator Reload 00004 Register PECCO FECO 60 PEC Channel 0 Control Register 00004 PECC1 FEC2 1614 PEC Channel 1 Control Register 0000 PECC2 FEC4 1624 PEC Channel 2 Control Register 0000 PECC3 FEC6 63y PEC Channel 3 Control Register 0000 PECCA FEC8 644 PEC Channel 4 Control Register 00004 PECC5 FECA 65y PEC Channel 5 Control Register 00004 PECC6 FECC 66 PEC Channel 6 Control Register 0000 PECC7 FECE 67y PEC Channel 7 Control Register 0000 POL b FFOO 804 Port 0 Low Register Lower half of PORTO 004 POH b FFO2 814 Port 0 High Register Upper half of PORTO 004 P1L b FF04 824 Port 1 Low Register Lower half of PORT1 00 P1H b FFO6 834 Port 1 High Register Upper half of PORT1 00H BUSCONO b FFOC 864 Bus Configuration Register 0 00004 MDC b FFOE 874 CPU Multiply Divide Control Register 0000 PSW b FF104 884 CPU Program Status Word 0000 SYSCON b FF124 89 CPU System Configuration Register 0xxo BUSCON1 b FF14 8Ay Bus Configuration Register 1 0000 BUSCON b FF16 8By Bus Configuration Register 2 0000 BUSCONS b FF18 8Cy Bus Configuration Register 3 0000 BUSCONA b FF1A 8D Bus Configuration Register 4 00004 ZEROS b FF1C4 8Ey Constant Value 0 s Register read onl
42. 1 FFy 25 6 us 1 6 ms 00 6 55 ms 419 ms Note For safety reasons the user is advised to rewrite WDTCON each time before the watchdog timer is serviced Semiconductor Group 12 3 SIEMENS The Bootstrap Loader C167 13 The Bootstrap Loader The built in bootstrap loader of the C167 provides a mechanism to load the startup program which is executed after reset via the serial interface In this case no external ROM memory or an internal ROM is required for the initialization code starting at location 00 0000 The bootstrap loader moves code data into the internal RAM but it is also possible to transfer data via the serial interface into an external RAM using a second level loader routine ROM memory internal or external is not necessary However it may be used to provide lookup tables or may provide core code ie a set of general purpose subroutines eg for IO operations number crunching system initialization etc 32 bytes 6 Int Boot ROM BSL routine user software 1 BSL initialization time gt 2us 9 fopy 20 MHz 2 Zero byte 1 start bit eight 0 data bits 1 stop bit sent by host 3 Identification byte sent by C167 4 32 bytes of code data sent by host Caution TxDO is only driven a certain time after reception of the zero byte 2 5us fcpu 20 MHZ 9 Internal Boot ROM Figure 13 1 Bootstrap Loader Sequence The Bootstrap Loader may be used to load the complete application s
43. 1 group priority 3 level 1 group priority 3 0001 00 CPU interrupt CPU interrupt level 1 group priority O level 1 group priority 0 0000 XX No service No service Note All requests on levels 13 1 cannot initiate PEC transfers They are always serviced by an interrupt service routine No PECC register is associated and no COUNT field is checked Interrupt Control Functions in the PSW The Processor Status Word PSW is functionally divided into 2 parts the lower byte of the PSW basically represents the arithmetic status of the CPU the upper byte of the PSW controls the interrupt system of the C167 and the arbitration mechanism for the external bus interface Note Pipeline effects have to be considered when enabling disabling interrupt requests via modifications of register PSW see chapter The Central Processing Unit Semiconductor Group 5 9 SIEMENS Interrupt and Trap Functions C167 PSW FF10 88 SFR Reset Value 0000 15 14 13 12 11i 0 10 9 8 7 6 5 4 3 2 1 HLD MUL rw rw rw rw rw rw rw rw rw rw Bit Function N C V Z E CPU status flags Described in section The Central Processing Unit MULIP USRO Define the current status of the CPU ALU multiplication unit HLDEN HOLD Enable Enables External Bus Arbitration 0 Bus arbitration disabled P6 7 P6 5 may be used for general purpose IO 1 Bus arbitration enabled P6 7 P6 5 serve as BREQ HLDA HOLD resp ILVL
44. 20 MHz CPU clock The timer is counting downwards and can be started or stopped through the global enable bit SSCEN in register SSCCON Register SSCBR is the dual function Baud Rate Generator Reload register Reading SSCBR while the SSC is enabled returns the content of the timer Reading SSCBR while the SSC is disabled returns the programmed reload value In this mode the desired reload value can be written to SSCBR Note Never write to SSCBR while the SSC is enabled Semiconductor Group 11 10 SIEM ENS The High Speed Synchronous Serial Interface C167 The formulas below calculate either the resulting baud rate for a given reload value or the required reload value for a given baudrate fopu fopu SSCBR LL 1 Besc EET 2 Baudratessc lt SSCBR gt 1 lt SSCBR gt represents the content of the reload register taken as unsigned 16 bit integer The maximum baud rate that can be achieved when using a CPU clock of 20 MHz is 5 MBaud The table below lists some possible baud rates together with the required reload values and the resulting bit times assuming a CPU clock of 20 MHz Baud Rate Bit Time Reload Value Reserved Use a reload value gt 0 00004 5 MBaud 200 ns 00014 9 9 MBaud 300 ns 0002 2 5 MBaud 400 ns 0003 2 0 MBaud 500 ns 0004 1 0 MBaud 1 us 00094 100 KBaud 10 us 00634 10 KBaud 100 us 03E7y 1 0 KBaud 1 ms 270Fy 152 6 Baud 6 6 ms FEPE
45. 5 MHz see detailed description The minimum values depend on the width 16 bit and the resolution CLK 1 or CLK 64 of the PWM timers The maximum values assume that the PWM output signal changes with every cycle of the respective timer In a real application the maximum PWM frequency will depend on the required resolution of the PWM output signal Ports amp Direction Control Data Registers Counter Registers Control Registers and Alternate Functions Interrupt Control PWMCONO PWMCON 1 POUTO P7 0 PWMIC E POUT1 P7 1 POUT2 P7 2 POUT3 P7 3 Port 7 Open Drain Control Register PPx PWM Period Register x Port 7 Direction Control Register PWx PWM Pulse Width Register x Port 7 Data Register PTx PWM Counter Register x PWM Interrupt Control Register PWMCONx PWM Control Register 0 1 Figure 15 1 SFRs and Port Pins Associated with the PWM Module The Pulse Width Modulation Module consists of 4 independent PWM channels Each channel has a 16 bit up down counter PTx a 16 bit period register PPx with a shadow latch a 16 bit pulse width register PWx with a shadow latch two comparators and the necessary control logic The operation of all four channels is controlled by two common control registers PWMCONO and PWMCON1 and the interrupt control and status is handled by one interrupt control register PWMIC which is also common for all channels Semiconductor Group 15 1 SIEMENS The Pulse Width Modulation Module C167 Clock 1 Up Dow C
46. 6 0000 CC6IC b FF84 C24 CAPCOM Register 6 Interrupt Control Register 0000 CC7 FE8Ey 474 CAPCOM Register 7 0000 CC7IC b FF86 C34 CAPCOM Register 7 Interrupt Control Register 0000 CC8 FE90 484 CAPCOM Register 8 0000 CC8IC b FF88 C4y CAPCOM Register 8 Interrupt Control Register 0000 CC9 FE924 49 CAPCOM Register 9 0000 CC9IC b FF8A C54 CAPCOM Register 9 Interrupt Control Register 0000 CC10 FE94 4Ay CAPCOM Register 10 0000 CC10IC b FF8C C6y CAPCOM Register 10 Interrupt Control Register 0000 CC11 FE96 4By CAPCOM Register 11 0000 CC11IC b FF8E C74 CAPCOM Register 11 Interrupt Control Register 0000 CC12 FE98 4Cy CAPCOM Register 12 00004 CC121C b FF90 C84 CAPCOM Register 12 Interrupt Control Register 0000 CC13 FE9A 4Dy CAPCOM Register 13 0000 CC13IC b FF92 C94 CAPCOM Register 13 Interrupt Control Register 0000 CC14 FE9C 4E CAPCOM Register 14 0000 CC14IC b FF94 CAy CAPCOM Register 14 Interrupt Control Register 0000 CC15 FE9E 4Fu CAPCOM Register 15 0000 CC15IC b FF96 CBy CAPCOM Register 15 Interrupt Control Register 0000 CC16 FE60 304 CAPCOM Register 16 0000 CC16IC b F1604 E BO CAPCOM Register 16 Interrupt Control Register 0000 CC17 FE62y 314 CAPCOM Register 17 00004 Semiconductor Group 20 5 SIEMENS The Register Set C167 Name Physical 8 Bit Description Reset Address
47. 64 KByte MCD02227 Figure 3 1 Memory Areas and Address Space Semiconductor Group 3 1 SIEMENS Memory Organization C167 Most internal memory areas are mapped into segment 0 the system segment The upper 4 KByte of segment 0 00 F000 00 FFFF hold the Internal RAM and Special Function Register Areas SFR and ESFR The lower 32 KByte of segment 0 00 0000 00 7F FF may be occupied by a part of the on chip ROM or Flash memory and is called the Internal ROM area This ROM area can be remapped to segment 1 01 0000 01 7FFF j to enable external memory access in the lower half of segment 0 or the internal ROM may be disabled at all Code and data may be stored in any part of the internal memory areas except for the SFR blocks which may be used for control data but not for instructions Note Accesses to the internal ROM area on ROMless devices will produce unpredictable results Bytes are stored at even or odd byte addresses Words are stored in ascending memory locations with the low byte at an even byte address being followed by the high byte at the next odd byte address Double words code only are stored in ascending memory locations as two subsequent words Single bits are always stored in the specified bit position at a word address Bit position O is the least significant bit of the byte at an even byte address and bit position 15 is the most significant bit of the byte at the next odd byte address Bit address
48. 9 31 Tri State 8 13 T6CON 9 18 Watchdog 2 14 12 1 17 4 TFR 5 25 WDT 12 1 Threshold 6 2 WDTCON 12 2 Timer 2 14 9 1 9 16 Auxiliary Timer 9 8 9 23 X CAF GEMATI XBUS 2 9 8 29 Concatenation 9 11 9 26 XRAM on chip 3 9 Core Timer 9 3 9 18 Tools 1 6 Traps 5 5 5 24 Z Tri State Time 8 13 ZEROS 4 29 Semiconductor Group 1 6
49. Address Value CC171IC b F1624 E Bly CAPCOM Register 17 Interrupt Control Register 00004 CC18 FE64 324 CAPCOM Register 18 00004 CC18IC b F164 E B2 CAPCOM Register 18 Interrupt Control Register 0000 CC19 FE66 33H CAPCOM Register 19 00004 CC19IC b F166 E B3y CAPCOM Register 19 Interrupt Control Register 00004 CC20 FE68 344 CAPCOM Register 20 00004 CC20IC b F168 E B44 CAPCOM Register 20 Interrupt Control Register 00004 CC21 FE6AH 35H CAPCOM Register 21 0000 CC21IC b F16A E B5y CAPCOM Register 21 Interrupt Control Register 00004 CC22 FE6Cy 36 CAPCOM Register 22 0000 CC221C b F16C E B6 CAPCOM Register 22 Interrupt Control Register 0000 CC23 FE6E 374 CAPCOM Register 23 00004 CC23IC b FI6E E B7y CAPCOM Register 23 Interrupt Control Register 00004 CC24 FE704 38H CAPCOM Register 24 0000 CC24IC b F1704 E B8 CAPCOM Register 24 Interrupt Control Register 0000 CC25 FE72y 394 CAPCOM Register 25 00004 CC25IC b F172 E B9j CAPCOM Register 25 Interrupt Control Register 00004 CC26 FE74 3AH CAPCOM Register 26 0000 CC261C b F174 E BA CAPCOM Register 26 Interrupt Control Register 0000 CC27 FE76 3By CAPCOM Register 27 0000 CC27IC b F176 E BBy CAPCOM Register 27 Interrupt Control Register 0000 CC28 FE78 3Cy CAPCOM Register 28 0000 CC28IC b F1784 E BC CAPCOM Register 28 Interrupt Control Register 0000 CC29 FE7A 3D CAPCOM Register 29 0000 CC29IC b F1844 E C2 CAPCOM Register 29 Interrupt Control Register 00
50. Arbitration Register msg n UUUU LAR EFn4 X CAN Lower Arbitration Register msg n UUUU MCFG EFn6 X CAN Message Configuration Register msg n UU PTO F030 E 18 PWM Module Up Down Counter 0 0000 PT1 FO32y4 E 19 PWM Module Up Down Counter 1 0000 PT2 F034 E 1Ay PWM Module Up Down Counter 2 0000 PT3 F036 E 1By PWM Module Up Down Counter 3 0000 PPO FO38y E 1Cy PWM Module Period Register 0 00004 PP1 FO3AW E 1Dy PWM Module Period Register 1 0000 PP2 FO3Cy E 1Ey PWM Module Period Register 2 00004 PP3 FOSE E 1Fy PWM Module Period Register 3 00004 T7 F050 E 28 CAPCOM Timer 7 Register 00004 T8 F052 E 29 CAPCOM Timer 8 Register 0000 T7REL F0544 Ej 2Ay CAPCOM Timer 7 Reload Register 0000 T8REL F056 E 2By CAPCOM Timer 8 Reload Register 0000 ADDAT2 FOAO E 50 A D Converter 2 Result Register 0000 SSCTB FOBO E 58 SSC Transmit Buffer write only 00004 SSCRB FOB2 E 59 SSC Receive Buffer read only XXXXy Semiconductor Group 20 12 SIEMENS The Register Set C167 Name Physical 8 Bit Description Reset Address Address Value SSCBR FOB4 E 5Ay SSC Baudrate Register 0000 DPOL b F100 E 80 POL Direction Control Register 00H DPOH b F102 E 81 POH Direction Control Register 00 DP1L b F104 E 824 P1L Direction Control Register 004 DP1H b F106 E 83y P1H Direction Control Register 00 4 RPOH
51. B24 SFR Reset Value 00 7 rw 15 14 13 12 11 10 9 8 6 1 0 TAIR TAIE ILVL GLVL rw rw Note Please refer to the general Interrupt Control Register description for an explanation of the control fields Semiconductor Group 9 15 SIEMENS The General Purpose Timer Units C167 9 2 Timer Block GPT2 From a programmer s point of view the GPT2 block is represented by a set of SFRs as summarized below Those portions of port and direction registers which are used for alternate functions by the GPT2 block are shaded Ports amp Direction Control Data Registers Control Registers Interrupt Control Alternate Functions T5CON T6CON CAPREL T5IN P5 13 T5EUD P5 11 T6IN P5 12 TeEUD P5 10 T T P Port 3 Direction Control Register T6 GPT2 Timer 6 Register Port 3 Data Register CAPREL GPT2 Capture Reload Register Port 5 Data Register T5IC GPT2 Timer 5 Interrupt Control Register GPT2 Timer 5 Control Register T6IC GPT2 Timer 6 Interrupt Control Register GPT2 Timer 6 Control Register CRIC GPT2 CAPREL Interrupt Control Register Figure 9 11 SFRs and Port Pins Associated with Timer Block GPT2 Timer block GPT2 supports high precision event control with a maximum resolution of 200 ns 20 MHz CPU clock It includes the two timers T5 and T6 and the 16 bit capture reload register CAPREL Timer T6 is referred to as the core timer and T5 is referred to as the auxiliary timer of GPT2 Each timer has an alternate
52. Baudrate Register 0000 SSCCON b FFB2 D94 SSC Control Register 0000 SSCEIC b FF76 BBuy SSC Error Interrupt Control Register 0000 SSCRB FOB2 E 59 SSC Receive Buffer read only XXXXy SSCRIC__b FF74 BAy SSC Receive Interrupt Control Register 0000 SSCTB FOBO E 58 SSC Transmit Buffer write only 0000 SSCTIC b FF724 B94 SSC Transmit Interrupt Control Register 00004 STKOV FE144 OAH CPU Stack Overflow Pointer Register FAOO STKUN FE16y OBy CPU Stack Underflow Pointer Register FCOO SYSCON b FF124 894 CPU System Configuration Register OXX0 TO FE50y 284 CAPCOM Timer 0 Register 00004 TO1CON b FF50 A84 CAPCOM Timer 0 and Timer 1 Control Register 00004 TOIC b FF9Cy CEy CAPCOM Timer 0 Interrupt Control Register 0000 TOREL FE54 2A CAPCOM Timer 0 Reload Register 00004 Semiconductor Group 20 9 SIEMENS The Register Set C167 Name Physical 8 Bit Description Reset Address Address Value T1 FE524 294 CAPCOM Timer 1 Register 00004 T1IC b FF9E CFy CAPCOM Timer 1 Interrupt Control Register 00004 T1REL FE56 2Buy CAPCOM Timer 1 Reload Register 0000 T2 FE40y 204 GPT1 Timer 2 Register 00004 T2CON b FF40y Ady GPT1 Timer 2 Control Register 0000 T2lC b FF60 Boy GPT1 Timer 2 Interrupt Control Register 00004 T3 FE424 214 GPT1 Timer 3 Register 00004 T3CON b FF424 Aly GPT1 Timer 3 Control Register 0000 T3IC b FF
53. CMOS microcontrollers without the constraints of backward compatibility Of course the architecture of the 16 bit microcontroller family pursues successfull hardware and software concepts which have been established in Siemens s popular 8 bit controller families About this Manual This manual describes the functionality of a number of 16 bit microcontrollers of the Siemens C166 family the socalled C167 class As these microcontrollers provide a great extent of identical functionality it makes sense to describe a superset of the provided features For this reason some sections of this manual do not refer to all the C167 derivatives that are offered eg devices without a CAN interface These sections contain respective notes wherever possible The descriptions in this manual refer to the following derivatives of the C167 class C167CR LM Version with PLL 2 KByte XRAM CAN module C167CR 4RM Version with PLL 2 KByte XRAM 32 KByte ROM CAN module C167CR 16RM Version with PLL 2 KByte XRAM 128 KByte ROM CAN module C167CR 16FM Version with PLL 2 KByte XRAM 128 KByte Flash memory CAN module e C167SR LM Version with PLL 2 KByte XRAM C167S 4RM Version with PLL 32 KByte ROM e C167 LM Basic version This manual is valid for the versions with on chip ROM or Flash memory of the mentioned derivatives as well as for the romless versions Of course it refers to all devices of the different available temperature ranges and
54. Call and Loop Processing Due to the high percentage of branching in controller applications branch instructions have been optimized to require one extra machine cycle only when a branch is taken This is implemented by precalculating the target address while decoding the instruction To decrease loop execution overhead three enhancements have been provided The first solution provides single cycle branch execution after the first iteration of a loop Thus only one machine cycle is lost during the execution of the entire loop In loops which fall through upon completion no machine cycles are lost when exiting the loop No special instructions are required to perform loops and loops are automatically detected during execution of branch instructions The second loop enhancement allows the detection of the end of a table and avoids the use of two compare instructions embedded in loops One simply places the lowest negative number at the end of the specific table and specifies branching if neither this value nor the compared value have been found Otherwise the loop is terminated if either condition has been met The terminating condition can then be tested The third loop enhancement provides a more flexible solution than the Decrement and Skip on Zero instruction which is found in other microcontrollers Through the use of Compare and Increment or Decrement instructions the user can make comparisons to any value This allows loop counters
55. Capture Compare Units C167 Contents of Ty FFFF Compare Value cv2 Compare Value cv1 00004 l l l i l l i l l Reload Value lt TyREL gt l Interrupt Requests Ius CCxIR CCxIR hys CCxIR CCxIR uL State ot CCxlO l l l l 1 A rm t gt MCT02023 x 23 16 7 0 y 0 1 7 8 z 31 24 15 8 Figure 14 11 Timing Example for Double Register Compare Mode 14 6 Capture Compare Interrupts Upon a capture or compare event the interrupt request flag CCxIR for the respective capture compare register CCx is set to 1 This flag can be used to generate an interrupt or trigger a PEC service request when enabled by the interrupt enable bit CCxIE Capture interrupts can be regarded as external interrupt requests with the additional feature of recording the time at which the triggering event occurred see also section External Interrupts Each of the 32 capture compare registers CCO CC31 has its own bitaddressable interrupt control register CCOIC CC311C and its own interrupt vector CCOINT CC31INT These registers are organized the same way as all other interrupt control registers The figure below shows the basic register layout and the table lists the associated addresses CCxIC See Table SFR ESFR Reset Value 00 a ee Seo Se wi rw rw rw Note Please refer to the general Interrupt Control Register description for an explanation
56. Central Processing Unit CPU C167 4 4 CPU Special Function Registers The core CPU requires a set of Special Function Registers SFRs to maintain the system state information to supply the ALU with register addressable constants and to control system and bus configuration multiply and divide ALU operations code memory segmentation data memory paging and accesses to the General Purpose Registers and the System Stack The access mechanism for these SFRs in the CPU core is identical to the access mechanism for any other SFR Since all SFRs can simply be controlled by means of any instruction which is capable of addressing the SFR memory space a lot of flexibility has been gained without the need to create a set of system specific instructions Note however that there are user access restrictions for some of the CPU core SFRs to ensure proper processor operations The instruction pointer IP and code segment pointer CSP cannot be accessed directly at all They can only be changed indirectly via branch instructions The PSW SP and MDC registers can be modified not only explicitly by the programmer but also implicitly by the CPU during normal instruction processing Note that any explicit write request via software to an SFR supersedes a simultaneous modification by hardware of the same register Note Any write operation to a single byte of an SFR clears the non addressed complementary byte within the specified SFR Non implemente
57. DP3 y 1 Port line P3 y is an output ODP3 F1C6j E3p ESFR Reset Value 00004 15 14 13 12 11 10 09 8 7 6 5 4 3 2 1 0 ODPS3 ODP3 ODP3 ODP3 ODP3 10 9 8 T4 6 rw i rw rw rw rw rw rw rw rw rw rw rw rw Bit Function ODP3 y Port 3 Open Drain control register bit y ODP3 y 0 Port line P3 y output driver in push pull mode ODP3 y 1 Port line P3 y output driver in open drain mode Semiconductor Group 6 15 SIEMENS Parallel Ports C167 Alternate Functions of Port 3 The pins of Port 3 serve for various functions which include external timer control lines the two serial interfaces and the control lines BHE WRH and CLKOUT The table below summarizes the alternate functions of Port 3 Port 3 Pin Alternate Function P3 0 TOIN CAPCOM Timer 0 Count Input P3 1 T6OUT Timer 6 Toggle Output P3 2 CAPIN GPT2 Capture Input P3 3 TSOUT Timer 3 Toggle Output P3 4 T3EUD Timer 3 External Up Down Input P3 5 T4IN Timer 4 Count Input P3 6 TSIN Timer 3 Count Input P3 7 T2IN Timer 2 Count Input P3 8 MRST SSC Master Receive Slave Transmit P3 9 MTSR SSC Master Transmit Slave Receive P3 10 TxDO ASCO Transmit Data Output P3 11 RxDO ASCO Receive Data Input P3 12 BHE WRH Byte High Enable Write High Output P3 13 SCLK SSC Shift Clock Input Output P3 14 No pin assigned P3 15 CLKOUT System Clock Output Alternate Function General Purpose Input Output Figure 6 10 Port 3 I
58. Due to the internal pipelining it is very difficult to determine the first instruction fetch that will use the new configuration Only change the configuration for address areas that are not currently accessed This applies to BUSCON registers as well as to ADDRSEL registers The usage of the BUSCON ADDRSEL registers is controlled via the issued addresses When an access code fetch or data is initiated the respective generated physical address defines if the access is made internally uses one of the address windows defined by ADDRSELA 1 or uses the default configuration in BUSCONO After initializing the active registers they are selected and evaluated automatically by interpreting the physical address No additional switching or selecting is necessary during run time except when more than the four address windows plus the default is to be used Switching from demultiplexed to multiplexed bus mode represents a special case The bus cycle is started by activating ALE and driving the address to Port 4 and PORT1 as usual if another BUSCON register selects a demultiplexed bus However in the multiplexed bus modes the address is also required on PORTO In this special case the address on PORTO is delayed by one CPU clock cycle which delays the complete multiplexed bus cycle and extends the corresponding ALE signal see figure below This extra time is required to allow the previously selected device via demultiplexed bus to release the dat
59. E 1Ay PWM Module Up Down Counter 2 0000 PT3 FO36 E 1By PWM Module Up Down Counter 3 0000 PWO FE30 184 PWM Module Pulse Width Register 0 00004 PW1 FE324 19 PWM Module Pulse Width Register 1 0000 Semiconductor Group 20 8 SIEMENS The Register Set C167 Name Physical 8 Bit Description Reset Address Address Value PW2 FE344 1Ay PWM Module Pulse Width Register 2 00004 PW3 FE36 1By PWM Module Pulse Width Register 3 0000 PWMCONO b FF30 984 PWM Module Control Register 0 0000 PWMCON1 b FF32 994 PWM Module Control Register 1 0000 PWMIC b F17Ep E BFy PWM Module Interrupt Control Register 00004 RPOH b F108 E 84 System Startup Configuration Register Rd only XXy SOBG FEB4 SAW Serial Channel 0 Baud Rate Generator Reload 00004 Register SOCON b FFBO D84 Serial Channel 0 Control Register 0000 SOEIC b FF70 B84 Serial Channel 0 Error Interrupt Control Register 00004 SORBUF FEB2y 594 Serial Channel 0 Receive Buffer Register XXXXy read only SORIC b FF6E B7y Serial Channel 0 Receive Interrupt Control 00004 Register SOTBIC b F19C E CE Serial Channel 0 Transmit Buffer Interrupt Control 00004 Register SOTBUF FEBOW 584 Serial Channel 0 Transmit Buffer Register 0000 SOTIC b FF6Cy B6y Serial Channel 0 Transmit Interrupt Control 0000 Register SP FE12y 09 CPU System Stack Pointer Register FCOOW SSCBR FOB4 E 5Ay SSC
60. E5y Port 4 Direction Control Register 00H DP6 b FFCE E7y Port 6 Direction Control Register 00H DP7 b FFD24 E94 Port 7 Direction Control Register 00H DP8 b FFD6 EB Port 8 Direction Control Register 004 DPPO FEOO 004 CPU Data Page Pointer O Register 10 bits 00004 DPP1 FE024 014 CPU Data Page Pointer 1 Register 10 bits 0001 DPP2 FE044 024 CPU Data Page Pointer 2 Register 10 bits 00024 DPP3 FEO6 034 CPU Data Page Pointer 3 Register 10 bits 00034 EXICON b F1iC0 E E0 External Interrupt Control Register 0000 LAR EFn44 X CAN Lower Arbitration Register msg n UUUU MCFG EFn6 X CAN Message Configuration Register msg n UU MCR EFnO X CAN Message Control Register msg n UUUU MDC b FFOE 874 CPU Multiply Divide Control Register 00004 MDH FEOCy 064 CPU Multiply Divide Register High Word 00004 MDL FEOE 074 CPU Multiply Divide Register Low Word 0000 ODP2 b F1C24 E E1y Port 2 Open Drain Control Register 00004 ODP3 b F1C64 E E3y Port 3 Open Drain Control Register 00004 ODP6 b F1CEp E E74 Port 6 Open Drain Control Register 004 ODP7 b F1D2 E E94 Port 7 Open Drain Control Register 00H Semiconductor Group 20 7 SIEMENS The Register Set C167 Name Physical 8 Bit Description Reset Address Address Value ODP8 b F1D6 E EBy Port 8 Open Drain Control Register 00H ONES b FF1E 8Fy Constant
61. Mode Input Edge Selection T21 TAI Triggering Edge for Counter Increment Decrement X00 None Counter Tx is disabled 0 0 1 Positive transition rising edge on TxIN 010 Negative transition falling edge on TxIN 01 1 Any transition rising or falling edge on TxIN 101 Positive transition rising edge of output toggle latch T3OTL 110 Negative transition falling edge of output toggle latch T3OTL 111 Any transition rising or falling edge of output toggle latch T3OTL Note Only state transitions of T3OTL which are caused by the overflows underflows of T3 will trigger the counter function of T2 T4 Modifications of T3OTL via software will NOT trigger the counter function of T2 T4 Semiconductor Group 9 10 SIEMENS The General Purpose Timer Units C167 For counter operation pin TxIN must be configured as input ie the respective direction control bit must be 0 The maximum input frequency which is allowed in counter mode is fopy 8 1 25 MHz fcpu 20 MHz To ensure that a transition of the count input signal which is applied to TxIN is correctly recognized its level should be held for at least 8 fcpy cycles before it changes Timer Concatenation Using the toggle bit T3OTL as a clock source for an auxiliary timer in counter mode concatenates the core timer T3 with the respective auxiliary timer Depending on which transition of T3OTL is selected to clock the auxiliary timer this concatenation for
62. Mode is off Note In emulation mode the direct drive clock option is selected with P0 15 POH 7 2 1 Adapt Mode Pin POL 1 ADP selects the Adapt Mode when low during reset In this mode the C167 goes into a passive state which is similar to its state during reset The pins of the C167 float to tristate or are deactivated via internal pullup pulldown devices as described for the reset state In addition also the RSTOUT pin floats to tristate rather than be driven low and the on chip oscillator is switched off This mode allows switching a C167 that is mounted to a board virtually off so an emulator may control the board s circuitry even though the original C167 remains in its place The original C167 also may resume to control the board after a reset sequence with POL 1 high Default Adapt Mode is off Note When XTAL1 is fed by an external clock generator while XTAL2 is left open this clock signal may also be used to drive the emulator device However if a crystal is used the emulator device s oscillator can use this crystal only if at least XTAL2 of the original device is disconnected from the circuitry the output XTAL2 will still be active in Adapt Mode Bootstrap Loader Mode Pin POL 4 BSL activates the on chip bootstrap loader when low during reset The bootstrap loader allows moving the start code into the internal RAM of the C167 via the serial interface ASCO The C167 will remain in bootstrap loader mode until a
63. P3 3 Interrupt gt TAIR Request Reload Register T4 MCB02037 Note Lines only affected by over underflows of T3 but NOT by software modifications of T3OTL Figure 9 9 GPT1 Timer Reload Configuration for PWM Generation Note Although it is possible it should be avoided to select the same reload trigger event for both auxiliary timers In this case both reload registers would try to load the core timer at the same time If this combination is selected T2 is disregarded and the contents of T4 is reloaded Semiconductor Group 9 13 SIEMENS The General Purpose Timer Units C167 Auxiliary Timer in Capture Mode Capture mode for the auxiliary timers T2 and T4 is selected by setting bit field TxM in the respective register TXCON to 101g In capture mode the contents of the core timer are latched into an auxiliary timer register in response to a signal transition at the respective auxiliary timer s external input pin TxIN The capture trigger signal can be a positive a negative or both a positive and a negative transition The two least significant bits of bit field Txl are used to select the active transition see table in the counter mode section while the most significant bit Txl 2 is irrelevant for capture mode It is recommended to keep this bit cleared Txl 2 0 Note When programmed for capture mode the respective auxiliary timer T2 or T4 stops independent of its run flag T2R or T4R E
64. PW1 FE32 19 SFR PTI F0324 194 ESFR PW2 FE34 1Ay SFR PT2 F0344 1A4 ESFR PW3 FE36 1B SFR PT3 F036 1B ESFR PPO F038 1C ESFR PP1 FO3Ay 1D ESFR PP2 F03C 1E ESFR Note These registers are not bit addressable PP3 FO3E4 1F ESFR Semiconductor Group 15 8 SIEMENS The Pulse Width Modulation Module C167 PWM Control Register PWMCONO Register PWMCONO controls the function of the timers of the four PWM channels and the channel specific interrupts Having the control bits organized in functional groups allows eg to start or stop all 4 PWM timers simultaneously with one bitfield instruction PWMCONO FF30 984 SFR Reset Value 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bit Function PTRx PWM Timer x Run Control Bit 0 Timer PTx is disconnected from its input clock 1 Timer PTx is running PTIx PWM Timer x Input Clock Selection 0 Timer PTx clocked with CLKcpy 1 Timer PTx clocked with CLKcpy 64 PIEx PWM Channel x Interrupt Enable Flag 0 Interrupt from channel x disabled 1 Interrupt from channel x enabled PIRx PWM Channel x Interrupt Request Flag 0 No interrupt request from channel x 1 Channel x interrupt pending must be reset via software Semiconductor Group 15 9 SIEMENS The Pulse Width Modulation Module C167 PWM Control Register PWMCON1 Regi
65. Roo Roc es Ed cera D x 14 4 14 2 CAPCOM Unit Timer Interrupts 0 00 cee eee 14 8 14 3 Capture Compare Registers 0 00 14 9 14 3 1 Selection of Capture Modes and Compare Modes 14 11 14 4 Capture Mode 1 9 3999 05a dere x ue Your 3 grips en dx cung Mu od aod nS wake 14 12 14 5 Gornpare Mod s ura ona sita qas ch cuo do sapra ti qe Re P CN Pedir t td 14 13 14 5 1 Double Register Compare Mode lllllll eee eee 14 18 14 6 Capture Compare Interrupts 0 0 eee 14 20 15 The Pulse Width Modulation Module 15 1 15 1 Operating Modes s 2 doin saca ed paced heating 2 he TUR EOD Ro Rea ia ded 2 15 2 15 2 PWM Module Registers slllllllllllllllllllleen 15 7 15 3 Interrupt Request Generation 0 0c ccc ees 15 11 15 4 PWM Output Signals 5 2 2 2 20614 x Perse 1er aah wanda e Bao ROI Ride E es 15 12 16 The Analog Digital Converter llus 16 1 16 1 Mode Selection and Operation 0000 eee eee 16 3 16 2 Conversion Timing Control 0 000 c eee eee 16 10 16 3 A D Converter Interrupt Control 0 0 0 cc eee 16 11 17 System Reset wise cio dE Y RYE Erud ee ELLE Tine 17 1 17 0 1 System Startup Configuration 0 0 00 ees 17 7 18 Power Reduction Modes lleeeeeesess 18 1 18 1 e quo snn oP ae era tf CA SAw Oa ose AMR ME ECEE 18 1 18 2 Power Down TID 4 3
66. SP register after each operation which pushes data onto the system stack eg PUSH and CALL instructions or interrupts and after each subtraction from the SP register If the content of the SP register is less than the content of the STKOV register a stack overflow hardware trap will occur Since the least significant bit of register STKOV is tied to 0 and bits 15 through 12 are tied to 1 by hardware the STKOV register can only contain values from F000 to FFFEy STKOV FE14 0A SFR Reset Value FA00 15 14 11 10 9 8 7 6 5 4 3 2 1 0 13 12 r r r r rw r Bit Function stkov Modifiable portion of register STKOV Specifies the lower limit of the internal system stack The Stack Overflow Trap entered when SP STKOV may be used in two different ways e Fatal error indication treats the stack overflow as a system error through the associated trap service routine Under these circumstances data in the bottom of the stack may have been overwritten by the status information stacked upon servicing the stack overflow trap Automatic system stack flushing allows to use the system stack as a Stack Cache for a bigger external user stack In this case register STKOV should be initialized to a value which represents the desired lowest Top of Stack address plus 12 according to the selected maximum stack size This considers the worst case that will occur when a stack overflow condition is detected just during entry i
67. SRL Ee ae ae EA ei Figure 4 3 Standard Branch Instruction Pipelining If a conditional branch is not taken there is no deviation from the sequential program flow and thus no extra time is required In this case the instruction after the branch instruction will enter the decode stage of the pipeline at the beginning of the next machine cycle after decode of the conditional branch instruction Semiconductor Group 4 4 SIEMENS The Central Processing Unit CPU C167 Cache Jump Instruction Processing The C167 incorporates a jump cache to optimize conditional jumps which are processed repeatedly within a loop Whenever a jump on cache is taken the extra time to fetch the branch target instruction can be saved and thus the corresponding cache jump instruction in most cases takes only one machine cycle This performance is achieved by the following mechanism Whenever a cache jump instruction passes through the decode stage of the pipeline for the first time and provided that the jump condition is met the jump target instruction is fetched as usual causing a time delay of one machine cycle In contrast to standard branch instructions however the target instruction of a cache jump instruction JMPA JMPR JB JBC JNB JNBS is additionally stored in the cache after having been fetched After each repeatedly following execution of the same cache jump instruction the jump target instruction is not fetched from progam memory but
68. Value 1 s Register read only FFFFy POL b FFO0O 804 Port 0 Low Register Lower half of PORTO 004 POH b FF02u 814 Port 0 High Register Upper half of PORTO 004 P1L b FF044 824 Port 1 Low Register Lower half of PORT1 00H P1H b FFO6 834 Port 1 High Register Upper half of PORT1 00H P2 b FFCO EO Port 2 Register 00004 P3 b FFC4 E2u Port 3 Register 00004 P4 b FFC8yu E44 Port 4 Register 8 bits 00H P5 b FFA2 D1 Port 5 Register read only XXXXy P6 b FFCC E6 Port 6 Register 8 bits 004 P7 b FFDO E84 Port 7 Register 8 bits 00H P8 b FFD4 EAy Port 8 Register 8 bits 00H PECCO FECO 160 PEC Channel 0 Control Register 0000 PECC1 FEC2 614 PEC Channel 1 Control Register 0000 PECC2 FEC4 1624 PEC Channel 2 Control Register 0000 PECC3 FEC6 63y PEC Channel 3 Control Register 00004 PECCA FEC8y 1644 PEC Channel 4 Control Register 0000 PECC5 FECA 1654 PEC Channel 5 Control Register 0000 PECC6 FECC 66 PEC Channel 6 Control Register 0000 PECC7 FECE 674 PEC Channel 7 Control Register 00004 PICON F1C44 E E24 Port Input Threshold Control Register 00004 PPO F038 E 1Cy PWM Module Period Register 0 00004 PP1 FOSA E 1Dyu PWM Module Period Register 1 00004 PP2 F03C E 1Ey PWM Module Period Register 2 00004 PP3 FOSE E 1Fy PWM Module Period Register 3 00004 PSW b FF104 884 CPU Program Status Word 0000 PTO F030 E 18 PWM Module Up Down Counter 0 0000 PT1 F032 4 E 19 PWM Module Up Down Counter 1 0000 PT2 F08344
69. Word 0000 CP FE10 084 CPU Context Pointer Register FCOO SP FE12y 09 CPU System Stack Pointer Register FCOO STKOV FE14 OAH CPU Stack Overflow Pointer Register FAO0 STKUN FE16 OBy CPU Stack Underflow Pointer Register FCOO ADDRSEL1 FE18 0Cy Address Select Register 1 0000 ADDRSEL2 FE1A ODy Address Select Register 2 00004 ADDRSEL3 FE1Cy OE Address Select Register 3 0000 ADDRSEL4 FE1E OF Address Select Register 4 0000 PWO FE30 184 PWM Module Pulse Width Register 0 00004 PW1 FE32y 19 PWM Module Pulse Width Register 1 00004 PW2 FE34 1Ay PWM Module Pulse Width Register 2 0000 PW3 FE36 1By PWM Module Pulse Width Register 3 00004 T2 FE40 204 GPT1 Timer 2 Register 0000 T3 FE424 21u GPT1 Timer 3 Register 0000 T4 FE444 224 GPT1 Timer 4 Register 0000 T5 FE46 23H GPT2 Timer 5 Register 0000 T6 FE48 244 GPT2 Timer 6 Register 0000 CAPREL FE4Ay 25H GPT2 Capture Reload Register 00004 TO FE50y 284 CAPCOM Timer 0 Register 0000 T1 FE52 294 CAPCOM Timer 1 Register 0000 Semiconductor Group 20 14 SIEMENS The Register Set C167 Name Physical 8 Bit Description Reset Address Address Value TOREL FE54y 2AH CAPCOM Timer 0 Reload Register 0000 TIREL FE56 2Bu CAPCOM Timer 1 Reload Register 00004 CC16 FE60 304 CAPCOM Register 16 0000 CC17 FE624 314 CAPCOM Register 17 0000 CC18 FE644 324 CAPCOM Register
70. a Stack Cache for a bigger external user stack In this case register STKUN should be initialized to a value which represents the desired highest Bottom of Stack address More details about the stack underflow trap service routine and virtual stack management are given in chapter System Programming Scope of Stack Limit Control The stack limit control realized by the register pair STKOV and STKUN detects cases where the stack pointer SP is moved outside the defined stack area either by ADD or SUB instructions or by PUSH or POP operations explicit or implicit ie CALL or RET instructions This control mechanism is not triggered ie no stack trap is generated when the stack pointer SP is directly updated via MOV instructions e the limits of the stack area STKOV STKUN are changed so that SP is outside of the new limits Semiconductor Group 4 26 SIEMENS The Central Processing Unit CPU C167 The Multiply Divide High Register MDH This register is a part of the 32 bit multiply divide register which is implicitly used by the CPU when it performs a multiplication or a division After a multiplication this non bit addressable register represents the high order 16 bits of the 32 bit result For long divisions the MDH register must be loaded with the high order 16 bits of the 32 bit dividend before the division is started After any division register MDH represents the 16 bit remainder MDH FEOC 064 SFR Reset Value
71. active low until the end of the initialization routine see description RSTOUT 3 Internal Reset Condition 9 Initialization E 7 Internal Reset Condition Initialization MCS02258 When the internal reset condition is prolongued by RSTIN the activation of the output signals is delayed until the end of the internal reset condition 1 Current bus cycle is completed or aborted 2 Switches asynchronously with RSTIN synchronously upon software or watchdog reset 3 The reset condition ends here The C167 starts program execution 4 Activation of the IO pins is controlled by software 5 Execution of the EINIT instruction 6 The shaded area designates the internal reset sequence which starts after synchronization of RSTIN Figure 17 2 Reset Input and Output Signals Semiconductor Group 17 3 SIEMENS System Reset C167 Reset Output Pin The RSTOUT pin is dedicated to generate a reset signal for the system components besides the controller itself RSTOUT will be driven active low at the begin of any reset sequence triggered by hardware the SRST instruction or a watchdog timer overflow RSTOUT stays active low beyond the end of the internal reset sequence until the protected EINIT End of Initialization instruction is executed see figure above This allows the complete configuration of the controller including its o
72. address output is selected for PORT1 During external accesses in demultiplexed bus modes PORT1 outputs the 16 bit intra segment address as an alternate output function During external accesses in multiplexed bus modes when no BUSCON register selects a demultiplexed bus mode PORT1 is not used and is available for general purpose IO Alternate Function P1H 7 CC27l0 P1H 6 CC2610 P1H 5 CC2510 P1H 4 CC2410 P1H 3 P1H 2 P1H 1 P1H 0 P1L 7 P1L 6 P1L 5 P1L 4 P1L 3 P1L 2 P1L 1 P1L 0 General Purpose 8 16 bit CAPCOM2 Input Output Demux Bus Capture Inputs Figure 6 6 PORTI1 IO and Alternate Functions When an external bus mode is enabled the direction of the port pin and the loading of data into the port output latch are controlled by the bus controller hardware The input of the port output latch is disconnected from the internal bus and is switched to the line labeled Alternate Data Output via a multiplexer The alternate data is the 16 bit intrasegment address While an external bus mode is enabled the user software should not write to the port output latch otherwise unpredictable results may occur When the external bus modes are disabled the contents of the direction register last written by the user becomes active Semiconductor Group 6 9 SIEMENS Parallel Ports C167 The figure below shows the structure of a PORT1 pin ZN Write uA DP1L y M 1 we MUX gt rection Read DP1H y DP1L
73. aid eed eee eae ea 9 16 9 2 1 GPi2 Core Timer T6 3 o 34 oss phe eels ooo ees seen ee EE 9 18 9 2 2 GPT2 Auxiliary Timer T5 3 4 arce ana een ay wea Oates Om eng 9 23 9 2 3 Interrupt Control for GPT2 Timers and CAPREL 9 31 10 The Asynchronous Synchronous Serial Interface 10 1 10 1 Asynchronous Operation aea ex ER REESE RES ERI ed EE SEX 10 4 10 2 Synchronous Operation s dete a ea 379 RIO CR ICT tee tr me 10 8 10 3 Hardware Error Detection Capabilities 0000000 10 10 10 4 ASCO Baud Rate Generation 0 000 eee 10 10 10 ASCO Interrupt Control 2 0 else 10 12 11 The High Speed Synchronous Serial Interface 11 1 11 1 Full Duplex Operation wens nthe 94 3 AF e aet ea eae ase aries ie des AD 11 6 11 2 Half Duplex Operation ta o ee oir Eo oe Sa PSP See RNC ee 11 8 11 3 Baud Rate Generation llli 11 10 Semiconductor Group l 2 SIEMENS d Table of Contents Page 11 4 Error Detection Mechanisms a35 a are tope ori d weed herd cows ACRRUR 1 11 12 11 5 SSC Interrupt Control ciao acn ananuna aa Eck Re o er o aic a ea 11 14 12 The Watchdog Timer WDT eeeeeeseeeese 12 1 12 0 1 Operation of the Watchdog Timer 00 cee eee eee 12 2 13 The Bootstrap Loader ce rr RII IRI I 13 1 14 The Capture Compare Units lesssss 14 1 14 1 The CAPCOM Timers 54 ses dax dog x tou er o
74. an either absolutely or indirectly addressed subroutine within the current code segment Unconditional calling of a relatively addressed subroutine within the current code segment Unconditional calling of an absolutely addressed subroutine within any code segment Unconditional calling of an absolutely addressed subroutine within the current code segment plus an additional pushing of a selectable register onto the system stack Unconditional branching to the interrupt or trap vector jump table in code segment 0 Return Instructions Returning from a subroutine within the current code segment Returning from a subroutine within any code segment Returning from a subroutine within the current code segment plus an additional popping of a selectable register from the system stack Returning from an interrupt service routine Semiconductor Group 21 3 JMPA JMPS JB JBC CALLA CALLR CALLS PCALL TRAP RET RETS RETP RETI JMPI JMPR JNB JNBS CALLI SIEMENS Instruction Set Summary C167 System Control Instructions Resetting the C167 via software SRST Entering the Idle mode IDLE Entering the Power Down mode PWRDN Servicing the Watchdog Timer SRVWDT Disabling the Watchdog Timer DISWDT Signifying the end of the initialization routine pulls pin RSTOUT high and disables the effect of any later execution of a DISWDT instruction EINIT Miscellaneous Null ope
75. are MTSR MRST RxDO and SCLK Note Enabling the CLKOUT function automatically enables the P3 15 output driver Setting bit DP3 15 1 is not required Semiconductor Group 6 17 SIEMENS Parallel Ports C167 S N Write p Open Drain Read ODP3 y Write DP3 y Direction Read DP3 y Q 5 350 5 lt Alternate Write P3 y vv Port Output gt P k P3 Latch Output y c Ww n Buffer Read P3 y y Clock F Y npu ey i J Alternate Data Input MCB02229 Figure 6 11 Block Diagram of a Port 3 Pin with Alternate Input or Alternate Output Function Semiconductor Group 6 18 SIEMENS Parallel Ports C167 Pin P3 12 BHE WRH is one more pin with an alternate output function However its structure is slightly different see figure below because after reset the BHE or WRH function must be used depending on the system startup configuration In these cases there is no possibility to program any port latches before Thus the appropriate alternate function is selected automatically If BHE WRH is not used in the system this pin can be used for general purpose IO by disabling the alternate function BYTDIS 1 WRCFG 0 Write DP3 x 4 U 9 1 Directi MUX irection Read DP3 x Alternate Function lt Enable P3 12 BHE ae Alternate P3 15 CLKOUT Port Output Output Latch Buffer Read P3 x A
76. be selected before the execution of EINIT Semiconductor Group 17 6 SIEMENS System Reset C167 System Startup Configuration Although most of the programmable features of the C167 are either selected during the initialization phase or repeatedly during program execution there are some features that must be selected earlier because they are used for the first access of the program execution eg internal or external start selected via EA These selections are made during reset via the pins of PORTO which are read at the end of the internal reset sequence During reset internal pullup devices are active on the PORTO lines so their input level is high if the respective pin is left open or is low if the respective pin is connected to an external pulldown device With the coding of the selections as shown below in many cases the default option ie high level can be used The value on the upper byte of PORTO POH is latched into register RPOH upon reset the value on the lower byte POL directly influences the BUSCONO register bus mode or the internal control logic of the C167 H 7 H6 H5 H4 H3 H2 H1 H0 L7 L6 L5 L4 L3 L2 L1 L ees See Sees Internal Control Logic Only on hardware reset Clock Port 4 Port 6 Generator Logic Logic SYSCON BUSCONO Figure 17 3 PORTO Configuration during Reset The pins that control the operation of the internal control logic and the reserved pins are evaluated only during a hardw
77. busline related bit timing according to the CAN protocol The BTL synchronizes on a recessive to dominant busline transition at Start of Frame hard synchronization and on any further recessive to dominant busline transition if the CAN controller itself does not transmit a dominant bit resynchronization The BTL also provides programmable time segments to compensate for the propagation delay time and for phase shifts and to define the position of the Sample Point in the bit time The programming of the BTL depends on the baudrate and on external physical delay times Semiconductor Group 23 3 SIEMENS The On Chip CAN Interface C167 Intelligent Memory The Intelligent Memory CAM RAM Array provides storage for up to 15 message objects of maximum 8 data bytes length Each of these objects has a unique identifier and its own set of control and status bits After the initial configuration the Intelligent Memory can handle the reception and transmission of data without further CPU actions Organization of Registers and Message Objects All registers and message objects of the CAN controller are located in the special CAN address area of 256 bytes which is mapped into segment 0 and uses addresses 00 EF00 through OO0 EFFF All registers are organized as 16 bit registers located on word addresses However all registers may be accessed bytewise in order to select special actions without effecting other mechanisms Note The addres
78. by hardware are marked with a shaded access box Semiconductor Group 20 1 SIEMENS The Register Set C167 20 1 CPU General Purpose Registers GPRs The GPRs form the register bank that the CPU works with This register bank may be located anywhere within the internal RAM via the Context Pointer CP Due to the addressing mechanism GPR banks can only reside within the internal RAM All GPRs are bit addressable Name Physical 8 Bit Description Reset Address Address Value RO CP 0 FOy CPU General Purpose Word Register RO UUUU R1 CP 2 Fiy CPU General Purpose Word Register R1 UUUU R2 CP 4 F2y CPU General Purpose Word Register R2 UUUU R3 CP 6 F3y CPU General Purpose Word Register R3 UUUU RA CP 8 F4y CPU General Purpose Word Register R4 UUUU R5 CP F54 CPU General Purpose Word Register R5 UUUU 10 R6 CP F64 CPU General Purpose Word Register R6 UUUU 12 R7 CP F7y CPU General Purpose Word Register R7 UUUU 14 R8 CP F8y CPU General Purpose Word Register R8 UUUU 16 R9 CP F9 CPU General Purpose Word Register R9 UUUU 18 R10 CP FAH CPU General Purpose Word Register R10 UUUU 20 R11 CP FBy CPU General Purpose Word Register R11 UUUU 22 R12 CP FCH CPU General Purpose Word Register R12 UUUU 24 R13 CP FDu CPU General Purpose Word Register R13 UUUU 26 R14 CP FEH CPU General Purpos
79. by software Bit T6OE Alternate Output Function Enable in register T6CON enables the state of T6OTL to be an alternate function of the external output pin TEOUT P3 1 For that purpose a 1 must be written into port data latch P3 1 and pin TEOUT P3 1 must be configured as output by setting direction control bit DP3 1 to 1 If T6OE 1 pin TOUT then outputs the state of T6OTL If TEOEz O pin TOUT can be used as general purpose IO pin In addition T6OTL can be used in conjunction with the timer over underflows as an input for the counter function of the auxiliary timer T5 For this purpose the state of T6OTL does not have to be available at pin T6OUT because an internal connection is provided for this option An overflow or underflow of timer T6 can also be used to clock the timers in the CAPCOM units For this purpose there is a direct internal connection between timer T6 and the CAPCOM timers Semiconductor Group 9 19 SIEMENS The General Purpose Timer Units C167 Timer 6 in Timer Mode Timer mode for the core timer T6 is selected by setting bit field T6M in register TECON to 000p In this mode T6 is clocked with the internal system clock divided by a programmable prescaler which is selected by bit field T6l The input frequency frg for timer T6 and its resolution rre are scaled linearly with lower clock frequencies fopy as can be seen from the following formula cPU 4 o T6l fg 9 rre uS
80. characteristics selectable for five programmable address areas 16 Priority Level Interrupt System 56 interrupt nodes with separate interrupt vectors 300 500 ns typical maximum interrupt latency in case of internal program execution Fast external interrupts Semiconductor Group 1 4 SIEMENS Introduction C167 8 Channel Peripheral Event Controller PEC Interrupt driven single cycle data transfer Transfer count option standard CPU interrupt after a programmable number of PEC transfers Eliminates overhead of saving and restoring system state for interrupt requests Intelligent On chip Peripheral Subsystems 16 Channel 10 bit A D Converter with programmable conversion time 9 7 us minimum auto scan modes channel injection mode Two 16 Channel Capture Compare Units with 2 independent time bases each very flexible PWM unit event recording unit with 5 different operating modes includes four 16 bit timers counters with 400 ns maximum resolution 4 Channel PWM Unit 2 Multifunctional General Purpose Timer Units GPT1 three 16 bit timers counters 400 ns maximum resolution GPT2 two 16 bit timers counters 200 ns maximum resolution Asynchronous Synchronous Serial Channel USART with baud rate generator parity framing and overrun error detection High Speed Synchronous Serial Channel programmable data length and shift direction Watchdog Timer with programmable time intervals Bootstrap Loader for flexible sys
81. command with falling edge of ALE MTTCx Memory Tristate Time Control 0 1 waitstate 1 No waitstate BTYP External Bus Configuration 0 0 8 bit Demultiplexed Bus 0 1 8 bit Multiplexed Bus 10 16 bit Demultiplexed Bus 11 16 bit Multiplexed Bus Note For BUSCONO BTYP is defined via PORTO during reset ALECTLx ALE Lengthening Control 0 Normal ALE signal 1 Lengthened ALE signal BUSACTx Bus Active Control 0 External bus disabled 1 External bus enabled within the respective address window see ADDRSEL RDYENx READY Input Enable 0 External bus cycle is controlled by bit field MCTC only 1 External bus cycle is controlled by the READY input signal CSRENx Read Chip Select Enable 0 The CS signal is independent of the read command RD 1 The CS signal is generated for the duration of the read command CSWENx Write Chip Select Enable 0 The CS signal is independent of the write command WR WRL WRH 1 The CS signal is generated for the duration of the write command Semiconductor Group 8 19 SIEMENS The External Bus Interface C167 ADDRSEL1 FE18 0C SFR Reset Value 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADDRSEL2 FE1Ay 0Dj SFR Reset Value 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADDRSEL3 FE1C OE SFR Reset Value 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADDRSEL4 FE1E OF S
82. controllers provide a number of powerful system resources designed around the CPU The combination of CPU and these resources results in the high performance of the members of this controller family Peripheral Event Controller PEC and Interrupt Control The Peripheral Event Controller allows to respond to an interrupt request with a single data transfer word or byte which only consumes one instruction cycle and does not require to save and restore the machine status Each interrupt source is prioritized every machine cycle in the interrupt control block If PEC service is selected a PEC transfer is started If CPU interrupt service is requested the current CPU priority level stored in the PSW register is tested to determine whether a higher priority interrupt is currently being serviced When an interrupt is acknowledged the current state of the machine is saved on the internal system stack and the CPU branches to the system specific vector for the peripheral The PEC contains a set of SFRs which store the count value and control bits for eight data transfer channels In addition the PEC uses a dedicated area of RAM which contains the source and destination addresses The PEC is controlled similar to any other peripheral through SFRs containing the desired configuration of each channel An individual PEC transfer counter is implicitly decremented for each PEC service except forming in the continuous transfer mode When this counter reaches ze
83. corresponding request flag When T2I or T4l are programmed to X11g both a positive and a negative transition will set the request flag In all three cases the contents of the core timer T3 will be captured into the auxiliary timer registers T2 or T4 based on the transition at pins T2IN or TAIN When the interrupt enable bits T2IE or T4IE are set a PEC request or an interrupt request for vector T2INT or T4INT will be generated Pin CAPIN differs slightly from the timer input pins as it can be used as external interrupt input pin without affecting peripheral functions When the capture mode enable bit T5SC in register T5ECON is cleared to 0 signal transitions on pin CAPIN will only set the interrupt request flag CRIR in register CRIC and the capture function of register CAPREL is not activated So register CAPREL can still be used as reload register for GPT2 timer T5 while pin CAPIN serves as external interrupt input Bit field Cl in register T5CON selects the effective transition of the external interrupt input signal When Cl is programmed to 01g a positive external transition will set the interrupt request flag Cl210g selects a negative transition to set the interrupt request flag and with Cl 11p both a positive and a negative transition will set the request flag When the interrupt enable bit CRIE is set an interrupt request for vector CRINT or a PEC request will be generated Note The non maskable interrupt input pin NMI and the rese
84. data line there is no gap between the two successive frames Eg two byte transfers would look the same as one word transfer This feature can be used to interface with devices which can operate with or require more than 16 data bits per transfer It is just a matter of software how long a total data frame length can be This option can also be used eg to interface to byte wide and word wide devices on the same serial bus Note Of course this can only happen in multiples of the selected basic data width since it would require disabling enabling of the SSC to reprogram the basic data width on the fly Semiconductor Group 11 9 SIEM ENS The High Speed Synchronous Serial Interface C167 Port Control The SSC uses three pins of Port 3 to communicate with the external world Pin P3 13 SCLK serves as the clock line while pins P3 8 MRST Master Receive Slave Transmit and P3 9 MTSR Master Transmit Slave Receive serve as the serial data input output lines The operation of these pins depends on the selected operating mode master or slave In order to enable the alternate output functions of these pins instead of the general purpose IO operation the respective port latches have to be set to 1 since the port latch outputs and the alternate output lines are ANDed When an alternate data output line is not used function disabled it is held at a high level allowing lO operations via the port latch The direction of the port lines depends
85. eg by clearing bit SOM O which enables it to also receive the data bytes that will be coming having the wake up bit cleared The slaves that were not being addressed remain in 8 bit data wake up bit mode ignoring the following data bytes Semiconductor Group 10 5 Sl EM ENS The Asynchronous Synchronous Serial Interface C167 Do Di D2 D3 D4 D5 D7 9th LSB Bit Data Bit D8 Parity Wake up Bit Figure 10 4 Asynchronous 9 bit Data Frames Asynchronous transmission begins at the next overflow of the divide by 16 counter see figure above provided that SOR is set and data has been loaded into SOTBUF The transmitted data frame consists of three basic elements the start bit the data field 8 or 9 bits LSB first including a parity bit if selected the delimiter 1 or 2 stop bits Data transmission is double buffered When the transmitter is idle the transmit data loaded into SOTBUF is immediately moved to the transmit shift register thus freeing SOTBUF for the next data to be sent This is indicated by the transmit buffer interrupt request flag SOTBIR being set SOTBUF may now be loaded with the next data while transmission of the previous one is still going on The transmit interrupt request flag SOTIR will be set before the last bit of a frame is transmitted ie before the first or the second stop bit is shifted out of the transmit shift register The transmitter output pin TXDO P3 10 must be co
86. enabled state of the timers ie the respective run flag is assumed to be set to 1 In all modes the timers are always counting upward The current timer values are accessible for the CPU in the timer registers Tx which are non bitaddressable SFRs When the CPU writes to a Semiconductor Group 14 5 SIEMENS The Capture Compare Units C167 register Tx in the state immediately before the respective timer increment or reload is to be performed the CPU write operation has priority and the increment or reload is disabled to guarantee correct timer operation Timer Mode The bits TxM in SFRs TO1CON and T78CON select between timer or counter mode for the respective timer In timer mode TxM 0 the input clock for a timer is derived from the internal CPU clock divided by a programmable prescaler The different options for the prescaler are selected separately for each timer by the bit fields Txl The input frequencies fr for Tx are determined as a function of the CPU clock as follows where Txl represents the contents of the bit field Txl fopu Tem o Txb 43 When a timer overflows from FFFF to 0000 it is reloaded with the value stored in its respective reload register TXREL The reload value determines the period Pr between two consecutive overflows of Tx as follows 216 lt TxREL gt 9 lt Txl gt 3 m fopu The timer input frequencies resolution and periods which result from the selected prescaler option
87. have bits ID17 0 filled with 0 This is implemented to keep the data bytes connected with the identifier even if arbitration mask registers are used When the CAN controller stores a remote frame only the data length code is stored into the corresponding message object The identifier and the data bytes remain unchanged There must not be more than one valid message object with a particular identifier at any time If some bits are masked by the Global Mask Registers ie dont t care then the identifiers of the valid message objects must differ in the remaining bits which are used for acceptance filtering If a received data frame is stored into a message object the identifier of this message object is updated If some of the identifier bits are set to don t care by the corresponding mask register these bits may be changed in the message object If a remote frame is received the identifier in transmit object remain unchanged except for the last message object which cannot start a transmission Here the identifier bits corresponding to the don t care bits of the last message object s mask may be overwritten by the incoming message Upper Arbitration Register EFn2 XReg Reset Value UUUU 15 34 13 12 dH 10 9 8 7 6 5 4 3 2 1 0 ae DTE oo oum rw rw Lower Arbitration Register EFn4j XReg Reset Value UUUU 15 14 13 12 1i 10 9 8 7 6 5 4 3 2 1 0 rw rw r r r Bit Function ID28 0 Identifier 29 bi
88. inactive PEC channels may be used for general data storage Only the required pointers occupy RAM locations Note If word data transfer is selected for a specific PEC channel ie BWT 0 the respective source and destination pointers must both contain a valid word address which points to an even byte boundary Otherwise the Illegal Word Access trap will be invoked when this channel is used Semiconductor Group 5 13 SIEMENS Interrupt and Trap Functions C167 5 3 Prioritization of Interrupt and PEC Service Requests Interrupt and PEC service requests from all sources can be enabled so they are arbitrated and serviced if they win or they may be disabled so their requests are disregarded and not serviced Enabling and disabling interrupt requests may be done via three mechanisms Control Bits allow to switch each individual source ON or OFF so it may generate a request or not The control bits xxIE are located in the respective interrupt control registers All interrupt requests may be enabled or disabled generally via bit IEN in register PSW This control bit is the main switch that selects if requests from any source are accepted or not For a specific request to be arbitrated the respective source s enable bit and the global enable bit must both be set The Priority Level automatically selects a certain group of interrupt requests that will be acknowledged disclosing all other requests The priority level of the
89. input function pin associated with it which serves as the gate control in gated timer mode or as the count input in counter mode The count direction Up Down may be programmed via software or may be dynamically altered by a signal at an external control input pin An overflow underflow of T6 is indicated by the output toggle bit TeOTL whose state may be output on an alternate function port pin In addition T6 may be reloaded with the contents of CAPREL The toggle bit also supports the concatenation of T6 with auxiliary timer T5 while concatenation of T6 with the timers of the CAPCOM units is provided through a direct connection Triggered by an external signal the contents of T5 can be captured into register CAPREL and T5 may optionally be cleared Both timer T6 and T5 can count up or down and the current timer value can be read or modified by the CPU in the non bitaddressable SFRs T5 and T6 Semiconductor Group 9 16 SIEMENS The General Purpose Timer Units C167 TSEUD CPU Clock VD 2 n22 8 T5IN J T6IN J CPU Clock T5 Mode Control GPT2 Timer T5 p erru Request Interrupt Request Interrupt Request GPT2 Timer T6 J teour D U to CAPCOM Figure 9 12 GPT2 Block Diagram Semiconductor Group Timers MCTO2142 SIEMENS The General Purpose Timer Units C167 GPT2 Core Timer T6 The operation of the core timer T6 is controlled by its bitaddressable control register T6
90. instruction is decoded without an error This enhances the safety and reliability of a microcontroller system Semiconductor Group 21 4 SIEMENS Device Specification C167 22 Device Specification The device specification describes the electrical parameters of the device It lists DC characteristics like input output or supply voltages or currents and AC characteristics like timing characteristics and requirements Other than the architecture the instruction set or the basic functions of the C167 core and its peripherals these DC and AC characteristics are subject to changes due to device improvements or specific derivatives of the standard device Therefore these characteristics are not contained in this manual but rather provided in a separate Data Sheet which can be updated more frequently Please refer to the current version of the Data Sheet of the respective device for all electrical parameters Note In any case the specific characteristics of a device should be verified before a new design is started This ensures that the used information is up to date The figure below shows the pin diagram of the C167 It shows the location of the different supply and IO pins A detailed description of all the pins is also found in the Data Sheet Note Not all alternate functions shown in the figure below are supported by all derivatives Please refer to the corresponding descriptions in the data sheets Semiconductor Group 22 1
91. interface One representative taking advantage of this technology is the integrated CAN module that is offered by some devices The C165 type devices are reduced versions of the C167 which provide a smaller package and reduced power consumption at the expense of the A D converter the CAPCOM units and the PWM module A variety of different versions is provided which offer mask programmable ROM Flash memory or no non volatile memory at all Also there are devices with specific functional units The devices may be offered in different packages temperature ranges and speed classes More standard and application specific derivatives are planned and in development Information about specific versions and derivatives will be made available with the devices themselves Contact your Siemens representative for up to date material Note Asthe architecture and the basic features ie CPU core and built in peripherals are identical for most of the currently offered versions of the C167 the descriptions within this manual that refer to the C167 also apply to the other variations unless otherwise noted Semiconductor Group 1 3 SIEMENS Introduction C167 1 2 Summary of Basic Features The C167 is an improved representative of the Siemens family of full featured 16 bit single chip CMOS microcontrollers It combines high CPU performance up to 10 million instructions per second with high peripheral functionality Several key features c
92. is implemented as an X Peripheral and is therefore accessed like an external memory or peripheral That means that the registers of the CAN Module can be read and written using 16 bit or 8 bit direct or indirect MEM addressing modes Since the XBUS to which the CAN Module is connected also represents the external bus CAN accesses follow the same rules and procedures as accesses to the external bus CAN accesses cannot be executed in parallel to external instruction fetches or data read writes but are arbitrated and inserted into the external bus access stream Accesses to the CAN Module use demultiplexed addresses and a 16 bit data bus byte accesses possible Two waitstates give an access time of 200 ns 20 MHz CPU clock No tristate waitstate is used The CAN address area starts at 00 EF00 and covers 256 Bytes A dedicated hardwired XADRS XBCON register pair selects the respective address window so none of the programmable register pairs must be sacrificed in order to access the on chip CAN Module Locating the CAN address area to address 00 EFO00 in segment 0 has the advantage that the CAN Module is accessible via data page 3 which is the system data page accessed usually through the system data page pointer DPP3 In this way the internal addresses such like SFRs internal RAM and the CAN registers are all located within the same data page and form a contiguous address space Power Down Mode If the C167 enters Power Down
93. is implicitly divided into equally sized blocks of different granularity and into logical memory areas Crossing the boundaries between these blocks code or data or areas requires special attention to ensure that the controller executes the desired operations Memory Areas are partitions of the address space that represent different kinds of memory if provided at all These memory areas are the internal RAM SFR area the internal ROM if available the on chip X Peripherals if integrated and the external memory Accessing subsequent data locations that belong to different memory areas is no problem However when executing code the different memory areas must be switched explicitly via branch instructions Sequential boundary crossing is not supported and leads to erroneous results Note Changing from the external memory area to the internal RAM SFR area takes place within segment 0 Segments are contiguous blocks of 64 KByte each They are referenced via the code segment pointer CSP for code fetches and via an explicit segment number for data accesses overriding the standard DPP scheme During code fetching segments are not changed automatically but rather must be switched explicitly The instructions JMPS CALLS and RETS will do this In larger sequential programs make sure that the highest used code location of a segment contains an unconditional branch instruction to the respective following segment to prevent the prefetcher from tr
94. is provided as a storage for temporary data The system stack is also located within the on chip RAM area and it is accessed by the CPU via the stack pointer SP register Two separate SFRs STKOV and STKUN are implicitly compared against the stack pointer value upon each stack access for the detection of a stack overflow or underflow Semiconductor Group 2 7 SIEMENS Architectural Overview C167 Hardware detection of the selected memory space is placed at the internal memory decoders and allows the user to specify any address directly or indirectly and obtain the desired data without using temporary registers or special instructions A 2 KByte 16 bit wide on chip XRAM provides fast access to user data variables user stacks and code The on chip XRAM is realized as an X Peripheral and appears to the software as an external RAM Therefore it cannot store register banks and is not bitaddressable The XRAM allows 16 bit accesses with maximum speed An optional internal ROM provides for both code and constant data storage This memory area is connected to the CPU via a 32 bit wide bus Thus an entire double word instruction can be fetched in just one machine cycle Program execution from the on chip ROM is the fastest of all possible alternatives For Special Function Registers 1024 Bytes of the address space are reserved The standard Special Function Register area SFR uses 512 bytes while the Extended Special Function Register area
95. is selected by bit field ADSTC sample time control The table below lists the possible combinations The timings refer to the unit TCL where fcpy 1 2TCL ADCTC Conversion clock fcc ADSTC Sample clock tsc 00 TCL 24 00 toc 01 Reserved do not use 01 too 2 10 TCL 96 10 fcc 4 11 TCL 48 11 fcc 8 A complete conversion will take 14tcc 2tsc 4TCL 9 7 us 20 MHz This time includes the conversion itself the sample time and the time required to transfer the digital value to the result register Note The non linear decoding of bit field ADCTC provides compatibility with 80C166 designs for the default value 00 after reset Semiconductor Group 16 10 SIEMENS The Analog Digital Converter C167 16 3 A D Converter Interrupt Control At the end of each conversion interrupt request flag ADCIR in interrupt control register ADCIC is set This end of conversion interrupt request may cause an interrupt to vector ADCINT or it may trigger a PEC data transfer which reads the conversion result from register ADDAT eg to store it into a table in the internal RAM for later evaluation The interrupt request flag ADEIR in register ADEIC will be set either if a conversion result overwrites a previous value in register ADDAT error interrupt in standard mode or if the result of an injected conversion has been stored into ADDAT2 end of injected conversion interrupt This interrupt request may be u
96. of 1 s in data Semiconductor Group 10 2 Sl EM ENS The Asynchronous Synchronous Serial Interface C167 Bit Function SOBRS Baudrate Selection Bit 0 Divide clock by reload value constant depending on mode 1 Additionally reduce serial clock to 2 3rd SOLB LoopBack Mode Enable Bit 0 Standard transmit receive mode d Loopback mode enabled SOR Baudrate Generator Run Bit 0 Baudrate generator disabled ASCO inactive 1 Baudrate generator enabled A transmission is started by writing to the Transmit Buffer register SOTBUF via an instruction or a PEC data transfer Only the number of data bits which is determined by the selected operating mode will actually be transmitted ie bits written to positions 9 through 15 of register SOTBUF are always insignificant After a transmission has been completed the transmit buffer register is cleared to 00004 Data transmission is double buffered so a new character may be written to the transmit buffer register before the transmission of the previous character is complete This allows the transmission of characters back to back without gaps Data reception is enabled by the Receiver Enable Bit SOREN After reception of a character has been completed the received data and if provided by the selected operating mode the received parity bit can be read from the read only Receive Buffer register SORBUF Bits in the upper half of SORBUF which are not valid in the selecte
97. on ROMless devices Exiting Bootstrap Loader Mode In order to execute a program in normal mode the BSL mode must be terminated first The C167 exits BSL mode upon a software reset ignores the level on POL 4 or a hardware reset POL 4 must be high then After a reset the C167 will start executing from location 00 0000 of the internal ROM or the external memory as programmed via pin EA Choosing the Baudrate for the BSL The calculation of the serial baudrate for ASCO from the length of the first zero byte that is received allows the operation of the bootstrap loader of the C167 with a wide range of baudrates However the upper and lower limits have to be kept in order to insure proper data transfer CPU Bci77 39 SOBRL 1 The C167 uses timer T6 to measure the length of the initial zero byte The quantization uncertainty of this measurement implies the first deviation from the real baudrate the next deviation is implied by the computation of the SOBRL reload value from the timer contents The formula below shows the association fcPU Post T6 36 72 i SOBRL T6 2 Semiconductor Group 13 4 SIEMENS The Bootstrap Loader C167 For a correct data transfer from the host to the C167 the maximum deviation between the internal initialized baudrate for ASCO and the real baudrate of the host should be below 2 5 The deviation Fg in percent between host baudrate and C167 baudrate can be calculated via the formula be
98. on the operating mode The SSC will automatically use the correct alternate input or output line of the ports when switching modes The direction of the pins however must be programmed by the user as shown in the tables Using the open drain output feature helps to avoid bus contention problems and reduces the need for hardwired hand shaking or slave select lines In this case it is not always necessary to switch the direction of a port pin The table below summarizes the required values for the different modes and pins Pin Master Mode Slave Mode Function Port Latch Direction Function Port Latch Direction P3 13 SCLK Serial Clock P3 132 1 DP3 132 1 Serial Clock P3 13 x DP3 13 0 Output Input P3 9 MTSR Serial Data P3 9 1 DP3 9 1 Serial Data P3 9 DP3 9 0 Output Input P3 8 MRST Serial Data P3 8 DP3 8 0 Serial Data P3 8 1 DP3 8 1 Input Output Note In the table above an x means that the actual value is irrelevant in the respective mode however it is recommended to set these bits to 1 so they are already in the correct state when switching between master and slave mode 11 3 Baud Rate Generation The serial channel SSC has its own dedicated 16 bit baud rate generator with 16 bit reload capability allowing baud rate generation independent from the timers The baud rate generator is clocked with the CPU clock divided by 2 10 MHz
99. overflow trap is entered where the user moves a predetermined portion of the internal stack to or from the external stack The amount of data transferred is determined by the average stack space required by routines and the frequency of calls traps interrupts and returns In most cases this will be approximately one quarter to one tenth the size of the internal stack Once the transfer is complete the boundary pointers are updated to reflect the newly allocated space on the internal stack Thus the user is free to write code without concern for the internal stack limits Only the execution time required by the trap routines affects user programs The following procedure initializes the controller for usage of the circular stack mechanism Specify the size of the physical system stack area within the internal RAM bitfield STKSZ in register SYSCON Define two pointers which specify the upper and lower boundary of the external stack These values are then tested in the stack underflow and overflow trap routines when moving data Set the stack overflow pointer STKOV to the limit of the defined internal stack area plus six words for the reserved space to store two interrupt entries The internal stack will now fill until the overflow pointer is reached After entry into the overflow trap procedure the top of the stack will be copied to the external memory The internal pointers will then be modified to reflect the newly allocated spac
100. pin MRST master mode or MTSR slave mode sampled with the same frequency as the CPU clock changes between one sample before and two samples after the latching edge of the clock signal see Clock Control This condition sets the error flag SSCPE and when enabled via SSCPEN the error interrupt request flag SSCEIR A Baud Rate Error Slave mode is detected when the incoming clock signal deviates from the programmed baud rate by more than 100 ie it either is more than double or less than half the expected baud rate This condition sets the error flag SSCBE and when enabled via SSCBEN the error interrupt request flag SSCEIR Using this error detection capability requires that the slave s baud rate generator is programmed to the same baud rate as the master device This feature detects false additional or missing pulses on the clock line within a certain frame Note If this error condition occurs and bit SSCAREN 1 an automatic reset of the SSC will be performed in case of this error This is done to reinitialize the SSC if too few or too many clock pulses have been detected Semiconductor Group 11 12 SIEM ENS The High Speed Synchronous Serial Interface C167 A Transmit Error Slave mode is detected when a transfer was initiated by the master shift clock gets active but the transmit buffer SSCTB of the slave was not updated since the last transfer This condition sets the error flag SSCTE and when enabled via SSCTEN th
101. priority level of this request is higher than the current CPU priority and the interrupt system is globally enabled After the PEC data transfer has been completed the CPU remains in Idle mode Otherwise if the PEC request cannot be serviced because of a too low priority or a globally disabled interrupt system the CPU does not remain in Idle mode but continues program execution with the instruction following the IDLE instruction Semiconductor Group 18 1 SIEMENS Power Reduction Modes C167 A CPU Interrupt Request IDLE instruction e Executed Denied PEC Request PEC Request Figure 18 1 Transitions between Idle mode and active mode Idle mode can also be terminated by a Non Maskable Interrupt ie a high to low transition on the NMI pin After Idle mode has been terminated by an interrupt or NMI request the interrupt system performs a round of prioritization to determine the highest priority request In the case of an NMI request the NMI trap will always be entered Any interrupt request whose individual Interrupt Enable flag was set before Idle mode was entered will terminate Idle mode regardless of the current CPU priority The CPU will not go back into Idle mode when a CPU interrupt request is detected even when the interrupt was not serviced because of a higher CPU priority or a globally disabled interrupt system IEN 0 The CPU will only go back into Idle mode when the interrupt system is globally enabled IEN 1 an
102. recessive level 1 but the monitored bus value was dominant 5 BitOError During the transmission of a message or acknowledge bit active error flag or overload flag the device wanted to send a dominant level 0 but the monitored bus value was recessive During busoff recovery this status is set each time a sequence of 11 recessive bits has been monitored This enables the CPU to monitor the proceeding of the busoff recovery sequence indicating the bus is not stuck at dominant or continously disturbed 6 CRCError The CRC check sum was incorrect in the message received TXOK Transmitted Message Successfully Indicates that a message has been transmitted successfully error free and acknowledged by at least one other node since this bit was last reset by the CPU the CAN controller does not reset this bit RXOK Received Message Successfully Indicates that a message has been received successfully since this bit was last reset by the CPU the CAN controller does not reset this bit EWRN Error Warning Status Indicates that at least one of the error counters in the EML has reached the error warning limit of 96 BOFF Busoff Status Indicates when the CAN controller is in busoff state see EML Note Reading the upper half of the Control Register status partition will clear the Status Change Interrupt value in the Interrupt Register if it is pending Use byte accesses to the lower half to avoid this Semi
103. source that won the arbitration is compared against the CPU s current level and the source is only serviced if its level is higher than the current CPU level Changing the CPU level to a specific value via software blocks all requests on the same or a lower level An interrupt source that is assigned to level O will be disabled and never be serviced The ATOMIC and EXTend instructions automatically disable all interrupt requests for the duration of the following 1 4 instructions This is useful eg for semaphore handling and does not require to re enable the interrupt system after the unseparable instruction sequence see chapter System Programming Interrupt Class Management An interrupt class covers a set of interrupt sources with the same importance ie the same priority from the system s viewpoint Interrupts of the same class must not interrupt each other The C167 supports this function with two features Classes with up to 4 members can be established by using the same interrupt priority ILVL and assigning a dedicated group level GLVL to each member This functionality is built in and handled automatically by the interrupt controller Classes with more than 4 members can be established by using a number of adjacent interrupt priorities ILVL and the respective group levels 4 per ILVL Each interrupt service routine within this class sets the CPU level to the highest interrupt priority within the class All requests from the s
104. stack underflow STKUN registers should be initialized After reset the CP SP and STKUN registers all contain the same reset value 00 FCOO while the STKOV register contains 00 FAO0 With the default reset initialization 256 words of system stack are available where the system stack selected by the SP grows downwards from 00 FBFE while the register bank selected by the CP grows upwards from 00 FCO00 Based on the application the user may wish to initialize portions of the internal memory before normal program operation Once the register bank has been selected by programming the CP register the desired portions of the internal memory can easily be initialized via indirect addressing At the end of the initialization the interrupt system may be globally enabled by setting bit IEN in register PSW Care must be taken not to enable the interrupt system before the initialization is complete The software initialization routine should be terminated with the EINIT instruction This instruction has been implemented as a protected instruction Execution of the EINIT instruction disables the action of the DISWDT instruction disables write accesses to register SYSCON see note and causes the RSTOUT pin to go high This signal can be used to indicate the end of the initialization routine and the proper operation of the microcontroller to external hardware Note All configurations regarding register SYSCON enable CLKOUT stacksize etc must
105. system The number of chip select signals is selected via PORTO during reset The selected value can be read from bitfield CSSEL in register RPOH read only eg in order to check the configuration during run time The table below summarizes the alternate functions of Port 6 depending on the number of selected chip select lines coded via bitfield CSSEL Port 6 Pin Altern Function Altern Function Altern Function Altern Function CSSEL 10 CSSEL 01 CSSEL 00 CSSEL 11 P6 0 Gen purpose IO Chip select CSO Chip select CSO Chip select CSO P6 1 Gen purpose IO Chip select CS1 Chipselect CS1 Chip select CS1 P6 2 Gen purpose IO Gen purpose IO Chip select CS2 Chip select CS2 P6 3 Gen purpose IO Gen purpose IO Gen purpose IO Chip select CS3 P6 4 Gen purpose IO Gen purpose IO Gen purpose IO Chip select CS4 P6 5 HOLD External hold request input P6 6 HLDA Hold acknowledge output P6 7 BREQ Bus request output Alternate Function General Purpose Input Output Figure 6 17 Port 6 IO and Alternate Functions Semiconductor Group 6 26 SIEMENS Parallel Ports C167 The chip select lines of Port 6 additionally have an internal weak pullup device This device is switched on under the following conditions always during reset if the Port 6 line is used as a chip select output and the C167 is in Hold mode invoked through HOLD and the respective pin driver is in push
106. the CAPCOM units TAIN T2IN the timer input pins CAPIN the capture input of GPT2 For each of these pins either a positive a negative or both a positive and a negative external transition can be selected to cause an interrupt or PEC service request The edge selection is performed in the control register of the peripheral device associated with the respective port pin The peripheral must be programmed to a specific operating mode to allow generation of an interrupt by the external signal The priority of the interrupt request is determined by the interrupt control register of the respective peripheral interrupt source and the interrupt vector of this source will be used to service the external interrupt request Note In order to use any of the listed pins as external interrupt input it must be switched to input mode via its direction control bit DPx y in the respective port direction control register DPx Pins to be used as External Interrupt Inputs Port Pin Original Function Control Register P2 0 15 CC0 15IO CAPCOM Register 0 15 Capture Input CCO0 CC15 P8 0 7 CC16 23IO CAPCOM Register 16 23 Capture Input CC16 CC23 P1H 4 7 CC24 271O CAPCOM Register 24 27 Capture Input CC24 CC27 P7 4 7 CC28 31IO CAPCOM Register 28 31 Capture Input CC28 CC31 P3 7 T21N Auxiliary timer T2 input pin T2CON P3 5 T4IN Auxiliary timer T4 input pin T4CON P3 2 CAPIN GPT2 capture input pin T5CON When port pins CCxlO are
107. the CPU will enter the NMI trap routine The IP value pushed on the system stack is the address of the instruction following the one after which normal processing was interrupted by the NMI trap Note The NMI pin is sampled with every CPU clock cycle to detect transitions Stack Overflow Trap Whenever the stack pointer is decremented to a value which is less than the value in the stack overflow register STKOV the STKOF flag in register TFR is set and the CPU will enter the stack overflow trap routine Which IP value will be pushed onto the system stack depends on which operation caused the decrement of the SP When an implicit decrement of the SP is made through a PUSH or CALL instruction or upon interrupt or trap entry the IP value pushed is the address of the following instruction When the SP is decremented by a subtract instruction the IP value pushed represents the address of the instruction after the instruction following the subtract instruction For recovery from stack overflow it must be ensured that there is enough excess space on the stack for saving the current system state PSW IP in segmented mode also CSP twice Otherwise a system reset should be generated Semiconductor Group 5 26 SIEMENS Interrupt and Trap Functions C167 Stack Underflow Trap Whenever the stack pointer is incremented to a value which is greater than the value in the stack underflow register STKUN the STKUF flag is set in register TFR and the C
108. the associated counter and leaves the respective output at its current level The individual PWM channel outputs are controlled by comparators according to the formula PWM output signal PTx 2 PWx shadow latch So whenever software changes registers PTx the respective output will reflect the condition after the change Loading timer PTx with a value greater than or equal to the value in PWx immediately sets the respective output a PTx value below the PWx value clears the respective output By clearing or setting the respective Port 7 output latch the PWM channel signal is driven directly or inverted to the port pin Clearing the enable bit PENx disconnects the PWM channel and switches the respective port pin to the value in the port output latch Note To prevent further PWM pulses from occurring after such a software intervention the respective counter must be stopped first Semiconductor Group 15 13 SIEMENS The Analog Digital Converter C167 16 The Analog Digital Converter The C167 provides an Analog Digital Converter with 10 bit resolution and a sample amp hold circuit on chip A multiplexer selects between up to 16 analog input channels alternate functions of Port 5 either via software fixed channel modes or automatically auto scan modes An automatic self calibration adjusts the ADC module to changing temperatures or process variations To fulfill most requirements of embedded control applications the AD
109. the intended bit s is are effected by the write back operation Note If a conflict occurs between a bit manipulation generated by hardware and an intended software access the software access has priority and determines the final value of the respective bit A summary of the protected bits implemented in the C167 can be found at the end of chapter Architectural Overview Semiconductor Group 4 9 SIEMENS The Central Processing Unit CPU C167 4 3 Instruction State Times Basically the time to execute an instruction depends on where the instruction is fetched from and where possible operands are read from or written to The fastest processing mode of the C167 is to execute a program fetched from the internal ROM In that case most of the instructions can be processed within just one machine cycle which is also the general minimum execution time All external memory accesses are performed by the C167 s on chip External Bus Controller EBC which works in parallel with the CPU This section summarizes the execution times in a very condensed way A detailled description of the execution times for the various instructions and the specific exceptions can be found in the C16x Family Instruction Set Manual The table below shows the minimum execution times required to process a C167 instruction fetched from the internal ROM the internal RAM or from external memory These execution times apply to most of the C167 instructions exc
110. to 110p When a match is detected in compare mode 2 for the first time within a timer period the interrupt request flag CCxIR is set to 1 The corresponding port 2 pin is not affected and can be used for general purpose IO However after the first match has been detected in this mode all further compare events within the same timer period are disabled for compare register CCx until the allocated timer overflows This means that after the first match even when the compare register is reloaded with a value higher than the current timer value no compare event will occur until the next timer period In the example below the compare value in register CCx is modified from cv1 to cv2 after compare event 1 Compare event 2 however will not occur until the next period of timer Ty Semiconductor Group 14 15 SIEMENS The Capture Compare Units C167 Interrupt Compare Reg CCx gt COxIR Request Latch Set Comparator e Vode 3 cexio Reset CCMODx Input Interrupt Clock gt CAPCOM Timer Ty i ER Request MCB02019 x 31 0 y 0 1 7 8 Figure 14 8 Compare Mode 2 and 3 Block Diagram Note The port latch and pin remain unaffected in compare mode 2 Contents of Ty FFFF Compare Value cv2 Compare Value cv1 l l i l Reload Value lt TyREL gt l 00004 l Interrupt Requests TylR CCxIR CCxIR TyIR 1 0 Event 1 Event
111. to 8 7 interrupts 5 21 SIEMENS Keyword Index C167 F Fast external interrupts 5 23 Flags 4 14 to 4 16 Full Duplex 11 7 G GPR 3 6 4 22 20 2 GPT 2 14 GPT1 9 1 GPT2 9 16 H Half Duplex 11 9 Hardware Reset 17 1 Traps 5 24 Hold State 8 27 Semiconductor Group j Idle Mode 18 1 Input threshold 6 2 Instruction 19 1 21 1 Bit Manipulation 21 2 Branch 4 4 Pipeline 4 3 protected 21 4 Timing 4 10 unseparable 19 12 Interface CAN 2 13 23 1 External Bus 8 1 serial async 10 1 serial sync 11 1 Internal RAM 3 4 Interrupt CAPCOM 14 20 Enable Disable 5 14 external 5 21 fast external 5 23 Handling CAN 23 8 Priority 5 7 Processing 5 1 5 6 Response Times 5 17 Sources 5 3 System 2 6 5 2 Vectors 5 3 IP 4 17 L LAR 23 16 1 3 SIEMENS Keyword Index C167 M Master mode 8 25 MCFG 23 17 MCR 23 14 MDC 4 28 MDH 4 27 MDL 4 27 Memory 2 7 bit addressable 3 4 External 3 11 RAM SFR 3 4 ROM 3 3 19 14 XRAM 3 9 Memory Cycle Time 8 12 Multiplexed Bus 8 3 Multiplication 4 27 19 1 N NMI 5 1 5 26 O ODP2 6 11 ODP3 6 15 ODP6 6 25 ODP7 6 30 ODP8 6 34 ONES 4 29 Open Drain Mode 6 2 Oscillator 2 9 Semiconductor Group P POL POH 6 5 P1L P1H 6 8 P2 6 11 P3 6 15 P4 6 20 P5 6 23 P6 6 25 P7 6 30 P8 6 34 PEC 2 7 3 7 5 11 Response Times 5 19 PECCx 5 11 Peripheral 2 11 Phase Locked Loop 2 9 PICON 6 3 Pins 7 1 22 2 in Idle and Power Down mode 18 5 Pip
112. to be used as external interrupt input pins bit field CCMODx in the control register of the corresponding capture compare register CCx must select capture mode When CCMODx is programmed to 001p the interrupt request flag COxIR in register CCxIC will be set on a positive external transition at pin CCxlO When CCMODx is programmed to 010g a negative external transition will set the interrupt request flag When CCMODx 01 1g both a positive and a negative transition will set the request flag In all three cases the contents of the allocated CAPCOM timer will be latched into capture register CCx independent whether the timer is running or not When the interrupt enable bit CCxIE is set a PEC request or an interrupt request for vector CCxINT will be generated Semiconductor Group 5 21 SIEMENS Interrupt and Trap Functions C167 Pins T2IN or T4IN can be used as external interrupt input pins when the associated auxiliary timer T2 or T4 in block GPT1 is configured for capture mode This mode is selected by programming the mode control fields T2M or T4M in control registers T2CON or T4CON to 101g The active edge of the external input signal is determined by bit fields T2I or T4l When these fields are programmed to X01g interrupt request flags T2IR or T4IR in registers T2IC or T4IC will be set on a positive external transition at pins T2IN or TAIN respectively When T2l or T4l are programmed to X10p then a negative external transition will set the
113. to cover any range This is particularly advantageous in table searching Semiconductor Group 2 4 SIEMENS Architectural Overview C167 Saving of system state is automatically performed on the internal system stack avoiding the use of instructions to preserve state upon entry and exit of interrupt or trap routines Call instructions push the value of the IP on the system stack and require the same execution time as branch instructions Instructions have also been provided to support indirect branch and call instructions This supports implementation of multiple CASE statement branching in assembler macros and high level languages Consistent and Optimized Instruction Formats To obtain optimum performance in a pipelined design an instruction set has been designed which incorporates concepts from Reduced Instruction Set Computing RISC These concepts primarily allow fast decoding of the instructions and operands while reducing pipeline holds These concepts however do not preclude the use of complex instructions which are required by microcontroller users The following goals were used to design the instruction set 1 Provide powerful instructions to perform operations which currently require sequences of instructions and are frequently used Avoid transfer into and out of temporary registers such as accumulators and carry bits Perform tasks in parallel such as saving state upon entry into interrupt routines or subroutines 2 Avoi
114. to the port output latch via the line Alternate Data Output When an overflow of the corresponding timer occurs a 0 is written to the port output latch In both cases the output latch is clocked by the signal Compare Trigger The direction of the pin should be set to output by the user otherwise the pin will be in the high impedance state and will not reflect the state of the output latch As can be seen from the port structure below the user software always has free access to the port pin even when it is used as a compare output This is useful for setting up the initial level of the pin when using compare mode 1 or the double register mode In these modes unlike in compare mode 3 the pin is not set to a specific value when a compare match occurs but is toggled instead When the user wants to write to the port pin at the same time a compare trigger tries to clock the output latch the write operation of the user software has priority Each time a CPU write access to the port output latch occurs the input multiplexer of the port output latch is switched to the line connected to the internal bus The port output latch will receive the value from the internal bus and the hardware triggered change will be lost As all other capture inputs the capture input function of pins P2 15 P2 0 can also be used as external interrupt inputs 400 ns sample rate 20 MHz CPU clock The upper eight Port 2 lines P2 15 P2 8 also can serve as Fast Ext
115. uses these bits to control internal operations Never modify these bits without saving and restoring register MDC When a division or multiplication was interrupted before its completion and the multiply divide unit is required the MDC register must first be saved along with registers MDH and MDL to be able to restart the interrupted operation later and then it must be cleared prepare it for the new calculation After completion of the new division or multiplication the state of the interrupted multiply or divide operation must be restored The MDRIU flag is the only portion of the MDC register which might be of interest for the user The remaining portions of the MDC register are reserved for dedicated use by the hardware and should never be modified by the user in another way than described above Otherwise a correct continuation of an interrupted multiply or divide operation cannot be guaranteed A detailed description of how to use the MDC register for programming multiply and divide algorithms can be found in chapter System Programming Semiconductor Group 4 28 SIEMENS The Central Processing Unit CPU C167 The Constant Zeros Register ZEROS All bits of this bit addressable register are fixed to 0 by hardware This register can be read only Register ZEROS can be used as a register addressable constant of all zeros ie for bit manipulation or mask generation It can be accessed via any instruction which is capab
116. write operation reads the value of the output latch modifies it and writes it back to the output latch thus also modifying the level at the pin Data Input Output Direction Control Threshold Open Drain Registers Registers Control Registers PICON E Figure 6 1 SFRs and Pins associated with the Parallel Ports Semiconductor Group 6 1 SIEMENS Parallel Ports C167 Open Drain Mode In the C167 certain ports provide Open Drain Control which allows to switch the output driver of a port pin from a push pull configuration to an open drain configuration In push pull mode a port output driver has an upper and a lower transistor thus it can actively drive the line either to a high or a low level In open drain mode the upper transistor is always switched off and the output driver can only actively drive the line to a low level When writing a 1 to the port latch the lower transistor is switched off and the output enters a high impedance state The high level must then be provided by an external pullup device With this feature it is possible to connect several port pins together to a Wired AND configuration saving external glue logic and or additional software overhead for enabling disabling output signals This feature is implemented for ports P2 P3 P6 P7 and P8 see respective sections and is controlled through the respective Open Drain Control Registers ODPx These registers allow the individual bit wise selection of the o
117. x4 e eese e Re EO Ca Bt aedes t oat Pa Naa ars 18 3 18 3 Status of Output Pins during Idle and Power Down Mode 18 4 19 System Programming ee xar xau dio unm Wise RR Re mr nca a a wt 19 1 19 1 Stack Operations cst cad eden e rat dik e S pare di m ba e D ett 19 4 19 2 Register Banking vo sr ups cst decet ducc rus Na ee b XU RENE S PDA 19 8 19 9 Procedure Call Entry and EXIU 2 5 os Mase toi oS ee APES awe a ERE 19 8 19 4 Table Searching so scx ant are Maire MICE EIS eae ata Be OR E PY 19 11 19 5 Peripheral Control and Interface 0 0 0 0 ee ee 19 11 19 6 Floating Point Support esx y See rata e BRE UIROS ek pea eee eos ENS 19 12 19 7 JTrapntermibP Entry and Exit 1 cwi paki au perc Y ERUPNOE S bec RD E 19 12 19 8 Unseparable Instruction Sequences lllssss 19 12 Semiconductor Group l 3 SIEMENS GIGI Table of Contents Page 19 9 Overriding the DPP Addressing Mechanism Lus 19 13 19 10 Handling the Internal ROM 0 0 ce eee 19 14 19 11 Pits Traps and Mines cae eee hla Gee Ce REN lee EORR eec 19 15 20 The Register Se oonrr lui le EN RIRei4w RE EIL 20 1 20 0 1 Register Description Format uy pc ade CUP EX EN EEG NEXU EA 20 1 20 1 CPU General Purpose Registers GPRS lsessssn 20 2 20 2 Special Function Registers ordered by Name sss 20 4 20 3 Registers ordered by Address 2200000 cee eee 20 12 20 4 Special NoteS road wear EE
118. 0000 T5IC b FF66 B34 GPT2 Timer 5 Interrupt Control Register 00004 T6IC b FF68 B44 GPT2 Timer 6 Interrupt Control Register 00004 CRIC b FF6A B5 GPT2 CAPREL Interrupt Control Register 00004 SOTIC b FF6Cy B6y Serial Channel 0 Transmit Interrupt Control 0000 Register SORIC b FF6E B7y Serial Channel 0 Receive Interrupt Control 0000 Register SOEIC b FF70y B8y Serial Channel 0 Error Interrupt Control Register 0000 SSCTIC b FF72 B94 SSC Transmit Interrupt Control Register 0000 SSCRIC _b FF74 BA SSC Receive Interrupt Control Register 00004 SSCEIC b FF764 BBy SSC Error Interrupt Control Register 00004 CCOIC b FF78 BCy CAPCOM Register 0 Interrupt Control Register 0000 CC1IC b FF7Ay BDy CAPCOM Register 1 Interrupt Control Register 0000 CC2IC b FF7Cy BEy CAPCOM Register 2 Interrupt Control Register 0000 CC3IC b FF7E BFy CAPCOM Register 3 Interrupt Control Register 0000 CC4IC b FF80 C04 CAPCOM Register 4 Interrupt Control Register 0000 Semiconductor Group 20 17 SIEMENS The Register Set C167 Name Physical 8 Bit Description Reset Address Address Value CC5IC b FF82 Ci CAPCOM Register 5 Interrupt Control Register 00004 CC6IC b FF84 C24 CAPCOM Register 6 Interrupt Control Register 00004 CC7IC b FF864 C34 CAPCOM Register 7 Interrupt Control Register 00004 CC8IC b FF88 C4y CAPCOM Register 8 Interrupt Control R
119. 004 CC30 FE7C 3Ey CAPCOM Register 30 0000 CC30lIC b F18C E C6 CAPCOM Register 30 Interrupt Control Register 0000 CC31 FE7E SFy CAPCOM Register 31 0000 CC311IC b F194 E CA CAPCOM Register 31 Interrupt Control Register 00004 CCMO b FF52 A9 CAPCOM Mode Control Register 0 0000 CCM1 b FF54 AAy CAPCOM Mode Control Register 1 0000 CCM2 b FF56 ABy CAPCOM Mode Control Register 2 0000 CCM3 b FF584 ACy CAPCOM Mode Control Register 3 0000 Semiconductor Group 20 6 SIEMENS The Register Set C167 Name Physical 8 Bit Description Reset Address Address Value CCM4 b FF224 914 CAPCOM Mode Control Register 4 0000 CCM5 b FF244 924 CAPCOM Mode Control Register 5 0000 CCM6 b FF26 934 CAPCOM Mode Control Register 6 00004 CCM7 b FF28 941 CAPCOM Mode Control Register 7 0000 CP FE10y 08y CPU Context Pointer Register FCOOW CRIC b FF6A B5 GPT2 CAPREL Interrupt Control Register 00004 CSP FEO8 044 CPU Code Segment Pointer Register 0000 8 bits not directly writeable DPOL b F100 E 80 POL Direction Control Register 00H DPOH b F102 E 81 POH Direction Control Register 00 DP1L b F104 E 824 P1L Direction Control Register 004 DP1H b F106 E 83 P1H Direction Control Register 00 DP2 b FFC2 Ely Port 2 Direction Control Register 00004 DP3 b FFC6 E3y Port 3 Direction Control Register 00004 DP4 b FFCAp
120. 10p 64 O0 FBFE 00 FB80 SP 6 SP 0 011g 32 O00 FBFE 00 FBCO SP 5 SP 0 1005g 512 00 FBFEy 00 F800 SP 9 SP 0 101g zu Reserved Do not use this combination An 110g Reserved Do not use this combination 1115 1024 00 FDFE 00 F600 Note No circular stack SP 11 SP 0 The virtual stack addresses are transformed to physical stack addresses by concatenating the significant bits of the stack pointer register SP see table with the complementary most significant bits of the upper limit of the physical stack area 00 FBFE This transformation is done via hardware see figure below The reset values STKOV ZFAO00 STKUN FCOO SP FCO00 STKSZz000g map the virtual stack area directly to the physical stack area and allow using the internal system stack without any changes provided that the 256 word area is not exceeded Semiconductor Group 19 5 SIEMENS System Programming C167 1111101111111110 1111101111111110 1111 1011 1000 0000 Phys A 1111 1010 0000 0000 1111 1011 11000 0000 lt SP gt 1111 1000 0000 0000 After PUSH l After PUSH 1111101111111110 FBFE 1111 101111111110 1111 1011 11111110 Phys A FBFE 1111 1011 1111 1110 1111101101111110 lt SP gt F7FE M 11111110 64 words Stack Size 256 words Figure 19 1 Physical Stack Address Generation The following example demonstrates the circular stack mechanism which is also an effect of this virtual stack mapping
121. 18 0000 CC19 FE66 33H CAPCOM Register 19 0000 CC20 FE684 344 CAPCOM Register 20 0000 CC21 FE6AH 35H CAPCOM Register 21 0000 CC22 FE6Cy 364 CAPCOM Register 22 0000 CC23 FE6E 37y CAPCOM Register 23 0000 CC24 FE70y 38y CAPCOM Register 24 00004 CC25 FE724 39 CAPCOM Register 25 0000 CC26 FE744 SAY CAPCOM Register 26 0000 CC27 FE764 3By CAPCOM Register 27 0000 CC28 FE78y 3Cy CAPCOM Register 28 0000 CC29 FE7A 3Dy CAPCOM Register 29 0000 CC30 FE7Cy 3Ey CAPCOM Register 30 0000 CC31 FE7E 3Fy CAPCOM Register 31 0000 CCO FE80 404 CAPCOM Register 0 0000 CC1 FE82 41u CAPCOM Register 1 00004 CC2 FE844 424 CAPCOM Register 2 00004 CC3 FE86 434 CAPCOM Register 3 0000 CC4 FE88 444 CAPCOM Register 4 00004 CC5 FE8A 454 CAPCOM Register 5 00004 CC6 FE8Cy 464 CAPCOM Register 6 0000 CC7 FE8E 474 CAPCOM Register 7 00004 CC8 FE90 484 CAPCOM Register 8 0000 CC9 FE92 494 CAPCOM Register 9 00004 CC10 FE944 4Ay CAPCOM Register 10 0000 CC11 FE96 4By CAPCOM Register 11 00004 CC12 FE98 4Cy CAPCOM Register 12 00004 CC13 FE9A 4Dyu CAPCOM Register 13 0000 CC14 FE9C 4Ey CAPCOM Register 14 0000 Semiconductor Group 20 15 SIEMENS The Register Set C167 Name Physical 8 Bit Description Reset Address Address Value CC15 FE9E 4Fu CAPCOM Register 15 0000 ADDAT FEAO 1504 A D Converter Result Register
122. 19 15 SIEMENS The Register Set C167 20 The Register Set This section summarizes all registers which are implemented in the C167 and explains the description format which is used in the chapters describing the function and layout of the SFRs For easy reference the registers are ordered according to two different keys except for GPRs Ordered by address to check which register a given address references Ordered by register name to find the location of a specific register Register Description Format In the respective chapters the function and the layout of the SFRs is described in a specific format which provides a number of details about the described special function register The example below shows how to interpret these details A word register looks like this REG NAME id 2 puc ee Reset Value 14 11 write read only only Bit Function bit field name Explanation of bit field name Description of the functions controlled by this bit field A byte register looks like this REG NAME A164 A84 SFR ESFR XReg Reset Value 15 14 13 12 1 10 9 8 7 6 5 4 3 2 Elements REG NAME Name of this register A16 A8 Long 16 bit address Short 8 bit address SFR ESFR XRegRegister space SFR ESFR or External XBUS Register p Register contents after reset 0 1 defined value X undefined U unchanged undefined X after power up hwbit Bits that are set cleared
123. 3 6 6 1 Alternate Functions of Port 5 scu o Rr RR RTT 6 23 6 7 POM 2 usan awh eek ate Cae ewena a ar s db qusdpdde Sd E So 6 25 6 7 1 Alternate Functions of Port6 ullllllllllllllllln 6 26 6 8 POMS sa ducto ERE bout bE Bates ead tea ra C da usd dd eR d E S d 6 30 6 8 1 A Alternate Functions of Port 7 00 0000 cece eee 6 31 6 9 DOE dint sat eo ate beat trip ENT Mu Ae ane IM Ate 6 34 6 9 1 Alternate Functions of Port8 0 00 22 cee eee 6 35 7 Dedicated PINS iux acude senina eee E wha ENSE yee tate 7 1 8 The External Bus Interface Lllelse 8 1 8 1 External BUS MOOSS ax sa coe sit canted a Rand d e rd Lane waa 8 2 8 2 Programmable Bus Characteristics 00 00 eee eee 8 10 8 3 READY Controlled Bus Cycles 0 00 cece eens 8 15 8 4 Controlling the External Bus Controller 000 00 00s 8 16 8 5 EBC Idle State zie dts kao cb OEE IN ese E UE UEM E 8 24 8 6 External BUS AIDIEAUOED usce wae tatg nm CEN TANG abe Ses SENE 8 25 8 7 The XBUS Interfa6B 3 cox Ree bet E S Sr A EQUES Ee 8 29 9 The General Purpose Timer Units 9 1 9 1 Timet Block OPTI Mohanta ts ca au cla o s o rebos oo e etae ta 9 1 GAA OPI Core TIMer B3 21 aco ats eg sare hte Ne ied re ec etis 9 3 9 1 2 GPT1 Auxiliary Timers T2 and T4 naaa ees 9 8 9 1 3 Interrupt Control for GPT1 Timers 0 0 0 0 ee 9 15 9 2 Timet BIOCK GP T2 eaa a ete ti
124. 3 Operation and Output Waveform in Mode 0 Semiconductor Group 15 3 SIEMENS The Pulse Width Modulation Module C167 Mode 1 Symmetrical PWM Generation Center Aligned PWM Mode 1 is selected by setting the respective bit PMx in register PWMCONT to 1 In this mode the timer PTx of the respective PWM channel is counting up until it reaches the value in the associated period shadow register Upon the next count pulse the count direction is reversed and the timer starts counting down now with subsequent count pulses until it reaches the value 00004 Upon the next count pulse the count direction is reversed again and the count cycle is repeated with the following count pulses The PWM output signal is switched to a high level when the timer contents are equal to or greater than the contents of the pulse width shadow register while the timer is counting up The signal is switched back to a low level when the respective timer has counted down to a value below the contents of the pulse width shadow register So in mode 1 this PWM value controls both edges of the output signal Note that in mode 1 the period of the PWM signal is twice the period of the timer PWM_Periodyoge1 2 PPx 1 The figure below illustrates the operation and output waveforms of a PWM channel in mode 1 for different values in the pulse width register This mode is referred to as Center Aligned PWM because the value in the pulse width shadow register effects bo
125. 3 13 to output NOP any instruction not accessing port 3 BSET P3 5 P3 13 is now output the rd mod wr reads the P3 13 output latch Semiconductor Group 4 7 SIEMENS The Central Processing Unit CPU C167 e Changing the System Configuration The instruction following an instruction that changes the system configuration via register S YSCON eg the mapping of the internal ROM segmentation stack size cannot use the new resources eg ROM or stack In these cases an instruction that does not access these resources should be inserted Code accesses to the new ROM area are only possible after an absolute branch to this area Note As a rule instructions that change ROM mapping should be executed from internal RAM or external memory e BUSCON ADDRSEL The instruction following an instruction that changes the properties of an external address area cannot access operands within the new area In these cases an instruction that does not access this address area should be inserted Code accesses to the new address area should be made after an absolute branch to this area Note As a rule instructions that change external bus properties should not be executed from the respective external memory area e Timing Instruction pipelining reduces the average instruction processing time in a wide scale from four to one machine cycles mostly However there are some rare cases where a particular pipeline situation causes the processin
126. 4 instructions to an unseparable code sequence during which the interrupt system standard interrupts and PEC requests and Class A Traps NMI stack overflow underflow are disabled A Class B Trap illegal opcode illegal bus access etc however will interrupt the atomic sequence since it indicates a severe hardware problem The interrupt inhibit caused by an ATOMIC instruction gets active immediately ie no other instruction will enter the pipeline except the one that follows the ATOMIC instruction and no interrupt request will be serviced in between All instructions requiring multiple cycles or hold states are regarded as one instruction in this sense eg MUL is one instruction Any instruction type can be used within an unseparable code sequence EXAMPLE ATOMIC 3 The following 3 instructions are locked No NOP required MOV RO 1234H Instruction 1 no other instr enters the pipeline MOV R1 5678H Instruction 2 MUL RO R1 Instruction 3 MUL regarded as one instruction MOV R2 MDL This instruction is out of the scope of the ATOMIC instruction sequence Semiconductor Group 19 12 SIEMENS System Programming C167 19 9 Overriding the DPP Addressing Mechanism The standard mechanism to access data locations uses one of the four data page pointers DPPx which selects a 16 KByte data page and a 14 bit offset within this data page The four DPPs allow immediate access to up to 64 KByte of data In applications with bi
127. 624 Bly GPT1 Timer 3 Interrupt Control Register 0000 T4 FE444 224 GPT1 Timer 4 Register 0000 T4CON b FF44 A24 GPT1 Timer 4 Control Register 0000 T4IC b FF64 B24 GPT1 Timer 4 Interrupt Control Register 00004 T5 FE464 23H GPT2 Timer 5 Register 0000 T5CON b FF46 A3y GPT2 Timer 5 Control Register 0000 T5IC b FF66 B3y GPT2 Timer 5 Interrupt Control Register 00004 T6 FE484 244 GPT2 Timer 6 Register 0000 T6CON b FF48y A4y GPT2 Timer 6 Control Register 0000 T6IC b FF68y B44 GPT2 Timer 6 Interrupt Control Register 00004 T7 F050 E 28 CAPCOM Timer 7 Register 00004 T78CON b FF20 904 CAPCOM Timer 7 and 8 Control Register 00004 T7IC b F17A4 E BDy CAPCOM Timer 7 Interrupt Control Register 0000 T7REL F0544 E 2Aj CAPCOM Timer 7 Reload Register 0000 T8 F052 E 29 CAPCOM Timer 8 Register 00004 T8IC b F17C4 E BE CAPCOM Timer 8 Interrupt Control Register 00004 T8REL FO564 E 2By CAPCOM Timer 8 Reload Register 0000 TFR b FFAC D6y Trap Flag Register 0000 UAR EFn2 X CAN Upper Arbitration Register msg n UUUU WDT FEAE 57H Watchdog Timer Register read only 0000 WDTCON b FFAE D74 Watchdog Timer Control Register 000X42 XPOIC b F186 E C3 X Peripheral 0 Interrupt Control Register 00004 XP1IC b F18E E C7 X Peripheral 1 Interrupt Control Register 00004 XP2IC b F196 E CBy X Peripheral 2 Interrupt Control Register 00004 Semiconductor Group 20 10 SIEMENS The Register Set C167 Name Physic
128. 67s are to be connected in this way the external glue logic can be left out In this case one of the controllers must be operated in its Master Mode default after reset DP6 7 0 while the other one must be operated in its Slave Mode selected with DP6 7 1 In Slave Mode the C167 inverts the direction of its HLDA pin and uses it as an input while the master s HLDA pin remains an output This approach does not require any additional glue logic for the bus arbitration see figure below HOLD HLDA C167 in C167 in Master Mode Slave Mode BREQ BREQ MCS02567 Figure 8 12 Sharing External Resources using Slave Mode When the bus arbitration is enabled HLDEN 1 the three corresponding pins are automatically controlled by the EBC Normally the respective port direction register bits retain their reset value which is 0 This selects Master Mode where the device operates compatible with earlier versions Slave Mode is enabled by intentionally switching pin BREQ to output DP6 72 1 which is neither required for Master Mode nor for earlier devices Semiconductor Group 8 26 SIEMENS The External Bus Interface C167 Entering the Hold State Access to the C167 s external bus is requested by driving its HOLD input low After synchronizing this signal the C167 will complete a current external bus cycle if any is active release the external bus and grant access to it by driving the HLDA output low During hold state th
129. 7 6 5 4 3 2 1 0 14 13 12 11 10 rw DPP1 FE02 014 SFR Reset Value 00014 15 14 11 10 9 8 7 6 5 4 3 2 1 0 13 12 rw DPP2 FE04 024 SFR Reset Value 00024 15 14 11 10 9 8 7 6 5 4 3 2 1 0 13 12 rw DPP3 FE06 034 SFR Reset Value 00034 15 14 11 10 9 8 7 6 5 4 3 2 1 0 13 12 rw Bit Function DPPxPN Data Page Number of DPPx Specifies the data page selected via DPPx Only the least significant two bits of DPPx are significant when segmentation is disabled Semiconductor Group 4 20 SIEMENS The Central Processing Unit CPU C167 Data paging is performed by concatenating the lower 14 bits of an indirect or direct long 16 bit address with the contents of the DDP register selected by the upper two bits of the 16 bit address The content of the selected DPP register specifies one of the 1024 possible data pages This data page base address together with the 14 bit page offset forms the physical 24 20 18 bit address In case of non segmented memory mode only the two least significant bits of the implicitly selected DPP register are used to generate the physical address Thus extreme care should be taken when changing the content of a DPP register if a non segmented memory model is selected because otherwise unexpected results could occur In case of the segmented memory mode the selected number of segment address bits 9 2 5 2 or 3 2 of the respective DPP register is output on the segm
130. C supports the following conversion modes Fixed Channel Single Conversion produces just one result from the selected channel Fixed Channel Continuous Conversion repeatedly converts the selected channel Auto Scan Single Conversion produces one result from each of a selected group of channels e Auto Scan Continuous Conversion repeatedly converts the selected group of channels e Wait for ADDAT Read Mode start a conversion automatically when the previous result was read e Channel Injection Mode insert the conversion of a specific channel into a group conversion auto scan A set of SFRs and port pins provide access to control functions and results of the ADC Ports amp Direction Control Data Registers Control Registers Interrupt Control Alternate Functions ADDAT ADCON ADCIC ANO P5 0 AN15 P5 15 ADDAT2 E ADEIC Port 5 Data Register ADCIC A D Converter Interrupt Control Register A D Converter Result Register End of Conversion A D Converter Channel Injection Result Register ADEIC A D Converter Interrupt Control Register A D Converter Control Register Overrun Error Channel Injection Figure 16 1 SFRs and Port Pins associated with the A D Converter Semiconductor Group 16 1 SIEMENS The Analog Digital Converter C167 The external analog reference voltages Varer and VAqawp are fixed The separate supply for the ADC reduces the interference with other digital signals The sample time as well as the conve
131. C167 Pins P7 7 P7 4 CC311O CC281O combine internal bus data and alternate data output before the port latch input as do the Port 2 pins Write ODP7 y Open Drain Latch Read ODP7 y Write DP7 y Direction Ea Read DP7 y 1 xy MUX Output P7 y Alternate Latch gt mm g CCzlO Data Output Buffer I n 1 e r n a ov c n Write Port P7 y 24 Compare Trigger Read P2 y lt y 4 7 Alternate Latch Data Input z 28 31 Alternate Pin Data Input MCB01986 Figure 6 22 Block Diagram of Port 7 Pins P7 7 P7 4 Semiconductor Group 6 33 SIEMENS Parallel Ports C167 6 9 Ports If this 8 bit port is used for general purpose IO the direction of each line can be configured via the corresponding direction register DP8 Each port line can be switched into push pull or open drain mode via the open drain control register ODP8 P8 FFD4 EAy SFR Reset Value 00 9 8 7 6 5 4 3 2 1 0 z rw rw rw rw rw rw rw rw Bit Function P8 y Port data register P8 bit y DP8 FFD6 EBy SFR Reset Value 00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DP68 7 DP8 6 DP8 5 DP8 4 DP8 3 DP8 2 DP8 1 DP8 0 PS S T x a z T DP8 y Port direction register DP8 bit y DP8 y 0 Port line P8 y is an input high impedance DP8 y 1 Port line P8 y is an output Bit Function ODPS8 F1D6 EBp ESF
132. CO 15 CAPCOM1 Register 0 15 CC16 31 CAPCOM2 Register 16 31 TO1CON CAPCOM1 Timers TO and T1 Control Register CCMO 8 CAPCOM1 Mode Control Register 0 3 T78CON CAPCOM2 Timers T7 and T8 Control Register CCM4 7 CAPCOMe Mode Control Register 4 7 TOIC T1IC CAPCOM Timer 0 1 Interrupt Control Register CC0 15IC CAPCOM1 Interrupt Control Register 0 15 T7IC T8IC CAPCOMe Timer 7 8 Interrupt Control Register CC16 31ICCAPCOM2 Interrupt Control Register 16 31 Figure 14 1 SFRs and Port Pins associated with the CAPCOM Units Semiconductor Group 14 1 SIEMENS The Capture Compare Units C167 A CAPCOM unit is typically used to handle high speed IO tasks such as pulse and waveform generation pulse width modulation or recording of the time at which specific events occur It also allows the implementation of up to 16 software timers The maximum resolution of the CAPCOM units is 400 ns 20 MHz CPU clock Each CAPCOM unit consists of two 16 bit timers TO T1 in CAPCOM1 T7 T8 in CAPCOM2 each with its own reload register TXREL and a bank of sixteen dual purpose 16 bit capture compare registers CCO through CC15 in CAPCOM 1 CC16 through CC31 in CAPCOM2 The input clock for the CAPCOM timers is programmable to several prescaled values of the CPU clock or it can be derived from an overflow underflow of timer T6 in block GPT2 TO and T7 may also operate in counter mode from an external input where they can be clocked
133. CON T6CON FF48j A4p SFR Reset Value 0000 15 14 13 12 1i 10 9 8 7 6 5 4 3 2 1 0 rw e rw rw rw rw rw rw rw Bit Function T6l Timer 6 Input Selection Depends on the Operating Mode see respective sections T6M Timer 6 Mode Control Basic Operating Mode 000 Timer Mode 001 Counter Mode 010 Gated Timer with Gate active low 011 Gated Timer with Gate active high 1XX Reserved Do not use this combination T6R Timer 6 Run Bit Te6R 2 0 Timer Counter 6 stops T6R 1 Timer Counter 6 runs T6UD Timer 6 Up Down Control T6UDE Timer 6 External Up Down Enable T6OE Alternate Output Function Enable T6OE 0 Alternate Output Function Disabled T6OE 1 Alternate Output Function Enabled T6OTL Timer 6 Output Toggle Latch Toggles on each overflow underflow of T6 Can be set or reset by software T6SR Timer 6 Reload Mode Enable T6SR 0 Reload from register CAPREL Disabled T6SR 1 Reload from register CAPREL Enabled For the effects of bits TEUD and T6UDE refer to the direction table below Timer 6 Run Bit The timer can be started or stopped by software through bit T6R Timer T6 Run Bit If T6R 0 the timer stops Setting T6R to 1 will start the timer In gated timer mode the timer will only run if T6R 1 and the gate is active high or low as programmed Semiconductor Group 9 18 SIEMENS The General Purpose Timer Units C167
134. CPU Priority Level Defines the current priority level for the CPU Fp Highest priority level Op Lowest priority level IEN Interrupt Enable Control Bit globally enables disables interrupt requests 0 Interrupt requests are disabled 1 Interrupt requests are enabled CPU Priority ILVL defines the current level for the operation of the CPU This bit field reflects the priority level of the routine that is currently executed Upon the entry into an interrupt service routine this bit field is updated with the priority level of the request that is being serviced The PSW is saved on the system stack before The CPU level determines the minimum interrupt priority level that will be serviced Any request on the same or a lower level will not be acknowledged The current CPU priority level may be adjusted via software to control which interrupt request sources will be acknowledged PEC transfers do not really interrupt the CPU but rather steal a single cycle so PEC services do not influence the ILVL field in the PSW Hardware traps switch the CPU level to maximum priority ie 15 so no interrupt or PEC requests will be acknowledged while an exception trap service routine is executed Note The TRAP instruction does not change the CPU level so software invoked trap service routines may be interrupted by higher requests Interrupt Enable bit IEN globally enables or disables PEC operation and the acceptance of
135. Code fetches are always made on even byte addresses The highest possible code storage location in the XRAM is either 00 E7FE for single word instructions or 00 E7FC for double word instructions The respective location must contain a branch instruction unconditional because sequential boundary crossing from XRAM to external memory is not supported and causes erroneous results Any word and byte data read accesses may use the indirect or long 16 bit addressing modes There is no short addressing mode for XRAM operands Any word data access is made to an even byte address The highest possible word data storage location in the XRAM is 00 E7FEy For PEC data transfers the XRAM can be accessed independent of the contents of the DPP registers via the PEC source and destination pointers Note As the XRAM appears like external memory it cannot be used for the C167 s system stack or register banks The XRAM is not provided for single bit storage and therefore is not bit addressable The on chip XRAM is accessed without any waitstates using 16 bit demultiplexed bus cycles which take 100 ns 20 MHz fcpy Even if the XRAM is used like external memory it does not occupy BUSCONX ADDRSELx registers but rather is selected via additional dedicated XBCON XADRS registers These registers are mask programmed and are not user accessible With these registers the address area 00 E000 to 00 E7FF is reserved for XRAM accesses XRAM Access via External M
136. ESFR uses the other 512 bytes E SFRs are wordwide registers which are used for controlling and monitoring functions of the different on chip units Unused E SFR addresses are reserved for future members of the C167 family with enhanced functionality External Bus Interface In order to meet the needs of designs where more memory is required than is provided on chip up to 16 MBytes of external RAM and or ROM can be connected to the microcontroller via its external bus interface The integrated External Bus Controller EBC allows to access external memory and or peripheral resources in a very flexible way For up to five address areas the bus mode multiplexed demultiplexed the data bus width 8 bit 16 bit and even the length of a bus cycle waitstates signal delays can be selected independently This allows to access a variety of memory and peripheral components directly and with maximum efficiency If the device does not run in Single Chip Mode where no external memory is required the EBC can control external accesses in one of the following four different external access modes 16 18 20 24 bit Addresses 16 bit Data Demultiplexed 16 18 20 24 bit Addresses 8 bit Data Demultiplexed 16 18 20 24 bit Addresses 16 bit Data Multiplexed 16 18 20 24 bit Addresses 8 bit Data Multiplexed The demultiplexed bus modes use PORT1 for addresses and PORTO for data input output The multiplexed bus modes use PORTO for both
137. F for the word data type or from 80 to 7F 1 for the byte data type For Boolean bit operations with only one operand the N flag represents the previous state of the specified bit For Boolean bit operations with two operands the N flag represents the logical XORing of the two specified bits C Flag After an addition the C flag indicates that a carry from the most significant bit of the specified word or byte data type has been generated After a subtraction or a comparison the C flag indicates a borrow which represents the logical negation of a carry for the addition This means that the C flag is set to 1 if no carry from the most significant bit of the specified word or byte data type has been generated during a subtraction which is performed internally by the ALU as a 2 s complement addition and the C flag is cleared when this complement addition caused a carry The C flag is always cleared for logical multiply and divide ALU operations because these operations cannot cause a carry anyhow For shift and rotate operations the C flag represents the value of the bit shifted out last If a shift count of zero is specified the C flag will be cleared The C flag is also cleared for a prioritize ALU operation because a 1 is never shifted out of the MSB during the normalization of an operand For Boolean bit operations with only one operand the C flag is always cleared For Boolean bit operations with two operands the C flag repr
138. FR Reset Value 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Function RGSZ Range Size Selection Defines the size of the address area controlled by the respective BUSCONx ADDRSELx register pair See table below RGSAD Range Start Address Defines the upper bits of the start address A23 of the respective address area See table below Note There is no register ADDRSELO as register BUSCONO controls all external accesses outside the four address windows of BUSCON4 BUSCON1 within the complete address space Semiconductor Group 8 20 SIEMENS The External Bus Interface C167 Definition of Address Areas The four register pairs BUSCON4 ADDRSEL4 BUSCON1 ADDRSEL1 allow to define 4 separate address areas within the address space of the C167 Within each of these address areas external accesses can be controlled by one of the four different bus modes independent of each other and of the bus mode specified in register BUSCONO Each ADDRSELx register in a way cuts out an address window within which the parameters in register BUSCONXx are used to control external accesses The range start address of such a window defines the upper address bits which are not used within the address window of the specified size see table below For a given window size only those upper address bits of the start address are used marked R which are not implicitly used for addresses inside the window The lower bits of the start addr
139. First register R1 is pushed onto the lowest physical stack location according to the selected maximum stack size With the following instruction register R2 will be pushed onto the highest physical stack location although the SP is decremented by 2 as for the previous push operation MOV SP 0F802H Set SP before last entry of physical stack of 256 words EC SP F802H Physical stack address FA02H PUSH R1 SP F800H Physical stack address FAOOH PUSH R2 SP F7FEH Physical stack address FBFEH The effect of the address transformation is that the physical stack addresses wrap around from the end of the defined area to its beginning When flushing and filling the internal stack this circular stack mechanism only requires to move that portion of stack data which is really to be re used ie the upper part of the defined stack area instead of the whole stack area Stack data that remain in the lower part of the internal stack need not be moved by the distance of the space being flushed or filled as the stack pointer automatically wraps around to the beginning of the freed part of the stack area Note This circular stack technique is applicable for stack sizes of 32 to 512 words STKSZ 000 to 100 it does not work with option STKSZ 111g which uses the complete internal RAM for system stack Semiconductor Group 19 6 SIEMENS System Programming C167 When a boundary is reached the stack underflow or
140. Generation Each of the four channels of the PWM module can generate an individual interrupt request Each of these channel interrupts can activate the common module interrupt which actually interrupts the CPU This common module interrupt is controlled by the PWM Module Interrupt Control register PWMIC The interrupt service routine can determine the active channel interrupt s from the channel specific interrupt request flags PIRx in register PWMCONO The interrupt request flag PIRx of a channel is set at the beginning of anew PWM cycle ie upon loading the shadow registers This indicates that registers PPx and PWx are now ready to receive a new value If a channel interrupt is enabled via its respective PIEx bit also the common interrupt request flag PWMIR in register PWMIC is set provided that it is enabled via the common interrupt enable bit PWMIE Note The channel interrupt request flags PIRx in register PWMCONO are not automatically cleared by hardware upon entry into the interrupt service routine so they must be cleared via software The module interrupt request flag PWMIR is cleared by hardware upon entry into the service routine regardless of how many channel interrupts were active However it will be set again if during execution of the service routine a new channel interrupt request is generated PWMIC F17Ey BFy ESFR Reset Value 004 REL ROL e aL E E E Pm US INE CNN EE Note Please refer to the general Interrup
141. H7 CP FFu CPU General Purpose Byte Register RH7 UU 15 Semiconductor Group 20 3 SIEMENS The Register Set C167 20 2 Special Function Registers ordered by Name The following table lists all SFRs which are implemented in the C167 in alphabetical order Bit addressable SFRs are marked with the letter b in column Name SFRs within the Extended SFR Space ESFRs are marked with the letter E in column Physical Address Registers within on chip X Peripherals CAN are marked with the letter X in column Physical Address Name Physical 8 Bit Description Reset Address Address Value ADCIC b FF98 CCy A D Converter End of Conversion Interrupt 00001 Control Register ADCON _ b FFAO0 DO A D Converter Control Register 0000 ADDAT FEAOW 50H A D Converter Result Register 00004 ADDAT2 FOAO E 50 A D Converter 2 Result Register 00004 ADDRSEL1 FE18 0C Address Select Register 1 0000 ADDRSEL2 FE1A 0Dy Address Select Register 2 0000 ADDRSEL3 FE1Cy OEY Address Select Register 3 00004 ADDRSEL4 FE1E OFy Address Select Register 4 00004 ADEIC b FF9A CDg A D Converter Overrun Error Interrupt Control 0000 Register BUSCONO b FFOC 864 Bus Configuration Register 0 0000 BUSCON1 b FF14j 8AQ Bus Configuration Register 1 00004 BUSCON b FF16 8By Bus Configuration Register 2 00004 BUSCONGS b FF18 8Cy Bus Configura
142. INT 00 0090 244 36p GPT2 Timer 5 T5IR T5IE T5INT 00 00944 254 37p GPT2 Timer 6 T6IR T6IE T6INT 00 0098 264 38p GPT2 CAPREL Register CRIR CRIE CRINT 00 009C 274 39p A D Conversion Complete ADCIR ADCIE ADCINT 00 00A0 284 40p A D Overrun Error ADEIR ADEIE ADEINT 00 00A44 294 41p ASCO Transmit SOTIR SOTIE SOTINT 00 00A8 2A 42p ASCO Transmit Buffer SOTBIR SOTBIE SOTBINT 0001104 474 71p ASCO Receive SORIR SORIE SORINT 00 00AC4 2By 435 ASCO Error SOEIR SOEIE SOEINT 00 00B0 2Cy 445 SSC Transmit SSCTIR SSCTIE SSCTINT 00 00B4 2Dy 45p SSC Receive SSCRIR SSCRIE SSCRINT 00 00B8 2E 465 SSC Error SSCEIR SSCEIE SSCEINT 00 00BC4 2Fy 47p PWM Channel 0 3 PWMIR PWMIE PWMINT 00 00FC 3Fj 63p CAN Interface XPOIR XPOIE XPOINT 00 0100 404 64p X Peripheral Node 1 XP1IR XP1IE XP1INT 00 0104 414 65p X Peripheral Node 2 XP2IR XP2IE XP2INT 00 0108 424 66p PLL Unlock XP3IR XP3IE XP3INT 00 010C 434 67p Note Each entry of the interrupt vector table provides room for two word instructions or one doubleword instruction The respective vector location results from multiplying the trap number by 4 4 bytes per entry For devices which do not incorporate a CAN Module or a PLL the respective interrupt nodes may be used for software triggered interrupts see X Peripheral node n Semiconductor Group 5 4 Interrupt and Trap Functions C167 SIEMENS The table below lists the vector locations for hardware tra
143. Injection Enable ADCRQ ADC Channel Injection Request Flag ADSTC ADC Sample Time Control ADCTC ADC Conversion Time Control ADSTC and ADCTC control the conversion timing Refer to Conversion Timing Control Bit field ADCH specifies the analog input channel which is to be converted first channel of a conversion sequence in auto scan modes Bit field ADM selects the operating mode of the A D converter A conversion or a sequence is then started by setting bit ADST Clearing ADST stops the A D converter after a certain operation which depends on the selected operating mode The busy flag read only ADBSY is set as long as a conversion is in progress Semiconductor Group 16 3 SIEMENS The Analog Digital Converter C167 The result of a conversion is stored in the result register ADDAT or in register ADDAT2 for an injected conversion Note Bit field CHNR of register ADDAT is loaded by the ADC to indicate which channel the result refers to Bit field CHNR of register ADDAT2 is loaded by the CPU to select the analog channel which is to be injected ADDAT FEAO 504 SFR Reset Value 00004 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw ADDAT2 F0A0j 504 ESFR Reset Value 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw Bit Function ADRES A D Conversion Result 10 bit CHNR Channel Number 4 bit identifies the converted analog channel A conversion is started by setting
144. Interrupt Control Registers 0 0 ccc ees 5 6 5 2 Operation of the PEC Channels 0 0 0 0 cece eee eee 5 11 5 3 Prioritization of Interrupt and PEC Service Requests 5 14 5 4 Saving the Status during Interrupt Service 000000 5 15 5 5 Interrupt Response Times 2000 ce es 5 17 5 5 1 PEC Response Times wii cance cee RR x RR mh wees 5 19 5 6 Extertial Intermupls 3 4 seta RA gwd SORTER eS RR SEED Oe Saws 5 21 5 7 Trap F NCGIONS E a a iot ard nq eke en PUR a Id IH 8 api UR IUE wane hawks 5 24 6 Parallel PORS e aac eI EEOERPENMERENCeESS tiie twee ETAGE E SEES 6 1 6 1 PORTO aia teks gaat ed RENE abaco oU EE IRR ak Re Seu acid e RN ire d 6 5 6 1 1 Alternate Functions of PORTO cre Seo ek ERIS EF EE PEE Erbe 6 6 6 2 PORTI zu dsosuc iota aci toe dome See bb re gets dele rator 6 8 6 2 1 Alternate Functions of PORT vo eso kw kr eIezcekrkem ems iip wes 6 9 6 3 go B NM MC Ce og Se Soar ETE 6 11 6 3 1 A Alternate Functions of Port2 0 aaaeeeaa 6 12 Semiconductor Group l 1 SIEMENS d Table of Contents Page 6 4 ROMS tiie ser soap ma seR aret apad na actae Sa da da cs i ae take dE d ad 6 15 6 4 1 Alternate Functions of Port 3 v osa EX EXAOUE Oe CREAR EARS 6 16 6 5 POMS ovni Suche cured iei uri ei ados sudare educa CU gre iuvw t d 6 20 6 5 1 Alternate Functions of Port 4 0 00022 cece eee 6 20 6 6 POM Bo uineas dws Eee Cae eee bats dta qusqiddsu Ed Canaan 6 2
145. J l Figure 4 8 Implicit CP Use by Short GPR Addressing Modes The Stack Pointer SP This non bit addressable register is used to point to the top of the internal system stack TOS The SP register is pre decremented whenever data is to be pushed onto the stack and it is post incremented whenever data is to be popped from the stack Thus the system stack grows from higher toward lower memory locations Since the least significant bit of register SP is tied to 0 and bits 15 through 12 are tied to 1 by hardware the SP register can only contain values from F000 to FFFE This allows to access a physical stack within the internal RAM of the C167 A virtual stack usually bigger can be realized via software This mechanism is supported by registers STKOV and STKUN see respective descriptions below The SP register can be updated via any instruction which is capable of modifying an SFR Note Due to the internal instruction pipeline a POP or RETURN instruction must not immediately follow an instruction updating the SP register SP FE12 094 SFR Reset Value FC00 15 14 11 10 9 8 7 6 5 4 3 2 1 0 13 12 r r r r rw r Bit Function sp Modifiable portion of register SP Specifies the top of the internal system stack Semiconductor Group 4 24 SIEMENS The Central Processing Unit CPU C167 The Stack Overflow Pointer STKOV This non bit addressable register is compared against the
146. K The Synchronization Segment Sync seg is always 1 t long The Propagation Time Segment and the Phase Buffer Segment1 combined to Tseg1 defines the time before the sample point while Phase Buffer Segment2 Tseg2 defines the time after the sample point The length of these segments is programmable except Sync Seg Note For exact definition of these segments please refer to the CAN Specification 1 Bit Time TSegl 1 Time Quantum Sample Point Transmit Point la MCTO2573 Figure 23 3 Bit Timing Definition Bit Timing Register EF04 XReg Reset Value UUUU 15 14 13 12 1i 10 9 8 7 6 5 4 3 2 1 0 oo TSEG2 TSEG1 SJW BRP r rw rw rw rw Bit Function BRP Baud Rate Prescaler For generating the bit time quanta the CPU frequency is divided by 2 BRP 1 SJW Re Synchronization Jump Width Adjust the bit time by maximum SJW 1 time quanta for resynchronization TSEG1 Time Segment before sample point There are TSEG1 1 time quanta before the sample point Valid values for TSEG1 are 2 15 TSEG2 Time Segment after sample point There are TSEG2 1 time quanta after the sample point Valid values for TSEG2 are 1 7 Note This register can only be written if the configuration change enable bit CCE is set Semiconductor Group 23 10 SIEMENS The On Chip CAN Interface C167 Mask Registers Messages can use standard or extended identifiers Incoming frames are masked with
147. L Note Only state transitions of TGOTL which are caused by the overflows underflows of T6 will trigger the counter function of T5 Modifications of TGOTL via software will NOT trigger the counter function of T5 The maximum input frequency which is allowed in counter mode is fcpy 4 2 5 MHz fopy 20 MHz To ensure that a transition of the count input signal which is applied to TSIN is correctly recognized its level should be held high or low for at least 4 fep cycles before it changes Semiconductor Group 9 26 SIEMENS The General Purpose Timer Units C167 Timer Concatenation Using the toggle bit TEOTL as a clock source for the auxiliary timer in counter mode concatenates the core timer T6 with the auxiliary timer Depending on which transition of T6OTL is selected to clock the auxiliary timer this concatenation forms a 32 bit or a 33 bit timer counter e 32 bit Timer Counter If both a positive and a negative transition of TGOTL is used to clock the auxiliary timer this timer is clocked on every overflow underflow of the core timer T6 Thus the two timers form a 32 bit timer 33 bit Timer Counter If either a positive or a negative transition of T6OTL is selected to clock the auxiliary timer this timer is clocked on every second overflow underflow of the core timer T6 This configuration forms a 33 bit timer 16 bit core timer T6OTL 16 bit auxiliary timer The count directions of the two concatenated timers are not requ
148. MI trap on the highest and the stack underflow trap on the lowest priority All class B traps have the same trap priority trap priority I When several class B traps get active at a time the corresponding flags in the TFR register are set and the trap service routine is entered Since all class B traps have the same vector the priority of service of simultaneously occurring class B traps is determined by software in the trap service routine A class A trap occurring during the execution of a class B trap service routine will be serviced immediately During the execution of a class A trap service routine however any class B trap occurring will not be serviced until the class A trap service routine is exited with a RETI instruction In this case the occurrence of the class B trap condition is stored in the TFR register but the IP value of the instruction which caused this trap is lost In the case where e g an Undefined Opcode trap class B occurs simultaneously with an NMI trap class A both the NMI and the UNDOPC flag is set the IP of the instruction with the undefined opcode is pushed onto the system stack but the NMI trap is executed After return from the NMI service routine the IP is popped from the stack and immediately pushed again because of the pending UNDOPC trap External NMI Trap Whenever a high to low transition on the dedicated external NMI pin Non Maskable Interrupt is detected the NMI flag in register TFR is set and
149. Mode the XCLK signal will be turned off which will stop the operation of the CAN Module Any message transfer is interrupted In order to ensure that the CAN controller is not stopped while sending a dominant level 0 on the CAN bus the CPU should set bit INIT in the Control Register prior to entering Power Down Mode The CPU can check if a transmission is in progress by reading bits TXRQ and NEWDAT in the message objects and bit TXOK in the Control Register After returning from Power Down Mode via hardware reset the CAN Module has to be reconfigured Semiconductor Group 23 19 SIEMENS The On Chip CAN Interface C167 The CAN Application Interface The on chip CAN Module of the C167 does not incorporate the physical layer that connects to the CAN bus This must be provided externally The module s CAN controller is connected to this physical layer ie the CAN bus via two signals CAN Signal Port Pin Function CAN RXD Port 4 5 Receive data from the physical layer of the CAN bus CAN TXD Port 4 6 Transmit data to the physical layer of the CAN bus A logic low level 0 is interpreted as the dominant CAN bus level a logic high level 1 is interpreted as the recessive CAN bus level Note These CAN signals are only available on the Port 4 pins if Port 4 is not programmed to output all 8 segment address lines Select 0 2 or 4 segment address lines if the CAN interface is to be used Figure 23 5
150. N Mode Reload Control Capture IVA CPU Clock alo nz Toggle FF T30UT T3IN J veu J Interrupt gt Request T4 TAIN Mode Control CPU Clock Interrupt Request MCT02141 Figure 9 2 GPT1 Block Diagram Semiconductor Group 9 2 SIEMENS The General Purpose Timer Units C167 GPT1 Core Timer T3 The core timer T3 is configured and controlled via its bitaddressable control register T3CON T3CON FF42 Alp SFR Reset Value 00004 15 14 13 12 1i 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw Bit Function T3I Timer 3 Input Selection Depends on the operating mode see respective sections T3M Timer 3 Mode Control Basic Operating Mode 000 Timer Mode 001 Counter Mode 010 Gated Timer with Gate active low 011 Gated Timer with Gate active high 1XX Reserved Do not use this combination T3R Timer 3 Run Bit TSR 2 0 Timer Counter 3 stops T3R 1 Timer Counter 3 runs T3UD Timer 3 Up Down Control T3UDE Timer 3 External Up Down Enable T30E Alternate Output Function Enable T30E 0 Alternate Output Function Disabled T30E 1 Alternate Output Function Enabled TSOTL Timer 3 Output Toggle Latch Toggles on each overflow underflow of T3 Can be set or reset by software For the effects of bits T3UD and T3UDE refer to the direction table below Timer 3 Run Bit The timer can be started or
151. NLY be executed during the time between a reset and execution of either the EINIT End of Initialization or the SRVWDT Service Watchdog Timer instruction Either one of these instructions disables the execution of DISWDT When the watchdog timer is not disabled via instruction DISWDT it will continue counting up even during Idle Mode If it is not serviced via the instruction SRVWDT by the time the count reaches FFFF the watchdog timer will overflow and cause an internal reset This reset will pull the external reset indication pin RSTOUT low It differs from a software or external hardware reset in that bit WDTR Watchdog Timer Reset Indication Flag of register WDTCON will be set A hardware reset or the SRVWDT instruction will clear this bit Bit WDTR can be examined by software in order to determine the cause of the reset A watchdog reset will also complete a running external bus cycle before starting the internal reset sequence if this bus cycle does not use READY or samples READY active low after the programmed waitstates Otherwise the external bus cycle will be aborted Note After a hardware reset that activates the Bootstrap Loader the watchdog timer will be disabled Semiconductor Group 12 2 SIEMENS The Watchdog Timer WDT 80C166 To prevent the watchdog timer from overflowing it must be serviced periodically by the user software The watchdog timer is serviced with the instruction SRVWDT which is a protected 32 bit in
152. O and Alternate Functions Semiconductor Group 6 16 SIEMENS Parallel Ports C167 The port structure of the Port 3 pins depends on their alternate function see figure below When the on chip peripheral associated with a Port 3 pin is configured to use the alternate input function it reads the input latch which represents the state of the pin via the line labeled Alternate Data Input Port 3 pins with alternate input functions are TOIN T2IN T3IN TAIN T3EUD and CAPIN When the on chip peripheral associated with a Port 3 pin is configured to use the alternate output function its Alternate Data Output line is ANDed with the port output latch line When using these alternate functions the user must set the direction of the port line to output DP3 y 1 and must set the port output latch P3 y21 Otherwise the pin is in its high impedance state when configured as input or the pin is stuck at 0 when the port output latch is cleared When the alternate output functions are not used the Alternate Data Output line is in its inactive state which is a high level 1 Port 3 pins with alternate output functions are T6OUT T3OUT TxDO and CLKOUT When the on chip peripheral associated with a Port 3 pin is configured to use both the alternate input and output function the descriptions above apply to the respective current operating mode The direction must be set accordingly Port 3 pins with alternate input output functions
153. OH O during reset 0 Pins WR and BHE retain their normal function 1 Pin WR acts as WRL pin BHE acts as WRH CLKEN System Clock Output Enable CLKOUT 0 CLKOUT disabled pin may be used for general purpose IO 1 CLKOUT enabled pin outputs the system clock signal BYTDIS Disable Enable Control for Pin BHE Set according to data bus width 0 Pin BHE enabled 1 Pin BHE disabled pin may be used for general purpose IO ROMEN Internal ROM Enable Set according to pin EA during reset 0 Internal ROM disabled accesses to the ROM area use the external bus 1 Internal ROM enabled SGTDIS Segmentation Disable Enable Control 0 Segmentation enabled CSP is saved restored during interrupt entry exit 1 Segmentation disabled Only IP is saved restored ROMS1 Internal ROM Mapping 0 Internal ROM area mapped to segment 0 00 0000 00 7FFF 1 Internal ROM area mapped to segment 1 01 0000 01 7FFFj STKSZ System Stack Size Selects the size of the system stack in the internal RAM from 32 to 1024 words Note Register SYSCON cannot be changed after execution of the EINIT instruction Bit SGTDIS controls the correct stack operation push pop of CSP or not during traps and interrupts Semiconductor Group 8 17 SIEMENS The External Bus Interface C167 The layout of the five BUSCON registers is identical Registers BUSCONA BUSCON 1 which
154. OPA BTRAP 000028 OAH Access Illegal Instruction Access ILLINA BTRAP 00 0028 OAH Illegal External Bus ILLBUS BTRAP 00 0028 OAH Access Reserved 2Cy 3Cy OBy OF y Software Traps Any Any Current TRAP Instruction 00 00004 00H 7Fu CPU 00 01 FC Priority in steps of 4u Semiconductor Group 5 5 SIEMENS Interrupt and Trap Functions C167 Normal Interrupt Processing and PEC Service During each instruction cycle one out of all sources which require PEC or interrupt processing is selected according to its interrupt priority This priority of interrupts and PEC requests is programmable in two levels Each requesting source can be assigned to a specific priority A second level called group priority allows to specify an internal order for simultaneous requests from a group of different sources on the same priority level At the end of each instruction cycle the one source request with the highest current priority will be determined by the interrupt system This request will then be serviced if its priority is higher than the current CPU priority in register PSW Interrupt System Register Description Interrupt processing is controlled globally by register PSW through a general interrupt enable bit IEN and the CPU priority field ILVL Additionally the different interrupt sources are controlled individually by their specific interrupt control registers IC Thus the acceptance of requests by the CPU is deter
155. P6 b FFCE E7y Port 6 Direction Control Register 00H P7 b FFDO E84 Port 7 Register 8 bits 00H DP7 b FFD2 E94 Port 7 Direction Control Register 00H Semiconductor Group 20 18 The Register Set C167 SIEMENS Name Physical 8 Bit Description Reset Address Address Value P8 b FFD4 EAH Port 8 Register 8 bits 00u DP8 b FFD6 EB Port 8 Direction Control Register 00H Note 1 The system configuration is selected during reset 2 Bit WDTR indicates a watchdog timer triggered reset 20 4 Special Notes PEC Pointer Registers The source and destination pointers for the peripheral event controller are mapped to a special area within the internal RAM Pointers that are not occupied by the PEC may therefore be used like normal RAM During Power Down mode or any warm reset the PEC pointers are preserved The PEC and its registers are described in chapter Interrupt and Trap Functions GPR Access in the ESFR Area The locations 00 F000H 00 F01EH within the ESFR area are reserved and provide access to the current register bank via short register addressing modes The GPRs are mirrored to the ESFR area which allows access to the current register bank even after switching register spaces see example below MOV R5 DP3 GPR access via SFR area EXTR 1 MOV R5 ODP3 GPR access via ESFR area Writing Bytes to SFRs All special function registers may be accessed wordwise or bytewi
156. PU will enter the stack underflow trap routine Again which IP value will be pushed onto the system stack depends on which operation caused the increment of the SP When an implicit increment of the SP is made through a POP or return instruction the IP value pushed is the address of the following instruction When the SP is incremented by an add instruction the pushed IP value represents the address of the instruction after the instruction following the add instruction Undefined Opcode Trap When the instruction currently decoded by the CPU does not contain a valid C167 opcode the UNDOPC flag is set in register TFR and the CPU enters the undefined opcode trap routine The IP value pushed onto the system stack is the address of the instruction that caused the trap This can be used to emulate unimplemented instructions The trap service routine can examine the faulting instruction to decode operands for unimplemented opcodes based on the stacked IP In order to resume processing the stacked IP value must be incremented by the size of the undefined instruction which is determined by the user before a RETI instruction is executed Protection Fault Trap Whenever one of the special protected instructions is executed where the opcode of that instruction is not repeated twice in the second word of the instruction and the byte following the opcode is not the complement of the opcode the PRTFLT flag in register TFR is set and the CPU enters the prot
157. Peripheral 1 Interrupt Control Register 00004 CC31IC b F194 E CA CAPCOM Register 31 Interrupt Control Register 0000 XP2IC b F196 E CB X Peripheral 2 Interrupt Control Register 00004 SOTBIC b F19C E CE Serial Channel 0 Transmit Buffer Interrupt Control 00004 Register XP3IC b FI9E E CFy X Peripheral 3 Interrupt Control Register 0000 EXICON b F1C0 E Ed External Interrupt Control Register 0000 ODP2 b F1C24 E E1y Port 2 Open Drain Control Register 00004 Semiconductor Group 20 13 SIEMENS The Register Set C167 Name Physical 8 Bit Description Reset Address Address Value PICON FiC4 E E24 Port Input Threshold Control Register 0000 ODP3 b F1C6 E E34 Port 3 Open Drain Control Register 0000 ODP6 b F1CE E E7y Port 6 Open Drain Control Register 004 ODP7 b F1D2 E E94 Port 7 Open Drain Control Register 00h ODP8 b F1D6 E EBy Port 8 Open Drain Control Register 004 DPPO FEOO 004 CPU Data Page Pointer 0 Register 10 bits 0000 DPP1 FEO2 O14 CPU Data Page Pointer 1 Register 10 bits 0001 DPP2 FE044 024 CPU Data Page Pointer 2 Register 10 bits 00024 DPP3 FE064 034 CPU Data Page Pointer 3 Register 10 bits 00034 CSP FE08 044 CPU Code Segment Pointer Register 0000 8 bits not directly writeable MDH FEOC 106 CPU Multiply Divide Register High Word 0000 MDL FEOE 074 CPU Multiply Divide Register Low
158. PxHIN Port x High Byte Input Level Selection 0 Pins Px 15 Px 8 switch on standard TTL input levels Ts Pins Px 15 Px 8 switch on special threshold input levels All options for individual direction and output mode control are availbale for each pin independent from the selected input threshold The input hysteresis provides stable inputs from noisy or slowly changing external signals Bit state Figure 6 3 Hysteresis for Special Input Thresholds Alternate Port Functions Each port line has one programmable alternate input or output function associated with it PORTO and PORT 1 may be used as the address and data lines when accessing external memory Port 4 outputs the additional segment address bits A23 19 17 A16 in systems where more than 64 KBytes of memory are to be accessed directly Port 6 provides the optional chip select outputs and the bus arbitration lines Port 2 Port 7 and Port 8 are associated with the capture inputs or compare outputs of the CAPCOM units and or with the outputs of the PWM module Port 2 is also used for fast external interrupt inputs and for timer 7 input Semiconductor Group 6 3 SIEMENS Parallel Ports C167 Port 3 includes alternate input output functions of timers serial interfaces the optional bus control signal BHE WRH and the system clock output CLKOUT Port 5 is used for the analog input channels to the A D converter or timer control signals If an alternate outpu
159. R Reset Value 00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ODP8 ODP8 ODP8 ODP8 ODP8 ODP8 ODP8 ODP8 7 6 5 4 3 2 1 0 a x z T ODP8 y Port 8 Open Drain control register bit y ODP8 y 0 Port line P8 y output driver in push pull mode ODP8 y 1 Port line P8 y output driver in open drain mode Bit Function Semiconductor Group 6 34 SIEMENS Parallel Ports C167 Alternate Functions of Port 8 All Port 8 lines P8 7 P8 0 serve as capture inputs or compare outputs CC23lO CC1610O for the CAPCOM2 unit see table below The usage of the port lines by the CAPCOM unit its accessibility via software and the precautions are the same as described for the Port 2 lines As all other capture inputs the capture input function of pins P8 7 P8 0 can also be used as external interrupt inputs 400 ns sample rate 20 MHz CPU clock Port 8 Pin Alternate Function P8 0 CC16lO Capture input compare output channel 16 P8 1 CC171O Capture input compare output channel 17 P8 2 CC18lO Capture input compare output channel 18 P8 3 CC19IO Capture input compare output channel 19 P8 4 CC20I0 Capture input compare output channel 20 P8 5 CC211IO Capture input compare output channel 21 P8 6 CC2210 Capture input compare output channel 22 P8 7 CC23IO Capture input compare output channel 23 Alternate Function CC2310 CC2210 CC2110 CC201O CC19IO CC18lO CC171O CC16lO Gen
160. R associated with the CAPREL register However interrupt request flag T6IR will be set indicating the overflow underflow of T6 CAPREL Register Iv eg n T6SR T60E v Input tar Interrupt Clock Core Timer T6 T6IR Request Up Down gt To CAPCOM Timers MCB02045 Figure 9 19 GPT2 Register CAPREL in Reload Mode Semiconductor Group 9 29 SIEMENS The General Purpose Timer Units C167 GPT2 Capture Reload Register CAPREL in Capture And Reload Mode Since the reload function and the capture function of register CAPREL can be enabled individually by bits T5SC and T6SR the two functions can be enabled simultaneously by setting both bits This feature can be used to generate an output frequency that is a multiple of the input frequency Interrupt Request Edge Select car Interrupt CRIR Request CAPREL Register VS ee T6OE Input R Interrupt Clock Core Timer T6 tx L Request T To CAPCOM y Up Down Timers MCB02046 Figure 9 20 GPT2 Register CAPREL in Capture And Reload Mode This combined mode can be used to detect consecutive external events which may occur aperiodically but where a finer resolution that means more ticks within the time between two external events is required For this purpose the time between the external events is measured using timer T5 and the CAPREL register Timer T5 runs in timer mode counting up with a frequency of eg fopy 32 The e
161. Register EFn0 XReg Reset Value UUUU 15 14 13 12 1i 10 9 8 7 6 5 4 3 2 1 0 MSGLST RMTPND TXRQ CPUUPD NEWDAT MSGVAL TXIE RXIE INTPND rw rw rw rw rw rw rw rw Bit Function INTPND Interrupt Pending Indicates if this message object has generated an interrupt request see TXIE and RXIE since this bit was last reset by the CPU or not RXIE Receive Interrupt Enable Defines if bit INTPND is set after successful reception of a frame TXIE Transmit Interrupt Enable Defines if bit INTPND is set after successful transmission of a frame 1 MSGVAL Message Valid Indicates if the corresponding message object is valid or not The CAN controller only operates on valid objects Message objects can be tagged invalid while they are changed or if they are not used at all NEWDAT New Data Indicates if new data has been written into the data portion of this message object by CPU transmit objects or CAN controller receive objects since this bit was last reset or not 2 MSGLST Message Lost This bit applies to receive objects only Indicates that the CAN controller has stored a new message into this object while NEWDAT was still set ie the previously stored message is lost CPUUPD CPU Update This bit applies to transmit objects only Indicates that the corresponding message object may not be transmitted now The CPU sets this bit in order to inhibit the transmission of a message that is currently updated or
162. Reset Value UUUU 15 14 13 12 11 430 9 8 7 6 5 4 3 2 1 0 rw rw r r r Bit Function ID28 0 Identifier 29 bit Mask to filter the last incoming message Nr 15 with standard or extended identifier as configured Semiconductor Group 23 12 SIEMENS The On Chip CAN Interface C167 The Message Object The message object is the primary means of communication between CPU and CAN controller Each of the 15 message objects uses 15 consecutive bytes see map below and starts at an address that is a multiple of 16 Note All message objects must be initialized by the CPU even those which are not going to be used before clearing the INIT bit Message Control Object Start Address Arbitration Datao Message Config R d Data7 Figure 23 4 Message Object Address Map Each element of the Message Control Register is made of two complementary bits This special mechanism allows the selective setting or resetting of specific elements leaving others unchanged without requiring read modify write cycles None of these elements will be affected by reset The table below shows how to use and interpret these 2 bit fields Value Function on Write Meaning on Read 0 0 reserved reserved 0 1 Reset element Element is reset 10 Set element Element is set 1 1 Leave element unchanged reserved Semiconductor Group 23 13 SIEMENS The On Chip CAN Interface C167 Message Control
163. S FORTH applications Network driver software CAN PROFIBUS Semiconductor Group 1 6 SIEMENS Introduction C167 1 3 Abbreviations The following acronyms and termini are used within this document ADC Analog Digital Converter ALE 1 xs Address Latch Enable ALU coy ata eats Arithmetic and Logic Unit ASC Asynchronous synchronous Serial Controller GAN o hia Controller Area Network License Bosch CAPCOM CAPture and COMpare unit CISC eoo Complex Instruction Set Computing CMOS Complementary Metal Oxide Silicon CPU x as Central Processing Unit EBG SEX External Bus Controller ESFEHosa dus Extended Special Function Register Flash Non volatile memory that may be electrically erased GPR ES isa General Purpose Register ad Pees eee General Purpose Timer unit PAL ee eos Bo High Level Language ID eos estos iit Input Output PEG siu EE Peripheral Event Controller PLAwrx menses Programmable Logic Array PI 4 desde ide Phase Locked Loop PWM Pulse Width Modulation RAM Random Access Memory RISO e saan Reduced Instruction Set Computing ROM sies Read Only Memory SFR 22 iL Special Function Register SO s oM sisi Synchronous Serial Controller ABUS zs Internal representation of the External Bus XRAM On chip extension RAM Semiconductor Group 1 7 SIEMENS Architectural Overview C167 2 Architectural Overview The architecture of the C167 combine
164. S bared a I s ARR OS MP Sa dede dis 20 19 21 Instruction Set Summary elleeeeeeeee 21 1 22 Device Specification 225 22 299 t RETI eR EXE Se ma EE 22 1 23 The On Chip CAN Interface 0 0c cece eee 23 1 24 Keyword Index os vex er E prp nere Se deectabwey a dune EE E 24 1 Semiconductor Group l 4 SIEMENS Introduction C167 1 Introduction The rapidly growing area of embedded control applications is representing one of the most time critical operating environments for today s microcontrollers Complex control algorithms have to be processed based on a large number of digital as well as analog input signals and the appropriate output signals must be generated within a defined maximum response time Embedded control applications also are often sensitive to board space power consumption and overall system cost Embedded control applications therefore require microcontrollers which offer a high level of system integration eliminate the need for additional peripheral devices and the associated software overhead provide system security and fail safe mechanisms With the increasing complexity of embedded control applications a significant increase in CPU performance and peripheral functionality over conventional 8 bit controllers is required from microcontrollers for high end embedded control systems In order to achieve this high performance goal Siemens has decided to develop its family of 16 bit
165. SC Transmit Buffer Register write only SSCRB SSC Receive Buffer Register read only SSCTIC SSC Transmit Interrupt Control Register SSCRIC SSC Receive Interrupt Control Register SSCEIC SSC Error Interrupt Control Register Figure 11 1 SFRs and Port Pins associated with the SSC Semiconductor Group 11 1 SIEM ENS The High Speed Synchronous Serial Interface C167 Slave Clock Baud Rate Clock Receive Int Request Transmit Int Request SSC Control Block Error Int Request Status Control Control v 16 Bit Shift Register Transmit Buffer Receive Buffer Register SSCTB Register SSCRB i v lt Internal Bus gt Figure 11 2 Synchronous Serial Channel SSC Block Diagram MCB01957 The operating mode of the serial channel SSC is controlled by its bit addressable control register SSCCON This register serves for two purposes during programming SSC disabled by SSCEN 0 it provides access to a set of control bits during operation SSC enabled by SSCEN 1 it provides access to a set of status flags Register SSCCON is shown below in each of the two modes Semiconductor Group 11 2 SIEM ENS The High Speed Synchronous Serial Interface C167 SSCCON FFB2 D94 SFR Reset Value 0000 14 15 SSC EN 0 rw 13 12 SSC SSC MS AREN rw rw 11 SSC BEN rw 10 9 8 7 6 5 4 3 2 1 0 SSC SSC SSC SSC SSC SSC rw rw rw rw rw rw rw
166. SIEMENS C167 Derivatives 16 Bit CM OS Single Chip M icrocontrollers User s Manual 03 96 Version 2 0 C167 Revision History Version 2 0 03 96 Previous Version Version 1 0 08 94 Preliminary User s Manual Revision 1 0 07 92 Page Page Subjects major changes since last revision in previous in current Version Version Extension of document scope to C167CR C167SR C167S Correction of the items published in the paper Corrections C167 Edition 03 96 This edition was realized using the software system FrameMaker Published by Siemens AG Bereich Halbleiter Marketing Kommunikation BalanstraBe 73 81541 M nchen Siemens AG 1996 All Rights Reserved Attention please As far as patents or other rights of third parties are concerned liability is only assumed for components not for applications processes and circuits implemented within components or assemblies The information describes the type of component and shall not be considered as assured characteristics Terms of delivery and rights to change design reserved For questions on technology delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies and Representatives worldwide see address list Due to technical requirements components may contain dangerous substances For information on the types in question please contact your nearest Siemens Office Semiconducto
167. T 00 00C4 314 49p CAPCOM Register 18 CC18IR CC18IE CC18INT 00 00C84 324 50p CAPCOM Register 19 CC19IR CC19IE CC19INT 00 00CC 1334 51p CAPCOM Register 20 CC20IR CC20IE CC20INT 00 00D0 344 52p CAPCOM Register 21 CC21IR CC21IE CC21INT 00 00D4 35 53p CAPCOM Register 22 CC22IR CC22lE CC221NT 00 00D84 364 54p CAPCOM Register 23 CC23IR CC23IE CC23INT 00 00DC 374 55p CAPCOM Register 24 CC24IR CC24IE CC24INT 00 00E0 384 565 CAPCOM Register 25 CC25IR CC25IE CC25INT 00 00E44 394 57p CAPCOM Register 26 CC26IR CC26IE CC26INT 00 00E8 3A 585 CAPCOM Register 27 CC27IR CC27IE CC27INT 00 00EC4 3By 59p CAPCOM Register 28 CC28IR CC28IE CC28INT 00 00F0 3Cy 60p CAPCOM Register 29 CC29IR CC29IE CC29INT 00 0110 444 68p CAPCOM Register 30 CC30IR CC30IE CC30INT 00 0114 454 69p CAPCOM Register 31 CC31IR CC31IE CC31INT 000118 464 70p Semiconductor Group 5 3 SIEMENS Interrupt and Trap Functions C167 Source of Interrupt or Request Enable Interrupt Vector Trap PEC Service Request Flag Flag Vector Location Number CAPCOM Timer 0 TOIR TOIE TOINT 00 00804 204 32p CAPCOM Timer 1 T1IR TIE T1INT 00 0084 214 33p CAPCOM Timer 7 T7IR T7IE T7INT 00 00F4 3Dy 61p CAPCOM Timer 8 T8IR T8IE T8INT 00 00F 8 3E 62p GPT1 Timer 2 T2IR T2IE T2INT 000088 224 34p GPT1 Timer 3 T3IR TSIE TSINT 00 008C 234 35p GPT1 Timer 4 T4IR T4IE T4
168. T3M in register T3CON to 000p In this mode T3 is clocked with the internal system clock CPU clock divided by a programmable prescaler which is selected by bit field T3l The input frequency fr4 for timer T3 and its resolution l 13 are scaled linearly with lower clock frequencies fcpy as can be seen from the following formula fcpu 8 o T3l fre 0 rrg us M 8 o lt T3l gt 3 fopu MHz D imt TxOTL ks TxOUT TxOE MCB02028 Figure 9 3 Block Diagram of Core Timer T3 in Timer Mode The timer input frequencies resolution and periods which result from the selected prescaler option when using a 20 MHz CPU clock are listed in the table below This table also applies to the Gated Timer Mode of T3 and to the auxiliary timers T2 and T4 in timer and gated timer mode Note that some numbers may be rounded to 3 significant digits GPT1 Timer Input Frequencies Resolution and Periods fopy 20MHz Timer Input Selection T2l T3I T4I 000p 001g 010p 011g 100g 101g 110g 111g Prescaler factor 8 16 32 64 128 256 512 1024 Input Frequency 2 5 1 25 625 312 5 1156 25 78 125 39 06 19 53 MHz MHz kHz kHz kHz kHz kHz kHz Resolution 400ns 800ns 1 6us 3 2us 6 4us 12 8 us 25 6 us 51 2 us Period 26ms 52 5ms 105 ms 210 ms 420 ms 840 ms 1 68s 3 36s Semiconductor Group 9 5 SIEMENS The General Purpose Timer Units C167 Timer 3 in Gated Timer Mode Gated timer mod
169. TO the direction must be switched several times for an instruction fetch in order to output the addresses and to input the data Obviously this cannot be done through instructions In these cases the direction of the port line is switched automatically by hardware if the alternate function of such a pin is enabled To determine the appropriate level of the port output latches check how the alternate data output is combined with the respective port latch output There is one basic structure for all port lines with only an alternate input function Port lines with only an alternate output function however have different structures due to the way the direction of the pin is switched and depending on whether the pin is accessible by the user software or not in the alternate function mode All port lines that are not used for these alternate functions may be used as general purpose IO lines When using port pins for general purpose output the initial output value should be written to the port latch prior to enabling the output drivers in order to avoid undesired transitions on the output pins This applies to single pins as well as to pin groups see examples below SINGLE BIT BSET P4 7 Initial output level is high BSET DP4 7 Switch on the output driver BIT_GROUP BFLDH P4 24H 24H Initial output level is high BFLDH DP4 24H 24H Switch on the output drivers Note When using several BSET pairs to control more pins of o
170. The channel to be converted in this mode is specified in bit field CHNR of register ADDAT2 Note These 4 bits in ADDAT2 are not modified by the A D converter but only the ADRES bit field Since the channel number for an injected conversion is not buffered bitfield CHNR of ADDAT2 must never be modified during the sample phase of an injected conversion otherwise the input multiplexer will switch to the new channel It is recommended to only change the channel number with no injected conversion running Conversion of Channel Write ADDAT x 1 EX ADDAT Full EZJ E Read ADDAT x 1 Xx Injected Conversion of Channel y Channel Injection Request by S Write ADDAT2 ADDAT2 Full 77 Int ADEINT Read ADDAT2 MCA01971 Figure 16 5 Channel Injection Example A channel injection can be triggered in two ways setting of the Channel Injection Request bit ADCRQ via software a compare or a capture event of Capture Compare register CC31 of the CAPCOM2 Unit which also sets bit ADCRQ The second method triggers a channel injection at a specific time on the occurrence of a predefined count value of the CAPCOM timers or on a capture event of register CC31 This can be either the positive negative or both the positive and the negative edge of an external signal In addition this option allows recording the time of occurrence of this signal Semiconductor Group 16 7 SIEMENS The Analog Digital Converter
171. UBC SUBCB 16 16 bit signed or unsigned multiplication MUL MULU 16 16 bit signed or unsigned division DIV DIVU 32 16 bit signed or unsigned division DIVL DIVLU 1 s complement of a word or byte CPL CPLB 2 s complement negation of a word or byte NEG NEGB Logical Instructions Bitwise ANDing of two words or bytes AND ANDB Bitwise ORing of two words or bytes OR ORB Bitwise XORing of two words or bytes XOR XORB Compare and Loop Control Instructions Comparison of two words or bytes CMP CMPB Comparison of two words with post increment by either 1 or 2 CMPI1 CMPI2 Comparison of two words with post decrement by either 1 or 2 CMPD1 CMPD2 Semiconductor Group 21 1 SIEMENS Instruction Set Summary C167 Boolean Bit Manipulation Instructions Manipulation of a maskable bit field in either the high or the low byte of a word Setting a single bit to 1 Clearing a single bit to 0 Movement of a single bit Movement of a negated bit ANDing of two bits ORing of two bits XORing of two bits Comparison of two bits Shift and Rotate Instructions Shifting right of a word Shifting left of a word Rotating right of a word Rotating left of a word Arithmetic shifting right of a word sign bit shifting Prioritize Instruction Determination of the number of shift cycles required to normalize a word operand floating point supp
172. USCONXx 8 18 8 22 SIEMENS Keyword Index C167 C C1BTR 23 10 C1CSR 23 6 C1GMS 23 11 C1IR 23 8 C1LGML 23 11 C1LMLM 23 12 C1UGML 23 11 C1UMLM 23 12 CAN Interface 2 13 23 1 CAPCOM 2 15 interrupt 14 20 timer 14 4 unit 14 1 Capture mode 14 12 Capture Mode GPT 9 14 9 28 Capture Compare unit 14 1 CCMO CCM1 CCM2 CCM3 14 9 CCM4 CCM5 CCM6 CCM7 14 10 CCxIC 14 20 Center aligned PWM 15 4 Chip Select 8 8 17 9 Clock Generator 2 9 17 10 Compare modes 14 13 Concatenation of Timers 9 11 9 26 Configuration Address 8 8 17 10 Bus Mode 8 2 17 9 Chip Select 8 8 17 9 PLL 2 10 17 10 Reset 17 5 Write Control 17 9 Context Switching 5 16 Conversion analog digital 16 1 Auto Scan 16 5 timing control 16 10 Count direction 9 4 9 19 Counter 9 7 9 10 9 22 9 25 15 7 CP 4 22 CPU 2 2 4 1 CRIC 9 31 CSP 4 18 Semiconductor Group 1 2 D Data Page 4 20 19 13 boundaries 3 12 Delay Read Write 8 14 Demultiplexed Bus 8 4 Development Support 1 6 Direction count 9 4 9 19 Disable Interrupt 5 14 Segmentation 4 13 Division 4 27 19 1 Double Register compare 14 18 DPOL DPOH 6 5 DP1L DP1H 6 8 DP2 6 11 DP3 6 15 DP4 6 20 DP6 6 25 DP7 6 30 DP8 6 34 DPP 4 20 19 13 E Edge aligned PWM 15 3 Emulation Mode 17 8 Enable Interrupt 5 14 Segmentation 4 13 Error Detection ASCO 10 10 CAN 23 3 SSC 11 13 EXICON 5 23 External Bus 2 8 Bus Characteristics 8 10 to 8 16 Bus Idle State 8 24 Bus Modes 8 2
173. a 1 Note that the PWM outputs must be enabled via the respective PENx bits in PWMCON1 The table below summarizes the alternate functions of Port 7 Port 7 Pin Alternate Function P7 0 POUTO PWM model channel 0 output P7 1 POUT1 PWM model channel 1 output P7 2 POUT2 PWM model channel 2 output P7 3 POUT3 PWM model channel 3 output P7 4 CC28l0 Capture input compare output channel 28 P7 5 CC29IO Capture input compare output channel 29 P7 6 CC30I0 Capture input compare output channel 30 P7 7 CC3110 Capture input compare output channel 31 CC3110 CC3010 CC29IO CC28lO POUT3 POUT2 POUT1 POUTO General Purpose Alternate Function Input Output Figure 6 20Port 7 IO and Alternate Functions Semiconductor Group 6 31 SIEMENS Parallel Ports C167 The port structures of Port 7 differ in the way the output latches are connected to the internal bus and to the pin driver see the two figures below Pins P7 3 P7 0 POUTS POUTO XOR the alternate data output with the port latch output which allows to use the alternate data directly or inverted at the pin driver Write ODP7 y Open Drain Latch Read pos Write DP7 y i Direction Latch Read DP7 y 0250 25 Alternate Data Output Cc w n Read P7 y i lt y 0 3 MCB01985 Figure 6 21 Block Diagram of Port 7 Pins P7 3 P7 0 Semiconductor Group 6 32 SIEMENS Parallel Ports
174. a bus which would be available in a demultiplexed bus cycle Semiconductor Group 8 5 SIEMENS The External Bus Interface C167 Demultiplexed Multiplexed w ldle State Bus Cycle Bus Cycle dus PD N GE C RAN UNE COD NS UNE ED Segmen P4 Address Address ALE N N X Ji MCTO2234 Figure 8 4 Switching from Demultiplexed to Multiplexed Bus Mode Semiconductor Group 8 6 SIEMENS The External Bus Interface C167 External Data Bus Width The EBC can operate on 8 bit or 16 bit wide external memory peripherals A 16 bit data bus uses PORTO while an 8 bit data bus only uses POL the lower byte of PORTO This saves on address latches bus transceivers bus routing and memory cost on the expense of transfer time The EBC can control word accesses on an 8 bit data bus as well as byte accesses on a 16 bit data bus Word accesses on an 8 bit data bus are automatically split into two subsequent byte accesses where the low byte is accessed first then the high byte The assembly of bytes to words and the disassembly of words into bytes is handled by the EBC and is transparent to the CPU and the programmer Byte accesses on a 16 bit data bus require that the upper and lower half of the memory can be accessed individually In this case the upper byte is selected with the BHE signal while the lower byte is selected with the AO signal So the two b
175. active register bank can be accessed individually Mapping of General Purpose Registers to RAM Addresses Internal RAM Address Byte Registers Word Register CP 1Ey Was R15 CP 1C4 R14 CP 1Ay cas R13 CP 184 R12 lt CP gt 164 x R11 CP 144 ra R10 CP 124 ees R9 CP 104 EE R8 CP OE RH7 RL7 R7 CP 0Cy RH6 RL6 R6 CP OAH RH5 RL5 R5 CP 08 RH4 RL4 R4 CP 064 RH3 RL3 R3 CP 044 RH2 RL2 R2 CP 024 RH1 RL1 R1 CP 00 RHO RLO RO The C167 supports fast register bank context switching Multiple register banks can physically exist within the internal RAM at the same time Only the register bank selected by the Context Pointer register CP is active at a given time however Selecting a new active register bank is simply done by updating the CP register A particular Switch Context SCXT instruction performs register bank switching and an automatic saving of the previous context The number of implemented register banks arbitrary sizes is only limited by the size of the available internal RAM Details on using switching and overlapping register banks are described in chapter System Programming Semiconductor Group 3 6 SIEMENS Memory Organization C167 PEC Source and Destination Pointers The 16 word locations in the internal RAM from 00 FCEO to 00 FCFE just below the bit ad
176. addresses and data input output All modes use Port 4 for the upper address lines A16 if selected Important timing characteristics of the external bus interface waitstates ALE length and Read Write Delay have been made programmable to allow the user the adaption of a wide range of different types of memories and or peripherals Access to very slow memories or peripherals is supported via a particular Ready function For applications which require less than 64 KBytes of address space a non segmented memory model can be selected where all locations can be addressed by 16 bits and thus Port 4 is not needed as an output for the upper address bits A23 A19 A17 A16 as is the case when using the segmented memory model Semiconductor Group 2 8 SIEMENS Architectural Overview C167 The on chip XBUS is an internal representation of the external bus and allows to access integrated application specific peripherals modules in the same way as external components It provides a defined interface for these customized peripherals The on chip XRAM and the on chip CAN Module are examples for these X Peripherals Clock Generator The on chip clock generator provides the C167 with its basic clock signal that controls all activities of the controller hardware Its oscillator can either run with an external crystal and appropriate oscillator circuitry see also recommendations in chapter Dedicated Pins or it can be driven by an extern
177. after returning from the service routine This return location is specified through the Instruction Pointer IP and in case of a segmented memory model the Code Segment Pointer CSP Bit SGTDIS in register SYSCON controls how the return location is stored The system stack receives the PSW first followed by the IP unsegmented or followed by CSP and then IP Segmented mode This optimizes the usage of the system stack if segmentation is disabled The CPU priority field ILVL in PSW is updated with the priority of the interrupt request that is to be serviced so the CPU now executes on the new level If a multiplication or division was in progress at the time the interrupt request was acknowledged bit MULIP in register PSW is set to 1 In this case the return location that is saved on the stack is not the next instruction in the instruction flow but rather the multiply or divide instruction itself as this instruction has been interrupted and will be completed after returning from the service routine Semiconductor Group 5 15 SIEMENS Interrupt and Trap Functions C167 High Status of Addresses Interrupted Addresses d System Stack before b System Stack after b System Stack after Interrupt Entry Interrupt Entry Interrupt Entry Unsegmented Segmented MCA02226 Figure 5 3 Task Status saved on the System Stack The interrupt request flag of the source that is being serviced is cleared The IP is loaded with the
178. aitstate control logic in this case would activate READY either upon the memory s chip select or with the peripheral s READY output After the predefined number of waitstates the C167 will check its READY line to determine the end of the bus cycle For a memory access it will be low already see example a in the figure above for a peripheral access it may be delayed see example b in the figure above As memories tend to be faster than peripherals there should be no impact on system performance When using the READY function with so called normally ready peripherals it may lead to erroneous bus cycles if the READY line is sampled too early These peripherals pull their READY output low while they are idle When they are accessed they deactivate READY until the bus cycle is complete then drive it low again If however the peripheral deactivates READY after the first sample point of the C167 the controller samples an active READY and terminates the current bus cycle which of course is too early By inserting predefined waitstates the first READY sample point can be shifted to a time where the peripheral has safely controlled the READY line eg after 2 waitstates in the figure above 8 4 Controlling the External Bus Controller A set of registers controls the functions of the EBC General features like the usage of interface pins WR BHE segmentation and internal ROM mapping are controlled via register SYSCON The properti
179. al 8 Bit Description Reset Address Address Value XP3IC b F19E E CFy X Peripheral 3 Interrupt Control Register 0000 ZEROS b FFiCy 8Ey Constant Value 0 s Register read only 0000 Note 1 The system configuration is selected during reset 2 Semiconductor Group Bit WDTR indicates a watchdog timer triggered reset 20 11 SIEMENS The Register Set C167 20 3 Registers ordered by Address The following table lists all SFRs which are implemented in the C167 ordered by their physical address Bit addressable SFRs are marked with the letter b in column Name SFRs within the Extended SFR Space ESFRs are marked with the letter E in column Physical Address Registers within on chip X Peripherals CAN are marked with the letter X in column Physical Address Name Physical 8 Bit Description Reset Address Address Value C1CSR EFOO X CAN Control Status Register XX01 44 C1IR EFO2 X CAN Interrupt Register XXH C1BTR EFO4 X CAN Bit Timing Register UUUU C1GMS EFO6 X CAN Global Mask Short UFUU C1UGML EFO8 X CAN Upper Global Mask Long UUUU C1LGML EFOAW X CAN Lower Global Mask Long UUUUH C1UMLM EFOC X CAN Upper Mask of Last Message UUUU C1LMLM EFOE X CAN Lower Mask of Last Message UUUU MCR EFnO X CAN Message Control Register msg n UUUU UAR EFn24 X CAN Upper
180. al Interface C167 SOCON FFBO D8 SFR Reset Value 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 so S0 S0 rw rw rw rw zi rw rw rw rw rw rw rw rw rw Bit Function SOM ASCO Mode Control 000 8 bit data synchronous operation 001 8 bit data async operation 010 Reserved Do not use this combination 011 7 bit data parity async operation 100 9 bit data async operation 101 8 bit data wake up bit async operation 110 Reserved Do not use this combination 111 8 bit data parity async operation SOSTP Number of Stop Bits Selection async operation 0 One stop bit 1 Two stop bits SOREN Receiver Enable Bit 0 Receiver disabled y Receiver enabled Reset by hardware after reception of byte in synchronous mode SOPEN Parity Check Enable Bit async operation 0 Ignore parity 1 Check parity SOFEN Framing Check Enable Bit async operation 0 Ignore framing errors 1 Check framing errors SOOEN Overrun Check Enable Bit 0 Ignore overrun errors 1 Check overrun errors SOPE Parity Error Flag Set by hardware on a parity error SOPEN 1 Must be reset by software SOFE Framing Error Flag Set by hardware on a framing error SOFEN 1 Must be reset by software SOOE Overrun Error Flag Set by hardware on an overrun error SOOEN 1 Must be reset by software SOODD Parity Selection Bit 0 Even parity parity bit set on odd number of 1 s in data 1 Odd parity parity bit set on even number
181. al oscillator The oscillator either directly feeds the external clock signal to the controller hardware through buffers of course divides the external clock frequency by 2 or feeds an on chip phase locked loop PLL which multiplies the input frequency by a selectable factor F depending on the device mode and or type This resulting internal clock signal is also referred to as CPU clock Two separated clock signals are generated for the CPU itself and the peripheral part of the chip While the CPU clock is stopped during the idle mode the peripheral clock keeps running Both clocks are switched off when the power down mode is entered The on chip PLL circuit allows operation of the C167 on a low frequency external clock while still providing maximum performance The PLL multiplies the external clock frequency by a selectable factor of 1 F and generates a CPU clock signal with 5096 duty cycle The PLL also provides fail safe mechanisms which allow the detection of frequency deviations and the execution of emergency actions in case of an external clock failure Oscillator Circuit PLL Circuit fpi 7 F fin reset sleep F lock XP3INT Reset Factor POH 6 5 POH 7 MCB02562 Figure 2 3 PLL Block Diagram Semiconductor Group 2 9 SIEMENS Architectural Overview C167 PLL Operation The PLL is enabled when pin POH 7 is latched high during reset On power up the PLL provides a stable clock signal within ca 1 ms after Vcc ha
182. ame or any lower level are blocked now ie no request of this class will be accepted The example below establishes 3 interrupt classes which cover 2 or 3 interrupt priorities depending on the number of members in a class A level 6 interrupt disables all other sources in class 2 by changing the current CPU level to 8 which is the highest priority IL VL in class 2 Class 1 requests or PEC requests are still serviced in this case The 24 interrupt sources excluding PEC requests are so assigned to 3 classes of priority rather than to 7 different levels as the hardware support would do Semiconductor Group 5 14 SIEMENS Interrupt and Trap Functions C167 Software controlled Interrupt Classes Example ILVL GLVL Interpretation Priority 5 5 41 g 15 PEC service on up to 8 channels 14 13 12 XIX X X Interrupt Class 1 11 x x x x 8 sources on 2 levels 10 9 8 X X X X Interrupt Class 2 7 x x x x 10 sources on 3 levels 6 XIX 5 XI X X X Interrupt Class 3 4 x x 6 sources on 2 levels 3 2 1 0 No service 5 4 Saving the Status during Interrupt Service Before an interrupt request that has been arbitrated is actually serviced the status of the current task is automatically saved on the system stack The CPU status PSW is saved along with the location where the execution of the interrupted task is to be resumed
183. an interrupt only mode which can be used for software timing purposes Compare mode 0 is selected for a given compare register CCx by setting bit field CCMODx of the corresponding mode control register to 100p In this mode the interrupt request flag CCxIR is set each time a match is detected between the content of compare register CCx and the allocated timer Several of these compare events are possible within a single timer period when the compare value in register CCx is updated during the timer period The corresponding port pin CCxIO is not affected by compare events in this mode and can be used as general purpose IO pin If compare mode 0 is programmed for one of the registers CC8 CC15 or CC24 CC31 the double register compare mode becomes enabled for this register if the corresponding bank 1 register is programmed to compare mode 1 see section Double Register Compare Mode Semiconductor Group 14 13 SIEMENS The Capture Compare Units C167 Interrupt Compare Reg CCx CCxIR Request Port FS IDs Mode 1 CCMODx Interrupt CAPCOM Timer Ty TyIR Request MCB02016 x 31 0 y 0 1 7 8 Figure 14 6 Compare Mode 0 and 1 Block Diagram Note The port latch and pin remain unaffected in compare mode 0 In the example below the compare value in register CCx is modified from cv1 to cv2 after compare events 1 and 3 and from cv2 to cv1 after events 2 and 4 etc This results in periodic interrupt re
184. an the desired frequency This jitter is irrelevant for longer time periods For short periods 1 4 CPU clock cycles it remains below 4 When the PLL detects a missing input clock signal it generates an interrupt request This warning interrupt indicates that the PLL frequency is no more locked ie no more stable This occurs when the input clock is unstable and especially when the input clock fails completely eg due to a broken crystal In this case the synchronization mechanism will reduce the PLL output frequency down to the PLL s basic frequency 2 5 MHz The basic frequency is still generated and allows the CPU to execute emergency actions in case of a loss of the external clock Operation without PLL The PLL is disabled when pin POH 7 is latched low during reset In this case the C167 s clock system is directly fed from the external clock input ie fosc fcpu The maximum input clock frequency depends on the clock signal s duty cycle because the minimum values for the clock phases TCLs must be respected Semiconductor Group 2 10 SIEMENS Architectural Overview C167 2 3 The On chip Peripheral Blocks The C167 family clearly separates peripherals from the core This structure permits the maximum number of operations to be performed in parallel and allows peripherals to be added or deleted from family members without modifications to the core Each functional block processes data independently and communicates informat
185. ansition rising edge on T6IN 010 Negative transition falling edge on T6IN 011 Any transition rising or falling edge on T6IN 1XX Reserved Do not use this combination The maximum input frequency which is allowed in counter mode is fopy 8 2 5 MHz fepy 20 MHz To ensure that a transition of the count input signal which is applied to T6IN is correctly recognized its level should be held high or low for at least 4 fepy cycles before it changes Semiconductor Group 9 22 SIEMENS The General Purpose Timer Units C167 GPT2 Auxiliary Timer T5 The auxiliary timer T5 can be configured for timer gated timer or counter mode with the same options for the timer frequencies and the count signal as the core timer T6 In addition to these 3 counting modes the auxiliary timer can be concatenated with the core timer Note The auxiliary timer has no output toggle latch and no alternate output function The individual configuration for timer T5 is determined by its bitaddressable control register TECON Note that functions which are present in both timers of block GPT2 are controlled in the same bit positions and in the same manner in each of the specific control registers T5CON FF46j A3p SFR Reset Value 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Function T5I Timer 5 Input Selection Depends on the Operating Mode see respective sections T5M Timer 5 Mode Control Basic Operating Mode 00 Timer Mode 01 Cou
186. any may be used for general purpose IO If segment address lines are selected the alternate function of Port 4 may be necessary to access eg external memory directly after reset For this reason Port 4 will be switched to this alternate function automatically The number of segment address lines is selected via PORTO during reset The selected value can be read from bitfield SALSEL in register RPOH read only eg in order to check the configuration during run time Devices with a CAN interface use 2 pins of Port 4 to interface the CAN Module to an external CAN transceiver In this case the number of possible segment address lines is reduced The table below summarizes the alternate functions of Port 4 depending on the number of selected segment address lines coded via bitfield SALSEL Semiconductor Group 6 20 SIEMENS Parallel Ports C167 Port 4 Pin Std Function Altern Function Altern Function Altern Function SALSEL 01 64 KB SALSEL 11 256KB SALSEL 00 1 MB SALSEL 10 16 MB P4 0 Gen purpose IO Seg Address A16 Seg Address A16 Seg Address A16 P4 1 Gen purpose IO Seg Address A17 Seg Address A17 Seg Address A17 P4 2 Gen purpose IO Gen purpose IO Seg Address A18 Seg Address A18 P4 3 Gen purpose IO Gen purpose IO Seg Address A19 Seg Address A19 P4 4 Gen purpose IO Gen purpose IO Gen purpose IO Seg Address A20 P4 5 Gen purpose IO Gen purpose IO Gen purpose IO Seg Address A21 P4 6 Gen purpos
187. are preset with a default value Most SFRs including system registers and peripheral control and data registers are cleared to zero so all peripherals and the interrupt system are off or idle after reset A few exceptions to this rule provide a first pre initialization which is either fixed or controlled by input pins DPP1 00014 points to data page 1 DPP2 00024 points to data page 2 DPP3 00034 points to data page 3 CP FCOO STKUN FCOO STKOV FAO0O SP FCOOy WDTCON 00024 if reset was triggered by a watchdog timer overflow 0000 otherwise SORBUF XX undefined SSCRB XXXX undefined SYSCON 0XXO0 j set according to reset configuration BUSCONO OXX0 set according to reset configuration RPOH XXy reset levels of POH ONES FFFF fixed value Semiconductor Group 17 4 SIEMENS System Reset C167 The Internal RAM after Reset The contents of the internal RAM are not affected by a system reset However after a power on reset the contents of the internal RAM are undefined This implies that the GPRs R15 RO and the PEC source and destination pointers SRCP7 SRCPO DSTP7 DSTPO which are mapped into the internal RAM are also unchanged after a warm reset software reset or watchdog reset but are undefined after a power on reset Ports and External Bus Configuration during Reset During the internal reset sequence all of the C167 s port pins are configured as inputs by clearing the associat
188. are triggered reset sequence The pins that influence the configuration of the C167 are evaluated during any reset sequence ie also during software and watchdog timer triggered resets The configuration via POH is latched in register RPOH for subsequent evaluation by software Register RPOH is described in chapter The External Bus Interface Note The reserved pins marked R must remain high during reset in order to ensure proper operation of the C167 The load on those pins must be small enough for the internal pullup device to keep their level high or external pullup devices must ensure the high level Semiconductor Group 17 7 SIEMENS System Reset C167 The following describes the different selections that are offered for reset configuration The default modes refer to pins at high level ie without external pulldown devices connected Please also consider the note above on reserved pins Emulation Mode Pin POL O EMU selects the Emulation Mode when low during reset This mode allows the access to integrated XBUS peripherals via the external bus interface pins in application specific versions of the C167 In addition also the RSTOUT pin floats to tristate rather than be driven low When the emulation mode has been latched the CLKOUT output is automatically enabled This mode is used for special emulator purposes and is of no use in basic C167 devices so in this case POL 0 should be held high Default Emulation
189. asters When bit XPER SHARE in register SYSCON is set the on chip XRAM of the C167 can be accessed by an external master during hold mode via the C167 s bus interface These external accesses must use the same configuration as internally programmed ie demultiplexed bus 100 ns minimum access cycle time No waitstates are required Note The configuration in register SYSCON cannot be changed after the execution of the EINIT instruction Semiconductor Group 3 9 SIEMENS Memory Organization C167 OO FFFFy Internal RAM SFR Area 00 F000 CAN Module 00 EFOO Reserved sepes E MM 16 KByte External Access 00 C000 MCB02563 Figure 3 5 On chip XRAM Area Note The address area 00 E800 to 00 EEFF is mapped to external memory but should be reserved for reasons of upward compatibility Semiconductor Group 3 10 SIEMENS Memory Organization C167 3 4 External Memory Space The C167 is capable of using an address space of up to 16 MByte Only parts of this address space are occupied by internal memory areas All addresses which are not used for on chip memory ROM or RAM or for registers may reference external memory locations This external memory is accessed via the C167 s external bus interface Four memory bank sizes are supported Non segmented mode 64 KByte with A15 A0 on PORTO or PORT1 2 bit segmented mode 256 KByte with A17 A16 on Port 4 and A15 A0 on PORTO or PORT1 4 bit segment
190. atic retransmission of messages which have been corrupted by noise or other external error conditions on the bus line is handled by the BSP Cyclic Redundancy Check Register This register generates the Cyclic Redundancy Check CRC code to be transmitted after the data bytes and checks the CRC code of incoming messages This is done by dividing the data stream by the code generator polynomial Error Management Logic The Error Management Logic EML is responsible for the fault confinement of the CAN device Its counters the Receive Error Counter and the Transmit Error Counter are incremented and decremented by commands from the Bit Stream Processor According to the values of the error counters the CAN controller is set into the states error active error passive and busoff The CAN controller is error active if both error counters are below the error passive limit of 128 It is error passive if at least one of the error counters equals or exceeds 128 It goes busoff if the Transmit Error Counter equals or exceeds the busoff limit of 256 The device remains in this state until the busoff recovery sequence is finished Additionally there is the bit EWRN in the Status Register which is set if at least one of the error counters equals or exceeds the error warning limit of 96 EWRN is reset if both error counters are less than the error warning limit Bit Timing Logic This block BTL monitors the busline input CAN RxD and handles the
191. b F108 E 84 System Startup Configuration Register Rd only XXy CC16IC b F1604 E B0 CAPCOM Register 16 Interrupt Control Register 0000 CC171IC b F1624 E B1y CAPCOM Register 17 Interrupt Control Register 00004 CC18IC b F164 E B2 CAPCOM Register 18 Interrupt Control Register 00004 CC19IC b F166 E B3 CAPCOM Register 19 Interrupt Control Register 0000 CC20IC b F168 E B4 CAPCOM Register 20 Interrupt Control Register 0000 CC21IC b F16A E B5 CAPCOM Register 21 Interrupt Control Register 0000 CC221C b F16C E B6u CAPCOM Register 22 Interrupt Control Register 00004 CC23IC b F16E E B7j CAPCOM Register 23 Interrupt Control Register 0000 CC24IC b F170 E B8j CAPCOM Register 24 Interrupt Control Register 0000 CC25IC b F1724 E B9 CAPCOM Register 25 Interrupt Control Register 0000 CC26IC b F174 E BAy CAPCOM Register 26 Interrupt Control Register 00004 CC271lC b F176 E BB CAPCOM Register 27 Interrupt Control Register 0000 CC28IC b F178 E BCj CAPCOM Register 28 Interrupt Control Register 0000 T7IC b F17A4 E BDy CAPCOM Timer 7 Interrupt Control Register 00004 T8IC b F17C E BEy CAPCOM Timer 8 Interrupt Control Register 0000 PWMIC b F17E E BFy PWM Module Interrupt Control Register 0000 CC29IC b F1844 Ej C2 CAPCOM Register 29 Interrupt Control Register 0000 XPOIC b F186 E C3 X Peripheral 0 Interrupt Control Register 00004 CC30IC b F18Cj E C64 CAPCOM Register 30 Interrupt Control Register 00004 XP1IC b F18E E C7 X
192. be saved into external memory to create space for further stack pushes This is called stack flushing When executing a number of return or pop instructions the upper boundary since the stack empties upward to higher memory locations is reached The entries that have been previously saved in external memory must now be restored This is called stack filling Because procedure call instructions do not continue to nest infinitely and call and return instructions alternate flushing and filling normally occurs very infrequently If this is not true for a given program environment this technique should not be used because of the overhead of flushing and filling The basic mechanism is the transformation of the addresses of a virtual stack area controlled via registers SP STKOV and STKUN to a defined physical stack area within the internal RAM via hardware This virtual stack area covers all possible locations that SP can point to ie 00 F000 through 00 FFFE STKOV and STKUN accept the same 4 KByte address range The size of the physical stack area within the internal RAM that effectively is used for standard stack operations is defined via bitfield STKSZ in register SYSCON see below STKSZ Stack Size Internal RAM Addresses Words Significant Bits of Words of Physical Stack Stack Pointer SP 000g 256 O0 FBFE j 00 FA00 Default after Reset SP 8 SP 0 001g 128 00 FBFE 00 FB00 SP 7 SP 0 0
193. be used for fixed software routines like IO drivers math libraries application specific invariant routines tables etc This combines the advantage of an integrated non volatile memory with the advantage of a flexible adaptable software system Enabling and Disabling the Internal ROM Area After Reset If the internal ROM does not contain an appropriate startup code the system may be booted from external memory while the internal ROM is enabled afterwards to provide access to library routines tables etc If the internal ROM only contains the startup code and or test software the system may be booted from internal ROM which may then be disabled after the software has switched to executing from eg external memory in order to free the address space occupied by the internal ROM area which is now unnecessary Semiconductor Group 19 14 SIEMENS System Programming C167 19 11 Pits Traps and Mines Although handling the internal ROM provides powerful means to enhance the overall performance and flexibility of a system extreme care must be taken in order to avoid a system crash Instruction memory is the most crucial resource for the C167 and it must be made sure that it never runs out of it The following precautions help to take advantage of the methods mentioned above without jeopardizing system security Internal ROM access after reset When the first instructions are to be fetched from internal ROM EA 15 the device must con
194. bit ADST 1 The busy flag ADBSY will be set and the converter then selects and samples the input channel which is specified by the channel selection field ADCH in register ADCON The sampled level will then be held internally during the conversion When the conversion of this channel is complete the 10 bit result together with the number of the converted channel is transferred into the result register ADDAT and the interrupt request flag ADCIR is set If bit ADST is reset via software while a conversion is in progress the A D converter will stop after the current conversion fixed channel modes or after the current conversion sequence auto scan modes Setting bit ADST while a conversion is running will abort this conversion and start a new conversion with the parameters specified in ADCON Note Abortion and restart see above are triggered by bit ADST changing from 0 to 1 ie ADST must be 0 before being set While a conversion is in progress the mode selection field ADM and the channel selection field ADCH may be changed ADM will be evaluated after the current conversion ADCH will be evaluated after the current conversion fixed channel modes or after the current conversion sequence auto scan modes Semiconductor Group 16 4 SIEMENS The Analog Digital Converter C167 Fixed Channel Conversion Modes These modes are selected by programming the mode selection field ADM in register ADCON to 00g si
195. bit reload register each time it underflows The resulting clock is again divided according to the operating mode and controlled by the Baudrate Selection Bit SOBRS If SOBRS 1 the clock signal is additionally divided to 2 3rd of its frequency see formulas and table So the baud rate of ASCO is determined by the CPU clock the reload value the value of SOBRS and the operating mode asynchronous or synchronous Register SOBG is the dual function Baud Rate Generator Reload register Reading SOBG returns the content of the timer bits 15 13 return zero while writing to SOBG always updates the reload register bits 15 13 are insiginificant An auto reload of the timer with the content of the reload register is performed each time SOBG is written to However if SOR 0 at the time the write operation to SOBG is performed the timer will not be reloaded until the first instruction cycle after SOR 1 Semiconductor Group 10 10 Sl EM ENS The Asynchronous Synchronous Serial Interface C167 Asynchronous Mode Baud Rates For asynchronous operation the baud rate generator provides a clock with 16 times the rate of the established baud rate Every received bit is sampled at the 7th 8th and 9th cycle of this clock The baud rate for asynchronous operation of serial channel ASCO and the required reload value for a given baudrate can be determined by the following formulas fopu fopu d NE PRES as eee Basyne 16 24
196. block GPT2 contains 2 timers counters with a maximum resolution of 200 ns 20 MHz CPU clock and a 16 bit Capture Reload register CAPREL Each timer in each block may operate independently in a number of different modes such as gated timer or counter mode or may be concatenated with another timer of the same block The auxiliary timers of GPT1 may optionally be configured as reload or capture registers for the core timer In the GPT2 block the additional CAPREL register supports capture and reload operation with extended functionality and its core timer T6 may be concatenated with timers of the CAPCOM units TO T1 T7 and T8 Each block has alternate input output functions and specific interrupts associated with it 9 1 Timer Block GPT1 From a programmer s point of view the GPT1 block is composed of a set of SFRs as summarized below Those portions of port and direction registers which are used for alternate functions by the GPT1 block are shaded Ports amp Direction Control Data Registers Control Registers Interrupt Control Alternate Functions T2IN P3 7 T2EUD P5 15 TSIN P3 6 TSEUD P3 4 T4IN P3 5 T4EUD P5 14 TSOUT P3 3 ODP3 Port 3 Open Drain Control Register GPT1 Timer 2 Register DP3 Port 3 Direction Control Register GPT1 Timer 3 Register P3 Port 3 Data Register GPT1 Timer 4 Register T2CON GPT1 Timer 2 Control Register GPT1 Timer 2 Interrupt Control Register T38CON GPT1 Timer 3 Control Register GPT1 Timer 3 Interrupt Control Registe
197. by external events Each capture compare register may be programmed individually for capture or compare function and each register may be allocated to either timer of the associated unit Each capture compare register has one port pin associated with it which serves as an input pin for the capture function or as an output pin for the compare function except for CC27 CC24 on P1H 7 P1H 4 which only provide the capture function The capture function causes the current timer contents to be latched into the respective capture compare register triggered by an event transition on its associated port pin The compare function may cause an output signal transition on that port pin whose associated capture compare register matches the current timer contents Specific interrupt requests are generated upon each capture compare event or upon timer overflow The figure below shows the basic structure of the two CAPCOM units Semiconductor Group 14 2 SIEMENS The Capture Compare Units C167 Reload Reg TxREL CPU Clock 2 n 3 10 Interrupt Request TxIN p CAPCOM Timer Tx gt GPT2 Timer T6 Over Underflow Mode ZZ Sixteen 2S 16 pour ZII 16 Bit 1227 16 Capture Inputs Capture Capture Capture Compare Compare Outputs or Compare Interrupt Requests Compare Registers CPU Clock Interrupt Ty Request Input CAPCOM Timer Ty Control GPT2 Timer T6 Ove
198. cautions that must be taken in order to prevent the system from crashing Semiconductor Group 3 3 SIEMENS Memory Organization C167 3 2 Internal RAM and SFR Area The RAM SFR area is located within data page 3 and provides access to 2 KByte of on chip RAM organized as 1K 16 and to two 512 Byte blocks of Special Function Registers SFRs The internal RAM serves for several purposes System Stack programmable size General Purpose Register Banks GPRs Source and destination pointers for the Peripheral Event Controller PEC Variable and other data storage or Code storage O0 FFFF 77 OO FFF 00 F000y XRAM CAN Data Page 3 00 FEO0 00 E000 H External 00 C0Q0 Memory s Internal is Page2 Rh RAM SFR Area 00 8000 4 Data Page SUBSP Internal ROM 00 4000 Reserved Area Data Page 0 002004 00 0000 00 F000j System Segment 0 RAM SFR Area 64 KByte 4 KByte MCD02233 Figure 3 3 Internal RAM Area and SFR Areas Note The upper 256 bytes of SFR area ESFR area and internal RAM are bit addressable see shaded blocks in the figure above Semiconductor Group 3 4 Memory Organization C167 SIEMENS Code accesses are always made on even byte addresses The highest possible code storage location in the internal RAM is either 00 FDFE for single word instructions or 00 FDFC for double word instructions The respective location must contain a branch instr
199. ceived synchronous to a shift clock which is generated by the C167 In asynchronous mode 8 or 9 bit data transfer parity generation and the number of stop bits can be selected Parity framing and overrun error detection is provided to increase the reliability of data transfers Transmission and reception of data is double buffered For multiprocessor communication a mechanism to distinguish address from data bytes is included Testing is supported by a loop back option A 13 bit baud rate generator provides the ASCO with a separate serial clock signal Ports amp Direction Control Data Registers Control Registers Interrupt Control Alternate Functions RXDO P3 11 TXDO P3 10 ODP3 Port 3 Open Drain Control Register DP3 Port 3 Direction Control Register Port 3 Data Register SOBG ASCO Baud Rate Generator Reload Register ASCO Control Register SOTBUF ASCO Transmit Buffer Register ASCO Receive Buffer Register read only SOTIC ASCO Transmit Interrupt Control Register ASCO Receive Interrupt Control Register SOTBIC ASCO Transmit Buffer Interrupt Control Reg ASCO Error Interrupt Control Register Figure 10 1 SFRs and Port Pins associated with ASCO The operating mode of the serial channel ASCO is controlled by its bitaddressable control register SOCON This register contains control bits for mode and error check selection and status flags for error identification Semiconductor Group 10 1 Sl EM ENS The Asynchronous Synchronous Seri
200. ch are distinguished by individual chip select signals CS Signal Generation During external accesses the EBC can generate a programmable number of CS lines on Port 6 which allow to directly select external peripherals or memory banks without requiring an external decoder The number of CS lines is selected during reset and coded in bit field CSSEL in register RPOH see table below CSSEL Chip Select Lines Note 1 1 Five C84 CS0 Default without pull downs 10 None Port 6 pins free for IO 0 1 Two CS1 CS0 00 Three CS2 CS0 The CSx outputs are associated with the BUSCONXx registers and are driven active low for any access within the address area defined for the respective BUSCON register For any access outside this defined address area the respective CSx signal will go inactive high At the beginning of each external bus cycle the corresponding valid CS signal is determined and activated All other CS lines are deactivated driven high at the same time Note The CSx signals will not be updated for an access to any internal address area ie when no external bus cycle is started even if this area is covered by the respective ADDRSELx register An access to an on chip X Peripheral deactivates all external CS signals Upon accesses to address windows without a selected CS line all selected CS lines are deactivated Semiconductor Group 8 8 SIEMENS The External Bus Interface C167 The chip sele
201. ck the shift clock can be generated master or received slave This allows the adaptation of the SSC to a wide range of applications where serial data transfer is required The Data Width Selection supports the transfer of frames of any length from 2 bit characters up to 16 bit characters Starting with the LSB SSCHB 0 allows communication eg with ASCO devices in synchronous mode C166 family or 8051 like serial interfaces Starting with the MSB SSCHB 1 allows operation compatible with the SPI interface Regardless which data width is selected and whether the MSB or the LSB is transmitted first the transfer data is always right aligned in registers SSCTB and SSCRB with the LSB of the transfer data in bit 0 of these registers The data bits are rearranged for transfer by the internal shift register logic The unselected bits of SSCTB are ignored the unselected bits of SSCRB will be not valid and should be ignored by the receiver service routine The Clock Control allows the adaptation of transmit and receive behaviour of the SSC to a variety of serial interfaces A specific clock edge rising or falling is used to shift out transmit data while the other clock edge is used to latch in receive data Bit SSCPH selects the leading edge or the trailing edge for each function Bit SSCPO selects the level of the clock line in the idle state So for an idle high clock the leading edge is a falling one a 1 to 0 transition The f
202. conductor Group 23 7 SIEMENS The On Chip CAN Interface C167 CAN Interrupt Handling The on chip CAN Module has one interrupt output which is connected through a synchronization stage to a standard interrupt node in the C167 in the same manner as all other interrupts of the standard on chip peripherals The control register for this interrupt is XPOIC located at address F186 C3 in the ESFR range The associated interrupt vector is called XPOINT at location 1004 trap number 40 With this configuration the user has all control options available for this interrupt such as enabling disabling level and group priority and interrupt or PEC service see note below As for all other interrupts the interrupt request flag XPOIR in register XPOIC is cleared automatically by hardware when this interrupt is serviced either by standard interrupt or PEC service Note As a rule CAN interrupt requests can be serviced by a PEC channel However because PEC channels only can execute single predefined data transfers there are no conditional PEC transfers PEC service can only be used if the respective request is known to be generated by one specific source and that no other interrupt request will be generated in between In practice this seems to be a rare case Since an interrupt request of the CAN Module can be generated due to different conditions the appropriate CAN interrupt status register must be read in the service routine to determin
203. crystal two low end capacitors and series resistor to limit the current through the crystal The additional LC combination is only required for 3rd overtone crystals to suppress oscillation in the fundamental mode A test resistor Ro may be temporarily inserted to measure the oscillation allowance of the oscillator circuitry An external clock signal may be fed to the input XTAL1 leaving XTAL2 open Note It is strongly recommended to measure the oscillation allowance or margin in the final target system layout to determine the optimum parameters for the oscillator operation E MCS02566 Figure 7 1 External Oscillator Circuitry The Reset Input RSTIN allows to put the C167 into the well defined reset condition either at power up or external events like a hardware failure or manual reset The input voltage threshold of the HSTIN pin is raised compared to the standard pins in order to minimize the noise sensitivity of the reset input Semiconductor Group 7 2 SIEMENS Dedicated Pins C167 The Reset Output RSTOUT provides a special reset signal for external circuitry RSTOUT is activated at the beginning of the reset sequence triggered via RSTIN a watchdog timer overflow or by the SRST instruction RSTOUT remains active low until the EINIT instruction is executed This allows to initialize the controller before the external circuitry is activated The Power Supply pins for the Analog Digital Converter VAREF and VAGND provid
204. ct signals allow to be operated in four different modes which are selected via bits CSWENx and CSRENx in the respective BUSCONXx register CSWENx CSRENx Chip Select Mode Address Chip Select Default after Reset mode for CSO Read Chip Select Write Chip Select Read Write Chip Select aja Olo 0 1 0 1 Address Chip Select signals remain active until an access to another address window An address chip select becomes active with the falling edge of ALE and becomes inactive with the falling edge of ALE of an external bus cycle that accesses a different address area No spikes will be generated on the chip select lines Read or Write Chip Select signals remain active only as long as the associated control signal RD or WR is active This also includes the programmable read write delay Read chip select is only activated for read cycles write chip select is only activated for write cycles read write chip select is activated for both read and write cycles write cycles are assumed if any of the signals WRH or WRL gets active These modes save external glue logic when accessing external devices like latches or drivers that only provide a single enable input Note CS0 provides an address chip select directly after reset except for single chip mode when the first instruction is fetched Internal pullup devices hold all CS lines high during reset After the end of a reset sequence the pullup devices are switche
205. ctable results will occur Semiconductor Group 19 7 SIEMENS System Programming C167 User Stacks User stacks provide the ability to create task specific data stacks and to off load data from the system stack The user may push both bytes and words onto a user stack but is responsible for using the appropriate instructions when popping data from the specific user stack No hardware detection of overflow or underflow of a user stack is provided The following addressing modes allow implementation of user stacks Rw Rb or Rw Rw Pre decrement Indirect Addressing Used to push one byte or word onto a user stack This mode is only available for MOV instructions and can specify any GPR as the user stack pointer Rb Rw or Rw Rw Post increment Index Register Indirect Addressing Used to pop one byte or word from a user stack This mode is available to most instructions but only GPRs RO R3 can be specified as the user stack pointer Rb Rw or Rw Rw Post increment Indirect Addressing Used to pop one byte or word from a user stack This mode is only available for MOV instructions and can specify any GPR as the user stack pointer 19 2 Register Banking Register banking provides the user with an extremely fast method to switch user context A single machine cycle instruction saves the old bank and enters a new register bank Each register bank may assign up to 16 registers Each register bank should be allocated duri
206. d reserved SFR bits cannot be modified and will always supply a read value of 0 The System Configuration Register SYSCON This bit addressable register provides general system configuration and control functions The reset value for register SYSCON depends on the state of the PORTO pins during reset see hardware effectable bits Semiconductor Group 4 11 SIEMENS The Central Processing Unit CPU C167 SYSCON FF12 894 SFR Reset Value OXX0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SGT BYT CLK WR VISI XPER rw rw rw rw rw rw rw rw rw rw XPER SHARE XBUS Peripheral Share Mode Control Bit Function 0 External accesses to XBUS peripherals are disabled 1 XBUS peripherals are accessible via the external bus during hold mode VISIBLE Visible Mode Control 0 Accesses to XBUS peripherals are done internally 1 XBUS peripheral accesses are made visible on the external pins XPEN XBUS Peripheral Enable Bit 0 Accesses to the on chip X Peripherals and their functions are disabled 1 The on chip X Peripherals are enabled and can be accessed Note This bit is valid only for derivates that contain X Peripherals WRCFG Write Configuration Control Set according to pin POH O during reset 0 Pins WR and BHE retain their normal function 1 Pin WR acts as WRL pin BHE acts as WRH CLKEN System Clock Output Enable CLKOUT 0 CLKOUT disabled p
207. d a PEC service on a priority level higher than the current CPU level is requested and executed Note An interrupt request which is individually enabled and assigned to priority level O will terminate Idle mode The associated interrupt vector will not be accessed however The watchdog timer may be used to monitor the Idle mode an internal reset will be generated if no interrupt or NMI request occurs before the watchdog timer overflows To prevent the watchdog timer from overflowing during Idle mode it must be programmed to a reasonable time interval before Idle mode is entered Semiconductor Group 18 2 SIEMENS Power Reduction Modes C167 18 2 Power Down Mode To further reduce the power consumption the microcontroller can be switched to Power Down mode Clocking of all internal blocks is stopped the contents of the internal RAM however are preserved through the voltage supplied via the Vcc pins The watchdog timer is stopped in Power Down mode This mode can only be terminated by an external hardware reset ie by asserting a low level on the RSTIN pin This reset will initialize all SFRs and ports to their default state but will not change the contents of the internal RAM There are two levels of protection against unintentionally entering Power Down mode First the PWRDN Power Down instruction which is used to enter this mode has been implemented as a protected 32 bit instruction Second this instruction is effective only if t
208. d by 2 state times The worst case interrupt response time during internal ROM program execution adds to 12 state times 600 ns 20 MHz CPU clock Any reference to external locations increases the interrupt response time due to pipeline related access priorities The following conditions have to be considered Instruction fetch from an external location Operand read from an external location Result write back to an external location Depending on where the instructions source and destination operands are located there are a number of combinations Note however that only access conflicts contribute to the delay A few examples illustrate these delays The worst case interrupt response time including external accesses will occur when instructions N N 1 and N22 are executed out of external memory instructions N 1 and N require external operand read accesses instructions N 3 through N write back external operands and the interrupt vector also points to an external location In this case the interrupt response time is the time to perform 9 word bus accesses because instruction 11 cannot be fetched via the external bus until all write fetch and read requests of preceding instructions in the pipeline are terminated When the above example has the interrupt vector pointing into the internal ROM the interrupt response time is 7 word bus accesses plus 2 states because fetching of instruction 11 from internal ROM can start earlie
209. d complex encoding schemes by placing operands in consistent fields for each instruc tion Also avoid complex addressing modes which are not frequently used This decreases the instruction decode time while also simplifying the development of compilers and assem blers 3 Provide most frequently used instructions with one word instruction formats All other instruc tions are placed into two word formats This allows all instructions to be placed on word boundaries which alleviates the need for complex alignment hardware It also has the bene fit of increasing the range for relative branching instructions The high performance offered by the hardware implementation of the CPU can efficiently be utilized by a programmer via the highly functional C167 instruction set which includes the following instruction classes Arithmetic Instructions e Logical Instructions Boolean Bit Manipulation Instructions Compare and Loop Control Instructions Shift and Rotate Instructions Prioritize Instruction Data Movement Instructions System Stack Instructions Jump and Call Instructions Return Instructions System Control Instructions Miscellaneous Instructions Possible operand types are bits bytes and words Specific instruction support the conversion extension of bytes to words A variety of direct indirect or immediate addressing modes are provided to specify the required operands Semiconductor Group 2 5 SIEMENS Archit
210. d data for ADDAT from a standard conversion or for ADDAT2 from an injected conversion Semiconductor Group 16 8 SIEMENS The Analog Digital Converter C167 Conversion of Channel Wait until ADDAT2 is Write ADDAT read ADDAT Full Read ADDAT Injected DR Conversion Channel Injection Write ADDAT2 of Channel xy Request by CC31 i M ADDAT2 Full Int Request ADEINT Read ADDAT2 Temp Latch Full Conversion of Channel Write ADDAT ADDAT Full Read ADDAT Temp Latch Full Channel Injection Request by CC31 wait until ADDAT2 is ADDAT2 Full read 7 Int Request ADEINT Read ADDAT2 y MCA01972 Figure 16 6 Channel Injection Example with Wait for Read Semiconductor Group 16 9 SIEMENS The Analog Digital Converter C167 16 2 Conversion Timing Control When a conversion is started first the capacitances of the converter are loaded via the respective analog input pin to the current analog input voltage The time to load the capacitances is referred to as sample time Next the sampled voltage is converted to a digital value in 10 successive steps which correspond to the 10 bit resolution of the ADC The next 4 steps are used for an internal self calibration of the converter module During these 14 steps the internal capacitances are repeatedly charged and discharged via the V aper pin The current that has to be drawn from the sources for sampling and changing charges depends on the
211. d of entering and exiting interrupt routines for each data transfer Semiconductor Group 2 16 Architectural Overview C167 SIEMENS 2 4 Protected Bits The C167 provides a special mechanism to protect bits which can be modified by the on chip hardware from being changed unintentionally by software accesses to related bits see also chapter The Central Processing Unit The following bits are protected Register Bit Name Notes T2IC T3IC T4IC T2IR T3IR T4IR GPT1 timer interrupt request flags T5IC T6IC T5IR T6IR GPT2 timer interrupt request flags CRIC CRIR GPT2 CAPREL interrupt request flag T3CON T6CON TSOTL T6OTL GPTx timer output toggle latches TOIC T1IC TOIR T1IR CAPCOM timer interrupt request flags T7IC T8IC T7IR T8IR CAPCOWN2 timer interrupt request flags SOTIC SOTBIC SOTIR SOTBIR ASCO transmit buffer interrupt request flags SORIC SOEIC SORIR SOEIR ASCO receive error interrupt request flags SOCON SOREN ASCO receiver enable flag SSCTIC SSCRIC SSCTIR SSCRIR SSC transmit receive interrupt request flags SSCEIC SSCEIR SSC error interrupt request flag SSCCON SSCBSY SSC busy flag SSCCON SSCBE SSCPE SSC error flags SSCCON SSCRE SSCTE SSC error flags ADCIC ADEIC ADCIR ADEIR ADC end of conv overrun intr request flag ADCON ADST ADCRQ ADC start flag injection request flag CC311C CC161C CC31IR CC16IR CAPCOWM2 interrupt req
212. d off and the pin drivers control the pin levels on the selected CS lines Not selected CS lines will enter the high impedance state and are available for general purpose IO The pullup devices are also active during bus hold on the selected CS lines while HLDA is active and the respective pin is switched to push pull mode Open drain outputs will float during bus hold In this case external pullup devices are required or the new bus master is responsible for driving appropriate levels on the CS lines Segment Address versus Chip Select The external bus interface of the C167 supports many configurations for the external memory By increasing the number of segment address lines the C167 can address a linear address space of 256 KByte 1 MByte or 16 MByte This allows to implement a large sequential memory area and also allows to access a great number of external devices using an external decoder By increasing the number of CS lines the C167 can access memory banks or peripherals without external glue logic These two features may be combined to optimize the overall system performance Enabling 4 segment address lines and 5 chip select lines eg allows to access five memory banks of 1 MByte each So the available address space is 5 MByte without glue logic Note Bit SGTDIS of register SYSCON defines if the CSP register is saved during interrupt entry segmentation active or not segmentation disabled Semiconductor Group 8 9 SIEMENS The E
213. d operating mode will be read as zeros Data reception is double buffered so that reception of asecond character may already begin before the previously received character has been read out of the receive buffer register In all modes receive buffer overrun error detection can be selected through bit SOOEN When enabled the overrun error status flag SOOE and the error interrupt request flag SOEIR will be set when the receive buffer register has not been read by the time reception of a second character is complete The previously received character in the receive buffer is overwritten The Loop Back option selected by bit SOLB allows the data currently being transmitted to be received simultaneously in the receive buffer This may be used to test serial communication routines at an early stage without having to provide an external network In loop back mode the alternate input output functions of the Port 3 pins are not necessary Note Serial data transmission or reception is only possible when the Baud Rate Generator Run Bit SOR is set to 1 Otherwise the serial interface is idle Do not program the mode control field SOM in register SOCON to one of the reserved combinations to avoid unpredictable behaviour of the serial interface Semiconductor Group 10 3 Sl EM ENS The Asynchronous Synchronous Serial Interface C167 10 1 Asynchronous Operation Asynchronous mode supports full duplex communication where both transmitter and recei
214. d to the system stack A so called circular stack mechanism allows to use a bigger virtual stack than this dedicated RAM area These techniques as well as the encoding of bitfield STKSZ are described in more detail in chapter System Programming Semiconductor Group 4 13 SIEMENS The Central Processing Unit CPU C167 The Processor Status Word PSW This bit addressable register reflects the current state of the microcontroller Two groups of bits represent the current ALU status and the current CPU interrupt status A separate bit USRO within register PSW is provided as a general purpose user flag PSW FF10 884 SFR Reset Value 0000 15 14 13 12 11 0 10 9 8 7 6 5 4 3 2 1 HLD MUL rw rw rw rw rw rw rw rw rw rw Bit Function N Negative Result Set when the result of an ALU operation is negative C Carry Flag Set when the result of an ALU operation produces a carry bit V Overflow Result Set when the result of an ALU operation produces an overflow Z Zero Flag Set when the result of an ALU operation is zero E End of Table Flag Set when the source operand of an instruction is 80004 or 80 MULIP Multiplication Division In Progress 0 There is no multiplication division in progress 1 A multiplication division has been interrupted USRO User General Purpose Flag May be used by the application software HLDEN Interrupt and EBC Control Fields ILVL IEN Def
215. d transition at the external input pin CAPIN is detected the contents of the auxiliary timer T5 are latched into register CAPREL and interrupt request flag CRIR is set With the same event timer T5 can be cleared to 0000 This option is controlled by bit T5CLR in register TSCON If T5CLR 0 the contents of timer T5 are not affected by a capture If TS5CLR 1 timer T5 is cleared after the current timer value has been latched into register CAPREL Note Bit T5SC only controls whether a capture is performed or not If T5SC 0 the input pin CAPIN can still be used to clear timer T5 or as an external interrupt input This interrupt is controlled by the CAPREL interrupt control register CRIC Up Down Auxiliary Timer T5 T5IR EE Interrupt CRIR Request CAPREL Register MCB02044 GPT2 Register CAPREL in Capture Mode Figure 9 18 Semiconductor Group 9 28 SIEMENS The General Purpose Timer Units C167 GPT2 Capture Reload Register CAPREL in Reload Mode This 16 bit register can be used as a reload register for the core timer T6 This mode is selected by setting bit TeSR 1 in register TECON The event causing a reload in this mode is an overflow or underflow of the core timer T6 When timer T6 overflows from FFFF to 0000 when counting up or when it underflows from 00004 to FFFFy when counting down the value stored in register CAPREL is loaded into timer T6 This will not set the interrupt request flag CRI
216. define four independent address windows while all external accesses outside these windows are controlled via register BUSCONO Semiconductor Group 8 1 SIEMENS The External Bus Interface C167 Single Chip Mode Single chip mode is entered when pin EA is high during reset In this case register BUSCONO is initialized with 0000 which also resets bit BUSACTO so no external bus is enabled In single chip mode the C167 operates only with and out of internal resources No external bus is configured and no external peripherals and or memory can be accessed Also no port lines are occupied for the bus interface When running in single chip mode however external access may be enabled by configuring an external bus under software control Single chip mode allows the C167 to start execution out of the internal program memory Mask ROM or Flash memory Note Any attempt to access a location in the external memory space in single chip mode results in the hardware trap ILLBUS 8 1 External Bus Modes When the external bus interface is enabled bit BUSACTx 1 and configured bitfield BTYP the C167 uses a subset of its port lines together with some control lines to build the external bus BTYP External Data Bus Width External Address Bus Mode Encoding 00 8 bit Data Demultiplexed Addresses 0 1 8 bit Data Multiplexed Addresses 10 16 bit Data Demultiplexed Addresses 11 16 bit Data Multiplexed Addresses The b
217. deliberately within a program eg to leave bootstrap loader mode or upon a hardware trap that reveals a system failure Note A software reset disregards the configuration of POL 5 POL 0 Watchdog Timer Reset When the watchdog timer is not disabled during the initialization or serviced regularly during program execution is will overflow and trigger the reset sequence Other than hardware and software reset the watchdog reset completes a running external bus cycle if this bus cycle either does not use READY at all or if READY is sampled active low after the programmed waitstates When READY is sampled inactive high after the programmed waitstates the running external bus cycle is aborted Then the internal reset sequence is started Note A watchdog reset disregards the configuration of POL 5 POL 0 The watchdog reset cannot occur while the C167 is in bootstrap loader mode Semiconductor Group 17 2 SIEMENS System Reset C167 The C167 s Pins after Reset After the reset sequence the different groups of pins of the C167 are activated in different ways depending on their function Bus and control signals are activated immediately after the reset sequence according to the configuration latched from PORTO so either external accesses can takes place or the external control signals are inactive The general purpose IO pins remain in input mode high impedance until reprogrammed via software see figure below The RSTOUT pin remains
218. dge Select Capture Register Tx A TxIN Interrupt P3 7 P3 5 b tue H Request Core Timer T3 T3IR Ba T30UT T3OTL Li T3OE MCB02038 Figure 9 10 GPT1 Auxiliary Timer in Capture Mode Upon a trigger selected transition at the corresponding input pin TxIN the contents of the core timer are loaded into the auxiliary timer register and the associated interrupt request flag TxIR will be set Note The direction control bits DP3 7 for T2IN and DP3 5 for TAIN must be set to 0 and the level of the capture trigger signal should be held high or low for at least 8 fopy cycles before it changes to ensure correct edge detection Semiconductor Group 9 14 SIEMENS The General Purpose Timer Units C167 Interrupt Control for GPT1 Timers When a timer overflows from FFFF to 0000 when counting up or when it underflows from 0000 to FFFF when counting down its interrupt request flag T2IR T3IR or T4IR in register TxIC will be set This will cause an interrupt to the respective timer interrupt vector T2INT T3INT or T4INT or trigger a PEC service if the respective interrupt enable bit T2IE T3IE or T4IE in register TxIC is set There is an interrupt control register for each of the three timers T2IC FF60 BOp SFR Reset Value 00 15 d4 13 12 11 10 9 8 5 4 3 2 7 6 1 0 J rw rw rw T3IC FF62 B1p SFR Reset Value 00 7 6 1 0 we rw rw TAIC FF64
219. disabled via bit BYTDIS in register SYSCON Default 16 bit data bus with multiplexed addresses Note If an internal start is selected via pin EA these two pins are disregarded and bit field BTYP of register BUSCONO is cleared Write Configuration Pin POH 0 WRC selects the initial operation of the control pins WR and BHE during reset When high this pin selects the standard function i e WR control and BHE When low it selects the alternate configuration i e WRH and WRL Thus even the first access after a reset can go to a memory controlled via WRH and WRL This bit is latched in register RPOH and its inverted value is copied into bit WRCFG in register SYSCON Default Standard function WR control and BHE Semiconductor Group 17 9 SIEMENS System Reset C167 Chip Select Lines Pins POH 2 and POH 1 CSSEL define the number of active chip select signals during reset This allows the selection which pins of Port 6 drive external CS signals and which are used for general purpose IO The two bits are latched in register RPOH Default All 5 chip select lines active CS4 CS0 CSSEL Chip Select Lines Note 11 Five C84 CS0 Default without pull downs 10 None Port 6 pins free for IO 0 1 Two CS1 CS0 00 Three CS2 CS0 Note The selected number of CS signals cannot be changed via software after reset Segment Address Lines Pins POH 4 and POH 3 SALSEL define the number of active segmen
220. dressable section are provided as source and destination address pointers for data transfers on the eight PEC channels Each channel uses a pair of pointers stored in two subsequent word locations with the source pointer SRCPx on the lower and the destination pointer DSTPx on the higher word address x 7 0 OQ FDOOj 00 FCFE y WY 00 FCFE y 00 FCFC 00 FCEO H A H 00 FDDEY PEC Source and Destination Internal Pointers RAM QU CE2H 00 F 6004 MCD02266 Figure 3 4 Location of the PEC Pointers Whenever a PEC data transfer is performed the pair of source and destination pointers which is selected by the specified PEC channel number is accessed independent of the current DPP register contents and also the locations referred to by these pointers are accessed independent of the current DPP register contents If a PEC channel is not used the corresponding pointer locations area available and can be used for word or byte data storage For more details about the use of the source and destination pointers for PEC data transfers see section Interrupt and Trap Functions Semiconductor Group 3 7 SIEMENS Memory Organization C167 Special Function Registers The functions of the CPU the bus interface the IO ports and the on chip peripherals of the C167 are controlled via a number of so called Special Function Registers SFRs These SFRs are arranged within two areas of 512 Byte size each The first register bl
221. e The memory tri state time waitstate requires one CPU clock 50 ns at fepy 20 MHz and is controlled via the MTTCx bits of the BUSCON registers A waitstate will be inserted if bit MTTCx is 0 default after reset Note External bus cycles in multiplexed bus modes implicitly add one tri state time waitstate in addition to the programmable MTTC waitstate Semiconductor Group 8 13 SIEMENS The External Bus Interface C167 Read Write Signal Delay The C167 allows the user to adjust the timing of the read and write commands to account for timing requirements of external peripherals The read write delay controls the time between the falling edge of ALE and the falling edge of the command Without read write delay the falling edges of ALE and command s are coincident except for propagation delays With the delay enabled the command s become active half a CPU clock 25 ns at fcpy 20 MHz after the falling edge of ALE The read write delay does not extend the memory cycle time and does not slow down the controller in general In multiplexed bus modes however the data drivers of an external device may conflict with the C167 s address when the early RD signal is used Therefore multiplexed bus cycles should always be programmed with read write delay a Bus Cycle ALE N H 1 w Read Write a Delay MCT02066 1 The data drivers from the previous bus cycle should be disabled whe
222. e C167 SIEMENS After starting the timer ie PTRx 1 the output pulse may be modified via software Writing to timer PTx changes the positive and or negative edge of the output signal depending on whether the pulse has already started ie the output is high or not ie the output is still low This multiple retriggering is always possible while the timer is running ie after the pulse has started and before the timer is stopped Loading counter PTx directly with the value in the respective PPx shadow register will abort the current PWM pulse upon the next clock pulse counter is cleared and stopped by hardware By setting the period PPx the timer start value PTx and the pulse width value PWx appropriately the pulse width tw and the optional pulse delay td may be varied in a wide range 15 2 PWM Module Registers The PWM module is controlled via two sets of registers The waveforms are selected by the channel specific registers PTx timer PPx period and PWx pulse width Three common registers control the operating modes and the general functions PWMCONO and PWMCON 1 of the PWM module as well as the interrupt behaviour PWMIC Up Down Counters PTx Each counter PTx of a PWM channel is clocked either directly by the CPU clock or by the CPU clock divided by 64 Bit PTIx in register PWMCONO selects the respective clock source A PWM counter counts up or down controlled by hardware while its respective ru
223. e After exiting from the trap procedure the internal stack will wrap around to the top of the internal stack and continue to grow until the new value of the stack overflow pointer is reached When the underflow pointer is reached while the stack is meptied the bottom of stack is reloaded from the external memory and the internal pointers are adjusted accordingly Linear Stack The C167 also offers a linear stack option STKSZ 1115 where the system stack may use the complete internal RAM area This provides a large system stack without requiring procedures to handle data transfers for a circular stack However this method also leaves less RAM space for variables or code The RAM area that may effectively be consumed by the system stack is defined via the STKUN and STKOV pointers The underflow and overflow traps in this case serve for fatal error detection only For the linear stack option all modifiable bits of register SP are used to access the physical stack Although the stack pointer may cover addresses from 00 F000 up to 00 FFFE the physical system stack must be located within the internal RAM and therefore may only use the address range 00 F600 to 00 FDFE It is the user s responsibility to restrict the system stack to the internal RAM range Note Avoid stack accesses within address range 00 F000 to 00 F5FE ESFR space and reserved area and within address range 00 FEO0 and 00 FFFE SFR space Otherwise unpredi
224. e Word Register R14 UUUU 28 R15 CP FFy CPU General Purpose Word Register R15 UUUU 30 Semiconductor Group 20 2 SIEMENS The Register Set C167 The first 8 GPRs R7 RO may also be accessed bytewise Other than with SFRs writing to a GPR byte does not affect the other byte of the respective GPR The respective halfs of the byte accessible registers receive special names Name Physical 8 Bit Description Reset Address Address Value RLO CP 0 FO CPU General Purpose Byte Register RLO UUy RHO CP 1 Fiy CPU General Purpose Byte Register RHO UU RL1 CP 2 F2y CPU General Purpose Byte Register RL1 UU RH1 CP 3 F3y CPU General Purpose Byte Register RH1 UU RL2 CP 4 F4y CPU General Purpose Byte Register RL2 UUy RH2 CP 5 F5y CPU General Purpose Byte Register RH2 UUy RL3 CP 6 F6j CPU General Purpose Byte Register RL3 UU RH3 CP 7 F7y CPU General Purpose Byte Register RH3 UU RL4 CP 8 F8y CPU General Purpose Byte Register RL4 UUy RH4 CP 9 F9y CPU General Purpose Byte Register RH4 UU RL5 CP FAQ CPU General Purpose Byte Register RL5 UUu 10 RH5 CP FBy CPU General Purpose Byte Register RH5 UU 11 RL6 CP FCy CPU General Purpose Byte Register RL6 UUu 12 RH6 CP FDy CPU General Purpose Byte Register RH6 UU 13 RL7 CP FE CPU General Purpose Byte Register RL7 UUu 14 R
225. e C167 treats the external bus interface as follows Address and data bus es float to tri state ALE is pulled low by an internal pulldown device Command lines are pulled high by internal pullup devices RD WR WRL BHE WRH CSx outputs are pulled high push pull mode or float to tri state open drain mode Should the C167 require access to its external bus during hold mode it activates its bus request output BREQ to notify the arbitration circuitry BREQ is activated only during hold mode It will be inactive during normal operation Other Signals mepe MCTO2238 Figure 8 13 External Bus Arbitration Releasing the Bus Note The C167 will complete the currently running bus cycle before granting bus access as indicated by the broken lines This may delay hold acknowledge compared to this figure The figure above shows the first possibility for BREQ to get active During bus hold pin P3 12 is switched back to its standard function and is then controlled by DP3 12 and P3 12 Keep DP3 12 0 in this case to ensure floating in hold mode Semiconductor Group 8 27 SIEMENS The External Bus Interface C167 Exiting the Hold State The external bus master returns the access rights to the C167 by driving the HOLD input high After synchronizing this signal the C167 will drive the HLDA output high actively drive the control signals and resume executing external bus cycles if required Depending on t
226. e IO Gen purpose IO Gen purpose IO Seg Address A22 P4 7 Gen purpose IO Gen purpose IO Gen purpose IO Seg Address A23 Alternate Function General Purpose Input Output Figure 6 13 Port 4 IO and Alternate Functions Semiconductor Group 6 21 SIEMENS Parallel Ports C167 Write DP4 y 4 1 MUX Direction 0 Latch Read DP4 Alternate Function Enable Write P4 y Alternate 4 Q 3S5 0 5 v gt P4 Port Output gt Output d Latch Buffer Read P4 y E Cc UJ MCB02075 Figure 6 14 Block Diagram of a Port 4 Pin Semiconductor Group 6 22 SIEMENS Parallel Ports C167 6 6 Port5 This 16 bit input port can only read data There is no output latch and no direction register Data written to P5 will be lost P5 FFA2 Dip SFR Reset Value XXXXy 15 14 11 1 0 13 12 0 9 8 7 6 5 4 3 2 1 r r r r r r r r r r r r r r r r Bit Function P5 y Port data register P5 bit y Read only Alternate Functions of Port 5 Each line of Port 5 is also connected to the input multiplexer of the Analog Digital Converter All port lines P5 15 P5 0 can accept analog signals AN15 ANO that can be converted by the ADC No special programming is required for pins that shall be used as analog inputs The upper 6 pins of Port 5 also serve as external timer control lines for GPT1 and GPT2 The table bel
227. e SP value is less than the value in the stack overflow register The contents of the stack pointer are compared to the contents of the underflow register whenever the SP is INCREMENTED either by a RET POP or ADD instruction An underflow trap will be entered when the SP value is greater than the value in the stack underflow register Note When a value is MOVED into the stack pointer NO check against the overflow underflow registers is performed In many cases the user will place a software reset instruction SRST into the stack underflow and overflow trap service routines This is an easy approach which does not require special programming However this approach assumes that the defined internal stack is sufficient for the current software and that exceeding its upper or lower boundary represents a fatal error It is also possible to use the stack underflow and stack overflow traps to cache portions of a larger external stack Only the portion of the system stack currently being used is placed into the internal memory thus allowing a greater portion of the internal RAM to be used for program data or register banking This approach assumes no error but requires a set of control routines see below Semiconductor Group 19 4 System Programming C167 SIEMENS Circular virtual Stack This basic technique allows pushing until the overflow boundary of the internal stack is reached At this point a portion of the stacked data must
228. e a separate power supply for the on chip ADC This reduces the noise that is coupled to the analog input signals from the digital logic sections and so improves the stability of the conversion results when VAREF and VAGND are properly discoupled from VCC and VSS The Flash Programming Voltage input VPP provides the programming voltage that is required to erase and program the on chip Flash memory areas During normal operation besides programming or erasing this pins should be connected to VCC For devices without a Flash memory Mask ROM or romless devices the VPP pin is reserved In this case it may be left open or it may be connected to VCC in order to be compatible with Flash devices The Power Supply pins VCC and VSS provide the power supply for the digital logic of the C167 The respective VCC VSS pairs should be decoupled as close to the pins as possible For best results it is recommended to implement two level decoupling eg the widely used 100 nF in parallel with 30 40 pF capacitors which deliver the peak currents Note All VCC pins and all VSS pins must be connected to the power supply and ground respectively Semiconductor Group 7 3 SIEMENS The External Bus Interface C167 8 The External Bus Interface Although the C167 provides a powerful set of on chip peripherals and on chip RAM and ROM except for ROMless versions areas these internal units only cover a small fraction of its address space of up to 16 MByte Th
229. e error interrupt request flag SSCEIR If a transfer starts while the transmit buffer is not updated the slave will shift out the old contents of the shift register which normally is the data received during the last transfer This may lead to the corruption of the data on the transmit receive line in half duplex mode open drain configuration if this slave is not selected for transmission This mode requires that slaves not selected for transmission only shift out ones ie their transmit buffers must be loaded with FFFF prior to any transfer Note A slave with push pull output drivers which is not selected for transmission will normally have its output drivers switched However in order to avoid possible conflicts or misinterpretations it is recommended to always load the slave s transmit buffer prior to any transfer Register SSCCON Register SSCEIR Error SSCEIE Error Receive y SSCEIE Interrupt SSCEIR SSCEINT MCA01968 Figure 11 6 SSC Error Interrupt Control Semiconductor Group 11 13 SIEM ENS The High Speed Synchronous Serial Interface C167 11 5 SSC Interrupt Control Three bit addressable interrupt control registers are provided for serial channel SSC Register SSCTIC controls the transmit interrupt SSCRIC controls the receive interrupt and SSCEIC controls the error interrupt of serial channel SSC Each interrupt source also has its own dedicated interrupt vector SCTINT is the transmit
230. e external bus interface allows to access external peripherals and additional volatile and non volatile memory The external bus interface provides a number of configurations so it can be taylored to fit perfectly into a given application system Ports amp Direction Control Address Registers Mode Registers Control Registers Alternate Functions PORTO EA PORT1 RSTIN ALE READY RD WR WRL BHE WRH POL POH PORTO Data Registers ADDRSELx Address Range Select Register 1 4 P1L P1H PORT1 Data Registers BUSCONx Bus Mode Control Register 0 4 DP3 Port 3 Direction Control Register SYSCON System Control Register P3 Port 3 Data Register RPOH Port POH Reset Configuration Register P4 Port 4 Data Register ODP6 Port 6 Open Drain Control Register DP6 Port 6 Direction Control Register P6 Port 6 Data Register Figure 8 1 SFRs and Port Pins Associated with the External Bus Interface Accesses to external memory or peripherals are executed by the integrated External Bus Controller EBC The function of the EBC is controlled via the SYSCON register and the BUSCONx and ADDRSELx registers The BUSCONXx registers specify the external bus cycles in terms of address mux demux data 16 bit 8 bit chip selects and length waitstates READY control ALE RW delay These parameters are used for accesses within a specific address area which is defined via the corresponding register ADDRSELx The four pairs BUSCON1 ADDRSEL1 BUSCON4 ADDRSEL4 allow to
231. e for the core timer T3 is selected by setting bit field T3M in register T3CON to 010g or 0115 Bit T3M 0 T3CON 3 selects the active level of the gate input In gated timer mode the same options for the input frequency as for the timer mode are available However the input clock to the timer in this mode is gated by the external input pin T3IN Timer T3 External Input which is an alternate function of P3 6 To enable this operation pin T3IN P3 6 must be configured as input ie direction control bit DP3 6 must contain 0 Int t om TxOTL TxOUT TxOE MCB02029 Figure 9 4 Block Diagram of Core Timer T3 in Gated Timer Mode If T3M 0 0 the timer is enabled when T3IN shows a low level A high level at this pin stops the timer If T3M 0 1 pin T3IN must have a high level in order to enable the timer In addition the timer can be turned on or off by software using bit T3R The timer will only run if T3R 1 and the gate is active It will stop if either T3R 0 or the gate is inactive Note A transition of the gate signal at pin T3IN does not cause an interrupt request Semiconductor Group 9 6 SIEMENS The General Purpose Timer Units C167 Timer 3 in Counter Mode Counter mode for the core timer T3 is selected by setting bit field T3M in register T3CON to 001p In counter mode timer T3 is clocked by a transition at the external input pin T3IN which is an alternate function of P3 6 The event cau
232. e receive interrupt request and an error interrupt request if appropriate Start bits that follow this frame will not be recognized Note In wake up mode received frames are only transferred to the receive buffer register if the 9th bit the wake up bit is 1 If this bit is 0 no receive interrupt request will be activated and no data will be transferred Semiconductor Group 10 7 Sl EM ENS The Asynchronous Synchronous Serial Interface C167 10 2 Synchronous Operation Synchronous mode supports half duplex communication basically for simple IO expansion via shift registers Data is transmitted and received via pin RXDO P3 11 while pin TXDO P3 10 outputs the shift clock These signals are alternate functions of Port 3 pins Synchronous mode is selected with SOM 000p 8 data bits are transmitted or received synchronous to a shift clock generated by the internal baud rate generator The shift clock is only active as long as data bits are transmitted or received Reload Register CPU Clock j 22 Baud Rate Timer SOR SOM 000B SOOE Clock SORIR Doce Int i Transmit Int TXD0 P3 10 Serial Port Control SOTIR Request Shift Clock Error Int Request Receive 1 Dp H Receive Shift RXDO P3 11 MUX Register 1 Transmit Receive Buffer Reg Transmit Buffer Reg SORBUF SOTBUF Internal Bus gt MCB02220 Figure 10 5 Synchronous Mode of Serial Channel ASCO Semiconductor Grou
233. e switched off Semiconductor Group 18 4 Power Reduction Modes C167 SIEMENS The table below summarizes the state of all C167 output pins during Idle and Power Down mode C167 Idle Mode Power Down Mode Output Pin s No External bus No External bus external bus enabled external bus enabled ALE Low Low Low Low RD WR High High High High CLKOUT Active Active High High RSTOUT 1 1 1 1 POL Port Latch Data Floating Port Latch Data Floating POH Port Latch Data A15 A8 2 Float Port Latch Data A15 A8 2 Float PORTI Port Latch Data Last Address Port Latch Data Last Address 9 Port Latch Data Port Latch Data Port 4 Port Latch Data Port Latch Data Port Latch Data Port Latch Data Last segment Last segment BHE Port Latch Data Last value Port Latch Data Last value HLDA Port Latch Data Last value Port Latch Data Last value BREQ Port Latch Data High Port Latch Data High CSx Port Latch Data Last value Port Latch Data Last value Other Port Port Latch Data Port Latch Data Port Latch Data Port Latch Data Output Pins Alternate Function Alternate Function Alternate Function Alternate Function Note 1 High if EINIT was executed before entering Idle or Power Down mode Low otherwise 2 3 4 For demultiplexed buses For multiplexed buses with 8 bit data bus The CS signal that corresponds to the last address r
234. e that the C167 is a pipelined machine requires attention by the programmer In these cases the delays caused by pipeline conflicts can be used for other instructions in order to optimize performance Context Pointer Updating An instruction which calculates a physical GPR operand address via the CP register is mostly not capable of using a new CP value which is to be updated by an immediately preceding instruction Thus to make sure that the new CP value is used at least one instruction must be inserted between a CP changing and a subsequent GPR using instruction as shown in the following example ln SCXT CP 0FCOOh select a new context lat en must not be an instruction using a GPR Ineo MOV RO datax write to GPR 0 in the new context e Data Page Pointer Updating An instruction which calculates a physical operand address via a particular DPPn n 0 to 3 register is mostly not capable of using a new DPPn register value which is to be updated by an immediately preceding instruction Thus to make sure that the new DPPn register value is used at least one instruction must be inserted between a DPPn changing instruction and a subsequent instruction which implicitly uses DPPn via a long or indirect addressing mode as shown in the following example ln MOV DPPO 4 select data page 4 via DPPO Ina A must not be an instruction using DPPO Ini MOV DPP0 0000H R1 move contents of R1 to address location 01 0000 i
235. e the cause of the interrupt request The Interrupt Identifier INTID a number in the Interrupt Register indicates the cause of an interrupt When no interrupt is pending the identifier will have the value 00 If the value in INTID is not 00 then there is an interrupt pending If bit IE in the Control Register is set also the interrupt line to the CPU is activated The interrupt line remains active until either INTID gets 00 ie the interrupt requester has been serviced or until IE is reset ie interrupts are disabled The interrupt with the lowest number has the highest priority If a higher priority interrupt lower number occurs before the current interrupt is processed INTID is updated and the new interrupt overrides the last one Interrupt Register EF02 XReg Reset Value XX4 155 14 13 12 1i 10 9 8 7 6 5 4 3 2 nl 0 r Bit Function INTID Interrupt Identifier This number indicates the cause of the interrupt When no interrupt is pending the value will be 00 Semiconductor Group 23 8 SIEMENS The On Chip CAN Interface C167 The table below lists the valid values for INTID and their corresponding interrupt sources INTID Cause of the Interrupt 00 Interrupt Idle There is no interrupt request pending 01 Status Change Interrupt The CAN controller has updated not necessarily changed the status in the Control Register This can refer to a change of the error status of
236. eceiver enable bit SOREN is reset and serial data reception stops Pin TXDO P3 10 must be configured for alternate data output ie P3 102 1 and DP3 10 1 in order to provide the shift clock Pin RXDO P3 11 must be configured as alternate data input DP3 11 0 Synchronous reception is stopped by clearing bit SOREN A currently received byte is completed including the generation of the receive interrupt request and an error interrupt request if appropriate Writing to the transmit buffer register while a reception is in progress has no effect on reception and will not start a transmission If a previously received byte has not been read out of the receive buffer register at the time the reception of the next byte is complete both the error interrupt request flag SOEIR and the overrun error status flag SOOE will be set provided the overrun check has been enabled by bit SOOEN Semiconductor Group 10 9 Sl EM ENS The Asynchronous Synchronous Serial Interface C167 10 3 Hardware Error Detection Capabilities To improve the safety of serial data exchange the serial channel ASCO provides an error interrupt request flag which indicates the presence of an error and three selectable error status flags in register SOCON which indicate which error has been detected during reception Upon completion of a reception the error interrupt request flag SOEIR will be set simultaneously with the receive interrupt request flag SORIR if one
237. ecording relative to external events Four 16 bit timers TO T1 T7 T8 with reload registers provide two independent time bases for the capture compare register array The input clock for the timers is programmable to several prescaled values of the internal CPU clock or may be derived from an overflow underflow of timer T6 in module GPT2 This provides a wide range of variation for the timer period and resolution and allows precise adjustments to the application specific requirements In addition external count inputs for CAPCOM timers TO and T7 allow event scheduling for the capture compare registers relative to external events Both of the two capture compare register arrays contain 16 dual purpose capture compare registers each of which may be individually allocated to either CAPCOM timer TO or T1 T7 or T8 respectively and programmed for capture or compare function Each register has one port pin associated with it which serves as an input pin for triggering the capture function or as an output pin except for CC24 CC27 to indicate the occurence of a compare event When a capture compare register has been selected for capture mode the current contents of the allocated timer will be latched captured into the capture compare register in response to an external event at the port pin which is associated with this register In addition a specific interrupt request for this capture compare register is generated Either a positive a negat
238. ection fault trap routine The protected instructions include DISWDT EINIT IDLE PWRDN SRST and SRVWDT The IP value pushed onto the system stack for the protection fault trap is the address of the instruction that caused the trap Illegal Word Operand Access Trap Whenever a word operand read or write access is attempted to an odd byte address the ILLOPA flag in register TFR is set and the CPU enters the illegal word operand access trap routine The IP value pushed onto the system stack is the address of the instruction following the one which caused the trap Illegal Instruction Access Trap Whenever a branch is made to an odd byte address the ILLINA flag in register TFR is set and the CPU enters the illegal instruction access trap routine The IP value pushed onto the system stack is the illegal odd target address of the branch instruction Illegal External Bus Access Trap Whenever the CPU requests an external instruction fetch data read or data write and no external bus configuration has been specified the ILLBUS flag in register TFR is set and the CPU enters the illegal bus access trap routine The IP value pushed onto the system stack is the address of the instruction following the one which caused the trap Semiconductor Group 5 27 SIEMENS Parallel Ports C167 6 Parallel Ports In order to accept or generate single external control signals or parallel data the C167 provides up to 111 parallel IO lines organized into o
239. ective interrupt request flag CCxIR which can cause an interrupt or a PEC service request when enabled Edge Select Capture Reg CCx A Interrupt CCxI0 OX gt CCxIR Request CCMODx Input Interrupt Clock 7 CAPCOM Timer Ty TylR Request MCB02015 Figure 14 5 Capture Mode Block Diagram In order to use the respective port pin as external capture input pin CCxIO for capture register CCx this port pin must be configured as input ie the corresponding direction control bit must be set to 0 To ensure that a signal transition is properly recognized an external capture input signal should be held for at least 8 CPU clock cycles before it changes its level During these 8 CPU clock cycles the capture input signals are scanned sequentially When a timer is modified or incremented during this process the new timer contents will already be captured for the remaining capture registers within the current scanning sequence If pin CCxlO is configured as output the capture function may be triggered by modifying the corresponding port output latch via software eg for testing purposes Semiconductor Group 14 12 SIEMENS The Capture Compare Units C167 14 5 Compare Modes The compare modes allow triggering of events interrupts and or output signal transitions with minimum software overhead In all compare modes the 16 bit value stored in compare register CCx in the following also referred to as compare val
240. ectural Overview C167 Programmable Multiple Priority Interrupt System The following enhancements have been included to allow processing of a large number of interrupt Sources 1 Peripheral Event Controller PEC This processor is used to off load many interrupt requests from the CPU It avoids the overhead of entering and exiting interrupt or trap routines by per forming single cycle interrupt driven byte or word data transfers between any two locations in segment 0 with an optional increment of either the PEC source or the destination pointer Just one cycle is stolen from the current CPU activity to perform a PEC service 2 Multiple Priority Interrupt Controller This controller allows all interrupts to be placed at any specified priority Interrupts may also be grouped which provides the user with the ability to prevent similar priority tasks from interrupting each other For each of the possible interrupt sources there is a separate control register which contains an interrupt request flag an inter rupt enable flag and an interrupt priority bitfield Once having been accepted by the CPU an interrupt service can only be interrupted by a higher prioritized service request For standard interrupt processing each of the possible interrupt sources has a dedicated vector location 3 Multiple Register Banks This feature allows the user to specify up to sixteen general pur pose registers located anywhere in the internal RAM A sing
241. ed and a trap is executed the CSP for the trap service routine is set to code segment 0 No Interrupt Request flags are affected by the TRAP instruction The interrupt service routine called by a TRAP instruction must be terminated with a RETI return from interrupt instruction to ensure correct operation Note The CPU level in register PSW is not modified by the TRAP instruction so the service routine is executed on the same priority level from which it was invoked Therefore the service routine entered by the TRAP instruction can be interrupted by other traps or higher priority interrupts other than when triggered by a hardware trap Hardware Traps Hardware traps are issued by faults or specific system states that occur during runtime of a program not identified at assembly time A hardware trap may also be triggered intentionally eg to emulate additional instructions by generating an Illegal Opcode trap The C167 distinguishes eight different hardware trap functions When a hardware trap condition has been detected the CPU branches to the trap vector location for the respective trap condition Depending on the trap condition the instruction which caused the trap is either completed or cancelled ie it has no effect on the system state before the trap handling routine is entered Hardware traps are non maskable and always have priority over every other CPU activity If several hardware trap conditions are detected within the same instr
242. ed direction registers and their pin drivers are switched to the high impedance state This ensures that the C167 and external devices will not try to drive the same pin to different levels Pin ALE is held low through an internal pulldown and pins RD and WR are held high through internal pullups Also the pins selected for CS output will be pulled high The registers SYSCON and BUSCONO are initialized according to the configuration selected via PORTO When an external start is selected pin EA 0 the Bus Type field BTYP in register BUSCONO is initialized according to POL 7 and POL 6 bit BUSACTO in register BUSCONO is set to 1 bit ALECTLO in register BUSCONO is set to 1 bit ROMEN in register SYSCON will be cleared to 0 bit BYTDIS in register SYSCON is set according to the data bus width When an internal start is selected pin EA 17 register BUSCONO is cleared to 0000 bit ROMEN in register SYSCON will be set to 1 bit BYTDIS in register SYSCON is cleared ie BHE is disabled The other bits of register BUSCONO and the other BUSCON registers are cleared This default initialization selects the slowest possible external accesses using the configured bus type The Ready function is disabled at the end of the internal system reset When the internal reset has completed the configuration of PORTO PORT1 Port 4 Port 6 and of the BHE signal High Byte Enable alternate function of P3 12 de
243. ed mode 1 MByte with A19 A16 on Port 4 and A15 A0 on PORTO or PORT1 8 bit segmented mode 16 MByte with A23 A16 on Port 4 and A15 A0 on PORTO or PORT1 Each bank can be directly addressed via the address bus while the programmable chip select signals can be used to select various memory banks The C167 also supports four different bus types Multiplexed 16 bit Bus with address and data on PORTO Default after Reset Multiplexed 8 bit Bus with address and data on PORTO POL Demultiplexed 16 bit Bus with address on PORT1 and data on PORTO e Demultiplexed 8 bit Bus with address on PORT1 and data on POL Memory model and bus mode are selected during reset by pin EA and PORTO pins For further details about the external bus configuration and control please refer to chapter The External Bus Interface External word and byte data can only be accessed via indirect or long 16 bit addressing modes using one of the four DPP registers There is no short addressing mode for external operands Any word data access is made to an even byte address For PEC data transfers the external memory in segment 0 can be accessed independent of the contents of the DPP registers via the PEC source and destination pointers The external memory is not provided for single bit storage and therefore it is not bit addressable Semiconductor Group 3 11 SIEMENS Memory Organization C167 3 5 Crossing Memory Boundaries The address space of the C167
244. egister The stack grows downward from higher towards lower RAM address locations Only word accesses are supported to the system stack A stack overflow STKOV and a stack underflow STKUN register are provided to control the lower and upper limits of the selected stack area These two stack boundary registers can be used not only for protection against data destruction but also allow to implement a circular stack with hardware supported system stack flushing and filling except for the 2KByte stack option The technique of implementing this circular stack is described in chapter System Programming Semiconductor Group 3 5 Memory Organization C167 SIEMENS General Purpose Registers The General Purpose Registers GPRs use a block of 16 consecutive words within the internal RAM The Context Pointer CP register determines the base address of the currently active register bank This register bank may consist of up to 16 word GPRs RO R1 R15 and or of up to 16 byte GPRs RLO RHO RL7 RH7 The sixteen byte GPRs are mapped onto the first eight word GPRs see table below In contrast to the system stack a register bank grows from lower towards higher address locations and occupies a maximum space of 32 bytes The GPRs are accessed via short 2 4 or 8 bit addressing modes using the Context Pointer CP register as base address independent of the current DPP register contents Additionally each bit in the currently
245. egister 00004 CC9IC b FF8A C5y CAPCOM Register 9 Interrupt Control Register 00004 CC10IC b FF8C C6y CAPCOM Register 10 Interrupt Control Register 0000 CC11IC b FF8E C74 CAPCOM Register 11 Interrupt Control Register 00004 CC12IC b FF90u C8y CAPCOM Register 12 Interrupt Control Register 00004 CC13IC b FF924 C94 CAPCOM Register 13 Interrupt Control Register 00004 CC14IC b FF94 CAy CAPCOM Register 14 Interrupt Control Register 0000 CC15IC b FF964 CBy CAPCOM Register 15 Interrupt Control Register 0000 ADCIC b FF98 CCy A D Converter End of Conversion Interrupt 00004 Control Register ADEIC b FF9A CDy A D Converter Overrun Error Interrupt Control 00004 Register TOIC b FF9C CEy CAPCOM Timer 0 Interrupt Control Register 00004 T1IC b FF9E CFy CAPCOM Timer 1 Interrupt Control Register 0000 ADCON _ b FFA0 DOW A D Converter Control Register 0000 P5 b FFA2 D1 Port 5 Register read only XXXXy TFR b FFACy D6 Trap Flag Register 0000 WDTCON b FFAE D74 Watchdog Timer Control Register 000X42 SOCON b FFBO D8y Serial Channel 0 Control Register 0000 SSCCON b FFB2 D94 SSC Control Register 0000 P2 b FFCO EO Port 2 Register 00004 DP2 b FFC2 E1y Port 2 Direction Control Register 0000 P3 b FFC4 E2u Port 3 Register 00004 DP3 b FFC6 E3y Port 3 Direction Control Register 00004 P4 b FFC8 E44 Port 4 Register 8 bits 00H DP4 b FFCA E5y Port 4 Direction Control Register 004 P6 b FFCCh E6y Port 6 Register 8 bits 004 D
246. eline 4 3 Effects 4 6 PLL 2 9 17 10 Port 2 12 input threshold 6 2 Power Down Mode 18 3 Protected Bits 2 17 4 9 instruction 21 4 PSW 4 14 5 9 Pulse Width Modulation 2 15 PWM 2 15 PWM Module 15 1 PWMCONO 15 9 PWMCON 15 10 PWMIC 15 11 SIEMENS Keyword Index C167 R RAM extension 3 9 internal 3 4 Read Write Delay 8 14 READY 8 15 Register 20 1 20 4 20 12 Reset 9 8 17 1 Configuration 17 5 Output 17 4 Values 17 4 ROM 19 14 RPOH 8 23 Semiconductor Group S SOBG 10 10 SOCON 10 2 SOEIC SORIC SOTIC SOTBIC 10 12 SORBUF 10 7 10 9 SOTBUF 10 6 10 9 Segment Address 8 8 17 10 boundaries 3 12 Segmentation 4 18 Enable Disable 4 13 Serial Interface 2 13 10 1 Asynchronous 10 4 CAN 2 13 23 1 Synchronous 10 8 11 1 SFR 3 8 20 4 20 12 Single Chip Mode 8 2 Single shot mode PWM 15 6 Slave mode 8 25 Software Reset 17 1 Traps 5 24 Source Interrupt 5 3 SP 4 24 SSC 11 1 Baudrate generation 11 11 Error Detection 11 13 Full Duplex 11 7 Half Duplex 11 9 SSCBR 11 11 SSCCON 11 2 SSCEIC SSCRIC SSCTIC 11 15 SSCRB SSCTB 11 8 Stack 3 5 4 24 19 4 Startup Configuration 17 5 STKOV 4 25 STKUN 4 26 Subroutine 19 9 Synchronous Serial Interface 11 1 SYSCON 4 11 4 12 8 17 1 5 SIEMENS Keyword Index C167 TO1CON T78CON 14 5 UAR 23 16 TOIC T11C T7IC T8IC 14 8 Unseparable instructions 19 12 T2CON 9 8 T2IC T3IC T4IC 9 15 W T3CON 9 3 TACON 9 8 Waitstate T5CON 9 23 Memory Cycle 8 12 T5IC T6IC
247. emains active low all other enabled CS signals remain inactive high By accessing an on chip X Periperal prior to entering a power save mode all external CS signals can be deactivated Semiconductor Group 18 5 SIEMENS System Programming C167 19 System Programming To aid in software development a number of features has been incorporated into the instruction set of the C167 including constructs for modularity loops and context switching In many cases commonly used instruction sequences have been simplified while providing greater flexibility The following programming features help to fully utilize this instruction set Instructions Provided as Subsets of Instructions In many cases instructions found in other microcontrollers are provided as subsets of more powerful instructions in the C167 This allows the same functionality to be provided while decreasing the hardware required and decreasing decode complexity In order to aid assembly programming these instructions familiar from other microcontrollers can be built in macros thus providing the same names Directly Substitutable Instructions are instructions known from other microcontrollers that can be replaced by the following instructions of the C167 Substituted Instruction C167 Instruction Function CLR Rn AND Rn 0 Clear register CPLB Bit BMOVN Bit Bit Complement bit DEC Rn SUB Rn 14 Decrement register INC Rn ADD Rn 14 Increment regi
248. emory areas after reset in Bootstrap Loader mode differs from the standard case Pin EA is not evaluated when BSL mode is selected and accesses to the internal ROM area are partly redirected while the C167 is in BSL mode see table below All code fetches are made from the special Boot ROM while data accesses read from the internal user ROM Data accesses will return undefined values on ROMless devices Note The code in the Boot ROM is not an invariant feature of the C167 User software should not try to execute code from the internal ROM area while the BSL mode is still active as these fetches will be redirected to the Boot ROM The Boot ROM will also move to segment 1 when the internal ROM area is mapped to segment 1 access to access to external external bus bus disabled enabled Depends on reset config EA PO O O access to O access to E int ROM ks int ROM 9 g enabled 9 enabled BSL mode active Yes POL 4 0 Yes POL 4 0 No POL 4 1 EA pin high low acc to application Code fetch from Boot ROM access Boot ROM access User ROM access internal ROM area Data fetch from User ROM access User ROM access User ROM access internal ROM area Semiconductor Group 13 3 SIEMENS The Bootstrap Loader C167 Loading the Startup Code After sending the identification byte the BSL enters a loop to receive 32 bytes via ASCO These bytes are stored sequentially int
249. en activated driven low during the last bus access 18 1 Idle Mode The power consumption of the C167 microcontroller can be decreased by entering Idle mode In this mode all peripherals including the watchdog timer continue to operate normally only the CPU operation is halted Idle mode is entered after the IDLE instruction has been executed and the instruction before the IDLE instruction has been completed To prevent unintentional entry into Idle mode the IDLE instruction has been implemented as a protected 32 bit instruction Idle mode is terminated by interrupt requests from any enabled interrupt source whose individual Interrupt Enable flag was set before the Idle mode was entered regardless of bit IEN For a request selected for CPU interrupt service the associated interrupt service routine is entered if the priority level of the requesting source is higher than the current CPU priority and the interrupt system is globally enabled After the RETI Return from Interrupt instruction of the interrupt service routine is executed the CPU continues executing the program with the instruction following the IDLE instruction Otherwise if the interrupt request cannot be serviced because of a too low priority or a globally disabled interrupt system the CPU immediately resumes normal program execution with the instruction following the IDLE instruction For a request which was programmed for PEC service a PEC data transfer is performed if the
250. ent address pins A23 A19 A17 A16 of Port 4 for all external data accesses A DPP register can be updated via any instruction which is capable of modifying an SFR Note Due to the internal instruction pipeline a new DPP value is not yet usable for the operand address calculation of the instruction immediately following the instruction updating the DPP register ata Pages 6 Bit Data Address 14 0 1023 4 1022 1021 DPP Registers v DPP3 11 14 Bi Intra Page Address DPP2 10 Concatenated with DPP4 0 4 content of DPPx DPPO 0 0 MCA02764 After reset or with segmentation disabled the DPP registers select data pages 3 0 All of the internal memory is accessible in these cases Figure 4 6 Addressing via the Data Page Pointers Semiconductor Group 4 21 SIEMENS The Central Processing Unit CPU C167 The Context Pointer CP This non bit addressable register is used to select the current register context This means that the CP register value determines the address of the first General Purpose Register GPR within the current register bank of up to 16 wordwide and or bytewide GPRs CP FE10 081 SFR Reset Value FC00 15 14 11 10 9 8 7 6 5 4 3 2 1 0 13 12 r r r r rw r Bit Function cp Modifiable portion of register CP Specifies the word base address of the current register bank
251. ept some of the branches the multiplication the division and a special move instruction In case of internal ROM program execution there is no execution time dependency on the instruction length except for some special branch situations The numbers in the table are in units of ns refer to a CPU clock of 20 MHz and assume no waitstates Minimum Execution Times Instruction Fetch Word Operand Access Memory Area Word Doubleword Read from Write to Instruction Instruction Internal ROM 100 100 100 Internal RAM 300 400 0 50 0 16 bit Demux Bus 100 200 100 100 16 bit Mux Bus 150 300 150 150 8 bit Demux Bus 200 400 200 200 8 bit Mux Bus 300 600 300 300 Execution from the internal RAM provides flexibility in terms of loadable and modifyable code on the account of execution time Execution from external memory strongly depends on the selected bus mode and the programming of the bus cycles waitstates The operand and instruction accesses listed below can extend the execution time of an instruction Internal ROM operand reads same for byte and word operand reads Internal RAM operand reads via indirect addressing modes Internal SFR operand reads immediately after writing External operand reads External operand writes Jumps to non aligned double word instructions in the internal ROM space Testing Branch Conditions immediately after PSW writes Semiconductor Group 4 10 SIEMENS The
252. er T3 Count Direction Control Pin TXEUD Bit TxUDE Bit TXUD Count Direction X 0 0 Count Up X 0 1 Count Down 0 1 0 Count Up 1 1 0 Count Down 0 1 1 Count Down 1 1 1 Count Up Note The direction control works the same for core timer T3 and for auxiliary timers T2 and T4 Therefore the pins and bits are named Tx Timer 3 Output Toggle Latch An overflow or underflow of timer T3 will clock the toggle bit T3OTL in control register T3CON TSOTL can also be set or reset by software Bit T3OE Alternate Output Function Enable in register T3CON enables the state of T3OTL to be an alternate function of the external output pin T3OUT P3 3 For that purpose a 1 must be written into port data latch P3 3 and pin T3OUT P3 3 must be configured as output by setting direction control bit DP3 3 to 1 If TSOE 1 pin T3OUT then outputs the state of T3OTL If T3OEz O pin TSOUT can be used as general purpose IO pin In addition T3OTL can be used in conjunction with the timer over underflows as an input for the counter function or as a trigger source for the reload function of the auxiliary timers T2 and T4 For this purpose the state of TSOTL does not have to be available at pin T3OUT because an internal connection is provided for this option Semiconductor Group 9 4 SIEMENS The General Purpose Timer Units C167 Timer 3 in Timer Mode Timer mode for the core timer T3 is selected by setting bit field
253. eral Purpose Input Output Figure 6 23 Port 8 IO and Alternate Functions Semiconductor Group 6 35 SIEMENS Parallel Ports C167 The pins of Port 8 combine internal bus data and alternate data output before the port latch input as do the Port 2 pins Write ODP8 y Open Drain Ta Read ODP8 y Write DP8 y Y Direction Latch UN 1 Y vux b hn 84 Alternate lo Output Data Output Buffer I n 1 e r n d UJ c n Write Port P8 y 21 Compare Trigger Read P8 y lt y 0 7 Alternate Latch Data Input 4 z 16 23 Alternate Pin Data Input MCBO1988 Figure 6 24 Block Diagram of Port 8 Pins Semiconductor Group 6 36 Dedicated Pins C167 SIEMENS 7 Dedicated Pins Most of the input output or control signals of the functional the C167 are realized as alternate functions of pins of the parallel ports There is however a number of signals that use separate pins including the oscillator special control signals and of course the power supply The table below summarizes the 33 dedicated pins of the C167 Pin s Function ALE Address Latch Enable RD External Read Strobe WR WRL External Write Write Low Strobe HEADY Ready Input EA External Access Enable NMI Non Maskable Interrupt Input XTAL1 XTAL2 Oscillator Input Output RSTIN Reset Input RSTOUT Reset Output VAREF VAGND
254. ered by one of two different signals The trigger signal is selected the same way as the clock source for counter mode see table above ie a transition of the auxiliary timer s input or the output toggle latch T3OTL may trigger the reload Note When programmed for reload mode the respective auxiliary timer T2 or T4 stops independent of its run flag T2R or T4R Ss Ed an i Reload Register Tx TxIN Interrupt P3 7 P3 5 Ps Iv gt Request v gt Core Timer T3 sr L ee Up Down T30UT P3 3 x 2 4 T30E MCB02035 Note Line only affected by over underflows of T3 but NOT by software modifications of T3OTL Figure 9 8 GPT1 Auxiliary Timer in Reload Mode Upon a trigger signal T3 is loaded with the contents of the respective timer register T2 or T4 and the interrupt request flag T2IR or T4IR is set Note When a T3OTL transition is selected for the trigger signal also the interrupt request flag T3IR will be set upon a trigger indicating T3 s overflow or underflow Modifications of T3OTL via software will NOT trigger the counter function of T2 T4 The reload mode triggered by T3OTL can be used in a number of different configurations Depending on the selected active transition the following functions can be performed If both a positive and a negative transition of T3OTL is selected to trigger a reload the core timer will be reloaded with the contents of the auxiliary timer each time it overflows o
255. ernal Interrupt inputs EXTIN EXOIN P2 15 in addition serves as input for CAPCOMe timer T7 T7IN Semiconductor Group 6 12 SIEMENS Parallel Ports C167 The table below summarizes the alternate functions of Port 2 Port 2 Pin Alternate Alternate Function b Alternate Function c Function a P2 0 CCOIO P2 1 CC1IO P2 2 CC2lO P2 3 CC3IO P2 4 CC4IO P2 5 CC5IO P2 6 CC6lO P2 7 CC7IO P2 8 CC8IO EXOIN Fast External Interrupt O Input P2 9 CC9IO EX1IN Fast External Interrupt 1 Input P2 10 CC10lIO EX2IN Fast External Interrupt 2 Input P2 11 CC111O EX3IN Fast External Interrupt 3 Input P2 12 CC121O EX4IN Fast External Interrupt 4 Input P2 13 CC1310 EX5IN Fast External Interrupt 5 Input P2 14 CC14lIO EX6IN Fast External Interrupt 6 Input P2 15 CC15IO EX7IN Fast External Interrupt 7 Input T7IN Timer T7 Ext Count Input Alternate Function P2 15 CC151O P2 14 CC14IO P2 13 CC1310 P2 12 CC1210 P2 11 CC1110 P2 10 CC10IO P2 9 CC9IO P2 8 CC8lO P2 7 CC7IO P2 6 CC 6IO P2 5 CC5IO P2 4 CC4IO P2 3 CCS3IO P2 2 CC2IO P2 1 CC1IO P2 0 CCOIO General Purpose CAPCOM1 Fast External CAPCOM2 Input Output Capt Inp Comp Output Interrupt Input Timer T7 Input Figure 6 8 Port 2 IO and Alternate Functions Semiconductor Group 6 13 SIEMENS Parallel Ports C167 The pins of Port 2 combine internal bus data and alternate data output before the port latch input
256. error status flags SOFE SOPE SOOE are not reset automatically upon entry into the error interrupt service routine but must be cleared by software SOTIC FF6C B6 SFR Reset Value 00 5 4 3 2 1 0 rw rw SORIC FF6E B71 SFR Reset Value 00 7 6 5 4 3 2 1 0 commons o mal 7 rw rw rw rw SOEIC FF70 B8j SFR Reset Value 00 7 6 5 4 3 2 1 0 soem um owe 7 rw rw rw rw SOTBIC F19C CEp ESFR Reset Value 00 7 5 4 3 2 1 0 r Sos TBIR TBIE ILVL GLVL E E E 3 rw rw rw Note Please refer to the general Interrupt Control Register description for an explanation of the control fields Semiconductor Group 10 12 Sl EM ENS The Asynchronous Synchronous Serial Interface C167 Using the ASCO Interrupts For normal operation ie besides the error interrupt the ASCO provides three interrupt requests to control data exchange via this serial channel SOTBIR is activated when data is moved from SOTBUF to the transmit shift register SOTIR is activated before the last bit of an asynchronous frame is transmitted or after the last bit of a synchronous frame has been transmitted SORIR is activated when the received frame is moved to SORBUF While the task of the receive interrupt handler is quite clear the transmitter is serviced by two interrupt handlers This provides advantages for the servicing software For single transfers
257. es an address area of 32 KByte even if the implemented mask ROM or Flash memory is smaller than that eg 8 KByte ROM Configuration during Reset The control input pin EA External Access enables the user to define the address area from which the first instructions after reset are fetched When EA is low 0 during reset the internal ROM area is disabled and the first instructions are fetched from external memory When EA is high 1 during reset the internal ROM area is globally enabled and the first instructions are fetched from the internal ROM Note Be sure not to select internal ROM access after reset on ROMless devices Mapping the Internal ROM Area After reset the internal ROM area is mapped into segment 0 the system segment 00 0000 00 7FFF as a default This is necessary to allow the first instructions to be fetched from locations 00 0000 ff The ROM area may be mapped to segment 1 01 0000 01 7FFFj by setting bit ROMS1 in register SYSCON The internal ROM may now be accessed through the lower half of segment 1 while accesses to segment 0 will now be made to external memory This adds flexibility to the system software The interrupt trap vector table which uses locations 00 0000 through 00 01FFy is now part of the external memory and may therefore be modified ie the system software may now change interrupt trap handlers according to the current condition of the system The internal ROM can still
258. es of a bus cycle like chip select mode usage of READY length of ALE external bus mode read write delay and waitstates are controlled via registers BUSCONA BUSCONO Four of these registers BUSCON4 BUSCON1 have an address select register ADDRSEL4 ADDRSEL1 associated with them which allows to specify up to four address areas and the individual bus characteristics within these areas All accesses that are not covered by these four areas are then controlled via BUSCONO This allows to use memory components or peripherals with different interfaces within the same system while optimizing accesses to each of them Semiconductor Group 8 16 SIEMENS The External Bus Interface C167 SYSCON FF12 894 SFR Reset Value OXX0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GT BYT CLK WR VISI XPER rw rw rw rw rw rw rw rw rw rw XPER SHARE XBUS Peripheral Share Mode Control Bit Function 0 External accesses to XBUS peripherals are disabled 1 XBUS peripherals are accessible via the external bus during hold mode VISIBLE Visible Mode Control 0 Accesses to XBUS peripherals are done internally 1 XBUS peripheral accesses are made visible on the external pins XPEN XBUS Peripheral Enable Bit 0 Accesses to the on chip X Peripherals and their functions are disabled 1 The on chip X Peripherals are enabled and can be accessed WRCFG Write Configuration Control Set according to pin P
259. esents the logical ANDing of the two specified bits V Flag For addition subtraction and 2 s complementation the V flag is always set to 1 if the result overflows the maximum range of signed numbers which are representable by either 16 bits for word operations 8000 to 7FFF or by 8 bits for byte operations 80 to 7Fp otherwise the V flag is cleared Note that the result of an integer addition integer subtraction or 2 s complement is not valid if the V flag indicates an arithmetic overflow For multiplication and division the V flag is set to 1 if the result cannot be represented in a word data type otherwise it is cleared Note that a division by zero will always cause an overflow In contrast to the result of a division the result of a multiplication is valid regardless of whether the V flag is set to 1 or not Since logical ALU operations cannot produce an invalid result the V flag is cleared by these operations The V flag is also used as Sticky Bit for rotate right and shift right operations With only using the C flag a rounding error caused by a shift right operation can be estimated up to a quantity of one half of the LSB of the result In conjunction with the V flag the C flag allows evaluating the rounding error with a finer resolution see table below For Boolean bit operations with only one operand the V flag is always cleared For Boolean bit operations with two operands the V flag represen
260. ess marked x are disregarded Bit field RGSZ Resulting Window Size Relevant Bits R of Start Address A23 A12 0000 4 KByte R RR Re oR Re RR RY RR R 0001 8 KByte R RR RR RR RH R R Xx 0010 16 KByte R RR RRR R RR R x X 0011 32 KByte R RR RRR H R RX x X 0100 64 KByte R RR R RR RR x x x x 0101 128 KByte R RR RRR R x xxx x 0110 256 KByte R RR RRR x x x x x x 0111 512 KByte R RR RR So XXX 30 X X 1000 1 MByte R RR Hox x x X X X X X 1001 2 MByte R RR X OX XX 3X ROE X 1010 4 MByte R Ree Xo X 360x326 0X0 0X XX 1011 8 MByte Hox OR SE Xo 030 X XX XX CX 11xx Reserved Semiconductor Group 8 21 SIEMENS The External Bus Interface C167 Address Window Arbitration For each access the EBC compares the current address with all address select registers programmable ADDRSELx and hardwired XADRSx This comparison is done in four levels Priority 1 The hardwired XADRSx registers are evaluated first A match with one of these registers directs the access to the respective X Peripheral using the corresponding XBCONx register and ignoring all other ADDRSELx registers Priority 2 Registers ADDRSEL2 and ADDRSEL4 are evaluated before ADDRSEL1 and ADDRSELS respectively A match with one of these registers directs the access to the respective external area using the corresponding BUSCONXx register and ignoring registers ADDRSEL 1 3 see figure below Priority 3 A match with registers ADDRSEL1 or ADDRSELS directs the access
261. essage object 15 may be configured for Basic CAN functionality Both modes provide separate masks for acceptance filtering which allows to accept a number of identifiers in Full CAN mode and also allows to disregard a number of identifiers in Basic CAN mode All message objects can be updated independent from the other objects and are equipped for the maximum message length of 8 bytes The bit timing is derived from the XCLK and is programmable up to a data rate of 1 MBaud The CAN Module uses two pins to interface to a bus transceiver Note The CAN Module is not part of all C167 derivatives This description of course refers to those devices only which incorporate a CAN Module Semiconductor Group 2 13 SIEMENS Architectural Overview C167 General Purpose Timer GPT Unit The GPT units represent a very flexible multifunctional timer counter structure which may be used for many different time related tasks such as event timing and counting pulse width and duty cycle measurements pulse generation or pulse multiplication The five 16 bit timers are organized in two separate modules GPT1 and GPT2 Each timer in each module may operate independently in a number of different modes or may be concatenated with another timer of the same module Each timer can be configured individually for one of three basic modes of operation which are Timer Gated Timer and Counter Mode In Timer Mode the input clock for a timer is derived from the i
262. g data arrays especially in HLL applications using large memory models this may require frequent reloading of the DPPs even for single accesses The EXTP extend page instruction allows switching to an arbitrary data page for 1 4 instructions without having to change the current DPPs EXAMPLE EXTP R15 1 The override page number is stored in R15 MOV RO R14 The 14 bit page offset is stored in R14 MOV R1 R13 This instruction uses the standard DPP scheme The EXTS extend segment instruction allows switching to a 64 KByte segment oriented data access scheme for 1 4 instructions without having to change the current DPPs In this case all 16 bits of the operand address are used as segment offset with the segment taken from the EXTS instruction This greatly simplifies address calculation with continuous data like huge arrays in C EXAMPLE EXTS 15 1 The override seg is 15 OF 0000 0F FFFF MOV RO R14 The 16 bit segment offset is stored in R14 MOV R1 R13 This instruction uses the standard DPP scheme Note Instructions EXTP and EXTS inhibit interrupts the same way as ATOMIC Short Addressing in the Extended SFR ESFR Space The short addressing modes of the C167 REG or BITOFF implicitly access the SFR space The additional ESFR space would have to be accessed via long addressing modes MEM or Rw The EXTR extend register instruction redirects accesses in short addressing modes to the ESFR s
263. g time for a single instruction to be extended either by a half or by one machine cycle Although this additional time represents only a tiny part of the total program execution time it might be of interest to avoid these pipeline caused time delays in time critical program modules Besides a general execution time description the following section provides some hints on how to optimize time critical program parts with regard to such pipeline caused timing particularities Semiconductor Group 4 8 SIEMENS The Central Processing Unit CPU C167 4 2 Bit Handling and Bit Protection The C167 provides several mechanisms to manipulate bits These mechanisms either manipulate software flags within the internal RAM control on chip peripherals via control bits in their respective SFRs or control IO functions via port pins The instructions BSET BCLR BAND BOR BXOR BMOV BMOVN explicitly set or clear specific bits The instructions BFLDL and BFLDH allow to manipulate up to 8 bits of a specific byte at one time The instructions JBC and JNBS implicitly clear or set the specified bit when the jump is taken The instructions JB and JNB also conditional jump instructions that refer to flags evaluate the specified bit to determine if the jump is to be taken Note Bit operations on undefined bit locations will always read a bit value of 0 while the write access will not effect the respective bit location All instructions that manipulate s
264. gnal selectable multiple of the oscillator frequency ie the input frequency These bits are latched in register RPOH P0 15 13 CPU External Clock Input Notes POH 7 5 Frequency fcpy Range fytaL F 1 1 1 faa 4 2 5 to 6 25 MHz Default configuration 1 1 0 fx 3 3 33 to 8 33 MHz 1 0 1 faa 2 5 to 12 5 MHz 1 00 haa D 2 to 5 MHz 0 X X fio A 1 to 25 MHz Direct drive 2 1 The external clock input range refers to a CPU clock range of 10 25 MHz for PLL operation 2 The maximum depends on the duty cycle of the external clock signal Default On chip PLL is active with a factor of 1 4 Note Watch the different requirements for frequency and duty cycle of the oscillator input clock for the possible selections Semiconductor Group 17 11 SIEMENS Power Reduction Modes C167 18 Power Reduction Modes Two different power reduction modes with different levels of power reduction have been implemented in the C167 which may be entered under software control In Idle mode the CPU is stopped while the peripherals continue their operation Idle mode can be terminated by any reset or interrupt request In Power Down mode both the CPU and the peripherals are stopped Power Down mode can only be terminated by a hardware reset Note All external bus actions are completed before Idle or Power Down mode is entered However Idle or Power Down mode is not entered if READY is enabled but has not be
265. h is set upon a compare event and and cleared upon a timer overflow see Timing Example above However when compare value and reload value for a channel are equal the respective interrupt requests will be generated only the output signal is not changed set and clear would coincide in this case Note If the port output latch is written to by software at the same time it would be altered by a compare event the software write will have priority In this case the hardware triggered change will not become effective On channels 24 27 compare mode 1 will generate interrupt requests but no output function is provided Semiconductor Group 14 17 SIEMENS The Capture Compare Units C167 Double Register Compare Mode In double register compare mode two compare registers work together to control one output pin This mode is selected by a special combination of modes for these two registers For double register mode the 16 capture compare registers of each CAPCOM unit are regarded as two banks of 8 registers each Registers CCO CC7 and CC16 CC23 form bank 1 while registers CC8 CC15 and CC24 CC31 form bank 2 respectively For double register mode a bank 1 register and a bank 2 register form a register pair Both registers of this register pair operate on the pin associated with the bank 1 register pins CCOIO CC7IO and CC161O CC231O The relationship between the bank 1 and bank 2 register of a pair and the effected output pin
266. hardware reset with POL 4 high or a software reset Default The C167 starts fetching code from location 00 0000 the bootstrap loader is off Semiconductor Group 17 8 SIEMENS System Reset C167 External Bus Type Pins POL 7 and POL 6 BUSTYP select the external bus type during reset if an external start is selected via pin EA This allows the configuration of the external bus interface of the C167 even for the first code fetch after reset The two bits are copied into bit field BTYP of register BUSCONO POL 7 controls the data bus width while POL 6 controls the address output multiplexed or demultiplexed This bit field may be changed via software after reset if required BTYP External Data Bus Width External Address Bus Mode Encoding 00 8 bit Data Demultiplexed Addresses 0 1 8 bit Data Multiplexed Addresses 10 16 bit Data Demultiplexed Addresses 11 16 bit Data Multiplexed Addresses PORTO and PORT1 are automatically switched to the selected bus mode In multiplexed bus modes PORTO drives both the 16 bit intra segment address and the output data while PORT1 remains in high impedance state as long as no demultiplexed bus is selected via one of the BUSCON registers In demultiplexed bus modes PORT1 drives the 16 bit intra segment address while PORTO or POL according to the selected data bus width drives the output data For a 16 bit data bus BHE is automatically enabled for an 8 bit data bus BHE is
267. hat entered the pipeline after setting of the interrupt request flag N 1 N 2 will be executed after returning from the interrupt service routine The minimum interrupt response time is 5 states 250 ns 20 MHz CPU clock This requires program execution from the internal ROM no external operand read requests and setting the interrupt request flag during the last state of an instruction cycle When the interrupt request flag is set during the first state of an instruction cycle the minimum interrupt response time under these conditions is 6 state times 300 ns 20 MHz CPU clock The interrupt response time is increased by all delays of the instructions in the pipeline that are executed before entering the service routine including N Semiconductor Group 5 17 SIEMENS Interrupt and Trap Functions C167 When internal hold conditions between instruction pairs N 2 N 1 or N 1 N occur or instruction N explicitly writes to the PSW or the SP the minimum interrupt response time may be extended by 1 state time for each of these conditions When instruction N reads an operand from the internal ROM or when N is a call return trap or MOV Rn Rm data16 instruction the minimum interrupt response time may additionally be extended by 2 state times during internal ROM program execution In case instruction N reads the PSW and instruction N 1 has an effect on the condition flags the interrupt response time may additionally be extende
268. he C167 is in Hold State code execution from internal RAM ROM this Hold State is left only after HOLD has been deactivated again le in this case the current Hold State continues and only the next HOLD request is not answered Connecting eg two C167s in this way would require additional logic to combine the respective output signals HLDA and BREQ This can be avoided by switching one of the controllers into Slave Mode where pin HLDA is switched to input This allows to directly connect the slave controller to another master controller without glue logic The Slave Mode is selected by setting bit DP6 7 to 1 DP6 7 0 default after reset selects the Master Mode Note The pins HOLD HLDA and BREQ keep their alternate function bus arbitration even after the arbitration mechanism has been switched off by clearing HLDEN All three pins are used for bus arbitration after bit HLDEN was set once Semiconductor Group 8 25 SIEMENS The External Bus Interface C167 Connecting Bus Masters When multiple C167s or a C167 and another bus master shall share external resources some glue logic is required that defines the currently active bus master and also enables a C167 which has surrendered its bus interface to regain control of it in case it must access the shared external resources This glue logic is required if the other bus master does not automatically remove its hold request after having used the shared resources When two C1
269. he NMI Non Maskable Interrupt pin is externally pulled low while the PWRDN instruction is executed The microcontroller will enter Power Down mode after the PWRDN instruction has completed This feature can be used in conjunction with an external power failure signal which pulls the NMI pin low when a power failure is imminent The microcontroller will enter the NMI trap routine which can save the internal state into RAM After the internal state has been saved the trap routine may set a flag or write a certain bit pattern into specific RAM locations and then execute the PWRDN instruction If the NMI pin is still low at this time Power Down mode will be entered otherwise program execution continues During power down the voltage at the Vcc pins can be lowered to 2 5 V while the contents of the internal RAM will still be preserved The initialization routine executed upon reset can check the identification flag or bit pattern within RAM to determine whether the controller was initially switched on or whether it was properly restarted from Power Down mode Semiconductor Group 18 3 SIEMENS Power Reduction Modes C167 18 3 Status of Output Pins during Idle and Power Down Mode During Idle mode the CPU clocks are turned off while all peripherals continue their operation in the normal way Therefore all ports pins which are configured as general purpose output pins output the last data value which was written to their port output latches
270. he analog inputs to the A D Converter Port 7 provides the output signals from the PWM unit and inputs outputs for the CAPCOM2 unit Port 8 provides inputs outputs for the CAPCOM2 unit Four pins of PORT1 may also be used as inputs for the CAPCOM2 unit All port lines that are not used for these alternate functions may be used as general purpose IO lines Semiconductor Group 2 12 SIEMENS Architectural Overview C167 Serial Channels Serial communication with other microcontrollers processors terminals or external peripheral components is provided by two serial interfaces with different functionality an Asynchronous Synchronous Serial Channel ASCO and a High Speed Synchronous Serial Channel SSC They are upward compatible with the serial ports of the Siemens 8 bit microcontroller families and support full duplex asynchronous communication at up to 625 KBaud and half duplex synchronous communication at up to 5 MBaud 2 5 MBaud on the ASCO 20 MHz CPU clock The SSC may be configured so it interfaces with serially linked peripheral components Two dedicated baud rate generators allow to set up all standard baud rates without oscillator tuning For transmission reception and error handling 3 separate interrupt vectors are provided on channel SSC 4 vectors are provided on channel ASCO In asynchronous mode 8 or 9 bit data frames are transmitted or received preceded by a start bit and terminated by one or two stop bits For mul
271. he arbitration logic the external bus can be returned to the C167 under two circumstances The external master does no more require access to the shared resources and gives up its own access rights or The C167 needs access to the shared resources and demands this by activating its BREQ output The arbitration logic may then deactivate the other master s HLDA and so free the external bus for the C167 depending on the priority of the different masters Note The Hold State is not terminated by clearing bit HLDEN Other M Signals MCD02236 Figure 8 14 External Bus Arbitration Regaining the Bus Note The falling BREQ edge shows the last chance for BREQ to trigger the indicated regain sequence Even if BREQ is activated earlier the regain sequence is initiated by HOLD going high BREQ and HOLD are connected via an external arbitration circuitry Please note that HOLD may also be deactivated without the C167 requesting the bus Semiconductor Group 8 28 SIEMENS The External Bus Interface C167 8 7 The XBUS Interface The C167 provides an on chip interface the XBUS interface which allows to connect integrated customer application specific peripherals to the standard controller core The XBUS is an internal representation of the external bus interface ie itis operated in the same way The current XBUS interface is prepared to support up to 3 X Peripherals For each
272. he carry flag are then used to round the floating point result based on the desired rounding algorithm 19 7 Trap Interrupt Entry and Exit Interrupt routines are entered when a requesting interrupt has a priority higher than the current CPU priority level Traps are entered regardless of the current CPU priority When either a trap or interrupt routine is entered the state of the machine is preserved on the system stack and a branch to the appropriate trap interrupt vector is made All trap and interrupt routines require the use of the RETI return from interrupt instruction to exit from the called routine This instruction restores the system state from the system stack and then branches back to the location where the trap or interrupt occurred 19 8 Unseparable Instruction Sequences The instructions of the C167 are very efficient most instructions execute in one machine cycle and even the multiplication and division are interruptable in order to minimize the response latency to interrupt requests internal and external In many microcontroller applications this is vital Some special occasions however require certain code sequences eg semaphore handling to be uninterruptable to function properly This can be provided by inhibiting interrupts during the respective code sequence by disabling and enabling them before and after the sequence The necessary overhead may be reduced by means of the ATOMIC instruction which allows locking 1
273. he hardware compares the contents of the shadow register with the contents of the associated counter PTx When a match is found between counter and PPx shadow register the counter is either reset to 0000p or the count direction is switched from counting up to counting down depending on the selected operating mode of that PWM channel Note For the register locations please refer to the table below Pulse Width Registers PWx This 16 bit register holds the actual PWM pulse width value which corresponds to the duty cycle of the PWM signal This register is buffered with a shadow register The CPU accesses the PWx register while the hardware compares the contents of the shadow register with the contents of the associated counter PTx The shadow register is loaded from the respective PWx register at the beginning of every new PWM cycle or upon a write access to PWx while the timer is stopped When the counter value is greater than or equal to the shadow register value the PWM signal is set otherwise it is reset The output of the comparators may be described by the boolean formula PWM output signal PTx gt PWx shadow latch This type of comparison allows a flexible control of the PWM signal Note For the register locations please refer to the table below PWM Module Channel Specific Register Addresses Register Address Reg Space Register Address Reg Space Pwo FE30 18 SFR PTO F0304 184 ESFR
274. he serial clock signal can be generated by the SSC itself master mode or be received from an external master slave mode Data width shift direction clock polarity and phase are programmable This allows communication with SPl compatible devices Transmission and reception of data is double buffered A 16 bit baud rate generator provides the SSC with a separate serial clock signal The high speed synchronous serial interface can be configured in a very flexible way so it can be used with other synchronous serial interfaces eg the ASCO in synchronous mode serve for master slave or multimaster interconnections or operate compatible with the popular SPI interface So it can be used to communicate with shift registers IO expansion peripherals eg EEPROMs etc or other controllers networking The SSC supports half duplex and full duplex communication Data is transmitted or received on pins MTSR P3 9 Master Transmit Slave Receive and MRST P3 8 Master Receive Slave Transmit The clock signal is output or input on pin SCLK P3 13 These pins are alternate functions of Port 3 pins Ports amp Direction Control Data Registers Control Registers Interrupt Control Alternate Functions SSCCON SSCTIC SSCRIC SSCEIC SCLK P3 13 MTSR P3 9 MRST P3 8 ODP3 Port 3 Open Drain Control Register DP3 Port 3 Direction Control Register P3 Port 3 Data Register SSCBR SSC Baud Rate Generator Reload Register SSCCON SSC Control Register SSCTB S
275. hen the interrupt routine is exited with the RETI instruction this bit is implicitly tested before the old PSW is popped from the stack If MULIP 1 the multiply divide instruction is re read from the location popped from the stack return address and will be completed after the RETI instruction has been executed Note The MULIP flag is part of the context of the interrupted task When the interrupting routine does not return to the interrupted task eg scheduler switches to another task the MULIP flag must be set or cleared according to the context of the task that is switched to BCD Calculations No direct support for BCD calculations is provided in the C167 BCD calculations are performed by converting BCD data to binary data performing the desired calculations using standard data types and converting the result back to BCD data Due to the enhanced performance of division instructions binary data is quickly converted to BCD data through division by 10p Conversion from BCD data to binary data is enhanced by multiple bit shift instructions This provides similar performance compared to instructions directly supporting BCD data types while no additional hardware is required Semiconductor Group 19 3 SIEMENS System Programming C167 19 1 Stack Operations The C167 supports two types of stacks The system stack is used implicitly by the controller and is located in the internal RAM The user stack provides stack access to the u
276. herals are connected or when no PLL is implemented may be used to generate software controlled interrupt requests by setting the respective XPnIR bit Semiconductor Group 5 2 SIEMENS Interrupt and Trap Functions C167 Source of Interrupt or Request Enable Interrupt Vector Trap PEC Service Request Flag Flag Vector Location Number CAPCOM Register 0 CCOIR CCOIE CCOINT 00 0040 104 165 CAPCOM Register 1 CC1IR CC1IE CC1INT 00 0044 114 17p CAPCOM Register 2 CC2IR CC2IE CC2INT 00 0048 124 18p CAPCOM Register 3 CC3IR CC3IE CC3INT 00 004C 134 195 CAPCOM Register 4 CC4IR CC4IE CC4INT 00 0050 144 20p CAPCOM Register 5 CC5IR CC5IE CC5INT 00 0054 154 21p CAPCOM Register 6 CC6IR CC6IE CC6INT 00 0058 164 22p CAPCOM Register 7 CC7IR CC7IE CC7INT 00 005C 174 23p CAPCOM Register 8 CC8IR CC8IE CC8INT 00 0060 184 24p CAPCOM Register 9 CC9IR CC9IE CC9INT 00 0064 194 25p CAPCOM Register 10 CC10IR CC10IE CC10INT 0070068 1A4 26p CAPCOM Register 1 1 CC11IR CC11IE CC11INT 00 006C 1By 27p CAPCOM Register 12 CC12IR CC12IE CC12INT 000070 1Cy 285 CAPCOM Register 13 CC13IR CC13IE CC13INT 00 0074 1D 29p CAPCOM Register 14 CC14IR CC14IE CC14INT 0070078 1Eu 30p CAPCOM Register 15 CC15IR CC15IE CC15INT 00 007C4 1Fu 31p CAPCOM Register 16 CC16IR CC16IE CC16INT 00 00C0 30 48p CAPCOM Register 17 CC17IR CC17IE CC17IN
277. hich all share the same interrupt vector The status flags in the Trap Flag Register TFR can then be used to determine which exception caused the trap For the special software TRAP instruction the vector address is specified by the operand field of the instruction which is a seven bit trap number The reserved vector locations build a jump table in the low end of the C167 s address space segment 0 The jump table is made up of the appropriate jump instructions that transfer control to the interrupt or trap service routines which may be located anywhere within the address space The entries of the jump table are located at the lowest addresses in code segment 0 of the address space Each entry occupies 2 words except for the reset vector and the hardware trap vectors which occupy 4 or 8 words The table below lists all sources that are capable of requesting interrupt or PEC service in the C167 the associated interrupt vectors their locations and the associated trap numbers It also lists the mnemonics of the affected Interrupt Request flags and their corresponding Interrupt Enable flags The mnemonics are composed of a part that specifies the respective source followed by a part that specifies their function IR2Interrupt Request flag IE2Interrupt Enable flag Note The currently unused nodes in the table X Peripheral nodes are prepared to accept interrupt requests from integrated XBUS peripherals Those of these nodes where no X Perip
278. ial interface ASCO If single chip mode is selected during reset the first instruction is fetched from the internal ROM Otherwise it is fetched from external memory When internal ROM access is enabled after reset in single chip mode bit ROMEN in register SYSCON the software initialization routine may enable and configure the external bus interface before the execution of the EINIT instruction When external access is enabled after reset it may be desirable to reconfigure the external bus characteristics because the SYSCON register is initialized during reset to the slowest possible memory configuration To decrease the number of instructions required to initialize the C167 each peripheral is programmed to a default configuration upon reset but is disabled from operation These default configurations can be found in the descriptions of the individual peripherals During the software design phase portions of the internal memory space must be assigned to register banks and system stack When initializating the stack pointer SP and the context pointer CP it must be ensured that these registers are initialized before any GPR or stack operation is performed This includes interrupt processing which is disabled upon completion of the internal reset and should remain disabled until the SP is initialized Note Traps incl NMT may occur even though the interrupt system is still disabled In addition the stack overflow STKOV and the
279. igure below is a summary SSCPO SSCPH Serial Clock eT ERES MTSR MRST First Bit x 1 Transmit Data Latch Data MCA01 960 Shift Data Figure 11 3 Serial Clock Phase and Polarity Options Semiconductor Group 11 5 SIEM ENS The High Speed Synchronous Serial Interface C167 11 1 Full Duplex Operation The different devices are connected through three lines The definition of these lines is always determined by the master The line connected to the master s data output pin MTSR is the transmit line the receive line is connected to its data input line MRST and the clock line is connected to pin SCLK Only the device selected for master operation generates and outputs the serial clock on pin SCLK All slaves receive this clock so their pin SCLK must be switched to input mode DP3 13 0 The output of the master s shift register is connected to the external transmit line which in turn is connected to the slaves shift register input The output of the slaves shift register is connected to the external receive line in order to enable the master to receive the data shifted out of the slave The external connections are hard wired the function and direction of these pins is determined by the master or slave operation of the individual device Note The shift direction shown in the figure applies for MSB first operation as well as for LSB first operation When initializing the devices in this configurat
280. imer The current count value of the Watchdog Timer is contained in the Watchdog Timer Register WDT which is a non bitaddressable read only register The operation of the Watchdog Timer is controlled by its bitaddressable Watchdog Timer Control Register WDTCON This register specifies the reload value for the high byte of the timer selects the input clock prescaling factor and provides a flag that indicates a watchdog timer overflow WDTCON FFAE D7 SFR Reset Value 000X 15 14 13 12 11 10 9 8 7 6 5 4 3 2 141 0 WDT WDT WDTREL R IN r I rw rw Bit Function WDTIN Watchdog Timer Input Frequency Selection 0 Input frequency is fopy 2 1 Input frequency is fepy 128 WDTR Watchdog Timer Reset Indication Flag Set by the watchdog timer on an overflow Cleared by a hardware reset or by the SRVWDT instruction WDTREL Watchdog Timer Reload Value for the high byte Note The reset value will be 0002 if the reset was triggered by the watchdog timer overflow It will be 0000p otherwise After any software reset external hardware reset see note or watchdog timer reset the watchdog timer is enabled and starts counting up from 0000 with the frequency fopy 2 The input frequency may be switched to fc pj 128 by setting bit WDTIN The watchdog timer can be disabled via the instruction DISWDT Disable Watchdog Timer Instruction DISWDT is a protected 32 bit instruction which will O
281. in compare mode 1 this port pin must be configured as output ie the corresponding direction control bit must be set to 1 With this configuration the initial state of the output signal can be programmed or its state can be modified at any time by writing to the port output latch In compare mode 1 the port latch is toggled upon each compare event see Timing Example above Note If the port output latch is written to by software at the same time it would be altered by a compare event the software write will have priority In this case the hardware triggered change will not become effective If compare mode 1 is programmed for one of the registers CCO CC7 or CC16 CC23 the double register compare mode becomes enabled for this register if the corresponding bank 1 register is programmed to compare mode 0 see section Double Register Compare Mode Note If the port output latch is written to by software at the same time it would be altered by a compare event the software write will have priority In this case the hardware triggered change will not become effective On channels 24 27 compare mode 1 will generate interrupt requests but no output function is provided Compare Mode 2 Compare mode 2 is an interrupt only mode similar to compare mode 0 but only one interrupt request per timer period will be generated Compare mode 2 is selected for register CCx by setting bit field CCMODx of the corresponding mode control register
282. in may be used for general purpose IO 1 CLKOUT enabled pin outputs the system clock signal BYTDIS Disable Enable Control for Pin BHE Set according to data bus width 0 Pin BHE enabled 1 Pin BHE disabled pin may be used for general purpose IO ROMEN Internal ROM Enable Set according to pin EA during reset 0 Internal ROM disabled accesses to the ROM area use the external bus 1 Internal ROM enabled SGTDIS Segmentation Disable Enable Control 0 Segmentation enabled CSP is saved restored during interrupt entry exit 1 Segmentation disabled Only IP is saved restored ROMS1 Internal ROM Mapping 0 Internal ROM area mapped to segment 0 00 0000 00 7 FFF 1 1 Internal ROM area mapped to segment 1 01 0000 01 7FFFj STKSZ System Stack Size Selects the size of the system stack in the internal RAM from 32 to 1024 words Note Register SYSCON cannot be changed after execution of the EINIT instruction The function of bits XPER SHARE VISIBLE WRCFG BYTDIS ROMEN and ROMS is described in more detail in chapter The External Bus Controller Semiconductor Group 4 12 SIEMENS The Central Processing Unit CPU C167 System Clock Output Enable CLKEN The system clock output function is enabled by setting bit CLKEN in register SYSCON to 1 If enabled port pin P3 15 takes on its alternate function as CLKOUT output pin The clock output
283. in the data detected at its input line MRST This exchanges the transmit data with the receive data Since the clock line is connected to all slaves their shift registers will be shifted synchronously with the master s shift register shifting out the data contained in the registers and shifting in the data detected at the input line After the preprogrammed number of clock pulses via the data width selection the data transmitted by the master is contained in all slaves shift registers while the master s shift register holds the data of the selected slave In the master and all slaves the content of the shift register is copied into the receive buffer SSCRB and the receive interrupt flag SSCRIR is set A slave device will immediately output the selected first bit MSB or LSB of the transfer data at pin MRST when the content of the transmit buffer is copied into the slave s shift register It will not wait for the next clock from the baudrate generator as the master does The reason for this is that depending on the selected clock phase the first clock edge generated by the master may be already used to clock in the first data bit So the slave s first data bit must already be valid at this time Semiconductor Group 11 7 SIEM ENS The High Speed Synchronous Serial Interface C167 Note On the SSC always a transmission and a reception takes place at the same time regardless whether valid data has been transmitted or received This
284. in the figure stays very well below it This depends on the host interface Semiconductor Group 13 5 SIEMENS The Capture Compare Units C167 14 The Capture Compare Units The C167 provides two almost identical Capture Compare CAPCOM units which only differ in the way they are connected to the C167 s IO pins They provide 32 channels which interact with 4 timers The CAPCOM units can capture the contents of a timer on specific internal or external events or they can compare a timer s content with given values and modify output signals in case of a match With this mechanism they support generation and control of timing sequences on up to 16 channels per unit with a minimum of software intervention From the programmer s point of view the term CAPCOM unit refers to a set of SFRs which are associated with this peripheral including the port pins which may be used for alternate input output functions including their direction control bits Ports amp Direction Control Data Registers Control Registers Interrupt Control Alternate Functions TO1CON TOIC TO T1 T7 T8 E E CC20 23 CC20IC 23IC E CCOIO P2 0 CC1510 P2 15 CC24 27 CC24IC 27IC E CC161O P8 0 CC23IO P8 7 CC24IO P1H 4 CC2710 P1H 7 CC28 31 CC281C 311C E CC2810O P7 4 CC811O P7 7 ODPx Port x Open Drain Control Register TxREL CAPCOM Timer x Reload Register DPx Port x Direction Control Register Tx CAPCOM Timer x Register Px Port x Data Register C
285. in this context means Transfer speed Data rates of up to 1 Mbit sec can be achieved Data integrity The CAN protocol provides several means for error checking Host processor unloading The controller here handles most of the tasks autonomously Flexible and powerful message passing The extended CAN protocol is supported Note The CAN Module is not part of all C167 derivatives This description of course refers to those devices only which incorporate a CAN Module The integrated CAN Module handles the completely autonomous transmission and reception of CAN frames in accordance with the CAN specification V2 0 part B active ie the on chip CAN Module can receive and transmit standard frames with 11 bit identifiers as well as extended frames with 29 bit identifiers It provides Full CAN functionality on up to 15 full sized message objects 8 data bytes each Message object 15 may be configured for Basic CAN functionality with a double buffered receive object Both modes provide separate masks for acceptance filtering which allows the acceptance of a number of identifiers in Full CAN mode and also allows disregarding a number of identifiers in Basic CAN mode All message objects can be updated independent from the other objects and are equipped with buffers for the maximum message length of 8 bytes The bit timing is derived from the XCLK and is programmable up to a data rate of 1 MBaud O 20 MHz CPU clock The CAN Module uses two
286. ine the response to interrupt requests and enable external bus arbitration Described in section Interrupt and Trap Functions ALU Status N C V Z E MULIP The condition flags N C V Z E within the PSW indicate the ALU status due to the last recently performed ALU operation They are set by most of the instructions due to specific rules which depend on the ALU or data movement operation performed by an instruction After execution of an instruction which explicitly updates the PSW register the condition flags cannot be interpreted as described in the following because any explicit write to the PSW register supersedes the condition flag values which are implicitly generated by the CPU Explicitly reading the PSW register supplies a read value which represents the state of the PSW register after execution of the immediately preceding instruction Note After reset all of the ALU status bits are cleared Semiconductor Group 4 14 SIEMENS The Central Processing Unit CPU C167 N Flag For most of the ALU operations the N flag is set to 1 if the most significant bit of the result contains a 1 otherwise it is cleared In the case of integer operations the N flag can be interpreted as the sign bit of the result negative N2 1 positive N 0 Negative numbers are always represented as the 2 s complement of the corresponding positive number The range of signed numbers extends from 8000 to 7FF
287. ing device with the C167 s integrated Peripheral Event Controller PEC Triggered by an interrupt request the PEC performs a single word or byte data transfer between any two locations in segment 0 data pages 0 through 3 through one of eight programmable PEC Service Channels During a PEC transfer the normal program execution of the CPU is halted for just 1 instruction cycle No internal program status information needs to be saved The same prioritization scheme is used for PEC service as for normal interrupt processing PEC transfers share the 2 highest priority levels Trap Functions Trap functions are activated in response to special conditions that occur during the execution of instructions A trap can also be caused externally by the Non Maskable Interrupt pin NMI Several hardware trap functions are provided for handling erroneous conditions and exceptions that arise during the execution of an instruction Hardware traps always have highest priority and cause immediate system reaction The software trap function is invoked by the TRAP instruction which generates a software interrupt for a specified interrupt vector For all types of traps the current program status is saved on the system stack External Interrupt Processing Although the C167 does not provide dedicated interrupt pins it allows to connect external interrupt sources and provides several mechanisms to react on external events including standard inputs non maskable interrupt
288. ing is supported for a part of the Special Function Registers a part of the internal RAM and for the General Purpose Registers a Bits x Bits s a po Byte Byte Word High Byte Word Low Byte MCA01996 Figure 3 2 Storage of Words Byte and Bits in a Byte Organized Memory Note Byte units forming a single word or a double word must always be stored within the same physical internal external ROM RAM and organizational page segment memory area Semiconductor Group 3 2 SIEMENS Memory Organization C167 3 1 Internal ROM The C167 may reserve an address area of variable size depending on the version for on chip mask programmable ROM organized as X 32 or Flash memory The lower 32 KByte of the on chip ROM Flash are referred to as Internal ROM Area Internal ROM accesses are globally enabled or disabled via bit ROMEN in register SYSCON This bit is set during reset according to the level on pin EA or may be altered via software If enabled the internal ROM area occupies the lower 32 KByte of either segment 0 or segment 1 This ROM mapping is controlled by bit ROMS1 in register SYSCON Note The size of the internal ROM area is independent of the size of the actual implemented ROM Also devices with less than 32 KByte of ROM or with no ROM at all will have this 32 KByte area occupied if the ROM is enabled Devices with larger ROMs provide the mapping option only for
289. ingle bits or bit groups internally use a read modify write sequence that accesses the whole word which contains the specified bit s This method has several consequences Bits can only be modified within the internal address areas ie internal RAM and SFRs External locations cannot be used with bit instructions The upper 256 bytes of the SFR area the ESFR area and the internal RAM are bit addressable see chapter Memory Organization ie those register bits located within the respective sections can be directly manipulated using bit instructions The other SFRs must be accessed byte word wise Note All GPRs are bit addressable independent of the allocation of the register bank via the context pointer CP Even GPRs which are allocated to not bit addressable RAM locations provide this feature The read modify write approach may be critical with hardware effected bits In these cases the hardware may change specific bits while the read modify write operation is in progress where the writeback would overwrite the new bit value generated by the hardware The solution is either the implemented hardware protection see below or realized through special programming see Particular Pipeline Effects Protected bits are not changed during the read modify write sequence ie when hardware sets eg an interrupt request flag between the read and the write of the read modify write sequence The hardware protection logic guarantees that only
290. interrupt vector SCRINT is the receive interrupt vector and SCEINT is the error interrupt vector The cause of an error interrupt request receive phase baudrate transmit error can be identified by the error status flags in control register SSCCON Note In contrary to the error interrupt request flag SSCEIR the error status flags SSCxE are not reset automatically upon entry into the error interrupt service routine but must be cleared by software SSCTIC FF72 B9 SFR Reset Value 00 MUN ts rls NEL ORUM ML EE NE WE CS EM ND 0 TIR TIE ILVL GLVL rw rw rw rw L O L L L L Ed SSCRIC FF74 BAy SFR Reset Value 00j 5 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RIR RIE ILVL GLVL mw rw rw rw L L L Zz L Ea SSCEIC FF76 BBy SFR Reset Value 00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 i 0 EIR EIE ILVL GLVL mw rw rw rw i i 28 E Note Please refer to the general Interrupt Control Register description for an explanation of the control fields Semiconductor Group 11 14 SIEMENS The Watchdog Timer WDT 80C166 12 The Watchdog Timer WDT To allow recovery from software or hardware failure the 80C166 provides a Watchdog Timer If the software fails to service this timer before an overflow occurs an internal reset sequence will be initiated This internal reset will also pull the RSTOUT pin low which also
291. ion select one device for master operation SSCMS 1 all others must be programmed for slave operation SSCMS 0 Initialization includes the operating mode of the device s SSC and also the function of the respective port lines see Port Control Master Device 1 Device 2 Shift Register Shift Register EE EL MR P 1 Receive vo gem pug Shift Register MCA01 963 Figure 11 4 SSC Full Duplex Configuration Semiconductor Group 11 6 SIEM ENS The High Speed Synchronous Serial Interface C167 The data output pins MRST of all slave devices are connected together onto the one receive line in this configuration During a transfer each slave shifts out data from its shift register There are two ways to avoid collisions on the receive line due to different slave data Only one slave drives the line ie enables the driver of its MRST pin All the other slaves have to program there MRST pins to input So only one slave can put its data onto the master s receive line Only receiving of data from the master is possible The master selects the slave device from which it expects data either by separate select lines or by sending a special command to this slave The selected slave then switches its MRST line to output until it gets a deselection signal or command The slaves use open drain output on MRST This forms a Wired AND connection The receive line needs an external pullup in this case
292. ion of the internal memory has been made bit addressable to allow user semaphores Instructions have also been provided to lock out tasks via software by setting or clearing user specific bits and conditionally branching based on these specific bits It is recommended that bit fields in control SFRs are updated using the BFLDH and BFLDL instructions or a MOV instruction to avoid undesired intermediate modes of operation which can occur when BCLR BSET or AND OR instruction sequences are used Semiconductor Group 19 11 SIEMENS System Programming C167 19 6 Floating Point Support All floating point operations are performed using software Standard multiple precision instructions are used to perform calculations on data types that exceed the size of the ALU Multiple bit rotate and logic instructions allow easy masking and extracting of portions of floating point numbers To decrease the time required to perform floating point operations two hardware features have been implemented in the CPU core First the PRIOR instruction aids in normalizing floating point numbers by indicating the position of the first set bit in a GPR This result can the be used to rotate the floating point result accordingly The second feature aids in properly rounding the result of normalized floating point numbers through the overflow V flag in the PSW This flag is set when a one is shifted out of the carry bit during shift right operations The overflow flag and t
293. ion or transmission is successfully completed or a CAN bus error is detected and registered in the status partition EIE Error Interrupt Enable Enables or disables interrupt generation on a change of bit BOFF or EWARN in the status partition CCE Configuration Change Enable Allows or inhibits CPU access to the Bit Timing Register 1 Test Mode Bit 7 Make sure that bit 7 is cleared when writing to the Control Register as this bit controls a special test mode that is used for production testing During normal operation however this test mode may lead to undesired behaviour of the device Semiconductor Group 23 6 SIEMENS The On Chip CAN Interface C167 Bit Function Status Bits LEC Last Error Code This field holds a code which indicates the type of the last error occurred on the CAN bus If a message has been transferred reception or transmission without error this field will be cleared Code 7 is unused and may be written by the CPU to check for updates 0 No Error 1 Stuff Error More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed 2 Form Error A fixed format part of a received frame has the wrong format 3 AckError The message this CAN controller transmitted was not acknowledged by another node 4 BittError During the transmission of a message with the exception of the arbitration field the device wanted to send a
294. ion over common buses Peripherals are controlled by data written to the respective Special Function Registers SFRs These SFRs are located either within the standard SFR area 00 FE004 00 FFFF or within the extended ESFR area 00 F000 00 F1FF j These built in peripherals either allow the CPU to interface with the external world or provide functions on chip that otherwise were to be added externally in the respective system The C167 generic peripherals are Two General Purpose Timer Blocks GPT1 and GPT2 Two Serial Interfaces ASCO and SSC A Watchdog Timer Two 16 channel Capture Compare units CAPCOM1 and CAPCOM2 A 4 channel Pulse Width Modulation unit A 10 bit Analog Digital Converter Nine IO ports with a total of 111 IO lines Each peripheral also contains a set of Special Function Registers SFRs which control the functionality of the peripheral and temporarily store intermediate data results Each peripheral has an associated set of status flags Individually selected clock signals are generated for each peripheral from binary multiples of the CPU clock Peripheral Interfaces The on chip peripherals generally have two different types of interfaces an interface to the CPU and an interface to external hardware Communication between CPU and peripherals is performed through Special Function Registers SFRs and interrupts The SFRs serve as control status and data registers for the peripherals Interru
295. iority increases with the numerical value of GLVL so 00g is the lowest and 11g is the highest group priority Semiconductor Group 5 7 SIEMENS Interrupt and Trap Functions C167 Note All interrupt request sources that are enabled and programmed to the same priority level must always be programmed to different group priorities Otherwise an incorrect interrupt vector will be generated Upon entry into the interrupt service routine the priority level of the source that won the arbitration and who s priority level is higher than the current CPU level is copied into bit field ILVL of register PSW after pushing the old PSW contents on the stack The interrupt system of the C167 allows nesting of up to 15 interrupt service routines of different priority levels level 0 cannot be arbitrated Interrupt requests that are programmed to priority levels 15 or 14 ie ILVL 111Xg will be serviced by the PEC unless the COUNT field of the associated PECC register contains zero In this case the request will instead be serviced by normal interrupt processing Interrupt requests that are programmed to priority levels 13 through 1 will always be serviced by normal interrupt processing Note Priority level 0000g is the default level of the CPU Therefore a request on level 0 will never be serviced because it can never interrupt the CPU However an enabled interrupt request on level 0000g will terminate the C167 s Idle mode and reactivate the CPU F
296. ired to be the same This offers a wide variety of different configurations T6 can operate in timer gated timer or counter mode in this case w t t Core Timer Ty TyIR n TyOTL eHO TyOUT Edge TyOE Up Down Select P4 Auxiliary Timer Tx URL MCB02034 A TxR Txl T6OUT P3 1 X 5 y 6 Note Line only affected by over underflows of T3 but NOT by software modifications of T3OTL Figure 9 17 Concatenation of Core Timer T6 and Auxiliary Timer T5 Semiconductor Group 9 27 SIEMENS The General Purpose Timer Units C167 GPT2 Capture Reload Register CAPREL in Capture Mode This 16 bit register can be used as a capture register for the auxiliary timer T5 This mode is selected by setting bit T5SC 1 in control register T5CON The source for a capture trigger is the external input pin CAPIN which is an alternate input function of port pin P3 2 Either a positive a negative or both a positive and a negative transition at this pin can be selected to trigger the capture function The active edge is controlled by bit field Cl in register T5CON The same coding is used as in the two least significant bits of bit field T5l see table in counter mode section The maximum input frequency for the capture trigger signal at CAPIN is fcpu 4 2 5 MHz fcpy 20 MHz To ensure that a transition of the capture trigger signal is correctly recognized its level should be held for at least 4 fopy cycles before it changes When a selecte
297. is a 50 duty cycle clock whose frequency equals the CPU operating frequency foyT fcpu Note The output driver of port pin P3 15 is switched on automatically when the CLKOUT function is enabled The port direction bit is disregarded After reset the clock output function is disabled CLKEN 0 Segmentation Disable Enable Control SGTDIS Bit SGTDIS allows to select either the segmented or non segmented memory mode In non segmented memory mode SGTDIS 1 it is assumed that the code address space is restricted to 64 KBytes segment 0 and thus 16 bits are sufficient to represent all code addresses For implicit stack operations CALL or RET the CSP register is totally ignored and only the IP is saved to and restored from the stack In segmented memory mode SGTDIS 0 it is assumed that the whole address space is available for instructions For implicit stack operations CALL or RET the CSP register and the IP are saved to and restored from the stack After reset the segmented memory mode is selected Note Bit SGTDIS controls if the CSP register is pushed onto the system stack in addition to the IP register before an interrupt service routine is entered and it is repopped when the interrupt service routine is left again System Stack Size STKSZ This bitfield defines the size of the physical system stack which is located in the internal RAM of the C167 An area of 32 512 words or all of the internal RAM may be dedicate
298. is different eg from asynchronous reception on ASCO The initialization of the SCLK pin on the master requires some attention in order to avoid undesired clock transitions which may disturb the other receivers The state of the internal alternate output lines is 1 as long as the SSC is disabled This alternate output signal is ANDed with the respective port line output latch Enabling the SSC with an idle low clock SSCPO 0 will drive the alternate data output and via the AND the port pin SCLK immediately low To avoid this use the following sequence e select the clock idle level SSCPO x load the port output latch with the desired clock idle level P3 132 x e switch the pin to output DP3 13 1 enable the SSC SSCEN 1 if SSCPO 0 enable alternate data output P3 13 1 The same mechanism as for selecting a slave for transmission separate select lines or special commands may also be used to move the role of the master to another device in the network In this case the previous master and the future master previous slave will have to toggle their operating mode SSCMS and the direction of their port pins see description above 11 2 Half Duplex Operation In a half duplex configuration only one data line is necessary for both receiving and transmitting of data The data exchange line is connected to both pins MTSR and MRST of each device the clock line is connected to the SCLK pin The master de
299. is is sufficient to use the transmitter interrupt SOTIR which indicates that the previously loaded data has been transmitted except for the last bit of an asynchronous frame For multiple back to back transfers it is necessary to load the following piece of data at last until the time the last bit of the previous frame has been transmitted In asynchronous mode this leaves just one bit time for the handler to respond to the transmitter interrupt request in synchronous mode itis impossible at all Using the transmit buffer interrupt SOTBIR to reload transmit data gives the time to transmit a complete frame for the service routine as SOTBUF may be reloaded while the previous data is still being transmitted Figure 10 6 ASCO Interrupt Generation As shown in the figure above SOTBIR is an early trigger for the reload routine while SOTIR indicates the completed transmission Software using handshake therefore should rely on SOTIR at the end of a data block to make sure that all data has really been transmitted Semiconductor Group 10 13 SIEM ENS The High Speed Synchronous Serial Interface C167 11 The High Speed Synchronous Serial Interface The High Speed Synchronous Serial Interface SSC provides flexible high speed serial communication between the C167 and other microcontrollers microprocessors or external peripherals The SSC supports full duplex and half duplex synchronous communication up to 5 MBaud 20 MHz CPU clock T
300. it instructions Semiconductor Group 19 1 SIEMENS System Programming C167 Multiplication or division is simply performed by specifying the correct signed or unsigned version of the multiply or divide instruction The result is then stored in register MD The overflow flag V is set if the result from a multiply or divide instruction is greater than 16 bits This flag can be used to determine whether both word halfs must be transferred from register MD The high portion of register MD MDH must be moved into the register file or memory first in order to ensure that the MDRIU flag reflects the correct state The following instruction sequence performs an unsigned 16 by 16 bit multiplication SAVE JNB MDRIU START Test if MD was in use SCXT MDC 0010H Save and clear control register leaving MDRIU set only required for interrupted multiply divide instructions BSET SAVED Indicate the save operation PUSH MDH Save previous MD contents PUSH MDL On system stack START MULU R1 R2 Multiply 16 16 unsigned Sets MDRIU JMPR cc NV COPYL Test for only 16 bit result MOV R3 MDH Move high portion of MD COPYL MOV R4 MDL Move low portion of MD Clears MDRIU RESTORE JNB SAVED DONE Test if MD registers were saved POP MDL Restore registers POP MDH POP MDC BCLR SAVED Multiplication is completed program continues DONE The above save sequence and the restore sequence after COPYL are only required if the current r
301. ive or both a positive and a negative external signal transition at the pin can be selected as the triggering event The contents of all registers which have been selected for one of the five compare modes are continuously compared with the contents of the allocated timers When a match occurs between the timer value and the value in a capture compare register specific actions will be taken based on the selected compare mode Pulse Width Modulation Unit The PWM Unit supports the generation of up to four independent high speed PWM signals It allows to generate standard edge aligned PWM signals as well as symmetrical center aligned PWM signals In Burst Mode two channels may be combined with their output signals ANDed where one channel gates the output signal of the other channel Single Shot Mode allows to generate single output pulses retriggerable under software control Each PWM channel is controlled by an up down counter with associated reload and compare registers The polarity of the PWM output signals may be controlled via the respective port output latch combination via EXOR Semiconductor Group 2 15 SIEMENS Architectural Overview C167 A D Converter For analog signal measurement a 10 bit A D converter with 16 multiplexed input channels and a sample and hold circuit has been integrated on chip It uses the method of successive approximation The sample time for loading the capacitors and the conversion time is program
302. ive bit PSx in register PWMCON1 to 1 This mode is available for PWM channels 2 and 3 In this mode the timer PTx of the respective PWM channel is started via software and is counting up until it reaches the value in the associated period shadow register Upon the next count pulse the timer is cleared to 0000 and stopped via hardware ie the respective PTRx bit is cleared The PWM output signal is switched to high level when the timer contents are equal to or greater than the contents of the pulse width shadow register The signal is switched back to low level when the respective timer is cleared ie is below the pulse width shadow register Thus starting a PWM timer in single shot mode produces one single pulse on the respective port pin provided that the pulse width value is between 0000 and the period value In order to generate a further pulse the timer has to be started again via software by setting bit PTRx PPx Period 7 PTx Count Value PWx Pulse Width 4 Set PTRx by LSR Set PTRx by Software PTRx Reset by Software for Hardware Next Pulse PTx stopped PTx Count Value PWx Pulse Width 4 Retrigger after Pulse Trigger before Pulse has has started Write PWx started Write PWx value value to PTx to PTx Shortens Delay Time f MCA01952 Figure 15 6 Operation and Output Waveform in Single Shot Mode Semiconductor Group 15 6 The Pulse Width Modulation Modul
303. l be 0 Therefore writing only 0 s to reserved locations provides portability of the current software to future devices Read accesses to reserved bits return 0 s Parallel Ports The C167 provides up to 111 IO lines which are organized into eight input output ports and one input port All port lines are bit addressable and all input output lines are individually bit wise programmable as inputs or outputs via direction registers The IO ports are true bidirectional ports which are switched to high impedance state when configured as inputs The output drivers of three IO ports can be configured pin by pin for push pull operation or open drain operation via control registers During the internal reset all port pins are configured as inputs All port lines have programmable alternate input or output functions associated with them PORTO and PORT1 may be used as address and data lines when accessing external memory while Port 4 outputs the additional segment address bits A23 19 17 A16 in systems where segmentation is used to access more than 64 KBytes of memory Port 6 provides optional bus arbitration signals BREQ HLDA HOLD and chip select signals Port 2 accepts the fast external interrupt inputs and provides inputs outputs for the CAPCOM unit Port 3 includes alternate functions of timers serial interfaces the optional bus control signal BHE and the system clock output CLKOUT Port 5 is used for timer control signals and for t
304. le of addressing an SFR ZEROS FF1Cy 8Ep SFR Reset Value 00004 15 14 13 12 1 10 9 8 7 6 5 4 3 2 0 The Constant Ones Register ONES All bits of this bit addressable register are fixed to 1 by hardware This register can be read only Register ONES can be used as a register addressable constant of all ones ie for bit manipulation or mask generation It can be accessed via any instruction which is capable of addressing an SFR ONES FF1Ey 8Fj SFR Reset Value FFFFy 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Semiconductor Group 4 29 SIEMENS Interrupt and Trap Functions C167 5 Interrupt and Trap Functions The architecture of the C167 supports several mechanisms for fast and flexible response to service requests that can be generated from various sources internal or external to the microcontroller These mechanisms include Normal Interrupt Processing The CPU temporarily suspends the current program execution and branches to an interrupt service routine in order to service an interrupt requesting device The current program status IP PSW in segmentation mode also CSP is saved on the internal system stack A prioritization scheme with 16 priority levels allows the user to specify the order in which multiple interrupt requests are to be handled Interrupt Processing via the Peripheral Event Controller PEC A faster alternative to normal software controlled interrupt processing is servicing an interrupt request
305. le one machine cycle instruction allows to switch register banks from one task to another 4 Interruptable Multiple Cycle Instructions Reduced interrupt latency is provided by allowing multiple cycle instructions multiply divide to be interruptable With an interrupt response time within a range from just 250 ns to 500 ns in case of internal program execution the C167 is capable of reacting very fast on non deterministic events Its fast external interrupt inputs are sampled every 50 ns and allow to recognize even very short external signals The C167 also provides an excellent mechanism to identify and to process exceptions or error conditions that arise during run time so called Hardware Traps Hardware traps cause an immediate non maskable system reaction which is similiar to a standard interrupt service branching to a dedicated vector table location The occurrence of a hardware trap is additionally signified by an individual bit in the trap flag register TFR Except for another higher prioritized trap service being in progress a hardware trap will interrupt any current program execution In turn hardware trap services can normally not be interrupted by standard or PEC interrupts Software interrupts are supported by means of the TRAP instruction in combination with an individual trap interrupt number Semiconductor Group 2 6 SIEMENS Architectural Overview C167 2 2 The On chip System Resources The C167
306. legk2 Ine OP 1 6 Bi 2 Jo Qd Control Run i E Control v Match Output a C t omparator Control df MEE POUTx e Write Shadow Register Control MCB01948 Figure 15 2 PWM Channel Block Diagram 15 1 Operating Modes The PWM module provides four different operating modes Standard PWM generation edge aligned PWM available on all four channels Symmetrical PWM generation center aligned PWM available on all four channels Burst mode combines channels 0 and 1 Single shot mode available on channels 2 and 3 Note The output signals of the PWM module are XORed with the outputs of the respective port output latches After reset these latches are cleared so the PWM signals are directly driven to the port pins By setting the respective port output latch to 1 the PWM signal may be inverted XORed with 1 before being driven to the port pin The descriptions below refer to the standard case after reset ie direct driving Semiconductor Group 15 2 SIEMENS The Pulse Width Modulation Module C167 Mode 0 Standard PWM Generation Edge Aligned PWM Mode 0 is selected by clearing the respective bit PMx in register PWMCON to 0 In this mode the timer PTx of the respective PWM channel is always counting up until it reaches the value in the associated period shadow register Upon the next count pulse the timer is reset to 0000 and continues counting up with subsequent count pulses The PWM
307. low Boontr PHost PContr Fp 100 Fg 25 Note Function Fg does not consider the tolerances of oscillators and other devices supporting the serial communication This baudrate deviation is a nonlinear function depending on the CPU clock and the baudrate of the host The maxima of the function Fg increase with the host baudrate due to the smaller baudrate prescaler factors and the implied higher quantization error see figure below B nost MCA02260 Figure 13 3Baudrate deviation between host and C167 The minimum baudrate B oy in the figure above is determined by the maximum count capacity of timer T6 when measuring the zero byte ie it depends on the CPU clock Using the maximum T6 count 216 in the formula the minimum baudrate for fgpy 20 MHz is 687 Baud The lowest standard baudrate in this case would be 1200 Baud Baudrates below B ow would cause T6 to overflow In this case ASCO cannot be initialized properly The maximum baudrate Bj in the figure above is the highest baudrate where the deviation still does not exceed the limit ie all baudrates between B py and Byigh are below the deviation limit The maximum standard baudrate that fulfills this requirement is 19200 Baud Higher baudrates however may be used as long as the actual deviation does not exceed the limit A certain baudrate marked l in the figure may eg violate the deviation limit while an even higher baudrate marked II
308. lt S0BRS gt lt SOBRI gt 1 16 2 lt S0BRS gt Bays lt SOBRL gt represents the content of the reload register taken as unsigned 13 bit integer lt SOBRS gt represents the value of bit SOBRS ie 0 or 1 taken as integer The maximum baud rate that can be achieved for the asynchronous modes when using a CPU clock of 20 MHz is 625 KBaud The table below lists various commonly used baud rates together with the required reload values and the deviation errors compared to the intended baudrate Baud Rate SOBRS 0 fcpy 20 MHz SOBRS 1 fcpy 20 MHz Deviation Error Reload Value Deviation Error Reload Value 625 KBaud 0 0 0000 19 2 KBaud 1 7 1 4 001F 0020 3 3 1 4 00144 0015H 9600 Baud 0 2 1 4 00404 00414 1 0 1 4 002A 002B4 4800 Baud 0 2 0 6 0081 0082 1 0 0 2 0055 00564 2400 Baud 0 2 0 2 01034 0104 0 4 0 2 00AC4 00AD 1200 Baud 40 296 0 4 0207 02084 0 1 0 2 015A4 015By 600 Baud 40 196 0 096 04104 0411 0 1 0 1 02B54 02B6 75 Baud 1 7 1FFF 0 0 0 00 15B24 15B34 Note The deviation errors given in the table above are rounded Using a baudrate crystal resulting in a CPU clock of eg 18 432 MHz provides correct baudrates without deviation errors Synchronous Mode Baud Rates For synchronous operation the baud rate generator provides a cl
309. mable and can so be adjusted to the external circuitry Overrun error detection protection is provided for the conversion result register ADDAT either an interrupt request will be generated when the result of a previous conversion has not been read from the result register at the time the next conversion is complete or the next conversion is suspended in such a case until the previous result has been read For applications which require less than 16 analog input channels the remaining channel inputs can be used as digital input port pins The A D converter of the C167 supports four different conversion modes In the standard Single Channel conversion mode the analog level on a specified channel is sampled once and converted to a digital result In the Single Channel Continuous mode the analog level on a specified channel is repeatedly sampled and converted without software intervention In the Auto Scan mode the analog levels on a prespecified number of channels are sequentially sampled and converted In the Auto Scan Continuous mode the number of prespecified channels is repeatedly sampled and converted In addition the conversion of a specific channel can be inserted injected into a running sequence without disturbing this sequence This is called Channel Injection Mode The Peripheral Event Controller PEC may be used to automatically store the conversion results into a table in memory for later evaluation without requiring the overhea
310. mance systems it may be efficient to share external resources like memory banks or peripheral devices among more than one controller The C167 supports this approach with the possibility to arbitrate the access to its external bus ie to the external devices This bus arbitration allows an external master to request the C167 s bus via the HOLD input The C167 acknowledges this request via the HLDA output and will float its bus lines in this case The CS outputs provide internal pullup devices The new master may now access the peripheral devices or memory banks via the same interface lines as the C167 During this time the C167 can keep on executing as long as it does not need access to the external bus All actions that just require internal resources like instruction or data memory and on chip peripherals may be executed in parallel When the C167 needs access to its external bus while it is occupied by another bus master it demands it via the BREQ output The external bus arbitration is enabled by setting bit HLDEN in register PSW to 1 In this case the three bus arbitration pins HOLD HLDA and BREQ are automatically controlled by the EBC independent of their IO configuration Bit HLDEN may be cleared during the execution of program sequences where the external resources are required but cannot be shared with other bus masters In this case the C167 will not answer to HOLD requests from other external masters If HLDEN is cleared while t
311. message object is transmitted On reception of a data frame with matching identifier that message is stored in this message object DLC Data Length Code Valid values for the data length are 0 8 Note The first data byte occupies the upper half of the message configuration register Data Area The data area of message object n covers locations 00 EFn7 through 00 EFnE Location 00 EFnFy is reserved Message data for message object 15 last message will be written into a two message alternating buffer to avoid the loss of a message if a second message has been received before the CPU has read the first one Semiconductor Group 23 17 SIEMENS The On Chip CAN Interface C167 Initialization and Reset The on chip CAN Module is connected to the XBUS Reset signal XRESET This signal is activated when the C167 s reset input is activated when a software reset is executed and in case of a watchdog reset Activating the CAN Module s reset line triggers a hardware reset This hardware reset sets the CAN TxD output to 1 recessive clears the error counters resets the busoff state e switches the Control Register s low byte to 01 leaves the Control Register s high byte and the Interrupt Register undefined does not change the other registers including the message objects notified as UUUU Note The first hardware reset after power on leaves the unchanged registers in an undefined state of cou
312. mined by both the individual interrupt control registers and the PSW PEC services are controlled by the respective PECCx register and the source and destination pointers which specify the task of the respective PEC service channel Interrupt Control Registers All interrupt control registers are organized identically The lower 8 bits of an interrupt control register contain the complete interrupt status information of the associated source which is required during one round of prioritization the upper 8 bits of the respective register are reserved All interrupt control registers are bit addressable and all bits can be read or written via software This allows each interrupt source to be programmed or modified with just one instruction When accessing interrupt control registers through instructions which operate on word data types their upper 8 bits 15 8 will return zeros when read and will discard written data The layout of the Interrupt Control registers shown below applies to each xxIC register where xx stands for the mnemonic for the respective source Semiconductor Group 5 6 SIEMENS Interrupt and Trap Functions C167 XXIC yyyyp ZZ SFR area Reset Value 00 15 14 13 12 1 10 9 8 7 6 5 4 3 2 1i 0 Bit Function GLVL Group Level Defines the internal order for simultaneous requests of the same priority 3 Highest group priority 0 Lowest group priority ILVL Interrupt Priority Level Defines the p
313. mory or peripheral which cannot keep pace with the controller s maximum speed by introducing wait states during the access see figure above During these memory cycle time wait states the CPU is idle if this access is required for the execution of the current instruction The memory cycle time wait states can be programmed in increments of one CPU clock 50 ns at fcpu 20 MHz within a range from 0 to 15 default after reset via the MCTC fields of the BUSCON registers 15 lt MCTC gt waitstates will be inserted Semiconductor Group 8 12 SIEMENS The External Bus Interface C167 Programmable Memory Tri State Time The C167 allows the user to adjust the time between two subsequent external accesses to account for the tri state time of the external device The tri state time defines when the external device has released the bus after deactivation of the read command RD a Bus Cycle Segment X Address MTTC Wait State MCT02065 Figure 8 8 Memory Tri State Time The output of the next address on the external bus can be delayed for a memory or peripheral which needs more time to switch off its bus drivers by introducing a wait state after the previous bus cycle see figure above During this memory tri state time wait state the CPU is not idle so CPU operations will only be slowed down if a subsequent external instruction or data fetch operation is required during the next instruction cycl
314. ms a 32 bit or a 33 bit timer counter 32 bit Timer Counter If both a positive and a negative transition of TSOTL is used to clock the auxiliary timer this timer is clocked on every overflow underflow of the core timer T3 Thus the two timers form a 32 bit timer 33 bit Timer Counter If either a positive or a negative transition of TSOTL is selected to clock the auxiliary timer this timer is clocked on every second overflow underflow of the core timer T3 This configuration forms a 33 bit timer 16 bit core timer TSOTL 4 16 bit auxiliary timer The count directions of the two concatenated timers are not required to be the same This offers a wide variety of different configurations T3 can operate in timer dated timer or counter mode in this case Tyl CPU Clock x Fe Core Timer Ty m L DRE TyR Up Down TyOTL eHO TyOUT MCB02034 Edge Select x eas Auxiliary Timer Tx Delo t TxR Txl TSOUT P33 X22 y 3 Note Line only affected by over underflows of T3 but NOT by software modifications of T3OTL Figure 9 7 Concatenation of Core Timer T3 and an Auxiliary Timer Semiconductor Group 9 11 SIEMENS The General Purpose Timer Units C167 Auxiliary Timer in Reload Mode Reload mode for the auxiliary timers T2 and T4 is selected by setting bit field TxM in the respective register TXCON to 100g In reload mode the core timer T3 is reloaded with the contents of an auxiliary timer register trigg
315. n chip peripheral units before releasing the reset signal for the external peripherals of the system Note RSTOUT will float as long as pins POL O and POL 1 select emulation mode or adapt mode Watchdog Timer Operation after Reset The watchdog timer starts running after the internal reset has completed It will be clocked with the internal system clock divided by 2 10 MHz Q fc p j 20 MHz and its default reload value is 004 so a watchdog timer overflow will occur 131072 CPU clock cycles 6 55 ms fcpy 20 MHz after completion of the internal reset unless it is disabled serviced or reprogrammed meanwhile When the system reset was caused by a watchdog timer overflow the WDTR Watchdog Timer Reset Indication flag in register WDTCON will be set to 1 This indicates the cause of the internal reset to the software initialization routine WDTR is reset to 0 by an external hardware reset or by servicing the watchdog timer After the internal reset has completed the operation of the watchdog timer can be disabled by the DISWDT Disable Watchdog Timer instruction This instruction has been implemented as a protected instruction For further security its execution is only enabled in the time period after a reset until either the SRVWDT Service Watchdog Timer or the EINIT instruction has been executed Thereafter the DISWDT instruction will have no effect Reset Values for the C167 Registers During the reset sequence the registers of the C167
316. n control bit PTRx is set A timer is started PTRx 1 via software and is stopped PTRx 0 either via hardware or software depending on its operating mode Control bit PTRx enables or disables the clock input of counter PTx rather than controlling the PWM output signal Note For the register locations please refer to the table further below This table summarizes the PWM frequencies that result from various combinations of operating mode counter resolution input clock and pulse width resolution Input Clock and Mode 8 bit PWM 10 bit PWM 12 bit PWM 14 bit PWM 16 bit PWM Counter resolution resolution resolution resolution resolution resolution fepy Mode 0 78 13 KHz 19 53 KHz 4 88 KHz 1 22 KHz 305 Hz 50 ns fcpu 64 Mode 0 1 22 KHz 305 Hz 76 3 Hz 19 1 Hz 4 77 Hz 3 2 us fcpu Mode 1 39 1 KHz 9 77 KHz 2 44 KHz 610 Hz 152 6 Hz 50 ns fopy 64 Mode 1 610 Hz 152 6 Hz 38 15 Hz 9 54 Hz 2 4 Hz 3 2 us Semiconductor Group 15 7 SIEMENS The Pulse Width Modulation Module C167 Period Registers PPx The 16 bit period register PPx of a PWM channel determines the period of a PWM cycle ie the frequency of the PWM signal This register is buffered with a shadow register The shadow register is loaded from the respective PPx register at the beginning of every new PWM cycle or upon a write access to PPx while the timer is stopped The CPU accesses the PPx register while t
317. n data page 4 supposed segmentation is enabled e Explicit Stack Pointer Updating None of the RET RETI RETS RETP or POP instructions is capable of correctly using a new SP register value which is to be updated by an immediately preceding instruction Thus in order to use the new SP register value without erroneously performed stack accesses at least one instruction must be inserted between an explicitly SP writing and any subsequent of the just mentioned implicitly SP using instructions as shown in the following example ln MOV SP 0FA40H select a new top of stack lad AM must not be an instruction popping operands from the system stack Ini2 POP RO pop word value from new top of stack into RO Semiconductor Group 4 6 SIEMENS The Central Processing Unit CPU C167 e External Memory Access Sequences The effect described here will only become noticeable when watching the external memory access sequences on the external bus eg by means of a Logic Analyzer Different pipeline stages can simultaneously put a request on the External Bus Controller EBC The sequence of instructions processed by the CPU may diverge from the sequence of the corresponding external memory accesses performed by the EBC due to the predefined priority of external memory accesses ist Write Data 2nd Fetch Code 3rd Read Data Controlling Interrupts Software modifications implicit or explicit of the PSW are done in the execute phase
318. n the RD signal becomes active Figure 8 9 Read Write Delay The read write delay is controlled via the RWDCx bits in the BUSCON registers The command s will be delayed if bit RWDOx is 0 default after reset Semiconductor Group 8 14 SIEMENS The External Bus Interface C167 8 3 READY Controlled Bus Cycles For situations where the programmable waitstates are not enough or where the response access time of a peripheral is not constant the C167 provides external bus cycles that are terminated via a READY input signal synchronous or asynchronous In this case the C167 first inserts a programmable number of waitstates 0 7 and then monitors the READY line to determine the actual end of the current bus cycle The external device drives READY low in order to indicate that data have been latched write cycle or are available read cycle Bus Cycle Bus Cycle with active READY extended via READY 1 WS 2 WS 1 WS 2 WS ALE f RD WR VA VA SREADY WA 7 Mi ey MN A Evaluation sampling of the READY input MCT02237 Figure 8 10 READY Controlled Bus Cycles The READY function is enabled via the RDYENx bits in the BUSCON registers When this function is selected RDYENx 1 only the lower 3 bits of the respective MCTC bit field define the number of inserted waitstates 0 7 while the MSB of bit field MCTC selects the READY operation
319. nal access has been attempted with no external bus defined ILLINA Illegal Instruction Access Flag A branch to an odd address has been attempted ILLOPA Illegal Word Operand Access Flag A word operand access read or write to an odd address has been attempted PRTFLT Protection Fault Flag A protected instruction with an illegal format has been detected UNDOPC Undefined Opcode Flag The currently decoded instruction has no valid C167 opcode STKUF Stack Underflow Flag The current stack pointer value exceeds the content of register STKUN STKOF Stack Overflow Flag The current stack pointer value falls below the content of register STKOV NMI Non Maskable Interrupt Flag A negative transition falling edge has been detected on pin NMI Semiconductor Group 5 25 SIEMENS Interrupt and Trap Functions C167 Note The trap service routine must clear the respective trap flag otherwise a new trap will be requested after exiting the service routine Setting a trap request flag by software causes the same effects as if it had been set by hardware The reset functions hardware software watchdog may be regarded as a type of trap Reset functions have the highest system priority trap priority III Class A traps have the second highest priority trap priority II on the 3rd rank are class B traps so a class A trap can interrupt a class B trap If more than one class A trap occur at a time they are prioritized internally with the N
320. nate function of P5 12 Int t nee ron PIS PD TxOUT li TxOE MCB02029 Figure 9 14 Block Diagram of Core Timer T6 in Gated Timer Mode If TeM 0 O the timer is enabled when T6IN shows a low level A high level at this pin stops the timer If TeM 0z 1 pin T6IN must have a high level in order to enable the timer In addition the timer can be turned on or off by software using bit T6R The timer will only run if T6 R 1 and the gate is active It will stop if either T6R 0 or the gate is inactive Note A transition of the gate signal at pin T6IN does not cause an interrupt request Semiconductor Group 9 21 SIEMENS The General Purpose Timer Units C167 Timer 6 in Counter Mode Counter mode for the core timer T6 is selected by setting bit field T6M in register T6CON to 001p In counter mode timer T6 is clocked by a transition at the external input pin T6IN which is an alternate function of P5 12 The event causing an increment or decrement of the timer can be a positive a negative or both a positive and a negative transition at this pin Bit field T6l in control register T6CON selects the triggering transition see table below ien TxOTL ne TxOUT TxOE MCB02030 Figure 9 15 Block Diagram of Core Timer T6 in Counter Mode GPT2 Core Timer T6 Counter Mode Input Edge Selection T6l Triggering Edge for Counter Increment Decrement 000 None Counter T6 is disabled 001 Positive tr
321. ne 16 bit IO port Port 2 eight 8 bit IO ports PORTO made of POH and POL PORT1 made of P1H and P1L Port 4 Port 6 Port 7 Port 8 one 15 bit IO port Port 3 and one 16 bit input port Port 5 These port lines may be used for general purpose Input Output controlled via software or may be used implicitly by C167 s integrated peripherals or the External Bus Controller All port lines are bit addressable and all input output lines are individually bit wise programmable as inputs or outputs via direction registers except Port 5 of course The IO ports are true bidirectional ports which are switched to high impedance state when configured as inputs The output drivers of five IO ports 2 3 6 7 8 can be configured pin by pin for push pull operation or open drain operation via control registers The logic level of a pin is clocked into the input latch once per state time regardless whether the port is configured for input or output A write operation to a port pin configured as an input causes the value to be written into the port output latch while a read operation returns the latched state of the pin itself A read modify write operation reads the value of the pin modifies it and writes it back to the output latch Writing to a pin configured as an output DPx y 1 causes the output latch and the pin to have the written value since the output buffer is enabled Reading this pin returns the value of the output latch A read modify
322. ne Stage FETCH DECODE EXECUTE WRITEBACK PEC Response Time Figure 5 5 Pipeline Diagram for PEC Response Time In the figure above the respective interrupt request flag is set in cycle 1 fetching of instruction N The indicated source wins the prioritization round during cycle 2 In cycle 3 a PEC transfer instruction is injected into the decode stage of the pipeline suspending instruction N 1 and clearing the source s interrupt request flag to 0 Cycle 4 completes the injected PEC transfer and resumes the execution of instruction Nc 1 All instructions that entered the pipeline after setting of the interrupt request flag N 1 N 2 will be executed after the PEC data transfer Note When instruction N reads any of the PEC control registers PECC7 PECCO while a PEC request wins the current round of prioritization this round is repeated and the PEC data transfer is started one cycle later The minimum PEC response time is 3 states 150 ns O 20 MHz CPU clock This requires program execution from the internal ROM no external operand read requests and setting the interrupt request flag during the last state of an instruction cycle When the interrupt request flag is set during the first state of an instruction cycle the minimum PEC response time under these conditions is 4 state times 200 ns 20 MHz CPU clock Semiconductor Group 5 19 SIEMENS Interrupt and Trap Functions C167 The PEC resp
323. ne port these pairs must be separated by instructions which do not reference the respective port see Particular Pipeline Effects in chapter The Central Processing Unit Each of these ports and the alternate input and output functions are described in detail in the following subsections Semiconductor Group 6 4 SIEMENS Parallel Ports C167 6 1 PORTO The two 8 bit ports POH and POL represent the higher and lower part of PORTO respectively Both halfs of PORTO can be written eg via a PEC transfer without effecting the other half If this port is used for general purpose IO the direction of each line can be configured via the corresponding direction registers DPOH and DPOL POL FFOO 801 SFR Reset Value 00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 POL 7 POL 6 POL 5 POL 4 POL 3 POL 2 POL 1 POL O T a x a a POH FFO02 814 SFR Reset Value 00 9 8 7 6 5 4 3 2 1 0 s rw rw rw rw rw rw rw rw Bit Function POX y Port data register POH or POL bit y DPOL F100 801 ESFR Reset Value 00 f 6 5 4 3 2 1 0 PEE 7 6 5 4 3 2 1 0 DPOH F102 814 ESFR Reset Value 00 inu de cds der is dg 9 8 7 6 5 4 3 2 1 0 DPOH DPOH DPOH DPOH 7 6 A 0 s s 5 s rw rw rw rw rw rw rw rw Bit Function DPOX y Port direction register DPOH or DPOL bit y DPOX y 0 Port line POX y is an input high impedance DPOX y 1 Port line POX y is an output
324. nfigured for alternate data output ie P3 10 1 and DP3 10 1 Semiconductor Group 10 6 Sl EM ENS The Asynchronous Synchronous Serial Interface C167 Asynchronous reception is initiated by a falling edge 1 to 0 transition on pin RXDO provided that bits SOR and SOREN are set The receive data input pin RXDO is sampled at 16 times the rate of the selected baud rate A majority decision of the 7th 8th and 9th sample determines the effective bit value This avoids erroneous results that may be caused by noise If the detected value is not a 0 when the start bit is sampled the receive circuit is reset and waits for the next 1 to 0 transition at pin RXDO If the start bit proves valid the receive circuit continues sampling and shifts the incoming data frame into the receive shift register When the last stop bit has been received the content of the receive shift register is transferred to the receive data buffer register SORBUF Simultaneously the receive interrupt request flag SORIR is set after the 9th sample in the last stop bit time slot as programmed regardless whether valid stop bits have been received or not The receive circuit then waits for the next start bit 1 to 0 transition at the receive data input pin The receiver input pin RXDO P3 11 must be configured for input ie DP3 11 0 Asynchronous reception is stopped by clearing bit SOREN A currently received frame is completed including the generation of th
325. ng Each single instruction has to pass through each of the four pipeline stages regardless of whether all possible stage operations are really performed or not Since passing through one pipeline stage takes at least one machine cycle any isolated instruction takes at least four machine cycles to be completed Pipelining however allows parallel ie simultaneous processing of up to four instructions Thus most of the instructions seem to be processed during one machine cycle as soon as the pipeline has been filled once after reset see figure below Instruction pipelining increases the average instruction throughput considered over a certain period of time In the following any execution time specification of an instruction always refers to the average execution time due to pipelined parallel instruction processing Semiconductor Group 4 3 SIEMENS The Central Processing Unit CPU C167 DECODE EXECUTE WRITEBACK Figure 4 2 Sequential Instruction Pipelining Standard Branch Instruction Processing Instruction pipelining helps to speed sequential program processing In the case that a branch is taken the instruction which has already been fetched providently is mostly not the instruction which must be decoded next Thus at least one additional machine cycle is normally required to fetch the branch target instruction This extra machine cycle is provided by means of an injected instruction see figure below v Injection
326. ng coding based on the needs of each task Once the internal memory has been partitioned into a register bank space internal stack space and a global internal memory area each bank pointer is then assigned Thus upon entry into a new task the appropriate bank pointer is used as the operand for the SCXT switch context instruction Upon exit from a task a simple POP instruction to the context pointer CP restores the previous task s register bank 19 3 Procedure Call Entry and Exit To support modular programming a procedure mechanism is provided to allow coding of frequently used portions of code into subroutines The CALL and RET instructions store and restore the value of the instruction pointer IP on the system stack before and after a subroutine is executed Procedures may be called conditionally with instructions CALLA or CALLI or be called unconditionally using instructions CALLR or CALLS Note Any data pushed onto the system stack during execution of the subroutine must be popped before the RET instruction is executed Semiconductor Group 19 8 SIEMENS System Programming C167 Passing Parameters on the System Stack Parameters may be passed via the system stack through PUSH instructions before the subroutine is called and POP instructions during execution of the subroutine Base plus offset indirect addressing also permits access to parameters without popping these parameters from the stack during execution of the subro
327. ngle conversion or to 01 continuous conversion After starting the converter through bit ADST the busy flag ADBSY will be set and the channel specified in bit field ADCH will be converted After the conversion is complete the interrupt request flag ADCIR will be set In Single Conversion Mode the converter will automatically stop and reset bits ADBSY and ADST In Continuous Conversion Mode the converter will automatically start a new conversion of the channel specified in ADCH ADCIR will be set after each completed conversion When bit ADST is reset by software while a conversion is in progress the converter will complete the current conversion and then stop and reset bit ADBSY Auto Scan Conversion Modes These modes are selected by programming the mode selection field ADM in register ADCON to 10g single conversion or to 11g continuous conversion Auto Scan modes automatically convert a sequence of analog channels beginning with the channel specified in bit field ADCH and ending with channel 0 without requiring software to change the channel number After starting the converter through bit ADST the busy flag ADBSY will be set and the channel specified in bit field ADCH will be converted After the conversion is complete the interrupt request flag ADCIR will be set and the converter will automatically start a new conversion of the next lower channel ADCIR will be set after each completed conversion After conversion of cha
328. nit All standard arithmetic and logical operations are performed in a 16 bit ALU In addition for byte operations signals are provided from bits six and seven of the ALU result to correctly set the condition flags Multiple precision arithmetic is provided through a CARRY IN signal to the ALU from previously calculated portions of the desired operation Most internal execution blocks have been optimized to perform operations on either 8 bit or 16 bit quantities Once the pipeline has been filled one instruction is completed per machine cycle except for multiply and divide An advanced Booth algorithm has been incorporated to allow four bits to be multiplied and two bits to be divided per machine cycle Thus these operations use two coupled 16 bit registers MDL and MDH and require four and nine machine cycles respectively to perform a 16 bit by 16 bit or 32 bit by 16 bit calculation plus one machine cycle to setup and adjust the operands and the result Even these Semiconductor Group 2 3 SIEMENS Architectural Overview C167 longer multiply and divide instructions can be interrupted during their execution to allow for very fast interrupt response Instructions have also been provided to allow byte packing in memory while providing sign extension of bytes for word wide arithmetic operations The internal bus structure also allows transfers of bytes or words to or from peripherals based on the peripheral requirements A set of consisten
329. nnel 0 the current sequence is complete In Single Conversion Mode the converter will automatically stop and reset bits ADBSY and ADST In Continuous Conversion Mode the converter will automatically start a new sequence beginning with the conversion of the channel specified in ADCH When bit ADST is reset by software while a conversion is in progress the converter will complete the current sequence including conversion of channel 0 and then stop and reset bit ADBSY Conversion of Channel Write ADDAT ADDAT Full Generate Interrupt Request ADDAT Full Read of ADDAT Channnel 0 Result of Channel ax 3 42 41 Result Lost 3 Overrun Error Interrupt Request MCA02241 Figure 16 3 Auto Scan Conversion Mode Example Semiconductor Group 16 5 SIEMENS The Analog Digital Converter C167 Wait for ADDAT Read Mode If in default mode of the ADC a previous conversion result has not been read out of register ADDAT by the time a new conversion is complete the previous result in register ADDAT is lost because it is overwritten by the new value and the A D overrun error interrupt request flag ADEIR will be set In order to avoid error interrupts and the loss of conversion results especially when using continuous conversion modes the ADC can be switched to Wait for ADDAT Read Mode by setting bit ADWR in register ADCON If the value in ADDAT has not been read by the time the current conversion is complete the new res
330. nstructions in particular The general instruction timing is described including standard and exceptional timing While internal memory accesses are normally performed by the CPU itself external peripheral or memory accesses are performed by a particular on chip External Bus Controller EBC which is automatically invoked by the CPU whenever a code or data address refers to the external address space If possible the CPU continues operating while an external memory access is in progress If external data are required but are not yet available or if a new external memory access is requested by the CPU before a previous access has been completed the CPU will be held by the EBC until the request can be satisfied The EBC is described in a dedicated chapter Internal RAM amm STKUN Mul Div HW Instr Ptr Bit Mask Gen General Purpose D 4 Stage 16 bit Pipeline Registers Barrel Shifter SYSCON Context Ptr BUSCON 0 BUSCON 1 BUSCON 2 BUSCON 3 BUSCON 4 Data Page Ptr Code Seg Ptr MCB02147 Figure 4 1 CPU Block Diagram Semiconductor Group 4 1 SIEMENS The Central Processing Unit CPU C167 The on chip peripheral units of the C167 work nearly independent of the CPU with a separate clock generator Data and control information is interchanged between the CPU and these peripherals via Special Function Registers SFRs Whenever peripherals need a non deterministic CPU action an on chi
331. nter Mode 10 Gated Timer with Gate active low 1 Fs Gated Timer with Gate active high T5R Timer 5 Run Bit T5R 2 0 Timer Counter 5 stops T5R 1 Timer Counter 5 runs T5UD Timer 5 Up Down Control T5UDE Timer 5 External Up Down Enable Cl Register CAPREL Input Selection 00 Capture disabled 01 Positive transition rising edge on CAPIN 10 Negative transition falling edge on CAPIN Todos Any transition rising or falling edge on CAPIN T5CLR Timer 5 Clear Bit T5CLR 0 Timer 5 not cleared on a capture T5CLR 1 Timer 5 is cleared on a capture T5SC Timer 5 Capture Mode Enable T5SC 0 Capture into register CAPREL Disabled T5SC 1 Capture into register CAPREL Enabled For the effects of bits TXUD and TxUDE refer to the direction table see T6 section Semiconductor Group 9 23 SIEMENS The General Purpose Timer Units C167 Count Direction Control for Auxiliary Timer The count direction of the auxiliary timer can be controlled in the same way as for the core timer T6 The description and the table apply accordingly Timer T5 in Timer Mode or Gated Timer Mode When the auxiliary timer T5 is programmed to timer mode or gated timer mode its operation is the same as described for the core timer T6 The descriptions figures and tables apply accordingly with one exception There is no output toggle latch and no alternate output pin for T5 Semiconductor Gro
332. nternal CPU clock divided by a programmable prescaler while Counter Mode allows a timer to be clocked in reference to external events via TxIN Pulse width or duty cycle measurement is supported in Gated Timer Mode where the operation of a timer is controlled by the gate level on its external input pin TxIN The count direction up down for each timer is programmable by software or may additionally be altered dynamically by an external signal TxEUD to facilitate eg position tracking The core timers T3 and T6 have output toggle latches TxOTL which change their state on each timer over flow underflow The state of these latches may be output on port pins TXOUT or may be used internally to concatenate the core timers with the respective auxiliary timers resulting in 32 33 bit timers counters for measuring long time periods with high resolution Various reload or capture functions can be selected to reload timers or capture a timer s contents triggered by an external signal or a selectable transition of toggle latch TXOTL The maximum resolution of the timers in module GPT1 is 400 ns 20 MHz CPU clock With its maximum resolution of 200 ns 20 MHz CPU clock the GPT2 timers provide precise event control and time measurement Watchdog Timer The Watchdog Timer represents one of the fail safe mechanisms which have been implemented to prevent the controller from malfunctioning for longer periods of time The Watchdog Timer is alway
333. nterrupt level is updated by hardware upon entry into an interrupt service routine but it can also be modified via software to prevent other interrupts from being acknowledged In case an interrupt level 15 has been assigned to the CPU it has the highest possible priority and thus the current CPU operation cannot be interrupted except by hardware traps or external non maskable interrupts For details please refer to chapter Interrupt and Trap Functions After reset all interrupts are globally disabled and the lowest priority ILVL 0 is assigned to the initial CPU activity The Instruction Pointer IP This register determines the 16 bit intra segment address of the currently fetched instruction within the code segment selected by the CSP register The IP register is not mapped into the C167 s address space and thus it is not directly accessable by the programmer The IP can however be modified indirectly via the stack by means of a return instruction The IP register is implicitly updated by the CPU for branch instructions and after instruction fetch operations IP Reset Value 00004 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Function ip Specifies the intra segment offset from where the current instruction is to be fetched IP refers to the current segment lt SEGNR gt Semiconductor Group 4 17 SIEMENS The Central Processing Unit CPU C167 The Code Segment Pointer CSP This non bit addres
334. nto an interrupt service routine Then six additional stack word locations are required to push IP PSW and CSP for both the interrupt service routine and the hardware trap service routine More details about the stack overflow trap service routine and virtual stack management are given in chapter System Programming Semiconductor Group 4 25 SIEMENS The Central Processing Unit CPU C167 The Stack Underflow Pointer STKUN This non bit addressable register is compared against the SP register after each operation which pops data from the system stack eg POP and RET instructions and after each addition to the SP register If the content of the SP register is greater than the the content of the STKUN register a stack underflow hardware trap will occur Since the least significant bit of register STKUN is tied to 0 and bits 15 through 12 are tied to 1 by hardware the STKUN register can only contain values from FOOO to FFFEy STKUN FE16 0B SFR Reset Value FC00 15 14 11 10 9 8 7 6 5 4 3 2 1 0 13 12 r r r r rw r Bit Function stkun Modifiable portion of register STKUN Specifies the upper limit of the internal system stack The Stack Underflow Trap entered when SP gt STKUN may be used in two different ways Fatal error indication treats the stack underflow as a system error through the associated trap service routine Automatic system stack refilling allows to use the system stack as
335. ntral Processing Unit CPU C167 Whenever this register is updated via software the Multiply Divide Register In Use MDRIU flag in the Multiply Divide Control register MDC is set to 1 The MDRIU flag is cleared whenever the MDL register is read via software When a multiplication or division is interrupted before its completion and when a new multiply or divide operation is to be performed within the interrupt service routine register MDL must be saved along with registers MDH and MDC to avoid erroneous results A detailed description of how to use the MDL register for programming multiply and divide algorithms can be found in chapter System Programming The Multiply Divide Control Register MDC This bit addressable 16 bit register is implicitly used by the CPU when it performs a multiplication or a division It is used to store the required control information for the corresponding multiply or divide operation Register MDC is updated by hardware during each single cycle of a multiply or divide instruction MDC FFOE 87 SFR Reset Value 0000 15 14 11 1 13 12 o 9 8 7 6 5 4 Cube 2 d 0 W rw rw rw rw rw mw rw Bit Function MDRIU Multiply Divide Register In Use 0 Cleared when register MDL is read via software 1 Set when register MDL or MDH is written via software or when a multiply or divide instruction is executed gi Internal Machine Status The multiply divide unit
336. o locations 00 FA40 through 00 FA5F of the internal RAM So up to 16 instructions may be placed into the RAM area To execute the loaded code the BSL then jumps to location 00 FA40y ie the first loaded instruction The bootstrap loading sequence is now terminated the C167 remains in BSL mode however Most probably the initially loaded routine will load additional code or data as an average application is likely to require substantially more than 16 instructions This second receive loop may directly use the pre initialized interface ASCO to receive data and store it to arbitrary user defined locations This second level of loaded code may be the final application code It may also be another more sophisticated loader routine that adds a transmission protocol to enhance the integrity of the loaded code or data It may also contain a code sequence to change the system configuration and enable the bus interface to store the received data into external memory This process may go through several iterations or may directly execute the final application In all cases the C167 will still run in BSL mode ie with the watchdog timer disabled and limited access to the internal ROM area All code fetches from the internal ROM area 00 0000 00 7FFF or 01 00004 01 7FFFj if mapped to segment 1 are redirected to the special Boot ROM Data fetches access will access the internal ROM of the C167 if any is available but will return undefined data
337. ock the SFR area is located in the 512 Bytes above the internal RAM 00 FFFF 00 FE00 the second register block the Extended SFR ESFR area is located in the 512 Bytes below the internal RAM 00 F1FFy 00 FO00 Special function registers can be addressed via indirect and long 16 bit addressing modes Using an 8 bit offset together with an implicit base address allows to address word SFRs and their respective low bytes However this does not work for the respective high bytes Note Writing to any byte of an SFR causes the non addressed complementary byte to be cleared The upper half of each register block is bit addressable so the respective control status bits can directly be modified or checked using bit addressing When accessing registers in the ESFR area using 8 bit addresses or direct bit addressing an Extend Register EXTR instruction is required before to switch the short addressing mechanism from the standard SFR area to the Extended SFR area This is not required for 16 bit and indirect addresses The GPRs R15 RO are duplicated ie they are accessible within both register blocks via short 2 4 or 8 bit addresses without switching Example EXTR 4 Switch to ESFR area for the next 4 instructions MOV ODP2 data16 ODP2 uses 8 bit reg addressing BFLDL DP6 mask data8 Bit addressing for bit fields BSET DP1H 7 Bit addressing for single bits MOV T8REL R1 T8REL uses 16 bit address R1 is duplicated
338. ock with 4 times the rate of the established baud rate The baud rate for synchronous operation of serial channel ASCO can be determined by the following formula fcpu cPU SOBRL M 1 4 2 SOBRS lt SOBRL gt 1 4 2 SOBRS Bsync lt SOBRL gt represents the content of the reload register taken as unsigned 13 bit integers lt SOBRS gt represents the value of bit SOBRS ie 0 or 1 taken as integer The maximum baud rate that can be achieved in synchronous mode when using a CPU clock of 20 MHz is 2 5 MBaud Semiconductor Group 10 11 Sl EM ENS The Asynchronous Synchronous Serial Interface C167 10 5 ASCO Interrupt Control Four bit addressable interrupt control registers are provided for serial channel ASCO Register SOTIC controls the transmit interrupt SOTBIC controls the transmit buffer interrupt SORIC controls the receive interrupt and SOEIC controls the error interrupt of serial channel ASCO Each interrupt source also has its own dedicated interrupt vector SOTINT is the transmit interrupt vector SOTBINT is the transmit interrupt vector SORINT is the receive interrupt vector and SOEINT is the error interrupt vector The cause of an error interrupt request framing parity overrun error can be identified by the error status flags in control register SOCON Note In contrary to the error interrupt request flag SOEIR the
339. od This mode is required for double register compare mode for registers CCO CC7 and CC16 CC23 110 Compare Mode 2 Interrupt Only Only one interrupt per timer period 111 Compare Mode 3 Set Output Pin on each Match Reset output pin on each timer overflow Only one interrupt per timer period The detailed discussion of the capture and compare modes is valid for all the capture compare channels so registers bits and pins are only referenced by the placeholder x Note Capture compare channels 24 27 generate an interrupt request but do not provide an output signal The resulting exceptions are indicated in the following subsections A capture or compare event on channel 31 may be used to trigger a channel injection on the C167 s A D converter if enabled Semiconductor Group 14 11 SIEMENS The Capture Compare Units C167 14 4 Capture Mode In response to an external event the content of the associated timer TO T1 or T7 T8 depending on the used CAPCOM unit and the state of the allocation control bit ACCx is latched into the respective capture register CCx The external event causing a capture can be programmed to be either a positive a negative or both a positive or a negative transition at the respective external input pin CCxlO The triggering transition is selected by the mode bits CCMODx in the respective CAPCOM mode control register In any case the event causing a capture will also set the resp
340. of the control fields Semiconductor Group 14 20 SIEMENS The Capture Compare Units C167 CAPCOM Unit Interrupt Control Register Addresses CAPCOM Unit CAPCON 2 Unit Register Address Reg Space Register Address Reg Space CCOIC FF784 BCH SFR CC161C F160 BOH ESFR CC1IC FF7A BDy SFR CC171C F162 Bi1y ESFR CC2IC FF7Cy BEy SFR CC18IC F164 B2 ESFR CC3IC FF7E BFy SFR CC19IC F166 B3y ESFR CC4IC FF80 COH SFR CC20IC F168y B44 ESFR CC5IC FF82 C1y SFR CC211C F16A B54 ESFR CC6IC FF84 C24 SFR CC221C F16C B6 ESFR CC7IC FF86 C3 SFR CC23IC F16E B74 ESFR CC8IC FF88y C44 SFR CC24IC F170y B84 ESFR CC9IC FF8A C54 SFR CC25IC F172 B94 ESFR CC10IC FF8Cj C6 SFR CC26IC F174 BAY ESFR CC111C FF8E C74 SFR CC27IC F176 BBy ESFR CC121C FF90 C8y SFR CC28IC F1784 BCH ESFR CC13IC FF92 C9 SFR CC29IC F184 C2 ESFR CC14IC FF94 CAy SFR CC30IC F18C C64 ESFR CC151C FF96 CBH SFR CC311C F194 CA ESFR Semiconductor Group 14 21 SIEMENS The Pulse Width Modulation Module C167 15 The Pulse Width Modulation Module The Pulse Width Modulation PWM Module of the C167 allows the generation of up to 4 independent PWM signals The frequency range of these PWM signals for a 20 MHz CPU clock is from 4 8 Hz up to 10 MHz for edge aligned signals For center aligned signals the frequency range is 2 4 Hz up to
341. of the respective instructions In order to maintain fast interrupt responses however the current interrupt prioritization round does not consider these changes ie an interrupt request may be acknowledged after the instruction that disables interrupts via IEN or ILVL or after the following instructions Timecritical instruction sequences therefore should not begin directly after the instruction disabling interrupts as shown in the following example INT OFF BCLR IEN globally disable interrupts IN 4 hon critical instruction CRIT 1ST In begin of uninterruptable critical sequence CRIT LAST ly end of uninterruptable critical sequence INT ON BSET IEN globally re enable interrupts Note The described delay of 1 instruction also applies for enabling the interrupts system ie no interrupt requests are acknowledged until the instruction following the enabling instruction e Initialization of Port Pins Modifications of the direction of port pins input or output become effective only after the instruction following the modifying instruction As bit instructions BSET BCLR use internal read modify write sequences accessing the whole port instructions modifying the port direction should be followed by an instruction that does not access the same port see example below WRONG BSET DP3 13 change direction of P3 13 to output BSET P3 5 P3 13 is still input the rd mod wr reads pin P3 13 RIGHT BSET DP3 13 change direction of P
342. oftware into ROMless systems it may load temporary software into complete systems for testing or calibration it may also be used to load a programming routine for Flash devices The BSL mechanism may be used for standard system startup as well as only for special occasions like system maintenance firmware update or end of line programming or testing Semiconductor Group 13 1 SIEMENS The Bootstrap Loader C167 Entering the Bootstrap Loader The C167 enters BSL mode if pin POL 4 is sampled low at the end of a hardware reset In this case the built in bootstrap loader is activated independent of the selected bus mode The bootstrap loader code is stored in a special Boot ROM no part of the standard mask ROM or Flash memory area is required for this After entering BSL mode and the respective initialization the C167 scans the RXDO line to receive a zero byte ie one start bit eight 0 data bits and one stop bit From the duration of this zero byte it calculates the corresponding baudrate factor with respect to the current CPU clock initializes the serial interface ASCO accordingly and switches pin TxDO to output Using this baudrate an identification byte is returned to the host that provides the loaded data This identification byte identifies the device to be bootet The following codes are defined 8xC166 55u C165 B5 C167 C54 previous versions returned A5p When the C167 has entered BSL mode the following configura
343. onse time is increased by all delays of the instructions in the pipeline that are executed before starting the data transfer including N When internal hold conditions between instruction pairs N 2 N 1 or N 1 N occur the minimum PEC response time may be extended by 1 state time for each of these conditions When instruction N reads an operand from the internal ROM or when N is a call return trap or MOV Rn Rm data16 instruction the minimum PEC response time may additionally be extended by 2 state times during internal ROM program execution In case instruction N reads the PSW and instruction N 1 has an effect on the condition flags the PEC response time may additionally be extended by 2 state times The worst case PEC response time during internal ROM program execution adds to 9 state times 450 ns 20 MHz CPU clock Any reference to external locations increases the PEC response time due to pipeline related access priorities The following conditions have to be considered Instruction fetch from an external location Operand read from an external location Result write back to an external location Depending on where the instructions source and destination operands are located there are a number of combinations Note however that only access conflicts contribute to the delay A few examples illustrate these delays The worst case interrupt response time including external accesses will occur when instructions
344. ontribute to the high performance of the C167 the indicated timings refer to a CPU clock of 20 MHz High Performance 16 Bit CPU With Four Stage Pipeline 100 ns minimum instruction cycle time with most instructions executed in 1 cycle 500 ns multiplication 16 bit 16 bit 1 us division 32 bit 16 bit Multiple high bandwidth internal data buses Register based design with multiple variable register banks Single cycle context switching support 16 MBytes linear address space for code and data von Neumann architecture System stack cache support with automatic stack overflow underflow detection Control Oriented Instruction Set with High Efficiency Bit byte and word data types Flexible and efficient addressing modes for high code density Enhanced boolean bit manipulation with direct addressability of 6 Kbits for peripheral control and user defined flags Hardware traps to identify exception conditions during runtime HLL support for semaphore operations and efficient data access Integrated On chip Memory 2 KByte internal RAM for variables register banks system stack and code 2 KByte on chip high speed XRAM for variables user stack and code not on all derivatives Internal Mask ROM or Flash memory not for romless devices External Bus Interface Multiplexed or demultiplexed bus configurations Segmentation capability and chip select signal generation 8 bit or 16 bit data bus Bus cycle
345. or interrupt requests which are to be serviced by the PEC the associated PEC channel number is derived from the respective ILVL LSB and GLVL see figure below So programming a source to priority level 15 ILVL 1111p selects the PEC channel group 7 4 programming a source to priority level 14 ILVL21110pg selects the PEC channel group 3 0 The actual PEC channel number is then determined by the group priority field GLVL MCA02006 Figure 5 1 Priority Levels and PEC Channels Simultaneous requests for PEC channels are prioritized according to the PEC channel number where channel 0 has lowest and channel 8 has highest priority Note All sources that request PEC service must be programmed to different PEC channels Otherwise an incorrect PEC channel may be activated Semiconductor Group 5 8 Interrupt and Trap Functions C167 SIEMENS The table below shows in a few examples which action is executed with a given programming of an interrupt control register Priority Level Type of Service ILVL GLVL COUNT 00H COUNT 00 1111 11 CPU interrupt PEC service level 15 group priority 3 channel 7 1111 10 CPU interrupt PEC service level 15 group priority 2 channel 6 1110 10 CPU interrupt PEC service level 14 group priority 2 channel 2 1101 10 CPU interrupt CPU interrupt level 13 group priority 2 level 13 group priority 2 0001 11 CPU interrupt CPU interrupt level
346. or more of the following conditions are met Ifthe framing error detection enable bit SOFEN is set and any of the expected stop bits is not high the framing error flag SOFE is set indicating that the error interrupt request is due to a framing error Asynchronous mode only e If the parity error detection enable bit SOPEN is set in the modes where a parity bit is received and the parity check on the received data bits proves false the parity error flag SOPE is set indicating that the error interrupt request is due to a parity error Asynchronous mode only Ifthe overrun error detection enable bit SOOEN is set and the last character received was not read out of the receive buffer by software or PEC transfer at the time the reception of a new frame is complete the overrun error flag SOOE is set indicating that the error interrupt request is due to an overrun error Asynchronous and synchronous mode 10 4 ASCO Baud Rate Generation The serial channel ASCO has its own dedicated 13 bit baud rate generator with 13 bit reload capability allowing baud rate generation independent of the GPT timers The baud rate generator is clocked with the CPU clock divided by 2 10 MHz 20 MHz CPU clock The timer is counting downwards and can be started or stopped through the Baud Rate Generator Run Bit SOR in register SOCON Each underflow of the timer provides one clock pulse to the serial channel The timer is reloaded with the value stored in its 13
347. ort Data Movement Instructions Standard data movement of a word or byte Data movement of a byte to a word location with either sign or zero byte extension BFLDH BSET BCLR BMOV BMOVN BAND BOR BXOR BCMP BFLDL SHR SHL ROR ROL ASHR PRIOR MOV MOVB MOVBS MOVBZ Note The data movement instructions can be used with a big number of different addressing modes including indirect addressing and automatic pointer in decrementing System Stack Instructions Pushing of a word onto the system stack Popping of a word from the system stack Saving of a word on the system stack and then updating the old word with a new value provided for register bank switching Semiconductor Group 21 2 PUSH POP SCXT SIEMENS Instruction Set Summary C167 Jump Instructions Conditional jumping to an either absolutely indirectly or relatively addressed target instruction within the current code segment Unconditional jumping to an absolutely addressed target instruction within any code segment Conditional jumping to a relatively addressed target instruction within the current code segment depending on the state of a selectable bit Conditional jumping to a relatively addressed target instruction within the current code segment depending on the state of a selectable bit with a post inversion of the tested bit in case of jump taken semaphore support Call Instructions Conditional calling of
348. orts C167 6 7 Port6 If this 8 bit port is used for general purpose IO the direction of each line can be configured via the corresponding direction register DP6 Each port line can be switched into push pull or open drain mode via the open drain control register ODP6 P6 FFCC E64 SFR Reset Value 00 zen 14 18 12 11 19 9 8 7 6 5 4 3 2 1 0 E rw rw rw rw rw rw rw rw Bit Function P6 y Port data register P6 bit y DP6 FFCE E74 SFR Reset Value 00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mde ee epee ee eae ae ae QUT E Bit Function DP6 y Port direction register DP6 bit y DP6 y 0 Port line P6 y is an input high impedance DP6 y 1 Port line P6 y is an output ODP6 F1CE E7 ESFR Reset Value 00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ODP6 ODP6 ODP6 ODP6 ODP6 ODP6 ODP6 ODP6 7 6 5 4 3 2 1 0 Sarre ms a m s m ODP6 y Port 6 Open Drain control register bit y ODP6 y 0 Port line P6 y output driver in push pull mode ODP6 y 1 Port line P6 y output driver in open drain mode Bit Function Semiconductor Group 6 25 Parallel Ports C167 SIEMENS Alternate Functions of Port 6 A programmable number of chip select signals CS4 CS0 derived from the bus control registers BUSCONA BUSCONO can be output on 5 pins of Port 6 The other 3 pins may be used for bus arbitration to accomodate additional masters in a C167
349. ose Timer Units C167 Count Direction Control for Auxiliary Timers The count direction of the auxiliary timers can be controlled in the same way as for the core timer T3 The description and the table apply accordingly Timers T2 and T4 in Timer Mode or Gated Timer Mode When the auxiliary timers T2 and T4 are programmed to timer mode or gated timer mode their operation is the same as described for the core timer T3 The descriptions figures and tables apply accordingly with one exception There is no output toggle latch and no alternate output pin for T2 and T4 Semiconductor Group 9 9 SIEMENS The General Purpose Timer Units C167 Timers T2 and T4 in Counter Mode Counter mode for the auxiliary timers T2 and T4 is selected by setting bit field TxM in the respective register TXCON to 001g In counter mode timers T2 and T4 can be clocked either by a transition at the respective external input pin TxIN or by a transition of timer T3 s output toggle latch T3OTL Edge Select DX Auxiliary Timer Tx dani X224 MCB02221 Figure 9 6 Block Diagram of an Auxiliary Timer in Counter Mode The event causing an increment or decrement of a timer can be a positive a negative or both a positive and a negative transition at either the respective input pin or at the toggle latch T3OTL Bit field Txl in the respective control register TxCON selects the triggering transition see table below GPT1 Auxiliary Timer Counter
350. outine could have interrupted a previous routine which contained a MUL or DIV instruction Register MDC is also saved because it is possible that a previous routine s Multiply or Divide instruction was interrupted while in progress In this case the information about how to restart the instruction is contained in this register Register MDC must be cleared to be correctly initialized for a subsequent multiplication or division The old MDC contents must be popped from the stack before the RETI instruction is executed For a division the user must first move the dividend into the MD register If a 16 16 bit division is specified only the low portion of register MD must be loaded The result is also stored into register MD The low portion MDL contains the integer result of the division while the high portion MDH contains the remainder Semiconductor Group 19 2 SIEMENS System Programming C167 The following instruction sequence performs a 32 by 16 bit division MOV MDH R1 Move dividend to MD register Sets MDRIU MOV MDL R2 Move low portion to MD DIV R3 Divide 32 16 signed R3 holds the divisor JMPR cc V ERROR Testfor divide overflow MOV R3 MDH Move remainder to R3 MOV R4 MDL Move integer result to R4 Clears MDRIU Whenever a multiply or divide instruction is interrupted while in progress the address of the interrupted instruction is pushed onto the stack and the MULIP flag in the PSW of the interrupting routine is set W
351. output signal is switched to high level when the timer contents are equal to or greater than the contents of the pulse width shadow register The signal is switched back to low level when the respective timer is reset to 0000 y ie below the pulse width shadow register The period of the resulting PWM signal is determined by the value of the respective PPx shadow register plus 1 counted in units of the timer resolution PWM_Perioduodeo PPX 1 The duty cycle of the PWM output signal is controlled by the value in the respective pulse width shadow register This mechanism allows the selection of duty cycles from 0 to 100 including the boundaries For a value of 0000 the output will remain at a high level representing a duty cycle of 100 For a value higher than the value in the period register the output will remain at a low level which corresponds to a duty cycle of 0 The figure below illustrates the operation and output waveforms of a PWM channel in mode 0 for different values in the pulse width register This mode is referred to as Edge Aligned PWM because the value in the pulse width shadow register only effects the positive edge of the output signal The negative edge is always fixed and related to the clearing of the timer PTx Count alue Duty Cycle PWx Pulse Width 0 PWx 1 PWx 2 PWx 4 E PWx 6 PWx 7 PWx 8 0 MCA01949 LSR Latch Shadow Register Interrupt Request Figure 15
352. ow summarizes the alternate functions of Port 5 Port 5 Pin Alternate Function a Alternate Function b P5 0 Analog Input ANO P5 1 Analog Input AN1 P5 2 Analog Input AN2 P5 3 Analog Input AN3 P5 4 Analog Input AN4 P5 5 Analog Input AN5 P5 6 Analog Input AN6 P5 7 Analog Input AN7 P5 8 Analog Input AN8 P5 9 Analog Input AN9 P5 10 Analog Input AN10 T6EUD Timer 6 ext Up Down Input P5 11 Analog Input AN11 T5EUD Timer 5 ext Up Down Input P5 12 Analog Input AN12 T6IN Timer 6 Count Input P5 13 Analog Input AN13 T5IN Timer 5 Count Input P5 14 Analog Input AN14 T4EUD Timer 4 ext Up Down Input P5 15 Analog Input AN15 T2EUD Timer 2 ext Up Down Input Semiconductor Group 6 23 SIEMENS Parallel Ports C167 Alternate Function P5 15 P5 14 P5 13 P5 12 P5 11 P5 10 P5 9 P5 8 P5 7 P5 6 P5 5 P5 4 P5 3 P5 2 P5 1 P5 0 General Purpose A D Converter Input Input Figure 6 15Port 5 IO and Alternate Functions Port 5 pins have a special port structure see figure below first because it is an input only port and second because the analog input channels are directly connected to the pins rather than to the input latches Channel Select to Sample Hold Circuit Read Port P5 y Clock 4 Y Input Read Latch Buffer 02550 2525 oo UJ MCB02076 Figure 6 16 Block Diagram of a Port 5 Pin Semiconductor Group 6 24 SIEMENS Parallel P
353. p 10 8 Sl EM ENS The Asynchronous Synchronous Serial Interface C167 Synchronous transmission begins within 4 state times after data has been loaded into SOTBUF provided that SOR is set and SOREN O half duplex no reception Data transmission is double buffered When the transmitter is idle the transmit data loaded into SOTBUF is immediately moved to the transmit shift register thus freeing SOTBUF for the next data to be sent This is indicated by the transmit buffer interrupt request flag SOTBIR being set SOTBUF may now be loaded with the next data while transmission of the previous one is still going on The data bits are transmitted synchronous with the shift clock After the bit time for the 8th data bit both pins TXDO and RXDO will go high the transmit interrupt request flag SOTIR is set and serial data transmission stops Pin TXDO P3 10 must be configured for alternate data output ie P3 102 1 and DP3 10 1 in order to provide the shift clock Pin RXDO P3 11 must also be configured for output P3 112 1 and DP3 11 1 during transmission Synchronous reception is initiated by setting bit SOREN 1 If bit SOR 1 the data applied at pin RXDO are clocked into the receive shift register synchronous to the clock which is output at pin TXDO After the 8th bit has been shifted in the content of the receive shift register is transferred to the receive data buffer SORBUF the receive interrupt request flag SORIR is set the r
354. p Interrupt Controller compares all pending peripheral service requests against each other and prioritizes one of them If the priority of the current CPU operation is lower than the priority of the selected peripheral request an interrupt will occur Basically there are two types of interrupt processing Standard interrupt processing forces the CPU to save the current program status and the return address on the stack before branching to the interrupt vector jump table PEC interrupt processing steals just one machine cycle from the current CPU activity to perform a single data transfer via the on chip Peripheral Event Controller PEC System errors detected during program execution socalled hardware traps or an external non maskable interrupt are also processed as standard interrupts with a very high priority In contrast to other on chip peripherals there is a closer conjunction between the watchdog timer and the CPU If enabled the watchdog timer expects to be serviced by the CPU within a programmable period of time otherwise it will reset the chip Thus the watchdog timer is able to prevent the CPU from going totally astray when executing erroneous code After reset the watchdog timer starts counting automatically but it can be disabled via software if desired Beside its normal operation there are the following particular CPU states Reset state Any reset hardware software watchdog forces the CPU into a predefined ac
355. pace for 1 4 instructions so the additional registers can be accessed this way too The EXTPR and EXTSR instructions combine the DPP override mechanism with the redirection to the ESFR space using a single instruction Note Instructions EXTR EXTPR and EXTSR inhibit interrupts the same way as ATOMIC The switching to the ESFR area and data page overriding is checked by the development tools or handled automatically Nested Locked Sequences Each of the described extension instruction and the ATOMIC instruction starts an internal extension counter counting the effected instructions When another extension or ATOMIC instruction is contained in the current locked sequence this counter is restarted with the value of the new instruction This allows the construction of locked sequences longer than 4 instructions Note Interrupt latencies may be increased when using locked code sequences PEC requests are not serviced during idle mode if the IDLE instruction is part of a locked sequence Semiconductor Group 19 13 SIEMENS System Programming C167 19 10 Handling the Internal ROM The Mask ROM or Flash versions of the C167 may provide and control a 32 KByte internal ROM area that may store code as well as data Access to this internal ROM area is controlled during the reset configuration and via software The ROM area may be mapped to segment 0 to segment 1 or may be disabled at all Note The internal ROM area always occupi
356. packages For simplicity all these various versions are referred to by the term C167 throughout this manual The complete pro electron comform designations are listed in the respective data sheets Semiconductor Group 1 1 SIEMENS Introduction C167 1 1 The Members of the 16 bit Microcontroller Family The microcontrollers of the Siemens 16 bit family have been designed to meet the high performance requirements of real time embedded control applications The architecture of this family has been optimized for high instruction throughput and minimum response time to external stimuli interrupts Intelligent peripheral subsystems have been integrated to reduce the need for CPU intervention to a minimum extent This also minimizes the need for communication via the external bus interface The high flexibility of this architecture allows to serve the diverse and varying needs of different application areas such as automotive industrial control or data communications The core of the 16 bit family has been developped with a modular family concept in mind All family members execute an efficient control optimized instruction set additional instructions for members of the second generation This allows an easy and quick implementation of new family members with different internal memory sizes and technologies different sets of on chip peripherals and or different numbers of IO pins The XBUS concept opens a straight forward path for the integra
357. pecified by the contents of the CP register ie the base of the current register bank Depending on whether a relative word Rw or byte Rb GPR address is specified the short 4 bit GPR address is either multiplied by two or not before it is added to the content of register CP see figure below Thus both byte and word GPR accesses are possible in this way GPRs used as indirect address pointers are always accessed wordwise For some instructions only the first four GPRs can be used as indirect address pointers These GPRs are specified via short 2 bit GPR addresses The respective physical address calculation is identical to that for the short 4 bit GPR addresses Short 8 Bit Register Addresses mnemonic reg or bitoff within a range from FO to FFy interpret the four least significant bits as short 4 bit GPR address while the four most significant bits are ignored The respective physical GPR address calculation is identical to that for the short 4 bit GPR addresses For single bit accesses on a GPR the GPR s word address is calculated as just described but the position of the bit within the word is specified by a separate additional 4 bit value Semiconductor Group 4 23 SIEMENS The Central Processing Unit CPU C167 Specified by reg or bitoff Z D Context 1111 4 Bit GPR Pointer 7 Address7 Internal RAM Must be within the GP internal Lats LA RAM area For byte GPR For word GPR accesses accesses MCA02005
358. pen drain mode for each port line If the respective control bit ODPx y is 0 default after reset the output driver is in the push pull mode If ODPx y is 1 the open drain configuration is selected Note that all ODPx registers are located in the ESFR space External Pullup 1 l Push Pull Output Driver Open Drain Output Driver MCA01975 Figure 6 2 Output Drivers in Push Pull Mode and in Open Drain Mode Input Threshold Control The standard inputs of the C167 determine the status of input signals according to TTL levels In order to accept and recognize noisy signals CMOS like input thresholds can be selected instead of the standard TTL thresholds for all pins of Port 2 Port 3 Port 7 and Port 8 These special thresholds are defined above the TTL thresholds and feature a defined hysteresis to prevent the inputs from toggling while the respective input signal level is near the thresholds The Port Input Control register PICON allows to select these thresholds for each byte of the indicated ports ie the 8 bit ports P7 and P8 are controlled by one bit each while ports P2 and P3 are controlled by two bits each Semiconductor Group 6 2 SIEMENS Parallel Ports C167 PICON F1C4 E24 ESFR Reset Value 004 Bit Function PxLIN Port x Low Byte Input Level Selection 0 Pins Px 7 Px 0 switch on standard TTL input levels 1 Pins Px 7 Px 0 switch on special threshold input levels
359. pends on the bus type which was selected during reset When any of the external bus modes was selected during reset PORTO and PORT 1 will operate in the selected bus mode Port 4 will output the selected number of segment address lines all zero after reset and Port 6 will drive the selected number of CS lines CSO will be 0 while the other active CS lines will be 1 When no memory accesses above 64 K are to be performed segmentation may be disabled When the on chip bootstrap loader was activated during reset pin TxDO alternate function of P3 10 will be switched to output mode after the reception of the zero byte All other pins remain in the high impedance state until they are changed by software or peripheral operation Semiconductor Group 17 5 SIEMENS System Reset C167 Application Specific Initialization Routine After the internal reset condition is removed the C167 fetches the first instruction from location 00 0000 which is the first vector in the trap interrupt vector table the reset vector 4 words locations 00 0000 through 000007 are provided in this table to start the initialization after reset As a rule this location holds a branch instruction to the actual initialization routine that may be located anywhere in the address space Note When the Bootstrap Loader Mode was activated during a hardware reset the C167 does not fetch instructions from location 00 0000 but rather expects data via ser
360. peripheral on the XBUS X Peripheral there is a separate address window controlled by an XBCON and an XADRS register As an interface to a peripheral in many cases is represented by just a few registers the XADRS registers select smaller address windows than the standard ADDRSEL registers As the register pairs control integrated peripherals rather than externally connected ones they are fixed by mask programming rather than being user programmable X Peripheral accesses provide the same choices as external accesses so these peripherals may be bytewide or wordwide with or without a separate address bus Interrupt nodes and configuration pins on PORTO are provided for X Peripherals to be integrated Note If you plan to develop a peripheral of your own to be integrated into a C167 device to create a customer specific version please ask for the specification of the XBUS interface and for further support Semiconductor Group 8 29 SIEMENS The General Purpose Timer Units C167 9 The General Purpose Timer Units The General Purpose Timer Units GPT1 and GPT2 represent very flexible multifunctional timer structures which may be used for timing event counting pulse width measurement pulse generation frequency multiplication and other purposes They incorporate five 16 bit timers that are grouped into the two timer blocks GPT1 and GPT2 Block GPT1 contains 3 timers counters with a maximum resolution of 400 ns 20 MHz CPU clock while
361. pins of Port 4 to interface to a bus transceiver The CAN module combines several functional blocks see figure below that work in parallel and contribute to the controller s performance These units and the functions they provide are described below Each of the message objects has a unique identifier and its own set of control and status bits Each object can be configured with its direction as either transmit or receive except the last message which is only a double receive buffer with a special mask register An object with its direction set as transmit can be configured to be automatically sent whenever a remote frame with a matching identifier taking into account the respective global mask register is received over the CAN bus By requesting the transmission of a message with the direction set as receive a remote frame can be sent to request that the appropriate object be sent by some other node Each object has separate transmit and receive interrupts and status bits giving the CPU full flexibility in detecting when a remote data frame has been sent or received For general purpose two masks for acceptance filtering can be programmed one for identifiers of 11 bits and one for identifiers of 29 bits However the CPU must configure bit XTD Normal or Extended Frame Identifier for each valid message to determine whether a standard or extended frame will be accepted The last message object has its own programmable mask for acceptance fil
362. ps and the corresponding status flags in register TFR It also lists the priorities of trap service for cases where more than one trap condition might be detected within the same instruction After any reset hardware reset software reset instruction SRST or reset by watchdog timer overflow program execution starts at the reset vector at location 00 0000 Reset conditions have priority over every other system activity and therefore have the highest priority trap priority III Software traps may be initiated to any vector location between 00 0000 and 00 01F Cy A service routine entered via a software TRAP instruction is always executed on the current CPU priority level which is indicated in bit field ILVL in register PSW This means that routines entered via the software TRAP instruction can be interrupted by all hardware traps or higher level interrupt requests Exception Condition Trap Trap Vector Trap Trap Flag Vector Location Number Priority Reset Functions Hardware Reset RESET 00 0000 004 li Software Reset RESET 00 0000 00H IH Watchdog Timer Over RESET 00 0000 004 Hl flow Class A Hardware Traps Non Maskable Interrupt NMI NMITRAP 00 00084 024 Stack Overflow STKOF STOTRAP 00 0010 044 I Stack Underflow STKUF STUTRAP 00 0018 064 I Class B Hardware Traps Undefined Opcode UNDOPC BTRAP 000028 OAH Protected Instruction PRTFLT BTRAP 00 0028 OAH Fault Illegal Word Operand ILL
363. pt request flag T5IR or T6IR in register TxIC will be set Whenever a transition according to the selection in bit field CI is detected at pin CAPIN interrupt request flag CRIR in register CRIC is set Setting any request flag will cause an interrupt to the respective timer or CAPREL interrupt vector T5INT T6INT or CRINT or trigger a PEC service if the respective interrupt enable bit T5IE or T6IE in register TxIC CRIE in register CRIC is set There is an interrupt control register for each of the two timers and for the CAPREL register T5IC FF66 B3 SFR Reset Value 00 fe ee EL AULEM M 7 6 1 0 7 x s x gt rw rw rw T6IC FF68 B4p SFR Reset Value 00 7 6 1 0 z ny rw rw CRIC FF6A B5 SFR Reset Value 00 7 15 14 13 12 11 10 9 8 6 CRIR CRIE ILVL GLVL rw Note Please refer to the general Interrupt Control Register description for an explanation of the control fields Semiconductor Group 9 31 Sl EM ENS The Asynchronous Synchronous Serial Interface C167 10 The Asynchronous Synchronous Serial Interface The Asynchronous Synchronous Serial Interface ASCO provides serial communication between the C167 and other microcontrollers microprocessors or external peripherals The ASCO supports full duplex asynchronous communication up to 625 KBaud and half duplex synchronous communication up to 2 5 MBaud 20 MHz CPU clock In synchronous mode data are transmitted or re
364. pt requests are generated by the peripherals based on specific events which occur during their operation eg operation complete error etc For interfacing with external hardware specific pins of the parallel ports are used when an input or output function has been selected for a peripheral During this time the port pins are controlled by the peripheral when used as outputs or by the external hardware which controls the peripheral when used as inputs This is called the alternate input or output function of a port pin in contrast to its function as a general purpose IO pin Peripheral Timing Internal operation of CPU and peripherals is based on the CPU clock fcpj The on chip oscillator derives the CPU clock from the crystal or from the external clock signal The clock signal which is gated to the peripherals is independent from the clock signal which feeds the CPU During Idle mode the CPU s clock is stopped while the peripherals continue their operation Peripheral SFRs may be accessed by the CPU once per state When an SFR is written to by software in the same state where it is also to be modified by the peripheral the software write operation has priority Further details on peripheral timing are included in the specific sections about each peripheral Semiconductor Group 2 11 SIEMENS Architectural Overview C167 Programming Hints Access to SFRs All SFRs reside in data page 3 of the memory space The following addre
365. pull mode ODP6 x 0 This feature is implemented to drive the chip select lines high during reset in order to avoid multiple chip selection and to allow another master to access the external memory via the same chip select lines Wired AND while the C167 is in Hold mode With ODP6 x 1 open drain output selected the internal pullup device will not be active during Hold mode external pullup devices must be used in this case When entering Hold mode the CS lines are actively driven high for one clock phase then the output level is controlled by the pullup devices if activated After reset the CS function must be used if selected so In this case there is no possibility to program any port latches before Thus the alternate function CS is selected automatically in this case Note The open drain output option can only be selected via software earliest during the initialization routine at least signal CS0 will be in push pull output driver mode directly after reset Semiconductor Group 6 27 SIEMENS Parallel Ports C167 Write ODP6 y Open Drain l MUX Read E 0 gt 0 Write DP6 y ul 447 b 1 Direct MUX Irection Read DP6 y Alternate Y Function 9 lt Enable Write P6 y Alternate i Port Output Output Latch Buffer Read P6 y y 0 4 6 7 MCB01982 I n t e r n a UJ c 7 Figure 6 18 Block Diagram of Por
366. quests from timer Ty and in interrupt requests from register CCx which occur at the time specified by the user through cv1 and cv2 Contents of Ty FFF Fy Compare Value cv2 Compare Value cv Reload Value lt TyREL gt 00004 Interrupt Requests TylR CCxIR CCxIR TyIR CCxIR CCxIR TyIR t Event 1 Event 2 Event 45 Event 4 CCx cv2 CCx cv1 CCx cv2 CCx cv1 MCT02017 Output pin CCxIO only effected in mode 1 No changes in mode 0 X Te 5 y 5 5 5 Figure 14 7 Timing Example for Compare Modes 0 and 1 Semiconductor Group 14 14 SIEMENS The Capture Compare Units C167 Compare Mode 1 Compare mode 1 is selected for register CCx by setting bit field CCMODx of the corresponding mode control register to 101p When a match between the content of the allocated timer and the compare value in register CCx is detected in this mode interrupt request flag COxIR is set to 1 and in addition the corresponding output pin CCxlO alternate port output function is toggled For this purpose the state of the respective port output latch not the pin is read inverted and then written back to the output latch Compare mode 1 allows several compare events within a single timer period An overflow of the allocated timer has no effect on the output pin nor does it disable or enable further compare events In order to use the respective port pin as compare signal output pin CCxlO for compare register CCx
367. r When instructions N N 1 and N 2 are executed out of external memory and the interrupt vector also points to an external location but all operands for instructions N 3 through N are in internal memory then the interrupt response time is the time to perform 3 word bus accesses When the above example has the interrupt vector pointing into the internal ROM the interrupt response time is 1 word bus access plus 4 states After an interrupt service routine has been terminated by executing the RETI instruction and if further interrupts are pending the next interrupt service routine will not be entered until at least two instruction cycles have been executed of the program that was interrupted In most cases two instructions will be executed during this time Only one instruction will typically be executed if the first instruction following the RETI instruction is a branch instruction without cache hit or if it reads an operand from internal ROM or if it is executed out of the internal RAM Note A bus access in this context also includes delays caused by an external READY signal or by bus arbitration HOLD mode Semiconductor Group 5 18 SIEMENS Interrupt and Trap Functions C167 PEC Response Times The PEC response time defines the time from an interrupt request flag of an enabled interrupt source being set until the PEC data transfer being started The basic PEC response time for the C167 is 2 instruction cycles Pipeli
368. r T4CON GPT1 Timer 4 Control Register GPT1 Timer 4 Interrupt Control Register Figure 9 1 SFRs and Port Pins Associated with Timer Block GPT1 Semiconductor Group 9 1 SIEMENS The General Purpose Timer Units C167 All three timers of block GPT1 T2 T3 T4 can run in 3 basic modes which are timer gated timer and counter mode and all timers can either count up or down Each timer has an alternate input function pin on Port 3 associated with it which serves as the gate control in gated timer mode or as the count input in counter mode The count direction Up Down may be programmed via software or may be dynamically altered by a signal at an external control input pin Each overflow underflow of core timer T3 may be indicated on an alternate output function pin The auxiliary timers T2 and T4 may additionally be concatenated with the core timer or used as capture or reload registers for the core timer The current contents of each timer can be read or modified by the CPU by accessing the corresponding timer registers T2 T3 or T4 which are located in the non bitaddressable SFR space When any of the timer registers is written to by the CPU in the state immediately before a timer increment decrement reload or capture is to be performed the CPU write operation has priority in order to guarantee correct results r2euo y o GPT1 Timer T2 Tert Request CPU Clock 075 715 T2 T2I
369. r the respective accesses do not generate valid external bus cycles Due to timing constraints address and write data of an XBUS cycle are reflected on the external bus interface see table below The address mentioned above includes PORT1 Port 4 BHE and ALE which also pulses for an XBUS cycle The external CS signals on Port 6 are driven inactive high because the EBC switches to an internal XCS signal The external control signals RD and WR or WRL WRH if enabled remain inactive high Status of the external bus interface during EBC idle state Pins Internal accesses only XBUS accesses PORTO Tristated floating Tristated floating for read accesses XBUS write data for write accesses PORT1 Last used external address Last used XBUS address if used for the bus interface if used for the bus interface Port 4 Last used external segment address Last used XBUS segment address on selected pins on selected pins Port 6 Active external CS signal Inactive high for selected CS signals corresponding to last used address BHE Level corresponding to last external Level corresponding to last XBUS access access ALE Inactive low Pulses as defined for X Peripheral RD Inactive high Inactive high WR WRL Inactive high Inactive high WRH Inactive high Inactive high Semiconductor Group 8 24 SIEMENS The External Bus Interface C167 8 6 External Bus Arbitration In high perfor
370. r Group Siemens AG is an approved CECC manufacturer Packing Please use the recycling operators known to you We can also help you get in touch with your nearest sales office By agreement we will take packing material back if it is sorted You must bear the costs of transport For packing material that is returned to us unsorted or which we are not obliged to accept we shall have to invoice you for any costs in curred Components used in life support devices or systems must be expressly authorized for such purpose Critical components of the Semiconductor Group of Siemens AG may only be used in life support devices or systems with the express written approval of the Semiconductor Group of Siemens AG 1 Acritical component is a component used in a life support device or system whose failure can reasonably be expected to cause the failure of that life support device or system or to affect its safety or effectiveness of that device or system 2 Life support devices or systems are intended a to be implanted in the human body or b to support and or maintain and sustain hu man life If they fail it is reasonable to assume that the health of the user may be endangered SIEMENS d Table of Contents Page 1 Introduction dox OE ore tee ats Reem ROUEN DUE Siete eee Re E 1 1 1 1 The Members of the 16 bit Microcontroller Family 1 2 1 2 Summary of Basic Features 0000 cece eee eee 1 4 1 3 ADDreVIatoNS
371. r Underflow Reload Reg TyREL MCB02143 Figure 14 2 CAPCOM Unit Block Diagram Note The CAPCOM2 unit provides 16 capture inputs but only 12 compare outputs Semiconductor Group 14 3 SIEMENS The Capture Compare Units C167 14 4 The CAPCOM Timers The primary use of the timers TO T1 and T7 T8 is to provide two independent time bases 400 ns maximum resolution 20 MHz CPU clock for the capture compare registers of each unit but they may also be used independent of the capture compare registers The basic structure of the four timers is identical while the selection of input signals is different for timers TO T7 and timers T1 T8 see figures below Reload Reg TxREL Txl Input Clock ZEN GPT2 Timer T6 A Interrupt Over Underflow Edge gt MUX fer CAPCOM Timer Tx Request Control Select n TxR T C Txi TxM Txl MCB02013 x 0 7 Figure 14 3 Block Diagram of CAPCOM Timers TO and T7 Reload Reg TxREL Txl CPU Clock gt 2x Interrupt GPT2 Timer T6 Request Over Underflow MCB02014 x 1 8 Figure 14 4 Block Diagram of CAPCOM Timers T1 and T8 Semiconductor Group 14 4 SIEMENS The Capture Compare Units C167 Note When an external input signal is connected to the input lines of both TO and T7 these timers count the input signal synchronously Thus the two timers can be regarded as one timer whose contents can be compared with 32 capture registers
372. r holds the selection for the number of chip selects and segment addresses Software can read this register in order to react according to the selected configuration if required When the reset is terminated the internal pullup devices are switched off and PORTO will be switched to the appropriate operating mode During external accesses in multiplexed bus modes PORTO first outputs the 16 bit intra segment address as an alternate output function PORTO is then switched to high impedance input mode to read the incoming instruction or data In 8 bit data bus mode two memory cycles are required for word accesses the first for the low byte and the second for the high byte of the word During write cycles PORTO outputs the data byte or word after outputting the address During external accesses in demultiplexed bus modes PORTO reads the incoming instruction or data word or outputs the data byte or word Alternate Function a POH 7 POH 6 POH 5 POH 4 POH 3 POH 2 POH 1 POH O POL 7 POL 6 POL 5 POL 4 POL 3 POL 2 POL 1 POL O General Purpose 8 bit Input Output Demux Bus Demux Bus Figure 6 4 PORTO IO and Alternate Functions Semiconductor Group 6 6 SIEMENS Parallel Ports C167 When an external bus mode is enabled the direction of the port pin and the loading of data into the port output latch are controlled by the bus controller hardware The input of the port output latch is disconnected from the internal b
373. r underflows This is the standard reload mode reload on overflow underflow e If either a positive or a negative transition of T3OTL is selected to trigger a reload the core timer will be reloaded with the contents of the auxiliary timer on every second overflow or underflow Semiconductor Group 9 12 SIEMENS The General Purpose Timer Units C167 Using this single transition mode for both auxiliary timers allows to perform very flexible pulse width modulation PWM One of the auxiliary timers is programmed to reload the core timer on a positive transition of TSOTL the other is programmed for a reload on a negative transition of T3OTL With this combination the core timer is alternately reloaded from the two auxiliary timers The figure below shows an example for the generation of a PWM signal using the alternate reload mechanism T2 defines the high time of the PWM signal reloaded on positive transitions and T4 defines the low time of the PWM signal reloaded on negative transitions The PWM signal can be output on T3OUT with T3OE 1 P3 32 1 and DP3 3 1 With this method the high and low time of the PWM signal can be varied in a wide range Note The output toggle latch T3OTL is accessible via software and may be changed if required to modify the PWM signal However this will NOT trigger the reloading of T3 Reload Register T2 ES Interrupt T2IR Request TOE Interrupt Request i T30UT Core Timer T3
374. ration which requires 2 bytes of storage and the minimum time for execution NOP Definition of an unseparable instruction sequence ATOMIC Switch reg bitoff and bitaddr addressing modes to the Extended SFR space EXTR Override the DPP addressing scheme using a specific data page instead of the DPPs and optionally switch to ESFR space EXTP EXTPR Override the DPP addressing scheme using a specific segment instead of the DPPs and optionally switch to ESFR space EXTS EXTSR Note The ATOMIC and EXT instructions provide support for uninterruptable code sequences eg for semaphore operations They also support data addressing beyond the limits of the current DPPs except ATOMIC which is advantageous for bigger memory models in high level languages Refer to chapter System Programming for examples Protected Instructions Some instructions of the C167 which are critical for the functionality of the controller are implemented as so called Protected Instructions These protected instructions use the maximum instruction format of 32 bits for decoding while the regular instructions only use a part of it eg the lower 8 bits with the other bits providing additional information like involved registers Decoding all 32 bits of a protected doubleword instruction increases the security in cases of data distortion during instruction fetching Critical operations like a software reset are therefore only executed if the complete
375. re used by the interrupting program must eventually be saved and restored eg the DPPs and the registers of the MUL DIV unit Semiconductor Group 5 16 SIEMENS Interrupt and Trap Functions C167 5 5 Interrupt Response Times The interrupt response time defines the time from an interrupt request flag of an enabled interrupt source being set until the first instruction 11 being fetched from the interrupt vector location The basic interrupt response time for the C167 is 3 instruction cycles Pipeline Stage FETCH DECODE EXECUTE WRITEBACK Interrupt Response Time Figure 5 4 Pipeline Diagram for Interrupt Response Time All instructions in the pipeline including instruction N during which the interrupt request flag is set are completed before entering the service routine The actual execution time for these instructions eg waitstates therefore influences the interrupt response time In the figure above the respective interrupt request flag is set in cycle 1 fetching of instruction N The indicated source wins the prioritization round during cycle 2 In cycle 3 a TRAP instruction is injected into the decode stage of the pipeline replacing instruction N 1 and clearing the source s interrupt request flag to 0 Cycle 4 completes the injected TRAP instruction save PSW IP and CSP if segmented mode and fetches the first instruction 11 from the respective vector location All instructions t
376. red by popping it from the stack and then the number of used local registers must be added to the SP to restore the allocated local space back to the system stack Note The system stack is growing downwards while the register bank is growing upwards Old Stack Area Allocated Register Bank pM pl Figure 19 2 Local Registers The software to provide the local register bank for the example above is very compact After entering the subroutine SUB SP 40D Free 5 words in the current system stack SCXT CP SP Set the new register bank pointer Before exiting the subroutine POP CP Restore the old register bank ADD SP 10D Release the 5 word of the current system stack Semiconductor Group 19 10 SIEMENS System Programming C167 19 4 Table Searching A number of features have been included to decrease the execution time required to search tables First branch delays are eliminated by the branch target cache after the first iteration of the loop Second in non sequentially searched tables the enhanced performance of the ALU allows more complicated hash algorithms to be processed to obtain better table distribution For sequentially searched tables the auto increment indirect addressing mode and the E end of table flag stored in the PSW decrease the number of overhead instructions executed in the loop The two examples below illustrate searching ordered tables and non ordered tables respectively MOV RO
377. resets the peripheral hardware which might be the cause for the malfunction When the watchdog timer is enabled and the software has been designed to service it regularly before it overflows the watchdog timer will supervise the program execution as it only will overflow if the program does not progress properly The watchdog timer will also time out if a software error was due to hardware related failures This prevents the controller from malfunctioning for longer than a user specified time The watchdog timer provides two registers a read only timer register that contains the current count and a control register for initialization Reset Indication Pin Data Registers Control Registers OQ so WETCON Figure 12 1 SFRs and Port Pins associated with the Watchdog Timer The watchdog timer is a 16 bit up counter which can be clocked with the CPU clock fe pj either divided by 2 or divided by 128 This 16 bit timer is realized as two concatenated 8 bit timers see figure below The upper 8 bits of the watchdog timer can be preset to a user programmable value via a watchdog service access in order to vary the watchdog expire time The lower 8 bits are reset on each service access fud MUX WDT Low Byte WDT High Byte WDTR il RSTOUT T JA WDTIN WDT Control WDTREL MCB02052 Reset Figure 12 2 Watchdog Timer Block Diagram Semiconductor Group 12 1 SIEMENS The Watchdog Timer WDT 80C166 Operation of the Watchdog T
378. riority level for the arbitration of requests Fu Highest priority level Op Lowest priority level xxlE Interrupt Enable Control Bit individually enables disables a specific source 0 Interrupt request is disabled 1 Interrupt Request is enabled xxIR Interrupt Request Flag 0 No request pending 1 This source has raised an interrupt request The Interrupt Request Flag is set by hardware whenever a service request from the respective source occurs It is cleared automatically upon entry into the interrupt service routine or upon a PEC service In the case of PEC service the Interrupt Request flag remains set if the COUNT field in register PECCx of the selected PEC channel decrements to zero This allows a normal CPU interrupt to respond to a completed PEC block transfer Note Modifying the Interrupt Request flag via software causes the same effects as if it had been set or cleared by hardware Interrupt Priority Level and Group Level The four bits of bit field ILVL specify the priority level of a service request for the arbitration of simultaneous requests The priority increases with the numerical value of ILVL so 0000p is the lowest and 1111 is the highest priority level When more than one interrupt request on a specific level gets active at the same time the values in the respective bit fields GLVL are used for second level arbitration to select one request for being serviced Again the group pr
379. river in open drain mode Semiconductor Group 6 11 SIEMENS Parallel Ports C167 Alternate Functions of Port 2 All Port 2 lines P2 15 P2 0 serve as capture inputs or compare outputs CC151O CC0lO for the CAPCOM unit When a Port 2 line is used as a capture input the state of the input latch which represents the state of the port pin is directed to the CAPCOM unit via the line Alternate Pin Data Input If an external capture trigger signal is used the direction of the respective pin must be set to input If the direction is set to output the state of the port output latch will be read since the pin represents the state of the output latch This can be used to trigger a capture event through software by setting or clearing the port latch Note that in the output configuration no external device may drive the pin otherwise conflicts would occur When a Port 2 line is used as a compare output compare modes 1 and 3 the compare event or the timer overflow in compare mode 3 directly effects the port output latch In compare mode 1 when a valid compare match occurs the state of the port output latch is read by the CAPCOM control hardware via the line Alternate Latch Data Input inverted and written back to the latch via the line Alternate Data Output The port output latch is clocked by the signal Compare Trigger which is generated by the CAPCOM unit In compare mode 3 when a match occurs the value 1 is written
380. ro a standard interrupt is performed to the vector location related to the corresponding source PEC services are very well suited for example to move register contents to from a memory table The C167 has 8 PEC channels each of which offers such fast interrupt driven data transfer capabilities Memory Areas The memory space of the C167 is configured in a Von Neumann architecture which means that code memory data memory registers and IO ports are organized within the same linear address space which covers up to 16 MBytes The entire memory space can be accessed bytewise or wordwise Particular portions of the on chip memory have additionally been made directly bit addressable A 2 KByte 16 bit wide internal RAM provides fast access to General Purpose Registers GPRs user data variables and system stack The internal RAM may also be used for code A unique decoding scheme provides flexible user register banks in the internal memory while optimizing the remaining RAM for user data The CPU disposes of an actual register context consisting of up to 16 wordwide and or bytewide GPRs which are physically located within the on chip RAM area A Context Pointer CP register determines the base address of the active register bank to be accessed by the CPU at a time The number of register banks is only restricted by the available internal RAM space For easy parameter passing a register bank may overlap others A system stack of up to 1024 words
381. rse The value 01 in the Control Register s low byte prepares for software initialization Software Initialization The Software Initialization is enabled by setting bit INIT in the Control Register This can be done by the CPU via software or automatically by the CAN controller on a hardware reset or if the EML switches to busoff state While INIT is set all message transfer from and to the CAN bus is stopped the CAN bus output CAN TxD is 1 recessive the control bits NEWDAT and RMTPND of the last message object are reset e the counters of the EML are left unchanged Setting bit CCE in addition allows changing the configuration in the Bit Timing Register To initialize the CAN Controller the following actions are required configure the Bit Timing Register CCE required set the Global Mask Registers initialize each message object If a message object is not needed it is sufficient to clear its message valid bit MSGVAL ie to define it as not valid Otherwise the whole message object has to be initialized After the initialization sequence has been completed the CPU clears the INIT bit To change the configuration of a message object during normal operation the CPU first clears bit MSQGVAL which defines it as not valid When the configuration is completed MSGVAL is set again Semiconductor Group 23 18 SIEMENS The On Chip CAN Interface C167 Accessing the On chip CAN Module The CAN Module
382. rsion time is programmable so the ADC can be adjusted to the internal resistances of the analog sources and or the analog reference voltage supply Conversion Interrupt Control Requests ANO P5 0 16 Result Reg ADDAT Analog 10 Bit Input Converter Channels Result Reg ADDAT2 MCB02240 Figure 16 2 Analog Digital Converter Block Diagram Semiconductor Group 16 2 SIEMENS The Analog Digital Converter C167 16 1 Mode Selection and Operation The analog input channels ANO AN15 are alternate functions of Port 5 which is a 16 bit input only port The Port 5 lines may either be used as analog or digital inputs No special action is required to configure the Port 5 lines as analog inputs The functions of the A D converter are controlled by the bit addressable A D Converter Control Register ADCON Its bit fields specify the analog channel to be acted upon the conversion mode and also reflect the status of the converter ADCON FFAO D0j SFR Reset Value 0000 1 14 11 3 2 1 0 5 13 12 10 9 8 7 6 5 4 AD AD AD rw rw rw rw rw r rw rw rw Bit Function ADCH ADC Analog Channel Input Selection ADM ADC Mode Selection 00 Fixed Channel Single Conversion 01 Fixed Channel Continuous Conversion 10 Auto Scan Single Conversion 11 Auto Scan Continuous Conversion ADST ADC Start Bit ADBSY ADC Busy Flag ADBSY 1 A conversion is active ADWR ADC Wait for Read Control ADCIN ADC Channel
383. s In the demultiplexed bus modes the 16 bit intra segment address is permanently output on PORT1 while the data uses PORTO 16 bit data or POL 8 bit data The upper address lines are permanently output on Port 4 if selected via SALSEL during reset No address latches are required The EBC initiates an external access by placing an address on the address bus After a programmable period of time the EBC activates the respective command signal RD WR WRL WRH Data is driven onto the data bus either by the EBC for write cycles or by the external memory peripheral for read cycles After a period of time which is determined by the access time of the memory peripheral data become valid Read cycles Input data is latched and the command signal is now deactivated This causes the accessed device to remove its data from the data bus which is then tri stated again Write cycles The command signal is now deactivated If a subsequent external bus cycle is required the EBC places the respective address on the address bus The data remain valid on the bus until the next external bus cycle is started E2 Bus Cycle sonet e DX ies TX ee ALE MCT02061 Figure 8 3 Demultiplexed Bus Cycle Semiconductor Group 8 4 SIEMENS The External Bus Interface C167 Switching between the Bus Modes The EBC allows to switch between different bus modes dynamically ie s
384. s and fast external interrupts These interrupt functions are alternate port functions except for the non maskable interrupt and the reset input Semiconductor Group 5 1 SIEMENS Interrupt and Trap Functions C167 5 1 Interrupt System Structure The C167 provides 56 separate interrupt nodes that may be assigned to 16 priority levels In order to support modular and consistent software design techniques each source of an interrupt or PEC request is supplied with a separate interrupt control register and interrupt vector The control register contains the interrupt request flag the interrupt enable bit and the interrupt priority of the associated source Each source request is activated by one specific event depending on the selected operating mode of the respective device The only exceptions are the two serial channels of the C167 where an error interrupt request can be generated by different kinds of error However specific status flags which identify the type of error are implemented in the serial channels control registers The C167 provides a vectored interrupt system In this system specific vector locations in the memory space are reserved for the reset trap and interrupt service functions Whenever a request occurs the CPU branches to the location that is associated with the respective interrupt source This allows direct identification of the source that caused the request The only exceptions are the class B hardware traps w
385. s enabled after a reset of the chip and can only be disabled in the time interval until the EINIT end of initialization instruction has been executed Thus the chip s start up procedure is always monitored The software has to be designed to service the Watchdog Timer before it overflows If due to hardware or software related failures the software fails to do so the Watchdog Timer overflows and generates an internal hardware reset and pulls the RSTOUT pin low in order to allow external hardware components to reset The Watchdog Timer is a 16 bit timer clocked with the CPU clock divided either by 2 or by 128 The high byte of the Watchdog Timer register can be set to a prespecified reload value stored in WDTREL in order to allow further variation of the monitored time interval Each time it is serviced by the application software the high byte of the Watchdog Timer is reloaded Thus time intervals between 25 us and 420 ms can be monitored 20 MHz The default Watchdog Timer interval after reset is 6 55 ms 20 MHz Semiconductor Group 2 14 SIEMENS Architectural Overview C167 Capture Compare CAPCOM Units The two CAPCOM units support generation and control of timing sequences on up to 32 channels with a maximum resolution of 400 ns The CAPCOM units are typically used to handle high speed IO tasks such as pulse and waveform generation pulse width modulation PWM Digital to Analog D A conversion software timing or time r
386. s for double register compare mode is listed in the table below Register Pairs for Double Register Compare Mode CAPCOM Unit CAPCON Unit Register Pair Associated Register Pair Associated Bank 1 Bank 2 Output Pin Bank 1 Bank 2 Output Pin CCO CC8 CCOIO CC16 CC24 CC16IO CC1 CC9 CC1IO CC17 CC25 CC171O CC2 CC10 CC2lO CC18 CC26 CC18IO CC3 CC11 CC3IO CC19 CC27 CC19IO CC4 CC12 CC4IO CC20 CC28 CC20IO CC5 CC13 CC5IO CC21 CC29 CC211O CC6 CC14 CC6lO CC22 CC30 CC2210 CC7 CC15 CC7IO CC23 CC31 CC23lO The double register compare mode can be programmed individually for each register pair In order to enable double register mode the respective bank 1 register see table must be programmed to compare mode 1 and the corresponding bank 2 register see table must be programmed to compare mode 0 If the respective bank 1 compare register is disabled or programmed for a mode other than mode 1 the corresponding bank 2 register will operate in compare mode 0 interrupt only mode In the following a bank 2 register programmed to compare mode 0 will be referred to as CCz while the corresponding bank 1 register programmed to compare mode 1 will be referred to as CCx When a match is detected for one of the two registers in a register pair CCx or CCz the associated interrupt request flag CCxIR or CCzIR is set to 1 and pin CCxlO corresponding to bank 1 register CCx is toggled The generated interr
387. s map shown below lists the registers which are part of the CAN controller There are also C167 specific registers that are associated with the CAN Module These registers however control the access to the CAN Module rather than its function Semiconductor Group 23 4 SIEMENS The On Chip CAN Interface C167 EF00 7 zz General Registers Control Status Register Message Object 1 Message Object 2 Interrupt i Register Message Object 3 Message Object 4 Bil zig Register Message Object 5 Message Object 6 Global Mask Short Message Object 7 Message Object 8 Message Object 9 Global Mask L Message Object 10 is Message Object 11 Message Object 12 Message Object 13 Mask of A Last Message Message Object 14 Message Object 15 CAN Address Area General Registers MCB02572 Figure 23 2 CAN Module Address Map Semiconductor Group 23 5 SIEMENS The On Chip CAN Interface C167 Control Status Register EF00 j XReg Reset Value XX01 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 wef oo m me r r r rw rw rw rw rw r r rw rw rw rw Bit Function Control Bits INIT Initialization Starts the initialization of the CAN controller when set IE Interrupt Enable Enables or disables interrupt generation from the CAN Module via the signal XINTR Does not affect status updates SIE Status Change Interrupt Enable Enables or disables interrupt generation when a message transfer recept
388. s reached 5V 10 even if there is no external clock signal in this case the PLL will run on its basic frequency of 2 5 MHz The PLL starts synchronizing with the external clock signal as soon as it is available Within ca 1 ms after stable oscillations of the external clock within the specified frequency range the PLL will be synchronous with this clock at a frequency of F fosc ie the PLL locks to the external clock Note If the C167 is required to operate on the desired CPU clock directly after reset make sure that RSTIN remains active until the PLL has locked ca 1 ms When PLL operation is selected the CPU clock is a selectable multiple of the oscillator frequency ie the input frequency The table below lists the possible selections P0 15 13 CPU External Clock Input Notes POH 7 5 Frequency fcpu Range fxraL F 1 1 1 faa 4 2 5 to 6 25 MHz Default configuration 1 1 0 fan 3 3 33 to 8 33 MHz 1 0 1 foc 5 to 12 5 MHz 1 0 0 faa 5 2 to 5 MHz 0 X X Tet 4 1 to 25 MHz Direct drive 2 1 The external clock input range refers to a CPU clock range of 10 25 MHz 2 The maximum depends on the duty cycle of the external clock signal In emulation mode direct drive is selected with P0 15 POH 7 1 The PLL constantly synchronizes to the external clock signal Due to the fact that the external frequency is 1 F th of the PLL output frequency the output frequency may be slightly higher or lower th
389. s the advantages of both RISC and CISC processors in a very well balanced way The sum of the features which are combined result in a high performance microcontroller which is the right choice not only for today s applications but also for future engineering challenges The C167 not only integrates a powerful CPU core and a set of peripheral units into one chip but also connects the units in a very efficient way One of the four buses used concurrently on the C167 is the XBUS an internal representation of the external bus interface This bus provides a standardized method of integrating application specific peripherals to produce derivates of the standard C167 XRAM CAN L Figure 2 1 C167 Functional Block Diagram Semiconductor Group 2 1 SIEMENS Architectural Overview C167 2 4 Basic CPU Concepts and Optimizations The main core of the CPU consists of a 4 stage instruction pipeline a 16 bit arithmetic and logic unit ALU and dedicated SFRs Additional hardware is provided for a separate multiply and divide unit a bit mask generator and a barrel shifter SP STKOV ETK N Exec Unit Mul Div HW Instr Ptr Bit Mask Gen it Instr Reg 4 Stage 16 bit Pipeline Barrel Shifter PSW SYSCON Context Ptr BUSCON 0 BUSCON 1 BUSCON 2 BUSCON 3 BUSCON 4 Data Page Ptr 4 Code Seg Ptr Figure 2 2 CPU Block Diagram General Purpose Registers Internal RAM MCB02147
390. sable register selects the code segment being used at run time to access instructions The lower 8 bits of register CSP select one of up to 256 segments of 64 Kbytes each while the upper 8 bits are reserved for future use CSP FEO08 044 SFR Reset Value 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Function SEGNR Segment Number Specifies the code segment from where the current instruction is to be fetched SEGNR is ignored when segmentation is disabled Code memory addresses are generated by directly extending the 16 bit contents of the IP register by the contents of the CSP register as shown in the figure below In case of the segmented memory mode the selected number of segment address bits 7 0 3 0 or 1 0 of register CSP is output on the segment address pins A23 A19 A17 A16 of Port 4 for all external code accesses For non segmented memory mode or Single Chip Mode the content of this register is not significant because all code acccesses are automatically restricted to segment 0 Note The CSP register can only be read but not written by data operations It is however modified either directly by means of the JMPS and CALLS instructions or indirectly via the stack by means of the RETS and RETI instructions Upon the acceptance of an interrupt or the execution of a software TRAP instruction the CSP register is automatically set to zero Semiconductor Group 4 18 SIEMENS The Central Processing Unit CPU
391. se some of them even bitwise Reading bytes from word SFRs is a non critical operation However when writing bytes to word SFRs the complementary byte of the respective SFR is cleared with the write operation Semiconductor Group 20 19 SIEMENS Instruction Set Summary C167 21 Instruction Set Summary This chapter briefly summarizes the C167 s instructions ordered by instruction classes This provides a basic understanding of the C167 s instruction set the power and versatility of the instructions and their general usage A detailed description of each single instruction including its operand data type condition flag settings addressing modes length number of bytes and object code format is provided in the Instruction Set Manual for the C16x Family This manual also provides tables ordering the instructions according to various criteria to allow quick references Summary of Instruction Classes Grouping the various instruction into classes aids in identifying similar instructions eg SHR ROR and variations of certain instructions eg ADD ADDB This provides an easy access to the possibilities and the power of the instructions of the C167 Note The used mnemonics refer to the detailled description Arithmetic Instructions Addition of two words or bytes ADD ADDB Addition with Carry of two words or bytes ADDC ADDCB Subtraction of two words or bytes SUB SUBB Subtraction with Carry of two words or bytes S
392. se refer to the general Interrupt Control Register description for an explanation of the control fields AR Semiconductor Group 14 8 SIEMENS The Capture Compare Units C167 14 3 Capture Compare Registers The 16 bit capture compare registers CCO through CC31 are used as data registers for capture or compare operations with respect to timers TO T1 and T7 T8 The capture compare registers are not bitaddressable Each of the registers CC0 CC31 may be individually programmed for capture mode or one of 4 different compare modes except for CC24 CC27 and may be allocated individually to one of the two timers of the respective CAPCOM unit TO or T1 and T7 or T8 respectively A special combination of compare modes additionally allows the implementation of a double register compare mode When capture or compare operation is disabled for one of the CCx registers it may be used for general purpose variable storage The functions of the 32 capture compare registers are controlled by 8 bitaddressable 16 bit mode control registers named CCMO CCM7 which are all organized identically see description below Each register contains bits for mode selection and timer allocation of four capture compare registers Capture Compare Mode Registers for the CAPCOM1 Unit CCO CC15 CCMO TH m SFR Reset Value n 14 rw CCM1 pia s SFR Reset Value ee 14 rw CCM2 ag eee SFR Reset Value uH 14 rw CCM3 vehi Mp SFR Reset Value an
393. sed to cause an interrupt to vector ADEINT or it may trigger a PEC data transfer ADCIC FF98j CCy SFR Reset Value 004 e SA pM rode ceu Se ee 80 9 wo IW rw rw ADEIC FF9A CDy SFR Reset Value 004 7 Note Please refer to the general Interrupt Control Register description for an explanation of the control fields Semiconductor Group 16 11 SIEMENS System Reset C167 17 System Reset The internal system reset function provides initialization of the C167 into a defined default state and is invoked either by asserting a hardware reset signal on pin RSTIN Hardware Reset Input upon the execution of the SRST instruction Software Reset or by an overflow of the watchdog timer Whenever one of these conditions occurs the microcontroller is reset into its predefined default state through an internal reset procedure When a reset is initiated pending internal hold states are cancelled and the current internal access cycle if any is completed An external bus cycle is aborted except for a watchdog reset see description After that the bus pin drivers and the IO pin drivers are switched off tristate RSTOUT is activated depending on the reset source The internal reset procedure requires 516 CPU clock cycles 25 8 us 20 MHz CPU clock in order to perform a complete reset sequence This 516 cycle reset sequence is started upon a watchdog timer overflow a SRST instruction or when the reset input
394. sequence has been completed the RSTIN input is sampled When the reset input signal is active at that time the internal reset condition is prolonged until RSTIN gets inactive During a hardware reset the PORTO inputs for the reset configuration need some time to settle on the required levels especially if the hardware reset aborts a read operation form an external peripheral During this settling time the configuration may intermittently be wrong In such a case also the PLL clock selection may be wrong It is therefore strongly recommended to provide an external reset pulse of ca 1 ms in order to allow the PLL to settle on the desired CPU clock frequency Note Shorter reset pulses may only be applied to devices not equipped with an on chip PLL The input RSTIN provides an internal pullup device equalling a resistor of 50 KO to 150 KQ the minimum reset time must be determined by the lowest value Simply connecting an external capacitor is sufficient for an automatic power on reset see b in figure above RSTIN may also be connected to the output of other logic gates see a in figure above Note A power on reset requires an active time of two reset sequences 1036 CPU clock cycles after a stable clock signal is available about 10 50 ms to allow the on chip oscillator to stabilize Software Reset The reset sequence can be triggered at any time via the protected instruction SRST Software Reset This instruction can be executed
395. ser in either the internal or external memory Both stack types grow from high memory addresses to low memory addresses Internal System Stack A system stack is provided to store return vectors segment pointers and processor status for procedures and interrupt routines A system register SP points to the top of the stack This pointer is decremented when data is pushed onto the stack and incremented when data is popped The internal system stack can also be used to temporarily store data or pass it between subroutines or tasks Instructions are provided to push or pop registers on from the system stack However in most cases the register banking scheme provides the best performance for passing data between multiple tasks Note The system stack allows the storage of words only Bytes must either be converted to words or the respective other byte must be disregarded Register SP can only be loaded with even byte addresses The LSB of SP is always 0 Detection of stack overflow underflow is supported by two registers STKOV Stack Overflow Pointer and STKUN Stack Underflow Pointer Specific system traps Stack Overflow trap Stack Underflow trap will be entered whenever the SP reaches either boundary specified in these registers The contents of the stack pointer are compared to the contents of the overflow register whenever the SP is DECREMENTED either by a CALL PUSH or SUB instruction An overflow trap will be entered when th
396. set of local registers by executing the SCXT switch context instruction This mechanism does not provide a method to recursively call a subroutine Saving and Restoring of Registers To provide local registers the contents of the registers which are required for use by the subroutine can be pushed onto the stack and the previous values be popped before returning to the calling routine This is the most common technique used today and it does provide a mechanism to support recursive procedures This method however requires two machine cycles per register stored on the system stack one cycle to PUSH the register and one to POP the register Use of the System Stack for Local Registers It is possible to use the SP and CP to set up local subroutine register frames This enables subroutines to dynamically allocate local variables as needed within two machine cycles A local frame is allocated by simply subtracting the number of required local registers from the SP and then moving the value of the new SP to the CP Semiconductor Group 19 9 SIEMENS System Programming C167 This operation is supported through the SCXT switch context instruction with the addressing mode reg mem Using this instruction saves the old contents of the CP on the system stack and moves the value of the SP into CP see example below Each local register is then accessed as if it was a normal register Upon exit from the subroutine first the old CP must be resto
397. signal RSTIN is latched low hardware reset The internal reset condition is active at least for the duration of the reset sequence and then until the RSTIN input is inactive When this internal reset condition is removed reset sequence complete and RSTIN inactive the reset configuration is latched from PORTO and pins ALE RD and WR are driven to their inactive levels Note Bit ADP which selects the Adapt mode is latched with the rising edge of RSTIN After the internal reset condition is removed the microcontroller will start program execution from memory location 00 0000 in code segment zero This start location will typically hold a branch instruction to the start of a software initialization routine for the application specific configuration of peripherals and CPU Special Function Registers RSTOUT External Hardware External Reset Sources a Generated Warm reset b Automatic Power on reset MCA02259 Figure 17 1 External Reset Circuitry Semiconductor Group 17 1 SIEMENS System Reset C167 Hardware Reset A hardware reset is triggered when the reset input signal RSTIN is latched low To ensure the recognition of the RSTIN signal latching it must be held low for at least 2 CPU clock cycles Also shorter RSTIN pulses may trigger a hardware reset if they coincide with the latch s sample point However it is recommended to keep HSTIN low for ca 1 ms After the reset
398. sing an increment or decrement of the timer can be a positive a negative or both a positive and a negative transition at this pin Bit field T3I in control register T3CON selects the triggering transition see table below uns TxOTL s f TxOUT TxOE MCB02030 Figure 9 5 Block Diagram of Core Timer T3 in Counter Mode GPT1 Core Timer T3 Counter Mode Input Edge Selection T3I Triggering Edge for Counter Increment Decrement 000 None Counter T3 is disabled 001 Positive transition rising edge on T3IN 010 Negative transition falling edge on T3IN 011 Any transition rising or falling edge on T3IN 1XX Reserved Do not use this combination For counter operation pin T3IN P3 6 must be configured as input ie direction control bit DP3 6 must be 0 The maximum input frequency which is allowed in counter mode is fopy 16 1 25 MHz fcpy 20 MHz To ensure that a transition of the count input signal which is applied to T3IN is correctly recognized its level should be held high or low for at least 8 fcpy cycles before it changes Semiconductor Group 9 7 SIEMENS The General Purpose Timer Units C167 GPT1 Auxiliary Timers T2 and T4 Both auxiliary timers T2 and T4 have exactly the same functionality They can be configured for timer gated timer or counter mode with the same options for the timer frequencies and the count signal as the core timer T3 In addition to these 3 counting modes the au
399. ss bits A15 A8 on POH do not change while POL multiplexes address and data a 16 bit data bus requires a word latch the least significant address line AO is not relevant for word accesses The upper address lines An A16 are permanently output on Port 4 if segmentation is enabled and do not require latches The EBC initiates an external access by generating the Address Latch Enable signal ALE and then placing an address on the bus The falling edge of ALE triggers an external latch to capture the address After a period of time during which the address must have been latched externally the address is removed from the bus The EBC now activates the respective command signal RD WR WRL WRH Data is driven onto the bus either by the EBC for write cycles or by the external memory peripheral for read cycles After a period of time which is determined by the access time of the memory peripheral data become valid Read cycles Input data is latched and the command signal is now deactivated This causes the accessed device to remove its data from the bus which is then tri stated again Write cycles The command signal is now deactivated The data remain valid on the bus until the next external bus cycle is started ja Bus Cycle TERT ALE BUS PO MCT02060 Figure 8 2 Multiplexed Bus Cycle Semiconductor Group 8 3 SIEMENS The External Bus Interface C167 Demultiplexed Bus Mode
400. ssing mechanisms allow to access the SFRs indirect or direct addressing with 16 bit mem addresses it must be guaranteed that the used data page pointer DPPO DPP3 selects data page 3 accesses via the Peripheral Event Controller PEC use the SRCPx and DSTPx pointers instead of the data page pointers short 8 bit reg addresses to the standard SFR area do not use the data page pointers but directly access the registers within this 512 Byte area short 8 bit reg addresses to the extended ESFR area require switching to the 512 Byte extended SFR area This is done via the EXTension instructions EXTR EXTP R EXTS R Byte write operations to word wide SFRs via indirect or direct 16 bit mem addressing or byte transfers via the PEC force zeros in the non addressed byte Byte write operations via short 8 bit reg addressing can only access the low byte of an SFR and force zeros in the high byte It is therefore recommended to use the bit field instructions BFLDL and BFLDH to write to any number of bits in either byte of an SFR without disturbing the non addressed byte and the unselected bits Reserved Bits Some of the bits which are contained in the C167 s SFRs are marked as Reserved User software should never write 1 s to reserved bits These bits are currently not implemented and may be used in future products to invoke new functions In this case the active state for these functions will be 1 and the inactive state wil
401. st is to be serviced by the PEC or by the interrupt service routine Note PEC transfers are only executed if their priority level is higher than the CPU level ie only PEC channels 7 4 are processed while the CPU executes on level 14 All interrupt request sources that are enabled and programmed for PEC service should use different channels Otherwise only one transfer will be performed for all simultaneous requests When COUNT is decremented to 00 4 and the CPU is to be interrupted an incorrect interrupt vector will be generated Semiconductor Group 5 12 SIEMENS Interrupt and Trap Functions C167 The source and destination pointers specifiy the locations between which the data is to be moved A pair of pointers SRCPx and DSTPx is associated with each of the 8 PEC channels These pointers do not reside in specific SFRs but are mapped into the internal RAM of the C167 just below the bit addressable area see figure below 00 FCFE 00 FCEE 00 FCFC 00 FCEC 00 FCFA 00 FCEA 00 FCF8 00 FCE8 00 FCF6 00 FCE6 00 FCFA 00 FCEA 00 FCF2 00 FCE2 00 FCFO 00 FCEO Figure 5 2 Mapping of PEC Pointers into the Internal RAM PEC data transfers do not use the data page pointers DPP3 DPPO The PEC source and destination pointers are used as 16 bit intra segment addresses within segment 0 so data can be transferred between any two locations within the first four data pages 3 0 The pointer locations for
402. ster SWAPB Rn ROR Rn 84 Swap bytes within word Modification of System Flags is performed using bit set or bit clear instructions BSET BCLR All bit and word instructions can access the PSW register so no instructions like CLEAR CARRY or ENABLE INTERRUPTS are required External Memory Data Access does not require special instructions to load data pointers or explicitly load and store external data The C167 provides a Von Neumann memory architecture and its on chip hardware automatically detects accesses to internal RAM GPRs and SFRs Multiplication and Division Multiplication and division of words and double words is provided through multiple cycle instructions implementing a Booth algorithm Each instruction implicitly uses the 32 bit register MD MDL lower 16 bits MDH upper 16 bits The MDRIU flag Multiply or Divide Register In Use in register MDC is set whenever either half of this register is written to or when a multiply divide instruction is started It is cleared whenever the MDL register is read Because an interrupt can be acknowledged before the contents of register MD are saved this flag is required to alert interrupt routines which require the use of the multiply divide hardware so they can preserve register MD This register however only needs to be saved when an interrupt routine requires use of the MD register and a previous task has not saved the current result This flag is easily tested by the Jump on B
403. ster PWMCON1 controls the operating modes and the outputs of the four PWM channels The basic operating mode for each channel standard edge aligned or symmetrical center aligned PWM mode is selected by the mode bits PMx Burst mode channels 0 and 1 and single shot mode channel 2 or 3 are selected by separate control bits The output signal of each PWM channel is individually enabled by bit PENx If the output is not enabled the respective pin can be used for general purpose IO and the PWM channel can only be used to generate an interrupt request PWMCONT1 FF32 994 SFR Reset Value 0000 15 14 13 12 1i 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw rw rw rw Bit Function PENx PWM Channel x Output Enable Bit 0 Channel x output signal disabled generate interrupt only 1 Channel x output signal enabled PMx PWM Channel x Mode Control Bit 0 Channel x operates in mode 0 ie edge aligned PWM 1 Channel x operates in mode 1 ie center aligned PWM PBO1 PWM Channel 0 1 Burst Mode Control Bit 0 Channels 0 and 1 work independently in respective standard mode 1 Outputs of channels 0 and 1 are ANDed to POUTO in burst mode PSx PWM Channel x Single Shot Mode Control Bit 0 Channel x works in respective standard mode 1 Channel x operates in single shot mode Semiconductor Group 15 10 SIEMENS The Pulse Width Modulation Module C167 15 3 Interrupt Request
404. stopped by software through bit T3R Timer T3 Run Bit If T3R 0 the timer stops Setting T3R to 1 will start the timer In gated timer mode the timer will only run if T3R 1 and the gate is active high or low as programmed Semiconductor Group 9 3 SIEMENS The General Purpose Timer Units C167 Count Direction Control The count direction of the core timer can be controlled either by software or by the external input pin TS3EUD Timer T3 External Up Down Control Input which is the alternate input function of port pin P3 4 These options are selected by bits T3UD and T3UDE in control register T3CON When the up down control is done by software bit TSUDE 0 the count direction can be altered by setting or clearing bit T3UD When TGUDE 1 pin T3EUD is selected to be the controlling source of the count direction However bit T3UD can still be used to reverse the actual count direction as shown in the table below If T3UD 0 and pin T3EUD shows a low level the timer is counting up With a high level at T3EUD the timer is counting down If T3UD 1 a high level at pin T3EUD specifies counting up and a low level specifies counting down The count direction can be changed regardless of whether the timer is running or not When pin T3EUD P3 4 is used as external count direction control input it must be configured as input ie its corresponding direction control bit DP3 4 must be set to 0 GPT1 Core Tim
405. struction Servicing the watchdog timer clears the low byte and reloads the high byte of the watchdog time register WDT with the preset value in bit field WDTREL which is the high byte of register WDTCON Servicing the watchdog timer will also reset bit WDTR After being serviced the watchdog timer continues counting up from the value lt WDTREL gt 28 Instruction SRVWDT has been encoded in such a way that the chance of unintentionally servicing the watchdog timer eg by fetching and executing a bit pattern from a wrong location is minimized When instruction SRVWDT does not match the format for protected instructions the Protection Fault Trap will be entered rather than the instruction be executed The time period for an overflow of the watchdog timer is programmable in two ways the input frequency to the watchdog timer can be selected via bit WDTIN in register WDTCON to be either fcpuy 2 or fopy 128 the reload value WDTREL for the high byte of WDT can be programmed in register WDTCON The period Pwpr between servicing the watchdog timer and the next overflow can therefore be determined by the following formula o lt WDTIN gt 6 216 lt WDTREL gt 29 Pwpr fopu The table below marks the possible ranges for the watchdog time which can be achieved using a CPU clock of 20 MHz Some numbers are rounded to 3 significant digits Reload value Prescaler for fcpy in WOTREL 2 WDTIN 0 128 WDTIN
406. t Identifier of a standard message ID28 18 or an extended message ID28 0 For standard identifiers bits ID17 0 are don t care Semiconductor Group 23 16 SIEMENS The On Chip CAN Interface C167 Message Configuration and Data The following fields hold a description of the message within this object The data field occupies the following 8 byte positions after the Message Configuration Register Note There is no don t care option for bits XTD and DIR So incoming frames can only match with corresponding message objects either standard XTD 0 or extended XTD 1 Data frames only match with receive objects remote frames only match with transmit objects When the CAN controller stores a data frame it will write all the eight data bytes into a message object If the data length code was less than 8 the remaining bytes of the message object will be overwritten by non specified values Message Configuration Register EFn6 XReg Reset Value UU 5 4 3 2 1 rw rw r rw rw r Bit Function XTD Extended Identifier Indicates if this message object will use an extended 29 bit identifier or a standard 11 bit identifier DIR Message Direction DIR 1 transmit On TXRQ the respective message object is transmitted On reception of a remote frame with matching identifier the TXRQ and RMTPND bits of this message object are set DIR 0 receive On TXRQ a remote frame with the identifier of this
407. t 6 Pins with an Alternate Output Function Semiconductor Group 6 28 SIEMENS Parallel Ports C167 The bus arbitration signals HOLD HLDA and BREQ are selected with bit HLDEN in register PSW When the bus arbitration signals are enabled via HLDEN also these pins are switched automatically to the appropriate direction Note that the pin drivers for HLDA and BHEQ are automatically enabled while the pin driver for HOLD is automatically disabled EN Write p Open Drain Latch Read ODP6 y lt Write DP6 y a Direction Read DP6 y lt Write P6 y Port Output Read P6 y v 1 K ra us O lt lt __ aQrdry8 8e De Cc o o Alternate Data 4 Input MCB01983 Figure 6 19 Block Diagram of Pin P6 5 HOLD Semiconductor Group 6 29 SIEMENS Parallel Ports C167 6 8 Port 7 If this 8 bit port is used for general purpose IO the direction of each line can be configured via the corresponding direction register DP7 Each port line can be switched into push pull or open drain mode via the open drain control register ODP7 P7 FFDO E8 SFR Reset Value 00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 s x x Bit Function P7 y Port data register P7 bit y DP7 FFD2y4 E94 SFR Reset Value 00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DP7 7 DP7 6 DP7 5 DP7 4 DP7 3 DP7 2 DP7 1 DP7 0
408. t Control Register description for an explanation of the control fields Semiconductor Group 15 11 SIEMENS The Pulse Width Modulation Module C167 15 4 PWM Output Signals The output signals of the four PWM channels POUTS3 POUTO are alternate output functions on Port 7 P7 3 P7 0 The output signal of each PWM channel is individually enabled by control bit PENx in register PWMCON 1 The PWM signals are XORed with the respective port latch outputs before being driven to the port pins This allows driving the PWM signal directly to the port pin P7 x 0 or drive the inverted PWM signal P7 x 1 Qz Latch P7 3 9 QZ Latch P 7 1 2 ac NJ Latch P7 0 9 J Pin P7 0 PENX PBO01 MCA02277 Figure 15 7 PWM Output Signal Generation Note Using the open drain mode on Port 7 allows the combination of two or more PWM outputs through a Wired AND configuration using an external pullup device This provides sort of a burst mode for any PWM channel Semiconductor Group 15 12 SIEMENS The Pulse Width Modulation Module C167 Software Control of the PWM Outputs In an application the PWM output signals are generally controlled by the PWM module However it may be necessary to influence the level of the PWM output pins via software either to initialize the system or to react on some extraordinary condition eg a system fault or an emergency Clearing the timer run bit PTRx stops
409. t address lines during reset This allows the selection which pins of Port 4 drive address lines and which are used for general purpose IO The two bits are latched in register RPOH Depending on the system architecture the required address space is chosen and accessible right from the start so the initialization routine can directly access all locations without prior programming The required pins of Port 4 are automatically switched to address output mode SALSEL Segment Address Lines Directly accessible Address Space 11 Two A17 A16 256 KByte Default without pull downs 10 Eight A23 A16 16 MByte Maximum 0 1 None 64 KByte Minimum 00 Four A19 A16 1 MByte Even if not all segment address lines are enabled on Port 4 the C167 internally uses its complete 24 bit addressing mechanism This allows the restriction of the width of the effective address bus while still deriving CS signals from the complete addresses Default 2 bit segment address A17 A16 allowing access to 256 KByte Note The selected number of segment address lines cannot be changed via software after reset Semiconductor Group 17 10 SIEMENS System Reset C167 Clock Generation Control Pins POH 7 POH 6 and POH 5 CLKCFG select the clock generation mode on chip PLL during reset The oscillator clock either directly feeds the CPU and peripherals direct drive or it is fed to the on chip PLL which then provides the CPU clock si
410. t flags is automatically updated in the PSW after each arithmetic logical shift or movement operation These flags allow branching on specific conditions Support for both signed and unsigned arithmetic is provided through user specifiable branch tests These flags are also preserved automatically by the CPU upon entry into an interrupt or trap routine All targets for branch calculations are also computed in the central ALU A 16 bit barrel shifter provides multiple bit shifts in a single cycle Rotates and arithmetic shifts are also supported Extended Bit Processing and Peripheral Control A large number of instructions has been dedicated to bit processing These instructions provide efficient control and testing of peripherals while enhancing data manipulation Unlike other microcontrollers these instructions provide direct access to two operands in the bit addressable space without requiring to move them into temporary flags The same logical instructions available for words and bytes are also supported for bits This allows the user to compare and modify a control bit for a peripheral in one instruction Multiple bit shift instructions have been included to avoid long instruction streams of single bit shift operations These are also performed in a single machine cycle In addition bit field instructions have been provided which allow the modification of multiple bits from one operand in a single instruction High Performance Branch
411. t function of a pin is to be used the direction of this pin must be programmed for output DPx y 1 except for some signals that are used directly after reset and are configured automatically Otherwise the pin remains in the high impedance state and is not effected by the alternate output function The respective port latch should hold a 1 because its output is ANDed with the alternate output data except for the PWM output signals If an alternate input function of a pin is used the direction of the pin must be programmed for input DPx y 0 if an external device is driving the pin The input direction is the default after reset If no external device is connected to the pin however one can also set the direction for this pin to output In this case the pin reflects the state of the port output latch Thus the alternate input function reads the value stored in the port output latch This can be used for testing purposes to allow a software trigger of an alternate input function by writing to the port output latch On most of the port lines the user software is responsible for setting the proper direction when using an alternate input or output function of a pin This is done by setting or clearing the direction control bit DPx y of the pin before enabling the alternate function There are port lines however where the direction of the port line is switched automatically For instance in the multiplexed external bus modes of POR
412. t input RSTIN provide another possibility for the CPU to react on an external input signal NMI and RSTIN are dedicated input pins which cause hardware traps Semiconductor Group 5 22 SIEMENS Interrupt and Trap Functions C167 Fast External Interrupts The input pins that may be used for external interrupts are sampled every 400 ns 20 MHz CPU clock ie external events are scanned and detected in timeframes of 400 ns The C167 provides 8 interrupt inputs that are sampled every 50 ns 20 MHz CPU clock so external events are captured faster than with standard interrupt inputs The upper 8 pins of Port 2 CC8lIO CC151O on P2 8 P2 15 can individually be programmed to this fast interrupt mode where also the trigger transition rising falling or both can be selected The External Interrupt Control register EXICON controls this feature for all 8 pins EXICON F1C0 E04 ESFR Reset Value 00004 1 14 5 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw Bit Function EXIxES External Interrupt x Edge Selection Field x 7 0 0 0 Fast external interrupts disabled standard mode 0 1 Interrupt on positive edge rising 1 0 Interrupt on negative edge falling 1 1 Interrupt on any edge rising or falling These fast external interrupts use the interrupt nodes and vectors of the CAPCOM channels CC8 CC15 so the capture compare function cannot be used on the respective Port 2 pins with EXIXES 00g Howe
413. t value appears in SFR TO T7 within 8 CPU clock cycles after the signal transition at pin TxIN Reload A reload of a timer with the 16 bit value stored in its associated reload register in both modes is performed each time a timer would overflow from FFFFy to 00004 In this case the timer does not wrap around to 00004 but rather is reloaded with the contents of the respective reload register TxREL The timer then resumes incrementing starting from the reloaded value The reload registers TxREL are not bitaddressable Semiconductor Group 14 7 SIEMENS The Capture Compare Units C167 14 2 CAPCOM Unit Timer Interrupts Upon a timer overflow the corresponding timer interrupt request flag TxIR for the respective timer will be set This flag can be used to generate an interrupt or trigger a PEC service request when enabled by the respective interrupt enable bit TxIE Each timer has its own bitaddressable interrupt control register TxIC and its own interrupt vector TXINT The organization of the interrupt control registers TxIC is identical with the other interrupt control registers TOIC FF9C CE SFR Reset Value 00 7 6 5 4 3 2 1 0 TOIR TOIE ILVL GLVL rw T1IC FF9E CF SFR Reset Value 004 7 6 1 0 rw rw rw T7IC F17A4 BEy ESFR Reset Value 004 7 1 0 rw rw T8IC F17C BF ESFR Reset Value 00j TUE NU 12 IT 0 E 7 5 4 3 2 1 0 T8IR T8IE ILVL GLVL rw rw rw rw Note Plea
414. tain ROM memory and the ROM must contain a valid reset vector and valid code at its destination Mapping the internal ROM to segment 1 Due to instruction pipelining any new ROM mapping will at the earliest become valid for the second instruction after the instruction which has changed the ROM mapping To enable accesses to the ROM after mapping a branch to the newly selected ROM area JMPS and reloading of all data page pointers is required This also applies to re mapping the internal ROM to segment 0 Enabling the internal ROM after reset When enabling the internal ROM after having booted the system from external memory note that the C167 will then access the internal ROM using the current segment offset rather than accessing external memory Disabling the internal ROM after reset When disabling the internal ROM after having booted the system from there note that the C167 will not access external memory before a jump to segment 0 in this case is executed General Rules When mapping the ROM no instruction or data accesses should be made to the internal ROM otherwise unpredictable results may occur To avoid these problems the instructions that configure the internal ROM should be executed from external memory or from the internal RAM Whenever the internal ROM is disabled enabled or remapped the DPPs must be explicitly re loaded to enable correct data accesses to the internal ROM and or external memory Semiconductor Group
415. taken from the cache and immediatly injected into the decode stage of the pipeline see figure below A time saving jump on cache is always taken after the second and any further occurrence of the same cache jump instruction unless an instruction which has the fundamental capability of changing the CSP register contents JMPS CALLS RETS TRAP RETI or any standard interrupt has been processed during the period of time between two following occurrences of the same cache jump instruction Injection Injection of cached Target Instruction Itarcet lrancET 1 lranGET 1 TaRGET 2 DECODE Cache Jmp linsect tarcet Cache Jmp Hancer tarcet 1 1st loop iteration gt Repeated loop iteration gt Figure 4 4 Cache Jump Instruction Pipelining Semiconductor Group 4 5 SIEMENS The Central Processing Unit CPU C167 Particular Pipeline Effects Since up to four different instructions are processed simultaneously additional hardware has been spent in the C167 to consider all causal dependencies which may exist on instructions in different pipeline stages without a loss of performance This extra hardware ie for forwarding operand read and write values resolves most of the possible conflicts eg multiple usage of buses in a time optimized way and thus avoids that the pipeline becomes noticeable for the user in most cases However there are some very rare cases where the circumstanc
416. tem initialization On chip CAN Module not on all derivatives 111 IO Lines With Individual Bit Addressability Tri stated in input mode Push pull or open drain output mode Selectable input thresholds not on all derivatives Different Temperature Ranges 0 to 70 C 40 to 85 C 40 to 110 C Siemens CMOS Process Low Power CMOS Technology including power saving Idle and Power Down modes 144 Pin Plastic Quad Flat Pack PQFP Package EIAJ standard 0 65 mm 25 6 mil lead spacing surface mount technology Semiconductor Group 1 5 SIEMENS Introduction C167 Complete Development Support A variety of software and hardware development tools for the Siemens family of 16 bit microcontrollers is available from experienced international tool suppliers The high quality and reliability of these tools is already proven in many applications and by many users The tool environment for the Siemens 16 bit microcontrollers includes the following tools Compilers C MODULA2 FORTH Macro Assemblers Linkers Locaters Library Managers Format Converters Architectural Simulators HLL debuggers Real Time operating systems VHDL chip models In Circuit Emulators based on bondout or standard chips Plug In emulators Emulation and Clip Over adapters production sockets Logic Analyzer disassemblers Evaluation Boards with monitor programs Industrial boards also for CAN FUZZY PROFIBU
417. tering allowing a large number of infrequent objects to be handled by the system Semiconductor Group 23 1 SIEMENS The On Chip CAN Interface C167 The object layer architecture of the CAN controller is designed to be as regular and orthogonal as possible This makes it easy to use CAN TxD PS PS BTL Configuration ue o mor Tx Rx Shift Register x at Messages Intelligent Memory Interrupt Register Messages Handlers JV CAN RxD Timing Generator Clocks to all Control Status K Control Status NA Register to XBUS Figure 23 1 CAN Controller Block Diagram Semiconductor Group 23 2 MCB02571 SIEMENS The On Chip CAN Interface C167 Tx Rx Shift Register The Transmit Receive Shift Register holds the destuffed bit stream from the bus line to allow the parallel access to the whole data or remote frame for the acceptance match test and the parallel transfer of the frame to and from the Intelligent Memory Bit Stream Processor The Bit Stream Processor BSP is a sequencer controlling the sequential data stream between the Tx Rx Shift Register the CRC Register and the bus line The BSP also controls the EML and the parallel data stream between the Tx Rx Shift Register and the Intelligent Memory such that the processes of reception arbitration transmission and error signalling are performed according to the CAN protocol Note that the autom
418. th edges of the output signal symmetrically PTx Count Value Duly Cycle PWx Pulse Width 0 PWx 1 PWx 2 PWx PWx 6 PWx 7 PWx 8 0 LSR Change Count MCAD1950 Latch Shadow Direction Register Interrupt Request Figure 15 4 Operation and Output Waveform in Mode 1 Semiconductor Group 15 4 SIEMENS The Pulse Width Modulation Module C167 Burst Mode Burst mode is selected by setting bit PBO1 in register PWMCON to 1 This mode combines the signals from PWM channels 0 and 1 onto the port pin of channel 0 The output of channel 0 is replaced with the logical AND of channels 0 and 1 The output of channel 1 can still be used at its associated output pin if enabled Each of the two channels can either operate in mode 0 or 1 Note It is guaranteed by design that no spurious spikes will occur at the output pin of channel 0 in this mode The output of the AND gate will be transferred to the output pin synchronously to internal clocks XORing of the PWM signal and the port output latch value is done after the ANDing of channel 0 and 1 Channel 0 PP1 PT1 Count Channel 1 Resulting Output POUTO MCA01951 Figure 15 5 Operation and Output Waveform in Burst Mode Semiconductor Group 15 5 SIEMENS The Pulse Width Modulation Module C167 Single Shot Mode Single shot mode is selected by setting the respect
419. the CAN controller EIE is set and BOFF or EWRN change or to a CAN transfer incident SIE must be set like reception or transmission of a message RXOK or TXOK is set or the occurrence of a CAN bus error LEC is updated The CPU may clear RXOK TXOK and LEC however writing to the status partition of the Control Register can never generate or reset an interrupt To update the INTID value the status partition of the Control Register must be read 02 Message 15 Interrupt Bit INTPND in the Message Control Register of message object 15 last message has been set The last message object has the highest interrupt priority of all message objects 1 2 N Message N Interrupt Bit INTPND in the Message Control Register of message object N has been set N 1 14 Note that a message interrupt code is only displayed if there is no other interrupt request with a higher priority 1 Bit INTPND of the corresponding message object has to be cleared to give messages with a lower priority the possibility to update INTID or to reset INTID to OO idle state Semiconductor Group 23 9 SIEMENS The On Chip CAN Interface C167 Configuration of the Bit Timing According to the CAN protocol specification a bit time is subdivided into four segments Sync segment propagation time segment phase buffer segment 1 and phase buffer segment 2 Each segment is a multiple of the time quantum tg with ty BRP 1 2 b CL
420. the ROM area Devices with a ROM size above 32 KByte expand the ROM area from the middle of segment 1 ie starting at address 01 8000 The internal ROM Flash can be used for both code instructions and data constants tables etc storage Code fetches are always made on even byte addresses The highest possible code storage location in the internal ROM is either xx xxFEy for single word instructions or xx xxFC for double word instructions The respective location must contain a branch instruction unconditional because sequential boundary crossing from internal ROM to external memory is not supported and causes erroneous results Any word and byte data read accesses may use the indirect or long 16 bit addressing modes There is no short addressing mode for internal ROM operands Any word data access is made to an even byte address The highest possible word data storage location in the internal ROM is xx xxFEy For PEC data transfers the internal ROM can be accessed independent of the contents of the DPP registers via the PEC source and destination pointers The internal ROM is not provided for single bit storage and therefore it is not bit addressable Note The x in the locations above depend on the available ROM Flash memory and on the mapping The internal ROM may be enabled disabled or mapped into segment O or segment 1 under software control Chapter System Programming shows how to do this and reminds of the pre
421. the mechanism how the internal CPU clock is generated from the externally applied XTAL1 input clock Note RPOH cannot be changed via software but rather allows to check the current configuration Precautions and Hints The external bus interface is enabled as long as at least one of the BUSCON registers has its BUSACT bit set PORT will output the intra segment address as long as at least one of the BUSCON registers selects a demultiplexed external bus even for multiplexed bus cycles Not all address areas defined via registers ADDRSELx may overlap each other The operation of the EBC will be unpredictable in such a case See chapter Address Window Arbitration The address areas defined via registers ADDRSELx may overlap internal address areas Internal accesses will be executed in this case Forany access to an internal address area the EBC will remain inactive see EBC Idle State Semiconductor Group 8 23 The External Bus Interface C167 SIEMENS 8 5 EBC Idle State When the external bus interface is enabled but no external access is currently executed the EBC is idle As long as only internal resources from an architecture point of view like IRAM GPRs or SFRs etc are used the external bus interface does not change see table below Accesses to on chip X Peripherals are also controlled by the EBC However even though an X Peripheral appears like an external peripheral to the controlle
422. the signal WRH alternate function of P3 12 BHE During reset and during Hold mode an internal pullup ensures an inactive high level on the WR WRL output During accesses to on chip X Peripherals WR WRL remains inactive high Semiconductor Group 7 1 SIEMENS Dedicated Pins C167 The Ready Input READY receives a control signal from an external memory or peripheral device that is used to terminate an external bus cycle provided that this function is enabled for the current bus cycle READY may be used as synchronous HEADY or may be evaluated asynchronously When waitstates are defined for a READY controlled address window the READY input is not evaluated during these waitstates The External Access Enable Pin EA determines if the C167 after reset starts fetching code from the internal ROM area EA 1 or via the external bus interface EA 0 Be sure to hold this input low for ROMless devices The Non Maskable Interrupt Input NMI allows to trigger a high priority trap via an external signal eg a power fail signal It also serves to validate the PWRDN instruction that switches the C167 into Power Down mode The NMI pin is sampled with every CPU clock cycle to detect transitions The Oscillator Input XTAL1 and Output XTAL2 connect the internal Pierce oscillator to the external crystal The oscillator provides an inverter and a feedback element The standard external oscillator circuitry see figure below comprises the
423. their appropriate global masks Bit IDE of the incoming message determines if the standard 11 bit mask in Global Mask Short is to be used or the 29 bit extended mask in Global Mask Long Bits holding a 0 mean don t care ie do not compare the message s identifier in the respective bit position The last message object 15 has an additional individually programmable acceptance mask Mask of Last Message for the complete arbitration field This allows classes of messages to be received in this object by masking some bits of the identifier Note The Mask of Last Message is ANDed with the Global Mask that corresponds to the incoming message Global Mask Short EF06 XReg Reset Value UFUU 15 14 13 11 1 7 6 5 4 3 2 1 0 12 0 9 8 rw r r r r r rw Bit Function ID28 18 Identifier 11 bit Mask to filter incoming messages with standard identifier Upper Global Mask Long EF08j XReg Reset Value VUUU 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Lower Global Mask Long EFOA XReg Reset Value UUUU 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw r r r Bit Function ID28 0 Identifier 29 bit Mask to filter incoming messages with extended identifier Semiconductor Group 23 11 SIEMENS The On Chip CAN Interface C167 Upper Mask of Last Message EFOC XReg Reset Value UUUU 15 14 13 12 1i 10 9 8 7 6 5 4 3 2 l 0 REP Vids oo um rw rw E Lower Mask of Last Message EFOE XReg
424. time that each respective step takes because the capacitors must reach their final voltage level within the given time at least with a certain approximation The maximum current however that a source can deliver depends on its internal resistance The time that the two different actions during conversion take sampling and converting can be programmed within a certain range in the C167 relative to the CPU clock The absolute time that is consumed by the different conversion steps therefore is independent from the general speed of the controller This allows adjusting the A D converter of the C167 to the properties of the system Fast Conversion can be achieved by programming the respective times to their absolute possible minimum This is preferable for scanning high frequency signals The internal resistance of analog source and analog supply must be sufficiently low however High Internal Resistance can be achieved by programming the respective times to a higher value or the possible maximum This is preferable when using analog sources and supply with a high internal resistance in order to keep the current as low as possible The conversion rate in this case may be considerably lower however The conversion times are programmed via the upper four bits of register ADCON Bit field ADCTC conversion time control selects the basic conversion clock used for the 14 steps of converting The sample time is a multiple of this conversion time and
425. tion Register 3 00004 BUSCONA b FF1A 8D Bus Configuration Register 4 00004 CiBTR EF044 X CAN Bit Timing Register UUUU C1CSR EFOO X CAN Control Status Register XX0144 C1GMS EF064 X CAN Global Mask Short UFUU C1IR EFO2 X CAN Interrupt Register XXy C1LGML EFOA X CAN Lower Global Mask Long UUUU C1LMLM EFOE X CAN Lower Mask of Last Message UUUU C1UGML EFO8 X CAN Upper Global Mask Long UUUU C1UMLM EFOC X CAN Upper Mask of Last Message UUUU CAPREL FEA4A 25y GPT2 Capture Reload Register 0000 CCO FE804 404 CAPCOM Register 0 0000 CCOIC b FF78 BCy CAPCOM Register 0 Interrupt Control Register 00004 Semiconductor Group 20 4 SIEMENS The Register Set C167 Name Physical 8 Bit Description Reset Address Address Value CC1 FE824 414 CAPCOM Register 1 00004 CC1IC b FF7A BDy CAPCOM Register 1 Interrupt Control Register 0000 CC2 FE84 424 CAPCOM Register 2 0000 CC2IC b FF7Cy BEy CAPCOM Register 2 Interrupt Control Register 0000 CC3 FE86 434 CAPCOM Register 3 00004 CC3IC b FF7E BFy CAPCOM Register 3 Interrupt Control Register 0000 CC4 FE88 444 CAPCOM Register 4 0000 CC4IC b FF80 COH CAPCOM Register 4 Interrupt Control Register 0000 CC5 FE8Ay 454 CAPCOM Register 5 0000 CC5IC b FF82 C1y CAPCOM Register 5 Interrupt Control Register 0000 CC6 FE8Cy 46 CAPCOM Register
426. tion is automatically set values that deviate from the normal reset values are marked Watchdog Timer Disabled Register SYSCON OE00y Context Pointer CP FA00 Register STKUN FA40 Stack Pointer SP FA40 Register STKOV FAOCy 0 lt gt C Register SOCON 80114 Register BUSCONO acc to startup config Register SOBG acc to 00 byte P3 10 TXDO F DP3 10 T Other than after a normal reset the watchdog timer is disabled so the bootstrap loading sequence is not time limited Pin TXDO is configured as output so the C167 can return the identification byte Note Even if the internal ROM is enabled no code can be executed out of it The hardware that activates the BSL during reset may be a simple pull down resistor on POL 4 for systems that use this feature upon every hardware reset You may want to use a switchable solution via jumper or an external signal for systems that only temporarily use the bootstrap loader External Signal YUU 177 Boot Circuit 2 MCA02261 Figure 13 2 Hardware Provisions to Activate the BSL Semiconductor Group 13 2 SIEMENS The Bootstrap Loader C167 After sending the identification byte the ASCO receiver is enabled and is ready to receive the initial 32 bytes from the host A half duplex connection is therefore sufficient to feed the BSL Memory Configuration after Reset The configuration ie the accessibility of the C167 s m
427. tion of application specific peripheral modules in addition to the standard on chip peripherals in order to build application specific derivatives As programs for embedded control applications become larger high level languages are favoured by programmers because high level language programs are easier to write to debug and to maintain Semiconductor Group 1 2 SIEMENS Introduction C167 The 80C166 type microcontrollers were the first generation of the 16 bit controller family These devices have established the C16x architecture The C165 type and C167 type devices are members of the second generation of this family This second generation is even more powerful due to additional instructions for HLL support an increased address space increased internal RAM and highly efficient management of various resources on the external bus Enhanced derivatives of this second generation provide additional features like additional internal high speed RAM an integrated CAN Module an on chip PLL etc Utilizing integration to design efficient systems may require the integration of application specific peripherals to boost system performance while minimizing the part count These efforts are supported by the so called XBUS defined for the Siemens 16 bit microcontrollers second generation This XBUS is an internal representation of the external bus interface that opens and simplifies the integration of peripherals by standardizing the required
428. tiprocessor communication a mechanism to distinguish address from data bytes has been included 8 bit data plus wake up bit mode In synchronous mode the ASCO transmits or receives bytes 8 bits synchronously to a shift clock which is generated by the ASCO The SSC transmits or receives characters of 2 16 bits length synchronously to a shift clock which can be generated by the SSC master mode or by an external master slave mode The SSC can start shifting with the LSB or with the MSB while the ASCO always shifts the LSB first A loop back option is available for testing purposes A number of optional hardware error detection capabilities has been included to increase the reliability of data transfers A parity bit can automatically be generated on transmission or be checked on reception Framing error detection allows to recognize data frames with missing stop bits An overrun error will be generated if the last character received has not been read out of the receive buffer register at the time the reception of a new character is complete The On chip CAN Module The integrated CAN Module handles the completely autonomous transmission and reception of CAN frames in accordance with the CAN specification V2 0 part B active ie the on chip CAN Module can receive and transmit standard frames with 11 bit identifiers as well as extended frames with 29 bit identifiers The module provides Full CAN functionality on up to 15 message objects M
429. tive state IDLE state The clock signal to the CPU itself is switched off while the clocks for the on chip peripherals keep running POWER DOWN state All of the on chip clocks are switched off A transition into an active CPU state is forced by an interrupt if being IDLE or by a reset if being in POWER DOWN mode The IDLE POWER DOWN and RESET states can be entered by particular C167 system control instructions A set of Special Function Registers is dedicated to the functions of the CPU core General System Configuration SYSCON RPOH CPU Status Indication and Control PSW Code Access Control IP CSP Data Paging Control DPPO DPP1 DPP2 DPP3 GPRs Access Control CP System Stack Access Control SP STKUN STKOV Multiply and Divide Support MDL MDH MDC ALU Constants Support ZEROS ONES Semiconductor Group 4 2 SIEMENS The Central Processing Unit CPU C167 4 1 Instruction Pipelining The instruction pipeline of the C167 partitiones instruction processing into four stages of which each one has its individual task 1st FETCH In this stage the instruction selected by the Instruction Pointer IP and the Code Segment Pointer CSP is fetched from either the internal ROM internal RAM or external memory 2nd DECODE In this stage the instructions are decoded and if required the operand addresses are calculated and the respective operands are fetched For all instr
430. to control the automatic response to remote requests TXRQ Transmit Request Indicates that the transmission of this message object is requested by the CPU or via a remote frame and is not yet done TXRQ can be disabled by CPUUPD 9 3 RMTPND Remote Pending Used for transmit objects Indicates that the transmission of this message object has been requested by a remote node but the data has not yet been transmitted When RMTPND is set the CAN controller also sets TXRQ RMTPND and TXRQ are cleared when the message object has been successfully transmitted Semiconductor Group 23 14 SIEMENS The On Chip CAN Interface C167 1 n message object 15 last message these bits are hardwired to 0 inactive in order to prevent transmission of message 15 2 When the CAN controller writes new data into the message object unused message bytes will be overwritten by non specified values Usually the CPU will clear this bit before working on the data and verify that the bit is still cleared once it has finished working to ensure that it has worked on a consistent set of data and not part of an old message and part of the new message For transmit objects the CPU will set this bit along with clearing bit CPUUPD This will ensure that if the message is actually being transmitted during the time the message was being updated by the CPU the CAN controller will not reset bit TXRQ In this way bit TXRQ is only reset once the actual
431. to the respective external area using the corresponding XBCONXx register Priority 4 If there is no match with any XADRSx or ADDRSELx register the access to the external bus uses register BUSCONO XBCONO BUSCON2 BUSCORA Inactive BUSCON1 L window Busco e a a aaae uA Figure 8 11 Address Window Arbitration Note Only the indicated overlaps are defined All other overlaps lead to erroneous bus cycles Eg ADDRSEL4 may not overlap ADDRSEL2 or ADDRSEL1 The hardwired XADRSx registers are defined non overlapping Semiconductor Group 8 22 SIEMENS The External Bus Interface C167 RPOH F108 844 SFR Reset Value XX 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CLKCFG SALSEL CSSEL r r r r r r Bit Function WRC Write Configuration 0 Pins WR and BHE operate as WRL and WRH signals 1 Pins WR and BHE operate as WR and BHE signals CSSEL Chip Select Line Selection Number of active CS outputs 0 0 3 CS lines CS2 CS0 0 1 2 CS lines CS1 CS0 1 0 No CS lines at all 1 1 5 CS lines CS4 CS0 Default without pulldowns SALSEL Segment Address Line Selection Number of active segment address outputs 0 0 4 bit segment address A19 A16 0 1 No segment address lines at all 1 0 8 bit segment address A23 A16 1 1 2 bit segment address A17 A16 Default without pulldowns CLKCFG Clock Generation Mode Configuration These pins define the clock generation mode i e
432. truction equals the lowest negative number which is representable by the data format of the corresponding instruction 8000 for the word data type or 80 for the byte data type the E flag is set to 1 otherwise it is cleared MULIP Flag The MULIP flag will be set to 1 by hardware upon the entrance into an interrupt service routine when a multiply or divide ALU operation was interrupted before completion Depending on the state of the MULIP bit the hardware decides whether a multiplication or division must be continued or not after the end of an interrupt service The MULIP bit is overwritten with the contents of the stacked MULIP flag when the return from interrupt instruction RETI is executed This normally means that the MULIP flag is cleared again after that Note The MULIP flag is a part of the task environment When the interrupting service routine does not return to the interrupted multiply divide instruction ie in case of a task scheduler that switches between independent tasks the MULIP flag must be saved as part of the task environment and must be updated accordingly for the new task before this task is entered Semiconductor Group 4 16 SIEMENS The Central Processing Unit CPU C167 CPU Interrupt Status IEN ILVL The Interrupt Enable bit allows to globally enable IEN 1 or disable IEN 0 interrupts The four bit Interrupt Level field ILVL specifies the priority of the current CPU activity The i
433. ts the logical ORing of the two specified bits Semiconductor Group 4 15 SIEMENS The Central Processing Unit CPU C167 Shift Right Rounding Error Evaluation C Flag V Flag Rounding Error Quantity 0 0 No rounding error 0 1 0 Rounding error lt gt LSB 1 0 Rounding error gt LSB 1 1 Rounding error gt 1 3 LSB e Z Flag The Z flag is normally set to 1 if the result of an ALU operation equals zero otherwise it is cleared For the addition and subtraction with carry the Z flag is only set to 1 if the Z flag already contains a 1 and the result of the current ALU operation additionally equals zero This mechanism is provided for the support of multiple precision calculations For Boolean bit operations with only one operand the Z flag represents the logical negation of the previous state of the specified bit For Boolean bit operations with two operands the Z flag represents the logical NORing of the two specified bits For the prioritize ALU operation the Z flag indicates if the second operand was zero or not e E Flag The E flag can be altered by instructions which perform ALU or data movement operations The E flag is cleared by those instructions which cannot be reasonably used for table search operations In all other cases the E flag is set depending on the value of the source operand to signify whether the end of a search table is reached or not If the value of the source operand of an ins
434. ubsequent external bus cycles may be executed in different ways Certain address areas may use multiplexed or demultiplexed buses or use READY control or predefined waitstates A change of the external bus characteristics can be initiated in two different ways Reprogramming the BUSCON and or ADDRSEL registers allows to either change the bus mode for a given address window or change the size of an address window that uses a certain bus mode Reprogramming allows to use a great number of different address windows more than BUSCONs are available on the expense of the overhead for changing the registers and keeping appropriate tables Switching between predefined address windows automatically selects the bus mode that is associated with the respective window Predefined address windows allow to use different bus modes without any overhead but restrict their number to the number of BUSCONs However as BUSCONO controls all address areas which are not covered by the other BUSCONS this allows to have gaps between these windows which use the bus mode of BUSCONO PORT will output the intra segment address when any of the BUSCON registers selects a demultiplexed bus mode even if the current bus cycle uses a multiplexed bus mode This allows to have an external address decoder connected to PORT1 only while using it for all kinds of bus cycles Note Never change the configuration for an address area that currently supplies the instruction stream
435. uction unconditional because sequential boundary crossing from internal RAM to the SFR area is not supported and causes erroneous results Any word and byte data in the internal RAM can be accessed via indirect or long 16 bit addressing modes if the selected DPP register points to data page 3 Any word data access is made on an even byte address The highest possible word data storage location in the internal RAM is OO0 FDFE For PEC data transfers the internal RAM can be accessed independent of the contents of the DPP registers via the PEC source and destination pointers The upper 256 Byte of the internal RAM 00 FDO0O through 00 FDFF and the GPRs of the current bank are provided for single bit storage and thus they are bit addressable System Stack The system stack may be defined within the internal RAM The size of the system stack is controlled by bitfield STKSZ in register SYSCON see table below lt STKSZ gt Stack Size Words Internal RAM Addresses Words 000p 256 00 FBFE 00 FA00 Default after Reset 001g 128 O0 FBFE 00 FB00 010g 64 00 FBFE 00 FB80y 011g 32 00 FBFE 00 FBCO 100p 512 00 FBFE 00 F800 101 Reserved Do not use this combination 110p Reserved Do not use this combination 1115 1024 00 FDFEy 00 F600 Note No circular stack For all system stack operations the on chip RAM is accessed via the Stack Pointer SP r
436. uction cycle the highest priority trap is serviced see table in section Interrupt System Structure PSW CSP in segmentation mode and IP are pushed on the internal system stack and the CPU level in register PSW is set to the highest possible priority level ie level 15 disabling all interrupts The CSP is set to code segment zero if segmentation is enabled A trap service routine must be terminated with the RETI instruction Semiconductor Group 5 24 SIEMENS Interrupt and Trap Functions C167 The eight hardware trap functions of the C167 are divided into two classes Class A traps are external Non Maskable Interrupt NMI Stack Overflow Stack Underflow trap These traps share the same trap priority but have an individual vector address Class B traps are Undefined Opcode Protection Fault Illegal Word Operand Access Illegal Instruction Access Illegal External Bus Access Trap These traps share the same trap priority and the same vector address The bit addressable Trap Flag Register TFR allows a trap service routine to identify the kind of trap which caused the exception Each trap function is indicated by a separate request flag When a hardware trap occurs the corresponding request flag in register TFR is set to 1 TFR FFAC D64 SFR Reset Value 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Function ILLBUS Illegal External Bus Access Flag An exter
437. uctions which implicitly access the system stack the SP register is either decremented or incremented as specified For branch instructions the Instruction Pointer and the Code Segment Pointer are updated with the desired branch target address provided that the branch is taken 3rd 5EXECUTE In this stage an operation is performed on the previously fetched operands in the ALU Additionally the condition flags in the PSW register are updated as specified by the instruction All explicit writes to the SFR memory space and all auto increment or auto decrement writes to GPRs used as indirect address pointers are performed during the execute stage of an instruction too 4th WRITE BACK In this stage all external operands and the remaining operands within the internal RAM space are written back A particularity of the C167 are the so called injected instructions These injected instructions are generated internally by the machine to provide the time needed to process instructions which cannot be processed within one machine cycle They are automatically injected into the decode stage of the pipeline and then they pass through the remaining stages like every standard instruction Program interrupts are performed by means of injected instructions too Although these internally injected instructions will not be noticed in reality they are introduced here to ease the explanation of the pipeline in the following Sequential Instruction Processi
438. ue is continuously compared with the contents of the allocated timer TO T1 or T7 T8 If the current timer contents match the compare value an appropriate output signal which is based on the selected compare mode can be generated at the corresponding output pin CCxlO except for CC241O CC271O and the associated interrupt request flag CCxIR is set which can generate an interrupt request if enabled As for capture mode the compare registers are also processed sequentially during compare mode When any two compare registers are programmed to the same compare value their corresponding interrupt request flags will be set to 1 and the selected output signals will be generated within 8 CPU clock cycles after the allocated timer is incremented to the compare value Further compare events on the same compare value are disabled until the timer is incremented again or written to by software After a reset compare events for register CCx will only become enabled if the allocated timer has been incremented or written to by software and one of the compare modes described in the following has been selected for this register The different compare modes which can be programmed for a given compare register CCx are selected by the mode control field CCMODx in the associated capture compare mode control register In the following each of the compare modes including the special double register mode is discussed in detail Compare Mode 0 This is
439. uest flags CC15IC CCOIC CC15IR CCOIR CAPCOMI interrupt request flags PWMIC PWMIR PWM module interrupt request flag TFR TFR 15 14 13 Class A trap flags TFR TFR 7 3 2 1 0 Class B trap flags P2 P2 15 P2 0 All bits of Port 2 P7 P7 7 P7 0 All bits of Port 7 P8 P8 7 P8 0 All bits of Port 8 XPyIC y 3 0 XPyIR yz3 0 X Peripheral y interrupt request flag Y 106 protected bits Semiconductor Group 2 17 SIEMENS Memory Organization C167 3 Memory Organization The memory space of the C167 is configured in a Von Neumann architecture This means that code and data are accessed within the same linear address space All of the physically separated memory areas including internal ROM Flash where integrated internal RAM the internal Special Function Register Areas SFRs and ESFRs the address areas for integrated XBUS peripherals eg XRAM or CAN module and external memory are mapped into one common address space The C167 provides a total addressable memory space of 16 MBytes This address space is arranged as 256 segments of 64 KBytes each and each segment is again subdivided into four data pages of 16 KBytes each see figure below FF FFFF OO FFFF Segment Data Page 1023 00 F 000 FF 0000 Data Page 3 00 E000 Segment External 00 C000j FE 0000 Menon Data Page2 00 8000 4 Data Page 1 Internal ROM 00 4000 Area Data Page 0 00 0000 Address m System Segment 0 16 MByte
440. ult is stored in a temporary buffer and the next conversion is suspended ADST and ADBSY will remain set in the meantime but no end of conversion interrupt will be generated After reading the previous value from ADDAT the temporary buffer is copied into ADDAT generating an ADCIR interrupt and the suspended conversion is started This mechanism applies to both single and continuous conversion modes Note While in standard mode continuous conversions are executed at a fixed rate determined by the conversion time in Wait for ADDAT Read Mode there may be delays due to suspended conversions However this only affects the conversions if the CPU or PEC cannot keep track with the conversion rate Conversion of Channel Write ADDAT ADDAT Full Temp Latch Full Generate Interrupt Hold Result K Request Temp Latch Read of ADDAT Result of Channel 3 2 1 0 MCA01970 Figure 16 4 Wait for Read Mode Example Semiconductor Group 16 6 SIEMENS The Analog Digital Converter C167 Channel Injection Mode Channel Injection Mode allows the conversion of a specific analog channel also while the ADC is running in a continuous or auto scan mode without changing the current operating mode After the conversion of this specific channel the ADC continues with the original operating mode Channel Injection mode is enabled by setting bit ADCIN in register ADCON and requires the Wait for ADDAT Read Mode ADWR 1
441. up 9 24 SIEMENS The General Purpose Timer Units C167 Timer T5 in Counter Mode Counter mode for the auxiliary timer T5 is selected by setting bit field T5M in register T5CON to 001g In counter mode timer T5 can be clocked either by a transition at the external input pin T5IN or by a transition of timer T6 s output toggle latch T6OTL Edge Select Bo o qe e Auxiliary Timer Tx r F diis P3 5 Up Down TxUD 0 MUX TxEUD EXOR 1 P5 15 o m P 7 x 5 P5 14 TxUDE MCB02221 Figure 9 16 Block Diagram of Auxiliary Timer T5 in Counter Mode The event causing an increment or decrement of the timer can be a positive a negative or both a positive and a negative transition at either the input pin or at the toggle latch T6OTL Bit field T5I in control register T5CON selects the triggering transition see table below Semiconductor Group 9 25 SIEMENS The General Purpose Timer Units C167 GPT2 Auxiliary Timer Counter Mode Input Edge Selection T5l Triggering Edge for Counter Increment Decrement X00 None Counter T5 is disabled 0 0 1 Positive transition rising edge on T5IN 010 Negative transition falling edge on T5IN 01 1 Any transition rising or falling edge on T5IN 101 Positive transition rising edge of output toggle latch T6OTL 110 Negative transition falling edge of output toggle latch T6OTL 111 Any transition rising or falling edge of output toggle latch T6OT
442. upt always corresponds to the register that caused the match Note If a match occurs simultaneously for both register CCx and register CCz of the register pair pin CCxIO will be toggled only once but two separate compare interrupt requests will be generated one for vector CCxINT and one for vector CCzINT Semiconductor Group 14 18 SIEMENS The Capture Compare Units C167 In order to use the respective port pin as compare signal output pin CCxlO for compare register CCx in double register compare mode this port pin must be configured as output ie the corresponding direction control bit must be set to 1 With this configuration the output pin has the same characteristics as in compare mode 1 CCIR sut CCxIR R t Compare Reg CCx CCMODx cen gt eques Mode 1 gt gt Interrupt Port CAPCOM Timer Ty TYR Request cc ice J coxo oggle Interrupt Lo Request MCB02022 Figure 14 10 Double Register Compare Mode Block Diagram In this configuration example the same timer allocation was chosen for both compare registers but each register may also be individually allocated to one of the two timers of the respective CAPCOM unit In the timing example for this compare mode below the compare values in registers CCx and CCz are not modified Note The pins CCzlO which do not serve for double register compare mode may be used for general purpose IO Semiconductor Group 14 19 SIEMENS The
443. us and is switched to the line labeled Alternate Data Output via a multiplexer The alternate data can be the 16 bit intrasegment address or the 8 16 bit data information The incoming data on PORTO is read on the line Alternate Data Input While an external bus mode is enabled the user software should not write to the port output latch otherwise unpredictable results may occur When the external bus modes are disabled the contents of the direction register last written by the user becomes active The figure below shows the structure of a PORTO pin Write DPOH y DPOL y Alternate Direction Direction Latch Read DPOH y DPOL y Alt i ernate Function 1 Enable Write POH y POL y Alternate Data gt Output Port Output Output Latch Buffer Read POH y POL y I n 1 e r n a w MCB02231 Figure 6 5 Block Diagram of a PORTO Pin Semiconductor Group 6 7 SIEMENS Parallel Ports C167 6 2 PORTI The two 8 bit ports P1H and P1L represent the higher and lower part of PORT1 respectively Both halfs of PORT1 can be written eg via a PEC transfer without effecting the other half If this port is used for general purpose IO the direction of each line can be configured via the corresponding direction registers DP1H and DP1L P1L FF04 824 SFR Reset Value 00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 i 0 P1L 7 P1L 6 P1L 5 P1L 4 P1L 3 P1L 2 P1L 1 P1L O M P1H
444. us configuration BTYP for the address windows BUSCONA BUSCON 1 is selected via software typically during the initialization of the system The bus configuration BTYP for the default address range BUSCONO is selected via PORTO during reset provided that pin EA is low during reset Otherwise BUSCONO may be programmed via software just like the other BUSCON registers The 16 MByte address space of the C167 is divided into 256 segments of 64 KByte each The 16 bit intra segment address is output on PORTO for multiplexed bus modes or on PORT1 for demultiplexed bus modes When segmentation is disabled only one 64 KByte segment can be used and accessed Otherwise additional address lines may be output on Port 4 and or several chip select lines may be used to select different memory banks or peripherals These functions are selected during reset via bitfields SALSEL and CSSEL of register RPOH respectively Note Bit SGTDIS of register SYSCON defines if the CSP register is saved during interrupt entry segmentation active or not segmentation disabled Semiconductor Group 8 2 SIEMENS The External Bus Interface C167 Multiplexed Bus Modes In the multiplexed bus modes the 16 bit intra segment address as well as the data use PORTO The address is time multiplexed with the data and has to be latched externally The width of the required latch depends on the selected data bus width ie an 8 bit data bus requires a byte latch the addre
445. utine Indirect addressing provides a mechanism of accessing data referenced by data pointers which are passed to the subroutine In addition two instructions have been implemented to allow one parameter to be passed on the system stack without additional software overhead The PCALL push and call instruction first pushes the reg operand and the IP contents onto the system stack and then passes control to the subroutine specified by the caddr operand When exiting from the subroutine the RETP return and pop instruction first pops the IP and then the reg operand from the system stack and returns to the calling program Cross Segment Subroutine Calls Calls to subroutines in different segments require the use of the CALLS call inter segment subroutine instruction This instruction preserves both the CSP code segment pointer and IP on the system stack Upon return from the subroutine a RETS return from inter segment subroutine instruction must be used to restore both the CSP and IP This ensures that the next instruction after the CALLS instruction is fetched from the correct segment Note lt is possible to use CALLS within the same segment but still two words of the stack are used to store both the IP and CSP Providing Local Registers for Subroutines For subroutines which require local storage the following methods are provided Alternate Bank of Registers Upon entry into a subroutine it is possible to specify a new
446. ve and a negative transition at pin TOIN alternate input function of port pin P3 0 or T7IN alternate input function of port pin P2 15 respectively can be selected to cause an increment of TO T7 When T1 or T8 is programmed to run in counter mode bit field Txl is used to enable the overflows underflows of timer T6 as the count source This is the only option for T1 and T8 and it is selected by the combination Txl X00g When bit field Txl is programmed to any other combination the respective timer T1 or T8 will stop When TO or T7 is programmed to run in counter mode bit field Txl is used to select the count source and transition if the source is the input pin which should cause a count trigger see description of TxyCON for the possible selections Note In order to use pin TOIN or T7IN as external count input pin the respective port pin must be configured as input ie the corresponding direction control bit DP3 0 or DP2 15 must be cleared 0 If the respective port pin is configured as output the associated timer may be clocked by modifying the port output latches P3 0 or P2 15 via software eg for testing purposes The maximum external input frequency to TO or T7 in counter mode is fopy 16 1 25 MHz 20 MHz fcpy To ensure that a signal transition is properly recognized at the timer input an external count input signal should be held for at least 8 CPU clock cycles before it changes its level again The incremented coun
447. ver general purpose IO is possible in all cases Note The fast external interrupt inputs are sampled every 50 ns The interrupt request arbitration and processing however is executed every 200 ns both 20 MHz CPU clock Semiconductor Group 5 23 SIEMENS Interrupt and Trap Functions C167 5 7 Trap Functions Traps interrupt the current execution similar to standard interrupts However trap functions offer the possibility to bypass the interrupt system s prioritization process in cases where immediate system reaction is required Trap functions are not maskable and always have priority over interrupt requests on any priority level The C167 provides two different kinds of trapping mechanisms Hardware traps are triggered by events that occur during program execution eg illegal access or undefined opcode software traps are initiated via an instruction within the current execution flow Software Traps The TRAP instruction is used to cause a software call to an interrupt service routine The trap number that is specified in the operand field of the trap instruction determines which vector location in the address range from 00 0000 through 00 01FC will be branched to Executing a TRAP instruction causes a similar effect as if an interrupt at the same vector had occurred PSW CSP in segmentation mode and IP are pushed on the internal system stack and a jump is taken to the specified vector location When segmentation is enabl
448. ver use the same data frame format and the same baud rate Data is transmitted on pin TXDO P3 10 and received on pin RXDO P3 11 These signals are alternate functions of Port 3 pins Reload Register CPU Clock jd Las Baud Rate Timer SOR SOPE SOM SOSTP SOFE A SOOE Clock SORIR Dire Int Serial Port Control SOTIR ee Int RXDO P3 11 ie Error Int Shift Clock Request Receive Shift Register TXDO0 P3 10 Receive Buffer Reg Transmit Buffer Reg SORBUF SOTBUF Internal Bus gt MCB02219 Figure 10 2 Asynchronous Mode of Serial Channel ASCO Semiconductor Group 10 4 Sl EM ENS The Asynchronous Synchronous Serial Interface C167 Asynchronous Data Frames 8 bit data frames either consist of 8 data bits D7 DO S0Mz 001 5 or of 7 data bits D6 DO plus an automatically generated parity bit SOM 011 Parity may be odd or even depending on bit SOODD in register SOCON An even parity bit will be set if the modulo 2 sum of the 7 data bits is 1 An odd parity bit will be cleared in this case Parity checking is enabled via bit SOPEN always OFF in 8 bit data mode The parity error flag SOPE will be set along with the error interrupt request flag if a wrong parity bit is received The parity bit itself will be stored in bit SORBUF 7 2nd DO D1 D2 D3 D4 D5 D7 Stoo Sto Asynchronous 8 bit Data Frames Figure 10 3 9 bit data frames either consist of 9 data bits D8
449. vice controls the data transfer by generating the shift clock while the slave devices receive it Due to the fact that all transmit and receive pins are connected to the one data exchange line serial data may be moved between arbitrary stations Similar to full duplex mode there are two ways to avoid collisions on the data exchange line only the transmitting device may enable its transmit pin driver the non transmitting devices use open drain output and only send ones Since the data inputs and outputs are connected together a transmitting device will clock in its own data at the input pin MRST for a master device MTSR for a slave By these means any corruptions on the common data exchange line are detected where the received data is not equal to the transmitted data Semiconductor Group 11 8 SIEM ENS The High Speed Synchronous Serial Interface C167 Master Device 1 Device 2 Shift Register Shift Register Common Transmit Receive Device 3 Line Shift Register h MCA01965 Figure 11 5 SSC Half Duplex Configuration Continuous Transfers When the transmit interrupt request flag is set it indicates that the transmit buffer SSCTB is empty and ready to be loaded with the next transmit data If SSCTB has been reloaded by the time the current transmission is finished the data is immediately transferred to the shift register and the next transmission will start without any additional delay On the
450. xiliary timers can be concatenated with the core timer or they may be used as reload or capture registers in conjunction with the core timer Note The auxiliary timers have no output toggle latch and no alternate output function The individual configuration for timers T2 and T4 is determined by their bitaddressable control registers T2CON and T4CON which are both organized identically Note that functions which are present in all 3 timers of block GPT1 are controlled in the same bit positions and in the same manner in each of the specific control registers T2CON FF40 AOp SFR Reset Value 0000 15 14 13 12 1i 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw T4CON FF44 A24 SFR Reset Value 0000 15 14 13 12 1i 10 9 8 7 6 5 4 3 2 1 0 T4 rw rw rw rw rw Bit Function Txl Timer x Input Selection Depends on the Operating Mode see respective sections TxM Timer x Mode Control Basic Operating Mode 000 Timer Mode 001 Counter Mode 010 Gated Timer with Gate active low 011 Gated Timer with Gate active high 100 Reload Mode 101 Capture Mode 11X Reserved Do not use this combination TxR Timer x Run Bit TxR 2 0 Timer Counter x stops TxR 1 Timer Counter x runs TxUD Timer x Up Down Control TxUDE Timer x External Up Down Enable For the effects of bits TXUD and TxUDE refer to the direction table see T3 section Semiconductor Group 9 8 SIEMENS The General Purp
451. xternal Bus Interface C167 8 2 Programmable Bus Characteristics Important timing characteristics of the external bus interface have been made user programmable to allow to adapt it to a wide range of different external bus and memory configurations with different types of memories and or peripherals The following parameters of an external bus cycle are programmable ALE Control defines the ALE signal length and the address hold time after its falling edge Memory Cycle Time extendable with 1 15 waitstates defines the allowable access time Memory Tri State Time extendable with 1 waitstate defines the time for a data driver to float Read Write Delay Time defines when a command is activated after the falling edge of ALE READY Control defines if a bus cycle is terminated internally or externally Note Internal accesses are executed with maximum speed and therefore are not programmable External acceses use the slowest possible bus cycle after reset The bus cycle timing may then be optimized by the initialization software MCT02225 ALECTL Figure 8 5 Programmable External Bus Cycle Semiconductor Group 8 10 SIEMENS The External Bus Interface C167 ALE Length Control The length of the ALE signal and the address hold time after its falling edge are controlled by the ALECTLx bits in the BUSCON registers When bit ALECTL is set to 1
452. xternal events are applied to pin CAPIN When an external event occurs the timer T5 contents are latched into register CAPREL and timer T5 is cleared T5CLR 1 Thus register CAPREL always contains the correct time between two events measured in timer T5 increments Timer T6 which runs in timer mode counting down with a frequency of eg fopy 4 uses the value in register CAPREL Semiconductor Group 9 30 SIEMENS The General Purpose Timer Units C167 to perform a reload on underflow This means the value in register CAPREL represents the time between two underflows of timer T6 now measured in timer T6 increments Since timer T6 runs 8 times faster than timer T5 it will underflow 8 times within the time between two external events Thus the underflow signal of timer T6 generates 8 ticks Upon each underflow the interrupt request flag T6IR will be set and bit T6OTL will be toggled The state of T6OTL may be output on pin TGOUT This signal has 8 times more transitions than the signal which is applied to pin CAPIN The underflow signal of timer T6 can furthermore be used to clock one or more of the timers of the CAPCOM units which gives the user the possibility to set compare events based on a finer resolution than that of the external events Interrupt Control for GPT2 Timers and CAPREL When a timer overflows from FFFF to 0000 when counting up or when it underflows from 0000 to FFFF when counting down its interru
453. y 0000 ONES b FF1E 8Fy Constant Value 1 s Register read only FFFFy T78CON Jb FF20 904 CAPCOM Timer 7 and 8 Control Register 00004 CCM4 b FF22 914 CAPCOM Mode Control Register 4 00004 CCM5 b FF24 924 CAPCOM Mode Control Register 5 00004 Semiconductor Group 20 16 SIEMENS The Register Set C167 Name Physical 8 Bit Description Reset Address Address Value CCM6 b FF264 934 CAPCOM Mode Control Register 6 00004 CCM7 b FF28 944 CAPCOM Mode Control Register 7 00004 PWMCONO b FF30 984 PWM Module Control Register 0 0000 PWMCON1 b FF32 994 PWM Module Control Register 1 0000 T2CON b FF404 AOH GPT1 Timer 2 Control Register 0000 T3CON b FF42 Aly GPT1 Timer 3 Control Register 00004 T4CON b FF44 A24 GPT1 Timer 4 Control Register 00004 T5CON b FF464 A3y GPT2 Timer 5 Control Register 0000 T6CON b FF484 A44 GPT2 Timer 6 Control Register 0000 TO1CON b FF504 A84 CAPCOM Timer 0 and Timer 1 Control Register 00004 CCMO b FF524 A9 CAPCOM Mode Control Register 0 0000 CCM1 b FF54 AAy CAPCOM Mode Control Register 1 00004 CCM2 b FF56y ABy CAPCOM Mode Control Register 2 0000 CCM3 b FF58 ACy CAPCOM Mode Control Register 3 0000 T2IC b FF60 BOH GPT1 Timer 2 Interrupt Control Register 00004 T3IC b FF62 Bi GPT1 Timer 3 Interrupt Control Register 00004 TAIC b FF644 B2y GPT1 Timer 4 Interrupt Control Register
454. y ene ernate Function lt Enable Write P1H y P1L y Alternate 0255025 Port Output Output Read P1H y P1L y Cc Ww Clock i Input Latch MCB02232 Figure 6 7 Block Diagram of a PORT1 Pin Semiconductor Group 6 10 SIEMENS Parallel Ports C167 6 3 Port2 If this 16 bit port is used for general purpose IO the direction of each line can be configured via the corresponding direction register DP2 Each port line can be switched into push pull or open drain mode via the open drain control register ODP2 P2 FFCO EO SFR Reset Value 00004 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bit Function P2 y Port data register P2 bit y DP2 FFC2 Elp SFR Reset Value 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DP2 DP2 DP2 DP2 DP2 DP2 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bit Function DP2 y Port direction register DP2 bit y DP2 y 0 Port line P2 y is an input high impedance DP2 y 1 Port line P2 y is an output ODP2 F1C2 Elp ESFR Reset Value 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PHP aa a ar a r pe er ar Para 15 14 11 10 9 8 7 6 A 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bit Function ODP2 y Port 2 Open Drain control register bit y ODP2 y 0 Port line P2 y output driver in push pull mode ODP2 y 1 Port line P2 y output d
455. ying to leave the current segment Data Pages are contiguous blocks of 16 KByte each They are referenced via the data page pointers DPP3 0 and via an explicit data page number for data accesses overriding the standard DPP scheme Each DPP register can select one of the possible 1024 data pages The DPP register that is used for the current access is selected via the two upper bits of the 16 bit data address Subsequent 16 bit data addresses that cross the 16 KByte data page boundaries therefore will use different data page pointers while the physical locations need not be subsequent within memory Semiconductor Group 3 12 SIEMENS The Central Processing Unit CPU C167 4 The Central Processing Unit CPU Basic tasks of the CPU are to fetch and decode instructions to supply operands for the arithmetic and logic unit ALU to perform operations on these operands in the ALU and to store the previously calculated results As the CPU is the main engine of the C167 controller it is also affected by certain actions of the peripheral subsystem Since a four stage pipeline is implemented in the C167 up to four instructions can be processed in parallel Most instructions of the C167 are executed in one machine cycle ie 100 ns 20 MHz CPU clock due to this parallelism This chapter describes how the pipeline works for sequential and branch instructions in general and which hardware provisions have been made to speed the execution of jump i
456. ytes of the memory can be enabled independent from each other or together when accessing words When writing bytes to an external 16 bit device which has a single CS input but two WR enable inputs for the two bytes the EBC can directly generate these two write control signals This saves the external combination of the WR signal with AO or BHE In this case pin WR serves as WRL write low byte and pin BHE serves as WRH write high byte Bit WRCFG in register SYSCON selects the operating mode for pins WR and BHE The respective byte will be written on both data bus halfs When reading bytes from an external 16 bit device whole words may be read and the C167 automatically selects the byte to be input and discards the other However care must be taken when reading devices that change state when being read like FIFOs interrupt status registers etc In this case individual bytes should be selected using BHE and AO Bus Mode Transfer Rate Speed factor System Requirements Free IO Lines for byte word dword access 8 bit Multiplexed Very low 1 5 3 6 Low 8 bit latch byte bus P1H P1L 8 bit Demultipl Low 1 2 4 Very low no latch byte bus POH 16 bit Multiplexed High 1 5 1 5 3 High 16 bit latch word bus P1H P1L 16 bit Demultipl Very high 1 172 Low no latch word bus Note PORT1 gets available for general purpose IO when none of the BUSCON registers selects a demultiplexed bus mode

C167 Derivatives

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