Home

AD520 and ADA520 MANUAL

Contents

1. 82C54 OPERATIONAL DESCRIPTION General After power up the state of the 82C54 is undefined The Mode count value and output of all Counters are undefined How each Counter operates is determined when it is programmed Each Counter must be programmed before it can be used Unused counters need not be programmed Control Word Format A Ao 11 CS 0 RD 1 WA 0 D De Ds Ds Programming the 82C54 Counters are programmed by writing a Contro Word and then an initial count The control word format is Shown in Figure 7 All Control Words are written into the Control Word Register which is selected when Ay Ag 11 The Control Word itself specifies which Counter is being programmed By contrast initial counts are written into the Coun ters not the Control Word Register The Ay Ag in puts are used to select the Counter to be written into The format of the initia count is determined by the Control Word used Da D2 D Do sci sco rw wo m2 Tw mo eco SC Select Counter SC1 Sco O SelectGountero 1 Select Counters Select Counter 2 Read Back Command See Read Operations EE RW Read Write RW1 RWO Counter Latch Command see Read Operations o 1 Read Write least significant byte only KEEN Read Write most significant byte only Read Write least significant byte first then most significant byte NOTE Don t care bits X should be O to insu
2. i f i RV CLOCK AND GATE Parameter Min Max Min Max Clock Period 125 DC High Pulse Width 60 Low Pulse Width 609 es lock Rise Time DR tetr tpwH tpwL 4 Q lock Fall Time zu ate Width High 50 ate Width Low 50 ate Setup Time to CLK T 50 Gate Hold Time After CLK T 502 Output Delay trom GLK 100 mo utput Delay from Gate twc LK Delay for Loading 4 ate Delay for Sampling 4 MEAR WE UT Delay from Mode Write RE o ES E r A il O ie l to CLK Set Up for Count Latch NOTES 2 In Modes 1 and 5 triggers are sampled on each rising clock edge A second trigger within 120 ns 70 ns for the 82C54 2 of the rising clock edge may not be detected 3 Low going glitches that violate tpwu tpwL may cause errors requiring counter reprogramming 4 Except for Extended Temp See Extended Temp A C Characteristics below 5 Sampled not 100 tested TA 25 C 6 If CLK present at Twc min then Count equals N 2 CLK pulses Twc max equals Count N 1 CLK pulse Twc min to Twc max count will be either N 1 or N 2 CLK pulses 7 In Modes 1 and 5 if GATE is present when writing a new Count value at Twa min Counter will not be triggered at Twa max Counter will be triggered 8 If CLK present when writing a Counter Latch or ReadBack Command at Toy min CLK will be reflected in count value latched at Tc max CLK will not be reflected i
3. P4 Single Ended Differential Analog Inputs Factory Setting D 8 Single Ended This header connector shown in Figure 1 2 is used with switch S2 to configure the ADAS20 for 8 differential 8 single ended with dedicated grounds or 16 single ended analog input channels When operating in the 16 input single ended mode three jumpers must be installed across the SE pins When operating in the 8 single ended with dedicated grounds or 8 differential mode three jumpers must be installed across the D pins DO NOT install jumpers across both SE and D pins at the same time SE SE SE P4 Fig 1 2 Single Ended Differential Analog Input Signal Type Jumpers P4 PS 8254 Timer Counter Clock Sources Factory Settings CLKO XTAL CLK1 OUTO CLK2 OUT1 This header connector shown in Figure 1 3 lets you select the clock sources for the 8254 timer counters TCO TC1 and TC2 The factory setting cascades all three timer counters with the clock source for TCO being the on board 8 MHz oscillator the output of TCO providing the clock for TC1 and the output of TC1 providing the clock for TC2 You can connect any or all of the sources to an external clock input through the P2 and P3 I O connectors or you can set TC1 and TC2 to be clocked by the 8 MHz oscillator Figure 1 4 shows a block diagram of the timer counter circuitry to help you with these connections NOTE When installing jumpers on this header make sure that only one jumper
4. BOARD 1 Stop Conversion PC6 O BOARD 1 Check Status Status 0 BOARD 1 BOARD 2 Set PC7 0 Set PC7 0 to enable MSB to enable MSB BOARD 1 BOARD 2 Read PPI Port A Read PPI Port A for MSB for MSB BOARD 1 BOARD 2 Set PC7 1 Set PC7 1 to enable LSB to enable LSB BOARD 1 BOARD 2 Yes CD for LSB for LSB No Fig 4 5 Cascaded Boards Single Convert Mode Flow Diagram 4 17 Interrupts What Is an Interrupt An interrupt is an event that causes the processor in your computer to temporarily halt its current process and execute another routine Upon completion of the new routine control is returned to the original routine at the point where its execution was interrupted Interrupts are very handy for dealing with asynchronous events events that occur at less than regular intervals Keyboard activity is a good example your computer cannot predict when you might press a key and it would be a waste of processor time for it to do nothing while waiting for a keystroke to occur Thus the interrupt scheme is used and the processor proceeds with other tasks Then when a keystroke does occur the keyboard interrupts the processor and the processor gets the keyboard data places it in memory and then returns to what it was doing before it was interrupted Other common devices that use interrupts are modems disk drives and mice Your ADAS20 board can interrupt the processor when a var
5. MODE 1 PORT 8 INTR interrupt Request A high on this output can be used to interrupt the CPU when an output device has accepted data transmitted by the CPU INTR is set when ACK is a one OBF is a one and INTE is a one It is reset by the falling edge of WR CONTROL WORD D Os Os Da D O D Do L DEED T p INTE A Controlled by bit set reset of PCs INTE B Controlled by bit set reset of PC 231256 16 Figure 11 MODE 1 Strobed Output 3 135 intel 82C55A Combinations of MODE 1 Port A and Port B can be individually defined as input or output in Mode 1 to support a wide variety of strobed IZO applications CONTROL WORD By De D D D D O O HUUUUH0e _ Y INPUT PORT A STROBED INPUT PORT B STROBED OUTPUT CONTROL WORD D De Ds D D Dz O O BOM PCs 1 INPUT RD PORT A STROBED OUTPUT PORT B STROBED INPUT 23125617 Figure 12 Combinations of MODE 1 Operating Modes MODE 2 Strobed Bidirectional Bus 1 O This functional configuration provides a means for com municating with a peripheral device or structure on a single 8 bit bus for both transmitting and receiving data bidirectional bus 1 0 Handshaking signals are provided to maintain proper bus flow discipline in a similar manner to MODE 1 Interrupt generation and enable disable functions are also available MODE 2 Basic Functional Definitions e Used
6. MODE 2 AND MODE 0 INPUT CONTROL WORD O D Ds Da D3 O D Do LLKP T wel la 1a INPUT MODE 2 AND MODE 1 OUTPUT CONTROL WORD D De D O O D O O LE Kr Le 82C55A MODE 2 AND MODE O OUTPUT CONTROL WORD D Dy O D Dy Dz O Dy DSL e Le fra Pao 1 INPUT MODE 2 AND MODE 1 INPUT CONTROL WORD O De O De Ds Dz O De pp bd L DI 231256 21 Figure 16 MODE Y Combinations 3 138 82C55A Mode Definition Summary Special Mode Combination Considerations There are several combinations of modes possible For any combination some or all of the Port C lines are used for control or status The remaining bits are either inputs or outputs as defined by a Set Mode command During a read of Port C the state of all the Port C lines except the ACK and STB lines will be placed on the data bus in place of the ACK and STB line states flag status will appear on the data bus in the PC2 PC4 and PC6 bit positions as illustrated by Figure 18 Through a Write Port C command only the Port C pins programmed as outputs in a Mode 0 group can be written No other pins can be affected by a Write Port C command nor can the interrupt enable flags be accessed To write to any Port C output pro grammed as an output in a Mode 1 group or to GROUP A ONLY MODE 0 OR MODE 1 ONLY change an interrupt enable flag the Set Reset Port C Bit command mu
7. ADA520 User s Manual Real Time Devices Inc ULL Accessing the Analog World s ISO9001 and AS9100 Certified ADAS20 meem User s Manual II REAL TIME DEVICES INC 820 North University Drive Post Office Box 906 State College Pennsylvania 16804 USA Phone 814 234 8087 FAX 814 234 5218 Published by Real Time Devices Inc 820 N University Dr P O Box 906 State College PA 16804 USA Copyright O 1992 by Real Time Devices Inc All rights reserved Printed in U S A 9231 TABLE OF CONTENTS Analog to Digital Conversion sasservee sneren sneerde ee ete a i 3 Digital to Analog Conversion sss esse onale RARO o SR RA RE i 3 Dial VO nenne A i 3 What Comes With Your Board na A PS DE E ects i4 A aande eenen ede SL Rie i 4 Application Software and Drivers esan i 4 FARO WARE ACCESSORIES aats aandoen A ee te re i4 Using This A O A aE E A cet 4 WIEN VOW Need Help A E N i4 CHAPTER 1 BOARD SETTINGS ee E Factory Configured Switch and Jumper Settings ssssssssssssssssssssessesssssesssasssssecsssssssssssstssestasssssescsscccsescccosccose 1 3 P4 Single Ended Differential Analog Inputs Factory Setting Single Ended aan 1 4 P5 8254 Timer Counter Clock Sources Factory Settings CLKO XTAL CLK1 OUTO CLK2 OUT1I 1 4 P6 DAC 1 Output Voltage Range Factory Setting 5 to 5 VOWS ccccccsecssssesssssssssssossecosssecceecccosescceeeccsseces 1 5
8. Mode 5 Hardware Triggered Strobe Retriggerable The output is initially high Counting is triggered by the rising edge of the gate input When the initial count has expired the output goes low for one clock pulse and then goes high again Digital VO The 8 PPI Port B and 24 buffered Ports A B and C TTL CMOS digital I O lines can be used to transfer data between the computer and external devices All 32 lines can have pull up pull down resistors installed as described in Chapter 1 On reset all 24 buffered digital 1 O lines are automatically set up as inputs Using pull up or pull down resistors will set the state of the inputs high or low After a reset you can set up the digital lines in each port to be inputs or outputs by writing the appropriate byte to BA 4 Bit 0 configures the lines of Port A as inputs or outputs bit 1 configures the lines of Port B and bit 2 configures the lines of Port C The remaining bits in the word are ignored so their states are irrelevant After the lines are configured as inputs or outputs you can set each line high or low by 4 23 writing the correct words to BA 5 Port A BA 6 Port B and BA 7 Port C Note that when you configure the lines as outputs they can be in any state their states are the same as the last data programmed If you are not using the pull up pull down resistor pack feature both inputs and outputs can be in any state at reset Writing to these ports will set the
9. 3 84 82C54 Block Diagram DATA BUS BUFFER This 3 state bi directional 8 bit buffer is used to in terface the 82C54 to the system bus see Figure 3 231244 4 Figure 3 Block Diagram Showing Data Bus Buffer and Read Write Logic Functions READ WRITE LOGIC The Read Write Logic accepts inputs from the sys tem bus and generates contro signals for the other functional blocks of the 82C54 A and Ay select one of the three counters or the Control Word Regis ter to be read from written into A iow on the RD input tells the 82C54 that the CPU is reading one of the counters A low on the WR input tells the 82C54 that the CPU is writing either a Control Word or an initial count Both RD and WR are qualified by CS RD and WR are ignored unless the 82C54 has been selected by holding CS low CONTROL WORD REGISTER The Control Word Register see Figure 4 is selected by the Read Write Logic when Ay Ag 11 If the CPU then does a write operation to the B2C54 the data is stored in the Control Word Register and is interpreted as a Control Word used to define the operation of the Counters The Control Word Register can only be written to status information is available with the Read Back Command Figure 4 Block Diagram Showing Control Word Register and Counter Functions COUNTER 0 COUNTER 1 COUNTER 2 These three functional blocks are identical in opera tion so only a single Counter wil
10. Fig 4 1 Setting the Gain to 100 Using Bit Set Reset Function 4 13 A D Conversion Modes The A D converter can perform conversions in two modes Single Convert and Continuous Convert Two lines from PPI port C PC6 and PCT are used to control the conversions These lines can be set by writing to PPI port C BA 2 or by using the single bit set reset function described in the previous section Setting the Gain and under BA 3 in the Defining the 1 0 Map section later in this chapter PC6 controls the Start Convert function Whenever PC6 is high conversions can be started PC7 determines which byte of the converted data the MSB or the LSB is to be read at PPI Port A When PC7 is low the MSB is read when it is high the LSB is read For each conversion the MSB is typically read first followed by the LSB Single Convert Mode The Single Convert mode lets you perform a single A D conversion each time you pulse the Start Convert line PC6 high Figure 4 1 shows the timing diagram for this mode and Figure 4 3 provides a flow diagram Start Convert Done l Status Status Converting Read Data nn 1 MSB LSB Fig 4 1 Single Convert Mode Timing Diagram Continuous Convert Mode The Continuous Convert mode lets you perform continuous A D conversions by keeping the Start Convert line PC6 high Figure 4 2 shows the timing diagram for this mode and Figure 4 4 provides a flow diagram Start Convert Done Don
11. 1 7 External Trigger In P8 P9 Interrupt Source and Channel Select Factory Setting OUT2 Interrupt Channels Disabled This header connector shown in Figure 1 8 lets you connect one of five interrupt sources to an interrupt channel IRQ2 through IRQ7 To connect the interrupt source to an interrupt channel you must install two jumpers on this header one across the desired source and a second across the desired IRQ channel The available sources are the end of convert signal EOC timer counter OUTI timer counter OUT2 PCO from the 8255 PPI and the external trigger available at P3 19 TRIGIN Figure 1 8a shows the factory setting with the IRQ jumper stored in a disabled position and Figure 1 8b shows OUT2 connected to IRQ3 Fig 1 8a Factory Setting IRQ disabled 335335555 dvoom DID IA DDDBDD2ABSSZE NW Sa HN G ZN 2 P9 Fig 1 8b OUT2 Connected to IRQ3 35535535 avd GQ m VID IDDI 285995285588 Do N 0 ZN Z Fig 1 8 Interrupt Source and Channel Select Jumper P9 S1 Base Address Factory Setting 300 hex 768 decimal One of the most common causes of failure when you are first trying your board is address contention Some of your computer s I O space is already occupied by internal I O and other peripherals When the ADA520 board attempts to use I O address locations already used by another device contention results and the board does not work To avoid this problem the ADA520 has
12. 168 out dx al Often assigning a range of bits is a mixture of setting and clearing operations You can set or clear each bit individually or use a faster method of first clearing all the bits in the range then setting only those bits that must be set using the method shown above for setting multiple bits in a port The following example shows how this two step operation is done Example Assign bits 3 4 and 5 in a port to 101 bits 3 and 5 set bit 4 cleared First read in the port and clear bits 3 4 and 5 by ANDing them with 199 Then set bits 3 and 5 by ORing them with 40 and finally write the resulting value back to the port In C this is programmed as v inportb port address v vyv amp 199 v v 40 outportb port_address v A final note Don t be intimidated by the binary operators AND and OR and try to use operators for which you have a better intuition For instance if you are tempted to use addition and subtraction to set and clear bits in place of the methods shown above DON T Addition and subtraction may seem logical but they will not work if you try to clear a bit that is already clear or set a bit that is already set For example you might think that to set bit 5 of a port you simply need to read in the port add 32 2 to that value and then write the resulting value back to the port This works fine if bit 5 is not already set But what happens when bit 5 is already set Bits O to 4 will be unaffect
13. Read back count and status of Counter O 1 jolo Read back status of Counter 1 Status latched for Counter 1 Read back status of Counters 2 1 Status latched for Counter 2 but not Counter 1 TSTS fofo Read back countot Counter Count latched tor Counter Read back count and status of Count latched for Counter 1 Counter 1 but not status ei TETE Read back status of Counter 1 Figure 13 Read Back Command Example 3 90 THIS ACTION A Write to the contro CAUSES word register Null count 1 B Write to the count u register CR 2 Null count 1 C New count is loaded B into CE CR CE Nuli count O 1 Only the counter specified by the control word will have its null count set to 1 Null count bits of other counters are unaffected 2 if the counter is programmed for two byte counts least significant byte then most significant byte null count goes to 1 when the second byte is written Figure 12 Null Count Operation If multiple status latch operations of the counter s are performed without reading the status al but the first are ignored i e the status that will be read is the status of the counter at the time the first status read back command was issued Both count and status of the selected counter s may be latched simultaneously by setting both COUNT and STATUS bits D5 D4 0 This is func tionally the same as issuing two separate read back commands at once and t
14. Similarly there are two 8 bit registers called CRy and CR for Count Register Both are normally referred to as one unit and called just CR When a new count is written to the Counter the count is stored in the CR and later transferred to the CE The Control Logic allows one register at a time to be loaded from the internal bus Both bytes are trans ferred to the CE simultaneously CRm and CR are cleared when the Counter is programmed In this way if the Counter has been programmed for one byte counts either most significant byte only or least significant byte only the other byte will be zero Note that the CE cannot be written into whenever a count is written it is written into the CR The Control Logic is also shown in the diagram CLK n GATE n and OUT n are all connected to the out side world through the Control Logic 82C54 SYSTEM INTERFACE The 82C54 is treated by the systems software as an array of peripheral I O ports three are counters and the fourth is a control register for MODE program ming Basically the select inputs Ag Ay connect to the Ag A address bus signals of the CPU The CS can be derived directly from the address bus using a linear select method Or it can be connected to the output of a decoder such as an Intel 8205 for larger sys tems A A E Be BB wm COUNTER COUNTER 0 1 COUNTER 2 OUT GATE CLK OUT GATE CLK OUT GATE CLK 231244 7 Figure 6 82C54 System Interface
15. do not use any DOS functions or routines that call DOS functions from within an ISR DOS is not reentrant that is a DOS function cannot call itself In typical programming this will not happen because of the way DOS is written But what about when using interrupts Then you could have a situation such as this in your program If DOS function X is being executed when an interrupt occurs and the interrupt routine makes a call to DOS function X then function X is essentially being called while it is already active Such a reentrancy attempt spells disaster because DOS functions are not written to support it This is a complex concept and you do not need to understand it Just make sure that you do not call any DOS functions from within your ISR The one wrinkle is that unfortunately it is not obvious which library routines included with your compiler use DOS functions A rule of thumb is that routines which write to the screen or check the status of or read the keyboard and any disk I O routines use DOS and should be avoided in your ISR The same problem of reentrancy exists for many floating point emulators as well meaning you may have to avoid floating point real math in your ISR 4 19 Note that the problem of reentrancy exists no matter what programming language you are using Even if you are writing your ISR in assembly language DOS and many floating point emulators are not reentrant Of course there are ways around this pr
16. nnen 10 volts max DOMINO UMB dass reias aan de xc ana Sa e en acess con 5 psec max AID GONVONROE zee nerede raean nerd ba ICL7109 A CRL desta aandeden Ed Dual slope integrating with auto zero POSTO ast edentate A IE 12 bits plus sign Conversion rate 60 Hz rejection ii 7 5 30 Hz switch selectable Conversion rate 50 Hz rejection cocoa 6 25 25 Hz switch selectable Relative accuracy gain 1 aaneen 1 bit Linearity gain 1 nnn 1 bit 7 5 Hz 3 bits 30 Hz E oneness O SU DT A 1 bit Digital VO debnaatenieeddvensd geria erssunsresnenssnnenennansennneenn CMOS 82055 Number of 8255 based lines nnn 8 input or output Logic compatibility nn TTUCMOS Configurable with optional I O pull up pull down resistors High level output Voltage nnen 4 2V min Low level output voltage nanne 0 45V max High level input voltage sss 2 2V min 5 5V max Low level input voltage sss 0 3V min 0 8V max Input load ds 10 pA Input capacitance CIN OR L corais ee hahai 10 pF Output capacitance CLOUT me MHZ n 20 pF Buffered Digital VO Number of buffered lines nnn 24 Logic compatibility sese TTL CMOS Configurable with optional I O pull up pull down resistors High level output voltage nanne 2 5V min Low level output voltage nnn 0 5V max High level input voltage nnn 2 2V min 5 5V max Low level input voltage nn 0 3V min 0 8V max High level output current SQUICS nnen 12 mA max Low
17. use these easy to follow instruc tions before you install the board in your computer Also note that by installing resistor packs at any or all of the four locations on the board RN2 RN3 RN4 and RN6 and solder ing a jumper between 5V and common or between ground and common in the associated pads for each resistor network you can configure each of the four groups of digital I O lines to be pulled up or pulled down This procedure is described at the end of this chapter 1 1 Factory Configured Switch and Jumper Settings Table 1 1 lists the factory settings of the user configurable jumpers and switches on the ADAS20 Figure 1 1 shows the board layout and the locations of the factory set jumpers The following paragraphs explain how to change the factory settings Table 1 1 Factory Settings Switch Jumper Function Controlled Factory Setting Sets 16 single ended or 8 single ended with 8 single ended with ground ground 8 differential analog input type used in 3 jumpers installed on D P4 conjunction with S2 pins Jumpers installed on CLKO XTAL CLK1 OUTO amp TCO TC2 CLK2 OUT1 pe Sets the D A output voltage range for DAC1 Sets the D A output voltage range for DAC2 Connects an external trigger for simultaneous triggering of cascaded boards Disabled not connected Connects 1 of 5 interrupt sources to an interrupt Jumper installed on OUT2 channel interrupt channels disabled Sets the base address
18. 3 1 3 2 4 1 4 2 4 3 4 4 4 5 4 6 5 1 Board Layout Showing Factory Configured Settings sssscssssssssssssossscesesseesessesssssesessnsnsessnsuscaceuseces 1 3 Single Ended Differential Analog Input Signal Type Jumpers P4 aen nanenersonseneene unseren vaneen 14 8254 Timer Counter Clock Source Jumpers PS ano neeaaea 1 4 8254 Timer Counter Circuit Block Diagram ne nsesesesevevernenovoneneneusveverseneneneveenenensuntsenss 1 5 DAC 1 Output Voltage Range Jumper P6 a seseunssenesursnenennenenneneneenensenenovsecersenersensvoensverns 1 5 DAC 2 Output Voltage Range Jumper PT asees 1 6 External Trigger In TT 1 6 Interrupt Source and Channel Select Jumper Pg sseni 1 7 Base Address Switch SH TT 1 7 Differential Single Ended Ground Switch S2 enesenn 1 8 A D Conversion Rate Switch SI sell 1 9 Pull up Pull down Resistor Circuitry nan sese 1 10 P2 and P3 I O Connector Pin Assignments naan anaeeeaenenenesnenesnenenceneneaneneneeenssn oneven ensenen 2 4 Single Ended Input Connections No Dedicated GND ssa 24 Single Ended Input Connections Dedicated GND sss 2 5 Differential Input Connections ad 2 6 Cascading Two Boards for Simultaneous Sampling sscsssssssssssessssssesnssssssessscsssssessesessanssessussecseessseee 2 7 ADAS20 Block Diagram innen edi Qu id 3 3 D A Converter Configuration for Improved Settling Time nesse 3 4 Single Convert Mode Timing Diagram essen 4 14 Continuous Convert Mode Timing Diagram nen se
19. 5 3 Calibration Trimpots 363 te mr in Ta EE HE EEEE 9 do 000008 aro 22922000 COR P PT call Eres 00000000 COR pocs llao E ss 90000000 B E sl CEO 66600000 o rl o 5 T Ef 9000000 00000000 EO om MO B0000000000000000005 mt E i 00 ER 5 o po alle Be 9000000 HEHE Mer 7000000 90 EFE bede ED 0 0 sos E 2299 aa DEI DDDODDDO p o fe oo ooo 000000090000 os ora fe TB esse us AD7237 O h E ee Hy lo Que esas mae EE 000000000000 2 prof ad 0000000 2020000000000 m nn EDED 600000000000 o oooo00000000 5 D 4 5000600000000 0000000000 Eo 5000000000 S 0000000 7415125 o 0000000 a we 0000 00000000000000000000 3 acaso FO nemen rend jn Ge 20000000 0000000 el ee ee O ISA Y 90000000 0000000 YU 000000000 LES So00000 M 00000000 8000000000 000900000000 omen else D XA S 0000000 1780000000 5000000000 000000000000 O pa EI 609006 o ne ED bs ACT 24S gts ED po 0000000000 117732839885 9000600060 E GO L 0000000000000000000B 00000000000000000000 5556660500 0000000000000000 na 00000000 u S Fig 5 2 Board Layout Showing Calibration Trimpots Offset Adjustment The offset adjustment compensates for the inherent offset output voltage of the programmable gain amplifier Four adjustments must made one for each gain setting To adjust the offset error connect O volts to a
20. 82C54 to be used as an event counter elapsed time indicator programmable one shot and in many other applications The 82C54 is fabricated on Intel s advanced CHMOS Ill technology which provides low power consumption with performance equal to or greater than the equivalent HMOS product The 82C54 is available in 24 pin DIP and 28 pin plastic leaded chip carrier PLCC packages OUT 1 OUTO GATES GND NE OUT OATENCLKt 231244 3 PLASTIC LEADED CHIP CARRIER Ctx 2 REGISTER bi J o 231244 1 Figure 1 82054 Block Diagram 231244 2 Diagrams are for pin reference only Package sizes are not to scale Figure 2 82C54 Pinout September 1969 3 83 Order Number 231244 005 a intel 82054 Table 1 Pin Description PinNumber_ eps PLCC O Data Bidirectional tri state data bus lines CLK O OUT 0 GATE o h N GATE 1 olle O Ciel em 21m 3 mw tw 17 _Clk2 18 a A1 Ao ER be N N 1 11 15 25 FUNCTIONAL DESCRIPTION General The 82C54 is a programmable interval tirner counter designed for use with Intel microcomputer systems Itis a general purpose multi timing element that can be treated as an array of I O ports in the system software The 82C54 solves one of the most common prob lems in any microcomputer system the generation of accurate time delays under software control In stead of setting up timing loops in software the pro grammer configures th
21. Cw 18 18803 o elolo 1181 UUUUHHHHL ele CW 16 188 a3 v JUVUUVVVUVUV he can E e DA E 231244 12 S822 Figure 19 Mode 4 MODE 5 HARDWARE TRIGGERED STROBE RETRIGGERABLE OUT will initially be high Counting is triggered by a rising edge of GATE When the initial count has ex pired OUT will go low for one CLK pulse and then go high again 3 94 After writing the Control Word and initial count the counter will not be loaded until the CLK pulse after a trigger This CLK pulse does not decrement the count so for an initial count of N OUT does not strobe low until N 1 CLK pulses after a trigger A trigger results in the Counter being loaded with the initial count on the next CLK pulse The counting sequence is retriggerable OUT will not strobe low for N 1 CLK puises after any trigger GATE has no effect on OUT If a new count is written during counting the current Counting sequence will not be affected If a trigger occurs after the new count is written but before the current count expires the Counter will be loaded with the new count on the next CLK pulse and counting will continue from there Cwets 60 Infebebebelslsle le 1818 Cwets 18803 B ERE BEE EEE CWzta 158 3 LSO 5 A EN 231244 13 Figure 20 Mode 5 Signal Status Modes Or Going Low Disables counting 1 Initiates counting 2 Resets output after next
22. EXCLU SIONS MAY NOT APPLY TO YOU THIS WARRANTY GIVES YOU SPECIFIC LEGAL RIGHTS AND YOU MAY ALSO HAVE OTHER RIGHTS WHICH VARY FROM STATE TO STATE ADA520 Board User Selected Settings Base 1 O Address Interrupt Source amp Channel Interrupt Source IRQ Channel
23. I O map section at the beginning of this chapter One of two clock sources the on board 8 MHz crystal or an external clock can be selected as the clock input to each timer counter In addition the timer counters can be cascaded by connecting TCO s output to TC1 s clock input and TC1 s output to TC2 s clock input The diagram shows how these clock sources are connected to the timer counters An external gate source can be connected to each timer counter through the I O connector When a gate is disconnected an on board pull up resistor automatically pulls the gate high enabling the timer counter The output from each timer counter is available at the I O connector where it can be used for interrupt genera tion or for counting functions The timer counters can be programmed to operate in one of six modes depending on your application The following paragraphs briefly describe each mode Mode 0 Event Counter Interrupt on Terminal Count This mode is typically used for event counting While the timer counter counts down the output is low and when the count is complete it goes high The output stays high until a new Mode O control word is written to the timer counter 4 22 520 1 HO CONNECTOR 1 l Iciko XTAL 8 MHz l l t P3 25 EXT CLK 0 o O 5 V P3 27_ EXT GATE 0 TIMER COUNTEA 0 P3 28 LTG OUT 0 l i l TIMER P3 29 L EXT CLK 1 COUNTER 5 V h EXT GATE 1 P3 32 L T C OUT 1
24. IBF Input Buffer Full F F A high on this output indicates that the data has been loaded into the input latch in essence an ac knowledgement IBF is set by STB input being low and is reset by the rising edge of the input INTR Interrupt Request A high on this output can be used to interrupt the id CPU when an input device is requesting service ble bn oe ard INTR is set by the STB is a one IBF is a one and INTE is a one It is reset by the falling edge of Hap RD This procedure allows an input device to re quest service from the CPU by simply strobing its data into the port INTE A Controlled by bit set reset of PC4 INTE B 231256 13 Controlled by bit set reset of PC Figure 8 MODE 1 Input INPUT FROM PERIPHERAL 23125614 Figure 9 MODE 1 Strobed Input 3 134 intel 82C55A Output Control Signal Definition OBF Output Butter Full F F The OBE output will go low to indicate that the CPU has written data out to the specified port The BF F F will be set b the rising edge of the WR input and reset by ACK Input being low MODE Y PORT A CONTROL WORD Dy Oy Dy D D O D Dy fe t fo o XX Pas ACK Acknowledge Input A low on this input informs the 82C55A that the data from Port A or Port B has been accepted In essence a response from the peripheral device indicating that it has received the data output by the CPU
25. OUT will be high for N 1 2 counts and low for N 1 2 counts Cue Libes el ao ey ee lelelo lle ls loisisisisisisis rn UU oan Tan a ee er O q AAA eis Cue 188 6 lnlolel Ie1sielelsisisisio1s 231244 11 NOTE A GATE transition should not occur one clock prior to terminal count Figure 18 Mode 3 MODE 4 SOFTWARE TRIGGERED STROBE OUT will be initially high When the initial count ex pires OUT will go low for one CLK pulse and then go high again The counting sequence is triggered by writing the initial count GATE 1 enables counting GATE O disables counting GATE has no effect on OUT After writing a Control Word and initial count the Counter will be loaded on the next CLK pulse This CLK pulse does not decrement the count so for an initial count of N OUT does not strobe low until N 1 CLK pulses after the initial count is written If a new count is written during counting it will be loaded on the next CLK pulse and counting will con tinue from the new count If a two byte count is writ ten the following happens 3 93 intel 82C54 1 Writing the first byte has no effect on counting 2 Writing the second byte allows the new count to be loaded on the next CLK pulse This allows the sequence to be retriggered by software OUT strobes low N 1 CLK pulses after the new count of N is written CWa18 003 0 ojo 0 5 FF aia 131813 1 FE
26. PROGRAMMABL 8 DIFF 16 S za a a E 6 8S E WITH AGND Gal AD AMPLIFIER CONVERTER q E TRIGGEA SELECT DAT VO CONNECTOR ADDRESS DEC 5 VOLTS Fig 3 1 ADA520 Block Diagram A D Conversion Circuitry The ADA520 performs analog to digital conversions on up to 16 analog input channels The following para graphs describe the A D circuitry Analog Inputs The input type is jumper and switch selectable for single ended single ended with dedicated ground or differential operation Single ended operation is typically used when the analog input voltage source is close to the board and the voltage levels are fairly high greater than 0 5 volts for a gain of 1 The differential mode provides noise immunity when long cable runs are unavoidable signal levels are low or surrounding electrical noise is high The input range is 5 to 5 volts for a gain of 1 Gain is used to match the input voltage levels being measured as closely as possible with the board s input voltage range For analog inputs ranging between 500 millivolts a gain of 10 can be used for analog inputs ranging between 50 millivolts a gain of 100 can be used and for analog inputs ranging between 5 millivolts a gain of 1000 can be used Because it reduces the input voltage range increasing the gain also increases the resolution of the conversion For example when the gain is set to 100 voltage changes of 13 microvolts are reflected in the digitized data Ove
27. X x x X D7 os os oa os o2 01 oo A D Status O not converting 1 converting A write programs the DAC1 MSB four bits into DO through D3 D4 through D7 are irrelevant Bit11 Bit10 BHO Bit 8 BA 14 D A Converter 2 LSB Write Only Programs the DAC2 LSB eight bits BA 15 D A Converter 2 MSB Write Only Programs the DAC2 MSB four bits into DO through D3 D4 through D7 are irrelevant Programming the ADA520 This section gives you some general information about programming and the ADAS20 board and then walks you through the major ADAS20 programming functions These descriptions will help you as you use the example programs included with the board and the programming flow diagrams at the end of this chapter All of the program descriptions in this section use decimal values unless otherwise specified The ADAS20 is programmed by writing to and reading from the correct I O port locations on the board These 1 0 ports were defined in the previous section Most high level languages such as BASIC Pascal C and C and of course assembly language make it very easy to read write these ports The table below shows you how to read from and write to I O ports using some popular programming languages ber TLE Assembly mov dx Address mov dx Address in al dx mov al Data out dx al In addition to being able to read write the I O ports on the ADAS20 you must be able to perform a variety of operations
28. an easily accessible DIP switch S1 which lets you select any one of 32 starting addresses in the computer s I O Should the factory setting of 300 hex 768 decimal be unsuitable for your system you can select a different base address simply by setting the switches to any one of the values listed in Table 1 2 The table shows the switch settings and their corresponding decimal and hexadecimal in parentheses values Make sure that you verify the order of the switch numbers on the switch 1 through 5 before setting them When the switches are pulled forward they are OPEN or set to logic 1 as labeled on the DIP switch package When you set the base address for your board record the value in the table inside the back cover Figure 1 9 shows the DIP switch set for a base address of 300 hex 768 decimal Fig 1 9 Base Address Switch S1 1 7 Base Address Switch Setting Decimal Hex 54321 Decimal Hex 54321 512 200 10000 528 210 544 220 10010 soo 00011 use room 576 240 10100 592 250 Pee 608 260 10110 624 270 10111 656 290 E 672 240 11010 688 2B0 11011 704 2C0 11100 720 2D0 pte 736 2E0 752 2F0 11111 0 closed 1 open S2 DifferentiaVSingle Ended Ground Switch Factory Setting CLOSED DIP switch S2 shown in Figure 1 10 is used in conjunction with header connector P4 to set up the analog inputs for 8 differential 8 single ended with ded
29. be used to synchronize the Counter After writing a Control Word and initial count the Counter will be loaded on the next CLK pulse OUT goes low N CLK Pulses after the initial count is writ ten This allows the Counter to be synchronized by software also CW 14 18883 nnnnnnnnanr lelefudetsiels CW 16 15843 NOTE A GATE transition should not occur one clock prior to terminal count Figure 17 Mode 2 intel 82C54 Writing a new count while counting does not affect the current counting sequence If a trigger is re ceived after writing a new count but before the end of the current period the Counter will be loaded with the new count on the next CLK pulse and counting will continue from the new count Otherwise the new count will be loaded at the end of the current counting cycle In mode 2 a COUNT of 1 is illegal MODE 3 SQUARE WAVE MODE Mode 3 is typically used for Baud rate generation Mode 3 is similar to Mode 2 except for the duty cycle of OUT OUT will initially be high When half the ini tial count has expired OUT goes low for the remain der of the count Mode 3 is periodic the sequence above is repeated indefinitely An initial count of N results in a square wave with a period of N CLK cycles GATE 1 enables counting GATE O disables counting If GATE goes low while OUT is low OUT is set high immediately no CLK pulse is required A trigger reloads the Counter with the init
30. in Group A only e One 8 bit bi directional bus port Port A and a 5 bit control port Port C e Both inputs and outputs are latched e The 5 bit control port Port C is used for control and status for the 8 bit bi directional bus port Port A Bidirectional Bus I O Control Signal Definition INTR Interrupt Request A high on this output can be used to interrupt the CPU for input or output oper ations Output Operations OBF Output Buffer Full The OBF output will go low to indicate that the CPU has written data out to port A ACK Acknowledge A low on this input enables the tri state output buffer of Port A to send out the data Otherwise the output buffer wilt be in the high impedance state INTE 1 The INTE Flip Flop Associated with OBF Controlled by bit set reset of PCs Input Operations STB Strobe Input A low on this input loads data into the input latch IBF Input Bufter Full F F A high on this output indicates that data has been loaded into the input tatch INTE 2 The INTE Flip Flop Associated with IBF Controlled by bit set reset of PC4 3 136 intel MODE 0 Configurations Continued CONTROL WORD 64 D PEREA Ds 0 0 O 0 El CONTROL WORD 96 D De Ds amp DO D D O CONTROL WORD 66 O D Ds D 0 0 D Do CONTROL WORD 97 D O 0 0 D O O Da 82C55A 3 132 CONTROL WORD 88 D O Ds D D Da D CONTROL WORD 09 D Og Ds D O
31. is installed in each group of two or three CLK pins XTAL EXTCLKO OUTO XTAL EXTCLK1 OUT1 XTAL EXTCLK2 CLKO CLK1 N x o Fig 1 3 8254 Timer Counter Clock Source Jumpers P5 Ce S 8254 ps l l l l Icixo 6 XTAL 8 MHz TIMER I 1 P3 25 EXT CLK 0 COUNTER O Q EV Y 0 P3 27 EXT GATE 0 P3 28 J T C OUT 0 520 VO CONNECTOR TIMER e l COUNTER CLK O 1 EXT CLK 1 P3 31 EXT GATE 1 EE EAT SEN paz q TIC OUT 1 GATE OUT TIMER N l P2 45 P3 99 EXT CLK 2 CLK o Op se ZOMEN fs es AE 5 V P2 46 P3 35 EXT GATE 2 P2 44 P3 364 TIC OUT 2 Fig 1 4 8254 Timer Counter Circuit Block Diagram P6 DAC 1 Output Voltage Range Factory Setting 5 to 5 volts This header connector shown in Figure 1 5 sets the output voltage range for DAC 1 at 0 to 5 5 0 to 10 or 10 volts Two jumpers must be installed one to select the range and one to select the multiplier The two top jumpers select the range bipolar 5 or unipolar 5 The two bottom jumpers select the multiplier X2 or X1 When a jumper is on the X2 multiplier pins the range values become 10 and 10 The table below shows the four possible combinations of jumper settings and the diagram shows the factory setting This header does not have to be set the same as P7 5 5 X1 X2 P6 Fig 1 5 DAC 1 Output Voltage Range Jumper P6 Jumpers Bottom to
32. reads 4 9982 volts 4998 2 millivolts see Table 5 1 Adjust trimpot TRS until the conversion data flickers between all Is and O in the least significant bit place hexa decimal FFF and FFE Table 5 1 provides a reference for the ideal A D converter input voltage for each bit weight in each voltage range The first line is the ideal full scale all ones value and each successive line decreases by one bit weight Between the full scale voltage and the next lower bit weight is the voltage value for full scale minus 1 1 2 bits Note that the voltage values in the table are in millivolts Table 5 1 A D Converter Calibration Table Ideal Input Voltage in millivolts 5 V gain 1 005V gain 1000 00977 00488 00244 5 5 D A Calibration The D A converter requires no calibration for the X1 ranges 0 to 5 and 5 volts The following paragraph describes the calibration procedure for the X2 multiplier ranges To calibrate for X2 0 to 10 or 10 volts set the DAC output voltage range to O to 10 volts jumpers on X2 and 5 on P6 AOUTI or P7 AOUT 2 Then program the corresponding D A converter DAC1 or DAC2 with the digital value 2048 The ideal DAC output for 2048 at X2 0 to 10 volt range is 5 0000 volts Adjust TRI for AOUTI and TR2 for AOUT2 until 5 0000 volts is read at the output Table 5 2 lists the ideal output voltages per bit weight for unipolar ranges and Table 5 3 lis
33. state of the interrupt mask register and the interrupt vector that you will be using The IMR is located at I O port 21H The interrupt vector you will be using is located in the interrupt vector table which is simply an array of 256 bit 4 byte pointers and is located in the first 1024 bytes of memory Segment 0 Offset 0 You can read this value directly but it is a better practice to use DOS function 35H get interrupt vector Most C and Pascal compilers provide a library routine for reading the value of a vector The vectors for the hardware interrupts are vectors 8 through 15 where IRQO uses vector 8 IRQ1 uses vector 9 and so on Thus if the ADAS20 will be using IRQ3 you should save the value of interrupt vector 11 Before you install your ISR temporarily mask out the IRQ you will be using This prevents the IRQ from requesting an interrupt while you are installing and initializing your ISR To mask the IRQ read in the current IMR at I O port 21H and set the bit that corresponds to your IRQ remember setting a bit disables interrupts on that IRQ while clearing a bit enables them The IMR is arranged so that bit O is for IRQO bit 1 is for IRQ1 and so on See the paragraph entitled Interrupt Mask Register IMR earlier in this chapter for help in determining your IRQ s bit After setting the bit write the new value to I O port 21H With the startup IMR saved and the interrupts on your IRQ temporarily disabled you can assign the inte
34. states to known values Once the digital I O lines are initialized you can use them to control or monitor external devices Example Programs and Flow Diagrams The software included with your ADA 520 board contains example programs in C Pascal and BASIC to help you get started using the board Also included is an easy to use menu driven diagnostics program 520DIAG which is especially helpful when first checking out the board after installation or when calibrating the board Before using the software included with your board make a backup copy of the disk You may make as many backups as you need The example programs included on the disk are listed below C and Pascal Programs These programs are source code files so that you can easily develop your own custom software for your ADAS20 board In the C directory ADA520 H and ADA520 INC contain all the functions needed to implement the main C programs H defines the addresses and INC contains the routines called by the main programs In the Pascal directory ADAS20 PNC contains all of the procedures needed to implement the main Pascal programs Analog to Digital SOFTTRIG Demonstrates how to use the software trigger mode for acquiring data Timer Counters TIMER A short program demonstrating how to program the 8254 for use as a timer Digital VO DIGITAL Simple program that shows how to read and write the digital I O lines Digital to Analog DAC Shows how to use the DACs Uses A D channe
35. that you might not normally use in your programming The table below shows you some of the operators discussed in this section with an example of how each is used with Pascal C and BASIC Note that the modulus operator is used to retrieve the least significant byte LSB of a two byte word and the integer division operator is used to retrieve the most significant byte MSB amp a b c a b c a b amp c MOD DIV AND OR a bMODc ai bDiVc a bAND c a bORC BASIC MOD backslash AND OR a bMODc a b c a bANDc a bORc Many compilers have functions that can read write either 8 or 16 bits from to an I O port For example Turbo Pascal uses Port for 8 bit port operations and PortW for 16 bits Turbo C uses inportb for an 8 bit read of a port and inport for a 16 bit read Be sure to use only 8 bit operations with the ADA520 Clearing and Setting Bits in a Port When you clear or set one or more bits in a port you must be careful that you do not change the status of the other bits You can preserve the status of all bits you do not wish to change by proper use of the AND and OR binary operators Using AND and OR single or multiple bits can be easily cleared in one operation To clear a single bit in a port AND the current value of the port with the value b where b 255 2 Example Clear bit 5 in a port Read in the current value of the port AND it with 223 223 255 2 and then write the resulting value to
36. the TS16 thermocouple board The special considerations for using the ADAS20 with ATLANTIS are given at the end of this appendix Before using ATLANTIS on the ADAS20 board check the following switch and jumpers S1 Base address PS 8254 timer counter I O configuration P9 Interrupts Figure E 1 shows the board layout 00000000 CNAE RICH SPEED di esses Ee EJuo ET Be TO m 1 09900000 00000 Nr kra E bre aa 000900900D Hi S Ko O reroz fo Do Basco ppal G L SE TH f no TT BRT 5 E 2 et 00000000 00 O oe DO Bm Etn bez 0000000 BBBBBBEE 00 O on o 0000000000000000000 2 ce SO0BODDA q elle EB Ele a Ama mm pole 0000 a SL Za ea men T A D 00000000000000000 fer aaide nf B00000000000 ER sor mr EESTE EEED d a 2200000000 preces co en ml 200000000000 Sere P orae pre 79090999900 sl Bn anas 000000008666 1009999999 ELLE penne 600000 corn eee 9000000000 amp 90 enn rcr maa nt 2 Ha D D 8 8 500000 Y 50000000 Y 5600000000 gets 5500050000 ED B us Pr Fig E 1 ADA520 Board Layout S1 Base Address ATLANTIS assumes that the base address of your ADA520 is the factory setting of 300 hex see Chapter 1 If you changed this setting you must run the ATINST program and reset the base address NOTE The ATINST program requires the base address to be entered in decimal notation PS 8254 Timer Counter I O Configuration The
37. 0111 channel 8 Stari Convert 1000 channel 9 1001 channel 10 1010 channel 11 1011 channel 12 1100 channel 13 O no convert 1 start convert Read A D Data 1101 channel 14 0 read MSB 1110 channel 15 1 read LSB 1111 channel 16 BA 3 8255 PPI Control Word Write Only When bit 7 of this word is set to 1 a write programs the PPI configuration On initialization the PPI must be programmed so that Port A is Mode O input Port B is Mode 0 input or output Port C lower is output and Port C upper is input as shown below X don t care Mode Set Flag E a de ae Port C Lower Mode Select Sroa 1 input 00 mode 0 01 mode 1 Port B 1x mode2 O output 1 input Port A O output Mode Select 1 input O mode O 1 mode 1 Port C Upper Pe cate soa O output 1 input Group A EE Jj 4 5 The table below shows the control words for the 16 possible Mode 0 Port I O combinations 8255 Port I O Flow Direction and Control Words Mode 0 Port C Port C Upper Port B Lower Binary Decimal 10000000 ENE asa opa oa omo Par oa opa m CE NC upa TN ou rooorooo ee ee oma ma ove wma 10001001 r o oma hor ma ma roomer 00 as ten over Goma oven rooroooo ma 10011000 10011001 10011010 154 155 Set Reset Bit Set Reset Function Bit 0 set bit to
38. 1 Disables counting Initiates 2 Sets output counting immediately high 1 Disables counting Initiates 2 Sets output counting immediately high Disables Enables counting counting Initiates Counting Figure 21 Gate Pin Operations Summary NOTE O is equivalent to 216 for binary counting and 104 for BCD counting Figure 22 Minimum and Maximum initial Counts 3 95 Operation Common to All Modes Programming When a Control Word is written to a Counter all Control Logic is immediately reset and OUT goes to a known initial state no CLK pulses are required for this GATE The GATE input is always sampled on the rising edge of CLK In Modes 0 2 3 and 4 the GATE input is level sensitive and the logic level is sampled on the rising edge of CLK In Modes 1 2 3 and 5 the GATE input is rising edge sensitive In these Modes a rising edge of GATE trigger sets an edge sensi tive flip flop in the Counter This flip flop is then sam pled on the next rising edge of CLK the flip flop is reset immediately after it is sampled In this way a trigger will be detected no matter when it occurs a high logic level does not have to be maintained until the next rising edge of CLK Note that in Modes 2 and 3 the GATE input is both edge and level sensi tive In Modes 2 and 3 if a CLK source other than the system clock is used GATE should be pulsed immediately following WR of a new cou
39. 1 the LSB is read Bit 7 of the MSB tells you whether the converted voltage is a positive or negative value Bit 6 goes to 1 when the input voltage exceeds the input voltage range The table below shows the expected converted data for maximum positive and negative input voltages and for O volts Bt11 Bit10 Bt9 Bits Polarity Flag O negative 1 positive Overrange Flag O in range 1 out of range Bt7 Bt6 Bits Bit4 Bit3 Bit2 Bit1 Bit O Converted Data 12 bits 1111 1111 1111 0 mm nm m lo 0000000 oooo oovots BA 1 PPI Port B Digital I O Read Write This port transfers the 8 bit PPI Port B digital input and digital output data between the board and an external device A read transfers data from the external device through P3 and into PPI Port B a write transfers the written data from Port B through P3 to an external device In7 In6 In5 In4 In3 In2 Int Ino D7 os os os os pe os Out Out6 Out5 Out4 Out3 Out2 Out1 Outo BA 2 PPI Port C Channel Select Gain Select A D Control Write Only BA 2 programs the channel and gain starts an A D conversion and selects the MSB or LSB to be read at BA 0 The bit control is as shown on the next page 4 4 Analog Input Channel Select 0000 channel 1 0001 channel 2 0010 channel 3 0011 channel 4 Gain Select 00 x1 0100 channel 5 01 x10 0101 channel 6 10 x100 0110 channel 7 11 x1000
40. 300 hex 768 decimal Connects negative side of differential inputs to Closed 8 single ended with 2 ground for 8 single ended with ground operation ground 29900 eo po od 00000000 HEEE SWITCH a y 90000 00 Soooo na E dl oe g IE YT Ta Ple a soso E ig 3 55 X Fe S Mp EHEN TI Ge o Eon ed 00000000 Eo joo 2900000 90000000 po 0000000 o o Sets the clock sources for the 8254 timer counters 155509 0 COS gr no o 19000009000000000900 do poor Dee 0000000 a on S Erf FE jk 8900 BEGREBER fir o 2999 y G29 0 f oD 09609609 o o o o 000000000000 Bree To o o 5680055 TEE ET TEEN EI core man 29000000 peace emd po ER al o oO u 2990000000000 0 ols Sooo VE0060000x V 00000000 e 2 oTe c00000000000 93 nS paso ED wks 9 RAA ge Zra M an coneisytem os 200000000000 E o oo 00000000 2000000 0000000000 p A S8 heera en se l y o o se S 900000005 y 0000000 Y 00060000000 QROHSHEHTEHRD S S gk Er en 90009900 8000000000 000000000000 al 44 J g e nn 9 e 55 00000009000 S 9600000 Y 00000900 0000000008 Y 000000000000 na saar Sn Pe 2 u E 0000000 WE m FREE 2099000000 Pe e a a TE B perna Toro Ba 8 59 059 0000000 Y Bo000000 Y 5600500000 1955512 90005500805 mn m ug Fig 1 1 Board Layout Showing Factory Configured Settings 1 3
41. 54 count all but the first are ignored i e the count which will be read is the count at the time the first read back command was issued The read back command may also be used to latch status information of selected counter s by setting STATUS bit D4 0 Status must be latched to be read status of a counter is accessed by a read from that counter The counter status format is shown in Figure 11 Bits DB through DO contain the counter s programmed Mode exactly as written in the last Mode Control Word OUTPUT bit D7 contains the current state of the OUT pin This allows the user to monitor the counter s output via software possibly eliminating some hardware from a system De Ds Dg D3 D2 Dy Do D NULL om o ee ichs D7 1 Out Pin is 1 O Out Pin is 0 De 1 Null count O Count available for reading Ds Do Counter Programmed Mode See Figure 7 Figure 11 Status Byte NULL COUNT bit D6 indicates when the last count written to the counter register CR has been loaded into the counting element CE The exact time this happens depends on the Mode of the counter and is described in the Mode Definitions but until the count is loaded into the counting element CE it can t be read from the counter If the count is latched or read before this time the count value will nct reflect the new count just written The operation of Null Count is shown in Figure 12 Command D7 De Ds D4 D3 D2 D Do Description
42. 8254 must be configured with the three jumpers placed between the pins as shown in Figure E 2 This configuration is the same as the factory setting After setting the jumpers verify that each is in the proper location Any remaining jumpers must be removed from the P5 header connector XTAL EXTCLKO OUTO XTAL EXTCLK1 OUT1 XTAL EXTCLK2 CLK1 CLKO CLK2 Fig E 2 8254 Timer Counter Clock Source Jumpers P5 P9 Interrupts To select an IRQ channel and an interrupt source you must install two jumpers on this header connector To configure this header for ATLANTIS place one jumper across the pins of your desired IRQ channel and place the second jumper across the pins labeled OUT2 Make certain that there are no other jumpers on this connector Also make sure that the IRQ channel you have selected is not used by any other device in your system Figure E 3 shows you how to configure P9 for IRQ channel 3 P9 O 6 LINO cino NIDIHL Fig E 3 Interrupts and Interrupt Channel Jumpers P9 E 4 Special Considerations for ATLANTIS and the ADA520 When using ATLANTIS with the ADA520 you must be aware of some special considerations for successful operation Sampling Rate First the maximum sampling rate is about 7 5 Hz Since ATLANTIS samples from all 8 channels in succession the maximum sampling rate per channel is just under 1 Hz Foreground Sampling Foreground sampling i
43. CLK2 i OUTI l TIMER l P2 45 P3 33 EXT CLK 2 CLK TA re EN TE A es 5 Y GATE P3 35 EXT GATE 2 P2 44 P3 36 T C OUT 2 I Fig 4 6 8254 Programmable interval Timer Circuit Block Diagram Mode 1 Hardware Retriggerable One Shot The output is initially high and goes low on the clock pulse following a trigger to begin the one shot pulse The output remains low until the count reaches 0 and then goes high and remains high until the clock pulse after the next trigger Mode 2 Rate Generator This mode functions like a divide by N counter and is typically used to generate a real time clock interrupt The output is initially high and when the count decrements to 1 the output goes low for one clock pulse The output then goes high again the timer counter reloads the initial count and the process is repeated This sequence continues indefinitely Mode 3 Square Wave Mode Similar to Mode 2 except for the duty cycle output this mode is typically used for baud rate generation The output is initially high and when the count decrements to one half its initial count the output goes low for the remainder of the count The timer counter reloads and the output goes high again This process repeats indefinitely Mode 4 Software Triggered Strobe The output is initially high When the initial count expires the output goes low for one clock pulse and then goes high again Counting is triggered by writing the initial count
44. D D Dy CONTROL WORD 010 D Os O O O 0 D CONTROL WORD 611 D De O 0 0 0 D rc Cya va 231256 11 intel 82C55A MODE 0 Configurations Continued CONTROL WORD 12 CONTROL WORD 14 D O D 0 0 0 D Be Ds Ds De D D O O CONTROL WORD 613 CONTROL WORD 915 D Os D D D D O 0D O De D D 0 0 0 0D Kr Perito Paes 231256 12 Mode 1 Basic functional Definitions Operating Modes ss 9 e Two Groups Group A and Group B MODE 1 Strobed Input Output This functional e Each group contains one 8 bit data port and one configuration provides a means for transferring 1 0 4 bit control data port data to or from a specified port in conjunction with E strobes or handshaking signals In mode 1 Port A The 8 bit data port can be either input or output and Port B use the lines on Port C to generate or Both inputs and outputs are latched accept these handshaking signals The 4 bit port is used for control and status of the 8 bit data port 3 133 intel 82C55A CONTROL WORD Dy De Ds D D O D D Den ee 231256 18 Figure 13 MODE Control Word 23125619 Figure 14 MODE 2 PERIPHERAL aus 23125620 Figure 15 MODE 2 Bidirectional NOTE Any sequence where WR occurs before ACK and STE occurs before RD is permissible INTR IBF e MASK e STB e AD OBF e MASK e ACK e WR e e r mma en 3 137
45. DIGITAL GND DIGITAL GND TRIGGER IN DIGITAL GND TRIGGER OUT DIGITAL GND DIGITAL GND DIGITAL GND EXT CLK 0 5 DIGITAL GND EXT GATE 0 Es T C OUT 0 EXT CLK 1 DIGITAL GND EXT GATE 1 98 T C OUT 1 EXT CLK 2 DIGITAL GND EXT GATE 2 6969 TIC OUT 2 12 VOLTS 6768 5 voLTs 12 VOLTS 696 DIGITAL GND APPENDIX C COMPONENT DATA SHEETS C 1 Intel 82C54 Programmable Interval Timer Data Sheet Reprint 82C54 CHMOS PROGRAMMABLE INTERVAL TIMER m Compatible with all Intel and most m Three independent 16 bit counters other microprocessors m Low Power CHMOS m High Speed Zero Walt State Icc 10 mA 8 MHz Count Operation with 8 MHz 8086 88 and frequency 80186 188 a Completely TTL Compatible m Handles Inputs from DC to 8 MHz 10 MHz for 82C54 2 a as Biggen oe Modes E Available in EXPRESS eRe ee oe g Status Read Back Command Standard Temperature Range Extended Temperature Range _ m Available In 24 Pin DIP and 28 Pin PLCC The Intel 82C54 is a high performance CHMOS version of the industry standard 8254 counter timer which is designed to solve the timing control problems common in microcomputer system design It provides three independent 16 bit counters each capable of handling clock inputs up to 10 MHz All modes are software programmable The 82C54 is pin compatible with the HMOS 8254 and is a superset of the 8253 Six programmable timer modes allow the
46. O O active Bit Select 1 set bit to 1 000 PCO 001 PC1 010 PC2 011 PC3 100 PC4 101 PCB 110 PC6 111 PC7 4 6 For example if you want to set Port C bit O to 1 you would set up the control word so that bit 7 is O bits 1 2 and 3 are O this selects PCO and bit O is 1 this sets PCO to 1 The control word is set up like this 0 x x x 0 0 0 1 Sets PCO to 1 written to BA 3 X don t care Set Reset Function Bit Bit Select 000 PCO BA 4 ID Register Buffered Digital I O Direction Read Write A read provides the contents of the ID register This value should be 1 A write programs the direction of the Port A Port B and Port C buffered digital I O lines The bottom 3 bits of this word set up the lines as inputs or outputs as shown below Note that on reset all 24 lines are automatically programmed as inputs until you write new data to BA 5 BA 6 and BA 7 If you change their direction to outputs the lines may be high or low depending on their last programmed values To set the lines to the values you want write new data to BA 5 BA 6 and BA 7 Port A Direction O input Port B Direction 1 output O input 1 output Port C Direction 0 input 1 output BA 5 Port A Digital I O Lines Read Write Transfers the 8 bit Port A buffered digital input and digital output data between the board and an external device BA 4 is used to set up the port as an input
47. OLTS 6 68 5 voLTs P3 on an 12 VOLTS 696 DIGITAL GND tour ANALOG GND E 40 Pin vour ANALOG GND DIGITAL GND T C OUT 2 EXT CLK 2 EXT GATE 2 P2 12 VOLTS 5 VOLTS l 12 VOLTS DIGITAL GND 50 Pin Fig 2 1 P2 and P3 I O Connector Pin Assignments Connecting the Analog Input Pins 16 Single Ended No Dedicated GND When operating in the 16 channel single ended mode P4 SE S2 OPEN connect the high side of the analog inputs to the analog input channels AIN through AIN16 and connect the low side to any of the ANALOG GND pins available at the connector pins 18 20 22 on P2 Ground any unused inputs Figure 2 2 shows how these connections are made 520 WO CONNECTOR P2 Fig 2 2 Single Ended Input Connections No Dedicated GND 2 4 8 Single Ended Dedicated GND When operating up to 8 channels in the single ended mode with a dedicated ground for each channel P4 D S2 CLOSED connect the high side of each analog input to the selected analog input channel AIN1 through AIN8 and connect the low side to its corresponding AGND AINI through AIN8 Ground any unused inputs Figure 2 3 shows how these connections are made Note that you can mix single ended with dedicated ground and differential channels by setting the individual switches on S2 to the proper position 520 WO CONNECTOR Pe Fig 2 3 Single Ended Input Connections Dedicated GND 8 Differential When operating in the differentia
48. P7 DAC 2 Output Voltage Range Factory Setting 5 to 5 volts mna 1 6 PR External Trigger In Factory Setting Disabled nnn 1 6 P9 Interrupt Source and Channel Select Factory Setting OUT2 Interrupt Channels Disabled 1 6 S1 Base Address Factory Setting 300 hex 768 decimal cc ean 1 7 S2 Differential Single Ended Ground Switch Factory Setting OPEN AS 1 8 S3 A D Conversion Rate Factory Setting 7 5 Hz sn 1 9 Pull up Pull down Resistors on Digital I O Lines senses 1 9 IOUT and VOUT References nein ee edet 1 9 CHAPTER 2 BOARD INSTALLATION O ZU Board Installation A A O elen 2 3 External UO Connections add 2 3 Connecting the Analog Input Pins pasasaanenormoeronunnessnensenvnonenenesenanensenneseronsossessonsorss 2 4 Connecting the Trigger In and Trigger Out Pins Cascading Boards nnn 2 6 Connecting the Analog Output mico neeaae 2 6 Connecting the Timer Counters and Digital UO 2 6 Running the 520DIAG Diagnostics Program sese 2 6 CHAPTER 3 HARDWARE DESCRIPTION ON Te A D Conversion CU ai 3 3 Analog INPUlS cad 3 3 PLD SON CINE ne UR AE IN RR 3 4 DIA COR VEREN heated A a ei 3 4 DIEIBLO nee RN e om RV os NR ee 3 4 A A ee np ee 3 4 IHISTTUDIS ne EE E EE ERATE E te 3 4 CHAPTER 4 BOARD OPERATION AND PROGRAMMING annae 4 1 Defining the I O Map na Se a EE diccsan chock 4 3 BA 0 PPI Port A Read A D Data Read Only cocinera 4 4 BA 1 PPI Port B Digital YO Read Write ess
49. PHERAL aus DATA FROM PERIPHERAL TO 8255 Note DATA FROM 8256 TO PERIPHERAL DATA FROM 8265 TO 8080 231256 26 Any sequence where WR occurs betore ACK AND STB occurs before RD is permissible INTR IBF e MASK o STB o RD WRITE TIMING 23125627 A C TESTING INPUT OUTPUT WAVEFORM 2 0 2 0 v gt TEST POINTS lt C 150 pF es o 23125629 A C Testing Inputs Are Driven At 2 4V For A Logic 1 And 0 45V For A Logic O Timing Measurements Are Made At 2 0V For A Logic 1 And 0 8 For A Logic 0 DEF e MASK e ACK WA READ TIMING HIGH IMPEDANCE 231256 28 A C TESTING LOAD CIRCUIT EN i E 231256 30 Vexr Is Set At Various Voltages During Testing To Guarantee The Specification C includes Jig Capacitance 3 146 APPENDIX D CONFIGURING THE ADA520 FOR SIGNAL MATH D 2 TO BE COMPETED D 3 D 4 APPENDIX E CONFIGURING THE ADA520 FOR ATLANTIS E 1 If you have purchased ATLANTIS data acquisition and real time monitoring application software for your ADAS20 please note that the ATLANTIS drivers for your board must be loaded from your ATLANTIS driver disk into the same directory as the ATLANTIS EXE program When running ATLANTIS you must change some of the ADA520 s on board jumpers from their factory set positions You should also be aware of how ATLANTIS operates with the ADA520 and
50. TO ANY PRODUCTS WHICH HAVE BEEN DAM AGED AS A RESULT OF ACCIDENT MISUSE ABUSE such as use of incorrect input voltages improper or insufficient ventilation failure to follow the operating instructions that are provided by REAL TIME DEVICES acts of God or other contingencies beyond the control of REAL TIME DEVICES OR AS A RESULT OF SERVICE OR MODIFICATION BY ANYONE OTHER THAN REAL TIME DEVICES EXCEPT AS EX PRESSLY SET FORTH ABOVE NO OTHER WARRANTIES ARE EXPRESSED OR IMPLIED INCLUDING BUT NOT LIMITED TO ANY IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE AND REAL TIME DEVICES EXPRESSLY DISCLAIMS ALL WARRANTIES NOT STATED HEREIN ALL IMPLIED WARRANTIES INCLUDING IMPLIED WARRANTIES FOR MECHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE LIMITED TO THE DURATION OF THIS WARRANTY IN THE EVENT THE PRODUCT IS NOT FREE FROM DEFECTS AS WARRANTED ABOVE THE PURCHASER S SOLE REMEDY SHALL BE REPAIR OR REPLACEMENT AS PROVIDED ABOVE UNDER NO CIRCUMSTANCES WILL REAL TIME DEVICES BE LIABLE TO THE PURCHASER OR ANY USER FOR ANY DAMAGES INCLUDING ANY INCIDENTAL OR CONSEQUENTIAL DAM AGES EXPENSES LOST PROFITS LOST SAVINGS OR OTHER DAMAGES ARISING OUT OF THE USE OR INABILITY TO USE THE PRODUCT SOME STATES DO NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR CONSE QUENTIAL DAMAGES FOR CONSUMER PRODUCTS AND SOME STATES DO NOT ALLOW LIMITA TIONS ON HOW LONG AN IMPLIED WARRANTY LASTS SO THE ABOVE LIMITATIONS OR
51. Top Voltage Range eeso om on o om ows or ow or on KCE on P7 DAC 2 Output Voltage Range Factory Setting 5 to 5 volts This header connector shown in Figure 1 6 sets the output voltage range for DAC 2 at 0 to 5 5 O to 10 or 10 volts Two jumpers must be installed one to select the range and one to select the multiplier The two rightmost jumpers select the range bipolar 5 or unipolar 5 The two leftmost jumpers select the multiplier X2 or X1 When a jumper is on the X2 multiplier pins the range values become 10 and 10 The table below shows the four possible combinations of jumper settings and the diagram shows the factory setting This header does not have to be set the same as P6 P7 SSL Fig 1 6 DAC 2 Output Voltage Range Jumper P7 Voltage Range and Polarity Mm ss 5 otossvots or on _towsovars on or on ote t0vors on P8 External Trigger In Factory Setting Disabled P8 shown in Figure 1 7 enables and disables the external trigger input When the jumper is set to the enabled position the external trigger in pin pin 19 at on board I O connector P3 is connected to the A D converter so that two or more boards can be run synchronously in a master slave configuration Note that this header connector enables and disables the trigger in only it does not affect the trigger out line EXT TRIG DIS EN P8 Fig
52. aking is required data is simply written to or read from a specified port MODE 0 BASIC INPUT 82C55A Mode O Basic Functional Definitions e Two 8 bit ports and two 4 bit ports e Any port can be input or output e Outputs are latched e Inputs are not latched e 16 different Input Output configurations are pos sible in this Mode HN tao MODE 0 BASIC OUTPUT 3 130 tor 231256 8 231256 9 Intel 82C55A MODE 0 Port Definition Te 0 a E o i AN A EE 0 EA E SIT E MODE 0 Configurations CONTROL WORD 0 amp O D 0 D D D Do CONTROL WORD 91 D De Ds Da D D a B GROUP A PORT C PORTA ones Es PORT B OUTPUT OUTPUT po o o o oureur ourur o OUTPUT OUTPUT OUTPUT INPUT OUTPUT INPUT 6 INPUT OUTPUT INPUT INPUT OUTPUT 8 OUTPUT OUTPUT OUTPUT 9 OUTPUT input OUTPUT 10 INPUT OUTPUT input OUTPUT 11 INPUT INPUT INPUT INPUT 12 OUTPUT OUTPUT INPUT INPUT 13 OUTPUT INPUT INPUT 14 INPUT OUTPUT 3 131 D De Ds D D D D 0 CONTROL WORO 3 D De Os DD 0 D Do lt GrourB PORT C LOWER dd 231256 10 intel 82C55A Input Control Signal Definition MODE 1 PORT A STB Strobe Input A low on this input loads data into the input latch CONTROL WORD D De O O Da Da O Do pe fo o we
53. ater ABR o ms tn Frusewen m TT to Data Detaytrom ABS m 7 or FBT wDawFioating to 75 m tev Recovery Time between ROAR 20 ns WRITE CYCLE IRV 82C55A 2 Test CI CA tw Address Stable Betoro WA o ms Address Hold Time After WAT 20 ns PonsaaB HEM ow Data Setup Time Before MET 100 ms Do eme 3 142 intel 82C55A OTHER TIMINGS CEN Conditions Parameter WR 1 to Output Peripheral Data Before RD Peripheral Data After RD STB Pulse Width tAD ACK 0 to Output ACK 1 to Output Float ACK Oto BF 1 tar AD Oto INTR 0 im tam wir Reset Pulse Width NOTE 1 INTR T may occur as early as WR L 2 Pulse width of initial Reset pulse after power on must be at least 50 Sec Subsequent Reset pulses may be 500 ns minimum a _ N q tAOB 5 a 3 143 intel 82C55A WAVEFORMS MODE 0 BASIC INPUT MODE 0 BASIC OUTPUT aeae en ne A eme 3 144 intel 82C55A WAVEFORMS Continued MODE 1 STROBED INPUT INPUT FROM qu f pn ma lt lt om eee oe ee me wee am oe ee oe cee ee oe oe oe en PERIPHERAL 231256 24 231256 25 3 145 intel 82C55A WAVEFORMS Continued MODE 2 BIDIRECTIONAL DATA FROM 8000 TO 8285 PERI
54. ch of the 16 channels Channels 9 through 16 are not used in the differential and single ended with dedicated ground modes Note that when you write to Port C to change the active channel you must preserve the other four bits of data as you had them if you want those settings to be unchanged Setting the Gain To set the gain you must assign values to bits 4 and 5 in the PPI Port C port at BA 2 The bit structure diagram for PPI Port C above shows you the 2 bit instruction for each of four gain settings 1 10 100 and 1000 Note that when you write to Port C to change the gain setting you must preserve the other six bits of data as you had them if you want those settings to be unchanged There is a way to individually set and reset the lines of Port C by writing the correct data to the control word at address location BA 3 For example you can individually set to logic 1 or reset to logic 0 PC4 and PCS by writing two sets of data to the control word not to Port C as shown in Figure 4 1 below This example shows how to set the gain to 100 When the most significant bit D7 of the control word is set to 0 it activates the bit set reset function which lets you individually set or reset any one of Port C s bits Sets PC4 to 1 written to BA 3 X don t care Set Reset Function Bit Bit Select 100 PC4 0 x x x 0 0 1 0 Sets PC5 to 0 written to BA 3 Set Reset Reset PC5 Function Bit Bit Select 101 PC5
55. count is then unlatched automatically and the OL returns to following the counting element CE This allows reading the contents of the Counters on the fly without affecting counting in progress Multiple Counter Latch Commands may be used to latch more than one Counter Each latched Coun ter s OL holds its count until it is read Counter Latch Commands do not affect the programmed Mode of the Counter in any way If a Counter is latched and then some time later latched again before the count is read the second Counter Latch Command is ignored The count read will be the count at the time the first Counter Latch Command was issued With either method the count must be read accord ing to the programmed format specifically if the Counter is programmed for two byte counts two bytes must be read The two bytes do not have to be read one right after the other read or write or pro 3 89 gramming operations of other Counters may be in serted between them Another feature of the B2C54 is that reads and writes of the same Counter may be interleaved for example if the Counter is programmed for two byte counts the following sequence is valid 1 Read least significant byte 2 Write new least significant byte 3 Read most significant byte 4 Write new most significant byte If a Counter is programmed to read write two byte counts the following precaution applies A program must not transfer control between
56. cuit as pull ups or pull downs Locate the three hole pads on the board near the resistor packs They are labeled G for ground on one end and V for Vee on the other end The middle hole is common Figure 1 12 shows a blowup of the pads for Ports A and C To operate as pull ups solder a jumper wire between the common pin middle pin of the three and the V pin For pull downs solder a jumper wire between the common pin middle pin and the G pin IOUT and VOUT References reference current output and reference voltage output are provided at the P2 1 O connector for use with external circuitry The reference current P2 39 is factory set at 5 milliamperes The reference voltage P2 41 is factory set at 5 volts On board trimpots are provided to adjust the output levels Chapter 5 tells you how to make these adjustments AN4 PC 0000000000 000000000000 Vv G E59 000000000000 PA 560 Ui RN3 nto 0000000000 den a 6000000 000 Perrin ATTA ET peso Br Hz f que a 7 A DoC EED o CE Ow oP seaside 5 o 00000000 A o oop CODCOD e z b 5 So y q h SIG GS Ra 5 LE q L p K El 00000000000000000000 00000000000000000000 ES 8000006 Fig 1 12 Pull up Pull down Resistor Circuitry 1 10 CHAPTER 2 BOARD INSTALLATION The 520 board is easy to install in your IBM PC XT AT or compatible computer It can be placed in any full size slot This chapt
57. d from a table that exists in the lowest 1024 bytes of memory This table is referred to as the interrupt vector table and each entry is called an interrupt vector Once the new CS and IP are loaded from the interrupt vector table the processor begins executing the code located at CS IP When the interrupt routine is completed the CS IP and flags that were pushed on the stack when the interrupt occurred are now popped from the stack and execution resumes from the point where it was interrupted Using Interrupts in Your Programs Adding interrupts to your software is not as difficult as it may seem and what they add in terms of performance is often worth the effort Note however that although it is not that hard to use interrupts the smallest mistake will often lead to a system hang that requires a reboot This can be both frustrating and time consuming But after a few tries you ll get the bugs worked out and enjoy the benefits of properly executed interrupts In addition to reading the following paragraphs study the INTRPTS source code included on your ADAS20 program disk for a better under standing of interrupt program development Writing an Interrupt Service Routine ISR The first step in adding interrupts to your software is to write the interrupt service routine ISR This is the routine that will automatically be executed each time an interrupt request occurs on the specified IRQ An ISR is different than standard routines that y
58. d of Interrupt EOI Command 4 18 What Exactly Happens When an Interrupt Occurs n se eraann 4 19 Using Interrupts in Your Programs esen 4 19 Writing an Interrupt Service Routine SR 4 19 Saving the Startup Interrupt Mask Register IMR and Interrupt Vector scccccssesssssscsecsscerssessssssessessees 4 20 Restoring the Startup IMR and Interrupt Vector seene 4 21 Common Interrupt Mistakes oss natens adden mare bieden aaan 4 21 DIA CONVE SOTS nrs A ended N RSRS 4 21 SP TIMI COUNUCES eenen een ea cd GR O rc Sal ce 4 22 HOERA ares catia santa dora a disp TATE DN AAA E 4 23 Example Programs and Flow Diagrams sese 4 24 AA IN herum a 4 24 BASIC PORS andaian II PE SAR 4 24 CHAPTER 5 CALIBRATION DO Required NN das 5 3 A NR 5 3 A A A A AN AN 5 4 A A len entered A 5 5 DIR Calibration A nn O raed 5 6 Reference Current and Voltage Out Adjust seen 5 7 APPENDIX A ADA520 SPECIFICATIONG ssccosscossssscsssssssvescsesurecessnscnsssssseseeesssecescescessoseceeees A l APPENDIX B CONNECTOR PIN ASSIGNMENTS annan B 1 APPENDIX C COMPONENT DATA SHEETS sssccssssssossssssecssscesscusssessnscsssseseseneseneconseoneeoeeece C 1 APPENDIX D CONFIGURING THE ADA520 FOR SIGNAL MATH PN DeL APPENDIX E CONFIGURING THE ADA520 FOR ATLANTIS a E 1 APPENDIX F WARRANTY Cana a ana F 1 ii LIST OF ILLUSTRATIONS 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 1 10 1 11 1 12 2 1 2 2 2 3 24 2 5
59. e PC6 l Status Status Converting Status Converting PC7 gt TTT Read Data i MSB LSB MSB LSB Fig 4 2 Continuous Convert Mode Timing Diagram 4 14 Program 8255 PPI Port A in Port C out Select Channel amp Gain Start Conversion PC6 1 Check Status Status 1 Yes Stop Conversion PCB 0 REN Status 0 Set PC7 0 to enable MSB Read PP Port A for MSB Set PC7 1 to enable LSB Read PPI Port A for LSB Fig 4 3 Single Convert Mode Flow Diagram Yes No Stop Program 4 15 Program 8255 PPI Port A in Port C out Seiect Channel amp Gain Start Conversion PCE 1 Check Status tal Status 1 Yes Es Status 0 Set PC7 0 to enabie MSB Read PPI Port A for MSB Set PC7 1 to enable LSB Yes No Read PPI Port A for LSB Stop Conversion Fig 4 4 Continuous Convert Mode Flow Diagram 4 16 Cascading Boards Two or more boards can be cascaded and triggered so that A D conversions are performed simultaneously on each board Figure 4 5 provides a flow diagram for cascaded operation Chapter 2 shows how to connect the boards for simultaneous triggering BOARDS 1 amp 2 Program 8255 PPI Port A in Port C out BOARDS 1 amp 2 Select Channel amp Gain BOARD 1 Start Conversion PC6 1 BOARD 1 Check Status Status 1
60. e 4 4 BA 2 PPI Port C Channel Select Gain Select A D Control Write AAA acces cxkstensesceneecX 4 4 BA 3 8255 PPI Control Word Write Only ias 4 5 o BA 4 ID Register Buffered Digital UO Direction Read Write sss 4 7 BA 5 Port A Digital I O Lines Read Write essen 4 7 BA 6 Port B Digital I O Lines Read Write essen enesenn 4 7 BA 7 Port C Digital I O Lines Read Write sss assa 4 7 BA 8 8254 Timer Counter 0 Read Write sss 4 8 BA 9 8254 Timer Counter 1 Read Write sss 4 8 BA 10 8254 Timer Counter 2 Read Write sss 4 8 BA 11 8254 Control Word Write Only sss 4 8 BA 12 Update DACs D A Converter 1 LSB Read Write anna 4 8 BA 13 Status D A Converter 1 MSB Read Write nennen 4 9 BA 14 D A Converter 2 LSB Write Only sassa 4 9 BA 15 D A Converter 2 MSB Write Only sesa 4 9 Programming DADAS as dd 4 10 Clearing and Setting Bits in a Port eee eee 4 10 pi AA O ed oale eten an cules 4 12 Initializing AA ana ee tee edele EN 4 12 Selecting a Channel an unirmos otras A a leew ted lac ane ists 4 13 SCH NE GAN A mi irado ia ane DUBR GR E 4 13 A D Conversion MAS jo isca a a Sn Ad bs 4 14 Single Convert Mode etna SE Cs E OD qua O 4 14 eContinuous Convert AA agent Ba 4 14 A Desde E O AS en 4 17 INERUDIE A A A A aile nd ela T neede Soc 4 18 What IS AN A O EE E A 4 18 Interrupt Request id 4 18 8259 Programmable Interrupt Controller 4 18 Interrupt Mask Register IMR eenn 4 18 En
61. e 82C54 to match his require ments and programs one of the counters for the de connected to system data bus lock O Clock input of Counter 0 tput O Output of Counter 0 ate 0 Gate input of Counter 0 round Power supply connection t 1 Output of Counter 1 Gate 1 Gate input of Counter 1 Clock 1 Clock input of Counter 1 ate 2 Gate input of Counter 2 ut 2 Output of Counter 2 lock 2 Clock input of Counter 2 Address Used to select one of the three Counters or the Control Word Register for read or write operations Normally connected to the system 2 o address bus 0 Counter O 0 Counter 1 1 Counter 2 1 Control Word Register Chip Select A low on this input enables the 82C54 to respond to RD and WR signals RD and WR are ignored otherwise Read Control This input is low during CPU read operations Write Control This input is low during CPU write operations Power 5V power supply connection No Connect sired delay After the desired delay the 82C54 will interrupt the CPU Software overhead is minimal and variable length delays can easily be accommodated Some of the other counter timer functions common to microcomputers which can be implemented with the 82C54 are e Real time clock e Even counter e Digital one shot e Programmable rate generator e Square wave generator e Binary rate multiplier e Complex waveform generator e Complex motor controller
62. e Port A and Port C lines of the PPI are used to read data control the A D converter and set the channel number and programmable gain Port A s eight lines are used to carry the converted data This data is output from the A D converter in two 8 bit words an MSB and an LSB The Port C lines are used to control the channel and gain selection and A D conversion Analog Input Channel Select 0000 channel 1 0001 channel 2 0010 channel 3 0011 channel 4 Gain Select 00 x1 0100 channel 5 01 x10 0101 channel 6 10 x100 0110 channel 7 11 x1000 0111 channel 8 Sine Convent 1000 channel 9 1001 channel 10 1010 channel 11 1011 channel 12 1100 channel 13 O no convert 1 start convert Read A D Data 1101 channel 14 0 read MSB 1110 channel 15 1 read LSB 1111 channel 16 To set the Port C lines up so that you can control the channel and gain and take A D conversions the PPI must be initialized whenever you power up or reset your system This is done by writing data to the PPI control word at I O address location BA 3 The I O map is defined at the beginning of this chapter The PPI must be set up like this 1 0 0 1 0 0 X 0 or os os os os o2 o oo 4 12 Selecting a Channel To select a conversion channel you must assign values to bits O through 3 in the PPI Port C port at BA 2 The bit structure diagram for PPI Port C above shows you the 4 bit instruction for ea
63. e selected expansion slot After carefully positioning the board in the expansion slot so that the card edge connector is resting on the computer s bus connector gently and evenly press down on the board until it is secured in the slot NOTE Do not force the board into the slot If the board does not slide into place remove it and try again Wiggling the board or exerting t00 much pressure can result in damage to the board or to the computer After the board is installed secure the slot bracket back into place and put the cover back on your computer The board is now ready to be connected via the external I O connector at the rear panel of your computer External VO Connections Figure 2 1 shows the ADAS20 s P2 I O connector pinout and P3 on board I O connector pinout Refer to these diagrams as you make your I O connections 2 3 DIFF SE AINI AIN2 AIN3 AING AINS AING AINT AINte AIN2 AIN3 AIN4e AINS AING AINT DIFE S E AIN1 AINQ AGND AIN2 AINIWAGND AIN3 AIN11 AGND AING AINIVAGND AINS AINIVAGND AING AINIWAGND AINT AINTSIAGND PB2 PB1 PBO AINS AINS re bars L bal raen E DIGITAL GND j Rea uag gt DIGITAL GND NALOG GND Gui eai ENE PA7 PCT DIGITAL GND PAS Pce sas bes T ouT o S R EXT CLK 1 16962 DIGITAL GND nas nes EXT GATE 1 GDG T c our 1 eas pc EXT CLK 2 6369 DIGITAL GND s o Bes EXT GATE 2 6368 T c our 2 12 V
64. e the rate you may need to recalibrate the board Chapter 5 Calibration explains the procedures 30HZ una 7 5HZ Fig 1 11 A D Conversion Rate Switch S3 Pull up Pull down Resistors on Digital I O Lines The 32 programmable TTL CMOS compatible digital I O lines can be interfaced with a number of external devices The lines are divided into four groups eight buffered Port A lines eight buffered Port B lines eight buffered Port C lines and eight unbuffered 8255 PPI Port B lines You can install and connect pull up or pull down resistors for any or all of these groups You may want to pull lines up for connection to switches This will pull the line high when the switch is disconnected Or you may want to pull down lines connected to relays which control turning motors on and off These motors tum on when the digital lines controlling them are high Pulling the lines down prevents them from floating high during that brief period after power up and before the lines are initialized To use the pull up pull down feature you must first install 10 kilohm 10 pin resistor packs in one or more of the resistor pack locations near the P2 connector the P3 connector and beside the 8255 IC this is the 8255 Port B pack The buffered digital I O line packs are labeled RN2 PA RN3 PB and RN4 PC The 8255 Port B pack is labeled RN6 PB Figure 1 12 shows the pack locations After the resistor packs are installed you can connect them into the cir
65. ed and we can t say for sure what happens to bits 6 and 7 but we can say for sure that bit 5 ends up cleared instead of being set A similar problem happens when you use subtraction to clear a bit in place of the method shown above Now that you know how to clear and set bits we are ready to look at the programming steps for the ADA520 board functions 4 11 A D Conversions Before you are ready to start taking A D conversions you must initialize the programmable peripheral interface PPI and select the channel and gain when you initialize the PPI the channel and gain are automatically set to 1 The software provided with your board contains example programs for board initialization You can monitor the conversion status using the status bit at I O address location BA 13 When bit O of this word goes high it means a conversion is in progress When it goes low the conversion is completed When you are monitoring the status line make sure you see it go high and then low before you assume the conversion is com pleted This line does not go high until slightly after the Start Convert line starts a conversion which means that you could read a false low when the conversion first begins Remember that the status signal is inverted to derive the end of convert signal which can be monitored through an IRQ line The end of convert line is low during a conver sion and goes high when the conversion is completed Initializing the PPI Th
66. ed 0 through 7 Two of the most common mistakes when writing an ISR are forgetting to clear the interrupt status of the ADAS20 and forgetting to issue the EOI command to the 8259 interrupt controller before exiting the ISR D A Conversions The two D A converters can be individually programmed to convert 12 bit di gital words into a voltage in the range of 5 10 0 to 5 or 0 to 10 volts DACI is programmed by writing the LSB of the 12 bit digital data word to BA 12 and the MSB to BA 13 DAC2 is identical with the LSB written to BA 14 and MSB written to BA 15 A read at BA 12 updates the DAC outputs The following tables list the key digital codes and corre sponding output voltages for the D A converters D A Bit Weight 0t0o 5V Oto 10 V ee mee Es e temo 12 4 2 1 78 125 9 7656 19 5313 1 2207 2 4414 0 0000 0 0000 4 21 D A Bit Weight ay 10 V ER E 4 1 ER Timer Counters An 8254 programmable interval timer provides three 16 bit 8 MHz timer counters for timing and counting functions such as frequency measurement event counting and interrupts All three timer counters are cascaded at the factory Figure 4 6 shows the timer counter circuitry Each timer counter has two inputs CLK in and GATE in and one output timer counter OUT They can be programmed as binary or BCD down counters by writing the appropriate data to the command word as described in the
67. ene 4 14 Single Convert Mode Flow Diagram ssssssssssssssssssssoscssvessssesssesssvessueesusssnecsensesecesasestuccescsanesasscesscenss 4 15 Continuous Convert Mode Flow Diagram sss sss 4 16 Cascaded Boards Single Convert Mode Flow Diagram e 4 17 8254 Programmable Interval Timer Circuit Block Diagram anna 4 23 Board Layout Showing Calibration TrimpOtS ensen sees 5 3 iii INTRODUCTION The ADAS20 differential integrating analog I O board turns your IBM PC XT AT or compatible computer into a high performance data acquisition and control system Installed within a single expansion slot in the computer the ADAS20 features 8 differential 8 single ended with dedicated grounds or 16 single ended analog input channels e 12 bit integrating A D converter for high stability and exceptional noise immunity 5 to 5 volt input range Programmable gains of 1 10 100 and 1000 Trigger in and trigger out for cascading boards 32 TTL CMOS digital I O lines 24 with buffered outputs optional pull up pull down resistors Three 16 bit 8 MHz timer counters Two 12 bit digital to analog output channels with dedicated grounds e 5 10 0 to 5 or 0 to 10 volt analog output range IOUT and VOUT references at I O connector for external circuitry Turbo Pascal Turbo C and BASIC source code diagnostics program The following paragraphs briefly describe the major functions of the board More de
68. er tells you step by step how to install and connect the board Board Installation Keep the board in its antistatic bag until you are ready to install it in your computer When removing it from the bag hold the board at the edges and do not touch the components or connectors Before installing the board in your computer check the jumper and switch settings Chapter 1 reviews the factory settings and how to change them If you need to change any settings refer to the appropriate instructions in Chapter 1 Note that incompatible jumper settings can result in unpredictable board operation and erratic response Also note that the P2 I O connector mounting bracket has an oversized cutout to allow space for running the cable to 40 pin on board connector P3 through the same I O slot If you want to run both cables through the same slot you must make these connections before installing the board To install the board 1 2 Turn OFF the power to your computer Remove the top cover of the computer housing refer to your owner s manual if you do not already know how to do this Select any unused full size expansion slot and remove the slot bracket Touch the metal housing of the computer to discharge any static buildup and then remove the board from its antistatic bag Holding the board by its edges orient it so that its card edge bus connector lines up with the expansion slot connector in the bottom of th
69. erformance TTL CMOS compatible chip has 24 digital I O lines divided into two groups of 12 lines each Group A Port A 8 lines and Port C upper 4 lines Group B Port B 8 lines and Port C lower 4 lines The ADA520 uses Ports A and C for on board data and control operations Port B is available to the user In addition 24 buffered TTL CMOS digital I O lines are available to the user for transferring data between the com puter and external devices These lines are grouped into three 8 bit ports Port A Port B and Port C These ports can be independently programmed as inputs or outputs The bidirectional buffers on the I O lines monitor the direction programmed at BA 4 to automatically set their direction Timer Counters An 8254 programmable interval timer provides three 16 bit 8 MHz timer counters to support a wide range of timing and counting functions These timer counters can be cascaded or used individually for many applications Each timer counter has two inputs CLK in and GATE in and one output timer counter OUT The clock sources for the timer counters can be selected using jumpers on header connector P5 see Chapter 1 The timer counters can be programmed as binary or BCD down counters by writing the appropriate data to the command word as described in Chapter 4 The command word also lets you set up the mode of operation The six programmable modes are Mode 0 Event Counter Interrupt on Terminal Count Mode 1 Ha
70. from the CR to the CE refer to the Functional Descrip tion MODE 0 INTERRUPT ON TERMINAL COUNT Mode 0 is typically used for event counting After the Control Word is written OUT is initially low and will remain low until the Counter reaches zero OUT then goes high and remains high until a new count or a new Mode O Control Word is written into the Coun ter GATE 1 enables counting GATE O disables counting GATE has no effect on OUT After the Control Word and initial count are written to a Counter the initial count will be loaded on the next CLK pulse This CLK pulse does not decrement the count so for an initial count of N OUT does not go high until N 1 CLK pulses after the initial count is written If a new count is written to the Counter it will be loaded on the next CLK pulse and counting will con tinue from the new count If a two byte count is writ ten the following happens 1 Writing the first byte disables counting OUT is set low immediately no clock pulse required 2 Writing the second byte allows the new count to be loaded on the next CLK pulse 2 91 This allows the counting sequence to be synchroniz ed by software Again OUT does not go high until N 1 CLK pulses after the new count of N is written if an initial count is written while GATE O it will still be loaded on the next CLK pulse When GATE goes high OUT will go high N CLK putses later no CLK pulse is needed to l
71. h a simple software maintenance routine The modes for Port A and Port B can be separately defined while Port C is divided into two portions as required by the Port A and Port B definitions All of the output registers including the status flip flops will be reset whenever the mode is changed Modes may be combined so that their functional definition can be tailored to almost any I O structure For instance Group B can be programmed in Mode 0 to monitor simple switch closings or display computa tional results Group A could be programmed in Mode 1 to monitor a keyboard or tape reader on an interrupt driven basis Pa MD MSC PAPA 8 A vo HO PB PB CONTROL OR 1 0 CONT PAP onno th a BI DIRECTIONAL VO A PA PA CONTROL 231256 5 Figure 5 Basic Mode Definitions and Bus interface CONTROL WORD PORT C LOWER 1 INPUT 0 OUTPUT PORT B Te INPUT 0 OUTPUT MODE SELECTION 0 MODE O 1e MODE 1 231256 6 Figure 6 Mode Definition Format The mode definitions and possible mode combina tions may seem confusing at first but after a cursory review of the complete device operation a simple logical 1 O approach will surface The design of the 82C55A has taken into account things such as effi cient PC board layout control signal definition vs PC layout and complete functional flexibility to support almost any peripheral device with no external logic Such design represents the maximum use of the a
72. h as mode bit set bit reset etc that initializes the func tional configuration of the 82C55A en eer en emee Each of the Control blocks Group A and Group B accepts commands from the Read Write Control Logic receives control words from the internal data bus and issues the proper commands to its as sociated ports Control Group A Port A and Port C upper C7 C4 Control Group B Port B and Port C lower C3 C0 The contro word register can be both written and read as shown in the address decode table in the pin descriptions Figure 6 shows the control word format for both Read and Write operations When the contro word is read bit D7 will always be a logic 4 as this implies control word mode information Ports A B and C The 82C55A contains three 8 bit ports A B and C All can be configured in a wide variety of functional characteristics by the system software but each has its own special features or personality to further enhance the power and flexibility of the 82C55A Port A One 8 bit data output latch buffer and one 8 bit input latch buffer Both pull up and pull down bus hold devices are present on Port A Port B One 8 bit data input output latch buffer Only pull up bus hold devices are present on Port B Port C One 8 bit data output latch buffer and one 8 bit data input buffer no latch for input This port can be divided into two 4 bit p
73. he above discussions ap ply here also Specifically if multiple count and or status read back commands are issued to the same counter s without any intervening reads all but the first are ignored This is illustrated in Figure 13 If both count and status of a counter are latched the first read operation of that counter will return latched status regardless of which was latched first The next one or two reads depending on whetner the counter is programmed for one or two type counts return latched count Subsequent reads return un latched count Results Count and status latched for Counter O Command ignored status already latched for Counter 1 82C54 cs AD WR AA o 1 0 0 0 writeimioCountero ol Jolol Write into Counter 1 ol ofa o wrteinocourter2 o 1 o 1 write control word o o 0 0 ReastromCountero RE aloji Read from Counter 1 ER Read from Counter 2 o of 1 1 NoOperation a Stato 1 x x x x no Operation 3 State Lo 1 x x no Operation 3 State Figure 14 Read Write Operations Summary Mode Definitions The following are defined for use in describing the operation of the 82C54 CLK PULSE a rising edge then a falling edge in that order of a Counter s CLK input TRIGGER a rising edge of a Counter s GATE in put COUNTER LOADING the transfer of a count
74. ial count on the next CLK pulse Thus the GATE input can be used to synchronize the Counter After writing a Control Word and initial count the Counter will be loaded on the next CLK pulse This allows the Counter to be synchronized by software also Writing a new count while counting does not affect the current counting sequence If a trigger is re ceived after writing a new count but before the end of the current half cycle of the square wave the Counter will be loaded with the new count on the next CLK pulse and counting will continue from the new count Otherwise the new count will be loaded at the end of the current half cycle Mode 3 is implemented as follows Even counts OUT is initially high The initial count is loaded on one CLK pulse and then is decremented by two on succeeding CLK pulses When the count expires OUT changes value and the Counter is re loaded with the initial count The above process is repeated indefinitely Odd counts OUT is initially high The initial count minus one an even number is loaded on one CLK pulse and then is decremented by two on succeed ing CLK pulses One CLK pulse after the count ex pires OUT goes low and the Counter is reloaded with the initial count minus one Succeeding CLK pulses decrement the count by two When the count expires OUT goes high again and the Counter is reloaded with the initial count minus one The above process is repeated indefinitely So for odd counts
75. icated grounds or 16 single ended operation When the eight switches are OPEN forward they support 8 differential or 16 single ended inputs depending on the setting of P4 When the switches are CLOSED back they support 8 single ended inputs with dedicated grounds With P4 set to D switches can be individually set for differential or single ended with ground operation Switch 1 sets channel 1 switch 2 sets channel 2 etc The table below shows the three configurations for P4 and S2 Input Configuration S2 Switches 8 DIFF 8 SE with AGND D CLOSED Fig 1 10 Differential Single Ended Ground Switch S2 1 8 S3 A D Conversion Rate Factory Setting 7 5 Hz DIP switch S3 shown in Figure 1 11 configures the board to perform A D conversions at a rate of 7 5 conver sions per second 7 5 Hz or 30 conversions per second 30 Hz The four switches operate as a group When all of the switches are in the DOWN closed position the conversion rate is 7 5 Hz This setting provides maximum rejection of 60 Hz line noise When all of the switches are in the UP open position the conversion rate is 30 Hz If you have 50 Hz line power and specified 6 25 25 Hz for your conversion speeds when ordering then down is 6 25 Hz and up is 25 Hz When changing the settings make sure ALL FOUR switches are set to the same position Note that the board has been factory calibrated for a 7 5 Hz rate If you chang
76. ied testing and debugging of prototype circuitry and XT50 and XP40 flat ribbon cable assemblies for external interfacing Using This Manual This manual is intended to help you install your new board and get it running quickly while also providing enough detail about the board and its functions so that you can enjoy maximum use of its features even in the most complex applications We assume that you already have an understanding of data acquisition principles and that you can customize the example software or write your own applications programs When You Need Help This manual and the example programs in the software package included with your board provide enough information to properly use all of the board s features If you have any problems installing or using this board contact our Technical Support Department 814 234 8087 during regular business hours eastern standard time or eastern daylight time or send a FAX requesting assistance to 814 234 5218 When sending a FAX request please include your company s name and address your name your telephone number and a brief description of the problem i4 CHAPTER 1 BOARD SETTINGS The ADAS20 has jumper and switch settings you can change if necessary for your application The board is factory configured with the most often used settings The factory settings are listed and shown on a diagram in the beginning of this chapter Should you need to change these settings
77. iety of conditions are met By using these interrupts you can write software that effectively deals with real world events Interrupt Request Lines To allow different peripheral devices to generate interrupts on the same computer the PC bus has eight different interrupt request IRQ lines A transition from low to high on one of these lines generates an interrupt request which is handled by the PC s interrupt controller The interrupt controller checks to see if interrupts are to be acknowledged from that IRQ and if another interrupt is already in progress it decides if the new request should supersede the one in progress or if it has to wait until the one in progress is done This prioritizing allows an interrupt to be interrupted if the second request has a higher priority The priority level is based on the number of the IRQ IRQO has the highest priority IRQ1 is second highest and so on through IRQ7 which has the lowest Many of the IRQs are used by the standard system resources IRQO is used by the system timer IRQ is used by the key board IRQ3 by COM2 IRQ4 by COMI and IRQ6 by the disk drives Therefore it is important for you to know which IRQ lines are available in your system for use by the ADA520 board 8259 Programmable Interrupt Controller The chip responsible for handling interrupt requests in the PC is the 8259 Programmable Interrupt Controller To use interrupts you need to know how to read and set the 8259 s interru
78. l 1 to monitor the output of DACI WAVES A more complex program that shows how to use the 8254 timer and the DACs as a waveform generator BASIC Programs These programs are source code files so that you can easily develop your own custom software for your ADAS20 board Analog to Digital SINGLE Demonstrates how to use the single convert mode for acquiring data SCAN Demonstrates how to scan channels to acquire data Timer Counters TIMER short program demonstrating how to program the 8254 for use as a timer Digital I O DIGITAL Simple program that shows how to read and write the digital I O lines Digital to Analog DASCAN Demonstrates D A conversion 4 24 CHAPTER 5 CALIBRATION This chapter tells you how to calibrate the ADA520 using the nine trimpots on the board These trimpots calibrate the A D input voltage range and gain the D A outputs and the reference current and voltage outputs available at connector P2 Calibration may be required if you change the A D conversion rate from 7 5 to 30 Hz or whenever you suspect inaccurate readings 5 2 This chapter tells you how to calibrate the A D converter input voltage range and gain the D A outputs and the reference current and voltage outputs The offset and full scale performance of the board s A D converter is factory calibrated for operation at 7 5 Hz If you change the conversion rate you may need to recalibrate your board Any
79. l be described The internal block diagram of a single counter is shown in Figure 5 The Counters are fully independent Each Counter may operate in a different Mode The Control Word Register is shown in the figure it is not part of the Counter itself but its contents de termine how the Counter operates 82C54 231244 6 Figure 5 Internal Block Diagram of a Counter The status register shown in the Figure when latched contains the current contents of the Control Word Register and status of the output and null count flag See detailed explanation of the Read Back command The actual counter is labelled CE for Counting Ele ment It is a 16 bit presettable synchronous down counter Oly and OL are two 8 bit latches OL stands for Output Latch the subscripts M and L stand for Most significant byte and Least significant byte respectively Both are normally referred to as one unit and called just OL These latches normally fol low the CE but if a suitable Counter Latch Com mand is sent to the 82C54 the latches latch the present count until read by the CPU and then return to following the CE One latch at a time is enabled by the counter s Control Logic to drive the internal bus This is how the 16 bit Counter communicates over the 8 bit internal bus Note that the CE itself cannot be read whenever you read the count it is the OL that is being read
80. l mode P4 D S2 OPEN twisted pair cable is recommended to reduce the effects of magnetic coupling at the input Your signal source may or may not have a separate ground reference When using the differential mode you should install a 10 kilohm resistor pack at RN7 on the board to provide a reference to ground for signal sources without a separate ground reference Connect the high side of the analog input to the selected analog input channel AIN1 through AIN8 and connect the low side to the corresponding AIN pin Then for signal sources with a separate ground reference connect the ground from the signal source to an ANALOG GND pins 18 and 20 22 on P2 Figure 2 4 shows how these connections are made Note that you can mix single ended with dedicated ground and differential channels by setting the individual switches on S2 to the proper position 820 UO CONNECTOR Pz SIGNAL SOURCE 1 OUT Fig 2 4 Differential Input Connections Connecting the Trigger In and Trigger Out Pins Cascading Boards The ADA520 board has an external trigger input P3 19 and output P3 21 so that two or more boards can be cascaded and run synchronously in a master slave configuration By cascading two or more boards as shown in Figure 2 5 they can be triggered to start an A D conversion at the same time Connecting the Analog Outputs For each of the two D A outputs connect the high side of the device receiving the
81. level output current Isink nennen 64 mA max D A GONVOROR T AD7237 Analog QUIPUIS als 2 channels HOSOlU RI ee hie Senne ern 12 bits Output ranges annen eenen Oto 5 5 Oto 10 10 volts Guaranteed linearity across output ranges Oto 5 5 0 to 9 2 9 2 volts Relative accuracy ear Renta ae 1 bit max Full scale accuracy rauser en neee 5 bits max A IS NON 1 bit max DOUG A A A AN 10 usec max Miscellaneous Outputs Reference current output Reference voltage output 5 volts 12 volts Digital ground Current Requirements Connectors P2 50 pin right angle shrouded box header P3 40 pin box connector Size 3 875 H x 8 90 W 99mm x 226mm A4 B 1 APPENDIX B CONNECTOR PIN ASSIGNMENTS B 2 P2 Connector DIFF S E AOUT AOUT2 ANALOG GND PA7 PA6 PAS PA4 PA3 PA2 PAS PAO OOS COCO DIFF S E AIN1 AIN9 AGND AIN2 AIN10 AGND AIN3 AIN11 AGND AIN4 AIN12 AGND AINS AIN13 AGND AING AIN14 AGND AIN7 AIN1S AGND AINS AIN16 AGND ANALOG GND ANALOG GND ANALOG GND PC7 PC6 Pcs PC4 PC3 PC2 PCI PCO 12 VOLTS DIGITAL GND OOOO GO OGO IOUT 60 ANALOG GND VOUT 42 ANALOG GND DIGITAL GND tc oure EXT CLK 2 65 ext GATE 2 12 VOLTS 5 VOLTS P3 Connector PPI 87 100 P87 PPI B6 PB6 PPI B5 PB5 PPI B4 PB4 PPI B3 PB3 PPI B2 PB2 PPI B1 PB1 PPI BO PBO
82. local distributor Board Accessories In addition to the items included in your ADA520 package Real Time Devices offers a full line of software and hardware accessories Call your local distributor or our main office for more information about these accessories and for help in choosing the best items to support your board s application Application Software and Drivers Our custom application software packages provide excellent data acquisition and analysis support Use SIGNAL MATH for integrated data acquisition and sophisticated digital signal processing and analysis or ATLANTIS for real time monitoring and data acquisition rtdLINX and labLINX drivers provide full featured high level interfaces between the ADA520 and custom or third party software including LABTECH NOTEBOOK NOTEBOOK XE and LT CONTROL rtdLINX source code is available for a one time fee Our Pascal and C Programmer s Toolkit provides routines with documented source code for custom programming Hardware Accessories Hardware accessories for the ADAS20 include the MX32 analog input expansion board which can expand a single input channel on your ADA520 to 16 differential or 32 single ended input channels MR series mechanical relay output boards OP series optoisolated digital input boards the TS16 temperature sensor board the TB50 terminal board and XBSO prototype terminal board for easy signal access and prototype development the EX XT and EX AT extender boards for simplif
83. ltage 3 0 Eca V lon 2 5 mA Voc 0 4 V loH 100 pA Input Leakage Current 1 pA Vin Vec to OV Note 1 lorL Output Float Leakage Current 10 pA Vin Voc to OV Note 2 Darlington Drive Current 25 Note 4 mA Ports A B C Rext 5000 Vext 1 7V IpHL Port Hold Low Leakage Current 50 300 pA Vout 1 0V _ Port A only Port Hold High Leakage Current pA Vout 3 0V Ports A B C Port Hold Low Overdrive Current Do pa Vour 0 8V IpHHo Port Hold High Overdrive Current 350 pa Vour 30v Voc Supply Current mA Vec Supply Current Standby o 0 gt q gt o 3 a a Vin Voc or GND Port Conditions If I P Open High O P Open Only With Data Bus High Low CS High Reset Low Pure Inputs Low High NOTES 1 Pins Ay Ao CS WA RD Reset nn Data Bus Ports B C x 3 Outputs open i 4 Limit output current to 4 0 mA 3 141 am T T ll ml intel 82C55A CAPACITANCE Ta 25 C Vcc GND OV Symbol Parameter Min Max Units Cn imputCapacitancs w pr NOTE 5 Sampled not 100 tested Test Conditions Unmeasured pins returned to GND fe 1 MHz 5 A C CHARACTERISTICS Ta 0 to 70 C Voc 5V 10 GND OV Ta 40 C to 85 C for Extended Temperature BUS PARAMETERS READ CYCLE wn Address StabieBetoroADL o m tm LS Hold Time
84. n the 82C54 There are three possible methods for reading the counters a simple read operation the Counter Latch Command and the Read Back Command Each is explained below The first method is to per form a simple read operation To read the Counter which is selected with the A1 AO imputs the CLK input of the selected Counter must be inhibited by using either the GATE input or external logic Other wise the count may be in the process of changing when it is read giving an undefined result 82C54 COUNTER LATCH COMMAND The second method uses the Counter Latch Com mand Like a Control Word this command is written to the Control Word Register which is selected when Ay Ao 11 Also like a Control Word the SCO SC1 bits select one of the three Counters but two other bits D5 and D4 distinguish this command from a Control Word Ay Ao 11 CS 0 RD 1 WR 0 D Ds Ds D4 D3 D2 D Do sci sco o o x x x x SC1 SCO specify counter to be latched SC1 SCO Counter Read Back Command D5 D4 00 designates Counter Latch Command X don t care NOTE Don t care bits X should be O to insure compatibility with future Intel products Figure 9 Counter Latching Command Format The selected Counter s output latch OL latches the count at the time the Counter Latch Command is received This count is held in the latch until it is read by the CPU or until the Counter is reprogrammed The
85. n the count value latched Writing a Counter Latch or ReadBack Command between Tc min and Tw max will result in a latched count valiue which is one least significant bit EXTENDED TEMPERATURE TA 40 C to 85 C for Extended Temperature RE a me En uti lc Oberland 2 25 ss m ine Gate Delay forSamping 2 2 26 m intel 82C54 WAVEFORMS WRITE DATA BUS 23124414 READ gt tos 2 A 231244 15 RECOVERY 3 98 CLOCK AND GATE 23124417 Last byte of count being written A C TESTING LOAD CIRCUIT 23124418 A C Testing Inputs are driven at 2 4V for a logic 1 and 0 45V for a logic 0 Timing measurements are made at 2 0V for a logic 1 and 0 8V for a logic 0 231244 19 3 99 Intel 82C55A Programmable Peripheral Interface Data Sheet Reprint gt E Intel 82C55A CHMOS PROGRAMMABLE PERIPHERAL INTERFACE m Compatible with all Intel and Most m Control Word Read Back Capability Other Microprocessors m Direct Bit Set Reset Capability m High Speed Zero Wait State ADC bilit Wi Operation with 8 MHz 8086 88 and ren ae Availabie in 40 Pin DIP and 44 Pin PLCC B 24 Programmable I O Pins a S w 9 m Available in EXPRESS m Low Power CHMOS Standard Temperature Range m Completely TTL Compatible Extended Temperature Range The Intel 82C55A is a high performance CHMOS
86. nalog input channel 1 this can be done by simply connecting the analog input to ground when in the single ended mode Set the gain to 1 and start continuous A D conversions Adjust trimpot TR9 until the conversion output is zero Then change the gain to 10 and repeat the conversion process adjusting TRS until the conversion output is zero Change the gain to 100 and repeat the procedure this time adjusting TR7 until the output is zero Finally change the gain to 1000 and adjust TR6 until the output is zero The trimpot assignment is summarized below The offset voltage is related solely to the performance of the programmable gain amplifier however the offset can affect the rollover performance of the A D converter if it is not set to zero Rollover is the difference in conver sion results between voltages having the same amplitude but different polarities Any gains which do not have a zero offset will give readings that are shifted from an ideal zero reference This means that the positive and negative readings for the same voltage will be slightly different This difference is caused by the offset 5 4 Full Scale Adjustment The full scale adjustment calibrates the reference voltage used by the A D converter to compensate for the analog input circuitry Set the gain and channel to 1 start continuous A D conversions and display the conversion results Apply the voltage source to the analog input and adjust it so that it
87. nded Temperature Input Low Voltage Output Low Voltage Input Load Current ES Vec Supply Current pnl Vec Supply Current Standby Cin I O Capacitance Output Capacitance A C CHARACTERISTICS Symbol Mn Units cos E EE E Vm inputHigh Voltage 20 vyoros v lt el EM FE V lorL Output Float Leakage Current BA VouT Vag to 00V mA BMHz 82C54 Cy Input Capacitance 0 T gt Test Conditions lon 2 5 mA V lo 2 5 mA loH 100 pA 20 Vin Voc to OV CLK Freq DC CS Vcc All Inputs Data Bus Voc All Outputs Floating Unmeasured pins returned to GND S Ta 0 C to 70 C Voo 5V 10 GND 0V TA 40 C to 85 C for Extended Temperature BUS PARAMETERS Note 1 READ CYCLE Symbol Parameter Address Stable Before RD Address Hold Time After RD T AD Pulse Width tan paia Delay from AD RD T to Data Floating Command Recovery Time NOTE 1 AC timings measured at Voy 2 0V Vo 0 8V Min tan En tsa ER Sabie Belas BB L o z er MEM Es Data Delay from Address ied 20 intel 82054 A C CHARACTERISTICS continued WRITE CYCLE Parameter Address Stable Before WA CS Stable Before WR Address Hold Time After WR T R Pulse Width Data Setup Time Before WR T ata Hold Time After WR T ommand Recovery Time gt W gt W
88. ns above is ac ceptable A new initial count may be written to a Counter at any time without affecting the Counter s pro grammed Mode in any way Counting will be affected as described in the Mode definitions The new count must follow the programmed count format If a Counter is programmed to read write two byte counts the following precaution applies A program must not transfer control between writing the first and second byte to another routine which also writes into that same Counter Otherwise the Counter will be loaded with an incorrect count h Control Word Counter 2 Control Word Counter 1 Control Word Counter O LSB of count Counter 2 MSB of count Counter 2 LSB of count Counter 1 MSB of count Counter 1 LSB of count Counter 0 0020022 COO a m aaa Y MSB of count Counter O Control Word Counter 1 Control Word Counter O LSB of count Counter 1 Control Word Counter 2 LSB of count Counter O MSB of count Counter 1 LSB of count Counter 2 MSB of count Counter O MSB of count Counter 2 0 200 0 k ua P 20000229 In all four examples all counters are programmed to read write two byte counts These are only four of many possibie programming sequences Figure 8 A Few Possible Programming Sequences Read Operations It is often desirable to read the value of a Counter without disturbing the count in progress This is easi ly done i
89. nt value COUNTER New counts are loaded and Counters are decre mented on the falling edge of CLK The largest possible initial count is O this is equiva lent to 216 for binary counting and 104 for BCD counting The Counter does not stop when it reaches zero In Modes 0 1 4 and 5 the Counter wraps around to the highest count either FFFF hex for binary count ing or 9999 for BCD counting and continues count ing Modes 2 and 3 are periodic the Counter reloads itself with the initial count and continues counting from there 82C54 ABSOLUTE MAXIMUM RATINGS Ambient Temperature Under Bias 0 C to 70 C Storage Temperature 65 to 150 C Supply Voltage 0 5 to 8 0V Operating Voltage 4V to 7V Voltage on any Input GND 2V to 6 5V Voltage on any Output GND 0 5V to Voc 0 5V Power Dissipation o o ooo 1 Watt D C CHARACTERISTICS Notice Stresses above those listed under Abso lute Maximum Ratings may cause permanent dam age to the device This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the opera tional sections of this specification is not implied Ex posure to absolute maximum rating conditions for extended periods may affect device reliability Ta 0 C to 70 C Voc 5V 10 GND 0V Ta 40 C to 85 C for Exte
90. oad the Counter as this has already been done ojojoj ojo jer sr Pefefufnfototo s o er se Cwete 8803 u AAA ae Leal sle sigi CW to 1880 180 2 GATE TTT A AMAN DIREI EHEHE 231244 8 NOTE The Following Conventions Apply To All Mode Timing Diagrams 1 Counters are programmed for binary not BCD counting and for Reading Writing least significant byte LSB only 2 The counter is always selected CS always low 3 CW stands for Control Word CW 10 means a control word of 10 hex is written to the counter 4 LSB stands for Least Significant Byte of count 5 Numbers below diagrams are count values The lower number is the least significant byte The upper number is the most significant byte Since the counter is programmed to Read Write LSB only the most significant byte cannot be read N stands for an undefined count Vertical lines show transitions between count values Figure 15 Mode O 82C54 MODE 1 HARDWARE RETRIGGERABLE ONE SHOT OUT will be initially high OUT will go low on the CLK pulse following a trigger to begin the one shot pulse and will remain low until the Counter reaches zero OUT will then go high and remain high until the CLK pulse after the next trigger After writing the Control Word and initial count the Counter is armed A trigger results in loading the Counter and setting OUT low on the next CLK p
91. oblem such as those which involve checking to see if any DOS functions are currently active when your ISR is called but such solutions are well beyond the scope of this discussion The second major concern when writing your ISR is to make it as short as possible in terms of execution time Spending long periods of time in your ISR may mean that other important interrupts are being ignored Also if you spend too long in your ISR it may be called again before you have completed handling the first run This often leads to a hang that requires a reboot Your ISR should have this structure Push any processor registers used in your ISR Most C and Pascal interrupt routines automatically do this for you Put the body of your routine here Issue the EOI command to the 8259 interrupt controller by writing 20H to port 20H Pop all registers pushed on entrance Most C and Pascal interrupt routines automatically do this for you The following C and Pascal examples show what the shell of your ISR should be like In C void interrupt ISR void Your code goes here Do not use any DOS functions outportb 0x20 0x20 Send EOI command to 8259 In Pascal Procedure ISR Interrupt begin Your code goes here Do not use any DOS functions Port 20 20 Send EOI command to 8259 end Saving the Startup Interrupt Mask Register IMR and Interrupt Vector The next step after writing the ISR is to save the startup
92. or an output When set up as inputs a read transfers data from the external device through P2 and onto the board where it can be placed in user memory when set up as outputs a write transfers the written data from the board through P2 to an external device BA 6 Port B Digital VO Lines Read Write Transfers the 8 bit Port B buffered digital input and digital output data between the board and an external device This is not the same as the 8255 PPI Port B lines the PPI lines are controlled at BA 1 BA 4 is used to set up the port as an input or an output When set up as inputs a read transfers data from the external device through P3 and onto the board where it can be placed in user memory when set up as outputs a write transfers the written data from the board through P3 to an external device BA 7 Port C Digital I O Lines Read Write Transfers the 8 bit Port C buffered digital input and digital output data between the board and an external device BA 4 is used to set up the port as an input or an output When set up as inputs a read transfers data from the external device through P2 and onto the board where it can be placed in user memory when set up as outputs a write transfers the written data from the board through P2 to an external device 4 7 BA 8 8254 Timer Counter 0 Read Write A read shows the count in the counter and a write loads the counter with a new value Counting begins as soon as the co
93. orts under the mode control Each 4 bit port contains a 4 bit latch and it can be used for the control signal outputs and status signal inputs in conjunction with ports A and B Only pull up bus hold devices are present on Port C See Figure 4 for the bus hold circuit configuration for Port A B and C 3 126 intel B2C55A BIDIRECTIONAL DATA BUS DATA WR NOTE 231256 4 Port pins loaded with more than 20 pF capacitance may not have their logic level guaranteed following a hardware reset Figure 4 Port A B C Bus hold Configuration 3 127 Ter e mercado do mn intel 82C55A 82C55A OPERATIONAL DESCRIPTION Mode Selection There are three basic modes of operation that can be selected by the system software Mode 0 Basic input output Mode 1 Strobed Input output Mode 2 Bi directiona Bus When the reset input goes high all ports will be set to the input mode with all 24 port lines held at a logic one level by the interna bus hold devices see Figure 4 Note After the reset is removed the 82C55A can remain in the input mode with no addi tional initialization required This eliminates the need for pullup or pulldown devices in all CMOS de signs During the execution of the system program any of the other modes may be selected by using a single output instruction This allows a single 82C55A to service a variety of peripheral devices wit
94. ou write First on entrance the processor registers should be pushed onto the stack BEFORE you do anything else Second just before exiting your ISR you must clear the interrupt status of the ADAS20 and write an end of interrupt command to the 8259 controller Finally when exiting the ISR in addition to popping all the registers you pushed on entrance you must use the IRET instruction and not a plain RET The IRET automatically pops the flags CS and IP that were pushed when the interrupt was called If you find yourself intimidated by interrupt programming take heart Most Pascal and C compilers allow you to identify a procedure function as an interrupt type and will automatically add these instructions to your ISR with one important exception most compilers do not automatically add the end of interrupt command to the procedure you must do this yourself Other than this and the few exceptions discussed below you can write your ISR just like any other routine It can call other functions and procedures in your program and it can access global data If you are writing your first ISR we recommend that you stick to the basics just something that will convince you that it works such as incrementing a global variable NOTE If you are writing an ISR using assembly language you are responsible for pushing and popping registers and using IRET instead of RET There are a few cautions you must consider when writing your ISR The most important is
95. output to the AOUT channel P2 17 or P2 19 and connect the low side of the device to an ANALOG GND P2 18 or P2 20 Connecting the Timer Counters and Digital O For all of these connections the high side of an external signal source or destination device is connected to the appropriate signal pin on the I O connector and the low side is connected to any DIGITAL GND Running the 520DIAG Diagnostics Program Now that your board is ready to use you will want to try it out An easy to use menu driven diagnostics program 520DIAG is included with your example software to help you verify your board s operation You can also use this program to make sure that your current base address setting does not contend with another device 520 1O CONNECTOR BOARD 1 MASTER BOARD 82 SLAVE Q ap e O m a m m e 8 8 TRIGGER IN Fig 2 5 Cascading Two Boards for Simultaneous Sampling 2 7 CHAPTER 3 HARDWARE DESCRIPTION This chapter describes the features of the ADA520 hardware The major circuits are the A D D A digital I O and 8254 timer counter Board interrupts are also described in this chapter 3 1 The ADA520 has four major circuits the A D the D A digital I O and timer counters Figure 3 1 shows the block diagram of the board This chapter describes the hardware which makes up the major circuits It also discusses interrupts 16 ANALOG INPUTS are te 12 BIT
96. pt mask register IMR and how to send the end of interrupt EOI command to the 8259 Interrupt Mask Register IMR Each bit in the interrupt mask register IMR contains the mask status of an IRQ line bit O is for IRQO bit 1 is for IRQ1 and so on If a bit is set equal to 1 then the corresponding IRQ is masked and it will not generate an interrupt If a bit is clear equal to 0 then the corresponding IRQ is unmasked and can generate interrupts The IMR is programmed through port 21H ar os os mas Tas maz Tas meo vormen For all bits 0 IRQ unmasked enabled 1 IRQ masked disabled End of Interrupt EOI Command After an interrupt service routine is complete the 8259 interrupt controller must be notified This is done by writing the value 20H to I O port 20H 4 18 What Exactly Happens When an Interrupt Occurs Understanding the sequence of events when an interrupt is triggered is necessary to properly write software interrupt handlers When an interrupt request line is driven high by a peripheral device such as the ADA520 the interrupt controller checks to see if interrupts are enabled for that IRQ and then checks to see if other interrupts are active or requested and determines which interrupt has priority The interrupt controller then interrupts the proces sor The current code segment CS instruction pointer IP and flags are pushed on the stack for storage and a new CS and IP are loade
97. rdware Retriggerable One Shot Mode 2 Rate Generator Mode 3 Square Wave Mode Mode 4 Software Triggered Strobe Mode 5 Hardware Triggered Strobe Retriggerable These modes are detailed in the 8254 Data Sheet reprinted from Intel in Appendix C Interrupts The ADA520 can use any one of five signal sources to generate interrupts These sources are A D end of convert EOC OUT1 and OUT 2 from the 8254 timer counter PCO from the 8255 PPI and the trigger in TRIGIN Chapter 1 tells you how to set the jumpers on interrupt header connector P9 and Chapter 4 provides some program ming information 3 4 CHAPTER 4 BOARD OPERATION AND PROGRAMMING This chapter shows you how to program and use your ADA520 board It provides a complete description of the I O map a detailed description of programming operations and a flow diagram to aid you in programming The example programs included on the disk in your board package are listed at the end of this chapter These programs written in Turbo C Turbo Pascal and BASIC include source code to simplify your applications programming Defining the VO Map The I O map for the ADA520 is shown in Table 4 1 belo port locations The base address designated as BA can be se Board Settings This switch can be accessed without removing the board from the computer S1 is factory set at 300 w As shown the board occupies 16 consecutive I O lected using DIP switch S1 as desc
98. re compatibility with future Intel products Binary Counter 16 bits Binary Coded Decima BCD Counter 4 Decades Figure 7 Control Word Format intel 82C54 Write Operations The programming procedure for the 82C54 is very flexible Only two conventions need to be remem bered 1 For each Counter the Control Word must be written before the initial count is written 2 The initial count must follow the count format specified in the Control Word least significant byte only most significant byte only or least sig nificant byte and then most significant byte Since the Control Word Register and the three Counters have separate addresses selected by the Ay Ao inputs and each Control Word specifies the Counter it applies to SCO SC1 bits no special in a Control Word Counter O LSB of count Counter 0 MSB of count Counter O Control Word Counter 1 LSB of count Counter 1 MSB of count Counter 1 Control Word Counter 2 LSB of count Counter 2 MSB of count Counter 2 2 0Q00 4 00 4 PP oO4u 1 004P Control Word Counter 0 Counter Word Counter 1 Control Word Counter 2 LSB of count Counter 2 LSB of count Counter 1 LSB of count Counter O MSB of count Counter O MSB of count Counter 1 MSB of count Counter 2 0000 44 uP 0200029 NOTE struction sequence is required Any programming sequence that follows the conventio
99. reading the first and second byte to another routine which also reads from that same Counter Otherwise an incorrect count will be read READ BACK COMMAND The third method uses the Read Back command This command allows the user to check the count value programmed Mode and current state of the OUT pin and Null Count flag of the selected coun ter s The command is written into the Control Word Reg ister and has the format shown in Figure 10 The command applies to the counters selected by set ting their corresponding bits D3 D2 D1 1 A0 A1 11 CS 0 RD 1 WR 0 D7 Ds Ds Da D3 Db Du Do 1 count srarus onr slour lansa Ds O Latch count of selected counter s Da O Latch status of selected counter s Da 1 Select counter 2 D2 1 Select counter 1 Ds 1 Select counter 0 Do Reserved for future expansion must be 0 Figure 10 Read Back Command Format The read back command may be used to latch multi le counter output latches OL by setting the COUNT bit D5 0 and selecting the desired coun ter s This single command is functionally equiva lent to several counter latch commands one for each counter latched Each counter s latched count is held until it is read or the counter is repro grammed That counter is automatically unlatched when read but other counters remain latched until they are read If multiple count read back commands are issued to the same counter without reading the 82C
100. ribed in Chapter 1 hex 768 decimal The following sections describe the register contents of each address used in the VO map Table 4 1 ADA520 I O Map Read Function Read A D converted data PPI Port A Read Data MSB amp LSB PPI Port B Read 8 digital input lines PPI Port Contra PPI Control Word Reserved ID Register Buffered Digital VO Direction Read ID number value 1 Port A Buffered VO Read Port A digital input lines Port B Buffered VO Read Port B digital input lines Update All DACs D A Converter 1 LSB Update outputs of all DACs Status D A Converter 1 MSB Read A D converter status Port C Buffered I O BA Base Address 4 3 Program 8 digital output lines Program control lines Program PPI configuration Program digital VO Ports A B amp C as inputs or outputs non 8255 digital VO lines Program Port A digital output lines Program Port B digital output lines Program Port C digital output BA 2 BA 4 BA 7 Load TCO count register Load TC1 count register Load TC2 count register Program control register Program DAC1 LSB Program DAC1 MSB Program DAC2 LSB Program DAC2 MSB BA 10 BA 13 BA 14 BA 15 Address Decimal BA 0 PPI Port A Read A D Data Read Only This address is used to read the MSB and LSB of the A D conversion as defined below When bit 7 of the PPI Port C word PC7 is 0 the MSB is read when PC7 is
101. rite operations NC 1 12 No Connect 23 34 3 125 PA7 4 37 40 41 44 O PORT A PINS 4 7 Upper nibble of an 8 bit data output latch buffer and an 8 bit data input latch 82C55A 82C55A FUNCTIONAL DESCRIPTION The 82C55A is a programmable peripheral interface device designed for use in Intel microcomputer sys tems Its function is that of a general purpose O component to interface peripheral equipment to the microcomputer system bus The functional configu ration of the 82C55A is programmed by the system software so that normally no external logic is neces sary to interface peripheral devices or structures Data Bus Buffer This 3 state bidirectional 8 bit buffer is used to inter face the 82C55A to the system data bus Data is transmitted or received by the buffer upon execution of input or output instructions by the CPU Control words and status information are also transferred through the data bus buffer Read Write and Control Logic The function of this block is to manage all of the internal and external transfers of both Data and Control or Status words It accepts inputs from the CPU Address and Control busses and in turn issues commands to both of the Control Groups Group A and Group B Controis The functional configuration of each port is pro grammed by the systems software In essence the CPU outputs a control word to the 82C55A The control word contains information suc
102. rom Port C A normal read operation of Figure 17a MODE 1 Status Word Format Port C is executed to perform this function CAREN TT GROUP A GROUP B Defined By Mode 0 or Mode 1 Selection Figure 17b MODE 2 Status Word Format interrupt Enable Flag Position Alternate Port C Pin Signal Mode INTEB PC2 ACKg Output Mode 1 or STBg input Mode 1 INTE A2 STBA Input Mode 1 or Mode 2 INTE A ACK Output Mode 1 or Mode 2 Figure 18 Interrupt Enable Fiags in Modes 1 and 2 3 140 intel 82C55A ABSOLUTE MAXIMUM RATINGS Notice Stresses above those listed under Abso lute Maximum Ratings may cause permanent dam Ambient Temperature Under Bias 0 C to 70 C age to the device This is a stress rating only and Storage Temperature 65 C to 150 C functional operation of the device at these or any other conditions above those indicated in the opera Supply Voltage FORMEN tional sections of this specification is not implied Ex Operating Voltage 4Vto 7V posure to absolute maximum rating conditions for Voltage on any Input GND 2Vto 6 5V extended periods may affect device reliability Voltage on any Output GND 0 5V to Voc 0 5V Power Dissipation anaana 1 Watt D C CHARACTERISTICS Ta 0 C to 70 C Voc 5V 10 GND OV Ta 40 C to 85 C for Extended Temperture Symbol Parameter 04 VoH Output High Vo
103. rrupt vector to point to your ISR Again you can overwrite the appropriate entry in the vector table with a direct memory write but this is a bad practice Instead use either DOS function 25H set interrupt vector or if your compiler provides it the library routine for setting an interrupt vector Remember that vector 8 is for IRQO vector 9 is for IRQ1 and so on 4 20 If you need to program the source of your interrupts do that next For example if you are using the program mable interval timer to generate interrupts you must program it to run in the proper mode and at the proper rate Finally clear the bit in the IMR for the IRQ you are using This enables interrupts on the IRQ Restoring the Startup IMR and Interrupt Vector Before exiting your program you must restore the interrupt mask register and interrupt vectors to the state they were in when your program started To restore the IMR write the value that was saved when your program started to 1 O port 21H Restore the interrupt vector that was saved at startup with either DOS function 35H get interrupt vector or use the library routine supplied with your compiler Performing these two steps will guarantee that the interrupt status of your computer is the same after running your program as it was before your program started running Common Interrupt Mistakes Remember that hardware interrupts are numbered 8 through 15 even though the corresponding IRQs are number
104. rsion The digital to analog D A circuitry on the ADA 520 features two independent 12 bit analog output channels with individually jumper selectable output ranges of 5 to 5 volts 10 to 10 volts O to 5 volts or O to 10 volts Data is programmed into the D A converter and a conversion is automatically triggered for both channels through a single read operation Digital UO The ADAS20 has 32 TTL CMOS compatible digital I O lines which can be directly interfaced with external devices or signals to sense switch closures trigger digital events or activate solid state relays Eight of these lines are provided by Port B of the on board 8255 programmable peripheral interface PPI chip The remaining 24 lines can be programmed in groups of eight as inputs or outputs To ensure high driving capacity CMOS buffers are installed on these 24 lines Pads for installing and activating pull up or pull down resistors on the digital I O lines are included on the board Installation procedures are given at the end of Chapter 1 Board Settings What Comes With Your Board You receive the following items in your ADA520 package e ADAS20 interface board Software and diagnostics diskette with example programs in BASIC Turbo Pascal and Turbo C source code User s manual If any item is missing or damaged please call Real Time Devices Customer Service Department at 814 234 8087 If you require service outside the U S contact your
105. rvoltage protection to 35 volts is provided at the inputs 3 3 A D Converter The dual slope integrating A D converter performs conversions at a rate of either 7 5 or 30 times per second depending on the setting of DIP switch S3 The output is a 12 bit data word plus a sign bit which tells you whether the digital value represents a positive or a negative voltage This gives you an effective resolution of 13 bits The converter samples the input voltage over a window of time before performing the conversion The con verter measures the time required to charge and discharge a capacitor A counter and a reference in the A D chip determine the integration period Because the input signal is sampled for a specified period instead of being instanta neously captured by a sample and hold device spikes and glitches which may be present at the input are averaged out The result is a highly accurate conversion D A Converters Two independent 12 bit analog output channels are included on the ADA520 The analog outputs are generated by two 12 bit D A converters with independent jumper selectable output ranges of 5 10 O to 5 or 0 to 10 volts The 10 volt range has a resolution of 4 88 millivolts the 5 and 0 to 10 volt ranges have a resolution of 2 44 millivolts and the 0 to 5 volt range has a resolution of 1 22 millivolts Digital VO An 8255 programmable peripheral interface PPI is used for digital control functions This high p
106. s not supported by the ADA520 Foreground sampling is omitted because it is not needed on this low speed board Background Sampling The background sampling rate must be set to 100 Hz ATLANTIS the ADA520 and the TS16 Thermocouple Board The TS16 temperature sensor board can be used with the ADA520 and ATLANTIS through a special series of drivers These drivers directly control the TS 16 and convert the voltage developed by the thermocouple to a tem perature before passing the converted value to ATLANTIS The drivers carry a precalculated lookup table that contains all the temperatures for each possible voltage generated by the TS16 This precalculation frees the applica tion software from performing a fifth order polynomial calculation for each data point The temperature values passed to ATLANTIS must be scaled by a factor of 10 This is done by changing the default calibration setting for the high value to 10 for each thermocouple channel All other default settings remain unchanged Five drivers are available to provide from 0 to 8 thermocouple input channels on an ADA520 board This allows support of both thermocouple and non thermocouple channels by a single board The drivers are AD520 ADAS20 driver only no thermocouple channels AD520J ADAS20 driver with support for 1 thermocouple channel channel 1 ADA520J2 ADAS20 driver with support for 2 thermocouple channels channels 1 amp 2 ADA520J4 ADA520 driver with support for 4 thermoco
107. st be used With a Set Reset Port C Bit command any Port C line Taina as an output including INTR IBF and OBF can be written or an interrupt enable flag can be either set or reset Port C lines programmed as inputs including ACK and STB lines associated with Port C are not affected by a Set Reset Port C Bit command Writing to the corresponding Port C bit positions of the ACK and STB lines with the Set Reset Port C Bit command will affect the Group A and Group B interrupt enable flags as illus trated in Figure 18 Current Drive Capability Any output on Port A B or C can sink or source 2 5 mA This feature allows the B2C55A to directly drive Darlington type drivers and high voltage displays that require such sink or source current 3 139 intel 82C55A Reading Port C Status INPUT CONFIGURATION D7 De Ds Ds Da Dz D Do In Mode 0 Port C transfers data to or from the pe ripheral device When the 82C55A is programmed to vo 170 iBFa NTE INTRA INTES lara NTR function in Modes 1 or 2 Port C generates or ac cepts hand shaking signals with the peripheral de GRRUPA SOONER vice Reading the contents of Port C allows the pro Efe ON grammer to test or verify the status of each pe Ds 7 Da ripheral device and change the program flow ac AAE TGE EE EEE Fa a cordingly GROUP A GROUP B There is no special instruction to read the status in formation f
108. tailed discussions of board functions are included in Chapter 3 Hardware Description and Chapter 4 Board Operation and Programming The board setup is described in Chapter 1 Board Settings Analog to Digital Conversion The analog to digital A D circuitry receives 8 differential 8 single ended with dedicated grounds or 16 single ended analog inputs and converts these inputs into 12 bit digital data words which can then be read and or transferred to PC memory The analog input channels can be set for single ended single ended with ground or differential operation by setting a jumper and switch on the board The input voltage range is 5 to 5 volts for a gain of 1 the range is 0 5 to 0 5 volts for gain 10 05 to 05 volts for gain 100 005 to 005 volts for gain 1000 The conversion rate is switch selectable for either 7 5 or 30 Hz The 7 5 Hz rate provides high rejection over 60 dB of 60 Hz line noise Customers with 50 Hz line power can specify 6 25 25 Hz switch selectable rates for high rejection of 50 Hz line noise A D conversions are performed by a 12 bit plus sign bit showing polarity dual slope integrating converter providing effectively 13 bit conversion resolution The programmable gains of 1 10 100 and 1000 let you discern changes in the input voltage as small as 1 3 microvolts The converted data is read and or transferred to PC memory one byte at a time through the PC data bus Digital to Analog Conve
109. the port In BASIC this is programmed as V INP PortAddress V V AND 223 OUT PortAddress V 4 10 To set a single bit in a port OR the current value of the port with the value b where b 2 Example Set bit 3 in a port Read in the current value of the port OR it with 8 8 2 and then write the resulting value to the port In Pascal this is programmed as Vv Port PortAddress V V OR 8 Port PortAddress V Setting or clearing more than one bit at a time is accomplished just as easily To clear multiple bits in a port AND the current value of the port with the value b where b 255 the sum of the values of the bits to be cleared Note that the bits do not have to be consecutive Example Clear bits 2 4 and 6 in a port Read in the current value of the port AND it with 171 171 255 2 2 25 and then write the resulting value to the port In C this is programmed as v inportb port address v v amp 171 outportb port address v i To set multiple bits in a port OR the current value of the port with the value b where b the sum of the individual bits to be set Note that the bits to be set do not have to be consecutive Example Set bits 3 5 and 7 in a port Read in the current value of the port OR it with 168 168 25 25 27 and then write the resulting value back to the port In assembly language this is programmed as mov dx PortAddress in al dx or al
110. time you suspect inaccurate readings you can check the accuracy of your conversions using the procedure below and make adjusts as necessary Using the 520DIAG diagnostics program is a convenient way to monitor conversions while you calibrate the board Calibration is done with the board installed in your system You can access the trimpots at the edge of the board Power up the system and let the board circuitry stabilize for 15 minutes before you start calibrating Required Equipment The following equipment is required for calibration Precision Voltage Source 10 to 10 volts Digital Voltmeter 5 1 2 digits Small Screwdriver for trimpot adjustment A voltage source can be made using a 9 volt battery and a precision 10 turn trimpot as shown in Figure 5 1 While not required the 520DIAG diagnostics program included with example software is heipful when performing calibrations Figure 5 2 shows the board layout with the trimpots located along the top edge of the board 1KQ 9 VOLTS 2KQ Fig 5 1 Adjustable Voltage Source A D Calibration During this procedure you will make connections to the analog input at external I O connector P2 The pin assignments for P2 are given in Appendix B Two adjustments are made to calibrate the A D converter One is the offset adjustment and the other is the full scale adjustment Trimpots TR6 through TR9 adjust the offset and TRS adjusts the full scale voltage
111. ts the ideal output voltages for bipolar ranges Table 5 2 D A Converter Unipolar Calibration Table Ideal Output Voltage in millivolts D A Bit Weight Oto 5 V Oto 10 V Table 5 3 D A Converter Bipolar Calibration Table Ideal Output Voltage in millivolts 4997 6 9995 1 Reference Current and Voltage Out Adjust The ADAS20 has a reference current and reference voltage output available at the P2 I O connector to support external circuit requirements The reference current is factory set for 5 milliamperes You can check the current output or set it to a different level by adjusting TR4 while monitoring the output at P2 39 The reference voltage is factory set for 5 volts You can check the voltage output or set it to a different level by adjusting TR3 while monitor ing the output at P2 41 5 7 APPENDIX A ADA520 SPECIFICATIONS ADAS520 Characteristics Typical 25 C Interface Analog Input IBM PC XT AT compatible Switch selectable base address 1 O mapped Jumper selectable interrupts 16 single ended 8 single ended with dedicated grounds 8 differential inputs Input impedance enen conan E E gt 10 megohms Gains software selectable nn 1 10 100 1000 Gain BMR saven antenne e eT Ra daneen dermee ede deden ideas 0 05 typ 25 max Input TANDO TTT 5 0 5 0 05 0 005 volts Overvoltage protection AAA A 35 Vdc Common mode input voltage
112. ulse thus starting the one shot pulse An initial count of N will result in a one shot pulse N CLK cycles in dura tion The one shot is retriggerable hence OUT will remain low for N CLK pulses after any trigger The one shot pulse can be repeated without rewriting the same count into the counter GATE has no effect on OUT If a new count is written to the Counter during a one shot pulse the current one shot is not affected un less the Counter is retriggered In that case the Counter is loaded with the new count and the one shot pulse continues until the new count expires CWa12 853 MUIH JHH CWet2 LS8 3 Senn ETS CW 12 158 2 RARA RAR A o FF ells 231244 9 Figure 16 Mode 1 MODE 2 RATE GENERATOR This Mode functions like a divide by N counter It is typicially used to generate a Real Time Clock inter rupt OUT will initially be high When the initial count has decremented to 1 OUT goes low for one CLK pulse OUT then goes high again the Counter re loads the initial count and the process is repeated Mode 2 is periodic the same sequence is repeated indefinitely For an initial count of N the sequence repeats every N CLK cycles GATE 1 enables counting GATE O disables counting If GATE goes low during an output pulse OUT is set high immediately A trigger reloads the Counter with the initial count on the next CLK pulse OUT goes low N CLK pulses after the trigger Thus the GATE input can
113. unt is loaded BA 9 8254 Timer Counter 1 Read Write A read shows the count in the counter and a write loads the counter with a new value Counting begins as soon as the count is loaded BA 10 8254 Timer Counter 2 Read Write A read shows the count in the counter and a write loads the counter with a new value Counting begins as soon as the count is loaded BA 11 8254 Control Word Write Only Accesses the 8254 control register to directly control the three timer counters BCD Binary 0 binary 1 BCD Counter Select 00 Counter O Counter Mode Select 01 Counter 1 000 Mode 0 event count 10 Counter 2 Read Load 001 Mode 1 programmable 1 shot 11 read back setting 00 latching operation x10 Mode 2 rate generator 01 read load LSB only x11 Mode 3 square wave rate generator 10 read load MSB only 100 Mode 4 software triggered strobe 11 read load LSB then MSB 101 Mode 5 hardware triggered strobe BA 12 Update DACs D A Converter 1 LSB Read Write A read updates the DACI and DAC 2 outputs A write programs the DAC1 LSB eight bits vee or os os a os oz or Bt7 Bt6 BtS Bit4 Bt3 Br2 Biti Bit O 4 8 BA 13 Status D A Converter 1 MSB Read Write A read provides the A D converter status bit defined below When you start a conversion the status line goes high After the line goes high then watch for it to go low signaling that the conversion is complete X x X
114. uple channels channels 1 through 4 ADA520J8 ADAS20 driver with support for 8 thermocouple channels channels 1 through 8 One of these drivers is included on your ATLANTIS driver disk Other drivers can be purchased from the factory Thermocouple drivers assign the thermocouple channels to the lowest channels while the non thermocouple channels use the standard assignments For example when using the ADA520J4 driver even though all of the thermocouple channels enter the ADA520 on channel 1 ATLANTIS will display the thermocouple channels as channels 1 through 4 and the non thermocouple channels as channels 5 through 8 E 6 F 1 APPENDIX F WARRANTY F 2 LIMITED WARRANTY Real Time Devices Inc warrants the hardware and software products it manufactures and produces to be free from defects in materials and workmanship for one year following the date of shipment from REAL TIME DE VICES This warranty is limited to the original purchaser of product and is not transferable During the one year warranty period REAL TIME DEVICES will repair or replace at its option any defective products or parts at no additional charge provided that the product is returned shipping prepaid to REAL TIME DEVICES All replaced parts and products become the property of REAL TIME DEVICES Before returning any product for repair customers are required to contact the factory for an RMA number THIS LIMITED WARRANTY DOES NOT EXTEND
115. vailable pins Single Bit Set Reset Feature Any of the eight bits of Port C can be Set or Reset using a single OUTput instruction This feature re duces software requirements in Control based appli cations When Port C is being used as status control for Port A or B these bits can be set or reset by using the Bit Set Reset operation just as if they were data output ports 3 128 intel 82C55A interrupt Controi Functions When the 82C55A is programmed to operate in mode 1 or mode 2 control signals are provided that can be used as interrupt request inputs to the CPU The interrupt request signals generated from port C can be inhibited or enabled by setting or resetting the associated INTE flip flop using the bit set reset BIT SELECT function of port C JOBAOGDE 10 1 0 1101 1 0 fad This function allows the Programmer to disallow or Li allow a specific 170 device to interrupt the CPU with out affecting any other device in the interrupt struc ture INTE flip flop definition 231256 7 BIT SET INTE is SET Interrupt enable BIT RESET INTE is RESET Interrupt disable Figure 7 Bit Set Reset Format Note All Mask flip flops are automatically reset during mode selection and device Reset 3 129 Operating Modes Mode 0 Basic Input Output This functional con figuration provides simple input and output opera tions for each of the three ports No handsh
116. version of the industry standard 8255A general purpose programmable I O device which is designed for use with all Intel and most other microprocessors It provides 24 1 0 pins which may be individually programmed in 2 groups of 12 and used in 3 major modes of operation The 82C55A is pin compatible with the NMOS 8255A and 8255A 5 In MODE 0 each group of 12 I O pins may be programmed in sets of 4 and 8 to be inputs or outputs In MODE 1 each group may be programmed to have 8 lines of input or output 3 of the remaining 4 pins are used for handshaking and interrupt control signals MODE 2 is a strobed bi directional bus configuration The 82C55A is fabricated on Intel s advanced CHMOS Ill technology which provides low power consumption with performance equal to or greater than the equivalent NMOS product The 82C55A is available in 40 pin DIP and 44 pin plastic leaded chip carrier PLCC packages Figure 1 82C55A Block Diagram 231256 2 Figure 2 82C55A Pinout Diagrams are for pin reterence only Package sizes are not to scale September 1987 3 124 Order Number 231256 004 inte 82C55A Table 1 Pin Description mea op Number FE PORT A PINS 0 3 Lower nibble of an 8 bit data output latch buffer and an 8 bit data input latch FD 5 e READ CONTROL This input is low during CPU read operations 7 CHIP SELECT A low on this input enables the 82C55A to respond to RD and WR signals RD and WR are ignored other
117. wise System Ground CO S y y y 8 9 ADDRESS These input signals in conjunction AD and WA control the selection of one of the three ports or the control word registers Ay Ap RD WA CS input Operation Read jo o lof o rona DataBus o p o 4 o Ports Daabus pr jolo o Portc Databus la o 1 o corwolword Data Bus po o To To Bas Ras Pana po fs is fo o DataBus PonB lo fofo Da s Bang pt ls sr fofo DataBus Conmi x x x x 1 DetsBus 3 S1e x x 1 o DataBus 3 State PCy 11 13 15 1 0 PORTC PINS 4 7 Upper nibble of an 8 bit data output latch buffer and an 8 bit data input buffer no latch for input This port can be divided into two 4 bit ports under the mode control Each 14 17 16 19 1 0 PORTC PINS 0 3 Lower nibble of Pon Z PBo 7 20 22 O PORT B PINS 0 7 An 8 bit data output latch buffer and an 8 24 28 bit data input buffer Vcc 20 _ SYSTEM POWER 5v Power Supp D7 0 27 34 HO DATA BUS Bi directional tri state data bus lines connected to system data bus 4 bit port contains a 4 bit latch and it can be used for the control signal outputs and status signai inputs in conjunction with ports A and B RESET RESET A high on this input clears the control register and all ports are set to the input mode WR WRITE CONTROL This input is low during CPU w

Download Pdf Manuals

Related Search

Related Contents

  User manual  Télécharger le document  Mode d`emploi  operator`s manual professional chest and roller cabinets with  Samsung MJC-960IU User Manual  Catalogue P.L.  KRONOS USER MANUAL - Cornell University  (Safety) Temperature Limiter  6155 UM-A4-25-04.QXD  

Copyright © All rights reserved. Failed to retrieve file