FS4405 PCI Express State Analysis Preprocessor User Manual
Contents
1. 10 bit 10 bit x1 mode x2 x4 x8 mode mode use B use B pods for pods for other other link link Align Flag 1 1 Alignment of multi lane link detected NA 4 4 A2 15 Any Invalid Error Flag 1 17 This state includes an 8b10b code error AA 0 4 3 either disparity error or decode error any A2 14 active lane LOS 3 2 1 0 4 1 Corresponding lane Loss of Signal NA 4 2 0 0 Signal detect on lane A3 16 2 x4 mode only Any LOS 1 17 Loss of Signal detected in any active lane 1 15 15 A2 13 07 Signal detected in all active lanes Lane 0 Disparity Error 1 1 Lane 0 data has incorrect 8b10b disparit 1 14 14 2 12 Lane 0 Invalid Decode Error 1 1 7 Lane 0 data is not a valid 8b10b code 1 13 A3 13 A2 11 LaneO 10 Physical Lane 0 Data 10 bit encoded A1 12 3 A3 12 3 A2 10 1 Lane 1 Disparity Error 1 1 Lane 1 data has incorrect 8b10b disparity NA A3 2 A2 0 Lane 1 Invalid Decode Error 1 1 7 Lane 1 data is not a valid 8b10b code NA A3 1 A1 15 Lane1 10 Physical Lane 1 Data 10 bit encoded NA A3 0 1 14 5 A2 16 8 Lane 2 Disparity Error 1 1 Lane 2 data has incorrect 8b10b disparity NA 2 7 A1 4 Lane 2 Invalid Decode Error 1 1 Lane 2 data is not a valid 8b10b code NA A2 6 1 3 Lane2 10 Physical Lane 2 Data 10 bit encoded NA A2 5 0 A1 2 0 A1 15 12 B4 16 10 Lane 3 Disparity Error 1 1 Lane data has incorrect 8b10b disparity NA 1 11 4 9 Lane 3 Invalid Decode Error 1 1 7 Lane data2. 10 times Consecutively This detects TS2 ordered sets during link initialization This assures the link is up and running because a PCle device issues TS2 ordered sets only after it has received valid TS1 ordered sets from the other direction Finding Link Startup During Fast Training in 10 bit Mode When link is expected to perform fast training set the analyzer to trigger on e LaneO FTS or FTS Finding the start of Signal Activity in 10 bit Mode Set the analyzer to trigger on signal detection status LOS loss of signal Note this method can only be used when the probe is not setup for ASPM mode e ANYLOS goes low all lanes signal detected Note Some links startup cleanly within 300 nS of de assertion of LOS flag but others do not The probe itself can not achieve lock quickly until it receives a stable signal and a stable reference clock Signal detection does not imply a valid serial data signal Signal detection LOS status is delayed relative to link data capture Finding the first Idle Characters in 10 bit Mode With scrambling assumed to be occurring the first 2 idle data words following TS1 TS2 training sets will be either depending on disparity e 2CD followed by 161 e 10D followed by 15E Note Idle data might not immediately follow TS1 TS2 there may be Skip Ordered Sets or DLLPs The Disassembler Display Captured data is as shown in the following figure The below figure displays the p
3. BA 8 Pat Rec 3 1 Packet recognized pulsed for one 4 11 9 4 7 5 Pat Rec 2 clock cycle These are to be used for Pat Rec 1 logic analyzer triggering only Do not Pattern Recognizers qualify with DS LaneO 10 Logical Lane 0 Data A3 6 0 A2 A2 16 7 spread data in x1 or x2 lane mode 16 14 Bit 9 is Invalid flag Bit 8 is Control flag Lane1 10 Logical Lane 1 Data A2 13 4 A2 6 0 spread data in x1 or x2 lane mode A1 16 14 Bit 9 is Invalid flag Bit 8 is Control flag Lane2 10 Logical Lane 2 Data A2 3 0 A1 A1 13 4 spread data in x1 or x2 lane mode 15 10 Bit 9 is Invalid flag Bit 8 is Control flag Lane3 10 Logical Lane 3 Data 1 9 0 A1 3 0 spread data in x1 or x2 lane mode B4 16 11 below x8 mode only Bit 9 is Invalid flag Bit 8 is Control flag Lane 4 10 Logical Lane 4 Data NA B3 11 2 x8 mode only Bit 9 is Invalid flag Bit 8 is Control flag Lane 5 10 Logical Lane 5 Data NA B3 1 0 x8 mode only B2 16 9 Bit 9 is Invalid flag Bit 8 is Control flag Lane 6 10 Logical Lane 6 Data NA B2 8 0 x8 mode only B1 15 Bit 9 is Invalid flag Bit 8 is Control flag Lane 7 10 Logical Lane 7 Data NA B1 14 5 Additional Bits PCle The FS4405 generates a number of identification and control bits that are used by the Protocol Decoder and logic analyzer There are a few that don t have pre defined labels other than being in the VAB label used by the
4. Connecting the Tektronix logic analyzer to the FS4405 The FS4405 is designed to enable the user to connect the FS4405 to the widest possible range of Tektronix logic analyzer modules cards The FuturePlus Systems 1055 cable is designed to attach to the 90 pin connectors on the FS4405 and to the TLA7A N connector on the other end Each FS1055 connects 2 FS4405 90 pin pods 17 channels each to 1 TLA card input 34 channels Connect the logic analysis cards to the 4405 The table below explains how to connect TLA7AAA card to the FS4405 Logic Analyzer FS4405 Comment C0 C3 1 Clock A2 00 1 1 A4 D2 3 A2 3 B1 B2 E0 3 B3 B4 Based on the probing needs install the appropriate modules into the Tektronix logic analyzer and remove any adapter cables that may be attached to the module cables When probing 2 directions of x1 x2 x4 links or a single direction of an x8 link the FS4405 drives 8 pods of signals 4 FS1055 cables to the logic analyzer When probing a single direction of a x1 x2 or x4 link the FS4405 drives 4 pods of signals 2 FS1055 cables to the logic analyzer It is important before you load a system file you initiate a self test on all your modules installed in your logic analyzer to insure all modules are working properly Loading system files You can access the system files by clicking on the FS1160 folder that was placed on the desktop When you click on the folder it should open up to display all
5. EP 0h Attr 1h Length 010h Completer ID 0000h cor RegID 0000h Tag 00h Lower Addr 40h Data 10C10400h Data 00000000h Data 10C10400h Data 00000000h Data 10C10400h Data 00000000h Data 10C10400h Data 00000000h Data 10C10400h Dati 0000000h Dat 0C10400h Dati 0000000h Dat 0C10400h Dati 0000000h Dat 0C10400h Data 00000000h CRC DFSED45Ah Completion With Data Seq 9Ch FMT 2h Type 0Ah TC 7h TD 0h 0 Attr 1h Length Completer ID 0000h complStatus Gh BCM 0h Byte Count 010h Re Data 10C10400h Data 00000000h Dat 0C10400h Data 00000000h CRC 74E2EB6Eh Completion With Data Seq 9Dh 2 Type 0Ah TC 7h TD 0h EP 0h Attr 1h Length 010h Completer ID 0000h cor RegID 0000h Tag 02h Lower Addr 00h Data 10C10400h Data 00000000h Data 10C10400h Dati 0000000h Dat 0C10400h Dati 0000000h Dat 0C10400h Data 00000000h Data 10C10400h Data 00000000h Data 10C10400h Data 00000000h Data 10C10400h Dat 0000000h Da 0C10400h Data 00000000h CRC B22F8FB3h Completion With Data Seq 9Eh FMT 2h Type 0Ah TC 7h TD 0h EP 0h Attr 1h Length Completer ID 0000h complStatus 0h BCM 0h Byte Count 040h Re Data 10C10400h Data 00000000h Data 10C10400h Data 00000000h The FS4405 Disassembler FS1160 will perform the following functions Decode all PCI Express command and cycle types Color code the transaction type The colors used by the software are as follows Ordered Sets Orange TLP Packets Green DLLP Purple Error Red Signal Probe gener
6. Error 1 1 7 Lane data is the wrong 10B disparity 4 Lane 2 Invalid Decode Error 1 1 Lane data is an invalid 10B decode 3 Lane 2 10B Data 10 Encoded 10b value 2 0 B4 16 10 Lane 3 Disparity Error 1 1 7 Lane data is the wrong 10B disparity 9 Lane 3 Invalid Decode Error 1 1 Lane data is an invalid 10B decode 8 Lane 3 10B Data 10 Encoded 10b value 7 0 B3 16 15 Lane 4 Disparity Error 1 1 7 Lane data is the wrong 10B disparity 14 Lane 4 Invalid Decode Error 1 1 Lane data is an invalid 10B decode 13 Lane 4 10B Data 10 Encoded 10b value 12 3 Lane 5 Disparity Error 1 1 7 Lane data is the wrong 10B disparity 2 Lane 5Invalid Decode Error 1 1 Lane data is an invalid 10B decode 1 Lane 5 10B Data 10 Encoded 10b value 0 B2 16 8 Lane 6 Disparity Error 1 1 Lane data is the wrong 10B disparity 7 Lane 6 Invalid Decode Error 1 1 Lane data is an invalid 10B decode 6 Lane 6 10B Data 10 Encoded 10b value 5 0 B1 15 12 Lane 7 Disparity Error 1 1 7 Lane data is the wrong 10B disparity 11 Lane 7 Invalid Decode Error 1 1 Lane data is an invalid 10B decode 10 Lane 7 10B Data 10 Encoded 10b value 9 0 The clock is on A1 bit 16
7. ID 0000h complStatus 0h BCM 0h Byte Count 080h Re Data 00230400h Data 04000000h Data 00C00400h Data 7109D4D3h Data 10C10400h Data 00000000h Data 10C10400h Data 00000000h Data 10C10400h Data 00000000h Data 10C10400h Data 00000000h Data 10C10400h Data 00000000h Data 10C10400h Data 00000000h CRC 663F16FBh Completion With Data Seq 9Bh FMT 2h Type 04h TC 7h TD 0h EP 0h Attr 1h Length 010h Completer ID 0000h RegID 0000h Tag 00h Lower Addr 40h Data 10C10400h Data 00000000h Data 10C10400h Data 00000000h Dati 0 10400 Data 00000000h Data 10C10400h Data 00000000h Data 10C10400h Data 00000000h 0 10400 Data 00000000h 0C10400h Data 00000000h Data 10C10400h Data 00000000h CRC DF9ED4SAh Completion With Data Seq 9Ch FMT 2h 0 TC 7h TD 0h EP 0h Attr 1h Length Completer ID 0000h complStatus 0h BCM 0h Byte Count 010h Data 10C10400h Data 00000000h Data 10C10400h Data 00000000h CRC 74E2EB6Eh Completion With Data Seq 9Dh FMT 2h Type 04h TC 7h TD 0h EP 0h Attr 1h Length 010h Completer ID 0000h ReqID 0000h Tag 02h Lower Addr 00h Data 10C10400h Data 00000000h 0C10400h Data 00000000h Data 00000000h Data 00000000h Data 00000000h Data 00000000h Data 00000000h Data 00000000h CRC B22F8FB3h Completion With Data Seq 9Eh FMT 2h 0 TC 7h TD 0h EP 0h Attr 1h Length Completer ID 0000h complStatus 0h BCM 0h Byte Count 040h Re Data 10C10400h Data 00000000h Data 10C10400h Data 00000000h 32 Besides d
8. Inverse Assembler These are also available to the user and can be used as described below Functional Name No of Definition Usage Logic Logic Bits Analyzer Analyzer Pod Pod In x1x2x4 n x8 mode mode ALIGNED 1 1 multi lane link is aligned 4 14 BA 9 0 lane deskew has failed DATA PRESENT 4 Exists in x1 x2 x4 mode only A3 14 11 NA 3 2 1 0 1 Lane data is present 0 Lane data is not present due to effects of spreading x1 or x2 data across 4 lanes LOS 4 Lane by Lane LOS bits A3 10 7 NA 3 2 1 0 Provided in x1 x2 x4 mode only 1 Loss of Signal in Lane 0 Signal Detected or Lane not used Any LOS 1 Composite LOS bit all active lanes NA B3 12 Provided in x8 mode only Event Code label definitions PCle mode Event Event code Unknown loss of frame synch 0x00 Electrical Idle Signal Event 0x01 Beacon Signal Event 0x02 Link Alive Signal Event 0x03 Signal Logical Idle 0x04 Signal Compliance Pattern 0x0C Ordered Set TS1 0x05 Ordered Set TS2 0x06 Ordered Set Skip 0x07 Ordered Set FTS 0x08 Ordered Set Electrical Idle 0x09 TLP Memory Read MRd 0x10 TLP Memory Read Locked MRdLk 0x11 TLP Memory Write MWr 0x12 TLP IO Read Request IORd 0x13 TLP IO Write Request IOWr 0x14 TLP Config Read Type 0 CfgRdO 0x15 Co
9. Trigger S Listina EEE TEk Staus lee 3 TLA off line dj F54405 10 d Desktop My Docun gt Probe Manager The Probe Manager software can be found as the FS44xx Probe Mgr exe file on the CD Appli cation provided in the Documentation package Insert the CD into the computer that will be used to control the FS4405 probe This computer must have a USB connection Using Windows File Manager select the FS44xx Probe Mgr exe file and double click it which initiates the installation software on the computer and places an icon on the desktop Follow the directions that follow including agreeing to the license terms once the software installation is complete click on finish To start the program manager simply double click its desktop icon The Probe Manager application detects all FS44xx probes that are connected to the USB bus and allows the user to select which probe will be controlled by the current instance of the Probe Manager application from the initial screen as seen below FS44xx Probe List Manufacturer FPSystems Description F54411 SN New Build 90 Gut The initial screen is followed by the Protocol Selection screen in which the user selects the protocol the FS4405 probe will be associated with Protocol Selection xi Once the protocol has been selected the application displays the Main dialog as seen below PCIE Probe Mgr SN New Build
10. between active LO and shallow power saving LOs the probe will achieve very low N FTS when operated in ASPM mode selected by clicking the ASPM checkbox on the Config window before running the probe This mode allows the probe to start capturing data early during the Fast Training ordered sets Finding Stable PCle Link Activity When link is expected to perform initialization set the analyzer to trigger on e Event Code TS2 training set This assures the link is up and running because a PCle device issues TS2 ordered sets only after it has received valid TS1 ordered sets from the other direction Finding Link Startup During Fast Training When link is expected to perform fast training set the analyzer to trigger on e Event Code FTS Ordered Set Finding the Start of Signal Activity Set the analyzer to trigger on e Event Code Link Alive Another method is to trigger based on signal detection status LOS loss of signal Note this method can only be used when the probe is not setup for ASPM mode e Event Code Beacon signal detected on lane 0 e LOS 0 goes low for 1 lane operation LOS 1 0 goes low all lanes signal detected in 2 lane operation LOS 3 0 goes low all lanes signal detected in 4 lane operation e ANYLOS goes low all lanes signal detected in 8 lane operation Note Some links startup cleanly within 300 nS of de assertion of LOS flag but others do not The probe itself
11. done in real time by the FS4405 hardware Filtering out unwanted traffic such as Logical Idles can extend the storage capabilities of the logic analyzer Filtering out irrelevant bus traffic can help users focus on specific packets of interest To filter out any particular traffic type click on the appropriate box so a Y appears and click apply You must restart the probe by pressing the green run button so the new values will be written to the probe hardware Filtering can also be done using any combination of packet header bits via the Pattern Recognizers The PR Drop filters drop the recognized packets The PR Pass filters over ride all other filters and force recognized packet to be clocked into the analyzer Log File The status of the probe and the link under test can be seen in this tab page PCI E Log File Log File Dialog Once started logging continues even if the probe is stopped and started or if the log window is closed and re opened Once a probe has been stopped the log entries can be written to a file of the user s choice by clicking the Write Log File button The PCI Express Protocol Disassembler Software b gt GoTo Sample For Help press F1 State Analysis This chapter explains how to use the FS4405 to perform state analysis The system file sets up the format specification menu of the logic analyzer for compatibility with the output of the FS4405 Load the appropriate sys
12. eee 13 ExpressCard Probing FS1033 Interposer assembly eee 14 Installing your Software for the First Time ccssccsssssssscssssscsssccsssssssssssesesess 15 Connecting the Tektronix logic analyzer to the FS4405 16 Loading system 17 Offline ANALYSIS s csecssscsssscosecsesssseonassssceeestssensscoudesssenssenssesunes sdeeseenanceodeseseeseseesesenessseses 18 Probe Manager A pplication sssssscssssscsssscsssscsssccssccssssssssssssssssssssssssssssssesessss 19 Probe Configurations RU RR E RO RR ERN Riga 22 o eere ee e meter eese del de pede er eer REUS 24 i 29 IE Agite 31 State AXIUDVSIS oe o droite ap dea aa erred eodera S RR RP ee n Ro 32 The PCI Express Protocol Disassembler Software eeeeeeeee eere 32 I rese teu opes E de 33 Additional Bits e Toe ee e due eve d Ies eua apo 34 IB TIERE e 36 37 IIIA Ice 38 10 Eese Sinior SESE esis 40 bp 40 Finding the first Idle Characters in 10 bit Mode eene 41 The Disassembler Display e ecce ee eee eee ee ene eee eo seen aestas eee en a
13. follows negative disparity Value follows positive disparity COM K28 5 COM 0101 111100 17C COM 1010 000011 283 FTS K28 1 FTS 1001 111100 27C FTS 0110 000011 183 SKP K28 0 SKP 0010 111100 OBC SKP 1101 000011 343 SDP K28 2 SDP 1010 111100 2BC SDP 0101 000011 143 IDL K28 3 IDL 1100 111100 33C IDL 0011 000011 0C3 PAD K23 7 PAD 0001 010111 057 PAD 1110 101000 3A8 STP K27 7 STP 0001 011011 05B STP 1110 100100 3A4 END K29 7 END 0001 011101 05D END 1110 100010 3A2 EDB K30 7 EDB 0001 011110 05 EDB 1110 100001 3A1 TSID1 D10 2 TSID1 1010 101010 2AA TSID1 1010 101010 2AA TSID2 D52 TSID2 1010 100101 2 5 TSID2 1010 100101 2A5 Verify Setup in 10 bit Mode To verify correct lane reverse settings make sure the SDP STP characters appear on the leftmost lane and the END characters appear on the rightmost lane To verify lane width settings verify Data LED is green checks for valid data on all lanes and the successful de skew of active lanes Observe a DLLP packet in the listing and verify it consists of 8 consecutive bytes from SDP through END To verify correct lane inversion settings check that the TSID last 10 states of every TS1 or TS2 ordered set during training is hex 2AA or 2A5 and not 155 or 15A Finding Stable PCle Link Activity in 10 bit Mode When link is expected to perform initialization set the analyzer to trigger on e LaneO TSID2 2A5
14. installed FuturePlus product e FS1150 exe Transaction Viewer e FS44xx Probe Manager exe 3 Once all the above files have been installed connect the FS4405 to the analyzer computer via the USB port Power on the FS4405 probe 4 The found new hardware wizard should appear the first time the probe is attached and powered up Select no not this time when it asks if the computer can go to Windows update to search for the software Then select next 5 Onthe next screen select the Advanced option not the Recommended to select from a specific list or location select Next 6 Select the CD ROM drive to load the driver from you do not have to select a specific directory Select next 7 There may be a warning that comes up about Windows XP compatibility ignore this warning and continue with installation 8 Click Finish to complete the installation Once all the previous steps have completed all necessary software as well as USB drivers will be installed This procedure only needs to be done on initial install You may now go to the desktop and click on the Probe manager icon to start the probe manager If you are installing on a PC to only control the FS4405 probe then you can omit the installation of the FS1160 exe FS1150 exe and FPSystems Disassembler Application but you must follow the rest of the steps For instructions on loading system files please refer to the section on loading system files later in this manual
15. is on A1 bit 16 STORAGE is on B1 bit 16 LAI Bit Definitions For a Single Direction x8 Link PCle mode Field Bits Definition Pod Bits Pod A4 is unused A4 Pod A3 is unused A3 Lane 0 Sym Invalid 1 0 Valid 8b decode 1 Incorrect disparity or code violation A2 16 Lane 0 Control Flag 1 12K character control 0 D character data 15 Lane 0 8b Data 8 Decoded 8b value 14 7 Lane 1 Sym Invalid 1 0 Valid 8b decode 1 7 Incorrect disparity or code violation 6 Lane 1 Control Flag 1 12K character control 0 D character data 5 Lane 1 8b Data 8 Decoded 8b value 4 0 A1 16 14 Lane 2 Sym Invalid 1 0 Valid 8b decode 1 7 Incorrect disparity or code violation 13 Lane 2 Control Flag 1 12K character control 0 D character data 12 Lane 2 8b Data 8 Decoded 8b value 11 4 Lane 3 Sym Invalid 1 0 Valid 8b decode 1 7 Incorrect disparity or code violation 3 Lane 3 Control Flag 1 12K character control 0 D character data 2 Lane 3 8b Data 8 Decoded 8b value 1 0 B4 16 11 STORAGE 1 1 Store this state 0 Discard 10 Aligned 1 1 Multi lane link is word aligned bonded 9 Data Error 1 1 This state includes an error 8 Packet Recognizer 3 12 Packet recognized pulsed for one clock cycle during packet 7 5 Unjust 1 1 TLP or DLLP Pack
16. matters Makes sure you know how the and sides of the signal are connected Adjustment to polarity can be made in the Probe manager ow Pin Il Ground Pin Il Ground Pin The FS1036 flying lead cable has 8 pairs of channel connectors which are labeled A G for up to 4 channels of a link and B H which can be used for another link Make the appropriate cable and channel selections in the Probe manager before taking any probe measurements ExpressCard Probing FS1033 Interposer assembly The FS1033 is a cable assembly that includes a slot interposer for an ExpressCard 34 slot The interposer is made to be of sufficient length to use without having to remove the covers on a target platform As specified by the PCMCIA organization the ExpressCard link works as either an x1 PCI Express module or as a USB2 0 module The FS1033 is a passive interposer of all signals except for the REF CLK which is re buffered appropriately and sent to both the ExpressCard module connector and to a Reference Clock header for use with the FS4405 probe To provide additional functionality probing pads are provided on the slot interposer for all the ExpressCard signals besides PET Rp n both directions of the x1 lane width links These points are clearly labeled in the silkscreen as shown below Probing USB with the FS1033 This can be done by using the FuturePlus Systems FS4120 USB2 0 probe and using custom pigtail cables s
17. or 8 The preprocessor can connect to the PCI Express target by a number of different means including full and half size midbus probes x4 slot x1 slot x8 slot and ExpressCard interposers or flying leads The preprocessor itself is controlled by the Probe Manager software which runs under Windows and communicates with the probe via a USB cable The FS4405 snoops a PCI Express link without significantly degrading its signal integrity The high speed serial signal is deserialized and processed for packet identification by the FS4405 before being sent to the logic analyzer connections Additionally the preprocessor provides trigger filtering and packet recognition functions The disassembler software running on the logic analyzer provides information regarding the transactions within the captured traffic and the Transaction Viewer provides a system level view of these transactions The FS4405 product consists of the following accessories e The FS4405 preprocessor power supply and cable Protocol Disassembler FS1160 Tek Transaction Viewer and Probe Manager applications on CD A USB cable is provided for connecting the FS4405 probe to the Windows based machine that the Probe Manager is loaded on WARNING If the unit is not used as specified by the manufacturer the overall safety will be impaired WARNING Only use power supply provided with the unit which is manufactured by Lambda P N DT70PWO5OP e This User Manual and the
18. some cases it may necessary to temporarily disconnect the Windows system from the local network to insure that Windows does not automatically default to getting the drivers from the Internet If the correct USB drivers are not loaded the user will see a Windows error Unable to load DLL as soon as the Run button is used NOTE The Microsoft NET Framework must be on the system for the Probe Manager application to load properly 2 FS4405 probe This preprocessor requires its own DC power supply which is provided Additionally this probe is completely initialized set up and controlled by the Probe Manager software that resides on a Windows based system either stand alone PC or TLA7xxx logic analyzer All communication to the 4405 probe is by means of the USB port on the PC or logic analyzer Improper or incomplete installation of either the correct USB driver or the Probe Manager software will prevent operation of the FS4405 Tektronix Logic Analyzer The files for the TLA7xxx analyzer FS1160 are on a CD TLA Disassembler files Install these files as required and follow the instructions for logic analyzer module card interconnections and logic analyzer connections to the FS4405 probe PCI Express target platform There are a number of different probing options including mid bus probe interposer flying lead etc There are also a wide variety of PCI E link implementations besides widths of x1 x2 x4 x8 etc There are prot
19. the system files to choose from If you put your mouse cursor on the name of the file a description will appear telling you what the setup consists of once you choose the system file that is appropriate for your configuration the TLA operating system should execute The analyzers supported by the FS4405 system files are for theTLA7xxx cards PE160 1 x1 2 way 10b analysis Requires 1 FS1055 cable and 34 logic analysis channels PE160 2 x2 and x4 2 way 10b analysis Requires 4 FS1055 cables and 136 logic analysis channels PE160 3 4 x8 1 way 10b analysis Requires FS1055 cables and 102 logic analysis channels 1 system file is used for each direction on the x8 link PE160 5 x1 x2 x4 2 way PCI Express analysis Requires 4 FS1055 cables and 136 logic analysis channels PE160 6 7 x8 1 way PCI Express analysis Requires 3 FS1055 cables and 102 logic analysis channels 1 system file is used for each direction on the x8 link When probing 2 directions of a x8 PCle link the TLA67xx cards do not have to be merged Offline Analysis Data that is saved as a tla file can be imported into the TLA7xxx environment for analysis You can do offline analysis on a PC if you have the TLA7xxx operating system installed on the PC if you need this software please contact Tektronix Offline analysis allows a user to be able to analyze a trace offline at a PC so it frees up the analyzer for another person to use the analyzer to ca
20. 6 LAI Bit Definitions for a Single Direction x2 x4 Link 10b mode 4 Pods 1 machine Field Bits Definition Pod Bits Unused 12 0 4 16 5 Align Flag 1 1 Alignment of multi lane link detected B4 4 Any Invalid Error Flag 1 1 This state includes a 10B code error disparity or 3 decode in any active lane LOS 3 2 1 0 4 1 Corresponding lane Loss of Signal 2 0 0 Signal detect A3 16 ANY LOS 1 1 Any Lane Loss of Signal B3 15 07 Signal detect on all active lanes Lane 0 Disparity Error 1 1 7 Lane data is the wrong 10B disparity 14 Lane 0 Invalid Decode Error 1 1 Lane data is an invalid 10B decode 13 Lane 0 10B Data 10 Encoded 10b value 12 3 Lane 1 Disparity Error 1 1 Lane data is the wrong 10B disparity 2 Lane 1Invalid Decode Error 1 1 Lane data is an invalid 10B decode 1 Lane 1 10B Data 10 Encoded 10b value 0 A2 16 8 Lane 2 Disparity Error 1 1 7 Lane data is the wrong 10B disparity B2 7 Lane 2 Invalid Decode Error 1 1 Lane data is an invalid 10B decode 6 Lane 2 10B Data 10 Encoded 10b value 5 0 A1 15 12 Lane 3 Disparity Error 1 1 7 Lane data is the wrong 10B disparity B1 11 Lane 3 Invalid Decode Error 1 1 Lane data is an invalid 10B decode 10 Lane 3 10B Data 10 Encoded 10b value 9 0 The clock is on A1 bit 16 LAI Bit Definitions For a Single Direction X1 Link 10 b 1 Po
21. 90 lOl x File Edit Run Stop Upgrade Help E B B Run Stop Probe Packet R izers Filters Log Entries Probe is ready to be configured The user configures and controls the probe from the main form The form is composed of a menu bar a tool bar and a status message bar The menu bar provides options that allow the user to configure and run the probe The tool bar provides options to configure the probe and the status bar displays the probes current status and or any errors that may have been encountered Error messages displayed in the status bar are also logged in the Log Form if logging is enabled The menu bar contains the following options File e Open Config File Displays a open file dialog in which the user may navigate to and open the file contains a previous session s saved probed settings e Save As Displays a save file dialog in which the user may specify where a probe settings system file may be saved e Exit Shut down the application Edit e Modify Title String Allows the user to specify the title string that appears in all sub dialog s title bar This is helpful when running multiple probes Run Stop e Run Probe Mgr Running the probe with the current settings This is an alternative to clicking the tool bar Run button e Stop Probe Mgr Stop the probe This is an alternative to clicking the tool bar Stop button Upgrade e Upgrade Upgrade one of four protocol specific FPAG co
22. FuturePlus Systems Corporation gt EXPHESS FS4405 PCI Express State Analysis Preprocessor User Manual For use with Tektronix Logic Analyzers Revision 1 4 Copyright 2007 FuturePlus Systems Corporation FuturePlus is a registered trademark of FuturePlus Systems Corporation Howto reach istic a 4 Product Warranty uso oap edo pM ORE A RA Ns 5 Limitation of Warranty 4 eere sS oo Esisi 5 Excl sive erre eerte d aS X 5 ASSISCANICE ER 5 Introduction m 6 How to Use This Manual 4 eeeeee eese eese etae eene etas ns ense ta senses snae toan 6 Definitions C M n 6 Analyzing the PCI Express BUS deeasscctrescevevin ARES Qo 7 Accessories Supplied 4 eerie eee eee enata stes sessao 7 Minimum Equipment Required eee e eere e eerte eese 7 Probing System Overview 8 Front eoii 10 FS4405 Probing Cables eene nni iro eroe oo ra ro erai Re isoa 11 Int rposer Probing FS1034 5 7 12 Flying Lead Probing FS1036 cable assembly
23. IFO over run or under run See Log for more information Orange Invalid Symbol or Disparity Error Green OK Data LED State Meaning Red FPGA Lost lock on clock s Probe needs to stop and run again Orange Any Error Invalid Symbol or Disparity Error Align Framing Idle Green OK Data clocking into analyzer Dark No Data due to filtering or not running All transient events such as a single bit error or a packet clocked into the analyzer are stretched to short visible pulses on the LEDs Observing Link Start up When using Internal Reference clock the probe can be run at any time before or after the target has powered up or link become active When using External Reference clock s the probe requires the target reference clock to be active before the probe is run In all cases links may be re started and target systems may be re booted while the probe is running This makes probing link initialization convenient Observing PCle Link Activity in ASPM PCI Express Active State Power Management ASPM protocol allows links to transition back and forth between active LO and low power states LOs L1 L2 etc The probe will follow links that go up and down e Whena link is constantly transitioning back and forth between active and low power states the Signal LEDs and the log file will report errors that can be ignored e probe can follow Fast Training If a link is transitioning
24. Tek TV Manual on CD and Quick Start sheet The minimum equipment required for analysis of a PCI Express Bus consists of the following equipment e Tektronix TLA7AAx or TLA 7NAx analysis frame with the TLA7AA1 TLA7NA1 modules or better e An FS4405 probing cable e Express target bus It is STRONGLY recommended that the user review and apply the probing guidelines described in the FuturePlus Systems application note Logic Analyzer Probing Design Guide for the FS440x when planning for use of the probe on any target system Probing System Overview The architecture of the FS4405 PCI Express preprocessor and the design of the PCI Express link to be probed should both be thoroughly understood before attempting to use the probe The following is a general outline of the steps to be taken when probing a new link Read the following pages for more specific information The FS4405 probe requires the understanding and correct set up of 4 different systems before a trace should be taken 1 Probe Manager software This software is identified as Probe Manager exe and is on the CD that comes with the FS4410 Additionally there is a folder within this CD that contains all the necessary USB drivers that your Windows system requires When Windows searches for the USB drivers to load during the first connection of the F54410 Windows MUST be directed to load the drivers from this CD in the system or the proper USB drivers will not load In
25. any other bits to qualify them 37 Acquiring Data First insure that the FS4405 probe is attached to its external power supply and powered on which would be indicated by a green Power On LED Open up the Probe Manager software and insure the appropriate selections are made and applied finally make sure that the probe is connected via the appropriate cable s to the target system Once connected with the link active open up the Probe Config window and select cable type lane width and reference clock options Verify that lane activity indicators show activity at the correct lanes Run the probe and observe the LEDs If a link s Signal LED is green but its Data LED is orange then there may be a need to select different options for lane width lane reverse or lane inversion in the Probe Config window The FS4405 probe should show a green Signal LED of any Link being probed as well as a green or dark data LED Configure the analyzer trigger menu to acquire PCI Express data Select RUN and as soon as there is activity on the bus the logic analyzer will begin to acquire data The analyzer will continue to acquire data and will display the data when the analyzer memory is full the trigger specification is TRUE or when you select STOP Link status is communicated by a pair of LEDs as follows Signal LED State Meaning Dark LOS no signal on an active lane Red RX Fault Lost Lock on Ref Clock Lost Synch on Data F
26. ate Analysis chapter explains how to configure the FS4405 to perform state analysis on your PCI Express bus The Transaction Viewer chapter is a brief overview of this application software that integrates with the FS4405 Protocol Decoder The General Information chapter provides information on the operating characteristics and cable header pinout for the FS4405 probe The following terms are used to describe aspects of the PCI Express bus Channel One differential signal 2 wires PCle Lane A pair of differential signals running in opposite directions 4 wires Link A bidirectional interface made with two sets of unidirectional signals A Link consists of 1 2 4 or 8 lanes Link One direction of a PCle link The FS4405 handles 1 or 2 links at a time independently This supports probing of both directions of a PCle link or probing of a pair of unrelated one direction links Links may be merged when displayed on the logic analyzer Lane One direction of a PCle lane Accessories Supplied Minimum Equipment Required Analyzing the PCI Express Bus This chapter introduces you to the FS4405 preprocessor and lists the minimum equipment required for PCI Express Bus analysis The FS4405 is a High Speed Flexible Serial bus State Analysis preprocessor It is designed to handle two directions of a link or a single direction from each of two unrelated links using two link processors A and B at lane widths of 1 2 4
27. ated packets Yellow Unknowns White 42 Transaction Viewer The FS4405 Protocol Decoder is fully integrated with the FuturePlus Systems Transaction Viewer application This following figure is an example Transaction Viewer and Settings Pauly D eese EAModules Set Preferences The Transaction Viewer is a powerful tool that allows the user to view data captured with the FS4405 in a graphical environment that presents the information by Transaction as opposed to State The Transaction Viewer itself is a separate application that needs to be downloaded from the FuturePlus Systems website www futureplus com The user manual for the Transaction Viewer is also separate and can be found either on the FuturePlus Systems Documentation CD or the FuturePlus Systems website The screen listed above displays the same set of transactions that are contained in the previous sections IA trace protocol decode screen As you can see the level of detail has been brought up to the transactional level with the effect of allowing the new tool to show a much greater range of decoded trace states General Information Characteristics Standards Supported Weight amp Dimensions Power Requirements Logic Analyzer Required Number of Probes Used Logic Analyzer State Clock Frequency Environmental Temperature Altitude Humidity Testing and Troubleshooting Servicing This chapter provides additiona
28. can not achieve lock quickly until it receives a stable signal and a stable reference clock Signal detection does not imply a valid serial data signal Signal detection LOS status is delayed relative to link data capture 10b Mode The FS4405 requires an external reference clock connection when used in 10b mode Debug The LEDs operate as described previously Note When using the FS4405 in 10 bit Mode the user must select a Logic Analyzer System file based on the lane width of the link being probed The user must also select the correct lane width in the Probe Config window The probe hardware does real time lane based 8b10b error checking lane deskew and lane deskew checking There are no filters or pattern recognizers provided in 10b mode Packets and ordered sets are detectable using the analyzer trigger capabilities looking for the values listed below There is no disassembler however there are pre defined symbols that make packet boundaries visible in the state listing The following are some useful 10b symbol definitions for PCI Express All but the TSID values are available pre loaded in the lane data symbol tables for convenient setup of triggers Trigger on COM to find any ordered set Trigger on FTS SKP or IDL to find specific ordered sets Trigger on SDP to find DLLP packets Trigger on STP to find TLP packets Remember there are usually two different possible codes representing each character in 10 bit Mode Value
29. d 1 machine repeat for a link direction disparity or decode in any active lane Field Bits Definition Pod Bits ANY LOS 1 1 Any Lane Loss of Signal Al 15 0 Signal detect on all active lanes B1 Lane 0 Disparity Error 1 1 Lane data is the wrong 10B disparity 14 Lane 0 Invalid Decode 1 1 Lane data is an invalid 10B decode 13 Error LaneO 10 Encoded 10b value 12 3 Unused 2 Set to 0 2 1 Any Invalid Error Flag 1 1 7 This state includes a 10B code error 0 The clock is on A1 bit 16 LAI Bit Definitions For a Single Direction x8 Link 10b mode 6 Pods 1 machine Field Bits Definition Pod Bits Unused 1 Set 0 A2 16 Align Flag 1 1 Alignment of multi lane link detected 15 Any Invalid Error Flag 1 1 7 This state includes a 10B code error disparity or 14 decode in any active lane Any LOS 1 1 Any Lane Loss of Signal 0 Signal detect 13 Lane 0 Disparity Error 1 1 7 Lane data is the wrong 10B disparity 12 Lane 0 Invalid Decode Error 1 1 Lane data is an invalid 10B decode 11 Lane 0 10B Data 10 Encoded 10b value 10 1 Lane 1 Disparity Error 1 1 7 Lane data is the wrong 10B disparity 0 Lane 1 Invalid Decode Error 1 1 Lane data is an invalid 10B decode A1 15 Lane 1 10B Data 10 Encoded 10b value 14 5 Lane 2 Disparity
30. e binary values by clicking the Accept button the binary value is converted to a hex representation and displayed in the pattern dialog Field Hex digits that are partially masked will be displayed with a character Binary Field Editor xj Out Binary Editor Dialog The packet recognition setups are created via sub dialogs that are displayed whenever the user selects a packet type via the radio buttons for each link pattern and clicks the Edit button The pattern is edited if the user clicks the Apply button on the packet specific sub dialogue form If edited the packet type string is displayed in a light blue color Once edited the pattern may be cleared by clicking the Clear button This will inactivate the recognizer Pattern Recognizers are used to trigger the logic analyzer whenever a specific packet or ordered set pattern is encountered Each Pattern recognizer outputs a PAT REC flag to the logic analyzer that pulses high during the 1 state of each packet Pattern recognizers may also be used as filters The Pattern Recognizer examines the first 24 bytes of each packet Recognizers are setup by the Probe Manager with a match pattern and a separate mask pattern giving the user control over the comparison bit by bit The probe must be stopped before editing patterns You must always restart the probe by pressing the green run button on the main window so the new values will be written to the probe ha
31. e serializing the data stream for the logic analyzer the FS4405 generates Labels PCle number of identification and control bits that are used by the Protocol Decoder and logic analyzer These are also available to the user and can be used as described Pre defined Label No Definition Usage Logic Logic of Analyzer Analyzer Bits Pod Pod X1 x2 x4 x8 mode mode VAB Collection of all flags for Inverse Assembler usage DS 1 1 Store this state 0 Discard 4 16 4 10 Default Store Flag This signal must be used for default CLK CLK store qualification PSS 2 PSS 1 Start of Packet flag 4 5 4 4 3 2 Packet Sample State PSS 0 End of Packet flag 10 start 01 11 2 start amp end 00 inside packet ordered set or idle Use PSS 1 1 in conjunction with Event Code to detect each occurrence Unjust 1 X8 only When set indicates a packet NA 4 4 beginning at lane 4 rather than lane 0 Event Code 6 Describes what type of packet ordered 4 0 3 4 1 0 Set signal event or error event Code is A3 16 15 B3 16 13 held for duration of packet or ordered set except that probe generated signal and error events can over write any state except the start state When start and end coincide the event code for the starting packet is displayed See next page for a list of event code values Bit 9 is Invalid flag Bit 8 is Control flag Error 1 17 This state includes an error A4 13
32. er Fault Red Processor Clock Error FS4405 Probing Cables The FS4405 PCI Express probe can be configured with a wide variety of different probing cables dependent on what the user requires FS1031 Full size midbus footprint probe cable for x1 x2 x4 FS1032 72 size midbus footprint probe cable for x1 x2 x4 x8 FS1033 ExpressCard Interposer probe cable with reference clock buffer FS1034 X1 slot Interposer probe cable FS1035 x4 slot Interposer probe cable FS1036 Flying lead probing cable for x1 x2 x4 x8 FS1037 x8 slot interposer cable requires 2 FS4405 probes FS1038 Full size midbus footprint probe cable for x8 requires 2 FS4405 probes FS1039 Full size midbus footprint probe cable for x8 requires 2 FS4405 probes Cables FS1038 and FS1039 can also support x1 x2 x4 probing Cables FS1038 and FS1039 differ in their pinouts the FS1039 better supports the routing of all lanes on the same surface layer The PCI Express Probing Design Guide for the F8440X provides specific information on the successful application of midbus probing and also details general requirements for the Reference Clock signal and other aspects of the link to be probed The FS4405 manual assumes that the user is familiar with this information and has applied it The cable should be attached to the FS4405 and carefully secured with the 2 captive fasteners on the cable The probing end should be attached to the target either by screwing into t
33. et starts in Lane 4 4 Packet Sample 2 PSS 1 SOP start of packet or ordered set 3 2 State PSS 0 EOP end of packet or ordered set 10 start 01 end 11 start amp end 00 inside packet inside ordered set or Idle Event Code 6 Describes what type of packet ordered set signal event or 1 0 error event Code is held for duration of packet or ordered set except that signal and error events can over write any state B3 16 13 except the start state When start and end coincide the event code for the starting packet is displayed Any LOS 1 1 Any active lane has Loss of Signal 12 0 All active lanes have Signal detect Lane 4 Sym Invalid 1 0 Valid 8b decode 1 Incorrect disparity or code violation 11 Lane 4 Control Flag 1 12K character control 0 D character data 10 Lane 4 8b Data 8 Decoded 8b value 9 2 Lane 5 Sym Invalid 1 0 Valid 8b decode 1 7 Incorrect disparity or code violation 1 Lane 5 Control Flag 1 12K character control 0 D character data 0 Lane 5 8b Data 8 Decoded 8b value B2 16 9 Lane 6 Sym Invalid 1 0 Valid 8b decode 1 7 Incorrect disparity or code violation 8 Lane 6 Control Flag 1 12K character control 0 D character data 7 Lane 6 8b Data 8 Decoded 8b value 6 0 B1 15 Lane 7 Sym Invalid 1 0 Valid 8b decode 1 7 Incorrect disparity or code violation 14 Lane 7 Control Flag 1 12K character control 0 D character data 13 Lane 7 8b Data 8 Decoded 8b value 12 5 Spare 5 Unused bits 4 0 The clock is on B1 bit 1
34. etates snae sean 42 Transaction RR 43 45 45 Standards Supported 45 Power Requirements 2 grin e 45 Logic Analyzer Required endete orare 45 Number of Probes Used ade rote obedece ciet tq ente e ze Prieto e 45 Logic Analyzer State Clock Frequency nennen nennen 45 Environmental Temperature 45 AGU 45 45 Testing and Troubleshooting ere A nee eet Sen 45 45 Signal m 46 LAI Bit Definitions for a Single Direction x1 x2 x4 Link PCIe 46 LAI Bit Definitions For a Single Direction x8 Link PCIe mode sss 47 Th clocks on B1 bit 16 eso eere piede renes puede e deren enne 47 LAI Bit Definitions for a Single Direction x2 x4 Link 106 48 LAI Bit Definitions For a Single Direction x8 Link 106 mode sess 49 How to reach us For Technical Support FuturePlus Systems Corporation 36 Olde English Road Bedford NH 03110 TEL 603 471 2734 FAX 603 471 2738 On the web http www futureplus com For Sales and Marketing Support FuturePlus Systems Corporation TEL 719 278 3540 FAX 719 278 9586
35. gnizer pattern The x1 x2 and x4 Packet Recognizer dialog allows the user to enter up to 6 patterns 3 on link A and 3 on link B In x8 mode the user can enter up to 3 patterns In x8 mode packets are detected if they start on lane O or lane 4 The pattern is entered via a sub dialog that is displayed after the user has clicked one of the six Edit buttons There are three sub dialog forms one for Ordered Sets one for DLLP packets and one for TLP packets as shown below IPCI E Pattern Recognizers Link Pattern 1 DLLP Pattern and Mask Dialog PCI E Pattern Recognizers Link A Pattern 1 amp I E LN 00 EN EN E EN Ez EX ML e TLP Pattern and Mask Dialog PCI E Pattern Recognizers Link Pattern 1 ir sr ST ST ST og aR P RF ST aOR GF RF RFS a ORF RF ORF gr Ordered Set Pattern and Mask Dialog The DLLP and Ordered Set sub dialog screens are designed such that the minimum numbers of fields are specified to form a valid packet Fields displaying X s will be masked out All reserved fields will be masked into the pattern Every field is validated as the user is entering the hex values The user may enter any combination of X s and hex digits into each field Each field may be edited in binary form by right clicking the mouse key at which point the contents of the field are displayed in binary format in a separate window When the user applies th
36. he retention module midbus probe or inserting the Interposer into the slot being probed Use of the flying lead probe requires careful installation and mechanical support of special axial leaded RF resistors Note that use of the external Reference Clock is required when e Spread Spectrum modulated clocking is occurring e The target transmitter frequency is not within 100 ppm of nominal even though the PCle standard allows 300 ppm deviation from nominal e When the probe is operated in 10b mode 10 bit undecoded mode e Only Reference Clock A is supported Both links being probed must use the same external Reference Clock Interposer Probing FS1034 5 7 Due to the source terminated nature of the Reference Clock used in PCle it is difficult to acquire a quality signal at a mid point of the Reference Clock trace which is where the Interposer probe sees it In order to provide a high quality signal at the Interposer probing point these probes FS1034 5 7 incorporate a PCle Reference Clock buffer chip which serves to terminate this signal and then re transmit it to both the target board and to a pin connector JR1 on the Interposer that can be used to connect the Ref CIk cable from the FS4405 probe The Reference Clock Buffer chip can be operated in two modes By Pass or PLL FuturePlus recommends that the Interposer probe be used in By Pass BP mode If used as a PLL it could create dynamic tracking error between the PLL used on
37. is not a valid 8b10b code NA A1 10 4 8 Lane3 10 Physical Lane 3 Data 10 bit encoded NA 1 9 0 4 7 0 B3 16 15 Lane 4 Disparity Error 1 1 Lane 4 data has incorrect 8b10b disparity NA NA B3 14 Lane 4 Invalid Decode Error 1 1 Lane 4 data is not a valid 8b10b code NA NA B3 13 Lane4 10 Physical Lane 4 Data 10 bit encoded NA NA B3 12 3 x8 mode only Lane 5 Disparity Error 1 1 Lane 5 data has incorrect 8b10b disparity NA NA B3 2 Lane 5 Invalid Decode Error 1 1 Lane 5 data is not a valid 8b10b code NA NA B3 1 Lane5 10 Physical Lane 5 Data 10 bit encoded NA NA B3 0 x8 mode only B2 16 8 Lane 6 Disparity Error 1 1 Lane 6 data has incorrect 8b10b disparity NA NA 2 7 Lane 6 Invalid Decode Error 1 1 Lane 6 data is not a valid 8b10b code NA NA B2 6 Lane6 10 Physical Lane 6 Data 10 bit encoded NA NA B2 5 0 x8 mode only B1 15 12 Lane 7 Disparity Error 1 17 Lane 7 data has incorrect 8b10b disparity NA NA B1 11 Lane 7 Invalid Decode Error 1 1 7 Lane 7 data is not a valid 8b10b code NA NA B1 10 Lane 10 Physical Lane 7 Data 10 bit encoded NA NA B1 9 0 x8 mode only Triggering The system files provide some logic analyzer based trigger set ups that utilize the pre defined symbols described earlier TLA off line Trigger LA 1 For Help press Fl 51 0 Sg GJEAKETMnst 1 d am HE gcx TE File Edit View System Tools Windo
38. ive State Power Management ASPM mode Activate when the target link state is repeatedly switching between normal operational LO and shallow power saving LOs states Activating this control allows the probe hardware to decode traffic starting early in the Fast Training process usually within the first few FTS Ordered Sets transmitted when the link returns to LO state Activating this control comes with a small price in that LOS status for the active lanes is not available while the probe is running There are two consequences of running in ASPM mode o Signal loss is reported on LEDs and in the Log File as other types of errors that result from signal loss o LOS status bits can not be used for triggering the logic analyzer and are not useful in the listing because they are forced to 0 only while running and only on active lanes Selection of Toggle mode When activated the probe output signals to the logic analyzer pods and the link status LEDs are toggled Packet Recognizers This dialog form provides the ability to setup the three 24 byte Pattern Recognizers provided on each link PCI E Pattern Recognizers E Pattern and Mask X1 X2 X4 Dialog Because the pattern recognizers look at the first 24 bytes of each packet or ordered set they are also referred to as packet recognizers x8 Pattern Recognizers Pattern and Mask X8 Dialog The Packet Recognizer dialog allows a user to specify the packet reco
39. l reference information including the characteristics and signal connections for the FS4405 probe The following operating characteristics are not specifications but are typical operating characteristics for the FS4405 probe If the product is used in a manner not specified by manufacturer then the protection provided by the equipment may become impaired PCI Express Base Specification Revision 1 0a and 1 1 17 x 10 x 1 4 5 Ibs 100 240VAC 2 amps into AC DC supply 5V at 8 amps to FS44xx Tektronix TLA7AA3 4 or TLA7NA3 4 modules installed in a TLA71x or TLA70xx frame The State Adapter Probe interface uses 4 FS1105 cables of 90 pin type 125MHz for x1 PCI Express Protocol Analysis or 250MHz for x2 x4 or x8 250 MHz for x1 x2 x4 or x8 PCI Express 10b analysis Non operating 40 to 75 degrees C 40 to 167 degrees F Operating 20 to 30 degrees C 68 86 degrees F Operating 1000m 3000 ft Non operating 15 3000m 50 000 ft Up to 80 relative humidity Avoid sudden extreme temperature changes which would cause condensation on the FS4405 module There are no automatic performance tests or adjustments for the FS4405 module If a failure is suspected in the FS4405 module contact the factory or your FuturePlus Systems authorized distributor The repair strategy for the FS4405 is module replacement However if parts of the FS4405 module are damaged or lost contact the factory for a list of replacement parts Signal C
40. nding lane Loss of Signal 0 Signal detect 10 7 3 2 1 0 Logically named reflects lane reverse status Lane 0 Symbol 1 0 Valid 8b decode 17 Incorrect disparity or code violation 6 Invalid 10b Mode Becomes 10b encoded data bit 9 Lane 0 Control Flag 1 12K character control 0 D character data 5 10b Mode Becomes 10b encoded data bit 8 Lane 0 8b Data 8 Decoded 8b value 4 0 10b Mode Becomes 10b encoded data bits 0 7 A2 16 14 Lane 1 Symbol 1 0 Valid 8b decode 1 Incorrect disparity or code violation B2 13 Invalid 10b Mode Becomes 10b encoded data bit 9 Lane 1 Control Flag 1 12K character control 0 2 D character data 12 10b Mode Becomes 10b encoded data bit 8 Lane 1 8b Data 8 Decoded 8b value 11 4 10b Mode Becomes 10b encoded data bits 0 7 Lane 2 Symbol 1 0 Valid 8b decode 1 Incorrect disparity or code violation 3 Invalid 10b Mode Becomes 10b encoded data bit 9 Lane 2 Control Flag 1 12K character control 0 D character data 2 10b Mode Becomes 10b encoded data bit 8 Lane 2 8b Data 8 Decoded 8b value 1 0 10b Mode Becomes 10b encoded data bits 0 7 A1 15 10 Lane 3 Symbol 1 0 Valid 8b decode 1 7 Incorrect disparity or code violation B1 9 Invalid 10b Mode Becomes 10b encoded data bit 9 Lane 3 Control Flag 1 1 K character control 0 D character data 8 10b Mode Becomes 10b encoded data bit 8 Lane 3 8b Data 8 Decoded 8b value 7 0 10b Mode Becomes 10b encoded data bits 0 7 The clock
41. nfig Write Type 0 CfgWro 0x16 TLP Config Read Type 1 CfgRd1 0 17 Config Write Type 1 CfgWr1 0x18 TLP Message Msg 0x19 TLP Message with Data MsgD Ox1A TLP Completion Cpl 0x1B TLP Completion with Data CpID Ox1C TLP Completion for Locked CpILk Ox1D TLP Completion Locked Data CpIDLk Ox1E DLLP Ack 0x20 DLLP Nak 0x21 DLLP PM Enter L1 0x22 DLLP PM Enter L23 0x23 DLLP PM Active State Req 0x24 DLLP PM Request Ack 0x25 DLLP Vendor specific 0x26 DLLP InitFC1 P 0x27 DLLP InitFC 1 NP 0x28 DLLP InitFC1 CPL 0x29 DLLP InitFC2 P 0 2 DLLP InitFC2 NP 0 2 DLLP InitFC2 CPL 0 2 DLLP UpdateFC P 0 20 DLLP UpdateFC NP Ox2E DLLP UpdateFC Cpl Ox2F Error Unexpected K 0x30 Error Packet Ends Bad 0x31 Link Down Signal Event 0x33 Error Logical Idle 0x34 Error Invalid Symbol Decode 0x35 Error Unexpected LOS 0x36 Error Framing 0x37 Error Alignment X8 mode only 0x38 Error Control Column X8 mode only 0x39 Error TSID X8 mode only Ox3A Error TLP Decode X8 mode only Ox3D Error DLLP Decode X8 mode only OxSE Besides de serializing the data stream for the logic analyzer the FS4405 in 10b Mode Labels 1 Ob generates a number of status bits that are available to the user and can be used for triggering and analysis as described below Pre defined Label No Definition Usage Logic Logic Logic of Analyzer Analyzer Analyzer Bits Pod Pod Pod 10 bit
42. nfigurations Help e About Display version numbers for the Probe Manager application and FPGA configuration The application displays up to five sub dialogs in a modeless manner The sub dialogs are used to configure the FS4405 probe The five sub dialogs are Probe Configuration Covers the type of probe cable used and basic aspects of the link being probed Packet Recognizers Set up the 3 Packet Recognizers provided per Link which may be used to specify packet header based triggering parameters Filters Allows the user to specify the types of packets to be filtered Log Entries Run time probe status Probe Configuration PCI E Probe Config PCI E X8 Probe Config Receive The Probe Configuration dialog provides the user with ability to configure the probe and monitor signal activity on each channel E a B B B B B Probe Config X1 X2 X4 Dialog EM GE GEM M UM M I Probe Config X8 Dialog The functions provided on these forms include Selection of the Probing Cable type Link width and pad arrangement referring to the arrangement of lanes on the mid bus probe pads see the PCI Express Probing Design Guide for the 440 for more specific information The Pad Assignment graphic shows the assignment of logical lanes as a result of user selections and also represents the physical layout of mid bus pads The FS4405 processes channels from the left c
43. ocol attributes such as lane inversion data scrambling lane reversal and spread spectrum that need to be defined in the Probe Manager in order for the probe to capture data properly It is strongly recommended that the user methodically proceed in the following manner when setting up the probe There is more detail on each step in this manual 1 Load the Probe Manager software and FS1160 on the PC and or logic analyzer Leave the CD in the system for access to the USB drivers 2 Configure merge the logic analyzer cards as required and run the Tektronix Logic analyzer s internal diagnostics on the cards If the analyzer passes then make the appropriate target probe connections to the FS4405 probe 3 Connect the appropriate probing cable s to the target system power up the probe This may result in a Windows dialog searching for the FTDI FTD2XX USB drivers direct it to the Probe Manager CD Check the Windows Device Manager to make sure that it loaded properly 4 Open up the Probe Manager application and select the appropriate settings for the probe cable being used and the PCI Express link Check that the expected Pad assignments for the probed link show green For the first capture turn off all the filters 5 If the FS4405 probe LEDs are all Green and the first trace file captured on the logic analyzer has no error messages then it is a good indication that all initial settings are correct 6 Alink showing Signal LED g
44. oldered to the pads at R17 and R18 Please contact FuturePlus Systems for these cables In many cases the ExpressCard module is not hot pluggable the FS1033 will have to be interposed between the target and the module before powering up the system The REFCLK signal is provided at JR1 for use with the FS4405 probe s cable The x1 PCI Express signals are cabled to a standard FS4405 probe connector Make sure all these connections are made before powering on the system or the probe J2 ce e GOH RSRVIBS USBD CPUSB R18 USBD R17 SMBDATABE SMBCLK RSRV Installing your The following outlines the software installation procedure when using the probe for the first time Please do not attach the probe to the analyzer or computer that will be Software for the First controlling the probe until told to do so Time 1 Place the software CD that came with the product into the logic analyzer or computer that you will be installing the software on In the case of a machine that does not have a CD drive the machine will either have to be put on a network and the files loaded remotely or the CD files can be transferred from a USB drive 2 Navigate to the installation CD using Windows explorer and click on the following files Follow the instructions on the screen to install e FS1160 exe PCle Protocol Decoder e FPSystems Disassembler exe This may already be installed if your system has a previously
45. olumn in link processor A and from the right column in link processor B Next or Previous buttons scroll through the various types of currently supported pad assignments see the PCI Express Probing Design Guide for the 440 for details of supported pad assignments Lane Inversion can be selected on an individual channel basis by clicking the INV button associated with each lane While the probe is stopped signal activity indicators are provided on each channel Signal presence is indicated by an up down arrow symbol and a lack of signal presence is indicated by a flat horizontal line symbol Selection of Lane Reversal on each link Selection of Data Descrambling on each link Reference Clocking choices are to use the FS4405 Internal reference on both links these links must have 100 PPM frequency accuracy or use External Reference Clock signal s from the target platform via the FS4405 external Ref Clock cable For PCle the expected frequency is 100 MHz If necessary PCle probing with a 125 MHz reference clock is supported by the FS4405 contact FuturePlus Systems for details Selection of external reference clock source for link B same as A common clock uses the Reference Clock A probe input or different distinct clock uses Reference Clock B probe input Selection of Spread Spectrum clock processing mode Activate only when spread spectrum modulation is in use requires external reference clock Selection of Act
46. onnections The FS4405 contains 8 90 pin Samtec pod connections The following is the pinout configuration of the connectors repeat for 2 link direction B pods LAI Bit Definitions for a Single Direction x1 x2 x4 Link PCle mode 4 Pods 1 machine Field Bits Definition Pod Bits Default Store Flag 1 17 Store this state 0 Discard 4 16 8b 10b Mode 1 0 Data is 8 bit decoded 1 Data is 10 bit encoded B4 15 Aligned 1 1 Multi lane link is word aligned bonded 14 Data Error 1 1 This state includes an error 13 In reset 1 1 This state affected by SYSRST 12 Packet Recognizer 3 1 Packet recognized pulsed for one clock cycle during packet 11 9 Spare 3 presently unused 8 6 Packet Sample 2 10 start 01 end 11 start amp end 00 packet ordered 5 4 State set or Idle Event Code 6 Describes what type of packet ordered set signal event or error 3 0 event Code is held for duration of packet or ordered set except that signal and error events can over write any state except the 1645 start state When start and end coincide the event code for the starting packet is displayed B3 Data Present 4 1 Corresponding lane data byte is present 0 Data not 14 11 3 2 1 0 present Not present is due to lane spreading of x1 and x2 to 4 lane format LOS 4 12 Correspo
47. pture data In order to view decoded data offline after installing the TLA7xxx environment on a PC you must install the FuturePlus software Please follow the installation instructions for Setting up TLA7xxx analyzer Once the FuturePlus software has been installed and licensed follow these steps to import the data and view it From the desktop double click on the Tektronix TLA icon When the application comes up there will be a series of questions answer the first question asking which startup option to use select Continue Offline On the analyzer type question select Cancel When the application comes all the way up you should have a blank screen with a menu bar and tool bar at the top Open the tla file using the File Load System menu selection and browse to the desired file aso BRS xt amp After the data has been imported you must load TLA disassembler before you will see any decoding To load the disassembler select Tools from the menu bar when the drop down menu appears select FPSSystems decoder then choose the name of the protocol for your particular product when the disassembler window appears You need to choose a disassembler and a data source for each direction The figure below is a general picture sdgri off line FPS Decoder View File System Tools Window Help E Protocol Designer FPSystems Disassembler iverify SE AutoDeskew 8 Xx setup IF
48. rdware Filtering Filters Bi The Filter dialogue page provides the user with a comprehensive suite of predefined filter functions to apply to either Link Filter types include all TLP and DLLP packets Ordered Sets Traffic Class Virtual channel and special signal states Additionally filters are provided to Pass or Drop packets that have been recognized by the three packet recognizers 202 u u u NM I E 9 2g NI Filters X1 X2 X4 Dialog Filtering is done in real time by the FS4405 hardware Filtering out unwanted traffic such as Logical Idles can extend the storage capabilities of the logic analyzer Filtering out irrelevant bus traffic can help users focus on specific packets of interest To filter out any particular traffic type click on the appropriate box so a Y appears and click apply You must restart the probe by pressing the green run button so the new values will be written to the probe hardware Use Link A and Link B buttons to switch to the other link s filter Filtering can also be done using any combination of packet header bits via the Pattern Recognizers The PR Drop filters drop the recognized packets The PR Pass filters over ride all other filters and force recognized packet to be clocked into the analyzer PCI E X8 Filters uuu ugi E uuu ugi ug M Filters X8 Dialog Filtering is
49. reen and Data LED orange constantly needs settings for link width lane reverse or lane inversion adjusted in the Probe Config window 7 Alink showing Signal LED orange or red may have a problem with the reference clock connection or need settings for Internal External reference clock adjusted in the Probe Config window More information on link signal status can be seen in the Log File window Front Panel The connections and features of the FS4405 probe include DC input for provided external AC to DC power supply please note that the use of any other power supply voids the warranty on the FS4405 On Off switch and USB connections to the Windows PC TLA7xxx where the Probe Manager software will be loaded Link Probe cable connection for any 1 of the different probing cables and Reference Clock probe cable connections Logic Analyzer probe 90 pin pod connections A1 A4 are connections for 1 Link Processor and B1 B4 are for the other Link Processor Reference Clock Probe Cable is permanently attached to the FS4405 LED indication of probe power on and Link status For each link there is a pair of LEDs which have the following states Link A or B Meaning Link A or B Meaning Signal LED Data LED color color Green Link OK Green Data clocking Into Analyzer Dark Loss of Signal Dark No Data clocking into Analyzer Orange Data Invalid 8b10b error Orange Any Error 8b10b Align Framing Idle Red Receiv
50. rotocol decode View File System Tools Window Help Protocol Designer FPSystems Disassembler Drama ore TK For Help press F1 362898322 362698465 362898465 362898807 362898807 36289896 36289896 362899052 362899052 36289909C 362899131 362899171 362899211 362899251 362899292 362899332 362899372 362899412 362899452 362899452 362899455 362899455 362899495 362899535 362899575 362699616 36289965 36289969 36289973 362899777 362899817 36289985 36289989 36289989 36289993 36289997 362900020 36290006C 36290006C 362900101 362900141 362900181 362900221 362900262 362900302 362900342 362900382 362900422 362900465 362900505 362900505 36290054 36290058 36290062 UpdateFC NP VC 0h HdrFC 17h DataFC 020h CRC 12B8h UpdateFC NP 0 HdrFC 18h DataFC 020h CRC 2BA8h Ack Seq 9AEh CRC 1220h UpdateFC NP VC 0h HdrFC 1Bh DataFC 020h CRC 1F1Bh Completion With Data Seq 9Ah FMT 2h Type 0Ah TC 7h TD 0h EP 0h Attr ih Length Completer ID 0000h complStatus Oh BCM 0h Byte Count 080h Re Data 00230400h Data 04000000h Dat 0CO0400h Data 7109D4D3h Data 10C10400h Data 00000000h Data 10C10400h Data 00000000h Data 10C10400h Data 00000000h Data 10C10400h Data 00000000h Dati 0C10400h Data 00000000h Dati 0C10400h Data 00000000h CRC 663F16FBh Completion With Data Seq 9Bh FMT 2h Type DAh UpdateFC P VC 0h HdrFC DOh DataFC 6C6h CRC 6FB6h TC 7h TD 0h
51. software and hardware designated by FuturePlus Systems for use with an instrument will execute its programming instructions when properly installed on that instrument FuturePlus Systems does not warrant that the operation of the hardware or software will be uninterrupted or error free The foregoing warranty shall not apply to defects resulting from improper or inadequate maintenance by the Buyer Buyer supplied software or interfacing unauthorized modification or misuse operation outside of the environmental specifications for the product or improper site preparation or maintenance NO OTHER WARRANTY IS EXPRESSED OR IMPLIED FUTUREPLUS SYSTEMS SPECIFICALLY DISCLAIMS THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE THE REMEDIES PROVIDED HEREIN ARE BUYER S SOLE AND EXCLUSIVE REMEDIES FUTUREPLUS SYSTEMS SHALL NOT BE LIABLE FOR ANY DIRECT INDIRECT SPECIAL INCIDENTAL OR CONSEQUENTIAL DAMAGES WHETHER BASED ON CONTRACT TORT OR ANY OTHER LEGAL THEORY Product maintenance agreements and other customer assistance agreements are available for FuturePlus Systems products For assistance contact Technical Support How to Use This Manual Definitions Introduction This manual is organized to help you quickly find the information you need Analyzing the PCI Express Bus chapter introduces you to the FS4405 and lists the minimum equipment required and accessories supplied for PCI Express bus analysis The St
52. tem file located in the FS1160 shortcut located on the desktop To load the disassembler select Tools from the menu bar when the drop down menu appears select FPSystems Disassembler Load the PCI Express Protocol Disassembler software FS4405 by selecting the correct protocol PCle and data source for each direction and press the decode button If you are analyzing 2 different protocols simply choose the data source and direction and the correct protocol for the data source 362898322 362898322 36289848t 36289848t 362898807 362898807 36289896 36289896 36289905C 36289905C 36289909C 362899131 362899171 362899211 362899251 362899292 362899332 36289937 36289941 36289945 36289945 36289945t 36289945t 362899495 362899535 36289957 36289961 36289965 36289969 36289973 362899777 362899817 36289985 36289989 36289989 36289993 36289997 362900027 36290006C 36290006C 362900101 362900141 362900181 362900221 362900262 362900302 362900342 36290038 36290042 362900465 362900505 362900505 362900545 36290058 36290062 Setup trigger 25 v UpdateFC P VC 0h HdrFC DOh DataFC 6C6h CRC 6FB6h UpdateFC NP VC 0h HdrFC 17h DataFC 020h CRC 12B8h UpdateFC NP VC 0h HdrFC 18h DataFC 020h CRC 2BA8h Ack Seq 9AEh CRC 1220h UpdateFC NP VC 0hHdrFC 1BhDataFC 020h CRC 1F1Bh Completion With Data Seq 9Ah FMT 2h Type 0Ah TC 7h TD 0h EP 0h Attr 1h Length Completer
53. the system board and the PLL function on the interposer during SSC operation It is possible to use the PLL function to reduce jitter in the Reference Clock This would require moving the JR2 jumper from connecting the center and right hand pins to connection the left hand and center pins Additional control of the PLL mode can be provided by changing the bandwidth of the PLL from Low to High by moving the jumper at JR3 This BW function is only active when the device is in PLL mode The proper recommended shunt location is shown by a dashed line below be VEM PLL a BP L o C JR1 REF CLK Flying Lead Probing FS1036 cable assembly The FS1036 flying lead cable assembly allows the FS4400 probe to connect to components on the target board by means of directly soldering a flex pcb to a component or feature on the target pcb then connecting the header on the flying lead cable to the other end of the flex pcb 100 2 54 REF MDC 100 2 54 REF 5 103 02 5 5 SUB SCF 134473 01 DA 4602 010 11 68 0 25 RES 0402 3010 F JB 5M 012 0 30 REF ose o s7 eer Bl gl os 053 034 0 84 REF 03 0 99 REF 210 5 33 REF 1 022 0 55 REF STIFFENER A few general guidelines about the use of the flying lead cable 1 There is an instruction booklet with the FS1036 cable that provides detail on how to solder the flex pcb to your board Refer to this document 2 Polarity
54. the web http www futureplus com FuturePlus Systems has technical sales representatives in several major countries For an up to date listing please see http www futureplus com contact html gt Limitation of Warranty Exclusive Remedies Assistance Product Warranty This FuturePlus Systems product has a warranty against defects in material and workmanship for a period of 1 year from the date of shipment During the warranty period FuturePlus Systems will at its option either replace or repair products proven to be defective For warranty service or repair this product must be returned to the factory Due to the complex nature of the FS4405 and the wide variety of customer target implementations the FS4405 has a 30 day acceptance period by the customer from the date of receipt If the customer does not contact FuturePlus Systems within 30 days of the receipt of the product it will be said that the product has been accepted by the customer If the customer is not satisfied with the FS4405 they may return the FS4405 within 30 days for a refund For products returned to FuturePlus Systems for warranty service the Buyer shall prepay shipping charges to FuturePlus Systems and FuturePlus Systems shall pay shipping charges to return the product to the Buyer However the Buyer shall pay all shipping charges duties and taxes for products returned to FuturePlus Systems from another country FuturePlus Systems warrants that its
55. w Help Urey Decode Y Protocol Desa E Vei iTe Wave Bsns GE Fri 2j L S itt 3 Storage Conditional Force MainPrefil Trigger Pos pos E EH Storage If Group STORAGE 1 Run Then Store Sample State 1 Trigger on the very first sample If Group A_Event_Code Ack DLLP Then Trigger Modules Remember to always use STORAGE for default storage and use default storage to fill memory If you are analyzing only 1 direction you should change the group name STORAGE to either A DS or B DS depending on which direction you are analyzing if you do not make this change the state listing may not show any valid data STORAGE is an OR of A DS and B DS if one side is not being used the DS bit may be held high which will fill the analyzer with invalid information The 6 bit probe generated Event Code field makes it easy to trigger on particular packet types When triggering on Event Code always qualify it with e DS 1 Already included in pre defined Event Code symbol definitions PSS 1 1 The start of packet flag The probe generated Packet Recognizer flags Pat_Rec_3 2 1 make it easy to trigger on packets based on header or data bit patterns in the first 24 bytes of each packet These flags are always valid pulse once at the start of each recognized packet and do not need
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