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MPC852TADS Users Manual - Freescale Semiconductor

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7. 92 Release 1 0 For More Information On This Product Go to www freescale com EUNT EET TODS SOI SE 1u luQ JO 9 savizseodN vioxosow joronpuo uctor ang Support Information FIGURE A 2 Table of Contents Freescale Semico 2 0 100 80 8 9d 9 50 129809 W S80 ISIN MS Sng Was LSOH SHOLO 3NNOO NOISNVdX3 YAZATVNY 91901 10 9 2259 usog SYHOLVOIGNI 8 13539 l3NH3Hl3 9 I3NH3H13 1S VJ H3M Od S39IA3G 3 l Q9HSV14 Suad4na Wvuas 1056804 SIUL yuo sng uoijduoseq lt TQ L Release 1 0 For More Information On This Product Go to www freescale com 93 uctor ang Freescale Semico Support Information FIGURE A 3 MPC852T
8. Cycle Type Single Read Burst Read Single Write Burst Write Refresh Exceptions Offset In 0 8 18 20 30 3C Contents 0 1FO7FC04 1F07FC04 1F27FC04 1FO7FC04 1FF5FC84 7FFFFCO7 ioi 1 EEAEFCOA EEAEFC04 EEAEBCOO EEAEBCOO FFFFFC04 X 2 11 4 10ADFC04 01B93C04 10AD7C00 FFFFFC04 X 3 EFBBBCOO FOAFFCOO 1FF77C47 FOAFFCOO FFFFFC04 X 4 1FF77C47 FOAFFCOO X FOAFFCOO FFFFFC84 5 1FF77C348 F1AFFCOO X E1BBBC04 FFFFFCO7 6 EFEABC34 EFBBBCOO X 1FF77C47 X 7 1FB57C35 1FF77C47 X X X 8 X X X 9 X X X A X X X B X X X C X X D X X E X X F X X a MRS initialization uses free space 33 Release 1 0 For More Information On This Product Go to www freescale com Freescale 5emiconductor INE Functional Description 4 Functional Description The design details of the various modules comprising the MPC852TADS are described in this chapter 4e Reset amp Reset Configuration The ADS has several reset sources 1 Regular Power On Reset 2 Manual Soft Reset 3 Manual Hard Reset 4 Host Hard Reset through on board command converter 5 MPC Internal Sources see the appropriate Spec or U M 4 1 1 Regular Power On Reset The power on reset to the MPC852T initializes the processor state after power up A dedicated logic using Seiko S 80828ANMP EDR T2 which is a voltage detector of 2 8V 2 asserts PORESET inputs to the MPC852T and for a period of 500msec This time period is long
9. For More Information On This Product Go to www freescale com HaAuMd voor SOA T T T 1 T T ZW sa anio anioganro aio dio Tani oo IELO _ 0219 9810 0819 010 9910 9910 iru I wes enta 51 vin 99 uctor eng Freescale Semico Support Information FIGURE A 9 Power T 19 908 E002 Sz MeN epsa UPAM _ A pP 6 ev qun zi SQ V12S80dW enu 118 1 1 eyuays H 17 BJS QHEONEJQWIA an 029 T LEAL Hi i i oven Sven 10 sem c 5 Y 1 pe 6 QHEONEJQINN tren g T arloves ES lt 4 o E E Eren z y 4 TO T QHEONEJQININ 905 181911 even oo fan 22 S610 Q LP p meag V enen vau I SAY08 l iui it e on ar un ON38 4 LH39A g v 19048 t mo fe sho Sas iNav anto ano T am 99 m ion OddAD Od 0991999 En 78
10. 204 INSTALLATION INSTRUCTIONS Boards are shipped without DRAM EDO Since all the SW is based on the DRAM it is necessary that the user change BR2 BR3 BR4 and OR4 In BR2 BR3 the valid bit should be 0 bit 31 BR4 0x000000C1 and OR4 should be 0xFC 00A00 This configuration will map the SDRAM to ADD 0 amp 0x3000000 for 8MB configured the MPC852TADS may be installed as per the required working environment Host Controlled Operation Standalone 2e4e Host Controlled Operation For host controlled operation a host computer controls the board via the BDM Debug Port which is a subset of the JTAG port This configuration serves for extensive debugging using an on host debugger Host computer connects with the board as follows or through External Command Converter provided by a third party Macraigor System or through On Board Serial Command Converter No needs an external part or through On Board Enhanced Parallel Port EPP Converter No needs an external part A For FUTURE USE 10 Release 1 0 For More Information On This Product Go to www freescale com Freescale Semiconductor 16 Hardware Preparation and Installation FIGURE 2 7 Host Controlled Operation Scheme with External Command Converter PC
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12. PCCVPP 0 1 PC y did 00 0 01 5 10 428 11 Hi Z a Provided a 12V power supply is applied 4e1 1e3 5 2 Board Control Status Register 2 BCSR2 is a status register accessed at offset 8 from the BCSR base address It is a read only register that may be read at any time TABLE 4 14 BCSR2 Description on page 56 describes the various BCSR2 fields 23 Release 1 0 For More Information On This Product Go to www freescale com Freescale 5emiconductor INE Functional Description TABLE 4 14 BCSR2 Description BIT MNEMONIC Function PON DEF ATT FLASH PD 4 1 Flash Presence Detect 4 1 These lines are connected to the Flash SIMM Presence Detect lines that encode the Flash SIMM Type mounted on the Flash SIMM socket Three additional Presence Detect lines that encode the SIMM Delays appear in BCSR3 For FLASH PD 4 1 encoding see TABLE 4 15 Flash Presence Detect 4 1 Encoding on page 56 Reserved Not Implemented DRAM PD 4 1 DRAM Presence Detect These lines are connected to the DRAM SIMM Presence Detect lines that encode the size and delay of the DRAM SIMM mounted the DRAM SIMM socket For DRAM PD 4 1 encoding see TABLE 4 16 DRAM Presence Detect 2 1 Encoding on page 56 and TABLE 4 17 DRAM Presence Detect 4 3 Encoding on page 57 9 31 Reserved Not Implemented 56 TABLE 4 15 Flash Presence Detect 4
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21. 2100020 2100040 while BCSR1 appears at 2100004 2100024 2100044 and so on c Only upper 16 bit 00 015 are used d Refer to the relevant MPC User Manual for a complete description of the MPC internal memory map TABLE 3 2 Memory Map in MPC852TADS Compatible Mode ADDESS RANGE Memory Type Device Type il 00000000 003FFFFF DRAMSIMM MB321Bx 08 MB322Bx 08 Mc324Cx 00 MB328Cx 00 32 00400000 007FFFFF 32 00800000 OOFFFFFF 32 01000000 01FFFFFF 32 21 Release 1 0 For More Information On This Product Go to www freescale com Freescale Semiconductor INE OPERATING INSTRUCTIONS TABLE 3 2 Memory Map in MPC852TADS Compatible Mode ADDESS RANGE Memory Type Device Type ae 02000000 020FFFFF Empty Space 02000300 020003FF Control Register 02100000 02107FFF BCSR 0 4 P 32 02100000 02107FE3 BCSRO 2100004 02107FE7 BCSR1 2100008 02107FEB BCSR2 210000C 02107FEF BCSR3 2100010 02107FF3 BCSR4 02108000 021FFFFF Empty Space 02200000 02207FFF MPC Internal 32 MAP 02208000 027FFFFF Empty Space 02800000 029FFFFF Flash SIMM MCM29F020 MCM29F040 MCM29F080 32 SM732A1000A SM732A2000 02A00000 O2BFFFFF 32 02C00000 O2FFFFFF 32 03000000 037FFFFF SDRAM 32 8MB 03400000 FFFFFFFF Empty Space a x
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23. BA19 BAS30 A Resultant addresses lead to adjacent memory cells 41 Release 1 0 For More Information On This Product Go to www freescale com Freescale Semiconductor INE Functional Description 4 7 Flash Memory SIMM The MPC852TADS has 2MB of 90 nsec Flash Memory SIMM or more specifically Motorola s MCM29020 In addition to Motorola s MCM29020 support is also provided for the following Smart Technology products 4MB MCM29F040 8 MB MCM29F080 4 MB SM73218 and 8 MB SM73228 A Motorola SIMM is composed of one two or four banks of four Am29F040 compatible devices A Smart Technology SIMM is comprised of one or two banks of four 28F008 Intel devices The Flash SIMM resides on an 80 pin SIMM socket To minimize MPC chip select line usage one chip select line CSO is used in order to select the Flash Memory as a whole The distribution of chip select lines amongst the internal banks is done via on board programmable logic The latter is achieved according to the Presence Detect lines of the ADS s Flash SIMM FIGURE 4 3 Flash Memory SIMM Architecture Flash Presence Detect Lines ADD s VI29F040 1 8 M29F040 M29F040 M29F040 or 1MX8 EE M29F040 or M29F040 or M29F040 or bee F_
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25. 222 E 21 nds X IN o 8 T c 2 5 E Ls z Ie lz m en Release 1 0 For More Information On This Product Go to www freescale com Freescale Semiconductor 16 Hardware Preparation and Installation 2030 MPC Replacement of U1 Turn off the power prior to replacing the MPC Note the location of the original MPC A1 pin when replacing a U1 with another MPC Set the new MPC in the same direction as the previous one FIGURE 2 3 MPCTOP VIEW 20302 Clock Source Selection J1 The clock source for the MPC is selected by J1 When a jumper is placed between position 1 2 On board Clock is selected either 10MHz Clock generator or 10MHz Crystal resonator depending on SW4 position When a jumper is placed between position 2 3 External Clock is selected FIGURE 2 4 Clock Source Selection J1 1 J1 1 1 On Board Clock External Clock 20303 Modin Selection SW4 The on board clock source for the MPC is selected by SW4 The on board 10MHz crystal resonator connected between EXTAL XTAL MPC pins becomes the clock source when SW4 1 2 ON ON or PON OFF and the ADS is powered up However when SW4 1 2 OFF ON or OFF OFF but the ADS is powered up then the on board 10MHz clock generator connected to EXTCLK MPC pin becomes the clock source Clkout is calculated by CLK_IN 10MHz multiplied by the PLL
26. OFF ON or OFF OFF but the ADS is powered up then the on board 10MHz clock generator connected to EXTCLK MPC pin becomes the clock source Clkout is calculated by CLK_IN 10MHz multiplied by the PLL multiplication factor See TABLE 2 1 Power ON Reset DPLL Configuration on page 9 3e2e5 Software Options Switch SW5 The SW5 SOFTWARE OPTIONS switch is a 4 switch DIP switch The SW5 is connected over SWOPT 0 3 lines available at Software options may be manually selected according to the state of the SW5 30206 Power On RESET Switch SW6 The Power On RESET switch SW6 performs Power On reset to the MPC852T as if the power was re applied to the A Crystal resonator is not assembled on board 17 Release 1 0 For More Information On This Product Go to www freescale com Freescale Semiconductor 16 OPERATING INSTRUCTIONS ADS When the MPC is reset that way all configuration and all data residing in volatile memories are lost After PORST signal is negated the MPC re acquires the power on reset and hard reset configuration data from the hard reset configuration source Flash BCSR 30207 GND Bridges The 4 GND bridges on the MPC852TADS are intended to assist in general measurements and logic analyzer connec tions WARNING Use only INSULATED GND clips when connecting to a GND bridge Failure to do so may result in permanent damage to the MPC852TADS 3208 Ethernet 10Base T ETH TX RX LDI The gr
27. 0603 SMD RES T R DALE CRCW0603 3300F R11 R13 R17 R19 R21 R23 R25 R28 R31 0 ohm 1 0 1W 0603 SMD T R AVX CJ10 000 T R37 R38 R95 R96 R112 R116 R121 R123 R126 R127 R129 R133 R26 5 1K 5 1 4W 1206 SMD ROEDERSTEIN D25 05K1JCS R27 R36 R68 R120 1000hm 1 0603 SMD RES T R DALE CRCW0603 1000F 88 For More Information On This Product Go to www freescale com Release 1 0 Freescale Semiconductor 16 Support Information TABLE 5 16 MPC852TADS Part List Reference Designation Part Description Manufacturer Part R32 R35 R45 R46 R63 R65 R66 1K 1 0603 SMD T R DRALORIK D11 001KFCS R73 R85 R90 R98 R113 R131 R142 R149 R150 R152 R154 R160 R33 R83 2 21K 1 0603 SMD RES T R DALE CRCW0603 2211FRT1 R40 R44 R105 R110 R111 R162 R165 150ohm 1 0603 SMD RES T R DALE CRCW0603 1500F R167 R175 R47 510 1 0603 SMD RES T R DALE CRCW0603 5100F R50 R51 R77 R82 78 70hm 1 0603 SMD RES T R DALE CRCW0603 78R7F R53 R58 R88 R93 R122 49 9 OHM 1 SMD 0603 RES T R DALE CRCW0603 49R9F R56 R57 R60 R61 R80 R81 R86 R91 R92 75 ohm 1 0603 SMD T R DRALORIK D11 075RFCS R78 1 5K 1 0603 SMD RES T R DALE CRCW0603 1501F R114 143 OHM 1 1 8W 1206 ROEDERSTEIN D25 143RFCS R115 63 4ohm 1 0603 SMD RES T R DRALORIK D11 63R4FCS R166 51 1ohm 1 0 1W 0603 SMD T ROEDERSTEIN D11 51R1FCS SK1 SEP 1162 PIEZO SP
28. Freescale Semico Support Information FIGURE A 13 RS232 amp CLOCK n Zr jo er 00210 sun AEpUNS areg 8 2259 ev wiueumoog ez Sd v1zseodW u 0Z19r 19125 WIOHOLOW SIEUAS 28 7612 e 01010 eoei3 eua go pue 8025 2915 TOTO 9070 T T T Deve 9509 a eoinos y ST zoqez u p5 xoo o eui UT HI 2760 zqN9 434 HK OSAS A E Deu mmm vano 5 815 Jp mo ta 9 eio vno Zr 2X 195458 pro 9 VV RR Ewo lt Tenb su3Buel 3 deex 204 HOLVH3N39 3909 311016670 3110010675 ener mm NNOO GEESM semp semp semp semp sump semp 042 S uen ogzi S il 1E 911 ji IV O3LrZEXVIW ZX EOO9S OL p lb uuoO INS 12 zt ZNIdO INS LZLOVSLWTE v1 1105 LH ZNISLD INS IZLOVSLWIE 011 2H z 8 19 aACEC SH ety zezsu INS IZ LOV8LAT 911 INS 12 81 INS IZLOV8LATR i qui qut 120 220
29. MPC852TADS P16 Fe C d Parallel AC DC aralle Power Supply DC Input Debug con Converter Pott FIGURE 2 8 Host Controlled Operation on board Command Converter schem PC MPC852TADS P20 BOE ES D type25pin M Power Supply Input P Port mE SSS 20402 Standalone Operation In this mode the ADS is not controlled by the host via the debug port Rather connection to the host may be made via another port e g RS232 port Ethernet port etc Operations in this mode require that an application be programmed into the board s Flash memory No memory is required with host controlled operations Release 1 0 For More Information On This Product Go to www freescale com 12 Freescale Semiconductor 16 Hardware Preparation and Installation FIGURE 2 9 Standalone operation schem PC MPC852TADS P17 down AC DC P16 COM Power Supply W DC Input RS 232 1 EE pJ P9 Ethernet m E 2e4e3 10 100 Base T Ethernet Port
30. T I z Zr 9 Pg TOs EZ EN 55 UDSM 8180 WvuasHsvi4 ev my Niueumoog ezig Sa vizsgodW on 02199 e 399465 1 exueus piileeisp1ojonpuoomueg L01040 v lt gt eolaa O8WWIS 4 sel4 ld ooo 66 He Hsvi4 S56 SES seoa 700 d Yzd8 Bz 0599 in zeod SEO ospa 1209 dud 8208 32 8200 ash 20d st 20 8200 109 2 6208 31H szoa 400 Ad gg 0990 pi 2204 1 Q8 gr eo 69N foa oon LO sas da s keel 4300038 Liga zd 0200 SE ape umm C3 6100 14 i flog avsa za Bd sraa ans E q vSaa xa amp tioa PER 210 2100 2 0 88 010a tea H 600 2180 ug g 800 oloa m shag 600 pan sag ZON ESL orwnua g3 900 ION HA 5200 10 990 Fz Soa EM 5 d 50 HE goa XOL XOL 2 MOL MOL 290 M sync 2018 cod gt D 00 EN Ger sag 0 0 0 atz Py e sdy Toa r NHA ey PE HSV13 lv 2 sss 38 9 E EL ODA SDA gt f uid aW SVINHG dani anro aniod anro SOA end 2929 6929 8920 229 0229 5929 99291 1929 1 ddA umana 1 T z T 97 uctor ang Freescale Semico Support Information FIGURE A 7 PCMCIA I F 002 Sc Aen AepseupeM
31. 1 Encoding FLASH_PD 4 1 FLASH TYPE SIZE Reserved SM732A2000 SM73228 8 MB SIMM by SMART Modular Technologies SM732A1000A SM73218 4 MB SIMM by SMART Modular Technologies MCM29080 8 MB SIMM by Motorola MCM29040 4 MB SIMM by Motorola MCM29020 2 MB SIMM by Motorola Reserved TABLE 4 16 DRAM Presence Detect 2 1 Encoding DRAM PD 2 1 DRAM TYPE SIZE 00 MCM36100 by Motorola or MT8D132X by Micron 4 MB SIMM 01 MCM36800 by Motorola or MT16D832X by Micron 32 MB SIMM 10 MCM36400 by Motorola or MT8D432X by Micron 16 MB SIMM Release 1 0 For More Information On This Product Go to www freescale com Freescale 5emiconductor 1 Functional Description TABLE 4 16 DRAM Presence Detect 2 1 Encoding DRAM_PD 2 1 DRAM SIZE 11 MCM36200 by Motorola or MT16D832X by Micron 8 MB SIMM TABLE 4 17 DRAM Presence Detect 4 3 Encoding DRAM_PD 4 3 DRAM DELAY 00 Reserved 01 Reserved 10 70 nsec 11 60 nsec WARNING SWOPT 0 3 lines may be driven low 0 by the DIP switch Off board tools should never drive lines high as this may result in permanent damage to the ADS and or to the off board logic 4e led BCSR3 Board Control Status Register 3 BCSR3 is an additional BCSR that may be accessed at offset OxC from the BCSR base address BCSR3 sets defaults
32. Card Detect 2 buffered A6 BCD1b Input Port A 4 Card Detect 1 buffered A7 BBVD2 Input Port 5 Battery Voltage Detect 2 buffered A8 BBVD1 Input Port 6 Battery Voltage Detect 1 buffered A9 BRDY Input Port 7 Ready Busy buffered A10 GND GND 11 RESETA Output Port 0 Card Reset 12 GND GND A13 N C A14 BWEOb O MPC852T WEO Pin used for external peripheral A15 BDRMWb O MPC852T GPLO Signal used for DRAM write signal A16 BEDOOEb MPC852T GPL1 Pin used for DRAM oe signal 17 BGPL2b MPC852T GPL2 Pin buffered 18 BGPL3b MPC852T GPL3 Pin buffered 19 BGPL4Ab MPC852T GPL4A Pin buffered A20 N C A21 BGPL5Ab MPC852T GPL5A Pin buffered A22 BGPL5Bb MPC852T GPL5B Pin buffered A23 GND A24 BSYSCLK3 852 CLKOUT Pin driven by zero delay buffer A25 GND GND A26 BBSAO0b MPC852T BSOb Pin buffered A27 GND GND A28 BRW2b MPC852T RWb Pin buffered A29 BTSb 852 TSb Pin buffered 67 Release 1 0 For More Information On This Product Go to www freescale com Freescale Semiconductor INE Support Information TABLE 5 1 P1 ADD Data and PCMCIA Expansion Connector Interconnect Signals Pin No Signal Name Attribute Description A30 TAb MPC852T TA Pin A31 BCS7b 852 CS7 Pin buffered A32 BCS6b 852 56 Pin buffered B1 3 3V Power 3 3V B2 3 3V Power 3 3V B3 3 3V Power 3 3V B4 3 3V
33. Connector VFLSO GND GND HRESET VDD 4e 3e Standard MPC852T Debug Port Connector Pin Description The standard debug port connector pins are needed to support debug port controllers for MPC852TADS 4e 3ele VFLS 0 1 These pins indicate to the debug port controller whether or not the MPC is in debug mode When both VFLS 0 1 are I the MPC is in debug mode As these lines may serve varying functions for MPC the FRZ must be selected on either the ADS or target system 4e13e1e2 HRESET This is the MPC s Hard Reset bidirectional signal When asserted low the MPC enters a Hard Reset sequence that includes Hard Reset configuration The signal is made redundant with the MPC852T debug port controller as there is a Hard Reset command integrated into the debug port protocol However for compatibility with existing MPC5XX boards and software the local debug port controller uses this signal 4e 3e e3 SRESET This is the MPC852T s Soft Reset bidirectional signal whereas on the MPC5XX it is an output The debug port con figuration is sampled and determined on the rising edge of SRESET for both processor families On the MPC852T this bidirectional signal may be driven externally to generate a Soft Reset sequence Regarding the MPC852T debug port controller the signal is redundant as there is a Soft Reset command integrated into the debug port protocol However for compatibility with existing MPC5XX boards and software th
34. Ethernet port transceiver Davicom DM9161E is active Je2e 6 5232 2 ON LD9 The yellow RS232 Port 1 ON LED signifies that the RS232 transceiver connected to SCC3 is active and that com munication via that medium is allowed The RS232 transceiver is in shutdown mode when unlit an indication that the associated MPC pins may be used off board via the expansion connectors 3e2e17 Fast Ethernet 10 100Base T ON LD10 The yellow FAST ETH ON LED indicates that the Fast Ethernet port transceiver Davicom DM9161E is active The Davicom outputs pins are in tri states when unlit an indication that the associated Port D pins may be used off board via the expansion connectors 3Je2e 8 RS232 Port 1 ON LD12 The yellow RS232 Port 1 ON LED signifies that the RS232 transceiver connected to SMC1 is active and that com munication via that medium is allowed The RS232 transceiver is in shutdown mode when unlit an indication that the associated MPC pins may be used off board via the expansion connectors 302019 PCMCIA ON LDI3 The yellow PCMCIA ON LED indicates the following 1 Address amp strobe buffers are driven towards the PCMCIA card 2 Data buffers are driven to from the PCMCIA card whenever CE1A or CE2A signals are asserted 3 Card status lines are driven towards the MPC from the PCMCIA card When unlit it indicates that the above noted buffers are tri stated and that the pins associated with the PCMCIA channel A ma
35. MPC852T PAO Pin 17 VCC VCC A18 RSRXD2 MPC852T PA11 Pin used on the board as RS232_2 RXD signal A19 RSTXD2 y o MPC852T PA10 Pin used on the board as RS232 2 TXD signal A20 ETHRXD MPC852T PA9 Pin used on the board as 10Base T Ethernet port receive data A21 ETHTXD y o MPC852T PA8 Pin used on the board as 10Base T Ethernet port transmit data A22 GND GND A23 GND GND A24 N C A25 FRZ MPC852T FRZ pin A26 N C A27 IRQ3b LL MPC852T IRQ3 Pin 71 Release 1 0 For More Information On This Product Go to www freescale com Freescale Semiconductor INE Support Information TABLE 5 2 P2 I O Port Expansion Interconnect Signals Pin No Signal Name Attribute Description A28 IRQ2b LL MPC852T IRQ2 Pin A29 IRQ1b LL MPC852T IRQ1 Pin A30 NMIb LL MPC852T NMI Pin A31 nRSEN1 O L RS232 _1 Enable A32 GND GND B1 PB31 MPC852T PB31 Pin B2 PB30 MPC852T PB30 Pin B3 PB29 MPC852T 29 Pin B4 PB28 MPC852T 28 Pin B5 N C B6 N C B7 RSTXD1 MPC852T PB25 Pin used on the board as 5232 1 TXD signal B8 RSRXD1 MPC852T 24 Pin used on the board as 5232 1 RXD signal B9 N C B10 N C B11 N C B12 N C B13 N C B14 N C B15 N C B16 N C B17 PB15 MPC852T 15 Pin B18 N C B19 GND GND B20 BINPACKb MPC8
36. POWER CONTROL Power Logic From BGSSR v LTC1315 or equivalent D 8 15 Data_A 15 8 Data A 7 0 From BCSR PCMCIA EN CE1 CE2 WE PGM WE PGM OE OE IORD IOWR IORD IOWR MPC852T RESET_A B RESET Buffer with OE POE_A B Transparent Latch with OE A 6 31 Address A 25 0 REG REG WAIT A B 101516 A B A B BVD 1 2 A B CD 1 2 _A B VS 1 2 _A B SPKROUT gt LPF Release 1 0 For More Information On This Product Go to www freescale com Freescale 5emiconductor INE Functional Description 491091 PCMCIA Power Control In order to support hot insertion socket power is controlled via LINEAR TECHNOLOGY s LTC1315 dedicated PCMCIA power controller The LTC1315 through which the PC Card VCC is switched switches 12V VPP s for the purpose of card programming as well as gate control of external MOSFET transistors The LTC1315 is controlled by BCSRI If for example a PC Card is inserted while the PCMCIA channel is enabled via BCSR1 then both of the CD 1 2 Card Detect lines are asserted low Thereafter read the voltage select lines VS 1 2 status to determine the PC Card s operation voltage level accordingly to which PCCVCC 0 1 bits in BCSR1 should be set in order to drive the correct VCC 5V to the PC Card If a PC Card is removed from the socket while the channel is enabl
37. PTA formula calculation Refresh Period X Number Of Beats Per Refresh Cycle Number Of Rows To Refresh X T BRG X MPTPR X Number Of Banks PTA Where PTA Periodic Timer A filed in MAMR The value of the second divider Refresh Period time usually in msec required to refresh a DRAM bank Number Of Beats Per Refresh Cycle using UPM looping capability more than one refresh cycle per refresh burst up to 16 may be performed Number_Of_Rows_To_Refresh number of rows in a DRAM bank T_BRG cycle time of the BRG clock MPTPR value of the PTP or Periodic Timer Prescaler 2 to 64 Number_Of_Banks number of DRAM banks to refresh As an example a MCM36200 SIMM has the following data Refresh_Period 16 msec Number Of Beats Per Refresh Cycle 4 on the ADS Number_Of_Rows_To_Refresh 1024 T_BRG 20 nsec system clock 50 Mhz MPTPR arbitrarily chosen to 16 Number_Of_Banks 2 for that SIMM If these figures are assigned to the PTA formula then the PTA value should be 97 decimal or 61 hex 4 4 Variable Bus Width Control Port width determines address line connection schemes The number of address lines required for byte selection varies according to port width 1 for 16 bit port and 2 for 32 bit port thus address connections to a memory port must be changed if the width is changed For example a memory initially configured as a 32 bit port will have a list s
38. TON ey 28 tah INST ZISV8LIWTS SZT 4 aa ov 28 3 Scoto ta Y EE q dd j NS IZIOVETWIR SZT 280 019 Y ev eg 4 xii sq 670190 tolv zv za INS EVANTA DET 180 zn Secolo 8 goriv Gay dd dd 8 Y ig oara INS IZISV8IWT SVET zm 11019 8 4 im a ls Ns wu T ud e iolo v L SESESRERSE er 7 siola 75 iem E oven lt lt 919 into n m rmm HILL H199 NI Sg Te SIYSG SS SLO FTT 8 1019 0 Heg anes 09 ve BPR YIO por m emn VIT ens uL L em dues Edl srole a 000 zs est INS 12 VSL TA 01 0 0191V82LEWd3 Lvdl sels enea DOA Qu 1SV 4 INSE ZLOVBLWTEN amp 7 71 rtosmsoNi 0 INS d8 193005 SI 8 X10 dd3 i 9 IS dA lt lt 55555565 o T EJ 655555 0145993 s 20 2 20 0820 1920 3 9898959 a His m Po easen n 1 993 P antoj enea enea 197 2 1 e c BEL ex nro anro an m ano enm ire Da r l 3a3nro aanro dnio a E Ae Me ie k M NEA vvzo eezo L220 ezzo vezo eezo pres iva T E N l mm f oy ly Ensa erd a r ast et 301 daz T T z D T T s Release 1 0 For More Information On This Product Go to ww
39. Trademarks This document includes these trademarks Motorola and the Motorola logo are registered trademarks of Motorola Inc Windows is a registered trademark of Microsoft Corporation in the U S and other countries Intel is a registered trademark of Intel Corporation Motorola Inc is an Equal Opportunity Affirmative Action Employer For an electronic copy of this book visit Motorola s web site at http e www motorola com Motorola Inc 2002 All Rights Reserved MPC852TADS Version 1 0 User s Manual MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Hardware Preparation lel Jumpers and Dip Switches Ensure the following jumpers are in place TABLE 1 1 Default Jumpers and dip switches settings Reference Name Description Default J1 Clock Oscillator source 1 2 10MHz on board 1 2 10MHz on board clock oscillator clock oscillator 2 3 External clock oscillator SW1 Power Switch ON OFF Power Switch OFF Sw4 Modin Selector Modin 1 2 Modin 1 2 OFF ON OFF ON 1 0 SW5 S W Options 4 1 S W Option 4 1 ON ON ON ON ON ON ON ON 0000 1 2 Connections Connect the following connectors P16 Power Supply 5 0V DC Power Supply 12 0V DC for PCMCIA channel or for Flash Programming P12 Connector via External Command Converter to Hos
40. UPM 0 8 18 20 30 3C Contents 0 8FFFCCO4 8FFFCC04 8FEFCCOO 8FEFCCOO 80FFCC84 S3FFCCO7 ae 1 O8FFCCOO O8FFCC08 39BFCC47 O9AFCC48 17FFCC04 X 2 S3FFCC47 08FFCCO8 X O9AFCC48 FFFFCC86 X 3 X O8FFCC08 X O9AFCC48 FFFFCCO5 X 4 X 08FFCCOO X 39BFCC47 X 5 X 3FFFCC47 X X X 6 X X X X X 7 X X X X X 8 X X X 9 X X X A X X X B X X X C X X D X X E X X F X X 31 Release 1 0 For More Information On This Product Go to www freescale com Freescale Semiconductor 16 OPERATING INSTRUCTIONS TABLE 3 9 UPMB Initialization for KS643232C TC60 upto 32MHz Cycle Type Single Read Burst Read Single Write Burst Write Refresh Exceptions Offset In 0 8 18 20 30 3C Contents 0 0126CC04 0026FC04 OE26BC04 0E26BC00 1FF5FC84 7FFFFCO7 eae 1 OFB98C00 10ADFCOO 01B93C00 10AD7C00 FFFFFC04 X 2 1FF74C45 FOAFFCOO 1FF77C45 FOAFFCOO FFFFFC84 X F1AFFCOO X FOAFFCOO FFFFFCO05 X 4 X EFBBBCOO X E1BBBC04 X 5 1FE77C34 1FF77C45 X 1FF77C45 X 6 EFAABC34 X X X X 7 1FA57C35 X X X X 8 X X X 9 X X X A X X X B X X X C X X D X X E X X F X X a MRS initialization uses free space 32 Release 1 0 For More Information On This Product Go to www freescale com Freescale Semiconductor 16 OPERATING INSTRUCTIONS TABLE 3 10 UPMB Initialization for KS643232C TC60 32 MHz 50MHz
41. axa i A 994 96 NNOO 96 NNOO 96 NNOO N N o Her o 8 digas Stew z ot Bey asia eH olg 62 dX3 LA 627 1 6 dX 2E Sti 1 E Sev dX3 STsev l govsaa e T ses T SZV d SC 529 tev dX3 exTosAsa of 1 SEP Hay rpzze OATF NS of ev ES 5 58 of 8 amr 5 YAZ H pupe 05 o Sea SA e 961498 o f 34 off caw dX ZAZ W gwos 917 Qv dX3 Kad ns of 318 suom 043 SIY d STW 518 S 8lv dX3 Comsat SH f o1 oO dX ots of sis TOON of dX3 Uy vaasa i m m avizog of ev Zvdr ofeg pee rd Longa o L38 ole sais SVdl 9v 9 098 E SIS T T bela W PE VS SEV Wal 5 Fs Q8 dX fey Wa ISAE anto Janto Janto Tanto IVLIVM8 008 dX3 ged 9 zso V V 2 Vid ald ENSA Old 4 I ENEA Oras dxa Fan Pac 96 NNOO 96 NNOO 96 NNOO ch cs oz otze t ro saa e teg Suoui3 Her td 230 Oey NUN So 293 tH 410 20950 9002 ave saz op x bev 529 99d Bev azul ops Zod Nid dA 282 227 0 29 Pe xii 59 sve 2 saz o 92v of 01999 pve vac C OTSN 23 99287 91520 Sieve sac TOV vee
42. enough to cover also for the stabilization of the VDDL power buses of the MPC852T powered by different voltage regulators It is assumed that the stabilization time for all linear regulators see also 4 14 Power on page 63 is about the same Power On Reset may be generated manually as well by a dedicated push button SW6 4 1 2 Manual Soft Reset A Soft Reset button has been provided in order to support application development in areas other than around the debug port and resident debuggers Pressing the SW3 button asserts the SRESET pin of the MPC and generates a Soft Reset sequence When SRESET is asserted to the MPC then the debug port controller makes a Soft Reset configuration available to the MPC See 4 1 6 3 Soft Reset Configuration 4e e3 Manual Hard Reset A Hard Reset button has been provided in order to support application development in areas other than around the debug port Pressing the SW3 Soft Reset button in conjunction with the SW2 ABORT button asserts the HRESET line thus generating a HARD RESET sequence In order to economize on board space the button sharing was devel oped However this does not in any way effect functionality When HRESET is asserted to the MPC then a Hard Reset configuration via BCSRO is made available See 4 1 6 2 Hard Reset Configuration and TABLE 4 10 BCSRO Description 4e ed Host Hard Reset through on board command converter Hardware Reset through on board Command Converte
43. is located at OXFF000000 6 Debug Pin Configuration PCMCIA port BP pins become PCMCIA port B pins A Debug Port Soft Hard Resets are part of the development system and therefore bear mentioning B In the 1 6 5 PLL operation the HRESET line drives the MODCK lines longer C With respect to the ADS s power on defaults 35 Release 1 0 For More Information On This Product Go to www freescale com Freescale 5emiconductor 1 Functional Description 7 Debug Port Pin Configuration Debug port pins are located on the JTAG port 8 External Bus Division Factor internal to external clock frequencies are selected at a ratio of 1 1 4e e e3 Soft Reset Configuration The SRESET rising edge is used to configure the development port Prior to the negation of SRESET the DSCK is sampled in order to determine the debug mode enable disable After SRESET negation in the instance that the debug mode was enabled DSCK is again sampled for debug mode entry non entry DSDI is used to determine the debug port clock mode DSDI is sampled after the negation of SRESET The debug port controller via on board command converter provides the Soft Reset configuration Option exists for entering the debug mode directly 4e2 Local Interrupter Generated by a button the ABORT NMI is the only external interrupt applied to the MPC via its interrupt controller When pressed NMI input to the MPC is asserted This interrupt type is meant t
44. multiplication factor See TABLE 2 1 Power ON Reset DPLL Configuration on page 9 NOTE Crystal resonator circuit is not assembled on board Release 1 0 For More Information On This Product Go to www freescale com Freescale Semiconductor 16 Hardware Preparation and Installation FIGURE 2 5 Modin Selection SW4 10MHz Clock generator 10MHz Clock generator 10MHz Crystal Oscillator 10MHz Crystal Oscillator TABLE 2 1 Power ON Reset DPLL Configuration MODCK 1 2 pn In E System Frequency MFI 12 15 PDF 27 30 00 8 0000 OSCM Freq 40MHz for 10MHz input Crystal 01 15 0000 OSCM Freq 75MHz for 10MHz input Crystal 10 8 0011 EXTCLK Freq 1 1 11 15 0000 EXTCLK Freq 75MHz for 10MHz input Clock Oscillator a OSCM Freq means the Frequency between EXTAL and XTAL MPC pins b If Clock in is 1OMHz Clock Oscillator the System Frequency is 10MHz 2 3 4 Software Option SWS SWS is a 4 Dip Switch This switch is connected over SWOPT 0 3 lines which are available at BCSR2 S W Options may be manually selected according to SW5 state SW5 is factory set to al ON Release 1 0 For More Information On This Product Go to www freescale com Freescale Semiconductor 16 Hardware Preparation and Installation FIGURE 2 6 S W Option SW5 SW3 SW2 SWI SWO SW5
45. or 30 or 60 Periodic 30B21114 timer enabled Type 3 address multiplexing scheme 2 60B21114 cycle disable timer GPL4 disabled for data sampling edge flexibility 1 loop read 1 loop write 4 beats refresh burst MBMR KS643232C TC60 D0802114 Refresh clock divided by DO or 80 Periodic timer 808021149 enabled 0 address multiplexing scheme 2 cycle disable timer GPL4 enabled 1 loop read 1 loop write 4 beats refresh burst a Assuming 16 67 MHz b Assuming 25MHz BRGCLK c For 66MHz BRGCLK d Assuming 32MHz BRGCLK 27 Release 1 0 For More Information On This Product Go to www freescale com TABLE 3 6 UPMA Initialization for 0 DRAMs 66MHz Freescale Semiconductor 16 OPERATING INSTRUCTIONS For More Information On This Product Go to www freescale com Cycle Type Single Read Burst Read Single Write Burst Write Refresh Exceptions Offset in UPM 0 8 18 20 30 3C Contents 0 FFFFCC24 FFFFCC24 FFFFCC24 FFFFCC24 EOFFCC84 33FFCCO7 iei 1 OFFFCC24 OFFFCC24 OFAFCC24 OFAFCC24 OOFFCC04 FFFFFFFF 2 OFFFCC04 OFFFCC04 OFAFCC04 OFAFCC04 OOFFCC04 FFFFFFFF 3 OCFFCCO4 08FFCCO4 08AFCCO4 08AFCCOO OFFFCC04 FFFFFFFF 4 OOFFCC04 OOFFCC04 OOAFCCOO0 07AFCC4C 7FFFCC04 5 OOFFCCOO OOFFCC08 37FFCC47 08AFCCOO FFFFCC86 6 37FFCC47 OCFFCC44 FFFFFFFF 07AFCC4C FFFFCCO5 7 FFFFFFFF OOFFECOC FFFFFFFF
46. ss d d sso eso 99 85 k 2 5 He 5 B TOWLNOD 8 3x 50 283 255 L z c v g oOo 5 3 o9 ig zi a o 2m 8 le es 2 NO lo 2 e 1 RAS L Ne s i c GN e El rO o 7 983 i a 923 s ee H 8 r A g daH t e i Ad apii S 212 2 seo 69 269 ESO At a 5 A es L TTD 612 273 BED 27 257 TAS 5 R O19 812 929 262 102 S2 IS 190 S99 499 699 dz O LII ao L E M I e99 677 SES SED 03 Hd 882 87 53 5905 z c 8 v 13539 z IN 85 Eld 91 1udau 135395 5 5 ens EMS aS a a d t 28 mo g 5 1 a sA s O A ll n aT HSU14 4 3 For More Information On This Product Go to www freescale com Release 1 0 FIGURE 2 2 MPC852TADS Bottom Freescale Semiconductor 16 Hardware Preparation and Installation de Part Location Diagram
47. steps listed in 4 6 1 DRAM 16 Bit Operation on page 38 are taken the DRAM is 16 bit wide When inactive the DRAM is 32 bit wide R W 13 RS232EN_2 RS232 Port 2 Enable When asserted low the RS232 Port 2 transceiver is enabled When negated the transceiver enters standby mode and the relevant MPC Communication Port pins become available for off board use via the expansion connectors RW 14 SDRAMEN SDRAM Enable When active high the SDRAM module is enabled on the local memory map When inactive the SDRAM is placed in low power mode RW 54 Release 1 0 For More Information On This Product Go to www freescale com Freescale Semiconductor 1 Functional Description TABLE 4 11 BCSR1 Description PON BIT MNEMONIC Function DEF ATT 15 PCCVCC1 Pe Card VCC Select 1 These signals in conjunction with PCCVCCO 1 R W determine the voltage applied to the PCMCIA card s VCC Possible values are 0 3 3 5 V For line encoding and associated voltages see TABLE 4 12 PCCVCC 0 1 Encoding on page 55 16 31 Reserved Not implemented a Configuration data is handled in this manner provided that the MPC supports the option by driving address lines low and asserting CSO during Hard Reset TABLE 4 12 PCCVCC 0 1 Encoding PCcCVCC 0 1 P vee 00 0 01 5 10 3 3 11 0 TABLE 4 13 PCCVPP 0 1 Encoding
48. that provide In System Programming capability for the board s Altera made programmable logic U8 BCSR and U17 BDM to EPP I F respectively The pinout is shown 85 Release 1 0 For More Information On This Product Go to www freescale com Freescale Semiconductor 16 Support Information in TABLE 5 15 P18 P19 JTAG connector for Altera programing below TABLE 5 15 P18 P19 JTAG connector for Altera programing Pin No Pin Name Attribute Description 1 TCK I Test Port Clock The clock shifts data in out and to from the programmable logic JTAG chain 2 GND Digital GND Main GND plane 3 TDO Transmit Data Output The programmable logic JTAG serial data output is driven by the TCK s falling edge 4 V3U3 3 3V Power Supply Bus 5 TMS I Test Mode Select The signal qualified with TCK changes the state of the programmable logic JTAG machine 6 N C Not connected 7 N C Not connected 8 N C Not connected 9 TDI I Transmit Data In The programmable logic JTAG serial data input 10 GND Digital GND Main GND plane Se e P20 Parallel Host Port Connector The Parallel Host port connector P20 is a D Type 25 pins male connector It should be connected to IEEE 1284 1994 cable For Serial transfer mode the signals are presented in TABLE 4 22 Parallel Host Port Connector s Signal Description with Serial Command Converter I F below For EPP transfer mode th
49. the use of between 14 to 18 AWG wires is recommended 2 4 6 5V Power Supply Connection P16 The MPC852TADS requires a 5 VDC 3A max power supply for operation Connect the 5V power supply to connector P16 as shown below FIGURE 2 12 P16 5V Power Connector P16 Terminal B _ Terminal P16 is a power jack connector NOTE Hardware applications may be connected to the MPC852TADS via expansion connectors amp P2 Power consumption should be considered when a power supply is connected to the MPC852TADS Thus when adding HW to the expansion connectors note that the new addition will not consume more power than 1A 20407 Terminal to MPC852TADS RS 232 Connection P17 RS232 equipment and serial RS232 terminals may be connected to P17A and P17B RS 232 connectors The RS 232 shown in FIGURE 2 13 RS 232 Serial Port Connectors P17A amp P17B is a female 9 pin stacked D type connector The connectors are arranged in a manner that allows for a 1 1 connection via a flat cable to the serial port of an a personal computer Release 1 0 For More Information On This Product Go to www freescale com Freescale Semiconductor INE a Hardware Preparation and Installation FIGURE 2 13 RS 232 Serial Port Connectors P17A amp P17B li TX x DSR 7 RTS Rx Crs DTR O9 NC GND 50 Note On the MPC852TADS the RTS line pin 7 is not conne
50. via MIIRXEN bit in BCSR4 The DM9161E is able to interrupt the MPC via IRQ6 line 4 9 3 1 DM9161E Control The DM9161E is controlled via 2 wire interface a clock MDC and a bidirectional data line MDIO This is in fact a bus i e up to 32 devices may reside over it while the protocol defines a 5 bit slave address field which is compared against the slave address set to each device by hardware during device reset according to the levels on some pins On the board the slave address is hard set to b00000 for Fast Ethernet and b00011 for Ethernet The MPC interfaces this port using two PI O pins MII MDIO for MDIO and PD12 MIIMDC for MDC There is no special support within the MPC for the MDIO port and the protocol is implemented in S W The MDIO port may interrupt a host in 2 ways a driving low the MDIO line during IDLE time or b using a ded icated interrupt line MDINT This line is connected to the MPC s IRQ6 line in Fast Ethernet I F and IRQ3 line in Ethernet I F appearing also at the expansion connectors 4 10 PCMCIA Port To enhance PCMCIA I F development the ADS has a dedicated PCMCIA port Support is only provided to 5V PC Cards that are PCMCIA standard 2 1 compliant The MPC generates all necessary control signals To both protect MPC signals from external hazards and to provide sufficient drive capability a set of buffers and latches is provided over the PC Card address data and strobe lines To conform with the A
51. www freescale com Freescale 5emiconductor 16 Support Information 5e e7 P14 BNC Connector P14 is a BNC connector that drives the clock into the MPC EXTCLK pin Users may use this connector but only after connecting J1 pins 2 3 J1 Pins 1 2 are connected by default in the factory Seles P16 2 1 mm Power Jack 5V Connector P16 is a 2 1 mm Plug Jack connector connected to the board s power supply To operate the board users must plug the 5V power supply s connector into the P16 connector 5 9 P17 5232 Dual Port Connector P17A 1 down and P17B 2 up connectors are female 9 pin 90 D type stacked connectors The connector signals are outlined TABLE 5 14 P17B RS232 Interconnect Signals below Note output indicates data leaving the MPC852TADS whereas input indicates data entering the MPC852TADS TABLE 5 14 P17B RS232 Interconnect Signals Pin No Signal Name Description 1 CD MPC852TADS Carrier Detect output 2 TX MPC852TADS Transmit Data output 3 RX MPC852TADS Receive Data input 4 DTR MPC852TADS Data Terminal Ready input 5 GND MPC852TADS Ground Signal 6 DSR MPC852TADS Data Set Ready output 7 RTS N C Request To Send not connected in the MPC852TADS 8 CTS MPC852TADS Clear To Send output 9 Not connected In P17A only RX and TX signals are existed Sele 0 8 P19 Altera programming ISP Connectors P18 P19 are 10 pin generic 0 100 pitch header connector
52. 0 For More Information On This Product Go to www freescale com Freescale 5emiconductor 16 Support Information 10Base T Ethernet Port Interconnect Signals below Note output indicates data leaving the MPC852TADS whereas input indicates data entering the MPC852TADS TABLE 5 11 P9 P10 100 10Base T Ethernet Port Interconnect Signals Pin No Signal Name Description 1 TPTX MPC852TADS Twisted Pair Transmit Data positive output 2 TPTX MPC852TADS Twisted Pair Transmit Data negative output 3 TPRX MPC852TADS Twisted Pair Receive Data positive input 4 Not connected 5 i Not connected 6 TPRX MPC852TADS Twisted Pair Receive Data negative input 7 Not connected 8 Not connected Se e5 P12 External Debug Port Controller Input Interconnect P12 is a male 10 pin header connector The connector signals are outlined in TABLE 5 12 P12 External Debug 83 Release 1 0 For More Information On This Product Go to www freescale com Freescale Semiconductor INE Support Information Port Controller Input Interconnect Signals below TABLE 5 12 P12 External Debug Port Controller Input Interconnect Signals Pin No Signal Name Attribute Description 1 VFLSO Visible History Flushes Status 0 Indicates with VFLS1 the number of instructions flushed from the core s history buffer and if the MPC is in debug mode If debug port n
53. 0 Freescale Semiconductor Inc 77 Freescale Semiconductor INE a Support Information TABLE 5 6 P7 Logic Analyzer Interconnect Signals MPC852T Pin Signal Name 14 DP1 16 DP2 18 DP3 20 FRZ 22 SPKROUT 24 BVS1 24 BVS2 28 BWP 30 BCD2b 32 BCDib 34 BBVD2 36 BBVD1 38 BRDY TABLE 5 7 P8 Logic Analyzer Interconnect Signals Pin MPC852T Signal Name N C N C Oo N MIITXCLK MPCMDIO 10 MIICRS 12 MIITXEN 14 MIICOL 16 N C 18 N C 20 N C 22 N C For More Information On This Product Go to www freescale com Release 1 0 Freescale Semiconductor Inc 78 Freescale Semiconductor INE Support Information TABLE 5 7 P8 Logic Analyzer Interconnect Signals MPC852T Pin Signal Name 24 RSRXD1 26 RSTXD1 28 N C 30 N C 32 PB28 34 PB29 36 PB30 38 PB31 TABLE 5 8 P11 Logic Analyzer Interconnect Signals MPC852T Pin Signal Name 2 N C 4 N C 6 TSIZ1 8 D16 10 D17 12 D18 14 D19 16 D20 18 D21 20 D22 22 D23 24 D24 26 D25 28 D26 30 D27 32 D28 34 D29 36 D30 For More Information On This P
54. 08AFCCOO FFFFFFFF 8 O3FFECOO O7AFCC4C FFFFFFFF 9 OOFFEC44 O8AFCCOO FFFFFFFF A 00FFCC08 37AFCC47 FFFFFFFF B OCFFCC44 FFFFFFFF FFFFFFFF OOFFEC04 FFFFFFFF D O0FFECOO FFFFFFFF E 3FFFEC47 FFFFFFFF F FFFFFFFF FFFFFFFF 28 Release 1 0 Freescale Semiconductor 16 OPERATING INSTRUCTIONS TABLE 3 7 Memory Controller Initialization For 20Mhz Register Device Type Init Value hex Description BRO All Flash SIMMs 02800001 Base at 2800000 32 bit port size no parity GPCM supported ORO MCM29F020 90 FFEO0D20 2MB block size all types access CS early negate 2 W S MCM29F040 90 FFCOOD20 4MB block size all types access CS early negate 2 SM732A1000A 9 W S MCM29F080 90 FF800920 8MB block size all types access CS early negate 2 SM732A2000 9 W S timing relax MCM29F020 12 FFEO0D30 2MB block size all types access CS early negate w s MCM29F040 12 FFCOOD30 4MB block size all types access CS early negate SM732A1000A 12 w s MCM29F080 12 FF800930 8MB block size all types access CS early negate SM732A2000 12 3 w s BR1 BCSR 02100001 Base at 2100000 32 bit port size no parity GPCM OR1 FFFF8110 32 KB block size all types access CS early negate 1 W S BR2 All Dram SIMMs 00000081 Base at 0 32 bit port size no parity UPMA supported OR2 MB321 2BTO8TASN60 FFC00800 4MB block size all types access initial address multiplexing according to AMA
55. 10 velo 40 28 NOHSV gt 009AV 19900d ES DONDE ki xi 4 5922 009A9d Y 4 1noddAv 3 599 2288 5 A beh beh beh 99 loH Q O0 2 6 J j T i j Tar za Tar var sys semp sep z 5 ineo 100 zequg ELYZIONSL L 9619 k ig ed 09 Hg z 6 05 LONS Th SojoH Sununo lt aan da E sen p ant o o au 33770 Oq AS 51 gvl 2 299 p d T GNO T T t me b amt AD 7 T anor snp orzo 1820 E 005 62O9IN k L aot 3100 a o 190 z9qugW 1080 51 989 6820 svzo 2220 6a za 005 6ZOIN 230 O S2N vin o9zaws TNI UT no 92 20 L 0LLLWOV ed Enea IMS 434O0 NO WuMod Release 1 0 For More Information On This Product Go to www freescale com 100 Freescale semiconductor WF nual Support Information FIGURE A 10 Fast Ethernet amp Ethernet L
56. 142 Refresh clock divided by 40 or 600 or CO Periodic 60A21114 timer enabled Type 2 address multiplexing scheme 2 C0A21114 cycle disable timer GPL4 disabled for data sampling edge flexibility 1 loop read 1 loop write 4 beats refresh burst MB322BT08TASN60 20A211142 Refresh clock divided by 20 or 30 or 60 Periodic 30A21114 timer enabled Type 2 address multiplexing scheme 2 60A21114 cycle disable timer GPL4 disabled for data sampling edge flexibility 1 loop read 1 loop write 4 beats refresh burst MB324CTOOTBSN60 408211142 Refresh clock divided by 408 or 60 or CO Periodic 60B21114 timer enabled Type 3 address multiplexing scheme 2 COB21114 cycle disable timer GPL4 disabled for data sampling edge flexibility 1 loop read 1 loop write 4 beats refresh burst MB328CTOOTBSN60 208211142 Refresh clock divided by 208 or 30 or 60 Periodic 30B21114 timer enabled Type 3 address multiplexing scheme 2 60B21114 cycle disable timer GPL4 disabled for data sampling edge flexibility 1 loop read 1 loop write 4 beats refresh burst MBMR KS643232C TC60 D0802114 Refresh clock divided by DO or 80 Periodic timer 808021149 enabled 0 address multiplexing scheme 2 cycle disable timer GPL4enabled 1 loop read 1 loop write 4 beats refresh burst a Assuming 16 67 MHz b Assuming 25MHz BRGCLK c For 66MHz BRGCLK d Assuming 32MHz BRGCLK 25 Release 1 0 For More Information On
57. 2 4 2 2 2 Burst Write 4 2 2 2 4 2 2 2 3 1 2 2 3 2 2 2 Refresh 212P 258b 437 LE 5 Four beat refresh burst b Doesn t include arbitration overhead TABLE 4 3 EDO DRAM Performance Figures Number of System Clock Cycles System Clock Frequency MHz 50 25 DRAM Delay nsec 60 70 60 70 Single Read 6 6 3 4 Single Write 4 4 2 3 Burst Read 6 2 2 2 6 3 2 2 3 1 1 1 4 1 2 2 Burst Write 4 2 2 2 4 2 2 2 2 1 1 1 3 2 2 2 Refresh 212P 258b 133b 132P a Four beat refresh burst b Doesn t include arbitration overhead 40603 Refresh Control Prior to a RAS refresh the DRAM refresh is CAS The refresh is controlled by UPMA Refresh logic is clocked by the MPC s BRG clock The latter is not influenced by the MPC s low power divider 39 Release 1 0 For More Information On This Product Go to www freescale com Freescale 5emiconductor 16 Functional Description FIGURE 4 1 Refresh Scheme BRG Clock gt j DRAM BANKS As seen in FIGURE 4 1 above the BRG clock is divided twice Once by the PTP Periodic Timer Prescaler and thereafter by another prescaler the PTA Periodic Timer A with its dedicated UPM When there is more than one DRAM bank then refresh cycles are performed for consecutive banks resulting in faster refreshes Below is the
58. 52T 15 pin used as INPACK for B21 N C B22 nRSRTS2 MPC852T PC13 Pin used as 5232 2 RTS signal B23 ETHTXEN MPC852T 12 Pin used as 10Base T Ethernet port TENA signal B24 N C B25 N C B26 N C 72 Release 1 0 For More Information On This Product Go to www freescale com Freescale Semiconductor INE Support Information TABLE 5 2 P2 I O Port Expansion Interconnect Signals Pin No Signal Name Attribute Description B27 N C B28 nRSCTS2 852 PC7 Pin used as RS232_2 CTS signal B29 nRSCD2 MPC852T PC6 Pin used as RS232_2 CD signal B30 ETHCOL MPC852T 5 Pin used as 10Base T Ethernet port Collision signal B31 ETHCRS MPC852T PC4 Pin used as 10Base T Ethernet port CRS signal B32 GND GND C1 VCC VCC C2 C3 C4 C5 C6 nRSEN2 O L BCSR RS232 _2 Enable C7 GND GND C8 C9 C10 C11 C12 C13 C14 C15 MIIRXD3 y o MPC852T PD15 Pin used on the board as MII Receive data bit 3 C16 MIIRXD2 MPC852T PD14 Pin used on the board as MII Receive data bit 2 C17 MIIRXD1 MPC852T PD13 Pin used on the board as MII Receive data bit 1 C18 MPCMDC MPC852T PD12 Pin used on the board as MPC Management Data Clock C19 MIIRXERR y o MPC852T PD7 Pin used on the board as MII Receive Error signal C20 MIIRXDV y o MPC852T PD6 Pin used on the board as
59. 8 w s timing relax BR1 BCSR 02100001 Base at 2100000 32 bit port size no parity GPCM OR1 FFFF8110 32 KB block size all types access CS early negate 1 W S BR2 All DRAM SIMMs 00000081 Base at 0 32 bit port size no parity UPMA supported OR2 MCM36100 200 60 70 FFC00800 4MB block size all types access initial address multiplexing according to AMA MCM36400 800 60 70 FF000800 16MB block size all types access initial address MT8 16D432 832X 6 7 multiplexing according to AMA BR3 MCM36200 60 70 00400081 Base at 400000 32 bit port size no parity UPMA MCM36800 60 70 01000081 Base at 1000000 32 bit port size no parity UPMA MT16D832X 6 7 OR3 MCM36200 60 70 FFC00800 4MB block size all types access initial address multiplexing according to AMA MCM36800 60 70 FF000800 16MB block size all types access initial address MT16D832X 6 7 multiplexing according to AMA 24 Release 1 0 For More Information On This Product Go to www freescale com Freescale Semiconductor INE OPERATING INSTRUCTIONS TABLE 3 4 Memory Controller Initialization For 66Mhz with DRAM EDO Register Device Type Init Value hex Description BR4 45643232 60 030000C1 Base at 3000000 on UPMB Compatible Mode OR4 FFC00800 4 MB block size all types access initial address Compatible multiplexing according to AMB Mode MPTPR All Dram SIMMs 0400 Divide by 16 decimal supported MAMR MB321BT08TASN60 40A211
60. C217 C226 1nF 50V 5 X7R 0603 SMD AVX 06035C102JAT C227 C229 C230 C235 C241 C256 C263 C113 C116 C119 C122 C128 C130 C132 0 01UF 10nF 50V 10 SMD X7R 0603 AVX 06035C103KAT2A C134 C139 C141 C144 C148 C155 C160 C167 C170 C172 C175 C190 C201 C245 C249 C254 C255 C264 C266 C269 C271 C181 C186 C187 C194 C237 10uF 10V 10 SIZE A TANT SMD CAP SPRAGUE 293D106X9010A2T C196 68UF 20V 20 SIZE D or E CAP SPRAGUE 293D686X9020E2T C225 100pF 50V 10 0603 SMD AVX 06035A101KAT2A C239 1UF 16V SMD 10 X7R 1206 AVX 1206YC105KAT1A D1 D9 MBRD620CT ON SEMICONDUCTOR MBRD620CT D2 DIODE 1SMC5 OAT3 ON SEMICONDUCTOR 1SMC5 OAT3 D3 DIODE 1SMC12AT3 ON SEMICONDUCTOR 1SMC12AT3 D4 D8 LL4004 TSC LL4004G 1 SMD150 33 2 RAYCHEM FSMD150 33 2 F2 SMD260 POLYSWITCH 5 2A RAYCHEM FSMD260 JP1 JP4 JP7 GND Bridge PRECIDIP PD9991111210 JP5 JP6 BRIDGE MOLEX 87156 4003 J1 3 PIN SINGLE ROW MOLEX 87156 0303 87 Release 1 0 For More Information On This Product Go to www freescale com Freescale Semiconductor 16 Support Information TABLE 5 16 MPC852TADS Part List Reference Designation Part Description Manufacturer Part LD1 LD4 LD5 LD16 LD18 LD19 LED_GREEN KINGBRIGHT KPT 3216SGD LD2 LD6 LED_RED KINGBRIGHT KPT 3216ID LD3 LD7 LD15 LD17 LD20 LD21 LED_YELLOW KINGBRIGHT KPT 3216YD L1 PT12133 8 2MH INDUCTOR BOURNS PT12133 L2 ACM1110 102 2P COMMON MODE CHOCK TDK 1110 102 2 COIL TO DC LIN L3
61. CE B T b The device appears repeatedly in multiples of its size e g BCSRO appears at memory locations 2100000 2100020 2100040 while BCSRI appears at 2100004 2100024 2100044 and so on c Only upper 16 bit 00 015 are used d Refer to the relevant MPC User Manual for a complete description of the MPC internal memory map 3e4 MPC Register Programming The MPC offers the following functions on the MPC852TADS 1 DRAM Controller 2 SDRAM Controller 3 Chip Select Generator 4 UART for terminal or host computer connection 5 Ethernet Controller 6 Fast Ethernet Controller 7 General Purpose I O signals 22 For More Information On This Product Go to www freescale com Release 1 0 Freescale 5emiconductor 16 OPERATING INSTRUCTIONS The MPC internal registers must be programmed after Hard Reset See the following paragraphs for descriptions The addresses and programming values are in hexadecimal base For more information and a better understanding of the below noted initialization refer to the MPC866 User Manual TABLE 3 3 SIU REGISTER PROGRAMMING Register Init Value hex Description SIUMCR 01012440 Internal arbitration External master arbitration priority 0 External arbitration priority 0 PCMCIA channel II pins PCMCIA Debug Port on JTAG port pins FRZ IRQ6 FRZ Debug register locked No parity for non CS regions DP 0 3 IRQ 3 6 pins DP 0 3 Rese
62. CS2 MX8 iM X8 1 8 CS0 7 hM Logic 29 040 29 040 29 040 M29F040 M29F040 M29F040 M29F040 LL DATA MCM29F020 MCM29F040 MCM29F080 SM73218 SM73228 The ADS Flash Memory access time is 90 nsec although 120 nsec devices are also suitable Via ORO the debugger establishes the correct number of wait states for a 66MHz system clock frequency by reading the delay section of the Flash SIMM Presence Detect lines A Motorola SIMM is built from 5V programmable AMD Am29FO0XO devices As such there is no need for external programming voltage and the Flash may be written as a regular memory Smart Technology parts however require that 12V 0 5 programming voltage be applied during programming If on board programming of these devices is required then a 12V supply must be connected to the ADS P13 However during normal Flash operations a 12V supply is not required Flash control is achieved using both the GPCM and a dedicated CSO region with complete bank control During Hard Reset initialization the debugger reads the Flash Presence Detect lines via BCSR2 and thereafter concludes how to program the BRO amp ORO registers It is within these registers that a regions size and delay are determined Flash memory performance is outlined below in TABLE 4 5 A A manufacturer specific dedicated programming algorithm should be implemented during Flash programming B For example read only is an example of a normal
63. DO DRAM TUSHIBA THM3210CSG 60 MICRON MT2D132M 6X MICRON MT2D132M 60X 021 SOCKET SIMM80 FOR FLASH AMP 822021 5 021 2 55132T9DX SIMM FLASH WHITE WPF512K32 70PSC5T MICROELECTRONICS WPF512K32 70PSC5T WPF512K32 70PSC5T SOUTHLAND MICRO 55132T9DX SYSTEM U22 U23 U26 U30 U36 SN74LVC32244GKER TI SN74LVC32244GKER U24 U25 U29 SN74LVC32245GKER TI SN74LVC32245GKER U27 SN74LVCH32373AGKER TI SN74LVCH32373AGKER U28 MT48LC2M32B2TG 7 SDRAM 2MX32 MICRON MT48LC2M32B2TG 8 U32 BUS SWITCH QUAD 2 1 MUX DEMUX IDT IDT74CBTLV3257PG U33 74LCX08 ON SEMICONDUCTOR 74LCX08D U35 RESET CONTROLLER SEIKO1 S 80828CNMC B8N T2 Y1 25Mhz 3V SMD 25PPM PROGRAMMING CARDINAL CPPLC7LTBR 25 000MHZ TS CLK OSC 7X5mm COMPONENTS Y2 Y8 SOCKET 8PIN SMD SOCKET FOR CLOCK PRECIDIP 1109330841105 OSCILLTOR Y2 10MHz 3V TH 25PPM HS PROGRAMMING CARDINAL CPPLC4LBP10 00MTS OSCILLTOR COMPONENTS Y3 40MHz 3V TH 25PPM HS PROGRAMMING CARDINAL CPPLC4LBP40 00MTS OSCILLTOR COMPONENTS 90 Release 1 0 For More Information On This Product Go to www freescale com 91 Freescale Semiconductor INE Support Information APPENDIX A Schematics For More Information On This Product Go to www freescale com Release 1 0 Freescale Semiconductor INE Support Information FIGURE A 1 Bus Config Diagram waa ConfigDiagram E MPC852T
64. DS design spirit such as maximizing the number of available MPC resources available for external application development input buffers are provided for input control signals The buffers are controlled by the PCC_EN bit in BCSRI and by writing 1 0 to PCMCIA port that may be Disabled Enabled at any time If the PCMCIA channel has been disabled then its associated pins become available for off board use via the expansion connectors The board has a loudspeaker that is connected to the MPC s SPKROUT line The loudspeaker is buffered from the and low pass filtered When the PCC EN bit in BCSRI is negated high then the loudspeaker buffer is tri stated so the SPKROUT signal of the MPC may be used for an alternate function It is not recommended P to apply control signals to an unpowered PC Card as the strobe data signal buffers trans ceivers are tri stated and may only be driven when a PC Card is powered FIGURE 4 5 PCMCIA Port Configuration on page 50 illustrates a block diagram of the PCMCIA port A Not supported on the board B If the PC Card has protection diodes on its inputs then they will force down any input signals regardless of their driven level 49 Release 1 0 For More Information On This Product Go to www freescale com 50 Freescale Semiconductor INE Functional Description FIGURE 4 5 PCMCIA Port Configuration PCMCIA SOCKET PCCVCC PCCVPP PCMCIA
65. EAKER SOUNDTECH SEP 1162 SW1 SINGLE TOGGLE SWITCH C amp K 1101M2S3CQE2 swe ABORT BROWN PUSHBUTTON SMD C amp K KT11P2SM BROWN SW3 SW6 SRESET and POWER ON RESET RED C amp K KT11P2SM RED PUSHBUTTON SMD sw4 SW DIP 2 SM 2POS 4PIN SEALD DIP SW GRAYHIL 90HBWO2PR SMD SW5 SW DIP 4 SM 4POS 8PIN SEALD DIP SW GRAYHIL 90HBWO4PR SMD U1 SOCKET 256 PIN BGA SOCKET FOR MPC852T 3M 2256A 1381 50 0001 U1 MPC852T MOTOROLA MPC852T U2 U5 FAST ETHERNET ETHERNET PHY DAVICOM DM9161E U3 U6 TG22 3506ND TRANSFORMETR TG22 HALO TG22 3506ND 3506 U4 U31 74LCX125D ON SEMICONDUCTOR 74LCX125D U7 LTC1315 DUAL PCMCIA VPP SWITCH LINEAR TECH LTC1315CG U8 ALTERA CPLD FOR BCSR ALTERA EPM3256ATC144 7 U9 CY2309ZC 1H 3 3V ZD BUFFER 16P SOIC CYPRESS CY2309ZC 1H SEMICONDUCTOR IDT IDT 2309 1HDC U10 LM317MT Regulator Motorola LM317MT U12 U18 MAX3241ECAI 28 SSOP MAXIM MAX3241 ECAI EEAI U13 U34 74AC14D ON SEMICONDUCTOR 74AC14D U14 MIC29500 3 3BT TO220 MICREL MIC29500 3 3BT U15 U16 74LS244DW ON SEMICONDUCTOR SN74LS244DW U17 ALTERA CPLD FOR BDM to EPP I F ALTERA EPM3128ATC100 10 89 Release 1 0 For More Information On This Product Go to www freescale com Freescale Semiconductor 16 Support Information TABLE 5 16 MPC852TADS Part List Reference Designation Part Description Manufacturer Part U19 74LVX161284 LOW VOLTAGE EPP TRAN FAIRCHILD 74LVX161284MTD SEMICONDUCTOR U20 SOCKET SIMM72 4MB EDO DRAM SOCKET AMP 822021 4 U20 4MB E
66. Freescale Semiconductor 1 Support Information TABLE 5 10 P5 PCMCIA Connector Interconnect Signals Pin No Signal Name Attribute Description 55 PCCA24 PCMCIA Address line 24 56 PCCA25 PCMCIA Address line 25 57 CVS2 Card Voltage Sense 2 indicates with CVS1 the PC Card operational voltage 58 RESETA Card Reset signal 59 CWAITAb PC Card Cycle Wait active low 60 CINPACKb Input Port Acknowledge active low Indicates Card s ability to respond to I O access of a certain address 61 PCREGb Attribute Memory or I O Space Select active low For selecting either attribute card configuration memory or I O space 62 CBVD2 Battery Voltage Detect 2 used with CBVD1 to indicate the Card s battery condition 63 CBVD1 Battery Voltage Detect 1 used with CBVD2 to indicate the Card s battery condition 64 PCCD8 PCMCIA Data line 8 65 PCCD9 PCMCIA Data line 9 66 PCCD10 y o PCMCIA Data line 10 67 CCD2b Card Detect 2 active low Indicates with CCD1b the correct placement of a PC Card in a socket 68 GND Ground 5 1 4 9 P10 100 10BaseT Ethernet Port Connector The MPC852TADS s P9 P10 connectors are twisted pair 100 10 Base T compatible connector P9 P10 connectors are used with an 8 pin 90 RJ45 connectors The connectors signals are described in TABLE 5 11 P9 P10 100 82 Release 1
67. Freescale Semiconductor Inc User s Manual ele EN ej MOTOROLA digitaldna MPC852TADSRM D intelligence everywhere Version 1 0 June 1 2003 MPC852TADS User s Manual Motorola Inc 2003 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Important Notice to Users While every effort has been made to ensure the accuracy of all information in this document Motorola assumes no liability to any party for any loss or damage caused by errors or omissions or by statements of any kind in this document its updates supplements or special editions whether such errors are omissions or statements resulting from negligence accident or any other cause Motorola further assumes no liability arising out of the application or use of any information product or system described herein nor any liability for incidental or consequential damages arising from the use of this document Motorola disclaims all warranties regarding the information contained herein whether expressed implied or statutory including implied warranties of merchantability or fitness for a particular purpose Motorola makes no representation that the interconnection of products in the manner described herein will not infringe on existing or future patent rights nor do the descriptions contained herein imply the granting or license to make use or sell equipment constructed in accordance with this description
68. His us T oin ub S01 LOY Aye sN1 oo anav anav eavanareaxs 2 Z vLAHd Fony ioo ET 1 ALT c OR prr enea enea 256 950 850 85 is osoa 8 B8 E ref vez Sp 93H98 LE IIVIOSI rz 219 A 2 B5 lod Ly Te TONIS NE ABS ITE TT EH N Iu E ON3XHIIN s NOU OF gggg ZOKA rur OVH xu 2227 Ziwa MOTTA g XH ESSE f XUU3XL ZOVIAH d 2 T t RONS T 02 2201 on i a Nov MOVIE 66 0819 4819 eeu QUIS HONVHO Enea XON SPEO d 00000 55 IISNHIHIS ISYA s Release 1 0 101 For More Information On This Product Go to www freescale com Freescale Semiconductor WF nual Support Information FIGURE A 11 RESET amp INDICATORS T ZL p IL aus 0021090 Tr AEpung aE LOG SHOLVOIGNI 13539 v E Jaquin wiueumoog 50 v12s80dN aeus 0219 118249 1881s 1 eyuays pu tegis 1
69. L5 L8 FERRITE NFM60R30T222T MURATA NFM60R30T222T1 L4 L9 L34 BLM18AG121SN1 CHIP FERRITE BID 120 MURATA BLM18AG121SN1 OHM 0603 P1 P2 CONN 96 96P DIN C F 90 PC TAIL ELCO 268477096002025 P3 P4 P6 P8 P11 P15 MICTOR38 38P LOG ANL MICTOR CON AMP 2 767004 2 P5 PCMCIA TOP 90 SMD CON AMP AMP 822021 5 P9 P10 8P RJ45 90 PC MODULAR JACK MOLEX 43202 8110 8919 P12 P18 P19 10PIN TERM STRIP SHORT SMD 5X2 SAMTEC TSM10501 SDV AP P13 PWR2 2PIN PC STRGHT POW CON WIELEND BAMBERG 81135253303253 14 SMB Straight Jack for SUHNER 82SMB 50 0 1 111 P16 POWER JACK 2 1mm SWITCHCRAFT RAPC722 P17 RS232 9P DUAL F 90 DCON TAIL EDA 8LE009009D306H P20 CON D Type 25P D 90 TAIL M 7 2 8 08mm KCC DNR 25P CB SG Q1 Q3 MMDF3NO3HD ON SEMICONDUCTOR MMDF3NO3HD Q4 MMDF4N01HD ON SEMICONDUCTOR MMDF4NO1HD RN1 RN16 RN19 RN33 RN35 RN38 RN40 220 5 4R 8P SMD CHIP RE NETW AVX CRA3A4E220JT RN17 RN18 RN34 RN36 RN37 RN39 10K 5 8R 10 SMD CHIP RE NETW ROHM RS8A1002J OR RN41 RN43 RN48 MNR15EORPJ103 RN42 1K 596 8R 10P SMD CHIP RE NETW ROHM RS8A1001J OR MNR15EORPJ102 R1 R3 R6 R34 R41 R43 R48 R49 R52 R54 R55 R59 R64 R69 R71 R76 R79 R87 R89 R94 R97 R106 R109 R136 R137 R141 R143 R145 R147 R148 R151 R153 R155 R158 10K 1 0 1W 0603 SMD T R ROEDERSTEIN D11 010KFCS R2 R8 R62 R67 R72 R74 R117 R128 R132 R134 R135 R140 22 1ohm 1 0 1W 0603 SMD T R ROEDERSTEIN D11 22R1FCS R4 R9 6 8K 1 0603 SMD RES T R DALE CRCW0603 6801F R7 R39 R104 330ohm 1
70. LNS 1 217554 S3 Zivood eN Niva Suld YEZEZEHOATPLNS DOR QUU 1 ELEZEHOAT PNG ELEZEHOAT PENS 1 0 ber 30 im 801 eat EY i 808 sae wg a i iat ziy N 15 is Sa vod L d T 10995 e ot 10091 POE Ge vOOd al H 21 559 22 559 edt 06 Tanto EIvood 201 ZOE zae r 4 4 59 291 vevoOd ioe ie anto anro Tanio oso tro obo oto Siv55d S V99d iso svo wo o d vien azen Release 1 0 For More Information On This Product Go to www freescale com 98 uctor angu Support Information FIGURE A 8 Devices Power Freescale Semico ap 8 Pag E002 Be Aen eg Loia YAM Od S391430 ev e Niueumoog zs SQ V12S80dW en N 0219 ores amp v 102040 Release 1 0 Or dni antonio 4ni00 9619 6E19 9109 61LHOGA wey Hanumd staan T Pa a SLHGGA SLHGGA LHOGA dni anro 4nroo anro anoo anvo ant oo Haga _veipecio zeig 1210 8210 6010 oeg HaAuMd 1 1819 3niog anro anion anoo 21191 6910 0419 8910 191
71. M Refresh Communication Ports RS232 Ports RS232 Port Signal Descriptions Ethernet Port FETHC Fast Ethernet Controller on Port D DM9161E Control PCMCIA Port II For More Information On This Product Go to www freescale com Release 1 0 19 19 19 19 19 19 20 20 20 20 20 20 22 23 34 34 34 34 34 34 35 35 35 35 36 36 36 36 37 37 38 38 39 40 42 43 46 47 47 48 48 48 48 48 49 49 Freescale 5emiconductor 16 PCMCIA Power Control Board Control amp Status Register BCSR BCSRO Hard Reset Configuration Register BCSRI Board Control Register 1 BCSR2 Board Control Status Register 2 BCSR3 Board Control Status Register 3 BCSR4 Board Control Status Register 4 On board EPP SPP Command Converter EPP Register Definitions BDM Debug Port Standard MPC852T Debug Port Connector Pin Description VFLS 0 1 HRESET SRESET DSDI Debug Port Serial Data In DSCK Debug Port Serial Clock DSDO Debug Port Serial Data Out Power 5V Bus 3 3V Bus 12V Bus Support Information Interconnect Signals P1 P2 Expansion Connectors P3 P4 P6 P7 P8 P11 and P15 MICTOR Logic Analyzer connectors P5 PCMCIA Port Connector P9 P10 100 10BaseT Ethernet Port Connector P12 External Debug Port Controller Input Interconnect P13 12V Power In Connector P14 BNC Connector P16 2 1 mm Power Jack 5V Connector P17 RS232 Dual Port Connector P18 P19 Altera programming ISP Connectors P20 Parallel Host Port Connec
72. M for a 16 bit data bus width operation the following steps should be taken 1 Set the Dram Half Word bit in BCSRI to Half Word See TABLE 4 11 Description 2 Port size bits of BR2 and of BR3 for a 2 bank DRAM SIMM should be set to 16 bits 3 The AM bits in the OR2 register should be set to half of the nominal single bank DRAM SIMM volume or to a quarter of the nominal dual bank DRAM SIMM volume If a dual bank DRAM SIMM is being used then perform the following 4 Ifa contiguous DRAM block is required then set the base address bits in the BR3 register to DRAM BASE plus a quarter Nominal Volume 5 The AM bits of the OR3 register should be set to a quarter of the Nominal Volume If the above noted steps 1 5 are executed from a running code then during execution this code shouldn t reside on the DRAM for potentially erratic behavior may result in a system crash 4e6e2 DRAM Performance Figures Projected DRAM performance figures are shown in TABLE 4 2 Regular DRAM Performance Figures and in Release 1 0 For More Information On This Product Go to www freescale com Freescale 5emiconductor 16 Functional Description TABLE 4 3 EDO DRAM Performance Figures TABLE 4 2 Regular DRAM Performance Figures Number of System Clock Cycles System Clock Frequency MHz 50 25 DRAM Delay nsec 60 70 60 70 Single Read 6 6 3 4 Single Write 4 4 3 3 Burst Read 6 2 3 2 6 3 2 3 3 2 2
73. MB324 8CTOOTBSN60 FF000800 16MB block size all types access initial address multiplexing according to AMA BR38 MB322BT08TASN60 00400081 Base at 400000 32 bit port size no parity UPMA MB328CTOOTBSN60 01000081 Base at 1000000 32 bit port size no parity UPMA OR3 MB322BT08TASN60 FFC00800 4MB block size all types access initial address multiplexing according to AMA MB328CTOOTBSN60 FF000800 16MB block size all types access initial address multiplexing according to AMA BR4 K4S643232 TC60 030000C1 Base at 3000000 on UPM B Compatibl e Mode OR4 FFC00A00 4 MB block size all types access initial address Compatibl multiplexing according to AMB e Mode 20 Release 1 0 For More Information On This Product Go to www freescale com Freescale 5emiconductor INE OPERATING INSTRUCTIONS TABLE 3 7 Memory Controller Initialization For 20Mhz Register Device Type Init Value hex Description BR4 MPC86x New Mode OR4 MPC86x New Mode K4S643232 TC60 0x000000C1 Base at 0x0 on UPM B OxFC800A00 4 MB block size all types access initial address multiplexing according to AMB MPTPR All Dram SIMMs supported 0400 Divide by 16 decimal MAMR MB321BTOS8TASN6O 60A21114 Refresh clock divided by 60 Periodic timer enabled Type 2 address multiplexing scheme 2 cycle disable timer GPL4 disabled for data sampling edge flexibility 1 loop read 1 loop write 4 beats refre
74. MC1 SCC3 RS232 SCC4 Ethernet FETHC Fast Ethernet Controller on Port D PCMCIA Controller 4ege RS232 Ports The ADS has two identical RS232 ports for both assisting with user applications and as a means of providing conve nient communication channels between terminal and host computers The MPC type determines the MPC communi cation ports to which the RS232 ports are routed The MAX3241ECAI transceivers equipped with OE and shutdown mode are used to generate RS232 levels internally through use of a single 3 3V power supply When the RS232ENI or RS232EN2 bits in BCSRI are asserted low then the associated transceiver is enabled When negated the associ ated transceiver enters a standby mode characterized by tri stated receiver outputs that enables off board use of the associated port s pins via the expansion connectors A female Dual port 9 pin each D Type stacked connector is configured for direct connection via a flat cable to a standard IBM PC compatible RS232 connector 4e9e e 5232 Port Signal Descriptions The direction I O is relative to the ADS board For example P signifies ADS input CD Data Carrier Detect the ADS always asserts this line TX O Transmit Data RX D Receive Data e DTR D Data Terminal Ready ADS software may use this signal to detect whether a terminal is connected to the ADS board DSR O Data Set Ready the ADS always asserts this line RTS D Re
75. MII Receive Data Valid C21 VCC VCC C22 HRESET I O L MPC852T HRESET Pin C23 SRESET L MPC852T SRESET Pin C24 N C 73 Release 1 0 For More Information On This Product Go to www freescale com Freescale Semiconductor INE a Support Information TABLE 5 2 P2 I O Port Expansion Interconnect Signals Pin No Signal Name Attribute Description C25 VCC VCC C26 MIITXD1 MPC852T Pin used on the board as MII Transmit data bit 1 C27 VPPIN y o 12V input for PCMCIA Flash programming Parallel to Gan MPC852TADS s P13 C29 GND GND C30 MIITXD2 MPC852T PDA Pin used on the board as MII Transmit data bit 2 C31 GND GND C32 MIITXD3 MPC852T PD5 Pin used on the board as MII Transmit data bit 3 5e e2 P3 P4 P6 P7 P8 P11 and P15 MICTOR Logic Analyzer connectors The noted connectors are AMP 38 pin receptacle MICTOR connectors They connect to a dedicated adaptor from the HP 16500 Series of logic analyzers The adaptor joins between two 16 bit pods TABLE 5 3 P3 Logic Analyzer Interconnect Signals MPC852T Pin Signal Name 2 N C 4 N C 6 MODCK1 8 A16 10 A17 12 A18 14 A19 16 A20 18 A21 20 A22 22 A23 24 A24 26 A25 28 A26 30 A27 74 Release 1 0 For More Information On This Product Go to www freescale com Freescale Semiconductor INE a Support Informati
76. Power 3 3V B5 3 3V Power 3 3V B6 3 3V Power 3 3V B7 N C B8 GND GND B9 BCE2Ab Card Enable 2 for odd bytes in PCMCIA I F buffered B10 BCE1Ab O Card Enable 1 for even bytes in PCMCIA I F buffered B11 BALEA Address Latch Enable buffered Bi2 MIICOL 852 MII Collision Detect B13 MIITXEN MPC852T MII Transmit Enable B14 MPCMDIO 852 MII Management Data B15 MIICRS 852 MII Carrier Sense Detect B16 GND GND B17 N C B18 GND GND B19 N C 20 GND GND B21 N C 22 GND GND B23 N C 24 GND GND B25 N C B26 GND GND B27 N C 28 GND GND 68 Release 1 0 For More Information On This Product Go to www freescale com Freescale Semiconductor INE Support Information TABLE 5 1 P1 ADD Data and PCMCIA Expansion Connector Interconnect Signals Pin No Signal Name Attribute Description B29 N C B30 GND GND B31 N C B32 GND GND C1 EXP BDO MPC852T Buffered DO D7 C2 EXP_BD1 C3 EXP_BD2 y o C4 EXP_BD3 C5 EXP_BD4 C6 EXP BD5 7 EXP_BD6 C8 EXP_BD7 y o C9 EXP A16 O MPC852T buffered A16 A31 C10 EXP A17 11 _ 18 12 _ 19 C13 EXP_A20 14 _ 21 15 _ 22 16 EXP_A23 17 _ 24 18
77. This Product Go to www freescale com Freescale Semiconductor 16 OPERATING INSTRUCTIONS TABLE 3 5 Memory Controller Initialization For 66Mhz with No DRAM EDO Register Device Type Init Value hex Description BRO All Flash SIMMs 02800001 Base at 2800000 32 bit port size no parity GPCM supported ORO MCM29F020 90 FFE00D34 2MB block size all types access CS early negate 6 w s timing relax MCM29F040 90 FFC00D34 4MB block size all types access CS early negate 6 SM732A1000A 9 W S timing relax MCM29F080 90 FF800D34 8MB block size all types access CS early negate 6 SM732A2000 9 W S timing relax MCM29F020 12 FFEO0D44 2MB block size all types access CS early negate 8 W S timing relax MCM29F040 12 FFC00D44 4MB block size all types access CS early negate SM732A1000A 12 8 w s timing relax MCM29F080 12 FF800D44 8MB block size all types access CS early negate SM732A2000 12 8 w s timing relax BR1 BCSR 02100001 Base at 2100000 32 bit port size no parity GPCM OR1 FFFF8110 32 KB block size all types access CS early negate 1 W S BR2 All Dram SIMMs 00000080 Invalid bank supported OR2 MCM36100 200 60 70 FFC00800 Invalid bank MCM36400 800 60 70 FF000800 MT8 16D432 832X 6 7 BR3 MCM36200 60 70 00400080 Invalid bank MCM36800 60 70 01000080 Invalid bank MT16D832X 6 7 OR3 MCM36200 60 70 FFC00800 Invalid bank MCM36800 60 70 FF000800 In
78. _ 25 19 _ 26 20 _ 27 21 _ 28 22 EXP_A29 C23 EXP_A30 24 _ 1 25 26 N C C27 N C 69 Release 1 0 For More Information On This Product Go to www freescale com Freescale Semiconductor INE Support Information TABLE 5 1 P1 ADD Data and PCMCIA Expansion Connector Interconnect Signals Pin No Signal Name Attribute Description C28 N C C29 N C C30 N C C31 N C C32 N C 70 Release 1 0 For More Information On This Product Go to www freescale com Freescale 5emiconductor 16 Support Information TABLE 5 2 P2 I O Port Expansion Interconnect Signals Pin No Signal Name Attribute Description A1 N C A2 N C A3 N C A4 N C A5 MIITXERR y o MPC852T PD11 Pin used on the board as MII Transmit Error A6 MIIRXDO MPC852T PD10 Pin used on the board as MIl Receive data bit 0 A7 MIITXDO y o MPC852T PD9 Pin used on the board as MII Transmit data bit 0 A8 MIIRXCLK MPC852T PD8 Pin used on the board as MII Receive Clock A9 N C A10 N C A11 N C A12 N C A13 ETHRXCK y o MPC852T Pin used on the board as 10Base T Ethernet port receive clock A14 ETHTXCK y o MPC852T PA2 Pin used on the board as 10Base T Ethernet port transmit clock A15 PA1 MPC852T 1 Pin 16
79. ansa i 305 be T T T T A 9 m PAS VC Pow 9214 921908 ENY S y W SAS Svs SN 9195 951999 ie 9751955 9951998 9851959 anto anro anro Janto anro ENU 8 T EBENA avr ld wo eo so to wo 19 zo to EA svi oo sevsss FINE 2 TAL wz 1 1 i QEVSHH FiNH 9 ESE I aeen L NEA ENEA lie elva lt A anto Tanto anro tzo 919 80 vO 30r a 30 30g pent 30 pet H avsa wu 9 V HoH 97059 iB TAY yy Vg SINU 8 L zH SH IEY ZINH Sr lt T qiyssgg ied IP qviSH IH EAP Pda QEV ZINH oe LAP lve Fag sev E muy T9 ixt aes 02 2 LAY ae Y Sg Tey YAE pve ep YAE ye TAE tve ar eve 55 eve FS E eve 54 ZINH Sd OLY ZAE eve ZAE zve 59 og ZAE zve an LAE LE ae LAE INE SEN ove LAE WWE Sy SVN SINE 9 S3 Fev peva 53 TV eve NU SN 8v ONTPZNS HaNOrPEZE ONTPINS H33 rpZZeO ATPLNS aoz 30 bey 1 301 1 301 VAHI ONE em tys SINH Z X uU P Sd EZY s UE Dy IVWHO EA eve gzv 8 X EA eve Sd E EA eve 9v 3 i ive 8 EREIN NH 9 ThE tve 18 ive qvaod YAL vl EIEN ozvg 9NH AL 7 PAL put Lay 12 amp
80. as four different power 1 5V 2 3 3V 3 12V 4 1 8V A For example the DSDI must meet the DSCK s setup hold time to from rising edge criteria B In parallel i e full duplex communication 63 Release 1 0 For More Information On This Product Go to www freescale com Freescale Semiconductor INE Functional Description FIGURE 4 7 MPC852TADS Power Scheme ADS Logic amp Peripherals Expansion Connector VDDL VDDH MPC852T 1 lt Power Control PC Card Socket le To support off board application development the power buses are connected to the expansion connectors in order that external logic may be powered directly from the board The maximum current allowed drawn from each board bus is shown in TABLE 4 24 Off board Application Maximum Current Consumption below TABLE 4 24 Off board Application Maximum Current Consumption Power BUS Current 5V 1 5A 3 3V 1 5A 12V 100 mA In order to protect on board devices from supply spikes uncoupling capacitors typically 0 1uF are located in the closest possible proximity to the device s power leads and the GND 64 Release 1 0 For More Information On This Product Go to www freescale com Freescale 5emiconductor 16 Functional Description 4e de 5V Bus Some ADS peripherals reside on the 5V bus The MPC however is not 5V compatible Consequently 3 3V to 5V buffers were ad
81. ation for KS643232C TC60 upto 32MHz on page 32 or in TABLE 3 10 UPMB Initialization for KS643232C TC60 32 MHz 50MHz on page 33 Program the Memory Controller MPTPR MBMR and registers as per TABLE 3 7 Mem ory Controller Initializations For 20Mhz on page 29 or TABLE 3 4 Memory Controller Initializa tion For 66Mhz with DRAM EDO on page 24 Set the MAR to the correct value 0x48 for up to 32MHz or 0x88 for 32 50 MHz Run the MRS command programmed in locations five to eight of the UPMB by writing the MCR with 0x80808105 Change the MBMR TLEB field to eight in order to maintain 8 beat refresh bursts Run the refresh sequence 8 refresh cycles being performed by writing the MCR with 0x80808130 Restore the MBMR TLFB field to four in order to provide the 4 beat refresh bursts of normal operation The SDRAM is now initialized and ready for operation SDRAM Refresh Refresh the SDRAM by using its auto refresh mode For example the UPMB periodic timer issues a burst of four auto refresh commands to the SDRAM every 62 4 msec As a result all 2048 SDRAM rows are refreshed within a specific 32 8 msec slot 47 Release 1 0 For More Information On This Product Go to www freescale com Freescale 5emiconductor 16 Functional Description 4 9 Communication Ports The ADS board contains all the modules that could possibly be configured on the MPC852T The various communi cation ports are noted below S
82. ave been inadequate for a board is running at a lower frequency Thus for the best bus bandwidth availability the re fresh rate should be adapted to the current system clock frequency 23 Release 1 0 For More Information On This Product Go to www freescale com Freescale Semiconductor INE OPERATING INSTRUCTIONS Warning Due to availability problems with several of the supported mem ory components the initialization noted below were not tested with all the parts Consequently these initialization may CHANGE during the course of the testing period TABLE 3 4 Memory Controller Initialization For 66Mhz with DRAM EDO Register Device Type Init Value hex Description BRO All Flash SIMMs 02800001 Base at 2800000 32 bit port size no parity GPCM supported ORO MCM29F020 90 FFEO0D34 2MB block size all types access CS early negate 6 W S timing relax MCM29F040 90 FFCO0D34 4MB block size all types access CS early negate 6 SM732A1000A 9 w s timing relax MCM29F080 90 FF800D34 8MB block size all types access CS early negate 6 SM732A2000 9 w s timing relax MCM29F 020 12 FFE00D44 2MB block size all types access CS early negate 8 w s timing relax MCM29F040 12 FFC00D44 4MB block size all types access CS early negate SM732A1000A 12 8 w s timing relax MCM29F080 12 FF800D44 8MB block size all types access CS early negate SM732A2000 12
83. be cleared Programming OR4 Mask Register bits for SDRAM should be changed according to SDRAM size This where the 2 MS bits are not masked 8MB SDRAM ORA Mask bits OxFC80 In this case users may view address 0 and also add 30000000 they are the same word in the memory Users must also change the BIH to 0 A For FUTURE Use 20 Release 1 0 For More Information On This Product Go to www freescale com Freescale Semiconductor 16 OPERATING INSTRUCTIONS TABLE 3 1 Memory Map in MP852TADS New Mode ADDESS RANGE Memory Type Device Type ioi 00000000 007FFFFF SDRAM 8MByte 32 02000000 020FFFFF Empty Space 02000300 020003FF Control Register 02100000 02107FFF BCSR 0 4 P 32 02100000 02107FE3 BCSRO 2100004 02107FE7 BCSR1 2100008 02107FEB BCSR2 210000C 02107FEF BCSR3 2100010 02107FF3 BCSR4 02108000 021FFFFF Empty Space 02200000 02207FFF MPC Internal 32 MAP 02208000 027FFFFF Empty Space 02800000 029FFFFF Flash SIMM MCM29F020 MCM29F040 MCM29F080 32 E QSBEFEEE SM732A1000A SM732A2000 28 02600000 O2FFFFFF 32 03000000 037FFFFF SDRAM for 8MB 32 03400000 FFFFFFFF Empty Space 0 0 007 FFFF 0x0300 0000 0x037F FFFF are both mapped to SDRAM 8MB b The device appears repeatedly in multiples of its size e g BCSRO appears at memory locations 2100000
84. cator LD21 The yellow SPP connection LED indicates that the board is connected directly to the Pc s parallel port using SPP transfer mode and the BDM Debug connector P12 is irrelevant 3e3 MEMORY MAP All access to MPC852TADS memory slaves is controlled by the MPC s memory controller As a consequence the user may reprogram the memory map The debug station performs Hard Reset Then the debugger checks for the existence size delay and type of EDO DRAM and FLASH memory SIMMs that are mounted on board Accordingly the debugger initializes chip selects The SDRAM DRAM and FLASH memory respond to all types of memory access For example user supervisory program data and DMA Following is a memory map description for 2 options Compatible Mode and MPC852TADS New Mode The Compatible Mode uses an EDO DRAM and 8MB SDRAM Further all the programmable registers remain the same the memory map is the same as that of the MPC8xxFADS board with the exception of OR4 Mask Register bits The latter are changed according to SDRAM size to OxFF80 In the MPC852TADS New Mode the EDO DRAM is not used and consequently the SDRAM is mapped differently See TABLE 3 1 Memory Map in MP852TADS New Mode and TABLE 3 2 Memory Map in MPC852TADS Compatible Mode The following programmable changes are necessary in order to work on the board in the MPC852TADS New Mode Programming BR2 BR3 Base Address bits for EDO DRAM aren t valid The L bit should
85. cted 2048 Parallel Host Connector in EPP I F P20 The MPC852TADS P20 EPP interface connector is a male 25 pin D type connector The connection between the MPC852TADS and the host computer is by 25 line flat cable This connector enables connection to host computer when using On board serial command converter or EPP converter When connection to host is made via P20 the capability of working with an external BDM Debug connector is disabled FIGURE 2 14 Parallel host connector with EPP I F P20 below shows the pin configuration of the connector when choosing EPP Mode transfer FIGURE 2 15 Parallel host connector in serial mode P20 below shows the pin configuration of the same connector when choosing Serial Mode transfer FIGURE 2 14 Parallel host connector with EPP I F P20 WRITE DBO ERROR DB1 RESET ASTROBE DB2 DB3 GND DB4 GND DB5 t2 GND DB6 N GND DB7 N N GND IRQ N w GND WAIT N GND N C N O O SELECT 14 Release 1 0 For More Information On This Product Go to www freescale com Freescale Semiconductor INE a Hardware Preparation and Installation FIGURE 2 15 Parallel host connector in serial mode P20 QNA DSDI e xA DSCK o a NA 9 i RESET N A e o N A e e cv N A e ow N A gt d Len N A bed elo DSDO e o
86. ctive low and enables EVEN numbered address bytes 8 PCCA10 PCMCIA Address line 10 9 OE PCMCIA Output Enable Signal active low and enables data outputs from PC Card during memory read cycles 10 PCCA11 PCMCIA Address line 11 11 PCCA9 PCMCIA Address line 9 12 PCCA8 PCMCIA Address line 8 13 PCCA13 PCMCIA Address line 13 14 PCCA14 PCMCIA Address line 14 15 WE PCM O PCMCIA Memory Write Strobe active low and strobes data to PC Card during memory write cycles 16 CRDY PC Ready Busy Signal allows PC Card to stall host access when a previous access processing is incomplete 17 PCCVCC 5V VCC is switched by the MPC852TADS via BCSR1 18 PCCVPP 12V 5V VPP for PC Card programming 12V available only if applied to P13 in MPC852TADS controlled via BCSR1 19 PCCA16 PCMCIA Address line 16 20 PCCA15 PCMCIA Address line 15 21 PCCA12 PCMCIA Address line 12 22 PCCA7 PCMCIA Address line 7 23 PCCA6 PCMCIA Address line 6 24 PCCA5 PCMCIA Address line 5 25 PCCA4 PCMCIA Address line 4 26 PCCA3 PCMCIA Address line 3 80 Release 1 0 For More Information On This Product Go to www freescale com Freescale Semiconductor 1 Support Information TABLE 5 10 P5 PCMCIA Connector Interconnect Signals Pin No Signal Name Attribute Description 27 PCCA2 PCMCIA Address li
87. d on the information in this document Motorola reserves the right to make changes without further notice to any products herein Motorola makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Motorola assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters which may be provided in Motorola data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts Motorola does not convey any license under its patent rights nor the rights of others Motorola products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur Should Buyer purchase or use Motorola products for any such unintended or unauthorized application Buyer shall indemnify and hold Motorola and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expens
88. d separately This is achieved with 74L VC buffers operated by 3 3V though 5V tolerant The 74LVC buffer reduces board noise by reducing transition ampli tudes Additional reductions in noise and reflection are made when a series of resistors is placed over a DRAM address and strobe lines Data transceivers will open under two conditions available access to a valid P board address or during Hard Reset configuration Consequently data conflicts are avoided when the off board memory is read provided no mapping to a valid board address exists Avoiding such errors is the responsibility of the user D In cases where PCMCIA port B pins exist A At Hard Reset DSCK is configured to reside on the BDM Debug port P12 or in Altera logic when using on board command converter B Capacitive load is dependant on the DRAM SIMM s internal structure C A valid address being one covered within a Chip Select region D Excepting SDRAM which is unbuffered E Allows a configuration word stored in Flash memory to become active 36 Release 1 0 For More Information On This Product Go to www freescale com Freescale Semiconductor 16 Functional Description 4 5 Chip Select Generator The MPC memory controller is used as a chip select generator in order to access on board memories and reduce board area The latter cuts costs lessens power consumption and increases flexibility Off board application develop ment may be enhanced by d
89. ded between the MPC and the 5V devices in order that the MPC may operate 5V levels on its lines without damage The 5V bus is connected via a fuse 5A to an external power connector To forestall reverse voltage or over voltage being applied to the 5V inputs a set of high current diodes and a zener diode were connected between the 5V bus and the GND 4e 4e2 3 3V Bus The MPC and SDRAM as well as the address and data buffers are powered by a 3 3V bus produced from a 5V bus using Micrel s special low voltage drop linear voltage regulator the MIC29500 3 3BT This device is capable of driving a fuse of up to 5A as well as facilitating operation of external logic 4e 4de3 12V Bus The sole purpose of the 12V bus is to supply VPP programming voltage to the PCMCIA card and the Flash SIMMP The 12V bus is connected to a dedicated input connector via a fuse 1A and is protected from over reverse voltage application If the 12V supply is not required for either the PC Card or the Flash SIMM then 12V input to the ADS may be omitted A 3 3 V required for full speed Internal logic may be powered by a 2V bus for reduced performance levels B 12V necessary only for the PCMCIA card and the Flash SIMM 65 Release 1 0 For More Information On This Product Go to www freescale com Freescale 5emiconductor 16 Support Information 5 Support Information This chapter provides MPC852TADS support maintenance and connectivity informat
90. directly via On board Serial command converter or via On board EPP converter No needs external parts EPP is an asynchronous byte wide bidirectional channel controlled by the host device This interface provides the capability to send data from the host computer to the MPC852T at a high speed The bus is a multiplexed address data bus connected to a D Type 25 pins Parallel connector called P20 Typically EPP operates on a two phase bus cycle First an address is generated on the bus and is latched by Altera logic when the host generates an address strobe The Altera logic uses this cycle for control A separate Data strobe is generated to perform the actual data transfer Cycles are terminated when the Busy signal is transferred from the Altera to the host computer In the Altera logic there is a parallel to serial converter for write data and a serial to parallel converter for read data from the MPC The signals used for EPP Mode transfer are described in detail in TABLE 4 21 Parallel Host Port Connector s Signal Description with EPP I F below The signals used for Serial Command Converter Mode transfer are de scribed in detail in TABLE 4 22 Parallel Host Port Connector s Signal Description with Serial Command A For FUTURE Use 59 Release 1 0 For More Information On This Product Go to www freescale com Freescale 5emiconductor 1 Functional Description Converter I F below TABLE 4 21 Parallel Host Port Co
91. during Power On reset and may be read or written at any time TABLE 4 18 on page 58 describes the BCSR3 57 Release 1 0 For More Information On This Product Go to www freescale com Freescale 5emiconductor 1 Functional Description TABLE 4 18 BCSR3 Description Function DEF ATT 0 1 Reserved Implemented 00 R 2 8 Reserved Not Implemented i 9 11 FLASH_PD 7 5 Flash Presence Detect 7 5 These lines are connected to the Flash SIMM Presence Detect lines that encode the Flash SIMM Delay mounted on the Flash SIMM socket U21 Four additional Presence Detect lines that encode the SIMM Types appear in BCSR2 For FLASH_PD 7 5 encoding see TABLE 4 19 FLASH Presence Detect 7 5 Encoding on page 58 12 15 Reserved Not Implemented R TABLE 4 19 FLASH Presence Detect 7 5 Encoding FLASH PDX 7 5 Flash Delay nsec 000 Unsupported 001 150 010 120 011 90 100 111 Unsupported 4e le5 BCSR4 Board Control Status Register 4 The BCSR4 serves as an ADS control register is accessed at offset 10H from the BCSR base address may be read or written at any time and has defaults set at Power On reset BCSR4 fields are described in TABLE 4 20 BCSR4 Description on page 58 TABLE 4 20 BCSRA Description Function DEF ATT 0 2 Reserved Not Implement
92. e local debug port controller uses this signal 4 13 1 4 DSDI Debug Port Serial Data In The debug port controller sends its data to the MPC via the DSDI signal The DSDI also serves a role during Soft A The FRZ line should be connected to both VFLS 0 1 pins on the debug port connector when a target system needs to use either of the alternative VFLS 0 1 functions B The configuration is divided into two parts the first is sampled three system clock cycles prior to the rising edge of SRESET while the second is sampled eight clocks after the rising edge 62 Release 1 0 For More Information On This Product Go to www freescale com Freescale 5emiconductor 1 Functional Description Reset configuration See 4 1 6 3 Soft Reset Configuration on page 36 4e13e1e5 Debug Port Serial Clock Serial data is clocked into the MPC according to the DSCK clock during the asynchronous clock mode The DSCK also serves a role during Soft Reset configuration See 4 1 6 3 Soft Reset Configuration on page 36 4e13e1e6 DSDO Debug Port Serial Data Out The MPC clocks out the DSDO according to the debug port clock and in parallel with the DSDI being clocked in The DSDO also serves as a READY signal for the debug port controller by indicating that the debug port is ready to receive the controller s command or data 4e14 Power The MPC852T features three power buses 1 VO 2 Internal Logic 3 PLL The MPC852TADS h
93. e signals are presented in TABLE 4 21 Parallel Host Port Connector s Signal Description with EPP I F below 86 Release 1 0 For More Information On This Product Go to www freescale com Freescale 5emiconductor 16 Support Information 5 2 MPC852TADS Parts Listing This section lists the MPC852TADS s Bill of Material according to reference designations TABLE 5 16 MPC852TADS Part List Reference Designation Part Description Manufacturer Part C1 C28 C32 C58 C60 C69 C71 100NF 0 1uF 16V 10 X7R 0603 EPCOS 0603X7R104K016P07 C75 C76 C78 C81 C83 C84 C108 C112 114 115 117 118 120 121 123 125 127 129 C131 C133 C135 C138 C142 C143 C145 C147 C149 C154 C156 C158 C159 C163 C166 C168 C169 C171 C173 C174 C177 C180 C182 C184 C189 C191 C193 C195 C197 C200 C202 C203 C205 C207 C209 C212 C214 C216 C218 C224 C231 C234 C236 C238 C242 C244 C247 C248 C250 C253 C265 C267 C268 C270 C29 C30 C59 C72 10UF 25V 10 SMD C TANT SPRAGUE 293D106X9025C2T C31 C87 C124 C157 0 01uF 2KV X7R 1825 10 SMD JOHANSON 202S49W103KV4E DIELECTRIC C70 C73 C204 C228 C246 1uF 25V 10 SMD A TANT SPRAGUE 293D105X9025A2T C74 120PF 50V 5 SMD COG 1206 AVX 1206 5A 121 JTR C82 10NF 50V 10 NPO 1210 VITRAMON VJ1210A103KXAT C85 C240 47UF 16V 10 SIZE D AVX TAJD476K016 C86 100UF 10V TNT D SMT 10 SIEMENS B45196 H2107K C88 C105 C210 C211 C215
94. ector s Signal Description with Serial Command Converter I F Pin Signal ATT Description Mnemonic 1 N C Not Connected 2 DSDI Serial Data Input to the MPC852TADS 3 DSCK Serial Clock Input to the MPC852TADS 4 N C Not Connected 5 Reset Reset signal is active high Used by the Host to cause Hard reset to MPC852TADS 60 Release 1 0 For More Information On This Product Go to www freescale com Freescale 5emiconductor INE Functional Description TABLE 4 22 Parallel Host Port Connector s Signal Description with Serial Command Converter I F Pin Signal ATT a Description Mnemonic 3 10 N C Not Connected 11 DSDO Serial Data Out from the MPC852TADS 12 N C Not Connected 13 5V_OUT 5V_OUT This is the MPC852TADS 5V power supply which indicates to the debug station that the target processor is powered 14 17 N C Not Connected 18 24 GND MPC852TADS Ground Plane 25 IN This is a mechanical signal On the Host side it is connected to GND When on the MPC852TADS side it will identify GND on this pin it is indicated that the Parallel connector was pluged a Signal attributes are with reference to the MPC852TADS 4 12 1 EPP Register Definitions EPP is an Enhanced Parallel Port which is one of IEEE 1284 data transfer mode EPP is an extension to the register definitions for the standard parallel por
95. ed 3 SIGNAL_LAMP Signal Lamp When the signal is active low a dedicated LED illuminates 1 R W When inactive there is no LED light The LED is used for software signalling 4 RSTMII RSTMII When active low the MII Fast Ethernet Device Davicom 1 R W DM9161E gets reset and being initialized to its Reset value When inactive the MII Fast Ethernet Device is out of Reset 58 Release 1 0 For More Information On This Product Go to www freescale com Freescale 5emiconductor INE Functional Description TABLE 4 20 BCSR4 Description PON BIT MNEMONIC Function DEF ATT 5 MIIRXEN MIIRXEN When active high the MII Fast Ethernet Device Davicom 0 RW DM9161E connected to Port D is enabled When negated low all device output signals are tri stated 6 PORESET PORESET When active high PORESET is implemented the 0 R W MPC852TADS When negated low the board is out of Power on Reset 7 ETHRST ETHRST When active low the Ethernet Device Davicom DM9161E gets 1 R W reset and being initialized to its Reset value When inactive the Ethernet Device is out of Reset 8 31 Reserved Not Implemented R W a Not implemented 4 12 On board EPP SPP Command Converter For host controlled operation a host computer controls the board via the BDM Debug Port This configuration serves for extensive debugging using an on host debugger Host computer can be connected with the board
96. ed Not implemented FLASH CFG EN Flash Configuration Enable When asserted low the Hard Reset configuration held in BCSRO is NOT driven on the data bus during Hard Reset Also configuration data held at the 1 st word of the Flash Memory is driven to the data bus during Hard Reset RW Reserved Not implemented RS232EN 1 RS232 Port 1 Enable When asserted low the RS232 Port 1 transceiver is enabled When negated the transceiver is in standby mode and the relevant MPC Communication Port pins become available for off board use via the expansion connectors RW PCCEN PC Card Enable When asserted low the on board PCMCIA channel is enabled i e address and strobe buffers are enabled to from the card When negated all buffers to from the PCMCIA channel are disabled allowing off board use of its associated lines RW PCCVCCO PC Card VCC Select 0 These signals in conjunction with PCCVCC1 determine the voltage applied to the PCMCIA card s VCC Possible values are 0 3 3 5 V For line encoding and associated voltages see TABLE 4 12 PCCVCC 0 1 Encoding on page 55 RW 10 11 PCCVPP 0 1 PC Card VPP These signals determine the voltage applied to the PCMCIA card s VPP Possible values are 0 5 12 V For line encoding and associated voltages see TABLE 4 13 PCCVPP 0 1 Encoding on page 55 11 12 Dram_Half_Word DRAM Half Word When active low and the
97. ed via BCSRI the negation of CD1 and CD2 may be sensed by the MPC and consequently the Card s power supply may be cut Warning 5V power applied to a 3 3V only PC Card will inflict perma nent damage Prior to applying power to a PC Card all appli cation software handling the PCMCIA channel must check the Voltage Sense lines 4 11 Board Control amp Status Register BCSR The majority of MPC852TADS hardware options are controlled or monitored by the BCSR The BCSR is a 328 wide read write register file accessed via MPC s CS1 region that includes five registers BCSRO to BCSR4 A CS region has a minimum block size of 32 KB thus registers BCSRO BCSR4 are duplicated within that region See TABLE 3 2 Memory Map in MPC852TADS Compatible Mode on page 21 or TABLE 3 1 Memory Map in MP852TADS New Mode on page 21 The BCSR controls monitors the following functions 1 MPC Hard Reset Configuration 2 Flash Module Enable Disable 3 Flash Size Delay Identification 4 DRAM Module Enable Disable 5 DRAM Port Width 32 bit 16 bit 6 DRAM Type Size and Delay Identification 7 SDRAM Module Enable Disable 8 Fast Ethernet Port Enable Disable 9 Fast Ethernet Port Control 10 Reset Fast Ethernet PHY 11 RS232 Port 1 Enable Disable 12 RS232 Port 2 Enable Disable 13 Hard Reset Configuration Source BCSRO Flash Memory 14 PCMCIA controls A Hot insertion refers to card insertions made when the ADS is pow
98. een ETH TX RX LED indicates that the Ethernet port Davicom DM9161E on SCC4 is transmitting or receiv ing data via the 10 Base T port 30209 Ethernet Full Duplex Indicator LD2 The red ETH FDX LED indicates that the Ethernet port Davicom DM9161E on SCC4 is in Full Duplex operation mode 3e2e 0 Ethernet LINK Indicator LD3 The yellow ETH Twisted Pair LINK LED indicates that there is a good link integrity on the 10 Base T port LD3 is off when the link integrity fails 3e2e Fast Ethernet 100Mbps Indicator LD4 The green FAST ETH 100Mpbs LED indicates that the Fast Ethernet port Davicom DM9161E on Port D is in 100 Mbps operation mode 3e2e12 Fast Ethernet 10 100Base T TX RX LD5 The green FAST ETH TX RX LED indicates that the Fast Ethernet port Davicom DM9161E on Port D is transmit ting or receiving data via the 10 100 Base T port 3e2e13 Fast Ethernet Full Duplex Indicator LD6 The red FAST ETH FDX LED indicates that the Fast Ethernet port Davicom DM9161E on Port D is in Full Duplex operation mode 3e2e14 Fast Ethernet LINK Indicator LD7 The yellow FAST ETH Twisted Pair LINK LED indicates that there is a good link integrity on the 10 100 Base T port LD7 is off when the link integrity fails 18 Release 1 0 For More Information On This Product Go to www freescale com Freescale 5emiconductor INE OPERATING INSTRUCTIONS 3e2e 15 Ethernet 10Base T ETH ON LD8 The yellow ETH ON LED indicates that the
99. ered B Despite the BCSR being mapped as a 32 bit wide register that should be accessed as such only the upper 16 bits D 0 15 are used 5 Release 1 0 For More Information On This Product Go to www freescale com Freescale 5emiconductor 16 Functional Description Channel Enable Disable e PC Card VCC appliance e PC Card VPP appliance 15 External off board tool identification or software option selection switch SW5 status 16 Board Revision Code 4e le BCSR0 Hard Reset Configuration Register The BCSRO is located at offset 0 on BCSR space may be read or written at any time and has defaults set at the time of MAIN power on reset If the Flash Configuration Enable bit in BCSRI is inactive then during Hard Reset data contained in BCSRO is driven on the data bus to provide the MPC s Hard Reset configuration The BCSRO may be written at any time in order to change the MPC s Hard Reset configuration The new values regardless of the Hard Reset source become valid the next time a Hard Reset is issued to the MPC TABLE 4 10 provides a description of BCSRO bits TABLE 4 10 BCSRO0 Description BIT MNEMONIC FUNCTION ATT 0 ERB External Arbitration Arbitration is performed internally if 0 during Hard 0 R W Reset If 1 during Hard Reset Arbitration is performed externally 1 IP Interrupt Prefix Interrupt Prefix set to OXFFF00000 during Hard Res
100. es and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part MOTOROLA Motorola and the Stylized M Logo are registered in the U S Patent and Trademark Office digital dna is a trademark of Motorola Inc All other product or service names are the property of their respective owners Motorola Inc is an Equal Opportunity Affirmative Action Employer Motorola Inc 2003 MPC852TADSRM D For More Information On This Product Go to www freescale com Freescale Semiconductor Inc For More Information On This Product Go to www freescale com
101. et 1 RW IF1 during Hard Reset Interrupt Prefix set 0 2 Reserved Implemented 0 RW 3 BDIS Boot Disable CSO region is enabled for boot if 0 during Hard Reset 11 0 RW CS0 region is disabled for boot 4 5 BPS 0 1 Boot Port Size 00 32 bit 01 8 bit 10 16 bit 11 reserved 00 RW determines the CSO port size at boot 6 Reserved Implemented 0 RW 7 8 ISB 0 1 Initial Space Base Initial base address of the internal MPC s memory map 10 RW determined by the value at Hard Reset If O0 initial space at 0 If O1 initial space at 0x00F00000 If 10 initial space at OxFFOOOOOO If 11 initial space at OXFFF00000 9 10 DBGC 0 1 Debug Pin Configurations PCMCIA channel II pin function s determined 00 RW by the value during Hard Reset If O0 the pins function as PCMCIA channel II pins I 01 the pins serve as Watch Points If 10 the pins are reserved If 11 the pins become show cycle attributes e g VFLS VF 11 12 DBPC 0 1 Debug Port Pin Configurations Location of the debug port pins 00 R W determined by the value during Hard Reset If O0 debug port pins found on the JTAG port If 01 the debug port is non existent If 10 reserved If11 the debug port is on PCMCIA channel II pins A MAIN power on reset i e when VDDH is powered to the MPC 22 Release 1 0 For More Information On This Product Go to www freescale com Freescale 5emiconductor INE Functional Descr
102. evi qea 6LV8 GINH at Ht LV 0038 Ln wi 9100015 EREIN 8IVg 6INH avi gly valve SINE ENT vi LS TAL iE 9955 8NH TAL ivi LV qvz3o8 8 Tr ivi 9 255 Siva NH IY 398 WNE T vean azen b heolaa anann onsane1 lt _ 0114 5 i TH EH YN EN Ww 2 i I TWEWPXEX ONO eg eg VENEA C zg lt cH a 9 91 Suig amod 2 2 5 8 8 me eii amp amp sa 9 sg HOLOFTASS NOILdO MS 8 im 8 im a uc anto anro a 8 3 m anro Tanto anro Tanto i 180 0 sso s99 290 sso ELdOMS a v3 e3 ZLdOMS PQ EQ HES ONO 1 1 LLdOMS l ENEA 01 d MS TLS 7 I SMS i d Suid amod PZZEOATHLNS EEA shen ie ola Release 1 0 96 For More Information On This Product Go to www freescale com Support Information FIGURE A 6 Flash amp DRAM Freescale emiepnductor ang Release 1 0 For More Information On This Product Go to www freescale com s
103. g for 32 bits is being read TABLE 4 6 SDRAM ADD and MPC852T Pin Correlations MPC8xx SDRAM A9 A10 BS1 BSO A11 A21 11 ROW A22 A29 8 Column MPC address bits A11 21 are mapped to MPC lines A19 29 as row addresses via the UPM Register AMx 0b000 Starting with the MPC line A21 connection to A8 SD and MPC A20 to A9 SD it is necessary to provide for the leftover row address A10 SD This is not done through use of MPC line A19 as that would show MPC A10 as a mul tiplexed row address but rather as described above by using GPLO In UPM Register MxMR the GPLO is pro grammed to show MPC A10 with complete row addressing In this case the SDRAM device has four banks On occasion a single 32 bit SDRAM bank does not provide enough application memory Connecting multiple 32 bit SDRAM based banks to the MPC852T is fairly straightforward as is extending the above noted interface The most significant row address bit MPC BS SD A10 is connected due to the 19 bit address size 8 11 address mul tiplex covered by the selected SDRAM device SDRAM devices with two BS lines BSO SD and BS1 SD must use the next address bit e g MPC A10 A9 in order to keep the memory mapping linear in all address lines are used for binary encoding of the bank selection 44 Release 1 0 For More Information On This Product Go to www freescale com Freescale 5emiconductor 16 Functional Description TABLE 4 7 SDRAM MPC C
104. gt e 9 Ep ocks amp zum S 2 Interrupts 59 E SPRAM Debug Port ytes 10 Pin Connector Debug Port Controllers EPP SPP FLASH g Upto 8MByte lt SCC4 ma 10BaseT A MPC852T Ethernet Zt Not Populated e EE R5 DRAM EDO bi s Upto 64 Mbyte SMC ac E EE mA _ BCSR N ej E lt j ie Na nO mA Expansion Connectors A a PCMCIA 5 Control amp E Expansion Buffering 6 Connectors x x BCSR Control ES IO Ports BG m 3 Fast MII Port D Ethernet d 4 Release 1 0 For More Information On This Product Go to www freescale com Freescale Semiconductor INE Hardware Preparation and Installation 2 Hardware Preparation and Installation 2e INTRODUCTION This chapter describes unpacking instructions hardware preparation and installation instructions for the MPC852TADS 2 2 UNPACKING INSTRUCTIONS NOTE If the shipping carton arrives damaged request that the carrier agent be present at the time of equipment unpacking and inspection Remove equipment from the shipping carton Consult the packing list and verify that all listed items are present Save the packing material in the instance that either storage or reshipment of the equipment should become necessary CAUTION AVOID TOUCHING AREAS OF INTEGRATED CIRCUITRY AS STATIC DISCHARGE CAN DAMAGE CIRCUITS 293 HARDWARE PREPARATION Prior to installation it may be necessary to change the DIP s
105. ia region CS3 For example RAS and CAS signal generation is performed using UPMA under the following condi tions normal access refresh cycles and during necessary address multiplexing CS2 and CS3 signals are split to two in order to overcome the capacitive load on the DRAM SIMM RAS lines Further each is buffered from the DRAM The DRAM module may be enabled disabled at any time by writing DRAMEN bit in the BCSRI See TABLE 4 A Peripherals and off board B After removal the BCSR cannot be accessed unless power is reapplied to the ADS Data line contention is avoided during read cycles D Normal being for example Single Read Single Write Burst Read amp Burst Write E Address multiplexing must take into account support for narrower bus widths 37 Release 1 0 For More Information On This Product Go to www freescale com 38 Freescale 5emiconductor INE Functional Description 11 BCSR1 Description Note The DRAM is not populated on the board As such users may populate their own DRAM in order to either expand memory or to run old SW that ran on the old MPC8xxFADS 4e6e DRAM 16 Bit Operation In order to enhance evaluation capabilities and achieve the best fit for application requirements support is given to DRAM s with 16 bit and 32 bit data bus widths A DRAM in 16 bit mode is only 50 in use For example only the memory portion connected to data lines D 16 31 is in use To configure the DRA
106. ig nificant LS address line connected to both the memory s A0 line and the MPC s A29 line If the port is reconfigure as a 16 bit port then the MPC s LS address line becomes A30 To maintain a linear address scheme all address lines connected to a memory must shift one bit This shift involves 40 Release 1 0 For More Information On This Product Go to www freescale com Freescale Semiconductor 1 Functional Description extensive multiplexing passive or active If a linear addressing scheme is not mandatory then only minimal multi plexing is required in order to support variable port widths In TABLE 4 4 below the ADS DRAM address connection scheme is presented TABLE 4 4 DRAM ADDRESS CONNECTIONS Width 32 Bit 16 Bit Depth Depth DRAMADD 4M 1M 4M 1M A0 BA29 BA29 BA29 BA29 A1 BA28 BA28 BA28 BA28 A2 BA27 BA27 BA27 BA27 A3 BA26 BA26 BA26 BA26 A4 BA25 BA25 BA25 BA25 A5 BA24 BA24 BA24 BA24 A6 BA23 BA23 BA23 BA23 A7 BA22 BA22 BA22 BA22 A8 BA21 BA21 BA21 BA21 A9 BA20 BA20 BA20 BA30 A10 BA19 BA30 The above table shows that the majority of address lines remain fixed Only two lines shaded cells required switch ing In FIGURE 4 2 DRAM Address Line Switching Scheme the noted switches are implemented by active multiplexers controlled by the BCSR1 Dram_Half_Word bit FIGURE 4 2 DRAM Address Line Switching Scheme DRAM BA 21 29 BA20 BA30
107. ion Sel Interconnect Signals The MPC852TADS interconnects with external devices via the following connectors 1 2 3 4 5 6 7 8 9 P1 P2 Expansion Connectors P3 P4 P6 P7 P8 P11 P15 Logic Analyzer Mictor Connectors P5 PCMCIA Port P9 P10 100 10Base T Ethernet Port Connectors RJ45 P12 External Debug Port Controller P13 12V Power In P14 External Clock Connector P16 2 1 mm Power Jack 5V Connector P17 RS232 Dual Port Connector 10 P18 P19 Altera programming ISP Connectors 11 P20 Parallel Host Port connector Se e P1 P2 Expansion Connectors P1 P2 are a 96 pin 90 DIN 41612 connectors that enable convenient expansion of the MPC s signals P1 contains A For FUTURE Use 66 Release 1 0 For More Information On This Product Go to www freescale com Freescale Semiconductor 1 Support Information buffered data 0 7 buffered address 16 31 and PCMCIA signals P2 contains the I O ports signals TABLE 5 1 P1 ADD Data and PCMCIA Expansion Connector Interconnect Signals Pin No Signal Name Attribute Description Al BWAITAb Wait Slot A PCMCIA signal for extending bus cycle A2 BVS1 Input Port A 0 Voltage Sense 1 buffered A3 BVS2 Input Port 1 Voltage Sense 2 buffered A4 BWP Input Port 2 Write Protect buffered 5 BCD2b Input Port A 3
108. iption TABLE 4 10 BCSRO0 Description BIT MNEMONIC PON FUNCTION DEF ATT 13 14 EBDF 0 1 External Bus Division Factor The factor for dividing the CLKOUT of the 00 RW MPC s external bus with respect to its internal MPC clock is determined by the value at Hard Reset If 00 then CLKOUT is GCLK2 divided by 1 If 01 then CLKOUT is GCLK2 divided by 2 15 Reserved Implemented 0 R W 16 31 Reserved Not Implemented a Reserved mnemonics may be read and written as any other field They are presented at their associated data pins during Hard Reset 4e11e 2 BCSRI Board Control Register 1 BCSRI serves as an ADS control register may be read or written at any time is accessible at offset 4 from the BCSR 53 Release 1 0 For More Information On This Product Go to www freescale com Freescale Semiconductor INE Functional Description base address and has defaults set at the time of power on reset TABLE 4 11 describes BCSRI fields TABLE 4 11 BCSR1 Description BIT MNEMONIC Function PON DEF ATT FLASH EN Flash Enable When active low the Flash Memory module is enabled on the local memory map When inactive the Flash memory is removed from the local memory map RW DRAM EN DRAM Enable When active low the DRAM module is enabled on the local memory map When inactive the DRAM is removed from the local memory map RW Reserv
109. isabling memory modules including the BCSRx via BCSRIP in favour of an external memory connected via the expansion connectors In this way with the associated local memory disabled a CS line may be used off board via the expansion connectors Local data transceivers do not open when a particular CS region has been disabled via BCSR1 This avoids possible contention over data lines TABLE 4 1 MPC852TADS Chip Select Assignment outlines an MPC chip select assignment for various ADS memories registers TABLE 4 1 MPC852TADS Chip Select Assignment Chip Select Assignment 50 Flash Memory 51 BCSR 52 DRAM Bank 1 CS3 DRAM Bank 28 54 SDRAM CS5 Unused user available CS 6 7 Unused user available a If existent 4 6 DRAM DRAM EDO is not supplied with the board Users may place their own DRAM EDO on U20 DRAM SIMM The MPC852TADS can operate with 4 MB of 60nsec delay EDO DRAM SIMM Support is provided for the following 5V powered FPM EDO DRAM SIMM configured as X32 up to 2 X 4M X 32 with 60 nsec or 70nsec delay All DRAM configurations are supported via the Board Control amp Status Register BCSR For example DRAM size 4M to 32M and delay 60 70 nsec are read from BCSR2 and the associated registers including the UPM are programmed accordingly DRAM timing control is performed by the MPC s UPMA via the CS2 region or in the instance of a dual bank SIMM v
110. mode of operation it must after power up be initialized by means of programming The programming is undertaken by issuing a Mode Register Set command that passes data along the SDRAM address lines to the Mode Register The UPM fully supports the noted command by means of a dedicated Memory Address Register as well as the UPM command run option Mode Register programming values are shown in TABLE 4 9 SDRAM Mode Register Programming In order to operate the SDRAM at speeds higher than 66Mhz read the application note at http e www motoro la com brdata PDFDB docs AN2066 pdf and further refer to both the MPC860COD09 MPC860 UPM Program ming Tool UPM860 and the MPC860COD10 UPM860 Manual for MPC860 UPM Programming Tool found on the following web page http e www motorola com webapp sps site prod_summary jsp code MPC860 amp no deId 01M98657 46 Release 1 0 For More Information On This Product Go to www freescale com 4 8 1 1 Freescale Semiconductor INE Functional Description TABLE 4 9 SDRAM Mode Register Programming Value Frequency SDRAM Option 50MHz 25MHz Burst Length 4 4 Burst Type Sequential Sequential CAS Latency 2 1 Write Burst Length Burst Burst SDRAM Initializing Procedure Following power up the SDRAM needs to be initialized in the manner outlined below 1 2 3 4 5 6 7 8 4oge2 Program the UPMB with the values noted in TABLE 3 9 UPMB Initializ
111. nal functional and general in formation The MPC852T is a Power PC architecture based derivative of Motorola MPC860 Quad Integrated Communication Controller PowerQuicc As such the MPC852TADS board is a derivative of the MPC866ADS It is designed to serve as a platform for both software and hardware development using the MPC852T processor On board resources and the associated debugger enable developers to perform a variety of tasks download and run code set breakpoints display memory and registers and connect proprietary h w via the expansion connectors All these features may be incorporated into a selected system using the MPC852T processor The MPC852TADS board may be used as a demonstration tool For example the application software may be burned into its flash memory and run in exhibitions 1 2 List of Abbreviations ADS MPC852TADS the document subject BCSR Board Control amp Status Register Ball Grid Array GPCM General Purpose Chip Select Machine e GPL General Purpose Line associated with UPM SIMM Single In line Memory Module User Programmable Machine 1 3 Related Documentation 866 Family User Manual Davicom 10 100Mbps Fast Ethernet DM9161E Transceiver IEEE Std 1284 1994 Standard 1 4 SPECIFICATIONS The MPC852TADS specifications are given in TABLE 1 1 TABLE 1 1 MPC852TADS Specifications CHARACTERISTICS SPECIFICATIONS Power
112. ne 2 28 PCCA1 PCMCIA Address line 1 29 PCCAO PCMCIA Address line 0 30 PCCDO PCMCIA Data line 0 31 PCCD1 PCMCIA Data line 1 32 PCCD2 PCMCIA Data line 2 33 CWP l PC Card Write Protect indication 34 GND Ground 35 GND Ground 36 CCD1b Card Detect 1 active low Indicates with CCD2b that a PC Card is correctly placed in a socket 37 PCCD11 PCMCIA Data line 11 38 PCCD12 PCMCIA Data line 12 39 PCCD13 PCMCIA Data line 13 40 PCCD14 PCMCIA Data line 14 41 PCCD15 PCMCIA Data line 15 42 BCE2Ab O PCMCIA Chip Enable 2 active low and enables ODD numbered address bytes 43 CVS1 Card Voltage Sense 1 indicates with CVS2 the Card s operational voltage 44 IORD VO Read active low and drives data bus during l O Card read cycles 45 IOWR Write active low and strobes data to the PC Card during I O Card write cycles 46 PCCA17 PCMCIA Address line 17 47 PCCA18 O PCMCIA Address line 18 48 PCCA19 PCMCIA Address line 19 49 PCCA20 PCMCIA Address line 20 50 PCCA21 PCMCIA Address line 21 51 PCCVCC PC Card 5V VCC is switched by the MPC852TADS via BCSR1 52 PCCVPP 12V 5V VPP for PC Card programming 12V only available if applied to P13 Controlled by the MPC852TADS via BCSR1 53 PCCA22 PCMCIA Address line 22 54 PCCA23 PCMCIA Address line 23 81 Release 1 0 For More Information On This Product Go to www freescale com
113. nnector s Signal Description with EPP I F Pin Signal 1 ATT a Description Mnemonic 1 Write Write signal Used to denote an address or data read or write operation between the host and the MPC852TADS 2 9 15 AD1 AD8 y o 8 bit Bidirectional Address Data Muxed Bus 10 IRQ Interrupt signal Used by the MPC852TADS to Interrupt the Host 11 Wait BUSY Wait signal Used by the MPC852TADS to acknowledge that the Data or Address transfer requested by the Host has completed 12 FREEZEO Connected to VFLSO via the Altera logic See 4 13 1 1 VFLS 0 1 on page 62 13 Select 5V_OUT This is the MPC852TADS 5V power supply which indicate to the debug station that the target processor is powered 14 Dstrobe Data Strobe signal Used by the Host to denote a Data cycle 15 FREEZE1 Connected to VFLS1 via the Altera logic See 4 13 1 1 VFLS 0 1 on page 62 16 Reset PP_RST signal Used by the Host to initiate a termination cycle to return the interface to the Compatible mode 17 Astrobe Address Strobe signal Used by the Host to denote an Address cycle 18 24 GND MPC852TADS Ground Plane 25 IN This is a mechanical signal On the Host side it is connected to GND When on the MPC852TADS side it will identify GND on this pin it is indicated that the Parallel connector was pluged a Signal attributes are with reference to the MPC852TADS TABLE 4 22 Parallel Host Port Conn
114. o support the use of resident debuggers made available to the ADS MPC peripherals and the debug port generate all other MPC interrupts internally The IRQO line routed as an NMI input is driven by an open drain gate in order to support external off board NMI generation In order that external hardware may also drive this line it is mandatory that the IRQO be driven by an open drain or open collector gate 4e3 Clock Generator Clocking the MPC on the MPC852TADS is done by using 10MHz Clock Generator Y2 connected to an EXTCLK input With 1 6 5 PLL mode SW4 1 2 Z OFE ON 66MHz of Clkout is achieved All MPC852TADS bus timings are referenced to the Clkout Clkout signal drives all other clocks in the system via necessary buffering Use is done with Crystal 3 3V zero delay buffer which is connected to 4 outputs very low output to output skew 250 ps clock splitter the CY2309ZC 1H to split the load between all various clock consumers on board 4e4 Buffering The ADS is also meant to serve as a hardware development platform As such it is necessary to buffer the MPC from the local bus in order to avoid wasting its capacitive drive capability and further in order that the MPC remain avail able for off board applications via the expansion connectors Buffers provide address and strobe lines while transceivers provide data Since the capacitive load over DRAM address lines may exceed 200 pF the DRAM address lines are buffere
115. olonpuooluueS e 101010 30v 30v 308 230 zao 308 S a zaia gt r Z p IH H Vz gz lt L 882 r a We 2 k ive SE Sve Ed Ed THU ive s o FH AE ve 994 sve Q saz m a g saz FH rae ve 5x EAE eve x ve v pve tg EAE eve 9 ZAE eve eve eae 59 eve cae Hd TH or sa realised we Ae ive ag eve 5 E 544 eve S cu SENA FAE Ive H3wOrvzze OATHLNS 8 g N tY 182 H3y rrzze OATHLNS 3uvds z N 8 xd E 2 L L aT eke eve im 8 dm 245 ove ZAZ eve so 9VI or 99 2 eve ke 1 85V sal 8 98 TESE 8 PAL PL evi vaL HV ea pal wi PED vi xg EVI eal 9n tI 781 EAI gvi TRI at TOU 281 xi 181 evi i aH Y X ivi tal 8 zal 1 Ivi gel een 3uvas 3uvas Vi are agen 1 1 1 7 s anto anro anro anro Janto Janto anto Janto anro anto Janto anro Marbesty Z 8920 690 490 s99 190 seo zeo veo 22 60 LO 60 ep9 eso b 9 Per ENEA ENEA ENEA RH D Eos 99 3uvds 3uvds 3uvas 3uvas 9 PE ny 9 20d 4S08 ie 4007 1353404 YAL VE gU wi 1 jeuondo se usog 0 199uuoO ZAL Wi E ursus K G38VN31 3Nu3Hi3 ost Y SHOH13 wan sm anto 2922 anto 4001 Marrestbs 9020 920 Odzezsu T 081 V ort 92
116. on TABLE 5 3 P3 Logic Analyzer Interconnect Signals MPC852T Pin Signal Name 32 A28 34 A29 36 A30 38 A31 TABLE 5 4 P4 Logic Analyzer Interconnect Signals Q c MPC852T Pin 5 Signal im Names 9 2 NC Q 4 NC 6 CE2Ab 8 PAO Q 10 PAI 12 ETHTXCK o 14 ETHRXCK 16 N C 18 NC 4 20 N C 22 NC 24 ETHTXD U 26 ETHRXD 28 RSTXD2 30 RSRXD2 32 N C 34 N C 36 N C 38 N C 75 Release 1 0 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 76 Freescale Semiconductor INE a Support Information TABLE 5 5 P6 Logic Analyzer Interconnect Signals MPC852T Pin Signal Name 2 N C 4 N C 6 TEAb 8 FCSb 10 BCSRCSb 12 DRMCS1b 14 DRMCS2b 16 SDRMCSb 18 CS5b 20 CS6b 22 CS7b 24 BSOAb 26 BS1Ab 28 BS2Ab 30 BS3Ab 32 WEOb 34 WE1b 36 WE2b 38 WE3b TABLE 5 6 P7 Logic Analyzer Interconnect Signals Pins MPC852T Signal Name N C N C ALEA ao O N IRQ2b IRQ3b 12 DPO For More Information On This Product Go to www freescale com Release 1
117. onnections 29 AO A29 21 28 1 28 20 27 2 27 19 26 26 18 25 A4 A25 17 24 5 24 16 2 A6 A23 A15 A22 A7 A22 14 21 8 1 20 9 12 GPLO A10 AP 11 A10 Note1 11 A10 9 BSO A10 Note1 A9 A8 Note 1 BS1 A9 Note If users want a larger SDRAM via a 16M A11 connection to A10 then note that this connection is existent in the board layout Users must connect BSO BS1 to MPC ADD A9 amp A8 This is achieved by removing R31 R28 resistors and assemble R30 R29 TABLE 4 8 Estimated SDRAM Performance Figures Number of System Clock Cycles System Clock Frequency MHz 50 254 Single Read 5 3 Single Write 3 1b 2 1b Burst Read 5 1 1 1 3 1 1 1 Burst Write 3 1 1 1 1 2 1 1 1 1 Refresh 21 13 a Up to 32MHz b One additional cycle for RAS precharge c Four beat refresh burst doesn t include arbitration overhead 45 Release 1 0 For More Information On This Product Go to www freescale com Freescale Semiconductor 16 Functional Description FIGURE 4 4 SDRAM Connection Scheme 54 CS GPL1 RAS GPL2 CAS GPL3 W 11 10 A 9 10 BS 1 0 A 20 29 9 0 SDRAMEN CKE SYSCLK CLK BSO B DQM3 BS1B __ pawe Eun DQM1 BS3 B DQ 31 0 D 0 31 4 8 1 SDRAM Programming To establish the SDRAM s
118. operation 42 Release 1 0 For More Information On This Product Go to www freescale com Freescale 5emiconductor 1 Functional Description TABLE 4 5 Flash Memory Performance Figures Number of System Clock Cycles System Clock Frequency MHz 50 25 Flash Delay nsec 90 120 90 120 Read Write Access Clocks 8 10 4 5 a Table figures refer to actual write access Write operations continue internally and the device has to be polled for operation completion The Flash module may be disabled enabled at any time by writing of 1 0 in the FlashEn bit in BCSRI 4 8 Synchronous DRAM Performance is enhanced particularly at higher operation frequencies by the board s 8 MB of SDRAM The SDRAM is unbuffered from the MPC bus and then configured as 4 X 512K X 32 with Micron or compatible MT48LC2M32B2 chips Removing buffers eliminates the delay associated with address and data buffers Due to the fact that only one memory chip is involved overall system performance is not affected The SDRAM doesn t reside on a SIMM rather it is soldered directly to the ADS pcb The SDRAM may be enabled disabled at any time by writing 1 0 to the SDRAM bit in BCSRI See TABLE 4 11 BCSR1 Description on page 54 SDRAM timing is controlled by the UPMB via its assigned CS line See TABLE 4 1 MPC852TADS Chip Select Assignment on page 37 Unlike a regular DRAM the synchronous DRAM ha
119. ot used then may be configured for alternate function 2 SRESET MPC s Soft Reset line active low and open drain 3 GND Ground 4 CON_DSCK y o Debug Serial Clock Over its rising edge the MPC samples from the DSDI signal the serial date Over its falling edge the DSDI is driven to the MPC and the MPC drives DSDO Configured on the MPC s JTAG port Output when debug port controller is on the local MPC Input when disconnected from the ADS 5 GND Ground 6 VFLS1 See VFLSO 7 HRESET MPC s Hard Reset line active low open drain 8 CON_DSDI Debug Port s Debug Serial Data In Configured on the MPC s JTAG port Output when debug port controller is on the local MPC Input when disconnected from the ADS 9 V3 3 3 3V Power indication indicatory line from which no significant power may be drawn 10 CON_DSDO y o MPC s Debug Serial Data Output Configured on the MPC s JTAG port Output when debug port controller is on the local MPC 5e e P13 12V Power In Connector The P13 is a 2 lead 2 part terminal block connector The P13 supplies when necessary programming voltage to the Flash SIMM and or to the PCMCIA TABLE 5 13 P13 12V Power In Interconnect Signals Pin ipti Number Signal Name Description 1 12V 12V input from an external power supply 2 GND GND line from an external power supply 84 Release 1 0 For More Information On This Product Go to
120. oted in the following sub sections 3e2e ABORT Switch SW2 The SW2 ABORT switch is used for aborting program execution This is done by issuing a level 0 interrupt to the MPC There is no resident debugger with the MPC852TADS As such if the ADS is in standalone mode it is the users responsibility to provide a means of handling the interrupt The Abort switch signal is debouncing and cannot be disabled by software 3e2e2 SOFT RESET Switch SW3 The SW3 SOFT RESET switch performs Soft Reset on the MPC internal modules while maintaining MPC configuration clock amp chip select Dram and SDram contents The switch signal is debouncing and cannot be disabled by software Upon completion of the Soft Reset sequence the Soft Reset configuration is sampled prior to becoming valid 3e2e3 HARD RESET Switches SW2 amp SW3 When both the SW2 and SW3 switches are depressed simultaneously then HARD RESET is generated on the MPC When the MPC undergoes Hard Reset it must be re initialized as its configuration is lost including data stored in the DRAM or SDRAM Upon completion of the Hard Reset sequence the Hard Reset configuration stored in BCSRO becomes valid 3 2 4 Modin Selection SW4 The on board clock source for the MPC is selected by SW4 The on board 10MHz crystal resonator connected between EXTAL and XTAL MPC pins becomes the clock source when SW4 1 2 ON ON or PON OFF and the ADS 15 powered up However when SW4 1 2
121. pports one clock modes 1 6 5 PLL operation via an on board clock generator In this mode MODCK 1 2 are driven with 10 during power on reset 4e e 2 Reset Configuration When the RSTCONF pin is asserted during a Hard Reset sequence the MPC data bus is sampled in order to achieve the MPC s Hard Reset configuration The reset configuration word is driven by the BCSRO register whose defaults are set during power on reset The BCSRO drives half of the configuration word i e data bits D 0 15 wherein the reserved bits are designated as RSRVxx It is possible to change the Hard Reset configuration by rewriting the BCSRO with new values The configuration change becomes valid after Hard Reset has been applied to the MPC The RSTCONF line on the ADS is always driven during Hard Reset As consequent example being the MPC s internal Hard Reset configuration defaults become unusable The following system parameters act as the BCSRO default address during power on reset and further are character ized as being driven at Hard Reset 1 Arbitration internal arbitration 1s selected 2 Interrupt Prefix the internal default is the interrupt prefix at OXFFF00000 It is overridden in order to pro vide an interrupt prefix address 0 located within the DRAM 3 Boot Disable Boot is enabled 4 Boot Port Size a boot port size of 32 bit is selected 5 Initial Internal Space Base directly following Hard Reset the internal space
122. quest To Send in the ADS this line is not connected e CTS O Clear To Send the ADS always asserts this line 4 9 2 Ethernet Port The MPC852TADS has an Ethernet port with T P 10 Base T I F connected to SCC4 Use is done by Davicom DM9161E The initial configuration of the DM9161E on the MPC852TADS is set by external resistors to 10 GPSI 7 Wired mode The DM9161E is able to interrupt the MPC via IRQ3 line Ethernet SCC4 pins are located at the expansion connectors in order to allow for alternative usage of the board s port expansion connector P2 4e9e3 FETHC Fast Ethernet Controller on Port D Fast Ethernet port with T P 100 Base T I F is provided on the MPC852TADS These port also support 10 Mbps 48 Release 1 0 For More Information On This Product Go to www freescale com Freescale Semiconductor INE Functional Description ethernet 10 Base T via the same transceiver the DM9161E by Davicom The DM9161E are connected to Port D via MII interface The initial configuration of the DM9161E on the MPC852TADS is set by external resistors to 100Base T Full Duplex in MII mode The DM9161E reset input is driven by either asserting the RSTMII bit in BCSR4 see TABLE 4 20 or by asserting a specific bit in an internal register via MII I F To allow external use of Port D their pins appear at the expansion connectors and the ethernet transceiver may be Disabled Enabled at any time via the MIIs MDIO port or
123. r is implemented in Altera Logic When using Serial Transfer mode Reset should be send via DB3 When using EPP transfer mode Reset should be send via nInit signal and then the Host computer should enter into A The Hard Reset button is not dedicated B For FUTURE Use 34 Release 1 0 For More Information On This Product Go to www freescale com Freescale 5emiconductor 16 Functional Description EPP negotiation mode 4 1 5 MPC Internal Sources On board reset logic drives with open drain gates the MPC s HRESET and SRESET open drain lines Correct operation of the internal reset sources of the MPC facilitates As a rule an internal reset source asserts HRESET and or SRESET for a 512 system clock time minimum With the exception of the Debug Port Soft Hard Resets it is beyond the scope of this document to describe all the internal reset sources 4 1 6 Reset Configuration During reset the MPC device samples the state of some external pins in order to determine operational modes and pin configurations The MPC has 3 reset levels each levels configurations are sampled 1 Power On Reset Configuration 2 Hard Reset Configuration 3 Soft Reset Configuration 4 1 1 Power On Reset Configuration The power on reset configuration is sampled prior to the external logic s negation of the PORESET Included in this configuration are pins MODCK 1 2 that determine the MPC clock operation mode The MPC852TADS su
124. requirements no other boards attached 5V DC 1 4 A typical 3 A maximum 12V DC I1A Microprocessor MPC852T running 66 MHz bus speed A Either on board or off board 1 Release 1 0 For More Information On This Product Go to www freescale com Freescale 5emiconductor INE General Information TABLE 1 1 MPC852TADS Specifications CHARACTERISTICS SPECIFICATIONS Addressing Total Address Range 4 GB Flash Memory 2 MB 32 bit wide expandable to 8 MB Dynamic RAM optional not populated Synchronous DRAM 4 MB 32 bit wide EDO SIMM optional support for up to 32 MB EDO or FPM SIMM 8 MB SDRAM Operating temperature 0 C 30 C Storage temperature 25 C to 85 C Relative humidity 5 to 90 non condensing Dimensions Length 9 173 233 mm Width 5 9 150 mm Thickness 0 063 1 6 mm 2 Release 1 0 For More Information On This Product Go to www freescale com Freescale 5emiconductor INE General Information 1 5 MPC852TADS Features MPC852TADS is compatible with the old MPC86xADS board The MPC852T when mounted on a BGA socket runs at 66 MHz bus frequency 8 MB unbuffered synchronous DRAM 4 MB EDO 60nsec delay DRAM SIMM Support for 4 32 MB FPM or EDO DRAM SIMM with Automatic DRAM SIMM identification 16 bit data bus width support The optional EDO DRAM will not be populated on board 2 MB Flash SIMM Support for up
125. roduct Go to www freescale com Release 1 0 Freescale Semiconductor INE Support Information TABLE 5 8 P11 Logic Analyzer Interconnect Signals MPC852T Pin Signal Name 38 D31 TABLE 5 9 P15 Logic Analyzer Interconnect Signals MPC852T ins Signal Name O 2 N C E 4 NC 6 NC 8 HRESETb 9 10 PP_AD7 a 12 PP_AD6 14 PP_AD5 Q 16 PP AD4 Hic 18 PP_AD3 20 AD2 o 22 PP ADI lt 24 PP_ADO 24 PP_BUSY_OUT o 28 PP RSTb ws 30 PP_ASTRb im 32 PP_DSTRb 34 BDM DSDO 36 NC 38 NC 79 For More Information On This Product Go to www freescale com Release 1 0 5 1 3 Freescale 5emiconductor INE Support Information P5 PCMCIA Port Connector P5 is a male 68 pin 90 PC Card port connector type The connector signals are presented in TABLE 5 10 P5 PCMCIA Connector Interconnect Signals below TABLE 5 10 P5 PCMCIA Connector Interconnect Signals Pin No Signal Name Attribute Description 1 GND Ground 2 PCCD3 PCMCIA Data line 3 3 PCCD4 PCMCIA Data line 4 4 PCCD5 PCMCIA Data line 5 5 PCCD6 PCMCIA Data line 6 6 PCCD7 PCMCIA Data line 7 7 BCE1Ab PCMCIA Chip Enable 1 a
126. rvation disabled SPKROUT Tri stated BS _ 0 3 and WE 0 3 are only driven on their dedicated pins GPL B5 enabled GPL A B 2 3 function as GPLs SYPCR FFFFFF88 Software watchdog timer count FFFF Bus monitor timing FF Bus monitor Enabled S W watch dog Freeze S W watch dog disabled S W watch dog if enabled causes NMI S W if enabled not prescaled TBSCR 00C2 No interrupt level Reference match indications cleared Interrupts disabled No freeze Time base disabled PISCR 0082 No level for interrupt request Periodic interrupt disabled Clear status Interrupt disabled FREEZE Periodic timer disabled 3ede Memory Controller Registers Programming The MPC852TADS memory controller is initialized for 66 MHz operation For example register programming is based on a 66 MHZ timing calculation an exception being the refresh timer that is initialized for 16 67Mhz The latter is the lowest frequency at which the ADS may begin to operate The ADS may be made to wake up at 25MHz but with inefficient initialization for there are too many wait states inserted As a consequence an additional set of ini tialization is provided in order to support an effective 25MHz operation The ADS is initialized at 66Mhz in order to allow for a proper though not efficient ADS operation via all available ADS clock frequencies A The refresh rate parameter is the only one initialized to the start up frequency Initialization to 66Mhz would h
127. s CS input in addition to RAS and CAS signals The SDRAM connection scheme is shown in FIGURE 4 4 on page 46 and the performance figures are available in TABLE 4 8 on page 45 The selected SDRAM has 2048 rows and 256 columns thus necessitating eleven row and eight column address lines TABLE 4 6 on page 44 below suggests a glueless interface between an MPC852T and the SDRAM In the case of a 32 bit bus one 32 bit SDRAM device is connected Control is driven by the UPMB on the MPC852T thus the SDRAM s CS is interfaced to CS4 on the MPC852T Any chip select line that excludes CSO is suitable A utilized SDRAM device s DOM signals select byte lanes and connect to the appropriate MPC852T Byte Strobe BS0 3 signals A10 SD connects to GPLO as it has the functionality to either drive an address on the line or define a level This is required for A10 SD acts as both an address line and a control line RAS and CAS are generated by GPL1 and GPL2 respectively The WE is generated by GPL3 CLK is driven by the MPC852T s CLKOUT signal a reference point with respect to the MPC852T s Memory Controller The BS lines are connected to MPC lines A10 and A9 and are used as high order address bits Note in the table below that the numbering scheme of the MPC852T address lines 43 Release 1 0 For More Information On This Product Go to www freescale com Freescale Semiconductor INE Functional Description differs from those of the SDRAM when address line mappin
128. s Connection P9 P10 The 10 100 Base T port connectors P9 and P10 are an 8 pin 90 receptacle RJ45 connectors The connection between the 10 100 Base T ports to the network is done by a standard cable The pinout of P9 and P10 is described in TABLE 5 11 P9 P10 100 10Base T Ethernet Port Interconnect Signals on page 83 2 4 4 BDM Debug Port Connector P12 Users may also control the board via the Bdm debug port connector Currently the majority of control SW use this connector via a command converter box connected to the PC parallel port FIGURE 2 10 BDM Debug Connector P12 VFLSO SRESET GND DSCK GND VFLSI HRESET DSDI V3 3 DSDO 2e4e5 12V Power Supply Connection P13 The MPC852TADS requires a 12 Vdc 1 A max power supply for either the PCMCIA channel Flash programming capability or the 12V programmable Flash SIMM As long as there is no need to program either a 12V programmable PCMCIA flash card or a 12V programmable Flash SIMM then the MPC852TADS works properly without a 12V power supply Connect the 12V power supply to connector P13 as shown below Release 1 0 For More Information On This Product Go to www freescale com 13 Freescale Semiconductor 16 Hardware Preparation and Installation FIGURE 2 11 12V Power Connector P13 10 2 412V P13 is a 2 terminal block power connector with power plug The plug is designed to accept 14 to 22 AWG wires though
129. s Product Go to www freescale com uctor Ing Freescale Semico Support Information L I 19908 ee KEW USM are Wvuas ev Jequn wiueumoog Sa v1zs80dW enu Ozi9r 918 eje zie ys jeXuous H pr I eiS Tof npuooluuss e 01010 FIGURE A 4 SDRAM ieoa g gt pa quiessy 829 159 8V pejoeuuoo SI gy oed LEH 058 6V 62d jou SI OLY Auojoey eig uor3do ATO edep mWwvuqs pejquiessy 8geH 1589 6V WVHGS 8IA9110 uondo 0 H E Horea W8 104 pa quessy Led 059 OIV lev 159 LV8 01 papauuoo fubioe4 WvHOS WB 104 T 3 Q YXWZ W WHOS SNe lt lt lt lt lt lt lt SESE 60865886 SON by son 5 OE 058 BON HS z zon 8 04 39 yy N3nvaas ov ony X zr Tosxsa lt 1 ova oi 0 V WYHOS W8 104 So SINET SVE Pet 4300039 Wo BE Gedo T EXED enoa 55 TOM reuzgzewzonviw WOO Maz LIEN L LEI Sr ez 159 058 I 4 01 OT V 92 90795 WHO Anko 1810 anoo anro
130. sh burst MB322BT08TASN60 30A21114 Refresh clock divided by 30 Periodic timer enabled Type 2 address multiplexing scheme 2 cycle disable timer GPL4 disabled for data sampling edge flexibility 1 loop read 1 loop write 4 beats refresh burst MB324CTOOTBSN60 60B21114 Refresh clock divided by 60 Periodic timer enabled Type 3 address multiplexing scheme 2 cycle disable timer GPL4 disabled for data sampling edge flexibility 1 loop read 1 loop write 4 beats refresh burst MB328CTOOTBSN60 30B21114 Refresh clock divided by 30 Periodic timer enabled Type 3 address multiplexing scheme 2 cycle disable timer GPL4 disabled for data sampling edge flexibility 1 loop read 1 loop write 4 beats refresh burst MBMR KS643232C TC60 42802114 Refresh clock divided by 42 Periodic timer enabled Type 0 address multiplexing scheme 2 cycle disable timer GPL4 enabled 1 loop read 1 loop write 4 beats refresh burst a BR3 is not initialized for MB321xx or MB324xx EDO DRAM SIMMs b Assuming 16 67MHz BRGCLK 30 Release 1 0 For More Information On This Product Go to www freescale com Freescale Semiconductor 16 OPERATING INSTRUCTIONS TABLE 3 8 UPMA Initialization for 0 EDO DRAMs 20MHz Cycle Type Single Read Burst Read Single Write Burst Write Refresh Exceptions Offset in
131. st Of Figures MPC852TADS Block Diagram MPC852TADS Top Side Part Location Diagram MPC852TADS Bottom Side Part Location Diagram MPC TOP VIEW Clock Source Selection J1 Modin Selection SW4 S W Option SW5 Host Controlled Operation Scheme with External Command Converter Host Controlled Operation on board Command Converter schem Standalone operation schem BDM Debug Connector P12 12V Power Connector P13 P16 5V Power Connector RS 232 Serial Port Connectors P17A amp P17B Parallel host connector with EPP I F P20 Parallel host connector in serial mode P20 Memory SIMM Installation Refresh Scheme DRAM Address Line Switching Scheme Flash Memory SIMM Architecture SDRAM Connection Scheme PCMCIA Port Configuration Standard BDM Debug Port Connector MPC852TADS Power Scheme Bus Config Diagram Table of Contents MPC852T SDRAM Buffers Flash amp DRAM PCMCIA I F Devices Power Power Fast Ethernet amp Ethernet RESET amp INDICATORS BCSR RS232 amp CLOCK LOGIC ANALYZER EXPANSION CONNECTROS HOST I F BDM BUS SWITCH For More Information On This Product Go to www freescale com Release 1 0 Freescale 5emiconductor 1 Release 1 0 For More Information On This Product Go to www freescale com Freescale 5emiconductor INE General Information l1 General Information Je MPC852TADS Introduction and Goals This operation guide for the MPC852TADS board contains operatio
132. t 4 3 Encoding BCSR3 Description FLASH Presence Detect 7 5 Encoding BCSR4 Description Parallel Host Port Connector s Signal Description with EPP I F Parallel Host Port Connector s Signal Description with Serial Command Converter I F EPP Register Interface Off board Application Maximum Current Consumption P1 ADD Data and PCMCIA Expansion Connector Interconnect Signals P2 I O Port Expansion Interconnect Signals P3 Logic Analyzer Interconnect Signals P4 Logic Analyzer Interconnect Signals P6 Logic Analyzer Interconnect Signals P7 Logic Analyzer Interconnect Signals P8 Logic Analyzer Interconnect Signals Release 1 0 For More Information On This Product Go to www freescale com 21 21 23 24 26 28 29 31 32 33 37 39 39 41 43 44 45 45 47 52 54 55 55 56 56 56 57 58 58 58 60 60 61 64 67 71 74 75 76 76 77 Freescale 5emiconductor 16 P11 Logic Analyzer Interconnect Signals P15 Logic Analyzer Interconnect Signals P5 PCMCIA Connector Interconnect Signals P9 P10 100 10Base T Ethernet Port Interconnect Signals P12 External Debug Port Controller Input Interconnect Signals P13 12V Power In Interconnect Signals P17B RS232 Interconnect Signals P18 P19 JTAG connector for Altera programing MPC852TADS Part List VI For More Information On This Product Go to www freescale com Release 1 0 78 79 80 83 84 84 85 86 87 Freescale 5emiconductor 16 Li
133. t Computer Parallel Port P17A Down RS232 1 Connector to Host Computer 1 Port 13 Run Turn on the 5V power supply and verify LD8 LD14 LD15 LD17 LD18 Leds on board lit up MOTOROLA MPC852TADS Quick Start User s Manual For More Information On This Product Go to www freescale com MOTOROLA Freescale Semiconductor Inc MPC852TADS Quick Start User s Manual For More Information On This Product Go to www freescale com B Freescale 5emiconductor 16 Table Of Contents General Information MPC852TADS Introduction and Goals List of Abbreviations Related Documentation SPECIFICATIONS MPC852TADS Features Hardware Preparation and Installation INTRODUCTION UNPACKING INSTRUCTIONS HARDWARE PREPARATION MPC Replacement of U1 Clock Source Selection J1 Modin Selection SW4 Software Option SW5 INSTALLATION INSTRUCTIONS Host Controlled Operation Standalone Operation 10 100 Base T Ethernet Ports Connection P9 P10 BDM Debug Port Connector P12 12V Power Supply Connection P13 5V Power Supply Connection P16 Terminal to MPC852TADS RS 232 Connection P17 Parallel Host Connector in EPP I F P20 Memory Installation OPERATING INSTRUCTIONS INTRODUCTION CONTROLS AND INDICATORS ABORT Switch SW2 SOFT RESET Switch SW3 HARD RESET Switches SW2 amp SW3 Modin Selection SW4 Software Options Switch SW5 Power On RESET Switch SW6 GND Bridges Ethernet 10Base T ETH TX RX LD1 Ethernet Full D
134. t called SPP See TABLE 4 23 EPP Register Interface below TABLE 4 23 EPP Register Interface Port name I O MAP Address Mode Read Write Description SPP Data Port Base 0 SPP EPP w Standard SPP Data Port SPP Status Port Base 1 SPP EPP R Reads the input status lines on the interface SPP Control Port Base 2 SPP EPP W Sets the state of the Output Control lines EPP Address Port Base EPP R W Generates Address Read or Write Cycle EPP Data Port Base 4 EPP R W Generates Data Read or Write Cycle Not Defined Base 5 to Base 7 EPP N A Not Available a IBM PC defines two standard port base addresses 0x378 or 0x278 When both Parallel connector P20 and BDM Debug Connector P12 are connected priority will be to on board serial command converter or EPP transfer mode via P20 Default host selection is SPP Transfer Mode When the Host computer will begin an EPP negotiation access MPC852TADS will switch to EPP Transfer Mode For EPP negotiation please refer to IEEE 1284 EPP Protocol 61 Release 1 0 For More Information On This Product Go to www freescale com Freescale 5emiconductor 1 Functional Description 413 BDM Debug Port The MPC852TADS has a BDM Debug interface 10 pin generic header connector to enable debugging through external host The signals are described in detail in FIGURE 4 6 Standard BDM Debug Port Connector below FIGURE 4 6 Standard BDM Debug Port
135. to 8 MB 5V or 12V Programmable with Automatic Flash SIMM identification Can be changed up to 8MB Optional Hard Reset Configuration Burned in Flash Dual RS232 port Fast Ethernet connection to Port D using Davicom DM9161E 10 Base T Port On board using Davicom DM9161E Memory Disable Option for every local memory map slave Board Control amp Status Register 5 BCSR controlling board operation External Tool Identification Capability via BCSR Programmable Hard Reset Configuration via BCSR 5V only PCMCIA Socket with full buffering power control and port disable options Complies with PCMCIA 2 1 Standard Module Enable Indications in order to control external peripherals expansion connectors include all the CPM ports amp bus signals On board Debug Port Controller amp EPP SPP Interface Push button for Soft Hard P Reset ABORT button Single 5V supply Reverse Over Voltage Protection for Power Inputs 3 3V VDDH and 1 8V VDDL are supplied for MPC852T A Flash burning available only if also supported on the MPC852T B To activate hard reset press BOTH the soft reset amp ABORT buttons C Use 5V single supply unless a 12V supply is required for a PCMCIA card or a 12V programmable Flash SIMM Release 1 0 For More Information On This Product Go to www freescale com Freescale Semiconductor 1 General Information FIGURE 1 1 MPC852TADS Block Diagram N gt 58
136. tor MPC852TADS Parts Listing Schematics HI Release 1 0 For More Information On This Product Go to www freescale com 51 51 52 53 55 57 58 59 61 62 62 62 62 62 62 63 63 63 65 65 65 66 66 66 74 80 82 83 84 85 85 85 85 86 87 91 IV Freescale 5emiconductor 1 For More Information On This Product Go to www freescale com Release 1 0 Freescale 5emiconductor 16 List Of Tables MPC852TADS Specifications Power ON Reset DPLL Configuration Memory Map in MP852TADS New Mode Memory Map in MPC852TADS Compatible Mode SIU REGISTER PROGRAMMING Memory Controller Initialization For 66Mhz with DRAM EDO Memory Controller Initialization For 66Mhz with No DRAM EDO UPMA Initializations for 0 DRAMs 66MHz Memory Controller Initializations For 20Mhz UPMA Initializations for 60nsec EDO DRAMs 20MHz UPMB Initialization for KS643232C TC60 upto 32MHz UPMB Initialization for KS643232C TC60 322 MHz 50MHz MPC852TADS Chip Select Assignment Regular DRAM Performance Figures EDO DRAM Performance Figures DRAM ADDRESS CONNECTIONS Flash Memory Performance Figures SDRAM ADD and MPC852T Pin Correlations SDRAM MPC Connections Estimated SDRAM Performance Figures SDRAM Mode Register Programming BCSRO Description BCSRI Description PCCVCC 0 1 Encoding PCCVPP 0 1 Encoding BCSR2 Description Flash Presence Detect 4 1 Encoding DRAM Presence Detect 2 1 Encoding DRAM Presence Detec
137. uplex Indicator LD2 Ethernet LINK Indicator LD3 Fast Ethernet 100Mbps Indicator LD4 Fast Ethernet 10 100Base T TX RX LD5 Fast Ethernet Full Duplex Indicator LD6 Fast Ethernet LINK Indicator LD7 Ethernet 10 ETH ON LD8 RS232 Port 2 ON LD9 For More Information On This Product Go to www freescale com Release 1 0 GO CA NN Q i e O NO NO OO 1 1 1 1 A 200 LES L tD CO Freescale 5emiconductor 16 Fast Ethernet 10 100Base T ON LD10 RS232 Port 1 ON LD12 PCMCIA ON LD13 FLASH ON LD14 DRAM ON LD15 SGLAMP ON LD16 SDRAM ON LD17 5V Indicator LD18 RUN Indicator LD19 EPP Indicator LD20 SPP Indicator LD21 MEMORY MAP MPC Register Programming Memory Controller Registers Programming Functional Description Reset amp Reset Configuration Regular Power On Reset Manual Soft Reset Manual Hard Reset Host Hard Reset through on board command converter MPC Internal Sources Reset Configuration Power On Reset Configuration Hard Reset Configuration Soft Reset Configuration Local Interrupter Clock Generator Buffering Chip Select Generator DRAM DRAM 16 Bit Operation DRAM Performance Figures Refresh Control Variable Bus Width Control Flash Memory SIMM Synchronous DRAM SDRAM Programming SDRAM Initializing Procedure SDRA
138. v2 qias3us xa Led X 2159 EZI aL 3838H 990 06 SHE Xinia 9 85 RV g oT oO oO zg 12D S d au S 9m D sx 2 4908 91 XUSH 9118 S 84 0115 zidd DONDAN Ch et Iv Da gm gt 0115 109 S m ur on d 919187 919 vidd OXY II Mi SIV oa EIU 91915 evi eal 708 YIV wd Moxua OL vee ed Sag dx3 val sag Evd Sper 2 ag dx ivi tar 2 of Fama 109 dX ei zat L oa 9 008 o4 o of ev Spe Fa lig 0 ag 8v 809 X A ei Pead SRigusy el wren V 60d EL Sead Qxisu Sv 0109 oum 0795 gt zNasuu 9197 ridd szad T T of WS o eH 9 Lys Lys fanto Janto Janto Ved aza sco seo SOA SOA 2 ie z ENEA T z 3 7 T s Release 1 0 For More Information On This Product Go to www freescale com 106 uctor eng Freescale Semico Support Information FIGURE A 16 HOST I F H I z Ze 9L Pag 100982 Kepss ups M sred kon AN LSOH ev wiweumoog ez SQ V1zs80dW E ees Jeans 1yuous _
139. valid bank MT16D832X 6 7 BR4 K4S643232 TC60 0x000000C1 Base at 0x0 on UPMB MPC86x New Mode OR4 OxFC800A00 4 MB block size all types access initial address MPC86x multiplexing according to AMB New Mode MPTPR All Dram SIMMs 0400 Divide by 16 decimal supported 26 Release 1 0 For More Information On This Product Go to www freescale com Freescale Semiconductor 16 OPERATING INSTRUCTIONS TABLE 3 5 Memory Controller Initialization For 66Mhz with No DRAM EDO Register Device Type Init Value hex Description MAMR MB321BTO8TASN60 40A211142 Refresh clock divided by 40 or 600 or C0 Periodic 60A21114 timer enabled Type 2 address multiplexing scheme 2 C0A21114 cycle disable timer GPL4 disabled for data sampling edge flexibility 1 loop read 1 loop write 4 beats refresh burst MB322BT08TASN60 20A211142 Refresh clock divided by 20 or 30 or 60 Periodic 30A21114 timer enabled Type 2 address multiplexing scheme 2 60A21114 cycle disable timer GPL4 disabled for data sampling edge flexibility 1 loop read 1 loop write 4 beats refresh burst MB324CTOOTBSN60 408211148 Refresh clock divided by 40 or 60 or CO Periodic 608211140 timer enabled 3 address multiplexing scheme 2 COB21114 cycle disable timer GPL4 disabled for data sampling edge flexibility 1 loop read 1 loop write 4 beats refresh burst MB328CTOOTBSN60 208211142 Refresh clock divided by 208
140. w N C o sv our O 20409 Memory Installation The MPC852TADS has two types of memory SIMM Dynamic Memory SIMM will not be populated only the socket will be soldered Flash Memory SIMM Installation of a memory SIMM remove from packaging place diagonally in its socket difficult to err as the Flash socket has 80 contacts while the DRAM socket only has 72 twist to a vertical position until the metal lock clips are locked See FIGURE 2 16 Memory SIMM Installation 15 Release 1 0 For More Information On This Product Go to www freescale com 16 Freescale Semiconductor 16 Hardware Preparation and Installation CAUTION Near the 1 pin the memory SIMMs have an alignment nibble It is essential to correctly align the memory before twisting as damage may result to both the memory SIMM and its socket FIGURE 2 16 Memory SIMM Installation 1 2 Memory SIMM Metal Lock Clip a SIMM Socket For More Information On This Product Go to www freescale com Release 1 0 Freescale Semiconductor NF 1 101 OPERATING INSTRUCTIONS 3 OPERATING INSTRUCTIONS 3 1 INTRODUCTION Information necessary for using the MPC852TADS in both host controlled and standalone configurations is detailed in this chapter The information includes controls and indicators memory map details and board software initialization 3e2 CONTROLS AND INDICATORS The MPC852TADS features the switches and indicators n
141. w freescale com 107 Freescale 5emiconductor INE Support Information FIGURE A 17 BDM BUS SWITCH Rev PILOT MOTOROLA BDM BUS SWITCH Sheet 17 of 17 1 emiconductarisrael LTD le Wedn esday May 28 2003 all 55 bj 3 aS aj 2 7 2 EE E AA Box Hinr edic E amp On x o E 9 o oO o E 00000 86 8 Q y zz 2 5 a 6 86 8 S gw m 8 2 u z8 5 EI Hu zl Qi 2 8 a 8 9 9 9 J aaa 3 m a zz a a a 108 Release 1 0 For More Information On This Product Go to www freescale com Freescale 5emiconductor INE Support Information 109 Release 1 0 For More Information On This Product Go to www freescale com Freescale 5emiconductor INE Support Information 110 Release 1 0 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc HOW TO REACH US World Wide Web Address Motorola http www motorola com General index html Information in this document is provided solely to enable system and software implementers to use Motorola products There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits base
142. witch settings or jumpers in order to achieve both the desired configuration and ensure proper operation of the MPC852TADS board FIGURE 2 1 MPC852TADS Top Side Part Location Diagram illustrates the location of the switches LEDs DIP switches jumpers and connectors The factory tested boards are delivered with default DIP switch settings The default settings are described in the para graphs below Parameters relating to the below listed features may be changed MPC Clock Source Host Controlled Operation e PCMCIA Enable e MPC I O port connected to Expansion Connector Release 1 0 For More Information On This Product Go to www freescale com s x mace E xa lu T 2 N 5 alt dS ue _ s 9 i5 wa A a FO d x tt 6 o m OB a O w meo m E gt ce z Freescale Semiconductor 16 Hardware Preparation and Installation FIGURE 2 1 MPC852TADS Top Side Part Location Diagram
143. y be used off board via the expansion connectors 3e2e620 FLASH ON 1 14 The yellow FLASH ON LED indicates that the FLASH SIMM has been enabled in the BCSR1 register For example accessing the CSO address space will hit the Flash memory When unlit the Flash has been disabled 3e2e21 DRAM ON LDIS The yellow DRAM ON LED indicates that the DRAM SIMM has been enabled in BCSRI and that accessing CS2 or CS3 will hit on the DRAM When unlit the DRAM has been disabled in BCSRI 302022 SGLAMP ON LD16 The green SGLAMP LED indicates that this signal is active low When inactive there is no LED light The LED is used for software signalling Controlling the led is done via BCSRA 3 19 Release 1 0 For More Information On This Product Go to www freescale com Freescale Semiconductor 16 OPERATING INSTRUCTIONS Je223 SDRAM ON LD17 The yellow SDRAM ON LED indicates that the SDRAM has been enabled in BCSRI and that accessing CS4 will hit on the SDRAM When unlit the SDRAM has been disabled in BCSRI 302024 5V Indicator 1 218 The green 5V LED indicates the presence of a 5V supply at P16 3e2e25 RUN Indicator LD19 The green RUN LED indicates that the MPC isn t in debug mode 3e2e26 Indicator LD204 The yellow Enhanced Parallel Port connection LED indicates that the board is connected directly to the Pc s parallel port using EPP transfer mode and the BDM Debug connector P12 is irrelevant 3 227 SPP Indi

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