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C164CI - USBid

1. C164Cl Name Physical 8 Bit Description Reset Address Address Value DP3 b FFC6 E3y Port 3 Direction Control Register 00004 P4 b FFC8 E44 Port 4 Register 8 bits 004 DP4 b FFCA E5y Port 4 Direction Control Register 00H P8 b FFD44 EAy Port 8 Register 8 bits 004 DP8 b FFD6 EBu Port 8 Direction Control Register 00H 1 The system configuration is selected during reset 2 Semiconductor Group The reset value depends on the indicated reset source 23 15 Version 1 0 11 97 SIEMENS The Register Set C164CI 23 4 Special Notes PEC Pointer Registers The source and destination pointers for the peripheral event controller are mapped to a special area within the internal RAM Pointers that are not occupied by the PEC may therefore be used like normal RAM During Power Down mode or any warm reset the PEC pointers are preserved The PEC and its registers are described in chapter Interrupt and Trap Functions GPR Access in the ESFR Area The locations 00 F000H 00 F01EH within the ESFR area are reserved and allow to access the current register bank via short register addressing modes The GPRs are mirrored to the ESFR area which allows access to the current register bank even after switching register spaces see example below MOV R5 DP3 GPR access via SFR area EXTR 1 MOV R5 ODP3 GPR access via ESFR area Writing Bytes to SFRs All special function registers may be ac
2. Register Name Long Short Address Reset Value Notes T14 FOD2y 69 UUUU Prescaler timer generates input clock for RTC register and periodic interrupt T14REL FODO 684 UUUU Timer reload register RTCH FOD6 6B UUUU High word of RTC register RTCL FOD4 6Ay UUUUH Low word of RTC register Note The RTC registers are not affected by a reset After a power on reset however they are undefined Semiconductor Group 14 1 Version 1 0 11 97 SIEMENS The Real Time Clock C164CI T14REL Request Figure 14 2 RTC Block Diagram System Clock Operation A real time system clock can be maintained that keeps on running also during idle mode and power down mode optionally and represents the current time and date This is possible as the RTC module is not effected by a reset The maximum resolution minimum stepwidth for this clock information is determined by timer T14 s input clock The maximum usable timespan is achieved when T14REL is loaded with 0000 and so T14 divides by 216 Cyclic Interrupt Generation The RTC module can generate an interrupt request whenever timer T14 overflows and is reloaded This interrupt request may eg be used to provide a system time tick independent of the CPU frequency without loading the general purpose timers or to wake up regularly from idle mode The interrupt cycle time can be adjusted via the timer T14 reload register T14REL Please refer to RTC I
3. Read P8 y Alternate Latch Data Input Alternate Pin Data Input Y i P8 y Output CCzIO Buffer y 0 7 z 16 23 MCB01988 Figure 7 16 Block Diagram of Port 8 Pins Semiconductor Group 7 26 Version 1 0 11 97 Dedicated Pins C164CI SIEMENS 8 Dedicated Pins Most of the input output or control signals of the functional the C164Cl are realized as alternate functions of pins of the parallel ports There is however a number of signals that use separate pins including the oscillator special control signals and of course the power supply The table below summarizes the 21 dedicated pins of the C164Cl Pin s Function ALE Address Latch Enable RD External Read Strobe WR WRL External Write Write Low Strobe VPP EA External Access Enable and External Programming Voltage NMI Non Maskable Interrupt Input XTAL1 XTAL2 Oscillator Input Output RSTIN Reset Input RSTOUT Reset Output VAREF VAGND Power Supply for Analog Digital Converter VDD VSS Digital Power Supply and Ground 5 pins each The Address Latch Enable signal ALE controls external address latches that provide a stable address in multiplexed bus modes ALE is activated for every external bus cycle independent of the selected bus mode When an external bus is enabled one or more of the BUSACT bits set also X Peripheral accesses will generate an active ALE signal A
4. Figure 10 5 Block Diagram of Core Timer T3 in Counter Mode GPT1 Core Timer T3 Counter Mode Input Edge Selection T3I Triggering Edge for Counter Increment Decrement 000 None Counter T3 is disabled 001 Positive transition rising edge on T3IN 010 Negative transition falling edge on T3IN 011 Any transition rising or falling edge on T3IN 1XX Reserved Do not use this combination For counter operation pin T3IN must be configured as input ie the respective direction control bit DPx y must be 0 The maximum input frequency which is allowed in counter mode is fopy 16 To ensure that a transition of the count input signal which is applied to T3IN is correctly recognized its level should be held high or low for at least 8 fcpy cycles before it changes Semiconductor Group 10 7 Version 1 0 11 97 SIEM ENS The General Purpose Timer Unit C164Cl Timer 3 in Incremental Interface Mode Incremental Interface mode for the core timer T3 is selected by setting bit field T3M in register T3CON to 110p In incremental interface mode the two inputs associated with timer T3 TSIN T3EUD are used to interface to an incremental encoder T3 is clocked by each transition on one or both of the external input pins which gives 2 fold or 4 fold resolution of the encoder input T3I Edge detect T3R T3UDE Figure 10 6 Block Diagram of Core Timer T3 in Incremental Interface Mode B
5. 6 Clock Generation All activities of the C164Cl s controller hardware and its on chip peripherals are controlled via the system clock signal fcpy This reference clock is generated in three stages see also figure below Oscillator The on chip Pierce oscillator can either run with an external crystal and appropriate oscillator circuitry or it can be driven by an external oscillator e Frequency Control The input clock signal feeds the controller hardware directly providing phase coupled operation on not too high input frequency divided by 2 in order to get 5096 duty cycle clock signal Via an on chip phase locked loop PLL providing maximum performance on low input frequency Via the Slow Down Divider SDD in order to reduce the power consumption The resulting internal clock signal is referred to as CPU clock fopy e Clock Drivers The CPU clock is distributed via separate clock drivers which feed the CPU itself and two groups of peripheral modules The RTC is fed with the prescaled oscillator clock via a separate clock driver so it is not affected by the clock control functions Idle mode CPU Prescaler PCDDIS PLL p Peripherals Ports Intr Ctrl SDD Interfaces P D mode RTC Figure 6 1 CPU Clock Generation Stages Semiconductor Group 6 1 Version 1 0 11 97 SIEMENS Clock Generation C164CI 6 1 Oscillator The main oscillator of the C164Cl is a power optimized Pierce oscil
6. Old Stack Area Old SP p Newly Allocated Register Bank Old CP Contents p A New LLL Stack Area Figure 22 2 Local Registers The software to provide the local register bank for the example above is very compact After entering the subroutine SUB SP id 10D Free 5 words in the current system stack SCXT CP SP Set the new register bank pointer Before exiting the subroutine POP CP Restore the old register bank ADD SP 10D Release the 5 words P O0f the current system stack Semiconductor Group 22 10 Version 1 0 11 97 SIEMENS System Programming C164CI 22 4 Table Searching A number of features have been included to decrease the execution time required to search tables First branch delays are eliminated by the branch target cache after the first iteration of the loop Second in non sequentially searched tables the enhanced performance of the ALU allows more complicated hash algorithms to be processed to obtain better table distribution For sequentially searched tables the auto increment indirect addressing mode and the E end of table flag stored in the PSW decrease the number of overhead instructions executed in the loop The two examples below illustrate searching ordered tables and non ordered tables respectively MOV RO BASE Move table base into RO LOOP CMP R1 RO Compare target to table entry JMPR cc SGT LOOP Test whether target has not been found Note Th
7. Semiconductor Group 19 15 Version 1 0 11 97 SIEMENS The On Chip CAN Interface C164CI Arbitration Registers The Arbitration Registers are used for acceptance filtering of incoming messages and to define the identifier of outgoing messages A received message is stored into the valid message object with a matching identifier and DIR 0 data frame or DIR 1 remote frame Extended frames can be stored only in message objects with XTD 1 standard frames only in message objects with XTD 0 For matching the corresponding global mask has to be considered in case of message object 15 also the Mask of Last Message If a received message data frame or remote frame matches with more than one valid message object it is stored into that with the lowest message number When the CAN controller stores a data frame not only the data bytes but the whole identifier and the data length code are stored into the corresponding message object standard identifiers have bits ID17 0 filled with O This is implemented to keep the data bytes connected with the identifier even if arbitration mask registers are used When the CAN controller stores a remote frame only the data length code is stored into the corresponding message object The identifier and the data bytes remain unchanged There must not be more than one valid message object with a particular identifier at any time If some bits are masked by the Global Mask Register
8. A D Converter For analog signal measurement a 10 bit A D converter with 8 multiplexed input channels and a sample and hold circuit has been integrated on chip It uses the method of successive approximation The sample time for loading the capacitors and the conversion time is programmable and can so be adjusted to the external circuitry Overrun error detection protection is provided for the conversion result register ADDAT either an interrupt request will be generated when the result of a previous conversion has not been read from the result register at the time the next conversion is complete or the next conversion is suspended in such a case until the previous result has been read For applications which require less analog input channels the remaining channel inputs can be used as digital input port pins The A D converter of the C164Cl supports four different conversion modes In the standard Single Channel conversion mode the analog level on a specified channel is sampled once and converted to a digital result In the Single Channel Continuous mode the analog level on a specified channel is repeatedly sampled and converted without software intervention In the Auto Scan mode the analog levels on a prespecified number of channels are sequentially sampled and converted In the Auto Scan Continuous mode the number of prespecified channels is repeatedly sampled and converted In addition the conversion of a specific channel can be
9. SIEMENS Power Management C164Cl These three means described above can be applied independent from each other and thus provide a maximum of flexibility for each application For the basic power reduction modes Idle Power Down there are dedicated instructions while special registers control clock generation SYSCONZ2 and peripheral management SYSCONS Two different general power reduction modes with different levels of power reduction have been implemented in the C164Cl which may be entered under software control In Idle mode the CPU is stopped while the enabled peripherals continue their operation Idle mode can be terminated by any reset or interrupt request In Power Down mode both the CPU and the peripherals are stopped The real time clock and its selected oscillator may optionally be kept running Power Down mode can only be terminated by a hardware reset Note All external bus actions are completed before Idle or Power Down mode is entered However Idle or Power Down mode is not entered if READY is enabled but has not been activated driven low during the last bus access In addition the power management selects the current CPU frequency and controls which peripherals are active During Slow Down operation the basic clock generation path is bypassed and the CPU clock is generated via the programmable Slow Down Divider SDD from the selected oscillator clock signal Peripheral Management disables and enables th
10. if mapped to segment 1 are redirected to the special Boot ROM Data fetches access will access the internal code memory of the C164CI if any is available but will return undefined data on ROMless devices Exiting Bootstrap Loader Mode In order to execute a program in normal mode the BSL mode must be terminated first The C164Cl exits BSL mode upon a software reset ignores the level on POL 4 or a hardware reset POL 4 must be high then After a reset the C164Cl will start executing from location 00 0000 of the internal ROM or the external memory as programmed via pin EA Choosing the Baudrate for the BSL The calculation of the serial baudrate for ASCO from the length of the first zero byte that is received allows the operation of the bootstrap loader of the C164Cl with a wide range of baudrates However the upper and lower limits have to be kept in order to insure proper data transfer Cpu Beisacl 32 SOBRL 1 The C164Cl uses timer T3 to measure the length of the initial zero byte The quantization uncertainty of this measurement implies the first deviation from the real baudrate the next deviation is implied by the computation of the SOBRL reload value from the timer contents The formula below shows the association T3 18 36 i SOBRL Semiconductor Group 15 5 Version 1 0 11 97 SIEMENS The Bootstrap Loader C164Cl For a correct data transfer from the host to the C164Cl the maximum deviation bet
11. recessive the control bits NEWDAT and RMTPND of the last message object are reset the counters of the EML are left unchanged Setting bit CCE in addition allows changing the configuration in the Bit Timing Register To initialize the CAN Controller the following actions are required configure the Bit Timing Register CCE required set the Global Mask Registers initialize each message object If a message object is not needed it is sufficient to clear its message valid bit MSGVAL ie to define it as not valid Otherwise the whole message object has to be initialized After the initialization sequence has been completed the CPU clears the INIT bit To change the configuration of a message object during normal operation the CPU first clears bit MSGVAL which defines it as not valid When the configuration is completed MSGVAL is set again Semiconductor Group 19 18 Version 1 0 11 97 SIEMENS The On Chip CAN Interface C164CI Accessing the On chip CAN Module The CAN Module is implemented as an X Peripheral and is therefore accessed like an external memory or peripheral That means that the registers of the CAN Module can be read and written using 16 bit or 8 bit direct or indirect MEM addressing modes Since the XBUS to which the CAN Module is connected also represents the external bus CAN accesses follow the same rules and procedures as accesses to the external bus CAN accesses cannot be executed in parallel
12. Clock Generation C164CI fiN Reset PWRDN fpi F fin reset sleep jock EN PLL Circuit m fcpu CLKCFG SPANT POH 7 5 Figure 6 6 PLL Block Diagram Semiconductor Group 6 7 Version 1 0 11 97 SIEMENS Clock Generation C164CI 6 3 Oscillator Watchdog The C164Cl provides an Oscillator Watchdog OWD which monitors the clock signal fed to input XTAL1 of the on chip oscillator either with a crystal or via external clock drive in prescaler or direct drive mode For this operation the PLL provides a clock signal base frequency which is used to supervise transitions on the oscillator clock This PLL clock is independent from the XTAL1 clock When the expected oscillator clock transitions are missing the OWD activates the PLL Unlock OWD interrupt node and supplies the CPU with the PLL clock signal instead of the selected oscillator clock Under these circumstances the PLL will oscillate with its base frequency With this PLL clock signal the CPU can either execute a controlled shutdown sequence bringing the system into a defined and safe idle state or it can provide an emergency operation of the system with reduced performance based on this normally slower emergency clock Note The CPU clock source is only switched back to the oscillator clock after a hardware reset The oscillator watchdog can be disabled by setting bit OWDDIS in register SYSCON In this case the PLL remains idle and provides no c
13. The PCALL push and call instruction first pushes the reg operand and the IP contents onto the system stack and then passes control to the subroutine specified by the caddr operand When exiting from the subroutine the RETP return and pop instruction first pops the IP and then the reg operand from the system stack and returns to the calling program Cross Segment Subroutine Calls Calls to subroutines in different segments require the use of the CALLS call inter segment subroutine instruction This instruction preserves both the CSP code segment pointer and IP on the system stack Upon return from the subroutine a RETS return from inter segment subroutine instruction must be used to restore both the CSP and IP This ensures that the next instruction after the CALLS instruction is fetched from the correct segment Note Itis possible to use CALLS within the same segment but still two words of the stack are used to store both the IP and CSP Providing Local Registers for Subroutines For subroutines which require local storage the following methods are provided Alternate Bank of Registers Upon entry into a subroutine it is possible to specify a new set of local registers by executing the SCXT switch context instruction This mechanism does not provide a method to recursively call a subroutine Saving and Restoring of Registers To provide local registers the contents of the registers which are required for use by the
14. The Switch Context instruction SCXT allows to save the content of register CP on the stack and updating it with a new value in just one machine cycle Semiconductor Group 4 22 Version 1 0 11 97 SIEMENS The Central Processing Unit CPU C164Cl Internal RAM ad a l CP 30 CP 28 a A d co z no R Context Pointer z o 2v D PM A o N MCD02003 Figure 4 7 Register Bank Selection via Register CP Several addressing modes use register CP implicitly for address calculations The addressing modes mentioned below are described in chapter Instruction Set Summary Short 4 Bit GPR Addresses mnemonic Rw or Rb specify an address relative to the memory location specified by the contents of the CP register ie the base of the current register bank Depending on whether a relative word Rw or byte Rb GPR address is specified the short 4 bit GPR address is either multiplied by two or not before it is added to the content of register CP see figure below Thus both byte and word GPR accesses are possible in this way GPRs used as indirect address pointers are always accessed wordwise For some instructions only the first four GPRs can be used as indirect address pointers These GPRs are specified via short 2 bit GPR addresses The respective physical address calculation is identical to that for the short 4 bit GPR addresses Short 8 Bit Register Addres
15. curred Components used in life support devices or systems must be expressly authorized for such purpose Critical components of the Semiconductor Group of Siemens AG may only be used in life support devices or systems with the ex press written approval of the Semiconductor Group of Siemens AG 1 Acritical component is a component used in a life support device or system whose failure can reasonably be expected to cause the failure of that life support de vice or system or to affect its safety or ef fectiveness of that device or system 2 Life support devices or systems are in tended a to be implanted in the human body or b to support and or maintain and sustain human life If they fail it is reasonable to assume that the health of the user may be endangered C164CI Revision History Version 1 0 11 97 Previous Releases Page Subjects We Listen to Your Comments Any information within this document that you feel is wrong unclear or missing at all Your feedback will help us to continuously improve the quality of this document Please send your proposal including a reference to this document to I mcdocu comments hlI siemens de SIEMENS General Information C164CI Table of Contents Page 1 Introduclign cyrens v vRSEIGRUPRIUALES Son EC NIRE REN ame eee eles 1 1 1 1 The Members of the 16 bit Microcontroller Family 0 220000 eee 1 2 1 2 Summary or Basic Featu
16. sequence step 2 0011B sequence step 3 0111B access to SYSCON2 SYSCON3 CLKCON 00B basic frequ start PLL Next access to ESFR space PLLIE 1 ie PLL interrupt enabled Currently running on SDD frequency Switch Unlock Unlock Unlock Single to ESFR space and lock sequence sequence step 1 1001B sequence step 2 0011B sequence step 3 0111B access to SYSCON2 SYSCON3 CLKCON O1B stay on SDD start PLL Space for any user code that must or can be executed before P Switching back to basic clock Next access to ESFR space Wait until CLKLOCK 1 Switch Unlock Unlock Unlock Single to ESFR space and lock sequence sequence step 1 1001B sequence step 2 0011B sequence step 3 0111B access to SYSCON2 SYSCON3 CLKCON 00B basic frequency Next access to ESFR space SPLLIE 1 ie 21 14 PLL interrupt enabled Version 1 0 11 97 SIEMENS System Programming C164CI 22 System Programming To aid in software development a number of features has been incorporated into the instruction set of the C164Cl including constructs for modularity loops and context switching In many cases commonly used instruction sequences have been simplified while providing greater flexibility The following programming features help to fully utilize this instruction set Instructions Provided as Subsets of Instructions In many cases instructi
17. 15 14 13 12 11 10 9 8 T pee m n Bit Function DP8 y Port direction register DP8 bit y DP8 y 0 Port line P8 y is an input high impedance DP8 y 1 Port line P8 y is an output ODP8 F1D6 EBp ESFR Reset Value 00y 15 14 13 12 11 10 9 8 8 7 6 5 4 3 2 1 0 ODP8 ODP8 ODP8 ODP8 3 2 4 0 L l a _ ODP8 y Port 8 Open Drain control register bit y ODP8 y 0 Port line P8 y output driver in push pull mode ODP8 y 1 Port line P8 y output driver in open drain mode Bit Function Semiconductor Group 7 23 Version 1 0 11 97 SIEMENS Parallel Ports C164CI Alternate Functions of Port 8 All Port 8 lines serve as capture inputs or compare outputs CCxIO for the CAPCOM2 unit see table below When a Port 8 line is used as a capture input the state of the input latch which represents the state of the port pin is directed to the CAPCOM unit via the line Alternate Pin Data Input If an external capture trigger signal is used the direction of the respective pin must be set to input If the direction is set to output the state of the port output latch will be read since the pin represents the state of the output latch This can be used to trigger a capture event through software by setting or clearing the port latch Note that in the output configuration no external device may drive the pin otherwise conflicts would occur When a Port 8 line is used as a compare output
18. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw ADDAT2 F0A0j 504 ESFR Reset Value 00004 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw Bit Function ADRES A D Conversion Result 10 bit CHNR Channel Number 38 bit identifies the converted analog channel A conversion is started by setting bit ADST 1 The busy flag ADBSY will be set and the converter then selects and samples the input channel which is specified by the channel selection field ADCH in register ADCON The sampled level will then be held internally during the conversion When the conversion of this channel is complete the 10 bit result together with the number of the converted channel is transferred into the result register ADDAT and the interrupt request flag ADCIR is set If bit ADST is reset via software while a conversion is in progress the A D converter will stop after the current conversion fixed channel modes or after the current conversion sequence auto scan modes Setting bit ADST while a conversion is running will abort this conversion and start a new conversion with the parameters specified in ADCON Note Abortion and restart see above are triggered by bit ADST changing from 0 to 1 ie ADST must be 0 before being set While a conversion is in progress the mode selection field ADM and the channel selection field ADCH may be changed ADM will be evaluated after the current conversion ADCH will b
19. C164Cl Status of Output Pins during Power Reduction Modes During Idle mode the CPU clocks are turned off while all peripherals continue their operation in the normal way Therefore all ports pins which are configured as general purpose output pins output the last data value which was written to their port output latches If the alternate output function of a port pin is used by a peripheral the state of the pin is determined by the operation of the peripheral Port pins which are used for bus control functions go into that state which represents the inactive state of the respective function eg WR or to a defined state which is based on the last bus access eg BHE Port pins which are used as external address data bus hold the address data which was output during the last external memory access before entry into Idle mode under the following conditions POH outputs the high byte of the last address if a multiplexed bus mode with 8 bit data bus is used otherwise POH is floating POL is always floating in Idle mode Port 4 outputs the segment address and the CS signals for the last access on those pins that were selected during reset otherwise the output pins of Port 4 represent the port latch data During Power Down mode the oscillator except for RTC operation and the clocks to the CPU and to the peripherals are turned off Like in Idle mode all port pins which are configured as general purpose output pins output the last data v
20. D1 D2 D3 D4 D5 D7 LSB Parity Asynchronous 8 bit Data Frames Figure 11 3 9 bit data frames either consist of 9 data bits D8 DO SOM 100p of 8 data bits D7 DO plus an automatically generated parity bit SOMz 111g or of 8 data bits D7 DO plus wake up bit S0Mz 101g Parity may be odd or even depending on bit SOODD in register SOCON An even parity bit will be set if the modulo 2 sum of the 8 data bits is 1 An odd parity bit will be cleared in this case Parity checking is enabled via bit SOPEN always OFF in 9 bit data and wake up mode The parity error flag SOPE will be set along with the error interrupt request flag if a wrong parity bit is received The parity bit itself will be stored in bit SORBUF 8 In wake up mode received frames are only transferred to the receive buffer register if the 9th bit the wake up bit is 1 If this bit is 0 no receive interrupt request will be activated and no data will be transferred This feature may be used to control communication in multi processor system When the master processor wants to transmit a block of data to one of several slaves it first sends out an address byte which identifies the target slave An address byte differs from a data byte in that the additional 9th bit is a 1 for an address byte and a 0 for a data byte so no slave will be interrupted by a data byte An address byte will interrupt all slaves operating in 8 bit da
21. F1DE EF ESFR Reset Value 00004 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Function xxIR Interrupt Request Flag for Source xx 0 No request from source xx pending 1 Source xx has raised an interrupt request xxIE Interrupt Enable Control Bit for Source xx 0 Source xx interrupt request is disabled 1 Source xx interrupt request is enabled Sub node Control Bit Allocation Bit pos Interrupt Source Associated Node 15 4 Reserved Reserved 3 2 PLL OWD XP3IC 1 0 RTC XP3IC Note In order to ensure compatibility with other derivatives application software should never set reserved bits within register ISNC Semiconductor Group 5 20 Version 1 0 11 97 SIEMENS Interrupt and Trap Functions C164CI 5 6 External Interrupts Although the C164Cl has no dedicated INTR input pins it provides many possibilities to react on external asynchronous events by using a number of IO lines for interrupt input The interrupt function may either be combined with the pin s main function or may be used instead of it ie if the main pin function is not required Interrupt signals may be connected to EXSIN EXOIN the fast external interrupt input pins CC271O CC2410O capture input lines of the CAPCOM units e CC19lIO CC161O capture input compare output lines of the CAPCOM units TAIN T2IN the timer input pins For each of these pins either a positive a negative or both a pos
22. FFOC 864 Bus Configuration Register 0 0000 BUSCON1 b FF14 8A Bus Configuration Register 1 0000 BUSCON b FF16 8By Bus Configuration Register 2 0000 BUSCONGS b FF18 8C Bus Configuration Register 3 0000 BUSCON4 b FF1A 8Dy Bus Configuration Register 4 0000 C1BTR EFO4 X CAN Bit Timing Register UUUU C1CSR EFOO X CAN Control Status Register XX014 C1GMS EFO6 X CAN Global Mask Short UFUU C1IR EF024 X CAN Interrupt Register XXy C1LGML EFOA X CAN Lower Global Mask Long UUUU C1LMLM EFOE X CAN Lower Mask of Last Message UUUUH C1UGML EFO8 X CAN Upper Global Mask Long UUUU C1UMLM EFOC X CAN Upper Mask of Last Message UUUU CC10IC b FF8Cy C64 CAPCOM Register 10 Interrupt Control Register 0000 CC11IC b FF8Ey C7y CAPCOM Register 11 Interrupt Control Register 00004 CC16 FE60y 304 CAPCOM Register 16 0000 Semiconductor Group 23 4 Version 1 0 11 97 SIEMENS The Register Set C164Cl Name Physical 8 Bit Description Reset Address Address Value CC16IC b F160 E BO CAPCOM Register 16 Interrupt Control Register 0000 CC17 FE62 314 CAPCOM Register 17 00004 CC171IC b F162 E B1y CAPCOM Register 17 Interrupt Control Register 0000 CC18 FE644 324 CAPCOM Register 18 00004 CC18IC b F164 E B2j CAPCOM Register 18 Interrupt Control Register 0000 CC19 FE66 334 CAPCOM Register 19 0000 CC19IC b F
23. Gated Timer Counter Mode and Incremental Interface Mode In Timer Mode the input clock for a timer is derived from the internal CPU clock divided by a programmable prescaler while Counter Mode allows a timer to be clocked in reference to external events via TxIN Pulse width or duty cycle measurement is supported in Gated Timer Mode where the operation of a timer is controlled by the gate level on its external input pin TxIN In Incremental Interface Mode timer T3 can be directly connected to the incremental position sensor signals A and B via the respective inputs T3IN and T3EUD Direction and count signals are internally derived from these two input signals so the contents of timer T3 corresponds to the sensor position The third position sensor signal TOPO can be connected to an interrupt input The count direction up down for each timer is programmable by software or may additionally be altered dynamically by an external signal TxEUD to facilitate eg position tracking The core timer T3 has an output toggle latch T3OTL which changes its state on each timer over flow underflow The state of this latch may be used internally to concatenate the core timer with the auxiliary timers resulting in 32 33 bit timers counters for measuring long time periods with high resolution Various reload or capture functions can be selected to reload timers or capture a timer s contents triggered by an external signal or a selectable transition of
24. Reload Reg TyREL MCB02143 Figure 16 2 CAPCOM Unit Block Diagram Note The CAPCOM2 unit provides 8 capture inputs but only 4 compare outputs Semiconductor Group 16 3 Version 1 0 11 97 SIEMENS The Capture Compare Unit CAPCOM2 C164Cl 16 1 The CAPCOM Timers The primary use of the timers T7 T8 is to provide two independent time bases 16 TCL maximum resolution for the capture compare registers of each unit but they may also be used independent of the capture compare registers The basic structure of the two timers is identical while the selection of input signals is different for timer T7 and timer T8 see figures below Reload Reg TxREL D Input ut Control CPU Clock gt X GPT2 Timer T6 Interrupt OverlUnderflow c gt MUX CAPCOM Timer Tx Request Select _ MCB02013 i TxR ww CJ bd Td TxM Txl Figure 16 3 Block Diagram of CAPCOM Timer T7 Reload Reg TXREL Interrupt CAPCOM Timer Tx Request Over Underflow MCB02014 Txl CPU Clock gt X GPT2 Timer T6 F n TxR TxM Figure 16 4 Block Diagram of CAPCOM Timer T8 Semiconductor Group 16 4 Version 1 0 11 97 SIEMENS The Capture Compare Unit CAPCOM2 C164Cl The functions of the CAPCOM timers are controlled via the bitaddressable 16 bit control register T78CON The high byte of T78CON controls T8 the low byte of T78CON controls T7 The control options are identical for both ti
25. Semiconductor Group 17 21 Version 1 0 11 97 SIEMENS The Capture Compare Unit CAPCOM6 C164CI CC6MCON FF32 991 SFR Reset Value 00FF 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BCMP BC COUT COUT COUT COUT COUT rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bit Function CCnl Compare Output CC6n Initial Value n 0 2 The compare output CC6n drives the value of CCnl when the compare timer T12 is not running CCnl represents the passive output level for an enabled compare channel Note The initial values are only valid for capture compare outputs which are enabled for compare mode operation compare output COUTnI Compare Output COUTE6n Initial Value n 0 2 The compare output COUT6n drives the value of COUTnI when the compare timer T12 is not running COUTnI represents the passive output level for an enabled compare channel Note The initial values are only valid for capture compare outputs which are enabled for compare mode operation compare output COUTXI COUTS6n Inversion Control 0 113 s output signal is directly connected to compare outputs COUTS6n in burst or multi channel mode n 0 2 1 T 13 s output signal is inverted and then connected to compare outputs COUTS6n in burst or multi channel mode n 0 2 COUTSI Compare Output COUT63 Initial Value This bit defines the initial logic state of the output COUT63 before timer T13 is started the first time Further COUTSI defines the logic state of COUT63
26. bs SP zF802H Physical stack addr FA02H PUSH R1 SP F800H Physical stack addr FAO00H PUSH R2 SP F7FEH Physical stack addr FBFEH The effect of the address transformation is that the physical stack addresses wrap around from the end of the defined area to its beginning When flushing and filling the internal stack this circular stack mechanism only requires to move that portion of stack data which is really to be re used ie the upper part of the defined stack area instead of the whole stack area Stack data that remain in the lower part of the internal stack need not be moved by the distance of the space being flushed or filled as the stack pointer automatically wraps around to the beginning of the freed part of the stack area Note This circular stack technique is applicable for stack sizes of 32 to 512 words STKSZ 000 to 100g it does not work with option STKSZ 111g which uses the complete internal RAM for system stack In the latter case the address transformation mechanism is deactivated Semiconductor Group 22 6 Version 1 0 11 97 SIEMENS System Programming C164CI When a boundary is reached the stack underflow or overflow trap is entered where the user moves a predetermined portion of the internal stack to or from the external stack The amount of data transferred is determined by the average stack space required by routines and the frequency of calls traps interrupts and returns In most cases th
27. from a group of different sources on the same priority level At the end of each instruction cycle the one source request with the highest current priority will be determined by the interrupt system This request will then be serviced if its priority is higher than the current CPU priority in register PSW Interrupt System Register Description Interrupt processing is controlled globally by register PSW through a general interrupt enable bit IEN and the CPU priority field ILVL Additionally the different interrupt sources are controlled individually by their specific interrupt control registers IC Thus the acceptance of requests by the CPU is determined by both the individual interrupt control registers and the PSW PEC services are controlled by the respective PECCx register and the source and destination pointers which specify the task of the respective PEC service channel Interrupt Control Registers All interrupt control registers are organized identically The lower 8 bits of an interrupt control register contain the complete interrupt status information of the associated source which is required during one round of prioritization the upper 8 bits of the respective register are reserved All interrupt control registers are bit addressable and all bits can be read or written via software This allows each interrupt source to be programmed or modified with just one instruction When accessing interrupt control registers through inst
28. from the external memory and the internal pointers are adjusted accordingly Linear Stack The C164CI also offers a linear stack option STKSZ 1115 where the system stack may use the complete internal RAM area This provides a large system stack without requiring procedures to handle data transfers for a circular stack However this method also leaves less RAM space for variables or code The RAM area that may effectively be consumed by the system stack is defined via the STKUN and STKOV pointers The underflow and overflow traps in this case serve for fatal error detection only For the linear stack option all modifiable bits of register SP are used to access the physical stack Although the stack pointer may cover addresses from 00 F000 up to OO0 FFFE the physical system stack must be located within the internal RAM and therefore may only use the address range 00 F600 to 00 FDFE It is the user s responsibility to restrict the system stack to the internal RAM range Note Avoid stack accesses below the IRAM area ESFR space and reserved area and within address range 00 FEO00 and OO0 FFFE SFR space Otherwise unpredictable results will occur Semiconductor Group 22 7 Version 1 0 11 97 SIEMENS System Programming C164CI User Stacks User stacks provide the ability to create task specific data stacks and to off load data from the system stack The user may push both bytes and words onto a user stack but is responsib
29. in both operating modes of timer T12 CCnF Capture Compare Falling Edge Interrupt Flag 0 Idle 1 The interrupt request flag is set in capture mode upon a falling edge at the corresponding CC6n input in compare mode when T12 matches compare register CC6n while counting down in center aligned mode timer T12 only CT12FC Timer T12 Count Direction Change Flag 0 Idle 1 Aninterrupt request is generated when T12 counting down in center aligned mode matches 0000 and changes to counting up There is no effect in edge aligned mode CT12FP Timer T12 Period Flag 0 Idle 1 An interrupt request is generated when T12 matches the period value Note All CAPCOMSG interrupt request bits in register CC6MIC must be cleared by software Semiconductor Group 17 25 Version 1 0 11 97 SIEMENS The Capture Compare Unit CAPCOM6 C164Cl The CAPCOMG6 Interrupt Structure The figure below summarizes the CAPCOM6 s interrupt sources and the related status and control flags and shows the association with the 4 CAPCOM6 interrupt nodes CAPCOM6 Intr Contr CC60 CCOREN CCOFEN compare event CC6CIC CC61 CC1REN Reg CC61 CC1FEN compare event CC62 input CC2REN CC2FEN Reg CC62 compare event CC6EIC TRF c E WS So S Emergency ETRP interrupt 9 IE Ee ee ey a iu rune RE Ted T121C CT12FP were Wee i po eee MTS Mus SS Timer T12 ECTP gt
30. is write protected after the execution of EINIT unless it is released via the unlock sequence Semiconductor Group 21 8 Version 1 0 11 97 SIEMENS Power Management C164Cl Reset X gt State transition when writing xx to CLKCON Automatic transition after clock is stable ie CLKLOCK z 1 Figure 21 4 Clock Switching State Machine Clock Switching State Description State PLL fopy CLK Note number status source CON 1 Locked 1 Basic 00 Standard operation on basic clock frequency 2 Locked SDD 01 SDD operation with PLL On Fast without delay or manual switch back from 5 to basic clock frequency 3 Transient SDD 00 Intermediate state leading to state 1 4 Transient SDD 01 Intermediate state leading to state 2 5 Off SDD 10 SDD operation with PLL Off Reduced power consumption 1 The indicated PLL status only applies if the PLL is selected as the basic clock source If the basic clock source is direct drive or prescaler the PLL will not lock If the oscillator watchdog is disabled OWDDIS 1 the PLL will be off Note When the PLL is the basic clock source and a reset occurs during SDD operation with the PLL off the internal reset condition is extended so the PLL can lock before execution begins The reset condition is terminated prematurely if no stable oscillator clock is detected This ensures the operability of the devi
31. numbers in the table are in units of CPU clock cycles and assume no waitstates Minimum Execution Times Instruction Fetch Word Operand Access Memory Area Word Doubleword Read from Write to Instruction Instruction Internal code memory 2 2 2 Internal RAM IRAM 6 8 0 1 16 bit Mux Bus 3 6 3 8 bit Mux Bus 6 12 6 Execution from the internal RAM provides flexibility in terms of loadable and modifyable code on the account of execution time Execution from external memory strongly depends on the selected bus mode and the programming of the bus cycles waitstates The operand and instruction accesses listed below can extend the execution time of an instruction Internal code memory operand reads same for byte and word operand reads Internal RAM operand reads via indirect addressing modes Internal SFR operand reads immediately after writing External operand reads External operand writes Jumps to non aligned double word instructions in the internal ROM space Testing Branch Conditions immediately after PSW writes Semiconductor Group 4 10 Version 1 0 11 97 SIEMENS The Central Processing Unit CPU C164Cl 4 4 CPU Special Function Registers The core CPU requires a set of Special Function Registers SFRs to maintain the system state information to supply the ALU with register addressable constants and to control system and bus configuration multiply and divide ALU operations cod
32. o T3l 3 fopy MHz CPU Interrupt Up TxR Tx3UD Down TxOTL ae TxOUT i j MUX TxOE MCB02028 TxEUD l EKOR Figure 10 3 Block Diagram of Core Timer T3 in Timer Mode The timer input frequencies resolution and periods which result from the selected prescaler option are listed in the table below This table also applies to the Gated Timer Mode of T3 and to the auxiliary timers T2 and T4 in timer and gated timer mode Note that some numbers may be rounded to 3 significant digits GPT1 Timer Input Frequencies Resolution and Periods fopy 20MHz Timer Input Selection T2l T3I T4I 000p 001g 010g 011g 100p 101g 110g 111g Prescaler factor 8 16 32 64 128 256 512 1024 Input Frequency 20 1 25 625 312 5 158 25 78 125 3905 15 53 MHz MHz kHz kHz kHz kHz kHz kHz Resolution 400ns 800ns 1 6us 3 2us 6 4us 12 8 us 25 6 us 51 2 us Period 26ms 52 5ms 105ms 210ms 420 ms 840 ms 1 68s 3 36 s Semiconductor Group 10 5 Version 1 0 11 97 SIEM ENS The General Purpose Timer Unit C164Cl Timer 3 in Gated Timer Mode Gated timer mode for the core timer T3 is selected by setting bit field T3M in register T3CON to 010g or 011 Bit T3M 0 T3CON 3 selects the active level of the gate input In gated timer mode the same options for the input frequency as for the timer mode are available However the input clock to the timer in this mode is gated by the external input
33. the accessibility of the C164Cl s memory areas after reset in Bootstrap Loader mode differs from the standard case Pin EA is not evaluated when BSL mode is selected and accesses to the internal code memory are partly redirected while the C164Cl is in BSL mode see table below All code fetches are made from the special Boot ROM while data accesses read from the internal code memory Data accesses will return undefined values on ROMless devices Note The code in the Boot ROM is not an invariant feature of the C164Cl User software should not try to execute code from the internal ROM area while the BSL mode is still active as these fetches will be redirected to the Boot ROM The Boot ROM will also move to segment 1 when the internal ROM area is mapped to segment 1 LO i e i access to external bus disabled int RAM e Teke to p int ROM 9 enabled ta access to external bus enabled int RAM O access to T int ROM 9 enabled ta Depends on reset config EA PO BSL mode active Yes POL 4 0 Yes POL 4 0 No POL 4 1 EA pin high low acc to application Code fetch from internal ROM area Boot ROM access Boot ROM access User ROM access Data fetch from internal ROM area User ROM access User ROM access User ROM access Semiconductor Group 15 4 Version 1 0 11 97 SIEMENS The Bootstrap Load
34. 0 57 COUTx CC 5 T COINI Bit 1 one CC content of the CCxH CCxL compare registers CCP content of the CCPH CCPL period register CT1OF content of the CTTOFH CT1OFL offset registers MCT02603 Figure 17 7 Operation in Center Aligned Mode Note In order to generate correct dead times for PWM signals the offset value stored in T12OF must be lower than the value stored in the compare registers The offset value affects all COUT6x outputs Semiconductor Group 17 7 Version 1 0 11 97 SIEMENS The Capture Compare Unit CAPCOM6 C164Cl Timing Relationships The resolution of the compare timers depends on the selected internal clock frequency The period range of the output signals in turn depends on the actual timer resolution minimum value and on the timer and period values maximum value The table below lists the respective values for both compare timers for the possible clock selections Due to the internal operation the minimum possible output period is 2 internal clock cycles Operating Mode 0 Load Reg with Load Reg with Count A CCxReg 2 COxReg 2 Value Start of CT1 CCxReg 1 cCP 1 a CCx COUTx min 100 ns 40 MHz clock rate Operating Mode 1 Load Reg with Count A CCxReg 1 Value CCP 4 Start of CT1 CCxReg 1 CCP 2 CCx COUTx min 200 ns 40 MHz clock rate MCTO2604 Figure 17 8 Operation in Center Align
35. 10 OTP 3 11 Multi Channel Modes CAPCOMO 17 12 Protected Multiplexed Bus 9 3 Bits 2 16 4 9 Multiplication 4 27 22 1 instruction 24 4 PSW 4 14 5 8 Semiconductor Group 26 3 Version 1 0 11 97 SIEMENS Index C164Cl R Full Duplex 12 6 RAM Half Duplex 12 8 internal 3 4 SSCBR 12 10 SSCCON 12 2 Read Write Delay 9 12 Real Time Clock gt RTC 14 1 Registers 23 1 sorted by address 23 10 sorted by name 23 4 Reset 10 11 20 1 Bidirectional 20 3 Configuration 20 6 Output 20 5 source indication 13 4 Values 20 5 ROM Handling 22 14 RPOH 9 20 RTC 2 14 S SOBG 11 10 SOCON 11 2 SOEIC SORIC SOTIC SOTBIC 11 12 SORBUF 11 7 11 9 SOTBUF 11 6 11 9 Segment Address 9 6 20 12 boundaries 3 10 Segmentation 4 18 Enable Disable 4 13 Serial Interface 2 11 11 1 Asynchronous 11 4 CAN 2 11 19 1 Synchronous 11 8 12 1 SFR 3 8 23 4 23 10 Single Chip Mode 9 2 Slow Down Mode 21 7 Software Reset 20 1 Traps 5 25 Source Interrupt 5 3 SP 4 24 Special operation modes config 20 10 SSC 12 1 Baudrate generation 12 10 Error Detection 12 12 Semiconductor Group SSCEIC SSCRIC SSCTIC 12 14 SSCRB SSCTB 12 7 Stack 3 5 4 24 22 4 Startup Configuration 20 6 STKOV 4 25 STKUN 4 26 Subroutine 22 9 Synchronous Serial Interface gt SSC 12 1 SYSCON 4 11 9 13 SYSCON2 21 8 SYSCON3 21 11 T T121C T13IC 17 27 T2CON 10 11 T2IC T3IC T4IC 10 18 T3CON 10 3 T4CON 10 11 T7IC T8IC 16 8 TFR 5 26 Th
36. 12 Block Commutation Mode 17 16 double register 16 17 Bootstrap Loader 15 1 20 10 Concatenation of Timers 10 14 Boundaries 3 10 Configuration Burst Mode Address 9 6 20 12 CAPCOM6 17 10 Bus Mode 9 2 20 11 Bus Chip Select 9 6 20 12 CAN 2 11 19 1 19 20 PLL 6 6 20 13 Idle State 9 21 Reset 20 6 Semiconductor Group 26 1 Version 1 0 11 97 SIEMENS Index C164Cl special modes 20 10 ASCO 11 10 Write Control 20 11 CAN 19 3 Context Switching 5 15 SSC 12 12 Conversion EXICON 5 22 analog digital 18 1 EXISEL 5 24 Auto Scan 18 5 External timing control 18 10 Bus 2 8 Count direction 10 4 Bus Characteristics 9 8 9 12 Counter 10 7 10 13 Bus Idle State 9 21 CP 4 22 Bus Modes 9 2 9 5 CPU 2 2 4 1 Host Mode EHM 20 10 Host Mode CHM 20 10 Interrupt source control 5 24 CSP 4 18 Interrupts 5 21 CTCON 17 20 F D Fast external interrupts 5 22 Data Page 4 20 22 13 Flags 4 14 4 16 boundaries 3 10 Full Duplex 12 6 Delay Read Write 9 12 G Development Support 1 6 GPR 3 6 4 22 23 2 Direct Drive 6 4 GPT 2 12 Direction GPT1 10 1 count 10 4 Disable H Interrupt 5 13 Half Duplex 12 8 Peripheral 21 11 Hardware Segmentation 4 13 Reset 20 1 Division 4 27 22 1 Traps 5 25 Double Register compare 16 17 I DPOL DPOH 7 6 Idle DP UZDE TH qae Stae Bus 9 21 ee Idle Mode 21 2 ip eae Incremental Interface 10 8 DEE since Indication of reset source 13 4 SUP ieee ts Input threshold 7 2 E Instruction 22 1 24 1 Early chip select 9 7 Bit Manipulation 24 2
37. 15 14 13 12 11 10 9 8 0 7 6 5 4 3 2 1 2 2 wo w rw rw rw Bit Function RDQ Read Signal active low 0 OTP module selected for a verify read access 1 Read access is completed WRQ Write Signal active low 0 OTP module selected for a write access programming 1 Write access is completed CEQ OTP Module Enable Signal active low 0 OTP module is selected 1 OTP module is deselected no access RS Register Select Signal RSEL 0 Access the OTP memory module 1 Access the control section read protection control SEGAD Physical Segment Address Provides the upper address lines A23 A16 to the OTP memory module Note SEGAD must be 00 for the C164Cl An OTP programming verify cycle is executed by a sequence of accesses to the programming interface which emulate the externally controlled cycles see example below Semiconductor Group 3 14 Version 1 0 11 97 SIEMENS Memory Organization C164Cl OTP Module Addressing When the OTP module is read in normal mode via its CPU interface it appears like a standard ROM and its lower 32 KByte block within the internal ROM area can also be mapped to the respective lower half of segment 0 or segment 1 For segment 0 mapping it uses locations 00 0000 to 00 7FFFy and 01 8000 to 01 FFFFy for segment 1 mapping it uses locations 01 0000 to 01 FFFFy In programming mode however the OTP module is addressed physically via the
38. 15B3y Note The deviation errors given in the table above are rounded Using a baudrate crystal eg 18 432 MHz will provide correct baudrates without deviation errors Synchronous Mode Baud Rates For synchronous operation the baud rate generator provides a clock with 4 times the rate of the established baud rate The baud rate for synchronous operation of serial channel ASCO can be determined by the following formula fopu fopu Bsync _ _ ________ SOBRL n 1 4 2 SOBRS lt SOBRL gt 1 4 2 lt SOBRS gt Bsync lt SOBRL gt represents the content of the reload register taken as unsigned 13 bit integers lt SOBRS gt represents the value of bit SOBRS ie 0 or 1 taken as integer The maximum baud rate that can be achieved in synchronous mode when using a CPU clock of 20 MHz is 2 5 MBaud Semiconductor Group 11 11 Version 1 0 11 97 Sl EM ENS The Asynchronous Synchronous Serial Interface C164CI 11 5 ASCO Interrupt Control Four bit addressable interrupt control registers are provided for serial channel ASCO Register SOTIC controls the transmit interrupt SOTBIC controls the transmit buffer interrupt SORIC controls the receive interrupt and SOEIC controls the error interrupt of serial channel ASCO Each interrupt source also has its own dedicated interrupt vector SOTINT is the transmit interrupt vector SOTBINT is the transmit interrupt vector SORINT
39. 16 6 17 17 1 17 2 17 3 17 4 17 5 17 6 17 7 17 8 17 9 C164Cl Page The External Bus Interface 00000 es 9 1 External Bus Modes iue ie eR A ELA EUESESEN RED hate le hes 9 2 Programmable Bus Characteristics 0 0 00 cee eee 9 8 Controlling the External Bus Controller 0 00 c eee eee 9 13 EBG Idle Stateira n Qaa ihe qe D pmi RR Debs a e due eae oe le Re 9 21 The XBUS Interface cst can rre cen MALe tev e qa teat eat dant hee ot dee 9 22 The General Purpose Timer Unit 02000000 eee eee 10 1 The Asynchronous Synchronous Serial Interface 11 1 Asynchronous ODSFAllOTic d e vae recs oa dre gh in ee DVEE MERD CENE PA RI ES 11 4 Synchronous Operation sedeo en REX tk ewe EA RE R Gat EE mpi 11 8 Hardware Error Detection Capabilities clesie 11 10 ASCO Baud Rate Generation 000 eee ee 11 10 ASCO Interrupt Control veo RERERECL 3 ERO aN eee bd Seow es 11 12 The High Speed Synchronous Serial Interface 12 1 Full Duplex Operation tou Re Se WEES WHET EDR E Ret ie oe tee 12 6 Half Duplex Operation i 123 xm hex E putea aU ENEAN er EE aD Eu ESAE 12 8 Baud Rate Generation x52 dieit abe EXPERS Eb E EE 12 10 Error Detection Mechanisms ccce ck ck eee bate iweb eS bays es 12 12 SSC Interrupt Control 2 p traut anh baie telus Testez eee sets te Db nd 12 14 The Watchdog Timer WDT 0 00 c eee eee 13 1 The He
40. 7 A short hardware reset is extended until the end of the reset sequence in Bidirectional reset mode 8 A software or WDT reset activates the RSTIN line in Bidirectional reset mode Figure 20 3 Reset Input and Output Signals Semiconductor Group 20 4 Version 1 0 11 97 SIEMENS System Reset C164CI Reset Output Pin The RSTOUT pin is dedicated to generate a reset signal for the system components besides the controller itself RSTOUT will be driven active low at the begin of any reset sequence triggered by hardware the SRST instruction or a watchdog timer overflow RSTOUT stays active low beyond the end of the internal reset sequence until the protected EINIT End of Initialization instruction is executed see figure above This allows the complete configuration of the controller including its on chip peripheral units before releasing the reset signal for the external peripherals of the system Note RSTOUT will float as long as pins POL O and POL 1 select emulation mode or adapt mode Watchdog Timer Operation after Reset The watchdog timer starts running after the internal reset has completed It will be clocked with the internal system clock divided by 2 10 MHz Q fc p j 20 MHz and its default reload value is 00 so a watchdog timer overflow will occur 131072 CPU clock cycles 6 55 ms fcpy 20 MHz after completion of the internal reset unless it is disabled serviced or reprogrammed meanwhile When the system re
41. CAPCOM Register 25 0000 CC26 FE74 3AH CAPCOM Register 26 0000 Semiconductor Group 23 12 Version 1 0 11 97 SIEMENS The Register Set C164Cl Name Physical 8 Bit Description Reset Address Address Value CC27 FE764 3By CAPCOM Register 27 0000 ADDAT FEAO 504 A D Converter Result Register 00004 WDT FEAE 57H Watchdog Timer Register read only 0000 SOTBUF FEBO 584 Serial Channel 0 Transmit Buffer Register 00004 SORBUF FEB2y 594 Serial Channel 0 Receive Buffer Register XXXXy read only SOBG FEB4 5Ay Serial Channel 0 Baud Rate Generator Reload 00004 Register PECCO FECO 160 PEC Channel 0 Control Register 00004 PECC1 FEC2 614 PEC Channel 1 Control Register 00004 PECC2 FEC4 624 PEC Channel 2 Control Register 00004 PECC3 FEC6y4 63y PEC Channel 3 Control Register 00004 PECCA FEC8 644 PEC Channel 4 Control Register 00004 PECC5 FECA 65y PEC Channel 5 Control Register 00004 PECC6 FECC 66 PEC Channel 6 Control Register 00004 PECC7 FECE 67y PEC Channel 7 Control Register 00004 POL b FFOO 804 Port 0 Low Register Lower half of PORTO 004 POH b FF024 814 Port 0 High Register Upper half of PORTO 004 P1L b FF044 824 Port 1 Low Register Lower half of PORT1 004 P1H b FF064 834 Port 1 High Register Upper half of PORT1 004 BUSCONO b FFOC 864 Bus Configuration Register 0 00004 MDC b FFOE 874
42. CPU Multiply Divide Control Register 0000 PSW b FF10 884 CPU Program Status Word 0000 SYSCON b FF12 894 CPU System Configuration Register 0xxo BUSCON1 b FF14 8Ay Bus Configuration Register 1 0000 BUSCON2 b FF16 8By Bus Configuration Register 2 0000 BUSCONS b FF184 8C4 Bus Configuration Register 3 0000 BUSCON4 b FF1A 8D Bus Configuration Register 4 0000 ZEROS b FF1Cy 8Ey Constant Value 0 s Register read only 0000 ONES b FF1E 8Fy Constant Value 1 s Register read only FFFFy T78CON b FF20 904 CAPCOM Timer 7 and 8 Control Register 00004 CCM4 b FF22 914 CAPCOM Mode Control Register 4 00004 CCM6 b FF26 93 CAPCOM Mode Control Register 6 00004 Semiconductor Group 23 13 Version 1 0 11 97 SIEMENS The Register Set C164Cl Name Physical 8 Bit Description Reset Address Address Value CTCON b FF30 984 CAPCOM 6 Compare Timer Control Register 10104 CC6MCON b FF324 994 CAPCOM 6 Mode Control Register 00F F TRCON b FF344 9A CAPCOM 6 Trap Enable Control Register 00XXy CC6MIC b FF36 9B CAPCOM 6 Mode Interrupt Control Register 0000 T2CON b FF404 A0y GPT1 Timer 2 Control Register 0000 T3CON b FF424 Aly GPT1 Timer 3 Control Register 0000 T4CON b FF44 A2y GPT1 Timer 4 Control Register 0000 T2IC b FF60 BOH GPT1 Timer 2 Interrupt Control Register 00004 T3IC b FF624 Bly GPT1 Timer 3 Interrupt
43. Control Register 0000 T4IC b FF644 B24 GPT1 Timer 4 Interrupt Control Register 0000 SOTIC b FF6C B6y Serial Channel 0 Transmit Interrupt Control 0000 Register SORIC b FF6E B7y Serial Channel 0 Receive Interrupt Control 00004 Register SOEIC b FF70y B84 Serial Channel 0 Error Interrupt Control Register 00004 SSCTIC b FF72 B94 SSC Transmit Interrupt Control Register 0000 SSCRIC b FF74 BAy SSC Receive Interrupt Control Register 00004 SSCEIC b FF76 BBuy SSC Error Interrupt Control Register 0000 CC8IC b FF884 C44 CAPCOM Register 8 Interrupt Control Register 0000 CC9IC b FF8A C5y CAPCOM Register 9 Interrupt Control Register 0000 CC10IC b FF8Cy C64 CAPCOM Register 10 Interrupt Control Register 00004 CC11IC b FF8E C74 CAPCOM Register 11 Interrupt Control Register 0000 ADCIC b FF984 CC A D Converter End of Conversion Interrupt 0000 Control Register ADEIC b FF9A CDy A D Converter Overrun Error Interrupt Control 00004 Register ADCON b FFAO0Q DO A D Converter Control Register 0000 P5 b FFA2 Diy Port 5 Register read only XXXXy P5DIDIS b FFA4 D2y Port 5 Digital Input Disable Register 0000 TFR b FFAC D64 Trap Flag Register 00004 WDTCON b FFAE D74 Watchdog Timer Control Register 00XX SOCON b FFBO D8y Serial Channel 0 Control Register 0000 SSCCON b FFB2 D94 SSC Control Register 0000 P3 b FFC4 E24 Port 3 Register 0000 Semiconductor Group 23 14 Version 1 0 11 97 SIEMENS The Register Set
44. EJ EF Interrupt Subnode Control Register 00004 DPPO FEOO 004 CPU Data Page Pointer 0 Register 10 bits 0000 DPP1 FE024 01g CPU Data Page Pointer 1 Register 10 bits 0001 DPP2 FE044 024 CPU Data Page Pointer 2 Register 10 bits 0002 DPP3 FEO6 034 CPU Data Page Pointer 3 Register 10 bits 0003 CSP FEO8y 044 CPU Code Segment Pointer Register 0000 8 bits not directly writeable MDH FEOCyH 064 CPU Multiply Divide Register High Word 0000 MDL FEOE 07y CPU Multiply Divide Register Low Word 0000 CP FE10y 084 CPU Context Pointer Register FC00 SP FE124 09 CPU System Stack Pointer Register FC00 STKOV FE14y OAH CPU Stack Overflow Pointer Register FA00u STKUN FE16y OBH CPU Stack Underflow Pointer Register FCOO ADDRSEL1 FE18 0Cy Address Select Register 1 0000 ADDRSEL2 FE1A 0Dy Address Select Register 2 0000 ADDRSEL3 FE1Cy OEY Address Select Register 3 00004 ADDRSEL4 FE1E OFy Address Select Register 4 00004 CC60 FE30y 184 CAPCOM 6 Register 0 0000 CC61 FE32 194 CAPCOM 6 Register 1 0000 CC62 FE344 1Ay CAPCOM 6 Register 2 0000 CMP13 FE36y 1By CAPCOM 6 Timer 13 Compare Register 00004 T2 FE40 204 GPT1 Timer 2 Register 0000 T3 FE42 214 GPT1 Timer 3 Register 0000 T4 FE444 224 GPT1 Timer 4 Register 0000 CC16 FE60y 304 CAPCOM Register 16 0000 CC17 FE62 314 CAPCOM Register 17 00004 CC18 FE64 324 CAPCOM Register 18 00004 CC19 FE66 334 CAPCOM Register 19 0000 CC24 FE70y 38H CAPCOM Register 24 0000 CC25 FE72y 394
45. F102 E81 POH Direction Control Register 00 Semiconductor Group 23 5 Version 1 0 11 97 SIEMENS The Register Set C164CI Name Physical 8 Bit Description Reset Address Address Value DPOL b F100 Ej 80 POL Direction Control Register 00H DP1H b F106 E 834 P1H Direction Control Register 001 DP1L b F1044 E 824 P1L Direction Control Register 00H DP3 b FFC6 E3u Port 3 Direction Control Register 00004 DP4 b FFCA E5y Port 4 Direction Control Register 00H DP8 b FFD6 EBu Port 8 Direction Control Register 00H DPPO FEOO 004 CPU Data Page Pointer 0 Register 10 bits 0000 DPP1 FE024 01g CPU Data Page Pointer 1 Register 10 bits 00014 DPP2 FE044 024 CPU Data Page Pointer 2 Register 10 bits 0002 DPP3 FEO6 034 CPU Data Page Pointer 3 Register 10 bits 0003 EXICON b F1C0 Ej E0 External Interrupt Control Register 00004 EXISEL b F1DA E EDy External Interrupt Source Select Register 0000 IDCHIP F07C E S3E Identifier 0A014 IDMANUF FO7E E 3Fy Identifier 1820 IDMEM FO7A E 3Dy Identifier X010 IDPROG F0784 E 3Cy Identifier XXXXy ISNC b FIDE E EF Interrupt Subnode Control Register 00004 LAR EFn44 X CAN Lower Arbitration Register msg n UUUU MCFG EFn6 X CAN Message Configuration Register msg n UUu MCR EFnO X CAN Message Control Register msg n UUUU MDC b FFOE 874 CPU
46. Flash memory is smaller than that eg 8 KByte Of course the total implemented memory may exceed 32 KBytes Code Memory Configuration during Reset The control input pin EA External Access enables the user to define the address area from which the first instructions after reset are fetched When EA is low 0 during reset the internal code memory is disabled and the first instructions are fetched from external memory When EA is high 1 during reset the internal code memory is globally enabled and the first instructions are fetched from the internal memory Note Be sure not to select internal memory access after reset on ROMIess devices Mapping the Internal ROM Area After reset the internal ROM area is mapped into segment 0 the system segment 00 0000 00 7FFFj4 as a default This is necessary to allow the first instructions to be fetched from locations 00 0000 ff The ROM area may be mapped to segment 1 01 00004 01 7FFF by setting bit ROMS1 in register SYSCON The internal ROM area may now be accessed through the lower half of segment 1 while accesses to segment 0 will now be made to external memory This adds flexibility to the system software The interrupt trap vector table which uses locations 00 0000 through 00 01FF is now part of the external memory and may therefore be modified ie the system software may now change interrupt trap handlers according to the current condition of the system The inte
47. Multi channel PWM Mode Selection This bitfield selects the output signal pattern in all multi channel PWM modes also refer to bitfield BCM 00 3 phase block commutation mode 01 4 phase multi channel PWM mode 10 5 phase multi channel PWM mode 11 6 phase multi channel PWM mode BCMP Machine polarity Valid only in multi channel PWM mode 0 Only the COUT6n outputs are switched to the timer T13 output signal during the active phase in multi channel PWM mode CMSELn3 must be set for that functionality 1 All enabled compare outputs COUT6n and CC6n are switched to the timer T13 output signal during their active phase in multi channel PWM mode BCEM Error mode select bit Valid only in block commutation mode 0 A wrong follower condition is not notified as an error 1 A wrong follower condition in rotate right or rotate left mode sets flag BCERR if EBCE is set Note When a multi channel PWM mode is initiated the first time after reset CC6MCON must be written twice first write operation with bit BCEN cleared and all other bits set cleared as required BCM must be 00 for idle mode followed by a second write operation with the same CC6MCON bit pattern of the first write operation but with BCEN set After this second CC6MCON write operation timer T12 can be started setting CT12R in CTCON and thereafter BCM can be put into another mode than the idle mode Semiconductor Group 17 23 Version 1 0 11 97 SIEMENS The Cap
48. Serial Data P3 92 x DP3 9 0 Output Input MRST Serial Data P3 8 X DP3 8 0 Serial Data P3 8 1 DP3 8 1 Input Output Note In the table above an x means that the actual value is irrelevant in the respective mode however it is recommended to set these bits to 1 so they are already in the correct state when switching between master and slave mode 12 3 Baud Rate Generation The serial channel SSC has its own dedicated 16 bit baud rate generator with 16 bit reload capability allowing baud rate generation independent from the timers The baud rate generator is clocked with the CPU clock divided by 2 fcpy 2 The timer is counting downwards and can be started or stopped through the global enable bit SSCEN in register SSCCON Register SSCBR is the dual function Baud Rate Generator Reload register Reading SSCBR while the SSC is enabled returns the content of the timer Reading SSCBR while the SSC is disabled returns the programmed reload value In this mode the desired reload value can be written to SSCBR Note Never write to SSCBR while the SSC is enabled Semiconductor Group 12 10 Version 1 0 11 97 SIEM ENS The High Speed Synchronous Serial Interface C164CI The formulas below calculate either the resulting baud rate for a given reload value or the required reload value for a given baudrate fopu fopu Bssc T SSCBR lt SSCBR gt 1 2 Baudrategsc
49. The Capture Compare Unit CAPCOM6 C164Cl Block Commutation Mode Block commutation mode is a special variation of the multi channel modes where the phase sequence is not controlled internally but rather by the 3 input signals CC6POS2 0 The state of the 6 output signals is derived from the pattern present on the input signals The table below summarizes the possible combinations In block commutation mode CAPCOM channel 0 is automatically configured for capture mode Any signal transition at inputs CC6POS2 0 generates a capture pulse for CAPCOM channel 0 The values provide a measure for the rotation speed of the connected drive Note Modulation of the active phase via T12 is not supported PWM via T13 is possible on COUTEx Block Commutation Sequence Table Block Comm Control Inputs Output Level Definition Mode BCM CC6POS for actual state 0 1 2 CC60 CC61 CC62 COUT60 COUT61 COUT62 Rotate Left 1 0 1 passive passive ACTIVE ACTIVE passive passive 1 0 0 passive ACTIVE passive ACTIVE passive passive 1 1 0 passive ACTIVE passive passive passive ACTIVE 0 1 0 ACTIVE passive passive passive passive ACTIVE 0 1 1 ACTIVE passive passive passive ACTIVE passive 0 0 1 passive passive ACTIVE passive ACTIVE passive Rotate Right 1 1 0 ACTIVE passive passive passive ACTIVE passive 1 0 0 ACTIVE passive passive passi
50. The tri state time defines when the external device has released the bus after deactivation of the read command RD Segment X Address I l l l ALE N TIS paar 4 9 N71 ER Wait State ANA MCT02065 Figure 9 6 Memory Tri State Time The output of the next address on the external bus can be delayed for a memory or peripheral which needs more time to switch off its bus drivers by introducing a wait state after the previous bus cycle see figure above During this memory tri state time wait state the CPU is not idle so CPU operations will only be slowed down if a subsequent external instruction or data fetch operation is required during the next instruction cycle The memory tri state time waitstate requires one CPU clock 50 ns at fc py 20 MHz and is controlled via the MTTCx bits of the BUSCON registers A waitstate will be inserted if bit MTTCx is 0 default after reset Note External bus cycles in multiplexed bus modes implicitly add one tri state time waitstate in addition to the programmable MTTC waitstate Semiconductor Group 9 11 Version 1 0 11 97 SIEMENS The External Bus Interface C164CI Read Write Signal Delay The C164CI allows the user to adjust the timing of the read and write commands to account for timing requirements of external peripherals The read write delay controls the time between the falling edge of ALE and the falling edge of the command Without
51. Version 1 0 11 97 SIEMENS The Central Processing Unit CPU C164Cl The Context Pointer CP This non bit addressable register is used to select the current register context This means that the CP register value determines the address of the first General Purpose Register GPR within the current register bank of up to 16 wordwide and or bytewide GPRs CP FE10 08 SFR Reset Value FC00 15 14 11 10 9 8 7 6 5 4 3 2 1 0 13 12 r r r r rw r Bit Function cp Modifiable portion of register CP Specifies the word base address of the current register bank When writing a value to register CP with bits CP 11 CP 9 000 bits CP 11 CP 10 are set to 11 by hardware in all other cases all bits of bit field cp receive the written value Note It is the user s responsibility that the physical GPR address specified via CP register plus short GPR address must always be an internal RAM location If this condition is not met unexpected results may occur Do not set CP below the IRAM start address ie 00 FA00 00 F600 00 F200 1 2 3KB e Do not set CP above 00 FDFE Be careful using the upper GPRs with CP above 00 FDEO The CP register can be updated via any instruction which is capable of modifying an SFR Note Due to the internal instruction pipeline a new CP value is not yet usable for GPR address calculations of the instruction immediately following the instruction updating the CP register
52. Version 1 0 11 97 SIEMENS The On Chip CAN Interface C164CI Tx Rx Shift Register The Transmit Receive Shift Register holds the destuffed bit stream from the bus line to allow the parallel access to the whole data or remote frame for the acceptance match test and the parallel transfer of the frame to and from the Intelligent Memory Bit Stream Processor The Bit Stream Processor BSP is a sequencer controlling the sequential data stream between the Tx Rx Shift Register the CRC Register and the bus line The BSP also controls the EML and the parallel data stream between the Tx Rx Shift Register and the Intelligent Memory such that the processes of reception arbitration transmission and error signalling are performed according to the CAN protocol Note that the automatic retransmission of messages which have been corrupted by noise or other external error conditions on the bus line is handled by the BSP Cyclic Redundancy Check Register This register generates the Cyclic Redundancy Check CRC code to be transmitted after the data bytes and checks the CRC code of incoming messages This is done by dividing the data stream by the code generator polynomial Error Management Logic The Error Management Logic EML is responsible for the fault confinement of the CAN device Its counters the Receive Error Counter and the Transmit Error Counter are incremented and decremented by commands from the Bit Stream Processor According to the
53. accordingly for the new task before this task is entered Semiconductor Group 4 16 Version 1 0 11 97 SIEMENS The Central Processing Unit CPU C164Cl CPU Interrupt Status IEN ILVL The Interrupt Enable bit allows to globally enable IEN 1 or disable IEN 0 interrupts The four bit Interrupt Level field ILVL specifies the priority of the current CPU activity The interrupt level is updated by hardware upon entry into an interrupt service routine but it can also be modified via software to prevent other interrupts from being acknowledged In case an interrupt level 15 has been assigned to the CPU it has the highest possible priority and thus the current CPU operation cannot be interrupted except by hardware traps or external non maskable interrupts For details please refer to chapter Interrupt and Trap Functions After reset all interrupts are globally disabled and the lowest priority ILVL 0 is assigned to the initial CPU activity The Instruction Pointer IP This register determines the 16 bit intra segment address of the currently fetched instruction within the code segment selected by the CSP register The IP register is not mapped into the C164Cl s address space and thus it is not directly accessable by the programmer The IP can however be modified indirectly via the stack by means of a return instruction The IP register is implicitly updated by the CPU for branch instructions and after instruction
54. and a jump is taken to the specified vector location When segmentation is enabled and a trap is executed the CSP for the trap service routine is set to code segment 0 No Interrupt Request flags are affected by the TRAP instruction The interrupt service routine called by a TRAP instruction must be terminated with a RETI return from interrupt instruction to ensure correct operation Note The CPU level in register PSW is not modified by the TRAP instruction so the service routine is executed on the same priority level from which it was invoked Therefore the service routine entered by the TRAP instruction can be interrupted by other traps or higher priority interrupts other than when triggered by a hardware trap Hardware Traps Hardware traps are issued by faults or specific system states that occur during runtime of a program not identified at assembly time A hardware trap may also be triggered intentionally eg to emulate additional instructions by generating an Illegal Opcode trap The C164Cl distinguishes eight different hardware trap functions When a hardware trap condition has been detected the CPU branches to the trap vector location for the respective trap condition Depending on the trap condition the instruction which caused the trap is either completed or cancelled ie it has no effect on the system state before the trap handling routine is entered Hardware traps are non maskable and always have priority over every other C
55. and 1 Block Diagram Note The port latch and pin remain unaffected in compare mode 0 In the example below the compare value in register CCx is modified from cv1 to cv2 after compare events 1 and 3 and from cv2 to cv1 after events 2 and 4 etc This results in periodic interrupt requests from timer Ty and in interrupt requests from register CCx which occur at the time specified by the user through cv1 and cv2 Contents of Ty FFFF H Compare Value cv2 Compare Value cv1 Reload Value lt TyREL gt 00004 Interrupt Requests TyIR CCxIR CCxIR TyIR CCxIR CCxIR TyIR t Event 1 Event 2 Event 3 Event 4 CCx cv2 CCx cv1 CCx cv2 CCx cv1 MCT02017 Figure 16 7 Timing Example for Compare Modes 0 and 1 Semiconductor Group 16 13 Version 1 0 11 97 SIEMENS The Capture Compare Unit CAPCOM2 C164Cl Compare Mode 1 Compare mode 1 is selected for register CCx by setting bit field CCMODx of the corresponding mode control register to 101p When a match between the content of the allocated timer and the compare value in register CCx is detected in this mode interrupt request flag CCxIR is set to 1 and in addition the corresponding output pin CCxIO alternate port output function is toggled For this purpose the state of the respective port output latch not the pin is read inverted and then written back to the output latch Compare mo
56. and divide instructions normally take more than one machine cycle These instructions however have also been optimized For example branch instructions only require an additional machine cycle when a branch is taken and most branches taken in loops require no additional machine cycles at all due to the so called Jump Cache A 32 bit 16 bit division takes 20 CPU clock cycles a 16 bit 16 bit multiplication takes 10 CPU clock cycles The instruction cycle time has been dramatically reduced through the use of instruction pipelining This technique allows the core CPU to process portions of multiple sequential instruction stages in parallel The following four stage pipeline provides the optimum balancing for the CPU core FETCH In this stage an instruction is fetched from the internal ROM or RAM or from the external memory based on the current IP value DECODE In this stage the previously fetched instruction is decoded and the required operands are fetched EXECUTE In this stage the specified operation is performed on the previously fetched operands WRITE BACK In this stage the result is written to the specified location If this technique were not used each instruction would require four machine cycles This increased performance allows a greater number of tasks and interrupts to be processed Instruction Decoder Instruction decoding is primarily generated from PLA outputs based on the selected opcode No microcode i
57. as the clock line while pins P3 8 MRST Master Receive Slave Transmit and P3 9 MTSR Master Transmit Slave Receive serve as the serial data input output lines The operation of these pins depends on the selected operating mode master or slave In order to enable the alternate output functions of these pins instead of the general purpose IO operation the respective port latches have to be set to 1 since the port latch outputs and the alternate output lines are ANDed When an alternate data output line is not used function disabled it is held at a high level allowing IO operations via the port latch The direction of the port lines depends on the operating mode The SSC will automatically use the correct alternate input or output line of the ports when switching modes The direction of the pins however must be programmed by the user as shown in the tables Using the open drain output feature helps to avoid bus contention problems and reduces the need for hardwired hand shaking or slave select lines In this case it is not always necessary to switch the direction of a port pin The table below summarizes the required values for the different modes and pins SSC Port Control Pin Master Mode Slave Mode Function Port Latch Direction Function Port Latch Direction SCLK Serial Clock P3 132 1 DP3 13 1 Serial Clock P3 13 x DP3 13 0 Output Input MTSR Serial Data P3 9 1 DP3 9 2 1
58. between ideal and real frequency and therefore accumulates over time The total accuracy of the RTC can be further increased via software for specific applications that demand a high time accuracy The key to the improved accuracy is the knowledge of the exact oscillator frequency The relation of this frequency to the expected ideal frequency is a measure for the RTC s deviation The number N of cycles after which this deviation causes an error of 1 cycle can be easily computed So the only action is to correct the count by 1 after each series of N cycles This correction may be applied to the RTC register as well as to T14 Also the correction may be done cyclic eg within T14 s interrupt service routine or by evaluating a formula when the RTC registers are read for this the respective last RTC value must be available somewhere Note For the majority of applications however the standard accuracy provided by the RTC s structure will be more than sufficient Semiconductor Group 14 4 Version 1 0 11 97 SIEMENS The Bootstrap Loader C164Cl 15 The Bootstrap Loader The built in bootstrap loader of the C164Cl provides a mechanism to load the startup program which is executed after reset via the serial interface In this case no external memory or an internal ROM OTP Flash is required for the initialization code starting at location 00 0000 The bootstrap loader moves code data into the internal RAM but it is also pos
59. bigger can be realized via software This mechanism is supported by registers STKOV and STKUN see respective descriptions below The SP register can be updated via any instruction which is capable of modifying an SFR Note Due to the internal instruction pipeline a POP or RETURN instruction must not immediately follow an instruction updating the SP register SP FE124 094 SFR Reset Value FC00 15 14 11 10 9 8 7 6 5 4 3 2 1 0 13 12 cbpbl l l ut sss s lt r r r r rw r Bit Function sp Modifiable portion of register SP Specifies the top of the internal system stack Semiconductor Group 4 24 Version 1 0 11 97 SIEMENS The Central Processing Unit CPU C164Cl The Stack Overflow Pointer STKOV This non bit addressable register is compared against the SP register after each operation which pushes data onto the system stack eg PUSH and CALL instructions or interrupts and after each subtraction from the SP register If the content of the SP register is less than the content of the STKOV register a stack overflow hardware trap will occur Since the least significant bit of register STKOV is tied to 0 and bits 15 through 12 are tied to 1 by hardware the STKOV register can only contain values from FOOO to FFFEy STKOV FE14 0A SFR Reset Value FA00 15 14 11 10 9 8 7 6 5 4 3 2 1 0 13 12 a e e r r r r rw r Bit Function stkov Modifiable portion of register STKOV Specifies the lo
60. can be a positive a negative or both a positive and a negative transition The two least significant bits of bit field Txl are used to select the active transition see table in the counter mode section while the most significant bit Txl 2 is irrelevant for capture mode It is recommended to keep this bit cleared Txl 2 0 Note When programmed for capture mode the respective auxiliary timer T2 or T4 stops independent of its run flag T2R or T4R Edge Select Capture Register Tx TxIN C7 P3 7 P3 5 X ES Txl inst Clock Core Timer T3 Interrupt rar Interrupt T3IR Request Up Down T3OTL a X 2 4 T30E MCB02038 Figure 10 13 GPT1 Auxiliary Timer in Capture Mode Upon a trigger selected transition at the corresponding input pin TxIN the contents of the core timer are loaded into the auxiliary timer register and the associated interrupt request flag TxIR will be set Note The direction control bits for T2IN and T4IN must be set to 0 and the level of the capture trigger signal should be held high or low for at least 8 fc p cycles before it changes to ensure correct edge detection Semiconductor Group 10 17 Version 1 0 11 97 SIEM ENS The General Purpose Timer Unit C164Cl Interrupt Control for GPT1 Timers When a timer overflows from FFFF to 00004 when counting up or when it underflows from 0000 to FFFF when counting down its interrupt request flag T2IR T3IR or T4
61. can be interrupted during their execution to allow for very fast Semiconductor Group 2 3 Version 1 0 11 97 SIEMENS Architectural Overview C164Cl interrupt response Instructions have also been provided to allow byte packing in memory while providing sign extension of bytes for word wide arithmetic operations The internal bus structure also allows transfers of bytes or words to or from peripherals based on the peripheral requirements A set of consistent flags is automatically updated in the PSW after each arithmetic logical shift or movement operation These flags allow branching on specific conditions Support for both signed and unsigned arithmetic is provided through user specifiable branch tests These flags are also preserved automatically by the CPU upon entry into an interrupt or trap routine All targets for branch calculations are also computed in the central ALU A 16 bit barrel shifter provides multiple bit shifts in a single cycle Rotates and arithmetic shifts are also supported Extended Bit Processing and Peripheral Control A large number of instructions has been dedicated to bit processing These instructions provide efficient control and testing of peripherals while enhancing data manipulation Unlike other microcontrollers these instructions provide direct access to two operands in the bit addressable space without requiring to move them into temporary flags The same logical instructions available for words and
62. converts short hardware reset pulses to a minimum duration of the internal reset sequence Bidirectional reset is enabled by setting bit BDRSTEN in register SYSCON and changes RSTIN from a pure input to an open drain IO line When an internal reset is triggered by the SRST instruction or by a watchdog timer overflow or a low level is applied to the RSTIN line an internal driver pulls it low for the duration of the internal reset sequence After that it is released and is then controlled by the external circuitry alone The Bidirectional reset function is useful in applications where external devices require a defined reset signal but cannot be connected to the C164Cl s RS TOUT signal eg an external flash memory which must come out of reset and deliver code well before RSTOUT can be deactivated via EINIT The following behaviour differences must be observed when using the Bidirectional reset feature in an application e Bit BDRSTEN in register SYSCON cannot be changed after EINIT e After a reset bit BDRSTEN is cleared e Bit WDTR will always be 0 even after a watchdog timer reset e The PORTO configuration is treated like on a hardware reset Especially the bootstrap loader may be activated when POL 4 is low e Pin RSTIN may only be connected to external reset devices with an open drain output driver Semiconductor Group 20 3 Version 1 0 11 97 SIEMENS System Reset C164CI The C164CI s Pins after Reset After the reset sequ
63. direct drive or prescaler mode must be configured If the on chip oscillator is not supplied with a clock signal the oscillator watchdog must not be disabled so the PLL can provide the clock signal instead CPU Host Mode Programming CHM is useful for in system programming especially combined with the bootstrap loader mode CHM programming cycles are controlled via the C164Cl s programming interface which replaces the external bus interface signals Pin EA Vpp accepts the external programming voltage during programming cycles see diagram The programming interface is realized as an XBUS peripheral and uses the address area OO0 EDCO OOEDDF The interface is activated only in programming mode and cannot be accessed in all other cases The OTP module s interface signals are not externally asserted but rather controlled via three registers Semiconductor Group 3 13 Version 1 0 11 97 SIEMENS Memory Organization C164CI OTP Programming Interface Registers Register Physical Description Reset Name Address Value OPCTRL EDCO Control register provides the control signals and the upper 8 0007 address lines A23 A16 OPAD EDC2 Address register provides the lower 15 address lines of the 0000 physical OTP word address A15 A1 Note Address line AO is not evaluated OPDAT EDC4 Data register provides the word to be stored or read from the 00004 module OPCTRL EDCO XReg Reset Value 0007
64. direction register DP4 P4 FFC8 E44 SFR Reset Value 00 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw Bit Function P4 y Port data register P4 bit y DP4 FFCA E5y SFR Reset Value 00 15 14 13 12 11 10 9 8 7 6 5 4 38 2 1 0 rw rw rw rw rw rw Bit Function DP4 y Port direction register DP4 bit y DP4 y 0 Port line P4 y is an input high impedance DP4 y 1 Port line P4 y is an output Alternate Functions of Port 4 During external bus cycles that use segmentation ie an address space above 64 KByte a number of Port 4 pins may output the segment address lines or a selectable number of chip select lines The number of pins that is used for segment address output determines the external address space which is directly accessible The other pins of Port 4 if any may be used for general purpose IO or for the CAN interface If segment address lines are selected the alternate function of Port 4 may be necessary to access eg external memory directly after reset For this reason Port 4 will be switched to this alternate function automatically The number of segment address and or chip select lines is selected via PORTO during reset The selected value can be read from bitfield SALSEL or CSSEL in register RPOH read only eg in order to check the configuration during run time The CAN interface uses 2 pins of Port4 to interface the CAN Module to an external CAN transceiv
65. e Interrupt requests will still be recognized even while PCD is disabled No new output values are gated from the port output latches to the output port pins and no new input values are latched from the input port pins Semiconductor Group 21 11 Version 1 0 11 97 SIEMENS Power Management C164Cl Security Mechanism The power management control registers SYSCON2 and SYSCONGS control functions and modes which are critical for the C164Cl s operation For this reason they are locked except for bitfield SYSRLS in register SYSCONO after the execution of EINIT like register SYSCON so these vital system functions cannot be changed inadvertently eg by software errors However as these registers control the power management they need to be accessed during operation to select the appropriate mode The system control software gets this access via a special unlock sequence which allows one single write access to either SYSCON2 or SYSCONS when executed properly This provides a maximum of security Note Of course SYSCON2 and SYSCONS may be read at any time without restrictions The unlock sequence is executed by writing defined values to bitfield SYSRLS using defined instructions see table below The instructions of the unlock sequence including the intended write access must be secured with an EXTR instruction switch to ESFR space and lock interrupts Note The unlock sequence provides no write access to register SYSCON SYSCON2 SYSC
66. error and three selectable error status flags in register SOCON which indicate which error has been detected during reception Upon completion of a reception the error interrupt request flag SOEIR will be set simultaneously with the receive interrupt request flag SORIR if one or more of the following conditions are met Ifthe framing error detection enable bit SOFEN is set and any of the expected stop bits is not high the framing error flag SOFE is set indicating that the error interrupt request is due to a framing error Asynchronous mode only e Ifthe parity error detection enable bit SOPEN is set in the modes where a parity bit is received and the parity check on the received data bits proves false the parity error flag SOPE is set indicating that the error interrupt request is due to a parity error Asynchronous mode only Ifthe overrun error detection enable bit SOOEN is set and the last character received was not read out of the receive buffer by software or PEC transfer at the time the reception of a new frame is complete the overrun error flag SOOE is set indicating that the error interrupt request is due to an overrun error Asynchronous and synchronous mode 11 4 ASCO Baud Rate Generation The serial channel ASCO has its own dedicated 13 bit baud rate generator with 13 bit reload capability allowing baud rate generation independent of the GPT timers The baud rate generator is clocked with the CPU clock divided by 2
67. external interface or the OTP programming interface In this case the OTP module appears as a contiguous block using the physical addresses 00 0000 to 00 FFFFy Note When entering a programming mode EHM or CHM the on chip OTP module is disabled independent from the selection via pin EA The programming software in CHM must not enable the OTP module s CPU interface by setting bit ROMEN in register SYSCON Semiconductor Group 3 15 Version 1 0 11 97 SIEMENS Memory Organization C164Cl OTP Programming Example The on chip OTP memory is programmed in CHM executing the following procedure Note The example below assumes segment 0 RH3 00 MOV R1 OTP_START MOV R2 DATA_BLOCK MOV R3 0003H MOV DPP3 OPCTRL R3 BSET VPP ENABLE CALL MICROSEC 010 PROG OTP WORD MOV DPP3 OPAD R1 MOV RO R24 MOV DPP3 OPDAT RO MOV R3 0001H MOV DPP3 OPCTRL R3 CALL MICROSEC 100 MOV R3 0003H MOV DPP3 OPCTRL R3 ALT VERIFY BCLR VPP ENABLE CALL MICROSEC 010 MOV R3 0002H MOV DPP3 OPCTRL R3 MOV R3 0003H MOV DPP3 OPCTRL R3 CMP RO DPP3 OPDAT JMP cc NE PROG FAILED BSET VPP ENABLE CALL MICROSEC 010 PROG LOOP CMPI2 R1 BLOCK_LIMIT JMP cc ULE PROG OTP WORD BCLR VPP ENABLE CALL MICROSEC 010 MOV R3 0007H MOV DPP3 OPCTRL R3 Semiconductor Group R1 OTP pointer R2 Source data pointer 03H enable module cmd idle Initially enable the OTP module External progr voltage ON Le
68. faa 4 2 5 to 5 MHz Default configuration 1 1 0 fea 3 3 33 to 6 66 MHz 1 0 1 3352 5 to 10 MHz 100 fea 5 210 4 MHz O 1 1 3o i 1 to 20 MHz 2 Direct drive 2 O 1 0 faa 1 5 6 66 to 13 3 MHz 0 0 1 haa 2 2 to 40 MHz Prescaler operation 0 0 0 Feta 2 5 4to 8 MHz 1 The external clock input range refers to a CPU clock range of 10 20 MHz for PLL operation which is the specified operating frequency band for the PLL The maximum depends on the duty cycle of the external clock signal In emulation mode pin P0 15 POH 7 is inverted ie the configuration 111 would select direct drive in emulation mode 2 Default On chip PLL is active with a factor of 1 4 Note Watch the different requirements for frequency and duty cycle of the oscillator input clock for the possible selections Oscillator Watchdog Control The on chip oscillator watchdog OWD may be disabled via hardware by externally pulling the RD line low upon a reset similar to the standard reset configuration via PORTO At the end of any reset bit OWDDIS in register SYSCON reflects the inverted level of pin RD at that time The software may again enable the oscillator watchdog by clearing bit OWDDIS before the execution of EINIT Note If direct drive or prescaler operation is selected as basic clock generation mode see above the PLL is switched off whenever bit OWDDIS is set via software or via hardware configuration Semiconductor Group 20 13 V
69. how to use the MDH register for programming multiply and divide algorithms can be found in chapter System Programming The Multiply Divide Low Register MDL This register is a part of the 32 bit multiply divide register which is implicitly used by the CPU when it performs a multiplication or a division After a multiplication this non bit addressable register represents the low order 16 bits of the 32 bit result For long divisions the MDL register must be loaded with the low order 16 bits of the 32 bit dividend before the division is started After any division register MDL represents the 16 bit quotient MDL FEOE 0714 SFR Reset Value 0000 15 14 13 12 Td 10 9 8 7 6 5 4 3 2 l 0 rw Bit Function mdl Specifies the low order 16 bits of the 32 bit multiply and divide register MD Semiconductor Group 4 27 Version 1 0 11 97 SIEMENS The Central Processing Unit CPU C164Cl Whenever this register is updated via software the Multiply Divide Register In Use MDRIU flag in the Multiply Divide Control register MDC is set to 1 The MDRIU flag is cleared whenever the MDL register is read via software When a multiplication or division is interrupted before its completion and when a new multiply or divide operation is to be performed within the interrupt service routine register MDL must be saved along with registers MDH and MDC to avoid erroneous results A detailed description of how to use the MDL register
70. however do not preclude the use of complex instructions which are required by microcontroller users The following goals were used to design the instruction set 1 Provide powerful instructions to perform operations which currently require sequences of instructions and are frequently used Avoid transfer into and out of temporary registers such as accumulators and carry bits Perform tasks in parallel such as saving state upon entry into interrupt routines or subroutines 2 Avoid complex encoding schemes by placing operands in consistent fields for each instruc tion Also avoid complex addressing modes which are not frequently used This decreases the instruction decode time while also simplifying the development of compilers and assem blers 3 Provide most frequently used instructions with one word instruction formats All other instruc tions are placed into two word formats This allows all instructions to be placed on word boundaries which alleviates the need for complex alignment hardware It also has the bene fit of increasing the range for relative branching instructions The high performance offered by the hardware implementation of the CPU can efficiently be utilized by a programmer via the highly functional C164Cl instruction set which includes the following instruction classes Arithmetic Instructions Logical Instructions Boolean Bit Manipulation Instructions Compare and Loop Control Instructions Shift and Rotate I
71. ie the on chip CAN Module can receive and transmit standard frames with 11 bit identifiers as well as extended frames with 29 bit identifiers It provides Full CAN functionality on up to 15 full sized message objects 8 data bytes each Message object 15 may be configured for Basic CAN functionality with a double buffered receive object Both modes provide separate masks for acceptance filtering which allows the acceptance of a number of identifiers in Full CAN mode and also allows disregarding a number of identifiers in Basic CAN mode All message objects can be updated independent from the other objects and are equipped with buffers for the maximum message length of 8 bytes The bit timing is derived from the XCLK and is programmable up to a data rate of 1 MBaud fcpu 2 16 MHz The CAN Module uses two pins of Port 4 to interface to a bus transceiver The CAN module combines several functional blocks see figure below that work in parallel and contribute to the controller s performance These units and the functions they provide are described below Each of the message objects has a unique identifier and its own set of control and status bits Each object can be configured with its direction as either transmit or receive except the last message which is only a double receive buffer with a special mask register An object with its direction set as transmit can be configured to be automatically sent whenever a remote frame with a matching iden
72. in bootstrap loader is activated independent of the selected bus mode The bootstrap loader code is stored in a special Boot ROM no part of the standard mask ROM OTP or Flash memory area is required for this After entering BSL mode and the respective initialization the C164Cl scans the RXDO line to receive a zero byte ie one start bit eight 0 data bits and one stop bit From the duration of this zero byte it calculates the corresponding baudrate factor with respect to the current CPU clock initializes the serial interface ASCO accordingly and switches pin TxDO to output Using this baudrate an identification byte is returned to the host that provides the loaded data This identification byte identifies the device to be bootet The following codes are defined 55u 8xC166 A5y Previous versions of the C167 obsolete B5 C165 C54 C167 derivatives D5 All devices equipped with identification registers Note The identification byte D5 does not directly identify a specific derivative This information can in this case be obtained from the identification registers When the C164CI has entered BSL mode the following configuration is automatically set values that deviate from the normal reset values are marked Watchdog Timer Disabled Register STKUN FA40y Context Pointer CP FAO00 Register STKOV FAOCy 0 lt gt C Stack Pointer SP FA40 Register BUSCONO acc to startup config Register SOCON 8011 P3 10 TXD
73. is detected even when the interrupt was not serviced because of a higher CPU priority or a globally disabled interrupt system IEN 0 The CPU will only go back into Idle mode when the interrupt system is globally enabled IEN 1 and a PEC service on a priority level higher than the current CPU level is requested and executed Note An interrupt request which is individually enabled and assigned to priority level O will terminate Idle mode The associated interrupt vector will not be accessed however The watchdog timer may be used to monitor the Idle mode an internal reset will be generated if no interrupt or NMI request occurs before the watchdog timer overflows To prevent the watchdog timer from overflowing during Idle mode it must be programmed to a reasonable time interval before Idle mode is entered Semiconductor Group 21 3 Version 1 0 11 97 SIEMENS Power Management C164Cl 21 2 Power Down Mode To further reduce the power consumption the microcontroller can be switched to Power Down mode Clocking of all internal blocks is stopped RTC and selected oscillator optionally the contents of the internal RAM however are preserved through the voltage supplied via the Vpp pins The watchdog timer is stopped in Power Down mode This mode can only be terminated by an external hardware reset ie by asserting a low level on the RSTIN pin This reset will initialize all SFRs and ports to their default state but will not change th
74. is the receive interrupt vector and SOEINT is the error interrupt vector The cause of an error interrupt request framing parity overrun error can be identified by the error status flags in control register SOCON Note In contrary to the error interrupt request flag SOEIR the error status flags SOFE SOPE SOOE are not reset automatically upon entry into the error interrupt service routine but must be cleared by software SOTIC FF6Cj B64 SFR Reset Value 00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 SORIC FF6E B7 SFR EUN 7 SOEIC FF70 B8p SFR Reset Value 00 7 6 5 4 3 2 1 0 wee mo mal rw rw rw rw SOTBIC F19Cy CEy ESFR Reset Value 00 23 14 13 12 11 10 9 8 7 5 4 3 2 1 0 TBIR TBIE ILVL GLVL rw rw rw rw Note Please refer to the general Interrupt Control Register description for an explanation of the control fields Semiconductor Group 11 12 Version 1 0 11 97 Sl EM ENS The Asynchronous Synchronous Serial Interface C164CI Using the ASCO Interrupts For normal operation ie besides the error interrupt the ASCO provides three interrupt requests to control data exchange via this serial channel SOTBIR is activated when data is moved from SOTBUF to the transmit shift register SOTIR is activated before the last bit of an asynchronous frame is transmitted or after the last bit of a synchronous frame has been transmitted SORIR is activated whe
75. lines if the CAN interface is to be used CAN TxD CAN C164CI Interface CAN Bus SAN RXD Physical Layer Figure 19 5 Connection to the CAN Bus More information about the on chip CAN interface is provided in the separate document The On Chip CAN Module Advance Information 05 93 Future versions of this manual will also provide more detailled information Semiconductor Group 19 20 Version 1 0 11 97 SIEMENS System Reset C164CI 20 System Reset The internal system reset function provides initialization of the C164Cl into a defined default state and is invoked either by asserting a hardware reset signal on pin RSTIN Hardware Reset Input upon the execution of the SRST instruction Software Reset or by an overflow of the watchdog timer Whenever one of these conditions occurs the microcontroller is reset into its predefined default state through an internal reset procedure When a reset is initiated pending internal hold states are cancelled and the current internal access cycle if any is completed An external bus cycle is aborted except for a watchdog reset see description After that the bus pin drivers and the IO pin drivers are switched off tristate RSTOUT is activated depending on the reset source The internal reset procedure requires 516 CPU clock cycles in order to perform a complete reset sequence This 516 cycle reset sequence is started upon a watchdog timer overflow a SRST ins
76. long 16 bit addressing modes except for override accesses via EXTended instructions and PEC data transfers After reset the Data Page Pointers are initialized in a way that all indirect or direct long 16 bit addresses result in identical 18 bit addresses This allows to access data pages 3 0 within segment 0 as shown in the figure below If the user does not want to use any data paging no further action is required DPPO FE00 004 SFR Reset Value 00004 15 14 11 10 9 8 7 6 5 4 3 2 1 0 13 12 rw DPP1 FE02 011 SFR Reset Value 00014 15 14 1 11 10 9 8 7 6 5 4 3 2 1 0 3 12 rw DPP2 FE04 02 SFR Reset Value 0002 15 14 11 10 9 8 7 6 5 4 3 2 1 0 13 12 rw DPP3 FE06 03 SFR Reset Value 00034 15 14 11 10 9 8 7 6 5 4 3 2 1 0 13 12 rw Bit Function DPPxPN Data Page Number of DPPx Specifies the data page selected via DPPx Only the least significant two bits of DPPx are significant when segmentation is disabled Semiconductor Group 4 20 Version 1 0 11 97 SIEMENS The Central Processing Unit CPU C164Cl Data paging is performed by concatenating the lower 14 bits of an indirect or direct long 16 bit address with the contents of the DPP register selected by the upper two bits of the 16 bit address The contents of the selected DPP register specify one of the 1024 possible data pages This data page base address together with the 14 bit page offset forms the physical 24 bit address
77. lt SSCBR gt represents the content of the reload register taken as unsigned 16 bit integer The maximum baud rate that can be achieved when using a CPU clock of 20 MHz is 5 MBaud The table below lists some possible baud rates together with the required reload values and the resulting bit times assuming a CPU clock of 20 MHz Baud Rate Bit Time Reload Value Reserved Use a reload value gt 0 00004 5 0 MBaud 200 ns 00014 3 3 MBaud 300 ns 00024 2 5 MBaud 400 ns 0003 2 0 MBaud 500 ns 00044 1 0 MBaud 1 us 00094 100 KBaud 10 us 0063 10 KBaud 100 us 03E7y 1 0 KBaud 1 ms 270Fy 152 8 Baud 6 6 ms FFFFy Note The contents of SSCBR must be gt 0 Semiconductor Group 12 11 Version 1 0 11 97 SIEM ENS The High Speed Synchronous Serial Interface C164CI 12 4 Error Detection Mechanisms The SSC is able to detect four different error conditions Receive Error and Phase Error are detected in all modes while Transmit Error and Baudrate Error only apply to slave mode When an error is detected the respective error flag is set When the corresponding Error Enable Bit is set also an error interrupt request will be generated by setting SSCEIR see figure below The error interrupt handler may then check the error flags to determine the cause of the error interrupt The error flags are not reset automatically like SSCEIR but rather must be cleared by software after servicing This allows ser
78. of specific ports These special thresholds are defined above the TTL thresholds and feature a defined hysteresis to prevent the inputs from toggling while the respective input signal level is near the thresholds The Port Input Control register PICON allows to select these thresholds for each byte of the indicated ports ie 8 bit ports are controlled by one bit each while 16 bit ports are controlled by two bits each Semiconductor Group 7 2 Version 1 0 11 97 SIEMENS Parallel Ports C164CI PICON F1C4 E24 ESFR Reset Value 004 8 7 6 5 4 3 2 1 0 rw wo IW Bit Function PxLIN Port x Low Byte Input Level Selection 0 Pins Px 7 Px 0 switch on standard TTL input levels 1 Pins Px 7 Px 0 switch on special threshold input levels PxHIN Port x High Byte Input Level Selection 0 Pins Px 15 Px 8 switch on standard TTL input levels 1 Pins Px 15 Px 8 switch on special threshold input levels All options for individual direction and output mode control are availbale for each pin independent from the selected input threshold The input hysteresis provides stable inputs from noisy or slowly changing external signals Bit state Figure 7 3 Hysteresis for Special Input Thresholds Semiconductor Group 7 3 Version 1 0 11 97 SIEMENS Parallel Ports C164CI Alternate Port Functions In order to provide a maximum of flexibility for different applications and the
79. otherwise 2 For multiplexed buses with 8 bit data bus 3 The CS signal that corresponds to the last address remains active low all other enabled CS signals remain inactive high By accessing an on chip X Peripheral prior to entering a power save mode all external CS signals can be deactivated Semiconductor Group 21 6 Version 1 0 11 97 SIEMENS Power Management C164Cl 21 3 Slow Down Operation A separate clock path can be selected for Slow Down operation bypassing the basic clock path used for standard operation The programmable Slow Down Divider SDD divides the oscillator frequency by a factor of 1 32 which is specified via bitfield CLKREL in register SYSCON2 When bitfield CLKREL is written during SDD operation the reload counter will output one more clock pulse with the old frequency in order to resynchronize internally before generating the new frequency mmc E UE eam uem ie nho m dd CLKREL Reload Counter fosc fsoo Lm 3S al aye SS jee Se reU eS 4S SX Figure 21 3 Slow Down Divider Operation Using eg a 5 MHz input clock the on chip logic may be run at a frequency down to 156 25 KHz without an external hardware change An implemented PLL may be switched off in this case or kept running depending on the requirements of the application see table below Note During Slow Down operation the whole device including bus interface and generation of signal CLKOUT is clocke
80. priority levels level O cannot be arbitrated Interrupt requests that are programmed to priority levels 15 or 14 ie ILVL 111Xg will be serviced by the PEC unless the COUNT field of the associated PECC register contains zero In this case the request will instead be serviced by normal interrupt processing Interrupt requests that are programmed to priority levels 13 through 1 will always be serviced by normal interrupt processing Note Priority level 0000g is the default level of the CPU Therefore a request on level 0 will never be serviced because it can never interrupt the CPU However an enabled interrupt request on level 0000g will terminate the C164Cl s Idle mode and reactivate the CPU For interrupt requests which are to be serviced by the PEC the associated PEC channel number is derived from the respective ILVL LSB and GLVL see figure below So programming a source to priority level 15 ILVL21111g selects the PEC channel group 7 4 programming a source to priority level 14 ILVL 11105 selects the PEC channel group 3 0 The actual PEC channel number is then determined by the group priority field GLVL Interrupt Control Register PEC Control Figure 5 1 Priority Levels and PEC Channels Simultaneous requests for PEC channels are prioritized according to the PEC channel number where channel 0 has lowest and channel 8 has highest priority Note All sources that request PEC service must be programmed to different
81. selectable part is driven to the address pins In case of non segmented memory mode only the two least significant bits of the implicitly selected DPP register are used to generate the physical address Thus extreme care should be taken when changing the content of a DPP register if a non segmented memory model is selected because otherwise unexpected results could occur In case of the segmented memory mode the selected number of segment address bits via bitfield SALSEL of the respective DPP register is output on the respective segment address pins of Port 4 for all external data accesses A DPP register can be updated via any instruction which is capable of modifying an SFR Note Due to the internal instruction pipeline a new DPP value is not yet usable for the operand address calculation of the instruction immediately following the instruction updating the DPP register Data Pages 6 Bit Data Address 15 14 0 1023 1022 1021 ae DPP Registers v 3 DPP3 11 14 Bi Intra Page Address 2 Ww DPP2 10 Concatenated with 4 e 4 DPP1 0 1 content of DPPx 0 DPP0 0 0 MCA02264 After reset or with segmentation disabled the DPP registers select data pages 3 0 All of the internal memory is accessible in these cases Figure 4 6 Addressing via the Data Page Pointers Semiconductor Group 4 21
82. standard baudrate that fulfills this requirement is 19200 Baud Higher baudrates however may be used as long as the actual deviation does not exceed the limit A certain baudrate marked l in the figure may eg violate the deviation limit while an even higher baudrate marked ll in the figure stays very well below it This depends on the host interface Semiconductor Group 15 6 Version 1 0 11 97 SIEMENS The Capture Compare Unit CAPCOM2 C164Cl 16 The Capture Compare Unit CAPCOM2 The C164Cl provides a Capture Compare CAPCOM unit which provides 8 channels which interact with 2 timers The CAPCOM unit can capture the contents of a timer on specific internal or external events or can compare a timer s contents with given values and modify output signals in case of a match With this mechanism it supports generation and control of timing sequences on up to 8 channels with a minimum of software intervention From the programmer s point of view the term CAPCOM unit refers to a set of SFRs which are associated with this peripheral including the port pins which may be used for alternate input output functions including their direction control bits Ports amp Direction Control Data Registers Control Registers Interrupt Control Alternate Functions T78CON T7IC E T8IC E CC16 19 CCM4 CC16IC 19IC E CC24 27 CCM6 CC241C 271C E CC16lO P8 0 CC191O P8 3 CC24IO P1H 4 CC271O P1H 7 ODP8 Port 8 Open Drain Contro
83. suspended The temporary register can hold data for ADDAT from a standard conversion or for ADDAT2 from an injected conversion dx 3x1 x 2 x 3 Conversion of Channel Wait until LE ADDAT2 is Write ADDAT x 1 ix x1 read x 2 x3 ADDAT Full LJ E i 1 L Read ADDAT xd dx x 1 x 2 x 3 Conversion Channel Injection of Channel y Request by CC31 1 E a ADDAT2 Ful ee 4 Int Request ADEINT Read ADDAT2 dz y SS Temp Latch Ful Tx x 1 Conversion of Channel Write ADDAT ADDAT Ful Read ADDAT Temp Latch Full Channel Injection E Request by CC31 unti ADDAT2 Full read Int Request ADEINT Read ADDAT2 y MCA01972 Figure 18 6 Channel Injection Example with Wait for Read Semiconductor Group 18 8 Version 1 0 10 97 SIEMENS The Analog Digital Converter C164Cl Arbitration of Conversions Conversion requests that are activated while the ADC is idle immediately trigger the respective conversion If a conversion is requested while another conversion is currently in progress the operation of the A D converter depends on the kind of the involved conversions standard or injected Note A conversion request is activated if the respective control bit ADST or ADCRQ is toggled from 0 to 1 ie the bit must have been zero before being set The table below summarizes the ADC operation in the possible situations Conversion Arbitration Conve
84. this second generation provide additional features like additional internal high speed RAM an integrated CAN Module an on chip PLL etc Utilizing integration to design efficient systems may require the integration of application specific peripherals to boost system performance while minimizing the part count These efforts are supported by the so called XBUS defined for the Siemens 16 bit microcontrollers second generation This XBUS is an internal representation of the external bus interface that opens and simplifies the integration of peripherals by standardizing the required interface One representative taking advantage of this technology is the integrated CAN module The C165 type devices are reduced versions of the C167 which provide a smaller package and reduced power consumption at the expense of the A D converter the CAPCOM units and the PWM module The C164 type devices and some of the C161 type devices are further enhanced by a flexible power management and form the third generation of the 16 bit controller family This power management mechanism provides effective means to control the power that is consumed in a certain state of the controller and thus allows the minimization of the overall power consumption with respect to a given application Semiconductor Group 1 2 Version 1 0 11 97 SIEMENS Introduction C164CI A variety of different versions is provided which offer various kinds of on chip program memory mask
85. to any internal address area ie when no external bus cycle is started even if this area is covered by the respective ADDRSELx register An access to an on chip X Peripheral deactivates all external CS signals Upon accesses to address windows without a selected CS line all selected CS lines are deactivated The chip select signals allow to be operated in four different modes see table below which are selected via bits CSWENx and CSRENXx in the respective BUSCONXx register Semiconductor Group 9 6 Version 1 0 11 97 SIEMENS The External Bus Interface C164CI CSWENx CSRENx Chip Select Mode 0 Address Chip Select Default after Reset 1 Read Chip Select 0 Write Chip Select 1 Read Write Chip Select O Read or Write Chip Select signals remain active only as long as the associated control signal RD or WR is active This also includes the programmable read write delay Read chip select is only activated for read cycles write chip select is only activated for write cycles read write chip select is activated for both read and write cycles write cycles are assumed if any of the signals WRH or WRL gets active These modes save external glue logic when accessing external devices like latches or drivers that only provide a single enable input Address Chip Select signals remain active during the complete bus cycle For address chip select signals two generation modes can be selected via bi
86. to reset configuration BUSCONO OXX0 set according to reset configuration RPOH XX reset levels of POH ONES FFFF fixed value Semiconductor Group 20 5 Version 1 0 11 97 SIEMENS System Reset C164CI The Internal RAM after Reset The contents of the internal RAM are not affected by a system reset However after a power on reset the contents of the internal RAM are undefined This implies that the GPRs R15 RO and the PEC source and destination pointers SRCP7 SRCPO DSTP7 DSTPO which are mapped into the internal RAM are also unchanged after a warm reset software reset or watchdog reset but are undefined after a power on reset Ports and External Bus Configuration during Reset During the internal reset sequence all of the C164Cl s port pins are configured as inputs by clearing the associated direction registers and their pin drivers are switched to the high impedance state This ensures that the C164Cl and external devices will not try to drive the same pin to different levels Pin ALE is held low through an internal pulldown and pins RD and WR are held high through internal pullups Also the pins selected for CS output will be pulled high The registers SYSCON and BUSCONO are initialized according to the configuration selected via PORTO When an external start is selected pin EA 0 the Bus Type field BTYP in register BUSCONO is initialized according to POL 7 and POL 6 bit BUSACTO in register BU
87. transition at the respective external input pin CCxlO The triggering transition is selected by the mode bits CCMODx in the respective CAPCOM mode control register In any case the event causing a capture will also set the respective interrupt request flag CCxIR which can cause an interrupt or a PEC service request when enabled Ed N Capture Reg CCx A ose 4 X eon J 5 CCMODx Input Interrupt X 27 24 19 16 Clock P CAPCOM Timer Ty TYIR Beques Bun MCB02015 Figure 16 5 Capture Mode Block Diagram In order to use the respective port pin as external capture input pin CCxIO for capture register CCx this port pin must be configured as input ie the corresponding direction control bit must be set to 0 To ensure that a signal transition is properly recognized an external capture input signal should be held for at least 8 CPU clock cycles before it changes its level During these 8 CPU clock cycles the capture input signals are scanned sequentially When a timer is modified or incremented during this process the new timer contents will already be captured for the remaining capture registers within the current scanning sequence If pin CCxlO is configured as output the capture function may be triggered by modifying the corresponding port output latch via software eg for testing purposes Semiconductor Group 16 11 Version 1 0 11 97 SIEMENS The Capture Compare Unit CAPCOM2 C164Cl 16 5 Compare
88. trap can interrupt a class B trap If more than one class A trap occur at a time they are prioritized internally with the NMI trap on the highest and the stack underflow trap on the lowest priority All class B traps have the same trap priority trap priority I When several class B traps get active at a time the corresponding flags in the TFR register are set and the trap service routine is entered Since all class B traps have the same vector the priority of service of simultaneously occurring class B traps is determined by software in the trap service routine A class A trap occurring during the execution of a class B trap service routine will be serviced immediately During the execution of a class A trap service routine however any class B trap occurring will not be serviced until the class A trap service routine is exited with a RETI instruction In this case the occurrence of the class B trap condition is stored in the TFR register but the IP value of the instruction which caused this trap is lost In the case where e g an Undefined Opcode trap class B occurs simultaneously with an NMI trap class A both the NMI and the UNDOPC flag is set the IP of the instruction with the undefined opcode is pushed onto the system stack but the NMI trap is executed After return from the NMI service routine the IP is popped from the stack and immediately pushed again because of the pending UNDOPC trap External NMI Trap Whenever a high to
89. values of the error counters the CAN controller is set into the states error active error passive and busoff The CAN controller is error active if both error counters are below the error passive limit of 128 It is error passive if at least one of the error counters equals or exceeds 128 It goes busoff if the Transmit Error Counter equals or exceeds the busoff limit of 256 The device remains in this state until the busoff recovery sequence is finished Additionally there is the bit EWRN in the Status Register which is set if at least one of the error counters equals or exceeds the error warning limit of 96 EWRN is reset if both error counters are less than the error warning limit Bit Timing Logic This block BTL monitors the busline input CAN RxD and handles the busline related bit timing according to the CAN protocol The BTL synchronizes on a recessive to dominant busline transition at Start of Frame hard synchronization and on any further recessive to dominant busline transition if the CAN controller itself does not transmit a dominant bit resynchronization The BTL also provides programmable time segments to compensate for the propagation delay time and for phase shifts and to define the position of the Sample Point in the bit time The programming of the BTL depends on the baudrate and on external physical delay times Semiconductor Group 19 3 Version 1 0 11 97 SIEMENS The On Chip CAN Interface C164CI Intel
90. via bit ROMEN in register SYSCON This bit is set during reset according to the level on pin EA or may be altered via software If enabled the internal ROM area occupies the lower 32 KByte of either segment 0 or segment 1 This ROM mapping is controlled by bit ROMS1 in register SYSCON Note The size of the internal ROM area is independent of the size of the actual implemented ROM Also devices with less than 32 KByte of ROM or with no ROM at all will have this 32 KByte area occupied if the ROM is enabled Devices with larger ROMs provide the mapping option only for the ROM area Devices with a ROM size above 32 KByte expand the ROM area from the middle of segment 1 ie starting at address 01 8000 The internal ROM Flash can be used for both code instructions and data constants tables etc storage Code fetches are always made on even byte addresses The highest possible code storage location in the internal ROM is either xx xxFE for single word instructions or xx xxFC for double word instructions The respective location must contain a branch instruction unconditional because sequential boundary crossing from internal ROM to external memory is not supported and causes erroneous results Any word and byte data read accesses may use the indirect or long 16 bit addressing modes There is no short addressing mode for internal ROM operands Any word data access is made to an even byte address The highest possible word data stor
91. when bit ECT130 is reset COUT63 disabled BCM Multi channel PWM Mode Output Pattern Selection This bitfield selects the output signal pattern in all multi channel PWM modes also refer to bitfield MPWM 00 Idle mode 01 Rotate right mode 10 Rotate left mode 11 Slow down mode BCEN Block Commutation Enable 0 The multi channel PWM modes of the 16 bit capture compare channels selected by bitfield MPWM are disabled 1 The multi channel PWM modes are enabled Note Before bit BCEN is set all required PWM compare outputs should be pro grammed to operate as compare outputs by writing to register CC6MSEL Semiconductor Group 17 22 Version 1 0 11 97 SIEMENS The Capture Compare Unit CAPCOM6 C164Cl Bit Function BCERR Block Commutation Mode Error Flag 0 No error condition 1 An error condition in rotate right or rotate left mode has occurred After a transition at CC6POSx all CC6POSx inputs are at high or low level A wrong follower condition has occurred see description of bit BCEM If the block commutation interrupt is enabled EBCE 1 also a CAPCOM6 emergency interrupt will be generated BCERR must be cleared by software EBCE Enable Block Commutation Mode Error Interrupt 0 Block commutation mode error does not generate an interrupt 1 The emergency interrupt is activated for a block commutation mode error Refer to the description of bits BCERR and BCEM MPWM
92. 00ns 1 6us 3 2us 6 4us 12 8us 25 6 us 51 2 us Period 26ms 52 5ms 105ms 210 ms 420 ms 840 ms 1 68s 3 36 s After a timer has been started by setting its run flag TxR to 1 the first increment will occur within the time interval which is defined by the selected timer resolution All further increments occur exactly after the time defined by the timer resolution When both timers of a CAPCOM unit are to be incremented or reloaded at the same time T7 is always serviced one CPU clock before T8 Semiconductor Group 16 6 Version 1 0 11 97 SIEMENS The Capture Compare Unit CAPCOM2 C164Cl Counter Mode The bits TxM in SFR T78CON select between timer or counter mode for the respective timer In Counter mode TxM 1 the input clock for a timer can be derived from the overflows underflows of timer T3 in block GPT1 In addition timer T7 can be clocked by external events Either a positive a negative or both a positive and a negative transition at pin T7IN alternate port input function can be selected to cause an increment of T7 When T8 is programmed to run in counter mode bit field Txl is used to enable the overflows underflows of timer T3 as the count source This is the only option for T8 and it is selected by the combination Txl 000g When bit field Txl is programmed to any other valid combination timer T8 will stop When T7 is programmed to run in counter mode bit field Txl is used to
93. 02235 Semiconductor Group 9 9 Version 1 0 11 97 SIEMENS The External Bus Interface C164CI Programmable Memory Cycle Time The C164CI allows the user to adjust the controller s external bus cycles to the access time of the respective memory or peripheral This access time is the total time required to move the data to the destination It represents the period of time during which the controller s signals do not change Wait States 0 Segment X Address X l l ALE N l i l RD T eX WR i MCT02063 Figure 9 5 Memory Cycle Time The external bus cycles of the C164Cl can be extended for a memory or peripheral which cannot keep pace with the controllers maximum speed by introducing wait states during the access see figure above During these memory cycle time wait states the CPU is idle if this access is required for the execution of the current instruction The memory cycle time wait states can be programmed in increments of one CPU clock 50 ns at fc py 20 MHz within a range from 0 to 15 default after reset via the MCTC fields of the BUSCON registers 15 lt MCTC gt waitstates will be inserted Semiconductor Group 9 10 Version 1 0 11 97 SIEMENS The External Bus Interface C164CI Programmable Memory Tri State Time The C164Cl allows the user to adjust the time between two subsequent external accesses to account for the tri state time of the external device
94. 0o 0008 Internal i ROM 00 4000 4 Reserved Area Data Page 0 00 F200 H ESFR Area 00 0000 H 00 F000y System Segment 0 RAM SFR Area 64 KByte 4 KByte MCD02233 Figure 3 3 Internal RAM Area and SFR Areas Note The upper 256 bytes of SFR area ESFR area and internal RAM are bit addressable see shaded blocks in the figure above Semiconductor Group 3 4 Version 1 0 11 97 Memory Organization SIEMENS C164CI Code accesses are always made on even byte addresses The highest possible code storage location in the internal RAM is either 00 FDFE for single word instructions or 00 FDFC for double word instructions The respective location must contain a branch instruction unconditional because sequential boundary crossing from internal RAM to the SFR area is not supported and causes erroneous results Any word and byte data in the internal RAM can be accessed via indirect or long 16 bit addressing modes if the selected DPP register points to data page 3 Any word data access is made on an even byte address The highest possible word data storage location in the internal RAM is 00 FDFE For PEC data transfers the internal RAM can be accessed independent of the contents of the DPP registers via the PEC source and destination pointers The upper 256 Byte of the internal RAM 00 FD00 through 00 FDFF 4 and the GPRs of the current bank are provided for single bit storage and thus they are bit addressable System Stack
95. 1 events ie et eS tee uus A Timer T13 period CT13P i 1 o IE Figure 17 13 CAPCOM6 Interrupt Structure Semiconductor Group 17 26 Version 1 0 11 97 SIEMENS The Capture Compare Unit CAPCOM6 C164Cl Interrupt Node Control Registers T12IC F190 C8 ESFR Reset Value 00004 15 14 13 12 11 10 9 8 7 6 5 4 3 2 T12IR T12IE ILVL GLVL rw rw iz ES ES ES 1 L z H z eo T13IC F198 CCy ESFR Reset Value 0000 fee cnet Rm ere fet TENTER NEC NM QUE NN NEC T13IR T13IE ILVL GLVL rw rw _ 2 o CC6EIC F188j C44 ESFR Reset Value 00004 15 14 13 12 11 10 9 8 6 5 4 3 2 iun ru ILVL GLVL rw rw L L L E L L JE ex Z o CC6CIC F17E BFy ESFR Reset Value 0000 5 4 3 2 rt brc ILVL GLVL rw k L I i L JE 2 2 o Note Please refer to the general Interrupt Control Register description for an explanation of the control fields Semiconductor Group 17 27 Version 1 0 11 97 SIEMENS The Analog Digital Converter C164CI 18 The Analog Digital Converter The C164CI provides an Analog Digital Converter with 10 bit resolution and a sample amp hold circuit on chip A multiplexer selects between up to 8 analog input channels alternate functions of Port 5 either via software fixed channel modes or automatically auto scan modes An automatic self calibration adjusts the ADC module to changing temperatures or process variations To fulf
96. 1 0 11 97 SIEMENS Interrupt and Trap Functions C164CI 5 Interrupt and Trap Functions The architecture of the C164Cl supports several mechanisms for fast and flexible response to service requests that can be generated from various sources internal or external to the microcontroller These mechanisms include Normal Interrupt Processing The CPU temporarily suspends the current program execution and branches to an interrupt service routine in order to service an interrupt requesting device The current program status IP PSW in segmentation mode also CSP is saved on the internal system stack A prioritization scheme with 16 priority levels allows the user to specify the order in which multiple interrupt requests are to be handled Interrupt Processing via the Peripheral Event Controller PEC A faster alternative to normal software controlled interrupt processing is servicing an interrupt requesting device with the C164Cl s integrated Peripheral Event Controller PEC Triggered by an interrupt request the PEC performs a single word or byte data transfer between any two locations in segment 0 data pages 0 through 3 through one of eight programmable PEC Service Channels During a PEC transfer the normal program execution of the CPU is halted for just 1 instruction cycle No internal program status information needs to be saved The same prioritization scheme is used for PEC service as for normal interrupt processing PEC transfers
97. 1 0 11 97 SIEMENS Memory Organization C164Cl 3 3 External Memory Space The C164Cl is capable of using an address space of up to 16 MByte Only parts of this address space are occupied by internal memory areas All addresses which are not used for on chip memory ROM or RAM or for registers may reference external memory locations This external memory is accessed via the C164Cl s external bus interface Four memory bank sizes are supported Non segmented mode 64 KByte with A15 A0 on PORTO 2 bit segmented mode 256 KByte with A17 A16 on Port 4 and A15 A0 on PORTO 4 bit segmented mode 1 MByte with A19 A16 on Port 4 and A15 A0 on PORTO 6 bit segmented mode 4 MByte with A21 A16 on Port 4 and A15 A0 on PORTO Each bank can be directly addressed via the address bus while the programmable chip select signals can be used to select various memory banks The C164CI also supports two different bus types e Multiplexed 16 bit Bus with address and data on PORTO Default after Reset e Multiplexed 8 bit Bus with address and data on PORTO POL Memory model and bus mode are selected during reset by pin EA and PORTO pins For further details about the external bus configuration and control please refer to chapter The External Bus Interface External word and byte data can only be accessed via indirect or long 16 bit addressing modes using one of the four DPP registers There is no short addressing mode for external o
98. 16 bit Data Multiplexed e 16 18 20 22 bit Addresses 8 bit Data Multiplexed The multiplexed bus modes use PORTO for both addresses and data input output Port 4 is used for the upper address lines A16 if selected Important timing characteristics of the external bus interface waitstates ALE length and Read Write Delay have been made programmable to allow the user the adaption of a wide range of different types of memories and or peripherals u For applications which require less than 64 KBytes of address space a non segmented memory model can be selected where all locations can be addressed by 16 bits and thus Port 4 is not needed as an output for the upper address bits Axx A16 as is the case when using the segmented memory model The on chip XBUS is an internal representation of the external bus and allows to access integrated application specific peripherals modules in the same way as external components It provides a defined interface for these customized peripherals The on chip CAN Module is an example for these X Peripherals Semiconductor Group 2 8 Version 1 0 11 97 SIEMENS Architectural Overview C164Cl 2 3 The On chip Peripheral Blocks The C166 family clearly separates peripherals from the core This structure permits the maximum number of operations to be performed in parallel and allows peripherals to be added or deleted from family members without modifications to the core Each functional block proce
99. 164Cl Cache Jump Instruction Processing The C164Cl incorporates a jump cache to optimize conditional jumps which are processed repeatedly within a loop Whenever a jump on cache is taken the extra time to fetch the branch target instruction can be saved and thus the corresponding cache jump instruction in most cases takes only one machine cycle This performance is achieved by the following mechanism Whenever a cache jump instruction passes through the decode stage of the pipeline for the first time and provided that the jump condition is met the jump target instruction is fetched as usual causing a time delay of one machine cycle In contrast to standard branch instructions however the target instruction of a cache jump instruction JMPA JMPR JB JBC JNB JNBS is additionally stored in the cache after having been fetched After each repeatedly following execution of the same cache jump instruction the jump target instruction is not fetched from progam memory but taken from the cache and immediatly injected into the decode stage of the pipeline see figure below A time saving jump on cache is always taken after the second and any further occurrence of the same cache jump instruction unless an instruction which has the fundamental capability of changing the CSP register contents JMPS CALLS RETS TRAP RETI or any standard interrupt has been processed during the period of time between two following occurrences of the same c
100. 166 E B3 CAPCOM Register 19 Interrupt Control Register 0000 CC24 FE70y 38H CAPCOM Register 24 00004 CC24IC b F170 E B8j CAPCOM Register 24 Interrupt Control Register 0000 CC25 FE72y 394 CAPCOM Register 25 0000 CC25IC b F172 E B9j CAPCOM Register 25 Interrupt Control Register 0000 CC26 FE74 3Ay CAPCOM Register 26 00004 CC26lIC b F174 E BAy CAPCOM Register 26 Interrupt Control Register 0000 CC27 FE76 3By CAPCOM Register 27 0000 CC271lC b F176 E BB CAPCOM Register 27 Interrupt Control Register 0000 CC60 FE30y 184 CAPCOM 6 Register 0 00004 CC61 FE32 194 CAPCOM 6 Register 1 0000 CC62 FE34 1Ay CAPCOM 6 Register 2 0000 CC6EIC b F188 E C4 CAPCOM 6 Emergency Interrupt Control Reg 0000 CC6IC b F17E E BFy CAPCOM 6 Interrupt Control Register 00004 CC6MCON b FF32 994 CAPCOM 6 Mode Control Register OOFFy CC6MIC b FF36 9B CAPCOM 6 Mode Interrupt Control Register 0000 CCeMSEL F036 E 1By CAPCOM 6 Mode Select Register 0000 CC8IC b FF88u C4y CAPCOM Register 8 Interrupt Control Register 00004 CC9IC b FF8A C5y CAPCOM Register 9 Interrupt Control Register 00004 CCM4 b FF224 914 CAPCOM Mode Control Register 4 00004 CCM6 b FF264 934 CAPCOM Mode Control Register 6 0000 CMP13 FE36y 1By CAPCOM 6 Timer 13 Compare Register 00004 CP FE10y 08y CPU Context Pointer Register FCOO CSP FEO8 044 CPU Code Segment Pointer Register 0000 8 bits not directly writeable CTCON b FF30 984 CAPCOM 6 Compare Timer Control Register 10104 DPOH b
101. 2 12 ee ee ee TS 160 E OoOoo0o0o0o0o0ob5orIr SLS aacaacaagas A N aac wo Po Figure 25 1 Pin Description for C164Cl P MQFP 80 Package Semiconductor Group 25 2 Version 1 0 11 97 SIEMENS Index C164CI 26 Index Mode Configuration 9 2 20 11 Multiplexed 9 3 A BUSCONx 9 15 9 19 Acronyms 1 7 Adapt Mode 20 9 C ADC 2 14 18 1 CiBTR 19 10 ADCIC ADEIC 18 11 C1CSR 19 6 ADCON 18 3 C1GMS 19 11 ADDAT ADDAT2 18 4 C1IR 19 8 Address CiLGML 19 11 Arbitration 9 19 CiLMLM 19 12 Area Definition 9 18 C1UGML 19 11 Boundaries 3 10 C1UMLM 19 12 Segment 9 6 20 12 CAN Interface 2 11 19 1 ADDRSELx 9 17 9 19 CAPCOM 2 13 ALE length 9 9 interrupt 16 19 ALU 4 14 timer 16 4 Analog Digital Converter 2 14 18 1 Trap Function 17 17 Arbitration unit 16 1 17 1 Address 9 19 Capture Mode ASCO 11 1 CAPCOM2 16 11 Error Detection 11 10 CAPCOM6 17 11 Interrupts 11 12 GPT1 10 17 Asynchronous Serial Interface gt ASC0 11 1 X Capture Compare unit 16 1 17 1 Auto Scan conversion 18 5 CC6IC CC6EIC 17 27 CC6MCON 17 22 B CC6MIC 17 25 Baudrate CC6MSEL 17 24 ASCO 11 10 CCM4 CCM6 16 9 Bootstrap Loader 15 5 CCxIC 5 23 16 19 CAN 19 10 Center Aligned Mode SSC 12 10 CAPCOM6 17 7 BHE 7 16 9 5 Chip Select Bidirectional reset 20 3 Configuration 9 6 20 12 Bit Latched Early 9 7 addressable memory 3 4 Clock Handling 4 9 distribution 6 1 21 10 Manipulation Instructions 24 2 generator modes 6 6 20 13 protected 2 16 4 9 Compare modes 16
102. 2 5 22 6 22 7 22 8 22 9 22 10 22 11 23 23 1 23 2 23 3 23 4 24 25 26 27 The Analog Digital Converter Mode Selection and Operation Conversion Timing Control A D Converter Interrupt Control The On Chip CAN Interface System Reset 05 Power Management Idle MGS istos emo 8 Sous Gee IEEE Power Down Mode Slow Down Operation Flexible Peripheral Management System Programming Stack Operations Register Banking Procedure Call Entry and Exit Table Searching Peripheral Control and Interface Floating Point Support Trap Interrupt Entry and Exit Unseparable Instruction Sequences Overriding the DPP Addressing Mechanism Handling the Internal Code Memory Pits Traps and Mines The Register Set CPU General Purpose Registers GPRs Special Function Registers ordered by Name Registers ordered by Address Special Notes lues Instruction Set Summary Device Specification Microelectronics Training Center Information on Literature Semiconductor Group Addresses Semiconductor Group Page Version 1 0 11 97 SIEMENS Introduction C164CI 1 Introduction The rapidly growing area of embedded control applications is representing one of the most time critical operating environment
103. 3 2 l 0 Bit Function ILLBUS Illegal External Bus Access Flag An external access has been attempted with no external bus defined ILLINA Illegal Instruction Access Flag A branch to an odd address has been attempted ILLOPA Illegal Word Operand Access Flag A word operand access read or write to an odd address has been attempted PRTFLT Protection Fault Flag A protected instruction with an illegal format has been detected UNDOPC Undefined Opcode Flag The currently decoded instruction has no valid C164Cl opcode STKUF Stack Underflow Flag The current stack pointer value exceeds the content of register STKUN STKOF Stack Overflow Flag The current stack pointer value falls below the content of register STKOV NMI Non Maskable Interrupt Flag A negative transition falling edge has been detected on pin NMI Semiconductor Group 5 26 Version 1 0 11 97 SIEMENS Interrupt and Trap Functions C164CI Note The trap service routine must clear the respective trap flag otherwise a new trap will be requested after exiting the service routine Setting a trap request flag by software causes the same effects as if it had been set by hardware The reset functions hardware software watchdog may be regarded as a type of trap Reset functions have the highest system priority trap priority III Class A traps have the second highest priority trap priority II on the 3rd rank are class B traps so a class A
104. 3 is enabled and outputs the PWM signal of the 10 bit compare channel CT13P Timer T13 Period Flag The period flag CT13P is set whenever the contents of timer T13 match the contents of the timer T13 period register This also generates an interrupt request Bit CT13P must be cleared by software TRCON FF34j 9Ay SFR Reset Value 00004 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TRP TR TR TR TR TR TR EN TRF EN5 EN4 EN3 EN2 EN1 ENO rw rw rw rw rw rw rw rw s 2 7 7 Bit Function TRENn Trap Enable Control Bits at even bit positions 0 2 4 are assigned to the CC6n compare outputs bits at odd bit positions 1 3 5 are assigned to the COUT6n compare outputs 0 Compare channel output provides CAPCOM output signal in trap state 1 Compare channel output is enabled to set the logic level of the compare output CC6n or COUTS6n in the trap state to a logic state as defined by the corresponding bits of the port output latch register Note When writing TRENn bit TRF should be 0 otherwise a trap state interrupt will be generated TRF Trap Flag TRF is set by hardware if the trap function is enabled TRPEN 1 and CTRAP becomes active low If enabled an interrupt is generated when TRF is set TRF must be cleared by software TRPEN External CTRAP Trap Function Enable Bit 0 External trap input CTRAP is disabled default after reset 1 External trap input CTRAP is enabled
105. 4 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Function EXIOSS External Interrupt 0 Source Selection Field 0 0 Input from associated EXOIN pin 0 1 Input from CAN RxD pin 1 0 Input from EXOIN pin ORed with CAN RxD pin 1 1 Input from EXOIN pin ANDed with CAN RxD pin Semiconductor Group 5 24 Version 1 0 11 97 SIEMENS Interrupt and Trap Functions C164CI 5 7 Trap Functions Traps interrupt the current execution similar to standard interrupts However trap functions offer the possibility to bypass the interrupt system s prioritization process in cases where immediate system reaction is required Trap functions are not maskable and always have priority over interrupt requests on any priority level The C164CI provides two different kinds of trapping mechanisms Hardware traps are triggered by events that occur during program execution eg illegal access or undefined opcode software traps are initiated via an instruction within the current execution flow Software Traps The TRAP instruction is used to cause a software call to an interrupt service routine The trap number that is specified in the operand field of the trap instruction determines which vector location in the address range from 00 0000 through 00 01FC will be branched to Executing a TRAP instruction causes a similar effect as if an interrupt at the same vector had occurred PSW CSP in segmentation mode and IP are pushed on the internal system stack
106. 5 selectable via CLKCFG see table below and generates a CPU clock signal with 50 duty cycle ie fopy fosc F The on chip PLL circuit allows operation of the C164Cl on a low frequency external clock while still providing maximum performance The PLL also provides fail safe mechanisms which allow the detection of frequency deviations and the execution of emergency actions in case of an external clock failure When the PLL detects a missing input clock signal it generates an interrupt request This warning interrupt indicates that the PLL frequency is no more locked ie no more stable This occurs when the input clock is unstable and especially when the input clock fails completely eg due to a broken crystal In this case the synchronization mechanism will reduce the PLL output frequency down to the PLL s base frequency 2 5 MHz The base frequency is still generated and allows the CPU to execute emergency actions in case of a loss of the external clock On power up the PLL provides a stable clock signal within ca 1 ms after Vpp has reached 5 V t 1096 even if there is no external clock signal in this case the PLL will run on its base frequency of 2 5 MHz The PLL starts synchronizing with the external clock signal as soon as it is available Within ca 1 ms after stable oscillations of the external clock within the specified frequency range the PLL will be synchronous with this clock at a frequency of F fosc ie the PLL locks to t
107. 5 10 5 3 Prioritization of Interrupt and PEC Service Requests usus 5 13 5 4 Saving the Status during Interrupt Service 0 00 eee ees 5 14 5 5 Interrupt Response Times io suere anana 5 16 5 6 External Interrupts se o re quine aie oC Eee aU oe uve dre di ue ua fo 5 21 5 7 Trap uestis i erena i cash ral Stile oh NN E T eh AE EEA E e a 5 25 6 Clock Generation eq e e quee es ege e tee ER 6 1 6 1 IOSellldlOE i ethos UGE Eee t eA EDUC CEREREM MS Een IE 6 2 6 2 Frequency COMM ss i Sdn tee doe ederet eee Dae a heed SOR derer de get 6 3 6 3 Oscillator Watchdog 233g E tie oe aioe DERIT exw Ramey ween Re 6 8 6 4 CIOGK Drivers eos Uis E Sea ore ean ee eee y eau anes waa ants 6 9 7 Parallel POWMS aori nn Re oe EC RO ee a e es 7 1 7 1 POO E MUT 7 6 7 2 POTIUS dessus ee au du e Us tct Qu Dub EA Edad d Xu E ACRES 7 9 7 3 PORS a ccs toad dace eee ded ine Rede d Ses update le ended eee tes ed 7 12 7 4 Dol d eun MettcsuP ame C uc PI LR Patti to e e C 7 17 7 5 POMS is pies edebat b emus eb landet uw dunt eb Kov dea deter TLE du 7 20 7 6 POllO ain 43 0 eee re wee she wee wie ee Baas oo OG RIECOOLB RUPEE Ss 7 23 8 Dedicated Pins 2 asia cok teats SAU So etna Ros UU e dt 8 1 Semiconductor Group l 1 Version 1 0 11 97 SIEMENS General Information Table of Contents 9 9 1 9 2 9 3 9 4 9 5 10 11 11 1 11 2 11 3 11 4 11 5 12 12 1 12 2 12 3 12 4 12 5 13 14 15 16 16 1 16 2 16 3 16 4 16 5
108. 6x all shadow registers are transparent Leave CT12RES 0 in capture mode STE12 Timer T12 Shadow Latch Transfer Enable 0 Transfer from the shadow latches to the period compare and offset registers T12P CC6x T12OF of timer T12 is disabled 1 1T12 s period compare and offset registers are loaded from their shadow latches when T12 reaches the period value mode 0 or 0000 mode 1 Note STE12 is cleared by hardware after the shadow latch transfer ETRP Emergency Trap Interrupt Enable 0 The emergency interrupt for the CAPCOMS trap signal is disabled 1 The emergency interrupt for the CAPCOM6 trap signal is enabled CTM T12 Operating Mode 0 Edge Aligned Mode count up 1 Center Aligned Mode count up down Semiconductor Group 17 20 Version 1 0 11 97 SIEMENS The Capture Compare Unit CAPCOM6 C164Cl Bit Function STE13 Timer T13 Shadow Latch Transfer Enable 0 Transfer from the shadow latches to the period and compare registers CC62 CMPx of timer T13 is disabled 1 The period and compare registers of timer T13 are loaded from their shadow latches when T13 reaches the respective period value Note STE13 is cleared by hardware after the shadow latch transfer ECT130 Enable compare timer T13 output 0 When ECT130 is cleared and timer T13 is running signal COUT63 outputs the selected passive logic level COUTSI 1 When ECT130 is set and timer T13 is running timer T13 output COUT6
109. 7 SIEMENS The Capture Compare Unit CAPCOM2 C164CI Contents of Ty FFFF H Compare Value cv2 Compare Value cv1 Reload Value lt TyREL gt 77 00004 Interrupt Requests TyIR CCxIR CCxIR TyIR CCxIR CCxIR TyIR State ot CCxIO 1 TLO TFL t MCT02023 x 19 16 y 7 8 Z 27 24 Figure 16 11 Timing Example for Double Register Compare Mode 16 6 Capture Compare Interrupts Upon a capture or compare event the interrupt request flag CCxIR for the respective capture compare register CCx is set to 1 This flag can be used to generate an interrupt or trigger a PEC service request when enabled by the interrupt enable bit CCxIE Capture interrupts can be regarded as external interrupt requests with the additional feature of recording the time at which the triggering event occurred see also section External Interrupts Each of the 8 capture compare registers has its own bitaddressable interrupt control register CC161C CC19IC CC241C CC271C and its own interrupt vector CC16INT CC19INT CC24INT CC27INT These registers are organized the same way as all other interrupt control registers The figure below shows the basic register layout and the table lists the associated addresses CCxIC See Table SFR ESFR Reset Value 00 75 4 19 12 NO 9 8 7 86 9 4 3 29 1 0 x x rw rw rw rw Note Please refer to the general Interrupt Control Re
110. 7E E 3Fy Identifier 1820 ADDAT2 FOAO E 50 A D Converter 2 Result Register 00004 SSCTB FOBO E 58 SSC Transmit Buffer write only 0000 SSCRB FOB2 E 59 SSC Receive Buffer read only XXXXy Semiconductor Group 23 10 Version 1 0 11 97 SIEMENS The Register Set C164CI Name Physical 8 Bit Description Reset Address Address Value SSCBR FOB4 E 5A SSC Baudrate Register 0000 T14REL FODO E 68 RTC Timer 14 Reload Register XXXXy T14 FOD2 E 69 RTC Timer 14 Register XXXXy RTCL FOD4y E 6Ay RTC Low Register XXXXy RTCH FOD6 E 6By RTC High Register XXXXy DPOL b F100 Ej 80 POL Direction Control Register 00H DPOH b F102 E81 POH Direction Control Register 00 DP1L b F104 E 824 P1L Direction Control Register 004 DP1H b F106 E 834 P1H Direction Control Register 00 RPOH b F1084 E 844 System Startup Configuration Register Rd only XXy CC16IC b F1604 E B0 CAPCOM Register 16 Interrupt Control Register 0000 CC171IC b F162 E B1y CAPCOM Register 17 Interrupt Control Register 00004 CC18IC b F164 E B2j CAPCOM Register 18 Interrupt Control Register 0000 CC19IC b F166 E B3 CAPCOM Register 19 Interrupt Control Register 0000 CC24IC b F170 E B8j CAPCOM Register 24 Interrupt Control Register 0000 CC25IC b F172 E B9yu CAPCOM Register 25 Interrupt Control Register 0000 CC26lC b F174 E BAy CAPCOM R
111. ALE Inactive low Pulses as defined for X Peripheral RD Inactive high Inactive high WR WRL Inactive high Inactive high WRH Inactive high Inactive high Semiconductor Group 9 21 Version 1 0 11 97 SIEMENS The External Bus Interface C164CI 9 5 The XBUS Interface The C164CI provides an on chip interface the XBUS interface which allows to connect integrated customer application specific peripherals to the standard controller core The XBUS is an internal representation of the external bus interface ie it is operated in the same way For each peripheral on the XBUS X Peripheral there is a separate address window controlled by a hardwired register pair similar to registers BUSCON and ADDRSEL As an interface to a peripheral in many cases is represented by just a few registers the registers partly select smaller address windows than the standard ADDRSEL registers As the register pairs control integrated peripherals rather than externally connected ones they are fixed by mask programming rather than being user programmable X Peripheral accesses provide the same choices as external accesses so these peripherals may be bytewide or wordwide with or without a separate address bus Interrupt nodes are provided for X Peripherals to be integrated Note If you plan to develop a peripheral of your own to be integrated into a C164Cl device to create a customer specific version please ask for the specification of th
112. APCOM Units The CAPCOM units are typically used to handle high speed IO tasks such as pulse and waveform generation pulse width modulation PWM Digital to Analog D A conversion software timing or time recording relative to external events A number of dedicated timers with reload registers provide independent time bases for the capture compare channels The input clock for the timers is programmable to several prescaled values of the internal CPU clock or may be derived from an overflow underflow of timer T3 in module GPT1 for CAPCOM2 timers This provides a wide range of variation for the timer period and resolution and allows precise adjustments to the application specific requirements In addition external inputs for the CAPCOM units allow event scheduling for the capture compare registers relative to external events The CAPCOM2 unit supports generation and control of timing sequences on up to 8 channels with a maximum resolution of 8 CPU clock cycles The capture compare register array contains 8 dual purpose capture compare registers each of which may be individually allocated to either CAPCOM2 timer T7 or T8 and programmed for capture or compare function Each register has one port pin associated with it which serves as an input pin for triggering the capture function or as an output pin except for CC24 CC27 to indicate the occurence of a compare event When a capture compare register has been selected for capture mode the
113. APCOM2 unit All port lines that are not used for these alternate functions may be used as general purpose IO lines Semiconductor Group 2 10 Version 1 0 11 97 SIEMENS Architectural Overview C164Cl Serial Channels Serial communication with other microcontrollers processors terminals or external peripheral components is provided by two serial interfaces with different functionality an Asynchronous Synchronous Serial Channel ASCO and a High Speed Synchronous Serial Channel SSC The ASCO is upward compatible with the serial ports of the Siemens 8 bit microcontroller families and supports full duplex asynchronous communication at up to 625 KBaud and half duplex synchronous communication at up to 2 5 MBaud 20 MHz CPU clock A dedicated baud rate generator allows to set up all standard baud rates without oscillator tuning For transmission reception and error handling 4 separate interrupt vectors are provided In asynchronous mode 8 or 9 bit data frames are transmitted or received preceded by a start bit and terminated by one or two stop bits For multiprocessor communication a mechanism to distinguish address from data bytes has been included 8 bit data plus wake up bit mode In synchronous mode the ASCO transmits or receives bytes 8 bits synchronously to a shift clock which is generated by the ASCO The ASCO always shifts the LSB first A loop back option is available for testing purposes A number of optional hardware erro
114. Address Value SSCTB FOBO E 58 SSC Transmit Buffer write only 0000 SSCTIC b FF72 B9 SSC Transmit Interrupt Control Register 00004 STKOV FE144 OAH CPU Stack Overflow Pointer Register FAOO STKUN FE16y OBy CPU Stack Underflow Pointer Register FCOO SYSCON b FF12 89 CPU System Configuration Register OXX0 SYSCON2 b F1D0 E E8 CPU System Configuration Register 2 0000 SYSCON3 b F1D4 E EA CPU System Configuration Register 3 0000 T121C b F190 E C8 CAPCOM 6 Timer 12 Interrupt Control Register 0000 T120F F034 E 1Ay CAPCOM 6 Timer 12 Offset Register 00004 T12P F030 E 18 CAPCOM 6 Timer 12 Period Register 00004 T13IC b F198 E CCy CAPCOM 6 Timer 13 Interrupt Control Register 00004 T13P FO324 E 19y CAPCOM 6 Timer 13 Period Register 0000 T14 FOD2 E69 RTC Timer 14 Register XXXXy T14REL FODO E 68 RTC Timer 14 Reload Register XXXXy T2 FE40 204 GPT1 Timer 2 Register 0000 T2CON b FF40 Ady GPT1 Timer 2 Control Register 0000 T2lC b FF60 Boy GPT1 Timer 2 Interrupt Control Register 00004 T3 FE42 214 GPT1 Timer 3 Register 0000 T3CON b FF42 Aly GPT1 Timer 3 Control Register 0000 T3IC b FF624 Bly GPT1 Timer 3 Interrupt Control Register 0000 T4 FE444 224 GPT1 Timer 4 Register 0000 T4CON b FF44 A2u GPT1 Timer 4 Control Register 0000 T4IC b FF64 B24 GPT1 Timer 4 Interrupt Control Register 00004 T7 F050 E 28g CAPCOM Timer 7 Register 00004 T78CON b FF20 90H CAPCOM Timer 7 and 8 Control Register 00004 T7IC b F17A4 E B
115. BUSACTO and ALECTLO are set 1 and bit field BTYP is loaded with the bus configuration selected via PORTO Semiconductor Group 9 15 Version 1 0 11 97 SIEMENS The External Bus Interface C164Cl Bit Function MCTC Memory Cycle Time Control Number of memory cycle time wait states 0000 15 waitstates Number 15 lt MCTC gt 1111 No waitstates RWDCx Read Write Delay Control for BUSCONx 0 With read write delay activate command 1 TCL after falling edge of ALE 1 No read write delay activate command with falling edge of ALE MTTCx Memory Tristate Time Control 0 1 waitstate 1 No waitstate BTYP External Bus Configuration 00 Reserved 01 8 bit Multiplexed Bus 10 Reserved 11 16 bit Multiplexed Bus Note For BUSCONO BTYP is defined via PORTO during reset ALECTLx ALE Lengthening Control 0 Normal ALE signal 1 Lengthened ALE signal BUSACTx Bus Active Control 0 External bus disabled 1 External bus enabled within the respective address window see ADDRSEL CSRENx Read Chip Select Enable 0 The CS signal is independent of the read command RD 1 The CS signal is generated for the duration of the read command CSWENx Write Chip Select Enable 0 The CS signal is independent of the write command WR WRL WRH 1 The CS signal is generated for the duration of the write command Semiconductor Group 9 16 Version 1 0 11 97 SIEMENS The External Bu
116. CPU Basic tasks of the CPU are to fetch and decode instructions to supply operands for the arithmetic and logic unit ALU to perform operations on these operands in the ALU and to store the previously calculated results As the CPU is the main engine of the C164Cl controller it is also affected by certain actions of the peripheral subsystem Since a four stage pipeline is implemented in the C164Cl up to four instructions can be processed in parallel Most instructions of the C164Cl are executed in one machine cycle 2 CPU clock periods due to this parallelism This chapter describes how the pipeline works for sequential and branch instructions in general and which hardware provisions have been made to speed the execution of jump instructions in particular The general instruction timing is described including standard and exceptional timing While internal memory accesses are normally performed by the CPU itself external peripheral or memory accesses are performed by a particular on chip External Bus Controller EBC which is automatically invoked by the CPU whenever a code or data address refers to the external address space If possible the CPU continues operating while an external memory access is in progress If external data are required but are not yet available or if a new external memory access is requested by the CPU before a previous access has been completed the CPU will be held by the EBC until the request can be satisfied Th
117. Direction f E MUX irection Latch YE Read DPOH y DPOL y I Alternate n Function Enable r n Write POH y POL y Alternate a Data 1 POHy Output MUX e Port Output slo Output POL y B Latch Buffer u Read POH y POL y Clock 1 0 Input Latch MCB02231 y 7 0 Figure 7 5 Block Diagram of a PORTO Pin Semiconductor Group 7 8 Version 1 0 11 97 SIEMENS Parallel Ports C164CI 7 2 PORTI The two 8 bit ports P1H and P1L represent the higher and lower part of PORT1 respectively Both halfs of PORT1 can be written eg via a PEC transfer without effecting the other half If this port is used for general purpose IO the direction of each line can be configured via the corresponding direction registers DP1H and DP1L P1L FF04 82 SFR Reset Value 00 15 14 13 12 11 10 9 8 bin aa 6 5 4 3 2 1 0 P1L 7 P1L 6 P1L 5 P1L A P1L 3 P1L 2 P1L 1 P1L 0 P1H FF06 834 SFR Reset Value 00 8 7 6 5 4 3 2 1 0 x x rw rw rw rw rw rw rw rw Bit Function P1X y Port data register P1H or P1L bit y DP1L F104 824 ESFR Reset Value 00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DP1L DP1L DP1L DP1L DP1L DP1L DP1L DP1L 7 6 5 4 3 2 1 0 EU m DP1H F106 834 ESFR Reset Value 00 cds He du de cdi 10 9 0 8 7 6 5 4 3 2 1 DP1H 7 rw rw rw rw rw rw rw rw Bit Function DP1X y Port direction reg
118. Dy CAPCOM Timer 7 Interrupt Control Register 00004 T7REL F0544 E 2Ay CAPCOM Timer 7 Reload Register 00004 T8 F052 E 294 CAPCOM Timer 8 Register 00004 T8IC b F17Cu4 E BEy CAPCOM Timer 8 Interrupt Control Register 00004 T8REL F056 E 2By CAPCOM Timer 8 Reload Register 00004 TFR b FFAC D6j Trap Flag Register 00004 TRCON b FF34 9A CAPCOM 6 Trap Enable Control Register 00XXy UAR EFn24 X CAN Upper Arbitration Register msg n UUUU Semiconductor Group 23 8 Version 1 0 11 97 SIEMENS The Register Set C164CI Name Physical 8 Bit Description Reset Address Address Value WDT FEAE 57H Watchdog Timer Register read only 0000 WDTCON b FFAE D7 Watchdog Timer Control Register 00XX XPOIC b F186 E C3 X Peripheral 0 Interrupt Control Register 00004 XP3IC b F19E E CFy X Peripheral 3 Interrupt Control Register 0000 ZEROS b FFiCy 8Ey Constant Value 0 s Register read only 0000 The system configuration is selected during reset 2 The reset value depends on the indicated reset source Semiconductor Group 23 9 Version 1 0 11 97 SIEMENS The Register Set C164CI 23 3 Registers ordered by Address The following table lists all SFRs which are implemented in the C164Cl ordered by their physical address Bit addressable SFRs are marked with the letter b in column Name SFRs within the Extended SFR Space ESFRs are marked with the letter E in column Physic
119. EMENS Interrupt and Trap Functions C164CI Source of Interrupt or PEC Request Enable Interrupt Vector Trap Service Request Flag Flag Vector Location Number Fast External Interrupt 0 CC8IR CC8IE CC8INT 00 0060 184 Fast External Interrupt 1 CC9IR CC9IE CC9INT 00 0064 194 Fast External Interrupt 2 CC10IR CC10IE CC10INT 00 00684 1Ay Fast External Interrupt 3 CC11IR CC11IE CC11INT 00 006C 1By CAPCOM Register 16 CC16IR CC16IE CC16INT 00 00C0 304 CAPCOM Register 17 CC17IR CC17IE CC17INT 00 00C4 314 CAPCOM Register 18 CC18IR CC18IE CC18INT 00 00C8j 324 CAPCOM Register 19 CC19IR CC19IE CC19INT 00 00CC 334 CAPCOM Register 24 CC24IR CC24IE CC24INT 00 00E0 384 CAPCOM Register 25 CC25IR CC25IE CC25INT 00 00E4 394 CAPCOM Register 26 CC26IR CC26lIE CC426NT 00 00E8y 3AH CAPCOM Register 27 CC27IR CC27IE CC27INT 00 00EC 3By CAPCOM Timer 7 T7IR T7IE T7INT 00 00F4 3Dy CAPCOM Timer 8 T8IR T8IE T8INT 00 00F8 3Ey GPT1 Timer 2 T2IR Tele T2INT 00 0088 224 GPT1 Timer 3 T3IR T3IE T3INT 00 008C 23H GPT1 Timer 4 T4IR TAIE T4INT 00 0090 244 A D Conversion Complete ADCIR ADCIE ADCINT 00 00A0 284 A D Overrun Error ADEIR ADEIE ADEINT 00 00A44 294 ASCO Transmit SOTIR SOTIE SOTINT 00 00A8 2AQ ASCO Transmit Buffer SOTBIR SOTBIE SOTBINT 00011C 474 ASCO Receive SORIR SORIE SORINT 00 00AC 2By ASCO Error SOEIR SOEIE
120. Edge Aligned Mode Branch 44 CAPCOM6 17 5 Pipeline 4 9 Emulation Mode 20 9 protected Pat Enable Timing 4 10 Interrupt 5 13 unseparable 22 12 Peripheral 21 11 menace Segmentation 4 13 CAN 2 11 19 1 Error Detection External Bus 9 1 serial async gt ASCO 11 1 Semiconductor Group 26 2 Version 1 0 11 97 SIEMENS no C164CI serial sync SSC 12 1 N Internal RAM 3 4 NMI 5 1 5 27 Interrupt CAPCOM 16 19 O Enable Disable 5 13 ODP3 7 12 external 5 21 ODP8 7 23 fast external 5 22 ONES 4 29 Handling CAN 19 8 Open Drain Mode 7 2 Node Sharing 5 20 Oscillator Priority 5 6 circuitry 6 2 Processing 5 1 5 5 Watchdog 6 8 Response Times 5 16 OTP RTC 14 3 Handling 22 14 source control 5 24 Programming 3 11 Sources 5 3 System 2 6 5 2 P Vectors 5 3 POL POH 7 6 IP 447 P1L P1H 7 9 IRAM 3 4 P3 7 12 ISNC 5 20 pa de P5 7 20 L P8 7 23 LAR 19 16 PEC 2 7 3 7 5 10 Latched chip select 9 7 Response Times 5 18 PECCx 5 10 M Peripheral 2 9 Management Enable Disable 21 11 Peripheral 21 10 Management 21 10 Power 21 1 Phase Locked Loop 6 1 MCFG 19 17 Phase Sequences 17 14 MCR 19 14 PICON 7 3 MDC 4 28 Pins 8 1 25 2 MDH 4 27 in Idle and Power Down mode 21 5 MDL 4 27 Pipeline 4 3 Memory 2 7 Effects 4 6 bit addressable 3 4 PLL 6 1 20 13 Code memory handling 22 14 Port 2 10 External 3 9 input threshold 7 2 OTP 3 11 Power Down Mode 21 4 RAM SFR 3 4 Power Management 2 15 21 1 ROM 3 3 Prescaler 6 4 Tri state time 9 11 Programming Memory Cycle Time 9
121. FCH CPU General Purpose Byte Register RL6 UUu RH6 CP 13 FDy CPU General Purpose Byte Register RH6 UUu RL7 CP 14 FEy CPU General Purpose Byte Register RL7 UU RH7 CP 14 FFy CPU General Purpose Byte Register RH7 UUu Semiconductor Group 23 3 Version 1 0 11 97 SIEMENS The Register Set C164Cl 23 2 Special Function Registers ordered by Name The following table lists all SFRs which are implemented in the C164Cl in alphabetical order Bit addressable SFRs are marked with the letter b in column Name SFRs within the Extended SFR Space ESFRs are marked with the letter E in column Physical Address Registers within on chip X Peripherals are marked with the letter X in column Physical Address Name Physical 8 Bit Description Reset Address Address Value ADCIC b FF98 CCy A D Converter End of Conversion Interrupt 0000 Control Register ADCON b FFAO DO A D Converter Control Register 0000 ADEIC b FF A CDy A D Converter Overrun Error Interrupt Control 0000 Register ADDAT FEAOH 50H A D Converter Result Register 0000 ADDAT2 FOAO E50 A D Converter 2 Result Register 00004 ADDRSEL1 FE18 0C Address Select Register 1 0000 ADDRSEL2 FE1A 0Dy Address Select Register 2 0000 ADDRSEL3 FE1Cy OEY Address Select Register 3 00004 ADDRSEL4 FE E OFy Address Select Register 4 0000 BUSCONO b
122. FECE 67y PEC Channel 7 Control Register 00004 PICON FiC4 E E2 Port Input Threshold Control Register 00004 PSW FF10u 884 CPU Program Status Word 00004 RPOH F108 E 84 System Startup Configuration Register Rd only XXy RTCH FOD6 E 6B RTC High Register XXXXy RTCL FOD4 E 6A RTC Low Register XXXXy SOBG FEB4y SAY Serial Channel 0 Baud Rate Generator Reload 00004 Register SOCON FFBOW D84 Serial Channel 0 Control Register 00004 SOEIC FF70y B8y Serial Channel 0 Error Interrupt Control Register 00004 SORBUF FEB2y 594 Serial Channel 0 Receive Buffer Register XXXXy read only SORIC FF6EY B74 Serial Channel 0 Receive Interrupt Control 00004 Register SOTBIC F19C E CE Serial Channel 0 Transmit Buffer Interrupt Control 00004 Register SOTBUF FEBOy 584 Serial Channel 0 Transmit Buffer Register 0000 SOTIC FF6Cy B6y Serial Channel 0 Transmit Interrupt Control 0000 Register SP FE124 09 CPU System Stack Pointer Register FC00 SSCBR FOB4 E 5A SSC Baudrate Register 0000 SSCCON FFB2y D94 SSC Control Register 0000 SSCEIC FF76u BBy SSC Error Interrupt Control Register 0000 SSCRB FOB2 E 59 SSC Receive Buffer read only XXXXy SSCRIC FF7444 BAH SSC Receive Interrupt Control Register 0000 Semiconductor Group 23 7 Version 1 0 11 97 SIEMENS The Register Set C164Cl Name Physical 8 Bit Description Reset Address
123. Global Mask Message Object 10 Long Message Object 11 Message Object 12 EFOCy Message Object 13 Mask of Message Object 14 Last Message Message Object 15 CAN Address Area General Registers Figure 19 2 CAN Module Address Map Semiconductor Group 19 5 Version 1 0 11 97 SIEMENS The On Chip CAN Interface C164CI Control Status Register EF00 XReg Reset Value XX01 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r r r rw rw rw rw rw r r rw rw rw rw Bit Function Control Bits INIT Initialization Starts the initialization of the CAN controller when set IE Interrupt Enable Enables or disables interrupt generation from the CAN Module via the signal XINTR Does not affect status updates SIE Status Change Interrupt Enable Enables or disables interrupt generation when a message transfer reception or transmission is successfully completed or a CAN bus error is detected and registered in the status partition EIE Error Interrupt Enable Enables or disables interrupt generation on a change of bit BOFF or EWARN in the status partition CCE Configuration Change Enable Allows or inhibits CPU access to the Bit Timing Register 1 Test Mode Bit 7 Make sure that bit 7 is cleared when writing to the Control Register as this bit controls a special test mode that is used for production testing During normal operation however this test mode may lead to undesired behaviour of the device Se
124. IEMENS Interrupt and Trap Functions C164CI The source and destination pointers specifiy the locations between which the data is to be moved A pair of pointers SRCPx and DSTPx is associated with each of the 8 PEC channels These pointers do not reside in specific SFRs but are mapped into the internal RAM of the C164CI just below the bit addressable area see figure below 00 FCFE 00 FCEE 00 FCFC 00 FCEC 00 FCFA 00 FCEA 00 FCF8 00 FCE8 00 FCF6 00 FCE6 00 FCFA 00 FCE4 00 FCF2 00 FCE2 00 FCFO 00 FCEO Figure 5 2 Mapping of PEC Pointers into the Internal RAM PEC data transfers do not use the data page pointers DPP3 DPPO The PEC source and destination pointers are used as 16 bit intra segment addresses within segment 0 so data can be transferred between any two locations within the first four data pages 3 0 The pointer locations for inactive PEC channels may be used for general data storage Only the required pointers occupy RAM locations Note If word data transfer is selected for a specific PEC channel ie BWT 0 the respective source and destination pointers must both contain a valid word address which points to an even byte boundary Otherwise the Illegal Word Access trap will be invoked when this channel is used Semiconductor Group 5 12 Version 1 0 11 97 SIEMENS Interrupt and Trap Functions C164CI 5 3 Prioritization of Interrupt and PEC Service Requests
125. IR in register TxIC will be set This will cause an interrupt to the respective timer interrupt vector T2INT T3INT or T4INT or trigger a PEC service if the respective interrupt enable bit T2IE T3IE or T4IE in register TxIC is set There is an interrupt control register for each of the three timers T2IC FF60 BOp SFR Reset Value 00 LONE LN NEC MERE E EN RUNI 6 T2IR T2IE ILVL GLVL nw rw rw T3IC FF62 B14 SFR Reset Value 00 MON M NE NEUE EN NER 6 TSIR TSIE ILVL GLVL rw rw rw TAIC FF64 B2y SFR Reset Value 00 6 prr prrsreeee 7 5 4 3 2 1 0 TAIR T41E ILVL GLVL rw rw rw rw Note Please refer to the general Interrupt Control Register description for an explanation of the control fields Semiconductor Group 10 18 Version 1 0 11 97 Sl EM ENS The Asynchronous Synchronous Serial Interface C164CI 11 The Asynchronous Synchronous Serial Interface The Asynchronous Synchronous Serial Interface ASCO provides serial communication between the C164Cl and other microcontrollers microprocessors or external peripherals The ASCO supports full duplex asynchronous communication up to 625 KBaud and half duplex synchronous communication up to 2 5 MBaud 20 MHz CPU clock In synchronous mode data are transmitted or received synchronous to a shift clock which is generated by the C164Cl In asynchronous mode 8 or 9 bit data transfer parity gene
126. Interrupt and PEC service requests from all sources can be enabled so they are arbitrated and serviced if they win or they may be disabled so their requests are disregarded and not serviced Enabling and disabling interrupt requests may be done via three mechanisms Control Bits allow to switch each individual source ON or OFF so it may generate a request or not The control bits xxIE are located in the respective interrupt control registers All interrupt requests may be enabled or disabled generally via bit IEN in register PSW This control bit is the main switch that selects if requests from any source are accepted or not For a specific request to be arbitrated the respective source s enable bit and the global enable bit must both be set The Priority Level automatically selects a certain group of interrupt requests that will be acknowledged disclosing all other requests The priority level of the source that won the arbitration is compared against the CPU s current level and the source is only serviced if its level is higher than the current CPU level Changing the CPU level to a specific value via software blocks all requests on the same or a lower level An interrupt source that is assigned to level 0 will be disabled and never be serviced The ATOMIC and EXTend instructions automatically disable all interrupt requests for the duration of the following 1 4 instructions This is useful eg for semaphore handling and does n
127. LE is not activated for internal accesses ie accesses to ROM OTP Flash if provided the internal RAM and the special function registers In single chip mode ie when no external bus is enabled no BUSACT bit set ALE will also remain inactive for X Peripheral accesses During reset internal pulldown ensures an inactive low level on the ALE output The External Read Strobe RD controls the output drivers of external memory or peripherals when the C164Cl reads data from these external devices During accesses to on chip X Peripherals RD remains inactive high During reset internal pullup ensures an inactive high level on the RD output At the end of the internal reset sequence the level on the RD pin is latched together with the PORTO configuration The latched RD level determines the reset value of bit OWDDIS in register SYSCON The default high level on pin RD leaves the oscillator watchdog active OWDDIS 0 while a low level disables the watchdog OWDDIS 1 The external circuitry connected to pin RD must be designed either to maintain the default high level or provide a proper low level if desired Semiconductor Group 8 1 Version 1 0 11 97 SIEMENS Dedicated Pins C164CI The External Write Strobe WR WRL controls the data transfer from the C164CI to an external memory or peripheral device This pin may either provide an general WR signal activated for both byte and word write accesses or specifically control the low by
128. MRST pin All the other slaves have to program there MRST pins to input So only one slave can put its data onto the master s receive line Only receiving of data from the master is possible The master selects the slave device from which it expects data either by separate select lines or by sending a special command to this slave The selected slave then switches its MRST line to output until it gets a deselection signal or command The slaves use open drain output on MRST This forms a Wired AND connection The receive line needs an external pullup in this case Corruption of the data on the receive line sent by the selected slave is avoided when all slaves which are not selected for transmission to the master only send ones 1 Since this high level is not actively driven onto the line but only held through the pullup device the selected slave can pull this line actively to a low level when transmitting a zero bit The master selects the slave device from which it expects data either by separate select lines or by sending a special command to this slave After performing all necessary initializations of the SSC the serial interfaces can be enabled For a master device the alternate clock line will now go to its programmed polarity The alternate data line will go to either 0 or 1 until the first transfer will start After a transfer the alternate data line will always remain at the logic level of the last transmitted data bit When
129. Modes The compare modes allow triggering of events interrupts and or output signal transitions with minimum software overhead In all compare modes the 16 bit value stored in compare register CCx in the following also referred to as compare value is continuously compared with the contents of the allocated timer T7 or T8 If the current timer contents match the compare value an appropriate output signal which is based on the selected compare mode can be generated at the corresponding output pin CCxlO except for CC241O CC271O and the associated interrupt request flag CCxIR is set which can generate an interrupt request if enabled As for capture mode the compare registers are also processed sequentially during compare mode When any two compare registers are programmed to the same compare value their corresponding interrupt request flags will be set to 1 and the selected output signals will be generated within 8 CPU clock cycles after the allocated timer is incremented to the compare value Further compare events on the same compare value are disabled until the timer is incremented again or written to by software After a reset compare events for register CCx will only become enabled if the allocated timer has been incremented or written to by software and one of the compare modes described in the following has been selected for this register The different compare modes which can be programmed for a given compare register CCx ar
130. Multiply Divide Control Register 00004 MDH FEOC 06 CPU Multiply Divide Register High Word 0000 MDL FEOE 074 CPU Multiply Divide Register Low Word 0000 ODP3 b F1C6 E E3y Port 3 Open Drain Control Register 0000 ODP8 b F1D6 E EBy Port 8 Open Drain Control Register 00H ONES b FF1E 8Fy Constant Value 1 s Register read only FFFFy POH b FF024 814 Port 0 High Register Upper half of PORTO 004 POL b FFOO 804 Port 0 Low Register Lower half of PORTO 004 P1H b FF06u 834 Port 1 High Register Upper half of PORT1 004 P1L b FF044 824 Port 1 Low Register Lower half of PORT1 004 P3 b FFC4 E24 Port 3 Register 00004 P4 b FFC84 E44 Port 4 Register 8 bits 004 P5 b FFA24 Dip Port 5 Register read only XXXXy Semiconductor Group 23 6 Version 1 0 11 97 SIEMENS The Register Set C164Cl Name Physical 8 Bit Description Reset Address Address Value P5DIDIS FFA4y D2y Port 5 Digital Input Disable Register 0000 P8 FFD44 EAH Port 8 Register 8 bits 004 PECCO FECO 60 PEC Channel 0 Control Register 0000 PECC1 FEC2 61g PEC Channel 1 Control Register 00004 PECC2 FEC4 624 PEC Channel 2 Control Register 00004 PECC3 FEC6y4 634 PEC Channel 3 Control Register 00004 PECCA FEC8 64 PEC Channel 4 Control Register 00004 PECC5 FECA 1654 PEC Channel 5 Control Register 0000 PECC6 FECC 66 PEC Channel 6 Control Register 00004 PECC7
131. O fe Register SOBG acc to 00 byte DP3 10 T Other than after a normal reset the watchdog timer is disabled so the bootstrap loading sequence is not time limited Pin TXDO is configured as output so the C164Cl can return the identification byte Note Even if the internal ROM OTP Flash is enabled no code can be executed out of it The hardware that activates the BSL during reset may be a simple pull down resistor on POL 4 for systems that use this feature upon every hardware reset You may wantto use a switchable solution via jumper or an external signal for systems that only temporarily use the bootstrap loader Semiconductor Group 15 2 Version 1 0 11 97 SIEMENS The Bootstrap Loader C164Cl External Signal pM Normal Boot A i PA 7 POL 4 POL 4 MCA02261 Figure 15 2 Hardware Provisions to Activate the BSL After sending the identification byte the ASCO receiver is enabled and is ready to receive the initial 32 bytes from the host A half duplex connection is therefore sufficient to feed the BSL Note In order to properly enter BSL mode it is not only required to pull POL 4 low but also pins POL 2 POL 3 POL 5 must receive defined levels This is described in chapter System Reset Semiconductor Group 15 3 Version 1 0 11 97 SIEMENS The Bootstrap Loader C164Cl Memory Configuration after Reset The configuration ie
132. ON2 0FH 09H Unlock sequence step 1 1001B MOV SYSCON2 0003H Unlock sequence step 2 0011B BSET SYSCON2 2 Unlock sequence step 3 0111B Single access to SYSCON2 SYSCON3 BFLDH SYSCON2 03H 00H CLKCON 00B basic frequency Examples where the PLL is disabled ENTER SLOWDOWN Currently running on basic clock frequ EXTR 1H Next access to ESFR space BCLR ISNC 2 PLLIE 0 ie PLL interrupt disabled EXTR 4H Switch to ESFR space and lock sequence BFLDL SYSCON2 0FH 09H Unlock sequence step 1 1001B MOV SYSCON2 0003H Unlock sequence step 2 0011B BSET SYSCON2 2 Unlock sequence step 3 0111B Single access to SYSCON2 SYSCON3 BFLDH SYSCON2 03H 02H CLKCON 10B SDD frequency PLL off Semiconductor Group 21 13 Version 1 0 11 97 SIEMENS Power Management C164CI SDD EXIT AUTO EXTR BFLDL MOV BSET BFLDH EXTR BSET 4H SYSCON2 0FH 09H SYSCON2 0003H SYSCON2 2 SYSCON2 03H 00H 1H ISNC 2 SDD EXIT MANUAL EXTR 4H BFLDL SYSCON2 0FH 09H MOV SYSCON2 0003H BSET SYSCON2 2 BFLDH SYSCON2 03H 01H USER CODE CLOCK OK EXTR 1H JNB SYSCON2 15 CLOCK OK EXTR 4H BFLDL SYSCON2 0FH 09H MOV SYSCON2 0003H BSET SYSCON2 2 BFLDH SYSCON2 03H 00H EXTR 1H BSET ISNC 2 Semiconductor Group Currently running on SDD frequency Switch Unlock Unlock Unlock Single to ESFR space and lock sequence sequence step 1 1001B
133. ONS Unlock Sequence Step SYSRLS Instruction Notes 0000 Status before release sequence 1001 BFLDL OR ORB XOR XORB Read Modify Write access 00113 MOV MOVB MOVBS MOVBZ Write access 01115 BSET BMOV BHOVNP Read Modify Write access BOR BXOR bit instruction 4 Single read modify write access to SYSCON or SYSCONS a 0000 ES Status after release sequence Note SYSRLS must be set to 0000g before the first step if any OR command is used Usually byte accesses should not be used for special function registers 3 SYSRLS is cleared by hardware if unlock sequence and write access were successful SYSRLS shows the last value written otherwise Semiconductor Group 21 12 Version 1 0 11 97 SIEMENS Power Management C164Cl The code examples below show how an access to SYSCON2 SYSCONS can be accomplished in an application Examples where the PLL keeps running ENTER SLOWDOWN Currently running on basic clock frequ EXTR 4H Switch to ESFR space and lock sequence BFLDL SYSCON2 0FH 09H Unlock sequence step 1 1001B MOV SYSCON2 0003H Unlock sequence step 2 0011B BSET SYSCON2 2 Unlock sequence step 3 0111B Single access to SYSCON2 SYSCON3 BFLDH SYSCON2 03H 01H CLKCON 01B gt SDD frequency PLL on EXIT SLOWDOWN Currently running on SDD frequency EXTR 4H Switch to ESFR space and lock sequence BFLDL SYSC
134. PEC response time is the time to perform 7 word bus accesses When instructions N and N 1 are executed out of external memory but all operands for instructions N 3 through N 1 are in internal memory then the PEC response time is the time to perform 1 word bus access plus 2 state times Once a request for PEC service has been acknowledged by the CPU the execution of the next instruction is delayed by 2 state times plus the additional time it might take to fetch the source operand from internal code memory or external memory and to write the destination operand over the external bus in an external program environment Note A bus access in this context includes all delays which can occur during an external bus cycle Semiconductor Group 5 19 Version 1 0 11 97 SIEMENS Interrupt and Trap Functions C164CI Interrupt Node Sharing Interrupt nodes may be shared between several module requests either if the requests are generated mutually exclusive or if the requests are generated at a low rate If more than one source is enabled in this case the interrupt handler will first have to determine the requesting source However this overhead is not critical for low rate requests This node sharing is controlled via the sub node interrupt control register ISNC which provides a separate request flag and enable bit for each supported request source The interrupt level used for arbitration is determined by the node control register IC ISNC
135. PEC channels Otherwise an incorrect PEC channel may be activated Semiconductor Group 5 7 Version 1 0 11 97 Interrupt and Trap Functions C164Cl SIEMENS The table below shows in a few examples which action is executed with a given programming of an interrupt control register Priority Level Type of Service ILVL GLVL COUNT 00H COUNT 004 1111 11 CPU interrupt PEC service level 15 group priority 3 channel 7 1111 10 CPU interrupt PEC service level 15 group priority 2 channel 6 1110 10 CPU interrupt PEC service level 14 group priority 2 channel 2 1101 10 CPU interrupt CPU interrupt level 13 group priority 2 level 13 group priority 2 0001 11 CPU interrupt CPU interrupt level 1 group priority 3 level 1 group priority 3 0001 00 CPU interrupt CPU interrupt level 1 group priority 0 level 1 group priority 0 0000 XX No service No service Note All requests on levels 13 1 cannot initiate PEC transfers They are always serviced by an interrupt service routine No PECC register is associated and no COUNT field is checked Interrupt Control Functions in the PSW The Processor Status Word PSW is functionally divided into 2 parts the lower byte of the PSW basically represents the arithmetic status of the CPU the upper byte of the PSW controls the interrupt system of the C164Cl and the arbitration mechanism for the external bus interface Note Pipeline effects
136. PU activity If several hardware trap conditions are detected within the same instruction cycle the highest priority trap is serviced see table in section Interrupt System Structure PSW CSP in segmentation mode and IP are pushed on the internal system stack and the CPU level in register PSW is set to the highest possible priority level ie level 15 disabling all interrupts The CSP is set to code segment zero if segmentation is enabled A trap service routine must be terminated with the RETI instruction Semiconductor Group 5 25 Version 1 0 11 97 SIEMENS Interrupt and Trap Functions C164CI The eight hardware trap functions of the C164Cl are divided into two classes Class A traps are external Non Maskable Interrupt NMT Stack Overflow Stack Underflow trap These traps share the same trap priority but have an individual vector address Class B traps are Undefined Opcode Protection Fault e Illegal Word Operand Access Illegal Instruction Access Illegal External Bus Access Trap These traps share the same trap priority and the same vector address The bit addressable Trap Flag Register TFR allows a trap service routine to identify the kind of trap which caused the exception Each trap function is indicated by a separate request flag When a hardware trap occurs the corresponding request flag in register TFR is set to 1 TFR FFAC D64 SFR Reset Value 00004 15 14 13 12 1 10 9 8 7 6 5 4
137. Port 4 pin the segment address always takes preference The chip select lines of Port 4 additionally have an internal weak pullup device which is switched on during reset in order to provide an inactive level on the optional chip select lines until the controller begins operation Semiconductor Group Version 1 0 11 97 SIEMENS Parallel Ports C164CI 1 1 Directi MUX irection Latch gt 10 Read DP4 y I Alternate d Function t Enable e r n Alternate Data 1 a Output MUX gt e pay Port Output gt lo Output Latch Buffer Clock Input Latch MCB02075 Figure 7 12 Block Diagram of a Port 4 Pin Semiconductor Group 7 19 Version 1 0 11 97 SIEMENS Parallel Ports C164CI 7 5 Port5 This 8 bit input port can only read data There is no output latch and no direction register Data written to P5 will be lost P5 FFA2 Dip SFR Reset Value XXXXy 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 i x E r r r r r r r r Bit Function P5 y Port data register P5 bit y Read only Alternate Functions of Port 5 Each line of Port 5 is also connected to the input multiplexer of the Analog Digital Converter All port lines can accept analog signals ANx that can be converted by the ADC For pins that shall be used as analog inputs it is recommended to disable the digital input stage via register PSDIDIS see description below This avoids undesi
138. R So incoming frames can only match with corresponding message objects either standard XTD 0 or extended XTD 1 Data frames only match with receive objects remote frames only match with transmit objects When the CAN controller stores a data frame it will write all the eight data bytes into a message object If the data length code was less than 8 the remaining bytes of the message object will be overwritten by non specified values Message Configuration Register EFn6 XReg Reset Value UU 5 4 3 2 1 rw rw r rw rw r Bit Function XTD Extended Identifier Indicates if this message object will use an extended 29 bit identifier or a standard 1 1 bit identifier DIR Message Direction DIR 1 transmit On TXRQ the respective message object is transmitted On reception of a remote frame with matching identifier the TXRQ and RMTPND bits of this message object are set DIR 0 receive On TXRQ a remote frame with the identifier of this message object is transmitted On reception of a data frame with matching identifier that message is stored in this message object DLC Data Length Code Valid values for the data length are O 8 Note The first data byte occupies the upper half of the message configuration register Data Area The data area of message object n covers locations 00 EFn7 through 00 EFnE Location 00 EFnFy is reserved Message data for message object 15 last message will be
139. SCONO is set to 1 bit ALECTLO in register BUSCONO is set to 1 bit ROMEN in register SYSCON will be cleared to 0 bit BYTDIS in register SYSCON is set according to the data bus width bit WRCFG in register SYSCON is set according to pin POH 0 WRC When an internal start is selected pin EA 1 register BUSCONO is cleared to 0000 bit ROMEN in register SYSCON will be set to 1 bit BYTDIS in register SYSCON is cleared ie BHE is disabled bit WRCFG in register SYSCON is set according to pin POH O WRC The other bits of register BUSCONO and the other BUSCON registers are cleared This default initialization selects the slowest possible external accesses using the configured bus type When the internal reset has completed the configuration of PORTO Port 4 and of the BHE signal High Byte Enable alternate function of P3 12 depends on the bus type which was selected during reset When any of the external bus modes was selected during reset PORTO will operate in the selected bus mode Port 4 will output the selected number of segment address lines all zero after reset and will drive the selected number of CS lines CSO will be 0 while the other active CS lines will be 1 When no memory accesses above 64 K are to be performed segmentation may be disabled When the on chip bootstrap loader was activated during reset pin TxDO alternate function of P3 10 will be switched to output mode af
140. SIEMENS CloAC 16 Bit CM OS Single Chip M icrocontrollers User s M anual 11 97 Version 1 0 Version 1 0 11 97 Published by Siemens AG Bereich Halbleiter Marketing Kommunikation BalanstraBe 73 81541 Munchen Siemens AG 1997 All Rights Reserved Attention please As far as patents or other rights of third par ties are concerned liability is only assumed for components not for applications pro cesses and circuits implemented within com ponents or assemblies The information describes the type of compo nent and shall not be considered as assured characteristics Terms of delivery and rights to change design reserved For questions on technology delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies and Representatives worldwide see address list Due to technical requirements components may contain dangerous substances For in formation on the types in question please contact your nearest Siemens Office Semi conductor Group Siemens AG is an approved CECC manufac turer Packing Please use the recycling operators known to you We can also help you get in touch with your nearest sales office By agreement we will take packing material back if it is sorted You must bear the costs of transport For packing material that is returned to us un sorted or which we are not obliged to accept we shall have to invoice you for any costs in
141. SOEINT 00 00B0 2Cy SSC Transmit SCTIR SCTIE SCTINT 00 00B4 2Dy SSC Receive SCRIR SCRIE SCRINT 00 00B8 2Ey SSC Error SCEIR SCEIE SCEINT 00 00BC 2Fy XPER Node 0 Int CAN XPOIR XPOIE XPOINT 00 0100 40u XPER Node 3 Int PLL T14 XP3IR XP3IE XP3INT 00 010C 43y CAPCOM 6 Interrupt CC6IR CC6IE CC6INT 00 00FC SFy CAPCOM 6 Timer 12 T121R T12lE T121NT 00 01344 4D CAPCOM 6 Timer 13 T1S3IR TISIE T13INT 00 01384 4Ey CAPCOM 6 Emergency CC6EIR CC6EIE CC6EINT 00 013C 4Fy Semiconductor Group 5 3 Version 1 0 11 97 Interrupt and Trap Functions C164Cl SIEMENS The table below lists the vector locations for hardware traps and the corresponding status flags in register TFR It also lists the priorities of trap service for cases where more than one trap condition might be detected within the same instruction After any reset hardware reset software reset instruction SRST or reset by watchdog timer overflow program execution starts at the reset vector at location 00 0000 Reset conditions have priority over every other system activity and therefore have the highest priority trap priority Ill Software traps may be initiated to any vector location between 00 0000 and 00 01FC A service routine entered via a software TRAP instruction is always executed on the current CPU priority level which is indicated in bit field ILVL in register PSW This means that routines entered via the software TRAP instruction can be interru
142. STKUN M Exec Unit Mul Div HW Instr Ptr Bit Mask Gen General Instr Reg Purpose 4 Stage 16 bit ROM lt 7 Pipeline Registers Barrel Shifter PSW SYSCON l l l l l l l l l BUSCON 2 ADDRSEL 2 BUSCON 3 ADDRSEL 3 BUSCON 4 ADDRSEL 4 Data Page Ptr Code Seg Ptr MCB02147 Figure 2 2 CPU Block Diagram To meet the demand for greater performance and flexibility a number of areas has been optimized in the processor core Functional blocks in the CPU core are controlled by signals from the instruction decode logic These are summarized below and described in detail in the following sections 1 High Instruction Bandwidth Fast Execution 2 High Function 8 bit and 16 bit Arithmetic and Logic Unit 3 Extended Bit Processing and Peripheral Control 4 High Performance Branch Call and Loop Processing 5 Consistent and Optimized Instruction Formats 6 Programmable Multiple Priority Interrupt Structure Semiconductor Group 2 2 Version 1 0 11 97 SIEMENS Architectural Overview C164Cl High Instruction Bandwidth Fast Execution Based on the hardware provisions most of the C164Cl s instructions can be executed in just one machine cycle which requires 2 CPU clock cycles 2 1 fcpy 4 TCL For example shift and rotate instructions are always processed within one machine cycle independent of the number of bits to be shifted Branch multiply
143. SUBB Subtraction with Carry of two words or bytes SUBC SUBCB 16 16 bit signed or unsigned multiplication MUL MULU 16 16 bit signed or unsigned division DIV DIVU 32 16 bit signed or unsigned division DIVL DIVLU 1 s complement of a word or byte CPL CPLB 2 s complement negation of a word or byte NEG NEGB Logical Instructions Bitwise ANDing of two words or bytes AND ANDB Bitwise ORing of two words or bytes OR ORB Bitwise XORing of two words or bytes XOR XORB Compare and Loop Control Instructions Comparison of two words or bytes CMP CMPB Comparison of two words with post increment by either 1 or 2 CMPI1 CMPI2 Comparison of two words with post decrement by either 1 or 2 CMPD1 CMPD2 Semiconductor Group 24 1 Version 1 0 11 97 SIEMENS Instruction Set Summary C164CI Boolean Bit Manipulation Instructions Manipulation of a maskable bit field in either the high or the low byte of a word BFLDH BFLDL Setting a single bit to 1 BSET Clearing a single bit to 0 BCLR Movement of a single bit BMOV Movement of a negated bit BMOVN ANDing of two bits BAND ORing of two bits BOR XORing of two bits BXOR Comparison of two bits BCMP Shift and Rotate Instructions Shifting right of a word SHR Shifting left of a word SHL Rotating right of a word ROR Rotating left of a word ROL Arithmetic shifting right of a word sign bit
144. The system stack may be defined within the internal RAM The size of the system stack is controlled by bitfield STKSZ in register SYSCON see table below lt STKSZ gt Stack Size Words Internal RAM Addresses Words 000p 256 00 FBFE 00 FA00 Default after Reset 001 128 00 FBFE 00 FB00 010g 64 00 FBFEw 00 FB80 O11 32 O0 FBFE 00 FBCO 100p 512 00 FBFE 00 F800 101 ss Reserved Do not use this combination 110 Reserved Do not use this combination 1115g 1024 00 FDFE 00 F600 Note No circular stack For all system stack operations the on chip RAM is accessed via the Stack Pointer SP register The stack grows downward from higher towards lower RAM address locations Only word accesses are supported to the system stack A stack overflow STKOV and a stack underflow STKUN register are provided to control the lower and upper limits of the selected stack area These two stack boundary registers can be used not only for protection against data destruction but also allow to implement a circular stack with hardware supported system stack flushing and filling except for option 111 The technique of implementing this circular stack is described in chapter System Programming Semiconductor Group 3 5 Version 1 0 11 97 Memory Organization C164Cl SIEMENS General Purpose Registers The General Purpose Registers GPRs use a block of 16
145. U R12 CP 24 FC CPU General Purpose Word Register R12 UUUU R13 CP 26 FDy CPU General Purpose Word Register R13 UUUU R14 CP 28 FE CPU General Purpose Word Register R14 UUUU R15 CP 30 FFy CPU General Purpose Word Register R15 UUUU Semiconductor Group 23 2 Version 1 0 11 97 SIEMENS The Register Set C164CI The first 8 GPRs R7 RO may also be accessed bytewise Other than with SFRs writing to a GPR byte does not affect the other byte of the respective GPR The respective halves of the byte accessible registers receive special names Name Physical 8 Bit Description Reset Address Address Value RLO CP 0 FOy CPU General Purpose Byte Register RLO UUu RHO CP 1 Ftg CPU General Purpose Byte Register RHO UU RL1 CP 2 F2y CPU General Purpose Byte Register RL1 UU RH1 CP 3 F3y CPU General Purpose Byte Register RH1 UUu RL2 CP 4 F4y CPU General Purpose Byte Register RL2 UUu RH2 CP 5 F5y CPU General Purpose Byte Register RH2 UUu RL3 CP 4 6 F6y CPU General Purpose Byte Register RL3 UU RH3 CP 7 F7y CPU General Purpose Byte Register RH3 UUu RL4 CP 8 F8y CPU General Purpose Byte Register RL4 UUu RH4 CP 9 F94 CPU General Purpose Byte Register RH4 UUu RL5 CP 10 FAH CPU General Purpose Byte Register RL5 UU RH5 CP 11 FB4 CPU General Purpose Byte Register RH5 UUu RL6 CP 12
146. When the first instructions are to be fetched from internal memory EA 1 the device must contain code memory and this must contain a valid reset vector and valid code at its destination Mapping the internal ROM area to segment 1 Due to instruction pipelining any new ROM mapping will at the earliest become valid for the second instruction after the instruction which has changed the ROM mapping To enable accesses to the ROM area after mapping a branch to the newly selected ROM area JMPS and reloading of all data page pointers is required This also applies to re mapping the internal ROM area to segment 0 Enabling the internal code memory after reset When enabling the internal code memory after having booted the system from external memory note that the C164CI will then access the internal memory using the current segment offset rather than accessing external memory Disabling the internal code memory after reset When disabling the internal code memory after having booted the system from there note that the C164Cl will not access external memory before a jump to segment 0 in this case is executed General Rules When mapping the code memory no instruction or data accesses should be made to the internal memory otherwise unpredictable results may occur To avoid these problems the instructions that configure the internal code memory should be executed from external memory or from the on chip RAM Whenever the internal code me
147. XOK Transmitted Message Successfully Indicates that a message has been transmitted successfully error free and acknowledged by at least one other node since this bit was last reset by the CPU the CAN controller does not reset this bit RXOK Received Message Successfully Indicates that a message has been received successfully since this bit was last reset by the CPU the CAN controller does not reset this bit EWRN Error Warning Status Indicates that at least one of the error counters in the EML has reached the error warning limit of 96 BOFF Busoff Status Indicates when the CAN controller is in busoff state see EML Note Reading the upper half of the Control Register status partition will clear the Status Change Interrupt value in the Interrupt Register if it is pending Use byte accesses to the lower half to avoid this Semiconductor Group 19 7 Version 1 0 11 97 SIEMENS The On Chip CAN Interface C164CI CAN Interrupt Handling The on chip CAN Module has one interrupt output which is connected through a synchronization stage to a standard interrupt node in the C164Cl in the same manner as all other interrupts of the standard on chip peripherals The control register for this interrupt is XPOIC located at address F186 C3 in the ESFR range The associated interrupt vector is called XPOINT at location 100 trap number 40 With this configuration the user has all control options available for this int
148. a timer overflow the corresponding timer interrupt request flag TxIR for the respective timer will be set This flag can be used to generate an interrupt or trigger a PEC service request when enabled by the respective interrupt enable bit TxIE Each timer has its own bitaddressable interrupt control register TxIC and its own interrupt vector TXINT The organization of the interrupt control registers TxIC is identical with the other interrupt control registers T7IC F17A4 BEy ESFR Reset Value 004 ESOENLEE NS ONSE SS BECOMES NUS X HN NE NEUES T7IR T7IE ILVL GLVL wo IW rw rw T8IC F17C BFp ESFR Reset Value 00j Ub 14 AG 2 11 10 9 8 7 6 5 4 3 2 1 0 T8IR T8IE ILVL GLVL wo rw rw rw Note Please refer to the general Interrupt Control Register description for an explanation of the control fields Semiconductor Group 16 8 Version 1 0 11 97 SIEMENS The Capture Compare Unit CAPCOM2 C164Cl 16 3 Capture Compare Registers The 16 bit capture compare registers CC16 CC19 and CC24 CC27 are used as data registers for capture or compare operations with respect to timers T7 and T8 The capture compare registers are not bitaddressable Each of the registers CCx may be individually programmed for capture mode or one of 4 different compare modes no output signal for CC24 CC27 and may be allocated individually to one of the two timers T7 or T8 respectively A special combi
149. ables the effect of any later execution of a DISWDT instruction EINIT Miscellaneous Null operation which requires 2 bytes of storage and the minimum time for execution NOP Definition of an unseparable instruction sequence ATOMIC Switch reg bitoff and bitaddr addressing modes to the Extended SFR space EXTR Override the DPP addressing scheme using a specific data page instead of the DPPs and optionally switch to ESFR space EXTP EXTPR Override the DPP addressing scheme using a specific segment instead of the DPPs and optionally switch to ESFR space EXTS EXTSR Note The ATOMIC and EXT instructions provide support for uninterruptable code sequences eg for semaphore operations They also support data addressing beyond the limits of the current DPPs except ATOMIC which is advantageous for bigger memory models in high level languages Refer to chapter System Programming for examples Protected Instructions Some instructions of the C164Cl which are critical for the functionality of the controller are implemented as so called Protected Instructions These protected instructions use the maximum instruction format of 32 bits for decoding while the regular instructions only use a part of it eg the lower 8 bits with the other bits providing additional information like involved registers Decoding all 32 bits of a protected doubleword instruction increases the security in cases of data distortion during ins
150. ache jump instruction Injection of cached Target Instruction ItaRGeT 1 TaRGET 2 Cache Jmp Irarcet tarGet 41 Injection 1st loop iteration gt Repeated loop iteration J9 9 Figure 4 4 Cache Jump Instruction Pipelining Semiconductor Group 4 5 Version 1 0 11 97 SIEMENS The Central Processing Unit CPU C164Cl Particular Pipeline Effects Since up to four different instructions are processed simultaneously additional hardware has been spent in the C164Cl to consider all causal dependencies which may exist on instructions in different pipeline stages without a loss of performance This extra hardware ie for forwarding operand read and write values resolves most of the possible conflicts eg multiple usage of buses in a time optimized way and thus avoids that the pipeline becomes noticeable for the user in most cases However there are some very rare cases where the circumstance that the C164CIl is a pipelined machine requires attention by the programmer In these cases the delays caused by pipeline conflicts can be used for other instructions in order to optimize performance Context Pointer Updating An instruction which calculates a physical GPR operand address via the CP register is mostly not capable of using a new CP value which is to be updated by an immediately preceding instruction Thus to make sure that the new CP value is used atleast one in
151. active state Upon reaching the period value stored in register TxP the timer is cleared and repeats counting up At this time also the output signals are switched to their passive state In the figure below the selected edge offset is zero therefore the output signal refers to CC6x and or COUT6x CT1 Value CCP 7 Period Reg Offset Reg CTIOF 0 Start of CTI gt Time Duty Cycles CC 0 100 87 5 CC 4 50 CCx or COUTx COINI Bit is 0 active high signals CC 7 12 5 CC gt 7 CC 0 100 CC 1 87 5 CC 4 50 CCx or COUTx active low signals COINI Bit is 1 CC 7 12 5 CC gt 7 CC content of the CCxH CCxL compare registers CCP content of the CCPH CCPL period register CTIOF content of the CT1OFH CT1OFL offset registers MCT02601 Figure 17 5 Operation in Edge Aligned Mode The example above shows how to generate PWM output signals with duty cycles between 0 and 100 including the corner values The duty cycle directly corresponds to the programmed compare value The indicated output signals can be output on the respective pin CC6x or COUT6x or both of them The pin allocation is controlled via bitfields CMSELx in register CCeMSEL Register CC6MCON selects the passive level for enabled outputs The example above uses active high signals ie the passive level is low associated select bit is 0 Semiconductor Gr
152. age location in the internal ROM is xx xxFEy For PEC data transfers the internal ROM can be accessed independent of the contents of the DPP registers via the PEC source and destination pointers The internal ROM is not provided for single bit storage and therefore it is not bit addressable Note The x in the locations above depend on the available ROM Flash memory and on the mapping The internal ROM may be enabled disabled or mapped into segment O or segment 1 under software control Chapter System Programming shows how to do this and reminds of the precautions that must be taken in order to prevent the system from crashing Semiconductor Group 3 3 Version 1 0 11 97 SIEMENS Memory Organization C164Cl 3 2 Internal RAM and SFR Area The RAM SFR area is located within data page 3 and provides access to the internal RAM IRAM organized as X 16 and to two 512 Byte blocks of Special Function Registers SFRs The C167 provides 2 KByte of IRAM The internal RAM serves for several purposes System Stack programmable size General Purpose Register Banks GPRs Source and destination pointers for the Peripheral Event Controller PEC Variable and other data storage or Code storage PERE O o TASTE 00 FFFF RAMISFR Area UFFTTH 7 00 F000 yy SFR Area XRAMCAN Data Page 3 00 FEO0 4 00 E000 H External 00 C000 H Memory Internal Ed Page 2 RAM 00 8000 X Data Page 1 p
153. age object has been successfully transmitted Semiconductor Group 19 14 Version 1 0 11 97 SIEMENS The On Chip CAN Interface C164CI 1 n message object 15 last message these bits are hardwired to 0 inactive in order to prevent transmission of message 15 2 When the CAN controller writes new data into the message object unused message bytes will be overwritten by non specified values Usually the CPU will clear this bit before working on the data and verify that the bit is still cleared once it has finished working to ensure that it has worked on a consistent set of data and not part of an old message and part of the new message For transmit objects the CPU will set this bit along with clearing bit CPUUPD This will ensure that if the message is actually being transmitted during the time the message was being updated by the CPU the CAN controller will not reset bit TXRQ In this way bit TXRQ is only reset once the actual data has been transferred 3 When the CPU requests the transmission of a receive object a remote frame will be sent instead of a data frame to request a remote node to send the corresponding data frame This bit will be cleared by the CAN controller along with bit RMTPND when the message has been successfully transmitted if bit NEWDAT has not been set If there are several valid message objects with pending transmission request the message with the lowest message number is transmitted first
154. al Address Registers within on chip X Peripherals are marked with the letter X in column Physical Address Name Physical 8 Bit Description Reset Address Address Value C1CSR EFOO X CAN Control Status Register XX014 C1IR EFO2 X CAN Interrupt Register XXy C1BTR EFO4 X CAN Bit Timing Register UUUU C1GMS EF06 X CAN Global Mask Short UFUU C1UGML EFO8 X CAN Upper Global Mask Long UUUU C1LGML EFOA X CAN Lower Global Mask Long UUUUH C1UMLM EFOC X CAN Upper Mask of Last Message UUUU C1LMLM EFOE X CAN Lower Mask of Last Message UUUU MCR EFnO X CAN Message Control Register msg n UUUU UAR EFn2 X CAN Upper Arbitration Register msg n UUUU LAR EFn44 X CAN Lower Arbitration Register msg n UUUU MCFG EFn6 X CAN Message Configuration Register msg n UUu T12P F030 E 18 CAPCOM 6 Timer 12 Period Register 00004 T13P F032 E 194 CAPCOM 6 Timer 13 Period Register 0000 T120F F034 E 1Ay CAPCOM 6 Timer 12 Offset Register 00004 CCeMSEL F036 E 1By CAPCOM 6 Mode Select Register 0000 T7 F050 E 28 CAPCOM Timer 7 Register 00004 T8 F052 E 29 CAPCOM Timer 8 Register 0000 T7REL F0544 E 2Ay CAPCOM Timer 7 Reload Register 00004 T8REL F056 E 2By CAPCOM Timer 8 Reload Register 0000 IDPROG F078 E 3Cy Identifier XXXX IDMEM F07A 4 E 3Dy Identifier X010 IDCHIP F07C E S3E Identifier OAO IDMANUF FO
155. al programming However this approach assumes that the defined internal stack is sufficient for the current software and that exceeding its upper or lower boundary represents a fatal error It is also possible to use the stack underflow and stack overflow traps to cache portions of a larger external stack Only the portion of the system stack currently being used is placed into the internal memory thus allowing a greater portion of the internal RAM to be used for program data or register banking This approach assumes no error but requires a set of control routines see below Semiconductor Group 22 4 Version 1 0 11 97 System Programming C164CI SIEMENS Circular virtual Stack This basic technique allows pushing until the overflow boundary of the internal stack is reached At this point a portion of the stacked data must be saved into external memory to create space for further stack pushes This is called stack flushing When executing a number of return or pop instructions the upper boundary since the stack empties upward to higher memory locations is reached The entries that have been previously saved in external memory must now be restored This is called stack filling Because procedure call instructions do not continue to nest infinitely and call and return instructions alternate flushing and filling normally occurs very infrequently If this is not true for a given program environment this technique should not be used be
156. al Interface C164CI Master Device 1 Device 2 Slave Shift Register Shift Register gt Common Transmit Receive Device 3 Slave MCS01965 Figure 12 5 SSC Half Duplex Configuration Continuous Transfers When the transmit interrupt request flag is set it indicates that the transmit buffer SSCTB is empty and ready to be loaded with the next transmit data If SSCTB has been reloaded by the time the current transmission is finished the data is immediately transferred to the shift register and the next transmission will start without any additional delay On the data line there is no gap between the two successive frames Eg two byte transfers would look the same as one word transfer This feature can be used to interface with devices which can operate with or require more than 16 data bits per transfer It is just a matter of software how long a total data frame length can be This option can also be used eg to interface to byte wide and word wide devices on the same serial bus Note Of course this can only happen in multiples of the selected basic data width since it would require disabling enabling of the SSC to reprogram the basic data width on the fly Semiconductor Group 12 9 Version 1 0 11 97 SIEM ENS The High Speed Synchronous Serial Interface C164CI Port Control The SSC uses three pins of Port 3 to communicate with the external world Pin P3 13 SCLK serves
157. al ROM area mapped to segment 1 01 0000 01 7FFFj STKSZ System Stack Size Selects the size of the system stack in the internal RAM from 32 to 1024 words Note Register SYSCON cannot be changed after execution of the EINIT instruction Bit SGTDIS controls the correct stack operation push pop of CSP or not during traps and interrupts Semiconductor Group 9 14 Version 1 0 11 97 SIEMENS The External Bus Interface C164CI The layout of the five BUSCON registers is identical Registers BUSCON4 BUSCON1 which control the selected address windows are completely under software control while register BUSCONO which eg is also used for the very first code access after reset is partly controlled by hardware ie it is initialized via PORTO during the reset sequence This hardware control allows to define an appropriate external bus for systems where no internal program memory is provided BUSCONO gin b SFR Reset Value 0XX0j 14 11 1 0 CSW CSR BUS ALE MTT RWD BUSCON1 oe in SFR Reset Value 0000 14 11 1 0 CSW CSR eae ALE MTT RWD BUSCON2 gd ML SFR Reset Value 0000 14 11 1 0 CSW CSR BUS ALE MTT RWD BUSCON3 gis uw SFR Reset Value 0000 14 11 1 0 CSW CSR BUS ALE MTT RWD BUSCON4 i Ay on SFR Reset Value 00004 1 0 14 11 CSW CSR BUS ALE MTT RWD Note BUSCONDO is initialized with 0000y if pin EA is high during reset If pin EA is low during reset bits
158. al Time Clock regn ehe REID RII TUE a ae A Re HOES SE 14 1 The Bootstrap Loader 0 0 15 1 The Capture Compare Unit CAPCOM2 0 200000 16 1 THO CAPCOM THMGIS 472 sige nth ooo sole Sheen Tbeb S debui unt oe dans 16 4 CAPCOM Unit Timer Interrupts llle 16 8 Capture Compare Registers 5 i c oa bee bo ERE eee ees 16 9 Capture Mode cibuste ot ee t rarae niece efe G Se ai ne Q3 POE Pte 16 11 Compare Modas ases ae EARERG Xa eC Rb NAE CR xem dd bad 16 12 Capture Compare Interrupts 0 0000 ees 16 19 The Capture Compare Unit CAPCOM6 0055 17 1 Clocking Celle eat crea dst dite ead eode Res et eee Eu Gon GR oe eee Be 17 4 Output Signal Level Gotitlol ice whew Py Le eee Ree ee eee 17 4 Edge Aligned Mode 3t er hob de pi besar Read bandh eee 17 5 Center Aligned Mode rese ze Rep ECCE EC OF RECO eee dE 17 7 B rst Mode mrasa vo eoe ecl sciant PORE S olin areis EpL re RE S ees 17 10 Capture Mode xx 250408 pe mAu LA TESA EENE DEAE RENDER EE RA E 17 11 Combined Multi Channel Modes llslsessseleessllees 17 12 Trap FONGHON ala os Ee quote et tice ce wt OE OE ANE 17 17 Register Description 3d fades deep Rodez edit anle iictedtubste Sede eese der itu eg 17 18 Semiconductor Group Version 1 0 11 97 SIEMENS General Information C164CI Table of Contents 18 18 1 18 2 18 3 19 20 21 21 1 21 2 21 3 21 4 22 22 1 22 2 22 3 22 4 2
159. alid in the selected operating mode will be read as zeros Data reception is double buffered so that reception of a second character may already begin before the previously received character has been read out of the receive buffer register In all modes receive buffer overrun error detection can be selected through bit SOOEN When enabled the overrun error status flag SOOE and the error interrupt request flag SOEIR will be set when the receive buffer register has not been read by the time reception of a second character is complete The previously received character in the receive buffer is overwritten The Loop Back option selected by bit SOLB allows the data currently being transmitted to be received simultaneously in the receive buffer This may be used to test serial communication routines at an early stage without having to provide an external network In loop back mode the alternate input output functions of the Port 3 pins are not necessary Note Serial data transmission or reception is only possible when the Baud Rate Generator Run Bit SOR is set to 1 Otherwise the serial interface is idle Do not program the mode control field SOM in register SOCON to one of the reserved combinations to avoid unpredictable behaviour of the serial interface Semiconductor Group 11 3 Version 1 0 11 97 Sl EM ENS The Asynchronous Synchronous Serial Interface C164CI 11 1 Asynchronous Operation Asynchronous mode supports full duplex communi
160. als The trigger signal is selected the same way as the clock source for counter mode see table above ie a transition of the auxiliary timer s input or the output toggle latch T3OTL may trigger the reload Note When programmed for reload mode the respective auxiliary timer T2 or T4 stops independent of its run flag T2R or T4R TXIN P3 7 P3 5 sarin e Select d Reload Register Tx Interrupt ly tar Request Y 1 Input rar Interrupt Clock Core Timer T3 T3IR Request Up Down T30UT To P3 3 X 2 4 T30E MCB02035 Figure 10 12 GPT1 Auxiliary Timer in Reload Mode Upon a trigger signal T3 is loaded with the contents of the respective timer register T2 or T4 and the interrupt request flag T2IR or T4IR is set Note When a T3OTL transition is selected for the trigger signal also the interrupt request flag T3IR will be set upon a trigger indicating T3 s overflow or underflow Modifications of T3OTL via software will NOT trigger the counter function of T2 T4 The reload mode triggered by T3OTL can be used in a number of different configurations Depending on the selected active transition the following functions can be performed If both a positive and a negative transition of TSOTL is selected to trigger a reload the core timer will be reloaded with the contents of the auxiliary timer each time it overflows or underflows This is the standard reload mode reload on overflow under
161. alue which was written to their port output latches When the alternate output function of a port pin is used by a peripheral the state of this pin is determined by the last action of the peripheral before the clocks were switched off Note All pin drivers can be switched off by selecting the general port disable function prior to entering Power Down mode Semiconductor Group 21 5 Version 1 0 11 97 SIEMENS Power Management C164Cl State of C164Cl output pins during Idle and Power Down mode C164Cl Output Pin s Idle Mode Power Down Mode if pin drivers are generally enabled No External bus No External bus external bus enabled external bus enabled ALE Low Low Low Low RD WR High High High High CLKOUT Active Active High High RSTOUT 1 1 1 1 POL Port Latch Data Floating Port Latch Data Floating POH Port Latch Data A15 A8 2 Float PortLatch Data A15 A8 2 Float PORT1 Port Latch Data Port Latch Data Port Latch Data Port Latch Data Port 4 Port Latch Data Port Latch Data Port Latch Data Port Latch Data Last segment Last segment CSx 3 CSx 3 BHE Port Latch Data Last value Port Latch Data Last value Other Port Port Latch Data Port Latch Data Port Latch Data Port Latch Data Output Pins Alternate Function Alternate Function Alternate Function Alternate Function Note 1 High if EINIT was executed before entering Idle or Power Down mode Low
162. an only be read but not written by data operations It is however modified either directly by means of the JMPS and CALLS instructions or indirectly via the stack by means of the RETS and RETI instructions Upon the acceptance of an interrupt or the execution of a software TRAP instruction the CSP register is automatically set to zero Semiconductor Group 4 18 Version 1 0 11 97 SIEMENS The Central Processing Unit CPU C164Cl code Segment 15 CSP Register 0 15 IP Register 0 FF FFFFy 7 255 254 FE 0000 1 M A J 0109995 24 20 18 Bit Physical Code Address 0 000000 l A A i MCA02265 Figure 4 5 Addressing via the Code Segment Pointer Note When segmentation is disabled the IP value is used directly as the 16 bit address Semiconductor Group 4 19 Version 1 0 11 97 SIEMENS The Central Processing Unit CPU C164Cl The Data Page Pointers DPPO DPP1 DPP2 DPP3 These four non bit addressable registers select up to four different data pages being active simultaneously at run time The lower 10 bits of each DPP register select one of the 1024 possible 16 Kbyte data pages while the upper 6 bits are reserved for future use The DPP registers allow to access the entire memory space in pages of 16 Kbytes each The DPP registers are implicitly used whenever data accesses to any memory location are made via indirect or direct
163. an overflow of the watchdog timer The initialization and also the further operation of the microcontroller system can thus be adapted to the respective circumstances eg a special routine may verify the software integrity after a watchdog timer reset The reset indication flags are not mutually exclusive ie more than one flag may be set after reset depending on its source The table below summarizes the possible combinations Reset Indication Flag Combinations Reset Indication Flags Reset Source LHWR SHWR SWR WDTR Long Hardware Reset X X X Short Hardware Reset X X Software Reset T E X Watchdog Timer Reset X X When the bidirectional reset mode is enabled the indicated flags are also set in the respective reset case The WDTCON reset value will then be different from the table value Note The listed reset values for WDTCON assume the reserved bits as 0 Long Hardware Reset is indicated when the RSTIN input is still sampled low active at the end of a hardware triggered internal reset sequence Short Hardware Reset is indicated when the RSTIN input is sampled high inactive at the end of a hardware triggered internal reset sequence Software Reset is indicated after a reset triggered by the excution of instruction SRST Watchdog Timer Reset is indicated after a reset triggered by an overflow of the watchdog timer Note When bidirectional reset is enabled the RSTIN pin is pulled lo
164. and all auto increment or auto decrement writes to GPRs used as indirect address pointers are performed during the execute stage of an instruction too 4th gt WRITE BACK In this stage all external operands and the remaining operands within the internal RAM space are written back A particularity of the C164Cl are the so called injected instructions These injected instructions are generated internally by the machine to provide the time needed to process instructions which cannot be processed within one machine cycle They are automatically injected into the decode stage of the pipeline and then they pass through the remaining stages like every standard instruction Program interrupts are performed by means of injected instructions too Although these internally injected instructions will not be noticed in reality they are introduced here to ease the explanation of the pipeline in the following Sequential Instruction Processing Each single instruction has to pass through each of the four pipeline stages regardless of whether all possible stage operations are really performed or not Since passing through one pipeline stage takes at least one machine cycle any isolated instruction takes at least four machine cycles to be completed Pipelining however allows parallel ie simultaneous processing of up to four instructions Thus most of the instructions seem to be processed during one machine cycle as soon as the pipeline has been filled on
165. ansmission Separate select lines or special commands may also be used to move the role of the master to another device in the network In this case the previous master and the future master previous slave will have to toggle their operating mode SSCMS and the direction of their port pins see description above 12 2 Half Duplex Operation In a half duplex configuration only one data line is necessary for both receiving and transmitting of data The data exchange line is connected to both pins MTSR and MRST of each device the clock line is connected to the SCLK pin The master device controls the data transfer by generating the shift clock while the slave devices receive it Due to the fact that all transmit and receive pins are connected to the one data exchange line serial data may be moved between arbitrary stations Similar to full duplex mode there are two ways to avoid collisions on the data exchange line only the transmitting device may enable its transmit pin driver the non transmitting devices use open drain output and only send ones Since the data inputs and outputs are connected together a transmitting device will clock in its own data at the input pin MRST for a master device MTSR for a slave By these means any corruptions on the common data exchange line are detected where the received data is not equal to the transmitted data Semiconductor Group 12 8 Version 1 0 11 97 SIEM ENS The High Speed Synchronous Seri
166. ansmit Shift RXDO0 P3 11 Register Register Transmit Receive Buffer Reg Transmit Buffer Reg SORBUF SOTBUF 4 Internal Bus MCB02220 Figure 11 5 Synchronous Mode of Serial Channel ASCO 1 Semiconductor Group 11 8 Version 1 0 11 97 Sl EM ENS The Asynchronous Synchronous Serial Interface C164CI Synchronous transmission begins within 4 state times after data has been loaded into SOTBUF provided that SOR is set and SOREN 0 half duplex no reception Data transmission is double buffered When the transmitter is idle the transmit data loaded into SOTBUF is immediately moved to the transmit shift register thus freeing SOTBUF for the next data to be sent This is indicated by the transmit buffer interrupt request flag SOTBIR being set SOTBUF may now be loaded with the next data while transmission of the previous one is still going on The data bits are transmitted synchronous with the shift clock After the bit time for the 8th data bit both pins TXDO and RXDO will go high the transmit interrupt request flag SOTIR is set and serial data transmission stops Pin TXDO P3 10 must be configured for alternate data output ie P3 10 1 and DP3 10 1 in order to provide the shift clock Pin RXDO P3 11 must also be configured for output P3 112 1 and DP3 11 1 during transmission Synchronous reception is initiated by setting bit SOREN 1 If bit SOR 1 the data applied at pin RXDO are clocked
167. arate control register which contains an interrupt request flag an inter rupt enable flag and an interrupt priority bitfield Once having been accepted by the CPU an interrupt service can only be interrupted by a higher prioritized service request For standard interrupt processing each of the possible interrupt sources has a dedicated vector location 3 Multiple Register Banks This feature allows the user to specify up to sixteen general pur pose registers located anywhere in the internal RAM A single one machine cycle instruction allows to switch register banks from one task to another 4 Interruptable Multiple Cycle Instructions Reduced interrupt latency is provided by allowing multiple cycle instructions multiply divide to be interruptable With an interrupt response time within a range from just 5 to 10 CPU clock cycles in case of internal program execution the C164Cl is capable of reacting very fast on non deterministic events Its fast external interrupt inputs are sampled every CPU clock cycle and allow to recognize even very short external signals The C164Cl also provides an excellent mechanism to identify and to process exceptions or error conditions that arise during run time so called Hardware Traps Hardware traps cause an immediate non maskable system reaction which is similiar to a standard interrupt service branching to a dedicated vector table location The occurrence of a hardware trap is additionally signif
168. are supported by all derivatives Please refer to the corresponding descriptions in the data sheets Semiconductor Group 25 1 Version 1 0 11 97 SIEMENS Device Specification C164CI zzz a Xx z uu t B fo ooookE 2999 RSASAR EE Bw e Lre cu OTHO S D Zzzzoooo 5 ooooutnoo Oxcxc x0000 ozmxoovoq op0OOWN oOo0qwWN 7oO cL IL TITITIIIIITra2o LG 515 56 Ow wo E bp Am ym m m o am eL 0nndanononnnzumcnnunnnnnsr ETE TETEIEILIEITEIETETEILILE TIL IETEITLILILI CQ O OO Pl K QO LO TON eo OO PF KO LO st CO QN ernrrnmrrr prnrg rr N O O O O O O CO oO Varer L 1 L Vss P5 4 AN4 T2EUD L 2 _ P1H 0 CCEPOSO EXOIN P5 5 AN5 T4EUD 3 P1L 7 CTRAP P5 6 AN6 T2IN 4 P1L 6 COUT63 P5 7 AN7 T4IN L 5 Vss Vss U6 XTAL1 VDD 7 XTAL2 P3 4 T3EUD 8 Vpop P3 6 T3IN P3 8 MRST P3 9 MTSR L P3 10 TxDO P3 11 RxDO P3 12 BHE WRH P3 13 SCLK P3 15 CLKOUT P4 0 A16 CS3 P4 1 A17 CS2 P4 2 A18 CS1 c C1 64CI P1L 5 COUT62 P1L 4 CC62 P1L 3 COUT61 P1L 2 CC61 P1L 1 COUT60 P1L 0 CC60 POH 7 AD15 POH 6 AD14 POH 5 AD13 POH 4 AD12 POH 3 AD11 E mk sm ukcomd mh ums md c mms uus OANODOaAKRWNY o Ves L 20 Vss cx R OMOMROrAMYNONRADRBDYS an AADMA x L IL LILI LILI LILI LIL LILI LILI aio LI Lu OornmaytrynNoOorRDMODOA ape eeeshsoagagagaas a 0dcr EXgy xzzxxxaxxxcxio 2 Z TOA O NO O NO rac
169. as WR and BHE signals CSSEL Chip Select Line Selection Number of active CS outputs 0 0 3 CS lines CS2 CS0 0 1 2 CS lines CS1 CSO 1 0 No CS lines at all 11 4 CS lines CS3 CS0 Default without pulldowns SALSEL Segment Address Line Selection Number of active segment address outputs 0 0 4 bit segment address A19 A16 0 1 No segment address lines at all 1 0 6 bit segment address A21 A16 1 1 2 bit segment address A17 A16 Default without pulldowns CLKCFG Clock Generation Mode Configuration These pins define the clock generation mode ie the mechanism how the the internal CPU clock is generated from the externally applied XTAL1 input clock Note RPOH cannot be changed via software but rather allows to check the current configuration Precautions and Hints The external bus interface is enabled as long as at least one of the BUSCON registers has its BUSACT bit set Not all address windows defined via registers ADDRSELx may overlap each other The operation of the EBC will be unpredictable in such a case See chapter Address Window Arbitration The address windows defined via registers ADDRSELx may overlap internal address areas Internal accesses will be executed in this case For any access to an internal address area the EBC will remain inactive see EBC Idle State Semiconductor Group 9 20 Version 1 0 11 97 The External Bus Interface C164CI SIEMENS 9 4 EBC idl
170. as external count direction control input it must be configured as input ie its corresponding direction control bit DP3 4 must be set to 0 GPT1 Core Timer T3 Count Direction Control Pin TXEUD Bit TxUDE Bit TXUD Count Direction X 0 0 Count Up X 0 1 Count Down 0 1 0 Count Up 1 1 0 Count Down 0 1 1 Count Down 1 1 1 Count Up Note The direction control works the same for core timer T3 and for auxiliary timers T2 and T4 Therefore the pins and bits are named Tx Timer 3 Output Toggle Latch An overflow or underflow of timer T3 will clock the toggle bit T3OTL in control register T3CON T3OTL can also be set or reset by software In addition T3OTL can be used in conjunction with the timer over underflows as an input for the counter function or as a trigger source for the reload function of the auxiliary timers T2 and T4 Semiconductor Group 10 4 Version 1 0 11 97 SIEM ENS The General Purpose Timer Unit C164Cl Timer 3 in Timer Mode Timer mode for the core timer T3 is selected by setting bit field T3M in register T3CON to 0003 In this mode T3 is clocked with the internal system clock CPU clock divided by a programmable prescaler which is selected by bit field T3l The input frequency fr4 for timer T3 and its resolution l r3 are scaled linearly with lower clock frequencies fcpy as can be seen from the following formula fcpu 8 o T3l s o e tra us 8
171. as the highest priority If a higher priority interrupt lower number occurs before the current interrupt is processed INTID is updated and the new interrupt overrides the last one Interrupt Register EF024 XReg Reset Value XXy 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r Bit Function INTID Interrupt Identifier This number indicates the cause of the interrupt When no interrupt is pending the value will be 00 Semiconductor Group 19 8 Version 1 0 11 97 SIEMENS The On Chip CAN Interface C164Cl The table below lists the valid values for INTID and their corresponding interrupt sources INTID Cause of the Interrupt 00 Interrupt Idle There is no interrupt request pending 01 Status Change Interrupt The CAN controller has updated not necessarily changed the status in the Control Register This can refer to a change of the error status of the CAN controller EIE is set and BOFF or EWRN change or to a CAN transfer incident SIE must be set like reception or transmission of a message RXOK or TXOK is set or the occurrence of a CAN bus error LEC is updated The CPU may clear RXOK TXOK and LEC however writing to the status partition of the Control Register can never generate or reset an interrupt To update the INTID value the status partition of the Control Register must be read 02 Message 15 Interrupt Bit INTPND in the Message Control Register of message object 15 last mes
172. as the interrupt vector pointing into the internal code memory the interrupt response time is 1 word bus access plus 4 states After an interrupt service routine has been terminated by executing the RETI instruction and if further interrupts are pending the next interrupt service routine will not be entered until at least two instruction cycles have been executed of the program that was interrupted In most cases two instructions will be executed during this time Only one instruction will typically be executed if the first instruction following the RETI instruction is a branch instruction without cache hit or if it reads an operand from internal code memory or if it is executed out of the internal RAM Note A bus access in this context includes all delays which can occur during an external bus cycle Semiconductor Group 5 17 Version 1 0 11 97 SIEMENS Interrupt and Trap Functions C164CI PEC Response Times The PEC response time defines the time from an interrupt request flag of an enabled interrupt source being set until the PEC data transfer being started The basic PEC response time for the C164Cl is 2 instruction cycles Pipeline Stage Cycle 1 Cycle 2 Cycle 3 Cycle 4 FETCH N N 1 N 2 N 2 DECODE N 1 N PEC N 1 EXECUTE N 2 N 1 N PEC WRITEBACK N 3 N 2 N 1 N IR Flag PEC Response Time Figure 5 5 Pipeline Diagram for PEC Response Time In the figure above the respectiv
173. at an address th at is a multiple of 16 Note All message objects must be initialized by the CPU even those which are not going to be used before clearing the INIT bit Message Control Arbitration Reserved 0 Object Start Address 2 4 6 8 10 12 14 Figure 19 4 Message Object Address Map Each element of the Message Control Register is made of two complementary bits This special mechanism allows the selective setting or resetting of specific elements leaving others unchanged without requiring read modify write cycles None of these elements will be affected by reset The table below shows how to use and interpret these 2 bit fields Value Function on Write Meaning on Read 00 reserved reserved 0 1 Reset element Element is reset 10 Set element Element is set 1 1 Leave element unchanged reserved Semiconductor Group 19 13 Version 1 0 11 97 SIEMENS The On Chip CAN Interface C164Cl Message Control Register EFn0 XReg Reset Value UUUU 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MSGLST rw rw rw rw rw rw rw rw Bit Function INTPND Interrupt Pending Indicates if this message object has generated an interrupt request see TXIE and RXIE since this bit was last reset by the CPU or not RXIE Receive Interrupt Enable Defines if bit INTPND is set after successful reception of a frame TXIE Transmit Interrupt Enable Defines if bit INTPND is s
174. ation 00 0000 the bootstrap loader is off no OTP programming modes are active Semiconductor Group 20 10 Version 1 0 11 97 SIEMENS System Reset C164CI External Bus Type Pins POL 7 and POL 6 BUSTYP select the external bus type during reset if an external start is selected via pin EA This allows the configuration of the external bus interface of the C164Cl even for the first code fetch after reset The two bits are copied into bit field BTYP of register BUSCONO POL 7 controls the data bus width while POL 6 must remain high This bit field may be changed via software after reset if required BTYP Encoding External Data Bus Width External Address Bus Mode 00 Reserved Do not use this combination 0 1 8 bit Data Multiplexed Addresses 10 Reserved Do not use this combination 11 16 bit Data Multiplexed Addresses PORTO is automatically switched to the selected bus mode PORTO drives both the 16 bit intra segment address and the output data For a 16 bit data bus BHE is automatically enabled for an 8 bit data bus BHE is disabled via bit BYTDIS in register SYSCON Default 16 bit data bus with multiplexed addresses Note If an internal start is selected via pin EA these two pins are disregarded and bit field BTYP of register BUSCONO is cleared Write Configuration Pin POH 0 WRC selects the initial operation of the control pins WR and BHE during reset When high this pin selects the standard
175. ation of the External Bus Semiconductor Group 1 7 Version 1 0 11 97 SIEMENS Architectural Overview C164Cl 2 Architectural Overview The architecture of the C164Cl combines the advantages of both RISC and CISC processors in a very well balanced way The sum of the features which are combined result in a high performance microcontroller which is the right choice not only for today s applications but also for future engineering challenges The C164Cl not only integrates a powerful CPU core and a set of peripheral units into one chip but also connects the units in a very efficient way One of the four buses used concurrently on the C164Cl is the XBUS an internal representation of the external bus interface This bus provides a standardized method of integrating application specific peripherals to produce derivates of the standard C164Cl A e IR J O Z5 ey ee Interrupt Controller Ext Bus PORTO Cirl PORT1 CAPCOM6 ADC Pons PLL Figure 2 1 C164CI Functional Block Diagram Semiconductor Group 2 1 Version 1 0 11 97 SIEMENS Architectural Overview C164Cl 2 4 Basic CPU Concepts and Optimizations The main core of the CPU consists of a 4 stage instruction pipeline a 16 bit arithmetic and logic unit ALU and dedicated SFRs Additional hardware is provided for a separate multiply and divide unit a bit mask generator and a barrel shifter C Internal l SP RAM I STKOV MB I
176. bit WDTIN in register WDTCON to be either fcpuy 2 or fopy 128 the reload value WDTREL for the high byte of WDT can be programmed in register WDTCON The period Pwpr between servicing the watchdog timer and the next overflow can therefore be determined by the following formula P o lt WDTIN gt 6 218 eNDTRELs 28 WOTE c no fopu The table below marks the possible ranges for the watchdog time which can be achieved using a certain CPU clock Some numbers are rounded to 3 significant digits Watchdog Time Ranges Reload value Prescaler for fopy in WOTREL 2 WDTIN 0 128 WDTIN 1 20 MHz 16 MHz 12MHz 20MHz 16MHz_ 12 MHz FFy 25 6 us 32 0 us 42 67 us 1 64 ms 2 05 ms 2 73 ms 7Fy 3 3 ms 4 13ms 5 5ms 211 ms 264 ms 352 ms 004 6 55 ms 8 19 ms 10 92 ms 419 ms 524 ms 699 ms Note For safety reasons the user is advised to rewrite WDTCON each time before the watchdog timer is serviced Semiconductor Group 13 3 Version 1 0 11 97 SIEMENS The Watchdog Timer WDT C164CI Reset Source Indication The reset indication flags in register WDTCON provide information on the source for the last reset As the C164Cl starts executing from location 00 0000 after any possible reset event the initialization software may check these flags in order to determine if the recent reset event was triggered by an external hardware signal via RSTIN by software itself or by
177. block commutation Compare timers T12 16 bit and T13 10 bit are free running timers which are clocked by the prescaled CPU clock In capture mode the contents of compare timer T12 is stored in the capture registers upon a programmable signal transition at pins CC6x From the programmer s point of view the term CAPCOM unit refers to a set of SFRs which are associated with this peripheral including the port pins which may be used for alternate input output functions including their direction control bits Ports amp Direction Control Data Registers Control Registers Interrupt Control Alternate Functions DPIH E T12P E T13P E CC6POS2 0 P1H 2 0 CTRAP P1L 7 CMP13 COUT63 P1L 6 COUT62 CC62 P1L 5 P1L 4 CC60 COUT61 CC61 P1L 3 P1L 2 COUT60 CC60 P1L 1 P1L 0 CC61 CC62 CTCON T12IC E TRCON T13IC E CC6MCON CCeEIC E CC6MSEL CCeCcIO E CC6MIC DP1H Port P1H Direction Control Register CC60 62 CAPCOM6 Register 0 2 P1H Port P1H Data Register TRCON CAPCOM6 Trap Control Register CC6MCON CAPCOM6G Mode Control Register TxP CAPCOM6 Timer x Period Register CC6MSEL CAPCOM6 Mode Select Register T120F CAPCOM6 Timer T12 Offset Register CC6MIC CAPCOM6 Mode Interrupt Control Register CMP13 CAPCOM6 Timer T13 Compare Register CC6EIC CAPCOM6 Emergency Interrupt Control Reg CTCON CAPCOM6 Timer Control Register CC6CIC CAPCOM6 Channel Interrupt Control Reg Figure 17 1 SFRs and Port Pins associated with
178. bytes are also supported for bits This allows the user to compare and modify a control bit for a peripheral in one instruction Multiple bit shift instructions have been included to avoid long instruction streams of single bit shift operations These are also performed in a single machine cycle In addition bit field instructions have been provided which allow the modification of multiple bits from one operand in a single instruction High Performance Branch Call and Loop Processing Due to the high percentage of branching in controller applications branch instructions have been optimized to require one extra machine cycle only when a branch is taken This is implemented by precalculating the target address while decoding the instruction To decrease loop execution overhead three enhancements have been provided The first solution provides single cycle branch execution after the first iteration of a loop Thus only one machine cycle is lost during the execution of the entire loop In loops which fall through upon completion no machine cycles are lost when exiting the loop No special instructions are required to perform loops and loops are automatically detected during execution of branch instructions The second loop enhancement allows the detection of the end of a table and avoids the use of two compare instructions embedded in loops One simply places the lowest negative number at the end of the specific table and specifies branch
179. cation where both transmitter and receiver use the same data frame format and the same baud rate Data is transmitted on pin TXDO P3 10 and received on pin RXDO P3 11 These signals are alternate functions of Port 3 pins Reload Register Cock J gt Baud Rate Timer 16 SOR SOM SOSTP SOREN Clock SORIR Receive Int Request SOPEN gt Serial Port Control SOTIR im Int RXDO P3 11 SOOEN q Error Int SOLB e Shift Clock PED Request Receive Shift Register Receive Buffer Reg Transmit Buffer Reg SORBUF SOTBUF lt Internal Bus gt Figure 11 2 Asynchronous Mode of Serial Channel ASCO TXDO P3 10 Semiconductor Group 11 4 Version 1 0 11 97 Sl EM ENS The Asynchronous Synchronous Serial Interface C164CI Asynchronous Data Frames 8 bit data frames either consist of 8 data bits D7 D0 S0M z 0015g or of 7 data bits D6 DO plus an automatically generated parity bit SOM 011 Parity may be odd or even depending on bit SOODD in register SOCON An even parity bit will be set if the modulo 2 sum of the 7 data bits is 1 An odd parity bit will be cleared in this case Parity checking is enabled via bit SOPEN always OFF in 8 bit data mode The parity error flag SOPE will be set along with the error interrupt request flag if a wrong parity bit is received The parity bit itself will be stored in bit SORBUF 7 Do
180. cation Flag WDTR in register WDTCON will be set in this case Semiconductor Group 13 2 Version 1 0 11 97 The Watchdog Timer WDT C164CI SIEMENS A watchdog reset will also complete a running external bus cycle before starting the internal reset sequence if this bus cycle does not use READY or samples READY active low after the programmed waitstates Otherwise the external bus cycle will be aborted To prevent the watchdog timer from overflowing it must be serviced periodically by the user software The watchdog timer is serviced with the instruction SRVWDT which is a protected 32 bit instruction Servicing the watchdog timer clears the low byte and reloads the high byte of the watchdog timer register WDT with the preset value from bitfield WDTREL which is the high byte of register WDTCON Servicing the watchdog timer will also reset bit WDTR After being serviced the watchdog timer continues counting up from the value lt WDTREL gt 29 Instruction SRVWDT has been encoded in such a way that the chance of unintentionally servicing the watchdog timer eg by fetching and executing a bit pattern from a wrong location is minimized When instruction SRVWDT does not match the format for protected instructions the Protection Fault Trap will be entered rather than the instruction be executed The time period for an overflow of the watchdog timer is programmable in two ways the input frequency to the watchdog timer can be selected via
181. cause of the overhead of flushing and filling The basic mechanism is the transformation of the addresses of a virtual stack area controlled via registers SP STKOV and STKUN to a defined physical stack area within the internal RAM via hardware This virtual stack area covers all possible locations that SP can point to ie 00 F000 through 00 FFFEy STKOV and STKUN accept the same 4 KByte address range The size of the physical stack area within the internal RAM that effectively is used for standard stack operations is defined via bitfield STKSZ in register SYSCON see below lt STKSZ gt Stack Size Internal RAM Addresses Words Significant Bits of Words of Physical Stack Stack Pointer SP 000 256 00 FBFE 00 FA00 Default after Reset SP 8 SP 0 001 128 00 FBFE 00 FB00 SP 7 SP 0 010p 64 O0 FBFE 00 FB80 SP 6 SP 0 011g 32 00 FBFE 00 FBCO SP 5 SP 0 100p 512 00 FBFE 00 F800 not for 1KByte IRAM SP 9 SP 0 101 Sa Reserved Do not use this combination 110g ex Reserved Do not use this combination 1115 1024 O0 FDFEj 00 FX00 Note No circular stack SP 11 SP 0 00 FX00 represents the lower IRAM limit ie 1 KB 00 FA00 2 KB 00 F600 3 KB 00 F200 The virtual stack addresses are transformed to physical stack addresses by concatenating the significant bits of the stack pointer register SP see table with the complementary most
182. ce after reset see figure below Instruction pipelining increases the average instruction throughput considered over a certain period of time In the following any execution time specification of an instruction always refers to the average execution time due to pipelined parallel instruction processing Semiconductor Group 4 3 Version 1 0 11 97 SIEMENS The Central Processing Unit CPU C164CI Figure 4 2 Sequential Instruction Pipelining Standard Branch Instruction Processing Instruction pipelining helps to speed sequential program processing In the case that a branch is taken the instruction which has already been fetched providently is mostly not the instruction which must be decoded next Thus at least one additional machine cycle is normally required to fetch the branch target instruction This extra machine cycle is provided by means of an injected instruction see figure below Were RA time Figure 4 3 Standard Branch Instruction Pipelining If a conditional branch is not taken there is no deviation from the sequential program flow and thus no extra time is required In this case the instruction after the branch instruction will enter the decode stage of the pipeline at the beginning of the next machine cycle after decode of the conditional branch instruction Semiconductor Group 4 4 Version 1 0 11 97 SIEMENS The Central Processing Unit CPU C
183. ce in case of a missing input clock signal Semiconductor Group 21 9 Version 1 0 11 97 SIEMENS Power Management C164Cl 21 4 Flexible Peripheral Management The power consumed by the C164Cl also depends on the amount of active logic Peripheral management enables the system designer to deactivate those on chip peripherals that are not required in a given system status eg a certain interface mode or standby All modules that remain active however will still deliver their usual performance If all modules that are fed by the peripheral clock driver PCD are disabled and also the other functions fed by the PCD are not required this clock driver itself may also be disabled to save additional power This flexibility is realized by distributing the CPU clock via several clock drivers which can be separately controlled and may also be smaller Idle mode Clock Generation CPU PCDDIS Peripherals Ports Intr Ctrl Interface Peripherals Figure 21 5 CPU Clock Distribution Note The Real Time Clock RTC is fed by a separate clock driver so it can be kept running even in Power Down mode while still all the other circuitry is disconnected from the clock The registers of the generic peripherals can be accessed even while the respective module is disabled as long as PCD is running the registers of peripherals which are connected to ICD can be accessed even in this case of course The registers of X periphe
184. cessed wordwise or bytewise some of them even bitwise Reading bytes from word SFRs is a non critical operation However when writing bytes to word SFRs the complementary byte of the respective SFR is cleared with the write operation Semiconductor Group 23 16 Version 1 0 11 97 SIEMENS Instruction Set Summary C164Cl 24 Instruction Set Summary This chapter briefly summarizes the C164Cl s instructions ordered by instruction classes This provides a basic understanding of the C164Cl s instruction set the power and versatility of the instructions and their general usage A detailed description of each single instruction including its operand data type condition flag settings addressing modes length number of bytes and object code format is provided in the Instruction Set Manual for the C16x Family This manual also provides tables ordering the instructions according to various criteria to allow quick references Summary of Instruction Classes Grouping the various instruction into classes aids in identifying similar instructions eg SHR ROR and variations of certain instructions eg ADD ADDB This provides an easy access to the possibilities and the power of the instructions of the C164Cl Note The used mnemonics refer to the detailled description Arithmetic Instructions Addition of two words or bytes ADD ADDB Addition with Carry of two words or bytes ADDC ADDCB Subtraction of two words or bytes SUB
185. checked using bit addressing When accessing registers in the ESFR area using 8 bit addresses or direct bit addressing an Extend Register EXTR instruction is required before to switch the short addressing mechanism from the standard SFR area to the Extended SFR area This is not required for 16 bit and indirect addresses The GPRs R15 RO are duplicated ie they are accessible within both register blocks via short 2 4 or 8 bit addresses without switching ESFR SWITCH EXAMPLE EXTR 4 Switch to ESFR area for next 4 instr MOV ODP2 datal6 ODP2 uses 8 bit reg addressing BFLDL DP6 mask data8 Bit addressing for bit fields BSET DP1H 7 Bit addressing for single bits MOV T8REL R1 T8REL uses 16 bit mem address R1 is duplicated into the ESFR space EXTR is not required for this access poss j The scope of the EXTR 4 instruction ends here MOV T8REL R1 T8REL uses 16 bit mem address R1 is accessed via the SFR space In order to minimize the use of the EXTR instructions the ESFR area mostly holds registers which are mainly required for initialization and mode selection Registers that need to be accessed frequently are allocated to the standard SFR area wherever possible Note The tools are equipped to monitor accesses to the ESFR area and will automatically insert EXTR instructions or issue a warning in case of missing or excessive EXTR instructions Semiconductor Group 3 8 Version
186. chip oscillator watchdog is disabled and the CPU clock is always fed from the oscillator input The PLL is switched off in this case CSCFG Chip Select Configuration Control 0 Latched CS mode The CS signals are latched internally and driven to the enabled port pins synchronously 1 Unlatched CS mode The CS signals are directly derived from the address and driven to the enabled port pins Semiconductor Group 9 13 Version 1 0 11 97 SIEMENS The External Bus Interface C164CI Bit Function WRCFG Write Configuration Control Set according to pin POH O during reset 0 Pins WR and BHE retain their normal function 1 Pin WR acts as WRL pin BHE acts as WRH CLKEN System Clock Output Enable CLKOUT 0 CLKOUT disabled pin may be used for general purpose IO 1 CLKOUT enabled pin outputs the system clock signal BYTDIS Disable Enable Control for Pin BHE Set according to data bus width 0 Pin BHE enabled 1 Pin BHE disabled pin may be used for general purpose IO ROMEN Internal ROM Enable Set according to pin EA during reset 0 Internal ROM disabled accesses to the ROM area use the external bus 1 Internal ROM enabled SGTDIS Segmentation Disable Enable Control 0 Segmentation enabled CSP is saved restored during interrupt entry exit 1 Segmentation disabled Only IP is saved restored ROMS1 Internal ROM Mapping 0 Internal ROM area mapped to segment 0 00 0000 00 7FFF 4 1 Intern
187. cleared when the interrupt handler is vectored to while the subnode request bit T14IR must be cleared by software Defining the RTC Time Base The reload timer T14 determines the input frequency of the RTC timer ie the RTC time base as well as the T14 interrupt cycle time The table below lists the interrupt period range and the T14 reload values for a time base of 1 s and 1 ms for several oscillator frequencies RTC Interrupt Periods and Reload Values Oscillator RTC Interrupt Period Reload Value A Reload Value B Frequency Minimum Maximum Ti4REL Base TI4REL Base 32 KHz 8 ms 524s FF83 1 000 s 4 MHz 64 0 us 4 19s C2F74 1 000 s FFFO 1 024 ms 5 MHz 51 2 us 3 35 s B3B54 0 999 s FFEC 1 024 ms 8 MHz 32 0 us 2 10s 85EE 1 000 s FFE1 0 992 ms 10 MHz 25 6 us 1 68 s 676A 0 999 s FFD9 0 998 ms 12 MHz 21 3 us 1 40s 48E5 1 000 s FFD2y 1 003 ms 16 MHz 16 0 us 1 05s OBDC 1 000 s FFC2 0 992 ms Semiconductor Group 14 3 Version 1 0 11 97 SIEMENS The Real Time Clock C164CI Increased RTC Accuracy through Software Correction The accuracy of the C164Cl s RTC is determined by the oscillator frequency and by the respective prescaling factor excluding or including T14 The accuracy limit generated by the prescaler is due to the quantization of a binary counter where the average is zero while the accuracy limit generated by the oscillator frequency is due to the difference
188. commended to always load the slave s transmit buffer prior to any transfer Register SSCCON Register SSCEIR SSCEINT SSCEIE Error Interrupt SSCEIR MCA01968 Figure 12 6 SSC Error Interrupt Control Semiconductor Group 12 13 Version 1 0 11 97 SIEM ENS The High Speed Synchronous Serial Interface C164CI 12 5 SSC Interrupt Control Three bit addressable interrupt control registers are provided for serial channel SSC Register SSCTIC controls the transmit interrupt SSCRIC controls the receive interrupt and SSCEIC controls the error interrupt of serial channel SSC Each interrupt source also has its own dedicated interrupt vector SCTINT is the transmit interrupt vector SCRINT is the receive interrupt vector and SCEINT is the error interrupt vector The cause of an error interrupt request receive phase baudrate transmit error can be identified by the error status flags in control register SSCCON Note In contrary to the error interrupt request flag SSCEIR the error status flags SSCxE are not reset automatically upon entry into the error interrupt service routine but must be cleared by software SSCTIC FF72 B9y SFR Reset Value 00 EL OM UM CT DUNG NEL EN NS ONU NM NEM DI M ONSE SSCRIC FF74 BAy SFR Reset Value 00j 19 14 19 12 101 10 9 8 7 SSCEIC FF76 BB SFR Reset Value 00 N OO es 10 Ot Y LR NUT n 0 Note Please refer to the general Interrupt Control Reg
189. compare modes 1 and 3 the compare event or the timer overflow in compare mode 3 directly effects the port output latch In compare mode 1 when a valid compare match occurs the state of the port output latch is read by the CAPCOM control hardware via the line Alternate Latch Data Input inverted and written back to the latch via the line Alternate Data Output The port output latch is clocked by the signal Compare Trigger which is generated by the CAPCOM unit In compare mode 3 when a match occurs the value 1 is written to the port output latch via the line Alternate Data Output When an overflow of the corresponding timer occurs a 0 is written to the port output latch In both cases the output latch is clocked by the signal Compare Trigger The direction of the pin should be set to output by the user otherwise the pin will be in the high impedance state and will not reflect the state of the output latch As can be seen from the port structure below the user software always has free access to the port pin even when it is used as a compare output This is useful for setting up the initial level of the pin when using compare mode 1 or the double register mode In these modes unlike in compare mode 3 the pin is not set to a specific value when a compare match occurs but is toggled instead When the user wants to write to the port pin at the same time a compare trigger tries to clock the output latch the write operation of the us
190. consecutive words within the internal RAM The Context Pointer CP register determines the base address of the currently active register bank This register bank may consist of up to 16 word GPRs RO R1 R15 and or of up to 16 byte GPRs RLO RHO RL7 RH7 The sixteen byte GPRs are mapped onto the first eight word GPRs see table below In contrast to the system stack a register bank grows from lower towards higher address locations and occupies a maximum space of 32 Byte The GPRs are accessed via short 2 4 or 8 bit addressing modes using the Context Pointer CP register as base address independent of the current DPP register contents Additionally each bit in the currently active register bank can be accessed individually Mapping of General Purpose Registers to RAM Addresses Internal RAM Address Byte Registers Word Register CP 1E ave R15 CP 1Cy R14 CP 1Ay R13 lt CP gt 184 R12 CP 164 R11 lt CP gt 144 Eu R10 CP 124 Sd R9 CP 104 _ R8 CP OE RH7 RL7 R7 CP 0Cy RH6 RL6 R6 CP OAH RH5 RL5 R5 CP 08 RH4 RL4 R4 CP 064 RH3 RL3 R3 CP 044 RH2 RL2 R2 CP 024 RH1 RL1 R1 CP 00 RHO RLO RO The C164CI supports fast register bank context switching Multiple register banks can physically exist within the internal RAM at the same time Only the register bank selecte
191. controllers provide a great extent of identical functionality it makes sense to describe a superset of the provided features For this reason some sections of this manual do not refer to all derivatives that are offered or planned eg devices with different kinds of on chip memory The descriptions in this manual refer to the following derivatives of the C164 class C164CI 8EM Version with 64 KByte on chip OTP memory e C164CI Version with on chip mask ROM under discussion This manual is valid for the mentioned derivatives Of course it refers to all devices of the different available temperature ranges and packages For simplicity all these various versions are referred to by the term C164Cl throughout this manual The complete pro electron conforming designations are listed in the respective data sheets Semiconductor Group 1 1 Version 1 0 11 97 SIEMENS Introduction C164CI 1 1 The Members of the 16 bit Microcontroller Family The microcontrollers of the Siemens 16 bit family have been designed to meet the high performance requirements of real time embedded control applications The architecture of this family has been optimized for high instruction throughput and minimum response time to external stimuli interrupts Intelligent peripheral subsystems have been integrated to reduce the need for CPU intervention to a minimum extent This also minimizes the need for communication via the external bus interface The high flexibilit
192. ction can be executed deliberately within a program eg to leave bootstrap loader mode or upon a hardware trap that reveals a system failure Note A software reset disregards the configuration of POL 5 POL 0 Watchdog Timer Reset When the watchdog timer is not disabled during the initialization or serviced regularly during program execution is will overflow and trigger the reset sequence Other than hardware and software reset the watchdog reset completes a running external bus cycle if this bus cycle either does not use READY at all or if READY is sampled active low after the programmed waitstates When READY is sampled inactive high after the programmed waitstates the running external bus cycle is aborted Then the internal reset sequence is started Note A watchdog reset disregards the configuration of POL 5 POL 0 The watchdog reset cannot occur while the C164Cl is in bootstrap loader mode Semiconductor Group 20 2 Version 1 0 11 97 SIEMENS System Reset C164CI Bidirectional Reset In a special mode Bidirectional reset the C164Cl s line RSTIN normally an input may be driven active by the chip logic eg in order to support external equipment which is required for startup eg flash memory RSTIN Internal Circuitry A Reset sequence active BDRSTEN 1 Figure 20 2 Bidirectional Reset Operation Bidirectional reset reflects internal reset sources software watchdog also to the RSTIN pin and
193. ction to the ESFR space using a single instruction Note Instructions EXTR EXTPR and EXTSR inhibit interrupts the same way as ATOMIC The switching to the ESFR area and data page overriding is checked by the development tools or handled automatically Nested Locked Sequences Each of the described extension instruction and the ATOMIC instruction starts an internal extension counter counting the effected instructions When another extension or ATOMIC instruction is contained in the current locked sequence this counter is restarted with the value of the new instruction This allows the construction of locked sequences longer than 4 instructions Note Interrupt latencies may be increased when using locked code sequences PEC requests are not serviced during idle mode if the IDLE instruction is part of a locked sequence Semiconductor Group 22 13 Version 1 0 11 97 SIEMENS System Programming C164CI 22 10 Handling the Internal Code Memory The Mask ROM OTP Flash versions of the C164Cl provide on chip code memory that may store code as well as data The lower 32 KByte of this code memory are referred to as the internal ROM area Access to this internal ROM area is controlled during the reset configuration and via software The ROM area may be mapped to segment 0 to segment 1 or the code memory may be disabled at all Note The internal ROM area always occupies an address area of 32 KByte even if the implemented mask ROM OTP
194. ctively Note Bit SGTDIS of register SYSCON defines if the CSP register is saved during interrupt entry segmentation active or not segmentation disabled Semiconductor Group 9 2 Version 1 0 11 97 SIEMENS The External Bus Interface C164CI Multiplexed Bus Modes In the multiplexed bus modes the 16 bit intra segment address as well as the data use PORTO The address is time multiplexed with the data and has to be latched externally The width of the required latch depends on the selected data bus width ie an 8 bit data bus requires a byte latch the address bits A15 A8 on POH do not change while POL multiplexes address and data a 16 bit data bus requires a word latch the least significant address line AO is not relevant for word accesses The upper address lines An A16 are permanently output on Port 4 if segmentation is enabled and do not require latches The EBC initiates an external access by generating the Address Latch Enable signal ALE and then placing an address on the bus The falling edge of ALE triggers an external latch to capture the address After a period of time during which the address must have been latched externally the address is removed from the bus The EBC now activates the respective command signal RD WR WRL WRH Data is driven onto the bus either by the EBC for write cycles or by the external memory peripheral for read cycles After a period of time which is determined by the access tim
195. ctor Group 1 4 Version 1 0 11 97 SIEMENS Introduction C164CI 8 Channel Peripheral Event Controller PEC Interrupt driven single cycle data transfer Transfer count option standard CPU interrupt after a programmable number of PEC transfers Eliminates overhead of saving and restoring system state for interrupt requests Intelligent On chip Peripheral Subsystems 8 Channel 10 bit A D Converter with programmable conversion time 9 7 uus minimum auto scan modes channel injection mode Two Capture Compare Units with independent time bases each very flexible PWM unit event recording unit with different operating modes Multifunctional General Purpose Timer Unit three 16 bit timers counters 400 ns maximum resolution Asynchronous Synchronous Serial Channel USART with baud rate generator parity framing and overrun error detection High Speed Synchronous Serial Channel programmable data length and shift direction Watchdog Timer with programmable time intervals Bootstrap Loader for flexible system initialization On chip CAN Module 2 0B active 59 IO Lines With Individual Bit Addressability Tri stated in input mode Push pull or open drain output mode Selectable input thresholds not on all pins Different Temperature Ranges 0 to 70 C 40 to 85 C 40 to 125 C Siemens CMOS Process Low Power CMOS Technology including power saving Idle and Power Down modes 80 Pin Plastic Metric Q
196. current contents of the allocated timer will be latched captured into the capture compare register in response to an external event at the port pin which is associated with this register In addition a specific interrupt request for this capture compare register is generated Either a positive a negative or both a positive and a negative external signal transition at the pin can be selected as the triggering event The contents of all registers which have been selected for one of the five compare modes are continuously compared with the contents of the allocated timers When a match occurs between the timer value and the value in a capture compare register specific actions will be taken based on the selected compare mode The CAPCOM6 unit provides 3 capture compare channels and 1 additional compare channel The 3 capture compare channels can control two output lines each which can be programmed to generate non overlapping pulse patterns The additional compare channel may either generate a separate output signal or modulate the output signals of the 3 other channels Versatile multichannel PWM signals can be generated either controlled internally via a timer or externally eg via hall sensors The active level for each output can be selected individually The trap function allows to drive the outputs to a defined level in response to an external signal Semiconductor Group 2 13 Version 1 0 11 97 SIEMENS Architectural Overview C164Cl
197. d Class A Traps NMI stack overflow underflow are disabled A Class B Trap illegal opcode illegal bus access etc however will interrupt the atomic sequence since it indicates a severe hardware problem The interrupt inhibit caused by an ATOMIC instruction gets active immediately ie no other instruction will enter the pipeline except the one that follows the ATOMIC instruction and no interrupt request will be serviced in between All instructions requiring multiple cycles or hold states are regarded as one instruction in this sense eg MUL is one instruction Any instruction type can be used within an unseparable code sequence ATOMIC 3 The next 3 instr are locked No NOP requ MOV RO 1234H Instr 1 no other instr enters pipeline MOV R1 5678H Instr 2 MUL RO R1 Instr 3 MUL regarded as one instruction MOV R2 MDL This instruction is out of the scope 0f the ATOMIC instruction sequence Semiconductor Group 22 12 Version 1 0 11 97 SIEMENS System Programming C164CI 22 9 Overriding the DPP Addressing Mechanism The standard mechanism to access data locations uses one of the four data page pointers DPPx which selects a 16 KByte data page and a 14 bit offset within this data page The four DPPs allow immediate access to up to 64 KByte of data In applications with big data arrays especially in HLL applications using large memory models this may require frequent reloading of the DPPs even for single acc
198. d T3EUD When the on chip peripheral associated with a Port 3 pin is configured to use the alternate output function its Alternate Data Output line is ANDed with the port output latch line When using these alternate functions the user must set the direction of the port line to output DP3 y 1 and must set the port output latch P3 y 1 Otherwise the pin is in its high impedance state when configured as input or the pin is stuck at 0 when the port output latch is cleared When the alternate output functions are not used the Alternate Data Output line is in its inactive state which is a high level 1 Port 3 pins with alternate output functions are TxDO and CLKOUT When the on chip peripheral associated with a Port 3 pin is configured to use both the alternate input and output function the descriptions above apply to the respective current operating mode The direction must be set accordingly Port 3 pins with alternate input output functions are MTSR MRST RxDO and SCLK Semiconductor Group 7 14 Version 1 0 11 97 Parallel Ports SIEMENS ae aes Write pos Open Drain Read ODP3 y i Write DP3 y n t Direction s e Latch r n Read DP3 y a Alternate Data B Output u S Write P3 y Port Output P3 y Latch Output Buffer Read P3 y Alternate NU Data MCB02229 Input Figure 7 9 Block Diagram of a Port 3 Pin with Alternate Inp
199. d also the locations referred to by these pointers are accessed independent of the current DPP register contents If a PEC channel is not used the corresponding pointer locations area available and can be used for word or byte data storage For more details about the use of the source and destination pointers for PEC data transfers see section Interrupt and Trap Functions Semiconductor Group 3 7 Version 1 0 11 97 SIEMENS Memory Organization C164Cl Special Function Registers The functions of the CPU the bus interface the IO ports and the on chip peripherals of the C164Cl are controlled via a number of so called Special Function Registers SFRs These SFRs are arranged within two areas of 512 Byte size each The first register block the SFR area is located in the 512 Bytes above the internal RAM 00 FFFFj 00 FE00 j the second register block the Extended SFR ESFR area is located in the 512 Bytes below the internal RAM 00 F1FF 00 F000 Special function registers can be addressed via indirect and long 16 bit addressing modes Using an 8 bit offset together with an implicit base address allows to address word SFRs and their respective low bytes However this does not work for the respective high bytes Note Writing to any byte of an SFR causes the non addressed complementary byte to be cleared The upper half of each register block is bit addressable so the respective control status bits can directly be modified or
200. d at even or odd byte addresses Words are stored in ascending memory locations with the low byte at an even byte address being followed by the high byte at the next odd byte address Double words code only are stored in ascending memory locations as two subsequent words Single bits are always stored in the specified bit position at a word address Bit position 0 is the least significant bit of the byte at an even byte address and bit position 15 is the most significant bit of the byte at the next odd byte address Bit addressing is supported for a part of the Special Function Registers a part of the internal RAM and for the General Purpose Registers XXXX6 H Sm T mt nie om de mm Byte XXXX3 H Byte XXXX2 H Word High Byte xxxx1 H Word Low Byte XXXx0 H XXXXF H MCD01996 Figure 3 2 Storage of Words Byte and Bits in a Byte Organized Memory Note Byte units forming a single word or a double word must always be stored within the same physical internal external ROM RAM and organizational page segment memory area Semiconductor Group 3 2 Version 1 0 11 97 SIEMENS Memory Organization C164Cl 3 1 Internal ROM The C164Cl may reserve an address area of variable size depending on the version for on chip mask programmable ROM Flash OTP memory organized as X 32 The lower 32 KByte of this on chip memory block are referred to as Internal ROM Area Internal ROM accesses are globally enabled or disabled
201. d bit is sampled at the 7th 8th and 9th cycle of this clock The baud rate for asynchronous operation of serial channel ASCO and the required reload value for a given baudrate can be determined by the following formulas fopu fopu Basme lt SOBRL c 1 Async 16 2 lt SOBRS gt lt SOBRL gt 1 T6 2 lt S0BRS gt Banc lt SOBRL gt represents the content of the reload register taken as unsigned 13 bit integer lt SOBRS gt represents the value of bit SOBRS ie 0 or 1 taken as integer The maximum baud rate that can be achieved for the asynchronous modes when using a CPU clock of 20 MHz is 625 KBaud The table below lists various commonly used baud rates together with the required reload values and the deviation errors compared to the intended baudrate ASCO Baudrate Generation Baud Rate SOBRS 0 fcpy 20 MHz SOBRS 1 fcpy 20 MHz Deviation Error Reload Value Deviation Error Reload Value 625 KBaud 0 0 00004 19 2 KBaud 1 7 1 4 001F4 0020 4 43 396 1 4 00144 00154 9600 Baud 0 2 1 4 00404 00414 1 0 1 4 002A4 002By 4800 Baud 0 2 0 6 1 0081 00824 1 0 0 2 0055 00564 2400 Baud 0 2 0 2 01034 01044 0 4 0 2 00AC 00ADY 1200 Baud 40 296 0 4 02074 0208 0 1 0 2 015A 015By 600 Baud 0 1 0 096 04104 0411 40 196 0 1 02B54 02B6 75 Baud 1 7 1FFFg 0 0 96 0 0 15B2y
202. d bits implemented in the C164Cl can be found at the end of chapter Architectural Overview Semiconductor Group 4 9 Version 1 0 11 97 SIEMENS The Central Processing Unit CPU C164Cl 4 3 Instruction State Times Basically the time to execute an instruction depends on where the instruction is fetched from and where possible operands are read from or written to The fastest processing mode of the C164Cl is to execute a program fetched from the internal code memory In that case most of the instructions can be processed within just one machine cycle which is also the general minimum execution time All external memory accesses are performed by the C164Cl s on chip External Bus Controller EBC which works in parallel with the CPU This section summarizes the execution times in a very condensed way A detailled description of the execution times for the various instructions and the specific exceptions can be found in the C16x Family Instruction Set Manual The table below shows the minimum execution times required to process a C164CI instruction fetched from the internal code memory the internal RAM or from external memory These execution times apply to most of the C164Cl instructions except some of the branches the multiplication the division and a special move instruction In case of internal ROM program execution there is no execution time dependency on the instruction length except for some special branch situations The
203. d by the Context Pointer register CP is active at a given time however Selecting a new active register bank is simply done by updating the CP register A particular Switch Context SCXT instruction performs register bank switching and an automatic saving of the previous context The number of implemented register banks arbitrary sizes is only limited by the size of the available internal RAM Details on using switching and overlapping register banks are described in chapter System Programming Semiconductor Group 3 6 Version 1 0 11 97 SIEMENS Memory Organization C164Cl PEC Source and Destination Pointers The 16 word locations in the internal RAM from 00 FCEO to 00 FCFE just below the bit addressable section are provided as source and destination address pointers for data transfers on the eight PEC channels Each channel uses a pair of pointers stored in two subsequent word locations with the source pointer SRCPx on the lower and the destination pointer DSTPx on the higher word address x 7 0 00 FD00 H 00 FCFE H 00 FCFE H WESEN 00 FCE0 H 00 FDDE H PEC Source and Destination Internal Pointers RAM ree 00 F600 4 00 FCEO H 00 F5FE H MCD02266 Figure 3 4 Location of the PEC Pointers Whenever a PEC data transfer is performed the pair of source and destination pointers which is selected by the specified PEC channel number is accessed independent of the current DPP register contents an
204. d with the asymmetrical SDD clock see figure above PLL Operation if available in Slow Down Mode Advantage Disadvantage Oscillator Watchdog PLL Fast switching back to PLL adds to power Active if not disabled running basic clock source consumption via bit OWDDIS PLL PLL causes no additional PLL must lock before Disabled off power consumption switching back to the basic clock source if the PLL is the basic clock source All these clock options are selected via bitfield CLKCON in register SYSCON2 A state machine controls the switching mechanism itself and ensures a continuous and glitch free clock signal to the on chip logic This is especially important when switching back to PLL frequency when the PLL has temporarily been switched off In this case the clock source can be switched back either Semiconductor Group 21 7 Version 1 0 11 97 SIEMENS Power Management C164Cl automatically as soon as the PLL is locked again indicated by bit CLKLOCK in register SYSCON2 or manually ie under software control after bit CLKLOCK has become 1 The latter way is preferable if the application requires a defined point where the frequency changes Switching to Slow Down operation affects frequency sensitive peripherals like serial interfaces timers PWM etc If these units are to be operated in Slow Down mode their precalers or reload values must be adapted Please note that the reduced CPU frequency decreases eg t
205. de 1 allows several compare events within a single timer period An overflow of the allocated timer has no effect on the output pin nor does it disable or enable further compare events In order to use the respective port pin as compare signal output pin COxlO for compare register CCx in compare mode 1 this port pin must be configured as output ie the corresponding direction control bit must be set to 1 With this configuration the initial state of the output signal can be programmed or its state can be modified at any time by writing to the port output latch In compare mode 1 the port latch is toggled upon each compare event see Timing Example above Note If the port output latch is written to by software at the same time it would be altered by a compare event the software write will have priority In this case the hardware triggered change will not become effective If compare mode 1 is programmed for one of the registers CC16 CC19 the double register compare mode becomes enabled for this register if the corresponding bank 1 register is programmed to compare mode 0 see section Double Register Compare Mode Note If the port output latch is written to by software at the same time it would be altered by a compare event the software write will have priority In this case the hardware triggered change will not become effective On channels 24 27 compare mode 1 will generate interrupt requests but no output function is provi
206. ded Compare Mode 2 Compare mode 2 is an interrupt only mode similar to compare mode 0 but only one interrupt request per timer period will be generated Compare mode 2 is selected for register CCx by setting bit field CCMODx of the corresponding mode control register to 110g When a match is detected in compare mode 2 for the first time within a timer period the interrupt request flag CCxIR is set to 1 The corresponding port 2 pin is not affected and can be used for general purpose IO However after the first match has been detected in this mode all further compare events within the same timer period are disabled for compare register CCx until the allocated timer overflows This means that after the first match even when the compare register is reloaded with a value higher than the current timer value no compare event will occur until the next timer period In the example below the compare value in register CCx is modified from cv1 to cv2 after compare event 1 Compare event 2 however will not occur until the next period of timer Ty Semiconductor Group 16 14 Version 1 0 11 97 SIEMENS The Capture Compare Unit CAPCOM2 C164Cl Compare Reg CCx CCxIR sae Ae gt Set Port Mode 3 FAO CCXIO Reset CCMODx Input Interrupt Clock CAPCOM Timer Ty x gt TYIR Request MCB02019 Figure 16 8 Compare Mode 2 and 3 Block Diagram Note The port latch and pin remain unaffected i
207. dress of such a window defines the upper address bits which are not used within the address window of the specified size see table below For a given window size only those upper address bits of the start address are used marked R which are not implicitly used for addresses inside the window The lower bits of the start address marked x are disregarded Bit field RGSZ Resulting Window Size Relevant Bits R of Start Address A23 A12 0000 4 KByte R RRRRRRR RRR R 0001 8 KByte R RRRRRRRRR R x 0010 16 KByte R RRRR RR RR R x Xx 0011 32 KByte R RRRR RR RR x x xX 0100 64 KByte R RR RR RR R x x x x 0101 128 KByte R R R H R H H x X X X X 0110 256 KByte R RR RR HH x x x x x x 0111 512 KByte R ROR oR LR XX X Xe X 1000 1 MByte R RRR x x x x X x X X 1001 2 MByte R RR Gr Se x 2x0 x x X X 1010 4 MByte R R X X X X X X X X X X 1011 8 MByte HoX x X X X x X X X xXx Xx 11xx Reserved Semiconductor Group 9 18 Version 1 0 11 97 SIEMENS The External Bus Interface C164CI Address Window Arbitration The address windows that can be defined within the C164Cl s address space may partly overlap each other Thus eg small areas may be cut out of bigger windows in order to effectively utilize external resources especially within segment 0 For each access the EBC compares the current address with all address select registers programmable ADDRSELx and hardwired XADRSx This comparison is done in four levels Pr
208. duration of their active and passive phases which define the signals period and duty cycle In order to adapt these output signals to the requirements of a specific application the logic level of the passive state for each signal can be selected via register CC6MCON When using the trap function the outputs are switched to their trap level upon the activation of an external emergency signal The trap level is defined via the respective port output latches Note Changing the state levels during operation of CAPCOM6 will immediately affect the output signals It is rather recommended to define the output levels during initialization before the output signals are assigned and the CAPCOM6 unit is started In burst and multi channel modes the signals generated by the capture compare channels may additionally be modulated by the signal generated by the 10 bit compare channel This compare channel signal may optionally be inverted before modulating the other outputs The compare channel s signal may be output on pin COUT63 This output function is enabled by bit ECT130 in register CTCON If the output function is disabled COUT63 drives the defined passive level Semiconductor Group 17 4 Version 1 0 11 97 SIEMENS The Capture Compare Unit CAPCOM6 C164Cl 17 3 Edge Aligned Mode The compare timer counts up starting at 00004 When the timer contents match the respective compare value in register CC6x the associated output signal is switch to its
209. e Semiconductor Group 12 4 Version 1 0 11 97 SIEM ENS The High Speed Synchronous Serial Interface C164CI The transfer of serial data bits can be programmed in many respects the data width can be chosen from 2 bits to 16 bits transfer may start with the LSB or the MSB e the shift clock may be idle low or idle high data bits may be shifted with the leading or trailing edge of the clock signal the baudrate may be set from 152 Bd up to 5 MBd 20 MHz CPU clock the shift clock can be generated master or received slave This allows the adaptation of the SSC to a wide range of applications where serial data transfer is required The Data Width Selection supports the transfer of frames of any length from 2 bit characters up to 16 bit characters Starting with the LSB SSCHB 0 allows communication eg with ASCO devices in synchronous mode C166 family or 8051 like serial interfaces Starting with the MSB SSCHB 1 allows operation compatible with the SPI interface Regardless which data width is selected and whether the MSB or the LSB is transmitted first the transfer data is always right aligned in registers SSCTB and SSCRB with the LSB of the transfer data in bit 0 of these registers The data bits are rearranged for transfer by the internal shift register logic The unselected bits of SSCTB are ignored the unselected bits of SSCRB will be not valid and should be ignored by the receiver service routine The C
210. e evaluated after the current conversion fixed channel modes or after the current conversion sequence auto scan modes Semiconductor Group 18 4 Version 1 0 10 97 SIEMENS The Analog Digital Converter C164Cl Fixed Channel Conversion Modes These modes are selected by programming the mode selection field ADM in register ADCON to 00 single conversion or to 01 continuous conversion After starting the converter through bit ADST the busy flag ADBSY will be set and the channel specified in bit field ADCH will be converted After the conversion is complete the interrupt request flag ADCIR will be set In Single Conversion Mode the converter will automatically stop and reset bits ADBSY and ADST In Continuous Conversion Mode the converter will automatically start a new conversion of the channel specified in ADCH ADCIR will be set after each completed conversion When bit ADST is reset by software while a conversion is in progress the converter will complete the current conversion and then stop and reset bit ADBSY Auto Scan Conversion Modes These modes are selected by programming the mode selection field ADM in register ADCON to 10g single conversion or to 11 continuous conversion Auto Scan modes automatically convert a sequence of analog channels beginning with the channel specified in bit field ADCH and ending with channel 0 without requiring software to change the channel number After starting
211. e of the memory peripheral data become valid Read cycles Input data is latched and the command signal is now deactivated This causes the accessed device to remove its data from the bus which is then tri stated again Write cycles The command signal is now deactivated The data remain valid on the bus until the next external bus cycle is started a Bus Cycle Segment P4 ALE BUS PO L Address Loco Rbeta insiny E Enar Cup H7 BUS Po mI MCT02060 Figure 9 2 Multiplexed Bus Cycle Semiconductor Group 9 3 Version 1 0 11 97 SIEMENS The External Bus Interface C164CI Switching between the Bus Modes The EBC allows to switch between different bus modes dynamically ie subsequent external bus cycles may be executed in different ways Certain address areas may use an 8 bit or 16 bit data bus or predefined waitstates A change of the external bus characteristics can be initiated in two different ways Reprogramming the BUSCON and or ADDRSEL registers allows to either change the bus mode for a given address window or change the size of an address window that uses a certain bus mode Reprogramming allows to use a great number of different address windows more than BUSCONs are available on the expense of the overhead for changing the registers and keeping appropriate tables Switching between predefined address windows automatically selects the bus mode that is assoc
212. e selected by the mode control field CCMODx in the associated capture compare mode control register In the following each of the compare modes including the special double register mode is discussed in detail Compare Mode 0 This is an interrupt only mode which can be used for software timing purposes Compare mode 0 is selected for a given compare register CCx by setting bit field CCMODx of the corresponding mode control register to 100g In this mode the interrupt request flag CCxIR is set each time a match is detected between the content of compare register CCx and the allocated timer Several of these compare events are possible within a single timer period when the compare value in register CCx is updated during the timer period The corresponding port pin COxIO is not affected by compare events in this mode and can be used as general purpose IO pin If compare mode 0 is programmed for one of the registers CC24 CC27 the double register compare mode becomes enabled for this register if the corresponding bank 2 register is programmed to compare mode 1 see section Double Register Compare Mode Semiconductor Group 16 12 Version 1 0 11 97 SIEMENS The Capture Compare Unit CAPCOM2 C164Cl Interrupt CCxIR Request Compare Reg CCx Mode 1 Port gt CCxlO Toggle Latch CCMODx Input Clock Interrupt CAPCOM Timer Ty TyIR Request MCB02016 Figure 16 6 Compare Mode 0
213. e 9 1 SFRs and Port Pins Associated with the External Bus Interface Accesses to external memory or peripherals are executed by the integrated External Bus Controller EBC The function of the EBC is controlled via the SYSCON register and the BUSCONx and ADDRSELx registers The BUSCONXx registers specify the external bus cycles in terms of data width 16 bit 8 bit chip selects and length waitstates ALE RW delay These parameters are used for accesses within a specific address area which is defined via the corresponding register ADDRSELx The four pairs BUSCON1 ADDRSEL1 BUSCON4 ADDRSEL4 allow to define four independent address windows while all external accesses outside these windows are controlled via register BUSCONO Semiconductor Group 9 1 Version 1 0 11 97 SIEMENS The External Bus Interface C164CI Single Chip Mode Single chip mode is entered when pin EA is high during reset In this case register BUSCONO is initialized with 00004 which also resets bit BUSACTO so no external bus is enabled In single chip mode the C164Cl operates only with and out of internal resources No external bus is configured and no external peripherals and or memory can be accessed Also no port lines are occupied for the bus interface When running in single chip mode however external access may be enabled by configuring an external bus under software control Single chip mode allows the C164Cl to start execution out of the internal pr
214. e EBC is described in a dedicated chapter Internal Exec Unit Mul Div HW Instr Ptr Bit Mask Gen General Instr Reg 32 Purpose ROM 4 Stage 16 bit Pipeline Registers Barrel Shifter E l I I I SP I SUN L 1 I PSW SYSCON BUSCON 0 i BUSCON 1 ADDRSEL 1 d BUSCON 2 ADDRSEL 2 BUSCON 3 ADDRSEL 3 BUSCON 4 ADDRSEL 4 Data Page Ptr 1 Code Seg Ptr MCB02147 Figure 4 1 CPU Block Diagram Semiconductor Group 4 1 Version 1 0 11 97 SIEMENS The Central Processing Unit CPU C164Cl The on chip peripheral units of the C164Cl work nearly independent of the CPU with a separate clock generator Data and control information is interchanged between the CPU and these peripherals via Special Function Registers SFRs Whenever peripherals need a non deterministic CPU action an on chip Interrupt Controller compares all pending peripheral service requests against each other and prioritizes one of them If the priority of the current CPU operation is lower than the priority of the selected peripheral request an interrupt will occur Basically there are two types of interrupt processing Standard interrupt processing forces the CPU to save the current program status and the return address on the stack before branching to the interrupt vector jump table PEC interrupt processing steals just one machine cycle from the current CPU activity to perf
215. e Mode Each of the 3 capture compare channels can individually be programmed for capture mode via bitfields CMSELx in register CC6MSEL In capture mode the contents of timer T12 are copied to the channel s compare register CC6x upon a selectable transition rising falling or both at the associated pin CC6x Capture mode can be enabled in edge aligned mode as well as in center aligned mode Interrupts may be generated selectively at each transition of the capture input signal Pins CC6x used as inputs in capture mode are sampled every CPU clock period When evaluating a series of capture events it must be respected that every capture event overwrites the previous value in the respective register CC6x The control software must be designed to retrieve the capture values early enough Semiconductor Group 17 11 Version 1 0 11 97 SIEMENS The Capture Compare Unit CAPCOM6 C164Cl 17 7 Combined Multi Channel Modes When operating in a combined multi channel mode the output signals CC6x and COUT6x are controlled not only by the compare timers but combined with additional conditions Multi channel modes are selected via register CC6MCON In these modes a predefined signal pattern sequence is driven to the output lines Multi phase modes allow the effective generation of output signal patterns eg for 4 6 phase unipolar drives The phase sequence can either be controlled automatically by T12 overflows or under software control Block Commu
216. e PEC transfer counter allows to service a specified number of requests by the respective PEC channel and then when COUNT reaches 00p activate the interrupt service routine which is associated with the priority level After each PEC transfer the COUNT field is decremented and the request flag is cleared to indicate that the request has been serviced Continuous transfers are selected by the value FFy in bit field COUNT In this case COUNT is not modified and the respective PEC channel services any request until it is disabled again When COUNT is decremented from 01 to 00y after a transfer the request flag is not cleared which generates another request from the same source When COUNT already contains the value 004 the respective PEC channel remains idle and the associated interrupt service routine is activated instead This allows to choose if a level 15 or 14 request is to be serviced by the PEC or by the interrupt service routine Note PEC transfers are only executed if their priority level is higher than the CPU level ie only PEC channels 7 4 are processed while the CPU executes on level 14 All interrupt request sources that are enabled and programmed for PEC service should use different channels Otherwise only one transfer will be performed for all simultaneous requests When COUNT is decremented to 004 and the CPU is to be interrupted an incorrect interrupt vector will be generated Semiconductor Group Version 1 0 11 97 S
217. e State When the external bus interface is enabled but no external access is currently executed the EBC is idle As long as only internal resources from an architecture point of view like IRAM GPRs or SFRs etc are used the external bus interface does not change see table below Accesses to on chip X Peripherals are also controlled by the EBC However even though an X Peripheral appears like an external peripheral to the controller the respective accesses do not generate valid external bus cycles Due to timing constraints address and write data of an XBUS cycle are reflected on the external bus interface see table below The address mentioned above includes Port 4 BHE and ALE which also pulses for an XBUS cycle The external CS signals are driven inactive high because the EBC switches to an internal XCS signal The external control signals RD and WR or WRL WRH if enabled remain inactive high Status of the external bus interface during EBC idle state Pins Internal accesses only XBUS accesses PORTO Tristated floating Tristated floating for read accesses XBUS write data for write accesses Port 4 Last used external segment address Last used XBUS segment address on selected pins on selected pins Active external CS signal Inactive high for selected CS signals corresponding to last used address BHE Level corresponding to last external Level corresponding to last XBUS access access
218. e XBUS interface and for further support Semiconductor Group 9 22 Version 1 0 11 97 SIEM ENS The General Purpose Timer Unit C164Cl 10 The General Purpose Timer Unit The General Purpose Timer Unit GPT1 represents a very flexible multifunctional timer structure which may be used for timing event counting pulse width measurement pulse generation frequency multiplication and other purposes Block GPT1 contains 3 timers counters with a maximum resolution of 16 TCL Each timer may operate independently in a number of different modes such as gated timer or counter mode or may be concatenated with another timer of the same block The auxiliary timers of GPT1 may optionally be configured as reload or capture registers for the core timer GPT1 has alternate input output functions and specific interrupts associated with it Timer Block GPT1 From a programmer s point of view the GPT1 block is composed of a set of SFRs as summarized below Those portions of port and direction registers which are used for alternate functions by the GPT1 block are shaded Ports amp Direction Control Data Registers Control Registers Interrupt Control Alternate Functions T T2IN P5 6 T2EUD P5 4 TSIN P3 6 TSEUD P3 4 T4IN P5 7 T4EUD P5 5 ODP3 Port 3 Open Drain Control Register T2 GPT1 Timer 2 Register DP3 Port 3 Direction Control Register T3 GPT1 Timer 3 Register P3 Port 3 Data Register T4 GPT1 Timer 4 Register T2CON GPT1 Timer 2 Co
219. e contents of the internal RAM There are two levels of protection against unintentionally entering Power Down mode First the PWRDN Power Down instruction which is used to enter this mode has been implemented as a protected 32 bit instruction Second this instruction is effective only if the NMI Non Maskable Interrupt pin is externally pulled low while the PWRDN instruction is executed The microcontroller will enter Power Down mode after the PWRDN instruction has completed This feature can be used in conjunction with an external power failure signal which pulls the NMI pin low when a power failure is imminent The microcontroller will enter the NMI trap routine which can save the internal state into RAM After the internal state has been saved the trap routine may then execute the PWRDN instruction If the NMI pin is still low at this time Power Down mode will be entered otherwise program execution continues The initialization routine executed upon reset can check the reset identification flags in register WDTCON to determine whether the controller was initially switched on or whether it was properly restarted from Power Down mode The realtime clock RTC can be kept running in Power Down mode in order to maintain a valid system time as long as the supply voltage is applied This enables a system to determine the current time and the duration of the period while it was down by comparing the current time with a timestamp stored when P
220. e different structures due to the way the direction of the pin is switched and depending on whether the pin is accessible by the user software or not in the alternate function mode All port lines that are not used for these alternate functions may be used as general purpose IO lines When using port pins for general purpose output the initial output value should be written to the port latch prior to enabling the output drivers in order to avoid undesired transitions on the output pins This applies to single pins as well as to pin groups see examples below OUTPUT ENABLE SINGLE PIN BSET P4 0 Initial output level is high BSET DP4 0 Switch on the output driver OUTPUT ENABLE PIN GROUP BFLDL P4 05H 05H Initial output level is high BFLDL DP4 05H 05H Switch on the output drivers Note When using several BSET pairs to control more pins of one port these pairs must be separated by instructions which do not reference the respective port see Particular Pipeline Effects in chapter The Central Processing Unit Each of these ports and the alternate input and output functions are described in detail in the following subsections Semiconductor Group 7 5 Version 1 0 11 97 SIEMENS Parallel Ports C164CI 7 1 PORTO The two 8 bit ports POH and POL represent the higher and lower part of PORTO respectively Both halfs of PORTO can be written eg via a PEC transfer without effecting the other half If this port
221. e following behaviour differences must be observed when using the bidirectional reset feature in an application e Bit BDRSTEN in register SYSCON cannot be changed after EINIT e After a reset bit BDRSTEN is cleared e Bit WDTR will always be 0 even after a watchdog timer reset e The PORTO configuration is treated like on a hardware reset Especially the bootstrap loader may be activated when POL 4 is low e Pin RSTIN may only be connected to external reset devices with an open drain output driver The Reset Output RSTOUT provides a special reset signal for external circuitry RSTOUT is activated at the beginning of the reset sequence triggered via RSTIN a watchdog timer overflow or by the SRST instruction RSTOUT remains active low until the EINIT instruction is executed This allows to initialize the controller before the external circuitry is activated Note During emulation mode pin RSTOUT is used as an input and therefore must be driven by the external circuitry The Power Supply pins for the Analog Digital Converter VAREF and VAGND provide a separate power supply for the on chip ADC This reduces the noise that is coupled to the analog input signals from the digital logic sections and so improves the stability of the conversion results when VAREF and VAGND are properly discoupled from VDD and VSS The Power Supply pins VDD and VSS provide the power supply for the digital logic of the C164Cl The respective VDD VSS pairs sho
222. e interrupt request flag is set in cycle 1 fetching of instruction N The indicated source wins the prioritization round during cycle 2 In cycle 3 a PEC transfer instruction is injected into the decode stage of the pipeline suspending instruction N 1 and clearing the source s interrupt request flag to 0 Cycle 4 completes the injected PEC transfer and resumes the execution of instruction Nc 1 All instructions that entered the pipeline after setting of the interrupt request flag N 1 N 2 will be executed after the PEC data transfer Note When instruction N reads any of the PEC control registers PECC7 PECCO while a PEC request wins the current round of prioritization this round is repeated and the PEC data transfer is started one cycle later The minimum PEC response time is 3 states 6 TCL This requires program execution from the internal code memory no external operand read requests and setting the interrupt request flag during the last state of an instruction cycle When the interrupt request flag is set during the first state of an instruction cycle the minimum PEC response time under these conditions is 4 state times 8 TCL Semiconductor Group 5 18 Version 1 0 11 97 SIEMENS Interrupt and Trap Functions C164CI The PEC response time is increased by all delays of the instructions in the pipeline that are executed before starting the data transfer including N When internal hold conditions between instruction pa
223. e last entry in the table must be greater than the largest possible target MOV RO BASE Move table base into RO LOOP CMP R1 RO Compare target to table entry JMPR cc NET LOOP Test whether target is not found AND the end of table has not been reached Note The last entry in the table must be equal to the lowest signed integer 8000p 22 5 Peripheral Control and Interface All communication between peripherals and the CPU is performed either by PEC transfers to and from internal memory or by explicitly addressing the SFRs associated with the specific peripherals After resetting the C164Cl all peripherals except the watchdog timer are disabled and initialized to default values A desired configuration of a specific peripheral is programmed using MOV instructions of either constants or memory values to specific SFRs Specific control flags may also be altered via bit instructions Once in operation the peripheral operates autonomously until an end condition is reached at which time it requests a PEC transfer or requests CPU servicing through an interrupt routine Information may also be polled from peripherals through read accesses to SFRs or bit operations including branch tests on specific control bits in SFRs To ensure proper allocation of peripherals among multiple tasks a portion of the internal memory has been made bit addressable to allow user semaphores Instructions have also been provided to lock out tasks via sof
224. e memory segmentation data memory paging and accesses to the General Purpose Registers and the System Stack The access mechanism for these SFRs in the CPU core is identical to the access mechanism for any other SFR Since all SFRs can simply be controlled by means of any instruction which is capable of addressing the SFR memory space a lot of flexibility has been gained without the need to create a set of system specific instructions Note however that there are user access restrictions for some of the CPU core SFRs to ensure proper processor operations The instruction pointer IP and code segment pointer CSP cannot be accessed directly at all They can only be changed indirectly via branch instructions The PSW SP and MDC registers can be modified not only explicitly by the programmer but also implicitly by the CPU during normal instruction processing Note that any explicit write request via software to an SFR supersedes a simultaneous modification by hardware of the same register Note Any write operation to a single byte of an SFR clears the non addressed complementary byte within the specified SFR Non implemented reserved SFR bits cannot be modified and will always supply a read value of 0 The System Configuration Register SYSCON This bit addressable register provides general system configuration and control functions The reset value for register SYSCON depends on the state of the PORTO pins during reset see hardwa
225. e on chip peripheral modules independently reducing the amount of clocked circuitry including the respective clock drivers 21 1 Idle Mode The power consumption of the C164Cl microcontroller can be decreased by entering Idle mode In this mode all enabled peripherals including the watchdog timer continue to operate normally only the CPU operation is halted and the on chip memory modules are disabled Note Peripherals that have been disabled via software also remain disabled after entering Idle mode of course Idle mode is entered after the IDLE instruction has been executed and the instruction before the IDLE instruction has been completed To prevent unintentional entry into Idle mode the IDLE instruction has been implemented as a protected 32 bit instruction Idle mode is terminated by interrupt requests from any enabled interrupt source whose individual Interrupt Enable flag was set before the Idle mode was entered regardless of bit IEN For a request selected for CPU interrupt service the associated interrupt service routine is entered if the priority level of the requesting source is higher than the current CPU priority and the interrupt system is globally enabled After the RETI Return from Interrupt instruction of the interrupt service routine is executed the CPU continues executing the program with the instruction following the IDLE instruction Otherwise if the interrupt request cannot be serviced because of a too low priority
226. e second for the high byte of the word During write cycles PORTO outputs the data byte or word after outputting the address Alternate Function a b POH 7 A15 AD15 POH 6 A14 AD14 POH 5 A13 AD13 POH POH 4 A12 AD12 POH 3 A11 AD11 POH 2 A10 AD10 POH 1 A9 AD9 POH O A8 AD8 PORN POL 7 AD7 AD7 POL 6 AD6 AD6 POL 5 AD5 AD5 POL 4 AD4 AD4 POL POL 3 AD3 AD3 POL 2 AD2 AD2 POL 1 AD1 AD1 POL O ADO ADO General Purpose 8 bit 16 bit Input Output MUX Bus MUX Bus Figure 7 4 PORTO IO and Alternate Functions Semiconductor Group 7 7 Version 1 0 11 97 SIEMENS Parallel Ports C164CI When an external bus mode is enabled the direction of the port pin and the loading of data into the port output latch are controlled by the bus controller hardware The input of the port output latch is disconnected from the internal bus and is switched to the line labeled Alternate Data Output via a multiplexer The alternate data can be the 16 bit intrasegment address or the 8 16 bit data information The incoming data on PORTO is read on the line Alternate Data Input While an external bus mode is enabled the user software should not write to the port output latch otherwise unpredictable results may occur When the external bus modes are disabled the contents of the direction register last written by the user becomes active The figure below shows the structure of a PORTO pin Write DPOH y DPOL y Alternate
227. e segment pointer CSP for code fetches and via an explicit segment number for data accesses overriding the standard DPP scheme During code fetching segments are not changed automatically but rather must be switched explicitly The instructions JMPS CALLS and RETS will do this In larger sequential programs make sure that the highest used code location of a segment contains an unconditional branch instruction to the respective following segment to prevent the prefetcher from trying to leave the current segment Data Pages are contiguous blocks of 16 KByte each They are referenced via the data page pointers DPP3 0 and via an explicit data page number for data accesses overriding the standard DPP scheme Each DPP register can select one of the possible 1024 data pages The DPP register that is used for the current access is selected via the two upper bits of the 16 bit data address Subsequent 16 bit data addresses that cross the 16 KByte data page boundaries therefore will use different data page pointers while the physical locations need not be subsequent within memory Semiconductor Group 3 10 Version 1 0 11 97 SIEMENS Memory Organization C164Cl 3 5 OTP Memory Programming During normal operation the One Time Programmable OTP memory appears like a standard ROM In the special OTP programming modes however the OTP memory can be written ie programmed via its special programming interface Programming is executed in units of 16 bi
228. e supported In Edge Aligned Mode the compare timer counts up starting at 00004 Upon reaching the period value stored in register TxP the timer is cleared and repeats counting up At this time also the output signals are switched to their passive state Edge aligned mode is supported by both compare timers T12 and T13 In Center Aligned Mode the compare timer T12 counts up starting at 0000 Upon reaching the period value stored in register T12P the count direction is reversed and the timer counts down The output signals are switched to their active passive state upon a match with the compare value while counting up down Center aligned mode is only supported by compare timer T12 Semiconductor Group 17 2 Version 1 0 11 97 SIEMENS The Capture Compare Unit CAPCOM6 C164Cl The compare timers T12 and T13 are free running timers which are clocked with a programmable frequency of fopy to fepy 128 The respective output signals are changed if appropriate when the timer reaches the programmed compare value For switching the output signals COUT60 COUT62 the timer contents plus the offset value are compared against the compare value Timer T12 can operate in edge aligned or in center aligned PWM mode see figure below with or without a constant edge delay a or b in the figure Timer T13 can operate in edge aligned mode without edge delay Compare Timer 1 Operating Mode 0 a Standard PWM Edge Aligned Period Value C
229. ed Mode Semiconductor Group 17 8 Version 1 0 11 97 SIEMENS The Capture Compare Unit CAPCOM6 C164Cl Compare Timer Resolution and Period Range as Function of Internal Clock 2 fepy 20 MHz Internal Compare Timer Output Signal Period Range Txmin T12max T13max Clock Resolution Edge Aligned Mode Center Aligned Mode fcpu 50 ns 100 ns 3 28ms 51 2us 200ns 6 55ms 102 4 us fopy 2 100 ns 200ns 6 55ms 102 4us 400ns 13 11 ms 204 8 us fcpu 4 200 ns 400ns 13 11 ms 204 8 us 800 ns 26 21 ms 409 6 us fcpu 8 400 ns 800ns 26 21 ms 409 6 us 1 6 us 52 43ms 819 2 us fcpu 16 800 ns 16us 52 483ms 819 2us 3 2us 104 86 ms 1 64 ms fcpu 32 1 6 us 3 2us 104 86 ms 1 64 ms 6 4ys 209 72 ms 3 28 ms fcpu 64 3 2 Us 6 4us 209 72 ms 3 28 ms 12 8 us 419 43 ms 6 55 ms fcpu 128 6 4 ys 12 8 us 419 43 ms 6 55 ms 25 6 us 838 86 ms 13 1 ms Compare timer Tx period and duty cycle values can be calculated using the formulas below In these formulas the following abbreviations are used pv period value stored in register TxP Ov Offset value stored in register T12OF cv compare value stored in register CC6x or CMP13 Note For compare timer T13 only the output signal COUT63 in edge aligned mode is available Edge Aligned Mode Period value pv 1 Duty cycle of CC6x outputs 100 pv 1 cv ov i Duty cycle of COUT6x ou
230. ed in the C164Cl BCD calculations are performed by converting BCD data to binary data performing the desired calculations using standard data types and converting the result back to BCD data Due to the enhanced performance of division instructions binary data is quickly converted to BCD data through division by 10p Conversion from BCD data to binary data is enhanced by multiple bit shift instructions This provides similar performance compared to instructions directly supporting BCD data types while no additional hardware is required Semiconductor Group 22 3 Version 1 0 11 97 SIEMENS System Programming C164CI 22 1 Stack Operations The C164Cl supports two types of stacks The system stack is used implicitly by the controller and is located in the internal RAM The user stack provides stack access to the user in either the internal or external memory Both stack types grow from high memory addresses to low memory addresses Internal System Stack A system stack is provided to store return vectors segment pointers and processor status for procedures and interrupt routines A system register SP points to the top of the stack This pointer is decremented when data is pushed onto the stack and incremented when data is popped The internal system stack can also be used to temporarily store data or pass it between subroutines or tasks Instructions are provided to push or pop registers on from the system stack However in most cases t
231. ed out last If a shift count of zero is specified the C flag will be cleared The C flag is also cleared for a prioritize ALU operation because a 1 is never shifted out of the MSB during the normalization of an operand For Boolean bit operations with only one operand the C flag is always cleared For Boolean bit operations with two operands the C flag represents the logical ANDing of the two specified bits e V Flag For addition subtraction and 2 s complementation the V flag is always set to 1 if the result overflows the maximum range of signed numbers which are representable by either 16 bits for word operations 8000 to 7FFF or by 8 bits for byte operations 80 to 7F otherwise the V flag is cleared Note that the result of an integer addition integer subtraction or 2 s complement is not valid if the V flag indicates an arithmetic overflow For multiplication and division the V flag is set to 1 if the result cannot be represented in a word data type otherwise it is cleared Note that a division by zero will always cause an overflow In contrast to the result of a division the result of a multiplication is valid regardless of whether the V flag is set to 1 or not Since logical ALU operations cannot produce an invalid result the V flag is cleared by these operations The V flag is also used as Sticky Bit for rotate right and shift right operations With only using the C flag a rounding error caused by a
232. eference voltages Varer and Vacnp are fixed The separate supply for the ADC reduces the interference with other digital signals The sample time as well as the conversion time is programmable so the ADC can be adjusted to the internal resistances of the analog sources and or the analog reference voltage supply Conversion ADGIR Interrupt Control ADEIR Requests Result Reg ADDAT 10 Bit Converter Result Reg ADDAT2 MCB02240 Figure 18 2 Analog Digital Converter Block Diagram Semiconductor Group 18 2 Version 1 0 10 97 SIEMENS The Analog Digital Converter C164CI 18 1 Mode Selection and Operation The analog input channels ANO AN7 are alternate functions of Port 5 which is an 8 bit input only port The Port 5 lines may either be used as analog or digital inputs For pins that shall be used as analog inputs it is recommended to disable the digital input stage via register PSDIDIS This avoids undesired cross currents and switching noise while the analog input signal level is between V and Vin The functions of the A D converter are controlled by the bit addressable A D Converter Control Register ADCON Its bitfields specify the analog channel to be acted upon the conversion mode and also reflect the status of the converter ADCON FFAO DOp SFR Reset Value 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw r rw rw rw Bit Function ADCH ADC Analog Cha
233. efore the last bit of a frame is transmitted ie before the first or the second stop bit is shifted out of the transmit shift register The transmitter output pin TXDO P3 10 must be configured for alternate data output ie P3 10 1 and DP3 10 1 Semiconductor Group 11 6 Version 1 0 11 97 Sl EM ENS The Asynchronous Synchronous Serial Interface C164CI Asynchronous reception is initiated by a falling edge 1 to 0 transition on pin RXDO provided that bits SOR and SOREN are set The receive data input pin RXDO is sampled at 16 times the rate of the selected baud rate A majority decision of the 7th 8th and 9th sample determines the effective bit value This avoids erroneous results that may be caused by noise If the detected value is not a 0 when the start bit is sampled the receive circuit is reset and waits for the next 1 to 0 transition at pin RXDO If the start bit proves valid the receive circuit continues sampling and shifts the incoming data frame into the receive shift register When the last stop bit has been received the content of the receive shift register is transferred to the receive data buffer register SORBUF Simultaneously the receive interrupt request flag SORIR is set after the 9th sample in the last stop bit time slot as programmed regardless whether valid stop bits have been received or not The receive circuit then waits for the next start bit 1 to 0 transition at the receive data input pin The rec
234. egister 26 Interrupt Control Register 0000 CC271lC b F176 E BB CAPCOM Register 27 Interrupt Control Register 0000 T7IC b F17A4 E BDy CAPCOM Timer 7 Interrupt Control Register 00004 T8IC b F17Cu4 E BEy CAPCOM Timer 8 Interrupt Control Register 00004 CC6IC b F17E E BFy CAPCOM 6 Interrupt Control Register 00004 XPOIC b F186 E C3 X Peripheral 0 Interrupt Control Register 00004 CC6EIC b F1884 E C4 CAPCOM 6 Emergency Interrupt Control Reg 0000 T121C b F190 E C8 CAPCOM 6 Timer 12 Interrupt Control Register 0000 T13IC b F1984 E CCy CAPCOM 6 Timer 13 Interrupt Control Register 00004 SOTBIC b F19C EL CEQ Serial Channel 0 Transmit Buffer Interrupt Control 0000 Register XP3IC b F19E E CFy X Peripheral 3 Interrupt Control Register 00004 EXICON b F1C0 E E0 External Interrupt Control Register 00004 PICON F1iC4 E E2 Port Input Threshold Control Register 00004 ODP3 b F1C6 E E3y Port 3 Open Drain Control Register 0000 SYSCON2 b F1D0 E E8 CPU System Configuration Register 2 0000 SYSCON3 b F1D4 E EA CPU System Configuration Register 3 0000 Semiconductor Group 23 11 Version 1 0 11 97 SIEMENS The Register Set C164Cl Name Physical 8 Bit Description Reset Address Address Value ODP8 b F1D6 E EBy Port 8 Open Drain Control Register 001 EXISEL b FIDA E ED External Interrupt Source Select Register 00004 ISNC b F1DE
235. egister ADEIC will be set either if a conversion result overwrites a previous value in register ADDAT error interrupt in standard mode or if the result of an injected conversion has been stored into ADDAT2 end of injected conversion interrupt This interrupt request may be used to cause an interrupt to vector ADEINT or it may trigger a PEC data transfer ADCIC FF98 CC SFR Reset Value 00 7 6 5 4 3 2 1 0 ADC ADC IE ILVL GLVL rw rw rw rw ADEIC FF9A CDy SFR Reset Value 004 6 rw rw Note Please refer to the general Interrupt Control Register description for an explanation of the control fields Semiconductor Group 18 11 Version 1 0 10 97 SIEMENS The On Chip CAN Interface C164CI 19 The On Chip CAN Interface The Controller Area Network CAN bus with its associated protocol allows communication between a number of stations which are connected to this bus with high efficiency Efficiency in this context means Transfer speed Data rates of up to 1 Mbit sec can be achieved Data integrity The CAN protocol provides several means for error checking Host processor unloading The controller here handles most of the tasks autonomously Flexible and powerful message passing The extended CAN protocol is supported The integrated CAN Module handles the completely autonomous transmission and reception of CAN frames in accordance with the CAN specification V2 0 part B active
236. egister contents after reset 0 1 defined value X undefined U unchanged undefined X after power up hwbit Bits that are set cleared by hardware are marked with a shaded access box Semiconductor Group 23 1 Version 1 0 11 97 SIEMENS The Register Set C164CI 23 4 CPU General Purpose Registers GPRs The GPRs form the register bank that the CPU works with This register bank may be located anywhere within the internal RAM via the Context Pointer CP Due to the addressing mechanism GPR banks can only reside within the internal RAM All GPRs are bit addressable Name Physical 8 Bit Description Reset Address Address Value RO CP 0 FOy CPU General Purpose Word Register RO UUUU R1 CP 2 Fiy CPU General Purpose Word Register R1 UUUU R2 CP 4 F2y CPU General Purpose Word Register R2 UUUU R3 CP 6 F3y CPU General Purpose Word Register R3 UUUU R4 CP 8 F4y CPU General Purpose Word Register R4 UUUU R5 CP 10 F54 CPU General Purpose Word Register R5 UUUU R6 CP 12 F6 CPU General Purpose Word Register R6 UUUU R7 CP 14 F74 CPU General Purpose Word Register R7 UUUU R8 CP 16 F84 CPU General Purpose Word Register R8 UUUU R9 CP 18 F94 CPU General Purpose Word Register R9 UUUU R10 CP 20 FAH CPU General Purpose Word Register R10 UUUU R11 CP 22 FBy CPU General Purpose Word Register R11 UUU
237. egisters which are used for controlling and monitoring functions of the different on chip units Unused E SFR addresses are reserved for future members of the C164Cl family with enhanced functionality An optional internal ROM or OTP memory provides for both code and constant data storage This memory area is connected to the CPU via a 32 bit wide bus Thus an entire double word instruction can be fetched in just one machine cycle The ROM will be mask programmed in the factory while the OTP memory can also be programmed within the application Program execution from on chip program memory is the fastest of all possible alternatives External Bus Interface In order to meet the needs of designs where more memory is required than is provided on chip up to 4 MBytes of external RAM and or ROM can be connected to the microcontroller via its external bus interface The integrated External Bus Controller EBC allows to access external memory and or peripheral resources in a very flexible way For up to five address areas the data bus width 8 bit 16 bit and even the length of a bus cycle waitstates signal delays can be selected independently This allows to access a variety of memory and peripheral components directly and with maximum efficiency If the device does not run in Single Chip Mode where no external memory is required the EBC can control external accesses in one of the following external access modes e 16 18 20 22 bit Addresses
238. egment 0 data pages 3 0 This is the fastest possible interrupt response and in many cases is sufficient to service the respective peripheral request eg serial channels etc Each channel is controlled by a dedicated PEC Channel Counter Control register PECCx and a pair of pointers for source SRCPx and destination DSTPx of the data transfer The PECC registers control the action that is performed by the respective PEC channel PECCx FECy 624 see table SFR Reset Value 00004 15 14 11 7 6 5 4 3 2 1 0 13 12 10 9 8 rw rw rw Bit Function COUNT PEC Transfer Count Counts PEC transfers and influences the channel s action see table below BWT Byte Word Transfer Selection 0 Transfer a Word 1 Transfer a Byte INC Increment Control Modification of SRCPx or DSTPx 0 0 Pointers are not modified 0 1 Increment DSTPx by 1 or 2 BWT 1 0 Increment SRCPx by 1 or 2 BWT 1 1 Reserved Do not use this combination changed to 10 by hardware PEC Control Register Addresses Register Address Reg Space Register Address Reg Space PECCO FECO 60 SFR PECC4 FEC8 64 SFR PECC1 FEC24 61 SFR PECC5 FECA 65 SFR PECC2 FEC4 62 SFR PECC6 FECC 664 SFR PECC3 FEC6p 634 SFR PECC7 FECE 67 SFR Byte Word Transfer bit BWT controls if a byte or a word is moved during a PEC service cycle This selection controls the transferred data si
239. eiver input pin RXDO P3 11 must be configured for input ie DP3 11 0 Asynchronous reception is stopped by clearing bit SOREN A currently received frame is completed including the generation of the receive interrupt request and an error interrupt request if appropriate Start bits that follow this frame will not be recognized Note In wake up mode received frames are only transferred to the receive buffer register if the 9th bit the wake up bit is 1 If this bit is 0 no receive interrupt request will be activated and no data will be transferred Semiconductor Group 11 7 Version 1 0 11 97 Sl EM ENS The Asynchronous Synchronous Serial Interface C164CI 11 2 Synchronous Operation Synchronous mode supports half duplex communication basically for simple IO expansion via shift registers Data is transmitted and received via pin RXDO P3 11 while pin TXDO P3 10 outputs the shift clock These signals are alternate functions of Port 3 pins Synchronous mode is selected with SOM 000p 8 data bits are transmitted or received synchronous to a shift clock generated by the internal baud rate generator The shift clock is only active as long as data bits are transmitted or received Reload Register aces ce pons SOR SOM 000B SOOE SORIR Receive Int Request Serial Port Control SOTIR Transmit Int TXDO P3 10 gu Shift Clock Error Int POS Request Receive Dp hH Mm P MUX Receive Shift Tr
240. enabled in bootstrap loader mode the programming routine s can be loaded via the serial interface This allows in system programming of an empty OTP module Semiconductor Group 3 12 Version 1 0 11 97 SIEMENS Memory Organization C164Cl External Host Mode Programming In this mode the signals to control a programming cycle are generated by an external host using the C164Cl s bus interface The external host provides the data to be programmed The C164CI itself is switched off and its OTP module can be accessed like standalone memory In external host mode the following port pins represent the interface to the C164Cl s OTP module External Host Mode Interface Signals Signal Pin Description ADDR P1H 7 P1L 1 Physical OTP word address address line AO is not evaluated DATA POH 7 POL O Word to be programmed or verified RD RD Verify cycle control WR WR Programming cycle control CE P3 9 OTP enable signal RSEL P3 8 Control signal RSEL used for protection lock control must be 0 for OTP programming cycles RSTOUT RSTOUT Must be held high pullup resistor Vpp EA Vpp External programming voltage The access cycles generated by the external host must fulfill the timing requirements shown in the timing diagrams above Note EHM is a varity of the emulation mode where pin P0 15 POL 7 is inverted during the reset configuration This influences the selected clock generation mode For EHM operation
241. ence the different groups of pins of the C164Cl are activated in different ways depending on their function Bus and control signals are activated immediately after the reset sequence according to the configuration latched from PORTO so either external accesses can takes place or the external control signals are inactive The general purpose IO pins remain in input mode high impedance until reprogrammed via software see figure below The RSTOUT pin remains active low until the end of the initialization routine see description Yj 6 YL Li 2 RSTIN pee RD WR j ALE EAS Bus 4 7 oh CC f RSTOUT 2 3 f 5 t Q Internal Reset Condition 39 Initialization 2 GY 3 RSTIN Internal Reset Condition Initialization MCS02258 When the internal reset condition is extended by RSTIN or until the PLL has locked the activation of the output signals is delayed until the end of the internal reset condition 1 Current bus cycle is completed or aborted 2 Switches asynchronously with RSTIN synchronously upon software or watchdog reset 3 The reset condition ends here The C164CI starts program execution 4 Activation of the IO pins is controlled by software 5 Execution of the EINIT instruction 6 The shaded area designates the internal reset sequence which starts after synchronization of RSTIN
242. ent in all 3 timers of block GPT1 are controlled in the same bit positions and in the same manner in each of the specific control registers T2CON FF40 AOp SFR Reset Value 0000 15 14 13 12 1i 10 9 8 7 6 5 4 3 2 1 0 T2 rw rw rw rw rw T4CON FF44 A24 SFR Reset Value 00004 15 14 13 12 1i 10 9 8 7 6 5 4 3 2 1 0 T4 m rw rw rw rw rw Bit Function Txl Timer x Input Selection Depends on the Operating Mode see respective sections TxM Timer x Mode Control Basic Operating Mode 000 Timer Mode 001 Counter Mode 010 Gated Timer with Gate active low 011 Gated Timer with Gate active high 100 Reload Mode 101 Capture Mode 110 Incremental Interface Mode Ts Reserved Do not use this combination TxR Timer x Run Bit TxR 2 0 Timer Counter x stops TxR 2 1 Timer Counter x runs TxUD Timer x Up Down Control TxUDE Timer x External Up Down Enable For the effects of bits TXUD and TxUDE refer to the direction table see T3 section Semiconductor Group 10 11 Version 1 0 11 97 SIEM ENS The General Purpose Timer Unit C164Cl Note The auxiliary timers have no output toggle latch and no alternate output function Count Direction Control for Auxiliary Timers The count direction of the auxiliary timers can be controlled in the same way as for the core timer T3 The description and the table apply accordingly Timers T2 and T4 in Timer Mode or Gated Timer Mode Whe
243. er C164Cl Loading the Startup Code After sending the identification byte the BSL enters a loop to receive 32 bytes via ASCO These bytes are stored sequentially into locations 00 FA40 through 00 FASF of the internal RAM So up to 16 instructions may be placed into the RAM area To execute the loaded code the BSL then jumps to location 00 FA40y ie the first loaded instruction The bootstrap loading sequence is now terminated the C164Cl remains in BSL mode however Most probably the initially loaded routine will load additional code or data as an average application is likely to require substantially more than 16 instructions This second receive loop may directly use the pre initialized interface ASCO to receive data and store it to arbitrary user defined locations This second level of loaded code may be the final application code It may also be another more sophisticated loader routine that adds a transmission protocol to enhance the integrity of the loaded code or data It may also contain a code sequence to change the system configuration and enable the bus interface to store the received data into external memory This process may go through several iterations or may directly execute the final application In all cases the C164CI will still run in BSL mode ie with the watchdog timer disabled and limited access to the internal code memory All code fetches from the internal ROM area 00 0000 00 7FFF or 01 0000 01 7FFF
244. er In this case the number of possible segment address lines is reduced The table below summarizes the alternate functions of Port 4 depending on the number of selected segment address lines coded via bitfield SALSEL Semiconductor Group 7 17 Version 1 0 11 97 Parallel Ports C164CI SIEMENS Port 4 Std Function Altern Function Altern Function Altern Function Pin SALSEL 01 64 KB SALSEL 11 256KB SALSEL 00 1MB SALSEL 10 4MB P4 0 Gen p IO or CS3 Seg Address A16 Seg Address A16 Seg Address A16 P4 1 Gen p IO or CS2 Seg Address A17 Seg Address A17 Seg Address A17 P4 2 Gen p IO or CS1 Gen p IO or CS1 Seg Address A18 Seg Address A18 P4 3 Gen p IO or CSO Gen p IO or CS0 Seg Address A19 Seg Address A19 P4 5 Gen p lOorCAN Gen p lOor CAN Gen p lOorCAN Seg Address A20 P4 6 Gen p IO or CAN Gen p IO or CAN Gen p IO or CAN Seg Address A21 Alternate Function a b Port 4 P4 6 A21 CAN TxD P4 5 A20 CAN RxD P4 3 A19 CS0 A19 P4 2 A18 CS1 A18 P4 1 A17 CS2 A17 P4 0 A16 CS3 A16 General Purpose Input Output Figure 7 11 Port 4 IO and Alternate Functions Note Port 4 pins that are neither used for segment address output nor for chip select output or CAN interface may be used for general purpose IO The pins which are used for chip select output are defined via bitfield CSSEL see register RPOH If more than one function is selected for a
245. er pair operate on the pin associated with the bank 1 register pins CC161O CC19lO The relationship between the bank 1 and bank 2 register of a pair and the effected output pins for double register compare mode is listed in the table below Register Pairs for Double Register Compare Mode CAPCON Unit Register Pair Associated Output Pin Bank 1 Bank 2 CC16 CC24 CC16lO CC17 CC25 CC171O CC18 CC26 CC18lO CC19 CC27 CC19IO The double register compare mode can be programmed individually for each register pair In order to enable double register mode the respective bank 1 register see table must be programmed to compare mode 1 and the corresponding bank 2 register see table must be programmed to compare mode 0 If the respective bank 1 compare register is disabled or programmed for a mode other than mode 1 the corresponding bank 2 register will operate in compare mode 0 interrupt only mode In the following a bank 2 register programmed to compare mode 0 will be referred to as CCz while the corresponding bank 1 register programmed to compare mode 1 will be referred to as CCx When a match is detected for one of the two registers in a register pair CCx or CCz the associated interrupt request flag CCxIR or CCzIR is set to 1 and pin CCxIO corresponding to bank 1 register CCx is toggled The generated interrupt always corresponds to the register that caused the match Note If a match occurs simu
246. er software has priority Each time a CPU write access to the port output latch occurs the input multiplexer of the port output latch is switched to the line connected to the internal bus The port output latch will receive the value from the internal bus and the hardware triggered change will be lost As all other capture inputs the capture input function of the Port 8 pins can also be used as external interrupt inputs sample rate 16 TCL Port 8 Pin Alternate Function P8 0 CC16lO Capture input compare output channel 16 P8 1 CC171O Capture input compare output channel 17 P8 2 CC18lO Capture input compare output channel 18 P8 3 CC1910 Capture input compare output channel 19 Semiconductor Group 7 24 Version 1 0 11 97 SIEMENS Parallel Ports C164CI Alternate Function Port 8 upp i i 1 i LI i 1 LI 99 co 00 PU General Purpose Input Output CC19lO CC18lO CC171O CC16lO Figure 7 15 Port 8 IO and Alternate Functions Semiconductor Group 7 25 Version 1 0 11 97 SIEMENS Parallel Ports C164CI The pins of Port 8 combine internal bus data and alternate data output before the port latch input Write ODP8 y Open Drain Latch Read ODP8 y Write DP8 y Read DP8 y f0 0535 c5 D Dre c UJ wn Data Output Output Latch Alternate ear Ky Write Port P8 y a Compare Trigger
247. errupt such as enabling disabling level and group priority and interrupt or PEC service see note below As for all other interrupts the interrupt request flag XPOIR in register XPOIC is cleared automatically by hardware when this interrupt is serviced either by standard interrupt or PEC service Note As a rule CAN interrupt requests can be serviced by a PEC channel However because PEC channels only can execute single predefined data transfers there are no conditional PEC transfers PEC service can only be used if the respective request is known to be generated by one specific source and that no other interrupt request will be generated in between In practice this seems to be a rare case Since an interrupt request of the CAN Module can be generated due to different conditions the appropriate CAN interrupt status register must be read in the service routine to determine the cause of the interrupt request The Interrupt Identifier INTID a number in the Interrupt Register indicates the cause of an interrupt When no interrupt is pending the identifier will have the value 00 If the value in INTID is not 00 then there is an interrupt pending If bit IE in the Control Register is set also the interrupt line to the CPU is activated The interrupt line remains active until either INTID gets 00 ie the interrupt requester has been serviced or until IE is reset ie interrupts are disabled The interrupt with the lowest number h
248. errupt request that is to be serviced so the CPU now executes on the new level If a multiplication or division was in progress at the time the interrupt request was acknowledged bit MULIP in register PSW is set to 1 In this case the return location that is saved on the stack is not the next instruction in the instruction flow but rather the multiply or divide instruction itself as this instruction has been interrupted and will be completed after returning from the service routine Semiconductor Group 5 14 Version 1 0 11 97 SIEMENS Interrupt and Trap Functions C164CI High Status of Addresses Interrupted Task T Lr a re 5 j Low Addresses a System Stack before b System Stack after b System Stack after Interrupt Entry Interrupt Entry Interrupt Entry Unsegmented Segmented MCD02226 Figure 5 3 Task Status saved on the System Stack The interrupt request flag of the source that is being serviced is cleared The IP is loaded with the vector associated with the requesting source the CSP is cleared in case of segmentation and the first instruction of the service routine is fetched from the respective vector location which is expected to branch to the service routine itself The data page pointers and the context pointer are not affected When the interrupt service routine is left RETI is executed the status information is popped from the system stack in the reverse order taking into account t
249. ersion 1 0 11 97 SIEMENS Power Management C164Cl 21 Power Management For an increasing number of microcontroller based systems it is an important objective to reduce the power consumption of the system as much as possible A contradictory objective is however to reach a certain level of system performance Besides optimization of design and technology a microcontroller s power consumption can generally be reduced by lowering its operating frequency and or by reducing the circuitry that is clocked The architecture of the C164Cl provides three major means of reducing its power consumption see figure below under software control Reduction of the CPU frequency for Slow Down operation Flexible Clock Gen Management Selection of the active peripheral modules Flexible Peripheral Management Special operating modes to deactivate CPU port drivers and control logic Idle Power Down This enables the application ie the programmer to choose the optimum constellation for each operating condition so the power consumption can be adapted to conditions like maximum performance partial performance intermittend operation or standby Intermittend operation ie alternating phases of high performance and power saving is supported by the cyclic interrupt generation mode of the on chip RTC real time clock No of act Peripherals Figure 21 1 Power Reduction Possibilities Semiconductor Group 21 1 Version 1 0 11 97
250. eset all digital inputs are enabled P5DIDIS FFA4 D2 SFR Reset Value 00004 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 S x x x rw rw rw rw rw rw rw rw Bit Function P5D y Port P5 Bit y Digital Input Control P5D y 0 Digital input stage connected to port line P5 y P5D y 1 Digital input stage disconnected from port line P5 y Semiconductor Group 7 21 Version 1 0 11 97 SIEMENS Parallel Ports C164CI Port 5 pins have a special port structure see figure below first because it is an input only port and second because the analog input channels are directly connected to the pins rather than to the input latches Channel Select Analog Switch to Sample Hold Circuit P5 y ANy Read Port P5 y Clock Y x e Input Read Latch Buffer o D7 p S UJ e c MCB02076 Figure 7 14 Block Diagram of a Port 5 Pin Semiconductor Group 7 22 Version 1 0 11 97 SIEMENS Parallel Ports C164CI 7 6 Port8 If this 4 bit port is used for general purpose IO the direction of each line can be configured via the corresponding direction register DP8 Each port line can be switched into push pull or open drain mode via the open drain control register ODP8 P8 FFD4 EAy SFR Reset Value 004 8 7 6 5 4 3 2 1 0 wo IW w rw Bit Function P8 y Port data register P8 bit y DP8 FFD6 EBy SFR Reset Value 00
251. esses The EXTP extend page instruction allows switching to an arbitrary data page for 1 4 instructions without having to change the current DPPs EXTP R15 1 The override page number is stored in R15 MOV RO R14 The 14 bit page offset is stored in R14 MOV R1 R13 This instruction uses the std DPP scheme The EXTS extend segment instruction allows switching to a 64 KByte segment oriented data access scheme for 1 4 instructions without having to change the current DPPs In this case all 16 bits of the operand address are used as segment offset with the segment taken from the EXTS instruction This greatly simplifies address calculation with continuous data like huge arrays in C EXTS 15 1 The override seg is 15 0F 0000H 0F FFFFH MOV RO R14 The 16 bit segment offset is stored in R14 MOV R1 R13 This instruction uses the std DPP scheme Note Instructions EXTP and EXTS inhibit interrupts the same way as ATOMIC Short Addressing in the Extended SFR ESFR Space The short addressing modes of the C164Cl REG or BITOFF implicitly access the SFR space The additional ESFR space would have to be accessed via long addressing modes MEM or Rw The EXTR extend register instruction redirects accesses in short addressing modes to the ESFR space for 1 4 instructions so the additional registers can be accessed this way too The EXTPR and EXTSR instructions combine the DPP override mechanism with the redire
252. est flags SORIC SOEIC SORIR SOEIR ASCO receive error interrupt request flags SOCON SOREN ASCO receiver enable flag SSCTIC SSCRIC SSCTIR SSCRIR SSC transmit receive interrupt request flags SSCEIC SSCEIR SSC error interrupt request flag SSCCON SSCBSY SSC busy flag SSCCON SSCBE SSCPE SSC error flags SSCCON SSCRE SSCTE SSC error flags ADCIC ADEIC ADCIR ADEIR ADC end of conv overrun intr request flag ADCON ADST ADCRQ ADC start flag injection request flag CC27IC CC24IC CC27IR CC24IR CAPCOM2 interrupt request flags CC19IC CC16IC CC19IR CC16IR CAPCOM2 interrupt request flags TFR TFR 15 14 13 Class A trap flags TFR TFR 7 3 2 1 0 Class B trap flags P8 P8 3 P8 0 All bits of Port 8 XPOIC XP3IC XPOIR XPS3IC X Peripheral interrupt request flags Y 25 protected bits Semiconductor Group 2 16 Version 1 0 11 97 SIEMENS Memory Organization C164Cl 3 Memory Organization The memory space of the C164CI is configured in a Von Neumann architecture This means that code and data are accessed within the same linear address space All of the physically separated memory areas including internal ROM Flash OTP where integrated internal RAM the internal Special Function Register Areas SFRs and ESFRs the address areas for integrated XBUS peripherals and external memory are mapped into one common address space The C164CI provides a total addressable memory space of 16 MBytes This address space is arranged a
253. et after successful transmission of a frame MSGVAL Message Valid Indicates if the corresponding message object is valid or not The CAN controller only operates on valid objects Message objects can be tagged invalid while they are changed or if they are not used at all NEWDAT New Data Indicates if new data has been written into the data portion of this message object by CPU transmit objects or CAN controller receive objects since this bit was last reset or not 2 MSGLST Message Lost This bit applies to receive objects only Indicates that the CAN controller has stored a new message into this object while NEWDAT was still set ie the previously stored message is lost CPUUPD CPU Update This bit applies to transmit objects only Indicates that the corresponding message object may not be transmitted now The CPU sets this bit in order to inhibit the transmission of a message that is currently updated or to control the automatic response to remote requests TXRQ Transmit Request Indicates that the transmission of this message object is requested by the CPU or via a remote frame and is not yet done TXRQ can be disabled by CPUUPD 1 9 RMTPND Remote Pending Used for transmit objects Indicates that the transmission of this message object has been requested by a remote node but the data has not yet been transmitted When RMTPND is set the CAN controller also sets TXRQ RMTPND and TXRQ are cleared when the mess
254. f 1 s in data Semiconductor Group 11 2 Version 1 0 11 97 Sl EM ENS The Asynchronous Synchronous Serial Interface C164CI Bit Function SOBRS Baudrate Selection Bit 0 Divide clock by reload value constant depending on mode 1 Additionally reduce serial clock to 2 3rd SOLB LoopBack Mode Enable Bit 0 Standard transmit receive mode 1 Loopback mode enabled SOR Baudrate Generator Run Bit 0 Baudrate generator disabled ASCO inactive 1 Baudrate generator enabled A transmission is started by writing to the Transmit Buffer register SOTBUF via an instruction or a PEC data transfer Only the number of data bits which is determined by the selected operating mode will actually be transmitted ie bits written to positions 9 through 15 of register SOTBUF are always insignificant After a transmission has been completed the transmit buffer register is cleared to 0000p Data transmission is double buffered so a new character may be written to the transmit buffer register before the transmission of the previous character is complete This allows the transmission of characters back to back without gaps Data reception is enabled by the Receiver Enable Bit SOREN After reception of a character has been completed the received data and if provided by the selected operating mode the received parity bit can be read from the read only Receive Buffer register SORBUF Bits in the upper half of SORBUF which are not v
255. fepy 2 The timer is counting downwards and can be started or stopped through the Baud Rate Generator Run Bit SOR in register SOCON Each underflow of the timer provides one clock pulse to the serial channel The timer is reloaded with the value stored in its 13 bit reload register each time it underflows The resulting clock is again divided according to the operating mode and controlled by the Baudrate Selection Bit SOBRS If SOBRS 1 the clock signal is additionally divided to 2 3rd of its frequency see formulas and table So the baud rate of ASCO is determined by the CPU clock the reload value the value of SOBRS and the operating mode asynchronous or synchronous Register SOBG is the dual function Baud Rate Generator Reload register Reading SOBG returns the content of the timer bits 15 13 return zero while writing to SOBG always updates the reload register bits 15 13 are insiginificant An auto reload of the timer with the content of the reload register is performed each time SOBG is written to However if SOR 0 at the time the write operation to SOBG is performed the timer will not be reloaded until the first instruction cycle after SOR 1 Semiconductor Group 11 10 Version 1 0 11 97 Sl EM ENS The Asynchronous Synchronous Serial Interface C164CI Asynchronous Mode Baud Rates For asynchronous operation the baud rate generator provides a clock with 16 times the rate of the established baud rate Every receive
256. fetch operations IP Reset Value 00004 15 14 13 12 1 10 9 8 7 6 5 4 3 2 0 Bit Function ip Specifies the intra segment offset from where the current instruction is to be fetched IP refers to the current segment lt SEGNR gt Semiconductor Group 4 17 Version 1 0 11 97 SIEMENS The Central Processing Unit CPU C164Cl The Code Segment Pointer CSP This non bit addressable register selects the code segment being used at run time to access instructions The lower 8 bits of register CSP select one of up to 256 segments of 64 KBytes each while the upper 8 bits are reserved for future use CSP FE08 044 SFR Reset Value 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Function SEGNR Segment Number Specifies the code segment from where the current instruction is to be fetched SEGNR is ignored when segmentation is disabled Code memory addresses are generated by directly extending the 16 bit contents of the IP register by the contents of the CSP register as shown in the figure below In case of the segmented memory mode the selected number of segment address bits via bitfield SALSEL of register CSP is output on the respective segment address pins of Port 4 for all external code accesses For non segmented memory mode or Single Chip Mode the content of this register is not significant because all code acccesses are automatically restricted to segment 0 Note The CSP register c
257. flow e If either a positive or a negative transition of T3OTL is selected to trigger a reload the core timer will be reloaded with the contents of the auxiliary timer on every second overflow or underflow Semiconductor Group 10 15 Version 1 0 11 97 SIEM ENS The General Purpose Timer Unit C164Cl e Using this single transition mode for both auxiliary timers allows to perform very flexible pulse width modulation PWM One of the auxiliary timers is programmed to reload the core timer on a positive transition of T3OTL the other is programmed for a reload on a negative transition of T3OTL With this combination the core timer is alternately reloaded from the two auxiliary timers Note Although it is possible it should be avoided to select the same reload trigger event for both auxiliary timers In this case both reload registers would try to load the core timer at the same time If this combination is selected T2 is disregarded and the contents of T4 is reloaded Semiconductor Group 10 16 Version 1 0 11 97 SIEM ENS The General Purpose Timer Unit C164Cl Auxiliary Timer in Capture Mode Capture mode for the auxiliary timers T2 and T4 is selected by setting bit field TxM in the respective register TXCON to 101g In capture mode the contents of the core timer are latched into an auxiliary timer register in response to a signal transition at the respective auxiliary timer s external input pin TxIN The capture trigger signal
258. for programming multiply and divide algorithms can be found in chapter System Programming The Multiply Divide Control Register MDC This bit addressable 16 bit register is implicitly used by the CPU when it performs a multiplication or a division It is used to store the required control information for the corresponding multiply or divide operation Register MDC is updated by hardware during each single cycle of a multiply or divide instruction MDC FFOE 874 SFR Reset Value 00004 15 1 4 13 12 1 10 9 8 7 6 5 4 3 2 1 i mw rw rw rw rw mw mw 0 r w Bit Function MDRIU Multiply Divide Register In Use 0 Cleared when register MDL is read via software 1 Set when register MDL or MDH is written via software or when a multiply or divide instruction is executed i Internal Machine Status The multiply divide unit uses these bits to control internal operations Never modify these bits without saving and restoring register MDC When a division or multiplication was interrupted before its completion and the multiply divide unit is required the MDC register must first be saved along with registers MDH and MDL to be able to restart the interrupted operation later and then it must be cleared prepare it for the new calculation After completion of the new division or multiplication the state of the interrupted multiply or divide operation must be restored The MDRIU flag is the only p
259. function ie WR control and BHE When low it selects the alternate configuration ie WRH and WRL Thus even the first access after a reset can go to a memory controlled via WRH and WRL This bit is latched in register RPOH and its inverted value is copied into bit WRCFG in register SYSCON Default Standard function WR control and BHE Semiconductor Group 20 11 Version 1 0 11 97 SIEMENS System Reset C164CI Chip Select Lines Pins POH 2 and POH 1 CSSEL define the number of active chip select signals during reset This allows the selection which pins of Port 4 drive external CS signals and which are used for general purpose IO The two bits are latched in register RPOH Default All 4 chip select lines active CS3 CS0 CSSEL Chip Select Lines Note 11 Four CS3 CS0 Default without pull downs 10 None 0 1 Two CS1 CS0 00 Three CS2 CS0 Note The selected number of CS signals cannot be changed via software after reset If for a Port 4 pin both CS and segment address function is selected the segment address signal takes preference Segment Address Lines Pins POH 4 and POH 3 SALSEL define the number of active segment address lines during reset This allows the selection which pins of Port 4 drive address lines and which are used for general purpose IO The two bits are latched in register RPOH Depending on the system architecture the required address space is chosen and accessible right fro
260. g addressing mechanisms allow to access the SFRs indirect or direct addressing with 16 bit mem addresses must guarantee that the used data page pointer DPPO DPP3 selects data page 3 accesses via the Peripheral Event Controller PEC use the SRCPx and DSTPx pointers instead of the data page pointers short 8 bit reg addresses to the standard SFR area do not use the data page pointers but directly access the registers within this 512 Byte area short 8 bit reg addresses to the extended ESFR area require switching to the 512 Byte extended SFR area This is done via the EXTension instructions EXTR EXTP R EXTS R Byte write operations to word wide SFRs via indirect or direct 16 bit mem addressing or byte transfers via the PEC force zeros in the non addressed byte Byte write operations via short 8 bit reg addressing can only access the low byte of an SFR and force zeros in the high byte It is therefore recommended to use the bit field instructions BFLDL and BFLDH to write to any number of bits in either byte of an SFR without disturbing the non addressed byte and the unselected bits Reserved Bits Some of the bits which are contained in the C164Cl s SFRs are marked as Reserved User software should never write 1 s to reserved bits These bits are currently not implemented and may be used in future products to invoke new functions In this case the active state for these functions will be 1 and the inactive state w
261. g reset to the slowest possible memory configuration To decrease the number of instructions required to initialize the C164Cl each peripheral is programmed to a default configuration upon reset but is disabled from operation These default configurations can be found in the descriptions of the individual peripherals During the software design phase portions of the internal memory space must be assigned to register banks and system stack When initializing the stack pointer SP and the context pointer CP it must be ensured that these registers are initialized before any GPR or stack operation is performed This includes interrupt processing which is disabled upon completion of the internal reset and should remain disabled until the SP is initialized Note Traps incl NMT may occur even though the interrupt system is still disabled In addition the stack overflow STKOV and the stack underflow STKUN registers should be initialized After reset the CP SP and STKUN registers all contain the same reset value 00 FCO00 while the STKOV register contains 00 FA00 With the default reset initialization 256 words of system stack are available where the system stack selected by the SP grows downwards from 00 FBFE while the register bank selected by the CP grows upwards from 00 FCO00 Based on the application the user may wish to initialize portions of the internal memory before normal program operation Once the register bank ha
262. gister description for an explanation of the control fields Semiconductor Group 16 19 Version 1 0 11 97 SIEMENS The Capture Compare Unit CAPCOM2 C164Cl CAPCOM Unit Interrupt Control Register Addresses CAPCON Unit Register Address Reg Space CC161C F160 BO ESFR CC171C F162 Bi1y ESFR CC18IC F1644 B24 ESFR CC19IC F166 B3y ESFR CC24IC F170 B84 ESFR CC25IC F172 B94 ESFR CC261C F1744 BAH ESFR CC27IC F176 BBy ESFR Semiconductor Group 16 20 Version 1 0 11 97 SIEMENS The Capture Compare Unit CAPCOM6 C164Cl 17 The Capture Compare Unit CAPCOM6 The CAPCOM6 Unit of the C164Cl has been designed for applications which have a demand for digital signal generation and or event capturing eg pulse width modulation pulse width measuring It supports generation and control of timing sequences on up to three 16 bit capture compare channels plus one 10 bit compare channel In compare mode the CAPCOM6G unit provides two output signals per 16 bit channel which may have inverted polarity and non overlapping pulse transitions The 10 bit compare channel can generate a single PWM output signal and is further used to modulate the capture compare output signals For motor control applications both subunits may generate versatile multichannel PWM signals which are basically either controlled by compare timer T12 or by a typical hall sensor pattern at the interrupt inputs
263. grammable External accesses use the slowest possible bus cycle after reset The bus cycle timing may then be optimized by the initialization software ALE N RD WR rowR ST I NY EEUU M ALECTL MCTC MTTC MCD02225 Figure 9 3 Programmable External Bus Cycle Semiconductor Group 9 8 Version 1 0 11 97 SIEMENS The External Bus Interface C164CI ALE Length Control The length of the ALE signal and the address hold time after its falling edge are controlled by the ALECTLx bits in the BUSCON registers When bit ALECTL is set to 1 external bus cycles accessing the respective address window will have their ALE signal prolonged by half a CPU clock 1 TCL Also the address hold time after the falling edge of ALE will be prolonged by half a CPU clock so the data transfer within a bus cycle refers to the same CLKOUT edges as usual ie the data transfer is delayed by one CPU clock This allows more time for the address to be latched Note ALECTLO is 1 after reset to select the slowest possible bus cycle the other ALECTLx are 0 after reset Normal Multiplexed m Lengthened Multiplexed Bus Cycle Bus Ves ay CUP S mc 22 m He a md jus P0 Address X Quoi E m 1 Kuopa XC aN XN lus 60 Ces gt I S WR Figure 9 4 ALE Length Control MCT
264. h state are listed The states of a phase sequence are switched Automatically upon a T12 overflow e Software controlled by setting bit NMCS in register CC6MSEL Bit ESMC 2 1 enables the software controlled state switching and disables switching on T12 overflows Note The actual logic levels for active and passive state are defined in register CC6MCON In 4 phase 5 phase and 6 phase multi channle PWM mode all output signals can be modulated by timer T12 or timer T13 during their active phases 4 phase PWM Sequence Table g Output Level Definition for actual state Follower State for BCM CC60 COUT61 CC62 COUT60 CC61 COUTS62 01 10 00 11 0 passive passive passive passive 2 1 0 5 1 ACTIVE passive passive cns 2 ACTIVE 4 2 0 5 2 ACTIVE ACTIVE passive passive 1 3 0 5 3 passive ACTIVE ACTIVE em passive 2 4 0 5 Semiconductor Group 17 14 Version 1 0 11 97 SIEMENS The Capture Compare Unit CAPCOM6 C164Cl 4 phase PWM Sequence Table 2 Output Level Definition for actual state Follower State for BCM CC60 COUT61 CC62 COUT60 CC61 COUT62 01 10 00 11 4 passive passive ACTIVE ACTIVE 3 1 5 5 passive ACTIVE passive ACTIVE 2 1 5 5 phase PWM Sequence Table g Output Level Defini
265. han to 7 different levels as the hardware support would do Semiconductor Group 5 13 Version 1 0 11 97 SIEMENS Interrupt and Trap Functions C164CI Software controlled Interrupt Classes Example ILVL GLVL Interpretation Priority 3l2 l1lo 15 PEC service on up to 8 channels 14 13 12 X X X X Interrupt Class 1 11 X 5 sources on 2 levels 10 9 8 X X X X Interrupt Class 2 7 x x x x 9 sources on 3 levels 6 X 5 X X X X Interrupt Class 3 4 X 5 sources on 2 levels 3 2 1 0 No service 5 4 Saving the Status during Interrupt Service Before an interrupt request that has been arbitrated is actually serviced the status of the current task is automatically saved on the system stack The CPU status PSW is saved along with the location where the execution of the interrupted task is to be resumed after returning from the service routine This return location is specified through the Instruction Pointer IP and in case of a segmented memory model the Code Segment Pointer CSP Bit SGTDIS in register SYSCON controls how the return location is stored The system stack receives the PSW first followed by the IP unsegmented or followed by CSP and then IP segmented mode This optimizes the usage of the system stack if segmentation is disabled The CPU priority field ILVL in PSW is updated with the priority of the int
266. have to be considered when enabling disabling interrupt requests via modifications of register PSW see chapter The Central Processing Unit Semiconductor Group 5 8 Version 1 0 11 97 SIEMENS Interrupt and Trap Functions C164CI PSW FF10 884 SFR Reset Value 0000 15 14 13 12 11 0 10 9 8 7 6 5 4 3 2 1 HLD MUL rw rw rw rw rw rw rw rw rw rw Bit Function N C V Z E CPU status flags Described in section The Central Processing Unit MULIP USRO Define the current status of the CPU ALU multiplication unit HLDEN HOLD Enable Enables External Bus Arbitration 0 Bus arbitration disabled P6 7 P6 5 may be used for general purpose IO 1 Bus arbitration enabled P6 7 P6 5 serve as BREQ HLDA HOLD resp ILVL CPU Priority Level Defines the current priority level for the CPU Fu Highest priority level Op Lowest priority level IEN Interrupt Enable Control Bit globally enables disables interrupt requests 0 Interrupt requests are disabled 1 Interrupt requests are enabled CPU Priority ILVL defines the current level for the operation of the CPU This bit field reflects the priority level of the routine that is currently executed Upon the entry into an interrupt service routine this bit field is updated with the priority level of the request that is being serviced The PSW is saved on the system stack before The CPU level determines the minimum interrupt priority
267. he external clock When PLL operation is selected the CPU clock is a selectable multiple of the oscillator frequency ie the input frequency The table below lists the possible selections Semiconductor Group 6 5 Version 1 0 11 97 SIEMENS Clock Generation C164CI C164CI Clock Generation Modes P0 15 13 CPU External Clock Input Notes POH 7 5 Frequency fcpy Range fosc F 1 1 1 fara 4 2 5 to 5 MHz Default configuration 1 1 0 faa 3 3 33 to 6 66 MHz 1 0 1 faa 2 5to 10 MHz 1 0 0 faa 5 210 4 MHz 0 1 1 Tasa 1 to 20 MHz Direct drive 0 1 0 Feta 1 5 6 66 to 13 3 MHz 0 50 1 faa 2 2 to 40 MHz Prescaler operation 0 0 0 faa 2 5 4to 8 MHz 1 The external clock input range refers to a CPU clock range of 10 20 MHz for PLL operation which is the specified operating frequency band for the PLL 2 The maximum depends on the duty cycle of the external clock signal In emulation mode pin P0 15 POH 7 is inverted ie the configuration 111 would select direct drive in emulation mode The PLL constantly synchronizes to the external clock signal Due to the fact that the external frequency is 1 F th of the PLL output frequency the output frequency may be slightly higher or lower than the desired frequency This jitter is irrelevant for longer time periods For short periods 1 4 CPU clock cycles it remains below 4 Semiconductor Group Version 1 0 11 97 SIEMENS
268. he register banking scheme provides the best performance for passing data between multiple tasks Note The system stack allows the storage of words only Bytes must either be converted to words or the respective other byte must be disregarded Register SP can only be loaded with even byte addresses The LSB of SP is always 0 Detection of stack overflow underflow is supported by two registers STKOV Stack Overflow Pointer and STKUN Stack Underflow Pointer Specific system traps Stack Overflow trap Stack Underflow trap will be entered whenever the SP reaches either boundary specified in these registers The contents of the stack pointer are compared to the contents of the overflow register whenever the SP is DECREMENTED either by a CALL PUSH or SUB instruction An overflow trap will be entered when the SP value is less than the value in the stack overflow register The contents of the stack pointer are compared to the contents of the underflow register whenever the SP is INCREMENTED either by a RET POP or ADD instruction An underflow trap will be entered when the SP value is greater than the value in the stack underflow register Note When a value is MOVED into the stack pointer NO check against the overflow underflow registers is performed In many cases the user will place a software reset instruction SRST into the stack underflow and overflow trap service routines This is an easy approach which does not require speci
269. he source operand of an instruction is 80004 or 80 MULIP Multiplication Division In Progress 0 There is no multiplication division in progress 1 Amultiplication division has been interrupted USRO User General Purpose Flag May be used by the application software HLDEN Interrupt and EBC Control Fields ILVL IEN Define the response to interrupt requests and enable external bus arbitration Described in section Interrupt and Trap Functions ALU Status N C V Z E MULIP The condition flags N C V Z E within the PSW indicate the ALU status due to the last recently performed ALU operation They are set by most of the instructions due to specific rules which depend on the ALU or data movement operation performed by an instruction After execution of an instruction which explicitly updates the PSW register the condition flags cannot be interpreted as described in the following because any explicit write to the PSW register supersedes the condition flag values which are implicitly generated by the CPU Explicitly reading the PSW register supplies a read value which represents the state of the PSW register after execution of the immediately preceding instruction Note After reset all of the ALU status bits are cleared Semiconductor Group 4 14 Version 1 0 11 97 SIEMENS The Central Processing Unit CPU C164Cl N Flag For most of the ALU operations the N flag is set to 1 if the mos
270. he value of bit SGTDIS Context Switching An interrupt service routine usually saves all the registers it uses on the stack and restores them before returning The more registers a routine uses the more time is wasted with saving and restoring The C164Cl allows to switch the complete bank of CPU registers GPRs with a single instruction so the service routine executes within its own separate context The instruction SCXT CP New Bank pushes the content of the context pointer CP on the system stack and loads CP with the immediate value New Bank which selects a new register bank The service routine may now use its own registers This register bank is preserved when the service routine terminates ie its contents are available on the next call Before returning RETI the previous CP is simply POPped from the system stack which returns the registers to the original bank Note The first instruction following the SCXT instruction must not use a GPR Resources that are used by the interrupting program must eventually be saved and restored eg the DPPs and the registers of the MUL DIV unit Semiconductor Group 5 15 Version 1 0 11 97 SIEMENS Interrupt and Trap Functions C164CI 5 5 nterrupt Response Times The interrupt response time defines the time from an interrupt request flag of an enabled interrupt source being set until the first instruction 11 being fetched from the interrupt vector location The basic inter
271. her modes each passive phase is shortened or lengthened by one sequence phase respectively Start Trigger CC60 COUT61 CC60 COUT60 gum are Unmodulated Modulated Modulated Active Phase by T12 by T13 The trigger that switches to the next phase may be a T12 overflow or a 1 being written to bit NMCS via software In block commutation mode the trigger is represented by a change in the input pattern on pins CC6POSx The shown waveforms are active high Figure 17 11 Basic 5 phase Multi Channel Timing Semiconductor Group 17 13 Version 1 0 11 97 SIEMENS The Capture Compare Unit CAPCOM6 C164Cl The compare output signals are enabled according to the intended multi phase mode The table below lists the required coding Programming of Multi Channel PWM Outputs Multi Channel PWM Mode CMSEL2 CMSEL1 CMSELO Block commutation mode 011g 011g 011g 4 phase multi channel PWM 011g 010g 001g 5 phase multi channel PWM 011g 010g 011g 6 phase multi channel PWM 011g 011g 011g Note Bit CMSELx3 burst mode bit defines if the signal at the COUT6x pins is modulated by compare timer T13 CMSELx3 1 or not T13 modulation may be combined with T12 modulation Phase Sequence Tables The following tables list the phase sequences for the different multi phase modes The sequence is defined via the follower state for each state and also the output levels for eac
272. hm Each instruction implicitly uses the 32 bit register MD MDL lower 16 bits MDH upper 16 bits The MDRIU flag Multiply or Divide Register In Use in register MDC is set whenever either half of this register is written to or when a multiply divide instruction is started It is cleared whenever the MDL register is read Because an interrupt can be acknowledged before the contents of register MD are saved this flag is required to alert interrupt routines which require the use of the multiply divide hardware so they can preserve register MD This register however only needs to be saved when an interrupt routine requires use of the MD register and a previous task has not saved the current result This flag is easily tested by the Jump on Bit instructions Semiconductor Group 22 1 Version 1 0 11 97 SIEMENS System Programming C164CI Multiplication or division is simply performed by specifying the correct signed or unsigned version of the multiply or divide instruction The result is then stored in register MD The overflow flag V is set if the result from a multiply or divide instruction is greater than 16 bits This flag can be used to determine whether both word halfs must be transferred from register MD The high portion of register MD MDH must be moved into the register file or memory first in order to ensure that the MDRIU flag reflects the correct state The following instruction sequence performs an unsigned 16 by 16 bit mul
273. iated with the respective window Predefined address windows allow to use different bus modes without any overhead but restrict their number to the number of BUSCONs However as BUSCONDO controls all address areas which are not covered by the other BUSCONS this allows to have gaps between these windows which use the bus mode of BUSCONO Note Never change the configuration for an address area that currently supplies the instruction stream Due to the internal pipelining it is very difficult to determine the first instruction fetch that will use the new configuration Only change the configuration for address areas that are not currently accessed This applies to BUSCON registers as well as to ADDRSEL registers The usage of the BUSCON ADDRSEL registers is controlled via the issued addresses When an access code fetch or data is initiated the respective generated physical address defines if the access is made internally uses one of the address windows defined by ADDRSEL4 1 or uses the default configuration in BUSCONO After initializing the active registers they are selected and evaluated automatically by interpreting the physical address No additional switching or selecting is necessary during run time except when more than the four address windows plus the default is to be used Semiconductor Group 9 4 Version 1 0 11 97 SIEMENS The External Bus Interface C164CI External Data Bus Width The EBC can operate on 8 bit or 16 bit w
274. ic Analyzer disassemblers Starter Kits Evaluation Boards with monitor programs Industrial boards also for CAN FUZZY PROFIBUS FORTH applications Network driver software CAN PROFIBUS Semiconductor Group 1 6 Version 1 0 11 97 SIEMENS Introduction C164CI 1 3 Abbreviations The following acronyms and termini are used within this document ADC eek Analog Digital Converter ALE tire 2562224 Address Latch Enable ALUS G ienet Arithmetic and Logic Unit ASC ee ek Asynchronous synchronous Serial Controller CAN Controller Area Network License Bosch CAPCOM CAPture and COMpare unit CISC Complex Instruction Set Computing CMOS Complementary Metal Oxide Silicon GPU s Central Processing Unit EBC a meea ea External Bus Controller ESFR s Extended Special Function Register Flash Non volatile memory that may be electrically erased OP ee ere oes General Purpose Register GPT Seda i utes General Purpose Timer unit HL uris High Level Language jer Input Output OP arrana ass One Time Programmable memory PEG pioden Peripheral Event Controller PLA eres Programmable Logic Array Pl E Phase Locked Loop PWM ZI e Pulse Width Modulation RAM Random Access Memory RISC Reduced Instruction Set Computing ROM Read Only Memory SDD apra ana Slow Down Divider SFER sedis iE Special Function Register SO eve vie Synchronous Serial Controller XBUS sees ex Internal represent
275. ide external memory peripherals A 16 bit data bus uses PORTO while an 8 bit data bus only uses POL the lower byte of PORTO This saves on address latches bus transceivers bus routing and memory cost on the expense of transfer time The EBC can control word accesses on an 8 bit data bus as well as byte accesses on a 16 bit data bus Word accesses on an 8 bit data bus are automatically split into two subsequent byte accesses where the low byte is accessed first then the high byte The assembly of bytes to words and the disassembly of words into bytes is handled by the EBC and is transparent to the CPU and the programmer Byte accesses on a 16 bit data bus require that the upper and lower half of the memory can be accessed individually In this case the upper byte is selected with the BHE signal while the lower byte is selected with the AO signal So the two bytes of the memory can be enabled independent from each other or together when accessing words When writing bytes to an external 16 bit device which has a single CS input but two WR enable inputs for the two bytes the EBC can directly generate these two write control signals This saves the external combination of the WR signal with AO or BHE In this case pin WR serves as WRL write low byte and pin BHE serves as WRH write high byte Bit WRCFG in register SYSCON selects the operating mode for pins WR and BHE The respective byte will be written on both data bus halfs When read
276. ied by an individual bit in the trap flag register TFR Except for another higher prioritized trap service being in progress a hardware trap will interrupt any current program execution In turn hardware trap services can normally not be interrupted by standard or PEC interrupts Software interrupts are supported by means of the TRAP instruction in combination with an individual trap interrupt number Semiconductor Group 2 6 Version 1 0 11 97 SIEMENS Architectural Overview C164Cl 2 2 The On chip System Resources The C164CI controllers provide a number of powerful system resources designed around the CPU The combination of CPU and these resources results in the high performance of the members of this controller family Peripheral Event Controller PEC and Interrupt Control The Peripheral Event Controller allows to respond to an interrupt request with a single data transfer word or byte which only consumes one instruction cycle and does not require to save and restore the machine status Each interrupt source is prioritized every machine cycle in the interrupt control block If PEC service is selected a PEC transfer is started If CPU interrupt service is requested the current CPU priority level stored in the PSW register is tested to determine whether a higher priority interrupt is currently being serviced When an interrupt is acknowledged the current state of the machine is saved on the internal system stack and the CPU bra
277. ill be 0 Therefore writing only 0 s to reserved locations provides portability of the current software to future devices After read accesses reserved bits should be ignored or masked out Parallel Ports The C164CI provides up to 59 IO lines which are organized into five input output ports and one input port All port lines are bit addressable and all input output lines are individually bit wise programmable as inputs or outputs via direction registers The IO ports are true bidirectional ports which are switched to high impedance state when configured as inputs The output drivers of two IO ports can be configured pin by pin for push pull operation or open drain operation via control registers During the internal reset all port pins are configured as inputs All port lines have programmable alternate input or output functions associated with them PORTO may be used as address and data lines when accessing external memory while Port 4 outputs the additional segment address bits A21 19 17 A16 and or the chip select signals CS3 CSO in systems where segmentation is used to access more than 64 KBytes of memory PORT1 provides input and output signals for the CAPCOM units Port 3 includes alternate functions of timers serial interfaces the optional bus control signal BHE and the system clock output CLKOUT Port 5 is used for timer control signals and for the analog inputs to the A D Converter Port 8 provides inputs outputs for the C
278. ill most requirements of embedded control applications the ADC supports the following conversion modes Fixed Channel Single Conversion produces just one result from the selected channel Fixed Channel Continuous Conversion repeatedly converts the selected channel Auto Scan Single Conversion produces one result from each of a selected group of channels Auto Scan Continuous Conversion repeatedly converts the selected group of channels Wait for ADDAT Read Mode start a conversion automatically when the previous result was read Channel Injection Mode insert the conversion of a specific channel into a group conversion auto scan A set of SFRs and port pins provide access to control functions and results of the ADC Ports amp Direction Control Data Registers Control Registers Interrupt Control Alternate Functions ADDAT ADCON ADCIC P5DIDIS ADDAT2 E ADEIC P5 Port 5 Analog Input Port ANO P5 0 AN7 P5 7 ADCIC A D Converter Interrupt Control Register P5DIDIS Port 5 Digital Input Disable Register End of Conversion ADDAT A D Converter Result Register ADEIC A D Converter Interrupt Control Register ADDAT2 A D Converter Channel Injection Result Register Overrun Error Channel Injection ADCON A D Converter Control Register Figure 18 1 SFRs and Port Pins associated with the A D Converter Semiconductor Group 18 1 Version 1 0 10 97 SIEMENS The Analog Digital Converter C164CI The external analog r
279. ime description the following section provides some hints on how to optimize time critical program parts with regard to such pipeline caused timing particularities Semiconductor Group 4 8 Version 1 0 11 97 SIEMENS The Central Processing Unit CPU C164Cl 4 2 Bit Handling and Bit Protection The C164Cl provides several mechanisms to manipulate bits These mechanisms either manipulate software flags within the internal RAM control on chip peripherals via control bits in their respective SFRs or control IO functions via port pins The instructions BSET BCLR BAND BOR BXOR BMOV BMOVN explicitly set or clear specific bits The instructions BFLDL and BFLDH allow to manipulate up to 8 bits of a specific byte at one time The instructions JBC and JNBS implicitly clear or set the specified bit when the jump is taken The instructions JB and JNB also conditional jump instructions that refer to flags evaluate the specified bit to determine if the jump is to be taken Note Bit operations on undefined bit locations will always read a bit value of 0 while the write access will not effect the respective bit location All instructions that manipulate single bits or bit groups internally use a read modify write sequence that accesses the whole word which contains the specified bit s This method has several consequences Bits can only be modified within the internal address areas ie internal RAM and SFRs External locations can
280. imer resolution and increases the step width eg for baudrate generation The oscillator frequency in such a case should be chosen to accomodate the required resolutions and or baudrates SYSCON F1D0 E8 ESFR Reset Value 00X0 15 14 13 12 11 10 3 2 1 0 9 8 7 6 5 4 CLK LOCK CLKREL CLKCON SCS RCS PDCON SYSRLS rw rw rw rw r rw Bit Function SYSRLS SYSCON Release Function Unlock field Must be written in a defined way in order to execute the unlock sequence See separate description PDCON Power Down Control during power down mode 00 RTC On Ports On default after reset 01 RTC On Ports Off 10 RTC Off Ports On 11 RTC Off Ports Off RCS RTC Clock Source not affected by a reset 0 Main oscillator 1 Reserved SCS SDD Clock Source not affected by a reset 0 Main oscillator 1 Reserved CLKCON Clock State Control 00 Running on configured basic frequency 01 Running on slow down frequency PLL ON if implemented 10 Running on slow down frequency PLL OFF if implemented 11 Reserved Do not use this combination CLKREL Reload Counter Value for Slowdown Divider CLKLOCK Clock Signal Status Bit 0 Main oscillator is unstable or PLL is unlocked if PLL is implemented 1 Main oscillator is stable and PLL is locked if PLL is implemented If no PLL is implemented it is assumed to be always locked Note SYSCON2 except for bitfield SYSRLS of course
281. ing bytes from an external 16 bit device whole words may be read and the C164Cl automatically selects the byte to be input and discards the other However care must be taken when reading devices that change state when being read like FIFOs interrupt status registers etc In this case individual bytes should be selected using BHE and AO Bus Mode Transfer Rate Speed factor for System Requirements byte word dword access 8 bit Multiplexed Low 1 272 Low 8 bit latch byte bus 16 bit Multiplexed High 1 172 High 16 bit latch word bus Disable Enable Control for Pin BHE BYTDIS Bit BYTDIS is provided for controlling the active low Byte High Enable BHE pin The function of the BHE pin is enabled if the BYTDIS bit contains a 0 Otherwise it is disabled and the pin can be used as standard IO pin The BHE pin is implicitly used by the External Bus Controller to select one of two byte organized memory chips which are connected to the C164Cl via a word wide external data bus After reset the BHE function is automatically enabled BYTDIS 0 if a 16 bit data bus is selected during reset otherwise it is disabled BYTDIS 1 It may be disabled if byte access to 16 bit memory is not required and the BHE signal is not used Semiconductor Group 9 5 Version 1 0 11 97 SIEMENS The External Bus Interface C164CI Segment Address Generation During external accesses the EBC generates a programmable number of add
282. ing if neither this value nor the compared value have been found Otherwise the loop is terminated if either condition has been met The terminating condition can then be tested The third loop enhancement provides a more flexible solution than the Decrement and Skip on Zero instruction which is found in other microcontrollers Through the use of Compare and Increment or Decrement instructions the user can make comparisons to any value This allows loop counters to cover any range This is particularly advantageous in table searching Semiconductor Group 2 4 Version 1 0 11 97 SIEMENS Architectural Overview C164Cl Saving of system state is automatically performed on the internal system stack avoiding the use of instructions to preserve state upon entry and exit of interrupt or trap routines Call instructions push the value of the IP on the system stack and require the same execution time as branch instructions Instructions have also been provided to support indirect branch and call instructions This supports implementation of multiple CASE statement branching in assembler macros and high level languages Consistent and Optimized Instruction Formats To obtain optimum performance in a pipelined design an instruction set has been designed which incorporates concepts from Reduced Instruction Set Computing RISC These concepts primarily allow fast decoding of the instructions and operands while reducing pipeline holds These concepts
283. inserted injected into a running sequence without disturbing this sequence This is called Channel Injection Mode The Peripheral Event Controller PEC may be used to automatically store the conversion results into a table in memory for later evaluation without requiring the overhead of entering and exiting interrupt routines for each data transfer Real Time Clock The C164CI contains a real time clock RTC which serves for different purposes System clock to determine the current time and date even during idle mode and power down mode optionally Cyclic time based interrupt eg to provide a system time tick independent of the CPU frequency without loading the general purpose timers or to wake up regularly from idle mode 48 bit timer for long term measurements the maximum usable timespan is more than 100 years The RTC module consists of a chain of 3 divider blocks a fixed 8 1 divider the reloadable 16 bit timer T14 and the 32 bit RTC timer accessible via registers RTCH and RTCL Both timers count up Semiconductor Group 2 14 Version 1 0 11 97 SIEMENS Architectural Overview C164Cl 2 4 Power Management Features The known basic power reduction modes ldle and Power Down are enhanced by a number of additional power management features see below These features can be combined to reduce the controller s power consumption to the respective application s possible minimum e Flexible clock generation e Flexible
284. instruction cycle time with most instructions executed in 1 cycle 500 ns multiplication 16 bit x 16 bit 1 uus division 32 bit 16 bit Multiple high bandwidth internal data buses Register based design with multiple variable register banks Single cycle context switching support 16 MBytes linear address space for code and data von Neumann architecture System stack cache support with automatic stack overflow underflow detection Control Oriented Instruction Set with High Efficiency Bit byte and word data types Flexible and efficient addressing modes for high code density Enhanced boolean bit manipulation with direct addressability of 6 Kbits for peripheral control and user defined flags Hardware traps to identify exception conditions during runtime HLL support for semaphore operations and efficient data access Integrated On chip Memory 2 KByte internal RAM for variables register banks system stack and code 64 Byte on chip Mask ROM or OTP memory not for romless devices External Bus Interface Multiplexed bus configurations Segmentation capability and chip select signal generation 8 bit or 16 bit data bus Bus cycle characteristics selectable for five programmable address areas 16 Priority Level Interrupt System 32 interrupt nodes with separate interrupt vectors 300 500 ns typical maximum interrupt latency in case of internal program execution Fast external interrupts Semicondu
285. interrupt service routine is entered and it is repopped when the interrupt service routine is left again System Stack Size STKSZ This bitfield defines the size of the physical system stack which is located in the internal RAM of the C164Cl An area of 32 512 words or all of the internal RAM may be dedicated to the system stack A so called circular stack mechanism allows to use a bigger virtual stack than this dedicated RAM area These techniques as well as the encoding of bitfield STKSZ are described in more detail in chapter System Programming Semiconductor Group 4 13 Version 1 0 11 97 SIEMENS The Central Processing Unit CPU C164Cl The Processor Status Word PSW This bit addressable register reflects the current state of the microcontroller Two groups of bits represent the current ALU status and the current CPU interrupt status A separate bit USRO within register PSW is provided as a general purpose user flag PSW FF10 884 SFR Reset Value 00004 15 14 13 12 1i 0 10 9 8 7 6 5 4 3 2 1 HLD MUL ILVL EN IP V C rw rw w mw w w mw rw rw ed Bit Function N Negative Result Set when the result of an ALU operation is negative C Carry Flag Set when the result of an ALU operation produces a carry bit V Overflow Result Set when the result of an ALU operation produces an overflow Z Zero Flag Set when the result of an ALU operation is zero E End of Table Flag Set when t
286. into the receive shift register synchronous to the clock which is output at pin TXDO After the 8th bit has been shifted in the content of the receive shift register is transferred to the receive data buffer SORBUF the receive interrupt request flag SORIR is set the receiver enable bit SOREN is reset and serial data reception stops Pin TXDO P3 10 must be configured for alternate data output ie P3 10 1 and DP3 10 1 in order to provide the shift clock Pin RXDO P3 11 must be configured as alternate data input DP3 112 0 Synchronous reception is stopped by clearing bit SOREN A currently received byte is completed including the generation of the receive interrupt request and an error interrupt request if appropriate Writing to the transmit buffer register while a reception is in progress has no effect on reception and will not start a transmission If a previously received byte has not been read out of the receive buffer register at the time the reception of the next byte is complete both the error interrupt request flag SOEIR and the overrun error status flag SOOE will be set provided the overrun check has been enabled by bit SOOEN Semiconductor Group 11 9 Version 1 0 11 97 Sl EM ENS The Asynchronous Synchronous Serial Interface C164CI 11 3 Hardware Error Detection Capabilities To improve the safety of serial data exchange the serial channel ASCO provides an error interrupt request flag which indicates the presence of an
287. ion SWR Software Reset Indication Flag SHWR Short Hardware Reset Indication Flag LHWR Long Hardware Reset Indication Flag WDTREL Watchdog Timer Reload Value for the high byte of WDT Note The reset value depends on the reset source see description below The execution of EINIT clears the reset indication flags After any software reset external hardware reset see note or watchdog timer reset the watchdog timer is enabled and starts counting up from 0000 with the frequency fcpy 2 The input frequency may be switched to fopy 128 by setting bit WDTIN The watchdog timer can be disabled via the instruction DISWDT Disable Watchdog Timer Instruction DISWDT is a protected 32 bit instruction which will ONLY be executed during the time between a reset and execution of either the EINIT End of Initialization or the SRVWDT Service Watchdog Timer instruction Either one of these instructions disables the execution of DISWDT Note After a hardware reset that activates the Bootstrap Loader the watchdog timer will be disabled When the watchdog timer is not disabled via instruction DISWDT it will continue counting up even during Idle Mode If it is not serviced via the instruction SRVWDT by the time the count reaches FFFF the watchdog timer will overflow and cause an internal reset This reset will pull the external reset indication pin RSTOUT low and RSTIN in bidirectional reset mode The Watchdog Timer Reset Indi
288. ion fetch from an external location Operand read from an external location Result write back to an external location Depending on where the instructions source and destination operands are located there are a number of combinations Note however that only access conflicts contribute to the delay A few examples illustrate these delays The worst case interrupt response time including external accesses will occur when instructions N N 1 and N 2 are executed out of external memory instructions N 1 and N require external operand read accesses instructions N 3 through N write back external operands and the interrupt vector also points to an external location In this case the interrupt response time is the time to perform 9 word bus accesses because instruction 11 cannot be fetched via the external bus until all write fetch and read requests of preceding instructions in the pipeline are terminated When the above example has the interrupt vector pointing into the internal code memory the interrupt response time is 7 word bus accesses plus 2 states because fetching of instruction 11 from internal code memory can start earlier When instructions N N 1 and N 2 are executed out of external memory and the interrupt vector also points to an external location but all operands for instructions N 3 through N are in internal memory then the interrupt response time is the time to perform 3 word bus accesses When the above example h
289. ional action upon a baudrate error 1 The SSC is automatically reset upon a baudrate error SSCMS SSC Master Select Bit 0 Slave Mode Operate on shift clock received via SCLK 1 Master Mode Generate shift clock and output it via SCLK SSCEN SSC Enable Bit 0 Transmission and reception disabled Access to control bits Semiconductor Group 12 3 Version 1 0 11 97 SIEM ENS The High Speed Synchronous Serial Interface C164Cl SSCCON FFB2 D9 SFR Reset Value 0000 15 14 13 12 11 40 9 8 7 6 5 4 3 2 1 0 SSC SSC SSC SSC SSC SSC SSC rw rw rw rw rw rw rw r Bit Function Operating Mode SSCEN 1 SSCBC SSC Bit Count Field Shift counter is updated with every shifted bit Do not write to SSCTE SSC Transmit Error Flag 1 Transfer starts with the slave s transmit buffer not being updated SSCRE SSC Receive Error Flag dus Reception completed before the receive buffer was read SSCPE SSC Phase Error Flag qs Received data changes around sampling clock edge SSCBE SSC Baudrate Error Flag 1 More than factor 2 or 0 5 between Slave s actual and expected baudrate SSCBSY SSC Busy Flag Set while a transfer is in progress Do not write to SSCMS SSC Master Select Bit 0 Slave Mode Operate on shift clock received via SCLK he Master Mode Generate shift clock and output it via SCLK SSCEN SSC Enable Bit 1 Transmission and reception enabled Access to status flag
290. iority 1 The hardwired XADRSx registers are evaluated first A match with one of these registers directs the access to the respective X Peripheral using the corresponding XBCONx register and ignoring all other ADDRSELx registers Priority 2 Registers ADDRSEL2 and ADDRSELA are evaluated before ADDRSEL1 and ADDRSELS respectively A match with one of these registers directs the access to the respective external area using the corresponding BUSCONXx register and ignoring registers ADDRSEL1 3 see figure below Priority 3 A match with registers ADDRSEL1 or ADDRSEL3 directs the access to the respective external area using the corresponding BUSCONXx register Priority 4 If there is no match with any XADRSx or ADDRSELx register the access to the external bus uses register BUSCONO XBCONO BUSCON2 BUSCON4 BUSCON1 BUSCONS3 Active Window gt inactive Window Figure 9 8 Address Window Arbitration Note Only the indicated overlaps are defined All other overlaps lead to erroneous bus cycles Eg ADDRSEL4 may not overlap ADDRSEL2 or ADDRSEL1 The hardwired XADRSx registers are defined non overlapping Semiconductor Group 9 19 Version 1 0 11 97 SIEMENS The External Bus Interface C164CI RPOH F108 844 SFR Reset Value XX4 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CLKCFG SALSEL CSSEL r r r r Bit Function WRC Write Configuration 0 Pins WR and BHE operate as WRL and WRH signals 1 Pins WR and BHE operate
291. ir specific IO requirements port lines have programmable alternate input or output functions associated with them Alternate Port Functions Port Alternate Function s PORTO Address and data lines when accessing external resources eg memory PORT 1 Capture inputs or compare outputs of the CAPCOM units Port 3 Input output functions of timers serial interfaces Optional bus control signal BHE WRH and system clock output CLKOUT Port 4 Additional selected segment address bits Axx A16 in systems where more than 64 KBytes of memory are to be accessed directly Optional chip select outputs CAN interface Port 5 Analog input channels to the A D converter Timer control signal inputs Port 8 Capture inputs or compare outputs of the CAPCOM units If an alternate output function of a pin is to be used the direction of this pin must be programmed for output DPx y 1 except for some signals that are used directly after reset and are configured automatically Otherwise the pin remains in the high impedance state and is not effected by the alternate output function The respective port latch should hold a 1 because its output is combined with the alternate output data If an alternate input function of a pin is used the direction of the pin must be programmed for input DPx y2 0 if an external device is driving the pin The input direction is the default after reset If no external device is connected to the
292. irs N 2 N 1 or N 1 N occur the minimum PEC response time may be extended by 1 state time for each of these conditions When instruction N reads an operand from the internal code memory or when N is a call return trap or MOV Rn Rm data16 instruction the minimum PEC response time may additionally be extended by 2 state times during internal code memory program execution In case instruction N reads the PSW and instruction N 1 has an effect on the condition flags the PEC response time may additionally be extended by 2 state times The worst case PEC response time during internal code memory program execution adds to 9 state times 18 TCL Any reference to external locations increases the PEC response time due to pipeline related access priorities The following conditions have to be considered Instruction fetch from an external location Operand read from an external location Result write back to an external location Depending on where the instructions source and destination operands are located there are a number of combinations Note however that only access conflicts contribute to the delay A few examples illustrate these delays The worst case interrupt response time including external accesses will occur when instructions N and N 1 are executed out of external memory instructions N 1 and N require external operand read accesses and instructions N 3 N 2 and N 1 write back external operands In this case the
293. is connected to the slaves shift register input The output of the slaves shift register is connected to the external receive line in order to enable the master to receive the data shifted out of the slave The external connections are hard wired the function and direction of these pins is determined by the master or slave operation of the individual device Note The shift direction shown in the figure applies for MSB first operation as well as for LSB first operation When initializing the devices in this configuration select one device for master operation SSCMS 1 all others must be programmed for slave operation SSCMS 0 Initialization includes the operating mode of the device s SSC and also the function of the respective port lines see Port Control Master Device 1 Device 2 Slave Shift Register Shift Register q Transmit y Receive e q Clock Shift Register MCS01963 Figure 12 4 SSC Full Duplex Configuration Semiconductor Group 12 6 Version 1 0 11 97 SIEM ENS The High Speed Synchronous Serial Interface C164CI The data output pins MRST of all slave devices are connected together onto the one receive line in this configuration During a transfer each slave shifts out data from its shift register There are two ways to avoid collisions on the receive line due to different slave data Only one slave drives the line ie enables the driver of its
294. is not triggered ie no stack trap is generated when the stack pointer SP is directly updated via MOV instructions e the limits of the stack area STKOV STKUN are changed so that SP is outside of the new limits Semiconductor Group 4 26 Version 1 0 11 97 SIEMENS The Central Processing Unit CPU C164Cl The Multiply Divide High Register MDH This register is a part of the 32 bit multiply divide register which is implicitly used by the CPU when it performs a multiplication or a division After a multiplication this non bit addressable register represents the high order 16 bits of the 32 bit result For long divisions the MDH register must be loaded with the high order 16 bits of the 32 bit dividend before the division is started After any division register MDH represents the 16 bit remainder MDH FEOC 064 SFR Reset Value 00004 15 14 13 12 1 10 9 8 7 6 5 4 3 2 l 0 rw Bit Function mdh Specifies the high order 16 bits of the 32 bit multiply and divide register MD Whenever this register is updated via software the Multiply Divide Register In Use MDRIU flag in the Multiply Divide Control register MDC is set to 1 When a multiplication or division is interrupted before its completion and when a new multiply or divide operation is to be performed within the interrupt service routine register MDH must be saved along with registers MDL and MDC to avoid erroneous results A detailed description of
295. is used for general purpose IO the direction of each line can be configured via the corresponding direction registers DPOH and DPOL POL FF00 804 SFR Reset Value 00 15 14 13 12 11 10 9 8 ae 6 5 4 3 2 1 0 POL 7 POL 6 POL 5 POL 4 POL 3 POL 2 POL 1 POL O POH FF02 814 SFR Reset Value 00 8 7 6 5 4 3 2 1 0 x x rw rw rw rw rw rw rw rw Bit Function POX y Port data register POH or POL bit y DPOL F100 804 ESFR Reset Value 00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DPOL DPOL DPOL DPOL DPOL DPOL DPOL DPOL 7 6 5 4 3 2 1 0 a m x DPOH F102 815 ESFR Reset Value 00 zs ee LU nis 8 7 6 5 4 3 2 1 0 DPOH DPOH DPOH DPOH 7 6 A 0 E i rw rw rw rw rw rw rw rw Bit Function DPOX y Port direction register DPOH or DPOL bit y DPOX y 0 Port line POX y is an input high impedance DPOX y 1 Port line POX y is an output Semiconductor Group 7 6 Version 1 0 11 97 SIEMENS Parallel Ports C164CI Alternate Functions of PORTO When an external bus is enabled PORTO is used as address data bus PORTO is also used to select the system startup configuration During reset PORTO is configured to input and each line is held high through an internal pullup device Each line can now be individually pulled to a low level see DC level specifications in the respective Data Sheets through an external pulldown device A default configuratio
296. is will be approximately one quarter to one tenth the size of the internal stack Once the transfer is complete the boundary pointers are updated to reflect the newly allocated space on the internal stack Thus the user is free to write code without concern for the internal stack limits Only the execution time required by the trap routines affects user programs The following procedure initializes the controller for usage of the circular stack mechanism Specify the size of the physical system stack area within the internal RAM bitfield STKSZ in register SYSCON Define two pointers which specify the upper and lower boundary of the external stack These values are then tested in the stack underflow and overflow trap routines when moving data Set the stack overflow pointer STKOV to the limit of the defined internal stack area plus six words for the reserved space to store two interrupt entries The internal stack will now fill until the overflow pointer is reached After entry into the overflow trap procedure the top of the stack will be copied to the external memory The internal pointers will then be modified to reflect the newly allocated space After exiting from the trap procedure the internal stack will wrap around to the top of the internal stack and continue to grow until the new value of the stack overflow pointer is reached When the underflow pointer is reached while the stack is meptied the bottom of stack is reloaded
297. ister It will not wait for the next clock from the baudrate generator as the master does The reason for this is that depending on the selected clock phase the first clock edge generated by the master may be already used to clock in the first data bit So the slave s first data bit must already be valid at this time Semiconductor Group 12 7 Version 1 0 11 97 SIEM ENS The High Speed Synchronous Serial Interface C164CI Note On the SSC always a transmission and a reception takes place at the same time regardless whether valid data has been transmitted or received This is different eg from asynchronous reception on ASCO The initialization of the SCLK pin on the master requires some attention in order to avoid undesired clock transitions which may disturb the other receivers The state of the internal alternate output lines is 1 as long as the SSC is disabled This alternate output signal is ANDed with the respective port line output latch Enabling the SSC with an idle low clock SSCPO 0 will drive the alternate data output and via the AND the port pin SCLK immediately low To avoid this use the following sequence select the clock idle level SSCPO x load the port output latch with the desired clock idle level P3 132 x e switch the pin to output DP3 13 1 enable the SSC SSCEN 1 if SSCPO 0 enable alternate data output P3 13 1 The same mechanism as for selecting a slave for tr
298. ister DP1H or DP1L bit y DP1X y 0 Port line P1X y is an input high impedance DP1X y 1 Port line P1X y is an output Semiconductor Group 7 9 Version 1 0 11 97 SIEMENS Parallel Ports C164CI Alternate Functions of PORT1 The lower 11 pins of PORT1 P1H 2 P1L 0 serve as the inputs outputs for the CAPCOMG unit Pins P1H 3 P1H 0 accept the fast external interrupt inputs P1H 3 also serves as input for timer T7 The upper four pins of PORT1 P1H 7 P1H 4 also serve as capture input lines for the CAPCOM2 unit CC2710O CC241O As all other capture inputs the capture input function of pins P1H 7 P1H 4 can also be used as external interrupt inputs sample rate 16 TCL Alternate Function a b c P1H 7 CC2710 P1H 6 CC2610 P1H 5 CC2510 P1H 4 CC24IO P1H P1H 3 EX3IN T7IN P1H 2 CC6POS2 EX2IN P1H 1 CC6POS1 EX1IN P1H 0 CC6POSO EXOIN PORT1 P1L7 CTRAP P1L 6 COUT63 P1L 5 COUT62 P1L 4 CC62 P1L P1L 3 COUT61 P1L 2 CC61 P1L 1 COUT60 P1L 0 CC60 General Purpose CAPCOM Fast External Timer Input Output Inputs Outputs Interrupt Inputs Input Figure 7 6 PORTI1 IO and Alternate Functions Semiconductor Group 7 10 Version 1 0 11 97 SIEMENS Parallel Ports C164CI The figure below shows the structure of a PORT1 pin 00535 s OH 5 N c UJ Write DP1H y DP1L y T 9 1 m MUX irection Latch g Read DP1H y DP1L y Alternate Function a Enable Wri
299. ister banks in the internal memory while optimizing the remaining RAM for user data The CPU disposes of an actual register context consisting of up to 16 wordwide and or bytewide GPRs which are physically located within the on chip RAM area A Context Pointer CP register determines the base address of the active register bank to be accessed by the CPU at a time The number of register banks is only restricted by the available internal RAM space For easy parameter passing a register bank may overlap others A system stack of up to 1024 words is provided as a storage for temporary data The system stack is also located within the on chip RAM area and it is accessed by the CPU via the stack pointer SP register Two separate SFRs STKOV and STKUN are implicitly compared against the stack pointer value upon each stack access for the detection of a stack overflow or underflow Semiconductor Group 2 7 Version 1 0 11 97 SIEMENS Architectural Overview C164Cl Hardware detection of the selected memory space is placed at the internal memory decoders and allows the user to specify any address directly or indirectly and obtain the desired data without using temporary registers or special instructions For Special Function Registers 1024 Bytes of the address space are reserved The standard Special Function Register area SFR uses 512 bytes while the Extended Special Function Register area ESFR uses the other 512 bytes E SFRs are wordwide r
300. ister description for an explanation of the control fields O C1 iN wo D eo Semiconductor Group 12 14 Version 1 0 11 97 SIEMENS The Watchdog Timer WDT C164CI 13 The Watchdog Timer WDT To allow recovery from software or hardware failure the C164Cl provides a Watchdog Timer If the software fails to service this timer before an overflow occurs an internal reset sequence will be initiated This internal reset will also pull the RSTOUT pin low which also resets the peripheral hardware which might be the cause for the malfunction When the watchdog timer is enabled and the software has been designed to service it regularly before it overflows the watchdog timer will supervise the program execution as it only will overflow if the program does not progress properly The watchdog timer will also time out if a software error was due to hardware related failures This prevents the controller from malfunctioning for longer than a user specified time Note When the bidirectional reset is enabled also pin RSTIN will be pulled low for the duration of the internal reset sequence upon a watchdog timer reset The watchdog timer provides two registers a read only timer register that contains the current count and a control register for initialization and reset source detection Reset Indication Pin Data Registers Control Registers O seen WDTCON Figure 13 1 SFRs and Port Pins associated with the Watchdog Timer The wa
301. ite Configuration Control Set according to pin POH O during reset 0 Pins WR and BHE retain their normal function 1 Pin WR acts as WRL pin BHE acts as WRH CLKEN System Clock Output Enable CLKOUT 0 CLKOUT disabled pin may be used for general purpose IO 1 CLKOUT enabled pin outputs the system clock signal BYTDIS Disable Enable Control for Pin BHE Set according to data bus width 0 Pin BHE enabled 1 Pin BHE disabled pin may be used for general purpose IO ROMEN Internal ROM Enable Set according to pin EA during reset 0 Internal ROM disabled accesses to the ROM area use the external bus 1 Internal ROM enabled SGTDIS Segmentation Disable Enable Control 0 Segmentation enabled CSP and IP are saved restored during interrupt entry exit 1 Segmentation disabled Only IP is saved restored ROMS1 Internal ROM Mapping 0 Internal ROM area mapped to segment 0 00 0000 4 00 7 FF Fy 1 Internal ROM area mapped to segment 1 01 0000 01 7FFFj STKSZ System Stack Size Selects the size of the system stack in the internal RAM from 32 to 1024 words Note Register SYSCON cannot be changed after execution of the EINIT instruction The function of bits XPER SHARE VISIBLE WRCFG BYTDIS ROMEN and ROMS is described in more detail in chapter The External Bus Controller Semiconductor Group 4 12 Version 1 0 11 97 SIEMENS The Central Processing Unit CPU C164Cl System Clock Output Enable CLKEN The system clock
302. itfield T3l in control register T3CON selects the triggering transitions see table below In this mode the sequence of the transitions of the two input signals is evaluated and generates count pulses as well as the direction signal So T3 is modified automatically according to the speed and the direction of the incremental encoder and its contents therefore always represent the encoder s current position GPT1 Core Timer T3 Incremental Interface Mode Input Edge Selection T3I Triggering Edge for Counter Increment Decrement 000 None Counter T3 stops 001 Any transition rising or falling edge on T3IN 010 Any transition rising or falling edge on T3EUD 011 Any transition rising or falling edge on any T3 input T3IN or T3EUD 1XX Reserved Do not use this combination Semiconductor Group 10 8 Version 1 0 11 97 The General Purpose Timer Unit SIEMENS C164CI The incremental encoder can be connected directly to the C164Cl without external interface logic In a standard system however comparators will be employed to convert the encoder s differential outputs eg A A to digital signals eg A This greatly increases noise immunity Note The third encoder output TopO which indicates the mechanical zero position may be connected to an external interrupt input and trigger a reset of timer T3 eg via PEC transfer from ZEROS T3input T3input x Qo ne o o c LL Interrupt Fig
303. ither selected during the initialization phase or repeatedly during program execution there are some features that must be selected earlier because they are used for the first access of the program execution eg internal or external start selected via EA These selections are made during reset via the pins of PORTO and pin RD which are read at the end of the internal reset sequence During reset internal pullup devices are active on the PORTO lines and on RD so their input level is high if the respective pin is left open or is low if the respective pin is connected to an external pulldown device With the coding of the selections as shown below in many cases the default option ie high level can be used The value on the upper byte of PORTO POH is latched into register RPOH upon reset the value on the lower byte POL directly influences the BUSCONO register bus mode or the internal control logic of the C164Cl H 7 H6 H5 H4 H3 H2 H1 H0O L7 L6 L5 L4 L3 L2 LA LO CLKCFG SALSEL CSSEL BUSTYP aor emu a ae o3 x Internal Control Logic Only on hardware reset Clock Port 4 Port 4 Generator Logic Logic SYSCON Figure 20 4 PORTO Configuration during Reset BUSCONO Semiconductor Group 20 8 Version 1 0 11 97 SIEMENS System Reset C164CI The pins that control the operation of the internal control logic and the reserved pins are evaluated only during a hardware triggered reset sequence The pins
304. itive and a negative external transition can be selected to cause an interrupt or PEC service request The edge selection is performed in the control register of the peripheral device associated with the respective port pin The peripheral must be programmed to a specific operating mode to allow generation of an interrupt by the external signal The priority of the interrupt request is determined by the interrupt control register of the respective peripheral interrupt source and the interrupt vector of this source will be used to service the external interrupt request Note In order to use any of the listed pins as external interrupt input it must be switched to input mode via its direction control bit DPx y in the respective port direction control register DPx Pins to be used as External Interrupt Inputs Port Pin Original Function Control Register P1H 3 0 EX3 0IN Fast external interrupt input pin EXICON P1H 7 4 CC27 2410 CAPCOM Register 27 24 Capture Input CC27 CC24 P8 3 0 CC19 1610 CAPCOM Register 19 16 Capture Input CC19 CC16 P5 6 T2IN Auxiliary timer T2 input pin T2CON P5 7 T4IN Auxiliary timer T4 input pin T4CON When port pins CCxlO are to be used as external interrupt input pins bit field CCMODx in the control register of the corresponding capture compare register CCx must select capture mode When CCMODx is programmed to 001g the interrupt request flag CCxIR in register CCxIC will be set on a positive exte
305. l Register CC16 19 CAPCOM2 Register 16 19 DPx Port x Direction Control Register CC24 27 CAPCOM2 Register 24 27 Px Port x Data Register CCM4 CAPCOM2 Mode Control Register 4 TxREL CAPCONM Timer x Reload Register CCM6 CAPCOM2 Mode Control Register 6 Tx CAPCONM Timer x Register T78CON CAPCOM2 Timers T7 and T8 Control Register CC16 19ICCAPCOM2 Interrupt Control Register 16 19 TxIC CAPCOM Timer x Interrupt Control Register CC24 27IC CAPCOM2 Interrupt Control Register 24 27 Figure 16 1 SFRs and Port Pins associated with the CAPCOM Units Semiconductor Group 16 1 Version 1 0 11 97 SIEMENS The Capture Compare Unit CAPCOM2 C164Cl The CAPCOM2 unit is typically used to handle high speed IO tasks such as pulse and waveform generation pulse width modulation or recording of the time at which specific events occur It also allows the implementation of up to 8 software timers The maximum resolution of the CAPCOM2 unit is 8 CPU clock cycles 216 TCL The CAPCOM2 unit consists of two 16 bit timers T7 T8 each with its own reload register TxREL and a bank of eight dual purpose 16 bit capture compare registers CC 16 through CC24 and CC24 through CC27 The input clock for the CAPCOM timers is programmable to several prescaled values of the CPU clock or it can be derived from an overflow underflow of timer T3 in block GPT1 T7 may also operate in counter mode from an external input where it can be clocked by external e
306. lag can be altered by instructions which perform ALU or data movement operations The E flag is cleared by those instructions which cannot be reasonably used for table search operations In all other cases the E flag is set depending on the value of the source operand to signify whether the end of a search table is reached or not If the value of the source operand of an instruction equals the lowest negative number which is representable by the data format of the corresponding instruction 8000 for the word data type or 804 for the byte data type the E flag is set to 1 otherwise it is cleared MULIP Flag The MULIP flag will be set to 1 by hardware upon the entrance into an interrupt service routine when a multiply or divide ALU operation was interrupted before completion Depending on the state of the MULIP bit the hardware decides whether a multiplication or division must be continued or not after the end of an interrupt service The MULIP bit is overwritten with the contents of the stacked MULIP flag when the return from interrupt instruction RETI is executed This normally means that the MULIP flag is cleared again after that Note The MULIP flag is a part of the task environment When the interrupting service routine does not return to the interrupted multiply divide instruction ie in case of a task scheduler that switches between independent tasks the MULIP flag must be saved as part of the task environment and must be updated
307. lator providing an inverter and a feedback element Pins XTAL1 and XTAL2 connect the inverter to the external crystal The standard external oscillator circuitry see figure below comprises the crystal two low end capacitors and series resistor Rx2 to limit the current through the crystal The additional LC combination is only required for 3rd overtone crystals to suppress oscillation in the fundamental mode A test resistor Ro may be temporarily inserted to measure the oscillation allowance of the oscillator circuitry XTAL1 XTAL2 Rx2 Hk Figure 6 2 External Oscillator Circuitry The on chip oscillator is optimized for an input frequency range of 1 to 16 MHz An external clock signal eg from an external oscillator or from a master device may be fed to the input XTAL1 The Pierce oscillator then is not required to support the oscillation itself but is rather driven by the input signal In this case the input frequency range may be 0 to 50 MHz please note that the maximum applicable input frequency is limited by the device s maximum CPU frequency For input frequencies above 25 30 MHz the oscillator s output should be terminated as shown in the figure below at lower frequencies it may be left open This termination improves the operation of the oscillator by filtering out frequencies above the intended oscillator frequency XTAL1 XTAL2 3kQ Input clock Figure 6 3 Oscillator Output Termination N
308. le T12 is counting up the new value must be smaller than the current period value Otherwise no more matches will be detected and the output signals will not change any more If a compare value is written while T12 is counting down any value may be used Semiconductor Group 17 19 Version 1 0 11 97 SIEMENS The Capture Compare Unit CAPCOM6 C164Cl CTCON FF30 981 SFR Reset Value 10104 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CT13 ECT STE CT13 CT13 STE CT12 CT12 P 130 13 RES R CT13CLK CTM ETRP 12 RES R CT12CLK rw rw rw rw rw rw rw rw rw rw Bit Function CTnCLK Compare Timer Tn Input Clock Select Selects the input clock for timer T12 or T13 which is derived from the CPU clock fry 2 fopy 9 lt CTnCLk gt 000 fTx fcpu 111 ft 2 fcpu 128 CTnR Compare Timer Tn Run Bit CTnR starts and stops timer Tn T12 or T13 Together with bit CTnRES it controls Tn s operation see function table below 0 Timer Tn stops counting If bit CTnRES 1 timer Tn is cleared and the compare outputs are set to their defined idle state 1 Timer Tn starts counting from its current value CTnRES Compare Timer Tn Reset Control 0 No effect on timer Tn when it is stopped 1 Timer Tn is cleared when it is stopped and the compare outputs are set to their defined idle state Note for capture mode T12 only Clearing CT12R after a capture event while CT12RES 1 will destroy the value stored in the capture register CC
309. le for using the appropriate instructions when popping data from the specific user stack No hardware detection of overflow or underflow of a user stack is provided The following addressing modes allow implementation of user stacks Rw Rb or Rw Rw Pre decrement Indirect Addressing Used to push one byte or word onto a user stack This mode is only available for MOV instructions and can specify any GPR as the user stack pointer Rb Rw or Rw Rw Post increment Index Register Indirect Addressing Used to pop one byte or word from a user stack This mode is available to most instructions but only GPRs RO R3 can be specified as the user stack pointer Rb Rw or Rw Rw Post increment Indirect Addressing Used to pop one byte or word from a user stack This mode is only available for MOV instructions and can specify any GPR as the user stack pointer 22 2 Register Banking Register banking provides the user with an extremely fast method to switch user context A single machine cycle instruction saves the old bank and enters a new register bank Each register bank may assign up to 16 registers Each register bank should be allocated during coding based on the needs of each task Once the internal memory has been partitioned into a register bank space internal stack space and a global internal memory area each bank pointer is then assigned Thus upon entry into a new task the appropriate bank pointer is used as the operand fo
310. level that will be serviced Any request on the same or a lower level will not be acknowledged The current CPU priority level may be adjusted via software to control which interrupt request sources will be acknowledged PEC transfers do not really interrupt the CPU but rather steal a single cycle so PEC services do not influence the ILVL field in the PSW Hardware traps switch the CPU level to maximum priority ie 15 so no interrupt or PEC requests will be acknowledged while an exception trap service routine is executed Note The TRAP instruction does not change the CPU level so software invoked trap service routines may be interrupted by higher requests Interrupt Enable bit IEN globally enables or disables PEC operation and the acceptance of interrupts by the CPU When IEN is cleared no new interrupt requests are accepted by the CPU Requests that already have entered the pipeline at that time will process however When IEN is set to 1 all interrupt sources which have been individually enabled by the interrupt enable bits in their associated control registers are globally enabled Note Traps are non maskable and are therefore not affected by the IEN bit Semiconductor Group 5 9 Version 1 0 11 97 Interrupt and Trap Functions C164Cl SIEMENS 5 2 Operation of the PEC Channels The C164Cl s Peripheral Event Controller PEC provides 8 PEC service channels which move a single byte or word between two locations in s
311. ligent Memory The Intelligent Memory CAM RAM Array provides storage for up to 15 message objects of maximum 8 data bytes length Each of these objects has a unique identifier and its own set of control and status bits After the initial configuration the Intelligent Memory can handle the reception and transmission of data without further CPU actions Organization of Registers and Message Objects All registers and message objects of the CAN controller are located in the special CAN address area of 256 bytes which is mapped into segment 0 and uses addresses 00 EF 00 through 00 EFFF All registers are organized as 16 bit registers located on word addresses However all registers may be accessed bytewise in order to select special actions without effecting other mechanisms Note The address map shown below lists the registers which are part of the CAN controller There are also C164CI specific registers that are associated with the CAN Module These registers however control the access to the CAN Module rather than its function Semiconductor Group 19 4 Version 1 0 11 97 SIEMENS The On Chip CAN Interface C164CI General Registers Control Status EFOO i Register Message Object 1 F02 Message Object 2 ierit EFO2y Message Object 3 Register Message Object 4 Bit Timing EF04g Register Message Object 5 Message Object 6 Global Mask EF064 Short Message Object 7 Message Object 8 EF08 Message Object 9
312. lock Control allows the adaptation of transmit and receive behaviour of the SSC to a variety of serial interfaces A specific clock edge rising or falling is used to shift out transmit data while the other clock edge is used to latch in receive data Bit SSCPH selects the leading edge or the trailing edge for each function Bit SSCPO selects the level of the clock line in the idle state So for an idle high clock the leading edge is a falling one a 1 to 0 transition The figure below is a summary Serial Clock SSCPO SSCPH SCLK Mr IA A Kk oe CX X X MTSR MRST First Last Bit z Transmit Data Bit Latch Data MCD01960 Shift Data Figure 12 3 Serial Clock Phase and Polarity Options Semiconductor Group 12 5 Version 1 0 11 97 SIEM ENS The High Speed Synchronous Serial Interface C164CI 12 1 Full Duplex Operation The different devices are connected through three lines The definition of these lines is always determined by the master The line connected to the master s data output pin MTSR is the transmit line the receive line is connected to its data input line MRST and the clock line is connected to pin SCLK Only the device selected for master operation generates and outputs the serial clock on pin SCLK All slaves receive this clock so their pin SCLK must be switched to input mode DP3 13 0 The output of the master s shift register is connected to the external transmit line which in turn
313. lock cycles Also shorter RSTIN pulses may trigger a hardware reset if they coincide with the latch s sample point However it is recommended to keep RSTIN low for ca 1 ms After the reset sequence has been completed the RSTIN input is sampled When the reset input signal is active at that time the internal reset condition is prolonged until RSTIN gets inactive During a hardware reset the PORTO inputs for the reset configuration need some time to settle on the required levels especially if the hardware reset aborts a read operation from an external peripheral During this settling time the configuration may intermittently be wrong Note Shorter reset pulses are internally extended until the on chip PLL has locked The input RSTIN provides an internal pullup device equalling a resistor of 50 KQ to 150 KO the minimum reset time must be determined by the lowest value Simply connecting an external capacitor is sufficient for an automatic power on reset see b in figure above RSTIN may also be connected to the output of other logic gates see a in figure above See also section Bidirectional Reset in this case Note A power on reset requires an active time of two reset sequences 1036 CPU clock cycles after a stable clock signal is available about 10 50 ms to allow the on chip oscillator to stabilize Software Reset The reset sequence can be triggered at any time via the protected instruction SRST Software Reset This instru
314. lock signal while the CPU clock signal is derived directly from the oscillator clock or via prescaler Also no interrupt request will be generated in case of a missing oscillator clock Note Atthe end of any reset bit OWDDIS reflects the inverted level of pin RD at that time Thus the oscillator watchdog may also be disabled via hardware by externally pulling the RD line low upon a reset similar to the standard reset configuration via PORTO Semiconductor Group 6 8 Version 1 0 11 97 SIEMENS Clock Generation C164CI 6 4 Clock Drivers The operating clock signal fcpy is distributed to the controller hardware via several clock drivers which are disabled under certain circumstances The real time clock RTC is clocked via a separate clock driver which delivers the prescaled oscillator clock contrary to the other clock drivers The table below summarizes the different clock drivers and their function especially in power reduction modes Clock Drivers Description Clock Driver Clock Active Idle P Down Connected Circuitry Signal mode mode mode CCD fcpy ON Off Off CPU memory modules CPU Clock Driver ICD fopy ON ON Off ASCO WDT SSC Interface interrupt detection circuitry Clock Driver PCD fcpu Control via Control via Off X Peripherals timers etc Peripheral PCDDIS PCDDIS except ICD Clock Driver interrupt controller ports RCD fosc ON ON Control via Realtime clock RTC PDCON Clock D
315. lock the auxiliary timer this concatenation forms a 32 bit or a 33 bit timer counter 32 bit Timer Counter If both a positive and a negative transition of TSOTL is used to clock the auxiliary timer this timer is clocked on every overflow underflow of the core timer T3 Thus the two timers form a 32 bit timer 33 bit Timer Counter If either a positive or a negative transition of T3OTL is selected to clock the auxiliary timer this timer is clocked on every second overflow underflow of the core timer T3 This configuration forms a 33 bit timer 16 bit core timer T3OTL 16 bit auxiliary timer The count directions of the two concatenated timers are not required to be the same This offers a wide variety of different configurations T3 can operate in timer gated timer or counter mode in this case Tyl CPU Interrupt Clock LE Core Timer Ty TyIR Reanest TyR Up Down Ds e ECT en MCB02034 Edge Select Lu XC Auxiliary Timer Tx dee ji TxR Txl Figure 10 11 Concatenation of Core Timer T3 and an Auxiliary Timer Semiconductor Group 10 14 Version 1 0 11 97 SIEM ENS The General Purpose Timer Unit C164Cl Auxiliary Timer in Reload Mode Reload mode for the auxiliary timers T2 and T4 is selected by setting bit field TxM in the respective register TXCON to 100 In reload mode the core timer T3 is reloaded with the contents of an auxiliary timer register triggered by one of two different sign
316. low transition on the dedicated external NMI pin Non Maskable Interrupt is detected the NMI flag in register TFR is set and the CPU will enter the NMI trap routine The IP value pushed on the system stack is the address of the instruction following the one after which normal processing was interrupted by the NMI trap Note The NMI pin is sampled with every CPU clock cycle to detect transitions Stack Overflow Trap Whenever the stack pointer is decremented to a value which is less than the value in the stack overflow register STKOV the STKOF flag in register TFR is set and the CPU will enter the stack overflow trap routine Which IP value will be pushed onto the system stack depends on which operation caused the decrement of the SP When an implicit decrement of the SP is made through a PUSH or CALL instruction or upon interrupt or trap entry the IP value pushed is the address of the following instruction When the SP is decremented by a subtract instruction the IP value pushed represents the address of the instruction after the instruction following the subtract instruction For recovery from stack overflow it must be ensured that there is enough excess space on the stack for saving the current system state PSW IP in segmented mode also CSP twice Otherwise a system reset should be generated Semiconductor Group 5 27 Version 1 0 11 97 SIEMENS Interrupt and Trap Functions C164CI Stack Underflow Trap Whenever the stack pointe
317. ltaneously for both register CCx and register CCz of the register pair pin CCxIO will be toggled only once but two separate compare interrupt requests will be generated one for vector CCxINT and one for vector CCzINT In order to use the respective port pin as compare signal output pin CCxIO for compare register CCx in double register compare mode this port pin must be configured as output ie the corresponding direction control bit must be set to 1 With this configuration the output pin has the same characteristics as in compare mode 1 Semiconductor Group 16 17 Version 1 0 11 97 SIEMENS The Capture Compare Unit CAPCOM2 C164Cl Interrupt CCxIR Request Compare Reg CCx Input Interrupt 2 Port Clock CAPCOM Timer Ty TR H Request Ue ems MES coxo gt CCxIO Mode 0 CCMODz Interrupt gt CCzIR Request MCBO2022 o Y A Compare Reg CCz Figure 16 10 Double Register Compare Mode Block Diagram In this configuration example the same timer allocation was chosen for both compare registers but each register may also be individually allocated to one of the two timers of the respective CAPCOM unit In the timing example for this compare mode below the compare values in registers CCx and CCz are not modified Note The pins CCzlO which do not serve for double register compare mode may be used for general purpose IO Semiconductor Group 16 18 Version 1 0 11 9
318. m the start so the initialization routine can directly access all locations without prior programming The required pins of Port 4 are automatically switched to address output mode SALSEL Segment Address Lines Directly accessible Address Space 11 Two A17 A16 256 KByte Default without pull downs 10 Six A21 A16 4 MByte Maximum 01 None 64 KByte Minimum 00 Four A19 A16 1 MByte Even if not all segment address lines are enabled on Port 4 the C164Cl internally uses its complete 24 bit addressing mechanism This allows the restriction of the width of the effective address bus while still deriving CS signals from the complete addresses Default 2 bit segment address A17 A16 allowing access to 256 KByte Note The selected number of segment address lines cannot be changed via software after reset Semiconductor Group 20 12 Version 1 0 11 97 SIEMENS System Reset C164CI Clock Generation Control Pins POH 7 POH 6 and POH 5 CLKCFG select the basic clock generation mode during reset The oscillator clock either directly feeds the CPU and peripherals direct drive it is divided by 2 or it is fed to the on chip PLL which then provides the CPU clock signal selectable multiple of the oscillator frequency ie the input frequency These bits are latched in register RPOH P0 15 13 CPU Frequency External Clock Input Notes POH 7 5 fcpu fxraL F Range T o4
319. mers except for external input T78CON FF20 901 SFR Reset Value 00004 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Function Txl Timer Counter x Input Selection Timer Mode TxM 0 Input Frequency fopy 2 0 9 See also table below for examples Counter Mode TxM 1 000 Overflow Underflow of GPT1 Timer 3 001 Positive rising edge on pin T7IN 010 Negative falling edge on pin T7IN 011 Any edge rising and falling on pin T7IN 1XX Reserved TxM Timer Counter x Mode Selection 0 Timer Mode Input derived from internal clock 1 Counter Mode Input from External Input or T3 TxR Timer Counter x Run Control 0 Timer Counter x is disabled 1 Timer Counter x is enabled This selection is available for timer T7 Timer T8 will stop at this selection The timer run flags T7R and T8R allow for enabling and disabling the timers The following description of the timer modes and operation always applies to the enabled state of the timers ie the respective run flag is assumed to be set to 1 In all modes the timers are always counting upward The current timer values are accessible for the CPU in the timer registers Tx which are non bitaddressable SFRs When the CPU writes to a register Tx in the state immediately before the respective timer increment or reload is to be performed the CPU write operation has priority and the increment or reload is disabled to guarantee co
320. miconductor Group 18 6 Version 1 0 10 97 SIEMENS The Analog Digital Converter C164CI Channel Injection Mode Channel Injection Mode allows the conversion of a specific analog channel also while the ADC is running in a continuous or auto scan mode without changing the current operating mode After the conversion of this specific channel the ADC continues with the original operating mode Channel Injection mode is enabled by setting bit ADCIN in register ADCON and requires the Wait for ADDAT Read Mode ADWR 1 The channel to be converted in this mode is specified in bitfield CHNR of register ADDAT2 Note Bitfield CHNR in ADDAT2 is not modified by the A D converter but only the ADRES bit field Since the channel number for an injected conversion is not buffered bitfield CHNR of ADDAT2 must never be modified during the sample phase of an injected conversion otherwise the input multiplexer will switch to the new channel It is recommended to only change the channel number with no injected conversion running i xX Ex x2 x 3 x 4 Conversion of Channel v Write ADDAT x 1 8x 4x1 x 2 x 3 x 4 ADDAT Full Lo Mo O Le Em Read ADDAT x 1 x x 1 x 2 x 3 x 4 Injected er Channel Injection i Pine Request by CC31 y Write ADDAT2 ADDAT2 Full Int Request ADEINT Read ADDAT2 MCA01971 Figure 18 5 Channel Injection Example A channel injection can be triggered in two ways set
321. miconductor Group 19 6 Version 1 0 11 97 SIEMENS The On Chip CAN Interface C164Cl Bit Function Status Bits LEC Last Error Code This field holds a code which indicates the type of the last error occurred on the CAN bus If a message has been transferred reception or transmission without error this field will be cleared Code 7 is unused and may be written by the CPU to check for updates 0 No Error 1 Stuff Error More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed 2 Form Error A fixed format part of a received frame has the wrong format 3 AckError The message this CAN controller transmitted was not acknowledged by another node 4 Bit1Error During the transmission of a message with the exception of the arbitration field the device wanted to send a recessive level 1 but the monitored bus value was dominant 5 BitOError During the transmission of a message or acknowledge bit active error flag or overload flag the device wanted to send a dominant level 0 but the monitored bus value was recessive During busoff recovery this status is set each time a sequence of 11 recessive bits has been monitored This enables the CPU to monitor the proceeding of the busoff recovery sequence indicating the bus is not stuck at dominant or continously disturbed 6 CRCError The CRC check sum was incorrect in the message received T
322. mission and reception of CAN frames in accordance with the CAN specification V2 0 part B active ie the on chip CAN Module can receive and transmit standard frames with 11 bit identifiers as well as extended frames with 29 bit identifiers The module provides Full CAN functionality on up to 15 message objects Message object 15 may be configured for Basic CAN functionality Both modes provide separate masks for acceptance filtering which allows to accept a number of identifiers in Full CAN mode and also allows to disregard a number of identifiers in Basic CAN mode All message objects can be updated independent from the other objects and are equipped for the maximum message length of 8 bytes The bit timing is derived from the XCLK and is programmable up to a data rate of 1 MBaud The CAN Module uses two pins to interface to a bus transceiver Semiconductor Group 2 11 Version 1 0 11 97 SIEMENS Architectural Overview C164Cl General Purpose Timer GPT Unit The GPT1 unit represents a very flexible multifunctional timer counter structure which may be used for many different time related tasks such as event timing and counting pulse width and duty cycle measurements pulse generation or pulse multiplication Each timer may operate independently in a number of different modes or may be concatenated with another timer of the same module Each timer can be configured individually for one of four basic modes of operation which are Timer
323. mory Organization C164Cl 5O0ns ADDR OTP Word Address i 15nSs_ i 50ns RD 10pus Vpp y SVpp The special signals CE and RSEL must fulfill the same timing requirements as the address lines All timings represent minimum values Figure 3 6 OTP Verify Read Cycle The programming cycles can be controlled in two different ways In External Host Mode EHM the C164CI is put into emulation mode where the CPU and the generic peripherals are disabled The on chip OTP memory can be accessed by an external master via the C164Cl s bus interface The bus interface signals change their direction in this mode In CPU Host Mode CHM the CPU of the C164CI itself controls the programming cycles via the OTP programming interface The programming routine must be fetched from outside the OTP memory eg IRAM or external memory Selecting an OTP Programming Mode Both programming modes can only be enabled via reset configuration External Host Mode is enabled by selecting emulation mode POL O 0 and also pulling low pin POL 5 Pins POL 5 0 represent 01 1110 in this case CPU Host Mode is enabled by pulling low pin POL 2 in either standard startup mode or in bootstrap loader mode Pins POL 5 0 here represent 11 1011 standard or 10 1011 BSL Note When CHM is enabled in standard startup mode program execution will always begin out of external memory disregarding the level on pin EA Vpp When CHM is
324. mory is disabled enabled or remapped the DPPs must be explicitly re loaded to enable correct data accesses to the internal and or external memory Semiconductor Group 22 15 Version 1 0 11 97 SIEMENS The Register Set C164CI 23 The Register Set This section summarizes all registers which are implemented in the C164Cl and explains the description format which is used in the chapters describing the function and layout of the SFRs For easy reference the registers are ordered according to two different keys except for GPRs Ordered by address to check which register a given address references Ordered by register name to find the location of a specific register Register Description Format In the respective chapters the function and the layout of the SFRs is described in a specific format which provides a number of details about the described special function register The example below shows how to interpret these details A word register looks like this REG NAME oo ae E SFR Reset Value 14 11 write read only only Bit Function bit field name Explanation of bit field name Description of the functions controlled by this bit field A byte register looks like this REG NAME A16 A8 E SFR Reset Value j Elements REG NAME Name of this register A16 A8 Long 16 bit address Short 8 bit address SFR ESFR XRegRegister space SFR ESFR or External XBUS Register idle aon R
325. n SYSCON RPOH CPU Status Indication and Control PSW Code Access Control IP CSP Data Paging Control DPPO DPP1 DPP2 DPP3 GPRs Access Control CP System Stack Access Control SP STKUN STKOV Multiply and Divide Support MDL MDH MDC ALU Constants Support ZEROS ONES Semiconductor Group 4 2 Version 1 0 11 97 SIEMENS The Central Processing Unit CPU C164Cl 4 1 Instruction Pipelining The instruction pipeline of the C164Cl partitiones instruction processing into four stages of which each one has its individual task 1st gt FETCH In this stage the instruction selected by the Instruction Pointer IP and the Code Segment Pointer CSP is fetched from either the internal ROM internal RAM or external memory 2nd DECODE In this stage the instructions are decoded and if required the operand addresses are calculated and the respective operands are fetched For all instructions which implicitly access the system stack the SP register is either decremented or incremented as specified For branch instructions the Instruction Pointer and the Code Segment Pointer are updated with the desired branch target address provided that the branch is taken 3rd 5EXECUTE In this stage an operation is performed on the previously fetched operands in the ALU Additionally the condition flags in the PSW register are updated as specified by the instruction All explicit writes to the SFR memory space
326. n semaphore support Call Instructions Conditional calling of an either absolutely or indirectly addressed subroutine within the current code segment Unconditional calling of a relatively addressed subroutine within the current code segment Unconditional calling of an absolutely addressed subroutine within any code segment Unconditional calling of an absolutely addressed subroutine within the current code segment plus an additional pushing of a selectable register onto the system stack Unconditional branching to the interrupt or trap vector jump table in code segment 0 Return Instructions Returning from a subroutine within the current code segment Returning from a subroutine within any code segment Returning from a subroutine within the current code segment plus an additional popping of a selectable register from the system stack Returning from an interrupt service routine Semiconductor Group 24 3 JMPA JMPI JMPR JMPS JB JNB JBC JNBS CALLA CALLI CALLR CALLS PCALL TRAP RET RETS RETP RETI Version 1 0 11 97 SIEMENS Instruction Set Summary C164Cl System Control Instructions Resetting the C164CIl via software SRST Entering the Idle mode IDLE Entering the Power Down mode PWRDN Servicing the Watchdog Timer SRVWDT Disabling the Watchdog Timer DISWDT Signifying the end of the initialization routine pulls pin RSTOUT high and dis
327. n 1 0 11 97 SIEMENS The Capture Compare Unit CAPCOM6 C164Cl 17 4 Center Aligned Mode The 3 capture compare channels associated with T12 may operate in center aligned mode The compare timer T12 counts up starting at 0000 When the timer contents match the respective compare value in register CC6x the associated output signal CC6x is switched to its active state while counting up Upon reaching the period value stored in register T12P the count direction is reversed and the timer counts down When the timer contents match the respective compare value in register CC6x the associated output signal CC6x is switched to its passive state while counting down The output signals COUT6x are switched upon matches of register CC6x with T12 T12OF Non zero offset values shift the COUT6x edges symmetrically against the CC6x edges see figure below This allows the generation of non overlapping signal pairs CC6x COUT6x with arbitrary active levels These signal pairs may eg be used to drive the high and low side switches of a power bridge without the risk of a branch shortcut prevented by the programmable dead time torr see figure below Count Value CT1 CT1OFF A 9 CCP 7 Period Reg CT1OF 2 Offset Reg 0 0 Start of CT1 go Ds OFF OFF OFF Cycles CCx CC 5 o COINI Bit 0 29 COUTx CC 5 COINI Bit
328. n compare mode 2 Contents of Ty FFFF y Compare Value cv2 Compare Value cv1 Reload Value lt TyREL gt 0000 H Interrupt Requests TyIR CCxIR TyIR CCxIR TyIR State of COxlO 1 NO ee EMEN ud t Event 1 Event 2 CCx cv2 CCx cv1 MCT02021 Figure 16 9 Timing Example for Compare Modes 2 and 3 Semiconductor Group 16 15 Version 1 0 11 97 SIEMENS The Capture Compare Unit CAPCOM2 C164Cl Compare Mode 3 Compare mode 3 is selected for register CCx by setting bit field CCMODx of the corresponding mode control register to 111g In compare mode 3 only one compare event will be generated per timer period When the first match within the timer period is detected the interrupt request flag CCxIR is set to 1 and also the output pin CCxIO alternate port function will be set to 1 The pin will be reset to 0 when the allocated timer overflows If a match was found for register CCx in this mode all further compare events during the current timer period are disabled for CCx until the corresponding timer overflows If after a match was detected the compare register is reloaded with a new value this value will not become effective until the next timer period In order to use the respective port pin as compare signal output pin COxlO for compare register CCx in compare mode 3 this port pin must be configured as output ie the corresponding direction control bit must be
329. n is selected when the respective PORTO lines are at a high level Through pulling individual lines to a low level this default can be changed according to the needs of the applications The internal pullup devices are designed such that an external pulldown resistors see Data Sheet specification can be used to apply a correct low level These external pulldown resistors can remain connected to the PORTO pins also during normal operation however care has to be taken such that they do not disturb the normal function of PORTO this might be the case for example if the external resistor is too strong With the end of reset the selected bus configuration will be written to the BUSCONO register The configuration of the high byte of PORTO will be copied into the special register RPOH This read only register holds the selection for the number of chip selects and segment addresses Software can read this register in order to react according to the selected configuration if required When the reset is terminated the internal pullup devices are switched off and PORTO will be switched to the appropriate operating mode During external accesses in multiplexed bus modes PORTO first outputs the 16 bit intra segment address as an alternate output function PORTO is then switched to high impedance input mode to read the incoming instruction or data In 8 bit data bus mode two memory cycles are required for word accesses the first for the low byte and th
330. n its internal resistance The time that the two different actions during conversion take sampling and converting can be programmed within a certain range in the C164CI relative to the CPU clock The absolute time that is consumed by the different conversion steps therefore is independent from the general speed of the controller This allows adjusting the A D converter of the C164Cl to the properties of the system Fast Conversion can be achieved by programming the respective times to their absolute possible minimum This is preferable for scanning high frequency signals The internal resistance of analog source and analog supply must be sufficiently low however High Internal Resistance can be achieved by programming the respective times to a higher value or the possible maximum This is preferable when using analog sources and supply with a high internal resistance in order to keep the current as low as possible The conversion rate in this case may be considerably lower however The conversion times are programmed via the upper four bits of register ADCON Bitfield ADCTC conversion time control selects the basic conversion clock used for the operation of the A D converter The sample time is derived from this conversion clock and is selected by bitfield ADSTC sample time control The table below lists the possible combinations The timings refer to CPU clock cycles where tcpy 1 fcpy The limit values for fac see data sheet must
331. n the 4 5 6 phase Multi Channel PWM modes NMCS is reset by hardware in the next clock cycle after it has been set ESMC Enable Software Controlled Multi Channel PWM Modes Defines the follower state selection in the 4 5 6 phase multi channel PWM modes 0 Follower state selection controlled by compare timer T12 1 Follower state selection controlled by bit NMCS software control Semiconductor Group 17 24 Version 1 0 11 97 SIEMENS The Capture Compare Unit CAPCOM6 C164Cl CC6MIC FF36 9By SFR Reset Value 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Function CCnREN Capture Compare Rising Edge Interrupt Enable 0 Rising edge interrupt disabled 1 An interrupt from request flag CCnR is enabled CCnFEN Capture Compare Falling Edge Interrupt Enable 0 Falling edge interrupt disabled 1 An interrupt from request flag CCnF is enabled ECTC Enable Timer T12 Count Direction Change Interrupt 0 Count direction change interrupt disabled 1 Aninterrupt from request flag CT12FC is enabled Note No effect in edge aligned mode ECTP Enable Timer T12 Period Interrupt 0 Period interrupt disabled 1 Aninterrupt from request flag CT12FP is enabled CCnR Capture Compare Rising Edge Interrupt Flag 0 Idle 1 The interrupt request flag is set in capture mode upon a rising edge at the corresponding CC6n input in compare mode when T12 matches compare register CC6n while counting up
332. n the auxiliary timers T2 and T4 are programmed to timer mode or gated timer mode their operation is the same as described for the core timer T3 The descriptions figures and tables apply accordingly with one exception There is no output toggle latch for T2 and T4 Timers T2 and T4 in Incremental Interface Mode When the auxiliary timers T2 and T4 are programmed to incremental interface mode their operation is the same as described for the core timer T3 The descriptions figures and tables apply accordingly Semiconductor Group 10 12 Version 1 0 11 97 SIEM ENS The General Purpose Timer Unit C164Cl Timers T2 and T4 in Counter Mode Counter mode for the auxiliary timers T2 and T4 is selected by setting bit field TxM in the respective register TxCON to 001g In counter mode timers T2 and T4 can be clocked either by a transition at the respective external input pin TxIN or by a transition of timer T3 s output toggle latch TSOTL Edge Select uj 2c Auxiliary Timer Tx Web P3 5 T TR Upi T4 Down TxUD 0 MUX TxEUD EXOR 1 P5 15 P5 14 TxUDE x 2 4 MCB02221 Figure 10 10 Block Diagram of an Auxiliary Timer in Counter Mode The event causing an increment or decrement of a timer can be a positive a negative or both a positive and a negative transition at either the respective input pin or at the toggle latch T3OTL Bit field Txl in the respective control register TxCON selects the triggering transition
333. n the received frame is moved to SORBUF While the task of the receive interrupt handler is quite clear the transmitter is serviced by two interrupt handlers This provides advantages for the servicing software For single transfers is is sufficient to use the transmitter interrupt SOTIR which indicates that the previously loaded data has been transmitted except for the last bit of an asynchronous frame For multiple back to back transfers it is necessary to load the following piece of data at last until the time the last bit of the previous frame has been transmitted In asynchronous mode this leaves just one bit time for the handler to respond to the transmitter interrupt request in synchronous mode it is impossible at all Using the transmit buffer interrupt SOTBIR to reload transmit data gives the time to transmit a complete frame for the service routine as SOTBUF may be reloaded while the previous data is still being transmitted Idle Synchronous Mode SORIR ORIR ORIR Figure 11 6 ASCO Interrupt Generation As shown in the figure above SOTBIR is an early trigger for the reload routine while SOTIR indicates the completed transmission Software using handshake therefore should rely on SOTIR at the end of a data block to make sure that all data has really been transmitted Semiconductor Group 11 13 Version 1 0 11 97 SIEM ENS The High Speed Synchronous Serial Interface C164CI 12 The High Speed Synchrono
334. nation of compare modes additionally allows the implementation of a double register compare mode When capture or compare operation is disabled for one of the CCx registers it may be used for general purpose variable storage The functions of the 8 capture compare registers are controlled by 2 bitaddressable 16 bit mode control registers named CCM4 and CCM6 which are organized identically see description below Each register contains bits for mode selection and timer allocation of four capture compare registers Capture Compare Mode Registers for the CAPCOM2 Unit CCM4 ii 91 pi SFR Reset Value ud 14 ee Pe ee e mes up ul CCM6 uisu Md SFR Reset Value d 14 LECCE NC ceon P ceo Bit Function CCMODx Mode Selection for Capture Compare Register CCx The available capture compare modes are listed in the table below ACCx Allocation Bit for Capture Compare Register CCx 0 CCx allocated to Timer T7 1 CCx allocated to Timer T8 Semiconductor Group 16 9 Version 1 0 11 97 SIEMENS The Capture Compare Unit CAPCOM2 C164Cl Selection of Capture Modes and Compare Modes CCMODx Selected Operating Mode 000 Disable Capture and Compare Modes The respective CAPCOM register may be used for general variable storage 001 Capture on Positive Transition Rising Edge at Pin CCxlO 010 Capture on Negative Transition Falling Edge at Pin CCxlO 0 1 1 Capture on Positive and Negative Transi
335. nches to the system specific vector for the peripheral The PEC contains a set of SFRs which store the count value and control bits for eight data transfer channels In addition the PEC uses a dedicated area of RAM which contains the source and destination addresses The PEC is controlled similar to any other peripheral through SFRs containing the desired configuration of each channel An individual PEC transfer counter is implicitly decremented for each PEC service except forming in the continuous transfer mode When this counter reaches zero a standard interrupt is performed to the vector location related to the corresponding source PEC services are very well suited for example to move register contents to from a memory table The C164Cl has 8 PEC channels each of which offers such fast interrupt driven data transfer capabilities Memory Areas The memory space of the C164Cl is configured in a Von Neumann architecture which means that code memory data memory registers and IO ports are organized within the same linear address space which covers up to 16 MBytes The entire memory space can be accessed bytewise or wordwise Particular portions of the on chip memory have additionally been made directly bit addressable A 2 KByte 16 bit wide internal RAM provides fast access to General Purpose Registers GPRs user data variables and system stack The internal RAM may also be used for code A unique decoding scheme provides flexible user reg
336. nd interrupt vector The control register contains the interrupt request flag the interrupt enable bit and the interrupt priority of the associated source Each source request is then activated by one specific event depending on the selected operating mode of the respective device For efficient usage of the resources also multi source interrupt nodes are incorporated These nodes can be activated by several source requests eg as different kinds of errors in the serial interfaces However specific status flags which identify the type of error are implemented in the serial channels control registers Additional sharing of interrupt nodes is supported via the interrupt subnode control register ISNC see description below The C164CI provides a vectored interrupt system In this system specific vector locations in the memory space are reserved for the reset trap and interrupt service functions Whenever a request occurs the CPU branches to the location that is associated with the respective interrupt source This allows direct identification of the source that caused the request The only exceptions are the class B hardware traps which all share the same interrupt vector The status flags in the Trap Flag Register TFR can then be used to determine which exception caused the trap For the special software TRAP instruction the vector address is specified by the operand field of the instruction which is a seven bit trap number The reserved vect
337. ng instructions as shown in the following example In MOV SP 0FA40H select a new top of stack lad Dane must not be an instruction popping operands from the system stack Ineo POP RO pop word value from new top of stack into RO Note Conflicts with instructions writing to the stack PUSH CALL SCXT are solved internally by the CPU logic Semiconductor Group 4 6 Version 1 0 11 97 SIEMENS The Central Processing Unit CPU C164Cl e External Memory Access Sequences The effect described here will only become noticeable when watching the external memory access sequences on the external bus eg by means of a Logic Analyzer Different pipeline stages can simultaneously put a request on the External Bus Controller EBC The sequence of instructions processed by the CPU may diverge from the sequence of the corresponding external memory accesses performed by the EBC due to the predefined priority of external memory accesses ist Write Data 2nd Fetch Code 3rd Read Data Controlling Interrupts Software modifications implicit or explicit of the PSW are done in the execute phase of the respective instructions In order to maintain fast interrupt responses however the current interrupt prioritization round does not consider these changes ie an interrupt request may be acknowledged after the instruction that disables interrupts via IEN or ILVL or after the following instructions Timecritical instruction sequences the
338. nnel Input Selection ADM ADC Mode Selection 00 Fixed Channel Single Conversion 01 Fixed Channel Continuous Conversion 10 Auto Scan Single Conversion 11 Auto Scan Continuous Conversion ADST ADC Start Bit ADBSY ADC Busy Flag ADBSY 21 Aconversion is active ADWR ADC Wait for Read Control ADCIN ADC Channel Injection Enable ADCRQ ADC Channel Injection Request Flag ADSTC ADC Sample Time Control ADCTC ADC Conversion Time Control ADSTC and ADCTC control the conversion timing Refer to Conversion Timing Control Bit field ADCH specifies the analog input channel which is to be converted first channel of a conversion sequence in auto scan modes Bit field ADM selects the operating mode of the A D converter A conversion or a sequence is then started by setting bit ADST Clearing ADST stops the A D converter after a certain operation which depends on the selected operating mode The busy flag read only ADBSY is set as long as a conversion is in progress Semiconductor Group 18 3 Version 1 0 10 97 SIEMENS The Analog Digital Converter C164Cl The result of a conversion is stored in the result register ADDAT or in register ADDAT2 for an injected conversion Note Bit field CHNR of register ADDAT is loaded by the ADC to indicate which channel the result refers to Bit field CHNR of register ADDAT2 is loaded by the CPU to select the analog channel which is to be injected ADDAT FEAO 504 SFR Reset Value 0000
339. not be exceeded when selecting ADCTC and fep ADCON 15 14 A D Converter Basic clock ADCON 13 12 Sample time ts ADCTC fec ADSTC 00 fopy 4 00 tac 8 01 fopy 2 01 tac 16 10 fcpu 16 10 tgc 32 11 fcpu 8 11 tgc 64 The time for a complete conversion includes the sample time the conversion itself and the time required to transfer the digital value to the result register see example below Note The non linear decoding of bit field ADCTC provides compatibility with 80C166 designs for the default value 00 after reset Semiconductor Group 18 10 Version 1 0 10 97 SIEMENS The Analog Digital Converter C164Cl Converter Timing Example Assumptions fcpy 20 MHz ie top 50 ns ADCTC 00 ADSTC 00 Basic clock fec fopu 4 5 MHz ie tac 200 ns Sample time ts tpo 8 1600ns Conversion time te ts 40 tgc 2 tcpy 1600 8000 100 ns 9 7 us Note For the exact specification please refer to the data sheet of the selected derivative 18 3 A D Converter Interrupt Control At the end of each conversion interrupt request flag ADCIR in interrupt control register ADCIC is set This end of conversion interrupt request may cause an interrupt to vector ADCINT or it may trigger a PEC data transfer which reads the conversion result from register ADDAT eg to store it into a table in the internal RAM for later evaluation The interrupt request flag ADEIR in r
340. not be used with bit instructions The upper 256 bytes of the SFR area the ESFR area and the internal RAM are bit addressable see chapter Memory Organization ie those register bits located within the respective sections can be directly manipulated using bit instructions The other SFRs must be accessed byte word wise Note All GPRs are bit addressable independent of the allocation of the register bank via the context pointer CP Even GPRs which are allocated to not bit addressable RAM locations provide this feature The read modify write approach may be critical with hardware effected bits In these cases the hardware may change specific bits while the read modify write operation is in progress where the writeback would overwrite the new bit value generated by the hardware The solution is either the implemented hardware protection see below or realized through special programming see Particular Pipeline Effects Protected bits are not changed during the read modify write sequence ie when hardware sets eg an interrupt request flag between the read and the write of the read modify write sequence The hardware protection logic guarantees that only the intended bit s is are effected by the write back operation Note If a conflict occurs between a bit manipulation generated by hardware and an intended software access the software access has priority and determines the final value of the respective bit A summary of the protecte
341. nstructions Prioritize Instruction Data Movement Instructions System Stack Instructions Jump and Call Instructions Return Instructions System Control Instructions Miscellaneous Instructions Possible operand types are bits bytes and words Specific instruction support the conversion extension of bytes to words A variety of direct indirect or immediate addressing modes are provided to specify the required operands Semiconductor Group 2 5 Version 1 0 11 97 SIEMENS Architectural Overview C164Cl Programmable Multiple Priority Interrupt System The following enhancements have been included to allow processing of a large number of interrupt sources 1 Peripheral Event Controller PEC This processor is used to off load many interrupt requests from the CPU It avoids the overhead of entering and exiting interrupt or trap routines by per forming single cycle interrupt driven byte or word data transfers between any two locations in segment 0 with an optional increment of either the PEC source or the destination pointer Just one cycle is stolen from the current CPU activity to perform a PEC service 2 Multiple Priority Interrupt Controller This controller allows all interrupts to be placed at any specified priority Interrupts may also be grouped which provides the user with the ability to prevent similar priority tasks from interrupting each other For each of the possible interrupt sources there is a sep
342. nterrupt Generation below for more details 48 bit Timer Operation The concatenation of the 16 bit reload timer T14 and the 32 bit RTC timer can be regarded as a 48 bit timer which is clocked with the RTC input frequency divided by the fixed prescaler The reload register T14REL should be cleared to get a 48 bit binary timer However any other reload value may be used The maximum usable timespan is 248 10 4 T14 input clocks which would equal more than 100 years at an oscillator frequency of 20 MHz Semiconductor Group 14 2 Version 1 0 11 97 SIEMENS The Real Time Clock C164CI RTC Interrupt Generation The RTC interrupt shares the XPER3 interrupt node with the PLL OWD interrupt if available This is controlled by the interrupt subnode control register ISNC The interrupt handler can determine the source of an interrupt request via the separate interrupt request and enable flags see figure below provided in register ISNC Note If only one source is enabled no additional software check is required of course PLL OWD Interrupt Intr Request Intr Enable XPER3 Interrupt Interrupt T14 Node Controller Interrupt Intr Request Intr Enable Note Only available if PLL is implemented Figure 14 3 RTC Interrupt Logic If T14 interrupts are to be used both the interrupt node XPS3IE 1 and the T14 subnode T141E 1 must be enabled Please note that the node request bit XP3IR is automatically
343. ntrol Register T2IC GPT1 Timer 2 Interrupt Control Register T3CON GPT1 Timer 3 Control Register T3IC GPT1 Timer 3 Interrupt Control Register T4CON GPT1 Timer 4 Control Register T4IC GPT1 Timer 4 Interrupt Control Register Figure 10 1 SFRs and Port Pins Associated with Timer Block GPT1 Semiconductor Group 10 1 Version 1 0 11 97 SIEM ENS The General Purpose Timer Unit C164Cl All three timers of block GPT1 T2 T3 T4 can run in 4 basic modes which are timer gated timer counter and incremental interface mode and all timers can either count up or down Each timer has an alternate input function pin TxIN associated with it which serves as the gate control in gated timer mode or as the count input in counter mode The count direction Up Down may be programmed via software or may be dynamically altered by a signal at an external control input pin Each overflow underflow of core timer T3 is latched in the toggle FlipFlop T3OTL The auxiliary timers T2 and T4 may additionally be concatenated with the core timer or used as capture or reload registers for the core timer The current contents of each timer can be read or modified by the CPU by accessing the corresponding timer registers T2 T3 or T4 which are located in the non bitaddressable SFR space When any of the timer registers is written to by the CPU in the state immediately before a timer increment decrement reload or capture is to be performed the CPU write operation has
344. oaded The result is also stored into register MD The low portion MDL contains the integer result of the division while the high portion MDH contains the remainder Semiconductor Group 22 2 Version 1 0 11 97 SIEMENS System Programming C164CI The following instruction sequence performs a 32 by 16 bit division MOV MDH R1 Move dividend to MD register Sets MDRIU MOV MDL R2 Move low portion to MD DIV R3 Divide 32 16 signed R3 holds divisor JMPR cc V ERROR Test for divide overflow MOV R3 MDH Move remainder to R3 MOV R4 MDL Move integer result to R4 Clears MDRIU Whenever a multiply or divide instruction is interrupted while in progress the address of the interrupted instruction is pushed onto the stack and the MULIP flag in the PSW of the interrupting routine is set When the interrupt routine is exited with the RETI instruction this bit is implicitly tested before the old PSW is popped from the stack If MULIP 1 the multiply divide instruction is re read from the location popped from the stack return address and will be completed after the RETI instruction has been executed Note The MULIP flag is part of the context of the interrupted task When the interrupting routine does not return to the interrupted task eg scheduler switches to another task the MULIP flag must be set or cleared according to the context of the task that is switched to BCD Calculations No direct support for BCD calculations is provid
345. ogram memory Mask ROM OTP or Flash memory Note Any attempt to access a location in the external memory space in single chip mode results in the hardware trap ILLBUS 9 1 External Bus Modes When the external bus interface is enabled bit BUSACTx 1 and configured bitfield BTYP the C164Cl uses a subset of its port lines together with some control lines to build the external bus BTYP Encoding External Data Bus Width External Address Bus Mode 00 Reserved 0 1 8 bit Data Multiplexed Addresses 10 Reserved 11 16 bit Data Multiplexed Addresses The bus configuration BTYP for the address windows BUSCONA BUSCON 1 is selected via software typically during the initialization of the system The bus configuration BTYP for the default address range BUSCONO is selected via PORTO during reset provided that pin EA is low during reset Otherwise BUSCONO may be programmed via software just like the other BUSCON registers The 16 MByte address space of the C164Cl is divided into 256 segments of 64 KByte each The 16 bit intra segment address is output on PORTO When segmentation is disabled only one 64 KByte segment can be used and accessed Otherwise additional address lines may be output on Port 4 addressing up to 4 MByte and or several chip select lines may be used to select different memory banks or peripherals These functions are selected during reset via bitfields SALSEL and CSSEL of register RPOH respe
346. ompare Value 00004 7 CC COUT Compare Timer 1 Operating Mode 1 c Symetrical PWM Center Aligned b Standard PWM Single Edge Aligned with programmable dead time torr Period Value Compare Value Offset d Symetrical PWM Center Aligned with programmable dead time torr 4 Period Period Value Value Compare Compare y A Value Value 00004 Offset t t m Lor loj 1 1 CCx CCx COINI 0 ee ross COINI 0 COUTx l COUTx COINI 1 COINI 1 Interrupts can be generated MCT03356 Figure 17 3 CAPCOM6 Basic Operating Modes Semiconductor Group 17 3 Version 1 0 11 97 SIEMENS The Capture Compare Unit CAPCOM6 C164Cl 17 1 Clocking Scheme The CAPCOME6 unit operates on a programmable clock fcpy fopy 128 This internal clock signal is used to control all actions within the unit The falling edge modifies the compare timers the rising edge modifies the output signals if required Progr Clock CAPCOM6 Internal Clock Signal 00 fopu HLELELELELELELELELELELELELELE LI o c2 LILII L Lfd L i o o fopu 4 o0 o fcpu 16 Q9 increment decrement compare timers O9 modify logic level on output lines Figure 17 4 CAPCOM6 Internal Clocking Scheme 17 2 Output Signal Level Control The output signals generated by the CAPCOM6 unit are characterized by the
347. on 1 0 11 97 The Capture Compare Unit CAPCOM6 C164Cl SIEMENS 17 9 Register Description The CAPCOMS register set provides a number of control data and status bits to control the operation of the two compare timers the generation of the up to 7 output signals and the combination of submodules for multi channel operation The table below summarizes the available registers In the following the control registers are described in detail Data registers eg period or compare registers are excluded from the detailled description Please note that the timer registers T12 T13 are not directly accessible CAPCOM6 Register Summary Name Description Address Read T12P Timer T12 period register FO30y 18y Sh L T120F Timer T12 offset register F034y 1Ay Sh L T13P Timer T13 period register F032 194 Sh L CMP13 Compare register for compare channel FE36 1By Sh L CC60 Compare register for capture compare channel 0 FE30y 184 Reg CCe61 Compare register for capture compare channel 1 FE32y 194 Reg CC62 Compare register for capture compare channel 2 FE34 1Ay Reg CTCON Compare timer control register FF30y 98 Reg TRCON Trap enable register FF344 9Ay Reg CC6MCON CAPCOM6 mode control register FF324 99 Reg CC6MSEL CAPCOM6 mode select register F036 1By Reg CC6MIC CAPCOM6E interrupt control register FF364 9B Reg Note When reading these registers either the regi
348. on of input CTRAP can be enabled disabled generally and the trap function can be applied to each capture compare channel CC6x and COUT6x individually The figure below shows examples for a trap state in edge aligned mode and in center aligned mode The trap state is entered when CTRAP becomes active The selected output signals are switched to their respective trap level defined by the port latch immediately ie without any CPU activity The trap flag TRF in register TRCON is set in order to signal this event to the software If bit CT12RES in register CTCON is set timer T12 is cleared upon a trap event otherwise it continues counting No more transitions on the output signals are generated any more however The trap state is exited when T12 reaches the value 0000 after input C TRAP has been sampled inactive This delay automatically resumes the generation of the programmed output signals after a trap event in a synchronized way Note In block commutation mode trap state is exited when timer T13 reaches 000 not T12 a Trap Function in CAPCOM Operating Mode 0 CT1 CT1OFF Period Value Compare Value Offset zl p CTRAP b Trap Function in CAPCOM Operating Mode 1 Period CT1 CT1OFF Value Compare Value Offset T I Fa TE CCx A Trap State LLL COUTx Trap State 1 See Figure 17 12 Trap Function Semiconductor Group 17 17 Versi
349. on the transition at pins T2IN or TAIN When the interrupt enable bits T2IE or T4IE are set a PEC request or an interrupt request for vector T2INT or T4INT will be generated Note The non maskable interrupt input pin NMI and the reset input RSTIN provide another possibility for the CPU to react on an external input signal NMI and RSTIN are dedicated input pins which cause hardware traps Fast External Interrupts The input pins that may be used for external interrupts are sampled every 16 TCL ie external events are scanned and detected in timeframes of 16 TCL The C164CI provides 4 interrupt inputs that are sampled every 2 TCL so external events are captured faster than with standard interrupt inputs The lower 4 pins of Port P1H P1H 3 P1H 0 can individually be programmed to this fast interrupt mode where also the trigger transition rising falling or both can be selected The External Interrupt Control register EXICON controls this feature for all 4 pins EXICON F1C0 E01 ESFR Reset Value 00004 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 gt x rw rw rw rw Bit Function EXIxES External Interrupt x Edge Selection Field x 7 0 0 0 Fast external interrupts disabled standard mode 0 1 Interrupt on positive edge rising 1 0 Interrupt on negative edge falling 1 1 Interrupt on any edge rising or falling Note The fast external interrupt inputs are sampled every 2 TCL The interrupt request arbitration and
350. ons found in other microcontrollers are provided as subsets of more powerful instructions in the C164Cl This allows the same functionality to be provided while decreasing the hardware required and decreasing decode complexity In order to aid assembly programming these instructions familiar from other microcontrollers can be built in macros thus providing the same names Directly Substitutable Instructions are instructions known from other microcontrollers that can be replaced by the following instructions of the C164CI Substituted Instruction C164CI Instruction Function CLR Hn AND Rn 0 Clear register CPLB Bit BMOVN Bit Bit Complement bit DEC Rn SUB Rn 14 Decrement register INC Rn ADD Rn 14 Increment register SWAPB Rn ROR Rn 84 Swap bytes within word Modification of System Flags is performed using bit set or bit clear instructions BSET BCLR All bit and word instructions can access the PSW register so no instructions like CLEAR CARRY or ENABLE INTERRUPTS are required External Memory Data Access does not require special instructions to load data pointers or explicitly load and store external data The C164Cl provides a Von Neumann memory architecture and its on chip hardware automatically detects accesses to internal RAM GPRs and SFRs Multiplication and Division Multiplication and division of words and double words is provided through multiple cycle instructions implementing a Booth algorit
351. open drain mode Semiconductor Group 7 12 Version 1 0 11 97 SIEMENS Parallel Ports C164CI Alternate Functions of Port 3 The pins of Port 3 serve for various functions which include external timer control lines the two serial interfaces and the control lines BHE WRH and CLKOUT The table below summarizes the alternate functions of Port 3 Port 3 Pin Alternate Function P3 4 T3EUD Timer 3 External Up Down Input P3 6 T3IN Timer 3 Count Input P3 8 MRST SSC Master Receive Slave Transmit P3 9 MTSR SSC Master Transmit Slave Receive P3 10 TxDO ASCO Transmit Data Output P3 11 RxDO ASCO Receive Data Input P3 12 BHE WRH Byte High Enable Write High Output P3 13 SCLK SSC Shift Clock Input Output P3 15 CLKOUT System Clock Output Alternate Function a b P3 15 CLK OUT P3 13 P3 12 SCLK WRH P3 11 BHE P3 10 RxDO P3 9 TxDO P3 8 MTSR MRST P3 6 T3IN P3 4 T3EUD General Purpose Input Output Figure 7 8 Port 3 IO and Alternate Functions Semiconductor Group 7 13 Version 1 0 11 97 SIEMENS Parallel Ports C164CI The port structure of the Port 3 pins depends on their alternate function see figure below When the on chip peripheral associated with a Port 3 pin is configured to use the alternate input function it reads the input latch which represents the state of the pin via the line labeled Alternate Data Input Port 3 pins with alternate input functions are T3IN an
352. or OTP programming so POL O should be held high Default Emulation Mode is off Note In emulation mode the direct drive clock option is selected with P0 15 POH 7 1 Adapt Mode Pin POL 1 ADP selects the Adapt Mode when low during reset In this mode the C164Cl goes into a passive state which is similar to its state during reset The pins of the C164CI float to tristate or are deactivated via internal pullup pulldown devices as described for the reset state In addition also the RSTOUT pin floats to tristate rather than be driven low and the on chip oscillator is switched off This mode allows switching a C164Cl that is mounted to a board virtually off so an emulator may control the board s circuitry even though the original C164Cl remains in its place The original C164Cl also may resume to control the board after a reset sequence with POL 1 high Please note that adapt mode overrides any other configuration via PORTO Default Adapt Mode is off Note When XTAL1 is fed by an external clock generator while XTAL2 is left open this clock signal may also be used to drive the emulator device However if a crystal is used the emulator device s oscillator can use this crystal only if at least XTAL2 of the original device is disconnected from the circuitry the output XTAL2 will still be active in Adapt Mode Semiconductor Group 20 9 Version 1 0 11 97 System Reset C164Cl SIEMENS Special Operation Modes Pin
353. or a globally disabled interrupt system the CPU immediately resumes normal program execution with the instruction following the IDLE instruction Semiconductor Group 21 2 Version 1 0 11 97 SIEMENS Power Management C164Cl For a request which was programmed for PEC service a PEC data transfer is performed if the priority level of this request is higher than the current CPU priority and the interrupt system is globally enabled After the PEC data transfer has been completed the CPU remains in Idle mode Otherwise if the PEC request cannot be serviced because of a too low priority or a globally disabled interrupt system the CPU does not remain in Idle mode but continues program execution with the instruction following the IDLE instruction accepted E IDLE instruction wo f Denied PEC Request CY p Figure 21 2 Transitions between Idle mode and active mode Idle mode can also be terminated by a Non Maskable Interrupt ie a high to low transition on the NMI pin After Idle mode has been terminated by an interrupt or NMI request the interrupt system performs a round of prioritization to determine the highest priority request In the case of an NMI request the NMI trap will always be entered Any interrupt request whose individual Interrupt Enable flag was set before Idle mode was entered will terminate Idle mode regardless of the current CPU priority The CPU will not go back into Idle mode when a CPU interrupt request
354. or locations build a jump table in the low end of the C164Cl s address space segment 0 The jump table is made up of the appropriate jump instructions that transfer control to the interrupt or trap service routines which may be located anywhere within the address space The entries of the jump table are located at the lowest addresses in code segment 0 of the address space Each entry occupies 2 words except for the reset vector and the hardware trap vectors which occupy 4 or 8 words The table below lists all sources that are capable of requesting interrupt or PEC service in the C164Cl the associated interrupt vectors their locations and the associated trap numbers It also lists the mnemonics of the affected Interrupt Request flags and their corresponding Interrupt Enable flags The mnemonics are composed of a part that specifies the respective source followed by a part that specifies their function IR2Interrupt Request flag IE Interrupt Enable flag Note Each entry of the interrupt vector table provides room for two word instructions or one doubleword instruction The respective vector location results from multiplying the trap number by 4 4 bytes per entry All interrupt nodes that are currently not used by their associated modules or are not connected to a module in the actual derivative may be used to generate software controlled interrupt requests by setting the respective IR flag Semiconductor Group 5 2 Version 1 0 11 97 SI
355. orm a single data transfer via the on chip Peripheral Event Controller PEC System errors detected during program execution socalled hardware traps or an external non maskable interrupt are also processed as standard interrupts with a very high priority In contrast to other on chip peripherals there is a closer conjunction between the watchdog timer and the CPU If enabled the watchdog timer expects to be serviced by the CPU within a programmable period of time otherwise it will reset the chip Thus the watchdog timer is able to prevent the CPU from going totally astray when executing erroneous code After reset the watchdog timer starts counting automatically but it can be disabled via software if desired Beside its normal operation there are the following particular CPU states Reset state Any reset hardware software watchdog forces the CPU into a predefined active state IDLE state The clock signal to the CPU itself is switched off while the clocks for the on chip peripherals keep running POWER DOWN state All of the on chip clocks are switched off RTC clock selectable A transition into an active CPU state is forced by an interrupt if being IDLE or by a reset if being in POWER DOWN mode The IDLE POWER DOWN and RESET states can be entered by particular C164Cl system control instructions A set of Special Function Registers is dedicated to the functions of the CPU core General System Configuratio
356. ortion of the MDC register which might be of interest for the user The remaining portions of the MDC register are reserved for dedicated use by the hardware and should never be modified by the user in another way than described above Otherwise a correct continuation of an interrupted multiply or divide operation cannot be guaranteed A detailed description of how to use the MDC register for programming multiply and divide algorithms can be found in chapter System Programming Semiconductor Group 4 28 Version 1 0 11 97 SIEMENS The Central Processing Unit CPU C164Cl The Constant Zeros Register ZEROS All bits of this bit addressable register are fixed to 0 by hardware This register can be read only Register ZEROS can be used as a register addressable constant of all zeros ie for bit manipulation or mask generation It can be accessed via any instruction which is capable of addressing an SFR ZEROS FF1C 8Ey SFR Reset Value 00004 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 The Constant Ones Register ONES All bits of this bit addressable register are fixed to 1 by hardware This register can be read only Register ONES can be used as a register addressable constant of all ones ie for bit manipulation or mask generation It can be accessed via any instruction which is capable of addressing an SFR ONES FF1Ey 8Fy SFR Reset Value FFFFy 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Semiconductor Group 4 29 Version
357. ory area and also allows to access a great number of external devices using an external decoder By increasing the number of CS lines the C164Cl can access memory banks or peripherals without external glue logic These two features may be combined to optimize the overall system performance Note If the configured segment address lines and CS lines overlap eg A19 A16 and CS1 CS0 the segment address lines take preference Bit SGTDIS of register SYSCON defines if the CSP register is saved during interrupt entry segmentation active or not segmentation disabled Semiconductor Group 9 7 Version 1 0 11 97 SIEMENS The External Bus Interface C164CI 9 2 Programmable Bus Characteristics Important timing characteristics of the external bus interface have been made user programmable to allow to adapt it to a wide range of different external bus and memory configurations with different types of memories and or peripherals The following parameters of an external bus cycle are programmable ALE Control defines the ALE signal length and the address hold time after its falling edge Memory Cycle Time extendable with 1 15 waitstates defines the allowable access time Memory Tri State Time extendable with 1 waitstate defines the time for a data driver to float Read Write Delay Time defines when a command is activated after the falling edge of ALE Note Internal accesses are executed with maximum speed and therefore are not pro
358. ot require to re enable the interrupt system after the unseparable instruction sequence see chapter System Programming Interrupt Class Management An interrupt class covers a set of interrupt sources with the same importance ie the same priority from the system s viewpoint Interrupts of the same class must not interrupt each other The C164CI supports this function with two features Classes with up to 4 members can be established by using the same interrupt priority ILVL and assigning a dedicated group level GLVL to each member This functionality is built in and handled automatically by the interrupt controller Classes with more than 4 members can be established by using a number of adjacent interrupt priorities ILVL and the respective group levels 4 per ILVL Each interrupt service routine within this class sets the CPU level to the highest interrupt priority within the class All requests from the same or any lower level are blocked now ie no request of this class will be accepted The example below establishes 3 interrupt classes which cover 2 or 3 interrupt priorities depending on the number of members in a class A level 6 interrupt disables all other sources in class 2 by changing the current CPU level to 8 which is the highest priority ILVL in class 2 Class 1 requests or PEC requests are still serviced in this case The 24 interrupt sources excluding PEC requests are so assigned to 3 classes of priority rather t
359. ote It is strongly recommended to measure the oscillation allowance or margin in the final target system layout to determine the optimum parameters for the oscillator operation The external circuitry is different from that required by previous derivatives Semiconductor Group 6 2 Version 1 0 11 97 SIEMENS Clock Generation C164CI 6 2 Frequency Control The CPU clock is generated from the oscillator clock in either of two software selectable ways The basic clock is the standard operating clock for the C164Cl and is required to deliver the intended maximum performance The configuration via PORTO CLKCFG after a long hardware reset determines one of three possible basic clock generation modes e Direct Drive the oscillator clock is directly fed to the controller hardware Prescaler the oscillator clock is divided by 2 to achieve a 50 duty cycle e PLL the oscillator clock is multiplied by a configurable factor of F 2 1 5 5 The Slow Down clock is the oscillator clock divided by a programmable factor of 1 32 This alternate possibility runs the C164Cl at a lower frequency depending on the programmed slow down factor and thus greatly reduces its power consumption Oscillator clock CPU clock Figure 6 4 Frequency Control Paths The internal operation of the C164CIl is controlled by the internal CPU clock fcpy Both edges of the CPU clock can trigger internal eg pipeline or external eg bus cycles opera
360. oup 17 5 Version 1 0 11 97 SIEMENS The Capture Compare Unit CAPCOM6 C164Cl In the figure below a non zero offset value is used In this case the compare value is not compared with the timer contents directly but rather with timer contents plus offset As a consequence the active edge of signal COUT6x is shifted against CC6x The figure shows some output signals that can be generated compare value 3 a Standard output signal using T12 directly active high b Shifted output signal using T12 T12OF active high c Same signal as b but active low d 0 output signal compare value in CC6x gt T12P T120F e 100 output signal compare value in CC6x T120F CT1 CT1OFF Count Value A CCP 7 Period Reg CTOF 2 Offset Reg Start of CT1 CC COINI Pin 3 0 CCx a 3 0 COUTx b 3 1 COUTx C CT10F Toce 0 COUT T 0 d CHOF 0 COUTx 100 e CC content of the CCxH CCxL compare registers CCP content of the CCPH CCPL period register CT1OF content of the CTTOFH CT1OFL offset registers MCT02602 Figure 17 6 Operation with Non zero Offset Note Offset operation is only possible for the 3 capture compare channels on timer T12 The compare channel on timer T13 does not provide an offset register and has no second output signal Semiconductor Group 17 6 Versio
361. output function is enabled by setting bit CLKEN in register SYSCON to 1 If enabled port pin P3 15 takes on its alternate function as CLKOUT output pin The clock output is a 50 duty cycle clock except for slowdown operation where CLKOUT mirrors the CPU clock signal whose frequency equals the CPU operating frequency four fcpy Note The output driver of port pin P3 15 is switched on automatically wnen the CLKOUT function is enabled The port direction bit is disregarded After reset the clock output function is disabled CLKEN 0 In emulation mode the CLKOUT function is enabled automatically Segmentation Disable Enable Control SGTDIS Bit SGTDIS allows to select either the segmented or non segmented memory mode In non segmented memory mode SGTDIS 1 it is assumed that the code address space is restricted to 64 KBytes segment 0 and thus 16 bits are sufficient to represent all code addresses For implicit stack operations CALL or RET the CSP register is totally ignored and only the IP is saved to and restored from the stack In segmented memory mode SGTDIS 0 it is assumed that the whole address space is available for instructions For implicit stack operations CALL or RET the CSP register and the IP are saved to and restored from the stack After reset the segmented memory mode is selected Note Bit SGTDIS controls if the CSP register is pushed onto the system stack in addition to the IP register before an
362. ower Down mode was entered The supply current in this case remains well below 1 mA During power down the voltage at the Vpp pins can be lowered to 2 7 V while the RTC and its selected oscillator will still keep on running and the contents of the internal RAM will still be preserved When the RTC and oscillator is disabled the internal RAM is preserved down to a voltage of 2 5 V Note When the RTC remains active in Power Down mode also the oscillator which generates the RTC clock signal will keep on running of course If the supply voltage is reduced the specified maximum CPU clock frequency for this case must be respected The total power consumption in Power Down mode depends on the active circuitry ie RTC on or off and on the current that flows through the port drivers To minimize the consumed current the RTC and or all pin drivers can be disabled pins switched to tristate via a central control bitfield in register SYSCONa If an application requires one or more port drivers to remain active even in Power Down mode also individual port drivers can be disabled simply by configuring them for input The bus interface pins can be separately disabled by releasing the external bus disable all address windows by clearing the BUSACT bits and switching the ports to input if necessary Of course the required software in this case must be executed from internal memory Semiconductor Group 21 4 Version 1 0 11 97 SIEMENS Power Management
363. perands Any word data access is made to an even byte address For PEC data transfers the external memory in segment 0 can be accessed independent of the contents of the DPP registers via the PEC source and destination pointers The external memory is not provided for single bit storage and therefore it is not bit addressable Semiconductor Group 3 9 Version 1 0 11 97 SIEMENS Memory Organization C164Cl 3 4 Crossing Memory Boundaries The address space of the C164Cl is implicitly divided into equally sized blocks of different granularity and into logical memory areas Crossing the boundaries between these blocks code or data or areas requires special attention to ensure that the controller executes the desired operations Memory Areas are partitions of the address space that represent different kinds of memory if provided at all These memory areas are the internal RAM SFR area the internal ROM if available the on chip X Peripherals if integrated and the external memory Accessing subsequent data locations that belong to different memory areas is no problem However when executing code the different memory areas must be switched explicitly via branch instructions Sequential boundary crossing is not supported and leads to erroneous results Note Changing from the external memory area to the internal RAM SFR area takes place within segment 0 Segments are contiguous blocks of 64 KByte each They are referenced via the cod
364. peripheral management peripherals can be enabled disabled separately or in groups Periodic wakeup from Idle mode via RTC timer The listed features provide effective means to realize standby conditions for the system with an optimum balance between power reduction ie standby time and peripheral operation ie system functionality Flexible Clock Generation The flexible clock generation system combines a variety of improved mechanisms partly user controllable to provide the C164Cl modules with clock signals This is especially important in power sensitive modes like standby operation The power optimized oscillator generally reduces the amount of power which is consumed in order to generate the clock signal within the C164Cl The clock system efficiently controls the amount of power which is consumed in order to distribute the clock signal within the C164Cl Slowdown operation is achieved by dividing the oscillator clock by a programmable factor 1 32 resulting in a low frequency device operation which significantly reduces the overall power consumption Flexible Peripheral Management The flexible peripheral management provides a mechanism to enable and disable each peripheral module separately In each situation eg several system operating modes standby etc only those peripherals may be kept running which are required for the respective functionality All others can be switched off It also allows the operation control of
365. pin however one can also set the direction for this pin to output In this case the pin reflects the state of the port output latch Thus the alternate input function reads the value stored in the port output latch This can be used for testing purposes to allow a software trigger of an alternate input function by writing to the port output latch On most of the port lines the user software is responsible for setting the proper direction when using an alternate input or output function of a pin This is done by setting or clearing the direction control bit DPx y of the pin before enabling the alternate function There are port lines however where the direction of the port line is switched automatically For instance in the multiplexed external bus modes of PORTO the direction must be switched several times for an instruction fetch in order to output the addresses and to input the data Obviously this cannot be done through instructions In these cases the direction of the port line is switched automatically by hardware if the alternate function of such a pin is enabled To determine the appropriate level of the port output latches check how the alternate data output is combined with the respective port latch output Semiconductor Group 7 4 Version 1 0 11 97 SIEMENS Parallel Ports C164CI There is one basic structure for all port lines with only an alternate input function Port lines with only an alternate output function however hav
366. pin T3IN Timer T3 External Input To enable this operation pin T3IN must be configured as input ie the respective direction control bit DPx y must contain 0 Es s d Down TxOTL ID TxOUT TxOE MCB02029 4 gt x lt c J TxUDE Figure 10 4 Block Diagram of Core Timer T3 in Gated Timer Mode If T3M 0 0 the timer is enabled when T3IN shows a low level A high level at this pin stops the timer If T3M 0 1 pin T3IN must have a high level in order to enable the timer In addition the timer can be turned on or off by software using bit T3R The timer will only run if T3Rz 1 and the gate is active It will stop if either T3R 0 or the gate is inactive Note A transition of the gate signal at pin T3IN does not cause an interrupt request Semiconductor Group 10 6 Version 1 0 11 97 SIEM ENS The General Purpose Timer Unit C164Cl Timer 3 in Counter Mode Counter mode for the core timer T3 is selected by setting bit field T3M in register T3CON to 001p In counter mode timer T3 is clocked by a transition at the external input pin T3IN The event causing an increment or decrement of the timer can be a positive a negative or both a positive and a negative transition at this pin Bit field T3l in control register T3CON selects the triggering transition see table below Edge Select w DX i Up TxR A Down i TX TxOTL cue TxOUT 0 1 MUX TxOE MCB02030 TEUD gt EXOR 1 TxUDE
367. pper transistor is always switched off and the output driver can only actively drive the line to a low level When writing a 1 to the port latch the lower transistor is switched off and the output enters a high impedance state The high level must then be provided by an external pullup device With this feature it is possible to connect several port pins together to a Wired AND configuration saving external glue logic and or additional software overhead for enabling disabling output signals This feature is controlled through the respective Open Drain Control Registers ODPx which are provided for each port that has this feature implemented These registers allow the individual bit wise selection of the open drain mode for each port line If the respective control bit ODPx y is 0 default after reset the output driver is in the push pull mode If ODPx y is 1 the open drain configuration is selected Note that all ODPx registers are located in the ESFR space A A External IE Pullup al l I l I Ol Push Pull Output Driver Open Drain Output Driver MCS01975 Figure 7 2 Output Drivers in Push Pull Mode and in Open Drain Mode Input Threshold Control The standard inputs of the C164CI determine the status of input signals according to TTL levels In order to accept and recognize noisy signals CMOS like input thresholds can be selected instead of the standard TTL thresholds for all pins
368. priority in order to guarantee correct results TeEUD e T GPT1 Timer T2 ded i 2 n 3 10 T2 T TOIN Mode Reload Control Capture IVA gt CPU Clock 7 tegen Mode T30TL An Control tseuD J Interrupt Request T4 Tan J Mode A Control 005 Sl 2 n 3 10 Interrupt GPT1 Timer T4 g Reed T4EUD Jt un MCB02141 Figure 10 2 GPT1 Block Diagram Semiconductor Group 10 2 Version 1 0 11 97 SIEM ENS The General Purpose Timer Unit C164Cl GPT1 Core Timer T3 The core timer T3 is configured and controlled via its bitaddressable control register T3CON T3CON FF42 Alp SFR Reset Value 00004 15 14 13 12 t1 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw Bit Function TSI Timer 3 Input Selection Depends on the operating mode see respective sections T3M Timer 3 Mode Control Basic Operating Mode 000 Timer Mode 001 Counter Mode 010 Gated Timer with Gate active low 011 Gated Timer with Gate active high 100 Reserved Do not use this combination 101 Reserved Do not use this combination 110 Incremental Interface Mode 111 Reserved Do not use this combination T3R Timer 3 Run Bit TSR2 0 Timer Counter 3 stops TSR2 1 Timer Counter 3 runs T3UD Timer 3 Up Down Control T3UDE Timer 3 External Up Down Enable TSOTL Timer 3 Output Toggle Latch Toggles on each overflow underflow of T3 Can be set or rese
369. processing however is executed every 8 TCL Semiconductor Group 5 22 Version 1 0 11 97 SIEMENS Interrupt and Trap Functions C164CI The interrupt control registers listed below CC111C CC81C control the fast external interrupts of the C164Cl These fast external interrupt nodes and vectors are named according to the C167 s CAPCOM channels CC11 CC8 so interrupt nodes receive equal names throughout the architecture See register description below CCxIC See Table SFR Reset Value 00 Note Please refer to the general Interrupt Control Register description for an explanation of the control fields Fast External Interrupt Control Register Addresses Register Address External Interrupt CC8IC FF88j C44 EXOIN CC9IC FF8A C54 EX1IN CC10IC FF8C C64 EX2IN CC111C FF8E C74 EXSIN Semiconductor Group 5 23 Version 1 0 11 97 SIEMENS Interrupt and Trap Functions C164CI External Interrupt Source Control The input source for the fast external interrupts controlled via register EXICON can be derived either from the associated port pin EXnIN or from an alternate source This selection is controlled via register EXISEL Activating the alternate input source eg allows the detection of transitions on the interface lines of disabled interfaces Upon this trigger the respective interface can be reactivated and respond to the detected activity EXISEL F1DA EDp ESFR Reset Value 0000
370. programmable ROM e Flash memory OTP memory ROMless with no non volatile memory at all Also there are devices with specific functional units The devices may be offered in different packages temperature ranges and speed classes More standard and application specific derivatives are planned and in development Note Not all derivatives will be offered in any temperature range speed class package or program memory variation Information about specific versions and derivatives will be made available with the devices themselves Contact your Siemens representative for up to date material Note As the architecture and the basic features ie CPU core and built in peripherals are identical for most of the currently offered versions of the C164Cl the descriptions within this manual that refer to the C164Cl also apply to the other variations unless otherwise noted Semiconductor Group 1 3 Version 1 0 11 97 SIEMENS Introduction C164CI 1 2 Summary of Basic Features The C164Cl is an improved representative of the Siemens family of full featured 16 bit single chip CMOS microcontrollers It combines high CPU performance up to 10 million instructions per second with high peripheral functionality and means for power reduction Several key features contribute to the high performance of the C164CI the indicated timings refer to a CPU clock of 20 MHz High Performance 16 Bit CPU With Four Stage Pipeline 100 ns minimum
371. pted by all hardware traps or higher level interrupt requests Exception Condition Trap Trap Vector Trap Trap Flag Vector Location Number Priority Reset Functions Hardware Reset RESET 00 0000 00H I Software Reset RESET 00 0000 00H I Watchdog Timer Over RESET 00 0000 004 I flow Class A Hardware Traps Non Maskable Interrupt NMI NMITRAP 00 0008y 024 Stack Overflow STKOF STOTRAP 00 0010 044 I Stack Underflow STKUF STUTRAP 00 0018 064 I Class B Hardware Traps Undefined Opcode UNDOPC BTRAP 00 0028 OAH Protected Instruction PRTFLT BTRAP 0000284 OAH Fault Illegal Word Operand ILLOPA BTRAP 00 0028 OAH Access Illegal Instruction Access ILLINA BTRAP 00 0028 OAH Illegal External Bus ILLBUS BTRAP 000028 OAH Access Reserved 2C 304 0B OF y Software Traps Any Any Current TRAP Instruction 0000004 00H 7Fy CPU 00 01FC Priority in steps of 44 Semiconductor Group 5 4 Version 1 0 11 97 SIEMENS Interrupt and Trap Functions C164CI Normal Interrupt Processing and PEC Service During each instruction cycle one out of all sources which require PEC or interrupt processing is selected according to its interrupt priority This priority of interrupts and PEC requests is programmable in two levels Each requesting source can be assigned to a specific priority A second level called group priority allows to specify an internal order for simultaneous requests
372. put the C164Cl into the well defined reset condition either at power up or external events like a hardware failure or manual reset The input voltage threshold of the RSTIN pin is raised compared to the standard pins in order to minimize the noise sensitivity of the reset input In bidirectional reset mode the C164Cl s line RSTIN may be be driven active by the chip logic eg in order to support external equipment which is required for startup eg flash memory Bidirectional reset reflects internal reset sources software watchdog also to the RSTIN pin and converts short hardware reset pulses to a minimum duration of the internal reset sequence Bidirectional reset is enabled by setting bit BDRSTEN in register SYSCON and changes RSTIN from a pure input to an open drain IO line When an internal reset is triggered by the SRST instruction or by a watchdog timer overflow or a low level is applied to the RSTIN line an internal driver pulls it low for the duration of the internal reset sequence After that it is released and is then controlled by the external circuitry alone The bidirectional reset function is useful in applications where external devices require a defined reset signal but cannot be connected to the C164Cl s RSTOUT signal eg an external flash memory which must come out of reset and deliver code well before RSTOUT can be deactivated via EINIT Semiconductor Group 8 2 Version 1 0 11 97 SIEMENS Dedicated Pins C164CI Th
373. r detection capabilities has been included to increase the reliability of data transfers A parity bit can automatically be generated on transmission or be checked on reception Framing error detection allows to recognize data frames with missing stop bits An overrun error will be generated if the last character received has not been read out of the receive buffer register at the time the reception of a new character is complete The SSC supports full duplex synchronous communication at up to 5 Mbaud 20 MHz CPU clock It may be configured so it interfaces with serially linked peripheral components A dedicated baud rate generator allows to set up all standard baud rates without oscillator tuning For transmission reception and error handling 3 separate interrupt vectors are provided The SSC transmits or receives characters of 2 16 bits length synchronously to a shift clock which can be generated by the SSC master mode or by an external master slave mode The SSC can start shifting with the LSB or with the MSB and allows the selection of shifting and latching clock edges as well as the clock polarity A number of optional hardware error detection capabilities has been included to increase the reliability of data transfers Transmit and receive error supervise the correct handling of the data buffer Phase and baudrate error detect incorrect serial data The On chip CAN Module The integrated CAN Module handles the completely autonomous trans
374. r is incremented to a value which is greater than the value in the stack underflow register STKUN the STKUF flag is set in register TFR and the CPU will enter the stack underflow trap routine Again which IP value will be pushed onto the system stack depends on which operation caused the increment of the SP When an implicit increment of the SP is made through a POP or return instruction the IP value pushed is the address of the following instruction When the SP is incremented by an add instruction the pushed IP value represents the address of the instruction after the instruction following the add instruction Undefined Opcode Trap When the instruction currently decoded by the CPU does not contain a valid C164Cl opcode the UNDOPC flag is set in register TFR and the CPU enters the undefined opcode trap routine The IP value pushed onto the system stack is the address of the instruction that caused the trap This can be used to emulate unimplemented instructions The trap service routine can examine the faulting instruction to decode operands for unimplemented opcodes based on the stacked IP In order to resume processing the stacked IP value must be incremented by the size of the undefined instruction which is determined by the user before a RETI instruction is executed Protection Fault Trap Whenever one of the special protected instructions is executed where the opcode of that instruction is not repeated twice in the second word of the in
375. r the SCXT switch context instruction Upon exit from a task a simple POP instruction to the context pointer CP restores the previous task s register bank 22 3 Procedure Call Entry and Exit To support modular programming a procedure mechanism is provided to allow coding of frequently used portions of code into subroutines The CALL and RET instructions store and restore the value of the instruction pointer IP on the system stack before and after a subroutine is executed Procedures may be called conditionally with instructions CALLA or CALLI or be called unconditionally using instructions CALLR or CALLS Note Any data pushed onto the system stack during execution of the subroutine must be popped before the RET instruction is executed Semiconductor Group 22 8 Version 1 0 11 97 SIEMENS System Programming C164CI Passing Parameters on the System Stack Parameters may be passed via the system stack through PUSH instructions before the subroutine is called and POP instructions during execution of the subroutine Base plus offset indirect addressing also permits access to parameters without popping these parameters from the stack during execution of the subroutine Indirect addressing provides a mechanism of accessing data referenced by data pointers which are passed to the subroutine In addition two instructions have been implemented to allow one parameter to be passed on the system stack without additional software overhead
376. rals cannot be accessed while the respective module is disabled by any means While a peripheral is disabled its output pins remain in the state they had at the time of disabling Semiconductor Group 21 10 Version 1 0 11 97 SIEMENS Power Management C164Cl Software controls this flexible peripheral mangement via register SYSCONS where each control bit is associated with an on chip peripheral module SYSCONS F1D4 EA ESFR Reset Value 00004 15 14 13 12 11 10 9 8 7 6 5 4 8 2 1 0 PCD CAN1 CC6 CC2 GPT SSC ASCO ADC m t meme wem rw rw z rw rw rw rw rw rw Bit Function associated peripheral module ADCDIS Analog Digital Converter ASCODIS USART ASCO SSCDIS Synchronous Serial Channel SSC GPTDIS General Purpose Timer Blocks CC2DIS CAPCOM Unit 2 CC6DIS CAPCOM Unit 6 CAN1DIS On chip CAN Module 1 PCDDIS Peripheral Clock Driver also X Peripherals Note The allocation of peripheral disable bits within register SYSCONGS is device specific and may be different in other derivatives than the C164CI SYSCONS is write protected after the execution of EINIT unless it is released via the unlock sequence When disabling the peripheral clock driver PCD the following details should be respected The clock signal for all connected peripherals is stopped Make sure that all peripherals enter a safe state before disabling PCD The output signal CLKOUT will remain high 1
377. ration and the number of stop bits can be selected Parity framing and overrun error detection is provided to increase the reliability of data transfers Transmission and reception of data is double buffered For multiprocessor communication a mechanism to distinguish address from data bytes is included Testing is supported by a loop back option A 13 bit baud rate generator provides the ASCO with a separate serial clock signal Ports amp Direction Control Data Registers Control Registers Interrupt Control Alternate Functions SOBG SOCON SOTIC SORIC SOTBUF SORBUF SOEIC SOTBIG E RXDO P3 11 TXDO P3 10 ODP3 Port 3 Open Drain Control Register DP3 Port 3 Direction Control Register P3 Port 3 Data Register SOBG ASCO Baud Rate Generator Reload Register SOCON ASCO Control Register SOTBUF ASCO Transmit Buffer Register SORBUF ASCO Receive Buffer Register read only SOTIC ASCO Transmit Interrupt Control Register SORIC ASCO Receive Interrupt Control Register SOTBIC ASCO Transmit Buffer Interrupt Control Reg SOEIC ASCO Error Interrupt Control Register Figure 11 1 SFRs and Port Pins associated with ASCO The operating mode of the serial channel ASCO is controlled by its bitaddressable control register SOCON This register contains control bits for mode and error check selection and status flags for error identification Semiconductor Group 11 1 Version 1 0 11 97 Sl EM ENS The Asynchronous Synchronous Serial In
378. re effectable bits SYSCON FF12 894 SFR Reset Value 0XX0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 T BYT CLK WR CS BDRS VISI XPER rw w w WwW w w wW mw w w w mw rm Bit Function XPER SHARE XBUS Peripheral Share Mode Control 0 External accesses to XBUS peripherals are disabled 1 XBUS peripherals are accessible via the external bus during hold mode VISIBLE Visible Mode Control 0 Accesses to XBUS peripherals are done internally 1 XBUS peripheral accesses are made visible on the external pins Semiconductor Group 4 11 Version 1 0 11 97 SIEMENS The Central Processing Unit CPU C164Cl Bit Function XPEN XBUS Peripheral Enable Bit 0 Accesses to the on chip X Peripherals and their functions are disabled 1 The on chip X Peripherals are enabled and can be accessed BDRSTEN Bidirectional Reset Enable Bit 0 Pin RSTIN is an input only 1 Pin RSTIN is pulled low during the internal reset sequence OWDDIS Oscillator Watchdog Disable Bit 0 The on chip oscillator watchdog is enabled and active 1 The on chip oscillator watchdog is disabled and the CPU clock is always fed from the oscillator input CSCFG Chip Select Configuration Control 0 Latched CS mode The CS signals are latched internally and driven to the enabled port pins synchronously 1 Unlatched CS mode The CS signals are directly derived from the address and driven to the enabled port pins WRCFG Wr
379. re generated by the peripherals based on specific events which occur during their operation eg operation complete error etc For interfacing with external hardware specific pins of the parallel ports are used when an input or output function has been selected for a peripheral During this time the port pins are controlled by the peripheral when used as outputs or by the external hardware which controls the peripheral when used as inputs This is called the alternate input or output function of a port pin in contrast to its function as a general purpose IO pin Peripheral Timing Internal operation of CPU and peripherals is based on the CPU clock fep The on chip oscillator derives the CPU clock from the crystal or from the external clock signal The clock signal which is gated to the peripherals is independent from the clock signal which feeds the CPU During Idle mode the CPU s clock is stopped while the peripherals continue their operation Peripheral SFRs may be accessed by the CPU once per state When an SFR is written to by software in the same state where it is also to be modified by the peripheral the software write operation has priority Further details on peripheral timing are included in the specific sections about each peripheral Semiconductor Group 2 9 Version 1 0 11 97 SIEMENS Architectural Overview C164Cl Programming Hints Access to SFRs All SFRs reside in data page 3 of the memory space The followin
380. read write delay the falling edges of ALE and command s are coincident except for propagation delays With the delay enabled the command s become active half a CPU clock 25 ns at fepy 20 MHz after the falling edge of ALE The read write delay does not extend the memory cycle time and does not slow down the controller in general In multiplexed bus modes however the data drivers of an external device may conflict with the C164Cl s address when the early RD signal is used Therefore multiplexed bus cycles should always be programmed with read write delay Read Write Delay Semet 70 Mies ALE BUS P0 Data Instr RD mE WR MCT02066 1 The data drivers from the previous bus cycle should be disabled when the RD signal becomes active Figure 9 7 Read Write Delay The read write delay is controlled via the RWDCx bits in the BUSCON registers The command s will be delayed if bit RWDOx is 0 default after reset Semiconductor Group 9 12 Version 1 0 11 97 SIEMENS The External Bus Interface C164CI 9 3 Controlling the External Bus Controller A set of registers controls the functions of the EBC General features like the usage of interface pins WR BHE segmentation and internal ROM mapping are controlled via register SYSCON The properties of a bus cycle like chip select mode length of ALE external bus mode read write delay and waitstates are controlled via registe
381. red cross currents and switching noise while the analog input signal level is between Vi and Vip Some pins of Port 5 also serve as external GPT timer control lines The table below summarizes the alternate functions of Port 5 Port 5 Pin Alternate Function a Alternate Function b P5 0 Analog Input ANO P5 1 Analog Input AN1 P5 2 Analog Input AN2 Pag Analog Input AN3 P5 4 Analog Input AN4 T2EUD Timer 2 ext Up Down Input P5 5 Analog Input AN5 T4EUD Timer 4 ext Up Down Input P5 6 Analog Input AN6 T2IN Timer 2 Count Input P5 7 Analog Input AN7 T4IN Timer 4 Count Input Semiconductor Group 7 20 Version 1 0 11 97 SIEMENS Parallel Ports C164CI Alternate Function a b Port 5 P5 7 AN7 T4IN P5 6 AN6 T2IN P5 5 AN5 T4EUD P5 4 AN4 T2EUD P5 3 AN3 P5 2 AN2 P5 1 AN1 P5 0 ANO General Purpose A D Converter Input Input Figure 7 13 Port 5 IO and Alternate Functions Port 5 Digital Input Control Port 5 pins may be used for both digital an analog input By setting the respective bit in register P5DIDIS the digital input stage of the respective port 5 pin can be disconnected from the pin This is recommended when the pin is to be used as analog input as it reduces the current through the digital input stage and prevents it from toggling while the analog input level is between the digital low and high thresholds So the consumed power and the generated noise can be reduced After r
382. refore should not begin directly after the instruction disabling interrupts as shown in the following example INT OFF BCLR IEN globally disable interrupts IN 4 hon critical instruction CRIT 1ST lw begin of uninterruptable critical sequence CRIT LAST ly end of uninterruptable critical sequence INT ON BSET IEN globally re enable interrupts Note The described delay of 1 instruction also applies for enabling the interrupts system ie no interrupt requests are acknowledged until the instruction following the enabling instruction e Initialization of Port Pins Modifications of the direction of port pins input or output become effective only after the instruction following the modifying instruction As bit instructions BSET BCLR use internal read modify write sequences accessing the whole port instructions modifying the port direction should be followed by an instruction that does not access the same port see example below PORT_INIT_WRONG BSET DP3 13 change direction of P3 13 to output BSET P3 9 P3 13 is still input rd mod wr reads pin P3 13 PORT INIT RIGHT BSET DP3 13 change direction of P3 13 to output NOP any instruction not accessing port 3 BSET P3 9 P3 13 is now output rd mod wr reads P3 13 s output latch Semiconductor Group 4 7 Version 1 0 11 97 SIEMENS The Central Processing Unit CPU C164Cl e Changing the System Configuration The instruction following an instruction that change
383. res 25 neo Rau acce egies IR em eee Meme eee da 1 4 1 3 Abbreviations xoxo cce Er el gee ee Ei aed ea eee 1 7 2 Architectural Overview 0 000 c eects 2 1 2 1 Basic CPU Concepts and Optimizations 0000 eee ee 2 2 2 2 The On chip System Resources 0000 eee eee 2 7 2 3 The On chip Peripheral Blocks s caw eC eva reet Ses een 2 9 2 4 Power Management Features 0 2 00 cette ee tees 2 15 2 5 Protected BiS os o ed be dE EO eT E aae AN pa i aaye AW en togae ell Diced 2 16 3 Memory Organization aLaaa aana ee 3 1 3 1 Internat R OM rete reis eek ee urere cee ie atl ak T AE S 3 3 3 2 Internal RAM and SFR Area e300 a06e haa ee bee ed FR a eee Y 3 4 3 3 External Memory Space zusenden eI Reed ecc bee are 3 9 3 4 Crossing Memory Boundaries 2 222642 EI RR REERESATECASNEERTA 3 10 3 5 OTP Memory Programming s s su eons qe Ete ge ine i e co e t e 3 11 4 The Central Processing Unit CPU 2 00 00 0c eae 4 1 4 1 Instr ction Pipelirilg s yes EXE HERES CE ERR E RE3XG EE eg REDE 4 3 4 2 Bit Handling and Bit Protection 2 err ER T RET SA E EIER 4 9 4 3 Instruction State Times c sesta bases soe qd se hard rr DE us o 4 10 4 4 CPU Special Function Registers 2 0 00 eee 4 11 5 Interrupt and Trap Functions 0 0000 eee 5 1 5 1 Interrupt System Structure 2 5 cn exem RIDERE oe ERR ING ERR SEE 5 2 5 2 Operation or the PEC Channels ios caw ic iR ek RE
384. reshold 7 2 Timer 2 12 10 1 Auxiliary Timer 10 11 CAPCOM2 16 4 CAPCOMG 17 3 Concatenation 10 14 Core Timer 10 3 Tools 1 6 Trap Function CAPCOM6 17 17 Traps 5 4 5 25 TRCON 17 21 Tri State Time 9 11 U UAR 19 16 Unseparable instructions 22 12 W Waitstate Memory Cycle 9 10 Tri State 9 11 Watchdog 2 12 13 1 20 5 Oscillator 6 8 WDT 13 1 26 4 Version 1 0 11 97 IE EN Index S M S C164CI WDTCON 13 2 X XBUS 2 8 9 22 Z ZEROS 4 29 Semiconductor Group 26 5 Version 1 0 11 97
385. ress lines on Port 4 which extend the 16 bit address output on PORTO and so increase the accessible address space The number of segment address lines is selected during reset and coded in bit field SALSEL in register RPOH see table below SALSEL Segment Address Lines Directly accessible Address Space 11 Two A17 A16 256 KByte Default without pull downs 10 Six A21 A16 4 MByte Maximum 0 1 None 64 KByte Minimum 00 Four A19 A16 1 MByte CS Signal Generation During external accesses the EBC can generate a programmable number of CS lines on Port 4 which allow to directly select external peripherals or memory banks without requiring an external decoder The number of CS lines is selected during reset and coded in bit field CSSEL in register RPOH see table below CSSEL Chip Select Lines Note 1 1 Four CS3 CS0 Default without pull downs 10 None 0 1 Two CS1 CS0 00 Three CS2 CS0 The CSx outputs are associated with the BUSCONXx registers and are driven active low for any access within the address area defined for the respective BUSCON register For any access outside this defined address area the respective CSx signal will go inactive high At the beginning of each external bus cycle the corresponding valid CS signal is determined and activated All other CS lines are deactivated driven high at the same time Note The CSx signals will not be updated for an access
386. river Note Disabling PCD by setting bit PCDDIS stops the clock signal for all connected modules Make sure that all these modules are in a safe state before stopping their clock signal The port input and output values will not change while PCD is disabled CLKOUT will be high if enabled Please also respect the hints given in section Flexible Peripheral Management of chapter Power Management Semiconductor Group 6 9 Version 1 0 11 97 SIEMENS Parallel Ports C164CI 7 Parallel Ports In order to accept or generate single external control signals or parallel data the C164Cl provides up to 59 parallel IO lines organized into four 8 bit IO ports PORTO made of POH and POL PORT1 made of P1H and P1L one 9 bit IO port Port 3 one 6 bit IO port Port 4 one 4 bit IO port Port 8 and one 8 bit input port Port 5 These port lines may be used for general purpose Input Output controlled via software or may be used implicitly by C164Cl s integrated peripherals or the External Bus Controller All port lines are bit addressable and all input output lines are individually bit wise programmable as inputs or outputs via direction registers except Port 5 of course The IO ports are true bidirectional ports which are switched to high impedance state when configured as inputs The output drivers of two IO ports 3 8 can be configured pin by pin for push pull operation or open drain operation via control registe
387. rnal code memory can still be used for fixed software routines like IO drivers math libraries application specific invariant routines tables etc This combines the advantage of an integrated non volatile memory with the advantage of a flexible adaptable software system Enabling and Disabling the Internal Code Memory After Reset If the internal code memory does not contain an appropriate startup code the system may be booted from external memory while the internal memory is enabled afterwards to provide access to library routines tables etc If the internal code memory only contains the startup code and or test software the system may be booted from internal memory which may then be disabled after the software has switched to executing from eg external memory in order to free the address space occupied by the internal code memory which is now unnecessary Semiconductor Group 22 14 Version 1 0 11 97 SIEMENS System Programming C164CI 22 11 Pits Traps and Mines Although handling the internal code memory provides powerful means to enhance the overall performance and flexibility of a system extreme care must be taken in order to avoid a system crash Instruction memory is the most crucial resource for the C164Cl and it must be made sure that it never runs out of it The following precautions help to take advantage of the methods mentioned above without jeopardizing system security Internal code memory access after reset
388. rnal transition at pin CCxlO When CCMODx is programmed to 010p a negative external transition will set the interrupt request flag When CCMODx 011 g both a positive and a negative transition will set the request flag In all three cases the contents of the allocated CAPCOM timer will be latched into capture register CCx independent whether the timer is running or not When the interrupt enable bit CCxIE is set a PEC request or an interrupt request for vector CCxINT will be generated Semiconductor Group 5 21 Version 1 0 11 97 SIEMENS Interrupt and Trap Functions C164CI Pins T2lN or T4IN can be used as external interrupt input pins when the associated auxiliary timer T2 or T4 in block GPT1 is configured for capture mode This mode is selected by programming the mode control fields T2M or T4M in control registers T2CON or TACON to 101g The active edge of the external input signal is determined by bit fields T21 or T4l When these fields are programmed to X01g interrupt request flags T2IR or T4IR in registers T21C or T4IC will be set on a positive external transition at pins T2IN or TAIN respectively When T2l or T4l are programmed to X10p then a negative external transition will set the corresponding request flag When T2I or T4l are programmed to X115 both a positive and a negative transition will set the request flag In all three cases the contents of the core timer T3 will be captured into the auxiliary timer registers T2 or T4 based
389. rovides access to a set of status flags Register SSCCON is shown below in each of the two modes Semiconductor Group 12 2 Version 1 0 11 97 SIEM ENS The High Speed Synchronous Serial Interface C164CI SSCCON FFB2 D9 SFR Reset Value 00004 15 14 13 12 1i 10 9 8 7 6 5 4 3 2 1 0 SSC SSC SSC SSC SSC SSC SSC SSC SSC SSC KA RAER RRR R SRE sco rw rw rw rw rw rw rw rw rw rw rw Bit Function Programming Mode SSCEN 0 SSCBM SSC Data Width Selection 0 Reserved Do not use this combination 1 15 Transfer Data Width is 2 16 bit lt SSCBM gt 1 SSCHB SSC Heading Control Bit 0 Transmit Receive LSB First 1 Transmit Receive MSB First SSCPH SSC Clock Phase Control Bit 0 Shift transmit data on the leading clock edge latch on trailing edge 1 Latch receive data on leading clock edge shift on trailing edge SSCPO SSC Clock Polarity Control Bit 0 Idle clock line is low leading clock edge is low to high transition 1 Idle clock line is high leading clock edge is high to low transition SSCTEN SSC Transmit Error Enable Bit 0 Ignore transmit errors 1 Check transmit errors SSCREN SSC Receive Error Enable Bit 0 Ignore receive errors d Check receive errors SSCPEN SSC Phase Error Enable Bit 0 Ignore phase errors 1 Check phase errors SSCBEN SSC Baudrate Error Enable Bit 0 Ignore baudrate errors Tz Check baudrate errors SSCAREN SSC Automatic Reset Enable Bit 0 No addit
390. rrect timer operation Semiconductor Group 16 5 Version 1 0 11 97 SIEMENS The Capture Compare Unit CAPCOM2 C164Cl Timer Mode The bits TxM in SFR T78CON select between timer or counter mode for the respective timer In timer mode TxM 0 the input clock for a timer is derived from the internal CPU clock divided by a programmable prescaler The different options for the prescaler are selected separately for each timer by the bit fields Txl The input frequencies fr for Tx are determined as a function of the CPU clock as follows where Txl represents the contents of the bit field Txl fopu mes o Txb 43 When a timer overflows from FFFF to 0000 it is reloaded with the value stored in its respective reload register TxREL The reload value determines the period Pr between two consecutive overflows of Tx as follows 219 TxREL 9 lt Txl gt 3 x fopu The timer input frequencies resolution and periods which result from the selected prescaler option in Txl when using a 20 MHz CPU clock are listed in the table below The numbers for the timer periods are based on a reload value of 0000 Note that some numbers may be rounded to 3 significant digits fcpy 20 MHz Timer Input Selection Txl 000g 001g 010g 011g 100p 101g 110g 111g Prescaler for f py 8 16 32 64 128 256 512 1024 Input Frequency 2 5 1 25 625 312 5 156 25 78 125 39 06 119 53 MHz MHz kHz kHz kHz kHz kHz kHz Resolution 400ns 8
391. rs The logic level of a pin is clocked into the input latch once per state time regardless whether the port is configured for input or output A write operation to a port pin configured as an input causes the value to be written into the port output latch while a read operation returns the latched state of the pin itself A read modify write operation reads the value of the pin modifies it and writes it back to the output latch Writing to a pin configured as an output DPx y 1 causes the output latch and the pin to have the written value since the output buffer is enabled Reading this pin returns the value of the output latch A read modify write operation reads the value of the output latch modifies it and writes it back to the output latch thus also modifying the level at the pin Data Input Output Direction Control Threshold Open Drain Registers Registers Control Registers PICON q ODP3 E P5DIDIS ODP8 E Figure 7 1 SFRs and Pins associated with the Parallel Ports Semiconductor Group 7 1 Version 1 0 11 97 SIEMENS Parallel Ports C164CI Open Drain Mode In the C164Cl certain ports provide Open Drain Control which allows to switch the output driver of a port pin from a push pull configuration to an open drain configuration In push pull mode a port output driver has an upper and a lower transistor thus it can actively drive the line either to a high or a low level In open drain mode the u
392. rs BUSCONA BUSCONO Four of these registers BUSCON4 BUSCON1 have an address select register ADDRSELA ADDRSEL 1 associated with them which allows to specify up to four address areas and the individual bus characteristics within these areas All accesses that are not covered by these four areas are then controlled via BUSCONO This allows to use memory components or peripherals with different interfaces within the same system while optimizing accesses to each of them SYSCON FF12 894 SFR Reset Value OXX0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 T BYT CLK WR CS BD VISI XPER rw w w WwW w w w mw we ow w w mw Bit Function XPER SHARE XBUS Peripheral Share Mode Control 0 External accesses to XBUS peripherals are disabled 1 XBUS peripherals are accessible via the external bus during hold mode VISIBLE Visible Mode Control 0 Accesses to XBUS peripherals are done internally 1 XBUS peripheral accesses are made visible on the external pins XPEN XBUS Peripheral Enable Bit 0 Accesses to the on chip X Peripherals and their functions are disabled 1 The on chip X Peripherals are enabled and can be accessed BDRSTEN Bidirectional Reset Enable Bit 0 Pin RSTIN is an input only 1 Pin RSTIN is pulled low during the internal reset sequence after a software or WDT reset OWDDIS Oscillator Watchdog Disable Bit Set according to pin RD during reset 0 The on chip oscillator watchdog is enabled and active 1 The on
393. rsion in New requested conversion Progress Standard Injected Standard Abort running conversion Complete running conversion and start requested new conversion start requested conversion after that Injected Complete running conversion Complete running conversion start requested conversion after that start requested conversion after that Bit ADCRQ will be 0 for the second conversion however Semiconductor Group 18 9 Version 1 0 10 97 SIEMENS The Analog Digital Converter C164Cl 18 2 Conversion Timing Control When a conversion is started first the capacitances of the converter are loaded via the respective analog input pin to the current analog input voltage The time to load the capacitances is referred to as sample time Next the sampled voltage is converted to a digital value in successive steps which correspond to the resolution of the ADC After the conversion itself one step of the internal self calibration of the converter module is executed During these phases except for the sample time the internal capacitances are repeatedly charged and discharged via pins V aper and VAGwp The current that has to be drawn from the sources for sampling and changing charges depends on the time that each respective step takes because the capacitors must reach their final voltage level within the given time at least with a certain approximation The maximum current however that a source can deliver depends o
394. ructions which operate on word data types their upper 8 bits 15 8 will return zeros when read and will discard written data The layout of the Interrupt Control registers shown below applies to each xxIC register where xx stands for the mnemonic for the respective source Semiconductor Group 5 5 Version 1 0 11 97 SIEMENS Interrupt and Trap Functions C164CI XXIC yyyyy ZZ SFR area Reset Value 00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Function GLVL Group Level Defines the internal order for simultaneous requests of the same priority 3 Highest group priority 0 Lowest group priority ILVL Interrupt Priority Level Defines the priority level for the arbitration of requests Fp Highest priority level Op Lowest priority level xxlE Interrupt Enable Control Bit individually enables disables a specific source 0 Interrupt request is disabled 1 Interrupt Request is enabled xxIR Interrupt Request Flag 0 No request pending 1 This source has raised an interrupt request The Interrupt Request Flag is set by hardware whenever a service request from the respective source occurs It is cleared automatically upon entry into the interrupt service routine or upon a PEC service In the case of PEC service the Interrupt Request flag remains set if the COUNT field in register PECCx of the selected PEC channel decrements to zero This allows a normal CPU interrupt to re
395. rupt request flag during the last state of an instruction cycle When the interrupt request flag is set during the first state of an instruction cycle the minimum interrupt response time under these conditions is 6 state times 12 TCL The interrupt response time is increased by all delays of the instructions in the pipeline that are executed before entering the service routine including N Semiconductor Group 5 16 Version 1 0 11 97 SIEMENS Interrupt and Trap Functions C164CI When internal hold conditions between instruction pairs N 2 N 1 or N 1 N occur or instruction N explicitly writes to the PSW or the SP the minimum interrupt response time may be extended by 1 state time for each of these conditions When instruction N reads an operand from the internal code memory or when N is a call return trap or MOV Rn Rm data16 instruction the minimum interrupt response time may additionally be extended by 2 state times during internal code memory program execution In case instruction N reads the PSW and instruction N 1 has an effect on the condition flags the interrupt response time may additionally be extended by 2 state times The worst case interrupt response time during internal code memory program execution adds to 12 state times 24 TCL Any reference to external locations increases the interrupt response time due to pipeline related access priorities The following conditions have to be considered Instruct
396. rupt response time for the C164Cl is 3 instruction cycles Pipeline Stage Cycle 1 Cycle 2 Cycle 3 Cycle 4 FETCH N N 1 N 2 I1 DECODE N 1 N TRAP 1 TRAP 2 EXECUTE N 2 N 1 N TRAP WRITEBACK N 3 N 2 N 1 N IR Flag Interrupt Response Time Figure 5 4 Pipeline Diagram for Interrupt Response Time All instructions in the pipeline including instruction N during which the interrupt request flag is set are completed before entering the service routine The actual execution time for these instructions eg waitstates therefore influences the interrupt response time In the figure above the respective interrupt request flag is set in cycle 1 fetching of instruction N The indicated source wins the prioritization round during cycle 2 In cycle 3 a TRAP instruction is injected into the decode stage of the pipeline replacing instruction N 1 and clearing the source s interrupt request flag to 0 Cycle 4 completes the injected TRAP instruction save PSW IP and CSP if segmented mode and fetches the first instruction I1 from the respective vector location All instructions that entered the pipeline after setting of the interrupt request flag N 1 N 2 will be executed after returning from the interrupt service routine The minimum interrupt response time is 5 states 10 TCL This requires program execution from the internal code memory no external operand read requests and setting the inter
397. s ie dont t care then the identifiers of the valid message objects must differ in the remaining bits which are used for acceptance filtering If a received data frame is stored into a message object the identifier of this message object is updated If some of the identifier bits are set to don t care by the corresponding mask register these bits may be changed in the message object If a remote frame is received the identifier in transmit object remain unchanged except for the last message object which cannot start a transmission Here the identifier bits corresponding to the don t care bits of the last message object s mask may be overwritten by the incoming message Upper Arbitration Register EFn2 XReg Reset Value UUUU 15 14 13 12 11 10 9 83 7 6 5 4 3 2 74d 0 siii m oo mmo rw rw Lower Arbitration Register EFn4 XReg Reset Value UUUU 15 14 13 12 11 10 9 8 Bit Function ID28 0 Identifier 29 bit Identifier of a standard message ID28 18 or an extended message ID28 0 For standard identifiers bits ID17 0 are don t care Semiconductor Group 19 16 Version 1 0 11 97 SIEMENS The On Chip CAN Interface C164CI Message Configuration and Data The following fields hold a description of the message within this object The data field occupies the following 8 byte positions after the Message Configuration Register Note There is no don t care option for bits XTD and DI
398. s 256 segments of 64 KBytes each and each segment is again subdivided into four data pages of 16 KBytes each see figure below FF FFFFY 00 FFFF H eee FF 0000 4 Data Page 3 00 E000 H Segment External 00 CO00 H FE 0000 4 Memory F4 Data Page 2 00 8000 H 0300004 Data Page 1 _ ft 02 s H Internal ROM 00 4000 Area 01 0000 H STU Data Page 3 Data Page 0 Data Page 0 000000 000000 Address Space System Segment 0 16 MByte 64 KByte MCD02227 Figure 3 1 Memory Areas and Address Space Semiconductor Group 3 1 Version 1 0 11 97 SIEMENS Memory Organization C164Cl Most internal memory areas are mapped into segment 0 the system segment The upper 4 KByte of segment 0 00 FO00 00 FFFF hold the Internal RAM and Special Function Register Areas SFR and ESFR The lower 32 KByte of segment 0 00 0000 00 7FFF j may be occupied by a part of the on chip ROM Flash OTP memory and is called the Internal ROM area This ROM area can be remapped to segment 1 01 0000 01 7FFF j to enable external memory access in the lower half of segment 0 or the internal ROM may be disabled at all Code and data may be stored in any part of the internal memory areas except for the SFR blocks which may be used for control data but not for instructions Note Accesses to the internal ROM area on ROMless devices will produce unpredictable results Bytes are store
399. s Control Registers Interrupt Control Al Functi SSCCON SSCTIC SSCRIC SSCEIC SCLK P3 13 MTSR P3 9 MRST P3 8 ODP3 Port 3 Open Drain Control Register DP3 Port 3 Direction Control Register P3 Port 3 Data Register SSCBR SSC Baud Rate Generator Reload Register SSCCON SSC Control Register SSCTB SSC Transmit Buffer Register write only SSCRB SSC Receive Buffer Register read only SSCTIC SSC Transmit Interrupt Control Register SSCRIC SSC Receive Interrupt Control Register SSCEIC SSC Error Interrupt Control Register Figure 12 1 SFRs and Port Pins associated with the SSC Semiconductor Group 12 1 Version 1 0 11 97 SIEM ENS The High Speed Synchronous Serial Interface C164CI Slave Clock CPU Baud Rate Clock Clock ee Master Clock 18 SCLK Shift Clock Receive Int Request Transmit Int Request SSC Control Block Error Int Request Status Control MTSR Pin Control 16 Bit Shift Register MRST Transmit Buffer Receive Buffer Register SSCTB Register SSCRB Internal Bus lt _InternalBus 7 MCB01957 Figure 12 2 Synchronous Serial Channel SSC Block Diagram The operating mode of the serial channel SSC is controlled by its bit addressable control register SSCCON This register serves for two purposes during programming SSC disabled by SSCEN 0 it provides access to a set of control bits during operation SSC enabled by SSCEN 1 it p
400. s Interface C164CI ADDRSEL1 FE18 0C SFR Reset Value 00004 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADDRSEL2 FE1Aj OD SFR Reset Value 00004 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADDRSEL3 FE1C OE SFR Reset Value 00004 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADDRSEL4 FE1E OF SFR Reset Value 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 UJ it Function RGSZ Range Size Selection Defines the size of the address area controlled by the respective BUSCONx ADDRSELx register pair See table below RGSAD Range Start Address Defines the upper bits of the start address A23 of the respective address area See table below Note There is no register ADDRSELO as register BUSCONO controls all external accesses outside the four address windows of BUSCON4 BUSCON1 within the complete address space Semiconductor Group 9 17 Version 1 0 11 97 SIEMENS The External Bus Interface C164CI Definition of Address Areas The four register pairs BUSCON4 ADDRSEL4 BUSCON1 ADDRSEL1 allow to define 4 separate address areas within the address space of the C164Cl Within each of these address areas external accesses can be controlled by one of the four different bus modes independent of each other and of the bus mode specified in register BUSCONO Each ADDRSELx register in a way cuts out an address window within which the parameters in register BUSCONXx are used to control external accesses The range start ad
401. s POL 5 to POL 2 SMOD select special operation modes of the C164CI during reset see table below Make sure to only select valid configurations in order to ensure proper operation of the C164Cl Definition of Special Modes for Reset Configuration P0 5 2 Special Mode Notes POL 5 2 1 1 1 1 Normal Start Default configuration Begin of execution as defined via pin EA 11 1 0 CPU Host Mode CPU programming mode for OTP memory CHM 1 1 0 1 Reserved Do not select this configuration 1 1 0 0 Reserved Do not select this configuration 1 0 1 1 Bootstrap Loader Load boot routine via ASCO 1 0 1 O Bootstrap Loader Serial OTP programming via ASCO using the bootstrap CHM loader 1 0 1 Reserved Do not select this configuration 1 0 Reserved Do not select this configuration 0 1 1 External Host Mode Programming mode for OTP memory via external host EHM Requires emulation mode O 1 1 O Reserved Do not select this configuration O 1 0 1 Reserved Do not select this configuration O 1 0 0 Reserved Do not select this configuration 0 0 X X Reserved Do not select this configuration The on chip Bootstrap Loader allows moving the start code into the internal RAM of the C164Cl via the serial interface ASCO The C164CI will remain in bootstrap loader mode until a hardware reset not selecting BSL mode or a software reset Default The C164CI starts fetching code from loc
402. s and M S control Note The target of an access to SSCCON control bits or flags is determined by the state of SSCEN prior to the access ie writing C0574 to SSCCON in programming mode SSCEN 0 will initialize the SSC SSCEN was 0 and then turn it on SSCEN 1 When writing to SSCCON make sure that reserved locations receive zeros The shift register of the SSC is connected to both the transmit pin and the receive pin via the pin control logic see block diagram Transmission and reception of serial data is synchronized and takes place at the same time ie the same number of transmitted bits is also received Transmit data is written into the Transmit Buffer SSCTB It is moved to the shift register as soon as this is empty An SSC master SSCMS 1 immediately begins transmitting while an SSC slave SSCMS 0 will wait for an active shift clock When the transfer starts the busy flag SSCBSY is set and a transmit interrupt request SSCTIR will be generated to indicate that SSCTB may be reloaded again When the programmed number of bits 2 16 has been transferred the contents of the shift register are moved to the Receive Buffer SSCRB and a receive interrupt request SSCRIR will be generated If no further transfer is to take place SSCTB is empty SSCBSY will be cleared at the same time Software should not modify SSCBSY as this flag is hardware controlled Note Only one SSC etc can be master at a given tim
403. s been selected by programming the CP register the desired portions of the internal memory can easily be initialized via indirect addressing At the end of the initialization the interrupt system may be globally enabled by setting bit IEN in register PSW Care must be taken not to enable the interrupt system before the initialization is complete in order to avoid eg the corruption of internal memory locations by stack operations using an uninitialized stack pointer The software initialization routine should be terminated with the EINIT instruction This instruction has been implemented as a protected instruction Semiconductor Group 20 7 Version 1 0 11 97 SIEMENS System Reset C164CI The execution of the EINIT instruction e disables the action of the DISWDT instruction disables write accesses to register SYSCON all configurations regarding register SYSCON enable CLKOUT stacksize etc must be selected before the execution of EINIT disables write accesses to registers SYSCON2 and SYSCONS further write accesses to SYSCON2 and SYSCONS can be executed only using a special unlock mechanism e clears the reset source detection bits in register WDTCON causes the RSTOUT pin to go high this signal can be used to indicate the end of the initialization routine and the proper operation of the microcontroller to external hardware System Startup Configuration Although most of the programmable features of the C164Cl are e
404. s feature detects false additional or missing pulses on the clock line within a certain frame Note If this error condition occurs and bit SSCAREN 1 an automatic reset of the SSC will be performed in case of this error This is done to reinitialize the SSC if too few or too many clock pulses have been detected Semiconductor Group 12 12 Version 1 0 11 97 SIEM ENS The High Speed Synchronous Serial Interface C164CI A Transmit Error Slave mode is detected when a transfer was initiated by the master shift clock gets active but the transmit buffer SSCTB of the slave was not updated since the last transfer This condition sets the error flag SSCTE and when enabled via SSCTEN the error interrupt request flag SSCEIR If a transfer starts while the transmit buffer is not updated the slave will shift out the old contents of the shift register which normally is the data received during the last transfer This may lead to the corruption of the data on the transmit receive line in half duplex mode open drain configuration if this slave is not selected for transmission This mode requires that slaves not selected for transmission only shift out ones ie their transmit buffers must be loaded with FFFF p prior to any transfer Note A slave with push pull output drivers which is not selected for transmission will normally have its output drivers switched However in order to avoid possible conflicts or misinterpretations it is re
405. s for today s microcontrollers Complex control algorithms have to be processed based on a large number of digital as well as analog input signals and the appropriate output signals must be generated within a defined maximum response time Embedded control applications also are often sensitive to board space power consumption and overall system cost Embedded control applications therefore require microcontrollers which offer a high level of system integration e eliminate the need for additional peripheral devices and the associated software overhead provide system security and fail safe mechanisms provide effective means to control and reduce the device s power consumption With the increasing complexity of embedded control applications a significant increase in CPU performance and peripheral functionality over conventional 8 bit controllers is required from microcontrollers for high end embedded control systems In order to achieve this high performance goal Siemens has decided to develop its family of 16 bit CMOS microcontrollers without the constraints of backward compatibility Of course the architecture of the 16 bit microcontroller family pursues successfull hardware and software concepts which have been established in Siemens popular 8 bit controller families About this Manual This manual describes the functionality of a number of 16 bit microcontrollers of the Siemens C166 family the C164 class As these micro
406. s the system configuration via register SYSCON eg the mapping of the internal ROM segmentation stack size cannot use the new resources eg ROM or stack In these cases an instruction that does not access these resources should be inserted Code accesses to the new ROM area are only possible after an absolute branch to this area Note As a rule instructions that change ROM mapping should be executed from internal RAM or external memory e BUSCON ADDRSEL The instruction following an instruction that changes the properties of an external address area cannot access operands within the new area In these cases an instruction that does not access this address area should be inserted Code accesses to the new address area should be made after an absolute branch to this area Note As a rule instructions that change external bus properties should not be executed from the respective external memory area e Timing Instruction pipelining reduces the average instruction processing time in a wide scale from four to one machine cycles mostly However there are some rare cases where a particular pipeline situation causes the processing time for a single instruction to be extended either by a half or by one machine cycle Although this additional time represents only a tiny part of the total program execution time it might be of interest to avoid these pipeline caused time delays in time critical program modules Besides a general execution t
407. s used and each pipeline stage receives control signals staged in control registers from the decode stage PLAs Pipeline holds are primarily caused by wait states for external memory accesses and cause the holding of signals in the control registers Multiple cycle instructions are performed through instruction injection and simple internal state machines which modify required control signals High Function 8 bit and 16 bit Arithmetic and Logic Unit All standard arithmetic and logical operations are performed in a 16 bit ALU In addition for byte operations signals are provided from bits six and seven of the ALU result to correctly set the condition flags Multiple precision arithmetic is provided through a CARRY IN signal to the ALU from previously calculated portions of the desired operation Most internal execution blocks have been optimized to perform operations on either 8 bit or 16 bit quantities Once the pipeline has been filled one instruction is completed per machine cycle except for multiply and divide An advanced Booth algorithm has been incorporated to allow four bits to be multiplied and two bits to be divided per machine cycle Thus these operations use two coupled 16 bit registers MDL and MDH and require four and nine machine cycles respectively to perform a 16 bit by 16 bit or 32 bit by 16 bit calculation plus one machine cycle to setup and adjust the operands and the result Even these longer multiply and divide instructions
408. sage has been set The last message object has the highest interrupt priority of all message objects 1 2 N Message N Interrupt Bit INTPND in the Message Control Register of message object N has been set N 1 14 Note that a message interrupt code is only displayed if there is no other interrupt request with a higher priority 1 1 Bit INTPND of the corresponding message object has to be cleared to give messages with a lower priority the possibility to update INTID or to reset INTID to OO idle state Semiconductor Group 19 9 Version 1 0 11 97 SIEMENS The On Chip CAN Interface C164CI Configuration of the Bit Timing According to the CAN protocol specification a bit time is subdivided into four segments Sync segment propagation time segment phase buffer segment 1 and phase buffer segment 2 Each segment is a multiple of the time quantum tg with tg BRP 1 2 CLK The Synchronization Segment Sync seg is always 1 t long The Propagation Time Segment and the Phase Buffer Segment1 combined to Tseg1 defines the time before the sample point while Phase Buffer Segment2 Tseg2 defines the time after the sample point The length of these segments is programmable except Sync Seg Note For exact definition of these segments please refer to the CAN Specification 1 bit time TSeg1 1 ife Usum sample point transmit point Figure 19 3 Bit Timing Definition Bit Timing Regis
409. see table below GPT1 Auxiliary Timer Counter Mode Input Edge Selection T21 TAI Triggering Edge for Counter Increment Decrement X00 None Counter Tx is disabled 00 1 Positive transition rising edge on TxIN 010 Negative transition falling edge on TxIN 0 1 1 Any transition rising or falling edge on TxIN 101 Positive transition rising edge of output toggle latch T3OTL 110 Negative transition falling edge of output toggle latch T3OTL 111 Any transition rising or falling edge of output toggle latch T3OTL Note Only state transitions of T3OTL which are caused by the overflows underflows of T3 will trigger the counter function of T2 T4 Modifications of T3OTL via software will NOT trigger the counter function of T2 T4 Semiconductor Group 10 13 Version 1 0 11 97 SIEM ENS The General Purpose Timer Unit C164Cl For counter operation pin TxIN must be configured as input ie the respective direction control bit must be 0 The maximum input frequency which is allowed in counter mode is fcpy 16 To ensure that a transition of the count input signal which is applied to TxIN is correctly recognized its level should be held for at least 8 fcpy cycles before it changes Timer Concatenation Using the toggle bit T3OTL as a clock source for an auxiliary timer in counter mode concatenates the core timer T3 with the respective auxiliary timer Depending on which transition of T3OTL is selected to c
410. select the count source and transition if the source is the input pin which should cause a count trigger see description of T78CON for the possible selections Note In order to use pin T7IN as external count input pin the respective port pin must be configured as input ie the corresponding direction control bit must be cleared DPx y 0 If the respective port pin is configured as output the associated timer may be clocked by modifying the port output latches Px y via software eg for testing purposes The maximum external input frequency to T7 in counter mode is fep j 16 To ensure that a signal transition is properly recognized at the timer input an external count input signal should be held for at least 8 CPU clock cycles before it changes its level again The incremented count value appears in SFR T7 within 8 CPU clock cycles after the signal transition at pin T7IN Reload A reload of a timer with the 16 bit value stored in its associated reload register in both modes is performed each time a timer would overflow from FFFF to 00004 In this case the timer does not wrap around to 0000p but rather is reloaded with the contents of the respective reload register TxREL The timer then resumes incrementing starting from the reloaded value The reload registers TxREL are not bitaddressable Semiconductor Group 16 7 Version 1 0 11 97 SIEMENS The Capture Compare Unit CAPCOM2 C164Cl 16 2 CAPCOM Unit Timer Interrupts Upon
411. ses mnemonic reg or bitoff within a range from FO to FFy interpret the four least significant bits as short 4 bit GPR address while the four most significant bits are ignored The respective physical GPR address calculation is identical to that for the short 4 bit GPR addresses For single bit accesses on a GPR the GPR s word address is calculated as just described but the position of the bit within the word is specified by a separate additional 4 bit value Semiconductor Group 4 23 Version 1 0 11 97 SIEMENS The Central Processing Unit CPU C164CI Specified by reg or bitoff Context 1111 4 Bit GPR Pointer Address Internal RAM Must be l within the internal RAM area For byte GPR For word GPR accesses accesses MCD02005 Figure 4 8 Implicit CP Use by Short GPR Addressing Modes The Stack Pointer SP This non bit addressable register is used to point to the top of the internal system stack TOS The SP register is pre decremented whenever data is to be pushed onto the stack and it is post incremented whenever data is to be popped from the stack Thus the system stack grows from higher toward lower memory locations Since the least significant bit of register SP is tied to 0 and bits 15 through 12 are tied to 1 by hardware the SP register can only contain values from F000 to FFFEy This allows to access a physical stack within the internal RAM of the C164Cl A virtual stack usually
412. set to 1 With this configuration the initial state of the output signal can be programmed or its state can be modified at any time by writing to the port output latch In compare mode 3 the port latch is set upon a compare event and cleared upon a timer overflow see Timing Example above However when compare value and reload value for a channel are equal the respective interrupt requests will be generated only the output signal is not changed set and clear would coincide in this case Note If the port output latch is written to by software at the same time it would be altered by a compare event the software write will have priority In this case the hardware triggered change will not become effective On channels 24 27 compare mode 3 will generate interrupt requests but no output function is provided Semiconductor Group 16 16 Version 1 0 11 97 SIEMENS The Capture Compare Unit CAPCOM2 C164Cl Double Register Compare Mode In double register compare mode two compare registers work together to control one output pin This mode is selected by a special combination of modes for these two registers For double register mode the 8 capture compare registers of the CAPCOM2 unit are regarded as two banks of 4 registers each Registers CC16 CC19 form bank 1 while registers CC24 CC27 form bank 2 respectively For double register mode a bank 1 register and a bank 2 register form a register pair Both registers of this regist
413. set was caused by a watchdog timer overflow the WDTR Watchdog Timer Reset Indication flag in register WDTCON will be set to 1 This indicates the cause of the internal reset to the software initialization routine WDTR is reset to 0 by an external hardware reset by servicing the watchdog timer or after EINIT After the internal reset has completed the operation of the watchdog timer can be disabled by the DISWDT Disable Watchdog Timer instruction This instruction has been implemented as a protected instruction For further security its execution is only enabled in the time period after a reset until either the SRVWDT Service Watchdog Timer or the EINIT instruction has been executed Thereafter the DISWDT instruction will have no effect Reset Values for the C164Cl Registers During the reset sequence the registers of the C164Cl are preset with a default value Most SFRs including system registers and peripheral control and data registers are cleared to zero so all peripherals and the interrupt system are off or idle after reset A few exceptions to this rule provide a first pre initialization which is either fixed or controlled by input pins DPP1 0001 points to data page 1 DPP2 0002 points to data page 2 DPP3 0003 points to data page 3 CP FCO00 STKUN FCOO STKOV FA00 SP FCO00 WDTCON 00XXj value depends on the reset source SORBUF XX undefined SSCRB XXXXj undefined SYSCON 0XXO0j set according
414. share the 2 highest priority levels Trap Functions Trap functions are activated in response to special conditions that occur during the execution of instructions A trap can also be caused externally by the Non Maskable Interrupt pin NMI Several hardware trap functions are provided for handling erroneous conditions and exceptions that arise during the execution of an instruction Hardware traps always have highest priority and cause immediate system reaction The software trap function is invoked by the TRAP instruction which generates a software interrupt for a specified interrupt vector For all types of traps the current program status is saved on the system stack External Interrupt Processing Although the C164CI does not provide dedicated interrupt pins it allows to connect external interrupt sources and provides several mechanisms to react on external events including standard inputs non maskable interrupts and fast external interrupts These interrupt functions are alternate port functions except for the non maskable interrupt and the reset input Semiconductor Group 5 1 Version 1 0 11 97 SIEMENS Interrupt and Trap Functions C164CI 5 1 Interrupt System Structure The C164CI provides 32 separate interrupt nodes that may be assigned to 16 priority levels In order to support modular and consistent software design techniques most sources of an interrupt or PEC request are supplied with a separate interrupt control register a
415. shift right operation can be estimated up to a quantity of one half of the LSB of the result In conjunction with the V flag the C flag allows evaluating the rounding error with a finer resolution see table below For Boolean bit operations with only one operand the V flag is always cleared For Boolean bit operations with two operands the V flag represents the logical ORing of the two specified bits Semiconductor Group 4 15 Version 1 0 11 97 SIEMENS The Central Processing Unit CPU C164CI Shift Right Rounding Error Evaluation C Flag V Flag Rounding Error Quantity 0 0 No rounding error 0 1 0 Rounding error lt 1 2 LSB 1 0 Rounding error 1 3 LSB 1 1 Rounding error gt 1 2 LSB e Z Flag The Z flag is normally set to 1 if the result of an ALU operation equals zero otherwise it is cleared For the addition and subtraction with carry the Z flag is only set to 1 if the Z flag already contains a 1 and the result of the current ALU operation additionally equals zero This mechanism is provided for the support of multiple precision calculations For Boolean bit operations with only one operand the Z flag represents the logical negation of the previous state of the specified bit For Boolean bit operations with two operands the Z flag represents the logical NORing of the two specified bits For the prioritize ALU operation the Z flag indicates if the second operand was zero or not e E Flag The E f
416. shifting ASHR Prioritize Instruction Determination of the number of shift cycles required to normalize a word operand floating point support PRIOR Data Movement Instructions Standard data movement of a word or byte MOV MOVB Data movement of a byte to a word location with either sign or zero byte extension MOVBS MOVBZ Note The data movement instructions can be used with a big number of different addressing modes including indirect addressing and automatic pointer in decrementing System Stack Instructions Pushing of a word onto the system stack PUSH Popping of a word from the system stack POP Saving of a word on the system stack and then updating the old word with a new value provided for register bank switching SCXT Semiconductor Group 24 2 Version 1 0 11 97 SIEMENS Instruction Set Summary C164CI Jump Instructions Conditional jumping to an either absolutely indirectly or relatively addressed target instruction within the current code segment Unconditional jumping to an absolutely addressed target instruction within any code segment Conditional jumping to a relatively addressed target instruction within the current code segment depending on the state of a selectable bit Conditional jumping to a relatively addressed target instruction within the current code segment depending on the state of a selectable bit with a post inversion of the tested bit in case of jump take
417. sible to transfer data via the serial interface into an external RAM using a second level loader routine ROM memory internal or external is not necessary However it may be used to provide lookup tables or may provide core code ie a set of general purpose subroutines eg for IO operations number crunching system initialization etc 32 bytes 6 Int Boot ROM BSL routine user software 1 BSL initialization time gt 2us fcpy 20 MHz 2 Zero byte 1 start bit eight 0 data bits 1 stop bit sent by host 3 Identification byte sent by C164CI A 32 bytes of code data sent by host Caution TxDO is only driven a certain time after reception of the zero byte 2 5us fepy 20 MHz 9 Internal Boot ROM o Figure 15 1 Bootstrap Loader Sequence The Bootstrap Loader may be used to load the complete application software into ROMless systems it may load temporary software into complete systems for testing or calibration it may also be used to load a programming routine for Flash devices The BSL mechanism may be used for standard system startup as well as only for special occasions like system maintenance firmware update or end of line programming or testing Semiconductor Group 15 1 Version 1 0 11 97 SIEMENS The Bootstrap Loader C164Cl Entering the Bootstrap Loader The C164Cl enters BSL mode if pin POL 4 is sampled low at the end of a hardware reset In this case the built
418. significant bits of the upper limit of the physical stack area 00 FBFE This transformation is done via hardware see figure below The reset values STKOVZFAO0 STKUN ZFCOO SPZFCO00 STKSZz000g map the virtual stack area directly to the physical stack area and allow using the internal system stack without any changes provided that the 256 word area is not exceeded Semiconductor Group 22 5 Version 1 0 11 97 SIEMENS System Programming C164CI FBFE 11111011 11111110 FBFE 1111 1011 1111 1110 FB80 1 1 1 1 101 1 1000 0000 Phys A FAOO 1 1 1 1 10 0000 0000 FB80 1111 1011 1000 0000 lt sP gt Feoo 1111 1000 0000 0000 After PUSH l After PUSH rare 1111 1011 1111 1110 FBFE4 1111 10 11111110 rare 1111 1011 11 11 1110 Physa FBFE Doin 1010 1111 1110 1111 01 11111110 FB7E 1 1 1 1 1011 0111 1110 lt SP gt F7FE 64 words Stack Size 256 words Figure 22 1 Physical Stack Address Generation The following example demonstrates the circular stack mechanism which is also an effect of this virtual stack mapping First register R1 is pushed onto the lowest physical stack location according to the selected maximum stack size With the following instruction register R2 will be pushed onto the highest physical stack location although the SP is decremented by 2 as for the previous push operation MOV SP 0F802H Set SP before last entry 0f physical stack of 256 words
419. spond to a completed PEC block transfer Note Modifying the Interrupt Request flag via software causes the same effects as if it had been set or cleared by hardware Interrupt Priority Level and Group Level The four bits of bit field ILVL specify the priority level of a service request for the arbitration of simultaneous requests The priority increases with the numerical value of ILVL so 0000g is the lowest and 1111g is the highest priority level When more than one interrupt request on a specific level gets active at the same time the values in the respective bit fields GLVL are used for second level arbitration to select one request for being serviced Again the group priority increases with the numerical value of GLVL so 00g is the lowest and 11g is the highest group priority Note All interrupt request sources that are enabled and programmed to the same priority level must always be programmed to different group priorities Otherwise an incorrect interrupt vector will be generated Semiconductor Group 5 6 Version 1 0 11 97 SIEMENS Interrupt and Trap Functions C164CI Upon entry into the interrupt service routine the priority level of the source that won the arbitration and who s priority level is higher than the current CPU level is copied into bit field ILVL of register PSW after pushing the old PSW contents on the stack The interrupt system of the C164CI allows nesting of up to 15 interrupt service routines of different
420. sses data independently and communicates information over common buses Peripherals are controlled by data written to the respective Special Function Registers SFRs These SFRs are located either within the standard SFR area 00 FEOOQ 00 FFFF or within the extended ESFR area 00 F000 00 F1FF j These built in peripherals either allow the CPU to interface with the external world or provide functions on chip that otherwise were to be added externally in the respective system The C164Cl generic peripherals are A General Purpose Timer Block GPT1 Two Serial Interfaces ASCO and SSC A Watchdog Timer Two Capture Compare units CAPCOM2 and CAPCOMO A 10 bit Analog Digital Converter Six IO ports with a total of 59 IO lines Each peripheral also contains a set of Special Function Registers SFRs which control the functionality of the peripheral and temporarily store intermediate data results Each peripheral has an associated set of status flags Individually selected clock signals are generated for each peripheral from binary multiples of the CPU clock Peripheral Interfaces The on chip peripherals generally have two different types of interfaces an interface to the CPU and an interface to external hardware Communication between CPU and peripherals is performed through Special Function Registers SFRs and interrupts The SFRs serve as control status and data registers for the peripherals Interrupt requests a
421. ster If the content of the SP register is greater than the the content of the STKUN register a stack underflow hardware trap will occur Since the least significant bit of register STKUN is tied to 0 and bits 15 through 12 are tied to 1 by hardware the STKUN register can only contain values from FOOO to FFFEy STKUN FE16 OB SFR Reset Value FC00 15 14 11 10 9 8 7 6 5 4 3 2 1 0 13 12 r r r r rw r Bit Function stkun Modifiable portion of register STKUN Specifies the upper limit of the internal system stack The Stack Underflow Trap entered when SP gt STKUN may be used in two different ways Fatal error indication treats the stack underflow as a system error through the associated trap service routine Automatic system stack refilling allows to use the system stack as a Stack Cache for a bigger external user stack In this case register STKUN should be initialized to a value which represents the desired highest Bottom of Stack address More details about the stack underflow trap service routine and virtual stack management are given in chapter System Programming Scope of Stack Limit Control The stack limit control realized by the register pair STKOV and STKUN detects cases where the stack pointer SP is moved outside the defined stack area either by ADD or SUB instructions or by PUSH or POP operations explicit or implicit ie CALL or RET instructions This control mechanism
422. ster itself or its shadow latch see description below is accessed This is indicated in column Read In addition there are 4 interrupt node control registers associated with the CAPCOM6 unit which are not part of the module however Semiconductor Group 17 18 Version 1 0 11 97 SIEMENS The Capture Compare Unit CAPCOM6 C164Cl Shadow Latches for Synchronous Update The timer period offset and compare values are written to shadow latches rather than to the actual registers Thus the values for a new output signal can be programmed without disturbing the currently generated signal s The transfer from the latches to the registers is enabled by setting the respective shadow latch transfer enable bit STEx in register CTCON If the transfer is enabled the shadow latches are copied to the respective registers as soon as the associated timer reaches the value zero the next time being cleared in edge aligned mode or counting down from 1 in center aligned mode When timer T12 is operating in center aligned mode it will also copy the latches if enabled if it reaches the currently programmed period value counting up After the transfer the respective bit STEx is cleared automatically Note When starting timer T12 for the first time after reset the shadow latch transfer is done automatically For timer T13 bit STE13 1 is also required for the first start Note If a new compare value is written to the shadow latches whi
423. struction and the byte following the opcode is not the complement of the opcode the PRTFLT flag in register TFR is set and the CPU enters the protection fault trap routine The protected instructions include DISWDT EINIT IDLE PWRDN SRST and SRVWDT The IP value pushed onto the system stack for the protection fault trap is the address of the instruction that caused the trap Illegal Word Operand Access Trap Whenever a word operand read or write access is attempted to an odd byte address the ILLOPA flag in register TFR is set and the CPU enters the illegal word operand access trap routine The IP value pushed onto the system stack is the address of the instruction following the one which caused the trap Illegal Instruction Access Trap Whenever a branch is made to an odd byte address the ILLINA flag in register TFR is set and the CPU enters the illegal instruction access trap routine The IP value pushed onto the system stack is the illegal odd target address of the branch instruction Illegal External Bus Access Trap Whenever the CPU requests an external instruction fetch data read or data write and no external bus configuration has been specified the ILLBUS flag in register TFR is set and the CPU enters the illegal bus access trap routine The IP value pushed onto the system stack is the address of the instruction following the one which caused the trap Semiconductor Group 5 28 Version 1 0 11 97 SIEMENS Clock Generation C164CI
424. struction must be inserted between a CP changing and a subsequent GPR using instruction as shown in the following example In SCXT CP 4 amp 0FCOOh select a new context lat Lo must not be an instruction using a GPR Ini2 MOV RO datax write to GPR 0 in the new context e Data Page Pointer Updating An instruction which calculates a physical operand address via a particular DPPn n 0 to 3 register is mostly not capable of using a new DPPn register value which is to be updated by an immediately preceding instruction Thus to make sure that the new DPPn register value is used at least one instruction must be inserted between a DPPn changing instruction and a subsequent instruction which implicitly uses DPPn via a long or indirect addressing mode as shown in the following example In MOV DPP9O 4 select data page 4 via DPPO lat eu must not be an instruction using DPPO Ini2 MOV DPP0 0000H R1 move contents of R1 to address location 01 0000 in data page 4 supposed segmentation is enabled e Explicit Stack Pointer Updating None of the RET RETI RETS RETP or POP instructions is capable of correctly using a new SP register value which is to be updated by an immediately preceding instruction Thus in order to use the new SP register value without erroneously performed stack accesses at least one instruction must be inserted between an explicitly SP writing and any subsequent of the just mentioned implicitly SP usi
425. subroutine can be pushed onto the stack and the previous values be popped before returning to the calling routine This is the most common technique used today and it does provide a mechanism to support recursive procedures This method however requires two machine cycles per register stored on the system stack one cycle to PUSH the register and one to POP the register Use of the System Stack for Local Registers It is possible to use the SP and CP to set up local subroutine register frames This enables subroutines to dynamically allocate local variables as needed within two machine cycles A local frame is allocated by simply subtracting the number of required local registers from the SP and then moving the value of the new SP to the CP Semiconductor Group 22 9 Version 1 0 11 97 SIEMENS System Programming C164CI This operation is supported through the SCXT switch context instruction with the addressing mode reg mem Using this instruction saves the old contents of the CP on the system stack and moves the value of the SP into CP see example below Each local register is then accessed as if it was a normal register Upon exit from the subroutine first the old CP must be restored by popping it from the stack and then the number of used local registers must be added to the SP to restore the allocated local space back to the system stack Note The system stack is growing downwards while the register bank is growing upwards
426. t words and each programming cycle takes about 100 uus OTP programming requires an external programming voltage of Vpp 11 5 V 5 which is applied to pin EA Vpp The OTP memory can be programmed in CPU Host Mode CHM via software or in External Host Mode EHM via external hardware 10ns 100ns ADDR E OTP Word Address i i DATA ME Programming Data 100pus s 120ns WR i i 1 Vpp 9uis y gions EA Vpp 1 2 lt Vpp 50ns 50ns 1 Earliest possible begin of next programming cycle 2 Wpp must be switched off for verify accesses It may remain on for subsequent programming cycles The special signal RSEL must fulfill the same timing requirements as the address lines All timings represent minimum values Figure 3 5 OTP Programming Cycle Verify cycles may be executed to ensure correct programming Programming cycles and verify cycles may alternate in order to check each word immediately However the total programing time can be reduced by programming blocks of data continuously and then verifying the blocks this saves the Vpp settling time Note The programming voltage Vpp must be applied for all programming cycles and must be removed for all other accesses ie verify cycles and standard read cycles The settling time is 10 uius in each case In EHM this must be controlled by the external host in CHM the CPU may control Vpp via an output port line Semiconductor Group 3 11 Version 1 0 11 97 SIEMENS Me
427. t CSCFG in register SYSCON A latched address chip select signal CSCFG 0 becomes active with the falling edge of ALE and becomes inactive at the beginning of an external bus cycle that accesses a different address window No spikes will be generated on the chip select lines and no changes occur as long as locations within the same address window or within internal memory excluding X Peripherals and XRAM are accessed An early address chip select signal CSCFG 1 becomes active together with the address and BHE if enabled and remains active until the end of the current bus cycle Early address chip select signals are not latched internally and may toggle intermediately while the address is changing Note CSO provides a latched address chip select directly after reset except for single chip mode when the first instruction is fetched Internal pullup devices hold all CS lines high during reset After the end of a reset sequence the pullup devices are switched off and the pin drivers control the pin levels on the selected CS lines Not selected CS lines will enter the high impedance state and are available for general purpose IO Segment Address versus Chip Select The external bus interface of the C164Cl supports many configurations for the external memory By increasing the number of segment address lines the C164Cl can address a linear address space of 256 KByte 1 MByte or 4 MByte This allows to implement a large sequential mem
428. t Entry and Exit Interrupt routines are entered when a requesting interrupt has a priority higher than the current CPU priority level Traps are entered regardless of the current CPU priority When either a trap or interrupt routine is entered the state of the machine is preserved on the system stack and a branch to the appropriate trap interrupt vector is made All trap and interrupt routines require the use of the RETI return from interrupt instruction to exit from the called routine This instruction restores the system state from the system stack and then branches back to the location where the trap or interrupt occurred 22 8 Unseparable Instruction Sequences The instructions of the C164Cl are very efficient most instructions execute in one machine cycle and even the multiplication and division are interruptable in order to minimize the response latency to interrupt requests internal and external In many microcontroller applications this is vital Some special occasions however require certain code sequences eg semaphore handling to be uninterruptable to function properly This can be provided by inhibiting interrupts during the respective code sequence by disabling and enabling them before and after the sequence The necessary overhead may be reduced by means of the ATOMIC instruction which allows locking 1 4 instructions to an unseparable code sequence during which the interrupt system standard interrupts and PEC requests an
429. t VPP settle for 10 pysec Select current address Move sorce data word to data register 01H enable module WR active Select OTP module for write access Keep the write signal low for 100 usec 03H enable module cmd idle Trailing edge of write signal This block only for alternating verify External progr voltage Off Let VPP settle for 10 pysec 02H enable module RD active Select OTP module for read access 03H enable module cmd idle Trailing edge of read signal Verify data reg with original data External progr voltage ON Let VPP settle for 10 usec Next OTP location Repeat for the whole data block External progr voltage Off Let VPP settle for 10 pysec Block verification could be executed here OTP module deselected 3 16 Version 1 0 11 97 SIEMENS Memory Organization C164Cl Read Protection Control The on chip OTP memory can be protected against unauthorized accesses read or execute When the read protection is active no programming cycles can be executed neither in EHM nor in CHM no verify cycles can be executed OTP locations can only be read by instructions fetched from the OTP itself The OTP read protection is activated by a specific programming cycle which has the register select signal RSEL active contrary to normal programming cycles This special cycle must write the value 0000 to register address OOOE A verify cycle can be exec
430. t by software For the effects of bits T3UD and T3UDE refer to the direction table below Timer 3 Run Bit The timer can be started or stopped by software through bit T3R Timer T3 Run Bit If T3R 0 the timer stops Setting T3R to 1 will start the timer In gated timer mode the timer will only run if T3R 1 and the gate is active high or low as programmed Semiconductor Group 10 3 Version 1 0 11 97 SIEM ENS The General Purpose Timer Unit C164Cl Count Direction Control The count direction of the core timer can be controlled either by software or by the external input pin T3EUD Timer T3 External Up Down Control Input which is the alternate input function of port pin P3 4 These options are selected by bits T3UD and T3UDE in control register T3CON When the up down control is done by software bit TSUDE 0 the count direction can be altered by setting or clearing bit T3UD When TSUDE 1 pin TSEUD is selected to be the controlling source of the count direction However bit T3UD can still be used to reverse the actual count direction as shown in the table below If T3UDz 0 and pin TSEUD shows a low level the timer is counting up With a high level at T3EUD the timer is counting down If TSUD 1 a high level at pin T3EUD specifies counting up and a low level specifies counting down The count direction can be changed regardless of whether the timer is running or not When pin T3EUD P3 4 is used
431. t significant bit of the result contains a 1 otherwise it is cleared In the case of integer operations the N flag can be interpreted as the sign bit of the result negative N 1 positive N 0 Negative numbers are always represented as the 2 s complement of the corresponding positive number The range of signed numbers extends from 8000 to 7FFF for the word data type or from 80 to 7F for the byte data type For Boolean bit operations with only one operand the N flag represents the previous state of the specified bit For Boolean bit operations with two operands the N flag represents the logical XORing of the two specified bits C Flag After an addition the C flag indicates that a carry from the most significant bit of the specified word or byte data type has been generated After a subtraction or a comparison the C flag indicates a borrow which represents the logical negation of a carry for the addition This means that the C flag is set to 1 if no carry from the most significant bit of the specified word or byte data type has been generated during a subtraction which is performed internally by the ALU as a 2 s complement addition and the C flag is cleared when this complement addition caused a carry The C flag is always cleared for logical multiply and divide ALU operations because these operations cannot cause a carry anyhow For shift and rotate operations the C flag represents the value of the bit shift
432. ta wake up bit mode so each slave can examine the 8 LSBs of the received character the address The addressed slave will switch to 9 bit data mode eg by clearing bit SOM 0 which enables it to also receive the data bytes that will be coming having the wake up bit cleared The slaves that were not being addressed remain in 8 bit data wake up bit mode ignoring the following data bytes Semiconductor Group 11 5 Version 1 0 11 97 Sl EM ENS The Asynchronous Synchronous Serial Interface C164CI Do D1 D2 D3 D4 D5 D7 9th LSB Bit Data Bit D8 Parity Wake up Bit Figure 11 4 Asynchronous 9 bit Data Frames Asynchronous transmission begins at the next overflow of the divide by 16 counter see figure above provided that SOR is set and data has been loaded into SOTBUF The transmitted data frame consists of three basic elements e the start bit the data field 8 or 9 bits LSB first including a parity bit if selected the delimiter 1 or 2 stop bits Data transmission is double buffered When the transmitter is idle the transmit data loaded into SOTBUF is immediately moved to the transmit shift register thus freeing SOTBUF for the next data to be sent This is indicated by the transmit buffer interrupt request flag SOTBIR being set SOTBUF may now be loaded with the next data while transmission of the previous one is still going on The transmit interrupt request flag SOTIR will be set b
433. tation mode is a special multi channel mode which especially supports the control of brushless DC drives In this mode the phase sequence is controlled by 3 input signals CC6POSx which are generated by the drive eg via hall sensors In all modes the output signals can be modulated during their active phases Emergency Interrupt Trap Control CTRAP CC6POSO Multi Channel CC6POS1 P Control CC60 CC61 CC6POS2 EOM Control Cte Logic COUT60 COUT61 COUT62 Capture Channel 0 in Interrupt Capture Mode Period Match COUT63 Interrupt Figure 17 10 Multi Channel Mode Control Semiconductor Group 17 12 Version 1 0 11 97 SIEMENS The Capture Compare Unit CAPCOM6 C164Cl Output Signals in Multi Channel Mode In multi channel mode the output signals are mainly controlled by the selected phase sequence see sequence tables below Each output is active for two phases and remains passive for all other phases of a sequence The active phases of each output signal may additionally be modulated by T12 or T13 For unmodulated active phases timer T12 must operate with 100 duty cycle ie its offset and compare registers must be cleared and T13 modulation must be off ie bits CMSELx3 must be cleared T12 modulation is effective when T12 s duty cycle is programmed below 100 T13 modulation is enabled via bits CMSELx3 see examples in the figure below The figure below shows the 5 phase output waveforms as an example For the ot
434. tchdog timer is a 16 bit up counter which can be clocked with the CPU clock fcpy either divided by 2 or divided by 128 This 16 bit timer is realized as two concatenated 8 bit timers see figure below The upper 8 bits of the watchdog timer can be preset to a user programmable value via a watchdog service access in order to vary the watchdog expire time The lower 8 bits are reset upon each service access jm MUX WDT Low Byte WDTIN WDT High Byte WDTR e RSTOUT Reset WDTREL MCB02052 WDT Control Figure 13 2 Watchdog Timer Block Diagram Semiconductor Group 13 1 Version 1 0 11 97 SIEMENS The Watchdog Timer WDT C164CI Operation of the Watchdog Timer The current count value of the Watchdog Timer is contained in the Watchdog Timer Register WDT which is a non bitaddressable read only register The operation of the Watchdog Timer is controlled by its bitaddressable Watchdog Timer Control Register WDTCON This register specifies the reload value for the high byte of the timer selects the input clock prescaling factor and provides flags that indicate the source of a reset WDTCON FFAE D7 SFR Reset Value 00XX 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 s r r r r rw rw Bit Function WDTIN Watchdog Timer Input Frequency Selection 0 Input frequency is fepy 2 1 Input frequency is fepy 128 WDTR Watchdog Timer Reset Indication Flag Cleared by a hardware reset or by the SRVWDT instruct
435. te P1H y P1L y Alternate Data 1 Output MUX Port Output 0 Latch Read P1H y P1L y P1Hy e Output PiLy Clock Input Latch EXzIN Buffer MCB02232 Figure 7 7 Block Diagram of a PORT1 Pin Semiconductor Group Version 1 0 11 97 SIEMENS Parallel Ports C164CI 7 3 Port3 If this 9 bit port is used for general purpose IO the direction of each line can be configured via the corresponding direction register DP3 Most port lines can be switched into push pull or open drain mode via the open drain control register ODP3 pins P3 15 and P3 12 do not support open drain mode P3 FFC4 E24 SFR Reset Value 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw rw Bit Function P3 y Port data register P3 bit y DP3 FFC6 E34 SFR Reset Value 00004 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DP3 rw rw rw rw rw rw rw rw rw Bit Function DP3 y Port direction register DP3 bit y DP3 y 0 Port line P3 y is an input high impedance DP3 y 1 Port line P3 y is an output ODP3 F1C6 E3 ESFR Reset Value 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ODP3 ODP3 ODP3 ODP3 ODP3 11 10 9 8 6 rw 2 rw rw rw rw s rw S rw Bit Function ODP3 y Port 3 Open Drain control register bit y ODP3 y 0 Port line P3 y output driver in push pull mode ODP3 y 1 Port line P3 y output driver in
436. te of an external 16 bit device WRL together with the signal WRH alternate function of P3 12 BHE During accesses to on chip X Peripherals WR WRL remains inactive high During reset an internal pullup ensures an inactive high level on the WR WRL output The External Access Enable Pin EA VPP determines if the C164Cl after reset starts fetching code from the internal ROM area EA 1 or via the external bus interface EA 0 Be sure to hold this input low for ROMless devices At the end of the internal reset sequence the EA signal is latched together with the PORTO configuration This pin also accepts the external programming voltage that is required to program the on chip OTP memory The Non Maskable Interrupt Input NMI allows to trigger a high priority trap via an external signal eg a power fail signal It also serves to validate the PWRDN instruction that switches the C164Cl into Power Down mode The NMI pin is sampled with every CPU clock cycle to detect transitions The Oscillator Input XTAL1 and Output XTAL2 connect the internal Pierce oscillator to the external crystal The oscillator provides an inverter and a feedback element The standard external oscillator circuitry see chapter Clock Generation comprises the crystal two low end capacitors and series resistor to limit the current through the crystal An external clock signal may be fed to the input XTAL1 leaving XTAL2 open The Reset Input RSTIN allows to
437. tents of T3 Note This example shows the timer behaviour assuming that T3 counts upon any transition on any input ie T3l 011p Figure 10 8 Evaluation of the Incremental Encoder Signals Forward Jitter Backward Jitter Forward Contents of T3 Note This example shows the timer behaviour assuming that T3 counts upon any transition on input T3IN ie T3l 001g Figure 10 9 Evaluation of the Incremental Encoder Signals Note Timer T3 operating in incremental interface mode automatically provides information on the sensor s current position Dynamic information speed acceleration deceleration may be obtained by measuring the incoming signal periods Semiconductor Group 10 10 Version 1 0 11 97 SIEM ENS The General Purpose Timer Unit C164Cl GPT1 Auxiliary Timers T2 and T4 Both auxiliary timers T2 and T4 have exactly the same functionality They can be configured for timer gated timer counter or incremental interface mode with the same options for the timer frequencies and the count signal as the core timer T3 In addition to these 4 counting modes the auxiliary timers can be concatenated with the core timer or they may be used as reload or capture registers in conjunction with the core timer The individual configuration for timers T2 and T4 is determined by their bitaddressable control registers T2CON and T4CON which are both organized identically Note that functions which are pres
438. ter EF04 XReg Reset Value UUUU 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 B TSEG2 TSEG1 SJW BRP r rw rw rw rw Bit Function BRP Baud Rate Prescaler For generating the bit time quanta the CPU frequency is divided by 2 BRP 1 SJW Re Synchronization Jump Width Adjust the bit time by maximum SJW 1 time quanta for resynchronization TSEG1 Time Segment before sample point There are TSEG1 1 time quanta before the sample point Valid values for TSEG1 are 2 15 TSEG2 Time Segment after sample point There are TSEG2 1 time quanta after the sample point Valid values for TSEG2 are 1 7 Note This register can only be written if the configuration change enable bit CCE is set Semiconductor Group 19 10 Version 1 0 11 97 SIEMENS The On Chip CAN Interface C164CI Mask Registers Messages can use standard or extended identifiers Incoming frames are masked with their appropriate global masks Bit IDE of the incoming message determines if the standard 11 bit mask in Global Mask Short is to be used or the 29 bit extended mask in Global Mask Long Bits holding a 0 mean don t care ie do not compare the message s identifier in the respective bit position The last message object 15 has an additional individually programmable acceptance mask Mask of Last Message for the complete arbitration field This allows classes of messages to be received in this object by masking some bits of
439. ter ADDAT is lost because it is overwritten by the new value and the A D overrun error interrupt request flag ADEIR will be set In order to avoid error interrupts and the loss of conversion results especially when using continuous conversion modes the ADC can be switched to Wait for ADDAT Read Mode by setting bit ADWR in register ADCON If the value in ADDAT has not been read by the time the current conversion is complete the new result is stored in a temporary buffer and the next conversion is suspended ADST and ADBSY will remain set in the meantime but no end of conversion interrupt will be generated After reading the previous value from ADDAT the temporary buffer is copied into ADDAT generating an ADCIR interrupt and the suspended conversion is started This mechanism applies to both single and continuous conversion modes Note While in standard mode continuous conversions are executed at a fixed rate determined by the conversion time in Wait for ADDAT Read Mode there may be delays due to suspended conversions However this only affects the conversions if the CPU or PEC cannot keep track with the conversion rate 3 2 1 wait 0 3 Charme OOOO OO aa es of Channel Y Write ADDAT ADDAT Full Temp Latch Full Generate Interrupt Hold Result in Request Temp Latch Read of ADDAT Result of Channel y 3 2 1 x 3 2 1 0 3 MCA01970 Figure 18 4 Wait for Read Mode Example Se
440. ter the reception of the zero byte All other pins remain in the high impedance state until they are changed by software or peripheral operation Semiconductor Group 20 6 Version 1 0 11 97 SIEMENS System Reset C164CI Application Specific Initialization Routine After the internal reset condition is removed the C164CI fetches the first instruction from location 00 0000 which is the first vector in the trap interrupt vector table the reset vector 4 words locations 00 0000 through 00 0006 are provided in this table to start the initialization after reset As a rule this location holds a branch instruction to the actual initialization routine that may be located anywhere in the address space Note When the Bootstrap Loader Mode was activated during a hardware reset the C164Cl does not fetch instructions from location 00 0000 but rather expects data via serial interface ASCO If single chip mode is selected during reset the first instruction is fetched from the internal ROM OTP Flash Otherwise it is fetched from external memory When internal ROM access is enabled after reset in single chip mode bit ROMEN 1 in register SYSCON the software initialization routine may enable and configure the external bus interface before the execution of the EINIT instruction When external access is enabled after reset it may be desirable to reconfigure the external bus characteristics because the BUSCONO register is initialized durin
441. terface C164Cl SOCON FFBO D8p SFR Reset Value 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 so S0 S0 rw rw rw rw rw rw rw rw rw rw rw rw rw Bit Function SOM ASCO Mode Control 000 8 bit data synchronous operation 001 8 bit data async operation 010 Reserved Do not use this combination 011 7 bit data parity async operation 100 9 bit data async operation 101 8 bit data wake up bit async operation 110 Reserved Do not use this combination 111 8 bit data parity async operation SOSTP Number of Stop Bits Selection async operation 0 One stop bit Ts Two stop bits SOREN Receiver Enable Bit 0 Receiver disabled T3 Receiver enabled Reset by hardware after reception of byte in synchronous mode SOPEN Parity Check Enable Bit async operation 0 Ignore parity 1 Check parity SOFEN Framing Check Enable Bit async operation 0 Ignore framing errors 1 Check framing errors SOOEN Overrun Check Enable Bit 0 Ignore overrun errors 1 Check overrun errors SOPE Parity Error Flag Set by hardware on a parity error SOPEN 1 Must be reset by software SOFE Framing Error Flag Set by hardware on a framing error SOFEN 1 Must be reset by software SOOE Overrun Error Flag Set by hardware on an overrun error SOOEN 1 Must be reset by software SOODD Parity Selection Bit 0 Even parity parity bit set on odd number of 1 s in data qu Odd parity parity bit set on even number o
442. that influence the configuration of the C164Cl are evaluated during any reset sequence ie also during software and watchdog timer triggered resets The configuration via POH is latched in register RPOH for subsequent evaluation by software Register RPOH is described in chapter The External Bus Interface Note The load on those pins that shall be latched as 1 must be small enough for the internal pullup device to keep their level high or external pullup devices must ensure the high level Those pins that shall be latched as 0 must be pulled low externally Make sure that the valid target levels are reached until the end of the reset sequence There is a specific application note to illustrate this The following describes the different selections that are offered for reset configuration The default modes refer to pins at high level ie without external pulldown devices connected Please also consider the note above Emulation Mode Pin POL O EMU selects the Emulation Mode when low during reset This mode allows the access to integrated XBUS peripherals via the external bus interface pins in application specific versions of the C164Cl In addition also the RSTOUT pin floats to tristate rather than be driven low When the emulation mode has been latched the CLKOUT output is automatically enabled This mode is used for special emulator purposes and is of no use in basic C164Cl devices except for enabling the external host mode EHM f
443. the CAPCOMSOG Unit Semiconductor Group 17 1 Version 1 0 11 97 SIEMENS The Capture Compare Unit CAPCOM6 C164Cl The three 16 bit capture compare channels are driven via timer T12 and can control two output lines each see Port Control Logic The offset register T12OF allows to shift the switching points of the COUTE6x output line of each channel by shifting the respective compare value The 10 bit compare channel is driven via timer T13 and can control one output line Additional control logic allows the combination of the capture compare channel outputs with the compare channel output or with external signals Thus flexible and complex output patterns can be generated automatically ie with very little or no CPU action at all Period Register T12P Mode Select Register CC6MSEL Trap Register Offset Register d CD aos IER 9 ind COE Eo T120F one 8 E CC Channel 1 pama g gt CC61 S S CC61 S gt COUTE1 a Compare Timer T12 TETTE e eee Bit anne S AA A A Control Register s CTCON Compare Timer T13 Compare Register vocari CMP13 gt COUT63 Block Commutation fopy 7 Prescaler Period Register Control T13P CC6M CON H 1 These Registers are not direct accessable The period and offset registers are loading a value into the timer registers MCB03700 Figure 17 2 CAPCOM6 Block Diagram Two basic operating modes ar
444. the converter through bit ADST the busy flag ADBSY will be set and the channel specified in bit field ADCH will be converted After the conversion is complete the interrupt request flag ADCIR will be set and the converter will automatically start a new conversion of the next lower channel ADCIR will be set after each completed conversion After conversion of channel 0 the current sequence is complete In Single Conversion Mode the converter will automatically stop and reset bits ADBSY and ADST In Continuous Conversion Mode the converter will automatically start a new sequence beginning with the conversion of the channel specified in ADCH When bit ADST is reset by software while a conversion is in progress the converter will complete the current sequence including conversion of channel 0 and then stop and reset bit ADBSY 3 2 1 0 3 2 imm d d A S T T T 3h E ce s Write ADDAT fx 3 2 1 0 3 ADDAT Full ___9L_ LLCO p p Generate Interrupt Request ADDAT Full Read of ADDAT Channnel 0 Result of Channel y 3 82 41 Result Lost 3 Overrun Error Interrupt Request MCA02241 Figure 18 3 Auto Scan Conversion Mode Example Semiconductor Group 18 5 Version 1 0 10 97 SIEMENS The Analog Digital Converter C164Cl Wait for ADDAT Read Mode If in default mode of the ADC a previous conversion result has not been read out of register ADDAT by the time a new conversion is complete the previous result in regis
445. the identifier Note The Mask of Last Message is ANDed with the Global Mask that corresponds to the incoming message Global Mask Short EF06 XReg Reset Value UFUU 15 14 13 11 7 6 5 4 3 2 1 0 12 10 9 8 rw r r r r r nw Bit Function ID28 18 Identifier 11 bit Mask to filter incoming messages with standard identifier Upper Global Mask Long EF08 j XReg Reset Value UUUU 15 14 13 12 11 10 9 83 7 6 5 4 3 2 i04 0 Lower Global Mask Long EFOA XReg Reset Value UUUU 15 14 13 12 11 30 9 8 rw r r r d O C1 A 2 99 N zu eo Bit Function ID28 0 Identifier 29 bit Mask to filter incoming messages with extended identifier Semiconductor Group 19 11 Version 1 0 11 97 SIEMENS The On Chip CAN Interface C164CI Upper Mask of Last Message EFOC XReg Reset Value UUUU 15 14 13 12 11 10 9 83 7 6 5 4 3 2 1i 0 Pauli ass oo mem rw rw rw Lower Mask of Last Message EFOE XReg Reset Value UUUU 15 14 13 32 11 10 9 8 Bit Function ID28 0 Identifier 29 bit Mask to filter the last incoming message Nr 15 with standard or extended identifier as configured Semiconductor Group 19 12 Version 1 0 11 97 SIEMENS The On Chip CAN Interface C164Cl The Message Object The message object is the primary means of communication between CPU and CAN controller Each of the 15 message objects uses 15 consecutive bytes see map below and starts
446. the serial interfaces are enabled the master device can initiate the first data transfer by writing the transmit data into register SSCTB This value is copied into the shift register which is assumed to be empty at this time and the selected first bit of the transmit data will be placed onto the MTSR line on the next clock from the baudrate generator transmission only starts if SSCEN 1 Depending on the selected clock phase also a clock pulse will be generated on the SCLK line With the opposite clock edge the master at the same time latches and shifts in the data detected at its input line MRST This exchanges the transmit data with the receive data Since the clock line is connected to all slaves their shift registers will be shifted synchronously with the master s shift register shifting out the data contained in the registers and shifting in the data detected at the input line After the preprogrammed number of clock pulses via the data width selection the data transmitted by the master is contained in all slaves shift registers while the master s shift register holds the data of the selected slave In the master and all slaves the content of the shift register is copied into the receive buffer SSCRB and the receive interrupt flag SSCRIR is set A slave device will immediately output the selected first bit MSB or LSB of the transfer data at pin MRST when the content of the transmit buffer is copied into the slave s shift reg
447. tifier taking into account the respective global mask register is received over the CAN bus By requesting the transmission of a message with the direction set as receive a remote frame can be sent to request that the appropriate object be sent by some other node Each object has separate transmit and receive interrupts and status bits giving the CPU full flexibility in detecting when a remote data frame has been sent or received For general purpose two masks for acceptance filtering can be programmed one for identifiers of 11 bits and one for identifiers of 29 bits However the CPU must configure bit XTD Normal or Extended Frame Identifier for each valid message to determine whether a standard or extended frame will be accepted The last message object has its own programmable mask for acceptance filtering allowing a large number of infrequent objects to be handled by the system The object layer architecture of the CAN controller is designed to be as regular and orthogonal as possible This makes it easy to use Semiconductor Group 19 1 Version 1 0 11 97 SIEMENS The On Chip CAN Interface C164CI CAN TxD CAN RxD Emus s iine Timing Generator Tx Rx Shift Register e Diese Clocks to all Intelligent Messages g Control Handlers Memory Interrupt Register Status Control to XBUS Register Figure 19 1 CAN Controller Block Diagram Semiconductor Group 19 2
448. ting of the Channel Injection Request bit ADCRQ via software a compare or a capture event of Capture Compare register CC27 of the CAPCOM2 Unit which also sets bit ADCRQ The second method triggers a channel injection at a specific time on the occurrence of a predefined count value of the CAPCOM timers or on a capture event of register CC27 This can be either the positive negative or both the positive and the negative edge of an external signal In addition this option allows recording the time of occurrence of this signal Semiconductor Group 18 7 Version 1 0 10 97 SIEMENS The Analog Digital Converter C164CI Note The channel injection request bit ADCRQ will be set on any interrupt request of CAPCOM2 channel CC27 regardless whether the channel injection mode is enabled or not It is recommended to always clear bit ADCRQ before enabling the channel injection mode After the completion of the current conversion if any is in progress the converter will start inject the conversion of the specified channel When the conversion of this channel is complete the result will be placed into the alternate result register ADDAT2 and a Channel Injection Complete Interrupt request will be generated which uses the interrupt request flag ADEIR for this reason the Wait for ADDAT Read Mode is required Note If the temporary data register used in Wait for ADDAT Read Mode is full the respective next conversion standard or injected will be
449. tion Both Edges at Pin CCxlO 100 Compare Mode 0 Interrupt Only Several interrupts per timer period Enables double register compare mode for registers CC24 CC27 101 Compare Mode 1 Toggle Output Pin on each Match Several compare events per timer period This mode is required for double register compare mode for registers CC16 CC19 110 Compare Mode 2 Interrupt Only Only one interrupt per timer period 111 Compare Mode 3 Set Output Pin on each Match Reset output pin on each timer overflow Only one interrupt per timer period The detailled discussion of the capture and compare modes is valid for all the capture compare channels so registers bits and pins are only referenced by the placeholder x Note Capture compare channels 24 27 generate an interrupt request but do not provide an output signal The resulting exceptions are indicated in the following subsections A capture or compare event on channel 27 may be used to trigger a channel injection on the C164Cl s A D converter if enabled Semiconductor Group 16 10 Version 1 0 11 97 SIEMENS The Capture Compare Unit CAPCOM2 C164Cl 16 4 Capture Mode In response to an external event the content of the associated timer T7 or T8 depending on the state of the allocation control bit ACCx is latched into the respective capture register CCx The external event causing a capture can be programmed to be either a positive a negative or botha positive or a negative
450. tion for actual state Follower State for BCM CC60 COUT61 CC62 COUT60 CC61 COUTS62 01 10 00 11 0 passive passive passive passive passive 2 1 0 6 1 ACTIVE passive passive passive ACTIVE 5 2 0 6 2 ACTIVE ACTIVE passive passive passive 1 3 0 6 3 passive ACTIVE ACTIVE passive passive 2 4 0 6 4 passive passive ACTIVE ACTIVE passive 3 5 0 6 5 passive passive passive ACTIVE ACTIVE 4 1 0 6 6 passive ACTIVE passive ACTIVE S ACTIVE 2 1 0 6 6 phase PWM Sequence Table Output Level Definition for actual state Follower State for BCMz CC60 COUT61 CC62 COUT60 CC61 COUT62 01 10 00 11 passive passive passive passive passive passive ACTIVE ACTIVE passive passive passive passive passive ACTIVE ACTIVE passive passive passive passive passive ACTIVE ACTIVE passive passive passive passive passive ACTIVE ACTIVE passive passive passive passive passive ACTIVE ACTIVE ACTIVE passive passive passive passive ACTIVE NIOJ ROIN State passive ACTIVE passive ACTIVE passive ACTIVE NIAJ AIIN aj P 0 01 25 cCc nm oO Oo oo o o o o NEN PNT NIN NIN Semiconductor Group 17 15 Version 1 0 11 97 SIEMENS
451. tions see figure below Semiconductor Group 6 3 Version 1 0 11 97 SIEMENS Clock Generation C164CI Phase Locked Loop Operation fxTAL fcpu TCLTCL Direct Clock Drive fXTAL fcpu TCL TCL Prescaler Operation fxTAL tu l L TCL 1 TCL SDD Operation fxTAL few ll TL TCL TCL Figure 6 5 Generation Mechanisms for the CPU Clock Direct Drive When direct drive is configured CLKCFG 011 the C164Cl s clock system is directly fed from the external clock input ie fopy fosc This allows operation of the C164Cl with a reasonably small fundamental mode crystal The specified minimum values for the CPU clock phases TCLs must be respected Therefore the maximum input clock frequency depends on the clock signal s duty cycle Prescaler Operation When prescaler operation is configured CLKCFG 001 the C164Cl s input clock is divided by 2 to generate then CPU clock signal ie fcpy fogc 2 This requires the oscillator or input clock to run on 2 times the intended operating frequency but guarantees a 50 duty cycle for the internal clock system independent of the input clock signal s waveform Semiconductor Group 6 4 Version 1 0 11 97 SIEMENS Clock Generation C164CI PLL Operation When PLL operation is configured via CLKCFG the C164Cl s input clock is fed to the on chip phase locked loop circuit which multiplies its frequency by a factor of F 1 5
452. tiplication SAVE JNB MDRIU START Test if MD was in use SCXT MDC 0010H Save and clear control register leaving MDRIU set only required for interrupted multiply divide instructions BSET SAVED indicate the save operation PUSH MDH Save previous MD contents PUSH MDL P On system stack START MULU R1 R2 Multiply 16 16 unsigned Sets MDRIU JMPR cc NV COPYL Test for only 16 bit result MOV R3 MDH Move high portion of MD COPYL MOV R4 MDL Move low portion of MD Clears MDRIU RESTORE JNB SAVED DONE Test if MD registers were saved POP MDL Restore registers POP MDH POP MDC BCLR SAVED Multiplication is completed program continues DONE The above save sequence and the restore sequence after COPYL are only required if the current routine could have interrupted a previous routine which contained a MUL or DIV instruction Register MDC is also saved because it is possible that a previous routine s Multiply or Divide instruction was interrupted while in progress In this case the information about how to restart the instruction is contained in this register Register MDC must be cleared to be correctly initialized for a subsequent multiplication or division The old MDC contents must be popped from the stack before the RETI instruction is executed For a division the user must first move the dividend into the MD register If a 16 16 bit division is specified only the low portion of register MD must be l
453. to external instruction fetches or data read writes but are arbitrated and inserted into the external bus access stream Accesses to the CAN Module use demultiplexed addresses a 16 bit data bus byte accesses possible two waitstates and no tristate waitstate The CAN address area starts at 00 EF0O0 and covers 256 Bytes A dedicated hardwired XADRS XBCON register pair selects the respective address window so none of the programmable register pairs must be sacrificed in order to access the on chip CAN Module Locating the CAN address area to address OO0 EF00 in segment 0 has the advantage that the CAN Module is accessible via data page 3 which is the system data page accessed usually through the system data page pointer DPP3 In this way the internal addresses such like SFRs internal RAM and the CAN registers are all located within the same data page and form a contiguous address space When the CAN Module is disabled by setting bit CANDIS in register SYSCONS no register accesses are possible Also the module s logic blocks are stopped and no CAN bus transfers are possible After re enabling the CAN Module CANDIS 0 it must be reconfigured as after returning from Power Down mode Note Incoming message frames can still be recognized not received in this case by monitoring the receive line CAN RxD For this purpose the receive line CAN RxD can be connected to fast external interrupt EXOIN via register EXISEL Power Do
454. toggle latch T3OTL The maximum resolution of the timers in module GPT1 is 8 CPU clock cycles 16 TCL Watchdog Timer The Watchdog Timer represents one of the fail safe mechanisms which have been implemented to prevent the controller from malfunctioning for longer periods of time The Watchdog Timer is always enabled after a reset of the chip and can only be disabled in the time interval until the EINIT end of initialization instruction has been executed Thus the chip s start up procedure is always monitored The software has to be designed to service the Watchdog Timer before it overflows If due to hardware or software related failures the software fails to do so the Watchdog Timer overflows and generates an internal hardware reset and pulls the RSTOUT pin low in order to allow external hardware components to reset The Watchdog Timer is a 16 bit timer clocked with the CPU clock divided either by 2 or by 128 The high byte of the Watchdog Timer register can be set to a prespecified reload value stored in WDTREL in order to allow further variation of the monitored time interval Each time it is serviced by the application software the high byte of the Watchdog Timer is reloaded Thus time intervals between 25 uus and 420 ms can be monitored 20 MHz The default Watchdog Timer interval after reset is 6 55 ms 20 MHz Semiconductor Group 2 12 Version 1 0 11 97 SIEMENS Architectural Overview C164Cl Capture Compare C
455. tputs a 100 Center Aligned Mode Period value 2 pv Duty cycle of CC6x outputs oo 100 Duty cycle of COUT6x outputs d 100 96 Semiconductor Group 17 9 Version 1 0 11 97 SIEMENS The Capture Compare Unit CAPCOM6 C164Cl 17 5 Burst Mode In burst mode the output signal COUT63 of the 10 bit compare channel modulates the active phases of the output signals COUT6x of the 3 capture compare channels Burst mode is not possible on the CC6x outputs The modulating signal typically has a higher frequency than the modulated output channels The figure below shows an example for a waveform generated in burst mode Burst mode is enabled for each capture compare output separately by setting the respective bit CMSELx3 in register CC6MSEL Count Value A Period Register Compare Timer 1 INTA PST nv Compare Register Start of CT1 EN Time COUTx COINI 1 CMSELx3 0 Burst Mode COUTx Disabled COINI 0 EK ay A V ALAA ala A V ATATA TAT T A V COUT3 COUTx COUTXI 0 COINI 1 COUTSI 0 COUTXI 1 WLLL MULL COUT3I 1 COUT Con COINI 0 COUT3I 1 Note If the Bits COUT3I and COUTXI in the COINI register are identical COUTS and the burst signals at COUTx have the same polarity MCT02605 Figure 17 9 Operation in Burst Mode Semiconductor Group 17 10 Version 1 0 11 97 SIEMENS The Capture Compare Unit CAPCOM6 C164Cl 17 6 Captur
456. truction fetching Critical operations like a software reset are therefore only executed if the complete instruction is decoded without an error This enhances the safety and reliability of a microcontroller system Semiconductor Group 24 4 Version 1 0 11 97 SIEMENS Device Specification C164CI 25 Device Specification The device specification describes the electrical parameters of the device It lists DC characteristics like input output or supply voltages or currents and AC characteristics like timing characteristics and requirements Other than the architecture the instruction set or the basic functions of the C164Cl core and its peripherals these DC and AC characteristics are subject to changes due to device improvements or specific derivatives of the standard device Therefore these characteristics are not contained in this manual but rather provided in a separate Data Sheet which can be updated more frequently Please refer to the current version of the Data Sheet of the respective device for all electrical parameters Note In any case the specific characteristics of a device should be verified before a new design is started This ensures that the used information is up to date The figure below shows the pin diagram of the C164Cl It shows the location of the different supply and IO pins A detailed description of all the pins is also found in the Data Sheet Note Not all alternate functions shown in the figure below
457. truction or when the reset input signal RSTIN is latched low hardware reset The internal reset condition is active at least for the duration of the reset sequence and then until the RSTIN input is inactive and the PLL has locked if the PLL is selected for the basic clock generation When this internal reset condition is removed reset sequence complete RSTIN inactive PLL locked the reset configuration is latched from PORTO and RD and then pins ALE RD and WR are driven to their inactive levels Note Bit ADP which selects the Adapt mode is latched with the rising edge of RSTIN After the internal reset condition is removed the microcontroller will start program execution from memory location 00 0000 in code segment zero This start location will typically hold a branch instruction to the start of a software initialization routine for the application specific configuration of peripherals and CPU Special Function Registers RSTOUT External Hardware External Reset amp Reset Sources a Generated Warm reset b Automatic Power on reset MCA02259 Figure 20 1 External Reset Circuitry Semiconductor Group 20 1 Version 1 0 11 97 SIEMENS System Reset C164CI Hardware Reset A hardware reset is triggered when the reset input signal RSTIN is latched low To ensure the recognition of the RSTIN signal latching it must be held low for at least 2 CPU c
458. ture Compare Unit CAPCOM6 C164CI CC6MSEL F036 1By ESFR Reset Value 0000 15 14 13 12 1 10 9 8 7 6 5 4 3 2 1 0 SEL SEL CMSEL SEL CMSEL2 1 SEL CMSELO ESMCNMCS 23 13 03 rw rw rw rw rw rw rw rw Bit Function CMSELn Capture Compare Mode Selection These bitfields select enable the operating mode and the output input pin configuration of the 16 bit capture compare channels Each channel can be programmed individually either for compare or capture operation 000 Compare outputs disabled CC6n COUTE6n can be used for IO 001 Compare output on pin CC6n COUT6n can be used for IO 010 Compare output on pin COUT6n CC6n can be used for IO 011 Compare output on pins COUT6n and CC6n 100 Capture mode not triggered by CC6n COUTEn is IO 101 Capture mode triggered by a rising edge on pin CC6n COUTEn is IO 110 Capture mode triggered by a falling edge on pin CC6n COUTEn is IO 111 Capture mode triggered by any transition on pin CC6n COUT6n is IO CMSELn3 COUT6n Control by Timer T13 in Compare Mode This bit determines if the output COUT6n is modulated during its active phase defined via register CC6MCON by the output signal of the 10 bit compare channel typically a higher frequency signal 0 COUTE6n drives its active level 1 COUTE6n is modulated by the output signal of the 10 bit compare channel NMCS Next Multi Channel PWM State Valid when ESMC 1 0 Idle 1 Select the next follower state i
459. tware by setting or clearing user specific bits and conditionally branching based on these specific bits It is recommended that bit fields in control SFRs are updated using the BFLDH and BFLDL instructions or a MOV instruction to avoid undesired intermediate modes of operation which can occur when BCLR BSET or AND OR instruction sequences are used Semiconductor Group 22 11 Version 1 0 11 97 SIEMENS System Programming C164CI 22 6 Floating Point Support All floating point operations are performed using software Standard multiple precision instructions are used to perform calculations on data types that exceed the size of the ALU Multiple bit rotate and logic instructions allow easy masking and extracting of portions of floating point numbers To decrease the time required to perform floating point operations two hardware features have been implemented in the CPU core First the PRIOR instruction aids in normalizing floating point numbers by indicating the position of the first set bit in a GPR This result can the be used to rotate the floating point result accordingly The second feature aids in properly rounding the result of normalized floating point numbers through the overflow V flag in the PSW This flag is set when a one is shifted out of the carry bit during shift right operations The overflow flag and the carry flag are then used to round the floating point result based on the desired rounding algorithm 22 7 Trap Interrup
460. uad Flat Pack MQFP Package 0 65 mm 25 6 mil lead spacing surface mount technology Semiconductor Group 1 5 Version 1 0 11 97 SIEMENS Introduction C164CI Complete Development Support For the development tool support of its microcontrollers Siemens follows a clear third party concept Currently around 120 tool suppliers world wide ranging from local niche manufacturers to multinational companies with broad product portfolios offer powerful development tools for the Siemens C500 and C166 microcontroller families guaranteeing a remarkable variety of price performance classes as well as early availability of high quality key tools such as compilers assemblers simulators debuggers or in circuit emulators Siemens incorporates its strategic tool partners very early into the product development process making sure embedded system developers get reliable well tuned tool solutions which help them unleash the power of Siemens microcontrollers in the most effective way and with the shortest possible learning curve The tool environment for the Siemens 16 bit microcontrollers includes the following tools Compilers C MODULA2 FORTH Macro Assemblers Linkers Locaters Library Managers Format Converters Architectural Simulators HLL debuggers Real Time operating systems VHDL chip models In Circuit Emulators based on bondout or standard chips Plug In emulators Emulation and Clip Over adapters production sockets Log
461. uld be decoupled as close to the pins as possible For best results it is recommended to implement two level decoupling eg the widely used 100 nF in parallel with 30 40 pF capacitors which deliver the peak currents Note All VDD pins and all VSS pins must be connected to the power supply and ground respectively Semiconductor Group 8 3 Version 1 0 11 97 SIEMENS The External Bus Interface C164CI 9 The External Bus Interface Although the C164Cl provides a powerful set of on chip peripherals and on chip RAM and ROM OTP Flash except for ROMless versions areas these internal units only cover a small fraction of its address space of up to 16 MByte The external bus interface allows to access external peripherals and additional volatile and non volatile memory The external bus interface provides a number of configurations so it can be taylored to fit perfectly into a given application system Ports amp Direction Control Address Registers Mode Registers Control Registers Alternate Functions POL POH BUSCONO SYSCON BUSCON1 RPOH BUSCON2 BUSCON3 BUSCON4 ADDRSEL3 BHE WRH _ RSTIN RD ALE WR WRL POL POH PORTO Data Registers ADDRSELx Address Range Select Register 1 4 PiL P1H PORT1 Data Registers BUSCONx Bus Mode Control Register 0 4 DP3 Port 3 Direction Control Register SYSCON System Control Register P3 Port 3 Data Register RPOH Port POH Reset Configuration Register P4 Port 4 Data Register Figur
462. ure 10 7 Connection of the Encoder to the C164Cl For incremental interface operation the following conditions must be met e Bitfield T3M must be 110g Both pins T3IN and T3EUD must be configured as input ie the respective direction control bits must be 0 e Bit T3EUD must be 1 to enable automatic direction control The maximum input frequency which is allowed in incremental interface mode is fepy 16 To ensure that a transition of any input signal is correctly recognized its level should be held high or low for at least 8 fcpy cycles before it changes In Incremental Interface Mode the count direction is automatically derived from the sequence in which the input signals change which corresponds to the rotation direction of the connected sensor The table below summarizes the possible combinations GPT1 Core Timer T3 Incremental Interface Mode Count Direction Level on respective TSIN Input TSEUD Input other input Rising s Falling X Rising Falling X High Down Up Up Down Low Up Down Down Up The figures below give examples of T3 s operation visualizing count signal generation and direction control It also shows how input jitter is compensated which might occur if the sensor rests near to one of its switching points Semiconductor Group 10 9 Version 1 0 11 97 SIEM ENS The General Purpose Timer Unit C164Cl Forward Jitter Backward Jitter Forward T3IN Con
463. us Serial Interface The High Speed Synchronous Serial Interface SSC provides flexible high speed serial communication between the C164Cl and other microcontrollers microprocessors or external peripherals The SSC supports full duplex and half duplex synchronous communication up to 5 MBaud 20 MHz CPU clock The serial clock signal can be generated by the SSC itself master mode or be received from an external master slave mode Data width shift direction clock polarity and phase are programmable This allows communication with SPl compatible devices Transmission and reception of data is double buffered A 16 bit baud rate generator provides the SSC with a separate serial clock signal The high speed synchronous serial interface can be configured in a very flexible way so it can be used with other synchronous serial interfaces eg the ASCO in synchronous mode serve for master slave or multimaster interconnections or operate compatible with the popular SPI interface So it can be used to communicate with shift registers IO expansion peripherals eg EEPROMs etc or other controllers networking The SSC supports half duplex and full duplex communication Data is transmitted or received on pins MTSR P3 9 Master Transmit Slave Receive and MRST P3 8 Master Receive Slave Transmit The clock signal is output or input on pin SCLK P3 13 These pins are alternate functions of Port 3 pins Ports amp Direction Control Data Register
464. ut or Alternate Output Function Semiconductor Group 7 15 Version 1 0 11 97 SIEMENS Parallel Ports C164CI Pin P3 12 BHE WRH is one more pin with an alternate output function However its structure is slightly different see figure below because after reset the BHE or WRH function must be used depending on the system startup configuration In these cases there is no possibility to program any port latches before Thus the appropriate alternate function is selected automatically If BHE WRH is not used in the system this pin can be used for general purpose IO by disabling the alternate function BYTDIS 1 WRCFG 0 Write DP3 x MUX Direction Latch Read DP3 x I Alternate n Function t Enable e P3 12 BHE n ae P3 15 CLKOUT Output g Port Output Latch Output Buffer UJ eo c Read P3 x Clock Input Latch MCB02073 Figure 7 10 Block Diagram of Pins P3 15 CLKOUT and P3 12 BHE WRH Note Enabling the BHE or WRH function automatically enables the P3 12 output driver Setting bit DP3 12 1 is not required Enabling the CLKOUT function automatically enables the P3 15 output driver Setting bit DP3 15 1 is not required Semiconductor Group 7 16 Version 1 0 11 97 SIEMENS Parallel Ports C164CI 7 4 Port4 If this 6 bit port is used for general purpose IO the direction of each line can be configured via the corresponding
465. uted directly after activating the read protection ie without leaving programming mode The active read protection is indicated with data bit DO 0 Note OTP read protection is irreversible When the OTP read protection was activated once it remains active for each and every subsequent access Also subsequent programming cycles are no more possible OTP Read Protection Example The OTP read protection is activated in CHM executing the following procedure Note The example below assumes segment 0 RH0z00 MOV RO 0003H Enable module cmd idle MOV DPP3 OPCTRL RO initially enable the OTP module BSET VPP_ENABLE External progr voltage ON CALL MICROSEC 010 Let VPP settle for 10 gnusec MOV RO 000EH Move special register address MOV DPP3 OPAD RO to address register MOV RO 0001H Move special control word MOV DPP3 OPDAT RO to data register MOV RO 0009H MOV DPP3 OPCTRL RO Select special OTP register for write access CALL MICROSEC 100 Keep the write signal low for 100 ppusec MOV RO 000BH MOV DPP3 OPCTRL RO Trailing edge of write signal BCLR VPP ENABLE External progr voltage Off CALL MICROSEC 010 Let VPP settle for 10 gnusec Read protection verification could be executed here MOV RO 0007H MOV DPP3 OPCTRL RO OTP module deselected Semiconductor Group 3 17 Version 1 0 11 97 SIEMENS The Central Processing Unit CPU C164Cl 4 The Central Processing Unit
466. ve passive ACTIVE 1 0 1 passive ACTIVE passive passive passive ACTIVE 0 0 1 passive ACTIVE passive ACTIVE passive passive 0 1 1 passive passive ACTIVE ACTIVE passive passive 0 1 0 passive passive ACTIVE passive ACTIVE passive Rotate Left 1 0 0 0 passive passive passive passive passive passive Rotate Right 1 1 1 passive passive passive passive passive passive Slow Down X X X passive passive passive ACTIVE ACTIVE ACTIVE Idle 2 X X X passive passive passive passive passive passive 1 If one of these two input signal combinations is detected in rotate left or rotate right mode bit BCERR is set If enabled an emergency interrupt is generated When these error states are encountered the idle state is entered immediately 2 Idle state is entered when a wrong follower is detected if bit BCEM 1 or in case of an illegal input pattern see note 1 When idle state is entered the BCERR flag is always set Idle state can only be left when the BCERR flag is cleared by software Semiconductor Group 17 16 Version 1 0 11 97 SIEMENS The Capture Compare Unit CAPCOM6 C164Cl 17 8 Trap Function The trap function provides very efficient means to protect external circuitry which is connected to the CAPCOM6 s output lines The trap function is controlled by register TRCON and triggered by the input signal CTRAP The trigger functi
467. vents Each capture compare register may be programmed individually for capture or compare function and each register may be allocated to either timer Each capture compare register has one port pin associated with it which serves as an input pin for the capture function or as an output pin for the compare function except for CC27 CC24 which only provide the capture function The capture function causes the current timer contents to be latched into the respective capture compare register triggered by an event transition on its associated port pin The compare function may cause an output signal transition on that port pin whose associated capture compare register matches the current timer contents Specific interrupt requests are generated upon each capture compare event or upon timer overflow The figure below shows the basic structure of the CAPCOM2 unit Semiconductor Group 16 2 Version 1 0 11 97 SIEMENS The Capture Compare Unit CAPCOM2 C164Cl Reload Reg TxREL CPU Clock gt 2 n 3 10 Interrupt Tx Request TxIN Input CAPCOM Timer Tx Control GPT2 Timer T6 Over Underflow Mode Sixteen 16 EOD LLL 16 Bit 122I 16 Capture Inputs Capture Capture Capture Compare Compare Outputs or 7 Interrupt Requests Compare gt CPU Clock 1 Interrupt Ty Request Input CAPCOM Timer Ty gt GPT2 Timer T6 Control Over Underflow
468. vicing of some error conditions via interrupt while the others may be polled by software Note The error interrupt handler must clear the associated enabled errorflag s to prevent repeated interrupt requests A Receive Error Master or Slave mode is detected when a new data frame is completely received but the previous data was not read out of the receive buffer register SSCRB This condition sets the error flag SSCRE and when enabled via SSCREN the error interrupt request flag SSCEIR The old data in the receive buffer SSCRB will be overwritten with the new value and is unretrievably lost A Phase Error Master or Slave mode is detected when the incoming data at pin MRST master mode or MTSR slave mode sampled with the same frequency as the CPU clock changes between one sample before and two samples after the latching edge of the clock signal see Clock Control This condition sets the error flag SSCPE and when enabled via SSCPEN the error interrupt request flag SSCEIR A Baud Rate Error Slave mode is detected when the incoming clock signal deviates from the programmed baud rate by more than 100 ie it either is more than double or less than half the expected baud rate This condition sets the error flag SSCBE and when enabled via SSCBEN the error interrupt request flag SSCEIR Using this error detection capability requires that the slave s baud rate generator is programmed to the same baud rate as the master device Thi
469. w for the duration of the internal reset sequence upon any sort of reset Therefore a long hardware reset LHWR will be recognized in any case Semiconductor Group 13 4 Version 1 0 11 97 SIEMENS The Real Time Clock C164CI 14 The Real Time Clock The Real Time Clock RTC module of the C164CI basically is an independent timer chain which is clocked directly with the oscillator clock and serves for different purposes System clock to determine the current time and date Cyclic time based interrupt e 48 bit timer for long term measurements Control Registers Data Registers Counter Registers Interrupt Control SYSCON2 E TI4REL CE ORA eee eg c E Fa TT T14REL Timer T14 Reload Register RTCL Real Time Clock Register Low Word T14 Timer T14 Count Register ISNC Interrupt Subnode Control Register XP3IC RTC Interrupt Control Register Figure 14 1 SFRs Associated with the RTC Module The RTC module consists of a chain of 3 divider blocks a fixed 8 1 divider the reloadable 16 bit timer T14 and the 32 bit RTC timer accessible via registers RTCH and RTCL Both timers count up The clock signal for the RTC module is directly derived from the on chip oscillator frequency not from the CPU clock and fed through a separate clock driver It is therefore independent from the selected clock generation mode of the C164Cl and is controlled by the clock generation circuitry RTC Register Location within the ESFR space
470. ween the internal initialized baudrate for ASCO and the real baudrate of the host should be below 2 596 The deviation Fg in percent between host baudrate and C164Cl baudrate can be calculated via the formula below Boontr BHost F B PContr 100 Fp 2 5 96 Note Function Fg does not consider the tolerances of oscillators and other devices supporting the serial communication This baudrate deviation is a nonlinear function depending on the CPU clock and the baudrate of the host The maxima of the function Fg increase with the host baudrate due to the smaller baudrate prescaler factors and the implied higher quantization error see figure below 25 Q i PN nni V V NM Blow B High P P uos P4 Cy MCA02260 Figure 15 3 Baudrate deviation between host and C164CI The minimum baudrate B ow in the figure above is determined by the maximum count capacity of timer T3 when measuring the zero byte ie it depends on the CPU clock Using the maximum T3 count 26 in the formula the minimum baudrate for fgpy 20 MHz is 343 Baud The lowest standard baudrate in this case would be 600 Baud Baudrates below B ow would cause T3 to overflow In this case ASCO cannot be initialized properly The maximum baudrate Byigh in the figure above is the highest baudrate where the deviation still does not exceed the limit ie all baudrates between B pw and Byigh are below the deviation limit The maximum
471. wer limit of the internal system stack The Stack Overflow Trap entered when SP STKOV may be used in two different ways Fatal error indication treats the stack overflow as a system error through the associated trap service routine Under these circumstances data in the bottom of the stack may have been overwritten by the status information stacked upon servicing the stack overflow trap Automatic system stack flushing allows to use the system stack as a Stack Cache for a bigger external user stack In this case register STKOV should be initialized to a value which represents the desired lowest Top of Stack address plus 12 according to the selected maximum stack size This considers the worst case that will occur when a stack overflow condition is detected just during entry into an interrupt service routine Then six additional stack word locations are required to push IP PSW and CSP for both the interrupt service routine and the hardware trap service routine More details about the stack overflow trap service routine and virtual stack management are given in chapter System Programming Semiconductor Group 4 25 Version 1 0 11 97 SIEMENS The Central Processing Unit CPU C164Cl The Stack Underflow Pointer STKUN This non bit addressable register is compared against the SP register after each operation which pops data from the system stack eg POP and RET instructions and after each addition to the SP regi
472. whole groups of peripherals including the power required for generating and distributing their clock input signal Other peripherals may remain active eg in order to maintain communication channels The registers of separately disabled peripherals not within a disabled group can still be accessed Periodic wakeup from Idle mode Periodic wakeup from Idle mode combines the drastically reduced power consumption in Idle mode in conjunction with the additional power management features with a high level of system availability External signals and events can be scanned at a lower rate by periodically activating the CPU and selected peripherals which then return to powersave mode after a short time This greatly reduces the system s average power consumption Semiconductor Group 2 15 Version 1 0 11 97 Architectural Overview C164CI SIEMENS 2 5 Protected Bits The C164Cl provides a special mechanism to protect bits which can be modified by the on chip hardware from being changed unintentionally by software accesses to related bits see also chapter The Central Processing Unit The following bits are protected Register Bit Name Notes T2IC T3IC T4IC T2IR T3IR T4IR GPT1 timer interrupt request flags T3CON TSOTL GPT1 timer output toggle latch T7IC T8IC T7IR T8IR CAPCOM2 timer interrupt request flags SOTIC SOTBIC SOTIR SOTBIR ASCO transmit buffer interrupt requ
473. wn Mode If the C164Cl enters Power Down mode the XCLK signal will be turned off which will stop the operation of the CAN Module Any message transfer is interrupted In order to ensure that the CAN controller is not stopped while sending a dominant level 0 on the CAN bus the CPU should set bit INIT in the Control Register prior to entering Power Down mode The CPU can check if a transmission is in progress by reading bits TXRQ and NEWDAT in the message objects and bit TXOK in the Control Register After returning from Power Down mode via hardware reset the CAN Module has to be reconfigured Semiconductor Group 19 19 Version 1 0 11 97 SIEMENS The On Chip CAN Interface C164CI The CAN Application Interface The on chip CAN Module of the C164Cl does not incorporate the physical layer that connects to the CAN bus This must be provided externally The module s CAN controller is connected to this physical layer ie the CAN bus via two signals CAN Signal Port Pin Function CAN RXD Port 4 5 Receive data from the physical layer of the CAN bus CAN TXD Port 4 6 Transmit data to the physical layer of the CAN bus A logic low level 0 is interpreted as the dominant CAN bus level a logic high level 1 is interpreted as the recessive CAN bus level Note These CAN signals are only available on the Port 4 pins if Port 4 is not programmed to output all segment address lines Select 0 2 or 4 segment address
474. written into a two message alternating buffer to avoid the loss of a message if a second message has been received before the CPU has read the first one Semiconductor Group 19 17 Version 1 0 11 97 SIEMENS The On Chip CAN Interface C164CI Initialization and Reset The on chip CAN Module is connected to the XBUS Reset signal XRESET This signal is activated when the C164Cl s reset input is activated when a software reset is executed and in case of a watchdog reset Activating the CAN Module s reset line triggers a hardware reset This hardware reset sets the CAN TxD output to 1 recessive clears the error counters resets the busoff state e switches the Control Register s low byte to 01 leaves the Control Register s high byte and the Interrupt Register undefined does not change the other registers including the message objects notified as UUUU Note The first hardware reset after power on leaves the unchanged registers in an undefined state of course The value 014 in the Control Register s low byte prepares for software initialization Software Initialization The Software Initialization is enabled by setting bit INIT in the Control Register This can be done by the CPU via software or automatically by the CAN controller on a hardware reset or if the EML switches to busoff state While INIT is set all message transfer from and to the CAN bus is stopped e the CAN bus output CAN TxD is 1
475. y of this architecture allows to serve the diverse and varying needs of different application areas such as automotive industrial control or data communications The core of the 16 bit family has been developped with a modular family concept in mind All family members execute an efficient control optimized instruction set additional instructions for members of the second generation This allows an easy and quick implementation of new family members with different internal memory sizes and technologies different sets of on chip peripherals and or different numbers of IO pins The XBUS concept opens a straight forward path for the integration of application specific peripheral modules in addition to the standard on chip peripherals in order to build application specific derivatives As programs for embedded control applications become larger high level languages are favoured by programmers because high level language programs are easier to write to debug and to maintain The 80C166 type microcontrollers were the first generation of the 16 bit controller family These devices have established the C166 architecture The C165 type and C167 type devices are members of the second generation of this family This second generation is even more powerful due to additional instructions for HLL support an increased address space increased internal RAM and highly efficient management of various resources on the external bus Enhanced derivatives of
476. ze and the increment step for the modified pointer Semiconductor Group Version 1 0 11 97 Interrupt and Trap Functions C164Cl SIEMENS Increment Control Field INC controls if one of the PEC pointers is incremented after the PEC transfer It is not possible to increment both pointers however If the pointers are not modified INC 00 the respective channel will always move data from the same source to the same destination Note The reserved combination 11 is changed to 10 by hardware However it is not recommended to use this combination The PEC Transfer Count Field COUNT controls the action of a respective PEC channel where the content of bit field COUNT at the time the request is activated selects the action COUNT may allow a specified number of PEC transfers unlimited transfers or no PEC service at all The table below summarizes how the COUNT field itself the interrupt requests flag IR and the PEC channel action depends on the previous content of COUNT Previous Modified IR after Action of PEC Channel COUNT COUNT PEC service and Comments FF FF 0 Move a Byte Word Continuous transfer mode ie COUNT is not modified FEy 02y FDy 01y 0 Move a Byte Word and decrement COUNT 01g 004 T Move a Byte Word Leave request flag set which triggers another request 004 001 1 No action Activate interrupt service routine rather than PEC channel Th

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