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Acer AcerNote 970 - Sevice Guide. www.s

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1. PUE CNOA 5 MZA PI L 0 pio P2 ae Pal D3 A CD1 Pag P5 3 P44 P45 P7 R68 P47 52 10K 8 Pl A Y 0 P2 3 CHE MUEVE PM5 A bee 54 PMS A 5 p RESET P54 E 3 CPUS AWATE PREIS P56 PB 3 P PORTS 3 3 ure 8 LAS PS 3 LY 9 REGE P 22 CERDO 13 Pet P23 P2 SEL 16 P5 PRE AONE P64 P mo MI P7 28 29 P7 P33 WP O P72 P34 PMS A 0 Pa RDY gt 3 TER POVSW P75 15 25 e POVCIA TE2PCON 3 3
2. HDDVCC CDFDDVCO HD5 005 1 s 10 j Nit 2 ute HD HDDM 2 9 HD5 m wc 1 8 HDS HDD 3 8 P HDSHDDI2 4 7 HD5 HDD3 15 CRS 2 CF5 FDDICD 2 6 3 2 HD5 HDDI5 5 6 5 HDD8 2 HDWC TOEN 4 HDS DIE B HHDH SARES10 peg 3 18 FDS DR O 6 HD5 DT m 82 HDDVCC 0850 5 mso 8 B 10 HD5 582 i HD5 D2 HM HD5HDD2 CF MTROHCDAD 51 x HOS HDD 1 10 CF5 DENSELCDN a m o 18 HDs HDDS 2 9 2 lt FDS 10 HS DTI 20 B HODIT HDSHDDS 3 8 HD5 HDD2 pta DIRE HS Di 23 9 m HD5 HDD4 4 7 HD5 HDD FD5 STEPH 12 HDS 010 256 HD5 HDDIO 5 6 HD5 CDIORF 0 B10 HDWC o 21 HDS CDIORF 14 5 05 29 HD5 HDDS WOATEF B11 18 FDS WGATEF 15 N 812 x SARES10 10K 5
3. 44350 WB b K 8 3 3 7 oltre 3 R301 r 5 806K 1 a amp 4 4 2 BMCVCC R306 1 2 22 3 27 20K 1 05 fa 5255904 2 2 1 00 use 6272 4350 100K pi 2 3 S14435DY 014112 K 8 DXX a BNX002 i 5 Mii DON 162227 4 n lt FUSE T 1 E 022 00fuF TES 1 gt 3 017 m f c 101 C280 R336 MBRS340 1 161512 af 2510 2 10000F 2 on 060 100 1 1 e R302 2 i WGGND 7 i R271 RS 3 100K 100K R270 10K 4 3 ps 6 i 1 3 1 5 oz R328 1 1 247002 8327 MMBZS245BLTI 016 932 8 2 bi 1K 1 806K 1 10K our R338 CRB gt 27 2 1 2 3 3 2 8 4 4 528904 les PGND T 835 2 2 1 021 1 020 8303 cs i 4 2 2N7002 1 2 2N7002 3 R30 4 10K ie C242 ER 01 f 14 R331 0281 16 lt ACN K m 2 2 499 196 oe 3248904 i 4 4 4 1 1 1 1 1 R300 20K 1 3 R37 024 bi BMCVCC 2
4. PavsW _ 0 OF tour T our 1 1 155 16V 1918 2 21818 65 507 17 39 2 155 506 1 07 ORME EKER AUDGND AUDGND 100pF 100pF 100 1 15 0080608 Y IS5 SD 13 UDGND AUDGND AUDGND 195 SD T 37 155 501 1 02 155 500 00 100pF Cit 18 2 022uF 0805 1 m 23 ADS MSCLK 8 0805 COAUDR 23 23 ADS MSDATA MSD 022uF 0805 53 __100 _ Odpuf 0805 482022 155 50 23 23 5 JOYRDB AUXAL pl 4 ADKCDAUD 23 SA 1 5 35 0 0805 015 885 AEN AUXAR 2 lt CORUDR 7 soan an 02205 0805 C65 ATO m LINER 5 0286 0805 e 30 i L3 Lour DD taa oni DOA UN 23 155 515 1 022 F 805 n T5 SM 100 om 58 2 i7 DOA FIN 2 55 SK CI Cs TE 65 066 E 155 580 qur 058 100pF 100pF 100pF 100pF TAVESS 8i 16 MESS EXTCLK REFSEL 6165 RS
5. PIAR PSVSW 028 1 25 8 12 APP VPP gt 4 s 5 34 Bw V n 4 PWS SER DNA 6 288 clock A 3414 3 PM5 SER LATCH LATCH BVOC 6 POLPORSTF RESET E RESET 43 4 APWR 6000 18 5000 Oe EE Pm TA F tev aur E iu oi gd TPSF gt n U22 8 I Lini 894041 8 3N TPOSIOLT 1 03 R51 F 16V 2 1 2 OF tl R52 1 300K 1 2 R53 PSVSW Rag 1 100K 300K 4 2 2 1 02 6 K5 MODPONE LT H 2N7002 P3VSW 2 5 984100 8 7 3 PNLVCC gt 13 5 9115 a 9 TPOSIOLT 1 C131 R72 9 x 10uF 16V 2 pas 1 2 OF S ITI ul L R76 5 300K PAR 2 mg 3 300K PSVR 3 2 m 16 1 05 PNVSW 12 9 2 PSVSW L ms ACER ADVANCED LABS Title PROJECT MARS MULTI MEDIA Size Document Number PCMCIA SOCKET PWR 8 INT CONTROL Date May 9 1996 TSheet
6. P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P c 3 3313131313 3 31313131 33 3 3 3 3 3 3 3 3 3 8 3 33 3 3131313 PavsW 2122 XR RR 2128 FG BER A A AJA AJA Al A AA D D D D ol D D D D ol Dl ol D of olol D ol ol D 01 o ol Dlo D p DD o o o D 9 2 0123456 7 8 o t 1 1 4 t 1111112 22212122221233 PSS 26 1 5 2 1 DPI 7 E ied 53888 10 AAAAAAAAAAARAAAAARAAAAAAAAAAAAR DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD PPPP IDE 5 DACK pea o DACKI2 DACKES 55 DACK S El CIBER packe P DA H POCLK Zn R5 49 SYSCLK SGNT n RI7 100K 100K m Om p ES 1315202231 6 PC3 PCRSTE H_POIRST ON 2101 41315202231 181 MEM R20 92 212223 151 DEL EE 155 20 2223 PCIINTEF 17 PCINTBE
7. 1 20 12 BR0 BRO 2 19 RO 12 GR3 BRI W 18 RI 12 03B GR3_BR2 4 7 GR3 R2 12 5 W 16 GRO R3 12 GR3 GR3 Lol 15 12 GROBRS 1 Lo 14 GR3 R5 12 683 885 8 Lol 18 GR3 R6 12 CRIER GR3 9 12 GR3 R7 H RCNT 15 RN3 1 20 12 683 GR3 BGO 2 ly 19 12 683 GR3 BGI GR3 G1 12 287802 62 12 ORT GR3 683 63 12 GF GR3 BG4 6 0M 15 GR3 G4 12 GR3 805 1 14 GR3_G5 12 683 683 06 8 M 13 083 G6 12 BG GR3 BG7 9 12 GR3 G7 10 11 RCNT_15 RN4 1 20 12 GR3 BB0 Hp 19 12 BBT 3 Ho 18 1 12 GR3 GR3 BE 4 I 17 GR3 B2 12 CRT 883 GR3 BBS 5 W 16 GR3 B3 12 GRE BB W 15 GR3 B4 12 GR3 865 GR3 BBS 7 14 GR3 B5 12 GR3 BB s GR3 86 12 CRY BB7 GR3 7 9 12 GR3 B7 RCNT_15 P5VR R PSVSW Ps
8. 6 7 8 9 91 46801 001 65 46806 01 LCD MODULE ASSEMBLY HITACHI 11 3 No Part No Description Q TY Remark 5 01 41 46805 002 LCD BEZEL FOR HIT 11 3 S J 02 34 47604 00 HOOK SPRING EJ SPG 05 42 46829 00 LED LENS FOR POWER S J 04 42 46828 00 LCD LATCH 5 0 05 40 46805 001 ACER LOGO S Y 06 47 46802 00 CUSHION BEZEL 2 P M 07 47 46803 00 CUSHION MICROPHONE P M 08 50 46806 00 FPC LCD HIT 11 3 ADFLEX 09 41 46804 002 LCD PANEL FOR HIT 11 3 Sal 10 44 46831 002 EMI SHIELD FOR HIT 11 3 11 86 4A453 6RO SCREW M2 5 L6 NYLON 0 CASHI 12 86 1A522 6RO SCREW PAN MECH 2 0 16 2 CASHI 3 31 46813 001 NAME PLATE FOR ACER OUDENSHA 4 56 07355 011 LCD SANYO SVGA SIN 11 3 HITACHI 5 19 20086 001 INVERTER FOR SANYO 11 3 AMBIT 6 25 42009 001 MICROPHONE HOSIDEN 7 4 46829 001 HINGE L FOR 970 CEMA 8 34 46830 001 HINGE R FOR 970 CEMA 9 86 4A453 6RO SCREW M2 5 L6 NYLON 2 CASHI 20 47 46810 002 CUSHION SPACER A CR 2 S Y 21 40 46814 001 LCD FPC MYLAR 1 S Y 22 25 24 25 65 46806 011 LCD 11 5 MODULE ASS Y MODEL NAME _ _ 5 10 970 LCD MODULE ASSEMBLY 1 add component 1996 Notice Director HITACHI LMG9900ZWCC DRN MATERIAL REV DESCRIPTIO SIGN DATE DSN HSIAO FINISH 5 050 QTY 1 I PM mm SCALE CKD PE L S
9. PSVSW UB 6 1155 3 ff os 1 6055 58 2 05 PavsW PSVSW 1 wc 1 2 TACTO 5 6 4 2 6 Em 5 LB PSVSW 1 _ usc T 4 TAACTOS 655 REN 9 7 o 9 5 E 6 VS5 c PSVSW C46 SC A _ 4 1 4 1 7 R79 t To 3 100K 8 2 5 Mos gt 8 cn ig i B Uto PWR ONSW Common 6185 SN 30 6185 SAT 6185 SN E H Ht HOLE HOLE2 HOLE HOLE HOLE HOLE H H H H H H 1 1 1 1 1 1 mor 56 5 HOLE HOLE HOLE HOLE 6 H H H H 0 x Hx 1 1 1 1 xi L L L 4 LRON vun H f DN 18 B AT BCKIN DCL 4 8 L cis PADS PAD603 18 5 DCR OF 16V 1 1 2 17 MUTE 9 1 5 RES M lt 12 PADE PADS zu ty aie OF 10K P M lt 5 voc 5 OF 2 19 TAACT32 42 ji 16V PVR PVR PNR PNR 1 1 AUDGND 12 9 oos 8 OF 18 10 0208 200 200 TAAC32 TAAC32 74AC32 PNR CONFIDENTIAL 6 PavsW 6 ACER ADVANCED LABS PROJECT MARS MULTIMEDIA Sze Document Number LOGICS 8 SPARE GA
10. P P P P P P P P P P P P P P P P P P P P P P P P p P P P P P P P 3 3 3 31313131 3313131313331 333 ADD31 8212223 DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD un 32222222222111111111 9876543210 MMMM 1088765452109876543210 PPP ADT PED SL 22 2 127 AD3 033 34 D33 Harn PEDE 04 Cu PON 5 TS ADS 036 31 095 AB Et ped 122 ADT D37 38 Dy 7 120 PT3 038 49 097 a 09 n 0 PCS ADIT V2 GS Apri D42 04 An 115 ADIZ O PED 08 044 AD4 D ADS ADIG PT3 D46 49 016 PT3 D47 50 046 Ps 106 ADI7 mI I y HE Oe PED 08 7 x 019 x PT3 D50 53 09 19 1 ADAD PD 5 HE 051 050 un iso 104 AD21 ere pet pst 109 2 08 8 09 us DA Fs ADS BEDS ADS PT3 056 09 A AD26 Hes 027 PD 8 057 E AD28 PD 6 05 33 PGADS 63 Pi PD 8 059 0 0 00
11. ode 1 403 GRO GR 12 4 6 R85 7 em GREP 12 6 9 x 112 o 2 GR3 R2 GREAT a i d 1 GRO R4 GR3 6 2 RS En 4 din GR3 G2 t 2s GREG s 2 9 1 GR3 G4 GR3 G6 1 5 GREG GREG 36 5 4 as i 37 GR3 B2 MU GRIET A 41241 1 GR3 B4 GR3 86 1 id B5 x SICAT 1 DIMG 5 49 CRIDING gt 5 b 4 i 54 53 lt lt a 0130 os 53 p4 STER DCN do amp 61 L d amp b 4 E 6 6 SMA BATADI 6 6 68 67 SWA CNTAD 6 6 KB5 6 SWSPWREDE 16 2n BATTLEDE 6 6 BNCVOC nm SHE ON FES SH lt AAO ME 2 6 4 8 79 ADVDD R55 100K LCD CON M AUDGND oO 8 OUTPUT END 12 1 SENSE 6 50 FR ARROW 5 ap 4 01 crack ACER ADVANCED LABS Tile PROJECT MARS MULTIMEDIA Sze Document Number LOD INTERFACE LOGICS Date May 9 1996 TSheet 18 PSVSW
12. ONTA 6 6 PCT ULKRUNF 6 6 1 POMCLK FRAME 6 BS DER H 6 lt ROSER PCIRST PADS 2 PADS TROYF 6 io NE 1 2 PAD603 EG 8 612 oy PCT C 612 m PCC BER 612 PSW C BER 612 I PERRE 612 25 CU C105 3 612 173 OF DSE 1 7 ADHD x R5 10 22 22 2 2 Jr B REEL uem aga bhe i PENS 08 A0 191 PE 16 444 116 PM5AA0 189 0 LES BB 73 5 AAT PMG B A2 uu y TNR EN 8E 0123 he AZ 15 842 Pid d NS Pi5 AA E M 13 883 MS Lu B 75 18i BM 870 05 PM5AA5 PNS LET 0 M5 A AS 8 0 BAT AAT lt 6 157 8 1 82 PNB AAS 9 15 88 MS Dm BEANS ATO M9 EAD ani B 1y lt P B Y E97 PW AA B 2 AM 84 182 BAIS 86 Bs EJ E 9 BAG PME B 161 rei BER w 88 ER 166 BAS ru 90 AMI 2 2 AMA 4 0015 8 DO B Dt
13. i 61 M 61 DAA RING 2 1 6 1 6 x VOND i 23 24 1 12 rg 3 e L8 4 3 13 8 4008 CRKCRN 2324 x 4006 5 55 155 501 5 65 5 6 5 8 K 8 8 23 24 185 50 5 16 66 I 4 55 522 7 17 15 lt KB PANDI 21 GRA 23 24 oe Sg 15 KB5 PANDO 3 19 8 RA V YN 2324 5535 8 KB5 KSOS 16 PWRLEDF 155 50 KB5 KSOS 16 BATTLEDE onm ADVDD onm KK 15 KBS CAPLEDE li p SMABRTA 16 SS 2 pe 4 15 NUMLEDE mH SMA CNTADJ 16 ae n Hi KEKO 27 BMC M n Hi 5 5 ON RES SW 16 ET n d x JUR MONT 30 e 5 15 s RES KSOTU 24 GRA CCD2BD Be m AUDGND 55 5 3 Bw KSOIT 24 GRA Luv POS PORSTE 6 ae KSOT2 8 I Hi K85 013 6 CG PNK m d 3 EG KB5 o 4 6 CKK ada Hd 1512 9 81 55 2 2 8 rg PCT DYE 682123 DEVSELF A 4 d FRAMER 6782123 Ep HE 8 PCTNIDE Blo 8 PCS INTO 8 5 1 5 1 dE 8 87 4 185 ORF 2 8 STOP PCT 6823 8 155
14. 2 44 R6723 12 Pin 2 46 R6684 17 Pin Descriptions 2 50 R6693 14 Pin 2 54 ESS1688W Pin 2 58 876552 Pin Descriptions ee eee pee te e ee eei ees 2 66 NS87336VLJ Pin 2 72 CL PD6730 Pin 044 4 a a nnne 2 83 10643 Signal 2 93 T62 036 C Pin 77 2 97 T62 039 C T62 055 C Pin 2 99 About My Computer Item 3 4 Diskette Drive Control 0 3 17 Hard Disk Drive Control 3 18 Start Up Sequences 3 18 Error Beep Sequences During the Boot ROM Process 3 19 Guide to Disassembly Sequence 4 4 Chapter 1 Introduction This chapter introduces the notebook computer and describes its features and specifications 1 1 Overview This Pentium based notebook computer combines high performance versatility multimedia capabilities and a truly advanced power management system 1 1 1 Features PERFORMANCE Mobile Pentium microprocessor P54CSLM 120 133 150
15. 5 x 579 lt s lt Pasw i R239 9 jy vec vec 20K voc N vec 2 cm 0 w 52 w AS 32K 32 d 32K 32 m voca voca PTS 99 3 p veca veca PTs AIS A veca MO veca pu 347 52 DO 52 PT3 D32 FEAT 4 D ot 02 x D2 8 Ds ADSCH 85 6 CHG 8 0500 9 7 PTs Ds 6 CHS ADVE 8 8 ADVE 05 06 x 06 x e me 5 P 6910 5 Sd we a 6910 07 6310 5 a 25 BW2 08 6910 BW2 08 9 WERT BW3 09 9 BW3 09 6910 SOR ONE 36 o po L8 6910 BWA po 8 6 8 cee CHa 38 2 0 GEN 52 GEM HA PT3 A18 gs a D PGD PT3 A18 g 9 5 08 n 86 78 CHE 86 78 6 CH3 COEF ns 89 89 Di 6 CHSTZCIKI 017 6 ORE LACK 017 s CH3 EN PT3 DIE CH3 FT SM De 7 nSz par 020 35 22 m s PT3 D52 B bI NC D23 NC NC D24 NC oy Ls ae R240 05 PTS 025 ROM ie 05 UT PH 5 100K 1 100K PT Da NE 07 07 23 NC 98 D28 NC 98 24 NC 029 NC 029 09
16. 2 81 10643 PCI E IDE Controller eese 2 91 2 9 1 Features it e eee oe cep e Ed 2 91 2 9 2 PY s 2 92 2 9 3 Signal Description sinari ne ne nee e edes 2 93 Ambit T62 036 C DC DC 2 97 2 10 1 2 97 2 10 2 Pin Description Si eee feet ie ec q e 2 97 Ambit T62 039 C T62 055 C DC AC 2 99 2 eu totes etate bt edu 2 99 2 11 2 Pin Descriptions 2 99 Chapter 3 BIOS Setup Information 3 1 3 2 3 3 3 4 When to Use eee tete eee es 3 1 Entering Setup 3 2 About My 3 3 System Configuration 3 5 3 4 1 Date and 3 5 3 4 2 Diskette eio en n e e rie ts 3 5 3 4 3 3 6 3 4 4 Num Lock After TR e 3 6 3 4 5 LCD Expansion teeth 3 6 3 4 6 Internal Cache 3 8 3 4 7 External Cache 3 8 3 4 8 Enhanced IDE Features 3 8 3 4 9 Onboard Communication 3 9 3410 Onbo rd erede etaed 3 11 3
17. 1 13 Media Board 5 1 14 Media Board Bottom 1 15 1 16 CPU board Bottom 1 16 Mainboard Jumpers and Connectors Top 1 17 Mainboard Jumpers and Connectors Bottom Side 1 18 Media Board Jumpers and Connectors Side 1 19 Media Board Jumpers and Connectors Bottom Side 1 20 System Functional Block Diagram 1 46 System Bus Block 1 47 Architecture Block 2 7 PT86C521 V1 LS Block 2 8 PT86C521 V1 LS Pin 2 9 PT86C522 V2 LS Block Diagram a 2 18 PT86C522 V2 LS Pin LS Su iiie 2 19 PT86C521 V3 LS Block 2 22 PT86C521 V3 LS Pin 2 23 NMG2090 Pin 2 31 RCV288Aci SVD Architecture Block Diagram 2 44 R6723 T Pini Dia Gram vines eee t
18. AD25 3 5 5 E AD24 7 17 AD23 90 AD22 55 8 ADAD 4 107 ADIS ADI7 10 rw ADIS a 015 7 18 102 04 ADI 4 172 PCS ADI ADIT 4 14 15 AD 46 18 AD8 AD a 107 4 406 ADS 4 18 ADI RD rm 0 RDT 5 0 10 rmm RD 9 12 3 REQRT 1 845 m HE 312 H m FEUDUM 312 3 5 15 5 12 56 116 56 116 VORCT 12 3 PMZ ROSER E 57 7 155 VDP 12 PAR o B s ne o S da HR WC 7 13 14 120 DON 8 POLCON ADJ0 311 155 500 7 155 155 10 8 8 14 10 814 5 14 4 3 14 14 3512 1 11 RING 10 2 3 63 155 500 111 5 155 501 5 65 IS5 SD 6 8 155 503 7 18 155 504 155 505 8 Pg 1 155 505 m s i 155 507 039 1 155 EM 5
19. PSVSW RNIT 155 540 1 4 155 SAT 2 9 155 SM 165 52 3 8 165 545 165 543 4 7 165 546 6 555 SARES10_100K RNIB 155 548 1 Do 165 549 2 3 165 SA12 165 SA10 3 8 165 SA13 165 4 7 165 PS 6 165 SAIS SARES10_100K 165 5416 1 10 165 SA17 2 9 155 5420 165 SAIS 3 8 165 165 4 155 6 165 5403 SARES10 100K 155 5000 15 6 PT3 HOLDBOFF 5 5 HLDA 6 PTS 220 VS3 BSERCLK S 155 RSTDRV 155 155 BB VERSION CC VERSION 65 500 1 155 501 7 3 65 504 155 502 3 5 155 505 155 503 1 T 155 505 SW oe 5 55 50 SARES10 10K 65 508 10 155 509 2 9 155 5012 155 5017 3 5 155 SDT 155 5011 1 155 5071 OL 5 155 805 SARES10 10K 828 1 20 PIS HOLD 5 Pape 1 Pere gt 5 Paor ss THDEDES 1 2 0 1 4 1 RI02 2 PIS ROOF 5 0 THA TAALS32 1 2 00 PAD603 08 VS3 BSERCLKV3 1 vec 0 155 7 PT3 3 i 19 155 B cp 455 ROVKECSEF d 17 OF 53 5 6 6 103 1 7 i 3 101 D 2 6 Pads 100 DECRE 1520 100K a 3 i GND PALCE16V8Z 15JJ
20. HDD _ 900 n y FRAMES OPSVR 6 PCS TRDYF iio DY 1 00 i noo ALIRIA I4 n 36 FOS UKRINE 1 9 mM WO C 2 5 4 18 CG RESET DOD HE SR 19 m PSVR 0900 N 6 35 n C96 SUSPEND ovss 19 XCKEN 0 55 H8 34 gt T ZT p DVSS A 10V R 6 683 MONT 4 19 STANDBYISTATUSI d L lt 6 6 CR 328 82 RIG32KSTATUS2 E MESI WES 6 59 PIQIAISTATUSS ore PMCLKISTATUS4 56 HDD FB4 dk PAR S o MIESIN CE PR 6 13 PD BUSSEL 57 HVDD XTALI i FBT 2 C88 092 AVSSXI GND 615 095 E x doc e AS CS AS ae LUE 10uF 16V a AVSSRI GRAGND 4 AVSSR2 VSP pe 10uF 16V 16 TF 10uF 10V VSP E FB5 Men nr pe 7 CONFIDENTIAL GRAGND _ GRAGND GRAGND AD 55 95 FB t 15 AVDDRI VSSP 4 AVDDR2 VSP 091 T 10uF 16V OF GRAGND 42 4 ACER ADVANCED LABS y PROJECT MARS MULTMEDIA Sze Document Number LCD CONTROLLER Date 15 1996 Sheet 12 of
21. 9 PSVR 1 4 1 4 RE gt G 83 04 58 450 058 TAACTOB TAACTOB 74801455 ACER ADVANCED LABS Title PROJECT MARS Size Document Number KEYBOARD CONTROLLER PSR 515 18 SM5 HDRST 7 lt SWB BAYSW 17 gt MODPONE 2223 515 2 SM5 CDRST 7 19 GPO ja 23 UNDOCK GNTR DKGNTE 623 ET 28 VSS 6 CONT 7 Pm 2 27 26 R315 100K 9 2 7 5 5 NBPWRGD 10 27 1 4 t 10 ANM 3 gt USPENDE 5 rod SM5 NBPWRGD a 66 seu Senn 4 28 MAIN T P5 1 ADC1 7 2328 CHARGSP 7 PIRON h 9 5 E SUI 5 PO7AD7 590 2 2545 TAHCTOASS 2 92 205405 POAIADA 1 4 4 S PO2
22. ot s 9 2 20224258 TEIG PUISBSDSESEBSRRSRRRIRNRSRPICPPIPUTTSSDSR MD23 4 gt 157 AD21 VCCDRAM 4 MD24 gt gt 4023 MD25 VCCPCI MD26 AD24 MD27 lt AD25 MD28 AD26 MD29 lt AD27 MD31 vssio MD32 4 5 AD28 MD33 gt AD29 MD34 AD30 MD35 gt 031 MD36 lt PCIRST MD37 pPCIMSTR MD38 807 MD39 _ 806 vssio x 805 MD40 804 V2 LS MD41 802 MD42 vssio PT86C522 044 gt 800 i oy E 208 Pin VQFP B MD46 BDCTLO CORE CORE MD47 V2CLK MD48 vssc MD49 NCBUF MD50 DECBUF MD51 lt 52 ADPAR 000 MD53 MD54 68 gt EVEN 67 063 MD55 66 062 VCCDRAM 65 061 MD56 64 060 MD57 63 _ 059 MD58 62 058 MD59 61 057 056 MD61 59 gt 055 58 054 MD63 57 053 56 052 01 Q 55 vssio 02 54 051 lt
23. 1 7 Environmental Requirements Table 1 39 Environmental Requirements Specification 45 435 20 60 Operating Non operating C Operating non condensing 20 80 Non operating non condensing 20 90 5 25 6Hz 0 38mm 25 6 250Hz 0 5G gt 1 minute octave Operating Sweep rate Number of test cycles 2 axis X Y Z 5 27 1Hz 0 6G 27 1 50Hz 0 41mm gt 2 minutes octave 4 axis X Y Z Non operating Sweep rate Number of text cycles Operating 5G peak 11 1ms half sine Non operating unpacked 406 11 1ms half sine Non operating packed 50G 11 1ms half sine 10 000 feet 40 000 feet Operating Non operating Air discharge 10kV no error 12 5kV no restart error 15kV no damage Contact discharge 6kV no error no restart error 8kV no damage 1 8 Mechanical Specifications Table 1 40 Mechanical Specifications Specification Weight includes battery with FDD module with CD ROM module Dimensions round contour 3 4 kg 7 4 lbs 3 5 kg 7 7 lbs 297 313 x 230 240mm x 48 53mm main footprint 11 7 x 9 1 x 2 Chapter 2 Major Component Introduction This chapter discusses the major components 2 1 Major Component List Table 2 1 Major Chips List Vesuvius LS Chipset Pico Power PT86C521 V1 LS System Controller PT86C522 V2 LS Data Path Controller PT86C523 V3 LS PCI
24. DENSEUADRATE1 BUSYANAITAMTR I 84 INDEX as MIT PO7MSEN1 66 DRi PD PDS DRATEO 67 DRO POSMSENO es MTRiADLE PO4 DSKCHG VSSB DA IE PC87336VLJ zii 91 92 WDA POVTRKO WGATE com pe 95 96 ROATA IRQS 97 HOSEL IRQS ADRATEO 95 vooc 99 109 A10 1 23 4 6 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Figure 2 14 NS87336VLJ Pin Diagram 2 7 4 Pin Description Table 2 10 NS87336VLJ Pin Descriptions Pin no 10 Deep Address These address lines from the microprocessor determine which internal register is accessed 15 are don t cares during DMA transfer Parallel Port Acknowledge This input is pulsed low by the printer to indicate that it has received the data from the parallel port This pin has a nominal 25 KO pull up resistor attached to it ADRATEO FDD Additional Data Rate 0 1 These outputs are similar to ADRATE1 DRATEO 1 They are provided in addition to DRATEO 1 They reflect the currently selected FDC data rate bits 0 and 1 in the Configuration Control Register CCR or the Data Rate Select Register DSR whichever was written to last ADRATEO is configured when bit 0 of ASC is 1 ADRATE1 is configured when bit 4 of ASC is 1 See IRQ5 and DENSEL for further information Parallel Port Automatic Feed XT
25. 1 13 1 3 3 Media Board Top 1 14 1 3 4 Media Board Bottom 1 15 1 3 5 CPU Board Top 1 16 1 3 6 CPU Board Bottom Side 1 16 Juimpers and Connectors Joe tet et e et ete ts 1 17 System Configurations and 1 21 1 5 1 Memory Address Map 1 21 1 5 2 Interrupt Channel 1 21 1 5 3 VO Address Map pe eR RETE 1 22 1 5 4 DMA Channel ees 1 23 1 5 5 GPIO Port Definition 1 23 1 5 6 PCI Devices 1 27 1 5 7 Power 1 28 1 5 8 1 35 1 5 9 BIOS US UN 1 35 1 5 10 System 1 36 Cache Memor 1 37 15 12 1 37 1 5 13 Video Display Modes 1 37 155 14 lt AUIGIO onte een een gene n gen eet paginas Ve ci DHT c vue qa ci geo 1 38 1 5 15 Modem ete eee ec 1 39 1 7 1 8 1 5 16 bee teu bn no indie Edit 1 39 1517 Parallel Pontu u ined ee en e ere Gene 1 40 15 esne 1 40 1 5 19 gt tH
26. 82123 PERRE 2 SERRE 8155 AEN 2 9 0 w C BEF 68212223 0 4 a L POC BEN 68212223 551007 is AD31 E AD30 2 FW POSADA 315 8 PC3 AD28 831 IS ROT 8 8 1 0 gt 1 95 5 05 831 155 5 ls DSTR US AES 3 4 et d Bes d 820 155 IOCHRUY 7107 519 8 AD20 Bede 188 8 B ADIS 4 190 HO RS DE 8155 DACKAT 014 100 HO a ADIS atr 52 100 E 22 102 22 102 x PCS 22 im 4 PCS 8155 DARES R oje w 12 KBS PED m E CTS ERG LM KS BT PCS ADIT 514 ADIO pax m ADS 8 15 ADS 5 18 SE T 10 T 10 07 AD6 4 2 rm ADS 4 8 15 ADE 14 lt PIS ROUTE 49 1 18 zm 223 dro EN uu x 5 n x A 5 n 5 TI 5 TI 1 53 0 10 Ge E 52 12 rm 7 6 5 18 m HB XI san lt n HE 6 m PCS 6 31 Sty m dE PSVSW 6 PCS 5 15 HB 5 VGADS 16 UDCN 515 15 oPSVSW 6 PCS GNTET 5 T 6 ne LB PSVSW 8 lt PMS 5 6 UXWD lt 49 w
27. Er 2 PD7MSENI 155 ADRATEOIROS s 1557905 ADRATEIIDENSEL FD5 DENSEL DRATEOMSENO DRATEINSENII MOSER 8 SS S I A 8 155 DACKST DROSURVZPNF 8 155 5 INDEX 46 5 56 Br m 33 DR gt 8 5 0802 DRG2 MTRTIDLE 1 FOS DIRE SIP 0 ip RO woare FOS WGATEF 9 ms 2 4 OAT 25 3 IE gt RB 2 m 80 1 vor 7 FOR STRAPPING OPTION FOR 2F CSI 820 58 He 3 s 155 TOCHRDY IOCHRDY 4 lt ES 822 R6 1 2 100 B TT SOUTIBOUTI 2 1 5 8 lt RS NSF 5 Umr Hi SUN 6155 RSTDRV MR 69 195 5415 3 ORE 14 xose DSRZIFOI2IRRX SINQIRRXt NIU TXD 4 58 50072800721 8 S EM 4556 meee Drem SSE z PavsW PC07336VLJ R65 2 _ 16 595 190200 2 1 16V Q5 PSVSW 1 1 9 C56 2 1 PADS R64 B RI 0221 0805 PADS w l 10K 10 14W Tm TX 4 16 ut vec 4 6 NC MISD 2 x 5 CH 3 4 022uF 0805 PSVSW DONOT POPULATE 1 TFDS3000 18 18 23 18 23 18 23 18 23 18 23 18 23 18 23 18 23 1823 831 22 TFDS6000 Rt 3 014 R64 15 OHM C43 22uF 16V PAD
28. a PCDBS 22513 oe x ca PIDI9 a ae pes 92 ADO at 55 SAT 4 EEA He ADB3 4 VS5 RONRBCSE 2 a 8155 ORF RDL ADS E 8 IS5 OWE WA ADS s 27 FPACET 30 su su d K85 FPAGEZ Pit PTR pix 1 U PSTIRD 4 CATED 1 i GATED 5 1 2 Ih E 201 E RESTART 6 P32INTO 2324 5 S 1803 x 5 16 KB5 CAPLEDI 8 J 2 9 y LEDI 4 100 100 uie i 2 PSVR L lt OOO AMI 19 67 2 80C51SL 4 wl att o E 5 G5 SARES10 47K n KBS s PTRDAT 2324 5 __ P33SIF10 KB5 PTROLK 2324 KSI7 m P31 SIF01 SWE 16 P30SIF00 4 te 8 3 _ PTO K85 KBDDAT 2324 PITIAT 5 8 Go PIGAS RBS HDDBENF 1721 5 7 7 K85 MOE 1748 8 1 1 5 CDBENF 1721 ee 33 1 3 1 son IDECLKEN 3 15 79 15 FES PANDO 2 1 LT PANDI 2 T ae LT RB 22 KSO15 ANS PANDS 2 68 RST am e 2 100K LOADREN 889668 RIT i 0000000 D R119 8 800819 1K 1 on
29. 5 7 KB5 ADB6 139 10 TPADCON F 5 KB5 ADBS P5VR 6 CONFIDENTIAL ACER ADVANCED LABS Title PROJECT MARS MULTIMEDIA Sue Document Number ERNAL KBD AND TOUCH PAD CONNECTOR Date May 9 1996 TSheet of R56 1 2 MODVCC 12 FB2 xr anne x BLMATPOI car cst 6 lt 80 7 Le 65 500 2 18 t x ED B E aac BD3 4 18pF DH 8 B B H5 dE roo L G voc DR THOTA cto BRE e BD3 89 78 35 4 p B MOS MODCS 5 g AD USE TAACT32 MODVCC NOS ONF 1098 gfe gy iee x 1 At 1 9 DPI NOTA Ot 2 10K ____ __ 17 25 MOS DS 7 92 2 92 15 15 4 7 NDS 16 05 lt 7 x 4 ES 1 WEN i 5 06 2
30. J DONOT POPULATE 9 1 t 1 11 4 1 1 1 212 22 2 2 2 2 2 3 3 N PSVR 01121 314 5 6 7 8 9 0 1231415 67 CASEO2 ul P 678124 59012 34 56 7898 901245767 5435 4 HCR Lok RO R227 05 We e 2858 BEBEBE bis CER 123456789012845678801 0172345 4444432 152 S1N4148 BE0 P 5 E BEP 2 C BE2 C BERG RE C158 DEVSEL f DEVSEL 10uF 35V BESE FRAME POS FRAMEF REQUE m REORU neo 3 SERVI 32KHZ REQ 518 PCS DRREOF CPU CLKIN V1 L S REQ3 REOS 45 058 GNTo 5m 4 PT D B GNT T 45 PIS MOF POS DEONT 45 PIS W R 1 4 WIRE GNT3 4 PTS HCUNLOCRE HLDALOCK FOYE 45 2 CACHER TROVE 154 POS TRDYE 45 PIS HIME 217 0 HIM ibi n 45 SMIACT PADS lt Vis sc POS 16 575 PWRRDY PWRGOOD PLOCK LOCKE 4 055 BSERSTOT TOT 10 BSERSTOT n 16 RCS RST 4 RCRST QE Pu pg POIRST POS POSTE 7 ni BDCTLO P3VR PSVR 7 VSTEDCILI HS PTT NT 7 VSS BDCTL2 bs PT3 INTR 7 178 o ADPAR EVEN 6139
31. MNS MD28 029 MD3O MN 1053 MD MS 8 MD39 TINS WDAZ MD43 WNG MNS MDS 58 P3VR 7 5 4 77 X8 15 ET E B 15 t 1 1 4 2 1K gt 2 2 C246 0228 0231 0223 t ES BANKO CAPACITORS DONOT POPULATE C261 35V C269 35V RESERVE RESERVE RESERVE RESERVE RESERVE RESERVE RESERVE RESERVE VSS VSS VSS VSS 20000000000000 67 DRMWER R267 100K 59 MM3_RASR O 23 0 25 115 117 CASARES 24 DIMMT44P BANKO C229 C268 C267 C265 26 CASRES 116 CASR 118 CASRET 29 MARO 31 MM3 MART 33 MAR2 34 MARS 103 MM3 MARG 104 MART NS 1 11 P3VR 5 5 0109 O tul CAPACITORS P3VR 11 MN DRMWERE gt AS
32. PMS E 3 PISSTATUSB 13 vox HE EME BWP 016 PUE B WP TOTS 3 EVIDEO XE 3 pen 16 PMS E AIT 15 BE RO 147 36 POALI DCLK SE gn un nm em y A PATS 5 PCT C BERT 02 PDATA4 y POATAG 128 aos n ADS g 07 iod 124 0 123 09 T uus Hm fase PDATAI4LCDID3 12 7 PDATAISLCDIDA in PDATAIBLCDD 171 00100 READS mmm g 07 15 PNR POA 16 4089 17 ft 8 PDATA23 18 PNR AD23 02 142 1 Je AD24 50 8 145 010 1 rppack 4 5 05 12 R4 1 23 GR3 FP 5 56 113 R 1 2 338 670 5 iul ts mE Hy 0 bed RE T 255 GRE DNG EE E ADSI FPHDEMOD 8 C as gm s C BERT a g OA pe GRA BLU i 4 36 d p GR 6 3 PCS PERRE S o PERRE wwe 9 URDU TORA VSYNC 6 6 PCS TROVE TROVE 0080 SHORT GRA CCDD 6 6 PCS STOP 8 o pocsc lt GRA CODEC 6 6 PCS DEVSELF 8 2 Ri ot 5 lt INTE 9 NA ro
33. 09 09 09 PTS ea S e 6173 C199 032 E 032 TET T D M Hox ND no LEX ND no Bg GND Ei GND Ex DX GND Ox 90 90 ND ND GND GND GND HB RHET AAA 100K 8 8281 o M 90 BWE 90 BWE R238 R242 KE 100K KE 10K 0197 C25 3 ee sy PavsW l 1 CONFIDENTIAL PavsW 0219 ke im 165 166 ka lea IRI m3 2 otu ACER ADVANCED LABS Title CACHE DATA SRAM BANK1 Size Document Number SYNC CACHE RI AIL AI TEL DRMWE amp R23 MM3_DRMWER 6 NIMS DRMWER 6 RASRIO 6 5 1 8 CASRIO TANS CAST 2 7 MN C 3 6 CASRIZ CASS 4 5 CASRE SARESS 38 RN20 CASH 1 8 CASS 2 7 MBTI MNS CASS 3 6 WB TI CASH 4 5 SARESS 38 6 WING RNB MAO 1 8 2 7 MART MI 3 6
34. 39 P40 p 8 B A16 n Ep ld S m B D3 be DB B 3 B A15 PW ED pago gt 8 DTI 82 amp B D5 59 5 PIS B Di 6 87 PIS EDT Pag Pit x ind Pa LS B D 89 3 lt P6 B VSA 51 9 Pus B D P53 PIS BCE 3 PM5 B RESET 92 PNS DIS S BE 93 94 lt P56 218 Fo a 3 B INPACRE PME E VSE SEI 13 EN AZ mo LZ PUE AIT 3 PM5 B REGE gt PS B 3 pe C B 0 m Eo PE E TOW 3 rave ps uw WEEDS ME B 08 52 4 105 B ATB B DI Per Eb PMS B AT PE EDO e HU P70 P32 13 010 es R66 3 P72 ex LIE PME 20 10K P73 P35 PRE EADY gt lt P BOD P74 Hi PNS B Ai P75 P37 j5 P76 POVCIA TE2PCON PM5 B 01 028 B VS2F CONFIDENTIAL ACER ADVANCED LABS Title PROJECT MARS MULTIMEDIA Size Document Number PCMCIA SOCKETS Date May 23 1996 Sheet 4 of Note SW to tum off P12VR during 5V suspend
35. External Clock Enable This pin is used to select between internally synthesized clocks or externally supplied clocks A low level on the pin selects internal mode and a high level selects external mode In the external clock mode the internal clock synthesizers will be disabled completely Both PVCLK and PMCLK pins should be driven with the desired clock rates in external mode This pin should be driven all the time during normal operation PMCLKI Memory Clock This pin is used for feeding external memory STATUS4 clock and observing internal memory clock When in internal clock mode XCKEN 0 the internal memory clock can be brought out using this pin When in external clock mode XCKEN 1 PMCLKI should be driven from an external memory clock source General purpose Status bit 4 can be read from reg CR27 bit 1 GR17 bit 0 defines the function of this pin Video Clock This pin is used for feeding external video STATUS3 clock and observing internal video clock When in internal clock mode the internal video clock can be brought out using this pin When in external clock mode XCKEN 1 PVCLKI should be driven from an external video clock source General purpose Status bit 3 can be read from reg CR27 bit2 GR17 bit 1 defines the function of this pin First Line Marker This signal indicates start of a frame For STN panels this pin is connected to FLM pin For TFT panels this pin is connecte
36. IORCHDY Channel Ready When IORCHDY is driven low the EPP extends the host cycle IRQ3 4 Interrupt 3 4 5 6 7 9 10 11 12 and 15 This pin can be a IRQ5 7 totem pole output an open drain output The interrupt can be 9 11 59 sourced by one of the following UART1 and or 2 parallel port IRQ12 15 FDC SIRQI1 pin SIRQI2 or SIRQIS pin IRQ5 is multiplexed with ADRATEO IRQ12 is multiplexed with DSR2 and IRRX2 IRQ15 is multiplexed with SIRQ11 IrDA or SHARP Infrared Receive One of these pins is the infrared serial data input IRRX1 is multiplexed with SIN2 IRRX2 is multiplexed with DSR2 and IRQ12 Infrared Transmit Infrared serial data output Software configuration selects either IrDA or Sharp IR protocol This pin is multiplexed with SOUT2 BOUT CFGO Master Reset Active high output that resets the controller to the idle state and resets all disk interface outputs to their inactive states The DOR DSR CCR Mode command Configure command and Lock command parameters are cleared to their default values The Specify command parameters are not affected Table 2 10 NS87336VLJ Pin Descriptions continued MSENO 52 51 MSEN1 Normal Mode MSENO 88 86 MSEN1 PPM Mode MTRO 46 43 FDC Motor Select 0 1 These are the motor enable lines for drives 0 and 1 and are controlled by bits 07 04 of the Digital Output Normal Mode register They are
37. interrupt line and using PCI Interrupt Signaling mode In External Hardware Interrupt Signaling mode this pin indicates interrupt request IRQ9 Table 2 14 CL PD6730 Pin Descriptions continued Description Pin Number RI OUT Ring Indicate Output PCI Bus Interrupt B ISA INTB Interrupt Request 10 In PCI Interrupt Signaling IRQ10 mode this output can be used as an interrupt output connected to the PCI bus INTB interrupt line In External Hardware Interrupt Signaling mode this pin indicates interrupt request IRQ10 SOUT Serial Interrupt Output PCI Bus Interrupt C 205 INTC Serial IRQ Load In PCI Interrupt Signaling mode ISLD this output can be used as an interrupt output connected to the PCI bus INTC interrupt line In PC PCI Serial Interrupt Signaling mode this pin is the serial interrupt output SOUT In External Hardware Interrupt Signaling mode this pin is the load signal ISLD used to load the serially transmitted interrupt data into the external serial to parallel shifters SIN Serial Interrupt Input PCI Bus Interrupt D INTD Serial IRQ Data In PCI Interrupt Signaling mode ISDAT his output can be used as an interrupt output connected to the PCI bus INTD interrupt line In PC PCI Serial Interrupt Signaling mode this pin is the serial interrupt input SIN In External Hardware Interrupt Signaling mode this pin is the IRQ vector data ISDAT that is s
38. 1206 1206 1206 1206 1206 1206 PVSW BUS FRACTION DEFINTION 2 2 PADS PAD603 PAD603 NOTDEFINED 1 1 1 lt J BF gt 1 lt J BF 2 1 PADO PADO 0 1 2 CPUCORE 1 10K 1 2 p 2 V 3 1 RIS vs 2 lt A 1 SH 90 C22 2 50 01 1206 T 560 2 CPUCORE He CPUCORE CPUCORE 12 GND CONFIDENTIAL PVSW i 12 1 1 PSVSW 7 lt MOUNTING HOLES 2 ACER ADVANCED LAB Tile 54 TCP CPU MODULE Size Document Number Apri 8 1996 TSheet Appendix E BIOS POST Checkpoints This appendix lists the POST checkpoints of the notebook BIOS Table E 1 POST Checkpoint List e Disables Non Maskable Interrupt NMI Alarm Interrupt Enable AIE Periodical Interrupt Enable PIE and Update ended Interrupt Enable UIE Note These interrupts are disabled in order to avoid any mis action happened during the POST routine DMA 8237 testing amp initialization System timer 8254 testing amp initialization Verifies CMOS shutdown byte battery and check sum Note Several parts of the POST routine require the system to be in protected mode When returning to real mode from protected mode the processor is reset therefore POST is re entered In order to prevent re initialization of the sy
39. 32KBR RNAI c R40 4 8 VIDEO E 1 2 6 MMVDR 1 10 3 3 8 IDECLKR 4 5 fa Ba SARESS 33 42427 4 2 4 PI503126 RI6 22K PSVR i R131 20K 2 CRN 6 3 L R129 Z 27002 2 1 H 2 ACER ADVANCED LABS Int Tie PROJECT MARS SYSTEM BOARD Sze Document Number MARS SYSTEM BOARD spo 8 13 15 20 22 31 P3VSW PSVSW 56 5 187 1 2 20K 5 RMB 1 2 R249 1 2 8214 1 2 20K 5 82151 2 20K 1 2 20K 6 lt P REM 1 2 20K 2 1 2 20K lt 1641 2 20K 166 1 2 NK 5 CPHEDS R218 1 2 6 CPIHIW 8216 1 2 20K 6 R213 1 2 20K 5 lt PRA 1 2 20K 5 1 2 NK 5 lt CPTS PICDO DPEN 5 3 Ri38 1 p 6 CPESMACE R246 1 2 20K 6 lt PISFERRF RM 1 2 _ 1 9 10 2 3 PT3 PT3 DF 3 8 PT3 DP5 PT3 DP 4 PT3 DPS 5 6 PT3 DP SARES10_100K R245 1 2 10K 5 lt CPISPICDTAPICEN 4 RS 1 2 10K COSE SR o gt 26 26 P3VSW 8 13 15 20 22 23 29 31
40. 4 x T M n 0260 7 EE eur R105 AUDGND 22 1 2 1 PSVR 1 220pF 3 4 _ 073 5 67 R73 TONA 31 PCSPKO 2 y 2 I 033uF 0805 R71 UDGND AUDGND 9 s AUDGND 2331 ADA C18 1 2 1 4 0 220uF_10V m 16V i 2 BYPASS 1 1 8 2 I 1 6 VSS SPKOFF 4 SPK CON D cn 100pF LEFT SPEAKER Um O 1uF 7 0uF 100pF gt a AUDGND 22k AUDGND 2 e 28 c51 AUDGND 220pF _ R74 1 2 1 2 2 033uF 0805 rs m E 6 UDGND AUDGND ut 3 RIS C50 2331 TOR 1 2 4 4 FBI 2 2 1 1 N23 16 4 bypass 2 9 j I 2 We to SPK CON p cm 100 100pF 100pF RIGHT SPEAKER Vu 16 our pr AUDGND AUDGND 1 R76 AUDGND DONOT POPULATE 22K 2 AUDGND 25 ACER ADVANCED LABS Title PROJECT MARS Size Document Number A SPEAKER OUTPUT CIRCUIT AI T lt gt PSVSW PSVSW PSVSW as 9 12 TM 09 H 10 027 0200 1 TANCTOS TANCTOS PSVSW PSVSW 9 1 4 SM 11 10 OF TARCTOASS PSVSW PSV
41. 5 R293 men x LS 445 5 8 100H 1 0083 OHM CSH 55 3 C198 C196 REF de 9 220F 10V 220uF 10V c i 4605 MBRS140 00 DL 12 PGND PGND R324 PGND 100K MAXI 1 2 Reve ms 2 U46 lt lt 8 b SW 1 1 2 R291 1 4 7 4 10 pag 1 PGND Our R325 13 1 Qoo 51K H R292 057 200K 4 MAS 470pF R326 PGND PGND 1 2 1 10k 021 PGND S1N4148 DXt 0 m m CN20 VDCF 28 1628 DCN 16 16 16 16 28 2328 28 LEFT RIGHT PGND PGND PGND PGND PIAR PR PSVR DCN CHRGOUT et c2 62 c2 CONFIDENTIAL 35 35 35 35 35 35 35 35 35 35 35 35 PGND PGND PGND PGND PGND PGND PGND ACER ADVANCED LABS Title PROJECT MARS Size Document Number DC DC CONVERTER TEL F
42. 64 bit DIMM memory architecture 256KB 512 KB external L2 cache memory e large display in DualScan STN 1 1 3 or active matrix TFT 11 8 or 12 1 local bus video with 128 bit graphics accelerator Flexible module bay 3 5 inch floppy drive or CD ROM drive High capacity Enhanced IDE hard disk Heuristic power management with suspend to memory and zero volt suspend to disk power saving modes Lithium lon smart battery pack High speed connectivity 16 bit stereo audio with built in FM synthesizer Built in microphone and dual angled stereo speakers 30 frames per second full screen true color MPEG video playback e Infrared wireless communication e Internal 28 8Kbps modem with DSVD digital simultaneous voice over data support with speakerphone and telephone answering device features HUMAN CENTRIC DESIGN AND ERGONOMICS Intuitive FlashStart automatic power on Sleek smooth and stylish design e Automatic tilt up full sized full function keyboard Wide and comfortable palm rest Ergonomically centered touchpad pointing device EXPANSION Card formerly PCMCIA slots two type or one type 111 Mini dock option with built in Ethernet User upgradeable memory 1 1 2 FlashStart Turning the Notebook Computer On and Off A noticeably unique feature about this notebook is that it has no on off switch Instead it employs a lid switch located n
43. 0000 O OO 00000000 NE us 2 ajajaja 12191918 Hh siele lelslelele 1818 1817171711171117 1 9868 1881 2654320 123 08765432 cc MMC MMMM MMMM HHHHHHHH HH HHHHHHHH PCS DKGNTE MMRR MMMM MMMM M HHIHH s333 3333 33 333333323 2 CLKRUNE R57 3 3 AA 3 3 33 1333383 3 3131313 zx EE 00060 06 155 FLASHROY PSVR 0000 0006 D AA23 AAAA DD EO 666 06 1 sis 151535 ssss M VS E 100000000 CW 5 RID 1 2 10K HH sese ses w alc 1011121314151617 1011121314151617 PADIB SNE_OVINE RI 1 2 10K PNR 011 0111213 14151617 2 CONFIDENTIAL GR3 VGACT mo WK o 3 VSS 1 PSR 90 I 910 PR 127 940 940 P3NSW ma 22 316 32 3 22 910 3 11 910 910 68 212223 68 212223 68 212223 68 21 2223 8212223 78212223 8212223 8212223 8212223 8212223 82223 82123 78212223 5 5 4 5 4 132531 8 ACER ADVACED LABS Inc Title VESUVIUS V1 Size Document Number 1 65 5810 PT3 00 53 EN
44. 19 20086 001 INVERTER 62 039 970 46 34 46850 002 DOOR DIMM AL 970 60 46807 001 ASSY CASE UPPER 050 970 77 42 46809 001 CHASSIS CD ROM PC 10GF 050 al 60 46814 001 ASSY LCD PANEL 11 8 970 47 86 1 522 280 SCRW MACHINE PAN M2 2 NI 570 86 6A522 4R0 SCREW MECH RWH M2 4L NI mz 60 46815 001 ASSY LCD BEZEL 11 8 970 48 42 46853 001 COVER SIR BACK NO RJ11 PC 56 10071 081 DRV TOSH XM1402B 6X 42 46803 001 RAIL R KEYBD NYLON66 050 970 a 56 10071 081 CD DRV TOSH XM1402B 6X E 56 07355 021 HITACHI 11 8 TFT SVGA 970 79 50 46804 001 ASSY CD ROM CABLE 52 970 TBODO1 39 46802 001 CASE UPPER PC 10GF 050 970 19 39 46801 001 CASE LOWER PC 10GF 050 970 79 __ 50 46801 001 CABLE ASSY 11 8 970 42 46847 001 KNOB R TOUCH ABS 050 970 E 34 46813 001 PEN HOOK MODULE SUS301 p M2 5 4L NI 23 42 46812 001 KNOB L TOUCH ABS 050 970 177 19 20086 001 INVERTER T62 039 C 970 23 60 46821 001 ASSY CD ROM BEZEL 050 970 42 46802 001 RAIL L NYLON66 050 970 42 46814 001 HOOK LOCK MDUL NYLON 050 m __ 60 46814 021 ASSY LCD PANEL 12 1 970 970 Bp nace ono __ 60 46815 031 ASSY LCD BEZEL 12 1 970 83 34 46829 001 L AL 970 25 42 46806 001 DOOR CARDBUS PC 10 GF i 050 970 42 429 8 001 GASKET EMI 71TS4 1 900 9 156 07468 001 IBM 12 1 SVGA SV50D 34 46811 001 SPRING DOOR CARDBUS 31 46803 001 PLATE SHD L C
45. 24 4 ESTO gt e 0180 2555 14 755 SUSPEND BMCVCC 1 02 hp S1N4148 1K FAN CON 04 029 2N7002 4 MADE 16 SUE H 2 3 lt 080 2N7002 D3 07 1 sma 16 0 R344 1M 0805 36V 4 DONOT POPULATE ACER ADVANCED LABS Title PROJECT MARS Size Document Number A RTC BATTERY RI R79 75K 2 1 R78 en 10uF 16V 2 FB12 3 ADAMEN 2 100pF AUDGND DONOT POPULATE FB10 C85 FB 16V FB9 xin 16V PSVSW 1 4 Roo 23 DDKHCHUT 20K 1 ROG T4HCTOASS 06 100k 1 RN1424 2 ADVDD PSVSW L s ADA 31 DRIN 31 AUDGND a CONFIDENTIAL ACER ADVANCED LABS Title PROJECT MARS Size Document Number MIC INPUT CIRCUIT Date June 11 1996 TSheet 30 of
46. CASRAO 7 11 MX MARO TI PAR MMB MDO lt 2 3 000 vcc 5 pat vec i 00 voc np Re Wc 1 Dat 15 Dodd 5 10 voc 10 voc par ST voc MOM 39 voc We 41 oaio ar 001 Nc 47 002 81 voc se voc ME NDS B 0007 vee 85 008 59 Hi SM5 CU 16222328 MES HOA Z T 0020 SDA E DATE 16222328 0001 97 0022 REUS x 9 Hex Lx NDS 18 005 RU w x 0026 mu S x MD28 1 0027 BU gx MENOS 171 mu 18 04 n 137 4 0081 8 0 wer 587 DRMWER g 008 WE 077 1 2 ARE 10 15 0 n 0 MN 5 008 REM 18 T pos 38 008 pa CASRIO 40 000 CASRET a 000 pis MDA 44 MCA 4 C Dou C I 0045 5 52 006 CE moose 5 006 MD48 84 41 49 36 0048 MARO 0009 D 30 UE NDS 0 MMS NDS 96 0082 jl MD54 006
47. CLKIN Connect to DTP IA1CLK 8 Connect to DTP TSTROBE TSTROBE Transmitter Strobe Connect to DTP IATCLK SA1CLK 87 SAICLK Connect to DTP TRESET TRESET Transmitter Reset Connect to DTP SA1CLK D 182 SR4tN Connect to MCU RXDAT SR3OUT D 83 SR3OUT Connect to MCU TXDAT 2 5 ESS1688W Sound Controller ESS Technology has developed the ES1688W AudioDrive a single chip solution for adding 16 bit stereo audio and four operator FM music synthesis to personal computers It has integrated all the major blocks of audio in to a single chip that can be designed into a motherboard notebook PC add on card or integrated onto other peripheral cards such as VGA LAN etc The ES1688W AudioDrive can record compress and playback voice sound and music with built in mixer controls It consists of an embedded microprocessor 16 bit stereo A D and D A 20 voice FM music synthesizer MIDI serial port compatible with MPU401 UART mode DMA control and ISA bus interface logic A DSP serial interface allows an external DSP to take over analog resources such as the D A or A D converters Control of I O address DMA and interrupt selection can be by jumper or by control of system software Interface to analog inputs is extremely simple There are stereo inputs for CD audio line in and an external music synthesis chip and a mono microphone input to an internal pre
48. Hix DGNDI os 2 21 TSTROBE 1ojF 16V 2 NC TRESET BOY Lx EYESYNC 2 NC TMODE NOS 8 H NC RMODE GPO R59 2 NG 888007 A 8 0 m HA 2 0 SRAIN 8 tour 16V 00 8 i 100 Xn 18 Hx 4 A NC BOUT Hi RODE 4 NC SR3IN Y Vest TMODE 1 59 MODGND 19 4g 4032MFZ 5 Do NC vsse TXDAT a 165 P e LE M 4 55 5 4 Ln 3 vs DPS IRQ 5 CT ae THOS DE 10 D3 30 35 10pF SLEEP 3 MOS SIEEPF GND2 CLKIN HJ 05 RN UN 10 WeD 0 Oh 07 i 7 MODGND R668424 eee SR M NE 1 Z mMm gg QR the tev READ WHITE READ LEX 4 2 WRITE Ly 4 SPSEL NC GM 2 CS Q NC GPb us wm NC GPIZIRINGD Ju TF 16V VOS RETE 17 POR eo Hi MODVCC z E UXCTRE ex 100 XIAU LEX MOS Dio NOS DD 8 So MOS 08 00502 Le 5 8 DGND3 DGND4 Hix 4992MHZ 06405 NC Pg x a Hm T DGNDAT CLKIN 3 p DGNDA2 AGNDI 7 P 4 DGNDAS AGND2 R6693 14 MODVCC Moovec
49. Petey T JGNNEF 1 OFF PADI PAD2 GND 8 175 GND lt GHD 82 GHD PIS INTE 1 8 CPUCORE rae 2 Im PT3 058 E 7 193MHZ CPU TED 8 PIS RST 55 PT3 D62 80 99 GND 7i 72 GND ON PADI Fo GND 1 89 2 CPUCORE 2 CPUCORE OFF R7 P D2 g PRA 67 8 Dou PTS 518 PT3 25 PT A6 1 PT TERRE HE ERR 1 00 6 a eU 150MHZ CPU GND 17 180 rm GND BPO 1 PAT 815 e 5 PT 28 ENS 105 10 TEES 5 58 ON R7 FO TEN 15 19 We PUES i GND 5 07 8 n GHD OFF PADI PAD 1 PTSCACHER 17 107 18 lt 1 5 1 LX 109 110 FIM 51 52 E GND i GND EWEEE 4 15 p PNSW GND 7 18 9 ope GHD CPUCORE 45 CPUCORE 1 15 5 HE PTS 1 at 5 45 5 mut 1 PT Ta ne HB PT 1 mS 8 18 a 1 PIS We WIE GHD Te A T GHD PIS NAE 1 GND 9143 2 UND PNSW 38 0 1 PMCT 125115 1 PTS FOD 1 dE MEAM 1 PTs v m PT3 PRDY 1 B 58 u L Um 10273 GHD 5825 omm GHD 1 CPUCORE onm CPUCORE PNSW AH 2 18 2 PTS
50. a 2223 18 SVEMWE 2223 PCINTD 3 a AEN EA 15202231 lt 21K say sa LE 5 32 62023 PAOR LOCK t ea mE 13 6212223 DEVSELF DEVSEL 10 o DEVSEL s i 672122 x FRAMES VSS gt IRDY 118 6212223 500 6212223 TROVE PCS 19 C i 01 02 2228 PMSROSER PNG 97 503 PERRE x 15 9 PERRA T EM T SERRE ERR 05 6212223 STOP STOP stops E 6212223 14 pap E 09 E s gn VS3 ESERTTOS BSERITO3 6 BSERCLKVS 48 BSERCLKV3 PIVEN 5012 gt 5013 15 82 5014 52 d 155 IR C35 023 1322 1551805 9 05 13 1557906 f ims 4 413152022232931 1322 55790 7 ro 29 B5 18 5 1322 55 9010 71 1331 TJ mon 15 ISS ROT 2 mmc E 21 551901 8 55 9075 1015 AS E ROMKBCS 1331 55 0900 2 0800 PSVSW 182231 155 0901 ST rat 13 55 DROP s DRG R12 55 OW y 0 2866 10 at 55 57 DRO 100K 155 2 9 1 s vew 22 55 DROS 1 z 59 BROS Cal 2 _ 2 155 SMEMWE 3 8 155 c ge 06 TX OE dev tour 2 16 55 1 7 155 SBHE 5 5 55 65 MASTER 88 FRA 2 9 MAS
51. memory address and data busses 5 2 2 2 burst read cycles with 60 ns EDO DRAM at 66 MHz e 6 3 3 3 page hit and 10 3 3 3 page miss burst read cycles with 60 ns standard DRAM at 66 MHz Two less wait states in the lead off cycle for pipeline access e Write buffers for CPU generated DRAM cycles Supports read reordering Support for ROM shadowing e SMM RAM size from 32 Kbyte to 128 Kbyte Easy SMI code copying to SMM RAM in normal memory mode Q Local Bus native architecture e Supports 32 bit PCI Local Bus Supports both 3 3 V and 5 V PCI e Provides synchronous interface between the CPU bus and the PCI bus e PCI Local Bus revision 2 01 compliant Supports Mobile PCI specification Supports PCI burst cycles Maximum 5 PCI masters and 4 PCI slots e Integrated PCI bus arbiter with rotating priority e PCI parity and system error support PCl to ISA memory post write PCI interrupt steering e Intelligent power management through clock scaling Docking station support PCI to ISA bridge 33 MHz operation on the PCI bus Fully supports the ISA bus Master slave interface for the PCI and the ISA bus PCI to ISA and ISA to PCI bus cycle translations Hidden AT bus refresh Quiet bus Supports PC parity and system error 8 bit BIOS ROM FLASH EPROM support Generates chip select for external KBC keyboard controller Coprocessor interface Highly integrated peripheral controller Two
52. 0 HDD6 CHETER FD5 118 HD5 HDDS CDFDDVCO HD5 CDDIS HD5 000 ANS 815 19 HD5 A0 Hd HDS HDA0 RNS HD5 00013 19 HDS AT Hd HDS 0015 1 10 HD5 CDDT2 2 pu HD5 HAZ HDS CDD 32 9 HD5 HD5 A HD5 ROY ni HD5 HDRDY HD 3 8 HD5 CODIO 2 HDS CDD 4 7 HD5 0009 HD5 009 2 1 Ex 58 HD5 0008 HD5 CDD6 5 13 SARES10 10K ADA CDAUDL GND 31 CDRUDL 27 HDDBENF KB5 HDDBENE 25 BEDE GND 31 ADA CDAUDR ae 28 16 SMSBAYSW SMS BAYSW 29 HD5 CDD 1 10 a CE HOSELOODE 2 9 CD 3 8 HD5 CDD2 HD5 0583 6004 4 21 HOS 5 5 05 0000 POR HD5 015 PE HD5 0015 CDFDOVCC 65 1008168 HD5 DO M Bo 7 8DS 6000 SARES10_10K si FOE COORG CDDACK HD5 Did A SMCDRDY p 9 UN C CDFDDVCO i IRE WORT WDATAF HD5 D2 35 HD CDD HD5 012 5 85 16 0012 21 HDs COE HD5 CDDRQ HD5 CDD 21 lt 105 CODAT 42 HD5 03 5 B6 io RDATARCDDS 2 I i HD5 DiT 87 m HD5 CODO a 8 p TFS WPHODDT PSVSW HD5 CDD 2 13 1 C156 155 0187 OFS RDATAFCDDS 2 1 T F dor HD5 CODA 2200pF 220
53. 2 PGND C208 4 PGND 024 S2N3904 2 91148 ar R255 PGND S2N3906 3 015 100K 2 4 SETDSW 16 PGND 314148 3 018 Fon 22 PHRLONSW 2N7002 1 314148 1 2 8273 100K 10K 33K PIAR DM 91448 CMPZ5243B 7 n l 3 1 NA 1 PGND 3 27 P 1 t 518904 m S1N4148 25230 171 2 R253 16 EVE BVCPWREN i 2 1 022 D10 D 1 10K 2200 27 PIR 3 M 1 R277 sdis 1K R256 BMCVCC 3184148 cua 2 100K oofuF 2 06 SIN4148 T aar PGND 3 R342 020 4 Mer 1 6 WIRE 7 515 12162223 10K 514148 CONFIDENTIAL 8 3 lt SWE DATE 12162223 018 ing 10 1 1 2 pi 5 MBR 140 1 CON ACER ADVANCED LABS In PON BAT CON POND PROJECT MARS Sze Document Number REV POWER ROUTING 30 AAA Tiri s PSVR PSVSW Ps IMCVCC PSVR PSVR 48 13 520222331 500 155 500 p 24 Ru x ADO ADI MEAT 10k 21 2 9 ADA RESET 5 gt ADT MOT PSVSW 8 VS5 ASRTC 14 AS 69 8 VS5 DSRTC 17 DS 8 VSS RWRTC RW m 1 25 155 RSTDRVB Cs NC R126 2 H 1 xi
54. 3 HDD power enable pin 42 SM5_HDPON of SMC This pin turns the power on off for the hard disk only 4 HDD reset pin 40 SM5 HDRST of SMC This pin provides the reset to the drive when the drive is newly powered up The reset pin is asserted when the drive is first powered up then the reset is removed after the drive is powered up and before the interface is enabled CD ROM The CD ROM and the hard disk are both IDE devices They share the same controller The following pins are dedicated toward the management of power on the CD ROM 1 IDE controller clock enable pin 32 KB5_IDECLKEN of KBC This pin is shared with the hard disk If either the hard disk or the CD ROM is in use then the clock enable pin must be enabled CD ROM buffer enable pin 35 KB5_CDBEN of KBC The CD buffer enable separates the CD ROM from the IDE controller This buffer must be disabled before the CD ROM is turned off The buffer is re enabled after the CD ROM is turned on and brought out of reset CD ROM power control pin 30 SM5 CD FDPON of SMC The power control pin is used to turn the CD ROM unit off or on This pin is shared as a power on off pin for the floppy disk as well If either the internal or external floppy or the CD ROM is active then this control pin must be asserted on CD ROM Reset pin 45 SM5_CDRST of SMC The reset pin is used to assert the hard reset needed for the CD ROM during power up The reset pin is asserted befo
55. 5 EB ET 7 155 505 25 B m E B 197 GND PMS TROSER gt D 37 80 DIG TX 155 507 80 ADE JO 81 GRABND lt LX e 1 831 5 8 232 192 DIG TX 72 32 GND 25 8 3 ARDY lt 00 00 M Bx 064 LE 5 16 4 25 4 16 SUE WODPONF 5 B35 1627 DAA FECT 76 36 237 36 B6 7 R113 DAA 7 4 B 97 lt 1 AT BN DON 122 38 198 20K DA 78 38 o 2 2 CE 88 uw wan AS __ moo 22 BO SE DOKSW 16 22 lt RING BO 1 R222 20K 2 1 R181 3 a 2 8i GND 1622 SM5ATNE ERR a PLUG Bs B3 H 5 19 BON 16 595 BVCPWREN Du amp HE 19 16 lt 916 ON RES SW 15 SPS 1 SPP RISE 19 PPS POS 7 87 d n od 5 19 P5 DCDB 19 RST DCKB 810 812 UBA TAALS08 86 B17 B18 B19 B20 68212223 821 822 823 682122 824 825 616 826 148 E lt 32 AUDGND lt 31 n 881 lt B EN 31 12 26 5 qA M5 aao lt A36 836 31 17 4 Bm AUDGND d 0 B3 16 lt D SHORT 380 84
56. Flow control and speed buffering Automatic format speed sensing to 115 2 kbps Serial async data parallel async data Auto dial and auto answer tone and pulse dialing Caller ID and distinctive ring detect Device packages R6723 100 pin PQFP e R6684 68 PLCC e R6693 100 PQFP 5V operation Power use typ Operating 1 75 W Sleep 220 mW Architecture Block Diagram XTALI MCU MDP Crystal XTALO Crystal XTALO AT Bus Interface PnP Telephone Line Telephone r Audio r NVMCLK Interface Circuit 32Kbyte NVRAM BAM Figure 2 9 RCV288Aci SVD Architecture Block Diagram Signal Types Annotation Table 2 7 RCV288Aci SVD Signal Type Annotation Description O8 T omuwiwsme ___________________ OD __ Relay driver output HB meaw HD freasa Oooo Table 2 7 RCV288Aci SVD Signal Type Annotation continued D Analog input input impedance gt 70 maximum AC input voltage range is 1 7Vp p and reference voltage is 2 5Vdc Analog output maximum load is 3000 output impedance gt 100 AC output voltage range is 2 2Vp p DC offset voltage is 200 and reference voltage is 2 5Vdc Analog output ma
57. PNR 5 n PR o 59 19 28 3 CRE 59 119 PSVSW 2027 PIR 8 120 12 1628 80 60 H2 POL CON F CONF 2 782123 m m 23 CUAK DAA RING PRAE gt 4813152031 155 SA0 ESSET BA 1000pF 1KV 1 7 7 3 b PAR 6 i o P3100SB 27 ON 1000pF 1KV PSVR 2 MM CONFIDENTIAL U TP Ion PavsW i R 1 ACER ADVANCED LABS Title PROJECT MARS Sue Document Number MULTIMEDIA BOARD CONNECTOR Date June 6 1996 TSheet 22 of 12 16 28 18 26 13 18 13 13 18 13 18 13 13 68 21 2223 672122 22 22 22 22 22 12 16 28 DATE 6 PC3 RST D SM5 DOCKED 48 13 15 20 22 29 31 NEW SIGNALS PIN41 35 LONG 20 N 161 LONG 545 DOCKSW WR 1 A ND
58. TARGET READY This indicates the ability of the target device to complete the current data phase of the bus transaction During a read phase TRDY indicates that the valid data is present During a write phase it indicates that the device is prepared to accept data DOCKED See GPIOS DOCK START See GPIO2 0 148 149 EXTERNAL ACTIVITY 1 0 These pins indicate that there is current external activity GPIOO LEDO 131 GENERALPURPOSE This pin can also be selected as a general purpose pin Its function can be enabled by index register 352H bit 0 LEDO LED indicator output 1 GPIO1 LED1 130 GENERAL PURPOSE 14 This can also be selected as general purpose pin Its function can be enabled by index register 352H bits 2 1 LED 1 LED indicator output 1 SUSPA 130 SUSPEND ACKNOWLEDGE This output from the Cyrix 1 CPU indicates a suspend acknowledge state GPIO2 129 GENERAL PURPOSE 2 This can also be selected as a DOCK START general purpose pin Its function can be enabled by index register 352H bit 3 DOCKING START This pin indicates that docking has started Table 2 2 V1 LS Pin Descriptions continued PinName Type GPIO3 128 GENERAL PURPOSE 3 This can also be selected as a DOCKED general purpose pin Its function can be enabled by index register 352H bit 4 DOCKED This pin ind
59. 2 9 CHI 57 9 CHEE 6 8 gg COEF 6 CRIARI IEEE 8 6 E 2 CH3 m CH3 FT eos 5 2 10 lt CH FTF 16 NC 2 2 m Ne co PADS x ne 1 1 6127 7 6142 cus Lu 5 i PT3 080 2 GND si GND i GND HX GND nme GND GND PavsW 90 an BO RBI DK GND GND Cus 0150 R170 PT SED 100K PD PAD603 Pasw ot H CACHE SIZE 512K INSTALL R174 R219 0015 AND REMOVE PAD13 PADIG 2 CACHE SIZE 256K INSTALL PADI3 PT3 TERES AND REMOVE U33 U34 R174 R219 PTS 3 5 SRI PIPELINED SRAM INSTALLRITS 8 PE 5 EUN FOLLOW THROUGH SRAM INSTALL PADI AIT 1 pea AND REMOVE R179 xy 3 x 3 AT 5 5V TAG SRAM INSTALL PADIS AND REMOVE R180 4 10 P3SW PTT 21 33V TAG SPAM INSTALL R180 AND REMOVE PADIS 0 187 2 i x PT3 A18 1 2 PRAN 2 R 0 l AM cd 2 5 PADIG PADS ji 1 vss ae MT5LC2568 520815 CONFIDENTIAL ACER ADVANCED LABS Title PROJECT MARS Size SYNC CACHE BANK 0
60. 23 gt 050 848888885888885889 549499 499001 2 o DOR 855555555 8848888885888888888838845332353433 7 8 5 2 Figure 2 5 PT86C522 V2 LS Pin Diagram Pin Descriptions This section contains detailed functional description of the pins on V2 LS For ease of reference the pins have been arranged alphabetically within each of the following functional interface groups CPU Interface CPU DRAM Interface DRAM PCI Interface PCI e V1 LS V2 LS Interface V1 GS V2 LS Power and Ground POWER GROUND The symbol at the end of a signal name indicates that the active or asserted state occurs when the signal is at a low voltage Signal names without the 4 symbol indicate that the signal is active or asserted at the high voltage level The symbol between signal names indicates that the signals are multiplexed and use the same pin for all functions The following conventions have been used to describe the pin type input only pins O output only pins and bi directional pins The pin type is defined relative to the Vesuvius platform For a list of pins arranged by pin name refer to the following table Table 2 3 V2 LS Pin Descriptions Pinno Description D 63 0 67 40 CPU DATA BUS D 63 0 These are the upper and lower bits of 38 22 the 64 bit Pentium processor data bus 20 8 6 4 1
61. 4 1 5 5 1 4 3 9 2 8 DPSEL 10 E 6 74F00 1 MODVCC CONFIDENTIAL 4 ESAE 4 4 12 5 11 13 068 74600 060 74600 ACER ADVANCED LABS Title PROJECT MARS MULTIMEDIA Sue Document Number DSP INTERFACE Date Way 9 1996 9 4 MODVCC ai 10uF 16V 5 RIS E 61 9K 1 0805 5 2 T 10uF 16V 3 3 3 PMBD7000 M y A PBD 1 1 1 2 0 047uF 200V 2 4 4 DARING 6 1 1 RI3 RI 1K 75K 2 un 2 1 8 RIP SER 2 1 2 1K Ld s 0 33uF 20V 2 o 5 1 1 4 Ey J TRES CON 689 lt T gt lt 3 20K ca 2 1000 2 1 2 f 100 PAD RT 1 PADS Dt MODVCC R22 499 1 0805 M 5 8 BASIE 12 phum R17 ves 1 1 1 x T AC noz 801 1 6 4 R30 1 3 R29 2 A NIS C63 10 1 Tue MODVCC 9 2 8 6 Ut38 PRI 73 7 7 4 5 R21 4 TLO2272 TR671 8274 n TIK 1 499K 1 0805 MODVCC MOD R28 8 4 2 c21 R25 1 1 R31
62. NR vum OISSA m X a M gt E 3 lt 38 154 lt 159099 oa gt Ai ASH WAVLINI lr N 50140 fL ws 0 9 o LE O i938 20149 lt gt 1099 g 5 M gt e 3409 Sr F lt 8 3409 SSA asss 145054 9415 50414358 rhs 3809 99 ISSA 81 SSA av rages a 359 UM AHGLSH lt ny av 1589 i gt uv lt i i 636 0 w 236 ov ISS siu z i gt TS 8883535 885 8588858 055254 888802 2 E 5 8 PT86C521 V1 LS Pin Diagram Figure 2 3 Pin Descriptions This section contains a detailed functional description of the pins on V1 LS For ease of reference the pins are arranged alphabetically within each of the following functional interface groups CPU Interface CPU DRAM Interface DRAM 2 Cache Interface L2 CACHE e PCI Interface PCI Power Management Interface PMC V1 GS V2 LS Interface V1 LS V2 LS V1 GS 3 15
63. These signals are decoded from the A2 and C BE 3 0 inputs DSA 1 is also sampled as inputs on the falling edge RESET All of these pins have internal pull up resistors 2 2KQ resistors are recommended where pull downs are required Table 2 15 PCIO643 Signal Descriptions continued DSD 15 0 Disk Data bits 0 through 15 These are 16 bit bidirectional data bus that connects to the IDE drive s DSD 7 0 define the lowest data byte while the DSD 15 8 define the most ENIDE FRAME significant data byte The DSD bus is normally in a high IDSEL 10 impedance state and is driven by the PCI0643 only during the DIOW command pulse Enable IDE This is an active high input that enables the PCIO643 s default mode disk operation following reset When set to low the 10643 is disabled following reset This mode allows software to scan for system hardware and enable the 10643 via the PCME register index 4 When left floating or pulled high the 10643 is enabled and cannot be disabled via software Cycle Frame This is driven by the current master to indicate the beginning and the duration of an access FRAME is asserted to indicate that a bus transaction is beginning While is asserted data transfers continue When FRAME is de asserted the transaction is in the final data phase Initialization Device Select This pin is used as chip select during configuration read and write tran
64. essent 4 9 Unplugging the Display Cable 4 10 Removing the Display Hinge Screws and Removing the Display 4 10 Removing the Hard Disk Drive Bay 4 11 Removing the Hard Disk Drive Bay 4 12 Installing and Removing 4 13 Installing a Memory Module via the Memory Door 4 13 Removing the Battery Bay 5 4 14 Detaching the Upper Housing from the Inside Frame Assembly 4 14 Removing the To chpad eere ue eee eus 4 15 Unplugging the Speaker Connectors and Battery Pack Connector 4 16 Removing the Main 4 16 Removing the Charger Board and Multimedia Board 4 17 Removing the PC Card Slots 4 17 Removing the LCD 4 18 Removing the Display Bezel 4 18 Removing the Display BeZel 4 19 Removing the Display Panel Screws and the Display Connectors 4 19 Removing the Display Cable 4 20 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 1 10 1 11 1 12 1 13 1 14 1 15 1 16 1 17 1 18 1 19 1 20 1 21 1 22 1 23 1 24 1 25 1 26 1 27 1 28 1 2
65. m Im P ly C161 C36 a 3 7253 153 17 ADPAR 000 CPURST 32 RSICPU NOH 31 18 4 1 L PTS CPUCIK 7 VSS DECBUF 134 DECBUF 153 20 7 VSS INCBUF 12 INCBUF PUN 0 7 VSS PCNSTR POIMSTR PCICLK rr 1 i um BSERCLKVS 800 8155 801 Ed PTS ROBE BD2 E AHOLD 803 BR PT3 BFDYF BD4 HOLDIBOFF 5 PTS FODEOFFF 805 bR 806 PT3 NAF 807 KENBINV KENE seem co BR mem urs epe ues WB_WT 3 F 143 RSTDRV 5 BSERVTOY Vert Ms 31 5 INTAWM RST PIS INT i VaR gt MG MATO GP2DDMA RETRY 10 31 2 VS5 DOWA 1 GP3SUPPRESS RESUME VS5 CONG GP4UNDOCKING 155 FLASHVPP RNG dn R50 5 15 KB 133 1 PCICLK_DCK 1 2 33 X CU 29 RTS tig WAI CLKRUN i F 22 ORI VGACT EXTACTO 198 PCIRST_DOCK 3 PNSW H 3 PT3 ARER EERE M 5555556 BRDYF 5556 T p b t PCICLKR D RRRRRRRRRRRRRRE REP PIKEN 4839 DDDDDDDDDDDDDDD 444 4434567 FF 01234567
66. 10K 2 4 3 8 55 FSTDRVE gt 29 TAAHCT1258S 1 0 PSVR 1 1 1 1 R87 R88 R83 R82 100K 100K 100K 2 2 2 2 1 2 gt i 4 0 5 2 3 Lak M PR o M wc PR 4 cH c92 1 3 T4HCTASS PSVR CONFIDENTIAL ACER ADVANCED LABS Title PROJECT MARS Size Document Number ISOLATION CIRCUITS RI TEL 039 984100 PAR I erst I PNW gt 4567891011212224 07 _ 9138 4 cx R235 0189 PINR o 4 2 3 1 2 4 1 10K R208 1 T 300K 984100 PER PSW 34589434415161748192021222324293031 236 I 4 15 1 4 gt 4 lt R132 2 015 1627 VS5_SUSPENDE 1 DA 4 1 2 4 O tuF 10K Ua R234 100K pe 2 PR o B k 3 gt 17 05 _ 2138 4 mp R62 124 PIAR o 2 3 1 2 1 L 10K R35 1 300K Sio4toDY 1 BMCVEG 8 86 R34 61 I 4121 12 1 pnm ADD gt
67. 87 88 inputs on DRAM bank pairs 7 6 5 4 3 2 and 1 0 respectively oss sew oS Dow n seo CA3 ADV 71 CACHE ADDRESS 3 Cache Data RAM address bits used for cache burst sequencing with asynchronous SRAM ADVANCE This active low default output is used with synchronous SRAM to advance the internal SRAM burst counter controlling burst accesses after the address is loaded CA4 ADSC CACHE ADDRESS 4 Cache Data RAM address bits used for cache burst sequencing with asynchronous SRAM ADDRESS STATUS _ONTR gt LLER This active low default output is used with synchronous SRAM and interrupts any ongoing SRAM burst causing a new address to be registered o Cache data RAM chip enable CHITM 6 10 SeeTAGD1I COE 81 CACHE OUTPUT Cache Data RAM output enable Table 2 2 V1 LS Pin Descriptions continued Deseription CWE 7 0 72 77 CACHE WRITE ENABLE 7 0 Cache data RAM byte write 79 80 enables 28 jo L2 CLOCK Clock output to synchronous cache data RAM MATCH ST See TAGDO NALE 59 NEXT ADDRESS LATCH ENABLE When not using synchronous SRAM this output controls an external latch for the cache addresses necessary for pipelining SONY_KEN See TAGD2 TAGCS 82 0 SELECT TAG Data RAM chip select TAGDO 67 TAG RAM Data Bit 0 Used to c
68. CL PD6730 Write Enable This output goes active low to indicate a memory write from the CL PD6730 to the PC Card socket Read This output goes active low for reads from the socket to the CL PD6730 UO Write This output goes active low for writes from the CL PD6730 to the socket Write Protect UO Is 16 Bit In Memory Card Interface mode this input is interpreted as the status of the write protect switch on the PC Card In I O Card Interface mode this input indicates the size of the I O data at the current address on the PC Card Table 2 14 Input Acknowledge The INPACK function is not applicable in PCI bus environments However for compatibility with other Cirrus Logic products this pin should be connected to the PC Card socket s INPACK pin Ready Interrupt Request In Memory Card Interface mode this input indicates to the CL PD6730 that the card is either ready or busy INPACK RDY IREQ WAIT CD 2 1 CE 2 1 RESET indicates a card interrupt request Wait This input indicates a request by the card to the CL PD6730 to delay the cycle in progress until this signal is deasserted Card Detect These inputs indicate to the CL PD6730 that a card is in the socket They are internally pulled high to the voltage of the 5V power pin Card Enable These outputs are driven low by the CL PD6730 during card access cycles to control byte word card access CE1 en
69. Devices zero clocked Since the remainder of the devices video CPU IDE controller ISA bus 87336 s devices serial and floppy are by design static devices their lowest power states are achieved by removing the clock to the device The very act of going into a suspend to memory means that the enable pin to the clock generator chip is deasserted removing all but the 32 kHz signal from the board This excludes however the clocks dedicated to the internal modem They will remained powered and oscillating For suspend to disk all devices are read saved to local memory and the local memory video memory are saved to a disk file which is created by SLEEP MANAGER utility The machine is then commanded to an off state Resume events for zero volt suspend suspend to disk The only resume event for zero volt suspend is the raising of the lid of the computer This electronically enables the power to the rest of the machine Resume events for static suspend suspend to memory 1 Resume on modem ring This is set in BIOS Setup in the power management section Enabling of this field to any ring count will disable the suspend to function except for battery very low 2 Resume on schedule In BIOS Setup this time field can be enabled then set to any value lt is possible to set it for a date and time in the past In this case the unit will resume at the next occurrence of the specified time date ignorant If a proper future date is spec
70. French Z keyboard German Memory amp CPU amp LCD lt OMB No CPU 11 3 STN SVGA Hitachi 9930 OMB No CPU 11 3 STN SVGA Sanyo FH53 16MB P54CSLM 120 11 3 STN SVGA Hitachi 9930 16MB P54CSLM 120 11 3 STN SVGA Sanyo FH53 16MB P54CSLM 133 11 3 STN SVGA Hitachi 9930 16MB P54CSLM 133 11 3 STN SVGA Sanyo FH53 16MB P54CSLM 150 11 3 STN SVGA Hitachi 9930 16MB P54CSLM 133 11 3 STN SVGA Hitachi 9930 Bulk Pack 16 No CPU 11 3 STN SVGA Sanyo FH53 Bulk Pack 16MB P54CSLM 133 11 3 STN SVGA Hitachi 9930 Generic Panel 076 16MB P54CSLM 133 11 3 STN SVGA Hitachi 9930 Generic Panel 050 HDD amp FDD amp CD ROM amp Fax Modem TopUPoocsom o No HDD FDD No CD ROM No Fax Modem No HDD FDD No CD ROM Fax Modem 1 0GB HDD FDD CD ROM No Fax Modem 1 0GB HDD FDD CD ROM Fax Modem 1 2GB HDD FDD CD ROM No Fax Modem 1 2GB HDD FDD CD ROM Fax Modem 1 35GB HDD FDD CD ROM No Fax Modem 1 35GB HDD FDD CD ROM Fax Modem 1 35GB HDD No FDD CD ROM Fax Modem 1 35GB HDD FDD No CD ROM Fax Modem 2 0GB HDD FDD CD ROM No Fax Modem 2 0GB HDD FDD CD ROM Fax Modem A 2 970CX X Y Z 970CX Keyboard Language Version gt Swiss US H Hebrew US 110V Italian US 220V J Japanese US w o power cord K Korean US K B w o power cord ACLA N Norwegian US
71. GND 31 32 GND PIS D7 129 130 PT D6 PNSW 3 GND 127 129 128 GND PT3 DP3 35 8 36 PI 01 COREVCC v5 10210 COREVCC PTS D33 7 5 35 30 oz 05 2555 PT3 DA PT3 D 121 1 PT3 D GND 4 8 2 GND GND 19 011 Eb 2 GND 43 COREVCC 17 118 COREVCC PT3 D37 45 46 PT3 D36 R141 PT3 Di 115 7 HH 116 PT3 00 D40 4 14 8 3 PIS PNSW Mic He M GND 3 DPENF t PSW 3 28 19 C PT3 DE 5 18 36 PTs Dn PTET PTS GND T GND 58 80 PT as COREVCC 18 REV PSNSW 2 pee E 9 63 amp 16 THER CPU 98 PASTURE 6 6 66 x LS Ps Dsi 190 COREVGG 8 8 REV ND 71 72 ND J 90 8 GND E 8 GND lt 4 x 5 76 x is 16 IEEE n 78 PENT 84 lt D56 79 80 8i 82 GND 8 s 8 Fe 6 PT3 GND 5 m GND PTS INTR 6 mmm 7 17 _ PT 060 APT PTS 07 25 B PIS RE Fis D62 85 a GND D COND 92 70 OEV PSNSW 8 2 PTS 23 8 8 8 24 DP 9 36 ADS 6 15 8 5 PT A6 97 98 9v S 1 amp LS GND x 5 95 4 8 6 5 ND 01 102 GND PT3
72. GPOO 57 Output that is set low by external reset and thereafter controlled by bit O of port 2x7H Available to system software for power management or other applications GPO1 85 Output that is set high by external reset and thereafter controlled by bit 1 of port 2x7H Available to system software for power management or other applications MSI 56 MIDI serial input Schmitt trigger input with internal pull up resistor GPI 55 Reserved General Purpose Input with internal pull down Currently no function is assigned to this pin and any connection is acceptable RESET Active high reset from ISA bus RSTB 84 Inverted RESET output SCLK 82 Clock selection input 90 Clock from EXTCLK input 1 Clock from crystal connected to pins XI and XO EXTCLK 81 14 32 MHz clock input from ISA bus Duty cycle must be 40 60 No connection if SCLK 1 J j o Optional crystal input No connection if SCLK 0 CE Input with internal pull up Active high chip enable When low all IRQ outputs and DRQ outputs become high impedance and AEN is forced high internally thereby disabling I O activity to from the ESI688 Outputs FMCSB JOYRDB and JOYWRB become inactive high Leave unconnected or connected to VDD for normal operation IORB 73 Jj Active low read strobe from ISA bus IOWB Jj Active low write strobe from ISA bus Table 2 11 ESS1688W Pin Descriptions continued Pin name Number VO Description A0
73. MARZ 4 5 MV MARG SARESS 38 RN 1 8 2 7 MARS 3 6 MARG 1 5 MART SARESS 38 1 8 MARB MAS 2 7 MN 3 6 WARTO MN MATT 4 5 WARTI SARESS 38 P3VSW PADID 2 1 PAD603 1 10 2 3 3 8 MI PADIO 2 1 PAD603 MM 4 7 5 6 510 100K PA 2 __ MAS MNB R158 1 2 100 MM R157 2 100K MIS 127 1 2 10K PD 2 1 MAS 1627 2 ADJUST CLOCK SKEW 0 1 12 11 gt 12 P3VSW CONFIG SETTINGS 26 CONFIDENTIAL ACER ADVANCED LABS Title PROJECT MARS Size Document Number A DRAM DAMPING RESISTORS AI T MM3 DRMWER 7 MMB MDO 1 R265 100K FOR EDO DRAM 2 DETECTION PR _ 0233 35V C224 10uF 35V P3VR C232 C221 C227 MMB MDO WNE WD VDA MNS MDAT MD2 MD MD26
74. PADS 2 1 PADIT PAD603 INSTALL U28 R28 R98 R102 AND REMOVE PAD2 PAD6 PAD8 PAD11 INSTALL PAD2 PAD6 PAD8 PAD11 AND REMOVE U28 R28 R98 R102 R345 CONFIDENTIAL ACER ADVANCED LABS Title P54C PULL UP PULL DOWN AND CAPS Size Document Number AL T ELI PSVSW ELE 2 GND m 28 160 GND 27 1 2 COREVCC Br 9 Dm COREVC GND 5 13 PT3 DTE e w PD 35 PIED 7 8 153 154 lt a f Gen Sum 8 1 1 2 e AST 41 PT 02 7 18 8 18 18 118 WM PTT DA im 18 Pr 1 cE GND 2 2 GND 012 mw LM Dii ER nmw Tum 9 D gU D28 7 18 08 REV 2 30 ate m
75. Pin Type Name And Function 1 me E 15 Port 4 8 bit quasi bidirectional I O port Alternate functions include CMSRO0 CMSRS5 4 0 4 5 Timer T2 compare and set reset outputs on a match with timer T2 13 14 CMTO 1 P4 6 P4 7 Timer T2 compare and toggle outputs on a match with timer T2 Port 5 8 bit input port ADCO ADC7 P5 0 P5 7 Alternate function Eight input channels to ADC Reset Input to reset the 87C552 It also provides a reset pulse as output when timer T3 overflows Crystal Input 1 Input to the inverting amplifier that forms the oscillator and input to the internal clock generator Receives the external clock signal when an external oscillator is used Crystal Input 2 Output of the inverting amplifier that forms the oscillator Left open circuit when an external clock is used Digital ground Program Store Enable Active low read strobe to external program memory Address Latch Enable Latches the low byte of the address during accesses to external memory It is activated every six oscillator periods During an external data memory access one ALE pulse is skipped ALE can drive up to eight LS TTL inputs and handles CMOS inputs without an external pull up This pin is also the program pulse input PROG during EPROM programming External Access When is held at TTL level high the CPU executes out of the internal program ROM provided the program counter is l
76. SCRW SOCKET STEEL 98 55 46803 021 MEDIO BOARD W O MODEM 970 60 46808 002 ASSY CASE LOWER 050 970 68 87 11242 200 NUT HEX M2 0 4 D NI 100 33 46803 001 BRKET MEDIA BD FIX COPPER 12 34 46839 001 SPRING COVER SWITCH 9710 SUS301 970 40 47 46812 001 RUBBER FOOT 000 970 E 19 20084 011 CONVERTER DC DC T62 036 C 86 14522 140 SCRW MACH PAN 2 141 NI 970 13 86 14553 4R0 SCRW MACH PAN NYLOK 41 186 1 553 8 0 SCRW MACH PAN NYLOK pum M2 5 8L NI 86 1A522 3R0 SCRW MACH PAN M2 3L NI 86 14522 680 SCRW MACH PAN M2 6L NI 14 34 46814 001 LIFTER SHAFT STEEL 970 42 31 46812 001 PLT KEY LOCK REING SUS301 71 60 46822 002 ASSY FDD L CASE 050 970 60 46802 011 ASSY HSINK CEU 970 970 c 56 01051 071 FDD 1 44 3 5 D353F2 31 46817 002 PLT SPRING CPU FIX SUS 970 15 34 46806 002 LIFTER KEYBOARD AL 970 var led aceon 43 34 46811 001 SPRING DOOR CARDBUS 000 3MODE __ 60 46814 011 ASSY LCD PANEL 11 3 970 SUS301 970 a 42 46846 002 CASE UP FDD PC GF 050 970 al 60 46815 011 ASSY LCD BEZEL 11 3 970 17 50 46808 001 CABLE ASSY TOUCH PAD pum 970 qur CARROS 50 46802 001 CABLE ASSY FDD 52 970 5607469 091 HITACHI 11 3 DSTN SVGA 9930 050 970 18 56 17468 001 TOUCHPAD LIED O So ES S 86 1A522 6R0 SCRW MACH PAN M2 6L NI __ 50 46806 001 CABLE ASSY FPC 11 3 HIT 970 SYNAPTIC TM1002SC 970 34 42801 001 STANDOFF HEX M2 5 0 45
77. Synthesizer Line in Microphone CD Voice channel 8 16 bit mono stereo Table 1 23 Audio Specifications IRQ setting auto allocation DMA channel auto allocation 1 5 15 Modem Table 1 24 Modem Specifications Support modem protocol V 34 data modem V 17 fax modem voice audio mode and digital simultaneous voice and data DSVD operation over a dial up telephone line Modem connector type RJ11 Modem connector location 1 5 16 PCMCIA Table 1 25 PCMCIA Specifications ______ ____ Specification Supported card type Type ll Type lll Number of slots Two or one ZV port support MPU 401 is Roland MIDI standard that most of the game software used for audio use 1 5 17 Parallel Port Table 1 26 Parallel Port Specifications ______ ____ Specification Number of parallel ports ECP EPP support Yes by BIOS Setup ECP DMA channel by BIOS Setup DRQ1 or DRQ3 Connector type 25 pin D type Selectable parallel port by BIOS Setup Parallel 1 378h IRQ7 Parallel 2 IRQ7 Parallel 3 278h IRQ5 or Disabled 1 5 18 Serial Port Table 1 27 Serial Port Specifications Selectable serial port by BIOS Setup Serial 1 SF8h IRQ4 or Serial 2 2F8h IRQ3 or Serial SE8h IRQ4 or Serial 4 2E8h IRQ3 or Disabled 1 5 19 Touchpad Table 1 28 Touchpad Specifications Specif
78. Title PROJECT MARS MULTIMEDIA BOARD X5 Sue Document Number MULTIMEDIA BOARD Date May 1 1996 TSheet 1 of REVISION HISTORY 1 MODIFICATIONS FROM X4 TO X5 1 DELETE COMPONENTS C78 0 01uF 10 CAP 2 VALAUE CHANGES R13 20K 5 RESISTOR gt 1 5 RESISTOR 50 10K 5 RESISTOR gt 4 7K 5 RESISTOR 3 ADD COMPONENTS R80 R83 10K 5 RESISTOR R81 R82 15K 5 RESISTOR R84 4 7K 5 RESISTOR R85 R86 150K 5 RESISTOR C137 4700pF 10 CAP C138 0 47uF 10 CAP 0805 ll POPULATED UNPOPULATED PARTS 1 NMG2090 VIDEO CONTROLLER UNPOPULATED PARTS 25 R63 R66 R67 R68 R73 R74 R77 R78 R83 Ota N1 2 NMG2093 VIDEO CONTROLLER POPULATED PARTS U25 0123012401250128 UNPOPULATED PARTS FES SS PST AGATA TS CONFIDENTIAL ACER ADVANCED LABS Title PROJECT MARS MULTIMEDIA BOARD Size Document Number A REVISION HISTORY Date May 23 1996 TSheet 2 612 41214 612
79. When this signal is low the printer automatically line feed after printing each line This is in a tristate condition 10 ns after a 0 is loaded into the corresponding Control Register bit The system should pull this pin high using a 4 7 KO resistor Address Enable When this input is high it disables function selection 15 0 Access during DMA transfer is not affected by this pin EPP Address Strobe This signal is used in EPP mode as address strobe It is an active low signal BADDRO Base Address These bits determine one of the four base addresses BADDR1 from which the Index and Data Registers are offset An internal pull down resistor of 30 KO is on this pin Use a 10 KO resistor to pull this pin to VCC UARTs Baud Output This multi function pin supports the associated serial channel Baud Rate generator output signal if the test mode is selected in the Power and Test Configuration Register and the DLAB bit LCR7 is set After the Master Reset this pin offers the SOUT function Parallel Port Busy This pin is set high by the printer when it cannot accept another character It has a nominal 25 KO pull down resistor attached to it Configuration on Power up These CMOS inputs select 1 of 4 default configurations in which the PC87336 powers up An internal pull down resistor of 30 is on each pin Use a 10 KO resistor to pull these pins to VCC Table 2 10 NS87336VLJ Pin Descriptions continued Prog
80. _ PRSI SARES8 33 VDD JE 8 we 2 1K PULL DOWN LEGACY MODE S D NO PULLDOWN PROG NATIVE OR LEGACY MODE PAD8O3 S 2 VSS L 8 REORIO ONTRHT P3NSW RN29 HD5 D15 1 10 HD5 HDIORBE gri HD5 Did 2 9 HDS 011 B HD5 DT3 3 HDS DIO 4 HD5 Di 1 TADS 09 Ed 3 Sa H4 SARESIO 5 85 M PavsW HD5 05882 E ANG 15 KB5 COBEN O15 90 tou x cu SARES10 10K HDS RDY Ba i YT HD5 CONFIDENTIAL 26 26 i ACER ADVANCED LABS Tile MARS MAN BOARD Sze Document Number F BUS MASTER IDE CONTROLLER Dale May 15 1986 TSheel d 3
81. and timer retriggers _ Power off either or both FDD and CD ROM Tri state FDD and CD ROM interfaces and stop IDE controller clock Timer retriggers The access to 3F2 5 3F7 170 7 376 will retrigger the timer Detective hardware The pin 89 IDECLK of 10643 is tri stated IDE controller clock is change stopped The KB5_CDBEN signal on 1 13 of S3384 UX1 and UX2 IDE interface buffer and pin 13 of S3384 U22 IDE interface buffer are from L to H CD ROM buffer is disabled The pin 30 31 32 CD FDDVCO of CN11 FDD CD connector is from H to L the FDD CD ROM is powered off 1 5 7 2 Component activities in power saving mode Hard disk The hard disk is fully power managed This means that when the hard disk is not in use the hard disk is powered off The following pins are dedicated toward the management of power on the hard disk 1 IDE controller clock enable pin 32 KB5 IDECLKEN of KBC Disabled only when both the HDD and the CD ROM are not in use timed out This pin stops the clock to the IDE controller chip This chip is static and has no internal power down capabilities 2 HDD buffer enable pin 36 KB5_HDDBEN of KBC When the hard disk is powered off the buffer disconnects the off state drive from the still operative controller The buffer is sequenced to disable the interface before the drive is powered down and to re enable the interface after the drive is powered up
82. reset Ems o 9 Reset to OSPRESET osere fo fk ose comet BO IRQ Interrupt Request Connect to DSP_IRQ DI 0 IAClock Connect to CLKIN Table 2 9 R6684 17 Pin Descriptions MDP continued PinName Pin Pin No Descriptions uw o Clock Receiver Mode Connect to THODE woos or 8 Transmitter Mode Coneci to WODE DTE INTERFACE Data Terminal Ready Not used pull up to VCC through 10k n Clear to Send Not used leave open Data Set Ready Not used leave open TXA1 O DF 27 Transmit Analog 1 and 2 The 1 and TXA2 outputs TXA2 NC 26 differential outputs 180 degrees out of phase with each other Each output drive 3000 load TXA2 is not used 23 Receive Analog is single ended receive data input from the telephone line audio interface circuit RINGD 1 Ring Detect The RINGD input is monitored for pulses in the range of 15 Hz to 68 Hz The frequency detection range may be changed by the host in DSP RAM The circuit driving RINGD should be a 4N35 optoisolator or equivalent The circuit driving RINGD should not respond to momentary bursts of ringing less than 125 ms in duration or less than 40 VRMS 15 Hz to 68 Hz across TIP and RING Detected ring signals are reflected on the output signal as well as the bit RLYA 31 Relay A Caller ID Control The MDP RLYA
83. the system boots from floppy drive A A only System boots from floppy drive A If the floppy drive is a non system disk an error message appears System boots from hard disk C If the hard disk is a non system disk an error message appears CD ROM then System boots from a CD ROM disc if one is installed in the CD ROM drive If no disc is C then A present the system boots from the hard disk C If the hard disk is a non system disk then the system boots from floppy drive A 3 6 5 Flash New BIOS Contact your authorized dealer if you need to upgrade your BIOS INTRODUCTION ON FLASH BIOS AND BOOT BLOCK The boot block is used to program and recover the system BIOS when the BIOS is destroyed and cannot perform normal boot It also programs the new BIOS into the flash ROM if the item Flash New BIOS is set to Enabled OPERATING INSTRUCTIONS FOR FLASHING IN A BIOS There are two ways to flash in a new BIOS 1 Hardware Jumper hardware jumper is provided for the BIOS to distinguished from booting from the boot block or doing normal booting see V1 GPIO pin 0 When the jumper is set the boot ROM will first do POST only to initialize the necessary components in the system then read the BIOS binary file from the floppy disk drive FDD to the memory buffer The file is and should be the first file in a DOS formatted 1 44MB diskette If two FDDs are connected to the system the first one is used After the system f
84. 04 0805 8 gt V MODGND MODGND 74VHC4052M MODGND NOK SPRHERD 6 DOWN gt 10 MODVCC CONFIDENTIAL ACER ADVANCED LABS Title PROJECT MARS MULTIMEDIA Size Document Number DSVD Date 23 1996 TSheet of 148 A9 3 m w y P2 15 E ATE B A8 3 Ne om PMS B SMB 3 B m PMS B 15 SEEN 15 uc T B 3 3 Ne E pm AZT E Ne Pe ce B 22 MERET s 5 162 2 NC Bo 16 EAZ 19 3 NG mo e Ova PMS B A23 3 PI2SSTATUSS PMB BATS 3 2 PI3STATUS6 m EE 21 3 PIASTATUS m
85. 10 ns after a 0 is loaded into the corresponding Control Register bit The system should pull high using a 4 7 STEP 40 FDC Step This output signal issues pulses to the disk drive at a Normal Mode software programmable rate to move the head during a seek operation STEP 81 FDC Step This pin gives an additional step signal in PPM Mode PPM Mode when PNF 0 Table 2 10 NS87336VLJ Pin Descriptions continued Pm No Dern TC Terminal Count Control signal from the DMA controller to indicate the termination of a DMA transfer TC is accepted only when FDACK is active TC is active high in PC AT and Model 30 modes and active low in PS 2 mode TRKO 37 FDC Track 0 This input indicates the controller that the head of the Normal Mode selected floppy disk drive is at track zero TRKO 93 FDC Track 0 This pin gives an additional Track 0 signal in PPM PPM Mode Mode when PNF 0 VDDB C 50 99 Power Supply This is the 3 3V 5V supply voltage for the 87336VLJ circuitry VSSB E 42 9 Ground This is the ground for the 87336VLJ circuitry LN 61 E Wait This signal is used in EPP mode by the parallel port ES to extend its access cycle It is an active low signal WDATA FDC Write Data This output is the write precompensated serial data Normal Mode that is written to the selected floppy disk drive Precompensation is software selectable WDATA FDC Write Data This pin provides an additional Write Data
86. 100 240 50 60 2 autosensing AC Extra AC adapter adapter 10 35 10 60 Extra battery pack 58 3WH Lithium lon battery with intelligent charging and built in battery gauge 2 0 hour rapid charge 3 0 hour charge in use 1 4 Jumpers and Connectors Ut CN4 CN6 CN9 CN13 CN14 CN15 CN16 Figure 1 10 CN4 CN6 CN9 CN13 CN14 CN15 CN16 CN10 CN7 d CN5 CN8 CN12 Modem RJ11 phone jack VGA port Mini dock port Parallel port Serial Port PS2 mouse keyboard port AC adapter plug in port CN10 CN7 Multimedia board connector CN11 JFDD CD ROM connector CN12 CN8 board connector CN5 Hard disk drive connector CN3 Speaker out Line out Jack CN2 Microphone in Line in Jack U1 SIR infrared LED Mainboard Jumpers and Connectors Top Side CN20 CN19 SWi CN23 a 080 B CN21 PAD21 PAD19 PAD20 CN20 CN19 DC DC converter connector PAD21 Password set
87. 110V for AAB S Spanish 220V Spanish w o power cord T Thailand Turkish U UK 250V Arabic W Swedish Finnish Chinese X Swiss German Danish Y Swiss French French Z w o keyboard German Memory amp CPU amp LCD Z OMB No CPU 11 8 TFT SVGA Hitachi TX30D 16MB P54CSLM 133 11 8 TFT SVGA Hitachi TX30D 16MB P54CSLM 150 11 8 TFT SVGA Hitachi TX30D 16MB P54CSLM 133 12 1 TFT SVGA IBM ITSV50D 16MB P54CSLM 150 12 1 TFT SVGA IBM ITSV50D 16MB P54CSLM 133 11 8 TFT SVGA Hitachi TX30D Bulk Pack 16MB P54CSLM 133 12 1 TFT SVGA IBM ITSV50D Bulk Pack 16MB P54CSLM 133 11 8 TFT SVGA Hitachi TX30D Generic Panel HDD amp FDD amp CD ROM amp Fax Modem gt No HDD FDD No CD ROM No Fax Modem No HDD FDD No CD ROM Fax Modem 1 0GB HDD FDD CD ROM No Fax Modem 1 0GB HDD FDD CD ROM Fax Modem 1 2GB HDD FDD CD ROM No Fax Modem 1 2GB HDD FDD CD ROM Fax Modem 1 35GB HDD FDD CD ROM No Fax Modem 1 35GB HDD FDD CD ROM Fax Modem 1 35GB HDD No FDD CD ROM Fax Modem 1 35GB HDD FDD No CD ROM Fax Modem 2 0GB HDD FDD CD ROM Fax Modem 2 0GB HDD FDD CD ROM Fax Modem IM CDI ISDN II 86 5A224 4R0 SCRW MACH FLAT M3 4L ZN 4246825001 L HINGE PC 10 GF 050 o 23 42009 001 MICROPHONE 5408 KUC8723 34 46803 001 COVER HDD AL 970 970 42 46819 001
88. 2 4 V3 LS Pin Descriptions ADDRESS ENABLE If AEN is driven high it indicates that the DMA controller has taken control of the CPU address bus and the AT bus command lines AS RTC RTC ADDRESS STROBE This output should be connected to the AS input of an 146818 type or equivalent RTC ATFLOAT 87 This pin is multiplexed with IOCHCK If the ATFLOATH pin function is enabled through register ATCR 2 bit 2 Then driving ATFLOAT low will float the ISA bus This function is to facilitate ISA hot docking design Docking operation details TBD BALE 3 BUFFERED ADDRESS LATCH ENABLE This output is driven to the AT bus where it indicates the presence of a valid address on the bus BSERCLKV3 48 1 Burst bus clock for serial system and power management bus BSER1TOS3 45 Serialized system amp power management information from V1 LS to V3 LS BSER3TO1 46 Serialized system amp power management information from V3 LS to V1 GS CLK14MHZ 1 14 318 MHz clock for the 8254 timer DACK 7 5 3 0 DMA ACKNOWLEDGE 7 5 3 0 DACKn asserted indicates the corresponding DMA channel request n has been granted DRQ 7 5 3 0 DMA REQUEST 7 5 3 0 DRQn asserted indicates DMA device is requesting DMA service using Channel n 48 DS_RTC RTC DATA STROBE This output should be connected to the DS_RTC input of an 14681 8 type or equivalent RTC Table 2 4 V3 LS Pin Descriptions continued GPEX
89. 20 162 TONG 7 DENNC y Be 165 BMOVCC 4 S ee 16 55 UNDOCK REQF 4 3 H 4 Ha fp 16 SM5_UNDOCK p 85 76 PPS 46 45 85 6 1 B6 1524 T B6 4 167 x 4T 7 11 PPS 13 1524 5 7 dS PPS 8 1524 K85 PTRDAT 8 28 89 PPS 18 1524 KB5 PTRCLK 89 GHD 210 170 GHD GHD 50 10 ADO 20 10 Bo ADI 10 Bo PVR EDO ZI An EDT 1627 VSS SUSPENDE St an HI PAR 27 aD 6 lt 155 5 A 82 PNR a 22 MONITOR HS 4 x A4 Bl x AM Bl 175 ND 5 15 PVR mome ANS 85 B5 020 27 M5 88 AD2T 7 4 86 pm PSVR i Z 02 2818 05 S 88 9 NA rg PSVR 00 STB 0 4 T P5VR y 68212223 1 d 18 PERRE 6822 dui 82 ub dE PC3 INTEF 8 5 00 DEVSELF 682122 x 84 31 R5 155 502 86 5 85 D p E 682122 CODED 24 187 3 RST Di 155 SD 67 27 228 B27 165 504 68 B27 28 24 lt 2 Hex A8 BD 105 NSO 31 29
90. 208 205 MD 63 0 204 195 DRAM DATA BUS These pins are dedicated DRAM array data 193 186 pins These pins are inputs during DRAM read cycles and 184 outputs during DRAM write cycles 182 178 176 174 159 157 155 142 140 138 131 AD 31 0 91 94 ADDRESS DATA MULTIPLEXED 31 0 These signals are 97 100 multiplexed on the same pins Each transaction is initiated by a 1012 105 32 bit physical address phase which is followed by one or more 107 data phases These bus transactions support both read and 109 115 write bursts AD 31 0 are also used as IDSELs in the 117 120 Configuration Cycle 122 125 127 130 FRAME FRAME FRAME is driven by the current initiator and indicates the start and duration of the transaction is deasserted to indicate that the initiator is ready to complete the final data phase A transaction may consist of one or more data transfers between the current initiator and the currently addresses target Table 2 3 V2 LS Pin Descriptions PinName Pinno Type BDeserpton PCICLK PCI CLOCK INPUT This is a clock generated by V1 LS and is derived from and delayed by 1 24 clock cycle or is the inversion of LCLK PCIRST 90 PCI RESET This signal is the PCI reset signal ADOE 71 AD BUS OUTPUT ENABLE When this signal is active V2 LS drives the PCI AD bus AD 31 0 ADPAR EVEN B BD 7 0 88 83 81 80 AD BUS PARITY This signal indicates the PCI
91. 27 59 60 PT3 28 PSW 184 111 PTS 29 S 8 9 ps 30 ge _ _____58 5 Ar 108 6 8 D PIER GHD m9 10 me GND PT3 AE 5815 z 5 PT AS eaw GND 0 GND 15 TE oee 6 15 16 PAOD 46 45 46 Hum 18 Dm ZEE 8 8 bee GND 121 121 12 122 GND GND 39 39 4 12 GND 12 2 nm REV J 35 95 TPCHR0 27 128 PROV AU 33 3 BREQ 29 1 130 2 APCHK0 GND 8 5 32 GND GND COREVOG 52 3 2 m COREVOG TA i PI ATS 4 Mois THU 4 x Ei H T S a Hi 4 lt 9 10 2 2 GND ws m GND PT3 9 14 2 7 pa mn is 18 46 6 PT RSTCEU 3 5 M6 7 3 15 16 3 CPUCU m m ca g 1 2 8 A PT3 M9 150 6 12 GND 11 9 Dm GND SCY 2 n Tu 8 GND FREE 153 154 6 7 1 8 G m 5 6 Ha COREVCC 515 i BEAT 157 158 PT3 T BEF 3 4 SS BER 19 010 8 6 COREVCC ip COREVCC JEA JED Bst 691020 TAGS MALE PavsW 70 DES FEMALE 4 PTS DPD LEE C194 0128 CH 1 Tx 35V F WO 35V 22 10 35V TS 10 35V PI
92. 303132 100K 3 2 4 1 1 ato rM Vd 10uF 16V d 16 SVE EH au 5 x AUDOND AUDGND 2 10K AUDGND Us Sio4toDY PER sist I 17 Qn 4 R39 37 PINR 2 3 1 2 4 O tuF 1 ill 10K R194 1 300K 1 2 R38 R193 100K 300K 1 Qt6 16 CDFDPON 2N7002 2 PVR IW J PSVR 9 s PIAR PIAR o oma 1 BMCVCC 8188 5 oe 2 R189 1 fa d 5 mee oi 3 10K 1828 2990 POLYSW Faw ns CONFIDENTIAL 18 SE 5 z 247002 0198 7441592 ACER ADVANCED LABS Title PROJECT MARS Size Document Number POWER MONITOR Dale May 13 1996 TSheet 26 of 16 28 14 16 2326 DCIN DCIN VS5_SUSPEND 20 22 23 26 6 12 22 23 26 28 15 16 22 23 26 28 29 3 6 14 15 16 20 22 23 25 26 28 29 0235 4 AT 16 087 0 1 R323 Tur Y 100K R347 D23 4 5 6 7 8 CORE OVPSNS gt 28 PGND 6 t 2 SHDN 2H Sir 100 514148 1 4 4 eT 2 C236 R294 6
93. 4 Parallel Port Base Address Operation Mode and ECP DMA Channel PARALLEL PORT BASE ADDRESS The Parallel Port Base Address parameter accepts the following values e 378h IRQ 7 3BCh IRQ 7 e 278h IRQ 5 Disabled The default setting is 378h IRQ 7 OPERATION MODE The Operation Mode parameter for the parallel port accepts the following e Standard and Bi directional e Enhanced Parallel Port EPP Extended Capabilities Parallel Port ECP Enhanced Parallel Port EPP provides greater throughput by supporting faster transfer times and a mechanism that allows the host to address peripheral device registers directly Extended Capabilities Port ECP supports a 16 byte FIFO first in first out which can be accessed by host DMA cycles and PIO cycles The default setting is SEandard and Bi directional ECP DMA CHANNEL The ECP DMA Channel parameter lets you set the DMA channel used for ECP mode You are required to set a value for this parameter if you select ECP as your parallel port operation mode It accepts 1 or 3 as its value 3 4 10 Onboard Audio This parameter lets you enable or disable the onboard audio functionality of the notebook This section also includes settings for onboard audio The default setting is Enabled 3 4 10 1 Base Address This parameter accepts the following values 220 240h 250 The default setting is 2405 3 4 10 2 MPU B
94. 595 4 m 155 SAB 155 507 ien 155 155 505 55 5 m 155 916 155 505 us 8 155 SAS 155 501 5 Z ja 155 SAE 155 503 5 p 155 583 155 502 17 18 155 50 ES SDI me G Dm 155 SAT 155 500 i 118 155 SAD 2 1 2 m DEBUG CON FEMALE 17 lt J 67 ________ gt 4813522232931 CONFIDENTIAL ACER ADVANCED LABS Title PROJECT MARS Size Document Number FLASH BIOS A TEL 782223 682223 682223 P3VSW PSVSW AD 0 3T RN33 HOS AD31 n HD5 0015 HD5 015 Y 7 36 X 1 8 090 8 0015 37 905 008 2 7 HD5 014 09 9 38 HD5 0013 3 6 HD5 lt 0018 35 HOS DDT 1 SRN HOS DT AD27 T 80 HD5 0011 1 8 HD5 Di E 12 rv mh 5T 05 0010 2 7 05 010 020 2 HD5 DDS 3 6 HD5 D9 REIHE Ts AD22 1 023 907 05 DD6 2 7 HD5 06 PCS 19 02 008 e4 HO5 DDS 3 amp HD3 05 2 005 65 HDS DX 4 5 HD5 D4
95. 6 1957088 5 NOE TRO 12 7 IM mE MOS lt 1 n ub dM ng NOS 1 MODVCC VS5 aii mows DR 20K 5 RI CONFIDENTIAL H 100K AUF 1 4 10 6 VS 27 ACER ADVANCED LABS PROJECT MARS MULTHIEDIA Sze Document Number POBUS INTERFACE June 6 1996 TSheet d 1 FB3 MODVCC MOOD MODVCC BLM4tPOT FR 3 0 C61 065 4 16V Ei C36 C25 FBI 10uF 16V LM4IP01 4 00 02 79 L15 D 1 MD D4 LT t 7 7 57 1 m 07 031 C26 632 C39 1 8 p fur 16V 0 4 Mif SPKR 23 6 RN T 8 4 voor AVDD
96. 7 155 SAT Bm 1 155 580 5 pm 155 583 16 76 IS SM 216 7 1 155 515 7 155 SAB oe P 1 ESSA m 0 K85 5015 7 65 17 211 8 pg EEJ 22 8 lt S 155 32 5 8 SESS 17 65 5 5 18 KB5 1 PNR 7 5 m p 1 30 90 3 9 55 1551804 28 pn MAG ERG 2 15 9 1 5518010 GE 85 DRO 1 55 DROS zig 1 feiner 3 2 85 ADBI 7 65 DACK 1 P d 100 1 85 10 set 5 2 1 Boa Lm ADB6 1 HOS ENG au d KES ADB7 7 VS5 MODEN 45 1 5 COMGF 41107 ISME RATA ADA MOM B las HE SMS PN5 ROUTE 215 w CL SPRR Ss HP 18 us si 118 m HE 71314 it 112 D 5 113 53 13 1 14 4 Ss 15 OR PSVSW KOUTA 56 16 PSVSW UDGND 4 417 n HE PVR 58 118 PSVSW COR ENS S da HR n 120 P3VSW SAGONM PNR PER gt 51214 PSVR PAR 571213 PavsW NSW gt 345 PASW 345813 4 ACER ADVANCED LABS Title PROJECT MARS MULTIMEDIA Sue Document Number SYSTEMMEDIA BOARD CONNECTOR A Tei P5VR o 5 510 22K KB5 KB5 KB5 KSI7 KBCONN8 KB5 KSO4 KB5 505 KBCONNI6 PSVR 5 k
97. A This active low level sensitive output indicates an interrupt request Table 2 6 NMG2090 Pin Descriptions continued PinName Type Pinno Deseptions Address These signals provide the physical memory or I O address to NMG2 Table 2 6 NMG2090 Pin Descriptions continued PinName Type Pinno Deserptions Data These bi directional 32 bit data bus is used to transfer data during memory and cycle Byte Enable These active low byte enables indicate which bytes of the 32 bit data path are valid This input indicates the memory or I O access currently executing on local bus High level of indicates a memory cycle and a low level indicates an I O cycle Write Read This input indicates the write or read access currently executing on the local bus High level of W R indicates a write cycle and a low level indicates read cycle Table 2 6 NMG2090 Pin Descriptions continued PinName Type Pinno _ Deseptions BLAST Burst Last This input indicates the completion of a burst cycle RESET 84 Reset This active low signal initializes the NM2090to a known state LCLK 71 Local Clock This is a 1X clock with the same phase as 486 type CPU RDYRTN 73 Ready Return This input establishes a handshake between the VESA VL bus master and NMG2 It is used by the local bus controller to generate LRDY LDEV Local Devic
98. ADS 141 lt IRQ4 vss 142 79 lt 805 ems V3 LS 55 man PT86C523 2 VSSCORE 153 68 05 H_PCIRST gt 154 VCCCORE 155 176 Pin y QO 48 4 BSERCLKV3 47 46 BSER3TO1 45 BSER1TO3 O lt 0 SIMILIA 5528 220 8 5 o lt a Figure 2 7 PT86C521 V3 LS Pin Diagram Pin Descriptions This chapter contains a detailed functional description of the pins on V3 LS For ease of reference the pins have been arranged alphabetically within each of the following functional interface groups Interface ISA PCI Interface PCI Power and Ground POWER GROUND The symbol at the end of a signal name indicates that the active or asserted state occurs when the signal is at a low voltage Signal names without the 4 symbol indicate that the signal is active or asserted at the high voltage level The symbol between signal names indicates that the signals are multiplexed and use the same pin for all functions The following conventions indicate the pin type input only pins O output only pins and bidirectional pins pin type is defined relative to the Vesuvius platform For a list of pins arranged by pin name refer to the following table Table
99. If yes set BIOS Setup parameter too default settings or keep the original settings Tests programmable interrupt controller 8259 Initializes system interrupt Enables system shadow RAM e Changes copy SMI Handler ssues 1st software SMI to communicate with PMU e Initializes the SMI environment Initializes interrupt vectors CPU clock checking Sets the DRAM timing in correspondent to the system speed e Scans PCI Devices to Initialize the PCI buffer that used by BIOS solations for PnP ISA Card 4Fh Configurations for PnP ISA Card Initializes the device according to ESCD data if ESCD data is valid Initialize the PCI Devices by BIOS Initialize the PCI VGA card Initializes video display Note If system has any display card here it should be initialized via its ROM or corresponding initialization program e VGA BIOS POST e Enables video shadow RAM Displays Acer or OEM logo if necessary e Displays Acer copyright message if necessary Displays BIOS serial number Memory testing External Cache sizing Enables disables L1 L2 cache according to the BIOS SETUP Tests keyboard interface Note The keyboard LEDs should flash once Table E 1 POST Checkpoint List Enables then checks update cycle Note The HTC executes an update cycle per second When the UIE is set an interrupt IRQ8 occurs after every update cycle and i
100. Interface V1 GS V3 LS Reset and Clock Interface RESET CLOCK Power and Ground POWER GROUND The symbol at the end of a signal name indicates that the active or asserted state occurs when the signal is at a low voltage Signal names without the symbol indicate that the signal is active or asserted at the high voltage level The symbol between signal names indicates that the signals are multiplexed or have dual functionality and use the same pin for all functions The following conventions have been used to describe the pin type input only pins O output only pins and bi directional pins The pin type is defined relative to the Vesuvius platform For a list of pins arranged by pin name refer to the following table Table 2 2 V1 LS Pin Descriptions Pin no Tye ADDRESS 20 This output to the CPU indicates that the CPU should mask A20 in order to emulate the 8086 address wrap around A 28 3 205 198 CPU ADDRESS LINES 28 3 These are address lines that 19 9 together with the byte enable signals BE 7 0 make the address 5 1 bus and define the physical area of memory or I O accessed and 208 206 are driven as outputs during DMA and bus master cycles NOTE CPU s unused pins 31 29 should be pulled down by 1K 4 7K resistors for proper snooping Table 2 2 V1 LS Pin Descriptions continued Pin no ADD
101. PC Card sockets The chip is compliant with PC Card Standard PCMCIA 2 1 and JEIDA 4 1 and is optimized for use in notebook and handheld computers where reduced form factor and low power consumption are critical design objectives The CL PD6730 chip employs energy efficient mixed voltage technology that can reduce system power consumption by over 50 percent The chip also provides a Suspend mode and an automatic Low Power Dynamic mode which stop transactions on the PC Card bus stop internal clock distribution and turn off much of the internal circuitry PC applications typically access PC Cards through the socket card services software interface To assure full compatibility with existing socket card services software and PC Card applications the register set in the CL PD6730 is a superset of the CL PD6729 register set The chip provides fully buffered PC Card interfaces meaning that no external logic is required for buffering signals to from the interface and power consumption can be controlled by limiting signal transitions on the PC Card bus 2 8 1 Features Single chip PC Card host adapter Direct connection to PCI bus and two PC Card sockets e Compliant with PCI 2 1 PC Card Standard and JEIDA 4 1 CL PD672X compatible register set EXCATV compatible Programmable interrupt protocol PCI PC PCI External Hardware or PCUUtay interrupt signaling modes e Serial interface to power control devices Automatic Low Powe
102. PD6730 that the card s internal status has changed Voltage Sense 2 This pin is used in conjunction with VS1 to determine the operating voltage of the card This pin is internally pulled high to the voltage of the 5V power pin This pin connects to PC Card socket pin 57 Voltage Sense 1 This pin is used in conjunction with VS2 to determine the operating voltage of the card This pin is internally pulled high to the voltage of the 5V power pin This pin connects to PC Card socket pin 43 SOCKET Socket Vcc Connect these pins to 117 98 79 200 180 160 _ the Vcc supply of the socket pins 17 60 143 and 51 of the respective PC Card socket These pins can be 0 3 3 or 5 V depending on card presence card type and system configuration The socket interface out puts listed in this table Table 2 2 will operate at the voltage applied to these pins independent of the voltage applied to other CL PD6730 pin groups Table 2 14 CL PD6730 Pin Descriptions continued Description Pin Number Power SPKR_OUT t LED OUT t SCLK SDATA SMBDATA SLATCH SMBCLKt Speaker Output This output can be used as a 128 4 digital output to a speaker to allow a system to support PC Card fax modem voice and audio sound output for the socket whose speaker signal is to be directed from BVD2 SPKR LED to this pin This pin is used for configuration information during
103. Qe 52 e 0 lt SS lt gt lt 25 5 25 lt gt 59 9 5 2 OR 559 x lt gt 50 lt X lt gt lt 5 e 5 5 5552 99 lt lt lt gt 59 X e lt 5 x lt gt lt gt lt gt KX K 52 0 us Removing the Center Hinge Cover Figure 4 6 a lifting up the keyboard b rotating the keyboard to one side and c pulling out the keyboard in the opposite direction Lifting out the keyboard takes three steps 3 to remove the Flip the keyboard over and unplug the keyboard connectors CN4 CN2 8 X 2 y 5 SAN MAAA 5 AW SUR NASA QU 4 N 9 T 5 Unplugging the Keyboard Connectors and Removing the Keyboard Figure 4 8 4 3 Removing or Replacing the CPU Follow these steps to remove the CPU module 1 The CPU module is locked in place by a metal lock which needs to be pulled back and removed before the CPU module can be removed Figure 4 9 Removing the CPU Module Lock 2 Pull up the module using the module handle CN8 CN12 connectors on the CPU module These should match the lt gt When inserting a CPU module take note of the female and male corresponding mal
104. Screw list w 2 514 x2 Figure 4 14 Removing the Hard Disk Drive Bay Cover If you want to install a new hard disk drive reverse the steps described above 4 5 3 Replacing Memory Both memory slots SIMM1 and SIMM2 are accessible after detaching the lower housing from the inside frame assembly You or the user can also upgrade memory via one of the two available memory slots SIMM1 without disassembling the housing accessed by opening the memory upgrade door at the base of the unit Installing Memory Module s Follow these steps to install memory module s 1 Remove the memory module s from its shipping container 2 Align the connector edge of the memory module with the key in the connector Insert the edge of the memory module board into the connector Use a rocking motion to fully insert the module Push downward on each side of the memory module until it snaps in place To remove the memory module release the slot locks found on both ends of the memory slot to release the DIMM Then pull out the memory module 4 5 4 Detaching the Upper Housing from the Inside Assembly Follow these steps 1 Remove three screws in the battery bay Screw list qi 2 514 x3 Figure 4 17 Removing the Battery Bay Screws 2 Turn the unit back over and remove two screws close to the back part of the unit Then snap out the upper part of the housing 1 first from the rear of th
105. Through which determines how the system uses the internal cache The default setting is Write Back 3 4 7 External Cache External cache greatly increases system performance by lessening the load of main memory It is also called L2 level 2 cache The default setting is Enabled 3 4 8 Enhanced IDE Features The Enhanced IDE Features section includes four parameters for optimizing hard disk performance These performance features depend on drive support Newer drives support most or all of these features As much as possible set these parameters to Auto when the Y option to do so is available This allows the notebook to use the hard drive with the highest possible performance level 3 4 8 1 Hard Disk Size gt 504MB If your hard disk size is greater than 504MB and you are operating in a DOS based environment this parameter should be set to DOS Win3 x Win95 If you operate in NetWare UNIX and Windows NT environments set this parameter to Others The default setting is DOS Win3 x Win95 3 4 8 2 Multiple Sectors Read Write This parameter enhances hard disk performance by reading writing more data at once The available values include 9 Auto 16 sectors 8 sectors Disabled The highest value 16 sectors may not give you the best performance every time because hard disks behave differently The default setting Auto allows the system to adjust itself to the optimum read write setting 3
106. Version TIME OF FAILURE INSTALLATION DURING OPERATION OTHERS CMOS SETUP SHADOW RAM BIOS RAM EMS MEMORY SPEED amp CACHE FDD WDD TYPE Date Resolved www s manuals com
107. amp A digital PC speaker input is converted to an analog signal with volume control and is available as an analog output signal Address decode outputs simplify interfacing to a game port Advanced power management features such as Suspend Resume and partial power down are supported The ES1688W AudioDrive is compatible with Sound Blaster PRO version 3 01 voice and music functions as documented in the Sound Blaster Series Developer Kit The ES1688W is pin compatible with the ES688 AudioDrive 2 5 1 Block Diagram DSP Interface FIFO 256 Bvte DMA FIFO Control amp D A ES1688 Control Bus Mixer Analog Interface Reaister Circuit Figure 2 13 ESS1688W Block Diagram 2 5 2 Pin Diagram ESTCLK SCLK RESET RSTB GPO1 FSR FSX DCLK DR DX MSD MCLK SE A10 A11 1 2 4 Figure 2 14 DACKBB DRQB DACKBC lt a a ES1688W AudioDrive ESS1688W Pin Diagram PCSPKO FDXO FDXI AOUTR AOUTL LINER LINEL CMR VREF CINR CINL VDDA REFSEL GNDA MIC AUXAR AUXAL AUXBR AUXBL FOUTR 2 5 3 Pin Descriptions Table 2 11 ESS1688W Pin Descriptions Number vo Description VDDD 3 28 51 Digital Supply Voltage 3 0V to 5 5V 75 20 60 78 GNDD 4 29 52 76 Digital Ground 19 61 77 JOYWRB 54 o Active low decode for joystick write to port 201H JOYRDB 5 Active low decode for joystick read from port 201H
108. and 0 1 pF ceramic in parallel Sleep Connect to DTP SLEEPO Receive Data In Connect to DTP SR41N Transmit Data In Connect to DTP SR30UT 23 Transmitter Mode Connect to MCU RMODE and to DTP TMODE RMODE and 28 29 38 Microphone Analog Input MIC RIN is a single ended microphone input from the audio interface circuit The input impedance is 70140 Receiver Mode Connect to MCU TMODE and to DTP TMODE RMODE and SR1IO CLKIN Connect to DTP IACLK 2 4 2 R6684 17 MDP Modem Data Pump Chip Pin Diagram cost oz o 9 s E GE O o N 586242 49550292929 DGND1 60 READ VDD1 59 F3 RESET 58 DSR RXRQ 57 TXD 56 5 VDD4 D2 55 E3 DGNDS D3 MDP 54 E3 XTCLK Modem Data Pump 2 DGND2 C sib RSO R6684 50 TDCLK 5VA 49 TXDAT AGND1 L 48 EYEXY RIN EYECLK VC EYESYNC VREF L TMODE 2 RMODE O O O e N 00 00 C vt U U UL L U LI LLILILILILILIL xecNGXZCIONDPOODS5Z 2 335265820 595079 5728 L lt 2 gt Figure 2 11 R6684 17 Pin Diagram Pin Descriptions Table 2 9 R6684 17 Pin Descriptions PinName Pin Type Pin No Descriptions XTLI 12 Crystal In and Crystal Out Connect to an external 40 32 XTLO 13 MHz crystal circuit or square wave generator sine wave o
109. by the PWRGOOD signal from the power supply or a reset switch On power up PWRGOOD going from low to high indicates that external VCC is stable and will wake up V1 LS from Standby to On If PWRGOOD goes low it will drive the chip back to Standby RCRST 146 RC RESET This input is used to reset V1 LS power management controller upon initial system power up It should have pull up resistor tied to the same power source as V1 LS RSTDRV lt AT BUS RESET OUTPUT This output provides a system reset SPNDNRST 145 SUSPEND NOT RESET This output provides a reset equivalent to RSTDRV except when in Suspend Mode During Resume SPNDNRST will not pulse so that any device not powered down during Suspend Mode should use this reset NOTE Do not connect thin pin for V1 LS this pin is only applicable to V1 Table 2 2 V1 LS Pin Descriptions continued PinName Type Description 23 137 VCCCPU 3 29 54 78 193 VCCCPU VSSIO 8 25 57 70 86 94 101 107 113 119 153 171 184 2 2 2 PT86C522 V2 LS Data Path Controller Block Diagram CPU Bus Data Path PCI Bus Data Path Write Buffers V1 LS V2 LS Interface DRAM Data Path Configuration Registers Figure 2 4 PT86C522 V2 LS Block Diagram Pin Diagram o 5 g
110. clock when both TRDY and IRDY are sampled asserted During read TRDY indicates that valid data is present on AD 31 0 During a write it indicates the target is prepared to accept data VDD 16 41 67 3V Positive Power Supply Input 91 VSS 15 27 40 Ground Reference Input 54 66 90 2 10 Ambit T62 036 C DC DC Converter This T62 036 C DC DC converter supplies multiple DC BV 3 3V 12V output to system and also supplies the battery charge current 0 3 5A total inputs from the notebook would be limited by the total output of 65 watts maximum 2 10 1 Pin Diagram T62 036 C CN1 CN2 VDCF 1 2 VDCF P12VR 1 2 P12vR VDCF 3 4 VDCF GND 3 9 4 GND GND 5 9 6 GND P3VR 5 9 6 P3VR 7 9 8 P3VR 7 8 P3VR 9 9 10 DCIN GND 9 6 6 10 GND CHARGCL 11 12 CHARGON BMCVCC 11 12 PSVRON CHARGEB 13 14 CHARGSP 13 9 14 Pi2VRON GND 15 16 GND GND 15 9 16 GND CHARGOUT 17 9 18 CHARGOUT P5VRON 17 18 PSVRON CHARGOUT 19 20 CHARGOUT P5VRON 19 9 20 Figure 2 20 T62 036 C Pin Diagram 2 10 2 Pin Descriptions Table 2 16 T62 036 C Pin Descriptions VDCF 1 2 3 4 18VDC input from battery DCIN 7 19VDC input from AC adapter 10 CHARGCL 11 Enables Charger output This input is driven by an ope
111. computer Table 1 3 Hotkey List Descriptions DT Suspend to memory Enters suspend to memory mode an ARM 2 Enters the BIOS Setup utility Allows the system to re configure itself and do self Configuration diagnostics Fn F4 C3 Screen Blackout Blanks the screen to save power To wake up the screen press any key Display Toggle Switches display from LCD to CRT to both LCD and CRT Fn F6 Fuel Gauge On Off Toggles battery gauge display on off Also shows the following e plug icon if a powered AC adapter is connected to the notebook speaker icon if speaker output is on toggled by 7 T icon if turbo mode is on toggled by Fn 2 Speaker Toggles speaker output on and of speaker output on and off Fn F8 Lock System _ notebook security by locking system from access Resources Requires password input to unlock system Table 1 3 Hotkey List Descriptions Icon Fn F9 Accesses the Eject menu See the following subsection Fn Ctrl T a Volume Up Increases audio volume Fn Ctrl L Decreases audio volume Fn Ctrl a Balance Left Shifts speaker balance to the left Fn Ctrl gt Balance Right Shifts speaker balance to the right Brightness Up Increases screen brightness Ea Brightness Down Decreases screen brightness to save power gt Contrast Up Increases screen contrast DSTN only Contrast Down Decreases screen contrast DSTN
112. contains spare parts information Appendix D Schematics This appendix contains the schematic diagrams of the notebook Appendix E BIOS POST Checkpoints This appendix lists all the BIOS POST checkpoints Appendix F Forms This appendix contains standard forms that can help improve customer service Related product information AcerNote 970 User s Manual contains system description and general operating instructions Vesuvius LS Chipset Data Sheets contain information on the system core chips V1 LS V2 LS V3 LS NMG2090 Data Sheet contains detailed information on the NeoMagic VGA controller RCV288Aci SVD Chipset Data Sheet contains detailed information on the Rockwell Modem controller ESS1688W Data Sheet contains detailed information on the ESS audio controller 87C552 Data Sheet contains detailed information on the Philips System Management Controller NS87336VLJ Data Sheet contains detailed information on the NS super I O controller CL PD6730 Data Sheet contains detailed information on the Cirrus Logic PCMCIA controller 10643 Data Sheets contain detailed information on the CMD PCI IDE controller T62 036 C T62 039 and C T62 055 C Data Sheets contain detailed information on the Ambit components M38802 Data Sheet contains detailed information on the Phoenix keyboard controller Conventions The following are the conventions used in this manual Text entered by user Screen messages S etc
113. controller and the power management controller It takes full advantage of the Pentium processor performance by supporting CPU bus frequencies up to 66 MHz By implementing both toggle and linear burst mechanism the V1 LS is armed with the support for Pentium class processors from multiple vendors The integrated 64 bit direct mapped L2 cache controller supports synchronous SRAM external TAG compare for TAG RAMs and both buffered write through and write back cache update schemes for highest performance The DRAM controller implements the logic required to use advanced high speed DRAMs that reduce the performance overhead of the L2 cache miss cycles The V1 LS has the control logic for write buffers in V2 LS to achieve 2 1 1 1 burst writes It implements a synchronous interface between the CPU and PCI buses to exploit the maximum potential of PCI bandwidth The V1 LS supports 64 bit two way set associative write back cache with Sony s Sonyc 2WP The V1 LS supports power management features like SMM SMI Stop Clock and AutoHalt It also features a thermal control mechanism that uses CPU clock throttling to efficiently control the power consumption and heat dissipation associated with the processor The V2 LS data path controller provides a 64 bit data path between the CPU and the main memory a 32 bit data path between the CPU bus and the PCI local bus and a 32 bit data path between the PCI local bus and the main memory The eight level dee
114. drive feature Speed 900KB sec 6X speed Buffer memory 128kbyte Interface Enhanced IDE ATAPI compatible communicate with system via system E IDE channel 2 Applicable disc format Red Book Yellow Book CD ROM XA CD I Bridge Photo CD Video CD CD I CD I Ready CD G and Multi session Photo CD CD EXTRA Loading mechanism Drawer type manual load release Power supply voltage V 1 5 23 Diskette Drive Table 1 32 Diskette Drive Specifications Vendor amp model name Mitsumi D353F2 Internal FDD CD ROM hot swappable No BIOS auto detect external FDD existence Yes External FDD hot swappable Yes 200 209 2HD 2M 04am mde m 6 Data transfer rate Kbits s 250 300 Rotational speed RPM 300 360 Read write heads 2 Encoding method MFM Input Voltage 45V 10 1 5 24 Hard Disk Drive Table 1 33 Hard Disk Drive Specifications Specification Vendor amp Model Name IBM DMCA 21440 IBM DCRA 22160 Spindle speed RPM 4009 4900 Data transfer rate disk buffer Mbytes s 4 9 7 7 6 1 9 8 Data transfer rate host buffer Mbytes s 16 6 mode 4 16 6 max PIO mode 4 Voltage tolerance V 1 5 25 Keyboard Table 1 34 Keyboard Specifications Hem Specification Vendor amp Model Name KAS1901 0111R SMK 51901 0132 SMK KAS1901 0151R English Germ
115. internal 3 3V operation with 3 3V 5V external configuration The General Purpose Pins e 2 pins for 2 separate programmable chip select decoders can be programmed for game port control Plug and Play Compatible e 16bit addressing full programmable e 10 selectable IRQs e 3 selectable DMA Channels e 3SIRQ Inputs allows external devices to mapping IRQs 100 Pin TQFP package PC87336VLJ 2 7 2 Block Diagram Config Serial Serial Interrupt IR Inputs Interface Interrupt Interface P Interface UART Configuration UART IrDA HP Sharp IR Registers 16550 or 16450 16550 or 16450 Floppy Disk Floppy Controller with Drive Digital Data Interface Separator lt 2 i Floppy Drive Enhabced 8477 idis Power Bue Interface MIpose Down Logic SINUM Registers Hifh Current Driver t t Interrupt I O Ports Control vu and Interrupt Data Handshake DMA Figure 2 13 NS87336VLJ Block Diagram 2 7 3 Pin Diagram SOUT1 80UT1 BADDR1 DRATE1 MSENT CSO SRIOI2 SOUT2 BOUT2 CFGOARTX SIN2 IRRX1 DRATEO MSENO RTS2 A14 CTS2 A13 DTR2 A12 Riga VSSE BsR2ARRX2 RQ12 8 80 79 78 77 76 75 74 73 72 T1 70 69 68 67 66 65 64 63 62 61 NI g SINSTEP ASTRG E SLCUANGATE 2
116. is a UART and is contained within the 87366 super I O chip The UART operates off of a 14 Mhz clock The serial port also has a transceiver a MAX211 Therefore there are several steps to the power conservation of the serial port as below 1 Disable the UART1 decode in the 87336 chip 2 Tri state the UART1 output pins 3 Assert the Power Down 46 5 5 of SMC on the MAX211 chip even while in the power down mode if the Resume On Modem Ring The MAX211 chip will still pass through the Ring Indicate signal in BIOS Setup is set to enabled 4 Disable the 14Mhz clock If the floppy and the SIR are also disabled If the 14Mhz is disabled through the 87336 power down mode then all serial and floppy functions will fail Recovery from power down is the opposite procedure SIR UART The SIR port is basically UART The UART operates off of a 14Mhz clock The IR port has a DA converter The UART2 disable control circuit is within the 87336 chip 1 Tri state the UART2 output pins 2 Assert the power down pin pin 39 SM5 IRDAPD of SMC on the DA converter 3 Disable the 14Mhz clock If the floppy and the serial port are also disabled If the 14Mhz is disabled through the National power down mode then all serial and floppy functions will fail Recovery from power down is the opposite procedure Parallel port Since there are no clock operations on the parallel port the requirement to power down this a
117. mode these pins are used for A18 thru A23 PDATA18 LCD 10 3 0 pins are general purpose read only bits which PDATA17 LCD IDO can be used for panel identification During RESET these PDATA16 LCD ID1 LCD pins are inputs The state of these bits are reflected PDATA15 LCD ID2 in register CR2Eh bits3 0 The state of these bit can also be PDATA14 LCD ID3 sampled anytime on the fly through register GR17 bit PDATA13 3 1nternally these pins are pulled up recommended external PDATA12 pull down resistor value is 47k ohm PDATA10 PDATA9 PDATA8 PDATA7 PDATA6 PDATA5 4 PDATA2 PDATA1 PDATAO CRT Vertical Sync This output is the vertical T S synchronization pulse for the CRT monitor CRT Horizontal sync This output is the horizontal T S synchronization pulse for the CRT monitor T S T S RED This DAC analog output drives the CRT interface Analog GREEN This DAC analog output drives the CRT interface BLUE This DAC analog output drives the CRT interface DAC Current Reference This pin is used as a current reference by the internal DAC Please refer to the NM2090system schematics for the external circuit Table 2 6 NMG2090 Pin Descriptions continued Type Descriptions Standby Standby Status1 The direction of the pin is controlled by Status1 GR18 bit 3 In output mode this pin indicates the
118. of 312 312 312 3612 3612 VIDEO OUT L ps ar 2 62 7 2 12 IDEO IN 3 6 L8 GRAGND i s 5 66 13 85 16 12 13 RBS PAND2 17 13 PANDT 59 HSYNC 18 KB5 PANDO 9 X 13 lt SM5 _PWRIEDF Tt 10 7 pn 18 m ell 13 y fg 13 13 y s Q SAC 8 18 BMOVCC F n di SMS ON RES SW 8 5 MCN 8 Jie 12 n 358 12 14 E lis 3 ORD gt 12 i 20 0 1 m 3 4 pm o TROYE ROVE 3 2 DEVSELF A a PELNO lt FRAMES 312 5 18 8 3 PC3 NTB 12 3 219 C BERS S 1 w H 3612 PC3 C a C 3612 1 um Se 5 AD
119. output is OHRC connected to the Caller ID relay DPDT When Caller ID is enabled the modem doses the Off hook relay and asserts this output to switch the Caller ID in order to detect Caller ID information between the first and second rings The RLYA output can directly drive a 5 reed relay coil with a minimum resistance of 360 ohms and having a must operate voltage of no greater than 4 0 Vdc A clamp diode such as a 1 N4148 should be installed across the relay coil An external transistor such as an MPSA20 can be used to drive heavier loads e a electro mechanical relays Table 2 9 R6684 17 Pin Descriptions MDP continued PinName Pin Type Pin No Descriptions RLYB 28 Relay B Voice Control The MDP RLYB output is TALK connected to the Voice relay DPDT In voice mode the modem asserts the this output to switch the handset from the telephone line to a current source to power the handset so it can be used as a microphone and speaker interface to the modem The RLYB output can directly drive a 5 reed relay coil with a minimum resistance of 3600 and having a must operate voltage of no greater than 4 0 Vdc A damp diode such as a 1N4148 should be installed across the relay coil An external transistor such as an 5 20 be used to drive heavier loads e g electro mechanical relays SPKR O DF 29 Modem Speaker Analog Output The SPKR output reflects MSPKR the received a
120. output to SMC P3 2 5 KBDCLK External keyboard clock P3 3 5 PTRCLK External PS 2 clock P3 4 5 KBDDAT External keyboard data P3 5 KB5 PTRDAT External PS 2 data P3 6 5 TOUCHWR Touchpad write P3 7 KB5_TOUCHRD PCOBF IS5_IRQ1 AINO KB5_PANIDO Touchpad read RQ1 ISA data bus IO address select 60h 64h for keyboard input buffer IO address select 60h 64h for keyboard input buffer PCDBO PCDB7 ISS_SDx A0 IS5_SA2 A1 IS5_SA1 CSL VS5_ROMKBCS RDL IS5_IOR O read WAL IS5_IOW 1 VO write KSI 0 7 5 KSI 0 7 KB input scan KSO 0 15 5 KSO 0 15 KB output scan line RST SM5 KBCRST Hold High EAL KB5 KBCXRAM Hold High for internal RAM access Keyboard chip select output Panel ID 0 1 2 and 3 AIN1 KB5_PANID1 ID3 ID2 ID1 ID0 TYPE AIN2 KB5_PANID2 0 0 0 0 TFT AIN3 KB5_PANID3 0 0 0 1 DSTN LOADREN ADB 0 7 5 ADB 0 7 Hold Low External address bus Table 1 11 GPIO Port Definition Map Go Description P0 3 SM5_P5VRON Enable 5V and 3V power SM5 0 4 V85 SUSPEND Suspend control to V1 LS P0 5 5 5 PWRLED4 Power LED 0 Reset CD ROM 1 Power down the serial port buffer P3 4 SM5 LIDSW LS 1 Power of the flash ROM BIOS Table 1 11 GPIO Port Definition Map Beim P4 2 PC3_DKREQ Dock request from docking sta
121. packaged in a 100 pin PQFP 6693 As a data modem the modem operates at line speeds to 28800 bps Error correction V 42 MNP 2 4 and data compression V 42 bis MNP 5 maximize data transfer integrity and boost average data throughput up to 115 2 kbps Non error correcting mode is also supported The modem performs error correction and data compression ECC in the modem using 32k bytes of external RAM ECC increases data throughput typically by a factor of four As a fax modem the modem supports Group 3 send and receive rates up to 14400 bps and supports T 30 protocol In voice mode enhanced ADPCM coding and decoding supports efficient digital storage of voice using 2 bit or 4 bit compression and decompression at 7200 bps Voice mode also supports business audio and the Integrated Communications System ICS program These features support applications such as digital answering machine voice annotation and audio file play record In DSVD mode the DigiTalk coprocessor DTP provides advanced speech compression technology for use in digital simultaneous voice and data Digital SVD or DSVD systems DSVD handset echo cancellation supports handset use through a hybrid Half duplex speakerphone HDSP or headset use is also supported in DSVD mode Full duplex speakerphone FDSP mode also uses the DigiTalk coprocessor Features Data modem throughput up to 115 2 kbps e V 34 V 32 bis V 32 V 22 bis V 22A B V 23 and V 21 Be
122. passwords are present the notebook prompts for the user or supervisor password during system boot up and resume from suspend The supervisor password also gives full access to Setup The user password give limited access to Setup setting the user password lt gt Setup requires the supervisor password to be set prior to If you enter Setup using the user password you cannot modify the supervisor password and certain BIOS settings SETTING A PASSWORD To set a password 1 Select the desired password Supervisor or User to set or edit and press or The password prompt a key appears C 2 Enter a password The password may consist of up to eight characters which do not appear on the screen when you type them After typing your password press Enter Another password prompt appears a 3 Retype your password and press Enter to verify your first entry After setting a password the notebook sets this parameter to Present The next time you boot the notebook resume from suspend mode run the Setup utility or unlock system resources the password prompt appears Key in the appropriate password Supervisor or User The system asks for your password input until you enter the correct password If you forget your password you must reset the configuration values stored in CMOS to defaults Resetting CMOS requires opening up the system unit so contact your dealer for assistance REMOVING A PASSWORD If you enter
123. s K5 and M1 64 bit processors e Supports all 3 0v processors with speeds up to 100 MHz Supports processor bus frequencies of 50 60 and 66 MHz Native PCI Local Bus architecture with direct connection to the Pentium processor bus Vesuvius LS Ideally suited for entry level to midrange portable systems and energy efficient desktop computers Supports L1 level 1 write back or write through cache protocols e Space efficient two 208 and one 176 pin TQFP packages 0 6 um CMOS technology 10096 IBM AT compatible PicoPower s exclusive Power on Demand 3 Best of class power and thermal management e Employs PicoPowers patented Power on Demand technologies to achieve superior power efficiency Active power management cuts power consumption even when the system is in use Passive power management cuts power consumption when the system is idle Supports SMM system management mode SMI system management interrupt Stop Clock and AutoHalt Flexible hybrid voltage implementation Optional thermal control with thermal clock throttling User programmable power setting 10 percent granularity Deep Sleep and Suspend to Disk modes Supports wake control interrupt as wake source and ring output as wake source External activity detection Status indicator Supports 3 3 V processor bus 3 3V 5 V PCI bus 5 V ISA bus 3 3V L2 cache controller and 3 3V 5 V DRAM subsystem Supports both tog
124. state of standby mode The state of this pin is reflected in reg CR25 bit 5 and be used as a status pin Suspend Suspend This pin can be configured as control Suspend input or status Suspend output The active high input mode is used for controlling hardware Suspend When asserted NM2090is forced into suspend mode where all the inputs are disabled and chip goes into the low power mode NM2090will come out of suspend only by de asserting this pin During output mode this pin will indicate the software Activitv Activity Address 25 The direction of this pin is controlled by A25 GR10C bit 7 This pin when in input mode and asserted indicates the system activity A high on this pin can be used to reset internal timers When in output mode it will indicate chip activity to the system Address line 25 in VL Bus mode GR12 bit 1 enables disables the Address 25 decoding Real Time Clock 32KhzlStatus2 This pin is used to feed 32 kHz from an external source It is used to generate the refresh timing for the internal display memory during Standby and software Suspend modes 14 MHz can be used to generate the memory refresh timing in above modes General purpose Status bit 3 can be read from reg CR27 bit 0 RTC32K Status2 Pixel Data 7 0 VAFC pixel data bi directional pins The direction of these pins are controlled ENVIDEO These data pins connect to NM2090from the VAFC compatible interface EVIDEO Enable External Video Data Thi
125. to ISA Controller 2090 Video LCD controller RCV288Aci SVD Modem Chipset Rockwell R6723 12 MCU Microcomputer Chip R6684 17 MDP Modem Data Pump Chip R6693 14 DTP DigiTalk Processor Chip senes Mangement Controller PCIO643 CMD Tech PCI local bus E IDE controller 62 036 00 DC DC Converter T62 039 C 00 Ambit DC AC Inverter T62 055 C 00 2 2 PicoPower Vesuvius LS Chipset The VESUVIUS platform is a high performance highly integrated system solution for IBM AT compatible computers offering universal support for Intel s 3 3 V Pentium processor and comparable 64 bit processors from AMD and Cyrix Based on a PCI Local Bus native architecture it offers a superior power efficient solution for both desktop and portable computers VESUVIUS is a native PCI system controller solution for the 3 3 V 75 90 MHz and 100 MHz Pentium processors from Intel It connects the Pentium processor bus to the industry standard PCI Local Bus and provides a bridge between the PCI and ISA busses to support popular ISA bus peripherals The VESUVIUS platform supports a full product line by offering different options to implement the second level cache and the DPAM subsystems The VESUVIUS system solution also supports a cacheless system configuration by providing a sophisticated DRAM controller that supports leading edge DRAM technology The V1 LS and V2 LS provide a native PCI interface to the Pentium processor bus along with a
126. whether the display is always on or not When enabled the screen will not blank The default setting is Disabled to save power 3 5 4 Internal Speaker This parameter lets you turn the internal speaker on and off The default setting is Enabled You can also do this by pressing the speaker on off toggle hot key Fn F7 Pressing this hot key changes this parameter setting in Setup 3 5 5 External Mouse Location This parameter lets you specify the location of your mouse or similar pointing device Four settings are available for this parameter 2 1 ps 2 Since the touchpad is a PS 2 compatible device the default setting is PS 2 If you connect external PS 2 mouse or similar pointing device you do not need to change the setting however you want to use an external serial mouse change this parameter setting accordingly 3 5 6 Internal Modem For models with an internal modem set this parameter to Power On when you are using the internal modem you are not actively using the internal modem you can set this parameter to Power Off 10 conserve power The default setting is Power On 3 5 7 Resume On Modem Ring You can set the notebook to resume from suspend to memory mode upon detection of a specific number of modem rings ranging from 1 to 7 Enabling this option overrides the suspend to disk function 3 5 8 Resume On Schedule When enabled the notebook resumes from suspend to memor
127. 0 Move Highlight Bar lt gt Change Setting PgDn PgUp Move Screen Fl Help Esc Exit Press T to move from one parameter to another and or gt to change parameter settings Most of the parameters are self explanatory but you can press F1 to get help on the selected parameter Press Esc to exit the screen and return to the main menu 3 4 1 Date and Time The current date is in MM DD YYYY format The current time is in HH MM SS format The system uses a 24 hour clock which means for example that 6 25 50 PM appears as 18 25 50 3 4 2 Diskette Drives The default setting for Diskette Drive A is 1 44 MB 3 5 inch and refers to the floppy drive whether it is installed in the module bay or connected externally via the parallel port Diskette Drive B by default is set to None and is only enabled if two floppy drives are connected to the notebook 3 4 3 Hard Disks The Hard Disk 0 parameter is reserved for the hard disk With this parameter set to Auto the BIOS automatically detects the hard disk parameters and displays the formatted capacity in the parentheses right after the Hard Disk 0 parameter heading It also displays the cylinder head and sector values of the hard disk Advanced hard disk settings are auto configured by Setup for optimum drive performance You can also choose to key in the drive parameters by setting Hard Disk to User To determine your drive parameters check the data fou
128. 0 nam E 00 31 1 CONRAD F CONFIDENTIAL PPS R278 1348 PORT Uk 555008 2 ACER ADVANCED LABS Tie PROJECT MARS Sus Document Number DOCKING CONNECTOR es 1523 1523 1523 1523 2223 2223 26 26 22 22 22 22 2 22 PSVSW 9298 32 1 1 1 8330 AK 2 fe POLYSW 11 KB5 PITRON 4 BB KB5 ea 0252 FBI7 1000 1000 9 4 KES KEDCIK 4 HE 1 RES KEDDAT 2 1 3 8 249 C248 1 1000pF 1000 T 0 TED FB2 FB 282 GRA i FB3 FB 2R2J 2 FB4 FB 282 GRA BLUF 3 MONITOR T R1111 2 IK CCD2BDR 19 lt CPA 5 FB5 HSYNCF as FGRA VERG FB7 VSYNCF R1081 2 K GRA CCD2BCR lo VIDEO CON GRAGND CONFIDENTIAL ACER ADVANCED LABS Title PROJECT MARS Size Document Number CONNECTOR FOR KEYBOARD MASTER LL TEL ELI 6 55 RSTDRI 55 SUSPEND 516 P5VR
129. 020 2 1 i mm HOS ADI7 29 08 002 73 HDD 3 amp HD5 01 07 001 HOS 000 4 5 HD5 DO ADIS 28 33 05 75 05 HDIROR 1__ 8 ADI3 06 76 7 7 HD5 m ur 31 09 87 06 3 6 HD5 HDDACKEF C READ 84 HD5 HDDROR 4 5 HD5 HDDROE D ADS 35 09 DOR 57 HDS HDICRRE 3 6 HDIOREF R229 C REA a 8 DIORA 88 4 5 HD5_HDIOWB R232 10K CSE 100K C ADI 8 fs 054 HE ooo as AD3 46 60 HD5 CDDRQ HD5 CDDRQ 7 AD2 a ie x ADI POMODE P 1 B n o ENDE 85 220 77 1 8 3 TEST 85 HD5 CDIRQ PCT C BERT 1 8 3 omo 9 HECORQ 17 C 3 6 5 155180148 R24 1 20 155 8014 4 5 5 noe 83 155 RB 270 155 Rats 155 RO C 1015 J J 5 ROT 8 TRAVES W ruler 6 upsam TN TE EH p DSA2 HD ARI 2 7 0 1 POS OYE mu OSAI x 1 HDS HDS 17 POS DESEE DEVSEL 0540 x 17 g Sio n CDIORBE PERR PERR 2NDIOR ADM 78 2 7 HD5 CDIOWBF O o PR 16 i E REOR 6 1 IDSEL H PCS_GNTHD 6 6 PC3 PCIRST 10 RESET Her RN2B 3 CKEIDECLK
130. 090 Video Controller The NM2090 is a high performance Flat Panel Video Accelerator that integrates in one single chip High Speed DRAM 24 bit true color RAMDAC Graphics Video Accelerator Dual clock synthesizer and a high speed glueless 32 bit PCI and VL bus interface By integrating the display DRAM and 128 bit graphics video accelerator the NM2090 achieves the highest performance of any notebook graphics controller Delivering over 400MB s of bandwidth the NM2090 has sufficient bandwidth to perform full screen 30fps video acceleration of MPEG Indeo Cinepak and other video playback CODECs The bandwidth headroom also allows the NM2090 to deliver the highest quality video playback of any notebook graphics solution without compromising simultaneous graphics performance The unique integration of the NM2090also allows the NM2090to consume 70 less power than equivalent video solutions with fewer chips and less board space The NM2090 Accelerated Super VGA Flat Panel Controller is the solution for the ultimate design goals of mobile computers providing the highest performance lowest power consumption and the smallest PCB footprint This is accomplished by integrating the display controller logic and display memory into one chip and allows system designers to meet all their design goals without having to make any compromises between power and performance A wide variety of LCD panels are supported including SVGA 800x600 at 64K colors in a s
131. 0pF HD5 CDD5 p HDSELICDDG 5 PI5C3384A m 51 i 16 CDRSTE 52 SCONES HDO 3 2 copio FDDICD PORT 05 4 10 w s HD5 09 B _ HD5 D6 E HD5 18 Tea 89 ig HD5 07 H Hr HD5 A0 7 85 HDS AT 8 8 ig DeNSELCDAT 2 2 M 87 20 CF5DSKCHGCDA2 HD5 RDY ue 88 3WCDRDY PavsW 15 gt 08 3 13 FOS MIRA 3 H GN EDs DANSE H FD5 DSKCH Hes 8 E ean HE 05 55 85 13 FDS HOSEL a HS HD5 HDRST 16 SUE FDRSTE HD5 HDD7 IAS HD5 HDD8 2 5 mx 3 4 HD5 HDD6 AE HD5 HDDS R52 FD5 INDEX me 1 2 K HDD5 HDS RODIO 1 2 1 RB 2 IK HD5 HDD4 i ie HD5 HDD11 CDFDOVCC 12 Ld 24 WP Bj 1 2 IK HD5 HDD3 3 3 HD5 HODIZ 9 RDATAF RAS 2 IK HD5 HDD2 HD5 HODIS F05 DSKCHG 8198 2 JK HD5 HDD m M HD5 HODIZ PECIA HD5 5 21 HD5 HODIS 0 2 21 lt FD HDDRG HD5 HDDRO 2 PNAN HDS 21 05 A 204 21 HDS Hoo 5 26 26 7 2 21 HDS E 2 3 4 CDFDDVOC 21 lt ADR 1 2 3 3 p S M HD5 HDA2 3 HD5 CSH HDDVCC 21 HD5 0680 A 5 HD5 a E Gt mr 1 KB5 CDBEN 1 4 4 HDDVCC Ht Hp 1 R140 t s
132. 1 6 SK 1 2 TAI ZI 100K 1 MODGND 10K 1 TLC2272 OF 10K 1 vw 5 DEUM T 4 y 4 di 04 1 0805 Try A uw Ab PADI MODVCC B Em c PADS 8 MODVCC 5 2 i Q s i 7 TREN 9 Tao 1 2 5 Jour NI 1 1 meds VK 1 4 D re 1 4 7062072 um 1 07 vodo CONFIDENTIAL 8 3 NODGND 470K BASIE BASI T000pF TAHOA 2 R20 100K 1 MODGND ACER ADVANCED LABS Se PROJECT MARS MULTIMEDIA Sze Document Number PARALLEL DAA Dale 25 1086 Sheet 10 VCLINEOUTI gt 10 R35 33K S UNEOUTI 047uF 0805 ve ma 4 15227 029 MODGND 1 R37 4 33 2K 1 0805 MODVCC R39 1 EU 499K 1 0805 3 8 6 XD t E 1 MEN 0 47uF 0805 ve 3 ss 4 0222 MODGND 1 R36 10K 2 ll 47K 4700pF Bx Xt 2 8 SPRR0UTI 3 LS 47K m i X RO NA 9 NSPRR 1 2 4 MODVOC v H m E C138 ey 8 1 5 MUXCRL 19 102272
133. 1 40 1 5 20 ett tt s 1 41 Jes MENO P A 1 41 I MEECDUIO 1 42 1 5 23 Diskette Drive er 1 42 1 5 24 Hard Disk Drive eodeni deer aa 1 43 15 25 Keyboard set tete ete ee ede tete edet 1 43 1 5 26 rennen nsns nennen 1 44 1 5 24 DC DC COnVerter eee 1 44 12520 JDC AG Inverter 1 44 1 5 29 E 1 45 System Block ee ree eee bee bens 1 46 1 6 1 System Functional Block 1 46 1 6 2 System Bus Block 1 47 Environmental 5 1 48 Mechanical 1 49 Chapter 2 Major Chips Description 2 1 2 2 2 3 2 4 Major Component 5 2 1 PicoPower Vesuvius LS Chipset 2 2 2 2 2 1 PT86C521 V1 LS System Controller 2 8 2 2 2 PT86C522 V2 LS Data Path Controller 2 18 2 2 3 PT86C523 V3 LS PCI to ISA Controller 2 22 NM2090 Video Controller aa 2 28 2 8 1 e 2 29 2 3 2 PI eu unu cuc 2 31 2 9 3 Pin L S n SS SS SS SSS nnne nn
134. 10 TST Test mode TST controls MCU access to internal ROM High enables internal ROM This pin has an internal pull up Connect TST to GND NVMCLK oa 9 clock NVMCLK output high enables the NVRAM NVMDATA IA OA 92 NVRAM Data The NVMDATA pin supplies a serial data interface to the NVRAM 0 15 8 15 Address Line 0 15 A0 A15 are the external memory bus 51 58 address lines aie ______ jo AddressLine 16 16 is a bank select line D0 D7 IA OA 99 100 Data line 0 7 D0 D7 an the external memory bus data lines 1 6 READ OA Read Enable READ output low enables data transfer from the selected device to the DSD7 lines Table 2 8 R6723 12 Pin Descriptions continued PinName Pin Pin No WRITE OA 67 Write Enable WRITE output low enables data transfer from the 00 07 lines to the selected device RAMSEL OA 63 RAM Select RAMSEL output low selects the external 32kbyte RAM ROMSEL ROM Select ROMSEL output low selects an external 128k byte ROM or flash ROM ES4 ES4 Select The ES4 output and address line A5 are used by external logic to generate the MDP chip select DPSEL ES4 low and A5 low and the DTP chip select SPSEL ES4 low and A5 high 2 j Host Bus Address Lines 0 2 During a host read or write operation with HCS low 2 select an internal MCU 16550A compatible register HDO HD7 IA OB 74 80 82 Ho
135. 14 023 E 9 86 44453 6RO SCREW MECH M2 5 L6 NYLON 2 CASHI lt gt 20 40 46816 001 INSULATION FOR FPC SY gt 1 21 40 46814 001 LCD FPC 1 22 34 45222 001 COPPER TAPE 270mm 23 42 45270 001 GASKET 717510 10 10 20mm 24 25 D 65 46806 041 LOD 12 1 MODULE ASS Y MODEL NAME Notice Directory 970 LCD 1 MBLY 1 aqa component 2 DRN MATERIAL REV DESCRIPTIO SIGN DATE a DSN TONY HSIAO FINISH 5 050 QTY 1 i m DM N mm SCALE E 9 CKD SHEET 1 1 DO NOT SCALE DRAWING APPD DRAWING NO CD 65 46806 041 1 2 j 4 7 8 9 Appendix Spare Parts This appendix lists the spare parts of the notebook Table C 1 Spare Parts List CONVERTER DC DC T62 036 C 970 19 20084 011 COVER MIDDLE PC 10 GF 050 970 42 46822 001 24 ASSY BTY PACK 10 8V BTP S31 60 46818 011 N MITSUMI A oO o e 7 e 9 23 24 Part numbers are subject to change without notice Contact the Acer spare parts department for updates 2 M
136. 15 the text easy to the eyes Are the illustrations helpful Clarity Design Tone Level Fonts and sizes Illustrations Others Binding method Size and weight Material Overall rating 2 What did you like most about it What would it take to make it better Postage Stamp Here Customer Support Division Acer Incorporated 6F 156 Min Sheng East Road Sec 3 Taipei 105 Taiwan R O C Manual Title AcerNote 970 Service Guide Part No R 49 46811 011 Doc No SG230 9701A Date mm dd yy Sheet Acer Products Incoming Inspection Report Distributor Year Month Major defect M Minor defect m Acceptable A Model Number Test Date mm dd yy Invoice Number Remarks Qty Received Qty Inspected 1 2 m 3 A Model Number Test Date mm dd yy Invoice Number Remarks Qty Received Qty Inspected 1 M 2 m 3 A Model Number Test Date mm dd yy Invoice Number Remarks Qty Received Qty Inspected 1 2 m 3 A Model Number Test Date mm dd yy Invoice Number Remarks Qty Received Qty Inspected 1 2 m 3 A Model Number Test Date mm dd yy Invoice Number Remarks Qty Received Qty Inspected 1 2 m 3 A Date mm dd yy Sheet Acer Products Field Maintenanc
137. 19 SERIAL PORT INTERFACE 20 FLASHBIOS AND DEBUG PORT 21 PCIIDE CONTROLLER 22 MULTHMEDIA BOARD CONNECTOR 23 DOCKING CONNECTOR 24 EXT KBD MOUSE AND VIDEO CONN 25 ISOLATION CIRCUITS amp MISC 26 POWERMONITOR 27 DC DC CONN 8 CPUCORE PWR 28 PWRROUTING MAINBRIDGE BATT 29 RTCCIRCUITS AND BATTERY 30 MICINPUT CIRCUIT 31 AUDIOCODEC 32 SPKROUTPUT CIRCUIT 33 SPAREPARTS PSVR PSVSW 15 FST CK5 FSO 6 6 IITCLKB 6 VSE VDCLKEN 15 KB5 IDECLKEN 1 N 26 R25 10K 2 4 FB8 E FBZ600100 T 0 6 025 A WE 4 PDI saz E 1855 1845 1820 17 EUR 2 5 2M 13 143MHZ 8 eK He 2 100K 100K 100K CPU 2 2 2 Bey R2 1 2 gt 6 19 18 L L zi 3 X320 2 i 4 6 1 M PAD603 R19 xi UG MMESS 1 4 5 1 PSVR 1 2 2 4 8159 1M 0805 zn 5 xn 9 NE 1 4 14318 7 c24 1 2 4 c 818 20K 4 TF 22pF 1 E
138. 2 me NOS t WATE NOS 9 2 9 9 89 NOS DO LEAD 0 10K iea S 00 WO5 DI 10 8 E MENS 4 1173 1 WR 5 10 58 Ux 5 D or NOS 05 ES 5 ie vec E w Ee ROMSELE 30 90 1 NC 5 RST 65 07 READ 1 7 1 amp amp N 47 RESP 67 WAIE OE 8 POR WRITE Ail WATE 9 RIS Net READ 3 a 111002 x TSOP m on _ 9 Nos TE Deer x uta aga E 2 gt xe 0 10 n 11 MOS DO mae 5 Zwe y ba 1 NOS M amp 0 16 Hs oe H see o RU ee 6 m mer 75 9 OS 1173 T0F 16V t lt W 2 5 VREF vec 2 4 n ew MNT Um 2 06 _ 2 OF 16V GNDS E i NDE 8 f 5 GND R672312 1 2 WATE 35 MODVCC 520845 MODVCC R58 R57 10K 5 10K MOS DD EDI 155 18 2 E MOS 16 615550 155 SAT 7858 3 10K 10K 05 E 6155 581 55 547 MI LE Su 6 155 582 15 5 OWE 6 55 5 ORE
139. 23 COMI CONFIDENTIAL ACER ADVANCED LABS Title PROJECT MARS Size Document Number REV SERIAL PORT INTERFACE 30 AL YI AI TEL iz 481315 822 22 31 155 SAD 23 c17 Psw 01 NE smu i 22232627 PINA 2 Ni R221 1 zun MS 100K 155 TJ 65 500 10K 65 SA16 6 165 5 17 PSVSW 3 TE 5 TAALS08 1 1 pe 9 1 8 R115 15 5 10 10K 7 2 7 TAALS32 6 NG 7 HI x 155 0 6 ne 5 ROMCS 2 lu um mer i T 8165 1 MEINE S W PSVSW PSVR 23 28F002BX T 1 R3 100K 40P TSOP utes gt 6 4 165 RONRBCSF TAAHCT125SS 1 3 8 Ut78 TAHCTO4SS Ufa UID T4HCTOASS 16 gt PSH2VSW pa 2 39 155 BIS 312 5 155 SATE 174 4 y 97 155 5415 Sm i s 8 EH 185 6 3 x 155 TOCHROYE 7 34 155 81322 155 IOCHRDY RES ROM 8 i M ES 155 SATT VS5 ROMCSE 2 18 3 155 155 2 D 155 549 155 MEMWE
140. 3 DTE 3 PTT Di7 53 54 PT3 1 2 e IRI 0 2 Sls pe GND 112 M GND CPUCORE 1520 CPUCORE 10K P3VSW 13 13 14 14 P3VSW 10K PT3 147 147 148 148 PT3 015 2 31 5 2 12 145 W0 L ma 1 s pane ME PAD603 GND 2 2 PAD603 PT3 012 m4 m PT3 Dit P3VSW 28 23 P3VSW j 57 3 18 138 1 TDS 88 9 2 1 GND 5 rms GND PT3 D28 27 28 CPUCORE 33 34 CPUCORE EI 3 8 a i GND Etc d Des GND s e Heu 8 PIU 19 PD 3 40 x x 121 12 x 4 2 GND GND 9 11 GND 8 7 A Fb 45 5 S x x TS tis HE x DS lt pi 8 30 GND Miss 8 E GND 1 5 mE 18 dE a 53 LH Ren 1 Prz PEDT wv 1 55 s HIR 10273700 Gm 15 me HE PT3 TUI 1 57 LS Mo LE 5 a GND 6666 8 ru ass a 5 ai E GHD 97 8 GHD PIE SIPGKE 1 e Pre Dae CPUCORE 67 TRUE g b sn 2 2 ayw or 8 GHD ESTEE 120MHZ CPU PT3 053 5 5 T6 Troe sg e 78 PIED 83 84
141. 4 11 Reset PnP 3 12 3 5 Power Saving Options 3 13 3 5 1 When Lid is 3 13 3 5 2 Suspend to Disk on Critical Battery 3 14 3 5 3 Display Always On nen eb eoe pe bae 3 14 3 5 4 Internal 3 14 3 5 5 External Mouse 3 14 3 5 6 Internal RR utet 3 15 3 5 7 Resume On Modem Ring 3 15 3 5 8 Resume On 3 15 3 5 9 Resume Date Resume 3 15 3 6 3 16 3 6 1 Supervisor and User 3 16 3 6 2 Diskette Drive 3 17 3 6 3 Hard Disk Drive 3 18 3 6 4 Start Up 3 18 3 6 5 Flash New 3 18 3 7 Reset to Default e E uus 3 20 Chapter 4 Disassembly and Unit Replacement 4 1 General Informatio 4 2 4 1 1 You Begin incepet cet eee cete eee C etes 4 2 4 1 2 Connector 5 4 3 4 1 3 Disassembly 4 4 4 2 Removing the 4 6 4 3 Removing t
142. 4 24 Removing the LCD Bumpers 2 Remove four screws on the display bezel 5 N N N N N 9 Screw list M2L6 x2 for 11 3 or 11 8 LCD 2 516 x2 for 12 1 LCD M2 5L6 bind head x2 Figure 4 25 Removing the Display Bezel Screws 3 Pull out and remove the display bezel by pulling on the inside of the bezel sides Figure 4 26 Removing the Display Bezel 4 Remove the four display panel screws and unplug the inverter and display panel connectors Then tilt up and remove the display panel Screw list QM2 5L6 bind head x4 Figure 4 27 Removing the Display Panel Screws and the Display Connectors 5 Remove the two display assembly screws and unplug the display cable connector from the display cable assembly Then remove the LCD inverter and ID boards Screw list M2 5L6 bind head x2 DC AC inverter Figure 4 28 Removing the Display Cable Assembly Appendix Model Number Definition This appendix shows the model number definition of the notebook A 1 970C 970C X Y Z me Keyboard Language Version gt Swiss US H Hebrew US 110V Italian US 220V J Japanese US w o power cord K Korean US K B w o power cord ACLA Norwegian US 110V for AAB S Spanish 220V Spanish w o power cord T Thailand Turkish U UK 250V Arabic W Swedish Finnish Chinese X Swiss German Danish Y Swiss French
143. 4 8 3 Advanced PIO Mode Advanced PIO Programmed Input Output Mode enhances drive performance by optimizing the hard disk timing The available values include 9 Auto Mode 0 The default setting is Auto 3 4 8 4 Hard Disk 32 Bit Access This parameter allows your hard disk to perform 32 bit access an increase from the original 16 bit access The available values include 9 Auto Disabled The default setting is Auto 3 4 9 Onboard Communication Ports The Onboard Communication Ports section includes settings for the serial and parallel ports on the notebook The addresses in this screen are all expressed in hexadecimal Resource conflicts are prevented by not allowing you to set the same IRQ and address values for different devices 3 4 9 1 Serial Port Base Address This parameter accepts the following values 3F8h 4 2F8h IRQ 31 3E8h 4 2kE8h IRQ 3 Disabled The default setting is 3F8h IRQ 41 3 4 9 2 IrDA Base Address This parameter accepts the following values 2F8h IRQ 3 Disabled The default setting is 2F8h IRQ 3 3 4 9 3 Modem Base Address and IRQ Setting MODEM BASE ADDRESS This parameter accepts the following values 3E8h 2E8h Disabled The default setting is 3E8h SETTING The IRQ Setting parameter for the modem accepts 3 4 5 7 or 10 as its value The default setting is 10 3 4 9
144. 5 C Pin Descriptions PinName Pin Pin No Descriptions This is the High voltage side of the Lamp The shorter wire to lamp connects to this output T62 039 C T62 055 C Max lamp start voltage Vrms 1200 1300 Typical lamp run voltage G25 C Vrms 520 650 Min open circuit voltage Vrms 1300 1100 Max open circuit voltage Vrms 1600 1500 GND GND 1 6 This the return signal for the input power and control signals and is an extension of the system ground CNTADJ Contrast adjustment reserved DCIN 3 4 5 This is the input DC voltage to supply the operating power Max value 19VDC Min value 7 VDC BRTADJ 7 This is an analog signal in the range of 0 to 3 volts to control the lamp current Vbrite 1 volt Lamp current 5095 1095 of Max Vbrite 3volts Lamp current Max 4 5mA Table 2 17 T62 039 C T62 055 C Pin Descriptions continued PinName Pin Type Pin No PANEL ON A control pin to control on off lamp This input enable the inverter operation Lamp On when high and disables the inverter when low This signal is output from a 3 3V CMOS device Max loading 100uA Logic Low 0 8 volts Max Logic High 21 8 volts Min PWRLED 12 This signal is an open collector sink signal to drive LED1 The LED current is limited by a series resistor of 1 BATTLED 13 This signal is an open collector sink signal to drive LED2 The LED current is limite
145. 5 PT3 A24 206 PT3 A25 211 PT3 A28 212 PT3 29 213 PTS R30 214 PTS AST 285 XM gt e 283 282 PTS BERG 279 278 PT3 277 140 PT3 2 127 PT3 114 PT3 DP2 99 PT3 DP3 54 PT3 DP6 37 PT3 DP7 308 u g A 3 d n 12 3 TERRE FERRE PT3 ADSE PTS 312 B 2 300 PT3 PC 20 P13 PWT 319 CPUCORE CPUCORE P3VSW P3VSW CPUCORE P3VSW PTS PTS PICDO CONFIDENTIAL ACER ADVANCED LABS Tile pear TAD PSVSW J 1 2 GND 159 160 GND PTA VOLTIDS VOLT 3 3 4 1100702 CPUCORE 157 m 1 158 CPUCORE GND 5 6 PT
146. 6 B T Byte Enable bits 0 through 3 These form the host CPU address bus These inputs are active low and specify which bytes are valid for host read write data transfers DMACK1 88 B T This signal normally is used in response to DMARQ1 to either acknowledge that data has been accepted DCHRDY 76 Disk Ready This is an active high input that indicates that the IDE disk drive has completed the current command cycle A 1KQ pull up resistor is recommended DCSO 5 o Disk Chip Select 0 Drive chip select for 1Fx DCS1 56 Disk chip Select 1 Drive chip select for 3F6 DCS2 Disk Select 2 This is used to select the second IDE port command registers in the drive DCS3 79 Disk Select 3 This is used to select the second IDE port auxiliary register Table 2 15 PCIO643 Signal Descriptions continued Signa Pin Type Descrpion DEVSEL 93 S T S Device Select When this signal is actively driven it indicates that the driving device has decoded its address as the target of the current access As an input it indicates to a master whether any device on the bus has been selected TEST1 61 This pin is used with TESTO when PCIMODE 0 to select different DC tests for this chip Primary Disk I O Read An active low output that enables the data to be read from the drive The duration and repetition rate of the DIO cycles is determined by the PCI0643 programming DIOR is driven high when inactive Primary
147. 64 bit L2 cache controller and a 64 and 32 bit mixed mode DRAM controller V3 LS provides a bridge between the PCI and the ISA bus The PCI Local Bus architecture automatically provides Plug and Play functionality for peripheral devices Implemented in 0 6um CMOS technology this platform supports a full range of the Pentium processor bus frequencies from 50 to 66 MHz Synchronous between the CPU and the PCI bus enables superior performance on 25 33 MHz PCI bus VESUVIUS makes best of class performance possible by virtue of its rich feature set advanced architecture and incomparable power management The VESUVIUS system solution offers the highest level of power and thermal management for the Pentium processor systems using PicoPower s patented Power on Demand technology that includes active and passive power management and heat regulation An innovative programming model simplifies the BIOS development task without compromising any power management features The power management control implemented in VESUVIUS goes beyond the standard EnergyStar requirements It offers an excellent time to market system solution for Pentium processor class portable systems The VESUVIUS portable system solution provides all the hooks required to support PCI and ISA hot and warm docking enabling a full featured docking station design The V1 LS chip integrates the CPU bus to the PCI bus interface controller arbiter an L2 cache controller a DRAM
148. 82C57 DMA controllers One 82C54 programmable interval timer Two 82 59 interrupt controllers One 7415612 memory mapper Hidden ISA refresh controller PCI interface controller ISA interface controller Power management interface Architecture Block Diagram The following is the architectural block diagram of the PicoPower Vesuvius chipset with respect to its implementation in this notebook computer Pentium Processor SRAM 3 3V Host Bus MD 63 0 V1 LS V2 LS Interface 3 3V PCI Bus PCI PCI PCI IDE VGA PCMCIA Controller Controller Controller ISA Bus Super I O Keyboard Controller Controller Figure 2 1 Architecture Block Diagram 2 2 1 PT86C521 V1 LS System Controller Block Diagram PCI Bus CPU Bus Interface Interface phe ics 22 Controller DRAM V1 LS V2 LS Controller Interface Reset amp Clock Configuration Interface Registers Figure 2 2 PT86C521 V1 LS Block Diagram Pin Diagram i i 2 8 Eg 53 P Ro Osea nanos 885 1094 5 8858855 88388 LAENE EEEE 884996 888688 58 ANVIEN3 SVN ANd meee
149. 9 1 30 1 31 1 32 1 33 1 34 List of Tables Port Descriptions eee Te dee te eed ede teet 1 4 Indicator Status 1 5 Hotkey List 1 6 Eject Menu Descriptions 1 8 System r 1 9 Mainboard Jumpers Pads Settings Bottom Side 1 18 Memory Address 5 1 21 Interrupt Channel 1 21 VO Address ttr oe tet e ated 1 22 Channel 1 23 GPIO Port Definition etre te te 1 23 PCI Devices 58 1 27 PMU Timers 115 s I 1 28 CPU Specifications 1 35 BIOS Specifications irte peer 1 35 System Memory Specifications 1 36 SIMM memory combination 1 5 7 1 36 Cache Memory 1 37 Video Memory Specification 1 37 Video Display Specification sssri aia 1 37 External CRT Resolution Modes 1 38 LCD Resolution 1 38 Audio Specifications nennen 1 38 Modem 1 39 PCMCIA Specifications 1 39 Parallel Port Speci
150. 9 5 DM WMG MARS 055 Too 004 5 MARG 56 12 104 MART nee 2 Dose NINE WDB 5 0067 NM 0058 MENS 59 00 Hi 132 106 Lu pom an 0061 0062 PAR 095 ys des RESERVE vss RESERVE VSS R289 9 RESERVE VSS 1K 0 RESERVE VSS RESERVE VSS 1 RESERVE vss RESERVE RESERVE VSS mi i VSS 1 vss VSS R288 2 5 ves 1K oT vss VSS VSS 3 DMMP CONFIDENTIAL ACER ADVANCED LABS Title EXPANSION MEMORY SOCKET Size Document Number A PSVSW U24 3 PUE VDD TRI PPS BUSYMATMTRT PPS BUSY DATA PPS 155 wr SICIMGATE PPS SICT E ORE H PPS SLNE 165 AEN AEN 1 PPS INTE 482022 85510 15 RRHDSEL E PP5 AF DSTREDENSE Pes REDE F n Eal A PDOINDEX 84 PES EDO 57 Z 2 z E PD2WP st POSIRDATA PDADSKCHG s PDSMSENO EM
151. 93 MODVCC is from H to L change The pin 25 of U48 MAX211 SM5 SPPD is to L COM2 SIR The 1 of Q5 TP0101T SM5 IRDAPD is from L to H Timer value First phase heuristic time out table for entering HDD standby mode 9sec 9sec 20sec 30sec 40sec 50sec 60sec 70sec 80sec 90sec 2min 4min 5min 30min if AC plugged in Second phase fixed timer for entering HDD suspend mode 9sec System activities System activities and timer retriggers First phase time out heuristic results in hard disk spin down and IDE interface disable The second time out 9 sec results in hard disk power off and IDE controller clock is stopped and its internal HDD buffer disabled Timer retriggers The access to 1 0 7 3F6 will retrigger the timer Detective hardware The pin 89 IDECLK of 10643 is tri stated IDE controller clock is change stopped The KB5 signal on pin 1 13 37 25 of 32XL384 U12 IDE interface buffer and pin 1 of 53384 U22 IDE interface buffer are from L to H HDD buffer is disabled The pin 41 42 of CN5 HDD connector HDDVCO is from H to L HDD is powered off Timer value The system with internal floppy 5sec The system with internal CD ROM 60sec 30min if AC plugged in This parameter is for both internal CD ROM and external floppy Table 1 13 PMU Timers List Lo Wem Deserplions System activities System activities
152. A9 96 100 1 2 Address inputs from ISA bus 5 7 A10 A11 94 95 Address inputs from ISA bus The ES1688W requires these pins to be low for all address decodes These pins have an internal pulldown device enabled when input signal AMODE O In this case they can float ES688 compatible designs CC NNNM Active low address enable from ISA bus D0 D7 10 17 Bi directional data bus These pins have weak pull up devices to prevent these inputs from floating when not driven ENB245 Active low output when ES1688W is being read or written to Intended to be connected to the enable control of an external 74LS245 050 DS1 26 27 Inputs with internal pull down devices These inputs select the DMA channel selected after external reset DRQx DACKBx Recommended ISA DRO DACK No DRQ or DACK DRQA DACKBA DRQO DACKO DRQB DACKBB DRQ1 DACK1 DRQC DACKBC DRQ3 DACK3 DSI 0 and DSO 0 is a special case no DMA request or interrupt request pin is selected after external reset Software configuration of interrupt and DMA channels are required ISO IS1 22 23 Inputs with internal pull down devices These inputs select the default interrupt request pin selected after external reset unless 051 0 and DS0 0 IRQX Recommended ISA IRQ IRQA IRQ9 IRQB IRQ5 IRQC IRQ7 IRQD IRQI0 AMODE 21 Input pin with internal pulldown device If this pin is low then AS0 and ASI act as in the ES688 namely they directly select the base address of the ESI680 1 address ba
153. AD 2 S CSW5 BVCPWREN 4 37 29 P OCMSRO 28 SUE AN 6 i EMS AGN AU LG 200008 4 5 505 THERM CPU 2 2 5 P54ADC4 ouf 27 lt CHARGON Re 74HCTOASS 18 SE PNF Mm 16 23 815 UNDOCK F OF T pracra 2223 ATE Pm 223 SME RST PLSRT2 AEN H 12222328 SMS CIK 22 py esol Ej 12222328 E DATE PLTISDA 15 SEBO E PORO 516 TD 28 SHB DSW 545 8 pam a 30 EM 2223 ON RES SW P3IRDE R148 C245 XI 20 F m ue S 20 F 380552 1525 5 9 TAACTOB R316 R319 SMS 18 1 2 1 FBI5 222128 56K gt Usar T4HCTOASS 2 R320 m hs OF 1 R285 R318 3 1 2 1 816 56K 56K gt 22 598 T4HCTOASS 1 c ow R317 OF 2 314 100K CONFIDENTIAL RC5 ARSTE gt 6 ACER ADVANCED LABS Title PROJECT MARS Sue Document Number SYSTEM MANAGERMENT CONTROLLER LL TEL T
154. AD BUS OUTPUT ENABLE When this signal is active V2 LS drives the PCI AD bus AD 31 0 ADPAR ODD 196 ODD AD BUS PARITY Input from V2 LS to indicate PCI AD Bus parity ADPAR EVEN 197 EVEN AD BUS PARITY Input from V2 LS to indicate PCI AD Bus parity BD 7 0 180 183 I O BURST DATA BUS 7 0 This 8 bit bus carries different 185 188 information during various phases between V1 LS and V2 LS Table 2 2 V1 LS Pin Descriptions continued BDCTL z0 189191 BDCTL 2 0 Data path control signals to V2 LS DECBUF 194 DECREMENT WRITE BUFFER COUNTER This output is used to decrease the pointer on the eight level write buffer INCBUF 192 INCREMENT WRITE BUFFER COUNTER This output is used to increase the pointer on the eight level write buffer PCIMSTR 179 PCI MASTER Indicates to V2 LS that V1 LS is responding to a PCI master cycle V2CLK 2 jo V2 CLOCK Clock for the interface between V1 LS and V2 LS 141 SERIAL BUS Serial bus interface from V1 LS to V3 LS BSER3TO 140 SERIAL BUS Serial bus interface from V3 LS to V1 LS 32KHZCK 147 CLOCK Clock source used for DRAM controller and power management functions CLKIN 138 CLOCK Input clock source to CPU clock CMOS level 50 5 duty cycle is recommended BSERCLKV3 141 CLOCK Clock for the serial interface between V1 LS and V3 LS PWRGOOD 142 POWER GOOD INPUT This input causes a complete system reset It is driven
155. AD Bus parity when V2 LS samples PCI AD Bus AD BUS PARITY Output to V1 LS to indicate PCI AD Bus parity BURST DATA BUS 7 0 This 8 bit bus carries different information during various phases BDCTL 2 0 Datapath control signals from V1 LS DECREMENT WRITE BUFFER COUNTER This input is used to decrease the pointer on the 8 level write buffer BDCTL 2 0 79 77 INCBUF 73 INCREMENT WRITE BUFFER COUNTER This input is used to increase the pointer on the 8 level write buffer PCIMSTR PCI MASTER This output from V1 LS indicates that Vesuvius is responding to a PCI master cycle VCCC 76 185 VCCC VCCCPU 7 28 48 69 158 177 196 VCCCPU 101 121 VSSIO 5 21 39 55 82 95 106 116 GND VSSIO 126 139 156 175 194 2 2 3 PT86C521 V3 LS PCI to ISA Controller Block Diagram Figure 2 6 PCI Bus Interface V1 LS V3 LS Interface Reset amp Clock Interface PT86C521 V3 LS Block Diagram ISA Bus Interface DMA Controller Interrupt Controller Memory Mapper 82C54 Timer Pin Diagram VCCPCI 99 lt H_PCICLK 97 AD27 88 MASTER 87 IOCHCK 86 14MHZCLK 85 VSS 84 lt 4 gt REFRESH gt SPKR VCCPCI 139 2 4 IRAI AD6 140 81
156. ADC5 6 ADC6 7 ADC7 9 P4 2 CMSR2 8 P4 1 CMSR1 7 P4 0 CMSRO 6 EW 5 PWM1 4 PWMO 3 STADC 2 VDD 1 P5 68 P5 67 P5 66 P5 65 P5 64 P5 63 P5 62 P5 61 AVDD 8 C552 00 00 00 0062 0 9 0 gt VUVVVUZZXX lt lt ZVUVUIUVUV COWWWOQOOAANHNONNNNNDA 22200 z ddzm N gt gt gt gt gt 09 Figure 2 16 87C552 Pin Diagram AVSS AVref AVref P0 0 ADO P0 1 AD1 P0 2 AD2 P0 3 AD3 P0 4 AD4 P0 5 AD5 P0 6 AD6 P0 7 AD7 EA VPP ALE PROG PSEN P2 7 A15 P2 6 A14 P2 5 A13 2 6 4 Pin Descriptions Table 2 12 87C552 Pin Descriptions Mnemonic Pin No Type Name And Function 2 Digital Power Supply 5V power supply during normal operation idle and power down mode STADC 3 Start ADC Operation Input starting analog to digital conversion ADC operation can also be started by software PWMOR 4 Pulse Width Modulation Output 0 5 Pulse Width Modulation Output 1 EW Enable Watchdog Timer Enable for T3 watchdog timer and disable power down mode 0 0 0 7 57 50 Port 0 Port 0 is an 8 bit open drain bidirectional I O port Port 0 pins that have 1s written to them float and can be used as high impedance inputs Port 0 is also the multiplexed low order address and data bus during accesses to external program and d
157. ADD ot PAA x S D ADSI 06 PT3 063 87 u 063 FRAME 108 lt P 68223 6 CRZ VPK 3 poicik 6 VS VCK 4 6 PC3 POIRSTE x PCIRST C187 C188 C226 C218 6148 C220 C186 wo 1181 MMB MDO MN 68 mi i2 WB ___ lt 68 ADPAR EVEN 133 6 VS ADPAR 5 ADPAR ODD is 6 VSZ ADEF 1 0 woe TOS ine es 6 VST DECBUF 2 1 DECBUF ters 6 VSS INCBUF INCBUF vo tne io 140 6 153 PCIVSTR 8 POMSIR n mewo 6 voo HS 6 1783 BDCTLI i Bona 16 MN 1 M 1 80 MOIS _ _ _ 5 1 10 35V TOF 35V F uF 16 Bof T 0 182 WTS 1 15 WING 807 12 MOD CONFIDENTIAL lt ACER ADVANCED LABS Tile VESUMUS V Size Document Number A 12 65 AI TEL gt 7212223 PCS AD 0 31 P3VSW
158. ARTS FES SS PST AGATA TS CONFIDENTIAL ACER ADVANCED LABS Title PROJECT MARS MULTIMEDIA BOARD Size Document Number A REVISION HISTORY Date May 23 1996 TSheet 2 Tfhis section shows the media board schematic diagrams of the notebook Schematics Page List Page D2 1 Index Page Page D2 2 Revision History Page D2 3 PCMCIA Controller Page D2 4 PCMCIA Sockets Page D2 5 PCMCIA Socket Power and Interrupt Control Page D2 6 System Media Board Connector Page D2 7 Internal Keyboard and Touchpad Connector Page D2 8 Modem Bus Interface Page D2 9 Modem DSP Interface Page D2 10 Modem Parallel DAA Page D2 11 Modem DSVD Page D2 12 CRT amp LCD Controller Page D2 13 LCD Interface Logics Page D2 14 Isolation Logic and Spare Parts LINK FMD2SCH FMD3SCH FMD4SCH FMD5SCH FMD8SCH FMD7SCH FMD8SCH FMD9SCH FMDIOSCH FMD11 SCH FMDI2SCH FMDI3SCH FMD14 SCH PAGE SYSTEM FUNCTION DESCRIPTION 1 INDEX PAGE 2 REVISION HISTORY 3 PCMCIA CONTROLLER 4 PCMCIA SOCKETS 5 SOCKET PWR amp INT CONTROL 6 SYSTEMMEDIA BOARD CONNECTOR 7 INTERNAL KBD amp TOUCH PAD CONNECTOR PROJECT MARS MULTI MEDIA BOARD PAGE SYSTEM FUNCTION DESCRIPTION 8 MODEMBUS INTERFACE 9 MODEM DSP INTERFACE 10 MODEM PARALLEL DAA 11 MODEM DSVD 12 CRT amp LCD CONTROLLER 18 LCDINTERFACE 100105 14 ISOLATION LOGIC AND SPARE PARTS CONFIDENTIAL ACER ADVANCED LABS
159. ASE EMI SPTH Bb SSREW BINDMAGHM2SISE NI 150 46809 001 C A 80P FPC 12 1 IBM 970 4 46830 001 HINGE R AL 97 SUS301 970 970 34 46830 00 GERAL 970 __ 19 21030 041 INVERTER T62 055 C 970 42 46811 001 KNOB TILT DISABLE ABS 050 40 46806 001 MYLAR LOWER CASE PC 970 ae 60 46814 022 ASSY LCD PANEL 12 1 050 970 970 42 46818 001 DOOR SLIDE PC 10 GF 050 86 4A553 6R0 SCREW BIND MACH M2 5 6L NI B 2 970 Service Guide ACER lt gt L X X gt x mdp a Oo y x D SITI J elo A a 25 WIRE OD p Be G C lt Y lt O U Ca C U elim A zz Z T w DL lt t 1 8 9 91 46801 001 65 46806 00 LCD MODULE ASSEMBLY SANYO 11 3 6 Part No Description Q TY Remark O1 41 46805 002 LCD BEZEL FOR HIT 11 3 1 02 34 47604 00 HO
160. AcerNote 970 Service Guide 4 M QU YN n lt gt N N ANY QAM QAAE NN X tx l UNA EN a V W WAY About this Manual Purpose This service guide contains reference information for the 370 notebook computer It gives the system and peripheral specifications shows how to identify and solve system problems and explains the procedure for removing and replacing system components It also gives information for ordering spare parts Manual Structure This service guide consists of four chapters and seven appendices as follows Chapter 1 Introduction This chapter gives the technical specifications for the notebook and its peripherals Chapter 2 Major Chip Descriptions This chapter lists the major chips used in the notebook and includes pin descriptions and related diagrams of these chips Chapter 3 BIOS Setup Information This chapter includes the system BIOS information focusing on the BIOS setup utility Chapter 4 Disassembly and Unit Replacement This chapter tells how to disassemble the notebook and replace components Appendix A Model Number Definition This appendix lists the model number definition of this notebook model series Appendix B Exploded View Diagram This appendix shows the exploded view diagram of the notebook Appendix C Spare Parts List This appendix
161. C coupled externally to CIN L R in order to remove DC offsets These outputs have internal series resistors of about 5K ohms Capacitors to analog ground on these pins can be used to create a lowpass filter pole that removes switching noise introduced by the switched capacitor filters CINL R 40 41 Capacitive coupled inputs left right These inputs have internal pull up resistors to CMR of approximately 50K ohms VREF 42 Reference generator resistor divider output Should be bypassed to analog ground with 0 1 uf capacitor Buffered reference output Should be bypassed to analog ground with a 47 uf electrolytic capacitor with a 1 uf capacitor in parallel Line level stereo outputs left right Option input Analog GND normal operation Analog VDD reserved AOUT L R 46 47 PCSPKO 50 ___ Analog output of PCSPKI with volume control Normally connected via an internal resistor Can be programmed to connect internal to FOUT R pin during DSP serial mode Input with internal pull up to CMR Alternate input to left channel filter stage in DSP serial mode 2 6 Philips 87C552 System Management Controller The 87 552 Single Chip 8 Bit Microcontroller is manufactured an advanced CMOS process and is a derivative of the 80C51 microcontroller family The 87C552 has the same instruction set as the 80C51 The 87C552 contains 8kx8 a volatile 256x8 read write data memory five 8 bit ports
162. C and SMC 0 Wake by RTC alarm IRQ monitor from docking 0 Ring indicator input VGA activity from VGA controller ACTIVITY pin KBC SMI request Keyboard number lock LED control Keyboard caps lock LED control LED3 KB5 KEYCLICK P1 0 5 FPAGE1 Key click output Force BIOS to high page P1 2 5 IDECLKEN P1 3 KB5 IITCLKEN P1 4 5 SMODE P1 6 5 HDDBEN 1 7 155 IRQ12 P2 0 5 MEMIDAO Local bus IDE PCI clock enable IIT PCI clock enable for video conference 0 3 mode FDD drive 0 Enable CD ROM buffer 1 Enable FDD buffer 0 Enable HDD buffer PS2 mouse IRQ12 Memory IDO and Memory ID1 for SIMM 1 2 1 5 MEMIDA1 0 50nS 1 40nS 0 70nS 1 60nS 1 US version without system power switch 0 Japan version with ON RESUME switch 1 FDD installed P2 2 MODE P2 3 KB5_FDD CD o o P1 1 5 FPAGE2 FPAGE2 FPAGE1 0 0 F EO 0 1 F E1 1 0 F E2 1 1 reserved mM Table 1 11 GPIO Port Definition Map L0 CDROM installed P2 4 5 MDMIDBO Memory IDO and Memory ID1 for SIMM 2 P2 6 KB5_MDMIDB1 IDO ID1 Memory speed 0 0 50 5 0 1 40nS 1 0 70nS 1 1 60 5 2 5 5 PSWD 1 Enable password P2 7 5 1 Enable Acer logo shown on screen while BIOS POST P3 0 5 5 TXD UART serial input from SMC P3 1 SM5 RXD UART serial
163. DOOR I O INS PC ABS 050 970 030839 2 IMVUAFUBBD 29 31 46815 001 SPEAKER NET L SPTH 000 970 33 46802 001 SUPPORTER DOOR SUS 301 47 46803 001 CSN MICROPHONE SILICON 000 970 5602941 001 HDD 2160MB IBM DCRA 22160 30 31 46814 001 SPEAKER NET R SPTH 000 970 970 ATA 42 46824 001 COVER R HINGE PC 10 GF 050 42 46820 001 DOOR PC ABS 050 970 90 50 46801 001 CABLE ASSY FPC 970 5 150 42003 002 CABLE ASSY FPC 44 43MM 970 55 46801 001 MAIN BD W O CPU 970 56 07468 001 12 1 TFT SVGA SV50D SS 32 86 64522 480 SCREW MECH RWH M2 4L NI 42 42948 001 GASKET EMI 71TS4 1 900 19 21030 041 INVERTER T62 055 C 970 86 1A553 4R0 SCRW MACH PAN NYLOK 33 42 46822 001 COVER MIDDLE 10 050 42 46842 011 MYLAR MAIN BOARD PC 970 60 46815 031 ASSY LCD BZL 12 1 050 970 M2 5 4L NI 870 33 46801 001 BRACKET AL 970 40 46805 001 PLATE LOGO 2 PC 050 9710 50 46807 001 CABLE ASSY 24 BTY 970 90 46807 001 84 KEY 51901 111 5 42 429 8 001 GASKET EMI 71T84 1 900 86 44553 680 SCREW BIND MACH 2 5 61 NI 86 1A553 4R0 SCRW MACH NYLOK a SCRW MACHAN ME SENI 64 34 00015 071 SCRW 144 40 4 40 L5 5 47 46802 001 CUSHION BEZEL SILCON 000 M2 5 4L NI 35 34 46805 001 FRAME KEYBOARD SECC 970 NI 970 y 38 67 34 46840 001
164. Disk Write This is an active low output that enables data to be written to the drive The duration and repetition rate of DIOW cycles is determined by 10643 programming DIOWX5 is driven high when inactive Disk Interrupt This pin is an input to the PCIO66 that generates the IRQ14 output DINT is asserted low then high by the drive at the beginning of a block transfer This input should have a external 1KQ resistor and 47pF capacitor pull down connected to it Disk Interrupt Input for the secondary IDE port It is used to generate the IRQ15 output DIRQ2 is asserted low then high by the drive at the beginning of a block transfer This input should have a external 1 resistor and a 47pF capacitor pull down connected to it DMARQO DMA Request 0 This signal is used in a handshake manner with DMACKO and should be asserted high by the primary drive when it is ready to transfer data to or from the host DMARQ1 DMA Request 1 This signal is used in a handshake manner with DMACK1 and should be asserted high by the primary drive when it is ready to transfer data to or from the host DRST Disk Reset This is an active low output which signals the IDE drive s to initialize its control registers DRST is a buffered version of the RESET input and connects directly to the ATA connector DSA2 Disk Address bits from 0 through 2 These are normally DSA1 outputs to the ATA connector for register selection in the DSAO drive s
165. Error Message Problem Description Assigned Product Engineer Comments Date Attachment BIOS Version EnE Version CHARACTERISTICS QUALITY ISSUE SPECIFICATION PERFORMANCE COMPATIBILITY PROBLEM OCCURS ONLY ONCE INTERMITTENTLY CONTINUOUSLY TIME OF FAILURE INSTALLATION DURING OPERATION OTHERS Date Resolved Multiuser Product Problem Report Form Customer Date Issue I D Attachment Model No BIOS Version RAM Size S EnE Version Add On Cards Disk Type amp Capacity Disk Controller A P Name amp Version Other Error Message Problem Description CHARACTERISTICS QUALITY ISSUE SPECIFICATION PERFORMANCE COMPATIBILITY PROBLEM OCCURS ONLY ONCE INTERMITTENTLY CONTINUOUSLY TIME OF FAILURE INSTALLATION DURING OPERATION OTHERS Assigned Product Engineer Date Resolved Comments Customer Issue 1 0 Model No RAM Size Add On Cards Disk Type amp Capacity Disk Controller A P Name amp Version Other Error Message Problem Description Assigned Product Engineer Comments S N S N O S CHARACTERISTICS QUALITY ISSUE SPECIFICATION PERFORMANCE COMPATIBILITY CONNECTIVITY PROBLEM OCCURS ONLY ONCE INTERMITTENTLY CONTINUOUSLY TIME OF FAILURE INSTALLATION DURING OPERATION OTHERS LAN Product Problem Report Form Date Attachment BIOS Version EnE
166. HEET 1 OF 1 DO NOT SCALE DRAWING APPD peer DRAWING CD 65 46806 011 1 2 4 5 6 7 8 9 1 2 5 4 5 6 7 8 9 91 46801 001 65 46806 021 LCD MODULE ASSEMBLY HITACHI 11 8 Q No Part No Description QTY Remark AE O1 41 46803 002 LCD BEZEL FOR HIT 11 8 1 S J 60 46815 002 02 34 47604 00 HOOK SPRING EJ SPG 1 H C 03 42 46829 00 LED LENS FOR POWER 1 S J 2 04 42 46828 00 LCD LATCH 1 S J 05 40 46805 001 ACER LOGO 1 S Y 06 47 46802 00 CUSHION BEZEL 2 P M 07 47 46803 00 CUSHION MICROPHONE P M 08 50 46801 00 FPC LCD HIT 11 8 ADFLEX 09 41 46802 002 LCD PANEL FOR HIT 11 8 S J 10 54 46815 002 EMI SHIELD FOR HIT 11 8 S Y 11 86 4 455 6 SCREW PAN M2 5 L6 NYLON 0 CASHI 12 86 14522 680 SCREW PAN MECH M2 0xL6 2 CASHI 3 31 46813 001 NAME PLATE FOR ACER OUDENSHA 4 56 07355 02 LCD HITACHI 11 8 HITACHI 5 19 20086 001 LCD INVERTER FOR HIT 11 8 AMBIT 6 23 42009 00 MICROPHONE HOSIDEN 7 34 46829 00 HINGE L FOR 970 CEMA 8 34 46830 00 HINGE R FOR 970 CEMA 9 86 44453 6RO SCREW MECH M2 5 L6 NYLON 2 CASHI 20 47 46810 001 CUSHION SPACER A CR 2 S Y 21 40 46814 001 LCD FPC MYALR 1 P M 22 34 45222 001 COPPER TAPE 70mm 23 24 25 65 46806 021 LCD 11 8 MODULE ASS Y MODEL NAME Notice Directory 970 OE emet EE DRN MATERIAL REV DESCRIPTIO SIGN DATE a ee DSN TONY HS
167. I IDE Controller Page D1 22 Media Board Connector Page D1 23 Docking Connector Page D1 24 External Keyboard Mouse and video Connector Page D1 25 Isolation Circuit and Misc Page D1 26 Power Monitor Page D1 27 DC DC Connector and CPU Core Power circuit Page D1 28 Power Routing Main Battery Page D1 29 Circuits and Battery Page D1 30 Microphone Input Circuit Page D1 31 Audio Codec Page D1 32 Speaker Output Circuit Page D1 33 Spare Parts IMARSYS2SCH MARSYS3 SCH MARSYS4SCH MARSYS5 SCH MARSYS6 SCH MARSYS7 SCH MARSYS8 SCH IMARSYS9 SCH MARSYSIOSCH MARSYSt1 SCH MARSYS12SCH IMARSYSI3SCH IMARSYS14SCH IMARSYS15SCH MARSYS16SCH IMARSYSI7SCH IMARSYSI8SCH MARSYSI9SCH MARSYS20 MARSYS21 SCH MARSYS22 SCH MARSYS23 IMARSYS24SCH MARSYS25SCH MARSYS26SCH MARSYS27 SCH MARSYS28 SCH MARSYS29 SCH MARSYS30 SCH MARSYS31 SCH MARSYS32 SCH IMARSYS33SCH PROJECT MARS SYSTEM BOARD PAGE SYSTEM FUNCTION DESCRIPTION 1 INDEXPAGE 2 REVISIONHISTORY 3 CLOCK GENERATOR 4 P54C PULL UP amp DOWN 5 5 MODULE CONNECTORS 6 VESUVIUS Vt 7 VESUVIUS V2 8 VESUVIUS V3 CACHE DATA SRAM LOWER 32 BIT CACHE DATA SRAM UPPER 32 BIT DRAM DAMPING RESISTORS EXPANSION MEMORY SOCKET SUPER IO CONTROLLER Ri INTERFACE LOGIC KEYBOARD CONTROLLER SYSTEM MANAGERMENT CONTROLLER CD FDD AND HDD INTERFACE PAGE SYSTEM FUNCTION DESCRIPTION 18 PARALLEL PORT INTERFACE
168. I and is an input to every PCI device All other PCI signals except RESET and IRQ are sampled on the rising edge of PCICLK and all other timings with respect to this edge PCIGNT 82 PCI Grant This signal indicates to the agent that access to the PCI bus has been granted PCIMODE 2 PCIMode This is et to high when chip is used in PCI bus PERR S T S PCI Request This signal indicates to the arbiter that this agent desires use of the PCI bus Pulsed Error Error may be pulsed active by an agent that detects a parity error PERR can be used by any agent to signal data corruption However on detection of a PERR pulse the central resource may generate a non Maskable interrupt to the host CPU which often implies that the system is unable to continue operation once an error processing is completed Reset This is an active high input that is used to set the internal registers of the 10643 to their initial state is typically the system power on reset signal as distributed on the PCI bus STOP 97 S T S Stop This indicates that the current target is requesting the master to stop the current transaction TESTO 85 TESTO This pin is used with DIOCS16 when PCIMODE 0 to select different DC tests for this chip TRDY S T S Target Ready This indicates that the target agent s ability to complete the current data phase of the transaction TRDY3 is used with IRDY data phase is completed on any
169. IAO FINISH MCS 050 QTY 1 i DIM mm SCALE 1 CKD lsHEET 1 DO NOT SCALE DRAWING APPD Arer medrporated DRAWING NO CD 65 46806 021 7 8 9 1 2 E 4 5 7 8 9 6 91 46801 001 65 46806 041 CD MODULE ASSEMBLY IBMITSVSOD 12 1 6 pu 5 No Part No Description Ory Remark O1 41 46808 002 LCD BEZEL FOR IBM 12 1 1 S J x 60 46815 032 02 34 47604 00 HOOK SPRING EJ SPG 1 H C O3 42 46829 00 LED LENS FOR POWER 1 S l 04 42 46828 00 LCD LATCH 1 S J O5 40 46805 001 ACER LOGO 1 S Y O6 47 46809 00 CUSHION BEZEL 2 P M 07 47 46803 00 CUSHION MICROPHONE P M 08 50 46809 00 FPC LCD IBM 12 1 ADFLEX 09 41 46807 002 LCD PANEL FOR IBM 12 1 S J B 40 46815 001 INSUALTION FOR INVERTER S Y 1 86 44453 6 SCREW PAN M2 5 L6 NYLON 0 CASHI 2 86 1A553 6RO SCREW PAN MECH M2 54L6 2 CASHI 3 31 46813 001 NAME PLATE FOR ACER OUDENSHA 4 56 07468 00 LCD IBM ITSV50D 12 1 HITACHI 5 19 21030 041 LCD INVERTER FOR IBM 12 1 AMBIT 6 25 42009 00 MICROPHONE HOSIDEN 7 34 46829 00 HINGE L FOR 970 CEMA C E 8 34 46830 00 HINGE R FOR 970 CEMA PANEL ASSEMBLY 60 468
170. IDE Channel Enable and DMA Request DAMCKO Acknowledge 0 This signal is used in response to DMARQO to wither acknowledge that data has been accepted or that data is available At power up the state of this signal is used to enable or disable the secondary channel 2NDIOR 77 T O Secondary Channel Disk I O Read This is an active low output which enables data to be read from the drive The duration and repetition rate of DIOR cycles is determined by PCI0643 programming DIOR is driven high when inactive 2NDIOW Secondary Channel Disk I O Write This is an active low output that enables data to be written to the drive The duration and repetition rate of DIOW cycles is determined by 10643 programming DIOW is driven high when inactive AD 31 0 Address and Data Address and data are multiplexed on the same PCI pins A bus transaction consists of an address phase followed by one or more data phases PCI supports both read and write bursts The address phase is the clock cycle in which FRAME is asserted During the address phase AD 31 0 contain a physical address 32 bits For this is a byte address For configuration and memory it is a Dword address During data phases AD 31 24 contain the least significant byte Isb and AD 31 24 contain the most significant byte msb Write data are stable and valid when TRDY is asserted Data are transferred during those clocks where both IRDY and are asserted C BE 3 0 3
171. IT 77 gt A A1 B ANPACK re B A2 q _ 73 B 72 RING GND B BVD2 SPKR LED 71 015 AO 70 mh BVO1 STSCHG RI 69 lt lt gt A Di4 RING 68 4 00 67 a 4 3 013 B D8 66 jm 4 0 A D6 65 4 012 B 09 4 64 pun 4 05 8 02 63 ka P Di B D10 n 62 jen 4 3 A 04 SOCKET 61 few lt A_ CD1 B WP 40I 16 60 SOCKET 02 e INTA 58 AESERVEDS ALOUTANTB ARQ10 t 57 RING GNO SOUTMNTCASLD t 56 ADO SINIKANTD4ASDAT 4 55 um 4 ADI RSTa gt PCI VCC 54 4 AD2 CLKRUN 53 a 4 ADS b b g Spg ant 5 g P 2 8 3 Pin Descriptions Pin signal type annotation The following conventions apply to the pin signals Apound sign at the end of a pin name indicates an active low signal for the PCI bus e A dash at the beginning of a pin name indicates an active low signal for the PC Card bus An asterisk at the end of a pin name indicates an active low signal that is general interface for the CL PD6730 Adouble dagger superscript at the end of the pin name indicates signals that
172. IUS V Sze DocumentNumber 363 t 5 PTS AB 18 lt PT3 032 PT3 052 PT3 053 8 175 1 2 10K pH 1 177 100K P3VSW C167 Jm C146 C133 C129 s T O tul zl O tul O tul O tul et 570 PNSW o Ust 1 1 R178 R176 PT3 7 a Y PDM 20K 20K C FEE S 2 2 16 ME AT 38 32K 32 32 PT AID 5148 99 x 8 J PTS T END PHAS 4 PHAM J PIAS E PHASE 3 AIT 9 52 PT3 00 38 ruota 8271 53 FEDT XL ap 85 mo 6 CH3 0507 THI ADSCH Dj 8 DSP 5g PIS DA CHE ADVE 6 CHE ADF ADVE 7 69 10 THI B o gue 6910 CWERT BW 6940 CHS CWERZ 39 6910 6 CR RITE 9 CHS PT3 1 2
173. M 144P C 316310 1 IC PCI IDE 10643 TQFP U SUPERVISORY MAX708ESA 508 IC CLK GEN MK1438 01RTR SSOP IC AUDIO CHIP ESS1688 PQFP100P IC RTC BQ3285E SSOP 24P IC BUS SWITCH QS32 L384 VSOP48 IC PCI SYS CTRL PT86C521 VQFP IC DATA PATH PT86C522 VQFP208P IC PCI ISA BRI PT86C523 VQFP IC SUPER PC87336VLJ QFP100 IC UCTRL 87C552 8BIT PLCC 68P IC EPROM 28F002BX T 2M SRAM KM732V588 32K 32 PQFP IC SRAM 7C1399 15NS 32K 8 SOJ IC EPROM 87C51SLAH 16K OTP 5V PAL 16V8Z 15JI PLCC 20 IC DC DC CONVERT MAX797 SO W TRANSCEVR MAX211ECAI SSOP28 IC AUDIO AMP LM4861 SO N 8P IC ANALOG SW PI5C3126 SO W Comment Location Qty 22 10139 001 CN2 3 22 10177 001 4 22 10179 001 CN16 22 40091 001 SW1 23 20004 014 BT1 24 20058 001 T1 50 42003 002 HDD CABLE 55 46801 001 55 46802 011 55 46804 011 56 15468 001 60 46801 001 62 10004 068 40 62 10017 144 511 2 71 00643 00G 038 71 00708 00A 52 55 71 01438 001 05 71 01688 00E 08 71 03285 001 U9 71 32384 00N 012 71 86521 00V U30 71 86522 00V U41 71 86523 00V U29 71 87336 00E U24 71 87552 00C U40 72 28002 009 U23 72 32588 005 U31 32 72 71399 23 035 72 87C51 16M 016 73 16V8Z BD3 028 74 00797 032 056 74 0211 0 9 048 74 04861 011 010 11 74 53126 091 04 k N U1 6 47 IC CLK GEN MK1438 01RTR
174. Map Interrupt Number Interrupt Source Device Name System Timer Keyboard Cascade IrDA 2F8h Serial Port 1 3F8h Audio ESS1688 Floppy Disk Controller FDC Parallel Port Real Time Clock RTC Ethernet on Port Replicator Internal Modem 3E8h PCMCIA PS 2 Mouse Co processor Hard disk CD ROM 1 5 3 Address Table 1 9 Address Address Range O O O O 000 00F DMA controller 1 020 021 Interrupt controller 1 024 026 BOh PicoPower chipset registers 02E CMD0643 IDE controller 040 043 Timer 1 048 04B Timer 2 060 06 Keyboard controller 8742 chip select 070 071 Real time clock and NMI mask 080 08F DMA page register 0 1 Interrupt controller 2 0C0 ODF DMA controller 2 1F7 Hard disk select 3F6 7 Hard disk select 170 177 CD ROM select 376 377 CD ROM select 220 22F Audio 240 24F Audio default 260 26F Audio 280 28F Audio 278 27F Parallel port 3 2E8 2EF COM 4 2F8 2FF COM 2 IrDA 300 301 MPU 401 port default 310 311 MPU 401 port 320 321 MPU 401 port 330 321 MPU 401 port 34C 34F Docking station 378 37F Parallel port 2 388 38B FM synthesizer 3BC 3BE Parallel port 1 3B4 3B5 3BA Video subsystem 3C5 3C6 3C9 Video DAC 3CF Enhanced graphics display 3D0 3DF Color graphics adapter 8 Modem 7 Floppy disk controlle
175. NS T3 TP PT3 TDI R209 1 2 lt 1 TD ao CONFIDENTIAL R142 1 2 IK PSVSW o 1 o TP PSVSW 26 PT3 TNS R136 1 21K 4 1 7 s LPs R1351 gt 4 L TP ACER ADVANCED LABS Title P54C MODULE CONNECTORS Size Document Number CPU INTERFACE CONNECTOR AL VS5 VGADIS 055 VGADS S PTEAEOT 89595 oe 55 CIEN 5 SPKOFF NSS SPKOFF 6 SV V V PSVR 55 VDCLKEN VSS VOCLKEN 3331313 333333 3333333 33333 33 3333 L 55 VOPD 35 VOPI K CHS WERT CH3 0500
176. OK SPRING EJ SPG 1 H C O3 42 46829 00 LED LENS FOR POWER 1 S J 04 42 46828 00 LCD LATCH 1 Salt 05 40 46805 001 ACER LOGO 1 S Y 06 47 46802 00 CUSHION BEZEL 2 P M O7 47 46803 00 CUSHION MICROPHONE P M O8 50 46806 00 FPC LCD HIT 11 3 ADFLEX 09 41 48804 002 LCD PANEL FOR HIT 11 3 Su O 34 46831 002 SHIELD FOR HIT 11 3 SY 1 86 4A453 6RO SCREW M2 5 L6 NYLON 0 CASHI 2 86 14522 6RO SCREW PAN MECH M2 0 L6 2 CASHI 13 31 46813 001 NAME PLATE FOR ACER OUDENSHA 4 56 07469 001 LCD SANYO 11 4 SANYO 15 19 20086 001 LCD INVERTER FOR HIT 11 3 AMBIT 16 23 42009 001 MICROPHONE HOSIDEN 17 34 46829 001 HINGE L FOR 970 CEMA C 18 34 46830 001 HINGE R FOR 970 CEMA PANEL ASSEMBLY 60 46814 013 E 19 86 4A453 6RO SCREW PAN M2 5 L6 NYLON 2 CASHI 20 47 46810 002 CUSHION SPACER A CR 2 S Y 1 21 40 46814 001 LCD FPC MYLAR 1 P M P 22 tA 24 25 D 65 46806 001 LCD 11 57 MODULE ASS Y MODEL NAME B 10 1 Notice Directory 970 2 2 component 1996 DRN MATERIAL REV DESCRIPTIO SIGN DATE p DSN TONY HSIAO FINISH MCS 050 QTY 1 1 DI mm SCALE z 1 SHEET 1 oF 1 DO NOT SCALE DRAWING APPD Acer DRAWING 65 46806 001 1 2 4 5 7 8 9
177. PP 4 4 184626 SARES8 33 3 08 1 RN1424 13 i 1323 PPS 3 6 1 1323 PPS SUNE 3 5 13 SARESS 33 5 2 C213 C212 C201 C206 lt T 330pF T C211 C210 C209 C200 330pF 680pF 330pF 680pF R183 15 5 2 si 2 KES 00006 1 1K 1 2 R182 Bu 100K 1 ACER ADVANCED LABS Title PROJECT MARS Size Document Number PARALLEL PORT INTERFACE AL Tei gt PSVSW R269 100K ug 2 2 5 1 TE 0 HE ET SHON SWESPPD 16 13 SPS DE i H 5 208 18 SPS RTS S mor H FERE ai 13 SPS DTR2 TN TOUT 1 2 x SARES8 99 1 8 SP5 RR 3 8 9 P5 RXDB 2 7 SP5 1 5 ROT RIN 4 SP5 3 1 SP5 CTSR 8 FEN ear SP5_DSRE 4 5 SP5 TXDR 3 id 2 SN 525 1 5 SPS RISR 7 MES RN LE SPS SPS RXDR 3 6 SP5 DSRR 6 vo 4 5 595 DOOR 1 voc GND SARES 33 SERS C9 35V 1595 23 SP5 2 SP5 DE 2 SP5 2 05058 23 5 RI 2 305 005
178. R PSVR PSVR 1 1 1 4 4 4 5 6 9 8 10 ESSI 17 peg 17 O tuF U25C 250 14 1455 14 1455 14 1455 PSVSW PSVSW PSVSW o o o U54C U54D 0 Ew TD 1 224 Lm24 4 12 13 1 1 1 4 0 13 1720 744508 ADVDD om 3 6 14 i 268 74HCTBS AUDGND AUDGND AUDGND H HOLE HOLE HOLE HOLE HOLE HOLE HOLE HOLE H H H H H H H H 1 1 1 1 1 1 1 1 H5 HOLE HOLE ET PD P4 H H pos 34 1 1 ACER ADVANCED LABS Title PROJECT MARS Size Document Number A SPARE PARTS RI T gt REVISION HISTORY 1 MODIFICATIONS FROM X4 TO X5 1 DELETE COMPONENTS C78 0 01uF 10 CAP 2 VALAUE CHANGES R13 20K 5 RESISTOR gt 1 5 RESISTOR 50 10K 5 RESISTOR gt 4 7K 5 RESISTOR 3 ADD COMPONENTS R80 R83 10K 5 RESISTOR R81 R82 15K 5 RESISTOR R84 4 7K 5 RESISTOR R85 R86 150K 5 RESISTOR C137 4700pF 10 CAP C138 0 47uF 10 CAP 0805 ll POPULATED UNPOPULATED PARTS 1 NMG2090 VIDEO CONTROLLER UNPOPULATED PARTS 25 R63 R66 R67 R68 R73 R74 R77 R78 R83 Ota N1 2 NMG2093 VIDEO CONTROLLER POPULATED PARTS U25 0123012401250128 UNPOPULATED P
179. RESS STROBE This input indicates the presence a new valid bus cycle is currently being driven by the CPU ADS is driven active in the first clock of a bus cycle and is driven inactive in the second or subsequent clocks of the cycle ADS is driven inactive when the bus is idle ADDRESS HOLD This output is used in conjunction with EADS for write protecting a cacheable ROM region CPU BYTE ENABLE 7 0 The byte enable pins are used to determine which bytes must be written to V2 LS memory or which bytes were requested by the processor for the current cycle They help define the physical area of the memory or I O accessed Byte enable pins are driven in the same clock as ADS They are driven with the same timing as the address lines A 28 3 BURST READY This output to the Pentium processor indicates completion of the current cycle BRDY indicates that the V2 LS has presented valid data in response to a read or that it has accepted the data from the Pentium processor in response to a write request CACHE This input from the Pentium processor indicates a CPU cacheable burstable operation CPU CLOCK OUTPUT This will be the clock output from V1 LS DATA This cycle definition input from the Pentium processor indicates whether the current cycle is a data or a code special access The D C4 pin is driven valid in the same clock as ADS and the cycle address t remains valid from the clock in which ADS is asserted unti
180. S 47K 5 1 16W R5 10K CONFIDENTIAL ACER ADVANCED LABS Title PROJECT MARS Size Document Number SUPER VO CONTROLLER 22 1627 2223 PSVSW PSVR R130 PSVR R199 10K 1 1 4 4 p UB PSVR TA 1 TAAHOT125SS TAACT08 4 1 VS5 SUSPENDE LT gt o VSS SUSPEND 2529 74456 PSVSW RI28 10K 1 4 SPORE 208 7AACTOB 1 4 MOS RING 5 6 T4HCTOASS 127 CONFIDENTIAL ACER ADVANCED LABS Title PROJECT MARS Size Document Number Rif INTERFACE LOGIC 48 13 20 22 23 29 31 482022 482022 BB INSTALL R89 CC REMOVE R89 _ 27 __ 26 27 20 20 PSVR PSVR 1 i88 6 RIA 10K 155 500 go eo I5 12 5 155 502 Poer HE ed 50 2 12 1 1 OFS FODDE m PCDBA PUT 1 5 K85
181. S 2 Warp system Keyboard and 84 85 key with Win95 keys 101 102 key PS 2 compatible pointing device auto tilt feature keyboard or 17 key numeric keypad Touchpad centrally located on palm rest External serial or PS 2 mouse or similar pointing device ports One 9 pin RS 232 serial port Serial mouse printer or other serial UART16550 compatible devices One 25 pin parallel port Parallel printer or other parallel EPP ECP compliant devices floppy drive module when used externally One 15 pin CRT port Up to a 1024x768 ultra VGA monitor Table 1 5 System Specifications Standard Optional Weight with FDD with CD ROM Dimensions Round contour Main footprint Temperature Operating Non operating Humidity Operating Non operating Battery pack Type Charge time One 6 pin PS 2 connector 17 key numeric keypad PS 2 keyboard mouse or trackball One 240 pin mini dock connector Mini dock One type lll or two type PC slot s LAN card or other PC cards One serial infrared port IIDA compliant External IR devices and peripherals One 3 5mm minijack microphone in line in Microphone or line in device jack One 3 5mm minijack speaker out line out Speakers or headphones jack RJ11 phone jack includes battery 3 4 kg 7 4 lbs 3 5 kg 7 7 lbs LxWxH Carrying bag 297 313mm x 230 240mm x 48 53mm 11 7 x 9 1 x 2 non condensing 20 80 RH 2096 80 RH AC adapter
182. SLM 120 133 150 10 8V 5400 for Li lon Line in speaker out EET PicoPower Vesuvius GS Chipset AC DC 256KB Sys Video flash ROM BIOS E NeoMagic NMG2 PCI video accelerator s 100V 240V Auto Switching 1MB Video Memory Cirrus Logic CL PD6730 PCI PCMCIA Chip DIMM x 2 257 HDD Rockwell RCV288Aci SVD Modem Chipset 8 16 32MB Philips 87C552 SMC controller 1440MB IBM DMCA 21440 NS87336 VJG I O Chip Touchpad 2160MB IBM DCRA 22160 ESS1688 sound controller DC AC Ambit T62 039 C Ext FDD module 10643 PCI IDE controller mbi or Int CD ROM Inverter Ambit T62 055 C FDD Mitsumi D353F2 CD ROM Toshiba 6x speed Keyboard DC DC Converter STN Color TFT Color LCD 84 87 Key amp Charger 11 3 STN SVGA HITACHI LMG9930ZWCC Ambit 162026 11 8 TFT SVGA HITACHI TX30D01VC1CAA 12 1 TFT SVGA IBM ITSV50D yoojg jeuonounJ 9 PBSRAM Pentium 256 Processor Address bus Ld Data bus L PCI E IDE DIMM v2 CMD0643 Sockets ain T Bus I I pis aude PCI PCMCIA PCI Video ES1688 CL PD6730 NM2090 5V S bus MDP Superl O BIOS Philips KBC MCU R6684 uL NS87336 256K 87C552 8051 R6723 LI DTP E R6693
183. SSOP_ 1 EN EN Table C 1 Spare Parts List N N9 IC PWR INTF SW TPS2202AIDF SOP 71 02202 00N U28 IC MODEM DIGI R6684 17 PLCC68P 71 06684 00C U19 0 IC MDP R6693 14 PQFP 100P 71 06693 00 03 27 X1 IC EEPROM ST24C02A 256K 8 SO N U U n CDR 630 91 46837 001 CDR 664 91 46837 003 2 6 LN 8 9 10 15 5 7 8 9 Appendix D Schematics The Appendix D has three sections for presenting system board media board and CPU board schematics This section shows the system board schematic diagrams of the notebook Schematics Page List Page D1 1 Index Page Page D1 2 Revision History Page D1 3 Clock Generator Page D1 4 P54C Pull Up and Pull Down Page D1 5 P54C Module Connection Page D1 6 V1 LS Page D1 7 V2 LS Page D1 8 V3 LS Page D1 9 Cache Data SRAM Lower 32 bit Page D1 10 Cache Data SRAM Upper 32 bit Page D1 11 DRAM Damping Resistors Page D1 12 Expansion Memory Socket Page D1 13 Super Controller Page D1 14 RI Interface Logic Page D1 15 Keyboard Controller Page D1 16 System Management Controller Page D1 17 CD FDD and HDD Interface Page D1 18 Parallel Port Interface Page D1 19 Serial Port Interface Page D1 20 Flash BIOS and Debug Port Page D1 21 PC
184. Setup using the user password you cannot modify or remove the supervisor password To remove a password select the desired password to remove and press lt gt 3 6 2 Diskette Drive Control This parameter allows you to enable or disable the read write functions of the floppy drive The following table summarizes the available options Table 3 2 Diskette Drive Control Settings Description Normal Floppy drive functions normally default Write Protect Disables any floppy drive write function protects all sectors only under DOS mode Disabled Disables the floppy drive 3 6 3 Hard Disk Drive Control This parameter allows you to enable or disable the read write functions of the hard disk The following table summarizes the available options Table 3 3 Hard Disk Drive Control Settings Setting Normal Hard disk functions normally default Write Protect Disables any hard disk write function protects all sectors only under DOS mode Disabled Disables the hard disk 3 6 4 Start Up Sequences This parameter determines which drive the system boots from when you turn on the system The following table lists the five possible settings Table 3 4 Start Up Sequences Settings Setting A then C System boots from floppy drive A If the diskette is a non system disk the system boots default from hard disk C C then A System boots from hard disk C If the hard disk is a non system disk
185. Supports Windows 95 Windows NT 3 1 and 3 5 Daytona OS 2 e CMD s complete set of 32 bit drivers handle both and Fully compatible with the latest PCI PCI IDE ATA 2 Enhanced IDE Fast IDE ATAPI plug and play and ATA 2 Power Management Feature Set Fully supports all ATAPI compatible devices including CD ROM tape MO and other devices Fully supports legacy IRQ 14 and 15 Hardware and software mode switching and chip enable disable capabilities Programmable read ahead and write back buffers enhance transfer rates Fully compatible with all major operating systems 100 2 9 2 DCHRDY 2NDIOR amp 2NDIOW DCS3 DCS2 PCIREQ PCIGNT 18015 INTA TESTO DIRQ2 2NDIDEENS DMACKO amp DMACK1 PCICLK VSS VDD TRDY DEVSEL DMARQO PERR PAR STOP FRAME IRDY IDSEL Figure 2 19 Pin Diagram PC10643 Pin Diagram PCIO643 DSD lt 7 gt TEST i DMARQI DRST DIOW AD lt 23 gt AD lt 22 gt DIOR lt 21 gt DCS1 DCS0 VSS uuu DSD lt 11 gt AD lt 0 gt AD lt 1 gt AD lt 2 gt AD lt 3 gt AD lt 4 gt AD lt 5 gt AD lt 6 gt VSS DSD lt 12 gt DSD lt 13 gt 050 lt 14 gt 050 lt 15 gt AD lt 8 gt AD lt 9 gt AD 10 AD lt 11 gt AD lt 12 gt AD lt 13 gt AD lt 14 gt AD lt 15 gt VSS AD lt 16 gt 2 9 3 Signal Descriptions Table 2 15 PCIO643 Signal Descriptions 2NDIDEEN Secondary
186. T IOCHCK IOCHRDY IOCS16 GENERAL PURPOSE OUTPUT EXTENSION The GPEXT is pulsed low when register GPEXT LB is being written The value being written to GPEXT LB and the value previously latched in GPEXT HB will be driven onto SD 7 0 and SD 15 8 respectively to extend by up to 16 general purpose outputs An external 8 bit or 16 bit flip flop should be used to latch the SD bus on the rising trailing edge of GPEXT UO CHANNEL CHECK This input indicates a parity error from some device on the AT bus This pin is multiplexed with ATFLOAT UO CHANNEL READY When this input is driven low it indicates that the device on the AT bus currently being accessed requires additional time to complete the cycle CHIP SELECT 16 This input from the AT bus indicates that the current access is to a 1 6 bit I O device 65 87 14 IOW 1 IRQ 15 14 12 3 1 70 71 72 82 MASTER MEMCS16 MEMR MEMW WRITE This output to the AT bus indicates an Write cycle INTERRUPT REQUEST ISA bus interrupt requests MASTERS This input from the AT bus indicates that a slot master has taken control of the AT bus MEMORY CHIP SELECT 16 BIT This input from the AT bus indicates that the current access is to a 16 bit memory device MEMORY READ This output to the AT bus indicates a Memory Read cycle to any valid AT bus address MEMORY WRITE This output to the AT bus indicates Memory Write cycle to any valid AT bus addr
187. TDRV ES STIR 8 RESET y V Ba AUDGND AUDGND AUDGND AUDGND AUDGND AUDGND 155 T SI SE Ohr SS 2 om DORMC 23 8 At ROE 4 1400 82 1000pF IR R109 1322 S RGB Dn 10k AND 18 T FO 2 8 DACH 4 8155 1000pF 8155 Sg DACKBA PA AUDGND 8 lt 55 DROS 381 prac rox Hex 470 68 __ ras P gt 8c 55 DRY pe mo 9 is 4 1 50 5 cud 5 PCSPKO 4 K 32 10K OF R67 READ SEQUENCE KEY ADDRESS sma 051 gt g ME 5 ast Kum HE gt 32 janet A ASO 2 AMODE T 2 S SE wo 4 ot ox EX D mo pm AUDIO gt DONOTPOPULATE 7 FSK 5 9 PR 9 FADE CEPR ADS PCSPK T2 PK lt giipiii xxo 8805758 ARRARIR ES1608W 813 1167 4 8 CONFIDENTIAL mms lt ACER ADVANCED LABS Tie PROJECT MARS Sze Document Number AUDIO CODEC oe nu xd ee PR C9 1 4 13 12 15 x 22 SPRR m 74 1455
188. TER SARES10 10K 3 BUE 155 SBHE ig X 155 1808 Do 10 155 1OCHCK d ook 1557801 2 3 155 4 lt 155 1905 3 8 1557809 182022 18 155 0576 Ya 155 1806 4 7 IS5 ROTO 155 MEMCSIGR EXE 179 PETENS 5 8 155 18 25 SARES10 10K mem se TEE PAS 1 H 165 1 2 1 FRAMER R42 1 2 R123 23 155 ZWS R120 1 2 90 IRDY R46 1 2 10K 100K nn 155 REFRESHE 8147 1 2 4K TRDYF R202 1 2 2 i 155 MEMCST6F R 2 330 DEVSELF 8201 T 10K 155 330 5 R195 1 2 DURER 155 MASTERF 89 T 2 330 RS 1 2 55 51 5 s s 5 5 59 35 5 5 3 555 5 SERRE 830 1 2 iK PC3 PAR R9 1 2 10K 51515151515 5 5 5 5 5 55 5 5 5 5 5 5515 51515 155 IOCHCK RIO 1 2 4K LOCKE T 2 iK 155 DROS RIS 2 100K 187 T 10K 155 DROS RH T 555555555555555555555555 155 IOCHRDY 151 1 2 C 186 1 2 C 85 1 210K 0 12 4 5 67 8 91 1 22 C BER 150 1 2 01121314 5167189 0 1213 INTAR 191 T 10K INTEF 8190 T 10K NE RoT 41315202231 155 54 27 Ri 1 210K ACER ADVANCED LABS IRQSER 1 2 CONFIDENTIAL VESUV
189. TER e 1 8 AiG x12 1 PCD 71 LOCK 1 a GND mnm GND H PT3 815 2 m PT3 119 e PNSW PTS i 2 T 145 146 15 16 1 PTS 057 M5 146 PEDS 1 1 15 16 gt wow HR PTS 1 58 OU Sm e O s 4 10 u m BERT 1 PTS 7 8 uoe _ SPEED 5 PTS FLUSHF i 515 m ES 157 158 PTS 3 4 jus US SERES CPUCORE 1 2 ET CPUCORE JED JRETGOR FEMALE MAE 1 3T 1 0 6 CPUCORE GE GND 0 7 PavsW PES CONFIDENTIAL 3 ACER ADVANCED LABS P54C CPU MODULE Sue Document Number CPU INTERFACE CONNECTOR Dale April 8 1996 TSheet P3VSW cat 16 c12 015 E 1206 1206 1206 1206 12 1206 12 1206 CPUCORE TS C20 4 16 47uF_16 11 fi C2 C5 C6 08 O tuF_12b6 1246
190. TES Dale Way 9 1996 TSheel 11 d This section shows the CPU board schematic diagrams of the notebook Schematics Page List Page D3 1 P54C TCP CPU Page D3 2 P54C TCP CPU Interface Connector Page D3 3 P54C TCP CPU 3 PT3 RSTCPU PT3 INIT 2 CFTE 00 84 010 Dii PT3 D PT3 013 PT3 014 PT3 D15 PT3 D18 PT3 019 CPUCORE m RESET M INT 5 6 BRDY NAE i BOFF HOLD AN AHOLD EADS n n WBWT n wa 6 FLUSH n EWBE INTRUNTO r NMILINTI I IGNNER r Suit STPCLK RSH i 54 BUSCHK 128 pr 30 Do 31 02 03 Ut BE0 D5 0 BE4 Dr De 010 D11 D12 DPO 013 04 DP2 015 DP3 016 017 DP5 018 DPS D19 DP7 D20 021 022 023 PCHK 024 IERR 025 FERRE D26 a 027 D28 DICE 029 WR 08 NO CONNECT 175 184 185 271 CACHER 031 SCYC 032 LOCK 033 HLDA 034 BREQ 035 HIT D36 037 038 039 SMIACT 040 041 042 043 044 045 046 047 048 219 PT3 A3 222 223 A5 227 PT3 A6 228 PD 7 231 PT3 234 9 237 PTS 238 PT3 245 PT3 AJ 248 x 251 PT3 A15 254 PT3 A16 259 PT3 A18 262 x 265 PT3 A20 E 202 PT3 A23 20
191. TREE S LER OL LLLI E LO D f f o o f mr DDC2BD DDC2BC PDATA18 19 Figure 2 8 NMG2090 Pin Diagram 88 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 2 3 3 Pin Description Conventions used in the pin description types Table 2 5 NMG2090 Pin Description Conventions Input into NMG2 Tri state during un driven state Output from NMG2 S T S Before becoming tri state the pin will be driven inactive O nput and Output to from NMG2 Open drain type output The following table lists the pin descriptions Table 2 6 NMG2090 Pin Descriptions PinName Type Pinno Descriptions Multiplexed Address and Data 31 0 These multiplexed and bi directional pins are used to transfer address and data on the PCI bus The bus master will drive the 32 bit physical address during address phase and data during data phase for write cycles NM2090will drive the data bus during data phase for read cycles Table 2 6 NMG2090 Pin Descriptions continued PinName Type Pinno BDeseptions 63 Multiplexed Command and Byte Enable These C BE2 51 multiplexed pins provide the command during address phase C BE1 40 and byte enable s during data phase to the NMG2 C BEO 31 FRAME 72 Frame This active low signal is driven by the bus master to indicate the beg
192. When low this output indicates to DTR2 the modem or data set that the UART is ready to establish a communications link The DTR signal can be set to an active low by programming bit 0 DTR of the Modem Control Register to a high level A Master Reset operation sets this signal to its inactive high state Loop mode operation holds this signal to its inactive state ERR 79 Parallel Port Error This input is set low by the printer when an error is detected This pin has a nominal 25 KOHM pull up resistor attached to it HDSEL 34 FDC Head Select This output determines which side of the FDD is Normal Mode accessed Active selects side 1 inactive selects side 0 HDSEL 79 FDC Head Select This pin offers an additional Head Select signal in PPM Mode PPM Mode when PNF 0 IDLE 43 FDD IDLE IDLE indicates that the FDC is in the IDLE state and can be powered down Whenever the FDC is in IDLE state or in power down state the pin is active high INDEX lt 1 Index This input signals the beginning of a FDD track INDEX 94 Index This pin gives an additional Index signal in PPM mode when Normal Mode PNF 0 Initialize When this signal is low it causes the printer to initialized This pin is in a tristate condition 10 ns after a 1 is loaded into the corresponding Control Register bit The system should pull this pin high using a 4 7 KO resistor Table 2 10 NS87336VLJ Pin Descriptions continued m re
193. ables even numbered address bytes and CE2 enables odd 2 or 3 numbered address bytes When configured for 8 bit cards only CE1 is active and is used to indicate access of odd or even numbered bytes Card Reset This output is low for normal operation and goes high to reset the card To prevent reset glitches to a card this signal is high impedance unless a card is seated in the socket card power is applied and the card s interface signals are enabled In Card Interface mode this input CL PD6730 Pin Descriptions continued Description Pin Number Pin Number socket A socket B 110 1 108 06 126 61 202 136 74 70 150 147 O TS 167 82 Table 2 14 CL PD6730 Pin Descriptions continued Description Pin Number Pin Number I O socket A socket B Battery Voltage Detect 2 Speaker LED In Memory Card Interface mode this input serves as the BVD2 battery warning status input In I O Card Interface mode this input can be configured to accept a card s SPKR digital audio output For ATA or non ATA SFF 68 disk drive support this input can also be configured as a drive status LED input BVD1 CBattery Voltage Detect 1 Status STSCHG change Ring Indicate In Memory RI Card Interface mode this input serves as the BVD1 battery dead status input in Card Interface mode this input is the STSCHG input which indicates to the CL
194. active low if it detects a data parity error during a write phase SERR System Error This output is pulsed by the CL PD6730 to indicate an address parity error PAR Parity This pin is sampled the clock cycle after completion of each corresponding address or write data phase For read operations this pin is driven from the cycle after TRDY is asserted until the cycle after completion of each data phase It ensures even parity across AD 31 0 and C BE 3 0 PCI CLK PCI Clock This input provides timing for all transactions on the PCI bus to and from the CL PD6730 All PCI bus interface signals described in this table except RST INTA INTB and INTD are sampled and driven on the rising edge of PCI CLK and all CL PD6730 PCI bus interface timing parameters are defined with respect to this edge This input can be operated at frequencies from 0 to 33 MHz Note that the PC Card socket interface cannot operate at more than 25 MHz RST Device Reset This input is used to initialize all registers and internal logic to their reset states and place most CL PD6730 pins in a high impedance state INTA PCI Bus Interrupt A ISA Interrupt Request 9 IRQ9 This output indicates a programmable interrupt request generated from any of a number of card actions Although there is no specific mapping requirement for connecting interrupt lines from the CL PD6730 to the system a common use is to connect this pin to the PCI bus
195. active low outputs They are encoded with information to control four FDDs when bit 4 of the Function Enable Register FER is set MTRO exchanges logical motor values with MTR1 when bit 4 of FCR is set Media Sense These pins are Media Sense input pins when bit O of FCR is 0 Each pin has a 10 internal pull up resistor When bit 0 of FCR is 1 these pins are Data Rate output pins and the pull up resistors are disabled Media Sense These pins gives additional Media Sense signals for PPM Mode and 0 FDC Motor Select 1 This pin offers an additional Motor Select 1 signal in PPM mode when PNF 2 0 This pin is the motor enable line for drive 1 when bit 4 of FCR is O It is the motor enable line for drive 0 when bit 4 of FCR 1 This signal is active low 1 84 Mode 45 Power Down This is PD output when bit 4 of PMC is 1 It is DR1 when bit 4 of PMC is 0 PD is active high whenever the FDC is in power down state either via bit 6 of the DSR or bit 3 of FER or 3 bit 0 of PTR or via the mode command 94 91 Parallel Port Data These bidirectional pins transfer data to and 89 86 from the peripheral data bus and the parallel port Data Register These pins have high current drive capability 4 9 RDATA 35 Normal Mode 9 1 PPM Mode Parallel Port Paper End This input is set high by the printer when it is out of paper This pin has a nominal 25 pull down
196. adapter IR capable printer PC slots One Type lll or two Type PC cards 10 Microphone in Line in External microphone or line input device Speaker out Line out Amplified speakers or headphones 1 1 4 Automatic Tilt up Keyboard A tilt Switch found right above the port cover on the rear of the notebook allows you to enable or disable this feature Follow these steps 1 Close the lid 2 To enable slide the tilt 3 Open the lid switch to the right Ez To disable slide the tilt switch to the left SSS 1 1 5 Indicator Light Two indicator lights are found on the display panel Indicator Battery Indicator MN WW M 222 r 225 n y 254 VM Y y M ES i 0 Ni i S V Figure 1 Indicator Lights These indicators and their descriptions are shown in the table below Table 1 2 Indicator Status Descriptions Indicator Light Power Indicator Lights when power is on Flashes when the notebook is in suspend to memory mode Battery Indicator Lights when battery pack is charging Flashes when battery power is low 1 1 6 Keyboard Hotkey List BEBO 0 X XJ JJ The following table lists and describes the hotkeys used by the notebook
197. age Expansion Peripherals PCMCIA Slot 0 PCMCIA Slot 1 Parallel Port Serial Port IrDA Modem AC Adapter Main Battery Onboard Audio Base Address MPU Base Address IRQ Setting DMA Channel About My Computer None None 378h 3F8h 2F8h 3E8h None 60W Li Ion 1204 IRQ3 10 33 6 kbps V 34 DSVD PgDn PgUp Move Screen Esc Exit Press PgUp to return to the first page To return to the main screen press Esc ABOUT MY COMPUTER ITEMS These screens display the current status of the notebook and its peripherals The items in this screen are not user configurable Table 3 1 About My Computer Item Descriptions __ Deseription Graphics Controller Graphics controller type Display Output Display type and resolution Hard Drive 0 IDE 0 drive type and size hard disk Floppy Drive B Floppy drive B type Bank B Bank B memory module size type and speed isk Hard Drive 1 IDE 1 drive type CD ROM or other IDE drives ice ice Floppy Drive A Floppy drive A type 3 4 System Configuration The following screen is the basic system configuration screen Basic System Configuration Page 1 1 Current Date Current Time Diskette Drive A Diskette Drive B Hard Disk 0 1160 MB Hard Disk 1 0 MB Num Lock After Boot LCD Expansion Mode 09 16 96 16 30 35 1 44 MB 3 5 inch None Cylinder Auto 2358 Auto 0 Disabled Disabled Head Sector 16 63 0
198. al pulldown resistor or a shorting block that goes to either VDDD or GNDD Note when AMODE 0 address inputs 10 A11 have internal pull down devices When AMODE 1 they not IRQA B C D 70 67 Active high interrupt request to ISA bus Unselected IRQ outputs are high impedance IRQs are selected after external reset based on the settings of inputs 151 and 150 and can reprogrammed thereafter Active high interrupt request to ISA bus Reserved for MPU401 Table 2 11 ESS1688W Pin Descriptions continued Pin name Number vo Description DRQA B C 65 63 59 Active high DMA request to ISA bus Unselected DRQ outputs are high impedance When DMA is not active the selected DRQ output has a pulldown device that holds the DRQ line inactive unless another device that shares the same DRQ line can source enough current to make the DRQ line active DRQs are selected after external reset based on the settings of inputs DS1 and 050 and can be reprogrammed thereafter DACKBA 66 64 62 Active low DMA acknowledge inputs from ISA bus PCSPKI 72 Normally low digital PC speaker signal input This signal is converted to an analog signal with volume control and appears on analog output PCSPKO FSR Input with internal pull down Frame Sync for Receive data from external DSP Programmable for active high or active low FSX 8S7 Input with internal pull down Frame Sync for Transmit request from external DSP Progr
199. ammable for active high or active low DCLK 88 Input with internal pull down Serial data clock from external DSP Typically 2 048 MHz Input with internal pull down Data Receive pin from external DSP DX Tri state output Data Transmit to external DSP High impedance when not transmitting MSD 91 Input with internal pull down Music Serial Data from external ES689 Music Synthesizer MCLK 92 Input with internal pull down Music Serial Clock from external ES689 Music Synthesizer SE 93 Input with internal pull down Active high to enable serial mode i e enables an external DSP to control analog resources of the ES1688W through the DSP serial interface VDDA 39 Analog supply voltage 4 5V to 5 5V Should be greater than or equal to VDDD 0 3V GNDA I Jj Analog Ground 6 Microphone input MIC has an internal pull up resistor to CMR LINE L R 44 45 Line input left right LINE L R has internal pull up resistors to CMR AUXA L R 34 35 Auxiliary input left right AUXA L R have internal pull up resistors to CMR Normally intended for connection to an internal or external CD or CD ROM analog output AUXB L R 32 33 Auxiliary input left right AUXB L R have internal pull up resistors to CMR Normally intended for connection to an external music synthesizer or other line level source Table 2 11 ESS1688W Pin Descriptions continued Pin name Number vo Description FOUTL R 30 31 Filter outputs left right A
200. anted access to DEVICE SELECT As an output it indicates whether V1 LS the aster requesting the ownership of the PCI bus the master is notified using this point to point signal Each PCI bus master has its own GNT Table 2 2 V1 LS Pin Descriptions continued Type IRDY 157 INITIATOR READY This indicates the bus master s state of readiness to complete the current data phase During a write IRDY shows that valid data is present During a read it indicates the bus master s readiness to accept data IRDY is used in conjunction with TRDY PAR 173 PARITY All PCI agents require parity generation PCICLK LEA PCI CLOCK This pin provides timing for all transactions on the PCI bus PCIRST 178 PCI RESET This signal when asserted resets all PCI devices PERR 170 This input indicates a data parity error It may be pulsed active by any agent that detects an error condition PLOCK 161 This signal allows the master to lock the PCI bus and the arbiter does not grant the PCI bus to a new master until this signal has been deasserted REQ 3 0 162 165 PCI REQUEST 3 0 This signal indicates to the arbiter that this agent requests use of the bus This is a point to point signal Every PCI bus master has its own REQ STOP STOP This signal facilitates either master abort or target abort cycles TRDY 158
201. any Japanese Total number of keypads 84 keys 85 keys 88 keys Windows95 keys Yes Logo key Yes Logo key Yes Logo key Application key Application key Application key External PS 2 keyboard hot Yes plug Internal amp external keyboard Yes work simultaneously Keyboard automatic tilt Yes feature The keyboard has the option of automatically tilting to a six degree angle whenever you open the lid This feature is set by an keyboard automatic tilt latch on the rear side of the system unit 1 5 26 Battery Table 1 35 Battery Specifications ____ Specification Vendor amp Model Name Sony LIP617LACP Battery Gauge es Battery type Li lon Cell capacity 900mAH Cell voltage 3 6V Number of battery cell 6 Cell Package configuration 3 serial 2 parallel Package voltage 10 8V Package capacity 58 3WH Second battery No 1 5 27 DC DC Converter DC DC converter generates multiple DC voltage level for whole system unit use and offer charge current to battery Table 1 36 DC DC Converter Specifications Mem _ Specification Vendor amp Model Name Ambit T62 036 C 00 Input voltage Vdc 7 19 Short circuit protection The DC DC converter shall be capable of withstanding a continuous short circuit to any output without damage or over stress to the component traces and cover material under the DC input 7719 V from AC adapter or 18V from battery It shall operate in shut down mode for
202. are used for power on configuration switches Thel O type code I O column indicates the input and output configurations of the pins on the CL PD6730 The possible types are defined below The possible types are defined below ho mum 000000 win neal eser o i oon openan ompun The power type code Pwr column indicates the output drive power source for an output pin or the pull up power source for an input pin on the CL PD6730 The possible types are defined below Power Output or Pull up Power Source Type 5v powered from a 5 volt power supply in most systems see description of 5V pin in Table 2 4 A SOCKET VCC powered from the Socket A Vcc supply connecting to PC Card pins 17 and 51 of Socket A PCI VCC powered from the PCI bus power supply CORE VDD powered from a 3 3 volt power supply 3 B SOCKET VCC powered from the Socket B Vcc supply connecting to PC Card pins 17 and 51 of Socket B The following table lists the pin descriptions Table 2 14 IRDY STOP IDSEL DEVSEL CL PD6730 Pin Descriptions Pin Name Description Pin Number vo 3 0 FRAME PCI Bus Address Input Data Input Output 4 5 7 12 16 20 4 These pins connect to PCI bus signals AD 31 0 a 24 48 49 51 PCI Bus Command Byte Enable The 13 25 36 47 command signaling and byte enables are multiplexed on the same pin
203. ase Address This parameter accepts the following values 300 310 320 330 The default setting is 300 3 4 10 3 IRQ Setting This parameter accepts 10 7 5 or 9 as its value The default setting is 5 3 4 10 4 DMA Channel This parameter accepts 0 1 or 3 as its value The default setting is 0 3 4 11 Reset PnP Resources The system resources are already properly configured If resource conflicts should arise set this parameter to Yes to reset the PnP resources and re do allocation The BIOS automatically sets this to No afterwards The default setting is No 3 5 Power Saving Options The following screen is the power saving options screen Power Saving Options Page 1 1 When Lid is Closed Suspend to Disk Suspend to Disk on Critical Battery Enabled Display Always On Disabled Internal Speaker Enabled External Mouse Location PS 2 Internal Modem Power On Resume On Modem Ring OFF Resume On Schedule OFF Resume Date 09 16 96 Resume Time 16 30 35 T Move Highlight Bar lt Change Setting PgDn PgUp Move Screen Fl Help Esc Exit Press T to move from one parameter to another and or gt to change parameter settings Most of the parameters are self explanatory but you can press F1 to get help on the selected parameter Press Esc to exit the screen and return to the main menu 3 5 1 When Lid is Closed The notebook s lid switch ac
204. ata memory In this application it uses strong internal pull ups when emitting 1s Port 0 is also used to input the code byte during programming and to output the code byte during verification 16 19 P1 0 P1 3 Capture timer input signals for timer T2 RT2 P1 5 T2 timer reset signal Rising edge triggered 2 T2 P1 T2 eventinput o a 2 SCL P1 6 Serial port clock line 1 2 C bus SDA P1 7 Serial port data line 2 C bus Port 1 is also used to input the lower order address byte during EPROM programming and verification AO is on P1 0 etc Port 2 8 bit quasi bidirectional port Alternate function High order address byte for external memory A08 A15 Port 2 is also used to input the upper order address during EPROM programming P2 0 P2 7 39 46 and verification A8 is on P2 0 A9 on P2 1 through A12 on P2 4 P1 0 P1 7 16 23 Port 1 8 bit I O port Alternate functions include 16 21 P1 0 P1 5 Quasi bidirectional port pins 22 23 P1 6 P1 7 Open drain port pins Port 3 8 bit quasi bidirectional I O port Alternate functions include RxD P3 0 Serial input port 20 21 22 23 P3 0 P3 7 pr gy wm pas baratos OOOO O 2 2 _ Table 2 12 P4 0 P4 7 P5 0 P5 7 87C552 Pin Descriptions continued
205. bled after programming the ROM and restarting the system 3 7 Reset to Default Settings Selecting this option allows you to load all the default settings These settings are the values initially stored in CMOS RAM intended to provide high performance If in the future you change these settings you can load the default settings again by selecting this option When you select this option the following prompt appears Reset to Default Settings Are you sure Select Yes to load the default settings or No to abort the operation Chapter 4 Disassembly and Unit Replacement This chapter contains step by step procedures on how to disassemble the notebook computer for maintenance and troubleshooting To disassemble the computer you need the following tools Wrist grounding strap and conductive mat for preventing electrostatic discharge Flat bladed screwdriver Phillips screwdriver Hexagonal screwdriver Tweezers Plastic stick disassembly process group the screws with the corresponding The screws for the different components vary in size During the components to avoid mismatch when putting back the components 4 1 General Information 4 1 1 Before You Begin Before proceeding with the disassembly procedure make sure that you do the following 1 Turn off the power to the system and all peripherals 2 Unplug the AC adapter and all power and signal cables from the system 3 Remove the battery pack from th
206. cd 2 HDD CON CONFIDENTIAL 2 35V ACER ADVANCED LABS Tile PROJECT MARS Sze Document Number HDD AND INTERFACE Dale June 6 19 TSheet 17 d 3 In order to minimize the crosstalk in ECP mode the termination circuits shown below are recommended Place all termination circuits close to the connector to avoid EMI 1 10 2 3 3 8 4 7 PNSW o E SARESIO 47K PEF 2326 1323 PSVEXF STB 1 f PPS 14 PP5 PDO 1 8 1 PPS PORO 2 PP5 i ERRR 15 PPS PD 3 5 i PP PORT 3 PPS 4 5 1 PPS INTRE 16 PPS PDR2 4 SARES8 33 SUNRE 17 PUR 5 TE PP5 PDA 1 8 1 PP5 PDR4 6 PPS PD5 2 7 19 PPS 3 6 T PDRS 59 PPS PD 4 5 i 0 PURE 8 SARESS 33 REX 1 2 K 21 6154 4 PP5 9 27 Ei a 3 PP5_BUSYR Tu lo 24 ep 645 PPS PER 12 e 25 ALL4TOpF PP5 SLCTR Tdi xp ALL 4TOpF id PRNT25 RN32 7 1 10 3 3 lt P 23 4 7 PNSW o 5 SARESIO 47K RNIS RIM 13 CPPSSTBE i 4 10K 1323 PPS 5 7 gt 13 4 4 5 13 S
207. d by a series resistor of 1KO BMCVCC 14 This a 5 volt supply for powering the LEDs It should not be used for any other purpose ADVDD 18 This is a 5 volt power line for the analog circuits and display LEDs on the inverter board AUDGND GND 19 20 This is the return ground for the microphone circuit It should not be connected to VGND or other circuit on the inverter board OUT This is the output of the microphone preamplifier circuit MIC CON Microphone input x AUDGND GND This is the return ground for the microphone circuit It should not be connected to VGND or other circuit on the inverter board Chapter J BIOS Setup Information The notebook has a BIOS Basic Input Output System setup utility that allows you to configure the notebook and its hardware settings This chapter tells how to use the Setup utility and describes each parameter item in the setup screens 3 1 When to Use Setup The notebook is already correctly configured for you and you do not need to run Setup If you make any changes to the notebook or you receive an Equipment Configuration Error message after you turn on the notebook you may need to run Setup Run Setup also if you want to do any of the following Check the system configuration Change the system date time or speed or change the location of the external mouse Change the system startup sequence Set the power saving suspend mode type Set or change resu
208. d to the VSYNC pin Line Pulse This signal indicates start of a line For STN panels this pin is connected to the CP1 pin For TFT Panels this pin is connected to the HSYNC pin Shift Clock This signal is used to drive the panel shift clock Some panel manufacturers call this CP2 Shift Clocki This signal is used to drive the panel shift clock This clock is used for panels which use two clocks one for the upper panel and the other for the lower panel Panel horizontal Display Enable MOD this signal indicates the horizontal display time to the panels For some panels it is used to drive the shift clock enable pin This pin can also be configured to drive FPHDE for certain types of TFT panels which require separate horizontal display time indicator Modulation This signal is used to drive the panel MOD or AC input Table 2 6 NMG2090 Pin Descriptions continued PinName Type Pinno _ BDeseptions FPVCC 142 Flat Panel VCC This is used to control the logic power to the panels FPVEE 143 Flat Panel VEE This is used to control the bias power to the panels FPBACK 108 Flat Panel Backlight This is used to control the backlight power to the panels 18 PDATA23 O Panel Data These pins are used to provide the data interface PDATA22 to different kinds o panels The following table shows the PDATA21 functions of these pins based on the selected panel type PDATA20 PDATA23 thru PDATA18 pin are not available in VL Bus PDATA19
209. e Mobile computing PCI design guide If this signal is sampled high by the NM2090and the PCI clock related functions are not completed then it will drive this signal low to request the Central Clock Resource for the continuation of the PCI clock This function can be Enabled Disabled through reg GR12 bit 4 DDC2BD DDC Data pin DDC2BC DDC Clock pin VSSP 10 29 44 59 80 Host bus interface ground 114 125 138 ____ ________ grounder VOLK entesizer Table 2 6 NMG2090 Pin Descriptions continued _ Type Pinno Descriptions AVSSX1 Analog ground for crystal oscillator HVDD 25 42 57 78 Host bus interface VDD 5v or 3v Includes the PCI VL CRT Power Management External clock pins PMCLKI and PVCLKI and Miscellaneous pins 27 62 107 Logic VDD 3V only DVDD 134 156 175 DRAM VDD 3V only LVDD 116 132 Panel VDD 5v or 3v 2 4 Rockwell RCV288Aci SVD Modem Chipset The Rockwell RC288ACi SVD integrated data fax voice SVD modem device set supports V 34 data V 17 fax voice audio digital simultaneous voice and data DSVD and full duplex speakerphone FDSP operation over a dial up telephone line Models supporting AutoSync and world class are also available The modem device set consists of an L39 8 bit microcomputer MCU packaged in a 100 pin POFP R6723 an RCV288DPi V 34 modem data pump MDP packaged in a 68 pin PLCC 6682 and a DigiTalk coprocessor DTP
210. e Report Distributor Year Month Fixed after repair F Not fixed after repair N Model Number Failure Classification Motherboard 96 Video board 96 Qty Installed Controller 96 Storage device 96 Qty Returned No problem found Others 9 Remarks Qty Repaired 1 2 Model Number Failure Classification Motherboard 96 Video board 96 Qty Installed Controller 96 Storage device 96 Qty Returned No problem found Others 96 Remarks Qty Repaired 1 2 Model Number Failure Classification Motherboard 96 Video board 96 Qty Installed Controller Storage device 96 Qty Returned No problem found Others Remarks Qty Repaired 1 2 Model Number Failure Classification Motherboard 96 Video board 96 Qty Installed Controller 96 Storage device 96 Qty Returned No problem found Others 96 Remarks Qty Repaired 1 2 Model Number Failure Classification Motherboard 96 Video board 96 Qty Installed Controller 96 Storage device 96 Qty Returned No problem found Others Remarks Qty Repaired 1 2 PC Peripheral Problem Report Form Customer Issue I D S N Model No S N RAM Size O S Add On Cards Disk Type amp Capacity Disk Controller A P Name amp Version Other
211. e This active Low output indicates that the S T S NM2090will respond to the current cycle LRDY O Local Ready This active low output is used to terminate the S T S claimed cycle BRDY O 67 Burst Ready This active low output terminates the current S T S active burst cycle INTR i o d Interrupt Request Address 24 This active low output 24 indicates as interrupt to CPU Address bit 24 GR12 bit 0 enables disables the Address 24 decoding VID2 Low Address Decode Address 26 This input signal is used A26 as upper address decode during memory cycles It is decoded from A31 A24 to select low meg address space For a value of zero for the addresses A31 A24 VID2 should go low Address bit 26 GR12 bit 2 enables disables the Address 26 decoding IDSEL High Address Decode This input signal is used as upper A27 address decode during memory cycles active low signal is the decode to support accesses to the linear memory and memory mapped 10 ports Address bit 27 GR12 bit 2 enables disables the Address 27 decoding XTAL1 Crystal Input This is the X1 pin of the on chip oscillator for crystal use This pin can also be used to feed the 14 31818 MHz from an external clock source XTAL2 Crystal Output This pin is used for the 14 31818 MHz clock internally to NM2090chip when a crystal oscillator is connected between this pin and pin 93 Table 2 6 NMG2090 Pin Descriptions continued PinName Type Pinno
212. e and female connectors on the main board Figure 4 10 Removing the CPU Module 4 4 Removing the Display Follow these steps to remove the display module 1 Remove the two screws that secure the display cable to the motherboard Then unplug the display cable CN6 Screw list 2 514 x2 Figure 4 11 Unplugging the Display Cable 2 Remove the four display hinge screws Detach the display from the main unit and set aside Screw list M2 5L8 x4 Figure 4 12 Removing the Display Hinge Screws and Removing the Display 4 5 Disassembling the Housing This section discusses how to disassemble the housing and during its course includes removing and replacing of certain major components like the hard disk drive memory and the main board 4 5 1 Detaching the Lower Housing from the Inside Assembly To detach the lower housing from the inside assembly turn the unit over and remove seven 7 base screws Then snap out the lower part of the housing Screw list M2 5L8 x7 Figure 4 13 Removing the Hard Disk Drive Bay Cover Detaching the lower housing from the inside frame assembly allows you to remove install the hard disk drive as well as remove install memory modules 4 5 2 Replacing the Hard Disk Drive Follow these steps 1 Remove two screws that secure the hard disk drive to the inside frame assembly 2 Turn the hard disk drive over and pull out the hard disk drive cable from its connector
213. e notebook by a pressing the battery compartment cover release button and b sliding out the cover Then c pull out the battery pack Figure 4 1 Removing the Battery Pack Removing all power sources from the system prevents accidental short circuit during the disassembly process 4 1 2 Connector Types There are two kinds of connectors on the main board Connectors with no locks Unplug the cable by simply pulling out the cable from the connector Connectors with locks You can use plastic stick to lock and unlock connectors with locks cables which are more delicate than normal plastic enclosed cables Therefore to prevent damage make sure that you unlock the connectors before pulling out the cables Do not force cables out of the connectors lt gt The cables used here are special FPC flexible printed circuit CONNECTORS WITH LOCKS e Unplugging the Cable To unplug the cable first unlock the connector by pulling up the two clasps on both sides of the connector with a plastic stick Then carefully pull out the cable from the connector Plugging the Cable To plug the cable back first make sure that the connector is unlocked then plug the cable into the connector With a plastic stick press the two clasps on both sides of the connector to secure the cables in place Plugging the Cable Unplugging Plugging the Cable the Cable Wwe the Cable Figure 4 2 Using Plas
214. e unit then 2 the front end of the unit Screw list 2 514 2 e 1 Figure 4 18 Detaching the Upper Housing from the Inside Frame Assembly 4 5 5 Removing the Touchpad Follow these steps to remove the touchpad 1 Unplug the touchpad connector CN5 2 Pull up and remove the touchpad Figure 4 19 Removing the Touchpad 4 5 6 Removing the Main Board Follow these steps to remove the main board from the inside assembly 1 Unplug the speaker connectors CN17 and CN23 and the battery pack connector CN21 Figure 4 20 Unplugging the Speaker Connectors and Battery Pack Connector 2 Remove three screws and gaskets to remove the main board from the inside assembly Screw list 2 514 x4 Figure 4 21 Removing the Main Board 3 Remove the charger board CN19 and CN20 and the multimedia board CN10 and CN7 from the main board DC DC converter Multimdeia board Figure 4 22 Removing the Charger Board and Multimedia Board 4 The PC card slot module is usually part of the main board spare part This removal procedure is for reference only To remove the PC card slot module remove two screws Screw list M2L14 x2 Figure 4 23 Removing the PC Card Slots 4 5 Disassembling the Display Follow these steps to disassemble the display 1 Remove the teardrop shaped LCD bumpers at the top of the display and the long bumper on the LCD hinge Figure
215. ear the center of the display hinge that tells the notebook when it should wake up or go to sleep Figure 1 1 FlashStart Automatic Power on Switch Lid Switch When you close the display lid the notebook enters suspend to memory or suspend to disk mode before turning off the power depending on the When Lid is Closed parameter setting in BIOS Setup When you open the lid the notebook resumes from where you left off before closing the lid Suspend to memory suspend to disk and other power management issues are discussed in detail in power management section 1 1 3 Ports The notebook computer s ports are found on the rear and left panel DC in Port PS 2 Port Serial Port Parallel Port Mini Dock Connector External CRT Port OQ Q N Figure 1 2 Ports RJ 11 Phone Jack Infrared Port PC Card Slots Microphone in Line in Jack Speaker out Line out Jack The following table describes the ports Table 1 1 Port Descriptions km Pont 2 4D PS 2 port PS 2 cue device e g PS 2 keyboard keypad mouse 3 Serial port Serial device 9 serial mouse UART16650 compatible 4 Parallel port Parallel device e g parallel printer floppy drive EPP ECP compliant module when used externally eom t External CRT port External monitor up to 1024x768 256 colors Infrared port Infrared aware device e g notebook with IR port desktop with IR
216. ee eee ee ede 2 45 R6684 17 Pin Diagram 2 49 H6693 14 PibiDIagral s c toro en A 2 53 ES91688W Block Diagram tine a eet etd 2 56 ESS1688W Pin Diagram eene nnne nennen sse nnn 2 57 87C552 Block 2 64 876552 Pini Diagram e e 2 65 NS87336VLJ Block 2 70 NS87336VLJ Pin a 2 71 10643 Pin Diagram nnne nennen 2 92 2 20 2 21 4 10 4 11 4 12 4 13 4 14 4 15 4 16 4 17 4 18 4 19 4 20 4 21 4 22 4 23 4 24 4 25 4 26 4 27 4 28 162 036 2 IT BBIETo ses 2 97 T62 039 C T62 055 C Pin 2 99 Removing the Battery Pack 4 2 Using Plastic Stick on Connector With 1 00 4 3 Disassembly FloWs 4 5 Removing the 4 6 Removing the Display Hinge Covers 1000 4 7 Removing the Center Hinge Cover 4 7 Lifting Out the 4 8 Unplugging the Keyboard Connectors and Removing the Keyboard 4 8 Removing the CPU Module Lock 4 9 Removing the CPU Module
217. en the sourced device is configured with no DMA it is also in TRI STATE Upon reset DRQ2 is used by the FDC Table 2 10 NS87336VLJ Pin Descriptions continued Pm __ No 10 Den FDD Drive2 This input indicates whether a second disk drive has been installed The state of this pin is available from Status Register A in PS 2 mode See PNF for further information DSKCHG Disk Change The input indicates if the drive door has been opened Normal Mode The state of this pin is available from the Digital Input Register This pin can also be configured as the RGATE data separator diagnostic input via the Mode command DSKCHG Disk Change This pin offers an additional Disk Change signal in PPM Mode PPM Mode when PNF 0 DSR1 76 68 UARTs Data Set Ready When low this indicates that the data set DSR2 or modem is ready to establish a communications link The DSR signal is a modem status input The CPU tests the DSR signal by reading bit 5 DSR of the Modem Status Register MSR for the appropriate channel Bit 5 is the complement of the DSR signal Bit 1 DDSR of the MSR indicates whether the DSR input has changed state since the previous reading of the MSR NOTE Whenever the DDSR bit of the NSR is set an interrupt is generated if Modem Status interrupts are enabled DSTRB 78 EPP Data Strobe This signal is used in EPP mode as data strobe It is an active low signal DTR1 71 63 UARTs Data Terminal Ready
218. er components required e Low power CMOS with enhanced power down mode e Automatic media sense support with full IBM TDR Tape Drive Register implementation Supports fast 2 Mbps and standard 1 Mbps 500 kbps 250 kbps tape drives The Bidirectional Parallel Port e Enhanced Parallel Port EPP compatible e Extended Capabilities Port ECP compatible including level 2 support e Bidirectional under either software or hardware control Compatible with ISA and EISA architectures e Ability to multiplex FDC signals on parallel port pins allows use of an external Floppy Disk Drive FDD e Includes protection circuit to prevent damage to the parallel port when a connected printer is powered up or is operated at a higher voltage UARTs e Software compatible with the PC16550A PC16450 e MIDI baud rate support e Infrared support on UART2 IrDA and Sharp compliant The Address Decoder e 6bitor 10 bit decoding e External Chip Select capability when 10 bit decoding e Full relocation capability No limitation Enhanced Power Management Special configuration registers for power down Enhanced programmable power down FDC command e Auto power down and wake up modes 2 special pins for power management Typical current consumption during power down is less than 10 uA e Reduced pin leakage current Mixed Voltage support Supports standard 5V operation Supports 3 3V operation Supports mixed
219. erially transmitted to the external serial to parallel shifters CLKRUN Clock Run This pin is an input to indicate the status of PCI_CLK or an open drain output to request the starting or speeding up of PCI_CLK This pin complies with the Mobile PCI Specification PCI VCC PCI Bus Vcc These pins can be connected to 6 21 37 50 either a 3 3 or 5 volt power supply The PCI bus interface pin outputs listed in this table will operate at the voltage applied to these pins independent of the voltage applied to other CL PD6730 pin groups Table 2 14 CL PD6730 Pin Descriptions continued Description Pin Number Pin Number socket A socket B D 15 0 IOWR WP 101516 Register Access In Memory Card Inter face mode this output chooses between attribute and common memory In Card Interface mode this signal is active low In ATA mode this signal is always high PC Card socket address outputs 102 99 98 176 174 172 O TS 94 92 90 170 168 166 88 85 83 164 161 158 93 95 86 169 171 162 84 97 77 159 173 153 73 80 82 149 155 157 175 178 100 103 181 105 107 183 185 187 109 111 189 191 113 116 PC Card socket data pins 71 69 67 148 145 142 65 63 140 138 124 68 199 144 66 64 62 59 1415139 123 121 119 137 135 198 196 194 Output Enable This output goes active low to indicate a memory read from the PC Card socket to the
220. ess REFRESH This output drives the bus to indicate REFRESH Memory Refresh cycle ROM_KB_CS Combined system BIOS keyboard and chip select output RW_RTC 67 RTC READ WRITE This output should be connected to the RW_RTC input of an 14681 8 type or equivalent RTC SA 23 0 2 SLOT ADDRESS 23 0 These signals decoded from AD 31 0 and BE 3 0 of PCI bus These signals will become 88 11 13 12 84 IOR 2 READ This output to the AT bus indicates an I O Read cycle inputs during ISA master cycles and will be outputs during all other cycles SBHE SLOT BYTE HIGH This output to the AT bus indicates a data transfer on the high byte of the SD bus Table 2 4 V3 LS Pin Descriptions continued PiName Pin no Descripton SD 15 0 157 158 SLOT DATA 15 0 These l Os are the data read and write path 160 164 for the AT bus 166 172 174 175 SMEMR SLOT MEMORY READY This output to the AT bus indicates that a Memory Read cycle is within the lower 1 Mbyte address range SMEMW 7 SLOT MEMORY WRITE This output to the AT bus indicates that a Memory Write cycle is within the lower 1 Mbyte address range SPKR i SPEAKER Speaker data output SYSCLK SYSTEM CLOCK AT bus clock It is derived from BSERCLKV3 and the divisor is selectable by register ATCR 1 bit 2 0 TERMINAL COUNT Signal on the ISA bus indicat
221. ess than 8192 When is held at TTL low level the CPU executes out of external program memory EA is not allowed to float This pin also receives the 12 75V programming supply voltage VPP during EPROM programming Analog to Digital Conversion Reference Resistor Low end Analog to Digital Conversion Reference Resistor High end Analog Ground Analog Power Supply 2 7 NS87336VLJ Super Controller The PC87336VLJ is a single chip solution for most commonly used I O peripherals in ISA and EISA based computers It incorporates a Floppy Disk Controller FDC two full featured UARTs and an IEEE 1284 compatible parallel port Standard PC AT address decoding for all the peripherals and a set of configuration registers are also implemented in this highly integrated member of the Super I O family Advanced power management features mixed voltage operation and integrated Serial Infrared both IrDA and Sharp support makes the 87336 an ideal choice for low power and or portable personal computer applications The PC87336 FDC uses a high performance digital data separator eliminating the need for any external filter components It is fully compatible with the PC8477 and incorporates a superset of DP8473 NEC PD765 and N82077 floppy disk controller functions All popular 5 25 and 3 5 floppy drives including the 2 88 MB 3 5 floppy drive are supported In addition automatic media sense and 2 Mbps tape drive support are provided b
222. fications 1 40 a 1 40 Touchpad Specifications ative ee 1 40 SIR Specifications 1 41 LCD Specifications 1 41 CD ROM 1 42 Diskette Drive 1 42 Hard Disk Drive 1 43 Keyboard Specifications 1 43 1 35 1 36 1 37 1 38 1 39 1 40 2 1 2 3 2 4 2 5 2 6 2 7 2 8 2 9 2 10 2 11 2 12 2 10 2 14 2 15 2 16 2 17 3 1 3 2 3 3 3 4 3 5 4 1 Battery Specifications 1 44 DC DC Converter 1 44 DC AC Inverter Specifications 1 45 AC Adapter Specifications 1 45 Environmental 1 48 Mechanical 1 49 Major Chips 2 1 Descriptions s epe eter e eo te ebbe 2 10 2 5 2 a 2 20 VLS Pin Descriptions I 2 24 NMG2090 Pin Description Conventions 2 32 NMG2090 Pin 2 32 RCV288Aci SVD Signal Type
223. gement is implemented by linking with APM interface closely the APM function Win95 or Win3 1 must be enabled and set to advanced level for optimum power management and the driver that installed in system must be Acer authorized and approved 1 5 7 1 PMU Timers There are several devices related timers available on the V1 LS chip Each timer may have zero or more devices assigned to the timer for the purpose of retriggering the timer Table 1 13 PMU Timers List mem Descrplions Timer value Heuristic time out table 30sec 1min 2min 3min 4min 5min 6min 7min 8min 9min 10min 20min 30min if AC plugged in System activities System activities and timer retriggers The video display CRT and LCD is in power saving mode Timer retriggers KBC PS 2 mouse serial mouse if defined in SETUP will retrigger the timer Table 1 13 PMU Timers List hardware The 77 U24 M2090 55 is from L to H change Modem parallel port COM1 COM2 SIR 5min 30min if AC plugged in System activities System activities and timer retriggers Modem controller is in power saving mode Parallel serial port pins are in standby mode serial port clock is stopped if COM1 4 not defined as a mouse in BIOS Setup and parallel port and UART1 decode in the 87336 chip is disabled Timer retriggers Modem parallel port COM1 COM2 SIR activities Detective hardware Modem The pin 6 of 03 R66
224. gle and linear burst sequences Supports CPU address pipelining and burst read write Supports eight level write buffer for DRAM and PCI cycles Integrated 64 bit write through and write back Level 2 L2 cache controller Direct mapped Supports cache size of 256 Kbytes to 1 Mbyte with 32byte line size Supports synchronous or asynchronous 3 3 V SRAM Internal and external TAG compare Supports 2 1 1 1 burst read and write with 10 ns synchronous 15 ns cycle time SRAM and with 8 ns TAG RAM at 66 2 and 1 1 1 with 10 ns synchronous SRAM and internal TAG compare at 66 MHz One less wait state for read lead off cycle with pipelining Supports S2 2 2 burst write with 17 ns asynchronous SRAM and 15 ns TAG SRAM with internal TAG compare at 66 MHz Intelligent L2 cache power management including stop dock for synchronous SRAMs and TAG chip select for TAGRAM Supports 64 bit 2 way set associative writeback cache with Sony s Sonyc 2WP Built in DRAM controller Mixable 64 or 32 bit DRAM bank support 3 3 and 5 V DRAM support Up to 256 Mbytes of system memory Four banks of 64 bit DRAM or eight banks of 32 bit DRAM Supports 256 Kbit 512 Kbit 1 Mbit 2 Mbit 4 Mbits and 16 Mbit DRAM Support for symmetric and asymmetric DRAM Supports mixed FPM fast page mode and EDO extended data output Slow self refresh support including hidden staggered CAS before RAS refresh or RAS only refresh Dedicated
225. gt gt gt fF Represents text input by the user Denotes actual messages that appear onscreen Represent the actual keys that you have to press on the keyboard NOTE Gives bits and pieces of additional information related to the current topic WARNING Alerts you to any damage that might result from doing or not doing specific actions CAUTION Gives precautionary measures to avoid possible hardware or software problems IMPORTANT Reminds you to do specific actions relevant to the accomplishment of procedures TIP Tells how to accomplish a procedure with minimum steps through little shortcuts Table of Contents Chapter 1 System Introduction 1 1 1 2 1 3 1 4 1 5 INI MM EL nC A a 1 1 1 1 1 1 1 1 1 2 FlashStart Turning the Notebook Computer On and 1 2 1 1 3 POMS 1 3 1 1 4 Automatic Tilt up 1 4 1 1 5 Indicator teda rete Tate dete s 1 5 1 1 6 Keyboard Hotkey List nennen 1 6 System Specification 1 9 Board Layout 2 9 1 11 1 3 1 System Board Top 1 12 1 3 2 System Board Bottom
226. hardware reset LED Output This output can be used as an LED 133 4 driver to indicate disk activity when a socket s BVD2 SPKR LED pin has been programmed for LED support BVD2 SPKR LED pin to reflect disk activity This pin is used for configuration information during hardware reset Serial Clock This input is used as a reference 132 clock 10 100 kHz usually 32 kHz to control the serial interface of the socket power control chips CAUTION This pin must be driven at all times Serial Data System Management Bus Data 131 20r 3 This pin serves as output pin SDATA when used with the serial interface of Texas Instruments TPS22021DF socket power control chip and serves as a bidirectional pin SMBDATA when used with Intel s System Management Bus used by Maxim s Socket power control chip This pin is used for configuration information during hardware reset Serial Latch System Management Bus Clock 130 2 or3 This pin serves as output pin SLATCH when used with the serial interface of Texas Instruments TPS22021DF socket power control chip and serves as a bidirectional pin SMBCLK hen used with Intel s System Management Bus used by Maxim s socket power control chip This pin is used for configuration information during hardware reset Table 2 14 CL PD6730 Pin Descriptions continued Description Pin Number Power This pin is connected to the system s 5 vo
227. he Keyboard 4 7 4 3 Removing or Replacing the CPU 4 9 4 4 a 4 10 4 5 Disassembling 4 11 4 5 1 Detaching the Lower Housing from the Inside Assembly 4 11 4 5 2 Replacing the Hard Disk Drive 4 12 4 5 3 Replacing 4 12 4 5 4 Detaching the Upper Housing from the Inside Assembly 4 14 4 5 5 Removing the 4 15 4 5 6 Removing the Main 4 16 4 5 Disassembling the 4 18 Appendix A Model Number Definition Appendix B Appendix C Appendix D Appendix E Appendix F Appendix G Exploded View Diagram Spare Parts List Schematics BIOS POST Checkpoints Technical Bulletins and Updates Forms 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 1 10 1 11 1 12 1 13 1 14 1 15 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 2 10 2 11 2 12 2 13 2 14 2 15 2 16 2 13 2 14 2 19 List of Figures FlashStart Automatic Power on Switch Lid Switch 1 2 Porites occu UC E UE REI 1 3 indicat r 1 5 System Board 1 12 System Board Bottom 5
228. icates that docking is complete GPIO4 127 GENERAL PURPOSE I O 4 This can also be selected as UNDOCKING general purpose pin Its function can be enabled by index register 352H bit 5 UNDOCKING This pin indicates that undocking has started GPIO5 126 GENERAL PURPOSE I O 54 This can also be selected as THERM general purpose pin Its function can be enabled by index register 352H bits 7 6 THERMAL SENSOR This input allows an external thermal sensor to feed thermal information back to the thermal throttler to regulate the control of heat generated by the CPU LEDO 131 122 See GPIOO LED1 130 121 See GPIO1 and PC 2 0 123 125 POWER CONTROL 2 0 This output provides individual power control for any system component PC3 LEDO 122 POWER CONTROL 3 This output provides individual power control for any system component LED 0 LED indicator output 0 PC4 LED1 121 POWER CONTROL 4 This output provides individual power control for any system component LED 1 LED indicator output 1 control for any system component FRING sas __ RING This input provides wake up modem WAKE 1 0 132 133 WAKE 1 0 These pins request V1 LS to a power up the system and initiate a resume operation if the system was previously in Suspend mode or b cold boot if the system was previously in the Standby mode or was powered down ADOE 195
229. icates that the modem or data set has detected the data carrier The DCD signal is a modem status input The CPU tests the condition of this DCD signal by reading bit 7 DCD of the Modem Status Register MSR for the appropriate serial channel Bit 7 is the complement of the DCD signal Bit 3 DDCD of the MSR indicates whether DCD input has changed state since the previous reading of the MSR NOTE Whenever the MSR DDCD bit is set an interrupt is generated if Modem Status interrupts are enabled Table 2 10 NS87336VLJ Pin Descriptions continued Pm No 10 Desorption DENSEL 48 FDC Density Select DENSEL indicates that a high FDC density Normal Mode data rate 500 Kbs 1 Mbs or 2 Mbs or a low density data rate 250 or 300 Kbs is selected DENSEL is active high for high density 5 25 drives when IDENT is high and active low for high density 8 5 inch drives when IDENT is low DENSEL is also programmable via the Mode command DENSEL 78 FDC Density Select This pin offers an additional Density Select PPM Mode signal in PPM Mode when 0 DIR 41 FDC Direction This output determines the direction of the floppy Normal Mode disk drive FDD head movement active step in inactive step out during a seek operation During reads or writes DIR is inactive DIR FDC Direction This pin offers an additional Direction signal in PPM PPM Mode Mode when PNF 0 FDC Drive Select 0 1 These are
230. ication Vendor amp model name Synaptics 10025 5V No Power supply voltage Location Palm rest center Internal amp external pointing device work simultaneously External pointing device serial PS 2 mouse hot plug Yes if itis enabled in BIOS Setup already X Y position resolution 500 points inch 200 iver Interface PS 2 compatible with Microsoft mouse driver 1 5 20 SIR Table 1 29 SIR Specifications Wem Specification Vendor amp model name TEMIC TFDS3000 Input power supply voltage 115 2 Kbit s 100cm Transfer data rate lt Transfer distance Compatible standard IrDA Infrared Data Association Output data signal voltage level Active Non active Vcc 0 5 15 Angle of operation Number of IrDA ports 16550 UART support Yes SIR location Selectable serial port by BIOS Setup 2F8h IRQ3 Disabled 1 5 21 LCD Table 1 30 LCD Specifications Specification Specification Specification Vendor amp Model Name HITACHI HITACHI IBM ITSV50D LMG9930ZWCC TX30D01VC1CAA supone _________ Supply voltage for LCD display 3 3 typ 3 3 typ 3 3 typ Supply voltage for LCD backlight Vrms 590 typ 2000 max 1500 typ 1 5 22 CD ROM Table 1 31 CD ROM Specifications Wem Specification Vendor amp model name Toshiba XM1402B Internal CD ROM FDD hot swappable BIOS support boot from CD
231. ified then the resume will only happen long enough to evaluate the date and the machine will re suspend After a successful resume has taken place the resume on schedule field will automatically disable Enabling of this field will disable the suspend to disk function except for battery very low The auto disable of resume on schedule still allows the unit to suspend to disk at the next occurrence of a suspend condition with the lid closed 3 Lid switch If the suspend to disk option is used then the lid switch will turn the unit on reboot and then resume to the application at the end of POST If the suspend to memory option is in place or a suspend to disk block is present then the lid switch opening will resume the machine 4 Keystroke Any key use on the internal keyboard will wake up the system from static suspend In addition a keystroke from an external keyboard on the primary PS 2 port will also wake the system up Mouse motion from any source will not wake the system up 5 Battery very low The SMC will wake the SMI if the battery reaches a very low condition during static suspend 1 5 8 CPU Table 1 14 CPU Specifications Speo oP es CPU voltage 3 3V 3 1V 2 9V 2 7V 2 5V 1 5 9 BIOS Table 1 15 BIOS Specifications BIOS ROM size 256KB BIOS ROM package type 40 pin TSOP PCI V2 1 V1 1 E IDE and PnP ESCD format V1 0a Unlock BIOS feature If user changes the BIOS Se
232. ing that a terminal count has reached for a given channel ZERO WAIT This input from the AT bus indicates that the device currently being accessed can complete the cycle with zero wait states AD 31 0 ADDRESS DATA MULTIPLEXED 31 0 These signals are 97 multiplexed on the same pins Each transaction is initiated by a 100 102 32 bit physical address phase which is followed by one or more 105 data phases These bus transactions support both read and 107 110 write bursts 112 114 115 127 129 131 133 136 138 140 141 143 147 C BE 3 0 103 116 COMMAND BYTE ENABLES 3 0 Both are multiplexed on 126 137 the same pins The pins define the Bus Command during the address phase During the data phase the pins are used as Byte Enables DEVSEL DEVICE SELECT As an output it indicates whether Vesuvius is the target of the current address As an input Vesuvius sees whether or not a PCI target exists Table 2 4 V3 LS Pin Descriptions continued PinName Pin _ Descrpton FRAME 117 CYCLE Cycle Frame is driven by the current initiator and indicates the start and duration of the transaction FRAME is deasserted to indicate that the initiator is ready to complete the final data phase A transaction may consist of one or more data transfers between the current initiator and the currently addresses target H PCICLK 9 _ PCICLOCK 33 25 MHz clock fo
233. ingle chip The CRT TFT panels can be driven up to a resolution of 1024x768 NI to provide a wide range of feature selection without redesign NM2090 delivers very high performance using integration and architectural advances The integrated DRAM is configured with a 128 bit wide data path providing very high bandwidth for the CRT LCD BitBLT Video engine and CPU to use The on chip DRAM allows flexible DRAM controls adding into overall performance The integration of the display memory offers lowest power consumption among all implementations of comparable performance and memory capacity NM2090 keeps system designers free of all the issues regarding memory design for performance power EMI radiation and board space The display memory integration provides the lowest chip count solution for space saving and packaging flexibility NM2090 supports 32 bit VL and PCI high performance Buses to interface with the system The PCI interface is designed to be fully compliant with the revision 2 0 PCI specification Both PCI and VL modes support O wait state write burst cycles to ensure fast writes into the graphics subsystem The bus interface can be independently operated at 3 3V 08YLjfcirtXwer savings 2090 incorporates GUI acceleration features to further increase the graphics performance It supports 64 bit BLT for screen to screen and host to screen operations Memory mapped I O and linear addressing allows faster updates into the graphics subsys
234. inimum ordering quantity Table C 1 Spare Parts List 2 Comment Location 2 INVERTER T62 039 C 970 19 20086 001 MICROPHONE 54DB KUC8723 030839 23 42009 001 ASSY LCD PNL 11 3HIT 050 970 ASSY LCD BZL 11 3 050 970 60 46815 011 N ASSY LCD BZL 11 8 050 970 60 46815 001 IC CPU P54CSLM 133 2 9V 01 1 54 03 U1 CHOKE 9UH A 1004 09 19 40116 001 LCDM TX30D01VC1CAA 11 8TFT HIT 56 07355 021 CONN D FML 3R15P RT D0 762 20 20076 015 CONN D SMD 52P RT D0 635 H11 21 A0006 052 CN11 HEADER SMD FML 2R20P ST D2 4S 21 E0004 210 CN19 20 L5 CN6 CN5 CN9 N 0 CONN CTR SMD ML 160P ST D0 5 21 F0009 160 CN12 CONN SMD FML 40P ST 00 5 21 F0010 040 CN18 CONN CTR SMD FML 160P ST 00 5 21 F0010 160 CN8 SKT MINI DIN FML 6P RT SHIELD 22 10021 011 CN15 ray tai 1 27 6 8 6 7 8 6 7 8 9 Table C 1 Spare Parts List SKT PHONE JACK 5P3C 27 SKT PHONE JACK FML 6 4 RT SKT DC 8A 20V TCP7631 01 0201 SW PUSH SPDT 0 05A 48V RT BATTERY LI 3V BR1225 T2V FILTER EMI BNX002 01 50V 10A CABLE ASSY 44P 43MM MAIN BD W O CPU 970 TCP CPU BD 133MHZ 970 DIMM EDO 16MB 3 3V 60NS SIR MODULE TFDS3000 ASSY BRACKET I O 970 SKT IC PLCC 68P SMD SKT DIM
235. inishes reading the file from the FDD the boot ROM will program the whole flash ROM except the boot block area If the flash is successful the FDD motor powers off and the system issues beeps to indicate that the programming has been completed The user then powers off the system to take away the jumper then power up the system to boot from the new BIOS If errors occur during the boot ROM process the system issues a beep sequence see table Table 3 5 Error Beep Sequences During the Boot ROM Process First file size mismatch OF1h 1 long beep 1 short beep File read error OF2h 1 long beep 2 short beeps Flash ROM erase error OE1h 2 long beeps 1 short beep Flash ROM programming error OE2h 2 long beeps 2 short beeps No FDD 0018 2 short beeps When successful the system gives off the following beep sequence 2 long 1 short 1 long CMOS Setup An item Flash New BIOS allows you to flash in a new BIOS When this item is set to Enabled the user needs to issue a hardware reset by pressing the reset button near the module bay near the rear of the system or remove all power to flash the new BIOS The boot ROM will do POST to initialize the necessary components check the FDD and read in the new BIOS binary file the same as method 1 except that when a FDD or BIOS binary file read error occurs the boot ROM will go to POST normal boot After the successful beep sequence sounds the user has to set the Flash New BIOS item back to Disa
236. inning and duration of an access PAR 65 Parity Even parity across AD31 0 amp C BE3 0 is driven by the bus master during address and write data phases and driven by NM2090during read data phases IRDY Initiator Ready This active low signal indicates the bus master s ability to complete the current data phase of the TRDY transaction During a write cycle IDRY indicates that valid STOP data is present on AD31 00 during a read cycle it indicates the master is prepared to accept data Wait states will be inserted until both IRDY and TRDY are asserted together DEVSEL IDSEL BCLK RESET INTA Target Ready This active low signal indicates NMG2 s ability to complete the current data phase of the transaction During a read cycle TRDY indicates that valid data is present on AD 31 00 During a write it indicates NM2090is prepared to accept data Wait states will be inserted until both TRDY amp IRDY are asserted together Stop This active low signal indicates that NM2090is requesting the master to terminate at the end of current transaction m Device Select This active low signal indicates that NM2090has decoded its address as the target of the current access Initialization Device Select This is selected during configuration read and write transactions Bus Clock This input provides the timing for all transactions on PCL bus Reset This active low input is used to initialize NMG2 Interrupt request
237. l the clock after the earlier of or the last BRDY EXTERNAL ADDRESS STROBE This output to the Pentium processor indicates that a valid address has been driven onto the CPU address bus for internal cache snoop cycle 40 FLOATING POINT ERROR This output from the Pentium processor is used for floating point error reporting HITM 51 HITM This input indicates that the snoop cycle hit a modified line in the level 1 cache inside the CPU such that V1 LS should suspend the master operation allow the CPU to evict the modified line then restart the master cycle HLDA 53 HOLD ACKNOWLEDGE This output from the Pentium processor indicates a Hold Acknowledge state HOLD 50 HOLD REQUEST This output to the Pentium processor indicates a Hold Request state Table 2 2 V1 LS Pin Descriptions continued Type _ IGNNE 39 IGNORE NUMERIC This pin indicates that a floating point error should be ignored RST 31 INIT The Pentium processor initialization input forces the Pentium processor to begin execution in a known state The INITNVM RST will typically be asserted when software reset commands are written to either Port 64 or 92 or a shutdown cycle is detected WM RST M1 processor initialization input forces the processor to begin execution in a known state INTR 7 MASKABLE INTERRUPT This pin indicates a maskable in
238. le Clear memory buffer used for POST ul Select boot device e Shutdown 5 e Shutdown A e Shutdown B Appendix F Debug Board Information This appendix shows the model number definition of the notebook PCB No 94359 SC Tool P N F005 022 Tool P N F006 008 Tool P N F005 021 CN18 AN970 main board Ordering contact person Michael Shieh by CC mail Ordering parts information PCB number Tool part Descriptions number 94369 SC soo Notebook debug board1 F005 021 PC Board bridges M B and cable 3 F005 022 PC Board bridges cable and debug board 1 The debug board is same to the one used on AN950 machine Appendix G Forms This appendix contains forms that can help improve Acer service Use these forms whenever necessary F 1 Reader Response Form This form helps gauge the organization the accuracy and the completeness of the manual It tells us if the manual is precise in its conveyance of the pertinent data information and facts concerning the unit F 2 Incoming Inspection Report This form lists all the necessary information regarding the defective unit s the model number invoice number quantity involved It also categorizes the line parameter of the defect whether it is a major defect a minor defect or if it is within the acceptable range of functioning F 3 Field Maintenance Report This form classifies the type of machine failure whether the trouble lies within the mo
239. ll 212A and 103 e V 42LAPM and MNP 2 4 error correction VA2 bis and MNP 5 data compression MNP 10 data throughput enhancement e MNP 10 enhanced cellular performance e Hayes AutoSync option Fax modem send and receive rates up to 14400 bps e V 33 V 17 V 29 V 27 ter and V 21 channel 2 Voice mode Enhanced ADPCM compression decompression Tone detection generation and call discrimination Concurrent detection Business audio mode using 8 bit monophonic audio data encoding at 11 025 kHz or 7200 Hz VoiceView alternating voice and data AVD Simultaneous voice and data over a telephone line using DSVD compatible modems DSVD 8 5 kbps voice coder decoder codec Robust DSVD timing recovery e Handset echo cancellation e Voice silence coding e Decoder adaptive postfilter Full duplex speakerphone e Acoustic and line echo cancellation e Selectable microphone AGC and muting Speaker volume control and muting e Auto fallback to pseudo duplex World class operation option Call progress blacklisting multiple country support Communication software compatible AT command sets NVRAM directory and stored profiles Built in DTE interfaces with speed up to 115 2 kbps Parallel 16550A UART compatible interface Serial CCITT V 24 EIAmA 232 E Supports Rockwell PnP ISA Bus Interface Device Supports Serial PnP interface per Plug and Play External COM Device Specification Rev 1 00
240. lt power 127 PWR supply In systems where 5 volts is not available this pin can be connected to the system s 3 3 volt supply but 5 volt only PC Cards will not be supported CORE_VDD This pin provides power to the core circuitry of the 134 PWR CL PD6730 It must be connected to 3 3 volt power supply CORE_GND All CL PD6730 ground pins should be connected to 26 GND system ground RING GND All CL PD6730 ground pins should be connected 10 14 28 44 57 129 GND system ground 146 163 177 193 RESERVED1 This pin is reserved For future expansion connect 2 this pin to GNT on the PCI bus RESERVED2 This pin is reserved For future expansion connect 3 this pin to REO on the PCI bus RESERVED3 This pin is reserved For future expansion connect 58 this pin to LOCK on the PCI bus 2 9 10643 PCI E IDE Controller 2 9 1 Features e Capable of 16 MB second transfer rates in DMA mode up to 20 MB second PIO mode Supports bus master DMA at 133 MB second PCI burst rate Support PCI DMA transfers for both DMA capable and PIO only drives Fully supports ATAPI DMA PIO transfers 2channels supports up to 4 IDE drives Surpasses and supports Enhanced IDE Mode Mode 4 and propose Mode 5 timing from the widest range of disk drive manufacturers Supports multi word and single word DMA modes 0 1 and 2 Fully supports the latest PCI IDE specification and all the Plug and Play PnP specifications
241. me options Set change or remove a system password The system configuration values reside in the battery powered CMOS RAM 3 2 Entering Setup Press Fn F2 to enter Setup The BIOS Utility main screen displays BIOS Utility About My Computer System Configuration Power Saving Options System Security Reset to Default Settings Tle Move Highlight Bar J Select Esc Exit There are five main menu items About My Computer System Configuration Power Saving Options e System Security e Resetto Default Settings Press T or to move from one menu item to another and press Enter to enter the selected menu Press Esc to exit Setup 3 3 About My Computer About My Computer gives you clear cut information about your notebook PC The following screen is the first of two pages in this section System Architecture System BIOS System ID Processor Coprocessor Internal Cache L1 External Cache L2 Total Memory Bank A Bank B Graphics Controller Display Output Hard Drive 0 Hard Drive 1 Floppy Drive A Floppy Drive B About My Computer MARS 1996 1997 BIOS V2 0 VGA010602 010607 Pentium 133MHz Integrated 16 Enabled 256KB Enabled 16 MB 0 MB 16 MB 128 bit Graphics Acceleration TFT 800x600 Hard Disk CD ROM 1 44 MB 3 5 inch None 5 010023 5 010210 1160 PgDn PgUp Move Screen Esc Exit Press PgDn to view the second p
242. n drain signal to set the charging current limit to a high 3 5A max or low 2A The lower limit is set when the signal is low switch on The system will generally set this signal low when the battery has been discharged to a low level The battery current sensor is built into the charger circuitry The resistance of the drain switch is less than 1 Note this signal sets the limit value of the charging current The CHARGFB and CHARGSP signals may restrict the charging current to a lower level Table 2 16 T62 036 C Pin Descriptions continued Pin name Pn Pinno CHARGON 12 This is a logic level signal active high to enable the adapter current output This signal allows the system board to turn off the charger output whenever the battery pack reports unsafe conditions such as over temperature error or no communication It may be used in response to any other detectable unsafe system conditions 1uA maximum loading CHARGFB 13 This signal is provided by a current sensor in the system to indicate the current drawn from the AC adapter or other power source such as docking station power supply This level is 2 Amps per volt nominal The source impedance is less than 1 CHARGSP 14 Analog input from the system board to limit the total current consumed by the system from the AC adapter This signal shall be compared by the module with the CHARGFB from the system mother board and the battery charger output cur
243. n to access the first of two hidden screens Advanced System Configuration Page 2 3 Internal Cac Enabled Cache Sc Write Back External Cac Enabled Enhanced IDE Features Hard Disk Hard Disk Size 504MB DOS Win3 x Win95 ultiple Sectors Read Write Auto Advanced PIO Mode Auto Hard Disk 32 Bit Access Auto Enhanced IDE Features Hard Disk Hard Disk Size 504MB DOS Win3 x Win95 ultiple Sectors Read Write Auto Advanced PIO Mode Auto Hard Disk 32 Bit Access Auto T Move Highlight Bar lt Change Setting PgDn PgUp Move Screen Fl Help Esc Exit Press PgDn again to access the next hidden screen Advanced System Configuration Page 3 3 Onboard Communication Ports Serial Port Base Address 3F8h IRQ4 IrDA Base Address 2F8h 1803 Modem Base Address 3E8h 1 IRQ Setting 10 Parallel Port Base Address 378h IRQ7 Operation Mode Standard and Bidirectional ECP DMA Channel Onboard Audio Enabled Base Address 240h MPU Base Address 300h IRQ Setting 5 DMA Channel 0 Reset PnP Resources No T Move Highlight Bar lt Change Setting PgDn PgUp Move Screen Fl Help Esc Exit 3 4 6 Internal Cache Internal cache refers to cache built into the CPU When enabled this setting boosts system performance It is also called CPU cache or L1 level one cache The default setting is Enabled The Cache Scheme parameter accepts two values Write Back Write
244. nalog input signal The SPKR is controlled by the ATMn command The SPKR output can drive an impedance as low as 3000 In a typical application the SPKR output is an input to an external LM386 audio power amplifier EYEXY Serial Eye Pattern W Y Output EYEXY is a serial output containing two 15 bit diagnostic words EYEX and EYEY for display on the oscilloscope X axis EYEX and Y axis EYEY EYECLK Serial Eye Pattern Clock EYECLK is a 288 kHz output clock for use by the serial to parallel converters EYESYNC Serial Eye Pattern Strobe EYESYNC is a strobe for loading the D A converters 2 4 3 R6693 14 DTP DigiTalk Processor Chip Pin Diagram S 3 8 255 229899 9995953 99558 aa 8 8258 8 88288 88588 253 79 583 RS2 78 2 RS1 77 VDD3 RSO 76 NC VDD1 75 NC 07 G XTLO 06 73 1 05 52 D4 SLEEPO 03 MUXCTRL p2 DTP AMODEO DigiTalk Processor Do 6 NC WRITE R6693 DGND2 DGND1 AMODE1 RXOUT 017 NC RMODE NC TSTROBE NC TRESET NC DGNDA1 NC NC NC TMODE VDD2 TXDAT 124 NC AVDD NC NC NC AGND1 NC LINEOUT TXA1 READ NC TXA2 CS 1 0602 M TUUUDUUUUUUDUUDUUUUUUUDUDUUD 2222 5829522262 2 5 40 gt 25 gt lt Bo z z Figure 2 12 R6693 14 Pin Diagram Pin Descriptions Table 2 10 R6693 14 Pin Descriptions PinName Pin Pin No Descriptions XTLI XTLO 73 74 Crystal In and Crystal O
245. nd on your hard disk or supplied in the hard disk vendor documentation We suggest that you set this parameter to Auto to allow the BIOS to auto detect the drive parameters at each boot up The Hard Disk 1 parameter is used when a CD ROM drive module or future IDE drive option is installed in the module bay The default setting for both parameters is Auto 3 4 4 Num Lock After Boot When enabled Num Lock turns on after boot and the embedded keypad acts as a numeric keypad The default setting is Disabled 3 4 5 LCD Expansion Mode When enabled the LCD screen shows in expanded mode By default this parameter is set to Disabled For advanced users the System Configuration section has two hidden pages called Advanced System Configuration that allow you to view and configure more technical aspects of the notebook optimum performance and you do not need to access these screens f you do not fully understand the items in these special screens do not attempt to change their values lt gt The notebooks BIOS configuration is already tuned for If you happen to change the values and decide you want to return the previous values select the Reset to Default Settings in the main menu to restore all default values To access the Advanced System Configuration screens press F8 from the main menu Then select System Configuration to enter the System Configuration screens Note that the pages in this section now total three Press PgD
246. ndicates that over 999ms are available to read valid time and date information KB device initialization Set KB led upon setup requests Enable KB device _____ _____ Issue 2nd software SMI to communicate with PMU e Enable the use of BIOS Setup system information and fuel gauge EMIT F Note The FDD LED should flash once and its head should be positioned HDD testing amp parameter table setup Displays POST status if necessary Changes POST mode to default text mode h Initializes ROM Note ROM is an optional extension of the BIOS located on an installed add on card as a part of the subsystem POST detects ROMs and gives them opportunity to initialize themselves and their hardware environment Shadows ROM if setup requests Builds up free expansion ROM table e Initializes PCI Card ROM e Writes ESCD data into NVRAM e Writes ESCD data into NVRAM Ah e Initializes timer counter for DOS use Ah Initializes security feature Enables Enables parity checking Sets video mode ssues 3rd software SMI to communicate with PMU e Starts all power management timers Checks whether system is resumed from suspend or not 68h 70h 74h 78h 7Ch 80h 84h 86h 6Ch 88h 90h 94 96h 97h AOh ACh AEh Table E 1 POST Checkpoint List BOh Power on password checking Display configuration tab
247. nk If this is high then ASO and ASI can be configured to select one of two software address selection techniques Table 2 11 ESS1688W Pin Descriptions continued Pinname Number vo 50 51 24 25 Inputs with internal pull down devices Along with AMODE these inputs select the I O address bank the software address selection technique They should be jumpered to VDDD ASI ASO Function 00 220 base address 01 230 base address 10 240 base address 11 250 base address 00 220 base address 01 Read Sequence Key address selection 10 240 base address 11 System Control Register address selection Because the pulldown devices on these pins are weak in a high noise environment there might be glitching on a floating trace running to an open option switch In such a case either use an external pulldown resistor or a shorting block that goes to either VDDD or GNDD Note when AMODE 0 address inputs 10 and A11 have internal pull down devices When AMODE 1 they do not ASI ASO Function 00 220 base address 01 230 base address 10 240 base address 11 250 base address 00 220 base address 01 Read Sequence Key address selection 10 240 base address 11 System Control Register address selection Because the pulldown devices on these pins are weak in a high noise environment there might be glitching on a floating trace running to an open option switch In such a case either use an extern
248. ns 2 32 Rockwell RCV288Aci SVD Modem 2 42 2 4 1 R6723 12 MCU Microcomputer Chip 2 45 2 4 2 R6684 17 MDP Modem Data Pump 2 49 2 4 3 R6693 14 DTP DigiTalk Processor Chip 2 53 2 5 2 6 2 7 2 8 2 9 2 10 2 11 ESS1688W Sound 2 40000 2 56 2 5 1 Block Diagram iii ri e a e qu mete ees 2 56 2 5 2 2 57 2 5 3 Pin Descriptions Ae ea ee RE 2 58 Philips 87C552 System Management Controller 2 63 2 6 1 Feature a Oed 2 63 2 6 2 Block DIAG CAIN cece cette tate te cele Bae ieee Oreste ee tee ee ee caedes 2 64 2 6 3 Pin Diagram a 2 65 2 6 4 Pin Descriptors tT 2 66 NS87336VLJ Super Controller a 2 68 2 7 1 2 68 2 7 2 Block i aee u aus 2 70 2 7 3 Pin 2 71 2 7 4 Pin Description RE 2 72 CL PD6730 PCI PCMCIA Controller 2 80 2 8 1 Features yu 2 80 2 8 2 EE NAE 2 81 2 8 3 Pin Descriptions
249. o reduce the EMI radiation programmable drives are provided on the panel interface signals to match the drive requirements from the panel manufacturers Simultaneous display on CRT and LCD panel are supported for all types of panels Integrated RAMDAC offers low power and low board space It contains 256X24 word palette for color selection The triple 8 bit DACs run up to 80 MHz at 3 3V NM2090 supports two integrated programmable frequency synthesizers to generate memory and video clock The clock synthesizers can be turned off for power savings VAFC compatible video interface is supported in 16 bit for VL bus and 2 3 1 Features 128 Bit Graphics Acceleration High speed BitBLT Engine Color Expansion e Accelerated Text Hardware Clipping X Y Coordinates Addressing Memory Mapped Up to 2X performance boost over 2070 Video Acceleration Integrated frame buffer for Video and Graphics Color Space Conversion YUV to RGB Arbitrary video scaling up to 8X ratio Bilinear interpolation and Filtering Video Overlay capability from on off screen memory Chroma Key Support Independent Brightness Control for Video Window Mixed color depth Video and Graphics Supports different color depths between video and graphics Supports RGB graphics and video in YUV format in one Integrated frame buffer Memory Support High Speed integrated 128 bit Memory Interface O
250. o a high level A Master Reset operation sets this signal to its inactive high state Loop mode operation holds this signal to its inactive state SIN1 75 67 UARTS Serial Input This input receives composite serial data from SIN2 the communications link peripheral device modem or data set 60 System interrupt 1 2 and 3 This input can be routed to one of the 51 following output pins IRQ3 IRQ7 IRQ9 IRQ12 SIRQ12 and 49 SIRQ13 can be also routed to IRQ15 Software configuration determines to which output pin the input pin is routed to SIRQ1 is multiplexed with IRQ15 SRIQ12 is multiplexed with DRATE1 MSEN1 CSO SIRQ3 is multiplexed with DRV2 PNF DR23 82 Parallel Port Select This input is set high by the printer when it is selected This pin has a nominal 25 KO pull down resistor attached to it 81 Parallel Port Select Input When this signal is low it selects the printer This pin is in a tristate condition 10 ns after a 0 is loaded into the corresponding Control Register bit The system should pull this pin high using 4 7 resistor 73 65 UARTS Serial Output This output sends composite serial data to the communications link peripheral device modem or data set The SOUT signal is set to a marking state logic 1 after a Master Reset operation 95 Parallel Port Data Strobe This output indicates to the printer that a valid data is available at the printer port This pin is in a tristate condition
251. obtained through managing resources not in use Pathological cases of measuring CPU speed or trying to periodically check for reaction time of specific peripherals can detect the presence of power management However in general since the device is trapped and the device managed SMI the power management of devices should be invisible to the user and the application Thermal management is the only overriding concern to the power management architecture By definition thermal management only comes into play when the resources of the computer are used in such a way as to accumulate heat and operate many devices at maximum bandwidth to create a thermal problem inside the unit This thermal problem indicates a danger of damaging components due to excessively high operating temperatures Hence in order to maintain a safe operating environment there may be occasions where we have to sacrifice performance in order to achieve operational safety Heuristic power management is designed to operate and adapt to the user while the user is using it It is the plug and play equivalent for power management There are no entries in BIOS Setup which are required to be set by the user in order to optimize the computers battery life or operation The only BIOS Setup entries are for condition information for suspend resume operations Normal operations and power management are done automatically see chapter 3 BIOS Setup for details Since the power mana
252. ompare addresses from the processor to determine L2 Cache cycles MATCH Match input from external TAG SRAM TAGD1 TAG RAM Data Bit 1 Used to compare addresses from the Pentium processor to determine L2 Cache cycles Input from SONY s Sonic 2WP TAGD2 65 TAG RAM DATA 2 Used to compare addresses from the SONY Pentium processor to determine L2 Cache cycles SONY Output to SONY s Sonyc 2WP TAGD 7 3 60 64 TAG RAM DATA BITS 7 3 Used to compare addresses from the Pentium processor to determine L2 Cache cycles TAGWE 84 0 TAG RAM WRITE ENABLE TAG Data RAM write enable BE 3 0 35 38 E See 3 0 C BE 3 0 150 151 BUS COMMAND BYTE ENABLES 3 0 Both are multiplexed 152 154 on the same PCI pins These pins define the Bus Command during the address phase and are used as Byte Enables during the data phase DEVSEL 159 system memory is the target of the current address As an input V1 LS sees whether or not a PCI target exists FRAME 155 FRAME is driven by the current initiator and indicates the start and duration of the transaction FRAME is deasserted to indicate that the initiator is ready to complete the final data phase A transaction may consist of one or more data transfers between the current initiator and the currently addressed target GNT 3 0 166 169 PCI GRANT 3 0 When the bus arbiter has gr
253. one 8 bit input port two 16 bit timer event counters identical to the timers of the 80C51 an additional 16 bit timer coupled to capture and compare latches a 15 source two priority level nested interrupt structure an 8 input ADC a dual DAC pulse width modulated interface two serial interfaces UART and l C bus a watchdog timer and on chip oscillator and timing circuits For systems that require extra capability the 876552 be expanded using standard TTL compatible memories and logic In addition the 87C552 has two software selectable modes of power reduction idle mode and power down mode The idle mode freezes the CPU while allowing the RAM timers serial ports and interrupt system to continue functioning The power down mode saves the RAM contents but freezes the oscillator causing all other chip functions to be inoperative The device also functions as an arithmetic processor having facilities for both binary and BCD arithmetic plus bit handling capabilities The instruction set consists of over 100 instructions 49 one byte 45 two byte and 17 three byte With a 16MHz 24MHz crystal 5896 of the instructions are executed in 0 75ms 0 5ms and 4096 in 1 5ms 1ms Multiply and divide instructions require 3ms 2ms 2 6 1 Features 80C51 central processing unit 8kx8 EPROM expandable externally to 64k bytes e 3 An additional 16 bit timer counter coupled to four capture registers and three compare registe
254. only Fuel Gauge Up With the fuel gauge onscreen moves the fuel gauge up fend Fuel Gauge Down With the fuel gauge onscreen moves the fuel gauge down Fuel Gauge Left With the fuel gauge onscreen moves the fuel gauge left F gt Fuel Gauge Right With the fuel gauge onscreen moves the fuel gauge right fend CD Eject Ejects the CD ROM drive Turbo Mode On Off Toggles turbo mode on and off 1 1 6 1 Using the Eject Menu Pressing Fn F9 The eject menu brings up the Eject Menu Eject Menu Battery Suspend to Disk CD ROM Disc Also 1 Power Off Also x3 Tl Move Highlight Bar J Select Esc Exit commands allow you to perform various eject related functions for the notebook See the following table for details Table 1 4 Battery CD ROM Disc Power Off Eject Menu Descriptions Change the battery This option forces the notebook to enter suspend to disk mode so that you can replace the battery with a charged one and then return to where you left off To resume close the display lid and open the display lid again Open the CD ROM drive There are many ways to open the CD ROM disc tray selecting this option pressing Fn 1 pressing the CD ROM eject button using software controls It is best to wait for the CD ROM light found on the CD ROM eject button to go off before ejecting the CD ROM drive Turn the system off witho
255. p 64 bit write buffers implemented in the V2 LS device are quad word wide and substantially improve the CPU to memory and the CPU to PCI write performance The VESUVIUS architecture offers a cost efficient interface between the V2 LS and V1 LS devices enabling a single chip implementation of the entire data path control The V3 LS chip completes the VESUVIUS solution for desktop portable systems Its primary function is to act as a bridge between the PCI and the ISA bus The V3 Gs provides interface between the PCI local bus and the industry standard ISA expansion bus It has the logic to support master and slave cycles on both PCI and ISA buses The V3 LS integrates most I O functions such as DMA controllers interrupt controllers programmable interval timer memory mapper and hidden ISA refresh controller found in ISA based personal computers The V3 LS isolates the bus and the ISA bus by providing the data buffers and buffer control logic It has a special serial interface with V1 LS to support power management features including ISA bus device activity detection and other PicoPower proprietary features Additionally the V3 LS supports proven ISA hot warm docking by appropriately tri stating the ISA bus Available in a 176 pin TQFP package the V3 LS chip also contains a highly integrated peripheral controller Features e Optimized three chip system controller solution for Intel s Pentium processors Universal support for AMD
256. r 3F8 3FF COM 1 Serial 1 CF8 CFF PCI configuration register 1 5 4 DMA Channel Table 1 10 DMA Channel Map 0087 Audio default 0083 Audio option ECP 0081 Diskette 0082 Audio option Cascade Cascade 008B 0089 Spare 008A N N N N 1 5 5 GPIO Port Definition Map Table 1 11 GPIO Port Definition Map PC0 1 Enable the clock source VS5_CLKEN PC1 Suspend control reserved VS5_SUSPEND PC2 1 Turn off the speaker VS5_SPKOFF 1 Video clock enable 55 VDCLKEN PC4 1 Power down the video controller in suspend mode VS5_VDPD PC5 0 Disable VGA controller from PCI VGADIS GPO LEDO 1 Flash ROM recover 55 FLASHRCY GP1 LD1 SUSPA Cache sleep VS5 ZZ GP2 DDMA RETRY DDMA distributed DMA retry V3 LS activates this pin to retry V85 DDMARETRY V1 LS GPS3 SUPPRESS RESUME Modem address 1 2E8h 0 3E8h VS5_COM4_COM3 GP4 UNDOCKING 1 Flash ROM Vpp Control VS5_FLSHVPP GP5 THRM 1 over temperature alarm from SMC SM5_OVTMP REQ2 0 Dock undock request used to tri state PCI bus before PC3_DKREQ dock undock Table 1 11 GPIO Port Definition Map GNT2 PC5_DKGNT WAKEO KB5_KBCSMIREQ WAKE1 RT5_IRQ8 SWITCH 55 DOCKIRQ RING VS5 RI amp EXTACTO GR3 VGACT LEDO KB5_KBCSMIREQ LED1 KB5_NUMLED LED2 KB5_CAPLED Description 0 Dock grant signal for ready to dock undock 0 Keyboard SMI from KB
257. r The modes are AMODE Receive Input Transmit Output Via 1 0 Function tothe Y tothe DAA X 00 Microphone Record Microphone Input TXA from 01 Sound Chips from DAA SCOUT from sound chips 10 5 from LINEOUT from DTP 11 Data FaxVoice BA PLXAfromDAA TXA from Record Conversation EN85 Enable 85 Bus Connect to GND PWR ND READ 1 5 Read Enable Connect to the MCU external bus READ line i DF Table 2 10 R6693 14 Pin Descriptions continued PinName Pin Pin No Descriptions SLEEPI IA 36 Sleep Connect to the DTP SLEEPO pin and to MCU SLEEPI pin VC 39 Low Voltage Reference Connect to analog ground through 10 pF polarized terminal to VC and 0 1uF ceramic in parallel VREF 40 High Voltage Reference Connect to VC through 10 pF polarized terminal to VREF and 0 1uF ceramic in parallel SR1IO SR1IO Connect to DTP TMODE amp RMODE and to the MCU TMODE and RMODE pins TMODE D 23 Transmitter Mode Connect to Transmitter Mode Connect to DTP 58110 RMODE D Receiver Mode Connect to DTP SR1IO SR31N D SR3IN Connect to DTP RXOUT RXOUT D 17 Receive Data Out Connect to DTP SR31N SR4OUT 9 SRA4OUT Connect to DTP TXDAT TXDAT Di 24 Transmit Data In Connect to DTP SRAOUT 50 IACLK Connect to DTP CLKIN and to MCU CWN CLKIN
258. r state The state where the system is put into lower power mode is termed static suspend suspend to memory System thermal alarm System thermal rating is obtained by the a thermal sensor aside charger and signaled by the 64 5 5 THERM SYS of SMC Full charge to battery is only available when the system temperature is less than 56 while trickle charge higher than 58 C System shutdown will be automatically executed while temperature is higher than 85 1 5 7 3 Suspend There are two forms of suspend and resume on the notebook static suspend suspend to memory and zero volt suspend suspend to disk Zero volt suspend is as the name implies an OFF condition The entire computer state is saved to a disk file and the computer is turned off In static suspend all components are placed into an idle state and the clocks are stopped to the entire machine except for the 32 kHz clock for memory refresh In either case all separate components in the system are put into their lowest power state at the start of either suspend process 1 Devices turned off The HDD except for suspend to disk since the file goes there CD ROM floppy are turned off at the start of any suspend 2 Devices brought to a low power state The modem audio serial port transceiver MAX213 SIR keyboard controller PCMCIA controller chip will be put into a low power state instantly through a pin asserting or prematurely expiring the device timer 3
259. r Dynamic mode for lowest power consumption Programmable Suspend mode Five programmable memory windows per socket Two programmable windows per socket ATA disk interface support Mixed voltage operation 3 3 5 0 V Supports low voltage Card specification 200 pin PQFP 2 8 2 Pin Diagram 8 8 8 3 2 8 2 b SL 2095 8 55 95 55 98 g s Uo nO plo aR 1349 28 3 2 ze a e 8 88 8558555858885 59090 822 ee ecco M omic EAT Xu B A13 lt A SOCKET VCC 102 m ve B_SOCKET_VCC 101 RING_GND 8 18 4 100 B A14 99 m A A24 RING GND 98 SOCKET 8 18 97 AA T 96 23 B 20 4 95 a Hh 15 8 ROY IREQ 94 21 4 93 A A16 16 4 92 B 2 A_RDY IREQ B A23 4 89 WE B A12 88 ja A A19 8 A24 57 RING GNO 7 4 B6 pm A A14 8 25 4 85 A18 RING GND 84 lt s _ 17 _VS2 4 B SOCKET VOC CL PD6730 LAS a B RESET 79 ut 208 Pin PQFP or mE L Mom 2 B_ WA
260. r the PCI bus H_PCIRST 154 PCIRESET V3 LS reset input IDSEL 104 ID SELECT ID Select for PCI interrupts IRDY 118 INITIATOR READY This indicates the bus master s state of readiness to complete the current data phase During a write IRDY shows that valid data is present During a read it indicates the bus master s readiness to accept data IRDY is used in conjunction with TRDY PCI 152 1 PCI LOCK Used for locking ISA resources PAR PARITY All PCI agents require parity generation PCI INT D A amp 148 151 PCI INTERRUPTS 0 These inputs from PCI devices are shareable level sensitive active low interrupt request They can be mapped to ISA IRQx through registers PINTM 1 and PINTM 2 PERR PARITY ERROR This input indicates a data parity error It may be pulsed active by any agent that detects an parity error condition SERR 123 SYSTEM ERROR This input may be pulsed active by any agent that selects any system error condition STOP 121 This allows the master to stop the bus transaction to the current target device TRDY 119 TARGET READY This indicates the ability of the target device to complete the current data phase of the bus transaction During a read phase TRDY indicates that the valid data is present During a write phase it indicates that the device is prepared to accept data kus 132 152 159 173 7 2 3 NM2
261. rammable Chip Select 50 1 are programmable chip select and or latch enable and or output enable signals that can be used as game port expand The decoded address and the assertion conditions are configured via the 87336VLJ s configuration registers UARTS Clear to Send When low this indicates that the modem or data set is ready to exchange data The CTS signal is a modem status input The CPU tests the condition of this CTS signal by reading bit 4 CTS of the Modem Status Register MSR for the appropriate serial channel Bit 4 is the complement of the CTS signal Bit 0 DCTS has no effect on the transmitter CTS2 is multiplexed with A13 When it is not selected it is masked to 0 NOTE Whenever the MSR DCTS bit is set an interrupt is generated if Modem Status interrupts are enabled Data These are bidirectional data lines to the microprocessor DO is the LSB and D7 is the MSB These signals have a 24 mA sink buffered outputs DACKO DMA Acknowledge 0 1 2 These active low inputs acknowledge DACK1 the DMA request and enable the RD and WR inputs during a DMA DACK2 transfer It can be used by one of the following FDC or Parallel Port If none of them uses this input pin it is ignored If the device which uses on of this pins is disabled or configured with no DMA this pin is also ignored DACKO 1 2should be held high during I O accesses DCD1 DCD2 UARTs Data Carrier Detect When low this ind
262. re CD ROM power up and is deasserted after CD ROM power up and before the buffer is enabled Floppy The floppy has two components involved in the process The floppy drive and the controller imbedded in the 87336 super chip The enable disabled function is controlled by 87336 chip In power saving mode there are following condition happened to floppy drive 1 External pin tri state Enabled whenever the floppy is turned off This control signal is same to CD ROM buffer enable pin pin 35 KB5 CDBEN of please see CD ROM portion for details 2 PLL disabled Disabled whenever the floppy and both serial channels are inactive or disabled 3 FDC power disable Disables the active decode of the floppy unit This control signal is same to CD ROM power control pin 30 SM5 CD FDPON of SMC please see CD ROM portion for details Video The video controller has two interfaces for controlling power consumption The sleep mode is controlled by software and is performed by BIOS calls The suspend operation is controlled by 55 VDPD signal pin 121 of V1 LS The video timer is not controlled or retriggered by video activity Instead the timer is retriggered by mouse and keyboard activity to detect activity to the video itself This pin is used as a speed up The video chip does have an activity pin pin 75 ACTIVITY used event for the CPU and the determination of software suspend Serial port The serial port
263. rea of the 87336 chip are less critical Also if the floppy is operated through the parallel port the parallel port must be enabled to allow operation to continue 1 Disable the parallel port decode Modem The modem is comprised of several chips and several clocks independent of the system clocks for the fax modem and the voice over capabilities There are only two control lines pin 56 SM5_MODEN and pin 43 SM5_MODPON of SMC and one software interface for the power controls on the modem The modem chip set cannot be actively power managed If the modem is enabled through BIOS Setup then the S24 register is used to control the power consumed by the modem If BIOS Setup is set to disable the modem then the modem enable and modem power pins are used to remove the modem from the circuit entirely Modem Enable A master enable pin pin 56 SM5 of SMC can be asserted to stop the decode and therefore the selects of the modem chip This line is used exclusively in cases of modem power off conditions Modem power enable This pin pin 43 SM5_MODPON of SMC will control the power to all of the modem chips Once powered down the modem chip set has no means of recovery except through full software initialization Audio The audio chip has an internal power down mode available This is done through a self timer However this self timer has two possible configurations When the self timer expires the digital section will po
264. rent adjusted until CHARGFB does not exceed CHARGSP The system board generates CHARGESP in conjunction with a ID resistor embedded in the LCD cable The scale is 2 amps per volt The source impedance is less than 2 Note The battery charger output may be reduced below the level of CHARGESP by the battery charger current limit signal CHARGECL CHRGOUT 17 18 Battery charger current source output at 3 5A max The output 19 20 current is controlled by two control signals which limit the battery charging current and AC adapter output current The output voltage is limited to 13 2V 13 5V P12VR 12 12V output 0 0 5 ibi 16 P3VR 567 8 3 3V output 0 3A BMCVCC 11 13 5V output 0 0 5 Used for resuming from suspend to memory mode PVRON o 12 Enables P3VR Logic level Active high IuA max loading o 14 Enables PSVR Logic level Active high 4 max loading P5VR 17 18 5V output 0 2 5A 19 20 2 11 Ambit T62 039 C T62 055 C DC AC Inverter This notebook has two kinds of DC AC inverter One T62 039 C is designed for HITACHI LMG9930ZWCC and TX30D01VC1CAA LCD use the other T62 055 C is for ITSV50D LCD use 2111 Pin Diagram T62 039 C AAEE as CNB ase ee CN3 T62 055 C CN Figure 2 21 T62 039 C T62 055 C Pin Diagram 2 11 2 Pin Descriptions Table 2 17 T62 039 C T62 05
265. resistor attached to it Printer Not Floppy PNF is the Printer Not Floppy pin when bit 2 of FCR is 1 It selects the device which is connected to the PPM pins A parallel printer is connected when PNF 1 and a floppy disk drive is connected when PNF 0 This pin is the DRV2 input pin when bit 2 of FCR is 0 Read Active low input to signal a data read by the microprocessor FDD Read Data This input is the raw serial data read from the floppy disk drive FDD Read Data This pin supports an additional Read Data signal in PPM Mode when PNF 0 Table 2 10 NS87336VLJ Pin Descriptions continued Pm No ro Desorption RI1 70 62 UARTs Ring Indicator When low this indicates that a telephone RI2 ring signal has been received by the modem The RI signal is a modem status input whose condition is tested by the CPU by reading bit 6 RI of the Modem Status Register MSR for the appropriate serial channel Bit 6 is the complement of the RI signal Bit 2 TERI of the MSR indicates whether the RI input has changed from low to high since the previous reading of the MSR NOTE When the TERI bit of the MSR is set and Modem Status interrupts are enabled an interrupt is generated RTS1 74 66 UARTs Request to Send When low this output indicates to the RTS2 modem or data set that the UART is ready to exchange data The RTS signal can be set to an active low by programming bit 1 RTS of the Modem Control Register t
266. rs Two standard 16 bit timer counters 256x8 RAM expandable externally to 64k bytes e Capable of producing eight synchronized timed outputs e A10 bit ADC with eight multiplexed analog inputs e Two 8 bit resolution pulse width modulation outputs Five 8 bit I O ports plus one 8 bit input port shared with analog inputs C bus serial port with byte oriented master and slave functions e Full duplex UART compatible with the standard 80C51 On chip watchdog timer Speed ranges 16MHz Extended temperature ranges package available 2 6 2 Block Diagram PWMO PWMT AVss ADC07 SDA SCL T1 TWO 16 BIT PROGRAM SERIAL TIMER EVENT MEMORY Pc PORT COUNTERS E ROM 80C51 CORE EXCLUDING ROM RAM PARALLEL SERIAL FOUR PORTS AND UART 16 CAPTURE EXTERNAL BUS PORT LATCHES CTOI CT3I CMSRO CMSR5 AST EW CMTO CMT1 9 ALTERNATE FUNCTION OF PORTO 3 ALTERNATE FUNCTION OF PORT 3 1 ALTERNATE FUNCTION OF PORT 4 ALTERNATE FUNCTION OF PORT 4 ALTERNATE FUNCTION OF PORT 2 5 ALTERNATE FUNCTION OF PORT 5 Figure 2 15 87C552 Block Diagram 2 6 3 Pin Diagram P4 3 CMSR3 P4 4 CMSR4 P4 5 CMSR5 P4 6 CMTO P4 7 CMT1 RST P1 0 CTOI P1 2 CT2l 1 1 4 2 P1 5 RT2 P1 6 SCL P1 7 SDA P3 0 RxD P3 1 TxD P3 2 INTO 0 ADCO 1 ADC1 2 ADC2 3 ADC3 4 ADC4 5
267. s During the address phase of a transaction C BE 3 0 are interpreted as the bus commands During the data phase C BE 3 0 are interpreted as byte enables The byte enables are to be valid for the entirety of each data phase and they indicate which bytes in the 32 bit data path are to carry meaningful data for the current data phase Cycle Frame This input indicates to the CL PD6730 that a bus transaction is beginning While is asserted data transfers continue When FRAMEZ is deasserted the transaction is in its final phase Initiator Ready This input indicates the initiating agent s ability to complete the current data phase of the transaction IRDY is used in conjunction with TRDY Stop This output indicates the current target is requesting the master to stop the current transaction Initialization Device Select This input is used as a chip select during configuration read and write transactions This is a point to point signal The CL PD6730 must be connected to its own unique IDSEL line from the PCI bus arbiter or one of the high order AD bus pins Device Select The CL PD6730 drives this output active low when it has decoded the PCI dress PC as one that it is programmed to support thereby acting as the target for the current PCI cycle Table 2 14 CL PD6730 Pin Descriptions continued Pin Name Description 0 PERR Parity Error The CL PD6730 drives this input
268. s continued PinName Pin Type Pin No Deseptions RLY4 70 Relay 4 Control EARTH When MCU port is enabled as a relay driver the active low RLY4 output be used to control the normally open earthing relay W class This port can also be used to drive the AMODE1 mux control line LCS 1 Loop Current Sense 5 is an active high input that indicates a handset off hook status RINGD 1 91 Ring Frequency A rising edge on the RINGD input initiates an internal ring frequency measurement The RINGD input from an external ring detect circuit is monitored to determine when to wake up from sleep mode The RINGD input is typically connected to the output of an optoisolator or equivalent The idle state no ringing output of the ring detect circuit should be low SPKROUT TXA1 NC TXA2 MIC RIN VREF SLEEPI RXDAT TXDAT TMODE RMODE CLKIN Speaker Analog Output The TXA1 and TXA2 outputs are differential outputs 180 degrees out of phase with each other The output characteristics are the same as a 1458 type OP amp 1 is used as a single ended output SPKROUT to an external amplifier in the audio interface circuit 2 is not connected open Low Voltage Reference Connect to analog ground through a 10 pF polarized terminal to VC and a 0 1 pF ceramic in parallel High Voltage Reference Connect to VC through 10 pF polarized terminal to VREF
269. s is an active low signal driven by the video system to drive P15 PO into NM2090chip Video system should provide a pull up on this signal If driven inactive NM2090will drive P7 PO lines with Pixel Data Status 15 8 VAFC pixel data input pins These pins are only used in 16 bit VAFC modes These data pins connect to NM2090from the VAFC compatible interface Table 2 6 NMG2090 Pin Descriptions continued PinName Type Pinno _ BDeseptions VCLK 168 Video Clock Pixel clock driven from the video system to NM2090chip It s used as a reference to the data and other line DCLK 147 Dot lock This is the reference clock driven by NM2090to the video system BLANK 146 BLANK This active low output indicates that NM2090is currently in the blanked region VSYNC Vertical SYNC NM2090will drive the vertical sync signal to the video system on this pin The polarity of the vertical sync will depend on the VGA mode selected HSYNC Horizontal SYNC NM2090will drive the horizontal sync signal to the video system on this pin The polarity of the horizontal sync will depend on the VGA mode selected MTEST 87 Memory Test This active low signal is used for internal memory testing This should be tied high for normal system operation BUSSEL 88 Bus Select This pin is used to define the host bus interface type 1 VESA VL bus 0 PCI bus CLKRUN 145 Clockrun The master device will control this signal to the NMG2 according to th
270. s the disassembly flow 4 quiessesiq Remove LCD bazel x2 11 3 or 11 8 LCD x2 12 1 LCD Rs Remove Open Release two Release the Detach speaker covers SIMM x1 FDD screws hinge 4 LCD on both sides door CD ROM 4 connector x2 and one center latches hinge cover Remove the Y pn unit of x7 Remove Y 3 ower case i M2 5L6 bind head the lower 7 Slide and unit of open the M2 5L8 p Y keyboard lower case battery door Remove the 5 Remove the upper unit of PC board lower case set 4 2 Removing the Module If you are going to disassemble the unit it is advisable to remove the module first before proceeding Follow these steps to remove the module 1 Slide out and hold the module release button 2 Press the module release latch and slide out the module Module Release Button Figure 4 4 Removing the Module Removing the Keyboard 4 3 Follow these steps to remove the keyboard Slide out the two display hinge covers on both sides of the notebook 1 Removing the Display Hinge Covers Figure 4 5 Pull out first from the edges and remove the center hinge cover 2 lt 24 lt gt 0 250
271. sactions Qo Interrupt A This is used to request an interrupt in PCI IDE Native Mode INTA is tristated when both IDE port are in Legacy Mode INTA IRDY IRQ14 IRQ15 Initiator Ready This indicates the initializing agent s bus master s ability to complete the current data phase of the transaction This signal is used with TRDY A data phase is completed on any clock when both IRDY and TRDY are sampled asserted Wait cycles are inserted until both IRDY and TRDY are asserted together IRQ14 This is used to request an interrupt PCI IDE legacy Mode for PC AT compatibles IRQ14 is tristated when IDE port 0 is in Native Mode IRQ15 This is used to request an interrupt PCI IDE legacy Mode for PC AT compatibles IRQ15 is tristated when IDE port 1 is in Native Mode Parity PAR is even parity across AD 31 0 and 3 0 Parity generation is required by all PCI agent PAR is stable and valid one clock after either IRDY is asserted on write transaction or TRDY is asserted on a write transaction or TRDY is asserted a read transaction Once PAR is valid it remains valid until one clock after the completion of the current data phase PAR has the same timing as ad 31 0 but delayed by one clock Table 2 15 PCIO643 Signal Descriptions continued Signa Pin Type Description Clock Signal This signal provides timing for all transaction on PC
272. scillator circuit RESET 1 59 Reset RESET low holds the in the reset state RESET going high releases the modem from the reset state and initiates normal operation using power turn on default values RESET must be held low for at least 3 us The modem is ready to use 400 ms after the low to high transition of RESET VDD1 VDD3 11 36 41 Digital Supply Voltage Connect 5V 5VA PWR 21 5V Analog Supply Voltage Connect to VCC through a decoupling circuit DGND1 GND 10 19 40 Digital Ground Connect to digital ground DGND5 43 55 AGND 1 22 30 Analog Ground Connect to analog ground AGND2 Centerpoint Voltage Connect to analog ground through 10 pF polarized terminal to VC and 0 1 pF ceramic in parallel Voltage Reference Connect to VC through 10 pF polarized terminal to VREF and 0 1 pF ceramic in parallel 00 08 IA OB 9 15 Data Lines Connect to the MCU external bus DO D7 lines 16 68 17 respectively 67 18 0 4 1 20 66 63 Register Select Lines Connect to the MCU external bus 0 4 lines respectively READ jo Read Enable Connect to MCU external bus READ line WRITE Write Enable Connect to MCU external bus WRITE line Chip Select Connect to DPSEL from the MDP DTP chip select decode logic OA 8 interrupt Request Connect to MCU DPIRQ ron _ o Comectio RESET 2
273. signal in PPM Mode PPM Mode when PNF 0 See PE WGATE 38 FDC Write Gate This output signal enables the write circuitry of the Normal Mode selected disk drive WGATE has been designated to prevent glitches during power up and power down This prevents writing to the disk when power is cycled WGATE 82 FDC Write Gate This pin gives an additional Write Gate signal in PPM Mode PPM mode when PNF 0 WP 36 FDC Write Protect This input indicates that the disk in the selected Normal Mode drive is write protected ANP 92 FDC Write Protect This pin gives an additional Write Gate signal in PPM Mode PPM mode when PNF 0 ANR 18 Write An active low input to signal a write from the microprocessor to the controller ANRITE 95 EPP Write Strobe This signal is used in EPP mode as write strobe It is active low X1 OSC Crystal1 Clock One side of an external 24 MHz 48 MHz crystal is attached here If a crystal is not used a TTL or CMOS compatible clock is connected to this pin Crystal 2 One side of an external 24 MHz 48 MHz crystal is attached here This pin is left unconnected if an external clock is Zero Wait State This pin is the Zero Wait State open drain output pin when bit 6 of FCR is 0 ZWS is driven low when the EPP or ECP is written and the access can be shortened 2 8 CL PD6730 PCI PCMCIA Controller The CL PD6730 is a single chip PC Card host adapter solution capable of controlling two fully independent
274. sor SUSP This output indicates a suspend request to Cyrix M1 CPU Sus m Table 2 2 V1 LS Pin Descriptions continued Pin _ Descrpon W R 44 WRITE READX This is a cycle definition input from the processor indicates whether the current cycle is a write or a read cycle It is one of the primary bus cycle definition pins W is driven valid in the same clock as ADS and the cycle address It remains valid from the clock in which ADS4 is asserted until the clock after earlier of or the last BRDY WB WT 48 WRITE BACK_WRITE THROUGH This output to the processor allows a data cache line to be defined as write back or write through on a line by line basis s SSCS CASA 3 0 COLUMN ADDRESS STROBES 13 0 GROUPS A AND In 5 3 0 64 bit bank mode CASA 3 0 corresponds to BE 3 0 and CASB 3 0 corresponds to BE 7 4 In 32 bit bank mode CASA 3 0 outputs drive the CAS inputs on DRAM bytes to 0 in even banks banks 0 2 4 6 and odd banks banks 1 3 5 7 DRMWE co DRAM WRITE ENABLE This output drives write enable for all DRAM 1 0 102 103 MEMORY ADDRESSES 11 0 These outputs drive MA lines for 105 106 all DRAM They are also used as RC RESET configuration inputs 108 109 during power up 111 112 114 115 117 118 RAS 3 0 84 85 ROW ADDRESS STROBES 3 0 These outputs drive the RAS
275. st Bus Data Lines 0 7 HDO HD7 are comprised of eight three state input output lines providing bidirectional communication between the host and the MCU Data control words and status information are transferred over HDO HD7 HCS Host Bus Chip Select HCS input low enables MCU host bus interface HRD Host Bus Read HRD is an active low read control input When HCS is low HRD low allows the host to read status information or data from a selected MCU register HWT When HCS is low HWT low allows the host to write data or control words into a selected MCU register HINT Host Bus Interrupt HINT output is set high when the receiver error flag received data available transmitter holding register empty or modem status interrupt is asserted HINT is reset low upon the appropriate interrupt service or master reset operation Host Bus Write HWT is an active low write control input RLY1 PEO RLY3 PE2 Relay 1 Control OH MCU port PEO is assigned to the RLY1 output signal The active low RLY1 output can be used to control the normally open off hook relay The PULSE function is also provided on this line for single OH PULSE relay application Relay 3 Control MUTE When MCU port PE2 is enabled as a relay driver the active low RLY3 output can be used to control the normally open mute relay W class This port can also be used to drive the AMODEO mux control line Table 2 8 R6723 12 Pin Description
276. stem POST reads the shutdown code stored in location OFh in CMOS Then it jumps around the initialization procedure to the appropriate entry point 04h Determines if the current booting procedure is from cold boot press reset button or turn the system on from warm boot press b or from exiting BIOS setup Note At the beginning of POST port 64 bit 2 8042 system flag is read to determine whether this POST is caused by a cold or warm boot If it is cold boot a complete POST is performed it is a warm boot the chip initialization and memory test is eliminated from the POST routine The CMOS shutdown byte verification assures that CMOS OFh area is fine to execute POST properly Initializes CMOS default setting Initializes RTC time base Note The RTC has an embedded oscillator that generates 32 768 KHz frequency To initial RTC time base turn on this oscillator and set a divisor to 32768 so that RTC can count time correctly DRAM type determination FPM or EDO type e DRAM sizing 32 64 bit Memory Accessing 2Ch Tests 128K base memory Note The 128K base memory area is tested for POST execution The remaining memory area is tested later Table E 1 POST Checkpoint List Tests keyboard controller 8041 8042 Determines keyboard type AT XT PS 2 then write default command byte upon KB type Detects whether keyboard U is depressed from system powered on till POST or not
277. tem also supports color expansion Clipping X Y Coordinates Addressing Text Acceleration hardware cursor and icon To accelerate video playback under Graphical User interface GUIs such as Windows95 The NM2090 has Color Space Conversion Horizontal and Vertical Scaling and Filtering built in the hardware to accelerate video overlay on the graphics screen Both alpha key and color key are supported for overlay control NM2090 is packaged in a low profile 176 pin TQFD package NM2090 supports complete power management features to reduce the graphics subsystem power and increase the battery life of the portables The core of NM2090 is always running at 3 3V to reduce the power consumed All of the interface including bus panel and VAFC can be operated independently at 3 3V or SV This allows designers a glueless mixed voltage systems Different power saving modes are supported under hardware or software controls NM2090 internally Switches off clocks that are not in use to reduce the power transparently Also sections of the chip such as DAC can be shut down to save power A wide range of VGA and SVGA panels are supported The panel interface can be selected for 3 3V or SV Frame rate control and dithering techniques are used for gray scales display Vertical and horizontal expansion and centering of video displays are supported on all the LCD panel resolutions Text mode contrast is enhanced using foreground background technique In order t
278. terrupt C to the Pentium processor KENZ INV rr This output to the Pentium processor indicates that the current cycle is cacheable INV This pin indicates a request to invalidate the processor cache line This output can also be used as INV output during snoop cycles If this function is not used CPU s INV pin should either be pulled high or connected to M IO MEMORY INPUT amp This cycle definition signal is one of the main pins that define the bus cycle It distinguishes a memory access from an I O access This signal is driven valid in the same clock as ADS and the cycle address It remains valid from the clock in which ADS is asserted until the clock after earlier of or the last BRDY 46 NEXT ADDRESS indicates to the Pentium processor that V1 GS is ready to accept a new bus cycle NMI NON MASKABLE INTERRUPT This pin indicates that an external non maskable interrupt has been generated 30 SYSTEM MANAGEMENT INTERRUPTH This output triggers a system management interrupt and is used to invoke the SMM system management mode SMIACT 55 SYSTEM MANAGEMENT INTERRUPT This input from the Pentium processor indicates that the CPU is operating In SMM Assertion of SMIACT enables remapping of SMRAM to physical DRAM at 000A0000 000BFFFF region STPCLK 20 STOP This output indicates stop clock request to SUSP Intel s Pentium and AMD s K5 proces
279. the decoded drive select outputs that are controlled by Digital Output Register bits DO D1 The Drive Normal Mode Select outputs are gated with DOR bits 4 7 These are active low outputs They are encoded with information to control four FDDs when bit 4 of the Function Enable Register FER is set DRO exchanges logical drive values with DR1 when bit 4 of Function Control Register is set FDC Drive Select 1 This pin offers an additional Drive Select signal PPM Mode in PPM Mode when PNF 0 It is drive select 1 when bit 4 of FCR is It is drive select 0 when bit 4 of FCR is 1 This signal is active FDC Drive 2 or 3 DR23 is asserted when either Drive 2 or Drive 3 is assessed except during logical drive exchange DRATEO 52 51 FDC Data Rate 0 1 These outputs reflect the currently selected DRATE1 FDC data rate bits 0 and 1 in the Configuration Control Register Normal Mode CCR or the Data Rate Select Register DSR whichever was written to last The pins are totem pole buffered outputs 6 mA sink 6 mA source DRATEO 87 FDC Data Rate 0 This pin provides an additional Data Rate signal PPM Mode in PPM mode When PNF 0 56 DMA Request 0 1 2 An active high output that signals the DMA 33 controller that a data transfer is required This DMA request can be 4 sourced by one of the following FDC or Parallel Port When it is not sourced by and of them it is in TRI STATE When the sourced device is disabled or wh
280. the shorting of any de output Load range w load A Load range w load V Voltage ripple noise max mV 1 5 28 DC AC Inverter DC AC inverter is used to generate very high AC voltage then supply to LCD CCFT backlight use The DC AC inverter area should be void to touch while the system unit is turned on Table 1 37 DC AC Inverter Specifications Specification Vendor amp Model Name Ambit T62 039 C 00 Ambit T62 055 C 00 Used LCD type HITACHI LMG9930ZWCC IBM ITSV50D HITACHI TX30D01VC1CAA Output voltage Vrms with load 450 550 650 typ Output current mArms with load 1 5 4 5 1 5 29 AC Adapter Table 1 38 AC Adapter Specifications item Specification Vendor amp Model Name EOS ZVC70NS 18 5 Nominal voltages Vrms 90 264 Nominal frequency Hz 47 63 Inrush current A 30 264 Efficiency 86 18V 3 6A output and 230Vac input Output power W mmn 36 max Hold up time 3 ms min 115 Vac input Short circuit protection Output can be shorted without damage Primary to secondary 3000 Vac for 1 minutes Leakage current 250 max 1 CISPR 55022 and CISPR55014 class B 230Vac and 115Vac requirements Scandinavia 2 47 CFR Part15 class B 115Vac with of margin USA epin Parallel CRT Serial PCMCIA Ext Keyboard Port Port Port 2x Type ll or PS2 mouse RJ11 Modem port P54C
281. therboard the video board the controller the storage devices or elsewhere t also lists the quantity percentage defect of the shipment to the distributor 4 Problem Report Forms The attached forms are for the user to explain any problem that may occur with an Acer product Acer engineers can better understand the problem through the feedback of the user whether electrical mechanical or electronic in nature Use of these forms saves time and effort in the repair process AcerNote 970 Reader Response Form Dear Reader At Acer documentation is not viewed as a necessary evil the contrary documentation support like product reliability and performance has always been viewed as a potentially decisive factor for market success Because documentation is important we want to know what you think about our manuals Please tell us by filling out and returning this Reader Response Card Thanks for your help Company Name Name Occupation Title Address Telephone Fax No Years of computer experience 1 How do you rate this manual Effectiveness s it organized so you can find things easily Are the index and table ot contents easy to use Are topics complete accurate and useful Excellent Good Fair Poor Table of Contents Index Organization Accuracy Completeness Writing and Layout 15 the writing clear and easy to understand 15 the tone friendly or patronizing Does the technical level match your needs
282. tic Stick on Connector With Locks Connectors mentioned in the following procedures are assumed to be no lock connectors unless specified otherwise 4 1 3 Disassembly Sequence The disassembly procedure described in this manual is divided into four major sections Section 4 2 gt Removing the module Section 4 3 X Removing the keyboard Section 4 4 Removing the hard disk drive Section 4 5 Disassembling the inside assembly frame Section 4 6 Disassembling the display The following table lists the components that need to be removed during servicing For example if you want to remove the motherboard you must first remove the keyboard then disassemble the inside assembly frame in that order Table 4 1 Guide to Disassembly Sequence Install CPU Remove the keyboard Remove the keyboard Remove two speaker covers on both sides and one center hinge cover Remove or replace the hard disk drive Remove the lower unit of lower case Install additional memory SIMM socket 1 Remove the lower unit of lower case SIMM socket 2 Remove the SIMM door Remove the touchpad 1 Remove the keyboard 2 Remove the LCD display module 3 Remove the upper unit of lower case Replace the LCD Remove the LCD display module Remove the motherboard for service 1 Remove the keyboard or replacement 2 Remove the LCD display module 3 Remove the lower unit of lower case The following diagram detail
283. ting pad CN17 Left speaker connector CN21 Battery connector CN18 Debug port CN23 Right speaker connector PAD19 Keyboard type setting pad Swi Reset Switch PAD20 BIOS type setting pad Figure 1 11 Mainboard Jumpers and Connectors Bottom Side Table 1 6 Mainboard Jumpers Pads Settings Bottom Side Jumper Pad Descriptions PAD19 Keyboard type selection Open Other keyboard Short Japan keyboard PAD20 BIOS type selection Open Acer BIOS Short OEM BIOS PAD21 Password settings Open Enable password Short Bypass password CN17 CN18 lp CN6 CN5 CN2 4 CN7 switch CN5 Touchpad connector CN6 LCD connector CN4 CN2 Keyboard connector Figure 1 12 Media Board Jumpers and Connectors Side 10 CN8 CN9 CN10 CN8 Mainboard connector CN9 PCMCIA socket connector Figure 1 13 Media Board Jumpers and Connectors Bottom Side 1 5 System Configurations and Specifications 1 5 1 Memory Address Map Table 1 7 Memory Address Map 0A0000 128 KB video RAM Reserved for graphics display buffer 0000 Duplicate of code assignment at OE0000 0FFFFF 1 5 2 Interrupt Channel Map Table 1 8 Interrupt Channel
284. tion P4 3 SM5 UNDOCK GNTZ Undock grant to docking station P4 4 SM5 ICONT Charge current control 0 4mA normal charge 1 2mA over 65 or battery energy is very low 7 PSTsUEMS _ Ps2 6m5 ACPWRGD ACsouree powergood gral Notebook powergood Psa sms THERM ceU CPU mermar ratnom P5 7 SM5 ACIN MAIN 1 Main AC adapter is connected o o Sus CONT PWMO SM5 BRIT LCD brightness 1 5 6 PCI Devices Assignment Table 1 12 PCI Devices Assignment PCI VGA AD19 Device 9 INTA Video IIT VPIC AD20 Device INTB V3 LS AD21 Device V2 LS AD22 Device C INTA 1 5 7 Power Management Power Management in this design is aimed toward the conservation of power on the device and system level when the devices or system is not in use This implies that if any device is detected as not active for a sustained period of time the device will be brought to some lower power state as soon as practicable With the exception of thermal management if a device has a demand upon it full performance and bandwidth will be given to that device for as long as the user demands it Power management should not cause the user to sacrifice performance or functionality in order to get longer battery life The longer battery life should be
285. ts as its power switch Simply put opening the display wakes up the notebook closing the display puts it to sleep The When Lid is Closed parameter determines which suspend mode the notebook enters when the display is closed There are two settings for this parameter Suspend to Memory 9 Suspend to Disk With this parameter set to Suspend to Memory the notebook enters suspend to memory mode saving all data into memory when you close the display or press the suspend hot key Fn Esc 77 The notebook wakes up when you open the display or press any key With the parameter set to Suspend to Disk the notebook enters suspend to disk mode saving all data into the hard disk when you close the display The notebook wakes up when you open the display again If an external monitor is connected to the notebook the notebook will not enter suspend mode if you close the display To enter suspend mode disconnect the monitor plug open the display and close the display again when it is run If the file becomes invalid the notebook will be unable to enter suspend to disk mode and enters suspend to memory mode gt The Sleep Manager automatically creates a suspend to disk file 3 5 2 Suspend to Disk on Critical Battery With this parameter set to Enabled the notebook enters suspend to disk mode when the battery becomes critically low The default setting is Enabled 3 5 3 Display Always On This parameter lets you specify
286. tup setting and causes the system cannot boot press before system turns on till POST completed then system will load BIOS Setup the default Boot block is an area inside of BIOS with the program for system boot Avoid this area to be modified while BIOS flash then system still can boot even the BIOS flash process is not successful x sms 1 1 5 10 System Memory Table 1 16 System Memory Specifications Specification SIMM package 144 pin Small Outline Dual In line Memory Module soDIMM 1 5 10 1 SIMM memory combination list Table 1 17 SIMM memory combination list 1 5 11 Cache Memory Table 1 18 Cache Memory Specifications item Specification Cache enabled disabled control SRAM package Cache enabled disabled control 1 5 12 Video Memory Table 1 19 Video Memory Specification _____ Specification Memory size 1 1MB Memory location Inside of graphic controller NMG2090 1 5 13 Video Display Modes Table 1 20 Video Display Specification 1 5 13 1 External CRT Resolution Modes Table 1 21 External CRT Resolution Modes Resolution x Color CRT Refresh Rate Simultaneous Simultaneous on Ext CRT on TFT LCD on STN LCD 1 5 13 2 LCD Resolution Modes Table 1 22 LCD Resolution Modes 1 5 14 Audio Table 1 23 Audio Specifications Specification Chipset Audio onboard or optional Mono or stereo Resolution Mixed sound sources Voice
287. ut Connect to an external 49 92 MHz fundamental or third overtone crystal circuit RESET Reset After application of 5V power RESET must be held low for at bast 15 ms after the 5 power reaches operating range The DTP is ready to use 25 ms after the low to high transition of RESET The reset sequence initializes the DTP interface memory to default values VDD1 VDD3 6 58 77 5V Digital Supply Voltage Connect to Vcc AVDD VAA1 25 35 5V Analog Supply Voltage Connect to VCC through VAA2 45 decoupling circuit DGND1 DGND5 GND 16 66 Digital Ground Connect to digital ground 80 81 97 DGNDA 1 3 G 21 30 Analog Ground Connect to analog ground AGND 1 2 42 27 37 D0 D7 IA OB 14 7 Data Lines Connect to the MCU external bus 00 07 lines respectively 0 4 5 1 Register Select Lines Connect to the MCU external bus 0 4 lines respectively CS 52 Chip Select Connect to SPSEL output from be MDP DTP chip select decode logic WRITE 15 Write Enable Connect to MCU external bus WRITE line 28 Line Out Analog Output The LINEOUT is a single ended output to the telephone line through the hybrid circuit The LINEOUT output can drive a 3000 load LINEIN 38 Line In Analog Input The LINEIN is a single ended input from the audio interface AMODEO SP2 OA 69 65 Audio Mode Select single ended output to the audio AMODE1 SP3 interface circuit typically through a 74HC4052 analog multiplexer demultiplexe
288. ut entering suspend to disk mode When you choose this option a cold boot occurs after re starting the system opening and closing the display You can choose this option when you want to swap modules or when you want to turn off the notebook without entering any of the suspend modes To turn the notebook back on close the display lid and open the display lid again 1 2 System Specification Overview Table 1 5 Specifications Standard r Optional Mobile Intel Pentium processor 133 150MHz Memory System 16MB Expandable to 64MB using 8 16 32 Dual 64 bit memory banks soDIMMs External cache 256KB L2 cache synchronous SRAM 512KB L2 cache System BIOS 256KB Boot Block Flash ROM Storage system One 2 5 inch high capacity Enhanced IDE Higher capacity E IDE hard disk hard disk One high speed IDE CD ROM drive module One 3 5 inch 1 44MB floppy drive module internal external use Display DualScan STN or active matrix TFT LCD Up to 1024x768 256 color ultra VGA 800x600 64K colors SVGA monitor LCD projection panel Video system PCI local bus video with 128 bit graphics accelerator Audio system 16 bit stereo audio with built in FM synthesizer Built in microphone and dual angled speakers Communications Built in V 34 fax data modem 28 8Kbps PC card modem system with digital simultaneous voice over data DSVD support Operating Windows 95 DOS and Windows 3 x O
289. ver 400MB s memory bandwidth Bus Support POCILocal Bus Zero wait states VESA VL Bus Zero wait states 3 3Volts 5Volts operation Hardware Cursor and Icon 64 X 64 Hardware Cursor 64 X 64 or 128 X 128 Hardware Icon Green PC Support VESA Display power Management DPMS DAC Power Down modes Suspend Standby Clock management VGA disable support Mobile Computing clockrun support Resolution and Color Support e VGA TFT DSTN CRT 85Hz 640 X 480 256 64k 16M e SVGA TFT DSTN CRT 85Hz 800X600 256 64 Supports 800x600x64K colors DSTN panels in a single chip XGA TFT CRT 75Hz 1024 X 768 256 Colors 64k Colors on XGA panels Simultaneous CRT Flat Panel operation Display Enhancements 24Bit Integrated RAMDAC with Gamma Correction 24bit TFT panel support Hardware expansion for low resolution display mode compensation to panels e Virtual Screen Panning Support e Integrated Dual Clock Synthesizer VESA DDCI and DDC2b Enhanced VAFC Input Port 2 3 2 Pin Diagram 8888 oooo 9999 8 gt 253538 555555552 SS P BARBA Og lt lt lt 0 lt lt lt lt lt lt lt 9 950 8 23 85532330555552202 22295507002 00 25220 f 29 05858 8389588 591505585 ee ee ee ee LT NM2090 8 LLLI
290. wer down and conserve power There is an option to power down the analog section as well If the analog section is power down with the timer then CD music played directly from the CD to the audio port will be unavailable Similarly any playback through the line in will be ignored CPU STPCLK signal Assertion of the STPCLK pin 20 STPCLK SUSP of V1 LS signal will stop the clock to the core of the CPU This line can be modulated to allow the CPU to achieve a simulated lower clock rate The STPCLK signal only affects the CPU core The internal cache and the bus handshake are still active when the STPCLK signal is asserted The CPU clock The clock to the CPU can be physically stopped The chip is static so the current state is retained During a clock stop state the CPU is stopped and the internal cache and external bus signals are inoperative Therefore any bus master or DMA activity is halted as well CPU thermal alarm Thermal alarm is signaled by the assertion of the one control pin pin 126 5 5 OVTMP of V1 LS will trigger a lower speed operation through clock throttling while the CPU temperature is higher than 80 C shut down the system while higher than 95 C The system returned to normal condition while the CPU temperature is lower to 75 C System The system can also be put into low power state However this state can only be performed after the individually power managed components have achieved their low powe
291. x5 ED ADI B Di PD6730 02 8 05 ADS 806 877 ADS ADB 809 07 010 6 30 ADB ADS B Di A DIO 8 013 ADI BDM ADI2 806 013 pes BRESET PM DIS ARESET BVSI WATE BVS2 A NPACK 10 NPACKE 4 BWPHOISIG lt 4 B ORD BA BOR AWPHOSIG WP 4 78 A ORD 4 BWE AJOWR 4 DEL ABVDI STSCHG BVOT 4 8 02 ABVD2 SPKR 1 4 S RERO 4 n 4 2 4 91 H 160 12 e PME 4 1 2 1 2 PADOS 180 Z x 1 200 mo 0 m 5 133 38 1 128 78 6132 200 80 rn 573 a TTA 7 100 16 72 OF 16V OF CONFIDENTIAL 6 lt 5 1 A A A Al AJA Al A A A AJA Al AJA Al A Al Al D D D D D po Df ol D ol o o ol D 01121314667 9t 1 1 1 1 1 1 11 1 2 2 2 212 2 2 2 2 2 3 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 67 8 9 0 1 PAS SER LATCH 5 5 IRE 6 4 4 ACER ADVANCED LABS Title PROJECT MARS MULTIMEDIA Size Document Number PCMCIA CONTROLLER Date 15 1996 Sheet 3 of 14 00 15 3
292. ximum load is 3000 output impedance gt 100 AC output voltage range is 2 2Vp p DC offset voltage is 20 and reference voltage is 2 5Vdc 2 4 1 R6723 12 MCU Microcomputer Chip Pin Diagram MCU AMODE1 RLY4 PE2 AMODE0 RLY3 Micro Computer TREAD R6723 Figure 2 10 R6723 12 Pin Diagram Pin Descriptions Table 2 8 R6723 12 Pin Descriptions PinName Pin Type Descriptions XTLI IE Crystal Clock In and Crystal Out Connect to an external XTLO OE 14 7456 MHz crystal circuit RES1 IC MCU Reset The active low RESn input resets the MCU RES2 IA x logic and restores the saved configuration from NVRAM or returns the modem to the factory default values if NVRAM is not present Resin low holds the modem in the reset state RESET going high releases the modem from the reset state After application of 5V RESn must be held low for at least 15 ms after the 5V power reaches operating range The modem device set is ready to use 25 ms after the low to high transition of RESn DPIRQ la MDP Interrupt Request Connect to the MDP IRQ output VDD1 VDD2 2 5V Digital Supply Voltage Connect 5V AVDD P5VD 5V Analog Supply Voltage Connect to VCC through a VAA1 P5VT decoupling circuit VAA2 PSVR GND4 GND7 ul Digital Ground Connected digital ground GND1 GND3 Analog Ground Connect to analog ground STPMODE Stop Mode Connect to through
293. y mode at the specified Resume Date and Resume Time settings Enabling this option overrides the suspend to disk function 3 5 9 Resume Date Resume Time The Resume Date and Resume Time parameters let you set the date and time for the resume operation The date and time fields take the same format as the System Date and Time parameters in the System Configuration screen If you set a date and time prior to the time of suspend this field is automatically disabled A successful resume occurring from a date and time match also automatically disables this field 3 6 System Security The following screen is the system security screen input the password before entering the System Security gt If password is currently present the system prompts you to screen System Security Page 1 1 Supervisor Password User Password Disk Drive Control Diskette Drive Hard Disk Drive Start Up Sequences Flash New BIOS Normal Normal A then C Disabled Tl Move Highlight Bar lt lt Setting Fl Help Esc Exit Press T or to move from one parameter to another and or gt to change parameter settings Most of the parameters are self explanatory but you can press F1 to get help on the selected parameter Press Esc to exit the screen and return to the main menu 3 6 1 Supervisor and User Passwords The supervisor and user passwords both prevent unauthorized access to the notebook When these
294. y the FDC The UARTSs are fully NS16450 and NS16550 compatible Both ports support MIDI baud rates and one port also supports IrDA s the HP SIR and Sharp SIR compliant signaling protocol The parallel port is fully IEEE 1284 level 2 compatible The SPP Standard Parallel Port is fully compatible wit ISA and EISA parallel ports In addition to the SPP EPP Enhanced Parallel Port and ECP Extended Capabilities Port modes are supported by the parallel port A set of configuration registers are provided to control the Plug and Play and other various functions of the PC87336 These registers are accessed using two 8 bit wide index and data registers The ISA 1 address of the register pair can be relocated using a power up strapping option and the software configuration after power up When idle advanced power management features allows the PC87336 to enter extremely low power modes under software control The PC87336 can operate from a 5V or a 3 3V power supply An unique cell structure allows the PC87336 to interface directly with 5V external components while operating from a 3 3V power supply 2 7 1 Features 100 compatible with ISA and EISA architectures Floppy Disk Controller e Software compatible with the DP8473 the 765A and the N82077 16 byte FlFO disabled by default e Burst and Non Burst modes e Perpendicular Recording drive support e New high performance internal digital data separator no external filt

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