EVBUM2057 - Evaluation Board User`s Manual for High Frequency
Contents
1. DOCE 0805 CHIP 0805 CHIP CAPACITOR EXPANDED BOTTOM VIEW CAPACITOR EXPANDED BOTTOM VIEW 0 01 uF EP40 0 01 uF N EP40 Shak Option 1 Internal Termination Resistor Option 2 External Termination Resistor Figure 9 Configuration 4 Table 6 Configuration 4 Device EP40 Options 1 8 2 E SEENE AKI ERE EA MISS REIN ELE LC IEEE ee ER EEE EC EAR IE ER ER Option 1 Internal Termination Resistor Configuration comer e Yes ves ves ve T es T es ves vs s Wo No Tes ves vs Ts No Tes No E essor mo No No No We m no we we wo we mo ne ves n Grd No no mo no rd Gra No Ves No ves wo No ne no ves Ne vec Option 2 External Termination Resistor Configuration Connector No ves ves ves ves ves ves ves ves You wo no Na vos ves vos es No ves wo messo No No No ves Yes ves Yor No no mo wo No Na No No No No No no We Power Vee No No Ne Ne No Ne No Wo No vee No Voc No no No No Ves No oc http onsemi com 9 ECLTSSOP20EVB SMA CONNECTORS tr A IE OG o q gi SO BANANA JACK PLUG NORMAL TOP VIEW EP56 LVEP56 PIN 1 0603 CHIP CAPACITOR 0 01 uF 402 CHIP ESISTOR 50 Q 0805 CHIP CAPACITOR 0 01 uF EXPANDED BOTTOM VIEW EP56 LVEP56 Figure 10 Configuration 5 Table 7 Configuration 5 Device EP56 and LVEP56 gt e e 2 o c c fo o S see v h2. e Qu 4 v oj o n 2 Q e b g tog amp y 3 j g j N J Wo j Se J N o N p E 6 a O A A Y A A A Q e gt A z Poy Third Layer Power and Ground Plane Left side Voc Right side Vee Middle Box Ground eva DS 20227 493 A HIV O VIA E008 FHAM Or Bottom Layer Figure 15 Gerber Files http onsemi com 16 ECLTSSOP20EVB ON Semiconductor and Q are registered trademarks of Semiconductor Components Industries LLC SCILLC SCILLC reserves the right to make changes without further notice to any products herein SCILLC makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does SCILLC assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation special consequential or incidental damages Typical parameters which may be provided in SCILLC data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts SCILLC does not convey any license under its patent rights nor the rights of others SCILLC products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to suppor
3. ECLTSSOP20EVB Evaluation Board User s Manual for High Frequency TSSOP 20 INTRODUCTION ON Semiconductor has developed an evaluation board for the devices in 20 lead TSSOP package These evaluation boards are offered as a convenience for the customers interested in performing their own engineering assessment on the general performance of the 20 lead TSSOP device samples The board provides a high bandwidth 50 Q controlled impedance environment Figures 1 and 2 show the top and bottom view of the evaluation board which can be configured in several different ways depending on device under test see Table 1 Configuration List This evaluation board manual contains e Information on 20 lead TSSOP Evaluation Board Assembly Instructions Appropriate Lab Setup Bill of Materials ON Semiconductor hitp onsemi com EVAL BOARD USER S MANUAL This manual should be used in conjunction with the device data sheet which contains full technical details on the device specifications and operation Board Lay Up The 20 lead TSSOP evaluation board is implemented in four layers with split dual power supplies see Figure 3 Evaluation Board Lay Up For standard ECL lab setup and test a split dual power supply is essential to enable the 50 Q internal impedance in the oscilloscope as a termination for ECL devices The first layer or primary trace layer is 0 008 thick Rogers RO4003 material which is designed to have eq
4. ELE K EO EE ERU EA K NDR KES ES OE oves ves ve Ys vs es ves ves vor fies vs No Ys Ys ve ves or vor e e Resor _ re e e ne ne No we we we we we ves ve ve 00 ves ves 00 ve No Bower no io ne ho No No wo No re no vee n Ro 10 no No Ne vec No voc http onsemi com 6 ECLTSSOP20EVB SMA CONNECTORS O 0603 CHIP CAPACITOR J1 0 1 uF BANANA JACK PLUG NORMAL TOP VIEW EP17 LVEP17 0603 CHIP PIN 1 CAPACITOR 0 01 uF 4 0402 CHIP RESISTOR 50 Q EE 1100000 TJ Sm 0805 CHIP CAPACITOR EXPANDED BOTTOM VIEW 0 01 uF EP17 LVEP17 Figure 7 Configuration 2 Table 4 Configuration 2 Device EP17 and LVEP17 mop ete ei p epp Semester we ves ve vs ves ves ves vor vee vs 00 Pee we rover us http onsemi com 7 ECLTSSOP20EVB SMA CONNECTORS 0603 CHIP S O CAPACITOR J19 0 1 uF BANANA JACK PLUG NORMAL TOP VIEW EP29 0603 CHIP PIN 1 CAPACITOR 0 01 uF 0402 CHIP MRE RESISTOR 50 Q 0805 CHIP CAPACITOR EXPANDED BOTTOM VIEW 0 01 uF EP29 Figure 8 Configuration 3 Table 5 Configuration 3 Device EP29 Power se e No ne hitp onsemi com 8 ECLTSSOP20EVB SMA 0603 CHIP CONNECTORS O O en SR 0 1 uF BANANA JACK PLUG 0603 CHIP 0603 CHIP NORMAL TOP VIEW CAPACITOR EP40 CAPACITOR 0 01 uF PIN 1 0 01 uF PIN 1 0402 CHIP RESISTOR 50 Q WIRE
5. he appropriate input of the device pin pads and the ground pads For ease of assembly it is advised to place and solder termination resistors on its vertical side position instead of its original or flat position Installing the SMA Connectors Each configuration indicates the number of SMA connectors needed to populate an evaluation board for a given configuration Each input and output requires one SMA connector Attach all the required SMA connectors onto the board and solder the connectors to the board on J1 through J20 Please note that alignment of the signal connector pin of the SMA can influence the lab results The reflection and launch of the signals are largely influenced by imperfect alignment and soldering of the SMA connector Validating the Assembled Board After assembling the evaluation board it is recommended to perform continuity checks on all soldered areas before commencing with the evaluation process Time Domain Reflectometry TDR is another highly recommended validation test http onsemi com 5 ECLTSSOP20EVB CONFIGURATIONS SMA CONNECTORS 0603 CHIP S o CAPACITOR J19 0 1 uF BANANA JACK PLUG NORMAL TOP VIEW EP14 LVEP14 0603 CHIP PIN 1 CAPACITOR 0 01 uF WIRE 0402 CHIP RESISTOR 50 Q 0805 CHIP CAPACITOR 0 01 uF EXPANDED BOTTOM VIEW EP14 LVEP14 Figure 6 Configuration 1 Table 3 Configuration 1 Device EP14 and LVEP14 Ei ai EA KA EAKR E ELS OK KAN EE ET ELA EN a KES
6. mple schematics are located in Figures 6 through 12 Place SMA connectors on J1 through J20 50 Q chip resistors between ground pad and Pin 1 pad through Pin 20 pad and chip capacitors C1 through C5 according to configuration figures C4 and C5 are 0 01 uF and C1 C2 and C3 are 0 1 uF See Figure 5 http onsemi com 2 ECLTSSOP20EVB Top View aj unuunu 111111 ECL TSSOP 20 EVB REV C VER A 10 MAR 2003 so Bottom View Figure 4 Evaluation Board Layout http onsemi com 3 Pin 20 Pin 19 Pin 18 Pin 17 Pin 16 Pin 15 Pin 14 Pin 13 Pin 12 Pin 11 ECLTSSOP20EVB Ground Figure 5 Enlarged Bottom View of the Evaluation Board Table 1 Configuration List eee come Bem http onsemi com 4 Pin 1 Pin 2 Pin 3 Pin 4 Pin 5 Pin 6 Pin 7 Pin 8 Pin 9 Pin 10 ECLTSSOP20EVB Evaluation Board Assembly Instructions The 20 lead TSSOP evaluation board is designed for characterizing devices in a 50 Q laboratory environment using high bandwidth equipment Each signal trace on the board has a via which has an option of placing a termination resistor depending on the input output configuration see Table 1 Configuration List Table 11 contains the Bill of Materials for this evaluation board Solder the Device on the Evaluation Board The soldering can be accomplished by hand soldering or soldering re flow techniques Make sure pin 1
7. of the device is located next to the white dotted mark and all the pins are aligned to the footprint pads Solder the 20 lead TSSOP device to the evaluation board Connecting Power and Ground Planes For standard ECL lab setup and test a split dual power supply is required enabling the 50 Q internal impedance in the oscilloscope to be used as a termination of the ECL signals VrT Vcc 2 0 V in split power supply setup VIT is the system ground Vcc is 2 0 V and Vgg is 3 0 V or 1 3 V see Table 2 Power Supply Levels Table 2 Power Supply Levels Connect three banana jack sockets to Vcc VEE and GND labeled holes Wire bond the appropriate device pin pad on the bottom side of the board to Vcc and VEE power stripes Device specific please see configuration for each desired device See Figure 5 It is recommended to solder 0 01 uF capacitors to C4 and C5 to reduce the unwanted noise from the power supplies C1 C2 and C3 pads are provided for 0 1 uF capacitor to further diminish the noise from the power supplies Adding capacitors can improve edge rates reduce overshoot and undershoot Termination All ECL outputs need to be terminated to VTT VIT Vcc 2 0 V GND via a 50 Q resistor 0402 chip resistor pads are provided on the bottom side of the evaluation board to terminate the ECL driver More information on termination is provided in AN8020 Solder the chip resistors to the bottom side of the board between t
8. sentative EVBUM2057 D Mouser Electronics Authorized Distributor Click to View Pricing Inventory Delivery amp Lifecycle Information ON Semiconductor ECLTSSOP20EVB
9. t or sustain life or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application Buyer shall indemnify and hold SCILLC and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part SCILLC is an Equal Opportunity Affirmative Action Employer This literature is subject to all applicable copyright laws and is not for resale in any manner PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT N American Technical Support 800 282 9855 Toll Free ON Semiconductor Website www onsemi com Literature Distribution Center for ON Semiconductor USA Canada P O Box 5163 Denver Colorado 80217 USA Europe Middle East and Africa Technical Support Order Literature http www onsemi com orderlit Phone 303 675 2175 or 800 344 3860 Toll Free USA Canada Phone 421 33 790 2910 VP Fax 303 675 2176 or 800 344 3867 Toll Free USA Canada Japan Customer Focus Center For additional information please contact your local Email orderlit onsemi com Phone 81 3 5817 1050 Sales Repre
10. ttp onsemi com 10 ECLTSSOP20EVB PIN 1 0603 CHIP CAPACITOR J1 NORMAL TOP VIEW EP57 BANANA JACK PLUG 0603 CHIP CAPACITOR 0 01 uF SMA CONNECTORS a I O N o I RESISTOR 0805 CHIP CAPACITOR 0 01 uF EXPANDED BOTTOM VIEW EP57 Figure 11 Configuration 6 Table 8 Configuration 6 Device EP57 o g O c c o O http onsemi com 11 ECLTSSOP20EVB 0603 CHIP CAPACITOR J1 NORMAL TOP VIEW EP139 BANANA JACK PLUG SMA CONNECTORS PIN 1 0603 CHIP CAPACITOR 0 01 uF 0402 CHIP RESISTOR 50 Q 0805 CHIP CAPACITOR EXPANDED BOTTOM VIEW EP139 0 01 uF Figure 12 Configuration 7 Table 9 Configuration 7 Device EP139 o g o c c o O Resistor http onsemi com 12 ECLTSSOP20EVB LAB SETUP Power Supply Vcc GND Vee Test Measuring Differential Equipment Signal hannert Generator Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 Channel 7 Channel 8 Trigger Figure 13 Example of Standard Lab Setup Configuration 1 1 Connect appropriate power supplies to Vcc VEE 2 Connect a signal generator to the input SMA and GND connectors Setup input signal according to the For standard ECL lab setup and test a split dual device data sheet power supply is required enabling the 50 Q 3 Connect a test measurement device on the device internal impedance in the oscilloscope to be
11. ual electrical length on all signal traces from the device under the test DUT to the sense output The second layer is the 1 0 oz copper ground The FR4 dielectric material is placed between second and third layer and between third and fourth layer The third layer is the power plane Vcc amp VEE and a portion of this layer is a ground plane The fourth layer is the secondary trace layer Figure 1 Top View of the 20 lead TSSOP Evaluation Board Semiconductor Components Industries LLC 2012 January 2012 Rev 2 Publication Order Number EVBUM2057 D ECLTSSOP20EVB Bottom View alli lli LITTTITITIL lt oO o Expanded Bottom View Figure 2 Bottom View of the 20 lead TSSOP Evaluation Board LAY UP DETAIL 4 LAYER SILKSCREEN TOP SIDE LAYER 2 GROUND PLANE P1 1 OZ ZZZ aoon ZZZ LAYER 3 GROUND VCC amp VEE PLANE P2 1 OZ _FR 40 025in LAYER 1 TOP SIDE 1 OZ ROGERS 4003 0 008 in Y 0 062 0 007 LAYER 4 BOTTOM SIDE 1 OZ Figure 3 Evaluation Board Lay up Board Layout The 20 lead TSSOP evaluation board was designed to be versatile and accommodate several different configurations The input output and power pin layout of the evaluation board is shown in Figures 4 and 5 The evaluation board has at least eight possible configurable options Table 1 list the devices and the relevant configuration that utilizes this PCB board Lists of components and si
12. used output SMA connectors as a termination of the ECL signals VT Vcc NOTE The test measurement device must contain 50 Q 2 0 V in split power supply setup Vrr is the termination system ground Vcc is 2 0 V and VEE is 3 0 V or 1 3 V see Table 10 Table 10 Power Supply Levels NGN http onsemi com 13 ECLTSSOP20EVB Table 11 Bill of Materials SMA Connector Johnson SMA Connector Side 142 0701 851 http www johnsoncomponents com Components Launch Gold Plated Banana Jack Keystone Standard Jack 6096 http www keyelco com Chip Capacitor Johanson 0603 0 01 uF 500R14Z100MVAE http www johansondielectrics com Dielectric 0805 0 01 uF 500R15Z100MV4E 0603 0 1 uF 250R14Z101MV4E Chip Resistor Panasonic 0402 50 Q 1 Precision ERJ 2RKF49R9X http www panasonic com Think Film Chip Resistor Evaluation Board ON Semiconductor TSSOP 20 Evaluation Board ECLTSSOP20EVB http www onsemi com Device Samples ON Semiconductor TSSOP 20 Package Device http www onsemi com Components are available through most distributors i e www newark com www digikey com http onsemi com 14 ECLTSSOP20EVB Top View Second Layer Ground Plane Figure 14 Gerber Files http onsemi com 15 ECLTSSOP20EVB E e o amp E d f T amp 4 N A Aw 6 6 Ja OS Pd SX gt SO lt d K N gt O se e e N A N 1 coco 00091 J voli Cool
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