Arria II GX FPGA Development Kit User Guide
Contents
1. 1 1 Hardware px REDI a pir 3 da dde edes 1 1 Software PEE 1 1 Quartus II Subscription Edition Software 2 1 2 Arria GX FPGA Development Kit Installer 2 1 2 Chapter 2 Getting Started Before You Begin oce oer ehe dte repe e epit ab haunt ne eae 2 1 Inspectthe Board eeri exem ls e ds sh ususqa a ua pk pe RES LE Da kaa 2 1 References aote perta Aces tes alba m denis ound Mewes adt s 2 2 Chapter 3 Software Installation Installing the Quartus II Subscription Edition Software 3 1 Licensing Considerations uuu usasapa e ee nnn 3 1 Installing the Arria GX FPGA Development 3 2 Installing the USB Blaster Driver ssssseesseeeeee I nnn 3 3 Chapter 4 Development Board Setup Setting Up the eR rer ee eA d ecce ga id 4 1 Factory Default Switch Settings etry ses aa sii Te enn 4 2 Chapter 5 Board Update Portal Connecting to the Board Update Portal Web Page rnern 5 1 Using the Board Update Portal to Update User Designs 5 2 Chapter 6 Board Test System Preparing the Board i e emen ke oh e hag E IE RE eee saa 6 3 Running the Board Test System i emm ee RR eR e2. 1 To restore the switches to their factory default settings perform the following steps 1 Set DIP switch bank SW3 to match Table 4 1 and Figure 4 1 Table 4 1 SW3 Dip Switch Settings Switch Board Label PCle x1 Function Switch 1 has the following options m When off the PCle card PCIE_PRSNT2n_x1 signal is connected to PCle card PRSNT1 signal m When on the PCle card PCIE PRSNT2n x1 signal floats Default Position On PCle x4 PCle x8 Switch 2 has the following options m When off the PCle card PCIE PRSNT2n 4 signal is connected to PCle card PRSNT1 signal m When on the PCle card PCIE PRSNT2n 4 signal floats Switch 3 has the following options m When off the PCle card PCIE PRSNT2n x8 signal is connected to PCle card PRSNT1 signal m When the PCle card PCIE PRSNT2n 8 signal floats On On Arria 11 GX FPGA Development Kit User Guide February 2011 Altera Corporation Chapter 4 Development Board Setup Factory Default Switch Settings 2 Set DIP switch bank SW4 to match Table 4 2 and Figure 4 1 Table 4 2 SW4 Dip Switch Settings 4 3 Switch irn Function pein Switch 1 has the following options 1 DIPO m When on reserved Off When off reserved Switch 2 has the following options 2 DIP1 m When on reserved Off m When off rese
3. 2 Chapter 3 Software Installation Installing the Arria 11 GX FPGA Development Kit 57 Your serial number is printed on the development kit box below the bottom bar code The number is 10 or 11 alphanumeric characters and does not contain hyphens Figure 3 1 shows 351505 as an example serial number Figure 3 1 Locating Your Serial Number DK DSP 3SL150 YY LOT XXXXX 3S150SPXXXX 2 Consult the Activate Products table to determine how to proceed a Ifthe administrator listed for your product is someone other than you skip the remaining steps and contact your administrator to become a licensed user b Ifthe administrator listed for your product is you proceed to step 3 c Ifthe administrator listed for your product is Stocking activate the product making you the administrator and proceed to step 3 3 Use the Create New License page to license your product for a specific user you on specific computers The Manage Computers and Manage Users pages allow you to add users and computers not already present in the licensing system 7 To license the Quartus II software you need your computer s network interface card NIC ID a number that uniquely identifies your computer On the computer you use to run the Quartus II software type ipconfig all at a command prompt to determine the NIC ID Your NIC ID is the 12 digit hexadecimal number on the Physical Address line 4 When licensi
4. 6 17 Using the Board Test System February 2011 m Memory Selects a generic data pattern stored in the on chip memory of the Arria GX device m Math Selects data generated from a simple math function within the FPGA fabric Error Control This control displays data errors detected during analysis and allows you to insert errors m Detected Errors Displays the number of data errors detected in the hardware m Inserted Errors Displays the number of errors inserted into the transmit data stream m Insert Error Inserts a one word error into the transmit data stream each time you click the button Insert Error is only enabled during transaction performance analysis m Clear Resets the Detected errors and Inserted errors counters to zeros Start This control initiates HSMC transaction performance analysis Stop This control terminates transaction performance analysis Performance Indicators These controls display current transaction performance analysis information collected since you last clicked Start m TXand RX performance bars Show the percentage of maximum theoretical data rate that the requested transactions are able to achieve m Tx MBytes s and Rx MBytes s Show the number of bytes of data analyzed per second The HSMA transceiver bus is 4 bits wide and the data rate is 3 75 Gbps totaling 1 5625 GBps full duplex The LVDS SERDES bus is 17 bits wide The transmit data bus is 16 bits wide and
5. ANU S 101 Innovation Drive San Jose CA 95134 www altera com UG 01066 1 1 Arria II GX FPGA Development Kit User Guide cy Subscribe Copyright 2011 Altera Corporation All rights reserved Altera The Programmable Solutions Company the stylized Altera logo and specific device designations are trademarks and or service marks of Altera Corporation in the U S and other countries All other words and logos identified as trademarks and or service marks are the property of Altera Corporation or their respective owners Altera products are protected under numerous U S and foreign patents and pending applications maskwork rights and copyrights Altera warrants performance of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of information product or service described herein except as agreed to in writing by Altera Altera customers advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services QUALITY 150 9001 2008 NSAI Certified Arria GX FPGA Development Kit User Guide February 2011 Altera Corporation N DTE Contents Chapter 1 About This Kit Sidi cic
6. DDR2 Project Data type PRBS Memory C Math E WIR Write Read C ReadOnly Write Only February 2011 Altera Corporation Arria 1 GX FPGA Development Kit User Guide 6 14 Chapter 6 Board Test System Using the Board Test System The following sections describe the controls on the DDR2 tab Start This control initiates DDR2 memory transaction performance analysis Stop This control terminates transaction performance analysis Performance Indicators These controls display current transaction performance analysis information collected since you last clicked Start m Write Read and Total performance bars Show the percentage of maximum theoretical data rate that the requested transactions are able to achieve m Write MBytes s Read MBytes s and Total MBytes s Show the number of bytes of data analyzed per second The data bus is 64 bits wide and the frequency is 333 MHz double data rate 667 Mbps per pin equating to a theoretical maximum bandwidth of 5333 MBps Error Control This control displays data errors detected during analysis and allows you to insert errors m Detected Errors Displays the number of data errors detected in the hardware m Inserted Errors Displays the number of errors inserted into the transaction stream m Insert Error Inserts a one word error into the transaction stream each time you click the button Insert Error is o
7. OCR2 from the GUI m PSO Sets the MAX II PSO register The following options are available m Use PSR Allows the PSR to determine the page of flash memory to use for FPGA reconfiguration m Use PSS Allows the PSS to determine the page of flash memory to use for FPGA reconfiguration Altera Corporation Arria 1 GX FPGA Development Kit User Guide 6 6 Chapter 6 Board Test System Using the Board Test System PSR Sets the MAX II PSR register The numerical values in the list corresponds to the page of flash memory to load during FPGA reconfiguration Refer to Table 6 1 for more information PSS Displays the MAX II PSS register value Refer to Table 6 1 for the list of available options OCR1 Sets the MAX II OCRI register Refer to Table 6 1 for the list of available options SRST Resets the system and reloads the FPGA with a design from flash memory based on the other MAX II register values Refer to Table 6 1 for more information Because the Config tab requires that a specific design is running in the FPGA ata specific clock speed writing a 0 to SRST writing a 1 2 or 3 to OCRZ or changing the PSO value can cause the Board Test System to stop running JTAG Chain This control shows all the devices currently in the JTAG chain The Arria II GX device is always the first device in the chain Uninstalling the shunt jumper from jumper J9 pins 1 2 includes the MAX II device in the JTAG chain Boa
8. SRST Use PSR Usepss 5 0 OCR1 150 JTAG Chain USB Blaster on localhost USB D 2 125 1 Messages 2 5M22102Z EPM2210 2 Detected the GPIO SRAM Flash Project SOPC Builder Mernory Map Block description 0 0800 0000 OBFF FFFF 0 0080 0000 OOFF FFFF max2 inf 0 0060 0000 0060 01FF onchip_memory 0 0010 0000 0017 FFFF xl Several designs are provided to test the major board features Each design provides data for one or more tabs in the application The Configure menu identifies the appropriate design to download to the FPGA for each tab After successful FPGA configuration the appropriate tab appears and allows you to exercise the related board features Highlights appear in the board picture around the corresponding components The Power Monitor button starts the Power Monitor application that measures and reports current power information for the board Because the application communicates over the JTAG bus to the MAX II device you can measure the power of any design in the FPGA including your own designs Arria II GX FPGA Development Kit User Guide February 2011 Altera Corporation Chapter 6 Board Test System 6 3 Preparing the Board The Board Test System and Power Monitor share the JTAG bus with other applications like the Nios II debugger and the SignalTap Embedded Logic Analyzer Because the Quartus II programmer us
9. Take advantage of the modular and scalable design by using the high speed mezzanine card HSMC connectors to interface to over 30 different HSMCs provided by Altera partners supporting protocols such as Serial RapidIO 10 Gigabit Ethernet SONET Common Public Radio Interface CPRI Open Base Station Architecture Initiative OBSAI and others Kit Features This section briefly describes the Arria II GX FPGA Development Kit contents Hardware The Arria II GX FPGA Development Kit includes the following hardware m Arria II GX FPGA development board A development platform that allows you to develop and prototype hardware designs running on the Arria II GX EP2AGX125 FPGA For detailed information about the board components and interfaces refer to the Arria II GX FPGA Development Board Reference Manual m Power supply and cables The kit includes the following items m Power supply and AC adapters for North America Japan Europe and the United Kingdom m USB cable m Ethernet cable m loopback board A daughtercard that allows for loopback testing all signals on the HSMC interface using the Board Test System m debug breakout board A daughtercard that routes 40 CMOS signals to 0 1 inch header and adds 20 LEDs to the remaining 40 CMOS signals Software The software for this kit described in the following sections is available on the Altera website for immediate downloading You can also request to h
10. of the kit m Installing the design and kit software m Setting up powering up and verifying correct operation of the FPGA development board m Configuring the Arria GX FPGA m Running the Board Test System designs For complete information about the FPGA development board refer to the Arria II GX FPGA Development Board Reference Manual Before You Begin Before using the kit or installing the software check the kit contents and inspect the board to verify that you received all of the items listed in Kit Features on page 1 1 If any of the items are missing contact Altera before you proceed Inspect the Board CAUTION To inspect the board perform the following steps 1 Placethe board on an anti static surface and inspect it to ensure that it has not been damaged during shipment CAUTION A Without proper anti static handling you can damage the board 2 Verify that all components are on the board and appear intact In typical applications with the Arria IT GX FPGA development board a heat sink is not necessary However under extreme conditions or for engineering sample silicon the board might require additional cooling to stay within operating temperature guidelines You can perform power consumption and thermal modeling to determine whether your application requires additional cooling The board has two holes near the FPGA that accommodate many different heat sinks including the Dynatron V31G For more information ab
11. the IP address 4 Launch a web browser on a PC that is connected to the same network and enter the IP address from the LCD into the browser address bar The Board Update Portal web page appears in the browser February 2011 Altera Corporation Arria 1 GX FPGA Development Kit User Guide 5 2 Chapter 5 Board Update Portal Using the Board Update Portal to Update User Designs 5 Click Arria GX FPGA Development Kit on the Board Update Portal web page to access the kit s home page Visit this page occasionally for documentation updates and additional new designs You also navigate directly to the Arria GX FPGA Development Kit page of the Altera website to determine if you have the latest kit software Using the Board Update Portal to Update User Designs The Board Update Portal allows you to write new designs to the user portion of flash memory Designs must be in the Nios II Flash Programmer File flash format Design files available from the Arria II GX FPGA Development Kit page include flash files You can also create flash files from your own custom design Refer to Preparing Design Files for Flash Programming on page A 2 for information about preparing your own design for upload To upload a design over the network into the user portion of flash memory on your board perform the following steps 1 Perform the steps in Connecting to the Board Update Portal Web Page to access the Board Update Portal web
12. the frequency is 300 MHz double data rate 600 Mbps per pin equating to a theoretical maximum bandwidth of 1200 MBps Altera Corporation Arria Il GX FPGA Development Kit User Guide 6 18 Chapter 6 Board Test System The Power Monitor The Power Monitor The Power Monitor measures and reports current power information for the board To start the application click Power Monitor in the Board Test System application You can also run the Power Monitor as a stand alone application PowerTool exe resides in the lt install dir gt kits arrialIGX_2agx125_fpga examples board_test_system directory On Windows click Start gt All Programs gt Altera gt Arria GX FPGA Development Kit lt version gt gt Power Monitor to start the application The Power Monitor communicates with the MAX II device on the board through the JTAG bus A power monitor circuit attached to the MAX II device allows you to measure the power that the Arria GX FPGA device is consuming regardless of the design currently running Figure 6 9 shows the Power Monitor Figure 6 9 The Power Monitor NU RA AN Power information e RMS Maximum Minimum General information mvolt 892 892 892 II version 10 Power rail A2NCC m mp 1185 1265 1098 mwatt 1055 1128 979 2000 mw 1000 mw Messages E Graph settings connections USB Blaster on localhost USB 0 5M2210Z EPM221082 Scale select U
13. the new values to SRAM and then reads the values back to guarantee that the graphical display accurately reflects the memory contents Random Test Starts an random data pattern test to flash memory Increment Test Starts an incrementing data pattern test to flash memory The DDR3 Tab The DDR3 tab allows you to read and write the DDR3 memory on your board Figure 6 6 shows the DDRS tab Figure 6 6 The DDR3 Tab Test System 5 ful f Configure Help About Messages Min Detected the DDR3 Project RUIN PRBS C Memory C Math WIR Control Stop write Read Total Write MBytes s 1135 5149 Read MBytes s 359 3252 Total MBytes s 1494 8401 Error Control 22 Detected Errors 0 Inserted Errors 0 B Insert Error Clear Number of Addresses to Write Read 1 Write Read ReadOnly Write Only February 2011 Altera Corporation Arria Il GX FPGA Development Kit User Guide 6 12 Chapter 6 Board Test System Using the Board Test System The following sections describe the controls on the DDR3 tab Start This control initiates DDR3 memory transaction performance analysis Stop This control terminates transaction performance analysis Performance Indicators These controls display current transaction performance analysis information collected since you last p
14. 2 Design Configure with HSMC Design Exit Ctri Q Power Monitor To configure the FPGA with a test system design follow these steps 1 Onthe Configure menu click the configure command that corresponds to the functionality you wish to test 2 In the dialog box that appears click Configure to download the corresponding design s SRAM Object File sof to the FPGA The download process usually takes about a minute 3 When configuration finishes click Close to complete the configuration process and run the design in the FPGA A corresponding application tab appears in the GUI that interfaces with the design in the FPGA The Config Tab The Config tab shows information about the board s current configuration Figure 6 1 on page 6 2 shows the Config tab The tab displays the contents of the MAX II registers the MAX II code version the JTAG chain the board s MAC address and the flash memory map The following sections describe the controls on the Config tab Arria GX FPGA Development Kit User Guide February 2011 Altera Corporation Chapter 6 Board Test System Using the Board Test System February 2011 MAX Registers 6 5 The MAX II registers control allow you to view and change the current MAX II register values as described in Table 6 1 Changes to the register values with the GUI take effect immediately For example selecting a new frequency in the OCR1 list immediately changes the clock
15. 2 KB AE zipfs html web content 8 192 KB rA Unused 6 287 8 User hardware 2 6 357 KB re tea AR February 2011 Altera Corporation Arria 1 GX FPGA Development Kit User Guide A 2 Appendix A Preparing Design Files for Flash Programming Table A 1 Byte Address Flash Memory Map Part 2 of 2 Block Description Size Address Range User hardware 1 6 357 KB M Factory hardware 6 357 KB presul PFL option bits 32 KB i BR Board information 32 KB pen Ethernet option bits 32 KB NE User design reset vector 32 KB Mores i A Altera recommends that you do not overwrite the factory hardware and factory software images unless you are an expert with the Altera tools If you unintentionally overwrite the factory hardware or factory software image refer to Restoring the Flash Device to the Factory Settings on page A 4 Preparing Design Files for Flash Programming You can obtain designs containing prepared flash files from the Arria II GX FPGA Development Kit page of the Altera website or create flash files from your own custom design The Nios II EDS sof2flash command line utility converts your Quartus II compiled sof into the flash format necessary for the flash device Similarly the Nios II EDS elf2flash command line utility converts your compiled and linked Executable and Linking Format File elf software design to flash After your design files are in the flash format use the Board Updat
16. FFFFFF 0000 0040 FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF 0000 0050 FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF 0000 0060 FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF 0000 0070 FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF Block description Unused 128KB 0 03 0000 O3FF FFFF a enn User software U 33 536KB 2 0000 03FD FFFF Detected the GPIO SRAM Flash Project Factory software 8192KB 0 0172 0000 O1F1 7FFF Unused 9728KB 009 0000 0131 FFFF o oo FF information 0 0001 0000 0001 FFF Ethernet Option Bits 0 0000 8000 0000 FFFF The following sections describe the controls on the Flash tab Arria Il GX FPGA Development Kit User Guide February 2011 Altera Corporation Chapter 6 Board Test System 6 9 Using the Board Test System The Read control reads the flash memory on your board To see the flash memory contents type a starting address in the text box and click Read Values starting at the specified address appear in the table The base address of flash memory in this Nios II based BTS design is 0x0800 0000 The valid address range within the 64 MB flash memory is 0x0000 0000 through 0x03FF FFFF as shown in the GUI If you enter an address outside of the 0x0000 0000 to 0x003F FFFF flash memory address space a warning message identifies the valid flash memory address range Write The Wr
17. a kukuona 6 9 Flash Memory o iae 6 9 TheSSRAM Tab u date be Saeed owe ERE RR emer REPRE ERE peed ee Ea de age ade 6 10 Read T 6 10 bas Re R EPPCPRbPIPEPIICERIDeOCEPSDeb EPI aS 6 11 Random Test uz qusa ua n UE oh Ge hha Malaga ese e SS 6 11 Increment lest dene Pi Shae aden Bree aad Y aus e gc oa Ghee eee agen teed eas 6 11 The DDR3 Tab cet ef eR RR PERDU E IIO eee ec n E esos ds ee IAS 6 11 uc P 6 12 SLOP LETT 6 12 Performance Indicators ERR Baa RE EE u VETERES Sg 6 12 Err r Control a Maes Mesa Melos S Sup Maga tema nng ery eee a asa 6 12 Number of Addresses to Write Read cece eee eee 6 12 Data Type a cach asuaka paha ps a pi ht ro UR do eque tee dea a ad 6 12 WIR reete eid alec saw uya get PER aqa 6 13 The DDR2 Tab ke Ree ERR Hert DRE RRIUU EDI IERI TUAE 6 13 uc A M 6 14 SIOP eios tiis Deas LI DL ILLI A LIII ME 6 14 Performance Indicators re ee n RR er mE bee EFIE RE E Regg 6 14 Error Control e RA RENE E er eR ERE RD CRI s 6 14 Number of Addresses to Write Read e 6 14 Data Ty
18. ave Altera mail the software to you on DVDs February 2011 Altera Corporation Arria 1 GX FPGA Development Kit User Guide 1 2 Chapter 1 About This Kit Kit Features Quartus Subscription Edition Software The Quartus II Subscription Edition Software is a licensed set of Altera tools with full functionality Your kit includes a one year license for the Quartus II software Windows platform only This license entitles you to all the features of the subscription edition for a period of one year After the year you must purchase a renewal subscription to continue using the software For more information refer to the Altera website www altera com T Download the Quartus II Subscription Edition Software from the Quartus II Subscription Edition Software page of the Altera website Alternatively you can request a DVD from the Altera IP and Software DVD Request Form page of the Altera website The Quartus II Subscription Edition Software includes the following items m Quartus Software The Quartus II software including the SOPC Builder system development tool provides a comprehensive environment for system on a programmable chip SOPC design The Quartus II software integrates into nearly any design environment and provides interfaces to industry standard EDA tools m MegaCore IP Library A library that contains Altera IP MegaCore functions You can evaluate MegaCore functions by using the OpenCore Plus feature to do the followi
19. cluded in the Quartus II Subscription Edition Software are the Quartus II software the Nios II EDS and the MegaCore IP Library The Quartus II software including SOPC Builder and the Nios II EDS are the primary FPGA development tools used to create the reference designs in this kit To install the Altera development tools perform the following steps 1 Run the Quartus II Subscription Edition Software installer you acquired in Software on page 1 1 2 Follow the on screen instructions to complete the installation process T Ifyou have difficulty installing the Quartus II software refer to Altera Software Installation and Licensing Manual Licensing Considerations Purchasing this kit entitles you to a one year license for the Quartus II Subscription Edition Software Before using the Quartus II software you must activate your license identify specific users and computers and obtain and install a license file If you already have a licensed version of the subscription edition you can use that license file with this kit If not you need to obtain and install a license file To begin go to the Self Service Licensing Center page of the Altera website log into or create your myAltera account and take the following actions 1 On the Activate Products page enter the serial number provided with your development kit in the License Activation Code box February 2011 Altera Corporation Arria Il GX FPGA Development Kit User Guide 3
20. cted the GPIO SRAM Flash Project 0000 0100 D9C00817 DA000917 DA400A17 DASOOB1 0000 0110 17 DBOOOD1 DB400E17 DBSOO0F17 0000 0120 DBCO1017 DECO1304 EF800831L DEFFF904 0000 0130 DFC00615 DF000515 DF000504 OZ11BE00 0000 0140 0005313 EOBFFF15 EOBFFF17 EOBFFE15 0000 0150 EOBFFE1 EOBFFE1S EOSFFD15 00800044 0000 0160 EOBFFCIS EOFFFE17 EOBFFC17 18847034 TANSANAA 1NNNNRIR nnrnnaasa Tarspanda The following sections describe the controls on the SSRAM tab This control allows you to read and write the SRAM on your board Type a starting address in the text box and click Read Values starting at the specified address appear in the table The base address of SRAM in this Nios II based BTS design is 0x0D00 0000 The valid address range within the 2 SRAM is 0x0000 0000 through 0x001F FFFF as shown in the GUI space a warning message identifies the valid SRAM address range Arria II GX FPGA Development Kit User Guide If you enter an address outside of the 0x0000 0000 to 0x001F FFFF SRAM address February 2011 Altera Corporation Chapter 6 Board Test System 6 11 Using the Board Test System Write The Write control writes the SRAM on your board To update the SRAM contents change values in the table and click Write The application writes
21. d Reference Manual The resulting flash files are ready for flash device programming If your design uses additional files such as image data or files used by the runtime program you must first convert the files to flash format and concatenate them into one flash file before using the Board Update Portal to upload them gt The Board Update Portal standard flash format conventionally uses either filename hw flash for hardware design files or filename sw flash for software design files Programming Flash Memory Using the Board Update Portal Once you have the necessary flash files you can use the Board Update Portal to reprogram the flash memory Refer to Using the Board Update Portal to Update User Designs on page 5 2 for more information 7 If you have generated sof that operates without a software design file you can still use the Board Update Portal to upload your design In this case leave the Software File Name field blank Programming Flash Memory Using the Nios Il EDS The Nios II EDS offers a nios2 flash programmer utility to program the flash memory directly To program the flash files or any compatible S Record File srec to the board using nios2 flash programmer perform the following steps 1 Set the USER LOAD switch SW4 4 to the off position to load the Board Update Portal design from flash memory on power up 2 Attach the USB Blaster cable and power up the board If the board has pow
22. e Portal or the Nios II EDS nios2 flash programmer utility to write the flash files to the user hardware 1 and user software locations of the flash memory For more information about Nios II EDS software tools and practices refer to the Embedded Software Development page of the Altera website Creating Flash Files Using the Nios II EDS If you have an FPGA design developed using the Quartus II software and software developed using the Nios II EDS follow these instructions 1 On the Windows Start menu click All Programs gt Altera gt Nios II EDS gt Nios II Command Shell Arria GX FPGA Development Kit User Guide February 2011 Altera Corporation Appendix A A 3 Programming Flash Memory Using the Board Update Portal 2 In the Nios II command shell navigate to the directory where your design files reside and type the following Nios II EDS commands m For Quartus II sof files sof2flash input lt yourfile gt hw sof output yourfile hw flash offset 0x00640000 pfl optionbit 0x18000 programmingmode PS m For Nios II elf files elf2flash base 0x08000000 end z0xOBFFFFFF reset 0x0A020000 input yourfile sw elf output yourfile sw flash boot SOPC KIT NIOS2 components altera nios2 boot loader 1 5 gt For boards with dual die CFI flash devices use base 0x0A000000 For more information refer to the Board Revision History appendix of the Arria II GX FPGA Development Boar
23. e the POWER switch SW1 off then on to load and run the restored factory design The restore script cannot restore the board s MAC address automatically In the Nios II command shell type the following Nios II EDS command nios2 terminal and follow the instructions in the terminal window to generate a unique MAC address To ensure that you have the most up to date factory restore files and information about this product refer to the Arria II GX FPGA Development Kit page of the Altera website Restoring the MAX II CPLD to the Factory Settings This section describes how to restore the original factory contents to the MAX II CPLD on the FPGA development board Make sure you have the Nios II EDS installed and perform the following instructions February 2011 1 Set the board switches to the factory default settings described in Factory Default Switch Settings on page 4 2 Uninstalling the shunt jumper from jumper 9 pins 1 2 includes MAX II device in the JTAG chain Altera Corporation Arria Il GX FPGA Development Kit User Guide A 6 Appendix A Restoring the MAX II CPLD to the Factory Settings 2 Launch the Quartus II Programmer 3 Click Auto Detect 4 Click Add File and select lt install dir NkitsNarrialIGX 2agx125 fpgaMfactory recovery max2 pof 5 Turn on the Program Configure option for the added file 6 Click Start to download the selected configuration file to the MAX II CPLD Configuratio
24. ections of an actual file such as a Report File references to parts of files for example the AHDL keyword SUBDESIGN and logic function names for example TRI t An angled arrow instructs you to press the Enter key Numbered steps indicate a list of items when the sequence of the items is important such as the steps listed in a procedure Bullets indicate a list of items when the sequence of the items is not important gm r gt The hand points to information that requires special attention A question mark directs you to a software help system with related information The feet direct you to another document or website with related information A caution calls attention to a condition or possible situation that can damage or destroy the product or your work a gt d z gt warning calls attention to a condition or possible situation that can cause you injury The envelope links to the Email Subscription Management Center page of the Altera website where you can sign up to receive update notifications for Altera documents Arria 11 GX FPGA Development Kit User Guide February 2011 Altera Corporation
25. el flash loader PFL megafunction When the board powers up the PFL reads a design from flash memory and configures the FPGA The USER LOAD switch SW4 4 controls which design to load When the switch is in the off position the PFL loads the design from the factory portion of flash memory When the switch is in the on position the PFL loads the design from the user portion of flash memory The kit includes a MAX II design which contains the MAX II PFL megafunction The design resides in the install dir gt kits arrialIGX_2agx125_fpga examples max2 directory When configuration is complete the CONF DONE LED D14 illuminates signaling that the Arria II GX device configured successfully For more information about the PFL megafunction refer to Parallel Flash Loader Megafunction User Guide February 2011 Altera Corporation Arria 1 GX FPGA Development Kit User Guide 4 2 Chapter 4 Development Board Setup Factory Default Switch Settings Factory Default Switch Settings This section shows the factory switch settings for the Arria II GX FPGA development board Figure 4 1 shows the switch locations and the default position of each switch Figure 4 1 Switch Locations and Default Settings on the FPGA Development Board 0 4 DIP Switch n ON or SW2 a Ru Sene J9 m m m ON ON 0 irc sW3 a
26. er 4 Development Board Setup Factory Default Switch Settings Table 4 3 JTAG Chain Jumper Settings Part 2 of 2 Board Board Reference Label Default Function Shunt Position This jumper has the following options J9 pins 5 6 HSMB DIS m Installing the shunt removes HSMC port B from the JTAG chain Installed m Removing the shunt includes port B in the JTAG chain This jumper has the following options J9 pins 7 8 PCle DIS m Installing the shunt removes the PCle device from the JTAG chain Installed m Removing the shunt includes the PCle device in the JTAG chain For more information about the FPGA board settings refer to the Arria GX FPGA Development Board Reference Manual Arria GX FPGA Development Kit User Guide February 2011 Altera Corporation 5 Board Update Portal JNO S RYAN The Arria II GX FPGA Development Kit ships with the Board Update Portal design example stored in the factory portion of the flash memory on the board The design consists of a Nios II embedded processor an Ethernet MAC and an HTML web server When you power up the board with the USER LOAD switch SW4 4 in the off position the Arria II GX FPGA configures with the Board Update Portal design example The design can obtain an IP address from any DHCP server and serve a web page from the flash on your board to any host computer on the same network The web page allows you to upload new FPGA designs to
27. ered up and the LCD displays either Connecting or a valid IP address such as 152 198 231 75 proceed to step 8 If no output appears on the LCD or if the CONF DONE LED D14 does not illuminate continue to step 4 to load the FPGA with a flash writing design 4 Launch the Quartus II Programmer to configure the FPGA with a sof capable of flash programming Refer to Configuring the FPGA Using the Quartus II Programmer on page 6 20 for more information February 2011 Altera Corporation Arria Il GX FPGA Development Kit User Guide A 4 Appendix A Restoring the Flash Device to the Factory Settings 5 Click Add File and select lt install dir NkitsNarrialIGX 2agx125 fpgaMfactory recovery ArrialIGX_2agx125_dev_ bup sof 6 Turn on the Program Configure option for the added file 7 Click Start to download the selected configuration file to the FPGA Configuration is complete when the progress bar reaches 100 The CONF DONE LED D14 and the four user LEDs D7 D10 illuminate indicating that the flash device is ready for programming 8 On the Windows Start menu click All Programs gt Altera gt Nios II EDS gt Nios Command Shell 9 In the Nios II command shell navigate to the install dir NkitsNarrialIGX 2agx125 fpgaMfactory recovery directory or to the directory of the flash files you created in Creating Flash Files Using the Nios II EDS on page 2 and type the following Nios II EDS command nios2 flash pro
28. es are available for analysis m PRBS Selects pseudo random bit sequences Frequency rates for production silicon speed grade only Arria GX FPGA Development Kit User Guide February 2011 Altera Corporation Chapter 6 Board Test System 6 13 Using the Board Test System m Memory Selects a generic data pattern stored in the on chip memory of the Arria II GX device m Math Selects data generated from a simple math function within the FPGA fabric W R Control This control specifies the type of transactions to analyze The following transaction types are available for analysis m Write Read Selects read and write transactions for analysis m Read Only Selects read transactions for analysis m Write Only 3elects write transactions for analysis The DDR2 Tab The DDR2 tab allows you to read and write the DDR2 memory on your board Figure 6 7 shows the DDR2 tab Figure 6 7 The 0082 Tab Test System mure Configure Help About config GPIO Flash SARAM DDR3 DDR2 HSMC Stop Write Read Total Write MBytes s 919 4665 Read 5 4274 6054 Total MBytes s 5194 0719 Error Control Detected Errors 0 gt z Inserted Errors Insert Error Clear 1 Number of Addresses to Write Read J iu LEES p bese Min Max 134217728 Messages Detected the
29. es most of the bandwidth of the JTAG bus other applications using the JTAG bus might time out Be sure to close the other applications before attempting to reconfigure the FPGA using the Quartus II Programmer Preparing the Board With the power to the board off perform the following steps 1 Connect the USB cable to the board 2 Verify the settings for the board settings DIP switch bank SW4 match Table 4 2 on page 4 3 3 Set the USER_LOAD switch SW4 4 to the on position 4 Verify the settings for the JTAG jumper block J9 match Table 4 3 on page 4 3 These settings determine the devices to include in the JTAG chain St For more information about the board s DIP switch and jumper settings refer to the Arria II GX FPGA Development Board Reference Manual 5 Turn the power to the board on The board loads the design stored in the user hardware 1 portion of flash memory into the FPGA If your board is still in the factory configuration or if you have downloaded a newer version of the Board Test System to flash memory through the Board Update Portal the design loads the GPIO SRAM and flash memory tests To ensure operating stability keep the USB cable connected and the board powered on when running the demonstration application The application cannot run correctly unless the USB cable is attached and the board is on CAUTION Running the Board Test System To run the application navigate to the lt install dir g
30. frequency on the board Table 6 1 MAX Registers Read Write Register Capability Description Write only Set to 0 to initiate an FPGA reconfiguration SRST Determines which of the up to eight 0 7 pages of flash Paga Select Register Read Write memory to use for FPGA reconfiguration The flash memory PSR l ships with pages 0 and 1 preconfigured When set to 0 the value in PSR determines the page of Page Select Override Read Write flash memory to use for FPGA reconfiguration When set to PSO 1 the value in PSS determines the page of flash memory to use for FPGA reconfiguration Holds the current value of the illuminated CONFIG LED D11 D13 based on the following encoding m 0 CONFIG LED D13 and corresponds to the flash Page Select Switch memory page for the factory hardware design Read only PSS 1 CONFIG LED 012 and corresponds to the flash memory page for the user hardware 1 design m 2 CONFIG LED D11 and corresponds to the flash memory page for the user hardware 2 design Determines the U26 oscillator output frequency based on the following options Oscillator Control 02100 MHz Register 1 Read Write 4 125 MHz m 2 150 MHz m 3 156 25 MHz Determines the U30 oscillator output frequency based on the following options m 0 100 MHz Oscillator Control 1 125 MHz Register 2 0082 Read Write m 2 150 MHz m 3 156 25 MHz You cannot change
31. gram the flash memory device so that your own design loads from flash memory into the FPGA on power up This appendix describes the preprogrammed contents of the common flash interface CFI flash memory device on the Arria GX FPGA development board and the Nios II EDS tools involved with reprogramming the user portions of the flash memory device The Arria IT GX FPGA development board ships with the CFI flash device preprogrammed with a default factory FPGA configuration for running the Board Update Portal design example and a default user configuration for running the Board Test System demonstration There are several other factory software files written to the CFI flash device to support the Board Update Portal These software files were created using the Nios EDS just as the hardware design was created using the Quartus II software St For more information about Altera development tools refer to the Design Software page of the Altera website CFI Flash Memory Map Table 1 shows the default memory contents of the 512 Mb 64 MB CFI flash device Numonyx PC28F512P30BF For the Board Update Portal to run correctly and update designs in the user memory this memory map must not be altered Table A 1 Byte Address Flash Memory Map Part 1 of 2 Block Description Size Address Range Unused 32KB Unused Unused 32KB 0 03FEB000 Unused User software 24 320 KB ake Factory software 8 19
32. grammer base 0x08000000 lt yourfile gt hw flash 10 After programming completes if you have a software file to program type the following Nios II EDS command nios2 flash programmer base 0x08000000 yourfile sw flash For boards with dual die CFI flash devices use base 0x0A000000 For more information refer to the Board Revision History appendix of the Arria II GX FPGA Development Board Reference Manual 11 Set the USER LOAD switch SW4 4 to the on position and power cycle the board to load and run the new user design Programming the board is now complete St For more information about the nios2 flash programmer utility refer to the Nios II Flash Programmer User Guide Restoring the Flash Device to the Factory Settings This section describes how to restore the original factory contents to the flash memory device on the FPGA development board Make sure you have the Nios II EDS installed and perform the following instructions 1 Setthe board switches to the factory default settings described in Factory Default Switch Settings on page 4 2 2 Launch the Quartus II Programmer to configure the FPGA with a sof capable of flash programming Refer to Configuring the FPGA Using the Quartus II Programmer on page 6 20 for more information 3 Click Add File and select install dir NkitsNarrialIGX 2agx125 fpgaMfactory recovery ArrialIGX_2agx125_dev_ bup sof 4 Turn on the Program Configu
33. he side opposite the power source and then measure the voltage on the other side The first measurement is Vsense and the difference between the two measurements is Vdif Plug the values into the equation to determine the power consumption Configuring the FPGA Using the Quartus Il Programmer You can use the Quartus II Programmer to configure the FPGA with a specific sof Before configuring the FPGA ensure that the Quartus II Programmer and the USB Blaster driver are installed on the host computer the USB cable is connected to the FPGA development board power to the board is on and no other applications that use the JTAG chain are running To configure the Arria II GX FPGA perform the following steps 1 Start the Quartus II Programmer 2 Click Add File and select the path to the desired sof 3 Turn on the Program Configure option for the added file 4 Click Start to download the selected file to the FPGA Configuration is complete when the progress bar reaches 100 Using the Quartus II programmer to configure a device on the board causes other JT AG based applications such as the Board Test System and the Power Monitor to loose their connection to the board Restart those applications after configuration is complete Arria GX FPGA Development Kit User Guide February 2011 Altera Corporation A Programming the Flash Memory JN OS RYAN Device As you develop your own project using the Altera tools you can pro
34. how to set up the Arria II GX FPGA development board Setting Up the Board To prepare and apply power to the board perform the following steps 1 The Arria II GX FPGA development board ships with its board switches preconfigured to support the design examples in the kit If you suspect your board might not be currently configured with the default settings follow the instructions in Factory Default Switch Settings on page 4 2 to return the board to its factory settings before proceeding 2 The FPGA development board ships with design examples stored in the flash memory device Verify the USER LOAD switch SW4 4 is set to the off position to load the design stored in the factory portion of flash memory Figure 4 1 shows the switch location on the Arria II GX FPGA development board 3 Setthe POWER switch SW1 to the off position To avoid damage to the board always have the board POWER switch SW1 in the off position before inserting the DC power jack 4 CAUTION 4 Connect the DC adapter 16 V 3 75 A to the DC power jack J4 on the FPGA board and plug the cord into a power outlet A Use only the supplied 16 V power supply Power regulation circuitry on the board can be damaged by power supplies with greater voltage 5 Set the POWER switch SW1 to the on position When power is supplied to the board a blue LED D18 illuminates indicating that the board has power The MAX II device on the board contains a parall
35. is considered synced when the start of the data sequence is detected Port This control allows you to specify the type of test to run on the HSMC ports The following HSMC port tests are available m HSMA x4 Tranceivers 0 3 m HSMA x17 LVDS SERDES m HSMA x3 single ended loopback PMA Setting The PMA Setting button allows you to make changes to the PMA parameters that affect the active transceiver interface The following settings are available for analysis m Serial Loopback Routes signals from the receiver to the transmitter VOD Specifies the voltage output differential of the transmitter buffer m Pre emphasis tap m Pre Specifies the amount of pre emphasis on the pre tap of the transmitter buffer m First post Specifies the amount of pre emphasis on the first post tap of the transmitter buffer m Second post Specifies the amount of pre emphasis on the second post tap of the transmitter buffer m Equalizer Specifies the setting for the receiver equalizer m DC gain Specifies the DC portion of the receiver equalizer For restrictions on the PMA settings refer to Volume 2 Transceivers of the Arria Device Handbook Data Type This control specifies the type of data contained in the transactions The following data types are available for analysis m PRBS Selects pseudo random bit sequences Arria GX FPGA Development Kit User Guide February 2011 Altera Corporation Chapter 6 Board Test System
36. ite control writes the flash memory on your board To update the flash memory contents change values in the table and click Write The application writes the new values to flash memory and then reads the values back to guarantee that the graphical display accurately reflects the memory contents L gt To prevent overwriting the dedicated portions of flash memory the application limits the writable flash memory address range from Ox03FE 0000 to 0x003F FFFF which corresponds to the unused flash memory address range shown in Figure 6 1 on page 6 2 and Table 1 on page A 1 Random Test Starts a random data pattern test to flash memory Limited to scratch page in the upper 128K block CFI Query The CFI Query control updates the memory table displaying the CFI ROM table contents from the flash device Increment Test Starts an incrementing data pattern test to flash memory Limited to scratch page in the upper 128K block Reset The Reset control executes the flash device s reset command and updates the memory table displayed on the Flash tab Erase Erases flash memory Limited to scratch page in the upper 128K blocks Flash Memory Map Displays the flash memory map for the Arria II GX FPGA Development Kit February 2011 Altera Corporation Arria Il GX FPGA Development Kit User Guide 6 10 The SSRAM Tab Chapter 6 Board Test System Using the Board Test System The SSRAM tab allows you to read and write SRAM and fla
37. le 3 1 Installed Directory Contents Directory Name Description of Contents Contains schematic layout assembly and bill of material board design files Use these files as a starting point for a new prototype board design board design files demos Contains demonstration applications documents Contains the kit documentation examples Contains the sample design files for the Arria Il GX FPGA Development Kit Contains the original data programmed onto the board before shipment Use this data to restore factory recovery the board with its original factory contents Installing the USB Blaster Driver The Arria II GX FPGA development board includes integrated USB Blaster circuitry for FPGA programming However for the host computer and board to communicate you must install the USB Blaster driver on the host computer UT Installation instructions for the USB Blaster driver for your operating system are available on the Altera website On the Cable amp Adapter Driver Information page of the Altera website locate the table entry for your configuration and click the link to access the instructions February 2011 Altera Corporation Arria Il GX FPGA Development Kit User Guide 3 4 Chapter 3 Software Installation Installing the USB Blaster Driver Arria Il GX FPGA Development Kit User Guide February 2011 Altera Corporation N DTE SYN 4 Development Board Setup The instructions in this chapter explain
38. mmand names dialog box titles dialog box options and other GUI ee LL labels For example Save As dialog box For GUI elements capitalization matches Letters the GUI Indicates directory names project names disk drive names file names file name bold type extensions software utility names and GUI labels For example qdesigns directory D drive and chiptrip gdf file Italic Type with Initial Capital Letters Indicate document titles For example Stratix IV Design Guidelines Indicates variables For example n 1 italic type Variable names are enclosed in angle brackets For example file name and project name pot file February 2011 Altera Corporation Arria Il GX FPGA Development Kit User Guide Info 2 Additional Information Typographic Conventions Visual Cue Initial Capital Letters Indicate keyboard keys and menu names For example the Delete key and the Options menu Subheading Title Quotation marks indicate references to sections within a document and titles of Quartus Help topics For example Typographic Conventions Courier type Indicates signal port register bit block and primitive names For example data1 tdi and input The suffix n denotes an active low signal For example resetn Indicates command line commands and anything that must be typed exactly as it appears For example c qdesigns tutorial chiptrip gdf Also indicates s
39. n is complete when the progress bar reaches 100 Ta that you have the most up to date factory restore files and information about this product refer to the Arria II GX FPGA Development Kit page of the Altera website Arria GX FPGA Development Kit User Guide February 2011 Altera Corporation Additional Information This chapter provides additional information about the document and Altera Document Revision History The following table shows the revision history for this document Date Version Changes Updates for production silicon speed grade C4N device new single die flash device LVDS Et DDR2 and DDR3 speed improvements July 2009 1 0 Initial release How to Contact Altera To locate the most up to date information about Altera products refer to the following table Contact 7 Contact Method Address Technical support Website www altera com support m Website www altera com training Technical training Email custrain altera com Product literature Website www altera com literature Non technical support General Email nacomp altera com Software Licensing Email authorization altera com Note to Table 1 You can also contact your local Altera sales office or sales representative Typographic Conventions The following table shows the typographic conventions this document uses Visual Cue Meaning Indicate co
40. ng m Simulate behavior of a MegaCore function within your system m Verify functionality of your design and quickly and easily evaluate its size and speed m Generate time limited device programming files for designs that include MegaCore functions m Program a device and verify your design in hardware gt The OpenCore Plus hardware evaluation feature is an evaluation tool for prototyping only You must purchase a license to use a MegaCore function in production For more information about OpenCore Plus refer to AN 320 OpenCore Plus Evaluation of Megafunctions m Nios II Embedded Design Suite EDS A full featured set of tools that allows you to develop embedded software for the Nios II processor which you can include in your Altera FPGA designs Arria Il GX FPGA Development Kit Installer The license free Arria II GX FPGA Development Kit installer includes all the documentation and design examples for the kit Download the Arria II GX FPGA Development Kit installer from the Arria GX FPGA Development Kit page of the Altera website Alternatively you can request a development kit DVD from the Altera Kit Installations DVD Request Form page of the Altera website Arria Il GX FPGA Development Kit User Guide February 2011 Altera Corporation AERA 2 Getting Started The remaining chapters in this user guide lead you through the following Arria IT GX FPGA development board setup steps m Inspecting the contents
41. ng is complete Altera emails a license dat file to you Store the file on your computer and use the License Setup page of the Options dialog box in the Quartus II software to enable the software Te Forcomplete licensing details refer to Altera Software Installation and Licensing Manual Installing the Arria Il GX FPGA Development Kit To install the Arria II GX FPGA Development Kit perform the following steps 1 Run the Arria II GX FPGA Development Kit installer you acquired in Software on page 1 1 Arria GX FPGA Development Kit User Guide February 2011 Altera Corporation Chapter 3 Software Installation 3 3 Installing the USB Blaster Driver 2 Follow the on screen instructions to complete the installation process Be sure that the installation directory you choose is in the same relative location to the Quartus II software installation The installation program creates the Arria IT GX FPGA Development Kit directory structure shown in Figure 3 2 Figure 3 2 Il GX FPGA Development Kit Installed Directory Structure 7 lt install dir gt The default Windows installation directory is C altera lt version gt kits arriallGX_2agx125_fpga C board_design_files By demos C documents C examples fas factory recovery Note to Figure 3 2 1 Early release versions might have slightly different directory names Table 3 1 lists the file directory names and a description of their contents Tab
42. nly enabled during transaction performance analysis m Clear Resets the Detected errors and Inserted errors counters to zeros Number of Addresses to Write Read This control determines the number of addresses to use in each iteration of reads and writes Valid values range from 8 to 134217728 m The minimum range when on the slider is at the Min position on the left is the maximum PHY burst of 8 m The maximum range when the slider is at the Max position on the right fills the full address space of the DDR2 SODIMM Data Type This control specifies the type of data contained in the transactions The following data types are available for analysis m PRBS Selects pseudo random bit sequences Frequency rates for production silicon speed grade only Arria GX FPGA Development Kit User Guide February 2011 Altera Corporation Chapter 6 Board Test System 6 15 Using the Board Test System m Memory Selects a generic data pattern stored in the on chip memory of the Arria II GX device m Math Selects data generated from a simple math function within the FPGA fabric W R Control This control specifies the type of transactions to analyze The following transaction types are available for analysis m Write Read Selects read and write transactions for analysis m Read Only Selects read transactions for analysis m Write Only Selects write transactions for analysis The HSMC Tab The HSMC tab allows y
43. or Flash Programming A 2 Creating Flash Files Using the Nios MEDS 0 ee A 2 Programming Flash Memory Using the Board Update Portal 3 Programming Flash Memory Using the Nios 5 2 A 3 Restoring the Flash Device to the Factory Settings A 4 Restoring the MAX II CPLD to the Factory Settings A 5 Additional Information Document Revision History nn Info 1 How to Contact Altera sss esse Gu bee _ Info 1 Arria GX FPGA Development Kit User Guide February 2011 Altera Corporation Contents i Typographic Conventions u u u ur maius III hee Info 1 February 2011 Altera Corporation Arria 1 GX FPGA Development Kit User Guide vi Contents Arria GX FPGA Development Kit User Guide February 2011 Altera Corporation N DTE RYN 1 About This Kit The Altera Arria II GX FPGA Development Kit is a complete design environment that includes both the hardware and software you need to develop Arria GX FPGA designs The PCI SIG compliant board and the one year license for the Quartus II software provide everything you need to begin developing custom Arria II GX FPGA designs The following list describes what you can accomplish with the kit m Develop and test PCI Express PCIe designs m Develop and test memory subsystems consisting of DDR2 and DDR3 memories m
44. ou to perform loopback tests on the HSMC port Figure 6 8 shows the HSMC tab Figure 6 8 The HSMC Tab ARAT Test System Configure Help About Flash Hc Status PLL Lock locked Channel Lock locked Pattern Sync synced HSMC Control Power Monitor Port HSMA x4 Transceivers 0 3 C HSMA x17 LVDS SERDES C 5 x3 Single Ended Loopback Setting r Data Type Error Control PRES7 Detected Errors 0 PRESIS Inserted Errors 0 PRBS23 Insert Error Clear PRB531 Messages Loopback Detected the HSMC Project Tx Rx Please install HSMC loop back connecto r Stop Tx MBytes s 2000 0235 Rx MBytes s 2000 0236 February 2011 Altera Corporation Arria 1 GX FPGA Development Kit User Guide 6 16 Chapter 6 Board Test System Using the Board Test System You must have the loopback HSMC installed on the HSMC connector that you are testing for this test to work correctly The following sections describe the controls on the HSMC tab Status This control displays the following status information during the loopback test m PLL lock Shows the PLL locked or unlocked state m Channel lock Shows the channel locked or unlocked state When locked all lanes are word aligned and channel bonded m Pattern sync Shows the pattern synced or not synced state The pattern
45. out power consumption and thermal modeling refer to AN 358 Thermal Management for FPGAs To avoid damage to the board always have the board POWER switch SW1 in the OFF position before inserting the DC power jack J4 February 2011 Altera Corporation Arria 1 GX FPGA Development Kit User Guide 2 2 References Chapter 2 Getting Started References Use the following links to check the Altera website for other related information For the latest board design files and reference designs refer to the Arria GX FPGA Development Kit page For additional daughter cards available for purchase refer to the Development Board Daughtercards page For the Arria II GX device documentation refer to the Literature Arria II GX Devices page To purchase devices from the eStore refer to the Devices page For Arria II GX OrCAD symbols refer to the Capture CIS Symbols page For Nios II 32 bit embedded processor solutions refer to the Embedded Processing page Arria GX FPGA Development Kit User Guide February 2011 Altera Corporation N BYA 3 Software Installation This chapter explains how to install the following software m Quartus II Subscription Edition Software m Arria II GX FPGA Development Kit m USB Blaster driver Installing the Quartus Il Subscription Edition Software The Quartus II Subscription Edition Software provides the necessary tools used for developing hardware and software for Altera FPGAs In
46. page 2 In the Hardware File Name field specify the flash file that you either downloaded from the Altera website or created on your own If there is a software component to the design specify it in the same manner using the Software File Name field otherwise leave the Software File Name field blank 3 Click Upload The progress bar indicates the percent complete 4 Toconfigure the FPGA with the new design after the flash memory upload process is complete set the USER LOAD switch 5W4 4 to the on position and power cycle the board or press the IMAGE SEL button PB6 until the CONFIG1 LED D12 illuminates and then press the LOAD IMAGE button PB5 Refer to Table 6 1 on page 6 5 for information about the CONFIG LEDs As long as you don t overwrite the factory image in the flash memory device you can continue to use the Board Update Portal to write new designs to the user portion of flash memory If you do overwrite the factory image you can restore it by following the instructions in Restoring the Flash Device to the Factory Settings on page A 4 Arria Il GX FPGA Development Kit User Guide February 2011 Altera Corporation N DTE P YA 6 Board Test System The kit includes a design example and application called the Board Test System to test the functionality of the Arria IT GX FPGA development board The application provides an easy to use interface to alter functional settings and observe the results You can use the applica
47. pdate speed z000mw m Fast The following sections describe the Power Monitor controls Arria 11 GX FPGA Development Kit User Guide February 2011 Altera Corporation Chapter 6 Board Test System 6 19 The Power Monitor General Information The General information controls display the following information about the MAX II device m MAXII Version Indicates the version of MAX II code currently running on the board The MAX II code resides in the lt install dir NkitsNarrialIGX 2agx125 fpgaMfactory recovery and install dir gt kits arrialIGX_2agx125_fpga examples max2 directories Newer revisions of this code might be available on the Arria II GX FPGA Development Kit page of the Altera website m Power Rail Selects the power rail to measure After selecting the desired rail click Reset to refresh the screen with new board readings T A table with the power rail information is available in the Arria GX FPGA Development Board Reference Manual Power Information This control displays RMS current maximum and minimum power readings for the following units m mVolt m mAmp m mWatt Power Graph This control displays the mWatt power consumption of your board over time The green line indicates the current value The red line indicates the maximum value read since the last reset The yellow line indicates the minimum value read since the last reset Graph Settings The following controls allow you
48. pe Er 6 14 WIR COMTO eer RC ae a aed EDI A a arte ar es d ended 6 15 The HSMC Tab e ee eR e DR Rr 6 15 Status tea nade epa ep eti o oes d ee oe iid 6 16 Porb o iis aen pk 6 16 SEMINE aiig keri ede El dc e efto as 6 16 Wate Type cus acest chee e porn eS RE d ta a Katee knee eR Rae LPS 6 16 Error Control eret E RS wk UN A s ere RE RR 6 17 St t secorir isti agn Epia dec ag RE E 6 17 DIOD ECan as ear s 6 17 Performance Indicators rese ceed Wales ERES E nae Ee a er REN 6 17 The Power Mor tot us acd exu eed e wapus Cea ewe eles 6 18 General Informati n sea aes Rer RECUERDO CU EA EXE lets aus auqa 6 19 Power Information ie RC RA eR er 6 19 P oWer Gia pla ex tei ee 6 19 Graph Seton gs 42 EMT 6 19 ROSCt incase ___________ _ 6 19 Calculating POWeE e a DANS kaya ayaka ac 6 20 Configuring the FPGA Using the Quartus II Programmer 2 2 6 20 Appendix A Programming the Flash Memory Device CFI Flash Memory Map ene teeta e ede pawa a wp REY I RE eee s sama A 1 Preparing Design Files f
49. rd Information This control displays static information about your board MAX II rev Indicates the version of MAX II code currently running on the board The MAX II code resides in the install dir NkitsNarrialIGX 2agx125 fpgaNexamples directory Newer revisions of this code might be available on the Arria II GX FPGA Development Kit page of the Altera website MAC Indicates the MAC address of the board Flash Memory Map This control shows the memory map of the flash memory device on your board Arria GX FPGA Development Kit User Guide February 2011 Altera Corporation Chapter 6 Board Test System 6 7 Using the Board Test System The GPIO Tab The GPIO tab allows you to interact with all the general purpose user I O components on your board You can write to the LCD read DIP switch settings turn LEDs on or off and detect push button presses Figure 6 3 shows the GPIO tab Figure 6 3 The GPIO Tab ARAT Test System EE N Configure Help About Config GPIO Flash SSRAM DORS DDRZ e feria zr ex J eee IT GX Display Development Kit Read User DIP switch 1 OFF s 0 ON User LEDs e Messages Detected the GPIO SRAM Flash Project The following sections describe the controls on the GPIO tab LCD This control allows you to display text strings on the character LCD on your board Type text in the
50. re option for the added file Arria Il GX FPGA Development Kit User Guide February 2011 Altera Corporation Appendix A A 5 Restoring the MAX 11 CPLD to the Factory Settings 10 11 12 13 Click Start to download the selected configuration file to the FPGA Configuration is complete when the progress bar reaches 100 The CONF DONE LED D14 and the four user LEDs D7 D10 illuminate indicating that the flash device is ready for programming On the Windows Start menu click All Programs gt Altera gt Nios II EDS gt Nios II Command Shell In the Nios command shell navigate to the lt install dir NkitsNarrialIGX 2agx125 fpgaMfactory recovery directory and type the following command to run the restore script restore sh Restoring the flash memory might take several minutes Follow any instructions that appear in the Nios II command shell After all flash programming completes cycle the POWER switch SW1 off then on Using the Quartus II Programmer click Add File and select install dir NkitsNarrialIGX 2agx125 fpgaMfactory recovery ArrialIGX 2agx125 dev _ bup sof Turn on the Program Configure option for the added file Click Start to download the selected configuration file to the FPGA Configuration is complete when the progress bar reaches 100 The CONF DONE LED D14 and the four user LEDs D7 D10 illuminate indicating the flash memory device is now restored with the factory contents Cycl
51. rede ee or b e ee 6 3 Using the Board Test System aa uma baka een 6 4 The Configure Menu uqa saywashaka aa rb pad e dence 6 4 The Contig Tabris TN E saa PE D eS 6 4 MAX ID IREGISEELS t Rire eter bu kuku Me nn beo pc et once ted ue Doi e DAD 6 5 JTAG Chaine idee ex e 6 6 Board Informati n vore bw ERE ANAS A AR rd a V p RC ee aE 6 6 Flash Memory Map ke me ke e n eda ec rtis er OPE EE RE E aed 6 6 The GPIO ek ed quema suo ved aided 6 7 ep 6 7 UserDipswitchusss eter terr eps de 6 7 User LEDS ick a tees a __ _ 6 8 Pushbutton Switches 24 lluta tr done aod Goa es dee ews kaa 6 8 The Flash pa hale a BA a Ghee MEG w Geen aaa Irak aoe 6 8 i 6 9 6 9 Random Test Ere x don 6 9 Query ket hk 6 9 Increment Test 4 2 Ande Paver gene naa 6 9 ol aa cua eee hee Yau a 6 9 February 2011 Altera Corporation Arria Il GX FPGA Development Kit User Guide iv Contents DSE eos eee eee ee eee ete ee su
52. ressed Start m Write Read and Total performance bars Show the percentage of maximum theoretical data rate that the requested transactions are able to achieve m Write MBytes s Read MBytes s and Total MBytes s Show the number of bytes of data analyzed per second The data bus is 16 bits wide and the frequency is 400 MHz double data rate 800 Mbps per pin equating to a theoretical maximum bandwidth of 1600 MBps Error Control These controls display data errors detected during analysis and allow you to insert errors m Detected Errors Displays the number of data errors detected in the hardware m Inserted Errors Displays the number of errors inserted into the transaction stream m Insert Error Inserts a one word error into the transaction stream each time you click the button Insert Error is only enabled during transaction performance analysis m Clear Resets the Detected errors and Inserted errors counters to zeros Number of Addresses to Write Read This control determines the number of addresses to use in each iteration of reads and writes Valid values range from 8 to 67108864 m Theminimum range when on the slider is at the Min position on the left is the maximum PHY burst of 8 m Themaximum range when the slider is at the Max position on the right fills the full address space of the DDR3 Data Type This control specifies the type of data contained in the transactions The following data typ
53. rved Switch 3 has the following options 3 DIP2 m When on reserved Off m When off reserved Switch 4 has the following options 4 USER LOAD m When on the PFL loads the user hardware 1 design on power up Off m When off the PFL loads the factory design on power up Switch 5 has the following options 5 PWR MON m When on reserved Off m When off reserved Switch 6 has the following options 6 USB DISn m When on reserved Off m When off reserved Switch 7 has the following options 7 CLK EN m When on all on board oscillators are enabled On m When off on board oscillators to the FPGA are disabled Switch 8 has the following options 8 CLK SEL m When on programmable oscillator clock U30 is selected On m When off LVPECL SMA clock J10 and J11 is selected 3 Set the board jumpers to match Table 4 3 and Figure 4 1 Table 4 3 JTAG Chain Jumper Settings Part 1 of 2 desc eh Function siunt eae This jumper has the following options m Installing the shunt removes the MAX Il EPM2210 device from the m Removing the shunt includes HSMC port A in the JTAG chain J9 pins 1 2 MAX DIS JTAG chain Not installed m Removing the shunt includes the MAX II EPM2210 device in the JTAG chain This jumper has the following options J9 pins 3 4 HSMA DIS m Installing the shunt removes HSMC port A from the JTAG chain Installed February 2011 Altera Corporation Arria 1 GX FPGA Development Kit User Guide 4 4 Chapt
54. sh memory on your board Figure 6 5 shows the SSRAM tab Figure 6 5 The SSRAM Tab Configure Help About oard Test system rr Kai Config GPIO Flash SSRAM DDR3 0082 SRAM Start Address Range 0 000 0000 QxO1F FFFF 0000 0000 Read Write Random a Increment E Lue os 7 cr F74 729CD EFE18B53 FA784168 5D6EB780 0000 0010 959 1986 F2A9E62 594BllO0E 4154 8 7 0000 0020 DA2C2936 ESEAB43B BESZEDO 54 718 2 0000 0030 4 605 42 62250427 32890522 S6C8E42 0000 0040 97100789 66830B46 DDB684D3 F16943C 0000 0050 SF1SF181 S86EBB29 FASOB890 F64DFB37 0000 0060 DEFFEDO4 DFC00015 D8400215 D8800315 0000 0070 DSC00415 D9000515 9400615 9800715 0000 0080 pscoosls DOO0B307A DAOO0915 DA400A15 0000 0030 15 DACOOCIS DBOO0D15 DB400E15 0000 0040 DESOOF1S DBCO1O1S D9401115 EBFFFFO4 0000 0080 DBCO1Z15 00093134 2880004C 10000326 0000 00C0 20000226 020012 0 00000306 DF401215 ESBFFF17 99401117 DF401217 0000 00 0 00017 28017074 D8400217 D8800317 Messages 0000 00F0 D8C00417 D9000517 9400617 D9800717 Dete
55. t kits arrialIGX_2agx125_fpga examples board_test_system directory and run the BoardTestSystem exe application On Windows click Start gt All Programs gt Altera gt Arria GX FPGA Development Kit lt version gt gt Board Test System to run the application A GUI appears displaying the application tab that corresponds to the design running in the FPGA The Arria GX FPGA development board s flash memory ships preconfigured with the design that corresponds to the Config GPIO and SSRAM and Flash tabs If you power up your board with the USER_LOAD switch SW4 4 in the off position or if you load your own design into the FPGA with the Quartus II Programmer you receive a message prompting you to configure your board with a valid Board Test System design Refer to The Configure Menu for information about configuring your board February 2011 Altera Corporation Arria Il GX FPGA Development Kit User Guide 6 4 Chapter 6 Board Test System Using the Board Test System Using the Board Test System This section describes each control in the Board Test System application The Configure Menu Each test design tests different functionality and corresponds to one or more application tabs Use the Configure menu to select the design you want to use Figure 6 2 shows the Configure menu Figure 6 2 The Configure Menu Configure Help About Configure with SRAM Flash GPIO Design Configure with DDR3 Design Configure with DDR
56. text boxes and then click Write If you exceed the 16 character display limit on either line a warning message appears User Dipswitch This read only control displays the current positions of the switches in the user DIP switch bank SW2 Change the switches on the board to see the graphical display change accordingly February 2011 Altera Corporation Arria 1 GX FPGA Development Kit User Guide 6 8 Chapter 6 Board Test System Using the Board Test System User LEDs This control displays the current state of the user LEDs Click the graphical representation of the LEDs to turn the board LEDs on and off Pushbutton Switches This read only control displays the current state of the board user push buttons Press a push button on the board to see the graphical display change accordingly The Flash Tab The Flash tab allows you to read and write flash memory on your board Figure 6 4 shows the Flash tab Figure 6 4 The Flash Tab zn lx Configure Help About Config GPIO Flash 55 DDRZ ASME Flash Start Address Range 0 000 0000 0000 0000 Read Write Random test Increment test CFI Query Reset Erase o 47 s cr 0000 0000 0001703 01800074 32001483A 31BFF804 0000 0010 303FFD1E 00002032A 0010 03 01800034 0000 0020 21800704 4197 83 00808054 10808054 0000 0030 12 5883 103EE83A 6 FF
57. the user hardware portion of flash memory and provides links to useful information on the Altera website including kit specific links and design resources 7 After successfully updating the user hardware flash memory you can load the user design from flash memory into the FPGA To do so set the USER LOAD switch SW4 4 to the on position and power cycle the board The source code for the Board Update Portal design resides in the install dir NkitsNarrialIGX 2agx125 fpgaNexamples directory If the Board Update Portal 15 corrupted or deleted from the flash memory refer to Restoring the Flash Device to the Factory Settings on page A 4 to restore the board with its original factory contents Connecting to the Board Update Portal Web Page This section provides instructions to connect to the Board Update Portal web page gt Before you proceed ensure that you have the following m APC with a connection to a working Ethernet port on a DHCP enabled network A separate working Ethernet port connected to the same network for the board m The Ethernet and power cables that are included in the kit To connect to the Board Update Portal web page perform these steps 1 With the board powered down set the USER LOAD switch SW4 4 to the off position 2 Attach the Ethernet cable from the board to your LAN 3 Power up the board The board connects to the LAN s gateway router and obtains an IP address The LCD on the board displays
58. tion to test board components modify functional parameters observe performance and measure power usage The application is also useful as a reference for designing systems To install the application follow the steps in Installing the Arria GX FPGA Development Kit on page 3 2 The application provides access to the following Arria II GX FPGA development board features m General purpose I O GPIO SRAM Flash memory DDR2 and DDR3 memories HSMC connectors m Character LCD m Programmable oscillator The application allows you to exercise most of the board components While using the application you reconfigure the FPGA several times with test designs specific to the functionality you are testing February 2011 Altera Corporation Arria 1 GX FPGA Development Kit User Guide 6 2 Chapter 6 Board Test System The Board Test System GUI communicates over the JTAG bus to a test design running in the Arria IT GX device Figure 6 1 shows the initial GUI for a board that is in the factory configuration Figure 6 1 Board Test System Graphical User Interface Board Test System m Configure Help About J GPIO Flash ssnaM DDR3 ODR2 enc Board Information Board Name Arria II GX FPGA Development Kit Board P N PN 6XX 40784R Serial number SN 2A125F00778 Factory test version Test Software Version 1 MAC 00 07 ed 15 04 5f gt MAX II Registers pso 5 v
59. to define the look and feel of the power graph m Scale Select Specifies the amount to scale the power graph Select a smaller number to zoom in to see finer detail Select a larger number to zoom out to see the entire range of recorded values m Update Speed Specifies how often to refresh the graph Reset This control clears the graph resets the minimum and maximum values and restarts the Power Monitor February 2011 Altera Corporation Arria Il GX FPGA Development Kit User Guide 6 20 Chapter 6 Board Test System Configuring the FPGA Using the Quartus Programmer Calculating Power The Power Monitor calculates power by measuring two different voltages with the LT2418 A D and applying the equation P V x I to determine the power consumption The LT2418 measures the voltage after the appropriate sense resistor Vsense and the voltage drop across that sense resistor Vdif The current I is calculated by dividing the measured voltage drop across the resistor by the value of the sense resistor I Vdif R Through substitution the equation for calculating power becomes P V x I Vsense x Vdif R Vsense Vdif x 1 009 except for the A2VCC rail which uses 001 for R You can verify the power numbers shown in the Power Monitor with a digital multimeter that is capable of measuring microvolts to ensure you have enough significant digits for an accurate calculation Measure the voltage on one side of the resistor t
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