Home

C505 C505 C

1. SIEMENS Fundamental Structure C505 C505C Voc V Oscillator SS Watchdog XRAM RAM ROM 256 x 8 256 x 8 16k x 8 XTAL1 OSC amp Timing XTAL2 CPU ALE DOEN Programmable PREN Watchdog Timer EA ott mer 8 Bit Digit 1 0 8 Bit Digit O 8 Bit Analog In USART Generator 8 Bit Digit I O Port 3 Port 4 VAREF A D Converter VAGND SBi Emulation Support Logic YA C505C only MCB03286 Figure 2 1 Block Diagram of the C505 Semiconductor Group 2 2 1997 08 01 IE Fundamental Structure ii zh gt C505 C505C 2 1 CPU The C505 is efficient both as a controller and as an arithmetic processor It has extensive facilities for binary and BCD arithmetic and excels in its bit handling capabilities Efficient use of program memory results from an instruction set consisting of 44 one byte 41 two byte and 15 three byte instructions With a 16 MHz external clock 58 of the instructions execute in 375 ns 20 MHz 300 ns The CPU Central Processing Unit of the C505 consists of the instruction decoder the arithmetic section and the program control section Each program instruction is decoded by the instruction decoder This unit generates the internal signals controlling the functions of the individual units within the CPU They have an effect on the source and destination of data transfers and control the ALU processing The arithmetic section of the processor per
2. Special Function Register DPSEL Address 925 Reset Value XXXXX000p Bit No MSB LSB 7 6 5 4 3 2 1 0 924 u z a z 2 a 0 DPSEL Bit Function DPSEL 2 0 Data pointer select bits DPSEL 2 0 defines the number of the actual active data pointer DPTRO 7 Semiconductor Group 4 6 1997 08 01 IEMEN External Bus Interface S S C505 C505C Spee eR Ear aL DPSEL 92 p DPTR7 DPSEL Selected Data 2 1 0 pointer DPTR 0 DPTR 1 DPTR 2 DPH 83j DPL 82 4 DPTR 3 DPTR 4 DPTR5 DPTR6 DPTR7 DPTRO External Data Memory MCD00779 O O O O Cc c amp c c O O O O Figure 4 3 Accessing of External Data Memory via Multiple Datapointers 4 6 3 Advantages of Multiple Datapointers Using the above addressing mechanism for external data memory results in less code and faster execution of external accesses Whenever the contents of the datapointer must be altered between two or more 16 bit addresses one single instruction which selects a new datapointer does this job If the program uses just one datapointer then it has to save the old value with two 8 bit instructions and load the new address byte by byte This not only takes more time it also requires additional space in the internal RAM 4 6 4 Application Example and Performance Analysis The following example shall demonstrate the invol
3. C505 C505C 10 6 ROM Verification Characteristics for C505 2R ROM Verification Mode 1 Parameter Symbol Limit Values Unit min max Address to valid data tavav 5 CLP ns P1 0 P1 7 Address P1 0 P1 7 AQ A7 Inputs P2 6 P2 7 PSEN Vas P2 0 P2 5 A8 A13 ALE EA Vi Data P0 0 P0 7 DO D7 RESET V MCT02629 ROM Verification Mode 1 Semiconductor Group 10 15 1997 08 01 SIEMENS Device Specifications C505 C505C ROM Verification Mode 2 Parameter Symbol Limit Values Unit min typ max ALE pulse width Tawo CLP ns ALE period tacy 6 CLP ns Data valid after ALE lova 2 CLP ns Data stable after ALE psA 4 CLP ns P3 5 setup to ALE low fas TCLH ns Oscillator frequency 1 CLP 4 6 MHz ALE Port 0 CCCQ Data Valid MCT02613 ROM Verification Mode 2 Semiconductor Group 10 16 1997 08 01 IE Device Specifications SIEMENS C505 C505C 0 2 Voo 0 9 Test Points 0 45 V MCT00039 AC Inputs during testing are driven at Voc 0 5 V for a logic 1 and 0 45 V for a logic 0 Timing measurements are made at V for a logic 1 and Vj for a logic 0 AC Testing Input Output Waveforms Voy 04 V Timing Reference Vi cad Points V cad 0 1 V VoL 0 1 V MCT00038 For timing purposes a port pin is no longer floating when a 100
4. Figure 8 3 Functional Block Diagram of the Oscillator Watchdog The frequency coming from the RC oscillator is divided by 10 and compared to the on chip oscillator s frequency If the frequency coming from the on chip oscillator is found lower than the frequency derived from the RC oscillator the watchdog detects a failure condition the oscillation at the on chip oscillator could stop because of crystal damage etc In this case it switches the input of the internal clock system to the output of the RC oscillator This means that the part is being clocked even if the on chip oscillator has stopped or has not yet started At the same time the watchdog activates the internal reset in order to bring the part in its defined reset state The reset is performed because clock is available from the RC oscillator This internal watchdog reset has the same effects as an externally applied reset signal with the following exceptions The Watchdog Timer Status flag WDTS is not reset the Watchdog Timer is however stopped and bit OWDS is set This allows the software to examine error conditions detected by the Watchdog unit even if meanwhile an oscillator failure occured The oscillator watchdog is able to detect a recovery of the on chip oscillator after a failure If the frequency derived from the on chip oscillator is again higher than the reference the watchdog starts a final reset sequence which takes typ 1 ms Within that time the clo
5. 1997 08 01 5 4 Power On Reset of the C505 Semiconductor Group Figure 5 2 SIEMEN System Reset S C505 C505C 5 3 Hardware Reset Timing This section describes the timing of the hardware reset signal The input pin RESET is sampled once during each machine cycle This happens in state 5 phase 2 Thus the external reset signal is synchronized to the internal CPU timing When the reset is found active high level the internal reset procedure is started It needs two complete machine cycles to put the complete device to its correct reset state i e all special function registers contain their default values the port latches contain 1 s etc Note that this reset procedure is also performed if there is no clock available at the device This is done by the oscillator watchdog which provides an auxiliary clock for performing a perfect reset without clock at the XTAL1 and XTAL2 pins The RESET signal must be active for at least one machine cycle after this time the C505 remains in its reset state as long as the signal is active When the signal goes inactive this transition is recognized in the following state 5 phase 2 of the machine cycle Then the processor starts its address output when configured for external ROM in the following state 5 phase 1 One phase later state 5 phase 2 the first falling edge at pin ALE occurs Figure 5 3 shows this timing for a configuration with EA O external program memory Thu
6. The function of the shaded bit is not described in this section Symbol Function PDS Power down start bit The instruction that sets the PDS flag bit is the last instruction before entering the power down mode IDLS Idle start bit The instruction that sets the IDLS flag bit is the last instruction before entering the idle mode SD Slow down mode bit When set the slow down mode is enabled GF1 General purpose flag GFO General purpose flag PDE Power down enable bit When set starting of the power down is enabled IDLE Idle mode enable bit When set starting of the idle mode is enabled Semiconductor Group 9 1 1997 08 01 SIEMENS Power Saving Modes C505 C505C Special Function Register PCON1 Mapped Address 88H Reset Value OXXOXXXXp Bit No MSB LSB 7 6 5 4 3 2 1 0 884 EWPD WS PCON1 Symbol Function EWPD External wake up from power down enable bit Setting EWPD before entering power down mode enables the external wake up from power down mode capability more details see section 9 4 2 WS Wake up from power down source select WS 0 wake up via pin P3 2 INTO WS 1 wake up via pin P4 1 RXDC Pin P3 2 INTO is selected as wake up source after reset Reserved bits for future use Read by CPU returns undefined values Semiconductor Group 9 2 1997 08 01 IE Power Saving Modes 2 ii ex C505 C505
7. 1 The notation n n 1 to F in the address definition defines the number of the related message object 2 X means that the value is undefined and the location is reserved U means that the value is unchanged by a reset operation U values are undefined as X after a power on reset operation Semiconductor Group 3 19 1997 08 01 IEMEN External Bus Interface S S C505 C505C 4 External Bus Interface The C505 allows for external memory expansion The functionality and implementation of the external bus interface is identical to the common interface for the 8051 architecture with one exception if the C505 is used in systems with no external memory the generation of the ALE signal can be suppressed Resetting bit EALE in SFR SYSCON register the ALE signal will be gated off This feature reduces RFI emissions of the system 4 1 Accessing External Memory It is possible to distinguish between accesses to external program memory and external data memory or other peripheral components respectively This distinction is made by hardware accesses to external program memory use the signal PSEN program store enable as a read strobe Accesses to external data memory use RD and WR to strobe the memory alternate functions of P3 7 and P3 6 Port 0 and port 2 with exceptions are used to provide data and address signals In this section only the port O and port 2 functions relevant to external memory accesses a
8. switches the control register s low byte to 01 4 leaves the control register s high byte and the interrupt register undefined does not change the other registers including the message objects notified as UUUU selects the prescaler for the CAN controller clock using the bit CMOD in SYSCON register The first hardware reset after power on leaves the unchanged registers in an undefined state of course The value 014 in the control register s low byte prepares for software initialization Software Initialization The very first step of the initialization is the CAN controller input clock selection A 2 prescaler is enabled by default after reset figure 6 39 Setting bit CMOD SYSCON 3 disables the prescaler The purpose of the prescaler selection is i to ensure that the CAN controller is operable when fosc is over 10 MHz bit CMOD 0 ii to achieve the maximum CAN baudrate of 1 Mbaud when fosc is 8 MHz bit CMOD 1 SYSCON 3 CMOD fosc Full CAN Module Condition CMOD 0 when fosc 10 MHz MCS03296 Frequency MHz CMOD BRP CAN fosc CAN SYSCON 3 BTRO 0 baudrate 5 Mbaud sec 8 8 1 000000p 1 8 4 0 000000p 0 5 16 8 0 000000p 1 Note The switch configuration shows the reset state of bit CMOD Figure 6 39 CAN controller input clock selection Semiconductor Group 6 88 1997 08 01 SIEMENS On Chip Peripheral Components C505C Only Special Functi
9. 6 40 to 6 42 Refreshing of the WDT 8 5 Compare TUNGNON so duc Spee AUS Reset operation 8 5 Compare mode 0 6 32 to 6 35 Starting of the WDT 8 4 Compare mode 1 6 36 to 6 37 Time out periods 5 8 2 Compare mode interrupts 6 38 WD T eol kun ae Bunnies 3 15 8 3 General operation 6 30 WDTPSEL 3 15 8 2 Port functions 5e a de Ferns 2 e eso 6 23 WDTREL 3 13 3 15 8 2 Registers 6 25 to 6 29 WDTS 0 3 1 5 8 3 Reload configuration 6 31 WBousstietteniseu 3 eq eeu ea 3 16 Timings Were tte aed eee edness 3 15 9 2 Data memory read cycle 10 14 Data memory write cycle 10 15 External clock timing 10 15 AMBPU set ote tide Ruta Sdn Proa AETA e oro i053 IMAP eaedem 3 3 3 16 ROM verification mode 1 10 16 XPAGE SLOTS 3 5 3 12 3 15 ROM verification mode 2 10 17 DEA EE Eee RSE RE BEES Be Teta atgiete Accessing through DPTR 25 o MMC 3 13 3 16 6 27 ACeossIg HOON RORI stanan Sae TMOD uie ft ons 3 13 3 15 6 18 Behaviour of P2 PO 3 9 E tert NNNM 3 15 6 17 DesecopelaloDc utere gi s LC UH DE Mi E 3 15 6 17 TARIE e Pe Gunna MOMS Nee 10 TSEGTu m echt cs esu 3 18 6 71 XPAGE regist ausos aet deed 3 5 TOE GO et i oca foment de 3 18 6 71 JSR ONEA AS POI miian 2 TX IS t cte dtc eus 3 16 6 43 Write page address to P2
10. An object with its direction set as transmit can be configured to be automatically sent whenever a remote frame with a matching identifier taking into account the respective global mask register is received over the CAN bus By requesting the transmission of a message with the direction set as receive a remote frame can be sent to request that the appropriate object be sent by some other node Each object has separate transmit and receive interrupts and status bits allowing the microcontroller full flexibility in detecting when a remote data frame has been sent or received For general purpose two masks for acceptance filtering can be programmed one for identifiers of 11 bits and one for identifiers of 29 bits However the microcontroller must configure bit XTD Normal or Extended Frame Identifier in the message configuration register for each valid message to determine whether a standard or extended frame will be accepted The last message object has its own programmable mask for acceptance filtering allowing a large number of infrequent objects to be handled by the system The object layer architecture of the CAN controller is designed to be as regular and orthogonal as possible This makes it easy to use and small for implementation The message storage is implemented in an intelligent memory which can be addressed by the CAN controller and the microcontroller interface The content of various bit fields in the object are used to perform
11. 7 13 Behavio l atresel is eo 2 ce 5 3 FIGquest NAGS iti natai TP NOE Block diagram cep repe 8 7 FIOSDOUSE UNG ns cA tese ch ue d EE ON CHARME 2 4 3 16 Sources and vector addresses 7 15 OWDS 3 15 8 6 INTTID its Rcs nen 3 18 6 70 INTTPIND dier tek 3 18 6 76 IPO 3 12 3 13 3 15 7 12 8 3 8 6 P airian e ee tM fca 2 4 3 16 Pi n eae aa 3 12 3 16 7 12 RO ais hr aN SE uu aet 3 12 3 15 eee T a aa E a 3 14 3 18 6 70 Pi tarea en AURA EA da 3 12 3 15 IRCON 3 12 3 16 6 28 6 103 7 9 PIANA 3 12 3 15 6 1 6 109 PO E NAP Sse ESL PU edges cris lu SEMAINE Bd qp Lees se caaraareeerta ds T5 4D PA PM Sharada ot Aiea EN 3 12 3 17 Package information 10 19 CAO ea nS BEE P Idee TEST Parallel UO sian areena shee 6 1 to 6 14 LART aes heat tas ait tats a deat 3 14 3 18 6 79 PCON 3 13 3 15 6 46 9 1 EO oae dac Ge ath es operat 3 18 6 69 PCON1 3 13 3 15 9 2 EG 1525s Rate et Gn d ad 3 18 6 69 P ten Salata faces teen 3 15 9 1 LEOZ oe a Cod d 3 18 6 69 PDS LoL LLL LLL 3 15 9 1 LGMLO essen S tuo Bp Ta Pin Configuration 0 1 4 ee 9147310 0 9 Pin Definitions and functions 1 5 MEMO a c emits Wa LL MEE MEME tees 6 1 to 6 14 Meus duit ode i n C Alternate functions 6 2 ce THIDOLc eds datioqde aq psg ix Loading and interfacing 6 13 Output drivers circuitry 6 9 MOr out eoe p Mesa eat t
12. Interfacing the C505 to devices with float times up to 25 ns is permissible This limited bus contention will not cause any damage to port 0 drivers Semiconductor Group 10 9 1997 08 01 SIEMENS Device Specifications C505 C505C AC Characteristics 20 MHz for C505 cont d External Data Memory Characteristics Parameter Symbol Limit Values Unit 20 MHz clock Variable Clock Duty Cycle 1 CLP 2 MHz to 0 5 to 0 5 20 MHz min max min max RD pulse width TRLRH 120 3CLP 30 ns WR pulse width tWLWH 120 3CLP 30 ns Address hold after ALE TLLax2 35 CLP 15 ns RD to valid data in fai pv 75 2 CLP ns TCL 4 50 Data hold after RD TRHDXx 0 0 ns Data float after RD faupz 38 CLP 12 ns ALE to valid data in Titov 150 4CLP 50 ns Address to valid data in Tavov 150 4 CLP ns TCLumin 75 ALE to WR or RD fiw 60 90 CLP CLP ns TCLimin 15 TOL 415 Address valid to WR Tavwe 70 2CLP 30 ns WR or RD high to ALE high TWHLH 10 40 TCL44 4 15 TCLumint 15 ns Data valid to WR transition favwx 5 TCLimn 20 ns Data setup before WR favwH 125 3 CLP ns TCL min DO Data hold after WR wuax 5 TCLymin 20 ns Address float after RD TRLaz 0 0 ns Semiconductor Group 10 10 1997 08 01 SIEMENS Device Specifications C505 C505C External Clock Drive Characteristics
13. 3 6 ioo o PERENNE eaten ies 3 17 6 97 Nate pagexadaress ID APAGES pce EXIB Gh ein Pua e Rete ads ova DUDEN stis 950 019 09 TXOK e RC 3 18 6 68 DPA ON HET EET 3 18 6 77 UARO inb rins 3 14 3 18 6 79 DUARTE S 3 14 3 18 6 79 UGMLO 245329 99122 35 3 14 3 18 6 73 HIGIMET e rhe se 3 14 3 18 6 73 UMLMO 3 14 3 18 6 74 Semiconductor Group 11 5 1997 08 01
14. 4 Request flag is cleared by hardware E C505C Only P 0 n g DO 5 c c o coc MCB03303 Figure 7 1 Interrupt Structure Overview Part 1 Semiconductor Group 7 2 1997 08 01 IE Interrupt System SIEMENS C505 C505C Timer 1 Le S Overflow o d TCON 7 q IENO 3 u PLAY e AN1 n cet IRCON 3 8 IEN1 3 Bit addressable IENO 7 4 Request flag is cleared by hardware MCB03304 Figure 7 2 Interrupt Structure Overview Part 2 Note Each of the 15 CAN controller message objects C505C only shown in the shaded area of Figure 7 1 provides the bits flags Semiconductor Group 7 3 1997 08 01 Interrupt System SIEMENS C505 C505C 1 ce SCON 0 1 SCONA IENO 4 P1 2 E Head INTS BD 7S 0 CC2 IRCON 4 i IEN1 4 i Timer 2 i Overflow P1 5 E AN5 q T2EX u IEN1 7 e P1 3 n INT6 IEX6 C CO3 IRCON 5 d IEN1 5 Bit addressable 4 Request flag is cleared by hardware MCB03305 Figure 7 3 Interrupt Structure Overview Part 3 Semiconductor Group 7 4 1997 08 01 Interrupt System SIEMENS C505 C505C 7 14 Interrupt Registers 7 1 1 Interrupt Enable Registers Each interrupt vector can be individually enabled or disabled by setting or clearing the corresponding bit in the interrupt enable registers IENO and IEN1 Register IENO also contains the global disable bit EA
15. ADDAT Cont conv BSY Bit Single conv IADC Bit oe First instr of an interrupt routine Start of next conversion Start of A D conversion cycle in continuous mode E ADCC x b Jp PP A D Conversion Cycle H Write ADDAT T Cont conv BSY Bit x l Ea Single conv IADC Bit First instr of an interrupt routine MCT03301 Figure 6 45 A D Conversion Timing in Relation to Processor Cycles Semiconductor Group 6 106 1997 08 01 SIEMENS On Chip Peripheral Components C505 C505C Depending on the selected prescaler ratio see figure 6 43 two different relationships between machine cycles and A D conversion are possible The A D conversion is always started with the beginning of a processor cycle when it has been started by writing SFR ADST with dummy data The ADST write operation may take one or two machine cycles In figure 6 45 the instruction MOV ADST 0 starts the A D conversion machine cycles X 1 and X The total A D conversion sample and conversion phase is finished with the end of the 10th ADC clock cycle after the A D conversion start The actual machine number of machine cycles needed follows the table in Figure 6 44 In the next machine cycle the conversion result is written into the ADDAT register and can be read in the same cycle by an instruction e g MOV A ADDAT If continuous conversion is selected bit ADM set the next conversion is started wi
16. and 2 Either SM2 0 or the received 9th data bit 1 If either of these conditions is not met the received frame is irretrievably lost and RI is not set If both conditions are met the received 9th data bit goes into RB8 and the first 8 data bit goes into SBUF One bit time later whether the above conditions were met or not the unit goes back to looking for a 1 to 0 transition at the RxD input Note that the value of the received stop bit is irrelevant to SBUF RB8 or RI Semiconductor Group 6 57 1997 08 01 On Chip Peripheral Components SIEMENS C505 C505C i Internal Bus 2 TB8 7 SBUF Stop Bit Shift gt Start Generation Data TX Control gt 16 TX Clock TI Send Baud Serial 21 Rate e Port Clock Interrupt gt 16 1 to 0 RX Clock RI Load r Transition Start SBUF Detector RX Control 1FF4 Shift Bit Detector A uid Input Shift Register Bits RXD Shift Load T Shit SBUF SZ SBUF Read SBUF NSZ Internal Bus MCS02105 Figure 6 28 Serial Interface Mode 2 and 3 Functional Diagram Semiconductor Group 6 58 1997 08 01 SIEMENS On Chip Peripheral Components C505 C505C Transmit S N e E e gt e oo CO aw ao Be ee D CN co e 5 gg ar g mi os c Ss E o zz e 5 F 2 i g aig zx E 2 wo c ala 5 x x D
17. must be programmed to a one 1 for that function to operate except for TxD and WR The secondary functions are assigned to the pins of port 3 as follows 5 P3 0 RxD Receiver data input asynch or data input output synch of serial interface 7 P3 1 TxD Transmitter data output asynch or clock output synch of serial interface 8 P3 2 INTO External interrupt O input timer 0 gate control input 9 P3 3 INTI External interrupt 1 input timer 1 gate control input 10 P3 4 TO Timer 0 counter input 11 P3 57 T1 Timer 1 counter input 12 P3 6 WR WR control output latches the data byte from port 0 into the external data memory 13 P3 7 RD RD control output enables the external data memory Input O Output Semiconductor Group 1 6 1997 08 01 SIEMENS Introduction C505 C505C Table 1 1 Pin Definitions and Functions Symbol Pin Number 1 O Function P4 0 6 y o Port 4 P4 1 28 O jis a 2 bit quasi bidirectional port with internal pull up arrangement Port 4 pins that have 1 s written to them are pulled high by the internal pull up transistors and in that state can be used as inputs As inputs port 4 pins being externally pulled low will source current Z in the DC characteristics because of the internal pullup transistors The output latch corresponding to the secondary function RXDC must be programmed to a one 1 for that function to operate The secondary functions are assigned to the two pins of port 4
18. of the interrupt request The interrupt identifier INTID a number in the interrupt register indicates the cause of an interrupt When no interrupt is pending the identifier will have the value 00 If the value in INTID is not 00 then there is an interrupt pending If bit IE in the control register is set also the interrupt line is activated The interrupt line remains active until either INTID gets 00 ie the interrupt requester has been serviced or until IE is reset ie interrupts are disabled The interrupt with the lowest number has the highest priority If a higher priority interrupt lower number occurs before the current interrupt is processed INTID is updated and the new interrupt overrides the last one Table 6 7 below lists the valid values for INTID and their corresponding interrupt sources Table 6 7 Interrupt IDs INTID Cause of the Interrupt 00 Interrupt idle There is no interrupt request pending 01 Status change interrupt The CAN controller has updated not necessarily changed the status register This can refer to a change of the error status of the CAN controller EIE is set and BOFF or EWRN change or to a CAN transfer incident SIE must be set like reception or transmission of a message RXOK or TXOK is set or the occurrence of a CAN bus error LEC is updated The microcontroller may clear RXOK TXOK and LEC however writing to the status partition of the control register can ne
19. request is released figure 5 2 IIl However an externally applied reset still remains active figure 5 2 IV and the device does not start program execution figure 5 2 V before the external reset is also released Although the oscillator watchdog provides a fast internal reset it is additionally necessary to apply the external reset signal when powering up The reasons are as follows Termination of Software Power Down Mode Reset of the status flag OWDS that is set by the oscillator watchdog during the power up sequence Using a crystal or ceramic resonator for clock generation the external reset signal must be held active at least until the on chip oscillator has started and the internal watchdog reset phase is completed after phase III in figure 5 2 When an external clock generator is used phase ll is very short Therefore an external reset time of typically 1 ms is sufficent in most applications Generally for reset time generation at power on an external capacitor can be applied to the RESET pin Semiconductor Group 5 3 1997 08 01 System Reset C505 C505C SIEMENS Sepp Y00190 1292000 OH 89 Xew pus 393H aw so q VEM Xo aaljoe aouanbas stl pe xew ueiboid jo vel Jo asneoaq 13S3u eu SUO 1e loieNoS Il yoo srl gi dA ceu s 13934 u Een SUels 280 e HOd je 13534 JO1E II9SQ Dy WO 490 9 suog jepun lt _ SUIEWAI Od diy9 u0 UQ J9MOg A N Ill Il 1393H mans SHOd
20. within each priority level there is a second priority structure determined by the polling sequence as follows Within one interrupt group the left interrupt is serviced first The interrupt groups are serviced from top to bottom of the table Semiconductor Group 7 13 1997 08 01 IE Interrupt System SIEMENS C505 C505C 7 3 How Interrupts are Handled The interrupt flags are sampled at S5P2 in each machine cycle The sampled flags are polled during the following machine cycle If one of the flags was in a set condition at S5P2 of the preceeding cycle the polling cycle will find it and the interrupt system will generate a LCALL to the appropriate service routine provided this hardware generated LCALL is not blocked by any of the following conditions 1 An interrupt of equal or higher priority is already in progress 2 The current polling cycle is not in the final cycle of the instruction in progress 3 The instruction in progress is RETI or any write access to registers IENO IEN1 or IPO IP1 Any of these three conditions will block the generation of the LCALL to the interrupt service routine Condition 2 ensures that the instruction in progress is completed before vectoring to any service routine Condition 3 ensures that if the instruction in progress is RETI or any write access to registers IENO IEN1 or IPO IP1 then at least one more instruction will be executed before any interrupt is vectored to this delay guarantees
21. 01 IE Interrupt System SIEMENS C505 C505C The timer 2 interrupt is generated by the logical OR of bit TF2 in register T2CON and bit EXF2 in register IRCON Neither of these flags is cleared by hardware when the service routine is vectored to In fact the service routine may have to determine whether it was TF2 or EXF2 that generated the interrupt and the bit will have to be cleared by software The A D converter interrupt is generated by IADC bit in register IRCON If an interrupt is generated in any case the converted result in ADDAT is valid on the first instruction of the interrupt service routine If continuous conversion is established IADC is set once during each conversion If an A D converter interrupt is generated flag IADC will have to be cleared by software The external interrupts 4 to 6 INT4 INT5 and INT6 are positive transition activated The flags that actually generate these interrupts are bits IEX4 IEX5 and IEX6 in register IRCON In addition these flags will be set if a compare event occurs at the corresponding output pin P1 3 AN3 INT6 CC3 P1 2 AN2 INT5 CC2 and P1 1 AN1 INT4 CC1 regardless of the compare mode established and the transition at the respective pin When an interrupt is generated the flag that generated it is cleared by the on chip hardware when the service routine is vectored to All of these interrupt request bits that generate interrupts can be set or cleared by software with the same result a
22. 1 If ET2 in IENO is set timer 2 interrupt enabled EXF2 1 will cause an interrupt EXF2 can be used as an additional external interrupt when the reload function is not used EXF2 must be cleared by software TF2 Timer 2 overflow flag Set by a timer 2 overflow and must be cleared by software If the timer 2 interrupt is enabled TF2 1 will cause an interrupt IEX6 External interrupt 6 edge flag Set by hardware when external interrupt edge was detected or when a compare event occured at P1 3 AN3 INT6 CC3 Cleared when interrupt is processed IEX5 External interrupt 5 edge flag Set by hardware when external interrupt edge was detected or when a compare event occured at P1 2 AN2 INT5 CC2 Cleared when interrupt is processed IEX4 External interrupt 4 edge flag Set by hardware when external interrupt edge was detected or when a compare event occured at P1 1 AN1 INT4 CC1 Cleared when interrupt is processed IEX3 External interrupt 3 edge flag Set by hardware when external interrupt edge was detected or when a compare event occured at P1 0 ANO INT3 CCO Cleared when interrupt is processed SWI This bit can be set by software to generate an interrupt This bit is cleared when the interrupt is processed The interrupt vector address is 004By IADC A D converter interrupt request flag Set by hardware at the end of an A D conversion Must be cleared by software Semiconductor Group 7 9 1997 08
23. 2 Using Two Datapointers Code for a C505 Initialization Routine MOV DPSEL 06H Initialize DPTR6 with source pointer MOV DPTR 1FFFH MOV DPSEL 07H Initialize DPTR7 with destination pointer MOV DPTR 2FA0H Table Look up Routine under Real Time Conditions Number of cycles PUSH DPSEL Save old source pointer 2 MOV DPSEL 06H Load source pointer 2 INC DPTR Increment and check for end of table execution time CJNE not relevant for this consideration MOVC A DPTR Fetch source data byte from ROM table 2 MOV DPSEL 07H Save source pointer and load destination pointer 2 MOVX DPTR A Transfer byte to destination address 2 POP DPSEL Save destination pointer and restore old datapointer 2 Total execution time machine cycles 12 The above example shows that utilization of the C505 s multiple datapointers can make external bus accesses two times as fast as with a standard 8051 or 8051 derivative Here four data variables in the internal RAM and two additional stack bytes were spared too This means for some applications where all eight datapointers are employed that a C505 program has up to 24 byte 16 variables and 8 stack bytes of the internal RAM free for other use Semiconductor Group 4 9 1997 08 01 SIEMENS External Bus Interface C505 C505C 4 7 ROM Protection for the C505 The C505 2R allows to protect the contents of the internal ROM against unauthorized read out The type of ROM protection protected
24. 20 pF can be used as single capacitance at any frequency together with a good quality crystal A ceramic resonator can be used in place of the crystal in cost critical applications If a ceramic resonator is used the two capacitors normally have different values depending on the oscillator frequency We recommend consulting the manufacturer of the ceramic resonator for value specifications of these capacitors Semiconductor Group 5 6 1997 08 01 IE System Reset SIEMENS C505 C505C N d To internal e timing circuitry C505 XTAL2 XTAL1 Tir C Co Crystal or ceramic resonator MCS03293 Figure 5 5 On Chip Oscillator Circuiry To drive the C505 with an external clock source the external clock signal has to be applied to XTAL1 as shown in figure 5 6 XTAL2 has to be left unconnected A pullup resistor is suggested to increase the noise margin but is optional if Vo of the driving gate corresponds to the V specification of XTAL1 C505 N C XTAL2 External Clock p XTAL1 Signal MCS03294 Figure 5 6 External Clock Source Semiconductor Group 5 7 1997 08 01 SIEMEN System Reset S C505 C505C 5 5 System Clock Output For peripheral devices requiring a system clock the C505 provides a clock output signal derived from the oscillator frequency as an alternate output function on pin P1 6 CLKOUT If bit CLK is set bit 6 of special function register ADCONO
25. 21 F709 UGML1 UUYy ID20 13 F70AW LGMLO UUY ID12 5 F70B4 LGML1 UUUU ID4 0 0 0 0 UO00p F70Cy UMLMO UUY ID28 21 F70Dy UMLM1 UUyY ID20 18 ID17 13 F70Ey LMLMO UUy ID12 5 F70Fu LMLM1 UUUU ID4 0 0 0 0 U000p F7n0y MCRO UUH MSGVAL TXIE RXIE INTPND F7niy MCR1 UUH RMTPND TXRQ MSGLST NEWDAT CPUUPD F7n24 UARO UUH ID28 21 F7n34 UAR1 UUg ID20 18 ID17 13 F7n44 LARO UUH ID12 5 F7n54 LAR1 UUUU ID4 0 0 0 0 U000p F n6j MCFG UUUU DLC DIR XTD JO 0 UUO0p 1 The notation n n 1 to F in the address definition defines the number of the related message object 2 X means that the value is undefined and the location is reserved U means that the value is unchanged by a reset operation U values are undefined as X after a power on reset operation Semiconductor Group 3 18 1997 08 01 SIEMEN Memory Organization S C505 C505C Table 3 4 Contents of the CAN Registers in numeric order of their addresses cont d C505C only Addr Register Content Bit7 Bit6 X Bit5 Bit4 Bit3 Bit2 Bit1 Bit 0 n 1 Fy after 1 Reset 2 F7n7y DBOn XXq 7 6 5 4 3 2 1 0 F7n84 DBin XXy_ 17 6 5 4 3 2 1 0 F7n94 DB2n XXy_ 7 6 5 4 3 2 1 0 F7nAy DB3n XX4 7 6 5 4 3 2 E 0 F7nBy DBan XXQ 7 6 5 4 iB 2 E 0 F7nCy DB5n XXq 7 6 5 4 3 2 1 0 F7nDj DB n XXy_ 7 6 5 4 3 2 1 0 F7nEy DB7n XXq 7 6 5 4 3 2 1 0
26. 6 25 CLP 1 25 CLP Clock cycle TCL 25 37 5 CLP DCmin CLP DCmax ns Note The 16 MHz values in the tables are given as an example for a typical duty cycle variation of the oscillator clock from 0 4 to 0 6 Semiconductor Group 10 8 1997 08 01 SIEMENS Device Specifications C505 C505C 10 5 AC Characteristics 20 MHz for C505 Voc 5 V 10 1596 Vss 0 V T 0 to 70 C for the SAB C505 T 40 to 85 C for the SAF C505 C for port 0 ALE and PSEN outputs 100 pF C for all other outputs 80 pF Program Memory Characteristics Parameter Symbol Limit Values Unit 20 MHz clock Variable Clock Duty Cycle 1 CLP 2 MHz to 0 5 to 0 5 20 MHz min max min max ALE pulse width f 35 CLP 15 ns Address setup to ALE AVLL 10 TCLumin 15 ns Address hold after ALE tLLAX 10 TCLumin 15 ns ALE low to valid instr in fiy 55 2 CLP 45 ns ALE to PSEN fup 1 0 Ee TCL min T 1 5 ZZ ns PSEN pulse width pi ph 60 CLP ns TCL qi yi 15 PSEN to valid instr in piiv 25 CLP ns TCLumin E 50 Input instruction hold after PSEN pxix 0 0 ns Input instruction float after PSEN tpyiz 20 TCL 4 5 NS Address valid after PSEN texray 20 TCLimin 5 ns Adaress to valid instr in taviy 65 2 CLP ns TCLumin 60 Address float to PSEN AZPL 5 5 ns
27. 8 o e amp E E s Q Receive 7 3 lt P o c 92 e wm Figure 6 29 Serial Interface Mode 2 and 3 Timing Diagram Semiconductor Group 6 59 1997 08 01 SIEMEN On Chip Peripheral Components 3 C505C Only 6 4 The On Chip CAN Controller The Controller Area Network CAN bus with its associated protocol allows communication between a number of stations which are connected to this bus with high efficiency Efficiency in this context means Transfer speed data rates of up to 1 Mbit sec can be achieved Data integrity the CAN protocol provides several means for error checking Host processor unloading the controller here handles most of the tasks autonomously Flexible and powerful message passing the extended CAN protocol is supported Note The CAN interface is a part of the C505C derivatives only The CAN interface which is integrated in the C505C is functionally fully compatible with the CAN module which is available in the 8 bit microcontroller C515C and in the 16 bit microcontroller C167CR The CAN module of the C167CR has been adapted with its internal bus interface clock generation logic register access control logic and interrupt function to the requirements of the 8 bit C500 microcontroller architecture Generally the CAN interface is made of two major blocks The CAN controller The internal bus interface The CAN controller is the functional heart which provides all resources that are required
28. AF AEQ ADy ACy AB AAG A94 ABy A8H EAL WDT ET2 ES ET1 EX1 ETO EXO IENO BF BE BD BC BB BA B9 B8y B8 EXEN2 SWDT EX6 EX5 EX4 EX3 ECAN EADC IEN1 Bit No 7 6 5 4 3 2 1 0 A94 OWDS WDTS IPO 5 IPO 4 IP0 3 IPO 2 IPO 1 IPO 0 IPO BS The shaded bits are not used for fail save control Bit Function WDT Watchdog timer refresh flag Set to initiate a refresh of the watchdog timer Must be set directly before SWDT is set to prevent an unintentional refresh of the watchdog timer SWDT Watchdog timer start flag Set to activate the Watchdog Timer When directly set after setting WDT a watchdog timer refresh is performed WDTS Watchdog timer status flag Set by hardware when a watchdog Timer reset occured Can be cleared and set by software Immediately after start the Watchdog Timer is initialized to the reload value programmed in WDTREL O WDTREL 6 After an external HW reset an oscillator watchdog power on reset or a watchdog timer reset register WDTREL is cleared to 00 4 The lower seven bits of WDTREL can be loaded by software at any time Semiconductor Group 8 3 1997 08 01 IE Fail Save Mechanisms ii bx C505 C505C 8 1 3 Starting the Watchdog Timer The Watchdog Timer can be started by software bit SWDT in SFR IEN1 but it cannot be stopped during active mode of the device If the software fai
29. Address C8 Reset Value 00X00000p MSB LSB Bit No CFy CEy CDy CCH CBy CA4 C94 C84 C84 T2PS ISFR T2R1 T2RO T2CM T2l1 T210 T2CON The shaded bits are not used for interrupt control Bit Function ISFR External interrupt 3 rising falling edge control flag If ISFR 0 the external interrupt 3 is activated by a falling edge at P1 0 ANO INT3 CCO If IBFR 1 the external interrupt 3 is activated by a rising edge at P1 0 ANO INT3 CCO This bit has no effect in the C505 The external interrupt 3 INT3 can be either positive or negative transition activated depending on bit I3FR in register T2CON The flag that actually generates this interrupt is bit IEX3 in register IRCON In addition this flag will be set if a compare event occurs at pin P1 0 ANO INT3 CCO regardless of the compare mode established and the transition at the respective pin The flag IEX3 is cleared by hardware when the service routine is vectored to Semiconductor Group 7 8 1997 08 01 SIEMENS Interrupt System C505 C505C Special Function Register IRCON Address C0 Reset Value 00H Bit No COL MSB LSB Ch Gau Cbs HCA Cary SEA Cig 2004 EXF2 TF2 IEX6 IEX5 IEX4 IEX3 SWI IADC IRCON Bit Function EXF2 Timer 2 external reload flag EXF2 is set when a reload is caused by a falling edge on pin T2EX while EXEN2
30. C505C 11 Index Block diagram 4k RR 6 62 Note Bold page numbers refer to the main definition Configuration examples 6 95 part of SFRs or SFR bits Idle mode 0005 6 94 A Initialization 6 88 Interface signals 6 97 A D converter 6 98 to 6 109 Interrupt handling 6 93 Analog input pin selection 6 109 Power dowirmoda ao a chen 6 94 Plock Diagram e D ie 6 99 Registers s edv todos 6 65 to 6 81 Clock selection 6 104 Address map gt ooun 6 66 Conversion time calculation 6 108 General registers 6 65 Conversion timing cce ve Bu 6 105 Message object address map 6 75 General operation 6 98 Message object handling 6 81 to 6 87 Registers IE 6 100 to 6 103 Message object registers 6 75 System clock relationship 6 106 Slow dowr mode ioo cc eus 6 94 A D converter characteristics 10 5 to 10 6 Synchronization sss 6 92 Absolute maximum ratings 10 1 a ction CEE 3 18 6 67 AC Ga tate TEIIILLLL LLLI 2 4 3 16 CCEN 3 13 3 16 6 29 AC characteristics TET 10 7 to 10 12 CCH1 3 13 3 16 BG Testing COHN HMM 3 13 3 16 Float waveforms 10 18 CCH3 3 13 3 16 Input output waveforms 10 18 ole LLL 3 13 3 16 a es au n EE teeta nahn athe akan 3 13 3 16 ADOLO ccrte Vw a ies 6 102 CCL
31. FET p1 is of p channel type It is activated for two oscillator periods S1P1 and S1P2 if a 0 to 1 transition is programmed to the port pin i e a 1 is programmed to the port latch which contained a 0 The extra pullup can drive a similar current as the pulldown FET n1 This provides a fast transition of the logic levels at the pin The pullup FET p2 is of p channel type It is always activated when a 1 is in the port latch thus providing the logic high output level This pullup FET sources a much lower current than p1 therefore the pin may also be tied to ground e g when used as input with logic low input level Semiconductor Group 6 9 1997 08 01 IE On Chip Peripheral Components SIEMENS C505 C505C The pullup FET p3 is of p channel type It is only activated if the voltage at the port pin is higher than approximately 1 0 to 1 5 V This provides an additional pullup current if a logic high level shall be output at the pin and the voltage is not forced lower than approximately 1 0 to 1 5 V However this transistor is turned off if the pin is driven to a logic low level e g when used as input In this configuration only the weak pullup FET p2 is active which sources the current 7 If in addition the pullup FET p3 is activated a higher current can be sourced 4 Thus an additional power consumption can be avoided if port pins are used as inputs with a low level applied However the driving capability is stronger if a
32. JB which is two machine cycles long possibly may not recognize the BSY 0 condition during the write result cycle in the continuous conversion mode A D conversion interrupt After the start of an A D conversion the A D converter interrupt is enabled The result of the A D conversion is read in the interrupt service routine If other C505 interrupts are enabled the interrupt latency must be regarded Therefore this software method is the slowest method to get the result of an A D conversion Semiconductor Group 6 107 1997 08 01 SIEMENS On Chip Peripheral Components C505 C505C Depending on the oscillator frequency of the C505 and the selected divider ratio of the conversion clock prescaler the total time of an A D conversion is calculated according figure 6 44 and table 6 8 Figure 6 46 shows the minimum A D conversion time in relation to the oscillator frequency fosc The minimum conversion time is 8 us and can be achieved at fosc of 10 MHz and with a prescalar ratio of 8 or whenever fApc 1 25 MHz Table 6 8 A D Conversion Time for Dedicated System Clock Rates fosc MHz Prescaler fApc MHz Sample Time Total Conversion Ratio PS ts us Time tApcc us 2 MHz 4 5 4 20 5 MHz 4 1 25 1 6 8 6 MHz 8 0 75 2 67 13 33 10 MHz 8 1 25 1 6 8 12 MHz 16 0 75 2 67 13 33 16 MHz 16 1 2 10 20 MHz 16 1 25 1 6 8 Note The prescaler ratios in table 6 8 are minimum values MCT0330
33. MSGVAL 1 XTD application specific CPUUPD 1 NEWDAT 1 write calculate message contents CPUUPD 0 want to send No update message Figure 6 35 MCD02741 Microcontroller Handling of Message Objects with Direction transmit Semiconductor Group 6 84 1997 08 01 IE On Chip Peripheral Components SIEMENS C505C Only Power Up all bits undefined TXIE application specific RXIE application specific INTPND 0 RMTPND 0 TXRQ 0 MSGLST 0 Identifier application specific NEWDAT 0 Direction receive DLC value of DLC in transmitter MSGVAL 1 XTD application specific Initialization Process Start NEWDAT 0 Process process message contents gt Y A Process End Restart Process MCD02742 Figure 6 36 Microcontroller Handling of Message Objects with Direction receive Semiconductor Group 6 85 1997 08 01 On Chip Peripheral Components SIEMENS C505C Only Power Up all bits undefined RXIE application specific INTPND 0 RMTPND 0 Initialization MSGLST 0 i Identifier application specific NEWDAT Direction feceive DLC value of DLC in transmitter MSGVAL 1 XTD application specific Process Start NEWDAT 0 Process process message contents Process End Restart Process MCD02743 Figure 6 37 Microcontroller Han
34. O0t5sxrm ziz gt F sxrag c o oO dZz0o0o qocc tor a Z lt 1 0 TA Se a o MCP03285 Figure 1 3 Pin Configuration top view Semiconductor Group 1 4 1997 08 01 SIEMEN Introduction S C505 C505C 1 2 Pin Definitions and Functions This section describes all external signals of the C505 with its function Table 1 1 Pin Definitions and Functions Symbol Pin Number 1 O Function P1 0 P1 7 40 44 1 3 VO Port1 is an 8 bit quasi bidirectional port with internal pull up arrangement Port 1 pins can be used for digital input output or as analog inputs of the A D converter Port 1 pins that have 1 s written to them are pulled high by internal pull up transistors and in that state can be used as inputs As inputs port 1 pins being externally pulled low will source current Ji in the DC characteristics because of the internal pullup transistors Port 1 pins are assigned to be used as analog inputs via the register P1ANA As secondary digital functions port 1 contains the interrupt timer clock capture and compare pins The output latch corresponding to a secondary function must be programmed to a one 1 for that function to operate except for compare functions The secondary functions are assigned to the pins of port 1 as follows 40 P1 0 ANO INT3 CCO Analog input channel 0 Interrupt 3 input capture compare channel 0 I O 41 P1 1 AN1 INT4 CC1 Analog input
35. Overlapping External Data and Program Memory Spaces In some applications it is desirable to execute a program from the same physical memory that is used for storing data In the C505 the external program and data memory spaces can be combined by the logical AND of PSEN and RD A positive result from this AND operation produces a low active read strobe that can be used for the combined physical memory Since the PSEN cycle is faster than the RD cycle the external memory needs to be fast enough to adapt to the PSEN cycle Semiconductor Group 4 3 1997 08 01 IEMEN External Bus Interface S S C505 C505C 4 4 ALE Address Latch Enable The C505 allows to switch off the ALE output signal If the internal ROM is used EA 1 and PC lt 3FFFp and ALE is switched off by EALE 0 then ALE will only go active during external data memory accesses MOVX instructions If EA 0 the ALE generation is always enabled and the bit EALE has no effect After a hardware reset the ALE generation is enabled Special Function Register SYSCON Address B1 4 Reset Value XX100X01p Bit No MSB LSB 7 6 5 4 3 2 1 0 BiH EALE RMAP CMOD XMAP1 XMAPO SYSCON j The shaded bits are not described in this section Bit Function EALE Enable ALE output EALE 2 0 ALE generation is disabled disables ALE signal generation during internal code memory accesses EA 1 With EA 1 ALE is automatically generated at MO
36. Parameter Symbol Limit Values Unit Variable Clock Freq 2 MHz to 20 MHz min max Oscillator period CLP 50 500 ns High time TCL 25 CLP TCL ns Low time TCL 25 CLP TCL ns Rise time tR 10 ns Fall time te 10 ns Note The 20 MHz values in the tables are given as an example for a typical duty cycle of the oscillator clock of 50 96 Semiconductor Group 10 11 1997 08 01 Device Specifications SIEMENS C505 C505C t LHLL ALE PSEN Port 0 Port 2 A8 A15 A8 A15 MCT00096 Program Memory Read Cycle Semiconductor Group 10 12 1997 08 01 Device Specifications SIEMENS C505 C505C UIT ALE PSEN t s LLDV j me lw om TT lau 4 nupz Port 0 tavwe aa tavov va Port 2 P2 0 P2 7 or A8 A15 from DPH A8 A15 from PCH MCT00097 Data Memory Read Cycle Semiconductor Group 10 13 1997 08 01 SIEMENS Device Specifications C505 C505C ALE Port 0 Port 2 uw wg yw cs z UIT PSEN P2 0 P2 7 or A8 A15 from DPH Instr IN A8 A15 from PCH MCT00098 Data Memory Write Cycle TCL y tR te XTAL1 Bet 0 2 Voc 0 1 TCL MCT03310 External Clock Drive on XTAL1 Semiconductor Group 10 14 1997 08 01 SIEMENS Device Specifications
37. S8 S4 and S5 of every machine cycle and high during S6 S1 and S2 At S6P2 of every machine cycle in which SEND is active the contents of the transmit shift register are shifted to the right one position As data bits shift out to the right zeroes come in from the left When the MSB of the data byte is at the output position of the shift register then the 1 that was initially loaded into the 9th position is just to the left of the MSB and all positions to the left of that contain zeroes This condition flags the TX control block to do one last shift and then deactivate SEND and set TI Both of these actions occur at S1P1 of the 10th machine cycle after Write to SBUF Reception is initiated by the condition REN 1 and RI 0 At S6P2 of the next machine cycle the RX control unit writes the bits 1111 1110 to the receive shift register and in the next clock phase activates RECEIVE RECEIVE enables SHIFT CLOCK to the alternate output function line of P3 1 SHIFT CLOCK makes transitions at S3P1 and S6P1 of every machine cycle At S6P2 of every machine cycle in which RECEIVE is active the contents of the receive shift register are shifted to the left one position The value that comes in from the right is the value that was sampled at the P3 0 pin at S5P2 of the same machine cycle As data bit comes in from the right 1s shift out to the left When the 0 that was initially loaded into the rightmost position arrives at the leftmost position in
38. Signal PSEN functions as a read strobe 4 1 3 External Program Memory Access The external program memory is accessed under two conditions whenever signal E is active low or whenever the program counter PC content is greater than 3FFFy When the CPU is executing out of external program memory all 8 bits of port 2 are dedicated to an output function and must not be used for general purpose l O The content of the port 2 SFR however is not affected During external program memory fetches port 2 lines output the high byte of the PC and during accesses to external data memory they output either DPH or the port 2 SFR depending on whether the external data memory access is a MOVX DPTR or a MOVX Ri 4 2 PSEN Program Store Enable The read strobe for external program memory fetches is PSEN It is not activated for internal program memory fetches When the CPU is accessing external program memory PSEN is activated twice every instruction cycle except during a MOVX instruction no matter whether or not the byte fetched is actually needed for the current instruction When PSEN is activated its timing is not the same as for RD A complete RD cycle including activation and deactivation of ALE and RD takes 6 oscillator periods A complete PSEN cycle including activation and deactivation of ALE and PSEN takes 3 oscillator periods The execution sequence for these two types of read cycles is shown in figure 4 1 a and b 4 3
39. T 40 to 85 C T 40 to 110 C T 40 to 125 C 4 V lt Varer Voc 0 1 V Vss 0 1 V lt Vienn Vss 0 2 V for the SAB C505 for the SAF C505 for the SAH C505 for the SAK C505 Parameter Symbol Limit Values Unit Test Condition min max Analog input voltage Von Visus pne V b 0 2 0 2 Sample time ts 64 X ftn ns Prescaler 32 32 X n Prescaler 16 16 X tn Prescaler 8 8 X tiny Prescaler 4 2 Conversion cycle time tapec 320 X tin Ns Prescaler 32 160 x fin Prescaler 16 80 X tn Prescaler 8 40 X tin Prescaler 4 9 Total unadjusted error Tue t2 LSB Vss 0 5V lt Vain Voc 0 5V Internal resistance of Rire i faoc 500 KO fapc in ns 99 reference voltage source 1 Internal resistance of Rise ts 500 kQ fsin ns 99 analog source 1 ADC input capacitance Can 50 pF 6 Notes see next page Clock calculation table ClockPrescaler ADCL1 0 tApc ts tADCC Ratio 32 1 1 32 X tin 64 x tin 320 x tin 16 1 0 16 x tin 32 X tin 160 x tin 8 0 1 8 X tin 16 x tin 80 x tin 4 0 0 4xtin 8 X tin 40 x tin Further timing conditions tapc min 800 ns tin 1 fosc tci P Semiconductor Group 10 4 1997 08 01 SIEMENS Device Specifications C505 C505C Notes 1 Vain may exeed Vacnp or VAngr up to the absolute maximum ratings However the conversion result in these cases will be 00y or FFy respect
40. TX RX Shift Register and the Intelligent Memory such that the processes of reception arbitration transmission and error signalling are performed according to the CAN protocol Note that the automatic retransmission of messages which have been corrupted by noise or other external error conditions on the bus line is handled by the BSP Cyclic Redundancy Check Register CRC This register generates the Cyclic Redundancy Check code to be transmitted after the data bytes and checks the CRC code of incoming messages This is done by dividing the data stream by the code generator polynomial Error Management Logic EML The Error Management Logic is responsible for the fault confinement of the CAN device Its counters the Receive Error Counter and the Transmit Error Counter are incremented and decremented by commands from the Bit Stream Processor According to the values of the error counters the CAN controller is set into the states error active error passive and busoff The CAN controller is error active if both error counters are below the error passive limit of 128 It is error passive if at least one of the error counters equals or exceeds 128 It goes busoff if the Transmit Error Counter equals or exceeds the busoff limit of 256 The device remains in this state until the busoff recovery sequence is finished Additionally there is the bit EWRN in the Status Register which is set if at least one of the error counters equals or exce
41. Thus a minimum of three complete machine cycles will elapse between activation and external interrupt request and the beginning of execution of the first instruction of the service routine A longer response time would be obtained if the request was blocked by one of the three previously listed conditions If an interrupt of equal or higer priority is already in progress the additional wait time obviously depends on the nature of the other interrupt s service routine If the instruction in progress is not in its final cycle the additional wait time cannot be more than 3 cycles since the longest instructions MUL and DIV are only 4 cycles long and if the instruction in progress is RETI or a write access to registers IENO IEN1 or IPO IP1 the additional wait time cannot be more than 5 cycles a maximum of one more cycle to complete the instruction in progress plus 4 cycles to complete the next instruction if the instruction is MUL or DIV Thus a single interrupt system the response time is always more than 3 cycles and less than 9 cycles Semiconductor Group 7 17 1997 08 01 SIEMENS Fail Save Mechanisms C505 C505C 8 Fail Save Mechanisms The C505 offers enhanced fail save mechanisms which allow an automatic recovery from software upset or hardware failure a programmable watchdog timer WDT with variable time out period from 192 us up to approx 412 5 ms at 16 MHz an oscillator watchdog OWD which monitors the on c
42. Voc all other pins are disconnected Icc active mode is measured with XTAL1 driven with tg t 5 ns Vi Vss 0 5 V Vy Vec 0 5 V XTAL2 N C EA Port 0 Vec RESET Vas all other pins are disconnected cc would be slightly higher if the crystal oscillator is used approx 1 mA oy Icc idle mode is measured with all output pins disconnected and with all peripherals disabled XTAL1 driven with tp tc 5 ns Vi Vss 0 5 V Vj Voc 0 5 V XTAL2 N C RESET EA Vas PortO Vcc all other pins are disconnected 6 Icc active mode with slow down mode is measured TBD 7 Icc idle mode with slow down mode is measured TBD 8 Overload conditions occur if the standard operating conditions are exceeded ie the voltage on any pin exceeds the specified range i e Voy gt Vec 0 5 V or Voy lt Vss 0 5 V The supply voltage Vcc and Vss must remain within the specified limits The absolute sum of input currents on all port pins may not exceed 50 mA 9 Not 100 tested guaranteed by design characterization 10 The typical cc values are periodically measured at 7 25 C but not 100 tested 11 The maximum ec values are measured under worst case conditions 74 0 C or 40 C and Voc 5 5 V Semiconductor Group 10 3 1997 08 01 SIEMENS Device Specifications C505 C505C 10 3 A D Converter Characteristics Voc 5 V 10 15926 Vas 20V T 0 to 70 C
43. a clock signal with 1 6 of the oscillator frequency is gated to pin P1 6 CLKOUT To use this function the port pin must be programmed to a one 1 which is also the default after reset Special Function Register ADCONO Address D8 Reset Value 00X000000p MSB LSB Bit No DFH DEH DDH DCH DBH DAH D9H D8H D8y BD CLK EZ BSY ADM MX2 MX1 MXO ADCONO The shaded bits are not used for clock output control Bit Function CLK Clockout enable bit When set pin P1 6 CLKOUT outputs the system clock which is 1 6 of the oscillator frequency Reserved bits for future use Read by CPU returns undefined values The system clock is high during S3P1 and S3P2 of every machine cycle and low during all other states Thus the duty cycle of the clock signal is 1 6 Associated with a MOVX instruction the system clock coincides with the last state S3 in which a RD or WR signal is active A timing diagram of the system clock output is shown in figure 5 7 Note During slow down operation the frequency of the CLKOUT signal is divided by 32 Semiconductor Group 5 8 1997 08 01 SIEMEN System Reset S C505 C505C se si se ss sass se st s2 o s 85 so st s2 ALE RD WR CLKOUT Do x j MCT01858 Figure 5 7 Timing Diagram System Clock Output Semiconductor Group 5 9 1997 08 01 IE On Chip Peripheral Components SIEMENS C505 C
44. actual data has been transferred 3 When the microcontroller requests the transmission of a receive object a remote frame will be sent instead of a data frame to request a remote node to send the corresponding data frame This bit will be cleared by the CAN controller along with bit RMTPND when the message has been successfully transmitted if bit NEWDAT has not been set If there are several valid message objects with pending transmission request the message with the lowest message number is transmitted first Semiconductor Group 6 77 1997 08 01 SIEMEN On Chip Peripheral Components 3 C505C Only Arbitration Registers The arbitration registers are used for acceptance filtering of incoming messages and to define the identifier of outgoing messages A received message is stored into the valid message object with a matching identifier and DIR 0 data frame or DIRZ 1 remote frame Extended frames can be stored only in message objects with XTD 1 standard frames only in message objects with XTD 0 For matching the corresponding global mask has to be considered in case of message object 15 also the mask of last message If a received message data frame or remote frame matches with more than one valid message object it is stored into that with the lowest message number When the CAN controller stores a data frame not only the data bytes but the whole identifier and the data length code are stored into the corresponding
45. addresses Addr Register Content Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit 0 after Reset 801 2 PO FFH v 6 5 4 3 2 1 0 814 ISP 074 7 6 5 4 3i 2 T 0 82H DPL 00H 7 6 5 4 3 2 1 0 834 DPH 00 7 6 E 4 3 2 1 0 864 WDTREL 00 4 WDT 6 5 4 3 2 1 0 PSEL 874 IPCON 00y SMOD PDS IDLS SD GF1 GFO PDE IDLE 884 TCON 00H TF1 TR1 TFO TRO IE1 IT1 IEO ITO 8849 PCON1 0XXO EWPD WS XXXXp 894 TMOD 00H GATE C T M1 MO GATE C T M1 MO 8Ay TLO 0014 7 6 5 4 3 2 E 0 8By TL1 0014 7 6 5 4 3 2 E 0 8C THO 00H 7 6 5 4 3 2 1 0 8Dy_ TH1 001 7 6 5 4 3 2 1 0 901 P1 FFy T2 CLK T2EX 4 26 INT5 INT4 0 OUT 904 P1ANA FFy EAN7 EAN6 EAN5 EAN4 EAN3 EAN2 EAN1 EANO 914 XPAGE 00j 7 6 b 4 B 2 1 0 924 DPSEL XXXX 2 A 0 X000p 984 ISCON 00y SMO SM1 SM2 REN TB8 RB8 ITI RI 994 SBUF XX4 7 6 5 4 3 2 1 0 AOy P2 FFy 7 6 5 4 3 2 1 0 A84 IENO 00H EA WDT ET2 ES ET1 EX1 ETO EXO A94 IPO 001 OWDS WDTS 5 4 3 2 E 0 AAy SRELL D94 7 6 5 4 3 2 ji 0 1 X means that the value is undefined and the location is reserved 2 Bit addressable special function registers 3 SFR is located in the mapped SFR area For accessing this SFR bit RMAP in SFR SYSCON must be set Semiconductor Group 1997 08 01 SIEMENS Memory Organization C505 C
46. as follows C505C only P4 0 TXDC Transmitter output of CAN controller P4 1 RXDC Receiver input of CAN controller XTAL2 14 O XTAL2 Output of the inverting oscillator amplifier XTAL1 15 XTAL1 Input to the inverting oscillator amplifier and input to the internal clock generator circuits To drive the device from an external clock source XTAL1 should be driven while XTAL2 is left unconnected To operate above a frequency of 16 MHz a duty cycle of 50 should be maintained Minimum and maximum high and low times as well as rise fall times specified in the AC characteristics must be observed Input O Output Semiconductor Group 1 7 1997 08 01 SIEMENS Introduction C505 C505C Table 1 1 Pin Definitions and Functions Symbol Pin Number I O Function P2 0 P2 7 18 25 I O Port 2 is a an 8 bit quasi bidirectional I O port with internal pullup resistors Port 2 pins that have 1 s written to them are pulled high by the internal pullup resistors and in that state can be used as inputs As inputs port 2 pins being externally pulled low will source current Z in the DC characteristics because of the internal pullup resistors Port 2 emits the high order address byte during fetches from external program memory and during accesses to external data memory that use 16 bit addresses MOVX DPTR In this application it uses strong internal pullup transistors when issuing 1s During accesses
47. before the CAN controller could transmit the remote frame Semiconductor Group 6 96 1997 08 01 SIEMEN On Chip Peripheral Components 3 C505C Only 6 4 10 The CAN Application Interface The on chip CAN controller of the C505C does not incorporate the physical layer that connects to the CAN bus This must be provided externally The module s CAN controller is connected to this physical layer ie the CAN bus via two signals CAN Signal Function P4 1 RXDC Receive data from the physical layer of the CAN bus P4 0 TXDC Transmit data to the physical layer of the CAN bus A logic low level 0 is interpreted as the dominant CAN bus level a logic high level 1 is interpreted as the recessive CAN bus level P4 0 TXDC CAN Interface C505C CAN Bus P4 1 RXDC Physical Layer S MCS03297 Figure 6 41 Connection to the CAN Bus Semiconductor Group 6 97 1997 08 01 IE On Chip Peripheral Components SIEMENS C505 C505C 6 5 A D Converter The C505 includes a high performance high speed 8 bit A D converter with 8 analog input channels It operates with a successive approximation technique and provides the following features 8 multiplexed input channels port 1 which can also be used as digital outputs inputs 8 bit resolution Internal start of conversion trigger Interrupt request generation after each conversion Single or continuous conversion mode The external
48. channel 1 Interrupt 4 input capture compare channel 1 I O 42 P1 2 AN2 INT5 CC2 Analog input channel 2 Interrupt 5 input capture compare channel 2 I O 43 P1 3 AN3 INT6 CC3 Analog input channel 3 Interrupt 6 input capture compare channel 4 I O 44 P1 4 ANA Analog input channel 4 1 P1 5 AN5 T2EX Analog input channel 5 Timer 2 external reload trigger input 2 P1 6 AN6 CLKOUT Analog input channel 6 System clock output 3 P1 7 AN7 T2 Analog input channel 7 Counter 2 input Port 1 is used for the low order address byte during program verification of the C505 2R Input O Output Semiconductor Group 1 5 1997 08 01 SIEMENS Introduction C505 C505C Table 1 1 Pin Definitions and Functions Symbol Pin Number 1 O Function RESET 4 RESET A high level on this pin for two machine cycles while the oscillator is running resets the device An internal diffused resistor to Vas permits power on reset using only an external capacitor to Voc P3 0 P3 7 5 7 13 O Port3 is an 8 bit quasi bidirectional port with internal pull up arrangement Port 3 pins that have 1 s written to them are pulled high by the internal pull up transistors and in that state can be used as inputs As inputs port 3 pins being externally pulled low will source current Z in the DC characteristics because of the internal pullup transistors The output latch corresponding to a secondary function
49. cycle and is repeated every cycle until RESET goes low again During reset pins ALE and PSEN are configured as inputs and should not be stimulated externally An external stimulation at these lines during reset activates several test modes which are reserved for test purposes This in turn may cause unpredictable output operations at several port pins At the reset pin a pulldown resistor is internally connected to Vss to allow a power up reset with an external capacitor only An automatic power up reset can be obtained when Vec is applied by connecting the reset pin to Voc via a capacitor After Vec has been turned on the capacitor must hold the voltage level at the reset pin for a specific time to effect a complete reset Semiconductor Group 5 1 1997 08 01 SIEMEN System Reset S C505 C505C The time required for a reset operation is the oscillator start up time plus 2 machine cycles which under normal conditions must be at least 10 20 ms for a crystal oscillator This requirement is typically met using a capacitor of 4 7 to 10 uF The same considerations apply if the reset signal is generated externally figure 5 1 b In each case it must be assured that the oscillator has started up properly and that at least two machine cycles have passed before the reset signal goes inactive C505 x RESET MCS03291 Figure 5 1 Reset Circuitries A correct reset leaves the processor in a defined state The program e
50. d E d EE MR 3 15 7 7 E XU seco dura holier athe Pr bea oda 3 15 7 5 Semiconductor Group 11 2 1997 08 01 SIEMENS index C505 C505C IET dose Scc Sek een eS 3 15 7 7 WORT 4 icin eho ada 3 14 3 18 6 76 IENO 3 12 3 13 3 15 6 28 7 5 8 3 Memory organization 3 1 IEN1 3 12 3 13 3 16 6 28 6 103 7 6 8 3 Datamemory 000000es 3 2 IEX nice dodo went ee 3 16 7 9 General purpose registers 3 2 EXT sibs ae ttem eus 3 16 7 9 Memory map sees 3 1 IEXS iter e ese es 3 16 7 9 Program memory 3 2 IE XD ur aci CI s m eee es 3 16 7 9 WMSGES 5 5 2 ES RC caet 3 18 6 77 INIT iso xe o et Rr ete x 3 18 6 67 MSGVAL esas eR RAV Rd 3 18 6 76 IET Genie dosi dbi od eit diae y dba 3 16 MXQ eri aes Darse 3 16 3 17 6 101 IN ED acsi qiiis ere qo VR eive 3 16 IL S a apenas 3 16 3 17 6 101 IE ados S op ea e wisi debe Beck te 3 15 MX2 oia e ebtabe vet 3 16 3 17 6 101 INT Sige ated Rte Se bd R3 ER A Pot 3 15 Interrupt system 7 1 to 7 17 NEWDAT 6c LoL ERR 3 18 6 77 Interrupts Block diagram LECTUS dana Oscillator operation 5 6 to 5 7 Enable TESI Eo y ora tts TOOTO External clock source 5 7 car STUDIE Me tn usan s On chip oscillator circuitry 5 7 Handling procedure Pudor D o Recommended oscillator circuit 5 6 Priority FEgISIGTS 3 epa e red upset Tte Oscillator watchdog 8 6 to 8 8 Priority within level structure
51. external counter input P3 6 WR B External data memory write strobe P3 7 RD B External data memory read strobe P4 0 TXDC B CAN controller transmit output C505C only P4 1 RXDC B CAN controller receive input C505C only Prior to the description of the port type specific port configurations the general port structure is described in the next section Semiconductor Group 1997 08 01 SIEMENS On Chip Peripheral Components C505 C505C 6 1 2 Standard I O Port Circuitry Figure 6 1 shows a functional diagram of a typical bit latch and I O buffer which is the core of each of the five I O ports The bit latch one bit in the port s SFR is represented as a type D flip flop which will clock in a value from the internal bus in response to a write to latch signal from the CPU The Q output of the flip flop is placed on the internal bus in response to a read latch signal from the CPU The level of the port pin itself is placed on the internal bus in response to a read pin signal from the CPU Some instructions that read from a port i e from the corresponding port SFR PO to P4 activate the read latch signal while others activate the read pin signal Read Latch Int Bus d Port Write vet Pin to Circuit Latch MCS01822 Read Pin Figure 6 1 Basic Structure of a Port Circuitry Semiconductor Group 6 3 1997 08 01 SIEMENS On Chip Peripheral Components C505 C505C The output driv
52. external interrupt 1 is selected If IT1 2 1 falling edge triggered external interrupt 1 is selected IEO External interrupt O request flag Set by hardware when external interrupt 0 edge is detected Cleared by hardware when processor vectors to interrupt routine ITO External interrupt O level edge trigger control flag If ITO 0 low level triggered external interrupt 0 is selected If ITO 1 falling edge triggered external interrupt 0 is selected The external interrupts 0 and 1 INTO and INT1 can each be either level activated or negative transition activated depending on bits ITO and IT1 in register TCON The flags that actually generate these interrupts are bits IEO and IE1 in TCON When an external interrupt is generated the flag that generated this interrupt is cleared by the hardware when the service routine is vectored to but only if the interrupt was transition activated If the interrupt was level activated then the requesting external source directly controls the request flag rather than the on chip hardware The timer 0 and timer 1 interrupts are generated by TFO and TF1 in register TCON which are set by a rollover in their respective timer counter registers When a timer interrupt is generated the flag that generated it is cleared by the on chip hardware when the service routine is vectored to Semiconductor Group 7 7 1997 08 01 IE Interrupt System SIEMENS C505 C505C Special Function Register T2CON
53. flag is cleared a capture occurs in response to a negative transition If the edge flag is set a capture occurs in response to a positive transition at pin P1 0 INT3 CCO In both cases the appropriate port 1 pin is used as input and the port latch must be programmed to contain a one 1 The external input is sampled in every machine cycle When the sampled input shows a low high level in one cycle and a high low in the next cycle a transition is recognized The timer 2 contents is latched to the appropriate capture register in the cycle following the one in which the transition was identified In mode 0 a transition at the external capture inputs of registers CC1 to CC3 will also set the corresponding external interrupt request flags IEX3 to IEX6 If the interrupts are enabled an external capture signal will cause the CPU to vector to the appropriate interrupt service routine In mode 1 a capture occurs in response to a write instruction to the low order byte of a capture register The write to register signal e g write to CRCL is used to initiate a capture The value written to the dedicated capture register is irrelevant for this function The timer 2 contents will be latched into the appropriate capture register in the cycle following the write instruction In this mode no interrupt request will be generated Figure 6 21 illustrates the operation of the CRC register while Figure 6 21a shows the operation of the compare capture re
54. has the wrong format O 1 1 Ack Error The message this CAN controller transmitted was not acknowledged by another node 1 0 O Bit1 Error During the transmission of a message with the exception of the arbitration field the device wanted to send a recessive level 1 but the monitored bus value was dominant 1 0 1 BitO Error During the transmission of a message or acknowledge bit active error flag or overload flag the device wanted to send a dominant level 0 but the monitored bus value was recessive During busoff recovery this status is set each time a sequence of 11 recessive bits has been monitored This enables the microcontroller to monitor the proceeding of the busoff recovery sequence indicating the bus is not stuck at dominant or continously disturbed 1 1 0 CRC Error The CRC check sum was incorrect in the message received Note Reading the SR when an interrupt is pending resets the pending interrupt request please see section 6 4 6 for further details about CAN interrupt handling Semiconductor Group 6 69 1997 08 01 SIEMENS On Chip Peripheral Components C505C Only CAN Interrupt Register IR Address F702 4 Reset Value XXy Bit No MSB LSB 7 6 5 4 3 2 1 0 F702 INTID IR Bit Function INTID Interrupt identifier This number indicates the cause of the interrupt When no interrupt is pending the value will be 00 See also
55. he e Eee e oe tie wit ex e o eds 6 98 6 5 1 A D GConverter Operation x estre eet age ts aul er eG nei pre Ua t ec e EA NR 6 98 6 5 2 A D Converter Registers x xemdsemtESAGA X3 UBER EAE AG CR we ERU RON as 6 100 6 5 3 A D Converter Clock Selection sellers 6 104 6 5 4 A D Converter Timing nassa aleve QN VERO EN UR RR SE es oes 6 105 6 5 5 A D Converter Analog Input Selection nnana annae 6 109 7 Interrupt System ozone ERE a a a a 7 1 7 1 Interrupt Registers eaire on beu det qas Sap qe do a A E bre 7 5 7 1 1 Interrupt Enable Registers 2 s ooa tales dee aie oS oe Rae wee eee 7 5 7 1 2 Interrupt Request Control Flags soci weenie vate RE ye Deke ede aes 7 7 7 1 3 Interrupt Priority Registers c ness ved eS ese ot ae ees 2S 86 Fes Meee IDEE 7 12 7 2 Interrupt Priority Level Structure 00 000 eee 7 13 7 3 How Interrupts are Handled ons iad cds heed RR BRI DA Ree Rat YES 7 14 7 4 External Interrupts a os os et ee te te Ds a estos often tk e a ae 7 16 7 5 Interrupt Response Time coke kb RE RERE DR RE wa ee ee oe eed 7 17 8 Fail Save Mechanisms 2 9 6evlt4e ME ENT LEX hee Gee eee EE MEET ES 8 1 8 1 Programmable Watchdog Timer 25 2 I Ga etes bd REA edhe keds 8 1 8 1 1 pul Clock Selection ure cig a rato EE ea Oe eee REF ERAS RENTES eee eM 8 2 8 1 2 Watchdog Timer Control Status Flags 0 0 0 cee eee eee 8 3 8 1 3 Starting ihe Watchdog Timers 2m eur ek whoa bd eed ed coh phate beens 8 4 8 1 4
56. idle mode is obtained by byte handling instructions as shown in the following example ORL PCON 00000001B Set bit IDLE bit IDLS must not be set ORL PCON 00100000B Set bit IDLS bit IDLE must not be set The instruction that sets bit IDLS is the last instruction executed before going into idle mode There are two ways to terminate the idle mode The idle mode can be terminated by activating any enabled interrupt The CPU operation is resumed the interrupt will be serviced and the next instruction to be executed after the RETI instruction will be the one following the instruction that had set the bit IDLS The other way to terminate the idle mode is a hardware reset Since the oscillator is still running the hardware reset must be held active only for two machine cycles for a complete reset Semiconductor Group 9 4 1997 08 01 SIEMENS Power Saving Modes C505 C505C 9 3 Slow Down Mode Operation In some applications where power consumption and dissipation are critical the controller might run for a certain time at reduced speed e g if the controller is waiting for an input signal Since in CMOS devices there is an almost linear dependence of the operating frequency and the power supply current a reduction of the operating frequency results in reduced power consumption In the slow down mode all signal frequencies that are derived from the oscillator clock are divided by 32 The slow down mode is activated by s
57. in this port with the above mentioned configuration might be changed if the value read from the pin were written back to th latch However reading the latch rather than the pin will return the correct value of 1 Semiconductor Group 6 14 1997 08 01 SIEMENS On Chip Peripheral Components C505 C505C 6 2 Timers Counters The C505 contains three 16 bit timers counters timer 0 1 and 2 which are useful in many applications for timing and counting In timer function the timer register is incremented every machine cycle Thus one can think of it as counting machine cycles Since a machine cycle consists of 6 oscillator periods the counter rate is 1 6 of the oscillator frequency In counter function the timer register is incremented in response to a 1 to 0 transition falling edge at its corresponding external input pin TO T1 or T2 alternate functions of P3 4 P3 5 and P1 7 resp In this function the external input is sampled during S5P2 of every machine cycle When the samples show a high in one cycle and a low in the next cycle the count is incremented The new count value appears in the register during S3P1 of the cycle following the one in which the transition was detected Since it takes two machine cycles 12 oscillator periods to recognize a 1 to 0 transition the maximum count rate is 1 12 of the oscillator frequency There are no restrictions on the duty cycle of the external input signal but to ensure that a given l
58. instruction sequence shown above ORL SYSCON 00010000B set RMAP ORL PCON1 80H enable wake up from power down via P3 2 INTO ANL SYSCON 11101111B reset RMAP for future SFR accesses Setting EWPD automatically disables all interrupts still maintaining all actual values of the interrupt enable bits In the above sequence the value of register PCON1 should be modified for choosing a wake up via the P4 1 RXDC bit PCON1 4 should be set Note Before entering the power down mode an A D conversion in progress must be stopped Semiconductor Group 9 6 1997 08 01 IE Power Saving Modes 2 ii ex C505 C505C 9 4 2 Exit from Software Power Down Mode If power down mode is exit via a hardware reset the microcontroller with its SFRs is put into the hardware reset state and the content of RAM and XRAM are not changed The reset signal that terminates the power down mode also restarts the RC oscillator and the on chip oscillatror The reset operation should not be activated before Vcc is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize similar to power on reset Figure 9 1 shows the procedure which must is executed when power down mode is left via the P3 2 INTO or the P4 1 RXDC wake up capability Execution of interrupt Power Down Latch Watchdog Circuit edel Mode Phase Oscillator Start Up Phase 1 2 4 P3 2 INTO 3 or 7 P4 1 R
59. internal clock signals are not user accessible the XTAL1 oscillator signals and the ALE address latch enable signal are shown for external reference ALE is normally activated twice during each machine cycle once during S1P2 and S2P1 and again during S4P2 and S5P1 Execution of a one cycle instruction begins at S1P2 when the op code is latched into the instruction register If it is a two byte instruction the second reading takes place during S4 of the same machine cycle If it is a one byte instruction there is still a fetch at S4 but the byte read which would be the next op code is ignored discarded fetch and the program counter is not incremented In any case execution is completed at the end of S6P2 Figures 2 2 a and b show the timing of a 1 byte 1 cycle instruction and for a 2 byte 1 cycle instruction Most C505 instructions are executed in one cycle MUL multiply and DIV divide are the only instructions that take more than two cycles to complete they take four cycles Normally two code bytes are fetched from the program memory during every machine cycle The only exception to this is when a MOVX instruction is executed MOVX is a one byte 2 cycle instruction that accesses external data memory During a MOVX the two fetches in the second cycle are skipped while the external data memory is being addressed and strobed Figure 2 2 c and d show the timing for a normal 1 byte 2 cycle instruction and for a MOVX instructi
60. logic high level is output The described activating and deactivating of the four different transistors translates into four states the pins can be input low state IL p2 active only input high state IH steady output high state SOH p2 and p3 active forced output high state FOH p1 p2 and p3 active output low state OL n1 active If a pin is used as input and a low level is applied it will be in IL state if a high level is applied it will switch to IH state If the latch is loaded with O the pin will be in OL state If the latch holds a 0 and is loaded with 1 the pin will enter FOH state for two cycles and then switch to SOH state If the latch holds a 1 and is reloaded with a 1 no state change will occur At the beginning of power on reset the pins will be in IL state latch is set to 1 voltage level on pin is below of the trip point of p3 Depending on the voltage level and load applied to the pin it will remain in this state or will switch to IH SOH state If itis used as output the weak pull up p2 will pull the voltage level at the pin above p3 s trip point after some time and p3 will turn on and provide a strong 1 Note however that if the load exceeds the drive capability of p2 l1 the pin might remain in the IL state and provide a week 1 until the first O to 1 transition on the latch occurs Until this the output level might stay below the trip point of the external circuitr
61. mV change from load voltage occurs and begins to float when a 100 mV change from the loaded Vow Vo level occurs Iolo 20 mA AC Testing Float Waveforms Crystal Oscillator Mode Driving from External Source C 01 XTAL2 NG XTAL2 2 20 MHz 7T External Oscillator Signal C XTAL1 XTAL1 Crystal Mode C 20 pF 10 pF incl stray capacitance MCS03311 Recommended Oscillator Circuits for Crystal Oscillator Semiconductor Group 10 17 1997 08 01 SIEMENS Device Specifications C505 C505C 10 7 Package Information Plastic Package P MQFP 44 2 SMD Plastic Metric Quad Flat Pack Z 4 2 53 Boy Qu 8 H FF x o Tal Pi D B Arm 7 nen nt LS 08 I i t i i 0 88 10 15 cuu eu Metus 03 510 2 WA BIDIC44 rm PU X 13 2 10 q DHOGOHBHOH Al HO 44 7 QUIETE Index Marking 1 06x45 eN 1 Does not include plastic or metal protrusion of 0 25 max per side i A O Sorts of Packing Package outlines for tubes trays etc are contained in our Data Book Package Information SMD Surface Mounted Device Semiconductor Group 10 18 1997 08 01 SIEMENS Index C505
62. message object standard identifiers have bits ID17 0 filled with O This is implemented to keep the data bytes connected with the identifier even if arbitration mask registers are used When the CAN controller stores a remote frame only the data length code is stored into the corresponding message object The identifier and the data bytes remain unchanged There must not be more than one valid message object with a particular identifier at any time If some bits are masked by the global mask registers ie don t care then the identifiers of the valid message objects must differ in the remaining bits which are used for acceptance filtering If a received data frame is stored into a message object the identifier of this message object is updated If some of the identifier bits are set to don t care by the corresponding mask register these bits may be changed in the message object If a remote frame is received the identifier in transmit object remain unchanged except for the last message object which cannot start a transmission Here the identifier bits corresponding to the don t care bits of the last message object s mask may be overwritten by the incoming message Semiconductor Group 6 78 1997 08 01 SIEMENS On Chip Peripheral Components C505C Only CAN Upper Arbitration Register Low UARO Address F7n2 CAN Upper Arbitration Register High UAR1 Address F7n3 4 CAN Lower Arbitration Register Low LARO Add
63. om ERE DEapx 3 18 6 80 Fail save mechanisms 8 1 to 8 8 DEG lave Meee bee EPIS 3 18 6 80 Fast power on reset 5 3 8 8 DPE s Se mus Sees ees 3 12 3 15 4 7 Features us c2 ree Bate re Se EST 1 2 DPE ov tL cote eas 3 12 3 15 4 7 Functional units 1 1 DPSEL 255 ck mE 3 12 3 15 4 6 Fundamental structure 2 1 E ced ucvorsteg quip detta Gen er ue a 3 15 7 5 GATE S1 Dua E eoi emet vts 3 15 6 18 BADG hiat ei eas 3 16 6 103 7 6 EU eunt ets Be a het 3 15 9 1 EALE eph rre hd 1 8 3 16 4 4 GP ure autetn severe IAE 3 15 9 1 EANO Eus s asm aon ts ah ss 3 15 6 109 GNIS us ome Prou Mahe toe 3 14 3 18 6 72 EAN T C o usce dettes eden 3 15 6 109 GMS Titel Pausa ied 3 14 3 18 6 72 EAN2 x62 E E EELEDBS ES 3 15 6 109 FANS 600s e ee 3 15 6 109 Hardware reset 0000 00s 5 1 EANA 6 25 3533223253335 3 15 6 109 CANS ope eRe Sore ee VO POSi gure uit tax A RE 6 1 to 6 14 BANG co bide piti hoa pis 3 19 97109 ISPR ara en 3 16 6 26 7 8 BANT scusa uud Sav EA 3 15 6 109 ABO O e 3 16 6 103 7 9 AR Hd ADA aa S e oa Ea 3 18 EO Nee eende eea ree T o eN EE eed sere 2 3 18 EIE tas che nie TEDE hrti SABRO ID mie cen eR eii 3 18 li a E E oe teas VIE T E 3 18 ee EERE Soan Diseria n mea 2G les 3 18 Se ee ee e Se IDLE ei orata ESN 3 15 9 1 ET PRERADE OST cas en re cal les Idle Modes fs due Bees 9 3 to 9 4 FIG ee ia aR eae Eo I que eiu AC EE ELE 3 15 9 1 zd EET du cM 3 18 6 67
64. purposes the XMAP1 bit should not be set Otherwise the I O function of the port 0 and port 2 lines is interrupted Semiconductor Group 3 3 1997 08 01 SIEM ENS Memory Organization C505 C505C After a reset operation bit XMAPO is set This means that the accesses to XRAM and CAN controller are generally disabled In this case all accesses using MOVX instructions within the address range of F700 to FFFFy generate external data memory bus cycles When XMAPO is cleared the access to XRAM and CAN controller is enabled and all accesses using MOVX instructions with an address in the range of F700 to F7FFy will access the CAN controller and FFOOW to FFFF will access the internal XRAM Internal accesses XMAPO 0 in the address range gap from F800 to FEFFy for the C505C as shown in figure 3 1 will have undefined data In the case of the pure C505 microcontroller without CAN controller internal accesses in the address range of F700y to FEFFy will have undefined data Bit XMAPO is hardware protected If it is cleared once XRAM and CAN controller access enabled it cannot be set by software Only a reset operation will set the XMAPO bit again This hardware protection mechanism is done by an asymmetric latch at XMAPO bit An unintentional disabling of XRAM and CAN controller could be dangerous since indeterminate values could be read from the external bus To avoid this the XMAPO bit is forced to 1 only by a reset operation Additionally dur
65. rrr 2 3 2 2 GPU TIMING nu case o ERE atone tai tem eae adh Ced ieee ee AE 2 5 3 Memory Organization 2000 e cece eee eee 3 1 3 1 Program Memory Code Space uses lr s be ee ea eee Ge ea eS 3 2 3 2 Data Memory Data Space ix dur sob cuca ent ext oc dv idR de Dar e Senate 3 2 3 3 General Purpose Registers O49 e A orae sitem t te bie uo tede duca edet E 3 2 3 4 XRAM ODOLSDOR spas tirar Bossier retenues diae odere m iedball c ur tede Silt weis 3 3 3 4 1 XRAM CAN Controller Access Control 000 cece eee 3 3 3 4 2 Accesses to XRAM using the DPTR 16 bit Addressing Mode 3 5 3 4 3 Accesses to XRAM using the Registers RO R1 8 bit Addressing Mode 3 5 3 4 4 Reset Operation of the XRAM 000 0c cece eee 3 9 3 4 5 BeFiaviout of Fort D and POoLt 22 nt ace ede Ea be hedge SA hee ade whe ees 3 9 3 5 Special Function Registers 4 0 2 eke ths A RARE M ERU HE X AM RR s 3 11 4 External Bus Interface 5c tr ecient eine Ed eE us epe estet 4 1 4 1 Accessing External Memory 000 00 eee eee 4 1 4 1 1 Role of PO and P2 as Data Address Bus 00000 es 4 1 4 1 2 FMN uno odode dit Dim LOoNERSE RR ON te ee Bae ha Se Sie SSeS wae ee 4 3 4 1 3 External Program Memory Access 00 02ers 4 3 4 2 PSEN Program Store Enable iuncti e hed MoE euenit debui 4 3 4 3 Overlapping External Data and Program Memory Spaces 4 3 4 4 ALE Address Lateh Enable oo s EA aa rhe a
66. that changes of the interrupt status can be observed by the CPU The polling cycle is repeated with each machine cycle and the values polled are the values that were present at S5P2 of the previous machine cycle Note that if any interrupt flag is active but not being responded to for one of the conditions already mentioned or if the flag is no longer active when the blocking condition is removed the denied interrupt will not be serviced In other words the fact that the interrupt flag was once active but not serviced is not remembered Every polling cycle interrogates only the pending interrupt requests The polling cycle LCALL sequence is illustrated in figure 7 4 C1 gt a C2 p lt C3 gt lt C4 p lt C5 S5P2 4 SS SS i Interrupts Long Call to Interrupt Interrupt Interrupt are polled Vector Address Routine is latched MCT01920 Figure 7 4 Interrupt Response Timing Diagram Semiconductor Group 7 14 1997 08 01 IE Interrupt System SIEMENS C505 C505C Note that if an interrupt of a higher priority level goes active prior to S5P2 in the machine cycle labeled C3 in figure 7 4 then in accordance with the above rules it will be vectored to during C5 and C6 without any instruction for the lower priority routine to be executed Thus the processor acknowledges an interrupt request by executing a hardware generated LCALL to the appropriate servicing routine In some cases it also clears the flag that generated the in
67. the functions of acceptance filtering transmit search interrupt search and transfer completion It can be filled with up to 15 messages of 8 bytes data The CAN controller offers significantly improved status information over earlier versions enabling a much easier diagnosis of the state of the network Semiconductor Group 6 61 1997 08 01 SIEMENS On Chip Peripheral Components C505C Only BTL Configuration NA CRC join Gen Check TX RX Sh ift Register fi Messages Messages Handlers Intelligent Memory Interrupt Register Timing Generator we Clocks to all Control Z Status Bit Control Stream Processor Status Register to internal Bus Figure 6 30 CAN Controller Block Diagram Semiconductor Group 6 62 Error Management Logic MCB02736 1997 08 01 SIEMENS On Chip Peripheral Components C505C Only TX RX Shift Register The Transmit Receive Shift Register holds the destuffed bit stream from the bus line to allow the parallel access to the whole data or remote frame for the acceptance match test and the parallel transfer of the frame to and from the Intelligent Memory Bit Stream Processor BSP The Bit Stream Processor is a sequencer controlling the sequential data stream between the TX RX Shift Register the CRC Register and the bus line The BSP also controls the EML and the parallel data stream between the
68. the shift register it flags the RX control block to do one last shift and load SBUF At S1P1 of the 10th machine cycle after the write to SCON that cleared RI RECEIVE is cleared and RI is set Semiconductor Group 6 51 1997 08 01 SIEMENS On Chip Peripheral Components C505 C505C Write to SBUF RXD P3 0 Alt Output Function TXD P3 1 Alt Output Function Serial Port Interrupt REN RI al Start Receive RX Control RXD PS8OAIt Input Function Load SBUF Read SBUF 9 Internal Bus 2 MCS02101 Figure 6 24 Serial Interface Mode 0 Functional Diagram Semiconductor Group 6 52 1997 08 01 SIEMENS On Chip Peripheral Components C505 C505C Transmit S 4 Write to SBUF t S6P2 Send Shift TXD Shift Clock TI Receive Write to SCON Clear RI Receive Shift MCT02102 S5P TXD Shift Clock Figure 6 25 Serial Interface Mode 0 Timing Diagram Semiconductor Group 6 53 1997 08 01 IE On Chip Peripheral Components SIEMENS C505 C505C 6 3 5 Details about Mode 1 Ten bits are transmitted through TxD or received through RxD a start bit 0 8 data bits LSB first and a stop bit 1 On reception the stop bit goes into RB8 in SCON The baud rate is determined either by the timer 1 overflow rate or by the internal baud rate generator Figure 6 26 shows a
69. to emit logic high level 1 external pullups are required Addr Data Voc Read Control Latch Int Bus Write to Latch Read MCS02434 Pin Figure 6 3 Port 0 Circuitry Semiconductor Group 6 5 1997 08 01 IE On Chip Peripheral Components SIEMENS C505 C505C 6 1 2 2 Port 1 Port 3 and Port 4 Circuitry The pins of ports 1 3 and 4 are multifunctional They are port pins and also serve to implement special features as listed in table 6 2 Figure 6 4 shows a functional diagram of a port latch with alternate function To pass the alternate function to the output pin and vice versa however the gate between the latch and driver circuit must be open Thus to use the alternate input or output functions the corresponding bit latch in the port SFR has to contain a one 1 otherwise the pulldown FET is on and the port pin is stuck at O After reset all port latches contain ones 1 Alternate V Output jen FUROR Internal Latch Pull Up Arrangement Pin Int Bus E j Write v MCS01827 Read Alternate Pin Input Function Figure 6 4 Ports 1 3 and 4 The alternate functions of Port 4 pins are available for the C505C only Semiconductor Group 6 6 1997 08 01 SIEMENS On Chip Peripheral Components C505 C505C 6 1 2 3 Port 2 Circuitry As shown in figure 6 3 and below in figure 6 5 the output drivers of ports 0 and 2 can be switched
70. to external data memory that use 8 bit addresses MOVX Ri port 2 issues the contents of the P2 special function register and uses only the internal pullup resistors PSEN 26 O The Program Store Enable output is a control signal that enables the external program memory to the bus during external fetch operations It is activated every three oscillator periods except during external data memory accesses Remains high during internal program execution This pin should not be driven during reset operation ALE 27 O The Address Latch Enable output is used for latching the low byte of the address into external memory during normal operation It is activated every three oscillator periodes except during an external data memory access When instructions are executed from internal ROM EA 1 the ALE generation can be disabled by bit EALE in SFR SYSCON This pin should not be driven during reset operation Input O Output Semiconductor Group 1 8 1997 08 01 SIEMEN Introduction S C505 C505C Table 1 1 Pin Definitions and Functions Symbol Pin Number I O Function EA 29 External Access Enable When held at high level instructions are fetched from the internal ROM when the PC is less than 40004 When held at low level the C505 fetches all instructions from external program memory This pin should not be driven during reset operation For the C505 L and the C505C L this pin must be tied
71. to run the standard CAN protocol 11 bit identifiers as well as the extended CAN protocol 29 bit identifiers It provides a sophisticated object layer to relieve the CPU of as much overhead as possible when controlling many different message objects up to 15 This includes bus arbitration resending of garbled messages error handling interrupt generation etc In order to implement the physical layer external components have to be connected to the C505C The internal bus interface connects the on chip CAN controller to the internal bus of the microcontroller The registers and data locations of the CAN interface are mapped to a specific 256 byte wide address range of the external data memory area F700 to F7FF 4 and can be accessed using MOVX instructions Semiconductor Group 6 60 1997 08 01 SIEMEN On Chip Peripheral Components 3 C505C Only 6 4 1 Basic CAN Controller Functions The on chip CAN controller combines several functional blocks see figure 6 30 that work in parallel and contribute to the controller s performance These units and the functions they provide are described below The CAN controller provides storage for up to 15 message objects of maximum 8 data bytes length Each of these objects has a unique identifier and its own set of control and status bits Each object can be configured with its direction as either transmit or receive except the last message which is only a receive buffer with a special mask register
72. 01 SIEMENS Introduction C505 C505C Listed below is a summary of the main features of the C505 family Fully compatible to standard 8051 microcontroller Superset of the 8051 architecture with 8 datapointers Up to 20 MHz operating frequency 375 ns instruction cycle time 16 MHz 300 ns instruction cycle time 20 MHz 50 duty cycle 16K byte on chip ROM C505 2R and C505C 2R only Optional ROM protection available 256 byte on chip RAM 256 byte on chip XRAM Five ports 32 2 digital I O lines Port 1 with mixed analog digital I O capability Three 16 bit timers counters Timer 0 1 C501 compatible Timer 2 with 4 channels for 16 bit capture compare operation Full CAN Module C505C only 256 register data bytes located in external data memory area 1 MBaud CAN baudrate when operating frequency is equal to or above 8 MHz internal CAN clock prescaler when input frequency is over 10 MHz Full duplex serial interface with programmable baudrate generator USART 8 bit A D Converter Twelve interrupt sources with four priority levels On chip emulation support logic Enhanced Hooks Programmable 15 bit Watchdog Timer Oscillator Watchdog Fast Power On Reset Power Saving Modes Slow down mode Idle mode can be combined with slow down mode Software power down mode with wake up capability through INTO or P4 1 pin P MQFP 44 package Pin configuration is compatible to C501 C504 C511 C513 family Tempera
73. 100X01p Bit No MSB LSB 7 6 5 4 3 2 1 0 BiH EALE RMAP CMOD XMAP1 XMAPO SYSCON a The functions of the shaded bits are not described here Bit Function XMAP1 XRAM CAN controller visible access control Control bit for RD WR signals during XRAM CAN Controller accesses If addresses are outside the XRAM CAN controller address range or if XRAM is disabled this bit has no effect XMAP1 0 The signals RD and WR are not activated during accesses to the XRAM CAN Controller XMAP1 1 Ports 0 2 and the signals RD and WR are activated during accesses to XRAM CAN Controller In this mode address and data information during XRAM CAN Controller accesses are visible externally XMAPO Global XRAM CAN controller access enable disable control XMAPO 0 The access to XRAM and CAN controller is enabled XMAPO 1 The access to XRAM and CAN controller is disabled default after reset All MOVX accesses are performed via the external bus Further this bit is hardware protected x Reserved bits for future use Read by CPU returns undefined values When bit XMAP1 in SFR SYSCON is set during all accesses to XRAM and CAN Controller RD and WR become active and port 0 and 2 drive the actual address data information which is read written from to XRAM or CAN controller This feature allows to check the internal data transfers to XRAM and CAN controller When port 0 and 2 are used for I O
74. 2 30 us ADCC 25 t ADCC min 9 US 16 18 MHz 20 X fosc Figure 6 46 Minimum A D Conversion Time in Relation to System Clock Semiconductor Group 6 108 1997 08 01 SIEMENS On Chip Peripheral Components C505 C505C 6 5 5 A D Converter Analog Input Selection The analog inputs are located at port 1 The corresponding pins have a port structure which allows to use them either as digital I O pins or as analog inputs see section 6 1 3 2 The analog input function of these digital analog port lines are selected via the register P1ANA This register lies in the mapped SFR area and can be accessed when bit RMAP in SFR SYSCON is set when writing to its address 90 4 If a specific bit location of P1ANA is set the corresponding port line is configured as a digital input With a 0 in the bit location the port line operates as analog port Special Function Registers P1ANA Address 90 Reset Value FFy Bit No MSB LSB 7 6 5 4 3 2 1 0 90 EAN7 EAN6 EAN5 EAN4 EANS EAN2 EAN1 EANO P1ANA Bit Function EAN7 EANO Enable analog port 1 inputs If EANx x 7 0 is cleared port pin P1 x is enabled for operation as an analog input If EANx is set port pin P1 x is enabled for digital I O function default after reset Semiconductor Group 6 109 1997 08 01 IE Interrupt System SIEMENS C505 C505C 7 Interrupt System T
75. 3 16 6 43 VB usta ste ipt etes 3 16 6 26 RDG i acies reo d rede 3 17 6 97 PZR PEE 3 16 6 26 RAIE on eese sets de s oh 3 18 6 76 IBS rius ee Pret et bes 3 15 6 44 6 45 RXOK sacs ductos atte en uan d 3 18 6 68 GONG s dei 3 12 3 13 3 15 6 17 7 7 TEST odios reor ado aces a 3 18 6 67 GBE sec een 3 13 3 15 6 44 6 45 TEO s SEES 3 15 6 17 7 7 SCON 3 12 3 13 3 15 6 44 6 45 7 11 WR os 2s fA REDE Gies 3 15 6 17 7 7 Sors ted ec Cees nee 3 15 9 1 U 3 16 6 28 7 9 Serial interface USART 6 43 to 6 59 THO 3 13 3 15 6 16 Semiconductor Group 11 4 1997 08 01 SIEMENS ges C505 C505C T Ella di eR tye BES 3 13 3 15 6 16 UMLM1 3 14 3 18 6 74 E EI ro iei usa 3 13 3 16 6 27 Unprotected ROM verify timing 4 10 Tr esos See ae h 3 15 6 44 6 45 7 11 Timer counter lllsss 6 15 Version registers 4 13 Timer counter 0 and1 6 15 to 6 22 YRO sene pave abe ses 2 3 12 3 17 4 13 Mode 0 13 bit timer counter 6 19 VRI PU metr mtra rU 3 12 3 17 4 13 Mode 1 16 bit timer counter 6 20 VR2 S does te Eo e red 3 12 3 17 4 13 Mode 2 8 bit rel timer counter 6 21 W Mode 3 two 8 bit timer counter 6 22 Watchdog timer 8 1 to 8 5 REJSTES oss dd its OIG 10 8719 Block diagram 2222 xS iae 8 1 Timeneounier ooo us pos BEIDE Control status flags 8 3 Block diagram Re tna PA ee 6 24 Input clock selection 8 2 Capture function
76. 3 MR HP CERE 3 13 3 16 Pise RTT 3 17 6 102 CU NN CN MM 3 16 5 8 ADCONO 3 12 3 13 3 16 5 8 6 46 6 101 GLROUT era aia lane 3 15 5 8 ASIN I unde GWE OMOBo ss te tia vee 3 16 6 89 ADDATA uou Sot ie e vos 3 12 3 16 6 100 COCAHO oo evene oci cows 3 16 6 29 ADNI sur Seu d nC RR 3 16 6 101 COCAH1 3 16 6 29 ADS eee tie sed oves 3 12 3 16 6 100 COCAH2 3 16 6 29 ALE sigiial vno nr tA hie 4 4 COCAH3 3 16 6 29 B COCALO vederii dide Pis 3 16 6 29 Be a gAn E As uu s babes 2 4 3 12 3 17 COCA V sur i doe ci mn due d 3 16 6 29 Basic CPU timing oan te 2 5 COCAL2 uno i eee ies 3 16 6 29 B obest bte dud terra f ad 3 16 6 46 COCAL3 S e duc ane ee 3 16 6 29 Block diagram 2 esp Re es 2 2 CPU BOFF eeeeeseeees 3 18 6 68 Accumulator oci cec os 2 3 BRP 0 eee eee eee eee 3 18 6 71 B register sei ture ict 2 4 BSY Ge 3 16 6 101 Basic timing use retrace atii 2 5 BIRO 2 seer eee 3 14 3 18 6 71 Fetch execute diagram 2 6 BIR1 1 2 22 eee eee 3 14 3 18 6 71 Functionality aana anana Sos 2 3 C Program status word 2 3 GT sb Lee d c vete 3 15 6 18 Stack pointer 2 4 CAN controller 6 60 to 6 97 CPULTIMING sary het et heo e oret 2 6 Access control 5 3 3 GPUUPD ERR 3 18 6 77 Basic function 6 61 SEU iu ehid deeds 3 14 3 18 6 67 Bit time calculation 6 92 G
77. 5 1997 08 01 SIEMENS Fail Save Mechanisms C505 C505C 8 2 Oscillator Watchdog Unit The oscillator watchdog unit serves for three functions Monitoring of the on chip oscillator s function The watchdog supervises the on chip oscillator s frequency if it is lower than the frequency of the auxiliary RC oscillator in the watchdog unit the internal clock is supplied by the RC oscillator and the device is brought into reset if the failure condition disappears i e the on chip oscillator has a higher frequency than the RC oscillator the part in order to allow the oscillator to stabilize executes a final reset phase of typ 1 ms then the oscillator watchdog reset is released and the part starts program execution from address 00004 again Fast internal reset after power on The oscillator watchdog unit provides a clock supply for the reset before the on chip oscillator has started The oscillator watchdog unit also works identically to the monitoring function Control of external wake up from software power down mode When the power down mode is left by a low level at the P3 2 INTO pin or the P4 1 RXDC pin the oscillator watchdog unit assures that the microcontroller resumes operation execution of the power down wake up interrupt with the nominal clock rate In the power down mode the RC oscillator and the on chip oscillator are stopped Both oscillators are started again when power down mode is released When the on chip oscill
78. 505C 6 On Chip Peripheral Components This chapter gives detailed information about all on chip peripherals of the C505 except for the integrated interrupt controller which is described separately in chapter 7 6 1 Parallel I O The C505 has four 8 bit I O ports and one 2 bit I O port Port 0 is an open drain bidirectional I O port while ports 1 to 4 are quasi bidirectional I O ports with internal pullup resistors That means when configured as inputs ports 1 to 4 will be pulled high and will source current when externally pulled low Port 0 will float when configured as input The output drivers of port 0 and 2 and the input buffers of port O are also used for accessing external memory In this application port 0 outputs the low byte of the external memory address time multiplexed with the byte being written or read Port 2 outputs the high byte of the external memory address when the address is 16 bits wide Otherwise the port 2 pins continue emitting the P2 SFR contents In this function port 0 is not an open drain port but uses a strong internal pullup FET Port 4 is 2 bit I O port with CAN controller specific alternate functions This port has no available bits at bit positions 2 7 6 1 1 Port Structures The C505 generally allows digital I O on 34 lines grouped into 4 bidirectional 8 bit ports and one 2 bit port Each port bit consists of a latch an output driver and an input buffer Read and write accesses to the I O ports
79. 505C Table 3 3 Contents of the SFRs SFRs in numeric order of their addresses cont d Addr Register Content Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit 0 after Reset Bou P3 FFy RD WR T1 TO INT1 INTO TxD RxD Bip SYSCON XX10 EALE RMAP CMOD XMAP1 XMAPO 0X01p B8p IEN1 00H EXEN2 SWDT EX6 EX5 EX4 EX3 ECAN EADC B94 IP1 XX00 35 A4 3 2 A 0 0000p BAW SRELH XXXX ra 0 XX11p CO IRCON 00g EXF2 TF2 IEX6 IEX5 IEX4 IEX3 SWI IADC Cip CCEN 00H COCA COCAL COCA COCAL COCA COCAL COCA COCAL H3 3 H2 2 H1 1 HO 0 C24 CCL1 00H cf 6 5 4 3 2 A 0 C34 CCH1 00H of 6 5 4 EC 2 J 0 C44 CCL2 00H 7 6 5 4 3 2 A 0 C5y CCH2 00H T 6 25 4 3 2 A 0 C64 CCL3 00H Jd 6 5 A4 3 2 A 0 C74 CCHS 00H 7 6 5 4 3 2 A 0 C84 T2CON 00X0 T2PS ISFR T2R1 T2RO T2CM T2l1 T210 0000p CAM CRCL 00H n 6 5 4 3 2 A 0 CBy CRCH 00H iT 6 5 4 3 2 A 0 CCH TL2 00H af 6 5 A4 2d 2 A 0 CDu TH 00H 7 6 5 4 3 2 0 DOW PSW 00H CY AC FO RS1 RSO OV F1 P D84 ADCONO 00X0 BD CLK BSY ADM MX2 MX1 MXO 0000p D94 ADDAT 00y4 E 6 25 4 3 2 A 0 DAW ADST XXXX XXXXp 1 X means that the value is undefined and the location is reserved 2 Bit addressable special function registers Semiconductor Group 3 16 1997 08 01 SIEMEN Memory Organization S C505 C505C Table 3 3 Contents of the SFRs SFRs in numeric order of their addresse
80. 6 counter is immediately reset and 1FFy is written into the input shift register and reception of the rest of the frame will proceed The 16 states of the counter divide each bit time into 16ths At the 7th 8th and 9th counter states of each bit time the bit detector samples the value of RxD The value accepted is the value that was seen in at least 2 of the 3 samples This is done for the noise rejection If the value accepted during the first bit time is not O the receive circuits are reset and the unit goes back to looking for another 1 to 0 transition This is to provide rejection or false start bits If the start bit proves valid it is shifted into the input shift register and reception of the rest of the frame will proceed As data bits come in from the right 1s shift out to the left When the start bit arrives at the leftmost position in the shift register which in mode 1 is a 9 bit register it flags the RX control block to do one last shift load SBUF and RB8 and set RI The signal to load SBUF and RB8 and to set RI will be generated if and only if the following conditions are met at the time the final shift pulse is generated 1 Rl 20 and 2 either SM2 0 or the received stop bit 1 If one of these two condtions is not met the received frame is irretrievably lost If both conditions are met the stop bit goes into RB8 the 8 data bit goes into SBUF and RI is activated At this time whether the above conditions are me
81. 75 16 MHz 16 1 20 MHz 16 1 25 Figure 6 43 A D Converter Clock Selection Semiconductor Group 6 104 1997 08 01 SIEMENS On Chip Peripheral Components C505 C505C 6 5 4 A D Converter Timing An A D conversion is started by writing into special function register ADST A write to ADST will start a new conversion even if a conversion is currently in progress The conversion begins with the next machine cycle and the busy flag BSY will be set The A D conversion procedure is divided into three parts Sample phase ts used for sampling the analog input voltage Conversion phase tco used for the A D conversion Write result phase twp used for writing the conversion result into the ADDAT register The total A D conversion time is defined by tapcc which is the sum of the two phase times ts and tco The duration of the three phases of an A D conversion is specified by its specific timing parameter as shown in figure 6 44 Start of an Result is written AD conversion into ADDAT BSY Bit Conversion Phase tco twn Write mag Result tapcc Phase A D Conversion Time Cycle Time twn tin tance 7 fs tco tin tosc MCTO3300 Prescalar Ratio tg tco Conversion Time PS 2x PS xt 8x PS x tin tADCC CPU Cycles n Time Ref 32 64 x tin 256 x tin 320 Xtiy 5842xt N 32 X tin 128 x tin 160 xt 26 4x ty 16 x tin 64 x tin 80 Xtiy 1342x tj 8 X tin 32 X t
82. 9 5 1997 08 01 SIEMEN Power Saving Modes 5 C505 C505C 9 4 Software Power Down Mode In the software power down mode the RC oscillator and the on chip oscillator which operates with the XTAL pins is stopped Therefore all functions of the microcontroller are stopped and only the contents of the on chip RAM XRAM and the SFR s are maintained The port pins which are controlled by their port latches output the values that are held by their SFR s The port pins which serve the alternate output functions show the values they had at the end of the last cycle of the instruction which initiated the power down mode ALE and PSEN held at logic low level see table 9 1 In the power down mode of operation Vec can be reduced to minimize power consumption It must be ensured however that Vcc is not reduced before the power down mode is invoked and that Voc is restored to its normal operating level before the power down mode is terminated The software power down mode can be left either by an active reset signal or by a low signal at one of the wake up source pins Using reset to leave power down mode puts the microcontroller with its SFRs into the reset state Using either the P3 2 INTO pin or the P4 1 RXDC pin for power down mode exit starts the RC oscillator and the on chip oscillator and maintains the state of the SFRs which have been frozen when power down mode is entered Leaving power down mode should not be done before Vec is restored t
83. C 9 2 Idle Mode In the idle mode the oscillator of the C505 continues to run but the CPU is gated off from the clock signal However the interrupt system the serial port the A D converter the CAN controller C505C only and all timers with the exception of the watchdog timer are further provided with the clock The CPU status is preserved in its entirety the stack pointer program counter program status word accumulator and all other registers maintain their data during idle mode The reduction of power consumption which can be achieved by this feature depends on the number of peripherals running If all timers are stopped and the A D converter and the serial interfaces are not running the maximum power reduction can be achieved This state is also the test condition for the idle mode Icc Thus the user has to take care which peripheral should continue to run and which has to be stopped during idle mode Also the state of all port pins either the pins controlled by their latches or controlled by their secondary functions depends on the status of the controller when entering idle mode Normally the port pins hold the logical state they had at the time when the idle mode was activated If some pins are programmed to serve as alternate functions they still continue to output during idle mode if the assigned function is on This especially applies to the serial interface in case it cannot finish reception or transmission durin
84. C505C Only CAN Control Register CR Address F700 Reset Value 01H Bit No MSB LSB 7 6 B 4 3 2 1 0 F700H TEST CCE 0 0 EIE SIE IE INIT CR rw rw r r rw rw rw rw Bit Function TEST Test mode Make sure that bit 7 is cleared when writing to the control register as this bit controls a special test mode that is used for production testing During normal operation however this test mode may lead to undesired behaviour of the device CCE Configuration change enable Allows or inhibits microcontroller access to the bit timing register EIE Error interrupt enable Enables or disables interrupt generation on a change of bit BOFF or EWRN in the status register SIE Status change interrupt enable Enables or disables interrupt generation when a message transfer reception or transmission is successfully completed or a CAN bus error is detected and registered in the status register IE Interrupt enable Enables or disables interrupt generation from the CAN module to the interrupt controller of the C505C Does not affect status updates Additionally bit ECAN in SFR IEN1 and bit EAL in SFR IENO must be set when a CAN controller interrupt should be generated INIT Initialization Starts the initialization of the CAN controller when set Semiconductor Group 6 67 1997 08 01 SIEMENS On Chip Peripheral Components C505C Only CAN Status Registe
85. CON TCON RTCON TCON RTCON Enhanced Hooks MCU Interface Circuit Optional ERR 1 0 Ports Port3 Port 1 RPort2 RPortO TEA TALE TPSEN Target System Interface MCS02647 Figure 4 2 Basic C500 MCU Enhanced Hooks Concept Configuration Port 0 port 2 and some of the control lines of the C500 based MCU are used by Enhanced Hooks Emulation Concept to control the operation of the device during emulation and to transfer informations about the program execution and data transfer between the external emulation hardware ICE system and the C500 MCU 1 Enhanced Hooks Technology is a trademark and patent of MetaLink Corporation licenced to Siemens Semiconductor Group 4 5 1997 08 01 SIEMEN External Bus Interface S C505 C505C 4 6 Eight Datapointers for Faster External Bus Access 4 6 1 The Importance of Additional Datapointers The standard 8051 architecture provides just one 16 bit pointer for indirect addressing of external devices memories peripherals latches etc Except for a 16 bit move immediate to this datapointer and an increment instruction any other pointer handling is to be handled bytewise For complex applications with peripherals located in the external data memory space e g CAN controller or extended data storage capacity this turned out to be a bottle neck for the 8051 s communication to the external world Especially programming in high level languages PLM51 C51 PASCAL51 requires ext
86. F30H is moved to accumulator Semiconductor Group 3 8 1997 08 01 SIEM ENS Memory Organization C505 C505C The register XPAGE provides the upper address byte for accesses to XRAM with MOVX Ri instructions If the address formed by XPAGE and Ri points outside the XRAM CAN Controller address range an external access is performed For the C505 the content of XPAGE must be F7 FF in order to use the XRAM CAN Controller The software has to distinguish two cases if the MOVX Ri instructions with paging shall be used a Access to XRAM CAN Contr The upper address byte must be written to XPAGE or P2 both writes select the XRAM CAN controller address range b Access to external memory The upper address byte must be written to P2 XPAGE will be automatically loaded with the same address in order to deselect the XRAM 3 4 4 Reset Operation of the XRAM The contents of the XRAM are not affected by a reset After power up the contents are undefined while they remain unchanged during and after a reset as long as the power supply is not turned off If a reset occurs during a write operation to XRAM the content of a XRAM memory location depends on the cycle in which the active reset signal is detected MOVX is a 2 cycle instruction Reset during 1st cycle The new value will not be written to XRAM The old value is not affected Reset during 2nd cycle The old value in XRAM is overwritten by the new value 3 4 5 Behaviour of Port 0 a
87. L3 Compare capture register 3 low byte C6H CCH3 Compare capture register 3 high byte C7H IENO Interrupt enable register 0 A8H IEN1 Interrupt enable register 1 B8H IRCON Interrupt control register COL Semiconductor Group 6 25 1997 08 01 SIEMENS On Chip Peripheral Components C505 C505C The T2CON timer 2 control register is a bit addressable register which controls the timer 2 function and the compare mode of registers CRC CC1 to CC3 Special Function Register T2CON Address C8p Reset Value 00X00000p Bit No MSB LSB 7 6 5 4 3 2 1 0 CFy CEy CDYy CC CBYy CAYy C94 C8H C84 T2PS I3FR E TeR1 T2RO T2CM T211 T2I0 T2CON EET The shaded bits are not used for controlling timer counter 2 Bit Function T2PS Prescaler select bit When set timer 2 is clocked in the timer or gated timer function with 1 12 of the oscillator frequency When cleared timer 2 is clocked with 1 6 of the oscillator frequency T2PS must be 0 for the counter operation of timer 2 IBFR External interrupt 3 falling rising edge flag Used for capture function in combination with register CRC If set a capture to register CRC if enabled will occur on a positive transition at pin P1 0 ANO INT3 CCO T2R1 Timer 2 reload mode selection T2RO i T2R1 T2R0 Function 0 X Reload disabled 1 0 Mode 0 auto reload upon timer 2 overflow TF2 1 1 Mode 1 reload on f
88. LST F7nig RMTPND TARG CPUUPD NEWDAT MCR1 rw rw rw rw Bit Function MSGVAL Message valid Indicates if the corresponding message object is valid or not The CAN controller only operates on valid objects Message objects can be tagged invalid while they are changed or if they are not used at all TXIE Transmit interrupt enable Defines if bit INTPND is set after successful transmission of a frame 1 RXIE Receive interrupt enable Defines if bit INTPND is set after successful reception of a frame INTPND Interrupt pending Indicates if this message object has generated an interrupt request see TXIE and RXIE since this bit was last reset by the microcontroller or not Semiconductor Group 6 76 1997 08 01 SIEMEN On Chip Peripheral Components 3 C505C Only Bit Function RMTPND Remote pending used for transmit objects Indicates that the transmission of this message object has been requested by a remote node but the data has not yet been transmitted When RMTPND is set the CAN controller also sets TXRQ RMTPND and TXRQ are cleared when the message object has been successfully transmitted TXRQ Transmit request Indicates that the transmission of this message object is requested by the CPU or via a remote frame and is not yet done TXRQ can be disabled by CPUUPD 3 MSGLST Message lost this bit applies to receive objects only Indicates that the CAN controller has stored a new message into this ob
89. O THO TLO and INTO for the corresponding timer 1 signals in figure 6 9 There are two different gate bits one for timer 1 TMOD 7 and one for timer 0 TMOD 3 d 0 e TLO THO i 5 Bits 8 Bits TFO Interrupt C T 1 Control P3 4 TO o Gate O gt 1 P3 2 INTO MCS02726 Figure 6 9 Timer Counter 0 Mode 0 13 Bit Timer Counter Semiconductor Group 6 19 1997 08 01 SIEMENS On Chip Peripheral Components C505 C505C 6 2 1 3 Mode 1 Mode 1 is the same as mode 0 except that the timer register is running with all 16 bits Mode 1 is shown in figure 6 10 LU 0 e TLO THO i 8 Bits 8 Bits TFO Interrupt C T 1 Control P3 4 TO o Gate P3 2 INTO MCS02727 Figure 6 10 Timer Counter 0 Mode 1 16 Bit Timer Counter Semiconductor Group 6 20 1997 08 01 IE On Chip Peripheral Components SIEMENS C505 C505C 6 2 1 4 Mode 2 Mode 2 configures the timer register as an 8 bit counter TLO with automatic reload as shown in figure 6 11 Overflow from TLO not only sets TFO but also reloads TLO with the contents of THO which is preset by software The reload leaves THO unchanged C T 0 Ss eo A em C T 1 TFO Interrupt P3 4 T0 o Control Gate 4 21 P3 2 NTO o MCS02728 Figure 6 11 Timer Counter 0 1 Mode 2 8 Bit Timer Counter with Auto Reload Semiconductor Group 6 21 1997 08 01 IE On Chip Perip
90. OCAHO Compare capture mode for CRC register Conte COCAHO COCALO Function 0 0 Compare capture disabled 0 1 Capture on falling rising edge at pin P1 0 ANO INT3 CCO 1 0 Compare enabled Capture on write operation into register CRCL Semiconductor Group 6 29 1997 08 01 IE On Chip Peripheral Components SIEMENS C505 C505C 6 2 2 2 Timer 2 Operation The timer 2 which is a 16 bit wide register can operate as timer event counter or gated timer The detailed operation is described below Timer Mode In timer function the count rate is derived from the oscillator frequency A prescaler offers the possibility of selecting a count rate of 1 6 or 1 12 of the oscillator frequency Thus the 16 bit timer register consisting of TH2 and TL2 is either incremented in every machine cycle or in every second machine cycle The prescaler is selected by bit T2PS in special function register T2CON If T2PS is cleared the input frequency is 1 6 of the oscillator frequency if T2PS is set the 2 1 prescaler gates 1 12 of the oscillator frequency to the timer Gated Timer Mode In gated timer function the external input pin T2 P1 7 functions as a gate to the input of timer 2 If T2 is high the internal clock input is gated to the timer T2 0 stops the counting procedure This facilitates pulse width measurements The external gate signal is sampled once every machine cycle Event Counter Mode In the counter func
91. PO P4 are performed via their corresponding special function registers Depending on the specific ports multiple functions are assigned to the port pins Therefore the parallel I O ports of the C505 can be grouped into three different types which are listed in table 6 1 Table 6 1 C505 Port Structure Types Type Description A Standard digital I O ports which can also be used for external address data bus B Standard multifunctional digital I O port lines C Mixed digital analog I O port lines with programmable analog input function Type A and B port pins are standard C501 compatible I O port lines which can be used for digital I O The type A ports port 0 and port 2 are also designed for accessing external data or program memory Type B port lines are located at port 3 and port 4 to provide alternate functions for the serial interface and CAN controller I O lines respectively or are used as control outputs during external data memory accesses The C505 provides eight analog input lines which are realized as mixed digital analog inputs type C The 8 analog inputs ANO ANT are located at the port 1 pins P1 0 to P1 7 After reset all analog inputs are disabled and the related pins of port 1 are configured as digital inputs The analog function of the specific port 1 pins are enabled by bits in the SFRs P1ANA Writing a O to a bit position of P1ANA assigns the corresponding pin to operate as analog input Note P1ANA is a
92. RGEl fos osi ele eee es 3 13 6 27 Bit timing configuration 6 90 OG La sue dioit recon stators 3 13 6 27 Semiconductor Group 11 1 1997 08 01 SIEMENS Index C505 C505C ra oa iE ue thea eS 2 4 3 16 EXT betta aaa we 3 15 7 5 EXO brats Vete CE EO ees 3 16 7 6 Datapointers 4 6 to 4 9 EX4 6 e eee ee eee 3 16 7 6 Application examples 4 7 to 4 9 EX Eron PhS eL en Dade 3 16 7 6 DPSEL register 00 4 6 EX6 2 6 3 16 7 6 Functionality 2 4 6 Execution of instructions 2 5 2 6 DBO Scared S bote 3 14 3 19 6 81 EXEN2 esses 3 16 6 28 7 6 DBI eu teeren died s 3 14 3 19 6 81 EXF2 essen 3 16 6 28 7 9 DB2 L 3 14 3 19 6 81 External bus interface 4 1 DBS oi coh emet as 3 14 3 19 6 81 ALE signal 54 44 IJBA uL ai Du cds comi add 3 14 3 19 6 81 ALE switch off control 4 4 BO ERES IS Gee eats 3 14 3 19 6 81 Overlapping of data program memory 4 3 DBO indians eine nae 3 14 3 19 6 81 Program memory access 4 3 DB occid vs GEV oski 3 14 3 19 6 81 Program data memory timing 4 2 DC characteristics 10 2 to 10 4 PSEN signal 22er dcbet 4 3 Device Characteristics 10 1 to 10 19 Role of PO and P2 4 1 AC characteristics 16 MHz timing 10 7 to 10 9 Esta ate ae EE ioi cur itta itd 2 4 3 16 20 MHz timing 10 10 to 10 12 amc TT 2 4 3 16 DIRS
93. Refreshing the Watchdog Timer 0 cece eee 8 5 8 1 5 Watchdog Reset and Watchdog Status Flag 000c cee eee eee 8 5 8 2 Oscillator Watchdog Unit xcu eoe melee RP RESERPPII er ete ee 8 6 9 Power Saving Modes 200 e cece eee eee nnn nnn 9 1 9 1 Power Saving Mode Control Registers 200 0c eee eee 9 1 9 2 lde Mode pex Sev e Cod ew irs i ae ata sie t eel RC Re DL RE 9 3 9 3 slow Down Mode Operation sisse hr ek Ea DR EE RE eo 9 5 9 4 Software Power Down Mode 0200 e eee eee eee 9 6 9 4 1 Invoking Software Power Down Mode 200 0 cece eee eee eee 9 6 9 4 2 Exit from Software Power Down Mode ss cece eee eee eee 9 7 9 5 State of Pins in Software Initiated Power Saving Modes 000 9 8 Semiconductor Group l 3 1997 08 01 SIEMENS General Information C505 C505C Table of Contents Page 10 Device Specitlcatlons 3 2sc0 fests Soe te ee ee Reet ETERNA qu EE 10 1 10 1 Absolute Maximum Ratings iiie RC RETE REFERT IEAREEETREERSAES 10 1 10 2 DO CharacterislieS 4 same Eh ax eb ewes gees Pause Soha levee ees eae 10 2 10 3 A D Converter Characteristics iu eset yew oi atte ww oe re ees ats cee 10 4 10 4 AC Characteristics 16 MHz for C505 0 2 00 ee 10 6 10 5 AC Characteristics 20 MHz for C505 0 00 cee 10 9 10 6 ROM Verification Characteristics for C505 2R saana aerae 10 15 10 7 Package Intotatlolt vum te depre eee ehe hi
94. SIEMENS s iemens S emiconduc tor Infineon in eon Technologies he next revision of this document will be updated accordingly C505 C505C 8 Bit CM OS M icrocontroller User s M anual 08 97 C505 User s Manual Revision History 1997 08 01 Previous Releases Original Version Page Page Subjects changes since last revision previous new version version Edition 1997 08 01 This edition was realized using the software system FrameMaker Published by Siemens AG Bereich Halbleiter Marketing Kommunikation BalanstraBe 73 81541 Munchen Siemens AG 1997 All Rights Reserved Attention please As far as patents or other rights of third parties are concerned liability is only assumed for components not for applications processes and circuits implemented within components or assemblies The information describes the type of component and shall not be considered as assured characteristics Terms of delivery and rights to change design reserved For questions on technology delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies and Representatives worldwide Due to technical requirements components may contain dangerous substances For information on the types in question please contact your nearest Siemens Office Semiconductor Group Siemens AG is an approved CECC manufacturer Packing Please use the recycling operators kn
95. TXRQ CPUUPD NEWDAT After updating the message the microcontroller should clear CPUUPD and set NEWDAT If the microcontroller wants to transmit the message it should also set TXRQ which should otherwise be left alone Semiconductor Group 6 95 1997 08 01 On Chip Peripheral Components IE SIEMENS C505C Only 6 4 9 Configuration Examples of a Reception Object The microcontroller wishes to configure an object for reception It wishes to receive an interrupt each time new data comes in From time to time the microcontroller sends a remote request to trigger the sending of this data from a remote node Initialization The identifier and direction are set up Message Control Register Bit No MSB LSB 7 6 3 2 1 0 1 0 1 0 0 1 MCRO MSGVAL TXIE RXIE INTPND 0 1 0 1 0 1 0 1 MCR 1 RMTPND TXRQ MSGLST NEWDAT Configuration after reception of data Message Control Register Bit No MSB LSB 7 6 3 2 1 0 1 0 1 0 1 0 MCRO MSGVAL TXIE RXIE INTPND 0 1 0 1 1 0 MCR1 RMTPND TXRQ MSGLST NEWDAT To process the message the microcontroller should clear IntPnd clear NewDat process the data and check that NewDat is still clear If not it should repeat the process again To send a remote frame to request the data the microcontroller simply needs to set the TXRQ bit This bit will be cleared by the CAN controller once the remote frame has been sent or if the data is received
96. U processes the interrupt call and during these two machine cycles ALE and PSEN behave as shown in figure 9 1 i e at the begining of phase 4 Instruction fetches during the interrupt call are however discarded 4 After the RETI instruction of the power down wake up interrupt routine has been executed the instruction which follows the initiating power down mode double instruction sequence will be executed The peripheral units timer 0 1 2 CAN controller and WDT are frozen until end of phase 4 All interrupts of the C505 are disabled from phase 2 until the end of phase 4 Other Interrupts can be first handled after the RETI instruction of the wake up interrupt routine The procedure to exit the software power down mode via the P4 1 RXDC pin is identical to the above procedure except that in this case pin P4 1 RXDC replaces pin P3 2 INTO and bit WS in SFR PCON1 should be set prior to entering software power down mode 9 5 State of Pins in Software Initiated Power Saving Modes In the idle mode and in the power down mode the port pins of the C505 have a well defined status which is listed in the following table 9 1 This state of some pins also depends on the location of the code memory internal or external Table 9 1 Status of External Pins During Idle and Software Power Down Mode Outputs Last Instruction Executed from Last Instruction Executed from Internal Code Memory External Code Memory Idle Power Dow
97. UUH MCR1 Message Control Register High F niQ9 UUH UARO Upper Arbitration Register Low F7n2y UUH UAR1 Upper Arbitration Register High F7n3y UUH LARO Lower Arbitration Register Low F7n4Q4 9 UUH LAR1 Lower Arbitration Register High F7n5H UUUUUO00g MCFG Message Configuration Register F7n6H UUUUUUO0g DBO Message Data Byte 0 F7 n7Q49 XXH DB1 Message Data Byte 1 F7n84 9 XXH DB2 Message Data Byte 2 F7n9y XXH DB3 Message Data Byte 3 F7nAy XXH DB4 Message Data Byte 4 F7nBy XXH DB5 Message Data Byte 5 F7nCH XXH DB6 Message Data Byte 6 F7nDy XXH DB7 Message Data Byte 7 F7nEy 9 XXH 1 Bit addressable special function registers 2 This special function register is listed repeatedly since some bits of it also belong to other functional blocks 3 X means that the value is undefined and the location is reserved U means that the value is unchanged by a reset operation U values are undefined as X after a power on reset operation 4 SFR is located in the mapped SFR area For accessing this SFR bit RMAP in SFR SYSCON must be set 5 The notation n n 1 to F in the message object address definition defines the number of the related message object Semiconductor Group 1997 08 01 SIEMENS Memory Organization C505 C505C Table 3 3 Contents of the SFRs SFRs in numeric order of their
98. UUUO00p Bit No MSB LSB 7 6 5 4 3 2 1 0 F708y ID28 21 UGMLO rw F709 ID20 13 UGML1 rw F70AH ID12 5 LGMLO rw F70By ID4 0 0 0 0 LGML1 rw r r r Bit Function ID28 0 Identifier 29 bit Mask to filter incoming messages with extended identifier Semiconductor Group 6 73 1997 08 01 IEMEN On Chip Peripheral Components iun i C505C Only CAN Upper Mask of Last Message Register Low UMLMO Addr F70Cjj Reset Value UUH CAN Upper Mask of Last Message Register High UMLM1 Addr F70D 4 Reset Value UUH CAN Lower Mask of Last Message Register Low LMLMO Addr F70Ey Reset Value UUH CAN Lower Mask of Last Message Reg High LMLM1 Addr F70Fy Reset Val UUUUUO00p Bit No MSB LSB 7 6 5 4 3 2 1 0 F70Cy ID28 21 UMLMO rw F70Dy ID20 18 ID17 13 UMLM1 rw rw F70Ey ID12 5 LMLMO rw F70Fy ID4 0 0 0 0 LMLM1 rw r r r Bit Function ID28 0 Identifier 29 bit Mask to filter the last incoming message no 15 with standard or extended identifier as configured Semiconductor Group 6 74 1997 08 01 SIEMEN On Chip Peripheral Components 3 C505C Only 6 4 2 2 The Message Object Registers Data Bytes The message object is the primary means of communication between microcontroller and CAN controller Each of the 15 message objects uses 15 consecutive bytes see figure 6 32 and starts at an address that is a multiple of 16 message object n base address N 1 to Fy Not
99. VX instructions EALE 1 ALE generation is enabled If EA 0 the ALE generation is always enabled and the bit EALE has no effect on the ALE generation Reserved bits for future use Read by CPU returns undefined values Semiconductor Group 4 4 1997 08 01 SIEMEN External Bus Interface S C505 C505C 4 5 Enhanced Hooks Emulation Concept The Enhanced Hooks Emulation Concept of the C500 microcontroller family is a new innovative way to control the execution of C500 MCUs and to gain extensive information on the internal operation of the controllers Emulation of on chip ROM based programs is possible too Each C500 production chip has built in logic for the support of the Enhanced Hooks Emulation Concept Therefore no costly bond out chips are necessary for emulation This also ensure that emulation and production chips are identical The Enhanced Hooks Technology which requires embedded logic in the C500 allows the C500 together with an EH IC to function similar to a bond out chip This simplifies the design and reduces costs of an ICE system ICE systems using an EH IC and a compatible C500 are able to emulate all operating modes of the different versions of the C500 microcontrollers This includes emulation of ROM ROM with code rollover and ROMless modes of operation It is also able to operate in single step mode and to read the SFRs after a break ICE System Interface to Emulation Hardware SYSCON RSYS
100. W could be moved into TB8 On receive the 9th data bit goes into RB8 in special function register SCON while the stop bit is ignored The baud rate is programmable to either 1 16 or 1 32 of the oscillator frequency See section 6 3 6 for more detailed information Mode 3 9 Bit USART Variable Baud Rate 11 bits are transmitted through TxD or received through RxD a start bit 0 8 data bits LSB first a programmable 9th data bit and a stop bit 1 In fact mode 3 is the same as mode 2 in all respects except the baud rate The baud rate in mode 3 is variable See section 6 3 6 for more detailed information In all four modes transmission is initiated by any instruction that uses SBUF as a destination register Reception is initiated in mode 0 by the condition RI 0 and REN 1 Reception is initiated in the other modes by the incomming start bit if REN 1 The serial interface also provides interrupt requests when transmission or reception of a frames have been completed The corresponding interrupt request flags are TI or RI resp See chapter 7 of this user manual for more details about the interrupt structure The interrupt request flags TI and RI can also be used for polling the serial interface if the serial interrupt is not to be used i e serial interrupt not enabled Semiconductor Group 6 43 1997 08 01 IE On Chip Peripheral Components SIEMENS C505 C505C 6 3 1 Multiprocessor Communication Modes 2 and 3 have
101. XDC me Np a RETI 10 us Insruction Detailed Timing of Beginning of Phase 4 ALE V OM VL M LL PSEN 4 VY Y V P2 Invalid Address o X PO Invalid Address Data 2 0D 1 st instr of ISR MCT03309 Figure 9 1 Wake up from Power Down Mode Procedure When the power down mode wake up capability has been enabled bit EWPD in SFR PCON1 set prior to entering power down mode and bit WS in SFR PCON 1 is cleared the power down mode can be exit via INTO while executing the following procedure 1 In power down mode pin P3 2 INTO must be held at high level 2 Power down mode is left when P3 2 INTO goes low for at least 10 us latch phase After this delay the internal RC oscillator and the on chip oscillator are started the state of pin P3 2 INTO is internally latched and P3 2 INTO can be set again to high level if required Thereafter the oscillator watchdog unit controls the wake up procedure in its start up phase Semiconductor Group 9 7 1997 08 01 IE Power Saving Modes 2 ii ex C505 C505C 3 The oscillator watchdog unit starts operation When the on chip oscillator clock is detected for stable nominal frequency the microcontroller starts again with its operation initiating the power down wake up interrupt The interrupt address of the first instruction to be executed after wake up is 007Bp ALE and PSEN are in their power down state up to this time At the end of phase 3 the CP
102. a sequence of 11 recessive bits has been monitored a BitOError code is written to the control register enabling the microcontroller to check up whether the CAN bus is stuck at dominant or continously disturbed and to monitor the proceeding of the busoff recovery sequence 6 4 5 Configuration of the Bit Timing According to the CAN specification a bit time is subdivided into four segments see figure 6 40 Each segment is a multiple of the time quantum t The synchronization segment Sync Seg is always one tg long The propagation time segment and the phase buffer segment1 combined to Tseg1 defines the time before the sample point while phase buffer segment2 Tseg2 defines the time after the sample point The length of these segments is programmable except Sync Seg Note For exact definition of these segments please refer to the CAN specification 1 Bit Time 1 Time Quantum Transmit ty Point MCT02745 Figure 6 40 Bit Timing Definition Semiconductor Group 6 90 1997 08 01 SIEMEN On Chip Peripheral Components 3 C505C Only The bit time is determined by the C505C clock period CLP see AC characteristics the Baud Rate Prescaler and the number of time quanta per bit bit time tsync Seg TSeg1 tTSeg2 lSync Seg 1xt tTSeg1 TSEG1 1 xXty min 4 x tg tTseg2 TSEG2 1 X tq min 3 x tg i BRP 1 x 2 1 7 CMOD x gi p TSEG1 TSEG2 and BRP are the programmed numerical values
103. a special provision for multiprocessor communications In these modes 9 data bits are received The 9th one goes into RB8 Then comes a stop bit The port can be programmed such that when the stop bit is received the serial port interrupt will be activated only if RB8 1 This feature is enabled by setting bit SM2 in SCON A way to use this feature in multiprocessor systems is as follows When the master processor wants to transmit a block of data to one of several slaves it first sends out an address byte which identifies the target slave An address byte differs from a data byte in that the 9th bit is 1 in an address byte and 0 in a data byte With SM2 1 no slave will be interrupted by a data byte An address byte however will interrupt all slaves so that each slave can examine the received byte and see if it is beeing addressed The addressed slave will clear its SM2 bit and prepare to receive the data bytes that will be coming The slaves that weren t being addressed leave their SM2s set and go on about their business ignoring the incoming data bytes SM2 has no effect in mode 0 SM2 can be used in mode 1 to check the validity of the stop bit In a mode 1 reception if SM2 1 the receive interrupt will not be activated unless a valid stop bit is received 6 3 2 Serial Port Registers The serial port control and status register is the special function register SCON This register contains not only the mode selection bits but also the 9
104. alling edge at pin P1 5 AN5 T2EX T2CM Compare mode bit for registers CRC CC1 through CC3 When set compare mode 1 is selected T2CM 0 selects compare mode 0 T211 Timer 2 input selection T210 T2l1 T210 Function 0 0 No input selected timer 2 stops 0 1 Timer function input frequency f55 6 T2PS 0 or fosc 12 T2PS 1 1 0 Counter function external input signal at pin P1 7 AN7 T2 1 1 Gated timer function input controlled by pin P1 7 AN7 T2 Semiconductor Group 6 26 1997 08 01 SIEMENS On Chip Peripheral Components C505 C505C Special Function Register TL2 Address CC j Special Function Register TH2 Address CD Special Function Register CRCL Address CA Special Function Register CRCH Address CB Reset Value 00H Reset Value 00H Reset Value 00H Reset Value 00H BitNo MSB LSB 7 6 5 4 0 CCy 7 6 5 4 LSB TL2 CDy MSB 6 5 4 0 TH2 CAH E 6 5 4 LSB CRCL CBy MSB 6 25 4 0 CRCH Bit Function TL2 7 0 Timer 2 value low byte The TL2 register holds the 8 bit low part of the 16 bit timer 2 count value TH2 7 0 Timer 2 value high byte The TH2 register holds the 8 bit high part of the 16 bit timer 2 count value CRCL 7 0 Reload register low byte compare capture functions CRCL is the 8 bit low byte of the 16 bit reload register of timer 2 It is also used for CRCH 7 0 Rel
105. and register contents not only manipulates the compare output but also sets the corresponding interrupt request flag Thus the current task of the CPU is interrupted of course provided the priority of the compare interrupt is higher than the present task priority and the corresponding interrupt service routine is called This service routine then sets up all the necessary parameters for the next compare event Advantages when using compare interrupts Firstly there is no danger of unintentional overwriting a compare register before a match has been reached This could happen when the CPU writes to the compare register without knowing about the actual timer 2 count Secondly and this is the most interesting advantage of the compare feature the output pin is exclusively controlled by hardware therefore completely independent from any service delay which in real time applications could be disastrous The compare interrupt in turn is not sensitive to such delays since it loads the parameters for the next event This in turn is supposed to happen after a suff icient space of time Please note the following special case where a program using compare interrupts could show a surprising behavior The configuration has already been mentioned in the description of compare mode 1 The fact that the compare interrupts are transition activated becomes important when driving timer 2 with a slow external clock In this case it should be carefully conside
106. ange for a PWM signal To calculate with reasonable numbers a reduction of the resolution to 8 bit is used Otherwise for the maximum resolution of 16 bit the modulation range would be so severely limited that it would be negligible Example Timer 2 in auto reload mode contents of reload register CRC FFOO Restriction of modulation range 1 256 x 2 x 100 0 195 This leads to a variation of the duty cycle from 0 195 to 99 805 for a timer 2 CCx register configuration when 8 of 16 bits are used Semiconductor Group 6 35 1997 08 01 IE On Chip Peripheral Components SIEMENS C505 C505C 6 2 2 3 3 Compare Mode 1 In compare mode 1 the software adaptively determines the transition of the output signal It is commonly used when output signals are not related to a constant signal period as in a standard PWM Generation but must be controlled very precisely with high resolution and without jitter In compare mode 1 both transitions of a signal can be controlled Compare outputs in this mode can be regarded as high speed outputs which are independent of the CPU activity If compare mode 1 is enabled and the software writes to the appropriate output latch at the port the new value will not appear at the output pin until the next compare match occurs Thus one can choose whether the output signal is to make a new transition 1 to 0 or 0 to 1 depending on the actual pinlevel or should keep its old value at the time the timer 2 co
107. ation Mode 2 ROM verification mode 2 is selected if the inputs PSEN EA and ALE are put to the specified logic levels With RESET going inactive the ROM verification mode 2 sequence is started The C505 outputs an ALE signal with a period of 3 CLP and expects data bytes at port 0 The data bytes at port 0 are assigned to the ROM addresses in the following way 1 Data Byte content of internal ROM address 0000H 2 Data Byte content of internal ROM address 0001 3 Data Byte content of internal ROM address 00024 16 Data Byte content of internal ROM address 000FH The C505 2R does not output any address information during the ROM verification mode 2 The first data byte to be verified is always the byte which is assigned to the internal ROM address 00004 and must be put onto the data bus with the falling edge of RESET With each following ALE pulse the ROM address pointer is internally incremented and the expected data byte for the next ROM address must be delivered externally Between two ALE pulses the data at port 0 is latched at 3 CLP after ALE rising edge and compared internally with the ROM content of the actual address If an verify error is detected the error Semiconductor Group 4 11 1997 08 01 SIEMENS External Bus Interface C505 C505C condition is stored internally After each 16th data byte the cumulated verify result pass or fail of the last 16 verify operations is output at P3 5 This means that P3 5 stays at stat
108. ator has a higher frequency than the RC oscillator the microcontroller starts program execution by processing a power down interrupt after a final delay of typ 1 ms in order to allow the on chip oscillator to stabilize Note The oscillator watchdog unit is always enabled Figure 8 3 shows the block diagram of the oscillator watchdog unit It consists of an internal RC oscillator which provides the reference frequency for the comparison with the frequency of the on chip oscillator It also shows the additional provisions for integration of the wake up from power down mode Special Function Register IPO Address A9 Reset Value 00H MSB LSB BitNo 7 6 5 4 3 2 1 0 A94 OWDS WDTS IPO 5 IPO 4 IPO 3 IPO 2 IPO 1 IPO 0 IPO The shaded bits are not used for fail save control Bit Function OWDS Oscillator Watchdog Status Flag Set by hardware when an oscillator watchdog reset occured Can be set and cleared by software Semiconductor Group 8 6 1997 08 01 SIEMENS Fail Save Mechanisms C505 C505C EWPD WS Power Down PCON1 7 PCON1 4 Mode Activated Power Down Mode P4 1 RXDC Wake Up Interrupt Control Control P3 2 INTO Logic Logic Internal Reset O e Start Stop RC Oscillator Frequency Comparator On Chip Oscillator IPO A94 o ows L Int Clock Oo gt MCB03308
109. bottle neck for the 8051 s communication to the external world Especially programming in high level languages PLM51 C51 PASCAL51 requires extended RAM capacity and at the same time a fast access to this additional RAM because of the reduced code efficiency of these languages Accumulator ACC is the symbol for the accumulator register The mnemonics for accumulator specific instructions however refer to the accumulator simply as A Program Status Word The Program Status Word PSW contains several status bits that reflect the current state of the CPU Semiconductor Group 2 3 1997 08 01 SIEMENS Fundamental Structure C505 C505C Special Function Register PSW Address DOj Reset Value 00H Bit No MSB LSB D7y D6y D5y D4y D3y D2y Diy DOH DOH CY AC FO RS1 RSO OV F1 P PSW Bit Function CY Carry Flag Used by arithmetic instructions AC Auxiliary Carry Flag Used by instructions which execute BCD operations FO General Purpose Flag RS1 Register Bank select control bits RSO These bits are used to select one of the four register banks RS1 RSO Function 0 0 Bank 0 selected data address 005 071 0 1 Bank 1 selected data address 08p 0F 1 0 Bank 2 selected data address 1054 17 1 1 Bank 3 selected data address 18 4 1F yy OV Overflow Flag Used by arithmetic instructions F1 General Purpose Flag P Parity Flag Set cleared by hardware after each instruct
110. by 16 results in the actual baud rate However all formulas given in the following section already include the factor and calculate the final baud rate Further the abrevation fosc refers to the external clock frequency oscillator or external input clock operation The baud rate of the serial port is controlled by two bits which are located in the special function registers as shown below Special Function Register ADCONO Address D8 Reset Value 00X00000p Special Function Register PCON Address 871 Reset Value 00H Bit No MSB LSB DFy DEY DDy DCy DBy DAY D94 D8H D8y BD CLK BSY ADM MX2 MX1 MXO ADCONO 7 6 5 4 3 2 1 0 874 SMOD PDS IDLS SD GF1 GFO PDE IDLE PCON The shaded bits are not used for controlling the baud rate Bit Function BD Baud rate generator enable When set the baud rate of serial interface is derived from the dedicated baud rate generator When cleared default after reset baud rate is derived from the timer 1 overflow rate SMOD Double baud rate When set the baud rate of serial interface in modes 1 2 3 is doubled After reset this bit is cleared Reserved bits for future use Read by CPU returns undefined values Figure 6 22 shows the configuration for the baud rate generation of the serial port Semiconductor Group 6 46 1997 08 01 SIEMENS On Chip Peripheral Components C505 C505C Tim
111. chdog unit avoids this situation In this case after power on the oscillator watchdog s RC oscillator starts working within a very short start up time typ less than 2 microseconds In the following the watchdog circuitry detects a failure condition for the on chip oscillator because this has not yet started a failure is always recognized if the watchdog s RC oscillator runs faster than the on chip oscillator As long as this condition is detected the watchdog uses the RC oscillator output as clock source for the chip rather than the on chip oscillator s output This allows correct resetting of the part and brings also all ports to the defined state see figure 5 2 Under worst case conditions fast Voc rise time e g 1us measured from Vec 4 25 V up to stable port condition the delay between power on and the correct port reset state is Typ 18 us Max 34ys The RC oscillator will already run at a Voc below 4 25V lower specification limit Therefore at slower Vcc rise times the delay time will be less than the two values given above After the on chip oscillator has finally started the oscillator watchdog detects the correct function then the watchdog still holds the reset active for a time period of max 768 cycles of the RC oscillator clock in order to allow the oscillation of the on chip oscillator to stabilize figure 5 2 Il Subsequently the clock is supplied by the on chip oscillator and the oscillator watchdog s reset
112. ck is still supplied by the RC Semiconductor Group 8 7 1997 08 01 SIEMENS Fail Save Mechanisms C505 C505C oscillator and the part is held in reset This allows a reliable stabilization of the on chip oscillator After that the watchdog switches the clock supply back to the on chip oscillator and releases the oscillator watchdog reset If no other reset is applied at this time the part will start program execution If an external reset or a watchdog timer reset is active however the device will retain the reset state until the other reset request disappears Furthermore the status flag OWDS is set if the oscillator watchdog was active The status flag can be evaluated by software to detect that a reset was caused by the oscillator watchdog The flag OWDS can be set or cleared by software An external reset request however also resets OWDS and WDTS If software power down mode is activated the RC oscillator and the on chip oscillator are stopped Both oscillators are again started in power down mode when a low level is detected at either the P3 2 INTO input pin or the P4 1 RXDC pin and when bit EWPD in SFR PCONI is set wake up from power down mode enabled The wake up source is chosen from one of P3 2 INTO and P4 1 RXDC by bit WS in SFR PCON1 In this case the oscillator watchdog does not execute an internal reset during startup of the on chip oscillator After the start up phase of the on chip oscillator the watchdog generates a pow
113. conductor Group 6 23 1997 08 01 SIEMENS On Chip Peripheral Components C505 C505C P1 5 TOEX Interrupt T2l0 Request m n EXEN2 o Reload IUBET 9 12 T2PS pe C ompare P10 INT3 cco Comparator Comparator Comparator Comparator T CC1 Output s SEI Ih m Lg INT5 Capture CC2 P1 2 INT6 CCL3 CCH3 CCL2 CCH2 CCL1 CCH1 CRCL CRCH CC3 MCB02730 Figure 6 13 Timer 2 Block Diagram Semiconductor Group 6 24 1997 08 01 IE On Chip Peripheral Components SIEMENS C505 C505C 6 2 2 1 Timer 2 Registers This chapter describes all timer 2 related special function registers of timer 2 The interrupt related SFRs are also included in this section Table 6 5 summarizes all timer 2 SFRs Table 6 5 Special Function Registers of the Timer 2 Unit Symbol Description Address T2CON Timer 2 control register C8y TL2 Timer 2 low byte CCH TH2 Timer 2 high byte CDH CCEN Compare capture enable register Ciy CRCL Compare reload capture register low byte CAH CRCH Compare reload capture register high byte CBy CCL1 Compare capture register 1 low byte C2y CCH1 Compare capture register 1 high byte C3y CCL2 Compare capture register 2 low byte C4y CCH2 Compare capture register 2 high byte C5y CC
114. dling of the Last Message Object Semiconductor Group 6 86 1997 08 01 SIEMENS On Chip Peripheral Components C505C Only MCU releases Buffer 2 MCU allocates Buffer 2 MCU releases Buffer 1 Buffer 1 released Buffer 2 released MCU access to Buffer 2 Buffer 1 released Buffer 2 allocated MCU access to Buffer 2 Store received Message into Buffer 1 Buffer 1 allocated Buffer 2 allocated MCU access to Buffer 2 Store received MCU releases message into Buffer 2 Buffer 1 MSGLST is set Allocated NEWDAT 1 OR RMTPND 1 Released NEWDAT 0 AND RMTPND 0 Store received Message into Buffer 1 Buffer 1 allocated Buffer 2 released MCU access to Buffer 1 Store received Message into Buffer 2 Buffer 1 allocated Buffer 2 allocated MCU access to Buffer 1 MCU releases Store received Buffer 1 message into Buffer 2 MSGLST is set MCD02744 Figure 6 38 Microcontroller Handling of the Last Message Object s Alternating Buffer Semiconductor Group 6 87 1997 08 01 SIEMEN On Chip Peripheral Components 3 C505C Only 6 4 4 Initialization and Reset The CAN controller is reset by a hardware reset the oscillator watchdog reset or by a watchdog timer reset of the C505C A reset operation of the CAN controller performs the following actions sets the TXDC output to 1 recessive clears the error counters resets the busoff state
115. ductor Group 6 64 1997 08 01 SIEMEN On Chip Peripheral Components 3 C505C Only 6 4 2 CAN Register Description Notational Conventions Each CAN register is described with its bit symbols address reset value and a functional description of each bit or bitfield Also the access type is indicated for each bit or bitfield r forread access w for write access rw for read and write access After reset the CAN registers either contain a defined reset value keep their previous contents UUy or are undefined XXH Locations that are unchanged UU after reset of course are undefined XX after a power on reset operation The reset values are defined either in hex with index p or binary with index p expressions The notation n in the address definition of the message object registers defines the number of the related message object n 1 15 6 4 2 1 General Registers The general registers of the CAN controller are located at the external data memory location F700 to F70Fy The registers of this general register block is shown in figure 6 31 The address mapping of the 16 registers bytes of a message object is shown in figure 6 32 Semiconductor Group 6 65 1997 08 01 IE On Chip Peripheral Components SIEMENS C505C Only CAN Register Address Area General Registers ia ci MCD02737 Figure 6 31 CAN Module Address Map Semiconductor Group 6 66 1997 08 01 IEMEN On Chip Peripheral Components iun i
116. e All message objects must be initialized by the C505C even those which are not going to be used before clearing the INIT bit Offset Register Address Calculation Message Control Reg Low Message Object n Register Address Message Object n Base Address Offset Message Control Reg High see also Figure 6 31 Upper Arbitration Reg Low Upper Arbitration Reg High Message Object n Message Object n j n 1 to F y Base Address 1 2 3 4 5 6 7 8 MCD02738 Figure 6 32 Message Object Address Map Semiconductor Group 6 75 1997 08 01 SIEMEN On Chip Peripheral Components 3 C505C Only Each element of the message control register is made of two complementary bits This special mechanism allows to selectively set or reset specific elements leaving others unchanged without requiring read modify write cycles None of these elements will be affected by reset Table 6 6 below shows how to use and interpret these 2 bit fields Table 6 6 Set Reset Bits Value of Function on Write Meaning on Read the 2 bit Field 0 0 reserved reserved 0 1 Reset element Element is reset 1 0 Set element Element is set 1 1 Leave element unchanged reserved CAN Message Control Register Low MCRO Address F7n0 Reset Value UUH CAN Message Control Register High MCR1 Address F7n1 4 Reset Value UUH Bit No MSB LSB 7 6 5 4 3 2 1 0 F7n0y MSGVAL TXIE RXIE INTPND MCRO rw rw rw rw 3 MSG
117. e A D converter Semiconductor Group 6 98 1997 08 01 SIEMENS On Chip Peripheral Components C505 C505C zac Bis Pans Peo T I or oe ADCONO 08 ADDAT ADST Single D94 DAy Continuous Mode Port 1 LSB Conversion Clock f Apc Conversion Clock Prescaler A D Converter Input Clock f inj nm o olrm us V AREF V AGND Start of conversion Internal Bus D Shaded Bit locations are not used in ADC functions Write to ADST MCB03298 Figure 6 42 Block Diagram of the A D Converter Semiconductor Group 6 99 1997 08 01 IE On Chip Peripheral Components SIEMENS C505 C505C 6 5 2 A D Converter Registers This section describes the bits functions of the registers which are used by the A D converter Special Function Register ADDAT Address D9j Reset Value 00H Bit No MSB LSB 7 6 5 4 3 2 1 0 D9y 7 6 5 4 3 2 1 0 ADDAT This register holds the result of the 8 bit conversion The most significant bit of the 8 bit conversion result is bit 7 and the least significant bit is bit 0 of the ADDAT register The data remains in ADDAT until it is overwritten by the next converted data ADDAT can be read or written under software control If the A D converter of the C505 is not used register ADDAT can be used as an add
118. e Cio 10 pF f 1 MHz Ta 25 C Overload current Tov 5 mA 89 Semiconductor Group 10 2 1997 08 01 SIEMENS Device Specifications C505 C505C Power Supply Current Parameter Symbol Limit Values Unit Test Condition typ 1 max Active Mode 16 MHz I c 26 TBD IMA Voc 5 V4 20 MHz Ic 32 TBD Idle Mode 16 MHz lcc 14 8 TBD MA Voc 5 V9 20 MHz loc 17 8 TBD Active Mode with 16 MHz cc TBD TBD MA Voc 5V 9 slow down enabled 20 MHz ec TBD TBD Idle Mode with 16 MHz Igc TBD TBD MA Voc 25V slow down enabled 20 MHz ec TBD TBD Power down current Ipp TBD TBD uA Voc 22 5 5 V9 1 Capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the Vo of ALE and port 3 The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1 to 0 transitions during bus operation In the worst case capacitive loading gt 100 pF the noise pulse on ALE line may exceed 0 8 V In such cases it may be desirable to qualify ALE with a schmitt trigger or use an address latch with a schmitt trigger strobe input u Capacitive loading on ports 0 and 2 may cause the Vo on ALE and PSEN to momentarily fall below the 0 9 Vcc specification when the address lines are stabilizing 3 Ipp power down mode is measured under following conditions EA Port0 Vss 3 RESET Voc j XTAL2 N C XTAL1 Vss j VAGND Vss y VAREF
119. e also combined with idle mode Power Down Mode If the C505C enters software Power Down Mode the system clock signal is turned off which will stop the operation of the CAN Module Any message transfer is interrupted In order to ensure that the CAN controller is not stopped while sending a dominant level 0 on the CAN bus the microcontroller should set bit INIT in the Control Register prior to entering Power Down Mode The microcontroller can check if a transmission is in progress by reading bits TXRQ and NEWDAT in the message objects and bit TXOK in the Control Register After returning from Power Down Mode the CAN Module has to be reconfigured Semiconductor Group 6 94 1997 08 01 On Chip Peripheral Components IE SIEMENS C505C Only 6 4 8 Configuration Examples of a Transmission Object The microcontroller wishes to configure an object for transmission It wants to allow automatic transmission in response to remote frames but does not wish to receive interrupts for this object Initialization The identifier and direction are set up Message Control Register Bit No MSB 7 6 3 2 1 0 MSGVAL TXIE RXIE INTPND 0 1 1 0 0 1 MCHR1 RMTPND TXRQ CPUUPD NEWDAT CPUUPD is initially set as the data bytes for the message have not yet been initialized Configuration after remote frame received Message Control Register Bit No MSB LSB 7 6 3 2 1 0 MSGVAL TXIE RXIE INTPND RMTPND
120. e for the CRC register The reason is that first the external interrupt input is controlled by the pin s level When the compare option is enabled the interrupt logic input is switched to the internal compare signal which carries a low level when no true comparison is detected So the interrupt logic sees a 1 to 0 edge and sets the interrupt request flag An unintentional generation of an interrupt during compare initialization can be prevented If the request flag is cleared by software after the compare is activated and before the external interrupt is enabled Semiconductor Group 6 39 1997 08 01 IE On Chip Peripheral Components SIEMENS C505 C505C 6 2 2 5 Capture Function Each of the compare capture registers CC1 to CC3 and the CRC register can be used to latch the current 16 bit value of the timer 2 registers TL2 and TH2 Two different modes are provided for this function In mode 0 an external event latches the timer 2 contents to a dedicated capture register In mode 1 a capture will occur upon writing to the low order byte of the dedicated 16 bit capture register This mode is provided to allow the software to read the timer 2 contents on the fly In mode O0 the external event causing a capture is for CC registers 1 to 3 a positive transition at pins CC1 to CC3 of port 1 forthe CRC register a positive or negative transition at the corresponding pin depending on the status of the bit IBFR in SFR T2CON If the edge
121. e sen aeesen hee e ee ete Ged ue 6 51 6 3 5 Details about MOOG T eee ER ee eee ae hee ES A CRACK REA ees 6 54 6 3 6 Details about Modes 2 and 3 sere quer ed oe Se ay daher e eee tnus 6 57 6 4 The On Chip CAN Controller lllillseleee ee 6 60 6 4 1 Basic CAN Controller Functions 2s Ret Ix eR ce pec oe poesi aed 6 61 Semiconductor Group I 2 1997 08 01 SIEMENS General Information C505 C505C Table of Contents Page 6 4 2 CAN Register Description liliis 6 65 64 21 General HBglsle S gegote sero etat geese NGC ead Bee aa EE RE Rd mad 6 65 6 4 2 2 The Message Object Registers Data Bytes llli es 6 75 6 4 3 Handling of Message Objects 00 cee eee 6 81 6 4 4 Initialization and Reset 2 ooo Dort bead he ee e teo gode Bed opt dun fce 6 88 6 4 5 Configuration of the Bit Timing dic ds eu sae sais etlecdie ted RR ay 6 90 6 4 5 1 Hard Synchronization and Resynchronization 00000 cece eee 6 92 6 4 5 2 Calculation of the Bit Time 2 6224 vu P RET ERRORI RUE ev ep ars 6 92 6 4 6 GAN Interrupt Handling ss ves mE REERPbURi 3 RE Ru na D VENE RU ER AS 6 93 6 4 7 CAN Controller in Power Saving Modes lsslleslelllselesss 6 94 6 4 8 Configuration Examples of a Transmission Object 000000000e 6 95 6 4 9 Configuration Examples of a Reception Object ssena aaaeeeaa 6 96 6 4 10 The CAN Application Interface llli 6 97 6 5 A D GOoIVOler aeos te kA RE
122. e system clock of the C505 There is a prescaler available which is software selectable and defines the input clock rate This prescaler is controlled by bit WDTPSEL in the SFR WDTREL Tabel 8 1 shows resulting timeout periods at fosc 12 and 16 MHz Special Function Register WDTREL Address 86j Reset Value 00H MSB LSB BitNo 7 6 5 4 3 2 1 0 86H en Reload Value WDTREL Bit Function WDTPSEL Watchdog timer prescaler select bit When set the watchdog timer is clocked through an additional divide by 16 prescaler WDTREL 6 0 Seven bit reload value for the high byte of the watchdog timer This value is loaded to WDTH when a refresh is triggered by a consecutive setting of bits WDT and SWDT Table 8 1 Watchdog Timer Time Out Periods WDTREL Time Out Period Comments fose 12 MHz fosc 16 MHz 00H 32 768 ms 24 576 ms This is the default value 80H 524 2 ms 393 2 ms Maximum time period 7Fy 256 us 192 us Minimum time period Semiconductor Group 8 2 1997 08 01 SIEMEN Fail Save Mechanisms S C505 C505C 8 1 2 Watchdog Timer Control Status Flags The watchdog timer is controlled by two control flags located in SFR IENO and IEN1 and one status flag located in SFR IPO Special Function Register IENO Address A814 Reset Value 00H Special Function Register IEN1 Address B8 Reset Value 00H Special Function Register IPO Address A9 Reset Value 00H MSB LSB
123. e to either 1 16 or 1 32 the oscillator frequency in mode 2 When bit SMOD in SFR PCON 871 is set the baud rate is fosc 16 In mode 3 the baud rate clock is generated by timer 1 which is incremented by a rate of fosc 6 or by the internal baud rate generator Figure 6 28 shows a functional diagram of the serial port in modes 2 and 3 The receive portion is exactly the same as in mode 1 The transmit portion differs from mode 1 only in the 9th bit of the transmit shift register The associated timings for transmit receive are illustrated in figure 6 29 Transmission is initiated by any instruction that uses SBUF as a destination register The Write to SBUF signal also loads TB8 into the 9th bit position of the transmit shift register and flags the TX control unit that a transmission is requested Transmission starts at the next rollover in the divide by 16 counter Thus the bit times are synchronized to the divide by 16 counter not to the Write to SBUF signal The transmission begins with activation of SEND which puts the start bit at TxD One bit time later DATA is activated which enables the output bit of the transmit shift register to TxD The first shift pulse occurs one bit time after that The first shift clocks a 1 the stop bit into the 9th bit position of the shift register Thereafter only zeroes are clocked in Thus as data bits shift out to the right zeroes are clocked in from the left When TB8 is at the output position o
124. e valid bit MSGVAL ie to define it as not valid Otherwise the whole message object has to be initialized After the initialization sequence has been completed the microcontroller clears the INIT bit Now the BSP synchronizes itself to the data transfer on the CAN bus by waiting for the occurrence of a sequence of 11 consecutive recessive bits ie bus idle before it can take part in bus activities and start message transfers Semiconductor Group 6 89 1997 08 01 SIEMEN On Chip Peripheral Components 3 C505C Only The initialization of the message objects is independent of the state of bit INIT and can be done on the fly the message objects should all be configured to particular identifiers or set to not valid before the BSP starts the message transfer however To change the configuration of a message object during normal operation the microcontroller first clears bit MSGVAL which defines it as not valid When the configuration is completed MSGVAL is set again Note that the busoff recovery sequence cannot be shortened by setting or resetting INIT If the device goes busoff it will set INIT of its own accord stopping all bus activities Once INIT has been cleared by the microcontroller the device will then wait for 129 occurrences of Bus Idle before resuming normal operation At the end of the busoff recovery sequence the error management counters will be reset During the waiting time after the resetting of INIT each time
125. eas 3 15 6 18 Mixed digital analog I O pins 6 11 Mi 3 15 6 18 Multifunctional digital I O pins 6 9 MOFGS tie ctp ER RE ud 3 14 3 18 6 80 Output input sample timing 6 12 IV PO uri eria 3 14 3 18 6 76 Semiconductor Group 11 3 1997 08 01 SIEMENS index C505 C505C Read modify write operation 6 14 Baudrate generation 6 46 Types and structures 6 1 with internal baud rate generator 6 48 Port O circuitry to Goce Bee Bt 6 5 with timer1 6 50 Port 1 3 4 circuitry ote 6 6 Multiprocessor communication 6 44 Port 2 circuitry aaan ence 6 7 Operating mode 0 6 51 to 6 53 Standard I O port circuitry 6 3 to 6 4 Operating mode 1 6 54 to 6 56 Power down mode Operating mode 2 and 3 6 57 to 6 59 by software 9 6 to 9 8 Registers scs xe eR RE REA 6 44 Power saving modes 9 1 to 9 8 SIES 2 teu Dee aeos dns 3 18 6 67 Control registers 9 1 to 9 2 3i Mg EE 3 18 6 71 Idle mode Lese 9 3 to 9 4 SM is Sak cin oad eae beat 3 15 6 45 Slow down mode 9 5 SM1 4 6 64 5 44 Sn Bie Ses DES 3 15 6 45 Software power down mode 9 6 to 9 8 SM2 eret ERES 3 15 6 45 Entry procedure 9 6 SMOD 22 iniu E uda 3 15 6 46 Exit wake up procedure 9 7 s Rit to aie hl Oat CREE 2 4 3 12 3 15 State of pins cers eerie ng 9 8 Special Function Registers 3 11 Pr
126. eds the error warning limit of 96 EWRN is reset if both error counters are less than the error warning limit Bit Timing Logic BTL This block monitors the busline input RXDC and handles the busline related bit timing according to the CAN protocol The BTL synchronizes on a recessive to dominant busline transition at Start of Frame hard synchronization and on any further recessive to dominant busline transition if the CAN controller itself does not transmit a dominant bit resynchronization The BTL also provides programmable time segments to compensate for the propagation delay time and for phase shifts and to define the position of the Sample Point in the bit time The programming of the BTL depends on the baudrate and on external physical delay times Semiconductor Group 6 63 1997 08 01 SIEMEN On Chip Peripheral Components 3 C505C Only Intelligent Memory The Intelligent Memory CAM RAM array provides storage for up to 15 message objects of maximum 8 data bytes length Each of these objects has a unique identifier and its own set of control and status bits After the initial configuration the Intelligent Memory can handle the reception and transmission of data without further microcontroller actions Organization of Registers and Message Objects All registers and message objects of the CAN controller are located in the CAN address area of 256 bytes which is mapped into the external data memory area of the C505C Semicon
127. ended RAM capacity and at the same time a fast access to this additional RAM because of the reduced code efficiency of these languages 4 6 2 How the eight Datapointers of the C505 are realized Simply adding more datapointers is not suitable because of the need to keep up 100 compatibility to the 8051 instruction set This instruction set however allows the handling of only one single 16 bit datapointer DPTR consisting of the two 8 bit SFRs DPH and DPL To meet both of the above requirements speed up external accesses 10096 compatibility to 8051 architecture the C505 contains a set of eight 16 bit registers from which the actual datapointer can be selected This means that the user s program may keep up to eight 16 bit addresses resident in these registers but only one register at a time is selected to be the datapointer Thus the datapointer in turn is accessed or selected via indirect addressing This indirect addressing is done through a special function register called DPSEL data pointer select register All instructions of the C505 which handle the datapointer therefore affect only one of the eight pointers which is addressed by DPSEL at that very moment Figure 4 3 illustrates the addressing mechanism a 3 bit field in register DPSEL points to the currently used DPTRx Any standard 8051 instruction e g MOVX DPTR A transfer a byte from accumulator to an external location addressed by DPTR now uses this activated DPTRx
128. entering the software power down mode A single A D conversion is started by writing to SFR ADST with dummy data A continuous conversion is started under the following conditions By setting bit ADM during a running single A D conversion By setting bit ADM when at least one A D conversion has occured after the last reset operation By writing ADST with dummy data after bit ADM has been set before if no A D conversion has occured after the last reset operation When bit ADM is reset by software in continuous conversion mode any ongoing A D conversion is stopped only after it is completed In any case the A D conversion is started with the next S1P1 Semiconductor Group 6 102 1997 08 01 SIEMENS On Chip Peripheral Components C505 C505C The A D converter interrupt is controlled by bits which are located in the SFRs IEN1 and IRCON Special Function Register IEN1 Address B84 Reset Value 00H Special Function Register IRCON Address CO Reset Value 00H MSB LSB BitNo BFy BE BD BC BBy BA B94 Bay B8 EXEN2 SWDT EX6 EX5 EX4 EX3 ECAN EADC IEN1 C7y C6H C5H C4y C3y C2y Cip COH COW EXF2 TF2 IEX6 IEX5 IEX4 IEX3 0 IADC IRCON Ez The shaded bits are not used for A D converter control Bit Function EADC Enable A D converter interrupt If EADC 0 the A D converter interrupt is disabled IADC A D converter interrup
129. er 0 interrupt is enabled EXO External interrupt O enable If EXO 0 the external interrupt 0 is disabled If EXO 1 the external interrupt 0 is disabled Semiconductor Group 7 5 1997 08 01 Interrupt System SIEMENS C505 C505C The IEN1 register contains enable disable flags of the timer 2 external timer reload interrupt the external interrupts 2 and 3 the CAN controller interrupt and the A D converter interrupt Special Function Register IEN1 Address B8 4 Reset Value 00H MSB LSB BitNo BFy BE BDy BCy BBy BA B94 Bay B8y EXEN2 SWDT EX6 EX5 EX4 EX3 ECAN EADC IEN1 Sj The shaded bits are not used for interrupt control Bit Function EXEN2 Timer 2 external reload interrupt enable If EXEN2 0 the timer 2 external reload interrupt is disabled If EXEN2 1 the timer 2 external reload interrupt is enabled The external reload function is not affected by EXEN2 EX6 External interrupt 6 capture compare interrupt 3 enable If EX6 0 external interrupt 6 is disabled If EX6 1 external interrupt 6 is enabled EX5 External interrupt 5 capture compare interrupt 2 enable If EX5 0 external interrupt 5 is disabled If EX5 1 external interrupt 5 is enabled EX4 External interrupt 4 capture compare interrupt 1 enable If EX4 0 external interrupt 4 is disabled If EX4 1 external interrupt 4 is enabled EX3 External interrupt 3 cap
130. er 1 Overflow ADCONO 7 BD Baud Rate Mode 3 Generator SRELH SRELL Baud Rate Clock f OSC Mode 2 Only one mode Mode 0 can be selected Note The switch configuration shows the reset state MCS02733 Figure 6 22 Baud Rate Generation for the Serial Port Depending on the programmed operating mode different paths are selected for the baud rate clock generation Figure 6 22 shows the dependencies of the serial port baud rate clock generation on the two control bits and from the mode which is selected in the special function register SCON 6 3 3 1 Baud Rate in Mode 0 The baud rate in mode 0 is fixed to oscillator frequency 6 Mode 0 baud rate 6 3 3 2 Baud Rate in Mode 2 The baud rate in mode 2 depends on the value of bit SMOD in special function register PCON If SMOD 0 which is the value after reset the baud rate is 1 32 of the oscillator frequency If SMOD 1 the baud rate is 1 16 of the oscillator frequency 2 SMOD Mode 2 baud rate ER x oscillator frequency Semiconductor Group 6 47 1997 08 01 SIEMENS On Chip Peripheral Components C505 C505C 6 3 3 3 Baud Rate in Mode 1 and 3 In these modes the baud rate is variable and can be generated alternatively by a baud rate generator or by timer 1 6 3 3 3 1 Using the Internal Baud Rate Generator In modes 1 and 3 the C505 can use an internal baud rate generator for the serial
131. er area Figure 3 1 illustrates the memory address spaces of the C505 Alternatively FFFF y a FFFF 4 Internal XRAM 256 KByte FF00 F7FF 4 Int CAN Exi Contr 256 Byte im F700 F6FF Indirect Addr 4000 H SFFF H Internal SE RAM Function Regs 80 Internal RAM 0000 0000 00 3 J N gk J Y Y Y Code Space Data Space internal Data Space C505C only MCD03288 Figure 3 1 C505 Memory Map Semiconductor Group 3 1 1997 08 01 SIEMEN Memory Organization S C505 C505C 3 1 Program Memory Code Space The C505 2R has 16 Kbytes of read only program memory which can be externally expanded up to 64 Kbytes If the EA pin is held high the C505 2R executes program code out of the internal ROM unless the program counter address exceeds 3FFFy Address locations 40004 through FFFFy are then fetched from the external program memory If the EA pin is held low the C505 fetches all instructions from the external program memory 3 2 Data Memory Data Space The data memory address space consists of an internal and an external memory space The internal data memory is divided into three physically separate and distinct blocks the lower 128 bytes of RAM the upper 128 bytes of RAM and the 128 byte special function register SFR area While the upper 128 bytes of data memory and the SFR area share the same address locations they are accessed through different addressing modes The lowe
132. er down mode wake up interrupt Detailed description of the wake up from software power down mode is given in section 9 4 2 Fast Internal Reset after Power On The C505 can use the oscillator watchdog unit for a fast internal reset procedure after power on Normally the members of the 8051 family e g SAB 80C52 do not enter their default reset state before the on chip oscillator starts The reason is that the external reset signal must be internally synchronized and processed in order to bring the device into the correct reset state Especially if a crystal is used the start up time of the oscillator is relatively long typ 1 ms During this time period the pins have an undefined state which could have severe effects e g to actuators connected to port pins In the C505 the oscillator watchdog unit avoids this situation After power on the oscillator watchdog s RC oscillator starts working within a very short start up time typ less than 2 microseconds Then the watchdog circuitry detects a failure condition for the on chip oscillator because this has not yet started a failure is always recognized if the watchdog s RC oscillator runs faster than the on chip oscillator As long as this condition is valid the watchdog uses the RC oscillator output as clock source for the chip This allows correct resetting of the part and brings all ports to the defined state see also chapter 5 of this manual Semiconductor Group 8 8 1997 08 01 IE Power Sa
133. eral Components SIEMENS C505 C505C Reload of Timer 2 The reload mode for timer 2 is selected by bits T2RO and T2R1 in SFR T2CON Figure 6 14 shows the configuration of timer 2 in reload mode Mode 0 When timer 2 rolls over from all l s to all 0 s it not only sets TF2 but also causes the timer 2 registers to be loaded with the 16 bit value in the CRC registers which are preset by software The reload will happen in the same machine cycle in which TF2 is set thus overwriting the count value 0000 Mode 1 A 16 bit reload from the CRC register is caused by a negative transition at the corresponding input pin P1 5 AN5 T2EX In addition this transition will set flag EXF2 if bit EXEN2 in SFR IEN1 is set If the timer 2 interrupt is enabled setting EXF2 will generate an interrupt The external input pin T2EX is sampled in every machine cycle When the sampling shows a high in one cycle and a low in the next cycle a transition will be recognized The reload of timer 2 registers will then take place in the cycle following the one in which the transition was detected Timer 2 Interrupt Request MCS01903 Figure 6 14 Timer 2 in Reload Mode Semiconductor Group 6 31 1997 08 01 SIEMENS On Chip Peripheral Components C505 C505C 6 2 2 3 Compare Function of Registers CRC CC1 to CC3 The compare function of a timer register combination can be described as follows The 16 bit value stored in a compare capt
134. ers Functional Blocks cont d Block Symbol Name Address Contents after Reset Serial ADCONO A D Converter Control Register 0 D8g 00X00000g Channel PCON Power Control Register 87H 00H SBUF Serial Channel Buffer Register 99H XXH SCON Serial Channel Control Register 98H 00H SRELL Serial Channel Reload Register low byte AAH D9u SRELH Serial Channel Reload Register high byte BAH XXXXXX11p Timer 0 TCON Timer 0 1 Control Register 88H 00H Timer 1 THO Timer 0 High Byte 8CH 00H TH1 Timer 1 High Byte 8DH 00H TLO Timer 0 Low Byte 8AH 00H TL1 Timer 1 Low Byte 8BH 00H TMOD Timer Mode Register 89H 00H Compare CCEN Comp Capture Enable Reg 00H Capture CCH1 Comp Capture Reg 1 High Byte 00H Unit CCH2 Comp Capture Reg 2 High Byte 00H Timer 2 CCH3 Comp Capture Reg 3 High Byte 00H CCL1 Comp Capture Reg 1 Low Byte 00H CCL2 Comp Capture Reg 2 Low Byte 00H CCL3 Comp Capture Reg 3 Low Byte 00H CRCH Reload Register High Byte 00H CRCL Reload Register Low Byte 00H TH2 Timer 2 High Byte 00H TL2 Timer 2 Low Byte 00H T2CON Timer 2 Control Register 00X00000p IENO 2 Interrupt Enable Register 0 00H IEN1 2 Interrupt Enable Register 1 00H Watchdog WDTREL Watchdog Timer Reload Register 86H 00H IENO 9 Interrupt Enable Register 0 A8 00H IEN1 2 Interrupt Enable Register 1 B8y 00H IPO 2 Interrupt Priority Register 0 A9H 00H Power PCON Power Control Register 87H 00H Save PCON1 Po
135. ers of Port 1 to 4 have internal pullup FET s see figure 6 2 Each I O line can be used independently as an input or output To be used as an input the port bit stored in the bit latch must contain a one 1 that means for figure 6 2 Q 0 which turns off the output driver FET n1 Then for ports 1 to 4 the pin is pulled high by the internal pullups but can be pulled low by an external source When externally pulled low the port pins source current Z or For this reason these ports are called quasi bidirectional Read Latch Vec Internal Pull Up Arrangement Int Bus Pin MCS01823 Read Pin Figure 6 2 Basic Output Driver Circuit of Ports 1 to 4 Semiconductor Group 6 4 1997 08 01 IE On Chip Peripheral Components SIEMENS C505 C505C 6 1 2 1 Port 0 Circuitry Port 0 in contrast to ports 1 to 4 is considered as true bidirectional because the port 0 pins float when configured as inputs Thus this port differs in not having internal pullups The pullup FET in the PO output driver see figure 6 3 is used only when the port is emitting 1 s during the external memory accesses Otherwise the pullup is always off Consequently PO lines that are used as output port lines are open drain lines Writing a 1 to the port latch leaves both output FETs off and the pin floats In that condition it can be used as high impedance input If port O is configured as general I O port and has
136. et timer 2 interrupt enabled EXF2 1 will cause an interrupt EXF2 can be used as an additional external interrupt when the reload function is not used EXF2 must be cleared by software TF2 Timer 2 overflow flag Set by a timer 2 overflow and must be cleared by software If the timer 2 interrupt is enabled TF2 1 will cause an interrupt Semiconductor Group 6 28 1997 08 01 SIEMENS On Chip Peripheral Components C505 C505C Special Function Register CCEN Address C14 Reset Value 00H Bit No MSB LSB 7 6 5 4 3 2 1 0 Ci COCAH3 COCAL3 COCAH2 COCAL2 COCAH1 COCAL1 COCAHO COCALO CCEN Bit Function COCAHS Compare capture mode for CC register 3 COCAL3 COCAH3 COCAL3 Function 0 0 Compare capture disabled 0 1 Capture on rising edge at pin P1 3 AN3 INT6 CC3 1 0 Compare enabled 1 1 Capture on write operation into register CCL3 COCAH2 Compare capture mode for CC register 2 eee COCAH2 COCAL2 Function 0 0 Compare capture disabled 0 1 Capture on rising edge at pin P1 2 AN2 INT5 CC2 1 0 Compare enabled 1 1 Capture on write operation into register CCL2 COCAH 1 Compare capture mode for CC register 1 S COCAH1 COCAL1 Function 0 0 Compare capture disabled 0 1 Capture on rising edge at pin P1 1 AN1 INT4 CC1 1 0 Compare enabled 1 1 Capture on write operation into register CCL1 C
137. etting the bit SD in SFR PCON If the slow down mode is enabled the clock signals for the CPU and the peripheral units are reduced to 1 32 of the nominal system clock rate The controller actually enters the slow down mode after a short synchronization period max two machine cycles The slow down mode is terminated by clearing bit SD The slow down mode can be combined with the idle mode by performing the following double instruction sequence ORL PCON 00000001B preparing idle mode set bit IDLE IDLS not set ORL PCON 00110000B entering idle mode combined with the slow down mode IDLS and SD set There are two ways to terminate the combined Idle and Slow Down Mode The idle mode can be terminated by activation of any enabled interrupt The CPU operation is resumed the interrupt will be serviced and the next instruction to be executed after the RETI instruction will be the one following the instruction that had set the bits IDLS and SD Nevertheless the slow down mode keeps enabled and if required has to be terminated by clearing the bit SD in the corresponding interrupt service routine or at any point in the program where the user no longer requires the slow down mode power saving The other possibility of terminating the combined idle and slow down mode is a hardware reset Since the oscillator is still running the hardware reset has to be held active for only two machine cycles for a complete reset Semiconductor Group
138. evel is sampled at least once before it changes it must be held for at least one full machine cycle 6 2 1 Timer Counter 0 and 1 Timer counter 0 and 1 of the C505 are fully compatible with timer counter 0 and 1 of the C501 and can be used in the same four operating modes Mode 0 8 bit timer counter with a divide by 32 prescaler Mode 1 16 bit timer counter Mode 2 8 bit timer counter with 8 bit auto reload Mode 3 Timer counter 0 is configured as one 8 bit timer counter and one 8 bit timer Timer counter 1 in this mode holds its count The effect is the same as setting TR1 0 External inputs INTO and INT1 can be programmed to function as a gate for timer counters 0 and 1 to facilitate pulse width measurements Each timer consists of two 8 bit registers THO and TLO for timer counter 0 TH1 and TL1 for timer counter 1 which may be combined to one timer configuration depending on the mode that is established The functions of the timers are controlled by two special function registers TCON and TMOD In the following descriptions the symbols THO and TLO are used to specify the high byte and the low byte of timer O TH1 and TL1 for timer 1 respectively The operating modes are described and shown for timer O If not explicity noted this applies also to timer 1 Semiconductor Group 6 15 1997 08 01 SIEMENS On Chip Peripheral Components C505 C505C 6 2 1 1 Time
139. f bit EXEN is set Since the external interrupt pins INT4 INT5 and INT6 are sampled once in each machine cycle an input high or low should be held for at least 6 oscillator periods to ensure sampling If the external interrupt is transition activated the external source has to hold the request pin low for at least one cycle and then hold it high for at least one cycle to ensure that the transition is recognized so that the corresponding interrupt request flag will be set see figure 7 5 The external interrupt request flags will automatically be cleared by the CPU when the service routine is called a Level Activated Interrupt P3 x INTX Low Level Threshold gt 1 Machine Cycle b Transition Activated Interrupt High Level Threshold e g P3 x INTx Low Level Threshold lt 4 gt gt 1 Machine Cycle gt 1 Machine Cycle MGT01921 Transition to be detected Figure 7 5 External Interrupt Detection Semiconductor Group 7 16 1997 08 01 IE Interrupt System SIEMENS C505 C505C 7 5 Interrupt Response Time If an external interrupt is recognized its corresponding request flag is set at S5P2 in every machine cycle The value is not polled by the circuitry until the next machine cycle If the request is active and conditions are right for it to be acknowledged a hardware subroutine call to the requested service routine will be the next instruction to be executed The call itself takes two cycles
140. f the shift register then the stop bit is just to the left of TB8 and all positions to the left of that contain zeroes This condition flags the TX control unit to do one last shift and then deactivate SEND and set TI This occurs at the 11th divide by 16 rollover after Write to SBUF Reception is initiated by a detected 1 to 0 transition at RxD For this purpose RxD is sampled at a rate of 16 times whatever baud rate has been established When a transition is detected the divide by 16 counter is immediately reset and 1FFy is written to the input shift register At the 7th 8th and 9th counter states of each bit time the bit detector samples the value of RxD The value accepted is the value that was seen in at least 2 of the 3 samples If the value accepted during the first bit time is not O the receive circuits are reset and the unit goes back to looking for another 1 to O transition If the start bit proves valid it is shifted into the input shift register and reception of the rest of the frame will proceed As data bit come from the right 1s shift out to the left When the start bit arrives at the leftmost position in the shift register which in modes 2 and 3 is a 9 bit register it flags the RX control block to do one last shift load SBUF and RB8 and to set RI The signal to load SBUF and RB8 and to set RI will be generated if and only if the following conditions are met at the time the final shift pulse is generated 1 RI 0
141. forms extensive data manipulation and is comprised of the arithmetic logic unit ALU an A register B register and PSW register The ALU accepts 8 bit data words from one or two sources and generates an 8 bit result under the control of the instruction decoder The ALU performs the arithmetic operations add substract multiply divide increment decrement BDC decimal add adjust and compare and the logic operations AND OR Exclusive OR complement and rotate right left or swap nibble left four Also included is a Boolean processor performing the bit operations as set clear complement jump if set jump if not set jump if set and clear and move to from carry Between any addressable bit or its complement and the carry flag it can perform the bit operations of logical AND or logical OR with the result returned to the carry flag The program control section controls the sequence in which the instructions stored in program memory are executed The 16 bit program counter PC holds the address of the next instruction to be executed The conditional branch logic enables internal and external events to the processor to cause a change in the program execution sequence Additionally to the CPU functionality of the C501 8051 standard microcontroller the C505 contains 8 datapointers For complex applications with peripherals located in the external data memory space e g CAN controller or extended data storage capacity this turned out to be a
142. from the respective fields of the Bit Timing Register and the bit CMOD in the SYSCON register bit 3 Semiconductor Group 6 91 1997 08 01 SIEMENS On Chip Peripheral Components C505C Only 6 4 5 1 Hard Synchronization and Resynchronization To compensate phase shifts between clock oscillators of different CAN controllers any CAN controller has to synchronize on any edge from recessive to dominant bus level if the edge lies between a sample point and the next synchronization segment and on any other edge if it itself does not send a dominant level If the hard synchronization is enabled at the start of frame the bit time is restarted at the synchronization segment otherwise the resynchronization jump width SJW defines the maximum number of time quanta a bit time may be shortened or lengthened by one resynchronization The current bit time is adjusted by tsyw SIW 1 Xt Note SJW is the programmed numerical value from the respective field of the bit timing register 6 4 5 2 Calculation of the Bit Time The programming of the bit time according to the CAN specification depends on the desired baudrate the CLP microcontroller system clock rate and on the external physical delay times of the bus driver of the bus line and of the input comparator These delay times are summarised in the propagation time segment tp op where tProp is two times the maximum of the sum of physical bus delay the input comparator delay and the output dr
143. g normal operation The control signals ALE and PSEN are held at logic high levels As in normal operation mode the ports can be used as inputs during idle mode Thus a capture or reload operation can be triggered the timers can be used to count external events and external interrupts will be detected The idle mode is a useful feature which makes it possible to freeze the processor s status either for a predefined time or until an external event reverts the controller to normal operation as discussed below The watchdog timer is the only peripheral which is automatically stopped during idle mode Semiconductor Group 9 3 1997 08 01 IE Power Saving Modes 2 ii ex C505 C505C The idle mode is entered by two consecutive instructions The first instruction sets the flag bit IDLE PCON O and must not set bit IDLS PCON 5 the following instruction sets the start bit IDLS PCON 5 and must not set bit IDLE PCON 0 The hardware ensures that a concurrent setting of both bits IDLE and IDLS does not initiate the idle mode Bits IDLE and IDLS will automatically be cleared after being set If one of these register bits is read the value that appears is 0 This double instruction is implemented to minimize the chance of an unintentional entering of the idle mode which would leave the watchdog timer s task of system protection without effect Note PCON is not a bit addressable register so the above mentioned sequence for entering the
144. gement Port 2 in I O function works similar to the Type B port driver circuitry section 6 1 3 1 whereas in address output function it works similar to Port O circuitry Semiconductor Group 6 8 1997 08 01 IE On Chip Peripheral Components SIEMENS C505 C505C 6 1 3 Detailed Output Driver Circuitry In fact the pullups mentioned before and included in figure 6 2 6 4 and 6 5 are pullup arrangements The differences of the port types available in the C505 are described in the next sections 6 1 3 1 Type B Port Driver Circuitry Figure 6 6 shows the output driver circuit of the type B multifunctional digital I O port lines The basic circuitry of these ports is shown in figure 6 4 The pullup arrangement of type B port lines has one n channel pulldown FET and three pullup FETs Delay 1 State Voc A e pi 4 p2 4 p3 e e o iu Q gt j Y Vss Input Data zi zi Read Pin MCS03230 Figure 6 6 Driver Circuit of Type B Port Pins The pulldown FET n1 is of n channel type It is a very strong driver transistor which is capable of sinking high currents o it is only activated if a 0 is programmed to the port pin A short circuit to Vc must be avoided if the transistor is turned on since the high current might destroy the FET This also means that no 0 must be programmed into the latch of a pin that is used as input The pullup
145. gisters 1 to 3 The two capture modes can be established individually for each capture register by bits in SFR CCEN compare capture enable register That means in contrast to the compare modes it is possible to simultaneously select mode 0 for one capture register and mode 1 for another register Semiconductor Group 6 40 1997 08 01 On Chip Peripheral Components SIEMENS C505 C505C Input Clock Timer 2 TF2 Interrupt Request a Write to T Iv gt n Capture P1 0 INT 3 CCO D Cw Mode 0 _ oS ied CON6 E External ra IEXS Interrupt 3 Request MCS01909 Figure 6 21 Timer 2 Capture with Register CRC Semiconductor Group 6 41 1997 08 01 SIEMENS On Chip Peripheral Components C505 C505C Input Timer 2 TF2 Interrupt oes Request Write to CCL1 v Mode 1 Mode 0 P1 1 INT 4 External cci gt A i IEX4 Interrupt 4 Request MCS01910 Figure 6 21a Timer 2 Capture with Registers CC1 to CC3 Semiconductor Group 6 42 1997 08 01 IE On Chip Peripheral Components SIEMENS C505 C505C 6 3 Serial Interface The serial port of the C505 is full duplex meaning it can transmit and receive simultaneously It is also receive buffered meaning it can commence reception of a second byte before a previously received byte has been read from the receive register however if the first byte still hasn t been read by t
146. haracteristics in the Data Sheet of the C505 or in chapter 10 of this User s Manual The corresponding parameters are Vo and Vou The same applies to port O output buffers They do however require external pullups to drive floating inputs except when being used as the address data bus When used as inputs it must be noted that the ports 1 to 4 are not floating but have internal pullup transistors The driving devices must be capable of sinking a sufficient current if a logic low level shall be applied to the port pin the parameters J and J in the DC characteristics specify these currents Port O as well as port 1 programmed to analog input function however have floating inputs when used for digital input Semiconductor Group 6 13 1997 08 01 IE On Chip Peripheral Components SIEMENS C505 C505C 6 1 6 Read Modify Write Feature of Ports 0 to 4 Some port reading instructions read the latch and others read the pin The instructions reading the latch rather than the pin read a value possibly change it and then rewrite it to the latch These are called read modify write instructions which are listed in table 6 3 If the destination is a port ora port pin these instructions read the latch rather than the pin Note that all other instructions which can be used to read a port exclusively read the port pin In any case reading from latch or pin resp is performed by reading the SFR PO P2 and P3 for example MOV A P3 reads the
147. he C505 provides 12 interrupt vectors with four priority levels Five interrupt requests can be generated by the on chip peripherals timer 0 timer 1 timer 2 serial interface A D converter One interrupt can be generated by the CAN controller C505C only or by a software setting and in this case the interrupt vector is the same Six interrupts may be triggered externally P3 2 INTO P3 3 INT1 P1 0 ANO INT3 CCO P1 1 AN1 INT4 CC1 P1 2 AN2 INT5 CC2 P1 3 AN3 INT6 CC3 Additionally the P1 5 AN5 T2EX can trigger an interrupt The wake up from power down mode interrupt has a special functionality which allows to exit from the software power down mode by a short low pulse at either pin P3 2 INTO or the pin P4 1 RXDC please refer to chapter 9 for further details The four external interrupts INT3 INT4 INT5 and INT6 can also be generated by the timer 2 in capture compare mode This chapter shows the interrupt structure the interrupt vectors and the interrupt related special function registers Figure 7 1 to 7 3 give a general overview of the interrupt sources and illustrate the request and the control flags which are described in the next sections Semiconductor Group 7 1 1997 08 01 SIEMENS Interrupt System C505 C505C P32 INTO TCON 0 A D Converter IADC Le IRCON O IEN1 0 DON TO TCON5 ETO IENO 1 SWI IRCON 1 P Status Le IEN1 1 CAN Controller Interrupt Sources Bit addressable
148. he time reception of the second byte is complete one of the bytes will be lost The serial port receive and transmit registers are both accessed at special function register SBUF Writing to SBUF loads the transmit register and reading SBUF accesses a physically separate receive register The serial port can operate in 4 modes one synchronous mode three asynchronous modes The baud rate clock for the serial port is derived from the oscillator frequency mode 0 2 or generated either by timer 1 or by a dedicated baud rate generator mode 1 3 Mode 0 Shift Register Synchronous Mode Serial data enters and exits through RxD TxD outputs the shift clock 8 data bits are transmitted received LSB first The baud rate is fixed at 1 6 of the oscillator frequency See section 6 3 4 for more detailed information Mode 1 8 Bit USART Variable Baud Rate 10 bits are transmitted through TxD or received through RxD a start bit 0 8 data bits LSB first and a stop bit 1 On receive the stop bit goes into RB8 in special function register SCON The baud rate is variable See section 6 3 5 for more detailed information Mode 2 9 Bit USART Fixed Baud Rate 11 bits are transmitted through TxD or received through RxD a start bit 0 8 data bits LSB first a programmable 9th bit and a stop bit 1 On transmit the 9th data bit TB8 in SCON can be assigned to the value of 0 or 1 Or for example the parity bit P in the PS
149. heral Components SIEMENS C505 C505C 6 2 1 5 Mode 3 Mode 3 has different effects on timer O and timer 1 Timer 1 in mode 3 simply holds its count The effect is the same as setting TR1 0 Timer 0 in mode 3 establishes TLO and THO as two seperate counters The logic for mode 3 on timer 0 is shown in figure 6 12 TLO uses the timer 0 control bits C T Gate TRO INTO and TFO THO is locked into a timer function counting machine cycles and takes over the use of TR1 and TF1 from timer 1 Thus THO now controls the timer 1 interrupt Mode 3 is provided for applications requiring an extra 8 bit timer or counter When timer 0 is in mode 3 timer 1 can be turned on and off by switching it out of and into its own mode 3 or can still be used by the serial channel as a baud rate generator or in fact in any application not requiring an interrupt from timer 1 itself f sc l6 OSC n p 2C e Timer Clock E e TLO i 8 Bits TFO Interrupt C T 1 P3 4 T0 o Control Gate O 21 P3 2 NTO o 2 THO 8 Bits TF1 Interrupt TR1 MCS02729 Figure 6 12 Timer Counter 0 Mode 3 Two 8 Bit Timers Counters Semiconductor Group 6 22 1997 08 01 IE On Chip Peripheral Components SIEMENS C505 C505C 6 2 2 Timer Counter 2 with Additional Compare Capture Reload The timer 2 with additional compare capture reload features is one of the most powerful peripheral units of the C505 It can be used f
150. hip oscillator and forces the microcontroller into reset state in case the on chip oscillator fails it also provides the clock for a fast internal reset after power on 8 1 Programmable Watchdog Timer To protect the system against software upset the user s program has to clear this watchdog within a previously programmed time period If the software fails to do this periodical refresh of the watchdog timer an internal hardware reset will be initiated The software can be designed so that the watchdog times out if the program does not work properly It also times out if a software error is based on hardware related problems The watchdog timer in the C505 is a 15 bit timer which is incremented by a count rate of fosc 12 upto fosc 192 The machine clock of the C505 is divided by two prescalers a divide by two and a divide by 16 prescaler For programming of the watchdog timer overflow rate the upper 7 bits of the watchdog timer can be written Figure 8 1 shows the block diagram of the watchdog timer unit WDT Reset Request IPO A94 owswos j f External HW Reset WDTPSEL WDTREL 864 Control Logic MCB03306 Figure 8 1 Block Diagram of the Programmable Watchdog Timer Semiconductor Group 8 1 1997 08 01 IE Fail Save Mechanisms ii bx C505 C505C 8 1 1 Input Clock Selection The input clock rate of the watchdog timer is derived from th
151. ibed as well as the actions that have to be taken by the microcontroller i e the servicing program Semiconductor Group 6 81 1997 08 01 IE On Chip Peripheral Components SIEMENS C505C Only TXRQ 1 CPUUPD 0 received remote frame with same identifier as this message object NEWDAT 1 load message into buffer TXRQ 1 RMTPND 1 transmission successful 9 Yes Yes INTPND 1 RMTPND 1 No Yes Yes Yes INTPND 1 MCD02739 Figure 6 33 CAN Controller Handling of Message Objects with Direction transmit Semiconductor Group 6 82 1997 08 01 SIEMEN On Chip Peripheral Components 3 C505C Only received frame with same identifier as this message object NEWDAT 0 load identifier and control into buffer transmission store message cates NEWDAT 1 TXRQ 0 RMTPND 0 TXRQ 0 RMTPND 0 Yes No INTPND 1 Yes INTPND 1 MCD02740 Figure 6 34 CAN Controller Handling of Message Objects with Direction receive Semiconductor Group 6 83 1997 08 01 SIEMENS On Chip Peripheral Components C505C Only Power Up Initialization Update Start Update Update End all bits undefined TXIE application specific RXIE application specific INTPND 0 RMTPND 0 TXRQ 0 CPUUPD 1 Identifier application specific NEWDAT 0 Direction transmit DLC application specific
152. ic level low for fail and high for pass during the time when the following 16 bytes are checked In ROM verification mode 2 the C505 must be provided with a system clock at the XTAL pins Figure 4 6 shows an application example of an external circuitry which allows to verify a protected ROM inside the C505 2R in ROM verification mode 2 With RESET going inactive the C505 2R starts the ROM verify sequence Its ALE is clocking a 14 bit address counter This counter generates the addresses for an external EPROM which is programmed with the contents of the internal protected ROM The verify detect logic typically displays the pass fail information of the verify operation P3 5 can be latched with the falling edge of ALE When the last byte of the internal ROM has been handled the C505 2R starts generating a PSEN signal This signal or the CY signal of the address counter indicate to the verify detect logic the end of the internal ROM verification Address Counter C505 2R Campare Code ROM MCS03290 Figure 4 6 ROM Verification Mode 2 External Circuitry Example Semiconductor Group 4 12 1997 08 01 IEMEN External Bus Interface S S C505 C505C 4 8 Version Registers Version registers are typically used for adapting the programming firmware to specific device characteristics such as ROM OTP size etc Three version registers are implemented in the C505 They can be read during nor
153. ics 16 MHz for C505 Voc 5 V 10 1596 Vss 0 V T 0 to 70 C for the SAB C505 T 40 to 85 C for the SAF C505 C for port 0 ALE and PSEN outputs 100 pF C for all other outputs 80 pF Program Memory Characteristics Parameter Symbol Limit Values Unit 16 MHz clock Variable Clock Duty Cycle 1 CLP 2 MHz to 0 4 to 0 6 16 MHz min max min max ALE pulse width fi 48 CLP 15 ns Address setup to ALE AVLL 10 TCLumin 15 ns Address hold after ALE fix 10 TCLumin 15 ns ALE to valid instruction in tow 15 2 CLP 50 ns PSEN pulse width pi ph 73 CLP ns TCLymin 15 PSEN to valid instruction in tery 38 CLP ns TCLymin 50 Input instruction hold after PSEN pxix 0 0 ns Input instruction float after PSEN tpxiz 15 TCL min 10 ns Address valid after PSEN lpxav 20 TCLimin 5 ns Address to valid instruction in tavy 95 2 CLP ns TCLumin 55 Address float to PSEN AZPL 5 5 ns Interfacing the C505 to devices with float times up to 20 ns is permissible This limited bus contention will not cause any damage to port 0 drivers Semiconductor Group 10 6 1997 08 01 SIEMENS Device Specifications C505 C505C AC Characteristics 16 MHz for C505 cont d External Data Memory Characte
154. in 40 x tin 6 4xt N Figure 6 44 A D Conversion Timing Semiconductor Group 6 105 1997 08 01 IE On Chip Peripheral Components SIEMENS C505 C505C Sample Time ts During this time the internal capacitor array is connected to the selected analog input channel and is loaded with the analog input voltage to be converted The analog voltage is internally fed to a voltage comparator With the beginning of the sample phase the BSY bit in SFR ADCONO is set Conversion Time tco During the conversion time the analog voltage is converted into an 8 bit digital value using the successive approximation technique with a binary weighted capacitor network At the end of the conversion time the BSY bit is reset and the IADC bit in SFR IRCON is set indicating an A D converter interrupt condition Write Result Time twp At the result phase the conversion result is written into the ADDAT registers Figure 6 43 shows how an A D conversion is embedded into the microcontroller cycle scheme using the relation 6 x tiv 1 instruction cycle It also shows the behaviour of the busy flag BSY and the interrupt flag IADC during an A D conversion Write Result Cycle MOV ADST 0 1 Instruction Cycle MOV A ADDAT Sh gres MU Start of A D Start of next conversion conversion cycle in continuous mode tapcc d a x K 4 E LL LL A D Conversion Cycle Write
155. ing reset an internal capacitor is charged So the reset state is a disabled XRAM and CAN controller Because of the charge time of the capacitor XMAPO bit once written to O that is discharging the capacitor cannot be set to 1 again by software On the other hand any distortion software hang up noise is not able to charge this capacitor too That is the stable status is XRAM and CAN controller enabled The clear instruction for the XMAPO bit should be integrated in the program initialization routine before XRAM or CAN controller is used In extremely noisy systems the user may have redundant clear instructions Note The CAN controller peripheral exists in the C505C only Semiconductor Group 3 4 1997 08 01 SIEMEN Memory Organization S C505 C505C 3 4 2 Accesses to XRAM using the DPTR 16 bit Addressing Mode The XRAM and CAN controller can be accessed by two read write instructions which use the 16 bit DPTR for indirect addressing These instructions are MOVX A DPTR_ Read MOVX DPTR A_ Write For accessing the XRAM the effective address stored in DPTR must be in the range of FFOOW to FFFFy For accessing the CAN controller the effective address stored in DPTR must be in the range of F700 to F7FFy 3 4 3 Accesses to XRAM using the Registers RO R1 8 bit Addressing Mode The 8051 architecture provides also instructions for accesses to external data memory range which use only an 8 bit address indi
156. ion SRELH 0 1 Baudrate generator reload high value Upper two bits of the baudrate timer reload value SRELL 0 7 Baudrate generator reload low value Lower 8 bits of the baudrate timer reload value Reserved bits for future use Read by CPU returns undefined values After reset SRELH and SRELL have a reload value of 3D9 4 With this reload value the baud rate generator has an overflow rate of input clock 39 With a 6 MHz oscillator frequency the commonly used baud rates 4800 baud SMOD 0 and 9600 baud SMOD 1 are available with 0 16 96 deviation With the baud rate generator as clock source for the serial port in mode 1 and 3 the baud rate of can be determined as follows 25V x oscillator frequency Mode 1 3 baud rate 32 x baud rate generator overflow rate Baud rate generator overflow rate 21 SREL with SREL SRELH 1 0 SRELL 7 0 Semiconductor Group 6 49 1997 08 01 SIEMENS On Chip Peripheral Components C505 C505C 6 3 3 3 2 Using Timer 1 to Generate Baud Rates In mode 1 and 3 of the serial port also timer 1 can be used for generating baud rates Then the baud rate is determined by the timer 1 overflow rate and the value of SMOD as follows SMOD Mode 1 3 baud rate 32 x timer 1 overflow rate The timer 1 interrupt is usually disabled in this application Timer 1 itself can be configured for either timer or counter operation and in any of its operating mode
157. ion to indicate an odd even number of one bits in the accumulator i e even parity B Register The B register is used during multiply and divide and serves as both source and destination For other instructions it can be treated as another scratch pad register Stack Pointer The stack pointer SP register is 8 bits wide It is incremented before data is stored during PUSH and CALL executions and decremented after data is popped during a POP and RET RETI execution i e it always points to the last valid stack byte While the stack may reside anywhere in the on chip RAM the stack pointer is initialized to 074 after a reset This causes the stack to begin a location 084 above register bank zero The SP can be read or written under software control Semiconductor Group 2 4 1997 08 01 SIEMENS Fundamental Structure C505 C505C 2 2 CPU Timing The C505 has no clock prescaler Therefore a machine cycle of the C505 consists of 6 states 6 oscillator periods Each state is devided into a phase 1 half and a phase 2 half Thus a machine Cycle consists of 6 oscillator periods numbererd S1P1 state 1 phase 1 through S6P2 state 6 phase 2 Each state lasts one oscillator period Typically arithmetic and logic operations take place during phase 1 and internal register to register transfers take place during phase 2 The diagrams in figure 2 2 show the fetch execute timing related to the internal states and phases Since these
158. ites the selection in ADCON 0 1 when ADCON 0 is written after ADCONO 1 The analog inputs are selected according to the following table MX2 MX1 MXO Selected Analog Input P1 0 ANO INT3 CCO P1 1 AN1 INTA CC1 P1 2 AN2 INT5 CC2 P1 3 AN3 INT6 CC3 P1 4 ANA P1 5 AN5 T2EX P1 6 AN6 CLKOUT P1 7 AN7 T2 OOOO OOo OO O 0 0 Qo0o Semiconductor Group 6 101 1997 08 01 SIEMENS On Chip Peripheral Components C505 C505C Bit Function ADCL1 A D converter clock prescaler selection ADCLO ADCL1 and ADCLO select the prescaler ratio for the A D conversion clock fapc Depending on the clock rate fosc of the C505 fapc must be adjusted in a way that the resulting conversion clock fapc is less than or equal to 1 25 MHz see section 6 5 3 The prescaler ratio is selected according to the following table ADCL1 ADCLO Prescaler Ratio 0 0 divide by 4 0 1 divide by 8 default after reset 1 0 divide by 16 1 1 divide by 32 Reserved bits for future use Read by CPU returns undefined values Note Generally before entering the software power down mode an A D conversion in progress must be stopped If a single A D conversion is running it must be terminated by polling the BSY bit or waiting for the A D conversion interrupt In continuous conversion mode bit ADM must be cleared and the last A D conversion must be terminated before
159. ith Additional Compare Capture Reload 6 23 62 271 Hmer2 Registers receten yu E ey HOR Hed PE PP uu veda 6 25 pe 209 mer Operation sts Locate dieu eo ete dte aUe Rabia ML c tend 6 30 6 2 2 3 Compare Function of Registers CRC CC1 to CC3 1 eee 6 32 6 2 2 3 1 Compare Mode Osco tect ee qu Fd Bs fae 8 anon wits et dee eines Sodan wean tee qu ats 6 32 6 2 2 3 2 Modulation Range in Compare Mode 0 0 00 e eee eee ee 6 34 p 223 dv GOMpare MOOOG eo fae es ey tea ep ERO Ese qua dcr Dire eed 6 36 6 2 2 4 Using Interrupts in Combination with the Compare Function 6 38 p22 9 Capt re FUNCTION k anrs Tineta oed dar er etr ose adem OR to te o M ad 6 40 6 3 Seri INTE ACE 6x cetus ctus Bic at eor Do nte ad s se fh esed Etro pus Eos 6 43 6 3 1 Multiprocessor Communication 0000 ccs 6 44 6 3 2 Serial Port Registers 59 x atr oe tg e Ds aaa E SRM rp rep ee erat 6 44 6 3 3 Baud hate Gerneratlori 20 vartecedver tea bicdes tne rede Wer PR ERE dS 6 46 p 3 3 1 Baud Rale ir MOOB D vexoiukee e AEEUCCEARATTSISRAREE ee tose RE ME SO es 6 47 6 3 3 2 Baud Rate in Mode 2 x suy i204 E RERWA ERE PCC EE CREE ERUEREC CERES AE 6 47 6 3 3 3 Baud Rate in Mode 1 and 3 ioo rec ER bp bb be pb E DERE eri 6 48 6 3 3 3 1 Using the Internal Baud Rate Generator 00 0c eee eee 6 48 6 3 3 3 2 Using Timer 1 to Generate Baud Rates 00 00 cee ees 6 50 6 3 4 Details about Mode D pv veg ad ade deg ee
160. itional general purpose register Special Function Register ADST Address DA Reset Value XX Bit No MSB LSB 7 6 5 4 3 2 1 0 DAH ADST This is the A D conversion start register Any write operation on the ADST register starts a new conversion process irrespective of the actual data written to this register Read by the CPU returns unefined values Semiconductor Group 6 100 1997 08 01 SIEMENS On Chip Peripheral Components C505 C505C Special Function Register ADCONO Address D8 Reset Value 00X00000p Special Function Register ADCON1 Address DC Reset Value 01XXX000p BitNo MSB LSB 7 6 5 4 3 2 1 0 D84 BD CLK BSY ADM MX2 MX1 MXO ADCONO DCH ADCL1 ADCLO MX2 MX1 MXO ADCON1 ni The shaded bits are not used for A D converter control Bit Function BSY Busy flag This flag indicates whether a conversion is in progress BSY 1 The flag is set by hardware during an A D conversion and cleared when the conversion is completed ADM A D conversion mode When set a continuous A D conversion is selected If cleared during a running A D conversion the conversion is stopped after current conversion process is completed MX2 MXO A D converter input channel select bits Bits MX2 0 can be written or read either in ADCONO or ADCON1 The channel selection done by writing to ADCON 1 0 overwr
161. ive b RD WR active b RD WR b RD WR active b RD WR active address inactive inactive range c XRAM CAN is c XRAM CAN is c ex memory c XRAM CAN is c XRAM CAN is c ext memory used used is used used used is used af MOVX XPAGE a PO Bus a PO Bus a PO Bus a PO Bus a PO Bus a PO Bus EH Ri P2 1 O P2 1 O P2 1 O P2 1 O P2 1 O P2 1 O XRAM CAN b RD WR active b RD WR active b RD WR active b RD WR active b RD WR active b RD WR active addr page c ext memory is c ext memory is c ext memory is c ext memory is c ext memory is c ext memory is range used used used used used used XPAGE a PO Bus a PO Bus a PO Bus a P0 P2 gt 1 O a POBus a PO Bus gt RD WR Data RD WR Data P2 1 O RD WR Data P2 1 O XRAM CAN P2 gt 1 O P2 1 O P2 1 O addr page b RD WR b RD WR active b RD WR active b RD WR b RD WR active b RD WR active range inactive inactive c XRAM CAN is c XRAM CAN is c ext memory is c XRAM CAN is c XRAM CAN is c ext memory is used used used used used used EN modes compatible to 8051 C501 family D Table 3 1 Behaviour of P0 P2 and RD WR During MOVX Accesses f Co o SN3IWIS uoneziuebDa4o Aowa 9S0S9 S099 SIEMEN Memory Organization S C505 C505C 3 5 Special Function Registers The registers except the program counter and the four general purpose register banks reside in the special function register area The special function register area c
162. ively 2 During the sample time the input capacitance Cay must be charged discharged by the external source The internal resistance of the analog source must allow the capacitance to reach their final voltage level within te After the end of the sample time ts changes of the analog input voltage have no effect on the conversion result amp This parameter includes the sample time tg the time for determining the digital result Values for the conversion clock tapc depend on programming and can be taken from the table on the previous page 4 TUE max is tested at 40 lt TA lt 125 C Voc 5 5 V VAREF lt Voc 0 1 V and Vas lt VAGND It is guaranteed by design characterization for all other voltages within the defined voltage range If an overload condition occurs on maximum 2 unused analog input pins and the absolute sum of input overload currents on all analog input pins does not exceed 10 mA an additional conversion error of 1 2 LSB is permissible g During the conversion the ADC s capacitance must be repeatedly charged or discharged The internal resistance of the reference source must allow the capacitance to reach their final voltage level within the indicated time The maximum internal resistance results from the programmed conversion timing 6 Not 100 tested but guaranteed by design characterization Semiconductor Group 10 5 1997 08 01 SIEMENS Device Specifications C505 C505C 10 4 AC Characterist
163. iver delay rounded up to the nearest multiple of tg To fulfill the requirements of the CAN specification the following conditions must be met ttseg2 2 3 X tg Information Processing Time ttseg2 2 tsuw trgegi 2 4 X tq ttseg1 2 tsuw tprop Note In order to achieve correct operation according to the CAN protocol the total bit time should be at least 8 tg i e ttsegi tTseg2 7 tg So to operate with a baudrate of 1 MBit sec the CLP frequency has to be at least 8 MHz with bit CMOD 1 The maximum tolerance for CLP depends on the phase buffer segment1 PB1 the phase buffer segment2 PB2 and the resynchronization jump width SJW min PB1 PB2 df lt 2 x 13 x bittime PB2 AND t df LL 20 x bit time Semiconductor Group 6 92 1997 08 01 SIEMEN On Chip Peripheral Components 3 C505C Only 6 4 6 CAN Interrupt Handling The CAN controller has one interrupt output which is connected with the interrupt controller unit in the C505C This interrupt can be enabled disabled using bit ECAN of SFR IEN1 further details about interrupt vector priority etc see chapter 7 Additionally three bits in the CAN control register F701 4 are used to enable specific interrupt sources for interrupt generation Since an interrupt request of the CAN Module can be generated due to different conditions the appropriate CAN interrupt status register must be read in the service routine to determine the cause
164. ject while NEWDAT was still set ie the previously stored message is lost CPUUPD CPU update this bit applies to transmit objects only Indicates that the corresponding message object may not be transmitted now The microcontroller sets this bit in order to inhibit the transmission of a message that is currently updated or to control the automatic response to remote requests NEWDAT New data Indicates if new data has been written into the data portion of this message object by microcontroller transmit objects or CAN controller receive objects since this bit was last reset or not 1 In message object 15 last message these bits are hardwired to 0 inactive in order to prevent transmission of message 15 2 When the CAN controller writes new data into the message object unused message bytes will be overwritten by non specified values Usually the microcontroller will clear this bit before working on the data and verify that the bit is still cleared once it has finished working to ensure that it has worked on a consistent set of data and not part of an old message and part of the new message For transmit objects the microcontroller will set this bit along with clearing bit CPUUPD This will ensure that if the message is actually being transmitted during the time the message was being updated by the microcontroller the CAN controller will not reset bit TXRQ In this way bit TXRQ is only reset once the
165. l 3 highest Reserved bits for future use Read by CPU returns undefined values Semiconductor Group 7 12 1997 08 01 SIEMENS Interrupt System C505 C505C 7 2 Interrupt Priority Level Structure The following table shows the interrupt grouping of the C505 interrupt sources Table 7 1 Interrupt Source Structure Interrupt Associated Interrupts Priority Group High priority gt Low priority 1 External interrupt 0 A D converter interrupt High 2 Timer 0 overflow CAN controller interrupt C505C Software Interrupt IRCON 1 3 External interrupt 1 External interrupt 3 4 Timer 1 overflow External interrupt 4 5 Serial channel interrupt External interrupt 5 6 Timer 2 interrupt External interrupt 6 Low Each pair of interrupt sources can be programmed individually to one of four priority levels by setting or clearing one bit in the special function register IPO and one in IP1 A low priority interrupt can be interrupted by a high priority interrupt but not by another interrupt of the same or a lower priority An interrupt of the highest priority level cannot be interrupted by another interrupt source If two or more requests of different priority levels are received simultaneously the request of the highest priority is serviced first If requests of the same priority level are received simultaneously an internal polling sequence determines which request is to be serviced first Thus
166. low P0 0 P0 7 37 30 VO PortO is an 8 bit open drain bidirectional I O port Port O pins that have 1 s written to them float and in that state can be used as high impendance inputs Port 0 is also the multiplexed low order address and data bus during accesses to external program or data memory In this application it uses strong internal pullup transistors when issuing 1 s Port 0 also outputs the code bytes during program verification in the C505C 2R External pullup resistors are required during program verification VAREF 38 Reference voltage for the A D converter VAGND 39 Reference ground for the A D converter Vss 16 5 Ground 0V Vec 17 Power Supply 5 V Input O Output Semiconductor Group 1 9 1997 08 01 IE Fundamental Structure ii zh gt C505 C505C 2 Fundamental Structure The C505 is fully compatible to the architecture of the standard 8051 C501 microcontroller family While maintaining all architectural and operational characteristics of the C501 the C505 incorporates a CPU with 8 datapointers an 8 bit A D converter a 4 channel capture compare unit a Full CAN controller unit C505C only an XRAM data memory as well as some enhancements in the Fail Save Mechanism Unit Figure 2 1 shows a block diagram of the C505 Semiconductor Group 2 1 1997 08 01
167. ls to clear the watchdog timer an internal reset will be initiated The reset cause external reset or reset caused by the watchdog can be examined by software status flag WDTS in IPO is set A refresh of the watchdog timer is done by setting bits WDT SFR IENO and SWDT consecutively This double instruction sequence has been implemented to increase system security It must be noted however that the watchdog timer is halted during the idle mode and power down mode of the processor see section Power Saving Modes It is not possible to use the idle mode in combination with the watchdog timer function Therefore even the watchdog timer cannot reset the device when one of the power saving modes has been entered accidentally Semiconductor Group 8 4 1997 08 01 SIEMENS Fail Save Mechanisms C505 C505C 8 1 4 Refreshing the Watchdog Timer At the same time the watchdog timer is started the 7 bit register WDTH is preset by the contents of WDTREL O to WDTREL 6 Once started the watchdog cannot be stopped by software but can only be refreshed to the reload value by first setting bit WDT IENO 6 and by the next instruction setting SWDT IEN1 6 Bit WDT will automatically be cleared during the second machine cycle after having been set For this reason setting SWDT bit has to be a one cycle instruction e g SETB SWDT This double instruction refresh of the watchdog timer is implemented to minimize the chance of an unintentional reset of the
168. ly applied reference voltage range has to be held on a fixed value within the DC specifications chapter 10 The main functional blocks of the A D converter are shown in Figure 6 42 6 5 1 A D Converter Operation An internal start of an A D conversion is triggered by a write to ADST instruction The start procedure itself is independent of the value which is written to the ADST register When single conversion mode is selected bit ADM 0 only one A D conversion is performed In continuous mode bit ADM 1 after completion of one A D conversion a new A D conversion is triggered automatically until the bit ADM ADCONO 3 is reset The busy flag BSY ADCONO 4 is automatically set when an A D conversion is in progress After completion of the conversion it is reset by hardware This flag is read only and a write has no effect The interrupt request flag IADC IRCON 0 is set when an A D conversion is completed The bits MXO to MX2 of special function register ADCONO are used for selection of the analog input channel The bits MXO to MX2 are represented in the register ADCON1 as well but in reality are present only once Therefore there are two methods of selecting an anlog input channel If a new channel is selected in ADCON1 the change is automatically done in the corresponding bits MXO to MX2 in ADCONO and vice versa The ADCON1 register is also used for selecting the required prescaler bits 6 and 7 for achieving the proper clock input to th
169. mal program execution mode as mapped SFRs when the bit RMAP in SFR SYSCON is set The first step of the C505 will contain the following information in the version registers Version register 2 will be incremented with each new step of the C505 Contents of Version registers Name Address C505 2R Version Register 0 FCH C5H Version Register 1 FDH 054 Version Register 2 FEH 01H Semiconductor Group 4 13 1997 08 01 IE System Reset SIEMENS C505 C505C 5 System Reset 5 1 Hardware Reset Operation The hardware reset function incorporated in the C505 allows for an easy automatic start up at a minimum of additional hardware and forces the controller to a predefined default state The hardware reset function can also be used during normal operation in order to restart the device This is particularly done when the power down mode is to be terminated Additional to the hardware reset which is applied externally to the C505 there are two internal reset sources the watchdog timer and the oscillator watchdog This chapter deals only with the external hardware reset The reset input is an active high input An internal Schmitt trigger is used at the input for noise rejection Since the reset is synchronized internally the RESET pin must be held high for at least two machine cycles 12 oscillator periods while the oscillator is running With the oscillator running the internal reset is executed during the second machine
170. mapped SFR and can be only accessed if bit RMAP in SFR SYSCON is set Semiconductor Group 6 1 1997 08 01 SIEMENS On Chip Peripheral Components C505 C505C As already mentioned port 1 3 and 4 are provided for multiple alternate functions These functions are listed in table 6 2 Table 6 2 Alternate Functions of Port 1 3 and 4 Port Second third Port Function Function Type P1 0 ANO INT3 C Analog input channel 0 External Interrupt 3 input CCO Capture compare 0 input output P1 1 AN1 INTA4 C Analog input channel 1 External Interrupt 4 input CC1 Capture compare 1 input output P1 2 AN2 INT5 C Analog input channel 2 External Interrupt 5 input CC2 Capture compare 2 input output P1 3 ANS INT6 C Analog input channel 3 External Interrupt 6 input CC3 Capture compare 3 input output P1 4 AN4 C Analog input channel 4 P1 5 AN5 T2EX C Analog input channel 5 Timer 2 external reload trigger input P1 6 AN6 CLKOUT C Analog input channel 6 System clock output P1 7 AN7 T2 C Analog input channel 7 Timer 2 external count input P3 0 RxD B Serial port s receiver data input asynchronous or data input output synchronous P3 1 TxD B Serial port s transmitter data output asynchronous or data clock output synchronous P3 2 INTO B External interrupt 0 input timer 0 gate control P3 3 INTT B External interrupt 1 input timer 1 gate control P3 4 TO B Timer 0 external counter input P3 5 T1 B Timer 1
171. me sen P veg 10 18 11 i qe PTT 11 1 Semiconductor Group 4 1997 08 01 SIEMENS Introduction C505 C505C 1 Introduction The C505 microcontroller is a member of the Siemens C500 family of 8 bit microcontrollers The C505 is fully compatible to the standard 8051 microcontroller Additionally the C505 provides extended power save provisions on chip RAM 16K of on chip program memory and RFI related improvements The C505 does not have an internal clock prescaler and with a maximum external clock rate of 20 MHz it achieves a 300 ns instruction cycle time The C505 2R operates with internal and or external program memory The C505 L is identical to the C505 2R except that it lacks the on chip porgram memory The C505C 2R and C505C L are identical to the C505 2R and the C505 L respectively except that they have in addition the full CAN interface Therefore the term C505 refers to all the above four versions within this documentation unless otherwise noted Figure 1 1 shows the different functional units of the C505 and Figure 1 2 shows the simplified logic symbol of the C505 Oscillator Watchdog 1 0 So 8 Bit ADC 8 Analog Inputs SZ 8 Digit O es Timer 2 ui CPU S10 2 amp V Ful CAN E E Controller 8 Datapointers 1 0 Watchdog Timer 16k x 8 Port 4 O 2 Bit O Port C505C only MCB03283 Figure 1 1 C505 Functional Units Semiconductor Group 1 1 1997 08
172. mode 1 as shown in figure 4 4 is used to read out the contents of the ROM The AC timing characteristics of the ROM verification mode is shown in the AC specifications chapter 10 P2 0 P2 5 Inputs PSEN P2 6 P2 7 Vas ALE EA Vy RESET V Port 0 Data OUT MCD02626 Figure 4 4 ROM Verification Mode 1 ROM verification mode 1 is selected if the inouts PSEN ALE EA and RESET are put to the specified logic level Then the 14 bit address of the internal ROM byte to be read is applied to the port 1 and port 2 lines After a delay time port 0 outputs the content of the addressed ROM cell In ROM verification mode 1 the C505 must be provided with a system clock at the XTAL pins and pullup resistors on the port 0 lines Semiconductor Group 4 10 1997 08 01 IEMEN External Bus Interface S S C505 C505C 4 7 2 Protected ROM Mode If the ROM is protected the ROM verification mode 2 as shown in figure 4 5 is used to verify the contents of the ROM The detailed timing characteristics of the ROM verification mode is shown in the AC specifications chapter 10 RESET ET 1 ALE pulse after reset iE ALE X x ie Latch Latch Latch Latch Port 0 Data for Adar 0 X Date for Data for Addr x 16X Data for Adar P3 5 Low Verify Error High Verify ok Inputs ALE Veg PSEN EA Vi RESET MCT03289 T 6 CLP Figure 4 5 ROM Verific
173. n Idle Power Down ALE High Low High Low PSEN High Low High Low PORT 0 Data Data Float Float PORT 2 Data Data Address Data PORT 1 3 4 Data Data Data Data alternate outputs last output alternate outputs last output Semiconductor Group 9 8 1997 08 01 SIEMENS Device Specifications C505 C505C 10 Device Specifications 10 1 Absolute Maximum Ratings Ambient temperature under bias T4 cccceeeeeeeeeeeeeeneeeeeeeeeeeeeeeaeeeeeeeeeeneeee 40 C to 125 C Storage temperature Ter iieri e ee eee o a me e dies eee n 65 C to 150 C Voltage on Vec pins with respect to ground Vas eseseeeeeenene 0 5V to 6 5 V Voltage on any pin with respect to ground Viag seseseeeeeeeeeese 0 5Vto Voc 0 5 V Input current on any pin during overload condition eeeesssssss 10 mA to 10 mA Absolute sum of all input currents during overload condition 100 mA Power diSsIpaltion i e e tete R a Must nde M n qu E TBD Note Stresses above those listed under Absolute Maximum Ratings may cause permanent damage of the device This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for longer periods may affect device reliability During overl
174. n be 1 1 2 x 100 This means that a variation of the duty cycle from 0 to real 10096 can never be reached if the compare register and timer register have the same length There is always a spike which is as long as the timer clock period This spike may either appear when the compare register is set to the reload value limiting the lower end of the modulation range or it may occur at the end of a timer period In a timer 2 CCx register configuration in compare mode 0 this spike is divided into two halves one at the beginning when the contents of the compare register is equal to the reload value of the timer the other half when the compare register is equal to the maximum value of the timer register here FFFF Please refer to figure 6 18 where the maximum and minimum duty cycle of a compare output signal are illustrated Timer 2 is incremented with the machine clock fosc 6 thus at 20 MHz operational frequency these spikes are both approx 150 ns long Semiconductor Group 6 34 1997 08 01 IE On Chip Peripheral Components SIEMENS C505 C505C a CCHx CCLx 0000 or CRCH CRCL maximum duty cycle P1 x H Appr 1 2 Machine Cycle b CCHx CCLx FFFF y minimum duty cycle Appr 1 2 Machine Cycle Pix E H MCT01907 Figure 6 18 Modulation Range of a PWM Signal generated with a Timer 2 CCx Register Combination in Compare Mode 0 The following example shows how to calculate the modulation r
175. nd Port 2 The behaviour of port 0 and port 2 during a MOVX access depends on the control bits in register SYSCON and on the state of pin EA The table 3 1 lists the various operating conditions It shows the following characteristics a Use of PO and P2 pins during the MOVX access Bus The pins work as external address data bus If internal XRAM CAN controller is accessed the data written to the XRAM CAN controller can be seen on the bus in debug mode I 0 The pins work as Input Output lines under control of their latch b Activation of the RD and WR pin during the access C Use of internal XRAM CAN controller or external XDATA memory The shaded areas describe the standard operation as each C5xx device without on chip XRAM CAN controller behaves Semiconductor Group 3 9 1997 08 01 o EA 0 EA 1 XMAP1 XMAPO XMAP1 XMAPO o 00 10 x1 00 10 x1 c S MOVX DPTR a PO P2Bus a PO P2Bus a PO P2Bus a P0 P2 Bus a PO P2Bus a PO P2Bus O DPTR lt b RD WR active b RD WR active b RD WR active b RD WR active b RD WR active b RD WR active o XRAM CAN c ext memory is c ext memory is c ext memory is c ext memory is c ext memory is c ext memory is 5 address used used used used used used range DPTR a PO P2Bus a P0 P2 gt Bus a P0O P2 gt Bus a PO P2 l O a P0 P2 gt Bus a P0 P2 Bus gt RD WR Data RD WR Data RD WR Data XRAM CAN b RD WR b RD WR act
176. ng message determines if the standard 11 bit mask in global mask short is to be used or the 29 bit extended mask in global mask long Bits holding a 0 mean don t care ie do not compare the message s identifier in the respective bit position The last message object 15 has an additional individually programmable acceptance mask mask of last message for the complete arbitration field This allows classes of messages to be received in this object by masking some bits of the identifier Note The mask of last message is ANDed with the global mask that corresponds to the incoming message CAN Global Mask Short Register Low GMSO Address F706j Reset Value UUH CAN Global Mask Short Register High GMS1 Address F707 4 Reset Value UUU11111p Bit No MSB LSB 7 6 5 4 3 2 1 0 F706 ID28 21 GMSO rw F707y ID20 18 1 1 1 1 1 GMS1 rw r r r r r Bit Function ID28 18 Identifier 11 bit Mask to filter incoming messages with standard identifier Semiconductor Group 6 72 1997 08 01 SIEMENS On Chip Peripheral Components C505C Only CAN Upper Global Mask Long Register Low UGMLO Addr F708j Reset Value UUH CAN Upper Global Mask Long Register High UGML1 Addr F709 Reset Value UUH CAN Lower Global Mask Long Register Low LGMLO Addr F70A 4 Reset Value UUH CAN Lower Global Mask Long Register High LGML1 Addr F70Bjj Reset Val UU
177. o its nominal operating level 9 4 1 Invoking Software Power Down Mode The software power down mode is entered by two consecutive instructions The first instruction has to set the flag bit PDE PCON 1 and must not set bit PDS PCON 6 the following instruction has to set the start bit PDS PCON 6 and must not set bit PDE PCON 1 The hardware ensures that a concurrent setting of both bits PDE and PDS does not initiate the power down mode Bits PDE and PDS will automatically be cleared after having been set and the value shown by reading one of these bits is always 0 This double instruction is implemented to minimize the chance of unintentionally entering the power down mode which could possibly freeze the chip s activity in an undesired status PCON is not a bit addressable register so the above mentioned sequence for entering the power down mode is obtained by byte handling instructions as shown in the following example ORL PCON 00000010B set bit PDE bit PDS must not be set ORL PCON 01000000B set bit PDS bit PDE must not be set enter power down The instruction that sets bit PDS is the last instruction executed before going into power down mode When the double instruction sequence shown above is used the power down mode can only be left by a reset operation If the external wake up from power down capability has also to be used its function must be enabled using the following instruction sequence prior to executing the double
178. o tee bed Soe wep ieee ie yee wba yee ee ed eee Steet 6 1 6 1 1 POR SIHOIBIBS 252 Sei en Meee coe Pee eee eenee es Seta sae eae M 6 1 6 1 2 Standard O Port Circuitry eon vp ex xac e aoe Baie EE 6 3 6 1217 Tort OCCU scuto n e Debes Dot oo erue zou dep ins debout de E dos 6 5 6 1 2 2 Port 1 Port 3 and Port 4 Circuitry v use x Les x REDIERE EXE EE RR Rx 6 6 53 29 Part 2S IFGUlT by eost da a Roa aine e eurn ge etras es Made di a ni 6 7 6 1 3 Detailed Output Driver Circuitry liliis 6 9 6 1 3 1 Type B Port Driver Circuitry visse sexe RUAEPIDG Ra wee UP ee CE ERU ea ae ds 6 9 6 1 3 2 Type C Port Driver Circuitry gt itae a ox der Ra PERDER NIU nonae ees 6 11 6 1 4 FORE FMIN osiea on 2 Er MAE oft Sie M LK c p I I E n E PE irs 6 12 6 1 5 Port Loading and Interfacing ur soo eint Aah ONES eec ER Der oe etd bs 6 13 6 1 6 Read Modify Write Feature of Ports Oto 4 0 0 eee 6 14 6 2 Timers COUhlels 95 feta etw ex tu ELDER tite Eexdibute t be es 6 15 6 2 1 Tire Gounter D sid T ous uen ettet e GU ed pre GU Cor UC e han TR eR 6 15 6 2 1 1 Timer Gounter 0 and 1 Begislers s sese ev URERIATRX RD ERE ee RESP 6 16 6 212 JMOGBUU ise oS ite 3s apatite ot re et dr diia aede aua De get spp 6 19 Beles Mode 2s tot usen Se chaste DEC LAM EIUL LIE NE I EC NECEM s 6 20 6214 MOS 3 25 0 Sid b ep DIR eee ek a adi mie iR he Rl E eif dci ted data 6 21 6215 MOUGUS Lava ee Sito d EE GER DUE YU GVLETRQQGSULIIS RESI eeu es 6 22 6 2 2 Timer Counter 2 w
179. oad conditions Vi gt Vcc or V lt Vss the Voltage on Vcc pins with respect to ground Vas must not exceed the values defined by the absolute maximum ratings Semiconductor Group 10 1 1997 08 01 SIEMENS Device Specifications C505 C505C 10 2 DC Characteristics Voc 5V 10 15 Vss 0 V T4 0 to 70 C T 40 to 85 C T 40 to 110 C T 40 to 125 C for the SAB C505 for the SAF C505 for the SAH C505 for the SAK C505 Parameter Symbol Limit Values Unit Test Condition min max Input low voltages all except EA RESET Vi 0 5 0 2 Vo 0 1 V EA pin Vi 0 5 0 2 Vec 0 3 V RESET pin Vio 0 5 0 2 Vec 0 1 V Input high voltages all except XTAL1 RESET Vin 0 2 Voc 0 9 Voc 0 5 V XTAL1 pin Vini 0 7 Voc Voc 4 0 5 V RESET pin Vino 0 6 Voc Voc 4 0 5 V Output low voltages Ports 1 2 3 4 Vor 0 45 V Ig 1 6 mA Port 0 ALE PSEN Vout 0 45 V Ig 2 3 2 mA Output high voltages Ports 1 2 3 4 Vou 2 4 V Toy 80 uA 0 9 Voc V Tow 10 uA Port 0 in external bus mode Vonoe 2 4 V Tou 800 uA ALE PSEN 0 9 Voc V Toy 80 uA 2 Logic 0 input current Ports 1 2 3 4 I 10 70 uA Vi 0 45 V Logical O to 1 transition current Mu 65 650 uA Vy 2V Ports 1 2 3 4 Input leakage current Port 0 ANO 7 Port 1 EA T 1 uA 0 45 lt Vy lt Vec Pin capacitanc
180. oad register high byte compare capture functions CRCH is the 8 bit high byte of the 16 bit reload register of timer 2 It is also used for Semiconductor Group 6 27 1997 08 01 SIEMENS On Chip Peripheral Components C505 C505C Special Function Register IENO Address A814 Reset Value 00H Special Function Register IEN1 Address B8pj Reset Value 00H Special Function Register IRCON Address CO Reset Value 00H MSB LSB Bit No AFy AEQ ADu ACy ABY AAW A9 A8y A84 EAL WDT ET2 ES ET1 EX1 ETO EXO IENO Bit No BFy BE BD BCy BBy BA B94 B8 B8y EXEN2 SWDT EX6 EX5 EX4 EX3 ECAN EADC IEN1 Bit No C74 C64 C5y C4y C34 C24 Ciy C0H4 COW EXF2 TF2 IEX6 IEXS IEX4 IEX3 SWI IADC IRCON The shaded bits are not used in timer counter 2 interrupt control Bit Function ET2 Timer 2 overflow external reload interrupt enable If ET2 0 the timer 2 interrupt is disabled If ET2 1 the timer 2 interrupt is enabled EXEN2 Timer 2 external reload interrupt enable If EXEN2 0 the timer 2 external reload interrupt is disabled If EXEN2 1 the timer 2 external reload interrupt is enabled The external reload function is not affected by EXEN2 EXF2 Timer 2 external reload flag EXF2 is set when a reload is caused by a falling edge on pin T2EX while EXEN2 1 If ET2 in IENO is s
181. on Semiconductor Group 2 5 1997 08 01 SIEMENS Fundamental Structure C505 C505C Er S3 ei S6 Pb S3 ies 96 p P2IP1 P2IPT P2 P P2 P1 P2 P1 P2 5 P21PT P2 P1 P2 P P2 P1 P2IP1 P2 OSC em LT ET ET ET ET ET ET ET ET ET ET L ALE Read Read Next Read Next Opcode Opcode Discard Opcode Again HOOGE a 1 Byte 1 Cycle Instruction e g INC A Read Read 2nd Read Next Opcode Byte Opcode sTsIsTsTs Ts b 2 Byte 1 Cycle Instruction e g ADD A DATA Read Read Next Opcode Discard Read Next Opcode Opcode Again sTIsT9T TsIS s Ts T9 Ts Ts T9 c 1 Byte 2 Cycle Instruction e g INC ii Read Read Next Read Next Opcode Again Opcode Opcode No Fetch MOVX Discard No Fetch No ALE On STgTSTSTSISTSISISISISIS ij Movx 1 Byte 2 Cycle ADDR DATA Access of External Memory MCD03287 Figure 2 2 Fetch Execute Sequence Semiconductor Group 2 6 1997 08 01 SIEMEN Memory Organization S C505 C505C 3 Memory Organization The C505 CPU manipulates operands in the following four address spaces up to 64 Kbytes of program memory 16K on chip program memory for C505 2R up to 64 Kbytes of external data memory 256 bytes of internal data memory 256 bytes of internal XRAM data memory 256 bytes CAN controller registers data memory C505C only a 128 byte special function regist
182. on Register SYSCON Address B1 Reset Value XX100X01p Bit No MSB LSB 7 6 5 4 3 2 1 0 Bly EALE RMAP CMOD XMAP1XMAPO SYSCON The functions of the shaded bits are not described here Bit Function CMOD Prescaler selection for CAN controller Control bit for CAN controller input clock selection The time quantum t of the CAN controller timing is affected by this and hecne the baudrate CMOD 0 The 2 prescaler is enabled reset value CMOD 1 The 2 prescaler is disabled This bit must be cleared when fosc is over 10 MHz The software Initialization is enabled by setting bit INIT in the control register This can be done by the microcontroller via software or automatically by the CAN controller on a hardware reset or if the EML switches to busoff state While INIT is set all message transfer from and to the CAN bus is stopped the CAN bus output TXDC is 1 recessive the control bits NEWDAT and RMTPND of the last message object are reset the counters of the EML are left unchanged Setting bit CCE in addition allows to change the configuration in the bit timing register For initialization of the CAN Controller the following actions are required configure the bit timing register CCE required set the Global Mask Registers initialize each message object If a message object is not needed it is sufficient to clear its messag
183. only for two oscillator periods Semiconductor Group 4 1 1997 08 01 SIEMENS External Bus Interface C505 C505C a One Machine Cycle lt One Machine Cycle gt s1 s2 s3 s4 s5 se st s2 s3 s4 s5 se ALE PSEN t A RD without MOVX OUT OUT OUT OUT OUT Po ANN Hoor AN Ait A N Ais A N i A 8 PCL OUT PCL OUT PCL OUT PCL OUT valid valid valid valid b One Machine Cycle 39 One Machine Cycle gt s1 s2 s3 s4 s5 se s1 S2 s3 s4 5 se ALE PSEN ecc db Emo vi Bn wi n MOVX P2 PCH PCH DPH OUT OR PCH OUT OUT P2 OUT OUT DATA Po N Houn e Qi A A A PCL OUT DPL or Ri PCL OUT valid valid valid MCD02575 Figure 4 1 External Program Memory Execution Semiconductor Group 4 2 1997 08 01 SIEMENS External Bus Interface C505 C505C 4 1 2 Timing The timing of the external bus interface in particular the relationship between the control signals ALE PSEN RD WR and information on port 0 and port 2 is illustated in figure 4 1 a and b Data memory in a write cycle the data byte to be written appears on port 0 just before WR is activated and remains there until after WR is deactivated In a read cycle the incoming byte is accepted at port O before the read strobe is deactivated Program memory
184. onsists of two portions the standard special function register area and the mapped special function register area One special function register of the C505 PCON1 is located in the mapped special function register area For accessing the mapped special function register area bit RMAP in special function register SYSCON must be set All other special function registers are located in the standard special function register area which is accessed when RMAP is cleared 0 The registers and data locations of the CAN controller CAN SFRs are located in the external data memory area at addresses F700 to F7FFy Details about the access of these registers is described in section 3 4 1 of this chapter Special Function Register SYSCON Address B1 Reset Value XX100X01p Bit No MSB LSB 7 6 5 4 3 2 1 0 BiH x EALE RMAP CMOD IXMAP1 XMAPO SYSCON The functions of the shaded bits are not described here Bit Function RMAP Special function register map bit RMAP 0 The access to the non mapped standard special function register area is enabled RMAP 1 The access to the mapped special function register area is enabled Reserved bits for future use Read by CPU returns undefined values As long as bit RMAP is set mapped special function register area can be accessed This bit is not cleared by hardware automatically Thus wnen non mapped mapped registers are to be acces
185. or all kinds of digital signal generation and event capturing like pulse generation pulse width modulation pulse width measuring etc Timer 2 is designed to support various automotive control applications as well as industrial applications frequency generation digital to analog conversion process control Please note that the functionality of this timer is not equivalent to timer 2 of the C501 The C505 timer 2 in combination with the compare capture reload registers allows the following operating modes Compare upto4 PWM output signals with 65535 steps at maximum and 300 ns resolution Capture upto 4 high speed capture inputs with 300 ns resolution Reload modulation of timer 2 cycle time The block diagram in figure 6 13 shows the general configuration of timer 2 with the additional compare capture reload registers The I O pins which can be used for timer 2 control are located as multifunctional port functions at port 1 see table 6 4 Table 6 4 Alternate Port Functions of Timer 2 Pin Symbol Function P1 0 ANO INT3 CCO Compare output capture input for CRC register P1 1 AN1 INT4 CC1 Compare output capture input for CC register 1 P1 2 AN2 INT5 CC2 Compare output capture input for CC register 2 P1 3 AN3 INTG CC3 Compare output capture input for CC register 3 P1 5 AN5 T2EX External reload trigger input P1 7 AN7 T2 External count or gate input to timer 2 Semi
186. or that the program left the current interrupt priority level A simple RET instruction would also have returned execution to the interrupted program but it would have left the interrupt control system thinking an interrupt was still in progress In this case no interrupt of the same or lower priority level would be acknowledged Semiconductor Group 7 15 1997 08 01 IE Interrupt System SIEMENS C505 C505C 7 4 External Interrupts The external interrupts 0 and 1 can be programmed to be level activated or negative transition activated by setting or clearing bit ITx x 0 or 1 respectively in register TCON If ITx 0 external interrupt x is triggered by a detected low level at the INTx pin If ITx 1 external interrupt x is negative edge triggered In this mode if successive samples of the INTx pin show a high in one cycle and a low in the next cycle interrupt request flag IEx in TCON is set Flag bit IEx 1 then requests the interrupt If the external interrupt O or 1 is level activated the external source has to hold the request active until the requested interrupt is actually generated Then it has to deactivate the request before the interrupt service routine is completed or else another interrupt will be generated The external interrupts 4 5 and 6 are activated only by a positive transition The external timer 2 reload trigger interrupt request flag EXF2 will be activated by a negative transition at pin P1 5 AN5 T2EX but only i
187. or unprotected is fixed with the ROM mask Therefore the customer of a C505 2R version has to define whether ROM protection has to be selected or not The C505 2R devices which operate from internal ROM are always checked for correct ROM contents during production test Therefore unprotected as well as protected ROMs must provide a procedure to verify the ROM contents In ROM verification mode 1 which is used to verify unprotected ROMs a ROM address is applied externally to the C505 2R and the ROM data byte is output at port 0 ROM verification mode 2 which is used to verify ROM protected devices operates different ROM addresses are generated internally and the expected data bytes must be applied externally to the device by the manufacturer or by the customer and are compared internally with the data bytes from the ROM After 16 byte verify operations the state of the P3 5 pin shows whether the last 16 bytes have been verified correctly This mechanism provides a very high security of ROM protection Only the owner of the ROM code and the manufacturer who know the contents of the ROM can read out and verify it with less effort The behaviour of the move code instruction when the code is executed from the external ROM is in such a way that accessing a code byte from a protected on chip ROM address is not possible In this case the byte accessed will be invalid 4 7 1 Unprotected ROM Mode If the ROM is unprotected the ROM verification
188. otected ROM verify timing 4 11 Access with RMAP 3 11 PSEN SIGITal cera sehe me E REESE 4 3 CAN registers address ordered 3 18to RSW T 2 4 3 12 3 16 3 19 Table address ordered 3 15 to 3 17 BEBE oL 3 15 6 44 6 45 Table functional order 3 12 to 3 14 peter DE 3 16 SR 3 14 3 18 6 68 Recommended oscillator circuits 10 18 SRELH 55 3 13 3 16 6 49 REN MP 3 15 6 45 SRELL ssssss 3 13 3 15 6 49 FOSSE eS tise eet Hee ind otia d s 5 1 SWDT eeseeenn eee 3 16 8 3 Fast power on reset 5 3 SW Cd d darent deb oes 3 16 7 9 Hardware reset timing 5 5 SYSCON 3 3 8 11 3 12 3 16 4 4 6 89 Power on reset timing 5 4 System clock output 5 8 to 5 9 Reset circuitries 5 2 FAD oie mettus pts 3 15 6 44 6 45 7 11 pcc Pm 3 16 AMAP 222 8226o42 ores E353 3 11 3 16 ies 622 36ee E EATA EAEE 3 16 RMTPND soccer gosta rata arteries 3 18 6 77 Dp areatea este etter E talaga as EEA 3 15 ROM protection os iv rry 4 10 TOC o aduenit e dod 3 16 6 26 Protected ROM mode 4 11 T2CON 3 12 3 13 3 16 6 26 7 8 Protected ROM verification example 4 12 TAE duas door rfc ur dta kata utis 3 15 Unprotected ROM mode 4 10 ANG iso e nere uta dus me s 3 16 6 26 RSO sie aad id re sad c AGE 2 4 3 16 Dog 3 16 6 26 BST scri edd obins Dodd 2 4 3 16 PES onec OU ener ace cat eg 3 16 6 26 RXD idet trice nte fein te Si
189. own to you We can also help you get in touch with your nearest sales office By agreement we will take packing material back if it is sorted You must bear the costs of transport For packing material that is returned to us unsorted or which we are not obliged to accept we shall have to invoice you for any costs incurred Components used in life support devices or systems must be expressly authorized for such purpose Critical components of the Semiconductor Group of Siemens AG may only be used in life support devices or systems with the express written approval of the Semiconductor Group of Siemens AG 1 Acritical component is a component used in a life support device or system whose failure can reasonably be expected to cause the failure of that life support device or system or to affect its safety or effectiveness of that device or system 2 Life support devices or systems are intended a to be implanted in the human body or b to support and or maintain and sustain human life If they fail itis reasonable to assume that the health of the user may be en dangered SIEMENS General Information C505 C505C Table of Contents Page 1 Introduction T cue tolerate hoes Sees eee ee ae 1 1 1 1 Fin GONnTQUIAIION sas dee bse tin bout tacts Gahan tig weiterer RES 1 4 1 2 Pin Definitions and Functions uos xe Fob eeeed See aces dee E X ERES 1 5 2 Fundamental Structure 20000 c cece eee enne 2 1 2 1 CPU
190. pare registers and it has a rising and a falling edge Thus when using the CRC register it can be selected whether an interrupt should be caused when the compare signal goes active or inactive depending on bit I8FR in T2CON For the CC registers 1 to 3 an interrupt is always requested when the compare signal goes active see figure 6 16 6 2 2 3 1 Compare Mode 0 In mode 0 upon matching the timer and compare register contents the output signal changes from low to high It goes back to a low level on timer overflow As long as compare mode 0 is enabled the appropriate output pin is controlled by the timer circuit only and not by the user Writing to the port will have no effect Figure 6 15 shows a functional diagram of a port latch in compare mode 0 The port latch is directly controlled by the two signals timer overflow and compare The input line from the internal bus and the write to latch line are disconnected when compare mode 0 is enabled Compare mode 0 is ideal for generating pulse width modulated output signals which in turn can be used for digital to analog conversion via a filter network or by the controlled device itself e g the inductance of a DC or AC motor Mode 0 may also be used for providing output clocks with initially defined period and duty cycle This is the mode which needs the least CPU time Once set up the output goes on oscillating without any CPU intervention Figure 6 16 and 6 17 illustrate the function of compa
191. port To enable this feature bit BD bit 7 of special function register ADCONO must be set Bit SMOD PCON 7 controls a divide by 2 circuit which affect the input and output clock signal of the baud rate generator After reset the divide by 2 circuit is active and the resulting overflow output clock will be divided by 2 The input clock of the baud rate generator is fosc Baud Rate Generator SRELH afol SRELL 10 Bit Timer Overy Note The switch configuration shows the reset state MCS02734 Figure 6 23 Serial Port Input Clock when using the Baud Rate Generator The baud rate generator consists of a free running upward counting 10 bit timer On overflow of this timer next count step after counter value 3FF there is an automatic 10 bit reload from the registers SRELL and SRELH The lower 8 bits of the timer are reloaded from SRELL while the upper two bits are reloaded from bit 0 and 1 of register SRELH The baud rate timer is reloaded by writing to SRELL Semiconductor Group 6 48 1997 08 01 SIEMENS On Chip Peripheral Components C505 C505C Special Function Register SRELH Address BA Reset Value XXXXXX11p Special Function Register SRELL Address AA Reset Value D94 Bit No MSB LSB 7 6 5 4 3 2 1 0 MSB BAY 9 8 SRELH Ay 7 6 5 Aol E 4 88 sRELL nni The shaded bits are not used for reload operation Bit Funct
192. previous phase 1 Consequently the new value in the port latch will not appear at the output pin until the next phase 1 which will be at S1P1 of the next machine cycle When an instruction reads a value from a port pin e g MOV A P1 the port pin is actually sampled in state 5 phase 1 or phase 2 depending on port and alternate functions Figure 6 8 illustrates this port timing It must be noted that this mechanism of sampling once per machine cycle is also used if a port pin is to detect an edge e g when used as counter input In this case an edge is detected when the sampled value differs from the value that was sampled the cycle before Therefore there must be met certain reqirements on the pulse length of signals in order to avoid signal edges not being detected The minimum time period of high and low level is one machine cycle which guarantees that this logic level is noticed by the port at least once S4 S5 S6 S1 S2 S3 Pi P2 Pi P2 P1 P2 Pi P2 Pi P2 PI Input sampled e g MOV A P1 m P1 active for 1 State driver transistor Port Old Data X New Data MCT03231 Figure 6 8 Port Timing Semiconductor Group 6 12 1997 08 01 SIEMENS On Chip Peripheral Components C505 C505C 6 1 5 Port Loading and Interfacing The output buffers of ports 1 to 4 can drive TTL inputs directly The maximum port load which still guarantees correct logic output levels can be be looked up in the DC c
193. pt service routines The 8 general purpose registers of the selected register bank may be accessed by register addressing With register addressing the instruction op code indicates which register is to be used For indirect addressing RO and R1 are used as pointer or index register to address internal or external memory e g MOV RO Reset initializes the stack pointer to location 074 and increments it once to start from location 08 4 which is also the first register RO of register bank 1 Thus if one is going to use more than one register bank the SP should be initialized to a different location of the RAM which is not used for data storage Semiconductor Group 3 2 1997 08 01 SIEMEN Memory Organization S C505 C505C 3 4 XRAM Operation The XRAM in the C505 is a memory area that is logically located at the upper end of the external data memory space but is integrated on the chip Because the XRAM is used in the same way as external data memory the same instruction types MOVX must be used for accessing the XRAM 3 4 1 XRAM CAN Controller Access Control Two bits in SFR SYSCON XMAPO and XMAP1 control the accesses to XRAM and the CAN controller XMAPO is a general access enable disable control bit and XMAP1 controls the external signal generation during XRAM CAN controller accesses CAN controller accesses are applicable only in the case of the C505C versions Special Function Register SYSCON Address B1pg Reset Value XX
194. r 1 DCH 01XXX000p ADDAT A D Converter Data Register D9H 00H ADST A D Converter Start Register DAH XXH P1ANA Port 1 Analog Input Selection Register 90H 9 FFH Interrupt IENO Interrupt Enable Register 0 A8y 00H System IEN1 Interrupt Enable Register 1 B8y 00H IPO 2 Interrupt Priority Register 0 A9H 00H IP1 Interrupt Priority Register 1 BOY XX000000p TCON Timer Control Register 88H 00H T2CON Timer 2 Control Register C8y 00X00000p SCON Serial Channel Control Register 98H 00H IRCON Interrupt Request Control Register Coy 00H XRAM XPAGE Page Address Register for Extended on chip 91 00H XRAM and CAN Controller SYSCON System Control Register BiH XX100X01p Ports PO Port 0 805 FFH P1 Port 1 90 FFH P1ANA Port 1 Analog Input Selection Register 904 FFH P2 Port 2 Ady FFH P3 Port 3 Boy FFH P4 Port 4 E8H XXXXXX11B Bit addressable special function registers This special function register is listed repeatedly since some bits of it also belong to other functional blocks This SFR is a mapped SFR For accessing this SFR bit RMAP in SFR SYSCON must be set 1 2 3 X means that the value is undefined and the location is reserved 4 5 The content of this SFR varies with the actual step of the C505 eg 01 for the first step Semiconductor Group 1997 08 01 SIEMENS Memory Organization C505 C505C Table 3 2 Special Function Regist
195. r 128 bytes of data memory can be accessed through direct or register indirect addressing the upper 128 bytes of RAM can be accessed through register indirect addressing the special function registers are accessible through direct addressing Four 8 register banks each bank consisting of eight 8 bit general purpose registers occupy locations 0 through 1Fp in the lower RAM area The next 16 bytes locations 204 through 2Fy contain 128 directly addressable bit locations The stack can be located anywhere in the internal RAM area and the stack depth can be expanded up to 256 bytes The external data memory can be expanded up to 64 Kbyte and can be accessed by instructions that use a 16 bit or an 8 bit address The internal CAN controller C505C only and the internal XRAM are located in the external memory address area at addresses F700j to F7FFY and FFOOW to FFFFy respectively The CAN controller registers and internal XRAM can therefore be accessed using MOVX instructions with addresses pointing to the respective address areas 3 3 General Purpose Registers The lower 32 locations of the internal RAM are assigned to four banks of eight general purpose registers GPRs each Only one of these banks may be enabled at a time Two bits in the program status word RS0 PSW 3 and RS1 PSW 4 select the active register bank see description of the PSW in chapter 2 This allows fast context switching which is useful when entering subroutines or interru
196. r Counter 0 and 1 Registers Totally six special function registers control the timer counter 0 and 1 operation TLO THO and TL1 TH1 counter registers low and high part TCON and TMOD control and mode select registers Special Function Register TLO Address 8Aq Reset Value 00H Special Function Register THO Address 8C Reset Value 00H Special Function Register TL1 Address 8By Reset Value 00H Special Function Register TH1 Address 8D Reset Value 00H Bit No MSB LSB 7 6 5 4 3 2 1 0 8A 7 6 iD 4 3 2 A 0 TLO 8Cy Ti 6 5 4 EC 2 A 0 THO 8By 7 6 5 4 EC 2 A 0 TL1 8Dy 7 6 5 4 2d 2 A 0 TH1 Bit Function TLx 7 0 Timer counter 0 1 low register 0 1 x 0 Operating Mode Description 0 TLx holds the 5 bit prescaler value 1 TLx holds the lower 8 bit part of the 16 bit timer counter value 2 TLx holds the 8 bit timer counter value 3 TLO holds the 8 bit timer counter value TL1 is not used THx 7 0 Timer counter 0 1 high register ud Operating Mode Description 0 THx holds the 8 bit timer counter value 1 THx holds the higher 8 bit part of the 16 bit timer counter value 2 THx holds the 8 bit reload value 3 THO holds the 8 bit timer value TH1 is not used Semiconductor Group 6 16 1997 08 01 SIEMENS On Chip Peripheral Components C505 C505C Special Function Register TCON Address 884 Reset Val
197. r SR Address F701 Reset Value XXH Bit No MSB LSB 7 6 5 4 3 2 1 0 F701 BOFF EWRN RXOK TXOK LEC SR r r r rw rw rw Bit Function BOFF Busoff status Indicates when the CAN controller is in busoff state see EML EWRN Error warning status Indicates that at least one of the error counters in the EML has reached the error warning limit of 96 RXOK Received message successfully Indicates that a message has been received successfully since this bit was last reset by the CPU the CAN controller does not reset this bit TXOK Transmitted message successfully Indicates that a message has been transmitted successfully error free and acknowledged by at least one other node since this bit was last reset by the CPU the CAN controller does not reset this bit Semiconductor Group 6 68 1997 08 01 IE On Chip Peripheral Components SIEMENS C505C Only Bit Function LEC Last error code This field holds a code which indicates the type of the last error occurred on the CAN bus If a message has been transferred reception or transmission without error this field will be cleared Code 7 is unused and may be written by the microcontroller to check for updates LEC2 0 Error Description 0 0 0 NoEmor 0 0 1 Stuff Error More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed O 1 0 Form Error A fixed format part of a received frame
198. range lt F700p the XRAM CAN controller may remain enabled and there is no need to overwrite XPAGE by a second move Semiconductor Group 3 6 1997 08 01 SIEM ENS Memory Organization C505 C505C p 22 22 222 2 2 2 2 22 2 2 2 2 I I I I gt Address Data I I I I XRAM I CAN Controller i XPAGE I i Write to I XPAGE I I Address i HO Dat I I I E EP EP Nr eee Ss es a ces ea oan E PE MCS02762 Figure 3 3 Write Page Address to XPAGE MOV XPAGE pageaddress will write the page address only to the XPAGE register Port 2 is available for addresses or I O data Semiconductor Group 3 7 1997 08 01 SIEM ENS Memory Organization C505 C505C gt Address Data XRAM CAN Controller gt I O Data MCS02763 Figure 3 4 Use of Port 2 as I O Port At a write to port 2 the XRAM CAN controller address in XPAGE register will be overwritten because of the concurrent write to port 2 and XPAGE register So whenever XRAM is used and the XRAM address differs from the byte written to port 2 latch it is absolutely necessary to rewrite XPAGE with the page address Example I O data at port 2 shall be AAy A byte shall be fetched from XRAM at address FF30y MOV RO 30H MOV P2 0AAH P2 shows AAH and XPAGE contains AAH MOV XPAGE 0FFH P2 still shows AAH but XRAM is addressed MOVX A RO the contents of XRAM at F
199. re Register CCx 1 L16 Bit JTL Compare Signal 1 16 Bit Overflow Interrupt Interrupt Shaded Function for CRC only Port Latch Circuit Shadow Latch O O O O 9 P1 7 P1 3 P1 0 INT6 NT3 CC3 cco MCS02732 Figure 6 20 Timer 2 with Registers CCx in Compare Mode 1 CCx stands for CRC CC1 to CC3 IEXx stands for IEX3 to IEX6 Semiconductor Group 6 37 1997 08 01 IE On Chip Peripheral Components SIEMENS C505 C505C 6 2 2 4 Using Interrupts in Combination with the Compare Function The compare service of registers CRC CC1 CC2 and CC3 are assigned to alternate output functions at port pins P1 0 to P1 3 Another option of these pins is that they can be used as external interrupt inputs However when using the port lines as compare outputs then the input line from the port pin to the interrupt system is disconnected but the pin s level can still be read under software control Thus a change of the pin s level will not cause a setting of the corresponding interrupt flag In this case the interrupt input is directly connected to the internal compare signal thus providing a compare interrupt The compare interrupt can be used very effectively to change the contents of the compare registers or to determine the level of the port outputs for the next compare match The principle is that the internal compare signal generated at a match between timer count
200. re described Fetches from external program memory always use a 16 bit address Accesses to external data memory can use either a 16 bit address MOVX DPTR or an 8 bit address MOVX Ri 4 1 1 Role of PO and P2 as Data Address Bus When used for accessing external memory port O provides the data byte time multiplexed with the low byte of the address In this state port 0 is disconnected from its own port latch and the address data signal drives both FETs in the port 0 output buffers Thus in this application the port O pins are not open drain outputs and do not require external pullup resistors During any access to external memory the CPU writes FFy to the port 0 latch the special function register thus obliterating whatever information the port 0 SFR may have been holding Whenever a 16 bit address is used the high byte of the address comes out on port 2 where it is held for the duration of the read or write cycle During this time the port 2 lines are disconnected from the port 2 latch the special function register Thus the port 2 latch does not have to contain 1s and the contents of the port 2 SFR are not modified If an 8 bit address is used MOVX Ri the contents of the port 2 SFR remain at the port 2 pins throughout the external memory cycle This will facilitate paging It should be noted that if a port 2 pin outputs an address bit that is a 1 strong pullups will be used for the entire read write cycle and not
201. re mode 0 Semiconductor Group 6 32 1997 08 01 SIEMENS On Chip Peripheral Components C505 C505C Compare Register Circuit Compare Reg IL Compare Match Timer Register IL D Timer Timer Circuit Overflow Port Circuit Internal Bus Write to Latch Read Pin MCS02661 Figure 6 15 Port Latch in Compare Mode 0 n Interrupt Shaded Function Compare Register CCx for CRC only 16 Bit C JTL Set Latch Compare Signal T 16 Bit Reset Latch Overflow Interrupt p13 p12 Pt 1 P1 0 gt INT6 INT5J INT4 INT3 cc3 CC2 CCI cco MCS03233 Figure 6 16 Timer 2 with Registers CCx in Compare Mode 0 Semiconductor Group 6 33 1997 08 01 SIEMENS On Chip Peripheral Components C505 C505C Timer Count FFFF H Timer Count Compare Value Contents of Timer 2 Timer Count Reload Value Interrupt can be generated on overflow Compare Output P1 x CCx j MCT01906 Interrupt can be generated on compare match Figure 6 17 Function of Compare Mode 0 6 2 2 3 2 Modulation Range in Compare Mode 0 Generally it can be said that for every PWM generation in compare mode 0 with n bit wide compare registers there are 2 different settings for the duty cycle Starting with a constant low level 0 duty cycle as the first setting the maximum possible duty cycle would the
202. rect addressing with registers RO or R1 The instructions are MOVX A Ri Read MOVX Ri A Write Aspecial page register is implemented in the C505 to provide the possibility of accessing the XRAM or CAN controller also with the MOVX Ri instructions i e XPAGE serves the same function for the XRAM and CAN controller as Port 2 for external data memory Special Function Register XPAGE Address 914 Reset Value 00H Bit No MSB LSB 7 6 5 4 3 2 1 0 91H x 6 Es 4 3 2 1 0 XPAGE Bit Function XPAGE 7 0 XRAM CAN controller high address XPAGE 7 0 is the address part A15 A8 when 8 bit MOVX instructions are used to access internal XRAM or CAN controller Figures 3 2 to 3 4 show the dependencies of XPAGE and Port 2 addressing in order to explain the differences in accessing XRAM CAN controller ext RAM or what is to do when Port 2 is used as an l O port Semiconductor Group 3 5 1997 08 01 SIEMEN Memory Organization S C505 C505C gt Address Data XRAM CAN Controller Write to Port 2 gt Page Address Da MM MCS02761 Figure 3 2 Write Page Address to Port 2 MOV P2 pageaddress will write the page address to port 2 and the XPAGE Register When external RAM is to be accessed in the XRAM CAN controller address range the XRAM CAN controller has to be disabled When additional external RAM is to be addressed in an address
203. red that the compare signal is active as long as the timer 2 count is equal to the contents of the corresponding compare register and that the compare signal has a rising and a falling edge Furthermore the shadow latches used in compare mode 1 are transparent while the compare signal is active Thus with a slow input clock for timer 2 the comparator signal is active for a long time high number of machine cycles and therefore a fast interrupt controlled reload of the compare register could not only change the shadow latch as probably intended but also the output buffer When using the CRC you can select whether an interrupt should be generated when the compare signal goes active or inactive depending on the status of bit IBFR in T2CON Initializing the interrupt to be negative transition triggered is advisable in the above case Then the compare signal is already inactive and any write access to the port latch just changes the contents of the shadow latch Please note that for CC1 to CC3 registers an interrupt is always requested when the compare signal goes active Semiconductor Group 6 38 1997 08 01 IE On Chip Peripheral Components SIEMENS C505 C505C The second configuration which should be noted is when compare function is combined with negative transition activated interrupts If the port latch of port P1 0 contains a 1 the interrupt request flags IEX3 will immediately be set after enabling the compare mod
204. ress F7n4 CAN Lower Arbitration Register High LAR1 Address F7n5p Reset Value UUH Reset Value UUH Reset Value UUH Reset Value UUUUUO00p Bit No MSB LSB 7 6 5 4 3 2 1 0 F7n2y ID28 21 UARO rw F7n3y ID20 18 ID17 13 UAR1 rw rw F7n4y4 ID12 5 LARO rw F7n5y ID4 0 0 0 0 LAR1 rw r r r Bit Function ID28 0 Identifier 29 bit Identifier of a standard message ID28 18 or an extended message ID28 0 For standard identifiers bits ID17 0 are don t care Semiconductor Group 6 79 1997 08 01 IEMEN On Chip Peripheral Components P C505C Only Message Configuration and Data The following fields hold a description of the message within this object The data field occupies the following 8 byte positions after the message configuration register Note There is no don t care option for bits XTD and DIR So incoming frames can only match with corresponding message objects either standard XTD 0 or extended XTD 1 Data frames only match with receive objects remote frames only match with transmit objects When the CAN controller stores a data frame it will write all the eight data bytes into a message object If the data length code was less than 8 the remaining bytes of the message object will be overwritten by non specified values CAN Message Configuration MCFG Register Address F7n6 ResetValue UUUUUUO00p Bi
205. ret ons t eter 4 4 4 5 Enhanced Hooks Emulation Concept 4s 12e rpm FPE ei qu 4 5 4 6 Eight Datapointers for Faster External Bus Access 0000 0 eee eee 4 6 4 6 1 The Importance of Additional Datapointers 0 0c eee ee 4 6 4 6 2 How the eight Datapointers of the C505 are realized 000000 00 4 6 4 6 3 Advantages of Multiple Datapointers 0 000 cee ee 4 7 4 6 4 Application Example and Performance Analysis 0000 eee eee eee eee 4 7 4 7 ROM Protection for the 505 vox cep Seat ped Seale eee REN 4 10 4 7 1 Unprotected ROM Mode iusso ket ace oe ale Seno mee Ue aw ee eite 4 10 4 7 2 Protected ROM Mode sest cece dum SAEC DET PESO Ex ehe wee Rear 4 11 4 8 Version ROS S oS d ero bo P RUE EORR ahaa sects Mma neural onside Ard dd 4 13 5 System HeSebt s ovesRERSAEE LERRA Face ie itas Vr n ute tere ae Dea i ee 5 1 5 1 Hardware Reset Operation s as ados Pete cane Raed ee eee et ae ae 5 1 5 2 Fast Internal Reset after Power On 0 000 cece eee 5 3 5 3 Hardware Reset Timing uua Soo espe aie btu eiae code d bo aaa teeth aed 5 5 5 4 Oscillator and Clock Circuit sec stew grace cte eio n E ORA Crap PDC DECR SORGE n 5 6 5 5 System Clock OUIDUI sve Sa Es PEST Eee padi eld Meses Cr a cR Rd dr 5 8 Semiconductor Group l 1 1997 08 01 SIEMENS General Information C505 C505C Table of Contents Page 6 On Chip Peripheral Components 002 200s e eee eee eee eee 6 1 6 1 Parallel UC cg
206. rial reception Cleared by software to disable serial reception TB8 Serial port transmitter bit 9 TB8 is the 9th data bit that will be transmitted in modes 2 and 3 Set or cleared by software as desired RB8 Serial port receiver bit 9 In modes 2 and 3 RB8 is the 9th data bit that was received In mode 1 if SM2 0 RB8 is the stop bit that was received In mode 0 RB8 is not used TI Serial port transmitter interrupt flag Tl is set by hardware at the end of the 8th bit time in mode 0 or at the beginning of the stop bit in the other modes in any serial transmission TI must be cleared by software RI Serial port receiver interrupt flag RI is set by hardware at the end of the 8th bit time in mode 0 or halfway through the stop bit time in the other modes in any serial reception exception see SM2 RI must be cleared by software Semiconductor Group 6 45 1997 08 01 IE On Chip Peripheral Components SIEMENS C505 C505C 6 3 3 Baud Rate Generation There are several possibilities to generate the baud rate clock for the serial port depending on the mode in which it is operating For clarification some terms regarding the difference between baud rate clock and baud rate should be mentioned The serial interface requires a clock rate which is 16 times the baud rate for internal synchronization Therefore the baud rate generators have to provide a baud rate clock to the serial interface which there divided
207. ristics Parameter Symbol Limit Values Unit 16 MHz Variable Clock clock 1 CLP 2 MHz to 16 MHz Duty Cycle 0 4 to 0 6 min max min max RD pulse width fai RH 158 3CLP 30 ns WR pulse width fwLwH 158 3CLP 30 ns Address hold after ALE TLLax2 48 CLP 15 ns RD to valid data in fai pv 100 2 CLP ns TCLmin 50 Data hold after RD RHDX 0 0 ns Data float after RD faupz 51 CLP 12 ns ALE to valid data in fip 200 4 CLP 50 ns Address to valid data in Tavov 200 4 CLP ns TCLpmin 75 ALE to WR or RD fiw 73 103 CLP CLP ns TCLimin 15 TCLimint 15 Address valid to WR Tavwe 95 2CLP 30 ns WR or RD high to ALE high WHLH 10 40 TCLyumin 15 TCLumin 15 ns Data valid to WR transition favwx 5 TCL min 20 ns Data setup before WR favwH 163 3 CLP ns TCL min 50 Data hold after WR twHax 5 TCLumin 20 ns Address float after RD TRLaz 0 0 ns Semiconductor Group 10 7 1997 08 01 SIEMENS Device Specifications C505 C505C AC Characteristics 16 MHz for C505 cont d External Clock Drive Characteristics Parameter Symbol CPU Clock 16 MHz Variable CPU Clock Unit Duty Cycle 0 4 to 0 6 1 CLP 2 to 16 MHz min max min max Oscillator period CLP 62 5 62 5 62 5 500 ns High time TCL 25 25 CLP TCL ns Low time TCL 25 25 CLP TCLy ns Rise time tr 10 10 ns Fall time te 10 10 ns Oscillator duty cycle DC 0 4 0
208. s between the release of the RESET signal and the first falling edge at ALE there is a time period of at least one machine cycle but less than two machine cycles I One Machine Cycle gt S4 S5 S6 St s2 s3 s4 5 6 1 Se2 s3 s4 S5 S6 S1 2 P1 P2 reset XXXXAKAXAAKAKAXA OUT in OUT PCH PCH ALE MCT02092 Figure 5 3 CPU Timing after Reset Semiconductor Group 5 5 1997 08 01 IE System Reset SIEMENS C505 C505C 5 4 Oscillator and Clock Circuit XTAL1 and XTAL2 are the input and output of a single stage on chip inverter which can be configured with off chip components as a Pierce oscillator The oscillator in any case drives the internal clock generator The clock generator provides the internal clock signals to the chip These signals define the internal phases states and machine cycles Figure 5 4 shows the recommended oscillator circuit C 20 pF 10 pF for crystal operation MCS03292 Figure 5 4 Recommended Oscillator Circuit In this application the on chip oscillator is used as a crystal controlled positive reactance oscillator a more detailed schematic is given in figure 5 5 It is operated in its fundamental response mode as an inductive reactor in parallel resonance with a capacitor external to the chip The crystal specifications and capacitances are non critical In this circuit
209. s In most typical applications it is configured for timer operation in the auto reload mode high nibble of TMOD 0010p In this case the baud rate is given by the formula 23VOD x oscillator frequency Mode 1 3 baud rate 32 x 6 x 256 TH1 Very low baud rates can be achieved with timer 1 if leaving the timer 1 interrupt enabled configuring the timer to run as 16 bit timer high nibble of TMOD 0001 p and using the timer 1 interrupt for a 16 bit software reload Semiconductor Group 6 50 1997 08 01 SIEMENS On Chip Peripheral Components C505 C505C 6 3 4 Details about Mode 0 Serial data enters and exists through RxD TxD outputs the shift clock 8 data bits are transmitted received LSB first The baud rate is fixed at fog 6 Figure 6 24 shows a simplified functional diagram of the serial port in mode 0 The associated timing is illustrated in figure 6 25 Transmission is initiated by any instruction that uses SBUF as a destination register The Write to SBUF signal at S6P2 also loads a 1 into the 9th position of the transmit shift register and tells the TX control block to commence a transmission The internal timing is such that one full machine cycle will elapse between Write to SBUF and activation of SEND SEND enables the output of the shift register to the alternate output function line of P3 0 and also enables SHIFT CLOCK to the alternate output function line of P3 1 SHIFT CLOCK is low during
210. s cont d Addr Register Content Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit 0 after Reset DCy ADCON 1 01XX ADCL1 ADCLO MX2 MX1 MXO X000p E0H ACC 001 Yi 6 5 4 B E 1 0 E8y2 P4 XXXX RXDC TXDC XX11p FOL B 001 iy 6 5 4 3 2 al 0 FC 43 VRO C5y 1 1 0 0 0 1 1 FDy9 9 VR1 05H 0 0 0 0 0 1 0 1 FE 94 VR2 5 y 6 5 4 3 2 1 0 1 X means that the value is undefined and the location is reserved 2 Bit addressable special function registers 3 SFR is located in the mapped SFR area For accessing this SFR bit RMAP in SFR SYSCON must be set 4 These are read only registers 5 The content of this SFR varies with the actual of the step C505 eg 014 for the first step Semiconductor Group 3 17 1997 08 01 SIEMEN Memory Organization S C505 C505C Table 3 4 Contents of the CAN Registers in numeric order of their addresses C505C only Addr Register Content Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 BitO n 1 Fy after 1 Reset 2 F700 CR 01H TEST CCE JO 0 EIE SIE IE INIT F701j SR XXH BOFF EWRN RXOK TXOK LEC2 LEC1 LECO F7024 IR XXH INTID F7044 BTRO UUH SJW BRP F7054 BTR1 OUUU J0 TSEG2 TSEG1 UUUUB F 064 GMSO UUH ID28 21 F707 GMS1 UUU1 ID20 18 1 1 1 1 1 1111p F708 UGMLO UUH ID28
211. s 5 bit prescaler 0 1 16 bit timer counter THx and TLx are cascaded there is no prescaler 1 0 8 bit auto reload timer counter THx holds a value which is to be reloaded into TLx each time it overflows 1 1 Timer O TLO is an 8 bit timer counter controlled by the standard timer 0 control bits THO is an 8 bit timer only controlled by timer 1 control bits Timer 1 Timer counter 1 stops Semiconductor Group 6 18 1997 08 01 SIEMENS On Chip Peripheral Components C505 C505C 6 2 1 2 Mode 0 Putting either timer counter 0 1 into mode 0 configures it as an 8 bit timer counter with a divide by 32 prescaler Figure 6 9 shows the mode 0 operation In this mode the timer register is configured as a 13 bit register As the count rolls over from all 1 s to all O s it sets the timer overflow flag TFO The overflow flag TFO then can be used to request an interrupt The counted input is enabled to the timer when TRO 1 and either Gate 0 or INTO 1 setting Gate 1 allows the timer to be controlled by external input INTO to facilitate pulse width measurements TRO is a control bit in the special function register TCON Gate is in TMOD The 13 bit register consists of all 8 bits of THO and the lower 5 bits of TLO The upper 3 bits of TLO are indeterminate and should be ignored Setting the run flag TRO does not clear the registers Mode 0 operation is the same for timer 0 as for timer 1 Substitute TRO TF
212. s if they had been set or cleared by hardware That is interrupts can be generated or pending interrupts can be cancelled by software The only exceptions are the request flags IEO and IE1 If the external interrupts O and 1 are programmed to be level activated IEO and IE1 are controlled by the external source via pin INTO and INT1 respectively Thus writing a one to these bits will not set the request flag IEO and or IE1 In this mode interrupts O and 1 can only be generated by software and by writing a 0 to the corresponding pins INTO P3 2 and INT1 P3 3 provided that this will not affect any peripheral circuit connected to the pins The bit IRCON 1 can be set by software to vector to location 004Bpg In the case of the C505C care should be taken while manipulating this bit to avoid any erroneous CAN interrupt generation Semiconductor Group 7 10 1997 08 01 IE Interrupt System SIEMENS C505 C505C Special Function Register SCON Address 984 Reset Value 00H MSB LSB Bit No 9Fu 9Ey 9Dy 9CH 9By 9AH 99H 98H 984 SMO SM1 SM2 REN TB8 RB8 TI RI SCON ai The shaded bits are not used for interrupt control Bit Function TI Serial interface transmitter interrupt flag Set by hardware at the end of a serial data transmission Must be cleared by software RI Serial interface receiver interrupt flag Set by hardware if a serial data byte has been received Must be cleared by sof
213. section 6 4 6 with table 6 7 for further details about the CAN controller interrupt handling Semiconductor Group 6 70 1997 08 01 SIEMENS On Chip Peripheral Components C505C Only CAN Bit Timing Register Low BTRO Address F704 Reset Value UUH Bit No MSB LSB 7 6 5 4 3 2 1 0 F704 SJW BRP BTRO rw rw Bit Function SJW Re Synchronization jump width Adjust the bit time by SUW 1 time quanta for resynchronization BRP Baud rate prescaler For generating the bit time quanta the oscillator frequency is divided by BRP 1 Note This register can only be written if the configuration change enable bit CCE is set CAN Bit Timing Register High BTR1 Address F705 4 Reset Value OUUUUUUUB Bit No MSB LSB 7 6 5 4 3 2 1 0 F705y 0 TSEG2 TSEG1 BTR1 r rw rw Bit Function TSEG2 Time segment after sample point There are TSEG2 1 time quanta after the sample point Valid values for TSEG2 are 1 7 TSEG1 Time segment before sample point There are TSEG1 1 time quanta before the sample point Valid values for TSEG1 are 2 15 Note This register can only be written if the configuration change enable bit CCE is set Semiconductor Group 6 71 1997 08 01 SIEMENS On Chip Peripheral Components C505C Only Mask Registers Messages can use standard or extended identifiers Incoming frames are masked with their appropriate global masks Bit IDE of the incomi
214. sed the bit RMAP must be cleared set respectively by software All SFRs with addresses where address bits 0 2 are 0 e g 80H 88H 90H 98y F8H FFH are bitaddressable The 52 special function registers SFRs in the standard and mapped SFR area include pointers and registers that provide an interface between the CPU and the other on chip peripherals The SFRs of the C505 are listed in table 3 2 and table 3 3 In table 3 2 they are organized in groups which refer to the functional blocks of the C505 The CAN SFRs applicable for the C505C only are also included in table 3 2 Table 3 3 illustrates the contents of the SFRs in numeric order of their addresses Table 3 4 list the CAN SFRs in numeric order of their addresses Semiconductor Group 3 11 1997 08 01 SIEMENS Memory Organization C505 C505C Table 3 2 Special Function Registers Functional Blocks Block Symbol Name Address Contents after Reset CPU ACC Accumulator E0y 00H B B Register FOH 00H DPH Data Pointer High Byte 83H 00H DPL Data Pointer Low Byte 82H 00H DPSEL Data Pointer Select Register 924 XXXXX000p PSW Program Status Word Register DOW 00H SP Stack Pointer 81H 07H SYSCON System Control Register Biy XX100X01 p VR0 Version Register 0 FCH C5H VR19 Version Register 1 FDH 05H VR29 Version Register 2 FEH zi A D ADCONO A D Converter Control Register 0 D84 00X00000p Converter ADCON1 A D Converter Control Registe
215. simplified functional diagram of the serial port in mode 1 The associated timings for transmit receive are illustrated in figure 6 27 Transmission is initiated by an instruction that uses SBUF as a destination register The Write to SBUF signal also loads a 1 into the 9th bit position of the transmit shift register and flags the TX control unit that a transmission is requested Transmission starts at the next rollover in the divide by 16 counter Thus the bit times are synchronized to the divide by 16 counter not to the Write to SBUF signal The transmission begins with activation of SEND which puts the start bit at TxD One bit time later DATA is activated which enables the output bit of the transmit shift register to TxD The first shift pulse occurs one bit time after that As data bits shift out to the right zeroes are clocked in from the left When the MSB of the data byte is at the output position of the shift register then the 1 that was initially loaded into the 9th position is just to the left of the MSB and all positions to the left of that contain zeroes This condition flags the TX control unit to do one last shift and then deactivate SEND and set TI This occurs at the 10th divide by 16 rollover after Write to SBUF Reception is initiated by a detected 1 to 0 transition at RxD For this purpose RxD is sampled at a rate of 16 times whatever baud rate has been established When a transition is detected the divide by 1
216. t No MSB LSB 7 6 5 4 3 2 1 0 F7n6y DLC DIR XTD 0 0 MCFG a rw rw r r Bit Function DLC Data length code Valid values for the data length are 0 8 DIR Message direction DIR 1 transmit On TXRQ the respective message object is transmitted On reception of a remote frame with matching identifier the TXRQ and RMTPND bits of this message object are set DIR 0 receive On TXRQ a remote frame with the identifier of this message object is transmitted On reception of a data frame with matching identifier that message is stored in this message object XTD Extended identifier Indicates if this message object will use an extended 29 bit identifier or a standard 11 bit identifier Semiconductor Group 6 80 1997 08 01 SIEMENS On Chip Peripheral Components C505C Only CAN Data Bytes DBO DB7 Addresses F7n7g F7nEp Reset Value XXH Bit No MSB LSB 7 6 5 4 3 2 1 0 F7n7g F7nEy 7 6 5 4 2d 2 1 0 DBO 7 rw rw rw rw rw rw rw rw Message data for message object 15 last message will be written into a two message alternating buffer to avoid the loss of a message if a second message has been received before the microcontroller has read the first one 6 4 3 Handling of Message Objects The following diagrams figures 6 33 to 6 38 summarize the actions that have to be taken in order to transmit and receive messages over the CAN bus The actions taken by the CAN controller are descr
217. t or not the unit goes back to looking for a 1 to 0 transition in RxD Semiconductor Group 6 54 1997 08 01 SIEMENS On Chip Peripheral Components C505 C505C g Write a to e Bus EE i S 2 AH gt 1 TxD D CLK Shift Data TX Control gt 16 TI Send Baud Serial gt 1 Rate e Port Clock Interrupt 16 Sample RI Load SBUF 1 to 0 Transition Detector RX Control iFFj Shift Bit gt Input Shift Register 9Bits RXD Shift Load PEE SBUF SBUF Read AE v Internal Bus MCS02103 Figure 6 26 Serial Interface Mode 1 Functional Diagram Semiconductor Group 6 55 1997 08 01 SIEMENS On Chip Peripheral Components C505 C505C Transmit 5 E D o JI a P sea 5 2 SE lt um Lo xo gt lt zc LL tcc o cc aw 72 cc gt So 26 ac ra ES E 5 5 z Receive Figure 6 27 Serial Interface Mode 1 Timing Diagram 1997 08 01 Semiconductor Group 6 56 IE On Chip Peripheral Components SIEMENS C505 C505C 6 3 6 Details about Modes 2 and 3 Eleven bits are transmitted through TxD or received through RxD a start bit 0 8 data bits LSB first a programmable 9th data bit and a stop bit 1 On transmission the 9th data bit TB8 can be assigned the value of 0 or 1 On reception the 9th data bit goes into RB8 in SCON The baud rate is programmabl
218. t request flag Set by hardware at the end of an A D conversion Must be cleared by software Semiconductor Group 6 103 1997 08 01 IE On Chip Peripheral Components SIEMENS C505 C505C 6 5 3 A D Converter Clock Selection The ADC uses two clock signals for operation the conversion clock fApc 1 tapc and the input clock fiy 1 tjN fApc is derived from the C505 system clock fosc which is applied at the XTAL pins via the ADC clock prescaler as shown in figure 6 43 The input clock is equal to fosc The conversion clock fApc is limited to a maximum frequency of 1 25 MHz Therefore the ADC clock prescaler must be programmed to a value which assures that the conversion clock does not exceed 1 25 MHz The prescaler ratio is selected by the bits ADCL1 and ADCLO of SFR ADCON1 The table in figure 6 43 shows the prescaler ratio which must be selected by ADCL1 and ADCLO for typical system clock rates Up to 5 MHz system clock the prescaler ratio 4 is selected Using a system clock greater than 5 and less than 10 MHz the prescaler ratio of at least 8 must be selected A prescaler ratio of 16 must be selected when using a system clock greater than 10 MHz Conversion Clock fpc A D Converter Clock Prescaler Input Clock fiy Condition f ADC max lt 1 25 MHz fin fosc A MCS03299 MCU System Clock fi Prescaler fApc Rate fosc Ratio MHz 2 MHz 4 0 5 5 MHz 4 1 25 6 MHz 8 0 75 10 MHz 8 1 25 12 MHz 16 0
219. terrupt while in other cases it does not then this has to be done by the user s software The hardware clears the external interrupt flags IEO and IE1 only if they were transition activated The hardware generated L CALL pushes the contents of the program counter onto the stack but it does not save the PSW and reloads the program counter with an address that depends on the source of the interrupt being vectored to as shown in the following table 7 2 Table 7 2 Interrupt Source and Vectors Interrupt Source Interrupt Vector Address Interrupt Request Flags External Interrupt 0 0003H IEO Timer 0 Overflow 000BH TFO External Interrupt 1 0013H IE1 Timer 1 Overflow 001BH TF1 Serial Channel 0023H RI TI Timer 2 Overflow Ext Reload 002By TF2 EXF2 A D Converter 0043H IADC CAN Controller Software Interrupt 004By External interrupt 3 0053H IEX3 External Interrupt 4 0005B4 IEX4 External Interrupt 5 0063H IEX5 External interrupt 6 0006B4 IEX6 Wake up from power down mode 007BH Execution proceeds from that location until the RETI instruction is encountered The RETI instruction informs the processor that the interrupt routine is no longer in progress then pops the two top bytes from the stack and reloads the program counter Execution of the interrupted program continues from the point where it was stopped Note that the RETI instruction is very important because it informs the process
220. th data bit for transmit and receive TB8 and RB8 and the serial port interrupt bits Tl and RI SBUF is the receive and transmit buffer of serial interface Writing to SBUF loads the transmit register and initiates transmission Reading out SBUF accesses a physically separate receive register Semiconductor Group 6 44 1997 08 01 SIEMENS On Chip Peripheral Components C505 C505C Special Function Register SCON Address 9814 Reset Value 00H Special Function Register SBUF Address 99 Reset Value XXH BitNo MSB LSB 9Fy 9EH 9DH 9CH 9BH 9AH 99H 98H 98H SMO SM1 SM2 REN TB8 RB8 TI RI SCON 7 6 5 4 3 2 1 0 99H Serial Interface Buffer Register SBUF Bit Function SMO Serial port 0 operating mode selection bits SM1 SMO SM1 Selected operating mode 0 0 Serial mode 0 Shift register fixed baud rate fosc 6 0 1 Serial mode 1 8 bit UART variable baud rate 1 0 Serial mode 2 9 bit UART fixed baud rate fosc 16 or fosc 32 1 1 Serial mode 3 9 bit UART variable baud rate SM2 Enable serial port multiprocessor communication in modes 2 and 3 In mode 2 or 3 if SM2 is set to 1 then RI will not be activated if the received 9th data bit RB8 is 0 In mode 1 if SM2 1 then RI will not be activated if a valid stop bit was not received In mode 0 SM2 should be 0 REN Enable receiver of serial port Enables serial reception Set by software to enable se
221. th the beginning of the machine cycle which follows the write result cycle The BSY bit is set at the beginning of the first A D conversion machine cycle and reset at the beginning of the write result cycle If continuous conversion is selected BSY is again set with the beginning of the machine cycle which follows the write result cycle This means that in continuous conversion mode BSY is not set for a complete machine cycle Therefore in continuous conversion mode it is not recommended to poll the BSY bit using for e g the JNB instruction The interrupt flag IADC is set at the end of the A D conversion so that it is polled the first time in S1P2 of the machine cycle following the completion of conversion If the A D converter interrupt is enabled and the A D converter interrupt is prioritized to be serviced immediately the first instruction of the interrupt service routine will be executed in the fourth machine cycle which follows the write result cycle The IADC bit must be reset by software Depending on the application typically there are three methods to handle the A D conversion in the C505 Software delay The machine cycles during an A D conversion are counted and the program executes a software delay e g NOPs before reading the A D conversion result in the write result cycle The end of conversion is indicated by the IADC flag Polling BSY bit The BSY bit is polled and the program waits until BSY 0 Attention a polling
222. tion the timer 2 is incremented in response to a 1 to O transition at its corresponding external input pin T2 P1 7 In this function the external input is sampled every machine cycle When the sampled inputs show a high in one cycle and a low in the next cycle the count is incremented The new count value appears in the timer register in the cycle following the one in which the transition was detected Since it takes two machine cycles 12 oscillator periods to recognize a 1 to 0 transition the maximum count rate is 1 12 of the oscillator frequency There are no restrictions on the duty cycle of the external input signal but to ensure that a given level is sampled at least once before it changes it must be held for at least one full machine cycle Note The prescaler must be off for proper counter operation of timer 2 i e T2PS must be 0 In either case no matter whether timer 2 is configured as timer event counter or gated timer a rolling over of the count from all 1 s to all O s sets the timer overflow flag TF2 in SFR IRCON which can generate an interrupt If TF2 is used to generate a timer overflow interrupt the request flag must be cleared by the interrupt service routine as it could be necessary to check whether it was the TF2 flag or the external reload request flag EXF2 which requested the interrupt Both request flags cause the program to branch to the same vector address Semiconductor Group 6 30 1997 08 01 IE On Chip Periph
223. to an internal address or address data bus for use in external memory accesses In this application they cannot be used as general purpose l O even if not all address lines are used externally The switching is done by an internal control signal dependent on the input level at the EA pin and or the contents of the program counter If the ports are configured as an address data bus the port latches are disconnected from the driver circuit During this time the PO P2 SFR remains unchanged Being an address data bus port 0 uses a pullup FET as shown in figure 6 3 When a 16 bit address is used port 2 uses the additional strong pullups p1 figure 6 5a to emit 1 s for the entire external memory cycle instead of the weak ones p2 and p3 used during normal port activity Addr Control Voc Read Latch Internal Pull Up Arrangement i e Port Pin Int Bus Write to Latch Y Read MCS03228 Pin Figure 6 5 Port 2 Circuitry If no external bus cycles are generated using data or code memory accesses port 0 can be used for I O functions Semiconductor Group 6 7 1997 08 01 SIEMENS On Chip Peripheral Components C505 C505C Addr Control Vec A TN e 1 MUX 9 e lt 1 po o 1 State e e e o a 1 ls e ni Y Vss 1 Input Data Read Pin o o MCS03229 Figure 6 5a Port 2 Pull up Arran
224. ture compare interrupt 0 enable If EX3 0 external interrupt 3 is disabled If EX3 1 external interrupt 3 is enabled ECAN CAN controller interrupt enable C505C only If ECAN 0 the CAN controller interrupt is disabled If ECAN 1 the CAN controller interrupt is enabled This bit must be set in order to enable the software interrupt at bit SWI for C505 and C505C EADC A D converter interrupt enable If EADC 0 the A D converter interrupt is disabled If EADC 1 the A D converter interrupt is enabled Semiconductor Group 7 6 1997 08 01 SIEMENS Interrupt System C505 C505C 7 1 2 Interrupt Request Control Flags Special Function Register TCON Address 884 Reset Value 00H MSB LSB Bit No 8Fy 8Ey 8Dy 8Cy 8By 8Ay 89H 88H 88H TF1 TR1 TFO TRO IE1 IT1 IEO ITO TCON ER The shaded bits are not used for interrupt control Bit Function TF1 Timer 1 overflow flag Set by hardware on timer counter 1 overflow Cleared by hardware when processor vectors to interrupt routine TFO Timer 0 overflow flag Set by hardware on timer counter 0 overflow Cleared by hardware when processor vectors to interrupt routine IE1 External interrupt 1 request flag Set by hardware when external interrupt 1 edge is detected Cleared by hardware when processor vectors to interrupt routine IT1 External interrupt 1 level edge trigger control flag If IT1 0 low level triggered
225. ture ranges SAB C505 Ta Oto 70 C SAF C505 Ta 40 to 85 C SAH C505 Ta 40 to 110 C max operating frequency TBD SAK C505 Ta 40to 125 C max operating frequency 8 MHz Semiconductor Group 1 2 1997 08 01 SIEMENS Introduction C505 C505C Vcc Vss VAREF VAGND Port 0 8 Bit Digital O XTAL1 Port 1 XTAL2 8 Bit Digital O 8 Bit Analog Inputs Port 2 RESET 8 Bit Digital O EA Port 3 ALE 8 Bit Digital O PSEN Port 4 2 Bit Digital O RXD Y Y TXDC 77 C505C only MCL03284 Figure 1 2 Logic Symbol Semiconductor Group 1 3 1997 08 01 SIEMEN Introduction S C505 C505C 1 4 Pin Configuration This section shows the pin configuration of the C505 in the P MQFP 44 package P0 4 AD4 P0 5 AD5 P0 6 AD6 P0 7 AD7 EA P4 1 RXDC P2 7 M5 P2 6 A14 P2 5 A13 ALE PSEN 33 32 31 30 29 28 27 26 25 24 23 P0 3 AD3 C4 P2 4 A12 P0 2 AD2 L3 P2 3 A11 P0 1 AD1 C4 P2 2 A10 P0 0 ADO L 1 P2 1 A9 V aper H 38 P2 0 A8 _ VAGND P1 0 ANO INT3 CCO L3 P1 1 AN1 INT4 CC1 C4 P1 2 AN2 INT5 CC2 L3 P1 3 AN3 INT6 CC3 P1 4 AN4 C O Vec Vss XTAL1 XTAL2 P3 7 RD P3 6 WR 5 6 7 8 91011 ENHA QJ or nse e x FF NO
226. tware The serial port interrupt is generated by a logical OR of flag RI and TI in SFR SCON Neither of these flags is cleared by hardware when the service routine is vectored to In fact the service routine will normally have to determine whether it was the receive interrupt flag or the transmission interrupt flag that generated the interrupt and the bit will have to be cleared by software Semiconductor Group 7 11 1997 08 01 SIEMENS Interrupt System C505 C505C 7 1 3 Interrupt Priority Registers The lower six bits of these two registers are used to define the interrupt priority level of the interrupt groups as they are defined in table 7 1 in the next section Special Function Register IPO Address A9j Special Function Register IP1 Address B9 Reset Value 00H Reset Value XX000000p MSB LSB Bit No 7 6 5 4 3 2 1 0 A94 OWDS WDTS IPO 5 IPO 4 IPO 3 IPO 2 IPO 1 IPO 0 IPO Bit No 7 6 5 4 3 2 1 0 Boy IP1 5 IP1 4 IP1 3 IP1 2 IP1 1 IP1 0 IP1 The shaded bits are not used for interrupt control Bit Function IP1 x Interrupt group priority level bits x 0 5 see table 7 1 IPO x IP1 x IPO x Function 0 0 Interrupt group x is set to priority level O lowest 0 1 Interrupt group x is set to priority level 1 1 0 Interrupt group x is set to priority level 2 1 1 Interrupt group x is set to priority leve
227. ue 00H Bit No MSB LSB 7 6 5 4 3 2 1 0 8Fy 8Ey 8DyH 8CH 8By 8AH 89H 88H 88H TF1 TR1 TFO TRO IE1 IT1 IEO ITO TCON SS The shaded bits are not used for controlling timer counter 0 and 1 Bit Function TRO Timer O run control bit Set cleared by software to turn timer counter 0 ON OFF TFO Timer 0 overflow flag Set by hardware on timer counter overflow Cleared by hardware when processor vectors to interrupt routine TR1 Timer 1 run control bit Set cleared by software to turn timer counter 1 ON OFF TF1 Timer 1 overflow flag Set by hardware on timer counter overflow Cleared by hardware when processor vectors to interrupt routine Semiconductor Group 6 17 1997 08 01 SIEMENS On Chip Peripheral Components C505 C505C Special Function Register TMOD Address 894 Reset Value 00H Bit No MSB LSB 7 6 5 4 3 2 1 0 89 Gate C T Mf MO Gate C T Mf MO TMOD Timer 1 Control Timer 0 Control Bit Function GATE Gating control When set timer counter x is enabled only while INT x pin is high and TRx control bit is set When cleared timer x is enabled whenever TRx control bit is set C T Counter or timer select bit Set for counter operation input from Tx input pin Cleared for timer operation input from internal system clock M1 Mode select bits MO z M1 MO Function 0 0 8 bit timer counter THx operates as 8 bit timer counter TLx serves a
228. unt matches the stored compare value Figure 6 19 and figure 6 20 show functional diagrams of the timer compare register port latch configuration in compare mode 1 In this function the port latch consists of two separate latches The upper latch which acts as a shadow latch can be written under software control but its value will only be transferred to the output latch and thus to the port pin in response to a compare match Note that the double latch structure is transparent as long as the internal compare signal is active While the compare signal is active a write operation to the port will then change both latches This may become important when driving timer 2 with a slow external clock In this case the compare signal could be active for many machine cycles in which the CPU could unintentionally change the contents of the port latch A read modify write instruction will read the user controlled shadow latch and write the modified value back to this shadow latch A standard read instruction will as usual read the pin of the corresponding compare output Semiconductor Group 6 36 1997 08 01 SIEMENS On Chip Peripheral Components C505 C505C Compare Register Circuit Compare Reg Internal JI Bus 1E Write t i 16 Bit Match Latch Timer Register Timer Circuit Port Circuit Read Latch Read Pin MCS02662 Figure 6 19 Port Latch in Compare Mode 1 Compa
229. ure register is compared with the contents of the timer register If the count value in the timer register matches the stored value an appropriate output signal is generated at a corresponding port pin and an interrupt is requested The contents of a compare register can be regarded as time stamp at which a dedicated output reacts in a predefined way either with a positive or negative transition Variation of this time stamp somehow changes the wave of a rectangular output signal at a port pin This may as a variation of the duty cycle of a periodic signal be used for pulse width modulation as well as for a continually controlled generation of any kind of square wave forms Two compare modes are implemented to cover a wide range of possible applications The compare modes 0 and 1 are selected by bit T2CM in special function register T2CON In both compare modes the new value arrives at the port pin 1 within the same machine cycle in which the internal compare signal is activated The four registers CRC CC1 to CC3 are multifunctional as they additonally provide a capture compare or reload capability CRC register only A general selection of the function is done in register CCEN Please note that the compare interrupt CCO can be programmed to be negative or positive transition activated The internal compare signal not the output signal at the port pin is active as long as the timer 2 contents is equal to the one of the appropriate com
230. value from port 3 pins while ANL P3 40AAH reads from the latch modifies the value and writes it back to the latch It is not obvious that the last three instructions in table 6 3 are read modify write instructions but they are The reason is that they read the port byte all 8 bits modify the addressed bit then write the complete byte back to the latch Table 6 3 Read Modify Write Instructions Instruction Function ANL Logic AND e g ANL P1 A ORL Logic OR e g ORL P2 A XRL Logic exclusive OR e g XRL P3 A JBC Jump if bit is set and clear bit e g JBC P1 1 LABEL CPL Complement bit e g CPL P3 0 INC Increment byte e g INC P4 DEC Decrement byte e g DEC P5 DJNZ Decrement and jump if not zero e g DJNZ P3 LABEL MOV Px y C Move carry bit to bit y of port x CLR Px y Clear bit y of port x SETB Px y Set bit y of port x The reason why read modify write instructions are directed to the latch rather than the pin is to avoid a possible misinterpretation of the voltage level at the pin For example a port bit might be used to drive the base of a transistor When a 1 is written to the bit the transistor is turned on If the CPU then reads the same port bit at the pin rather than the latch it will read the base voltage of the transitor approx 0 7 V i e a logic low level and interpret it as 0 For example when modifying a port bit by a SETB or CLR instruction another bit
231. vement of multiple data pointers in a table transfer from the code memory to external data memory Start address of ROM source table 1FFFH Start address of table in external RAM 2FA0H Semiconductor Group 4 7 1997 08 01 External Bus Interface E SIEMENS C505 C505C Example 1 Using only One Datapointer Code for a C501 Initialization Routine MOV LOW SRC PTR 0FFH MOV HIGH SRC_PTR 1FH MOV LOW DES PTR 0A0H MOV HIGH DES PTR 2FH Initialize shadow variables with source pointer Initialize shadow variables with destination pointer Table Look up Routine under Real Time Conditions Number of cycles PUSH DPL Save old datapointer 2 PUSH DPH 2 MOV DPL LOW SRC_PTR Load Source Pointer 2 MOV DPH HIGH SRC_PTR 2 INC DPTR Increment and check for end of table execution time CJNE not relevant for this consideration MOVC A DPTR Fetch source data byte from ROM table 2 MOV LOW SRC_PTR DPL Save source_pointer and 2 MOV HIGH SRC_PTR DPH load destination pointer 2 MOV DPL LOW DES PTR 2 MOV DPH HIGH DES PTR 2 INC DPTR Increment destination pointer ex time not relevant MOVX DPTR A Transfer byte to destination address 2 MOV LOW DES PTR DPL Save destination pointer 2 MOV HIGH DES PTR DPH 2 POP DPH Restore old datapointer 2 POP DPL 2 Total execution time machine cycles 28 Semiconductor Group 4 8 1997 08 01 SIEMENS External Bus Interface C505 C505C Example
232. ver generate or reset an interrupt To update the INTID value the status partition of the control register must be read 02 Message 15 interrupt Bit INTPND in the message control register of message object 15 last message has been set The last message object has the highest interrupt priority of all message objects 1 2 N Message N interrupt Bit INTPND in the message control register of message object N has been set N 1 14 Note that a message interrupt code is only displayed if there is no other interrupt request with a higher priority 1 Bit INTPND of the corresponding message object has to be cleared to give messages with a lower priority the possibility to update INTID or to reset INTID to OO idle state Semiconductor Group 6 93 1997 08 01 SIEMENS On Chip Peripheral Components C505C Only 6 4 7 CAN Controller in Power Saving Modes Idle mode In the idle mode of the C505C the CAN controller is fully operable When a CAN controller interrupt becomes active and the CAN controller interrupt is enabled the C505C restarts returns to normal operation mode and starts executing the CAN controller interrupt routine Slow Down Mode When the slow down mode is enabled the CAN controller is clocked with the reduced system clock rate 1 32 of the nominal clock rate Therefore also the CAN bit timing in slow down mode is reduced to 1 32 of the bit timing in normal mode The slow down mode can b
233. ving Modes 2 ii ex C505 C505C 9 Power Saving Modes The C505 provides two basic power saving modes the idle mode and the power down mode Additionally a slow down mode is available This power saving mode reduces the internal clock rate in normal operating mode and it can be also used for further power reduction in idle mode 9 1 Power Saving Mode Control Registers The functions of the power saving modes are controlled by bits which are located in the special function registers PCON and PCON1 The SFR PCON is located at SFR address 874 PCON1 is located in the mapped SFR area RMAP 1 at SFR address 884 Bit RMAP which controls the access to the mapped SFR area is located in SFR SYSCON B1 p The bits PDE PDS and IDLE IDLS located in SFR PCON select the power down mode or the idle mode respectively If the power down mode and the idle mode are set at the same time power down takes precedence Furthermore register PCON contains two general purpose flags For example the flag bits GFO and GF1 can be used to give an indication if an interrupt occurred during normal operation or during an idle For this an instruction that activates idle can also set one or both flag bits When idle is terminated by an interrupt the interrupt service routine can examine the flag bits Special Function Register PCON Address 874 Reset Value 00H Bit No MSB LSB 7 6 5 4 3 2 1 0 874 SMOD PDS IDLS SD GF1 GFO PDE IDLE PCON
234. watchdog The reload register WDTREL can be written to at any time as already mentioned Therefore a periodical refresh of WDTREL can be added to the above mentioned starting procedure of the watchdog timer Thus a wrong reload value caused by a possible distortion during the write operation to the WDTREL can be corrected by software 8 1 5 Watchdog Reset and Watchdog Status Flag If the software fails to refresh the watchdog in time an internally generated watchdog reset is entered at the counter state 7FFCp The duration of the reset signal then depends on the prescaler selection either 8 cycles or 128 cycles This internal reset differs from an external one only in so far as the watchdog timer is not disabled and bit WDTS watchdog timer status bit 6 in SFR IPO is set Figure 8 2 shows a block diagram of all reset requests in the C505 and the function of the watchdog status flags The WDTS flag is a flip flop which is set by a watchdog timer reset and cleared by an external HW reset Bit WDTS allows the software to eamine from which source the reset was activated The watchdog timer status flag can also be cleared by software OWD Reset Request WDT Reset Request IPO A9 4 owspwos I I LI IL H sworo reat Reset nization RESET Clear External HW Reset Request Internal Bus MCT03307 Figure 8 2 Watchdog Timer Status Flags and Reset Requests Semiconductor Group 8
235. wer Control Register 1 88H OXXOXXXXg 9 Modes 1 Bit addressable special function registers 2 This special function register is listed repeatedly since some bits of it also belong to other functional blocks 3 X means that the value is undefined and the location is reserved 4 SFR is located in the mapped SFR area For accessing this SFR bit RMAP in SFR SYSCON must be set Semiconductor Group 1997 08 01 SIEMENS Memory Organization C505 C505C Table 3 2 Special Function Registers Functional Blocks cont d Block Symbol Name Address Contents after Reset CAN CR Control Register F700H Otg Controller SR Status Register F701 XXH C505C IR Interrupt Register F702u XXH BTRO Bit Timing Register Low F704H UUH BTR1 Bit Timing Register High F705H OUUUUUUUg GMSO Global Mask Short Register Low F706 UUg GMS1 Global Mask Short Register High F707 UUU1111158 UGMLO Upper Global Mask Long Register Low F708y UUH UGML1 Upper Global Mask Long Register High F709 UUH LGMLO Lower Global Mask Long Register Low F70AW UU LGML1 Lower Global Mask Long Register High F70By UUUUUOO00g UMLMO Upper Mask of Last Message Register Low F70Cj UUH UMLM1 Upper Mask of Last Message Register High F70Dy UUH LMLMO Lower Mask of Last Message Register Low F70Ep UUH LMLM1 Lower Mask of Last Message Register High F70FH UUUUUO00g Message Object Registers MCRO Message Control Register Low F n0j 9
236. which can be cleared to disable all interrupts at once Generally after reset all interrupt enable bits are set to 0 That means that the corresponding interrupts are disabled The IENO register contains the general enable disable flags of the external interrupts O and 1 the timer interrupts and the USART interrupt Special Function Register IENO Address A8p Reset Value 00H MSB LSB BitNo AFy AEQ ADyY ACY ABu AAY A94 AH A8H EA WDT ET2 ES ET1 EX1 ETO EXO IENO The shaded bits are not used for interrupt control Bit Function EA Enable disable all interrupts If EA 0 no interrupt will be acknowledged If EA 1 each interrupt source is individually enabled or disabled by setting or clearing its enable bit ET2 Timer 2 overflow external reload interrupt enable If ET2 0 the timer 2 interrupt is disabled If ET2 1 the timer 2 interrupt is enabled ES Serial channel USART interrupt enable If ES 0 the serial channel interrupt 0 is disabled If ES 1 the serial channel interrupt 0 is enabled ET1 Timer 1 overflow interrupt enable If ET1 0 the timer 1 interrupt is disabled If ET1 2 1 the timer 1 interrupt is enabled EX1 External interrupt 1 enable If EX1 0 the external interrupt 1 is disabled If EX1 1 the external interrupt 1 is enabled ETO Timer 0 overflow interrupt enable If ETO 0 the timer O interrupt is disabled If ETO 1 the tim
237. xecution starts at location 0000 After reset is internally accomplished the port latches of ports 0 to 4 default in FFH This leaves port 0 floating since it is an open drain port when not used as data address bus All other I O port lines ports 1 3 and 4 output a one 1 Port 2 lines output a zero or one after reset if the EA is held low or high The internal SFRs are set to their initial states as defined in table 3 2 The contents of the internal RAM and XRAM of the C505 are not affected by a reset After power up the contents are undefined while it remains unchanged during a reset if the power supply is not turned off Semiconductor Group 5 2 1997 08 01 SIEMENS System Reset C505 C505C 5 2 Fast Internal Reset after Power On The C505 uses the oscillator watchdog unit for a fast internal reset procedure after power on Figure 5 1 shows the power on sequence under control of the oscillator watchdog Normally the devices of the 8051 family do not enter their default reset states before the on chip oscillator starts The reason is that the external reset signal must be internally synchronized and processed in order to bring the device into the correct reset state Especially if a crystal is used the start up time of the oscillator is relatively long typ 10 ms During this time period the pins have an undefined state which could have severe effects especially to actuators connected to port pins In the C505 the oscillator wat
238. y The same is true if a pin is used as bidirectional line and the external circuitry is switched from output to input when the pin is held at 0 and the load then exceeds the p2 drive capabilities If the load exceeds the pin can be forced to 1 by writing a 0 followed by a 1 to the port pin Semiconductor Group 6 10 1997 08 01 SIEMENS On Chip Peripheral Components C505 C505C 6 1 3 2 Type C Port Driver Circuitry Figure 6 7 shows the port driver circuit of the type C mixed digital analog I O port 1 lines of the C505 The analog function is selected by the bits in the SFR P1ANA When analog function is selected all output driver transistors p1 p2 p3 and n1 are switched off Delay 1 State Vcc A 1 1 2 D eo gt 1 Port Pin K e Enable Analog Input Input Data p 4 O Bits of SFR P1ANA Read Pin to A D Converter MCT03295 Figure 6 7 Driver Circuit of Type C Port Pins Semiconductor Group 6 11 1997 08 01 SIEMENS On Chip Peripheral Components C505 C505C 6 1 4 Port Timing When executing an instruction that changes the value of a port latch the new value arrives at the latch during S6P2 of the final cycle of the instruction However port latches are only sampled by their output buffers during phase 1 of any clock period during phase 2 the output buffer holds the value it noticed during the

C505 C505 C

Contents

Download Pdf Manuals

Related Search

Related Contents