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ST10166 16-BIT MCU USER MANUAL

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2. 5 25 MDL Multiply Divide Register Low Portion 5 25 MDC Multiply Divide Control 5 26 ONES Constant Ones Register 5 26 ZEROS Constant Zeros Register 2 222 4 5 26 6 INSTRUCTION SET OVERVIEW 6 1 6 1 1 6 1 2 6 1 3 6 1 4 6 1 5 6 1 6 6 1 7 6 1 8 6 1 9 6 1 10 6 1 11 6 1 12 6 1 13 6 2 6 2 1 6 2 2 6 2 3 6 2 4 6 2 5 6 3 SUMMARY OF INSTRUCTION 5 5 6 1 Arithmetic Instructions ee cete cho elds Poe ER da one 6 1 Logical Instr ctions 5 nee o 6 1 Boolean Bit Manipulation Instructions 6 1 Compare and Loop Control 6 1 Shift and Rotate rrene nenene reene 6 2 Prioritize INStruCtiom 23533205605 essed sees eee Ode t UM D 6 2 Data Movement Instructions 22 6 2 System Stack Instructions
3. 1 2 High Performance Branch Call and Loop Processing 1 2 Consistent and Optimized Instruction Formats 1 8 Programmable Multiple Priority Interrupt Structure 1 8 s tu eee dde ped lee p E e ed 1 4 TO BIL 1 4 INSTRUCTION DECODING e rer b Ee CENTER 1 4 ARITHMETIG AND LOGIG UNIT Ee dette odd 1 4 e eet ibt theo dia 1 4 Peripheral Event Controller and Interrupt Control 1 4 Internal RAM 7 727 E E 1 4 Internal Program Memory IRI Hee 1 4 Clock Generator EO PEG Pts E ER IRI UE Up IR Us 1 6 Peripherals and Ports steer ep dee eden ee ete 1 6 2 SYSTEM DESCRIPTION 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 2 10 MEMORY ORGANIZATION e eene eene 2 2 EXTERNAL BUS CONTROLLER esee 2 2 CENTRAL PROCESSING UNIT CPU see 2 2 INTERRUPT SYSTEM o e ek TDI He oe 2 4 CAPTURE COMPARE CAPCOM UNIT 2 4 GENERAL PURPOSE TIMER GPT UNIT 2 5 A D CO
4. 2 2 22 222 6 2 Jump and 5 22 2 6 2 Return Instruction oett eodem tese DUREE ROTE 6 2 System Control Instructions 2 2 2 1 6 2 MiscellaneOUs ceo e ad 6 3 Software Instruction Set 7227 6 3 ADDRESSING MODES scs eerta gd ec e d e S 6 3 Constants o ots 6 3 Short Addressing Modes ttc i 6 4 Long Addressing sse eene nennen 6 5 Indirect Addressing 2222 00 6 6 Branch Target Addressing Modes 6 7 CONDITION CODE SPECIFICATION 22 2 2 6 8 Ey SGS THOMSON 6 MICROELECTRGNICS GENERAL INDEX 7 INTERRUPT AND TRAP FUNCTION 7 1 7 2 7 2 1 7 2 1 1 7 2 1 2 7 2 2 7 2 2 1 7 2 2 2 7 2 3 7 2 3 1 7 2 3 2 7 2 3 3 7 2 4 7 2 4 1 7 2 4 2 7 2 4 3 7 2 5 7 2 6 7 2 7 7 3 7 3 1 7 3 2 7 3 2 1 7 3 2 2 7 3 2 3 7 3 2 4 7 3 2 5 7 3 2 6 7 3 2 7 7 3 2 8 INTERRUPT SYSTEM STRUCTURE 222 2 20
5. B 12 C APPLICATION EXAMPLE EXTERNAL BUS AND MEMORY C 1 CALCULATION OF THE USER SELECTABLE BUS TIMING PARAMETERS C 6 D APPLICATION NOTE PROGRAMMING FLASH MEMORY D 1 E EXAMPLE BOOT STRAP LOADER E 1 F DATASHEETS ST10F166 ST10166 and ST10R166 11 565 50 AJ M INTRODUCTION The rapidly growing area of embedded control applications represents one of the most time critical operating environments for today s microcontrollers Complex control algorithms must be processed based on a large number of digital as well as analog input signals and the appropriate output signals must be generated within a defined minimum response time With the increasing complexity of embedded control applications a significant increase in CPU performance and peripheral function ality over conventional 8 bit controllers is required of microcontrollers Driven by the non volatile FLASH memory technology developed internally by SGS THOMSON Microelectronics the new ST10 family of 16 bit CMOS microcontrollers achieves this high perform ance goal The ST10 family offers a 16 bit core FLASH ROM and RAM capabilities and advanced peripheral functions The real 16 bit core of the ST10 family combines the advantages of both RISC and CISC processors It
6. VROO1627 Ey SGS THOMSON 3 84 MICROELECTRGNICS A Ivotpux tiov Let 17 This part specifies the format of the instructions as it is represented in the ASM166 assembler listing QQ Figure A 1 shows the reference between the in struction format representation of the assembler py and the corespondinginternal organization of such an instruction format nibble 4 bits Symbols are used as follows to describe the in 77 struction formats 00h through FFh 0 1 4 84 Instruction Opcodes Constant Values Each of the 4 characters immediatelyollowing colon represents a single bit 2 bit short GPR address Rwi 2 bit code segment number seg 3 bit immediate constant data3 4 bit condition code specifi cation cc 4 bit short GPR address Rwn or Rbn 4 bit short GPR address Rwm or Rbm 4 bit position of the source bit within the word specified by QQ 4 bit position of the destin ation bit within the word specified by ZZ RR THE THE THE 4 bit immediate constant data4 8 bit word address of the source bit bitoff 8 bit relative target address word offset rel 8 bit word address reg 8 bit word address of the destination bit bitoff 8 bit immediate constant data8 8 bit immediate constant 8 16 bit address mem or caddr low
7. MEMOP Y FLASHP prog add Ip cnt 01h inc rementtheal go loop counter cmp Ipcnt ZMAXLOOP1 com pare to the limit jmpr cc Z prg fail jump if limit has b een reach ed mov addrev dat al pro gramning commad even word mov addrev dat ah pro gramning commad odd word waitpr mov fc rrd FCR read FCR jb busy wait pr jump if pro gramning is note nded TESTVPP jb vpp fail jump if FCVPP is set to know if a fail occured because VPP did not havetheco rrect valued uring pro gramning PROGRAMVERIFY MODE cmp first i nstru ction for PVM even calla cc UC wait 4 time out 4 us cmp daal add rev ond instr uctio nforPVM jmpr cc NZ prog jump if the word is not cor rectl y pro gramned resta rtp rogra mming cmp datah add rod first i nstru ction for PVM odd calla cc UC wait 4 time out 4 us cmp daah add rod sec ond instr uctio n forPVM jmpr cc NZ prog jump if the word is not cor y pro gramned resta rtp rogra mming EXITOF WRITE MODE mov fcrval mov FCR reset FCR and e xit write mode ret ret urn tomain program Ey SGS THOMSON 15 19 MICROELECTRONICS MEMOPY 16 T PROGRAMING ROUTNE pr o bit16p rg REGISTERS IN ITIAL IZATI ON mov mov mov mov mov mov mov mov mov Ipcnt ALLO fcrval ALLO unlock UNLOCK val fOu WAIT10 val4u WAIT4 wat_cn t AL LO
8. Lus feno ae m Cener eee Notequeandrotensorape 8 8 SGS THOMSON SGS THOMSON JJ MICROELECTRONICS CHAPTER 7 INTERRUPT AND TRAP FUNCTIONS 7 INTERRUPT AND TRAP FUNCTIONS The architecture of the ST10x166 supports several is halted for 1 instruction cycle No internal pro mechanisms for fast and flexible response to serv gram status information needs to be saved For ice requests that can be generated from various PEC service the same prioritization scheme is ap sources internal or external to the microcontrollerplied which is used for normal interrupt processing These mechanisms include PEC transfers share the 2 highest priority levels Normal Interrupt Processing Trap Functions The CPU temporarily suspends the current pro In response to the execution of certain instructions gram execution and branches to an interrupt serv trap functions are activated A trap can also be ice routine in order to service an interrupt caused externally by the Non Maskable Interrupt requesting device The current program status IP pin NMI Several hardware trap functions are pro PSW in segmentation mode also CSP is saved vided forhandlingerroneous conditions and e
9. is selectedlependingon the state of FEE bit oth erwise 0 for reading mode At 0 during reset 57 S65 THOMSON 8 MICROELECTRONICS 4 Flash Memor FLASH MEMORY PROTECTION THE WRITE MODE A programmable option set by the FLASH Pro To enter the Write mode a key code sequence of gramming Board prevents any access to the two dummy write instructions has to be performed FLASH memory from the internal RAM or External MOV Rn memory When this option isnabled the configuration of memory dspenes on The where MEM is any even absolute address in the FLASH memory space and Rn a General Purpose Registedoaded with the even address of any value Protection Opt RPROT Protect ioa within the FLASH memory address space seg ment 0 or segment 1 Yes The FWMSET bit of FCR is automatically set by NC the unlock sequence o d No Once in Write mode all read and write accessesto FCR are enabled However before performing the This bit is set at 1 during reset so any access toFIRST programming or erase operation a delay of the FLASH memory from the internal RAM or Ex 1048 must be executed The device requires this ternal memory is disabled and access to FCR is al time to set up the internal high voltage lowed only from the FLASH memory When the FLASH memory is mapped in segment To disable the protection thelfowingnstruction 0 itis recommended to disab
10. A Ivotpuxuov Let IIYXH IIYXH ov Xyoteu IIYXH OPERATION DATA TYPES FLAGS tmp c op1 SP SP 2 SP tmp WORD Moves the word specified by operand op1 to the location in the internal system stack speci fied by the Stack Pointer after the Stack Pointer has been decremented by two E 2 V Set if the value of the pushed word represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Set if the pushed word is equal to zero Cleared otherwise Not affected Not affected Set if the most significant bit of the pushed word is set Cleared otherwise m ZO lt N INSTRUCTION FORMAT PUSH BXO Taoxtivy Mvenovux Byteo PUSH reg RR 2 57 S6S THOMSON EE MICROELECTRONICS A Ivotpux tiov Let Evtep Ilowep Aowv Mode TIQPAN OPERATION Enter Power Down Mode This instruction causes the part to enter the power down mode In this mode all peripher als and the CPU are powered down until the part is externally reset To insure that this in struction is not accidentally executed it is implemented as a protected instruction To further control the action of this instruction the PWRDN instructigmy enabled when Dp non maskable interrupt piNMI is in the low state Otherwise this instruction has no effect FLAGS E 2 V C N E N
11. E amp oqurAe TOS equ OFA40h Top ofs tack 64 byte smax StartA ddres s equ OFA40h Start Address of RAMarea EndAddress equ OFDFFh End Addre ss of RAM area RamRouineS tart equnear OFA40h Start Address of RAMrouti ne REGBAS equ OFAOOh Regis ter bank decl arati on sskdef 0 Stack res ervat ion BTLCOLE section BTL_IN IT SYSOON SYSCNF initi alize system con figur ation reg ister SYS CNF Defin ed by the user DI SWDT disab le w atchd ogt imer MOV CP REGB set regis terba nk MOV SP 4 TOS set stack poi nter SGS THOMSON 34 MICROELECTRONICS Aoadep GetBau dRate W itSt artBi t P3 1 1 Wai tStar for star t bit at RXDO T6R start timer T6 WaitSt opBit P3 1 1 Wai tStop Bit wait for stop bitat RXDO T6R stop time r T6 R1 36 load divi def actor MDL T6 baudr ate T6 36 y2 1 R1 R2 MDL get divis ion resul t R2 1 round result CC Clnit Seria IPort R2 1 adjus t by one for baud ratege or nitSe rialP SOBGR2 load baudrate generator P3 1 0 initi alize TXDOou tput DP3 10 SOCN 80 11h initi alize ser ial port 0 8bit data no parit y one stop bit recei ver enabl ed SendAcknowl edge SOTBUF 5 5h send ackn owled ge byte for baudr ate check Receiv eData RO Start Addre ss Receiv eLoop SORIR Rec eiveL oop wait for rece ive inter rupt requ est RO S
12. D7h Watchdog Timer Control Register 0000h for Watchdog Timer overflow 0002h n SGS CTHIMSON 96 MICROELECTRONICS B ST10x166 Registers Address Address MU SOCON socon FFBOh 088 SerialChannel ControRegister Serial Channel 0 Control Register mem ww we 70 mem ow tee me ow temm O re ms ee _ me om tem 0212 rem pm we e Hem pum oon Lom From em Pontabnecton ConroiRegisr m rom em m Lom ree eon rem Rm ee me ee 10 16 Gr SGS THOMSON B ST10x166 Registers SPECIAL FUNCTION REGISTERS ALPHABETICAL ORDER The following table lists all SFRs which are imple Bit addressable SFRs are marked with the letter mented in the ST10x166 ialphabetial order in column Name Physical 8 Bit Description Reset Address Address Value ADCIC A D Converter End of Conversion 0000h Interrupt Control Register ADCON Du m A D Converter Control Register 0000h ADDAT FEAh son A D Converter Result Register 0000h ADDRSEL1 BEES Address Select Register 0000h ADEIC A D Converter Overrun Error Interrupt Contr6D00h Register BUSCON1 Bus Configuration Register ooh CAPREL EN GPT2 Capture Reload Register 0000h CAPCOM Register 0 Interrupt Control M EE CAPCOM Register Fon CAPCOM Register 1 Interrupt
13. i 0000h Interrupt Requests CCxIR CCxIR CCxIR COxIR TyIR t Event 1 Event 2 Event 3 Event 4 CCx cv2 CCx cv1 CCx cv2 CCx cv1 VROA1639 8 1 2 2 2 Compare Mode 1 mode 1 P2 x must be configured as output i e i i the correpondingdirection control bit DP2 x in bit leid COMODy ot ine dueponding registerDP2 must be set to T With this configura mode control register to 101b tion the initial state of the output signal can be pro grammed or its state can be modified at any time When a match between the contents of the allo py writing to bit latch P2 x However if P2 x is writ cated timer and the compare value in register CCx ten to by software at the same time it would be al is detected in this mode interrupt request flag tered by a compare event the software write will is set to 1 but also the correspling priority this case the hardwar gyered CCxIO alternate output function of Port 2 pin P2 x change will not become effective is toggled For this purpose the state of Port 2 out put latch P2 x not the pin is read inverted and then written back to the output latch mode compare mode 1 must be selected for the registers 0 to see section 8 1 2 2 5 for de Compare mode 1 allows several compare events tails on the double register mode within a single timer period An overflow of the Fi h he timi le f h timer t
14. om _ teme rm 2 16 Gr SGS THOMSON TT B ST10x166 Registers SPECIAL FUNCTION REGISTERS Ordered by Address Non Bit Addressable Special Function Registers Address Address Value Torro oon ceubwarepeFomeromegswrub om GPU pata Page Pointer regier ois prem can ceubwarepeFomerimegswrubte tom oon cpu pata Page Pointers Reiser ois _ om GPU code Segment Pointer Register read on oom rw e con cuwupypwiemegser gnwos em Regier Lowwora ooon om cpu comempoimer reger Foon se remm cru system scxPomernegater sov reum oan cpu suck Overtow Pointer neger Fern omn cpu stack undertowPoinerRegitr aooe rinm oon Address me wm m rem am Wem Cm rem Lm rem cmmmesmsse Cm rum Gom Lm rem Som reus me m wee 77 me m we Ey SGS THOMSON 3 16 MICROELECTRONICS B ST10x166 Registers Address WIN TO 28h CAPCOMTimerORegister CAPCOM Timer 0 Register oh ee a eee Lon capcom Timer o Reload Reg
15. Eu memory mode is se The ClockOutput function is enabled by setting the CLKEN bit of the SYSCON register to 1 If en abled port pin P3 15 takes on its alternate function 5 3 1 7 MAXIMUM SYSTEM STACK SIZE SELEC as CLKOUT output pin The Clock Output is a 50 TION VIA STKSZ duty cycle clock whose frequency is half the oscil The maximum size of the system stack is directly lator frequency fosc 2 Fora 40MHz clock determined by the two bit field STKSZ as shown in oscillator the CLKOUT frequency is 20MHz table below Note that it is the user s responsibility to set the di rection of the CLKOUT pin to output and to write a Table 5 4 Maximum System Stack Size T into port latch P3 15 before using this function After reset the Clock Output functiordisabled 00b 256 words 5 3 1 6 NON SEGMENTED MEMORY MODE SELEC 01b 128 words TION VIA SGTDIS 10b 64 words The SGTDIS bit allows selecting either the seg AP 92 words mented or non segmented memory mode In the 1 the entire address space is restricted to 64 diately affect the physical stack addregsnera Kbytes segment 0 and thus all addresses can be tion via the SP register described in section 5 3 9 represented by 16 bits Thus the contents of the After reset the maximum stack size of 256 word lo CSP register are totally ignored and only the two cations is selected by default least significant bits of the DPP registers ar
16. o MICROELECTRGNICS A Ivotpux tiov Let 2 3 DATA TYPES But PieAd Byte tmp c 1 low byte tmp Y low byte tmp op2 v op3 op1 tmp WORD Replacesthose bits in the low byte of the destination word operand op1 which are selected by an 1 in the AND mask op2 with the bits at therespondingpositions in the OR mask specified by op3 Note Bits which are masked off by a 0 in the AND mask op2 may be uninteatty al tered if the corresponding bitin the OR mask op3 contains 1 FLAGS E 2 V C N E Always cleared Z Set if the word result equals zero Cleared otherwise V Always cleared C Always cleared Setif the most significant bit of the word result is set Cleared otherwise INSTRUCTION FORMAT BXO Taoxivy Mvenoviy Mvenuovy Onepav o Byteo BFLDL BFLDL bito f mask data QQ 4 16 84 S amp S THOMSON A Ivotpuxuov BMOc BMOc Bit Moe onl 2 OPERATION 1 2 DATATYPES Moves a single bit from the source operand specified by op2 into the destinp oand specified by op1 The source bit is examined and the flags are updated FLAGS E 2 V E Always cleared Z Contains the logical negation of the previous state of the source bit V Always cleared C Always cleared Contains the previous sta
17. the run flags of TO 3 1 1 1 TIMER MODE and T1 respectively They allow fenablingand disablingthe timers Thefollowingdescription of Bits TOM and T1M uud H pid e is the timer modes and operation alwagppliesto Uer or counter mode for or T1 respectively In timer mode TOM 0 or T1Mz 07 the input clock the enabledstate of the timers i e when both TOR f and T1R are set to 1 or a timer is derived from the internal system clock divided by a programmable prescaler The differ ent options for the prescaler are selected sepa rately for TO and T1 by the bit fields TOI and T11 The inputfequenciesfro and fr1 for TO and T1 TO1CON FF50h determined as a function of the oscillator frequency CAPCOM Timer 0 and 1 Control Register as follows where lt 01 gt and lt T1I gt represent the Reset Value 0000h contents of the bit fields and T11 15 14 13 12 1 10 9 8 is fosc fr __lose r 16 x 2570 16 x 25711 6 5 4 3 2 0 When a timer overflows from FFFFh to 0000h it is tor reloaded wih the value stored in its respective re load register TOREL or T1REL The reload values b15 b13 b12 b7 b5 b4 H Reserved determine the periods 18 and between two b14 T1R Timer Counter 1 Run Bit consecutive overflows of TO and T1 as follows If setat 1 will enable the Timer Counter 1 b11 1 Timer Counter 1 Mode Selectio
18. 18 still ON by the Hon cation 0000h in code segment zero Here 656 sequence Is completed the sequence wi start again This procedure continues until a high would normally place a branch instruction to the start ofa software initialization routineforappli Vel isfound at thBSTIN pin at the end of a reset cation specific configuration p ripheralsand Sequence CPU Special Function Registers The RSTOUT pin will be pulled low after a hard ware reset signal has been asserted on tRSTIN ed pin It is also pulled low whenever the SRST 11 1 RSTIN and RSTOUT Pins struction is executed or a Watchdog Timer over mper flow has occurred The signal on tRSTOUT pin Two pins RSTIN Reset In andRSTOUT Reset be used to simulheouslyreset external hard Out are dedicated to the system reset function of ware whenever the ST10x166 is reset The the ST10x166 TheRSTIN pin is used for resetting RSTOUT pin stays low until the protected EINIT the microcontroller through an external hardware End of Initialization instruction is executed Fig reset signal To perform a complete reset se ure 11 2 shows the relation between tIRSTIN quence the ST10x166 requires 1040 state times and theRSTOUT signal 52us at 20MHz CPU clock witlRSTIN low 1 4 11 System Reset Figure 11 1 Reset Circuits ST10x166 External HW Reset RSTOUT Reset Source 1 Reset Source 2 External HW Reset RSTOUT
19. 212 50 71 0 currently 16 pages of 16 Kbytes each The DPP registers are implicitly used whenever data accessesto any memory space are made via indirect or direct long 16 bit addressing modes eo 01 cept for PEC data transfers After reset the Data ata Page Pointer Registers Page Pointers ardnitializedn a way that all indi Reset Value 0001h rect or direct long 16 bit addresses result identi 45 13 12 11 10 9 8 cal 18 bit addresses This allows accessing data pages 0 to 3 in segment 0 as shown figure 5 6 If the user does not want to use any data paging no 6 5 4 3 2 1 0 further action is required Data paging is performed by extending the lower 14 bits of indirect or direct long 16 bit addresses by the contents of a DDP register as shown in figure ppp FEO4h 02h 5 7 The two MSBs of the 16 bit address are inter preted as the number of the DPP register which is Data Page Pointer Register to beused for the address extension The contents Reset Value 0002h of nes ed 15 14 13 12 11 10 9 8 rently sixteen possible data pages This 4 page number in addition to themaining14 bit page offset address forms the physical 18 bit ad 7 6 5 4 3 2 1 0 open In the case of the non segmented memory mode only thetwo least significant bits of the implicitly
20. Figure 16 External Memory Write Cycle te t25 A17 A16 EL BHE t27 C in to i t23 22 VROCIB17 12 17 S amp S THOMSON C AE ST10F166 AC CHARACTERISTICS Continued Non Multiplexed Bus with Read Write Delay Ta 0 to 70 C 5 V 10 Vss 0 V for Ports 0 1 and 4 ALE RD WR CLKOUT 1 00pF ALE cycle time 4TCL 100ns at 20MHz CPU clock CPU Clock Variable Timing Symbol Parameter 20MHz 1 TCL 2 to 40MHz 15 ns ALE High Time TCL 10 Address Setupto ALE TCL 15 ALE Falling Edge to RD WR TCL 10 RD WR Low Time 2TCL 10 RD to Valid Data In ALE Low to Valid Data In Address to Valid Data In Data Hold after RD Rising Edge Data Float after RD Data Valid to WR 2TCL 15 Data Hold after WR TCL 10 ALE rising edge after RD WR 10 Address Hold after RD WR 0 This time may be longer if no external bus conflict can occur For example this requirement is always metif only code but no data are accessed externally n SGS CTHIMSON 7 MICROELECTRONICS ST10F166 Figure 17 External Memory Read Cycle A17 A16 15 0 BHE VROD1617 Figure 18 External Memory Write Cycle A17 A16 15 0 Coron t22 t24 VRDE1617 14 17 k S amp S THOMSON AE ST10F166 AC CHARACTERISTICS Continued Non Multiplexed Bus without Read Write Delay Ta 0 to 70 C
21. iw 1 IR Flag 2 Interrupt Response Time Whenever thepipelineis advanced and a new in flag is set during the first state of an instruction cy struction cycle is started all sources whose inter cle the minimum interrupt response time under rupt request flags have been set during the these conditions is 6 state times 300ns at 40MHz previous cycle compete for service in a round general all delays with respect to the standard prioritization In the next cycle a TRAP is per instruction execution time which may occur during formed to the vector location of tw nningsource execution of instructions in the pipeline may result and the source s interrupt request flag is reset toin a longer interrupt response time Wen internal 0 Fetching of the instruction 1 at the vector loca noiq conditions between instruction pairs N 2 N 1 tion is started in thfollowing ycle All instructions N 1 N occur or instruction explicitly writes to that are in the pipeline at the time the interrupt re the PSW the minimum interrupt response time quest flag is set will be completed before the inter may be extended by 1 state time for each of these rupt service routine while tiellowing insuction conditions When instruction N reads aperand N 1 will be executed after return from the interrupt from the internal ROM or when Nis a call return service routine As can be seen from figure 7 8 tran or MOV Rn Rm data16 instruction t
22. 1 and the For an overview of the resulting gate is active resolution and periods when using a 40MHz oscil Pin to D 27 The _ ock diagram of aauxiliarytimer in timer mode is 8 2 1 2 1 Timer Mode shown it indollowindiqure 6 20 The operation of the auxiliary timers in this mode is identical to that of the core timer T3 Timer mode is Figure 8 20 Block Diagram of an Auxiliary Timer in Timer Mode Auxiliary Timer Tx oiii VRDC1641 28 64 Gr SGS THOMSON TT 8 Peripherals 8 2 1 2 2 Gated Timer Mode The gated timer mode for the auxiliary timers func for timer T4 T2IN is an alternate function of P3 7 tions as described for the core timer For the auxil while T4IN is an alternate function of P3 5 In order iary timers an active low level for the gate is to use these alternate functions the selected by setting the mode control fields T2M or direction control bits DP3 7 and DP3 5 must be set TAM to 010b and an active high level is selected to 0 Figure 8 21 shows a block diagram of an by the bit ombinatiori011b The gate fortimer T2 auxiliaryimer in gated timer mode is the external input pin T2IN and TAIN is the gate Figure 8 21 Block Diagram of an Auxiliary Timer in Gated Mode Interrupt T Auxiliary Timer Tx Request x 2 4 vROD1641 e P3 7 P3 5 8 2 1 2 3 Counter Mode Basically the counter m
23. Counter T2 T4 is Incremented Decremented on ewanaiton Sessa Troiae ef o n To 0 wemwetwemsTamononn 0 s o e 3 o9 C esmemimeseTaeens OR Figure 8 22 Block diagram of an Auxiliary Timer in Counter Mode Source Edge Select or Auxiliary Timer Tx Interrupt Request P3 7 P3 5 x 2 4 1 VROE1641 concatenating the core timer and amixiliay clocked on every second overflow underflow of the timer Dependingon which transition of TSOTL is core timer This configuration forms 33 bit timer selected to clock the auxiliary timer one can forma 16 bit core timer T3OTL 16 bauxiliarytimer 32 bit or 33 bit timer This iexplainedin the fol count directions of the two concatenated tim lowing ers are not required to be the same This offers If both a positive and a negative transition of wide variety of different configurations A block dia TSOTL is used to clock the auxiliary timer this gram showing the concatenation of a core timer timer is clocked one very overflow underflow of theand an auxiliary timer is shown in Figure 8 23 core timer T3 Thus the two timers form a 32 bit timer If eithera positive or a negative transition of T3OTL is selected to clock thauxiliaryimer this timer is 30 64 Gr SGS THOMSON TT 8 Peripherals Figure 8 23 Concatenation of Core Timer T3
24. LESS RXDO P3 11 SOTBUF TXDO0 P3 10 RXD1 P3 9 TXD1 P3 8 50 64 SORBUF 5186 SITBUF SIRBUF VROD1 640 Port 3 Direction Control Register Port 3 Data Register Serial Channel 0 Baud Rate Generator Reload Register Serial Channel 0 Transmit Buffer Register write only Serial Channel 0 Receive Buffer Register read only Serial Channel 1 Baud Rate Generator Reload Register Serial Channel 1 Transmit Buffer Register write only Serial Channel 1 Receive Buffer Register read only Serial Channel 0 Control Register Serial Channel 1 Control Register Serial Channel 0 Transmit Interrupt Control Register Serial Channel 0 Receive Interrupt Control Register Serial Channel 0 Error Interrupt Control Register Serial Channel 1 Transmit Interrupt Control Register Serial Channel 1 Receive Interrupt Control Register Serial Channel 1 Error Interrupt Control Register SGS THOMSON MICROELECTRONICS 8 Peripherals on chip Serial Channel 0 ASCO and Serial Chan nel 1 ASC1 They support full duplex asynchro nous communication up to 625KBaud and half duplex synchronous communication up to 2 5MBaud In the synchronous mode data are transmitted or received synchronous to a shift clock which is generated by the ST10x166 In the asynchronous mode 8 or 9 bit data transfer parity generation and the number of stop bits can be se lected The reception of data is double buffered Parity framing and overrun error detection
25. SP SP SP 2 CSP SP SP SP 2 Returns from an inter segment subroutine The IP and CSP are popped from the system stack Execution resumes at the instriact following the 5 instrution in the calling routine E 2 V Not affected Not affected Not affected Not affected Not affected 2 lt INSTRUCTION FORMAT Mvenoviy RETS 70 84 BXO Taoxtvy Mvenuoviy Onepav o Byteo RET DB 00 2 S amp S THOMSON A Ivotpuxuov Let POA POA Potate POA onl 2 OPERATION count op2 0 DO WHILE count 0 C opts 1 Optn 1 n 1 to 15 opto C count count 1 END WHILE DATATYPES WORD Rotates the destination word operand op1 leftby as many times as specified by the source operand op2 Bit 15 is rotated into Bit 0 and into the Carry Only shift values between 0 and 15 areallowed When using a GPR as the count control only the least significant 4 bits are used FLAGS E 2 V E Always cleared Z Set if the result equals zero Cleared otherwise V Always cleared C The flag is set according to the last MSB shifted out of op1 Cleared for a rotate count of zero N Setif the most significant bit of the result is set Cleared otherwise INSTRUCTION FORMAT BXO Taoxtivy Mvenoviy Mvenoviy Onepav o Byteo ROL ROL Ruh RWm 0C nm 2 ROL ROL Rw data 1C n 2 57
26. d pos 32K x 16 pe OE CE cou Y P3 13 WR BUSACT P3 12 BHE Example with Byte and Word Organized Memory Devices Data Multiplexed VROB1646 4 10 Gr SGS THOMSON C Application Example Figure C 4 16 Bit Addresses 16 Bit Data Non Multiplexed Bus Configuration EBCO P1 0 15 P3 12 BHE P0 0 15 00 015 08015 ST10x166 32K x 16 i EPROM M27C516 P3 13 WR BUSACT Example with Byte and Word Organized Memory Devices Data Non Multiplexed VROC1646 Ey SGS THOMSON 5 10 MICROELECTRONICS C Application Examples C 2 CALCULATION OF THE USER SELECTABLE BUS TIMING PARAMETERS This section provides tables which ease the calcu lation of the number of the ST10x166 s wait states which must be programmed into the MCTC bit field and or MTTC bit of the SYSCON register to match the external memory timing specifications The followingparticular memory accesses are considered in this section Memory Read via a Multiplexed Bus with Read Write Delay Memory Write via a Multiplexed Bus with Read Write Delay Memory Read via a Non Multiplexed Bus with Read Write Delay Memory Write via a Non Multiplexed Bus with Read Write Delay Two types of tables existfor each of these memory accesses The tables signified by an extension contain formulas for the determination of both the maximum values of particular timing parameters at
27. put line which is tied directly to the pin This line isternal device is connected to the pin one can set used forthe synchronous Ready function the direction to output and write to the port output latch to trigger the Alternate Data Input line Figure 10 9 Block Diagram of a Port 3 Pin With an Alternate Input Function Write DP3 y Direction Latch DP3 y Read DP3 y Output P3 0 Buffer P3 2 P3 4 T3EUD P3 5 P36 Clock P3 7 T2IN P3 14 READY Read Buffer Allernale DataInput Synchronous READY Input y 2 4 5 6 7 14 Note This line only exists for Pin P3 14 READY SGs THomson mne 10 Parallel Ports 10 1 3 2 PORT 3PINS T3OUT T6OUT TXDO TXD1 functions the user must set the direction of the port WR CLKOUT line to output DP3 y 1 and must write a 1 into These six of the seven Port 3 pins which have only the port output latch Otherwise the is in its an alternate output function associated also have high impedane state when configured as input an identical structure shown in figure 10 10 The the pin is stuck at 0 when writing a 0 into the Alternate Data Output line which is controlled by Port output latch When the alternate output func the respective peripheral unit is ANDed with the tions arenot used the Alternate Data Output line is port output latch line When using these alternate in its inactive s
28. 2 1 lt gt op2 DATATYPES BYTE The source operand specified by op1 is compared to the source operand specified by op2 by performing a 2 s complement binary subtraction of op2 from op1 The flags are set ac cordi E ng to the rules of subtraction T ygerandsremainunchanged Z V Setif the value of op2 representsthe lowest possible negative number Cleared oth erwise Used to signal the end of a table Setif the result equals zero Cleared otherwise Set if an arithmetic underflow occurred i e the result can not be represented in the specified data type Cleared otherwise Setif a borrow is generated Cleared otherwise Setif the most significant bit of the result is set Cleared otherwise INSTRUCTION FORMAT 28 84 BXO Taokwy Onepav o Byteo CMP Rb Rbm 41 nm 2 CMP Rhb Rw 49 n 10ii 2 CMP Rb Rw 49 n 11ii 2 CMP Rh datas 49 n 0 2 CMP reg datac 47 RR 4 CMP reg mem 43 RR MM MM 4 none A Ivotpuxuov Let 1 1 Ivteyep avd Aexypeuevt By 1 XMIIA1 onl 2 OPERATION op1 lt 0 2 1 op1 1 DATATYPES WORD This instruction is used to enhance the performance and flexibility of loops The source op erand specified by op1 is compared to the source operand specified by op2 by performing a 2 s complement binary subtraction of op
29. ALLO mov FCR fcrv al reset FCR and e xit write mode ret ret urn tomain program wg SGS THOMsON 18 19 YF MICROELECTRGNICS MEMOPY 32 BI T PROGRAMING ROUTNE progr amming of add ress 0000Ch withO 8642h dress 000 OEh with 09753h bit32p rg REGISTER INI TIALI ZATION mov Ipcnt ALLO reseta 190 loop cou nter mov fcrval ALLO reset FCR d ata value mov unlock UNLOCK loadun lock data mov valiOu WAIT10 load10 usi oop data mov val4u WAIT4 load4 us loop data mov cn t AL LO resetw loop counter mov allt ALL1 set R2 to FFFF mov daal DATAL load data fore ven address mov datah ZDATAH load data for odd a ddres s mov addrev ZADDREV load evena ddres s mov addrod ADDROD load oddad dress UNL OCK SEQUNCE FOR ENTERNG IN THEWR ITE MODE mov FCR unlo ck firsti nstru ction mov unlock ock sec ond instr uctio n ofunlock seq uenceto enterinthe write mode calla cc UC wait 10 time out 10 us to set in terna sig nals FOR PROGRMMING bset fwe FWE 1d efine pro gramning opera tion belr ck ctlO TLO 0 belr ck ctl1 CKC TL1 0 defin 100 us pulse bset wdww WOWV 1 defin 32 bit configura tion bset fw mset FWM SET 1ena ble write mode mov FCR fcrv al load FCR set up TESTVPP mov fcrrd FCR read FCR jnb vp priv vpp fail test if VPP is high 14 19 Gr SGS THOMSON
30. Set FWMSET bit for program mode OPITE XOMMANA Perform the specific instruction to start automatically the erase process mov sca n fl scan erase command era sure star t OAIT ET The erasing time ET depends on the bits CKCTLO amp CKCTL1 of FCR see setting of FCR The end of programming be detected Ippllingon the FBUSY bit of FCR FBUSY set to 1 indicates erase is in progress FBUSY cleared indicates erase has ended XgIII 0v Test VPP to detect any discontinuity in VPP during erasure see previous section 8 19 Gr SGS THOMSON 6 IIPEXTO 9 Epaoe AXyopvtnu ALL WORDS 0000H N 0 ADDRESS 0 WRITE ERASE COMMAND TO FCR WRITE ERASE DATA ERASE VERIFY READ COMPARE DATA FFFFH INCREMENT ADDRESS WRITE FWE 0 FEE 0 ET 10ms VROA1B32 SGS THoMson 595 YF MICROELECTRONICS MEMOPY This mode equivalento the Program Verify Readjuaranteesa improved cell margin of a word Read the data at the address given by the address variable twice with the same instruction separated by a time of 4 5 XOMIIAPE Compare the data read FFFFh If it equals FFFFh this address has been erased continue verification until the last address of the block has been verified If not increment N variable Appl
31. This bit is set if the result cannot be represented in a word data type Cleared other wise C Always cleared Setif the most significant bit of the result is set Cleared otherwise N INSTRUCTION FORMAT BXO Taoxivy Mvepnovtux Onepav o Byteo MULU MULU Rw Rwm 1B nm 2 56 84 SGS THOMSO A A Ivotpuxuov XounAeuevt orl OPERATION op1 0 op1 DATA TYPES WORD Performs a binary 2 s complement of the source operand specified by op1 The result is then stored in op1 FLAGS E 2 V esL E Setifthe value of op1 represents the lowest possible negative number Cleared oth erwise Used to signal the end of a table 2 Set if result equals zero Cleared otherwise V Set if an arithmetic underflow occurred i e the result can not be represented in the specified data type Cleared otherwise C Setifa borrow is generated Cleared otherwise Setif the most significant bit of the result is set Cleared otherwise INSTRUCTION FORMAT BXO Taoxtivy Mvenuoviy Onepav o Byteo NEG NEG 81 2 57 S65 THOMSON o MICROELECTRGNICS A Ivotpux tiov Let NEI B NEI B onl OPERATION 1 0 1 DATATYPES BYTE Performs a binary 2 s complement of the source operand specified by op1 The result is then stored i
32. a fail occured because VPP did not havetheco rrect valued uring pro gramning PROGRAMVERIFY MODE cmp daal add rev first i nstru ction for PVM calla cc UC wait 4 time out 4 us cmp daal add rev sec ond instr uctio n forPVM jmpr cc NZ progw jump if the word is not cor y pro gramned resta rtp rogra mming EXITOF WRITE MODE mov fcrval mov FCR reset FCR and e xit write mode ret ret urn tomain progr am SUBROUTINES USED IN W G OPERATION add wait cn t 01 h inc rement unter cmp cn t val 4u com pare with finalv alue jmpr cc NZ wait 4 jump if not equal mov cn t ZAL LO resetc ounter ret Ey SGS THOMSON 17 19 MICROELECTRGNICS MEMOPY wait cn t 01 h inc rement co unter t val 10u com pare with finalv alue cc NZ wait 10 jump if not equal cn t ZAL LO resetc fa il VPPFAILRO UTINE DEFINED BY THE USER prg fa il PROGRAMFAIL ROUTINE DEFINED BY THE USER eras f ail ERASEF AIL ROUTINE DEFINED BY THE USER 18 19 Gr SGS THOMSON TT MEMOP Y THE SOFTWARE INCLUDED IN THIS NOTE IS FOR GUIDANCE ONLY SGS THOMSON SHALL BE HELD LIABLE FOR ANY DIRECT INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM USE OF THE SOFTWARE 57 S65 THOMSON de MICROELECTRONICS SGS THOMSON JJ MICR
33. erated by hardware and inserted at the MSB posi tion of the data frame The parity bit is set to 1 if the modulo 2 sum of the 7 data bits is 1 otherwise it is cleared even parity On reception the parity on the 7 data bits received is generated by hardware The result is then com pared to the 8th bit received which is the parity bit If the comparison proves false both the parity error flag and the error interrupt request flag for the re spective serial channel are set provided the parity check has been enabled in the serial channel s control register The actual parity bit received is placed in the 8th bit of the receive data buffer reg ister The upper byte of the receive buffer register is always zero in this mode 8 4 1 1 3 9 Bit Data Mode This mode is selected by programming the respec tive mode selection field SOM or S1M to 100b The data frame which will be transmitted consists of the lower 9 bits of the transmit buffer register On reception all 9 data bits received are trans ferred from the receive shift register to the receive buffer register and the remaining 7 bits 9 through 15 of the receive buffer register are cleared to zero The parity checking function upon reception is disabled in this mode independentof the state of SOPEN and S1PEN The overrun and framing checks however can be enabled 8 4 1 1 4 8 Bit Data Wake Up Bit Mode This is a special mode provided to facilitate multi pro
34. onl 2 OPERATION 1 lt op op2 DATATYPES WORD Performs a 2 s complement binary subtraction of the source operand specified by op2 from the destination operand specified by op1 The result is then stored in op1 FLAGS E Z V E Setifthe value of op2 represents the lowest possible negative number Cleared oth erwise Used to signal the end of a table 2 Set if result equals zero Cleared otherwise V Set if an arithmetic underflow occurred i e the result can not be represented in the specified data type Cleared otherwise C Setifa borrow is generated Cleared otherwise Setif the most significant bit of the result is set Cleared otherwise INSTRUCTION FORMAT BXO Taoxtvy Mvenoviy Onepav o Byteo SUB SUB Rw Rwm 20 nm 2 SUB SUB Rw datas 28 n 0 2 SUB SUB reg dat s 26 RR 4 SUB SUB Rw Rw 28 n 10ii 2 SUB SUB Rw Rw 28 n 11ii 2 SUB SUB reg mem 22 RR MM MM 4 SUB SUB mem reg 24 RR MM MM 4 lis A Ivotpuxuov XYBB gt Ivteyep onl 2 OPERATION 1 op1 op2 DATATYPES BYTE Performs a 2 s complement binary subtraction of the source operand specified by op2 from the destination operand specified by op1 The result is then stored in op1 FLAGS E 2 V E Setifthe value of op2 represents the lowest possible negative number Cleared oth erw
35. pare register isdisabledor programmed for a mode other than mode 1 the bank 2 register will operate in compare mode 0 interrupt only mode as described in section 8 1 2 2 1 Ey SGS THOMSON In thefollowinga bank 2 register programmed to compare mode 0 will be referred to as COurhile the correpondingbank 1 register programmed to compare mode 1 will be referred to as CCx When a match is detected for one of the two regis ters ina register pair CCx or CCz the associated interrupt request flag CCxIR or CCzIR is set to 1 and pin corresondirm to bank 1 register CCx is toggled The interrupt generated always corresponds to the register that caused the match NOTE If a match occurs simitaneouslyfor both register CCx and register CCz of the register pair pin CCxIO will be toggled only once but two sepa rate compare interrupt requests will be generated one for vector CCxINT and one for vector CCzINT In order to use P2 x CCxlO as compare signal output pin in thdouble regiter mode P2 x must be configured as output i e the cespondingii rection control bit DP2 x in register DP2 must be set to 1 With this configuration P2 x has the same characteristics as in compare mode 1 Figure 8 12 shows a functional diagram of a regis ter pair configured for thtpuble egister compare mode In this configuration example the same timer allocation was chosen for both compare reg isters buteach register
36. until the bus is tri stated again Therefore an addi tional Memory Tri State Time wait state must be in troduced before the next memory access The 1 ntroduce No States CPU is not idle during a Memory Tri State Time wait state Thus CPU operations will only be slowed down if subsequenexternal instruction or data feth operation is required durinbye next instruction cycle Figure 9 13 shows when a Mem ory Tri State Time wait state is introduced during the external memory accesses These programmable Memory Tri State Time wait states can be specified for all of the external bus configuration modes Note however that one im plicit Memory Tri State wait state is automatically added for both multiplexed external bus configura tion modes 14 200 2 n SGS THOMSON MICROELECTRONICS 9 External Bus Interface Figure 9 12 Memory Tri State Time ALE sus o Memory Tri state Time VROD1633 Figure 9 13 Memory Tri State Time Wait States 1 SEGMENT X Address l ALE Wait State VROE1633 SGS THOMSON 05 9 External Bus Interface 9 8 3 Read Write Signal Delay The ST10x166 allows the user to disable enable imi fault after reset Memory Read Writeignal The ST10x166 allows the user to adjust the timing de 272 of the data read and write output signals to accountDelays by means of the RWDC bit
37. used for program data or register banking yond the bottom of the internal memory location This basic technique allows data to be pushed untilFAO0h the data actually is pushed at the top of the overflow boundary of the internal stack isthe allocated stack space e g location FBFEh reached At this point a portion of the stacked data where 256 words have been allocated for the must be saved in the external memory to create stack Thus the internal access pointer wraps space for further stack pushes This is called stackaround the internal stack as specified by the stack flushing When executing a number of return or size in the SYSCON register The stack pointer al pop instructions the upp roundary since the ways points to the virtual location in the external stack empties upward to higher memory locations memory The boundary pointers STKOV and is reached The entrieshat have been previously STKUN also point to the external virtual stack lo saved on the external memory must now be re cations stored This is called stack filling Because tallowingprocedure is required uponitialia dure call instructions do not continue to nestiion of the controller indefinitely and return instructions are intersperse TO with calls flushing and filling normally occur very Specify inthe SYSCON register the size of the infrequently If this is not true for a given program nternal RAM to be dedicated to the system environment this
38. 001625 Figure 11 2 Reset Function Watchdog Timer Overflow or SRST Instruction Executed 11 2 RESET VALUES FOR ST10x166 REGISTERS Most SFRs includingyystem registers and periph eral control and data registers are forced to zero once the internal reset has completed This default configuration has been selected such that all pe ripherals and the interrupt system ad sabled from operation Only data page pointers DPP1 through DPP3 the CP SP STKOV STKUN SY SCON WDTCON and specific read only registers may contain defaulvalues other than zero after a system reset complete summary of all ST10x166 registers and their reset values is con tained in Appendix B Note that the contents of the internal RAM are not affected by a system reset After a power on reset the contents of the internal RAM are undefined This implies that the GPRs and the PEC source and destination pointers SRCPy DSTPy 0 7 which are mapped into the internal RAM are also undefined after a power on reset After a warm re set ora reset which is caused by an overflow of the Watchdog Timer or by execution of the SRST in struction the previous contents of the internal RAM remain unaffected The four Data Page Pointers DPPO through DPP4 are initializedluring a system reset such that they are pointing to the lowest four consecutive 16 K data pages DPPO points to data page 0 DPP1 points to data page 1 DPP2 points to data page 2 and
39. B The flag contains thexmplemen sent the condition flags of this instruction as usual ted value of the specified bit operand A 1 6 A86peocivy Note This part specifies which combinations of different If the PSW register was specified as the destina addressing modes aravailablefor the required tion operand of an instruction the condition flagsoperands Mostly the selected addressing mode can not be interpreted as just described because combination is specified by the opcode of the cor the PSW register is modifiedependingon the responding instruction However there are some data format of the instruction as follows arithmetic and logical instructions where the ad For word operations the PSW register is overwrit essing mode combination is not specified by the ten with the word result For bytgerationsthe identical opcodes but by particular bits within the non addresed byte iscleared and the addresed field byte is overwritten For bit or bit field operations onThe addressing modes are described in detail in the PSW register only the specified bits are modi section 6 2 fied Supposed that the condition flags were not Piyupe A 1 Ivotpux tiov oppo Representation in the Assembler Listing N2N1 NAN 3 N6NS N8N7 1 High Byte 2 nd word Low Byte 2 nd word High Byte 1754 word Low Byte 1 st word Internal Organization MSB Bits in ascending order LsB
40. BIT If the bit specified by op1 is set program execution continues at the location of the instruc tion pointer IP plus the specified displacement op2 The displacementis a two s comple ment number which is sign extended and counts the relative distance in words The value of the IP in the target address calculation is the address of the instruotiowingthe JB instruction If the specified bit is clear the instructibawingthe JB instruction is exe cuted next instruction FLAGS E 2 V Not affected Z Not affected V Not affected Not affected N Not affected INSTRUCTION FORMAT BXO Taoxtivy Onepav o Byteo JB JB bitaddy g rel q0 4 42 84 S amp S THOMSON A Ivotpuyuov Let VBX UBX Pe ate SOUT 1 Bit Let avd XAEap SBX onl 2 OPERATION DATA TYPES IF op1 1 THEN 1 0 sign extend op2 ELSE 1 0 next instruction END IF BIT If the bit specified by op1 is set program execution continues at the location of the instruc tion pointer IP plus the specified displacement op2 The bit specified by op1 is cleared allowing implementation of semaphore operations The displacement is a two s comple ment number which is sign extended and counts the relative distance in words The value of the IP used in the target addresalculation idhe address of the instrtion followig the JBC instruction
41. Disable Watchdog Timer Instruction DISWDT is a pro tected 32 bit instruction which will ONLY be exe cuted during the time between a reset and execution of either the EINIT End of Initialization or the SRVWDT Service Watchdog Timer in struction Either one of these instructions disables the execution of DISWDT When the Watchdog Timer is not disabled via in struction DISWDT it will continue counting up even during Idle Mode If it is not serviced via the instruction SRVWDT by the time the count reaches FFFFh the Watchdog Timer will overflow and cause an internal reset This reset will pull the ex ternal reset indication pin RSTOUT low It differs from a software or external hardware reset in that bit WDTR Watchdog Timer Reset Indication flag of register WDTCON will be set A hardware reset or the SRVWDT instruction will clear this bit Bit WDTR can then be examined by software in order to determine the cause of the reset To preventthe Watchdog Timer from overflowing it must be serviced periodically by the user soft ware The Watchdog Timer is serviced with the in struction SRVWDT which is a protected 32 bit instruction Servicing the Watchdog Timer clears the low byte and reloads the high byte of the Ey SGS THOMSON o MICROELECTRONICS 8 Peripherals Table 8 20 Watchdog Time Ranges WDTCON FFAEh D7h ww Watchdog Timer Control Register rescaler Tor WDTREL Reset Value 0000h 4 WDTIN 0 256 W
42. GPT1 Auxiliary Timer 2 Interrupt Control Register Reset Value 0000h 7 6 5 4 3 2 1 0 TAIC FF64h B2h GPT1 Auxiliary Timer 4 Interrupt Control Register Reset Value 0000h 7 6 5 4 3 2 1 0 b7 TxIR Timer x Interrupt Request Bit This flag can be reset to generate an interrupt or trigger a PEC service request b6 TxIE Timer x Interrupt Enable Bit If setat 1 will enable the timer x interrupt b5 tob2 ILVL Interrupt Priority Level Bits See chapter 7 for more details b1 tob0 GLVL Interrupt Group Priority bits See chapter 7 for more details Interrupt Request Interrupt Request VRDJIB41 35 64 MIGRCELECTREMICS 8 Peripherals register and the associated interrupt request flag T2IR for timer T2 or T4IR for timer T4 will be set Note thatthe direction control bits DP3 7 for T2IN and DP3 5 for TAIN must be set to 0 and that the level of the capture trigger signal should be held for at least 8 states to ensure correct edge de tection Figure below shows a block diagram of an auxiliary timer in capture mode 8 2 1 2 5 Interrupt Control Upon each overflow underflow or upon each cap ture or reload trigger of one of the auxiliary timers T2 or TA its corresponding interrupt request flag T2IR or will be set This flag may cause interrupt to the specific auxiliary timer s interrupt vector T2INT or T4INT or initiate a PEC transfer when the request is enabled Each of the
43. Not affected N Not affected INSTRUCTION FORMAT BXO Taoxtivy Mvepnovur Mvenuoviy Onepav o Byteo DISWDT DISWDT Ab 5A A5 A5 4 565 0 35 84 A Ivotpux tiov Let Alc Alc orl OPERATION DATA TYPES Alc 16 16 Xvyve 101610 MDL MDL 1 MDL mod op1 WORD Performs a signed 16 bit by 16 bit division of the low order word stored in the MD register by the source word operand op1 The quotient is then stored in the low order word of the MD register MDL and the reminder is stored in the high order word of the MD register MDH FLAGS E 2 V E Always cleared Z Set if result equals zero Cleared otherwise V Setif an arithmetic overflow occurred Overflow occurs when the result can not be represented in a word data type or if the divisor op1 was 0 Cleared otherwise C Always cleared N Setif the most significant bit of the result is set Cleared otherwise INSTRUCTION FORMAT BXO Taoxtivy Onepav o Byteo DIV DIV 4 2 36 84 S amp S THOMSON A Ivotpuxuov Let AIcA AIcA 32 16 Xvyve 101610 DATA TYPES FLAGS MDL MD op1 MD mod op1 WORD DOUBLE WORD Performs an extended signed 32 bit by 16 bit division of the two words stored in the MD register by the source word operand op1 The signed quotie
44. Parallel Ports Table 10 3 Alternate Functions of Port 5 P5 FFA2h Dth Port 5 Register P5 Symbol Alternate Description Reset Value XXXXh Symbol 15 14 13 12 11 10 9 8 250 Analog Input Channel 0 PTC Pss Pss Analog Input Channel 1 7 6 5 4 3 2 1 0 Analog Input Channel ps7 prs Pss psa Ps2 Ps Po b15 to b10 R Reserved b9 to b0 P5 y Port 5 Data Register Analog Input Channel 4 READ ONLY y 0 through 9 Analog Input Channel 3 Analog Input Channel 5 Analog Input Channel 6 Analog Input Channel 7 Analog Input Channel 8 Analog Input Channel 9 SGS THOMSON 175 10 Parallel Ports NOTES 18 18 y SGS THOMSON e MIGROELECTRONICS SGS THOMSON MICROELECTRONICS CHAPTER 11 SYSTEM RESET 11 SYSTEM RESET The internal system reset function provides initialidn order to obtain an automatic power on reset the zation of the ST10x166 into a defined default state RSTIN pin be connected to an external capaci This internal reset function is invoked by any of thetor since this pin already has an internal pullup re followingeonditions sistor connected to VCC see figure 11 1a The n reset signal orRSTIN first passes a Schmitt Trig 1 omine ger in order to obtain a fast transition For a power on reset theRSTIN pin has to be held low for the 2 Upontheexecution ofthe SRST Software Re minimum duration ofthe s
45. The range start state and the address hold time after ALE is also address can only be specifiedlpeundariesdeter lengthenecby one TCL mined by the selected range size That is for a After reset all bits of the BUSCON1 register are ange size of arid the start E cleared As opposed to SYSCON register the ange Fori be P OOK to yte state of the external bus control pins EBCO EBC1 DoundariesFor a range size o yte the start iadi address can be programmed to any 2Kbyte ad are nobepledinto BUSCONTAtar dress boundary If the range size is 128Kbyte then for the ST10x166 the start address can only be To ipn the vong ede an OKbyte or 128Kbyte since the total address range range plus a Start adc is 256 Kbyte two blocks of 128 Kbyte Bits 3 to 9 through ADDRSEL1 register then BUSCON1 red the Address Start Location bit field of register AD ister must be programmed to the desired bus con DRSEI 1 canbe ragarded the most significant figuration and the BUSACTI control bit must be address bits of the selected address range Thus set The BUSCON1 register will then take control dependingon the selected range size only a part of the externalbus when an accessto the specified of this bit field is relevant for specification of the address range is performed otherwise the SY start address This is shown in thellowingable SCON parameters control the external bus charac x don tcare relevant bit teristics F
46. not used VROE1628 8 20 SGS THOMSON MICROELECTRONICS 9 External Bus Interface Figure 9 7 16 18 Bit Address 16 Bit Data Non Multiplexed Bus Word Wide Memories Segment Addr Port 4 WR RD BHE Port 1 ST10x166 ADDR CS OE WR ADDR CS OE WR 8 8 Bit External External Memory Memory INSTR DATA INSTR DATA VROF 1628 9 7 EXTERNAL BUS TRANSFER A memory access is initiated by the controller by CHARACTERISTICS placing an address on the bus and thgenerating the Address Latch Enable signal ALE This signal With regard to timing characteristics there ba triggers an external latch to capture the address sically two types of external buses which can be After a period of time during which the address configured These are multiplexed and non multi must have been latched externally the address is plexed buses Transfer characteristics for these removed from the bus Note that in the 16 18 bit two types are described in detail in the following Address 8 bit Data Multiplexed bus mode only the lower eight bits of Port 0 are multiplexed on the external bus betwen address output and data in 9 7 1 Multiplexed Bus Transfer Characteristics put output while the upper eight bits of Port 0 con In both Multiplexed Bus modes the resource Ex tinue to output address bits A15 to A amp r ughout ternal Bus is time shared between addresses and the entire memory access cycle Note also that data Figure 9
47. pots 2 pos 6 5 4 3 2 1 7 0 Poz pos Pos poz P1 FF04h 82h Reset Value 0000h 15 14 13 12 11 10 9 8 Ports 0 through 3 Direction Registers DPO FF02h 81h Reset Value 0000h 15 14 13 12 11 10 9 8 2 pros pros 7 6 5 4 3 2 1 0 Ceres oras oros oroa oroa oroz sens sons DP1 FFO6h 83h Reset Value 0000h 15 14 13 12 11 10 9 8 DP1 15 DP1 14 DP1 13 1 12 DP1 11 DP1 10 DP1 9 DP1 8 P1 15 P1 14 P1 13 P1 12 P1 11 P1 10 6 5 4 3 2 1 7 0 rs os ez Dn P2 FFCOh EOh Reset Value 0000h 15 14 13 12 11 10 9 8 pats pats p212 Pert P210 6 5 4 3 2 7 1 0 P27 226 ras p22 pza 2o P3 FFC4h E2h Reset Value 0000h 15 14 13 12 11 10 9 8 pes rese re rane ran eun me 6 3 2 1 b15 to b0 Px y Port Px Data Register x 0 through 3 y 0 through 15 P4 FF08h 84h Port 4 Data Register P4 Reset Value 0000h 7 6 5 4 3 2 1 0 b7 to b2 R Reserved b1 to b0 P4 y Port Data Register y 0 through 1 7 6 5 4 3 2 1 0 Corr oris oris orra oris orre ve DP2 FFC2h E1h Reset Value 0000h 15 14 13 12 11 10 9 8 DP2 15 DP2 14 DP2 13 DP2 12 DP2 11 DP2 0 DP23 DP2 8
48. the external memoryjsace will caue a hardware plexing and nadditionabddress latch isequired trap to occur if the controller is in the single chipin this case As long as memory segmentation is mode not disabled Port 4 MY For applications where the on chip program mem Put for the two most significant bits of t amp quire ory is not sufficient the single chip mode can be 18 bit address The upper half of Port 0 can not be left by simply modifying the BTYP bit field and the USed for general purpose I O Figure 9 2 16 18 Bit Address 8 Bit Data Figure 9 1 Single Chip Mode Non Multiplexed Bus Segment Addr Port 4 WR RD ADDR OE WR 5 10 166 1 8 bit or Port ST10x156 External Memory Port INSTR DATA VROO1828 VROA1628 4 20 Ey SGS THOMSON o MICROELECTRONICS 9 External Bus Interface 9 4 16 18 BIT ADDRESS 8 BIT DATA dresses Port 1 can be used for general purpose MULTIPLEXED BUS functions Whenever a word is to be accessed externally in This external bus mode mustbe selected if a byte this mode the EBC generates two consecutive ad wide external memory shall be connected to the dresses and adjusts incoming bytes into words ST10x166 outgoing wordsnto bytes The low byte of a word As shown the figure 9 3 the lower address byte is accessed first then the high byte access is per and the data byte are time multiplexed on the formed lower portion of theord widexterna
49. x 0 through 15 interrupt input pin withoutaffecting peripheral func to be used as external interrupt input pins bit fieldtions When the capture mode enable bit 55 in CCMODx the control register of the correspond TSCON is set to 0 signal transitions on ing capture compare register CCx must be config Pin CAPIN P3 2 will only set the interrupt request ured for capture mode When CCMODx is flag CRIR in register CRIC and the capture func programmed to 001b the interrupt request flag tion of register CAPREL is not activated This in register CCxIC will be set on a positive Means that register CAPREL can still be used as external transition at pin 2 When eload register for GPT2 timer T5 while pin CCMODx is programmed to 010b a negative ex CAPIN P3 2 is used as external interrupt input ternal transition will set the interrupt request flag Through bit field Cl in register TSCON the effec When 0116 both a positive anda nega tive transition of the external interrupt input signal tive transition will set the request flag In all three be selected When Clis programmed to 01b a cases the contents of the allocated CAPCOM positive external transition will set the interrupt re timer TO or T1 will be latched into capture register quest flag Cl 10b selects a negative transition to CCx independent whether the timer is running or set the interrupt request flag and with Cl 1
50. 0 THROUGH 4 10 1 PortO and Ports 5 0s 0 et ese eae 10 4 10 6 10 10 10 PORT PINS 2 T4IN T3EUD CAPIN AND READY 10 11 PORT PINS T6OUT TXDO TXD1 WR CLKOUT 10 12 vitae tala re te E tect tip ep ee ee one cedi cec reed p eee ae as 10 13 PORT PINS RXDO AND RXD1 10 14 e ce heen A m m mp EL is 10 15 oto Rn Pila 10 16 11 SYSTEM RESET 11 1 11 2 11 3 11 4 11 5 11 6 RSTIN and RSTOUT Pins 11 1 RESET VALUES FOR ST10x166 REGISTERS RR 11 2 WATCHDOG TIMER OPERATION AFTER RESET 1 11 3 PORTS AND EXTERNAL BUS CONFIGURATION DURING RESET 11 3 INITIALIZATION SOFTWARE ROUTINE 11 4 THE BOOT STRAP MODE 22 11 4 S amp S THOMSON GENERAL INDEX 12 POWER REDUCTION MODE 12 1 POWER DOWN MODE QUERELIS UU 12 1 12 2 ore Dee a rette dds nen e fed et fe edet rte eo 12 1 12 3 STATUS OF OUTPUT PIN
51. 0n MM MM 4 MOV MOV mem Rw 94 0n MM MM 4 MOV MOV reg mem F2 RR MM MM 4 MOV MOV mem reg F6 RR MM MM 4 Ey SGS THOMSON MICROELECTRGNICS 51 84 A Ivotpux tiov Let MOGB MOGB Mode MOGB onl 2 OPERATION 1 2 DATATYPES BYTE Moves the contents of the source operand specified by op2 to the location specified by the destinaion operandop1 The contents of the moved data is examined and tbedition flags areupdated accordingly FLAGS E 2 V E Setifthe value of op2 represents the lowest possible negative number Cleared oth erwise Used to signal the end of a table 2 Set if the value of the source 2 equals zero Cleared otherwise V Not affected C Notaffected N Setif the most significant bit of the source operand 2 is set Cleared otherwise INSTRUCTION FORMAT BXO Taoxtvy Mveuovy Onepav o Byteo MOVB MOV RbRbm F1nm 2 MOVB MOV Rbn data E1 n 2 MOVB MOV reg dat s E7 RR 4 MOVB MOV Rb Rw A9 nm 2 MOVB MOV RW 99 nm 2 MOVB MOV Rum Rh B9 nm 2 MOVB MOV Rwy Rb 89 nm 2 MOVB MOV Rw Rum C9 nm 2 MOVB MOV Rwn Rwn D9 nm 2 MOVB MOV Rwa Rwn E9nm 2 MOVB MOV Rwm d16 F4 nm 4 MOVB MOV Rum d16 Rb E4 nm 4 MOVB MOV Rv mem A40n MM MM 4 MOVB MOV mem Rw B4 0n MM MM 4 MOVB MOV reg mem RR MM 4 MOVB MOV mem reg F7 RR MMMM 4 52 84 S amp S THOMSON A Ivotpuxuov
52. 1 Error Interrupt Control Serial Channel 1 Receive Buffer Register XXXXh read only S1RIC b FF74h Serial Channel 1 Receive Interrupt Control 0000h Register S1TBUF FEB8h 5Ch Serial Channel 1 Transmit Buffer Register 0000h write only S1TIC b FF72h Serial Channel 1 Transmit Interrupt Control 0000h Register STKOV E CPU Stack Overflow Pointer Register STRUN CPU Stack Underflow Pointer CPU Stack Underflow Pointer Register SYSCON CPU System Configuration Register system configuration selected during rese x pue pe pent CAPCOM Timer Register Timer 0 and Timer 1 Control b FFOCh ceh CAPCOM Timer 0 Interrupt Control Register CAPCOM Timer 0 Interrupt Control Registe Cron rm cau Tiner eed par rem capcom Timer t Regis ooon Tuc cr CAPCOM Timer t eruprGonvol Reise Won Cree rss CAPCOM Tier Reon megier wg SGS THOMsoN 1G YF MICROELECTRONICS B ST10x166 Registers Address Address Value rem um _ www sam aon GPTrTmeraConvomegaw ol rom oon tom _ m rem zm snmma wem am _ e rem _ o pran aan PTI TineraconvotRegiter a Tmor
53. 1 TCL 2to 40MHz ns Oscillator Period High Time Low Rise Tlme Fail Time VROO1631 Ey SGS THOMSON 7 17 e MIGROELECTRONICS ST10F166 AC CHARACTERISTICS Continued CLKOUT and READY Ta 0 to 70 C 5 V 1096 Vss 0 V for Ports 0 1 and 4 ALE RD WR CLKOUT 100pF CPU Clock Variable Timing Parameter 20MHz 1 TCL 2 to 40MHz 50 50 CLKOUT Cycle Time CLKOUT High Time CLKOUT Low Time CLKOUT Rise Tlme CLKOUT Fall Time ALE Rising to CLKOUT Falling Edge Synchronous READY 10 Setup Time to CLKOUT Synchronous READY 10 Hold Timeto CLKOUT Asynchronous READY 2TCL 15 Hold Time Figure 12 CLKOUT and READY CLKOUT Synchronous READY Asynchronous READY vROO1618 8 17 S amp S THOMSON AE ST10F166 AC CHARACTERISTICS Continued Multiplexed Bus with Read Write Delay Ta 0 to 70 C 5 V 10 Vss 0 V for Ports 0 1 and 4 ALE RD WR CLKOUT 1 00pF ALE cycle time 6TCL 150ns at 2OMHz CPU clock CPU Clock Variable Timing Symbol Parameter 20MHz 1 TCL 2 to 40MHz ns ALE High Time TCL 10 Address Setupto ALE TCL 15 Address Hold after ALE TCL 10 ALE Falling Edge to RD WR TCL 10 Address Float after RD WR RD WR Low Time 3 2TCL 10 RD to Valid Data In ALE Low to Valid Data In Address to Valid Data In Data Hold after RD Rising Edge Data Float after RD Data Valid to WR 2TCL 15
54. 2 1 0 of the internal system stack For more details about the implementation of a stack underflow trap serv o ice routine see chapter 13 b15 to b11 1 Bits tied to 1 by hardware This restricts contents 5 3 11 STKOV Stack Overflow Pointer to values from F800h to FFFEh This non bit addressable register is compared b10 to b1 STKUN Stack Underflow Pointer Reg against the SP register after each operation which ster pushes data no the system Slack e g PUSH Modifiableportion of the STKUN register and CALL instructions or interrupts and after eachbO 0 subtraction from the SP register If the contents of Bit tied to 0 by hardware because only even the SP register are less than the the contents ofthe STKUN contents are compared against the SP STKOV register a stack overflow hardware trap register will occur Stack Overflow Condition SP lt STKOV Since the least significant bit of the STKOV register STKOV FE14h OAh is tied to 0 and bits 11 to 15 are tied to 1 by hard Stack Overflow Pointer Register ware the STKOV register can only point to even R Value FA00h word addresses from OF800h to OFFFEh After re Reset Value set the STKOV register isnitialied to FAOOh 15 14 13 12 11 10 9 8 The defaultinitialiation allows treating a stack overflow as a fatal error in the cespondingrap ps passer soy service routine Note however that
55. 2 1 2 Timer T6 Interrupt Control When timer T6 overflows from FFFFh to 0000h when counting up or when it underflows from 0000h to FFFFh when counting down the inter rupt request flag T6IR in register T6IC will be set This will cause an interrupt to the timer T6 interrupt vector T6INT or will trigger a PEC transfer if the Figure 8 29 Block Diagram of GPT2 Core Timer T6 in Timer Mode T6R 38 64 To CAPCOM Timers TO T1 To GPT2 CAPREL Register Interrupt Request Timer T5 VROK1641 Ey SGS THOMSON MICROELECTRONICS 8 Peripherals T5CON FF46h A3h GPT2 Auxiliary Timer T5 Control Register Reset Value 0000h 15 14 13 12 11 10 9 8 msc rsen Ry 7 6 5 4 3 2 1 0 b15 T5SC Timer 5 Capture Mode Enable Bit Capture into register CAPREL is enabled if T5SC 1 b14 TBCLR Timer 5 Clear Bit T5CLR 0 Timer 5 is not cleared on a detected transition at CAPIN T5CCR 1 Timer 5 is clear in a detected transi tion at CAPIN b13 b12 Cl Register CAPREL Input Selection See table 8 15 b11 to b8 and b5 to b4 Reserved b7 T5UD Timer 5 Up Down Control Bit T5UD 0 Timer 5 is counting up T5UD 1 Timer 5 is counting down b6 T5R Timer 5 Run Bit Timer 5 runs if T5R 1 otherwise stops 5 Timer 5 Mode Control If 0 timer mode is enabled otherwise counter mode is enabled b2 tob0 T5I Timer 5 Input Selection See table 8 13 and 8 14 for more details inte
56. 20 0 Unsgnedgreertmn ceste iow 1__ Signediessthanorqual en co see Nev 0 Signed greater than orquai ph ceser mewn o signedgreatertnan Ah ce NeT jNotequalANDnotendoftable in vg SGS THOMSON 2555 YF MICROELECTRONICS A Ivotpux tiov Let XAAAI XAAAI LoPpovtive 1 CALLI op2 OPERATION IF op1 THEN SP SP 2 SP IP IP op2 ELSE END IF If the condition specified by op1 is met a branch to the location specified indirectly by the second operand op2 is taken The value of the instruction pointer IP is placed onto the System stack Because the IP always points to the instrud towinghe branch instruc tion the value stored on the system stack represents the return address of the calling rou tine If the condition is not met no action is taken and the next instruction is executed next instruction normally Condition Codes See Table A 1 FLAGS E Z V C N E Not affected Z Not affected V Not affected Not affected N Not affected INSTRUCTION FORMAT BXO Taoxtvy Mvenoviy Mvenoviy Onepav o Byteo CALLI CALL cc RwW ABcn 2 24 84 SGS THOMSO AJ M A Ivotpuyuov Let XAAAP XAAAP Peate XAAAP oml OPERATION FLAGS SP SP 2 SP IP IP sign extend op1 A branch is taken to the location specified by the in
57. 6 3GS THOMSON ss S71 SGS THOMSON e MICROELECTRONICS CHAPTER 2 SYSTEM DESCRIPTION 2 SYSTEM DESCRIPTION In this chapter a summary of the ST10x166 is pre advanced high bandwidth internal bus structure of sented Thefollowindcplock diagram gives an over the ST10F166 view ofthe different on chip components and ofthe Figure 2 1 Block Diagram Internal Internal ST10F166 FLASH EPROM RAM 32KBytes CPU CORE 1KBytes 10 bit USART USART ADC ASCO ASC1 VR001613 1 6 2 System Description 2 1 MEMORY ORGANIZATION In the non multiplexed bus mode Port 1 is used as an output for addresses and Port 0 is used as an The memory space ofthe ST10x166 is configured input output for data the upper half of Port 0 can in a Von Neumann architecturehich meansthat not be used for general purpose I O in the 8 bit code memory data memory registers and I O data bus mode In the multiplexed bus modes one ports areorganizedwithin the same linear address 16 bit port Port 0 is used as an input output for space which currently includes 256Kbytes Ad both addresses and data dress space expansion to 16 Mbytespsovided Important timing characteristics of the external bus for future versions The entire memory space Can interface Memory Cycle Time Memory Tri State be accessed by byte or by word Particular portions Time and Read Write Delay have been made pro of the on chip memory havedditionallybeen grammable
58. 6 5 4 3 2 1 7 0 peas pe2s 022 pees peo FFC6h E3h Reset Value 0000h 15 14 13 12 11 10 9 8 2235 0 2 peso ops 6 4 3 2 1 b15 to b0 DPx y Port Px Direction Control x 0 through 3 y 0 through 15 DPx y 0 Port Line Px y is Input high imped ance DPx y 1 PortLine Px y is Output 85h Port 4 Direction Control Register DP4 Reset Value 0000h 6 5 4 7 3 2 1 0 b7 to b2 R Reserved b1 to 50 DP4 y Port P4 Direction Control y 20 through 1 DP4 y z 0 Port Line P4 y is Input high imped ance DP4 y 1 Port Line P4 y is Output 2 18 Gi SGS THOMSON MICROELECTRGNICS 10 Parallel Ports Using PO through P4 as General Purpose corresponding port pins arswitched to the direc Ports tion required by the selected bus type This is ex When the alternate input or output function associ P ainedin detail in th ollowingections ated with a port jn is not enabled thpin can be logic level of a pin is clocked into the input used as a general purpose I O pin Each port pin latch once per state timaegardles whether the consists ofa port output latch an output buffer anport is configured for input or output input latch an input read buffer and a direction write operation to a portpin configured as an in oe por H ut qj Put ca
59. 7 2 NORMAL INTERRUPT PROCESSING AND 7 4 Interrupt System Register 7 5 INTERRUPT CONTROL REGISTERS 7 5 INTERRUPT CONTROL FUNCTIONS IN THE PSW 7 8 PEC Service Channels Register 7 9 PEC CHANNEL COUNTER CONTROL REGISTERS 7 9 PEC SOURCE AND DESTINATION POINTERS 7 10 Prioritization of Interrupt and PEC Service Requests 7 12 ENABLING AND DISABLING OF INTERRUPT SOURCES 7 12 PRIORITY LEVEE STRUCTURE teet REN qtio 7 12 EXAMPLE FOR THE USE OF THE CPU PRIORITY eene 7 12 Interrupt Procedure ose HR EN E edge 7 14 INTERRUPT PROCEDURE WITH SEGMENTATION DISABLED 7 14 INTERRUPT PROCEDURE WITH SEGMENTATION ENABLED 7 14 CONTEXT SWITCHING FOR INTERRUPT SERVICE ROUTINES 7 15 Interrupt Processing via the Peripheral Event Controller PEC 7 15 Interrupt and PEC Response Times 7 17 External Interrupts ette
60. 7 TABLE SEARCHING ore rotten tet heen 13 7 13 8 PERIPHERAL CONTROL AND INTERFACE 19 7 13 9 FLOATING POINT SUPPORT 222200222120220002 19 7 13 10 TRAP INTERRUPT ENTRY AND eee 19 7 Ey SGS THOMSON 7 7 0 MICROELECTRGNICS GENERAL INDEX APPENDICES A INSTRUCTION SET A 1 DEANT ONO teft RR e DER Ratan dacs GE INN ulteriore A 1 A 1 2 Instruction CO ERI UN A 1 3 Syntax 1 A 1 4 Operation 22 1 A 1 5 Data Types E EIAS C AAA 2 A 1 6 Condition Flags 2 Ad 7 Addressing Modes gt eb A 3 A 1 8 SRL as oh 4 1 9 Number of Bytes EH EE UE 4 2 SINGLE INSTRUCTION DESCRIPTION ees A 4 B REGISTERS B 1 CPU GENERAL PURPOSE REGISTERS GPRS B 2 B 2 SPECIAL FUNCTION REGISTERS Ordered by B 4 B 3 SPECIAL FUNCTION REGISTERS ALPHABETICAL ORDER
61. 70 C 40 to 85 C to 70 C PQFP100 40 to 85 C SGS THOMSON MICROELECTRONICS PQFP100 PQFP100 5 6 ST10166 ST10R166 NOTES Information furnished is believed to be accurate and reliable However SGS THOMSON Microelectronics assumes no re sponsability for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of SGS THOMSON Microelectronics Specifications mentioned in this publication are subject to change without notice This publication supersedes and replaces all information previously supplied SGS THOMSON Microelectronics products are not authorized for use as critical components in life support devices or sys tems without the express written approval of SGS THOMSON Microelectronics 1994 SGS THOMSON Microelectronics All rights reserved Purchase of C Components by SGS THOMSON Microelectronics conveys a license under the Philips I C Patent Rights to use these com ponents in an systemis granted provided thatthe system conforms to the 12 Standard Specification as defined by Philips SGS THOMSON Microelectronics Group of Companies Australia Brazil France Germany Hong Kong Italy Japan Korea Malaysia Malta Morocco The Netherlands Singapore Spain Sweden Switzerland Taiwan Thailand United Kingdom
62. 8 4 1 8 4 1 1 8 4 1 2 8 4 2 8 4 2 1 8 4 2 2 8 4 3 8 5 GENERAL INDEX Capture Compare Registers 0022 8 9 CAPTURE MODE qe teet tcd tee ie e tee ee dec NL d ee 8 11 seb repete leek Ges eee eee EO tue Se deese sue nue ia Te 8 12 NV RD tener adnate cass perpe d ue 8 19 GENERAL PURPOSE TIMERS 8 19 GPTIBIOCk uestes 8 22 CORE TIMER ideis tv 8 23 GPT1 AUXILIARY TIMERS T2 AND 4 22 2 9 8 27 GPT2 Block tee e e c fecta ah ca eui tu ef cte 8 36 GPT2 CORE TIMER os ete E e dote e a 8 37 GPT2 AUXILIARY TIMER TS 8 38 GPT2 CAPTURE RELOAD REGISTER 2 2 2 8 41 A D Converter ADC ettet eee ens 8 45 Conversion Modes and Operation 8 45 SINGLE CHANNEL CONVERSION MODE 2 2 2 9 99559 8 48 SINGLE CHANNEL CONTINUOUS 500 0 02 8 48 AUTO SCAN CONVERSION MODE 222 2 2 2 0000000000000000000 0 8 49 AUTO SCAN CONTINUOUS CONVERSION 2 2 54 2 2 2
63. 8 shows the timing sequence of a Port 4 is never time multiplexed and continues to memory read and memory write access via a mul output the two most significant segment address tiplexed bus bits A17 and A16 sg SGS THOMSON 9 9 External Bus Interface Figure 9 8 Multiplexed External Bu Accesses ALE BUS Dato ws X oem gt WR x VROO1633 9 7 1 1 MULTIPLEXED BUS MEMORY READS the bus and the active low memory write signal At the same time when the address is removed WR is appliedto the memory This enables the from the bus which is then tri stated again the ac Memory to store the data from the bus onto the ad tive low memory read signdRD is applied tothe dressed location After a period of time which is de memory Thisenablesthe memory to drive data termined by the access time of the memory the onto the bus After a period of time which is deter data become valid in the addressed memory loca mined by the access time of the memory data be tion Then the controller removes its memory write come valid on the bus signal The data remain valid on the bus until the next memory access cycle is started Then the controller latches the valid data from the y bus and removes its memory read signal This causes the memory to remove its data from the 9 7 2 Non Multiplexed Bus Transfer bus which is then tri stated again Characteristics In the Non Multiplexed Bus mode ther
64. Bit T6OE Alternate Output Function Enable in regis ter T6CON enables the state of TEOTL to be an al ternate function of the external output pin T6OUT P3 1 For that purpose a 1 must be writ ten into port data latch P3 1 and pin T6OUT P3 1 must be configured as output by setting direction control bit DP3 1 to 1 If TEOE 1 then outputs the state of If 0 pin T6OUT be used as a general purpose pin In addition T6OTL can be used as the trigger source for the counter function of auxiliary timer T5 For this purpose the state of TGOTL does not have to be available at pin because an in ternal connection is provided for this option This feature is described in detail in section 8 2 2 2 about auxiliary timer T5 A reload of timer T6 on overflow underflow with the contents of register CAPREL can be selected through bit T6SR in register A detailed de scription of this option can be found in sec tion 8 2 2 2 3 aboutthe CAPREL register T6IC FF68h B4h GPT2 Timer T6 Interrupt Control Register Reset Value 0000h 7 6 5 4 3 2 1 0 An overflow or underflow of timer T6 can also be used to clock timers TO or T1 in the CAPCOM unit For this purpose a direct internal connection be tween timer T6 and timers TO and T1 exists Refer to section 8 1 CAPCOM Unit for more details Figure below shows a block diagram of T6 in timer mode 8 2
65. Cycle Time Time 100 50 t 4TCL nx2TCL 00000 t 4TCL nx2TCL 00000 nx 2TCL Note ALE Cycle Time Memory Cycle Time 4TCL 100ns at 40MHz for 0 wait state operation t6 ts t12 t22 t24 See Device Specification Section Take care of h and ts These times cannot bprolonged states Table C 8 Non Multiplexed Memory Write With Read Write Delay Quick Table 10 10 Gr SGS THOMSON TT 2GS THOMSON AYA NOTE PROGRAMMING FLASH MEMORY OF THE ST10F166 INTPOAYXTION The ST10F166 high end microcontroller with on chip Flash Memory fulfills the requirements of applications requiring an updatto a part or all the program code The block eeaspabilk is also of use during the applicatiomevelopmenstage or for program updating For data acquisition the ST10F166allows the pro gramming of 16 or 32 bits datadependenly Operations on the Flash memory are under software control Erasure or programming is a simple proce dure however precautions must be taken to prevent damage to the ST10F166 This applicdbn note describes the basic characteristics of the Flash memory cell and the different algo rithms used for erasure and programming MEMOP P The Flash memoryncluded inthe ST10F166 combines the EPROM programming mechanism with elec trical erasability like EEPROM to create highd
66. D converter are controlled by the A D Converter Control Register ADCON This bit addressable register holds the bits which specify the analog channel the conversion mode and the status of the converter Figure 8 37 SFRs and Port pins Associated with the A D Converter Data Registers ADDAT Port 5 Data Register A D Converter Result Register A D Converter Control Register Control Registers Interrupt Control VROC 1 640 A D Converter End of Conversion Interrupt Control Register A D Converter Overrun Error Interrupt Control Register 46 64 SGS THOMSON MICROELECTRONICS 8 Peripherals Table 8 16 Conversion Mode Selection Conversion Mode Single Channel Conversion Single Channel Continuous Conversion Auto Scan Conversion Auto Scan Continuous Conversion ADDAT FEAOh 50h A D Converter Result Register Reset Value 0000h 15 14 13 12 11 10 9 8 On Ames 7 6 5 4 3 2 1 0 ADRES 7 0 b15 tob12 CHNR 4 Bit Channel Number b11 and b10 Reserved b9 to b0 ADRES 10 Bit Result of the A D Con version ADCON FFAOh A D Converter Control Register Reset Value 0000h 15 14 13 12001 10 9 8 7 6 5 4 3 2 1 0 b15 to b9 and b6 R Reserved b8 ADBSY ADC Busy Flag Read only bit Indicates if a conversion is in progress or not b7 ADST Start Bit Is used to start or stop the A D Converter b5 tob4 ADM Mode Selection bit Determines
67. Data the f i f the Bvte Hiah Enable pi Multiplexed Bus mode provides a middle level of seribed fon Enable pin as de Figure 9 4 16 18 Bit Address 16 Bit Data Bus Multiplexed Bus Word Wide Memories Segment Addr Port 4 WR RD ALE ST10x166 Port O ADDR WR 8 Bit External Memory INSTR DATA not used VROC1628 6 20 Ey SGS THOMSON MICROELECTRONICS 9 External Bus Interface Firstly the Byte Disable bit BYTDIS in the SY and the A0 address output pin must be connected SCON register must contain a 0 this is the default to the chip select input of the memory at the low after system reset and secondly a 16 bit Data byte location as shown in figure 9 5 Bus mode must have been configured If these Detailed application examples for the just men are fulfilled the Byte Higimable tioned external bus and memory configurations BHE function which is an alternate active low out shown irappendx C put function of Port 3 Pin 12 P3 12 becomes en abled and will be implicitly used by the External Bus Controller EBC whenever an external mem Table 9 3 Word or Byte Access to Two ory accessis performed Coupled Byte Wide Memories Table 9 3shows whicBHE output is generated by the EBC dependent on the least significant ad dress bit A0 and the type of access desired for the two coupled external byte memories Both byte memories are accessed to
68. Data Hold after WR 2TCL 15 ALE rising edge after RD WR 2TCL 15 Address Hold after RD WR 2TCL 15 n SGS CTHIMSON 917 o MICROELECTRONICS ST10F166 Figure 13 External Memory Read Cycle 5 127 tig aki tio tha 18 vROO1617 Figure 14 External Memory Write Cycle ts 125 A17 A16 41 127 tio i23 tg 22 VROA1617 10 17 S amp S THOMSON ST10F166 AC CHARACTERISTICS Continued Multiplexed Bus without Read Write Delay Ta 0 to 70 C 5 V 1096 Vss 0 V for Ports 0 1 and 4 ALE RD WR CLKOUT 100pF ALE cycle time 6TCL 150ns at 20MHz CPU clock CPU Clock Variable Timing Symbol Parameter 20MHz 1 TCL 2 to 40MHz ns ALE High Time TCL 10 Address Setupto ALE TCL 15 Address Hold after ALE TCL 10 ALE Falling Edge to RD WR 10 Address Floatafter RD WR TCL 5 RD WR Low Time 3TCL 30 RD to Valid Data In 3TCL 15 ALE Low to Valid Data In 3TCL 15 Address to Valid Data In 4TCL 25 Data Hold after RD Rising Edge Data Float after RD 2TCL 15 Data Valid to WR 2TCL 15 Data Hold after WR 2TCL 15 ALE rising edge after RD WR 2TCL 15 Address Hold after RD WR 2TCL 15 wy SGS THoMson YF MICROELECTRONICS ST10F166 Figure 15 External Memory Read Cycle A17 A16 15 in 115 VROB1617
69. FFFFh Any Byte or Word Any Byte or Word Any Byte or Word Any Byte or Word Long Address Bits 13 0 l specifies x Physical Address 0 3 Contents of DPPx SGS THOMSON MICROELECTRONICS Page Offset Address 5 8 6 Instruction Set Overview 6 2 4 Indirect Addressing Modes These addressing modes can be regarded as a 2 mixture of short and long addressing modes This means that long 16 bit addresses are specified in directly by the contents of a word GPR which is specified directly by a short 4 bit address Rw 0 to 15 Note that for some instructions only the low est four word GPRs RO to can be used as in direct address pointers which are specified via short 2 bit address in that case There are indirect addressing modes where the GPR contents are 3 modified by a constant addition before the long 16 bit address is calculated Moreover there are ad dressing modes which allow decrementing or incrementing the indirect address pointers by a data type dependentalue 4 In each case one of the four DPP registers is used to specify physical 18 bit addresses Any word or byte data within the entire memory space can be addressed indirectly Word accesses may not be performed on odd byte addresses Otherwise a hardware trap would occur After reset the DPP registers areinitializedn a way that all indirectly generated long addresses are directlyapped onto the identical physical addresses
70. Interrupt request programmed in order to specify the task which is tob6 xxIE Interrupt Enable Control Bit be performed by the respective PEC service chan xxIE 0 nel XXIE 1 Interrupenabled b5 to b2 ILVL Interrupt Priority Level 7 2 1 1 INTERRUPT CONTROL REGISTERS ILVL Fh Highest priority level ILVL 0 Request will not be serviced All interrupt control registers are organized identi cally An interrupt control register is 8 bits wide 1 60 GLVL Interrupt Group Priority contains the complete interrupt status information GLVL 3 Highest group priority of the associated source which is required during GLVL 0 Lowest group priority one round of prioritization All interrupt control reg isters are bit addressable and all bits can be read or written by software This allows each interrupt source to be programmed or modified with just one instruction When accessing interrupt control regis ters through instructions which operate on word data types bits 8 through 15 will be read as zeros xxIE Interrupt Enable Flag while the written value issignifient This bit is used to indiualy enable or disable the Besides an example of the SIDx166 sInterrupt acceptance ofa service request Control registers xxIC is shown where xx replaces i interrupt Priority Level Field xxIC 5 2 the mnemonic for the specific source Each inter 4 TS rupt control reg
71. Latch and the gate is active Toggles on each overflownderflowof Can be set or reset by software Count Direction Control b9 Alternate Output Function Enable The count direction of the core timer can be speci This function imabledif T30E 1 fied either by software or by the external input pin _ m TSEUD Timer T3 External Up Down Control In dimers External UpiBown Control put which is the alternate input function of port pin MS P3 4 These options are selected by bits T3UD and b7 T3UD Timer 3 Up Down Control Bit T3UDE in control register T3CON When the See table 8 6 up down control is done by software bit T3UDE b6 T3R Timer 3 Run Bit 0 the count direction can be altered by setting or If set at 1 will run Timer Counter 3 otherwise stops Clearing bit T3UD When T3UDE 1 pin T3EUD Timer Counter 3 is selected to be the controlling source of the count direction However bit T3UD can still be used to b4 b3 Timer 3 Mode Control reverse the actual count direction as listed in ta b2 to 60 zT3l Timer 3 Input Selection Bits ble 8 6 If T3UD 0 and T3EUD shows a low See table 8 7 and 8 8 for more details level the timer is counting up Witha high level at T3EUD the timer is counting down If TSUD 1 a high levelat pin T3EUD specifies counting up and a low level spedies counting down The count di Timer 3 Mode Selection rection can be changed regardlesof whethe
72. Let MOGBX MOGBX Mo e Byte MOcBY orl oz2 OPERATION DATA TYPES low byte op1 op2 IF 27 1 THEN high byte op1 OFFh ELSE high byte 1 00h END IF WORD BYTE Moves and sign extends the contents of the source byte specified by op2 to the word loca tion specified by the destination operand op1 The contents of the moved data are exam ined and the condition flags are updated accordingly FLAGS E 2 V E Always cleared Z Set if the value of the source operand op2 equals zero Cleared otherwise V Not affected C Notaffected Setif the most significant bit of the source operand op2 is set Cleared otherwise INSTRUCTION FORMAT BXO Taoxtivy Mvenoviy Mvenovy Onepav o Byteo MOVBS MOVBS Rb Rbm DO mn 2 MOVBS MOVBS reg mem D2 RR MM MM 4 MOVBS MOVBS mem reg D5 RR MM MM 4 57 S65 THOMSON XM MICROELECTRGNICS A Ivotpux tiov Let MOcBZ MOcBZ Mo e Byte Zepo E amp tev MOcBZ onl 2 OPERATION DATA TYPES low byte 1 op2 high byte op1 00h WORD BYTE Moves and zero extends the contents of the source byte specified by op2 to the word loca tion specified by the destination operand op1 The contents of the moved data are exam ined and the condition flags are updated accordingly FLAGS E 2 V C N E Always cleared Z Set if the value of the source operand op2 equals zero Cleared otherwise V Not affected C Notaffe
73. No multiply divide operation in pro the source operand of an institimn equals the gress lowest negative number which is representable MULIP z 1 Multiply divide operation in progress by the data format of the crespondingin _ Thie hi struction 8000h for the word data type or go ue hit suppor search operaton by 80h for the byte data type the E Flag is set to 1 otherwise i is b3 Z This bit represents a zero result from the Z Flag The Z Flag is normally set to 1 if the ipe result of ALU operation equals zero other b2 z V This bit represents an overflow result from wise it is cleared the ALU b1 C This bit represents a carry result from the For the addition and subtraction with carry the ALU Z flag is only set to 1 if the fag already con ZNI Thie hi tains 1 and if the result of the current ALU prie Ate bit represents a negative result from operation addi nally equalgero This mecha nism is provided for the support ofilt ple pre cision alculationd or Boolean bit operations with only one operand the Z flag represents the logical negation of the previous state of the specified bit 14 26 Ey SGS THOMSON MICROELECTRONICS 5 Central Processing Unit For Boolean bit operations with two operands the Z flag represents the logical NORing of the For Boolean bit operations with only one oper and the V flag is always cleared For Boolean two
74. Organized Memories This configuration shown in figure C 4 is the fastest external memory access mode The external memory is implemented by one 32Kx16 EPROM and by two 8Kx8 RAMs Be cause two separate 16 bit data and 16 bit ad dress buses are used no external address latch is required The EPROM can only be ac cessed wordwise while the RAMs can also be accessed bytewise provided that the function of the BHE output pin is nodisabled In this case the address signal 0 selects the lower byte memory and the active IoBHE signal selects the upper byte memory 1 10 C Application Examples Figure C 1 16 Bit Addresses 8 Bit Data Multiplexed Bus Configuration EBCO 1 P0 8 15 ST10x166 RD P3 13 WR BUSACT 74HC573 Address Latch ABDO ADT M27C256B ADO ADY Example with Byte Organized Memory Devices Data Multiplexed 210 ka SGS THOMSON wicresuerremcs VR00 1646 C Application Example Figure C 2 16 Bit Addresses 8 Bit Data Non Multiplexed Bus Configuration EBCO 1 P1 0 15 ST10x166 RD P3 13 WR BUSACT Example with Byte Organized Memory Devices Data Non Multiplexed vRoA1646 n SGS CTHIMSON 3 10 MICROELECTRONICS C Application Examples Figure C 3 16 Bit Addresses 16 Bit Data Multiplexed Bus Configuration i ADS ADIS EBCO 1 74H C573 74HC573 Address Address P0 0 15 MEC ALE ST10x166 LL UU
75. Page Address is concatened to the DDP contents VR001634 Figure 5 7 Addressing via the Data Page Pointers Sixteen 16 KByte Pages In the case that segmentation is desabled only the two least significant bits of the DPPs are used and thus only pages 0 to 3 can be specified 16 Bit Data Address DPP Registers specify 4 Bit Page Address 14 Bit Intra Page Address is concatened to the DDP contents VR0A1634 SGS THOMSON 1595 venous TROBICS 5 Central Processing Unit 5 3 8 CP Context Pointer The Switch Context SCXT instruction allows sav This non bit addressable register is used to selecting the contents of the CP register onthe stack and the current register context This means that the updating the CP with a new value in just one ma CP register value determines the address of the Chine cycle The aganizationof the GPRs within first GPR within a register bank of up to 16 word the internal RAM is described in the chapter 3 For wide and or bytewide GPRs detailed information about the different addressing Since the least significant bit of the CP register is modes mentioned chapter o tied to 0 and bit 10 is tied to the negated state of The CP register is implicitly used for address calcu bit 9 and bits 11 to 15 are tied to 1 by hardware lations by different addressing modes as follows the CP register can only point to even word ad dresses from OFA00h to ODFF
76. Performs 2 s complement binary addition of the source operand specified by op2 the destination operand specified by and the pously gererated carry bit The sum is then stored in op1 This instruction can be used to perform multiple precision arithmetic FLAGS E 2 V 6 E Setifthe value of op2 representsthe lowest possible negative number Cleared oth erwise Used to signal the end of a table 2 Setif result equals zero and previous Z flag was set Cleared otherwise V Set if an arithmetic overflow occurred i e the result can not be represented in the specified data type Cleared otherwise C Setifa carry is generated from the most significant bit of the specified data type Cleared otherwise Setif the most significant bit of the result is set Cleared otherwise INSTRUCTION FORMAT BXO Taokwy Mveuovty Onepav o Byteo ADDC ADDC Rw Rwm 10 nm 2 ADDC ADDC Rw Rw 18 n 10ii 2 ADDC ADDC Rw Rw 18 n 11ii 2 ADDC ADDC Rw datas 18 0 2 ADDC ADDC reg dat s 16 RR 4 ADDC ADDC reg mem 12 RR MM MM 4 ADDC ADDC mem reg 12 RRMMMM 4 A Ivotpux tiov Let AAAXB AAAXB Xappy AAAXB onl 2 OPERATION 1 1 2 C DATATYPES BYTE Performs a 2 s complement binary addition of the source operand specified by op2 the destination operand specified by op1 and the pously gererated carry bit The sum is the
77. RXDO TXD1 and RXD1 will go high the transmit interrupt request flag SOTIR S1TIR is set and serial datatransmission stops While a synchronous data transmission is in pro gress any write operation to the transmit buffer register of this serial channel will abort the current transmission and start a new transmit process When the receiver enable bit SOREN or S1REN is set to 1 during a transmission unpredictable re sults may occur on the affected channel In order to configure 10 or TXD1 P3 8 as shift clock output both the corresponding port out put bit latch P3 10 or P3 8 and the direction control bit DP3 10 or DP3 8 must be set to 1 Pin RXDO P3 11 or RXD1 P3 9 is each configured as transmit data output by setting both P3 11 1 and DP3 11 1 or P3 9 1 DP3 9 1 respec tively 8 4 1 2 2 Synchronous Data Reception Data reception is initiated by setting bit SOREN 1 S1REN 1 If bit SOR 1 S1R 1 the data applied at pin RXDO RXD1 are clocked into the receive shift register synchronous to the clock which is output at pin TXDO TXD1 After the 8th bit has been shifted in the contents of the receive shift register are transferred to the receive data buffer SORBUF S1RBUF the receive interrupt request flag SORIR S1RIR is set the receiver en able bit SOREN S1REN is reset and serial data reception stops RXDO P3 11 or RXD1 P3 9 are configure
78. Register m PTI TineraConvotRegitr own tineracontotRogiter rre aan timers _ recon pran wm Timers were SS me e pem pm Cocon rrsm an CAPCOM Tera Tiner Conley Frem CAPCOMMode ConrolRegitero owon oom resm aan pron aah Carcom moe contorRegter ooon Lows resen acn ode contol Registra _ rm 0 pem pm e rmm m Pri Timer2imerupt Gomor Regier ooon From em Primera am timers teruptcontor Regier _ Lec p rrem son arta timers _ rre GPr2TinersimteruptcontRegiser Ceme ron sw opra CAPEL meruptconta Regier SGS THOMSON 75 YF MICROELECTRONICS B ST10x166 Registers Name Physical 8 Bit Description Reset Address Address Value SOTIC FF6Ch Serial Channel 0 Transmit Interrupt Control 0000h Register SORIC B7h Serial Channel 0 Receive Interrupt Control 0000h Register SOEIC FF70h B8h Serial Channel 0 Error Interrupt Control 0000h Register S1TIC FF72h Serial Channel 1 Transmit Interrupt Control 0000h Register S1RIC FF74h Serial
79. Rounding Error 1 2LSB Rounding Error 1 2LSB Rounding Error 1 2LSB 157 SGS THOMSON 15 26 MIGRCELECTREMICS 5 Central Processing Unit N Flag For most of the ALU operations the N updated byhardware upon the enyrinto an inter flag is set to 1 if the most significant bit of therupt service routine but it can also be modified by result contains a 1 otherwise it is cleared In software to prevent other interrupts from being ac the case of integeioperations the N flag can knowledgedln the case that an interrupt level 15 be interpreted as the sign bit of the result has been assigned to the CPU it has the highest negative N 1 positive N 0 Negative num possible pridty and thus the current CPU opera bers are always represented as the 2 s com tion can not be interrupted except by hardware plement of the coespondingpositive number traps or external non maskable interrupts For de The range of gnednumbers extends from tails about the ST10x166 interrupt system see 8000h to 7FFFh for the word data type or chapter 7 from 80h to 7Fh for the byte data type After reset all interrupts agdoballydisabled and the lowest priority ILVL 0 is assigned to the initi For Boolean bibperationswith only one oper tial CPU activity and the N flag represents the previous state of the specified bit For Boolean bit operations with twooperands the N flag represents the 5 3 4 3 HOLD HLDA BREQ BUS
80. SP writing and any ticeable for the user in most of the cases subsequent of the just mentioned implicitly SP using However there are some very rare caseswhere instructions as shown in the following example must pay attention to the circumstance that the In MOV SP 0FA40h ST10x166 is a pipelined machine Intelligent selecta new top of stack ST10x166tools like the simulator and the emulator is support the user by easing the association with the must not be aninstructigropping following particular pipeline effects operands from the system stack 1 2 POP RO pop the word value from the new top of a Context Pointer Updating Stack into GPR 0 Aninstruction which calculatesa physical GPR oper and address via the CP register is mostly not capa ble of using a new CP value which is to be updated External Memory Accossoquences by an immediately preceding instruction Thus if oneThe effect described here will only become notice surely wants the new CP value to be used one must able if one looks at the external memory access se put at least one instruction between a CP changing quences on the external bus i e by means of a anda subsequent GPR using instruction as shown Logic Analyzer Differemipelinestages can si in the following example multaneoufy put a request on the External Bus Controlle EBC Since thepredefinedpriority of In mu Mrd oM di external memory accesses is as follows 1st Write Data 2n
81. T3IN which is an alternate function fosc 40MHz To ensure that a transition of the of P3 6 The event causing an increment or decre COUN input signal which gpliedto is cor ment of the timer can be a positive a negative ectly recognized its leveheuldbe held for at both a positive and a negative transition at this pin ast 8 state times before it changes Figure 8 19 The options are selected by bit field T3l in control Shows a block diagram of the core timer in this register T3CON as shown in table 8 8 mode Table 8 8 GPT1 Core Timer T3 Counter Mode Input Selection 9 o 1 Positive External Transition at Pin T3IN Counter T3 in Incremented Decremented on oo a o Negative External Transition at Pin T3IN 3 1 Positive and Negative Ext Transition at T3IN Figure 8 19 Block Diagram of Core Timer in Counter Mode Interrupt Request VROB1B41 26 64 Gr SGS THOMSON TT 8 Peripherals 8 2 1 1 4 Interrupt Control for Core Timer T3 When the timer overflows from FFFFha600h T2CON FF40h AOh GPT1 Auxiliary Timers T2 Control Register when counting up or when it underflows from 0000h to FFFFh when counting down interrupt Value request flag T3IR in register T3IC will be set This 15 14 13 12 11 10 9 8 will cause an interrupt to the timer interrupt tor T3INT or trigger a PEC service if the interrupt enable
82. T4 One can select either a positive a nega tive or both a positive and a negative transition at these input pins to cause a reload When a se lected transition is detected at the input pin T2IN or TAIN the core timer is reloaded with the con Figure 8 24 GPT1 Auxiliary Timer in External Reload Mode Edge Select TxIN P3 7 P3 5 32 64 Relood Register Tx Interrupt Request Interrupt Request VROG1641 SGS THOMSON o MICROELECTRONICS 8 Peripherals Figure 8 25 GPT1 Auxiliary Timer in Reload Mode Triggered by T30TL Edge Select Reload Register Tx Interrupt Request Up Down x 2 4 T30E Interrupt Request Note Line only affected by over underflows of T3 but NOT by software modifications of T3OTL tents of the auxiliary timer and the interrupt re quest flag T2IR or TAIR of the auxiliary timer is set The direction control bits DP3 7 for T2IN or DP3 5 for TAIN must be set to 0 and the input signal should hold its level for at least 8 states to ensure correct recognition of the triggering edge Figure below shows a block diagram of this external re load mode When bit 21 2 1 or bit 41 2 1 a transition of the toggle bit which is caused by an over flow underflow of T3 is the trigger for a reload Note that software modifications of TSOTL will NOT trig ger the reload function Again one can select either a positive a negative or bo
83. The followingalgorithm describes how physical addresses are generated via indirect address pointers 1 Determination of the physical address of the word GPR which is used as indirect address pointer This address is calculated via the reg ister bank base address specified by the CP register contents plus two times the specified short address Rw GPR Address CP 2 x Short Address 5 Table 6 4 Indirect Addressing Modes Rw Normally any word GPR can be used as indirect address pointer For some instructions however only the first tour word GPRs can be used as indirect address pointers In case of pre decrement signified by a lead ing minus sign the indirect address pointer is decremented by a data pe dependent value 1 for byte operations 2 for word operations before the long 16 bit address is generated GPR Address GPR Address optional step Then the long 16 bit address is determined by the contents of the indirect address pointer plus a selectable constant value in some cases Long Address GPR Address Constant Afterwards the physical 18 bit address is de termined via theresulting long address and the correpondingDPP register contents as al ready described for the long mem addressing modes For more details about data paging see section 5 3 7 In case of Post Increment signified by a sub sequent plus sign the indirect address point
84. There are port lines however 0 has both alternate input and alternate output where the direction of the port line is switched auto unctions while 1 P Y d Mb ue matically For instance in the multiplexed external unction Figure 10 2 shows the structure of a Port bus modes of Port 0 the direction must be 0 pin and figure 10 3 shows the structure of a Port switched several times for an instruction fetch in P n order tooutput the addresses and to input the data When an external bus mode is enabled the direc Obviously this can not be done through instruc tion of the port pin and the data input to the port out tions In these cases the direction of the portline isput latch are controlled by the bus controller switched automatically by hardware if the alternatehardware The input to the port output latch is dis function of such a pin nabled connected from the internal bus and is switched via There is one basic structure for all port lines with multiplexer to the line labeled Alternate Data Out only an alternate input function Port lines with onlyPUt On Port 0 cun n the 1 6 bit an alternate output function however have differ Intra segment address or the 8 16 bit data informa ent structures due to the way the direction of the tion On Port 1 the alternate data is the 16 bit intra pin is switchednd depending orwhether the pin segment address in the non multiplexed bus mode is accessible by the user soft
85. Unit GPT1 16 Bit Timer T2 16 Bit Timer T3 16 Bit Timer T4 16 Channel Capture Compare Unit 16 Bit Timer T1 External Bus Controller Ports Ks SGS THOMSON MICROELECTRONICS 16 Bit Timer T5 16 Bit Timer T6 1 Architectural Overview 10 Channel 10 Bit A D Converter Serial Channel ASCO Serial Channel ASC1 VR001622 5 6 1 Architectural Overview 1 2 5 Clock Generator 1 2 6 Peripherals and Ports The on chip clock generator contains a prescaler The ST10x166 also contains which divides the external clock frequency by 2 Thus the internal clock frequency is half the exter nwo Docks Orgeneral Purpose mets nal clock frequency 40MHz at internal capture compareunit clock frequency 20MHz Two separated clocks two serial interfacehannels are generated for the CPU and the peripheral part of the chip While the CPU clock is stopped during am AD converter wait statesor during the idle mod he peripheral watchdog timer clock keeps running Both clocks are switched off six I O ports with a total of 76 I O lines power downiamodels entered Each peripheral also contains a set of SFRs which control the functionality of the jdreral and tem porarily store intermediate data results Each pe ripheral has an associated set of status flags Individually selected clock signals ayenerated for eachperipheralfrom binary multiples of the system clock 6
86. a block diagram of T5 in timer mode 8 2 2 2 2 Counter Mode The counter mode of timer T5 selected by T5M 1 can only be used in conjunction with the toggle bit T6OTL of the core timer T6 since timer T5 has no external input pin In this mode timer T5 is clocked by a transition of T6OTL Note that only state transitions of T6OTL which are caused by overflows underflows of T6 will trigger the counter function of T5 Modifications of T6OTL by software will NOT trigger the counter function of T5 Either a positive a negative or both a positive and a nega tive transition of TGOTL can be selected to cause an increment or decrement of T5 The options are selected by bit field T5l in control register 5 FF66h B3h GPT2 Timer 5 Interrupt Control Register Reset Value 0000h 7 6 5 4 3 2 1 0 Table 8 14 Auxiliary Timer T5 Counter Mode Input Selection memes Dub Counter T5 is Incremented Decremented on s Poste Tanstionot Teont t Negative Transiionof Toot Postve and Negative Transition of T6OTL Figure 8 31 Block Diagram of GPT2 Auxiliary Timer T5 in Counter Mode Edge Select Auxiliary Timer T5 40 64 Interrupt Request VROM1641 Ey SGS THOMSON MICROELECTRONICS 8 Peripherals as shownin table 8 14 Figure below shows a block diagram oftimer T5 in this mode This mode can be used to concatenate the core t
87. after this step mov FCR ALLO reset FCRand exit pro gram mode mov FCR fc rval sg 565 THOMSON 1 19 Fl icrosuscrmenics MEMOPY THE IIPEXTO EPAXE The followingsection explains the Presto F Erase Algorithm shown in figure 6 but all parts already de scribed in the previous section will noebplainedagain Note that an entire block will be erased instead of oneor two words as programming AAA QOPAZ 00001 Prior to erasure program all block addresses to 0000h This stpmlizesthe charge on each memory cell of the block Erasure removes charge from all memory cells regardless of their previous state and not performing this programming will drive cells previously at a one to be stuck at Fundamentals of Flash memory section The Presto F Program Write Algorithm is used for this block programming refer to the previous section GAPIABAEINITIAAIZATION Initialize two vdables N 0 for the pulse count and the address variable to the first address of the block N can be incremented from 0 to 3000 Note with each pulse all the block will be erased XETYII XOMMANA INTO As for programming this step only prepares the device for erasure Set FWE FEE bits to enable erasure Clear CKCTLO amp set CKCTL1 bits to define a 10 ms erasing time Choose the block configuration for erasure BEO BE1 Clear WDWW bit
88. and Loop Control Instructions Shift and Rotate Instructions Prioritize Instruction Data Movement Instructions System Stack Instructions Jump and Call Instructions Return Instructions System Control Instructions Miscellaneougnstructions lowing instruction classes Arithmetic Instructions Logical Instructions Boolean BiManipulaion Instructions MICROELECTRONICS The basic instruction length is either 2 or 4 bytes Possible operand types are bits bytes and words A variety of direct indirect or immediate address ing modes are provided to specify the required op erands 3 6 2 System Description 2 4 INTERRUPT SYSTEM bit in the trap flag register TFR Except another higher prioritized trap service being in progress a With an interrupt response time within a range fromhardware trap will interrupt any actual program just 250ns to 500ns in case of internal program execution In turn hardware trap services can nor execution the ST10x166 is capable of reacting mally not be interrupted by standard or PEC inter very quickly to the occurrence of non deterministicrupts events The architecture of the ST10x166 supports several 2 5 CAPTURE COMPARE CAPCOM UNIT mechanisms for fast and flexible response to serv ice requests which be generated from various The CAPCOM unit supports generation and con Sources internal or external to the microcontroller trol of timing sequences on up to dBannelswith Any o
89. are both organ ized identically Note that functions which are present in all 3 timers of block GPT1 are controlled in the same bit positions and in the same manner in each of the specific control registers The control registers for thauxiliarytimers are shown below T4M n SGS THOMSON 27 64 MICROELECTRGNICS 8 Peripherals Table 8 9 GPT1 Auxiliary Timer T2 and T4 Mode Control T2M T4M wm Co o o heo o os emm 2 s o o9 UNE EM o O The operating modes for the auxiliary timers T2 selected for thauxiliay timers T2 or T4 by setting and T4 are independentlyselectable by bit fields the mode control field T2M or in the respec T2M and T4M The availableoptions for both tim tive control register T2CON or TACON 10006 ers are listed in table 8 93nd will be disussedin input frequencies and fra to T2 and T4 are detail thdollowingubsections determined by the contents of the timer input se In all of the counting modes of operation the auxil lection fields 21 and T4l as follows iary timers can count up or dowspendiry on the state of their control bits T2UD and T4UD They fio fosc fr4 fosc can be started or stopped through their run bits 16 2172 16 x 27745 T2R and T4R In gated timer mode the respective timer will only run if T2R 1 or T4R
90. before an overflow occurs an internal hardware re set will be initiated This internal reset will also pull the RSTOUT pin low see chapter 11 When the software has been designed to service the Watch dog Timer before it overflows the Watchdog Timer times out if the program does not progress prop erly The Watchdog Timer will also time out if a software error was due to hardware related fail ures This prevents the controller from malfunc tioning for longer than a user specified time The Watchdog Timer is a 16 bit up counter which can be clocked with either the oscillator frequency fosc divided by 4 or with fosc 256 The upper 8 bits of the Watchdog Timer can be preset to a user programmable value in order to vary the watchdog time Figure 8 43 shows a block diagram of the Watchdog Timer while Figure 8 44 shows the SFRs and the reset indication pin RSTOUT which are associated with the Watchdog Timer Watchdog Operation The current count value of the Watchdog Timer is contained in the Watchdog Timer Register WDT which is a non bit addressable READ ONLY regis 62 64 ter The operation of the Watchdog Timer is con trolled by the bit addressable Watchdog Timer Control Register WDTCON shown hereafter After any software external hardware or Watch dog Timer reset the Watchdog Timer is enabled and starts counting up from 0000h with the fre quency fosc 4 The Watchdog Timer can be dis abled via the instruction DISWDT
91. being set ceive the value from the internal bus The hard ware triggered change will be lost During an external HOLD request an amp wledged the ST10x166 set the external address data and control bus to the following states In order to support multi master systems and com munication with external DMA functions three pins of Port2 provide a bus arbitration Port 0 Tri state if an external bus is HM enabled The pin P2 15 configured in its alternate function HOLD is input When brought to low active Port 1 Tri state if a non mitiplexed state this input indicatesto the ST10x166 thatan bus mode is selected other master wants to perform one or several ac Port4 Tri state if an external bus and cesses on the external bus of the ST10x166 After segmentation are Babled synchronisation of this signal and complete g nation of the current external bus cycle if any the ST10x166 backs off its external bus and activates __ Float to 0 through high imped ance pull down the signaHLDA to flag the second master that the RD Float to 1 through high imped bus is now free This condition will be held until the ance pull up HOLD line goes back to high Then the signal WR Tri state even when used as HLDA is disabled and the ST10x166 takes over general purpose I O pin control of the external bus again if required During 4 the HOLD phase the ST1 0x1 66 can still operate SBHE Tri state
92. bit field in the SYSCON register The address space which can be addressed via the SP register addresses from OF800h to OFFFEh can be regarded as virtual stack range while the physical system stack range is forced by the hardware to be situated within the internal RAM with its uppeboundaryat address OFBFEh and with its lower boundary at the memory location which is specified by the selected maximum stack size shown intable 5 Dependingon the selected maximum stack size different numbers of signifi cant SP bits are used for the physical address cal culation while the remaining bits are masked off After reset the SP register iinitializedin a way that the system stack can be accessedas usual as long as the dynamic stackoundariesdo not ex ceed the selected maximum stack size This means that the virtual SP contents are directly mapped onto identical physical system stack ad dresses The virtual stack address space isilsdividedin portions whose size is identical to the maximum size of the selected physical stack space All of these virtual stack portions are mapped onto the availablephysical stack area by means of an ad dress calculation shown in tfedlowingA number of significant bits of the inverted SP contents is subtracted from the upper stack base address OFBFEh An AND mask being changed gending on the STKSZ bit field determines which of the bits are significant Context Pointer 22 26 SGS THOMSON MICROEL
93. bit or 9 bit data frame selected by bit fields SOM S1M One or two stop bits SOSTP S1STP in SOCON S1CON Figure 8 40 shows an information frame with an 8 bit data frame DO to D6 are data bits D7 can be configured as the 8th data bit 8 bit data mode or as the parity bit 7 bit data parity bit mode Figure 8 41 shows an information frame with a 9 bit data frame DO to D7 are data bits D8 can be configured to either be the 9th data bit 9 bit data mode the parity bit 8 bit data parity bit mode or the special wake up bit used in multiprocessor communication 8 bit data wake up bit mode Asynchronous Transmission selected by bits control registers 54 64 A transmissionis initiated by writing the data to be transmitted into the transmit data buffer register SOTBUF or S1TBUF respectively However a transmission will only be performed if the corre sponding baud rate generator run bit SOR 1 or S1R 1 at the time the write operation to the transmit buffer occurs Transmission then starts at the next overflow of the divide by 16 counter see figure 8 39 First the start bit will be output on the associated transmit data output pin TXDO or TXD1 followed by the selected number of data bits LSB first In the two modes with parity bit generation the parity bit will automatically be generated by hardware and inserted at the MSB position of the data frame during transmission When one stop bit has been selec
94. bit result For sents he low order16 bits of the 32 bit result For long divisions the MDH register must long divisions MDL must be loaded with the low or with the high order 16 bits of the 32 ividencbe der 16 bits of the 32 bit dividend before the division fore the division is started After any division theis started After any division the MDL register rep MDH register represents the 16 bit remainder resents the 16 bit quotient Whenever this register is updated via software the Whenever this register is updated via software the Multiply Divide Register In Use MDRIU flag in the Multiply Divide Register In Use MDRIU flag in the Multiply Divide Control register MDC is set to 1 MultiplyDivide Contol register MDC is set to 1 When a multiplication or division is interrupted be The MDRIU flag is cleared whenever the MDL reg fore its completioand when a new muiply or di ister is read via software When a multiplication or vide operation is to be performed in the interruptdivision is interrupted before its completion and service routine the MDH register must be saved When a new multiply or divide operation is to be along with the MDL and MDC registers to avoid er performed in the interrupt service routine the MDL roneous results register must be saved along with the MDH and After reset this register is initialized 600h MDC registers to avoid erroneous results A detailed description of how to use the
95. code accesses For the non segmented abled memory mode or the Single Chip Mode the con tents of this register are not significant because all code acccesses are automatically restricted to segment 0 Note that the CSP register can only be read but not written for data operations It is however modified either directly by means of the JMPS and CALLS instructions or indirectly via the stack by means of the RETS and RETI instructions Upon the accep tance of an interrupt or the execution of a software TRAP instruction the CSP register is automatically set to zero After reset the CSP register is initial ized to 0000h Figure 5 5 Addressing via the Code Segment Pointer Code segment 3FFFF CSP Register IP Register 15 415 0 16 Bit Intra Segment Address 15 SYSCON SGTDIS 00000 18 Bit Code Address 18 Bit Address Space VR001621 SGs THoMson 175 venous TROBICS 5 Central Processing Unit 5 3 7 DPPO DPP1 DPP2 DPP3 Data Page FEOOh 00h Pointers Data Page Pointer Registers These four non bit addressable registers select up Reset Value 0000h to four different data pages being active at run time Currently only the fourleastsignificantbitsof 15 4 13 12 11 10 9 8 each DPP register are implemented whilethe bits amp R R 4 to 15 are reserved for future use The DPP regis ters allow accessing the entire memory space in
96. consists of a RISC like architecture with a 16 bit ALU 4 stages of instruction pipeline and dedicated Special Function Registers SFRs and a CISC like instruction set for the high performance CPU 10 million instructions per second Intelligent peripherals have been integrated to reduce the need for CPU intervention to a minimum extent The ST10 family includes a 10 channel Analog to Digital Converter with 10 bits of resolution and 9 75us of conversion time Multifunction Timers a Capture Compare unit 2 serial channels USARTS offering 625Kbaud in full duplex asynchronous communication and 2 5Mbaud in half duplex synchronous communication an 8 channel Peripheral Event Controllerallowing data transfer in only 1 instruction cycle time and 76 I O lines with individual bit addressability Based on a von Neumann architecture up to 256Kbytes of linear address space for code and data can be accessed with the External Bus Controller interface This high performance 16 bit microcontroller family with its different sets of on chip peripherals and the FLASH memory technology meet the requirements of real time control applications such as automotive engine control industrial control and data communication In addition many applications require program or data updating during the product life In the same way it can be very helpfulto modify the program duringthe developmentor production phase in many control applications With the on chip Flash memory of
97. fer x 4 sg SGS THOMSON 98 10 Parallel Ports Alternate Input and Output Functions of PO bit addressable and eachline can be programmed through P4 individually for input or output When no external Each of the 76 port lines of the 80 166 hasan Program and or data memory is connected to the alternate input um output function associated with Port 0 PO and Port 1 P1 can be used as 34 port lines have both an alternate input and out Jeneral purpose ports put function the other 42 lines have either an alter As described in Chapter 9 ports PO and P1 are nate inputor an alternate output function used as the address and data lines in the various If an alternate output function ofa pin is to be used PYS configurations which be selected for con the direction of this pin must be programmed fo necting external memory to the chip Port 0 is used output DPx y 1 Otherwise the pin remains in in all 4 external bus configurations while P1 is only the high impedane state and is notaffected by the used as the address bus A15 AO in the 16 18 bit alternate output function Address Non Multiplexed Bus mode Port 1 can be i X used as a general purpose I O port in the multi If an alternate input function of a pin is used the di plexed external bus configuration modes rection of the pin must be programmed for input SER DPx y 0 if iis external driving the Di When a multiplexed bu
98. for control unit a bit mask generator and a barrel shifter ling and monitoring functions of the different on Based on these hardware provisions most of the chip units 118 SFRs are currently implemented sT10x166 sinstructions can be executed in just Unused SFR addresses are reserved for future one machine cycle which requires 100nsat 20MHz members of the ST10x166 family CPU clock For example shift and rotate instruc In order to meet the needs of designs where more tions are always processed during one machine memory is required than is provided on chip up tocycle independentof the number of bits to be 256Kbytes of external RAM and or ROM can be shifted All multiple cycle instructions have been connected to the microcontroller optimized so that they can be executed very fast as well 32 bit 16 bit division ind a 16 bit x 16 bit multiplication in 0 4 and branches in 200ns An 2 2 EXTERNAL BUS CONTROLLER other pipelineoptimization the Jump Cache al lows reducing the execution time of repeatedly All ofthe external memory accesses are performed performed jumps in a loop from 200ns to 100ns by a particular on chip Bus Controller Thig CPU disposes of an actual register context EBC It can be programmed to either the Single consictina ot up to TordwldeGPRs which af Chip Mode when no external memory is required il p dwithln th M 9 or to one of four different external memory access h Con y allocated with
99. h There tore only ipsapebon or capone d Therefore to write the FLASH memory the FWE bit reads are performed in this mode with all the a of FCR register has to be set to 1 dressing modes of the ST10x166 instruction set To enter the Write Program mode the FEE bit of No read or write operations on the FCR register FCR register has to be cleared If FEE and FWE of are possible in this mode except the protection bitECR register are set to 1 the Erase mode is en RPROT which can be modified in this mode but tered only from a program instruction within the FLASH memory In these two modes a Verify mode is automatically entered whenthe programming or erase operation is ended respectivly Program Verify Mode PVM and Erase Verify Mode EVM Figure 4 2 Flash Modes Description FLASH MODES FUNCTION VROG1B45 2 8 SGS THOMSON MIGRCELECTREMICS 4 Flash Memor FLASH CONTROL REGISTER During the normal operation mode the FLASH memory is read as normal ROM memory with all 00000h to 02FFFh addressing modes of the ST10x166 03000h to OSFFFh All programming or erase operations of the EID FLASH memory are controlled via the Flash Con trol Register FOR b7 WDWW if setat a logical 1 enables a 32 bit To prevent inadvertent writing of the FLASH mem operation otherwise it will be a 16 bit operation At FCR is locked and inactive during the normal 0 during reset operation
100. hold the address data which was interrupt system the CPU does not return to Idle output during the last external memory access be mode but restarts normal program execution with fore entry into Idle mode under thalbwingeondi the instructiofollowinghe IDLE instruction tions The Idle mode can also be terminated by a Non On 0 15 8 Port 0 outputs the high byte of the Maskable Interrupt through a high to low transition last transferred address if the 16 18 bit ad theNMI pin After the Idle mode has been termi dress 8 bit data multiplexed bus mode is nated by an interrupt or NMI request the interrupt used otherwise all pins of Port 0 are floating system performs a round of prioritization to deter Pins PO 7 0 are always floating in Idle mode mine the highest priority request In the case of an port 4 floats if the non midtexed bus mod s NMI request the NMI trap will always be entered used otherwise Port 1 Bus as a general pur Any interrupt request whosindividuallnterrupt pose port Enable flag was set before the Idle mode wasen _ port 4 outputs the segment address for the last tered will terminate the Idle modegardlessof the access if segmentation ienabled otherwise current CPU priority The CPU will NOT go back 4 acts us a general purpose I O port into Idle mode when a CPU interrupt request is de tected even when the interrupt was serviced DuringPower Down mode the clocks to the CPU because of a
101. implemented in the core CPU The first aids in nor Compare targetto table entry malizing floating point numbers by indicating the position of the first set bitin a GPR One can then NET LOOP use this result to rotate the floating point result ac Test whethertargetis not cordingly The second feature aids in properly found AND the end of table has not roundingthe result of normalized floating point been reached numbers through the overflow V flag in the PSW This flag is set when a one is shifted out of the carry Note The last entry in the table must be equal to bit The overflow flag and the carry flag are then the lowest signed integer 8000h used to round the floating point result based on the desiredroundingalgorithm 13 8 PERIPHERAL CONTROL AND INTERFACE 13 10 TRAP INTERRUPT ENTRY AND EXIT All communication betweeperipheralsand the Interrupt routines are entered when a requesting CPU is performed either by PEC transfers to and interrupt has a priority higher than the current CPU from the internal memory or by explicitly address priority level Traps are entera gardles of the ing the SFRs associated with the specific peripher current CPU priority When eithera trap or interrupt als After resetting the ST10x166 all peripherals routine is entered the state of the machine is pre except Watchdog Timer are disabled and initial served on the system stack and a branch to the ap ized to default values To progr
102. implicitly by the system and is contained in the internal RAM The second type provides stack access to the user in either the in ternal or external memory Both stack types grow from high memory addresses to low memory ad dresses and are described in thelfowingsubsec tions 13 4 1 Internal System Stack A system stack is provided to store return vectors segment pointers and processor status for proce dures and interrupt routines A system register SP points to the top of the stack This pointer is de cremented when data is pushed onto the stack and incremented when data igopped internal system stack can also be used to tem porarily store data between subroutines or tasks Instructions are provided to push or pop registers on from the system stack However in most cases the register banking scheme provides the best per formance for saving state between multiple tasks rupted multiply divide instruction will then be comNote THE SYSTEM STACK PERMITS STOR pleted after the RETI instruction has been executed Interrupt routines which require the use of the mu tiply divide hardware MUST first push and then clear the MDC register before starting a multiply di AGE OF WORDS ONLY Bytes can be stored on the system stack but must be extended to words first One must also consider that only even byte addresses can be stored in the SP register LSB of SP is always 0 vide operationif a multiply divide instruc
103. in the SYSCON for timing requirements of exterpslripheralsAs egister as shown in table 9 6 One Read Write shown in figur9 14 the Read Write Delay repre Signal Delay requires a quarter of a machine cycle sents the period of time between the falling edge 2515 at bsc 40MHz the Address Latch Enable ALE signal and the fall ing edge of the or write WR signal If no Table 9 6 RWDC Encoding of The Read Write additionalRead Write Delay is programmed the Signal Delay falling edges of the ALBVR and RD signals are coincident With the delay programmed the falling edge of the ALE signal leads the falling edges of the RD orWR signal by a quarter of a machine cy 0 Embed cle An additional Read Write Delay does not ex tend the Memory Cycle Time and thus it does not pissed slow down the controller in general These programmable Read Write Signal Delays can be specified for all of the external bus configu ration modes Figure 9 14 Memory Read Write Signal Delay Read Write Delay scouent X aus Po Datanet tue y C VROF1533 16 20 SGS THOMSON o MICROELECTRONICS 9 External Bus Interface 9 8 4 ALE signal delay The ST10x166 allows the user to adjust the Ad must be lengthened This feature is provided by dress Latch Enable signal to account for the ad the ST10x166 with the ALECTL1 bit of BUSCON1 dress setup and hold time of the external register co
104. is generated Cleared otherwise Setif the most significant bit of the result is set Cleared otherwise INSTRUCTION FORMAT BXO Taoxtvy Mvenoviy Mvenoviy Onepav o Byteo SUBC SUBC Rw Rwm 30 nm 2 SUBC SUBC Rw datag 38 n 0 2 SUBC SUBC reg datag 36 RR 4 SUBC SUBC Rw Rw 38 n 10ii 2 SUBC SUBC Rw Rw 38 n 11ii 2 SUBC SUBC reg mem 32 RR MM MM 4 SUBC SUBC mem reg 34 RR MM MM 4 80 84 5 S amp S THOMSON A Ivotpuxuov Let LYBXB WITH Xappy 2 OPERATION 1 lt op1 op2 C DATATYPES BYTE Performs a 2 s complement binary subtraction of the source operand specified by op2 and the previously generated carry bit fromthe destination operand specified by op1 The re sult is then stored in op1 This instruction can be used to perform multiple precision arith metic FLAGS E 2 V E Setifthe value of op2 representsthe lowest possible negative number Cleared oth erwise Used to signal the end of a table Set if result equals zero and previous Z flag was set Cleared otherwise Set if an arithmetic underflow occurred i e the result can not be represented in the specified data type Cleared otherwise C Setifa borrow is generated Cleared otherwise Setif the most significant bit of the result is set Cleared otherwise lt N INSTRUCTION FORMAT BXO Taoxtivy Onepav
105. is pro vided to increase the reliability of data transfers For multiprocessor communication a mechanism to distinguish address from data bytes is included and a loop back option is available for testing pur poses Each serial channel has separate interrupt vectors for receive transmit and error and each channel has its own dedicated baud rate gener ator This is a 13 bit timer with a 13 bit reload reg ister which supports a wide range of baud rates without oscillator tuning Figure 8 38 gives an overview of the SFRs and port pins which are associated with the serial channels Those portions of Port 3 and its direction control register DP3 which are not used for alternate func tions by the serial channels are not shaded 8 4 1 Modes of Operation The operation of the serial channels ASCO and ASC1 is controlled by the bit addressable control registers SOCON and S1CON which are shown below They contain control bits for mode and error SOCON FFBOh D8h Serial Channel Control Register SOCON Reset Value 0000h 15 14 13 12 11 10 9 8 son sos soems sore sore 7 6 5 4 3 2 1 0 157 SGS THOMSON S1CON FFB8h DCh Serial Channel Control Register S1CON Reset Value 0000h 15 14 13 12 11 10 9 8 sue sens a soe 7 6 5 4 3 2 1 0 b15 SxR ASCx Baud Rate Generator Run Bit The Baud Rate Generator is enabled if SxR 1 b14 SxLB Loop Back Mode Enable Bit The Loop Back Mode is
106. may also bedividuallgl located to either timer TO or T1 Figure 8 13 shows a timing example for this compare mode In this ex ample the compare values in registers CCx and CCz are not modified 17 64 MICROELECTRONICS 8 Peripherals Figure 8 12 Double Register Compare Mode Block Diagram Compare Reg CCx Interrupt Request Interrupt CAPCOM Timer Ty Request Interrupt Compare Reg CCz Request FFFFh Compare Value CCz Compare Value CCx Reload Value TyREL gt 0000h Interrupt Requests CCxIR t CCxIR TyIR State of CCxlO 0 VR001639 18 64 Gr SGS THOMSON TTT 8 Peripherals 8 1 2 3 CAPTURE COMPARE INTERRUPTS 8 2 GENERAL PURPOSE TIMERS GPT Upon a capture or compare event the interrupt re quest flag CCxIR for the respective capture com unit represents a very flexible multifunc pare register CCx is set to 1 This flag can be used tional timer structure which may be used fortiming to generate an interruptor trigger a PEC servicere event counting pulse width measurement pulse quest whenenabled by the interrupt enable bit generation frequency multiplication and other CCxIE purposes It incorporates five 16 bit timers that Capture interrupts can be regarded as external in been divided two blocks nd terrupt requests with the additional feature of re cording the time at which
107. memory ac cesses made externally sg SGS THOMSON 55 3 Memory Organization Figure 3 3 Memory Organization SI9L00HA AHONW3WNW IVNWHA2LIX3 IVNH3 LENI AYOWAW IVNHA ENI 0 e qesseJppy 19 400 30 epoo 10 eM gML HSV14 HSV14 ys 5 5 1 sei gMzcE 43 540 Jejuiog 1921 Jejuiog z TU 10 Kiowan Aoway Sevawee 1xejuo2 400008 seiAgMS 0 Erie sei gyro BuJ01X3 Kowa s gyzE 2 2 BuJ9 X3 9391 4433430 921006 53d 400340 SH4S 5149219 e MIGROELECTRONICS SGS THOMSON 4 10 3 Memory Organization 3 1 INTERNAL PROGRAM MEMORY 3 2 EXTERNAL MEMORY The Program memory is an on chip mask pro Basically the ST10x166 provides for up to 4 x grammable ROM for the ST10166 and on chip 64Kbytes of external ROM and or RAM which may programmable FLASH memory for the ST10F166 be organized in either 8 or 16 bits Since a part of The memory is organized in 8Kx32bits and the first 64Kbytes address space is already occu mapped in the same segment memory segment pied by the on chip memory areas only 62 5Kby during reset or segment 1 if remapped during in tes 30 5Kbytes for the ST10F166 and ST10166 itia
108. modes The FLASH memory mustbe set into the Write mode to provide valid access to the 05 6 CKCTL0 1 select the FLASH internal timer FCR A key code sequence is used to enter the 85 Shown in Table below Write mode In state 0 during reset The FCR is virtually located within the address TPRG space of the FLASH memory it does not occupy CKCTL1 CKCTLO 1 TCL 210 40MH an absolute address and is only accessed with a ZAN d direct addressing mode 4 10 TCL When the segmented memory mode abled 4 10 TCL the data page pointer must beoasideredfor all 4 10 TCL FCR accesses 4 10 TCL Note 1 Accordingto the IEEE Standard on floating gate arrays thedllowingerminology is used writ The maximum programming pulse PT allowed is ing means a state change of the floating gate pro 2001s with a maximum programming time of gramming means th oadingof electrons onto the 2 5ms Therefore the value 00b covers all the fre floating gate erase means the removal of elec quency range trons from the floating gate The maximum erasing pulse ET allowed is 10ms with a maximum erasing time of 30s FCR At 20MHz CPU clock 11b is the remmended value At 1MHz CPU clock 01b is the recom Flash Register mended value For all otherdquencies 10b is Reset Condition6000h recommended 15 M 13 12 1 10 9 8 b4 VPPRIV READ ONLYbit reflects the status of VPP in the write mode If VPP is not highoug
109. non multiplexed bus to a multi vice versa or can use the READY function ina cer Plexed bus an extra hold state is required due to tain addressrange while operating without READY timing constraints In addition Port 1 which is in theremainingaddress range This can either be USed for the address bus continues to output the done by using the SYSCON and BUSCON1 regis address although the address will also appear at ters with different parameters in certain address 0 time multiplexed with the data This has the ranges or by reprogramming the SYSCON or advantage that the chip select logic which is tied BUSCON1 register prior to an access which 9 the address bus does not have to either be should be performed with different bus charac SWitched from Port 1 to Port 0 or vice versa Figure teristics However it is not recommended or very 9 16 shows a timing diagram for switching from a useful to modify the SYSCON or BUSCON1 regis 9n multiplexed bus to a multiplexed bus ter which is currently being used for instructiorNote As long as any SYSCON or BUSCON1 se fetches since pipeline effects can make it very dif lects a non multiplexed bus Port 1 is dedicated for ficult to determine which of tiiellowingaccesses the address bus function and can not be used as will be made with the new configuration Thus it is general purpose I O port In order to use Port 1 for recommended to modify bus configuration regis general purpose I O both the SYSCO
110. performed to any vector lo trap service in case simultaneous trap conditionscation between and 1FCh A routine entered by might be detected within the same instruction Af sottware TRAP instruction is always executed ter any reset hardware reset software reset in the current CPU priority level whictiislicated in struction SRST or reset by watchdog timer the ILVL field in the PSW This means that routines overflow program execution starts from locationentereq via the software TRAP instruction can be 0000h Reset conditionshave priority over every other system activity have the high nierowerodepsothidberdevenin Table 7 2 Reset And Trap Vector Locations Trap Trap Vector Trap Trap Reset Functions Hardware Reset Software Reset Watchdog Timer Overflow Class A Hardware Traps Non Maskable Interrupt NMITRAP Stack Overflow STOTRAP Stack Underflow STUTRAP Class B Hardware Traps Undefined Opcode UNDOPC Protected Instruction Fault PRTFLT Illegal Word Operand Access ILLOPA Illegal Instruction Access ILLINA Illegal External Bus Access ILLBUS Software Traps TRAP Instruction Any Any Current Oh 1FCh 08 778 CPU in steps Priority of 4h 7 2 NORMAL INTERRUPT PROCESSING AND PEC SERVICE The priority of service for interrupts and PEC re simultaneous requests from a group of different quests is completely programmable Each source sources onthe same priority level At the end of th
111. programmed to the same priority terrupt the executing routine level ney are Spat arate according beir oP Upon entry into an interrupt service routine the pri P lorlty where 3 is highest group priority This also ority level of the source that won the arbitration 1 that imultaneousequests for PEC service ioritized according to their PE hannel copied into the ILVL field of the PSW afteushing 218 priori 2 the old PSW contents on the stack number the PEC channel with the highest number has the highest priority ote All interrupt sources that asnabled and rogrammed to the same priority level must always The interrupt system of the ST10x166 allows nest ing of up to 15 interrupt service routines of different priority levels Note that an interrupt source whichpe programmed to different group priorities Oth EY the CPU PHONE level yh erwise an incorrect interrupt vector will be gener 4 ated never be higher than the CPU priority F 25 ii h bl f g Tun igure 7 2 exemplifies the possible configurations GLVL Interrupt Group Priority Field xxIC 1 0 which can be programmed in the interrupt control registers 7 2 1 2 INTERRUPT CONTROL FUNCTIONS IN THE PSW Figure 7 1 Mapping Of ILVL And GLVL Fields For The Interrupt Control Registers Interrupt GLVL Control Register SSS SSS SS Prioritization PEC Channel x pue C pe Priority Level e Group Priorit E 22222
112. pulled high Internal routine user condition SRST Boot Strap add 0000h FLASH routine ROM VROO1648 tne eGapimA Iv cto POAAOWLVY Qnev tne 16 wit the AXTLOVO pop THE OYoTELL NMI itvteppumt tne 10 166 16106 1 8 vo ove 2 S EU p TNE Bit po EDLYE Goto THE PEXETTLOV o TE Qt bet 8 Bu dun vo 2 be 2 Qurt avd ve pwede Dress avs pate 9600 Bavd op 1 3 Tpavojux 960 Bytes the Xovvexted noot Tne Aevyt 00 Aeoo nav 960 Bua ape vee8e8 THE trece 90 pito to TO YAAXVATE yose THE NAG TPAVOUIT SLY OLAA TE npeoxoAep TNE yevepatop Leplokne Bytes owe THE LOOT QUA VOT ovt 0 lo THE BYTE 960 Byteo pexeue 5511 16 TO THE YOVOLPL THAT THE XYOMMVVLYATLOV 16 TPOTEPAYW EOTABALONED povtive une 206 066 poypau THE tvtepva yape pe Tne
113. requiring wait states this will have no impact on the access time to theperipheal 2 When using the asynchronous READY func tion the first time thaEADY line is checked is near the falling edge of the ALE signal Thus in order to guarantee a correct bus cycle the READY line has to present a valid logic level at this time_point Some peripherals however hold theREADY line at a low state when they are not accessed and require some time after being addressed by the CPU to signal their not ready state i e bring thBEADY line to a one But if theREADY line is still low with the falling edge of the ALE signal the CPU interprets this as external device is ready and inserts no wait states during the following bus cycle This problem is eliminated since the CPU will first insert the programmed wait states before checking theREADY line Figure 9 17 a and b illustrate this feature In this example three wait states have been programmed 19 20 9 External Bus Interface in field MCTC of register SYSCON in addition to READY line is checked and found to be high The the READY function In Figure 9 17 a theEADY chip now continues to hold the memory access cy line goes to zero prior to the execution of the wait cle until th amp dEADY line goes to low Then the bus states but the chip continues to hold the memorycycle is terminated This example could be the access cycle until all wait states are performed case
114. technique should not be used _ Stack because of the overhead of flushing and filling 2 Initialize two pointers in the internal data mem To avoid movement of data that remains internally Ory which specify the uppand lower bound on the stack during flushing and filling a circular ary of the external stack These values stack mechanism has been implemented by mask then tested in the stack underflow and over ing off the higher bits of the stack pointer Thus flow trap routines only portions of the internal RAM that are flushed3 Initialize the stack underflow pointer to the bot or filled need to be moved Without this circular tom of the external stack and the overflow stacking the user would have to move each entry pointer to the value of the underflow pointer mi that remainedon the stack by the distance of the nus the size ofthe internal stack plus six words space being flushed or filled for the reserved space The circular stack technique requires that the inter Followinghis procedure the internal stack will fill nal stack be one of theoflowingsizes 32 64 128 until the ovet w pointers reached After entry to or 256 words the overflow trap procedure the top of the stack or overflow trap is entered where the user moves a Pointers will then be modified to reflect the newly predetermined portion of the internal stack to orallocated space After exiting from the trap proce from the external stack The amount of data trans dure
115. the ST10F166 flexibility and security are brought to these applications The ST10x166 family currently includes ST10R166 ROMless Version ST10166 mask programmable ROM Version for volume production ST10F166 reprogrammable FLASH Version for prototyping preproduction small volume and repro grammable applications Note In this document any reference to the ST10x166 can be applied to the different members of the family unless otherwise noted The ST10R166 is ROMIess and the ST10166 and ST10F166 are fully compatible except for the program mode of the FLASH memory of the ST10F166 All time specifications Ey SGS THOMSON 12 MICROELECTRONICS _ INTRODUCTION Die photo of ST10F166 with 32K on chip FLASH Memory 13 S amp S THOMSON FEATURES High Performance 16 Bit CPU With Four Stage Pipeline 100ns minimum instruction cycle time with most instructions executed in 1 cycle 500ns multiplication 16 bit 16bit tus division 32 bit 1 6bit High bandwidth internal data buses a Register based design with multiple variable reg ister banks Single cycle context switching support 256Kbytes linear address space for code and data von Neumann architecture System stack cache support with automatic stack overflow underflow detection Control Oriented Instruction Set with High Effi ciency Bit byte and word data types a Flexible and effi
116. the associated serial channel These registers are non bit addressable READ ONLY registers Bits in the upper half of SORBUF and S1RBUF which are not significant for the selected operating mode will be read as zeros Data reception is double buffered so that recep tion of a second character may already begin be fore the previously received character has been read out of the receive buffer register In all modes receive buffer overrun error detection can be se lected through bits SOOEN and S1OEN When en abled the overrun error status flag SOOE or S1OE and the error interrupt request flag SOEIR or S1EIR for the respective channel will be set when the re ceive buffer register has not been read by the time reception of a second character is complete The Ey SGS THOMSON MICROELECTRONICS 8 Peripherals Figure 8 39 Serial Channel Asynchronous Mode Block Diagram Reload Register V Baud Rate Timer SxSTP SxFE SxREN SxFEN SxPEN SxOEN SxLB t RXDO P3 11 RXD1 P3 9 Receive Buffer Reg SxRBUF x 0 1 previously received characterin the receive buffer is overwritten In each of the operating modes provided by the se rial channels of the ST10x166 a loop back option can be selected through bits SOLB or S1LB This option allows to simultaneously receive the data which are being transmitted by the ST10x166 To increase the range of programmable baud rates for the two serial interfaces a
117. the mode of operation of the A D Converter as illustrates in table 8 16 to bO ADCH ADC Analog Input Channel Se lection See table 8 17 sg SGS THOMSON 0 0 010 0 0 4 6 8 Peripherals Table 8 17 Analog Input Channel Selection Selected Channel s o o Lo ms Los e ne O s nees O s o o e eono mec O Los O Lo Lt 6 3 Bit ADST is used to start or stop the A D converter The busy flag ADBSY is a read onlyflag which in dicates whether a conversion is in progress or not Bit field ADM determines the mode of operation of the A D converter as illustrated in table 8 16 These modes will be discussed in detail in the fol lowing subsections Bit field ADCH in register ADCON specifies the analog input channel which is to be converted in the single channel conversion modes or the chan nel with which a conversion sequence of different channels will be started in the auto scan modes Table 8 17 shows the reference between the ADCH field and the selected input channels Pro gramming ADCH to one of the reserved combina tions will produce invalid results The A D Converter Result Register ADDAT shown in figure b
118. the opcode the PRTFLT flag in Underflow register STKUN the STKUF flag is set 118 o in the register and the Stack Underflow trap is IS entered Ine protected instructiansiude entered Again which IP value will be pushed onto D SWDT EINIT IDLE PWRDN SRST and the system stack depends on which operation SRVWDT The IP value pushed onto the system caused the increment of the SP When an implicit Stack for the protection fault trap is the address of increment of the SP is made through a Pop or Re the instruction that caused the trap turn instruction the IP value pushedis the address of thefollowingnstruction When the SP is incre Bv anAdd 7 3 2 6 ILLEGAL WORD OPERAND ACCESS TRAP represents the address of the instruction after the Whenevera word operandead or write access is instructiondllowinghe Add instruction See chap Made to an odd byte address the ILLOPA flag is ter 13 for more details on stack usage set and the Illegal Word Operand Access trap is entered The IP value pushed onto the system stack is the address of the instructiotlowinghe 7 3 2 4 UNDEFINED OPCODE TRAP one which caused the trap Whenever the opcode of an instruction currently decoded by the CPU is notthe opcode ofa valid in 7 2 7 struction in the ST10x166 s instruction set the UN ILLEGAL PEGESA TRAP DOPC flag is setin the TFR register and the CPU Whenever a branch
119. then Register banking provides the user with an eX the reg operand from the system stack and re tremely fast method of switching user context A turns to the calling program single machine cycle instruction saves the old bank andenters a new register bank Each register bank may assign up to 16 registers Each register 13 6 2 Cross Segment Subroutine Calls bank should be allocated during coding based Ncalls to subroutines in different segments require the needs of each task Once the internal memory e A 21 use of the CALLS call inter segment subroutine has been partitioned into a register bank space in instruction This both ie ternal stack space and a global internal memory area each bank pointer is then assigned Thus ee segment pointer and IP on the system upon entry to a new task theppropriatebank pointer is used as the operand of the SCXT switch Upon return from the subroutine RETS return context instruction Upon exitfrom a task a simplefrom inter segment subroutine instruction must be POP instruction to the context pointer CP re Used to restore both the CSP and IP This ensures stores the previous task s register bank that the nextinstruction after the CALLS instruction is fetched from the correct segment It is possible to use CALLS within the same segment but two 13 6 PROCEDURE CALL ENTRY AND EXIT words of the stack are still used to store both the IP and CSP 13 6 3 SGS THOMS
120. through a direct connec tion Based on an external signal the contents of T5 can be captured into register CAPREL and T5 may optionally be cleared Both timer T6 and T5 can count up or down and the current timer value can be read or modified by the CPU in the non bit addressable SFRs T5 and T6 Each of the above features will be described in detail in the following subsections From a programmer s point of view the GPT2 block is represented by a set of SFRs as shown in figure below Those portions of port and direction registers which are not used for alternate functions by the GPT2 block are not shaded 8 2 2 1 GPT2 CORE TIMER T6 The operation of the core timer T6 is controlled by the bit addressable control register T6CON is shown below The core timer T6 can only run in timer mode It is started or stopped by software through bit T6R Timer T6 Run Bit If T6R 0 the timer stops Set ting T6R to 1 will startthe timer The count direc T6CON FF48h A4h GPT2 Core Timer T6 Control Register Reset Value 0000h 15 14 13 12001 10 9 8 men 7 6 5 4 3 2 1 0 mu m Tal b15 T6SR Timer Reload Mode Enable Bit The reload from register CAPREL is enabled if this bitis set at 1 b14 to 611 and b5 to b3 R Reserved b10 T6OTL Timer 6 Output Toggle Latch Toggles on each overflow underflow of T6 Can be set or reset by software b9 T6OE Timer 6 Alternate Output Functio
121. ttn e eee ptus 7 19 TRAP FUNCTIONS 3 dtt ete boten toco Heec e dit tege tns 7 21 Software Traps ore HOP epe there petet see eset 7 21 Hardware use ote n a Recte edet te 7 21 EXTERNAL NMI TRAP eec ee ee eee do tec decedit 7 22 STAGKOVEREEOW TRAP 7 22 STACK UNDERFLOW TRAP te ice 7 23 tet io 7 23 PROIECTION EAUET TRAP 7 23 ILLEGAL WORD OPERAND ACCESS eene eere eene 7 23 ILLEGAL INSTRUCTION ACCESS TRAP 2 2 7 23 ILLEGAL EXTERNAL BUS ACCESS 2 2 9 7 23 8 PERIPHERALS 8 1 8 1 1 8 1 1 1 8 1 1 2 8 1 1 3 8 1 1 4 8 1 1 5 CAPTURE COMPARE CAPCOM UNIT _ 8 2 Timers TO and TT ntt tdi Sed ee ee chase e e e e e E RE Ee 8 5 TIMER MODEL NE ui c Pe tutu AME RD RE EE 8 5 COUNTER 8 6 RUNE DUET 8 7 TIMER went EEEE E EEEE EEEE EEE EE 8 7 tem M cu ee eH 8 8 S6 amp S THOMSO YZ M 8 1 2 8 1 2 1 8 1 2 2 8 1 2 3 8 2 8 2 1 8 2 1 1 8 2 1 2 8 2 2 8 2 2 1 8 2 2 2 8 2 2 3 8 3 8 3 1 8 3 1 1 8 3 1 2 8 3 1 3 8 3 1 4 8 3 2 8 4
122. word data transfer is selected for a specific mented to zero after the PEC data transfer butthe PEC channel i e bit BWT 0 the respective Interrupt Request flag of the source which gener Sourceand Destination Pointers must both contain ated the request remains set This will cause an Valid word address which points to an even byte other request from the associated source boundary Otherwise the Illegal Word Access trap will be invoked when this channel is used see sec If the COUNT value equals 0 at the time the re tion 7 3 2 6 quest is generated no PEC data transfer will be performed Instead a CPU interrupt request is I the following a Source Pointer will be referred to generated onthe same priority level 15 or 14 85 SRCPx and a Destination Pointer will be re the originaPEC request The CPU branchestothe ferred to as DSTPx where x indicates the number interrupt service routine of the source that gener 01 ea oe Sr ih ated the request This interrupt service routine can through 7 Figure 7 4 shows the mapping of the be used to reprogram the associated PEC service PEC Source and Destination Pointers into the in channel ternal RAM Note This feature can be used to specifically gen Note thatfor all PEC data transfers the data page erate CPU interrupt requests on the 2 highest pri Pointers DPPO through are NOT used ority levels level 15 or 14 For any source request 9d dresses contained
123. 000h to FFFFh when counting down the value stored in register CAPREL is loaded into timer T6 This will not set the interrupt request flag CRIR associated with the CAPREL register How ever interrupt request flag T6IR will be set indicat ing the overflow underflow of T6 Figure below shows a block diagram of the reload mode of reg ister CAPREL 8 2 2 3 3 CAPREL Register Interrupt Control Whenever a transition according to the selection in bit field Cl is detected at pin CAPIN P3 2 interrupt request flag CRIR in register CRIC is set This will cause aninterruptto the CAPREL register interrupt vector CRINT or will trigger a PEC service if the in terrupt enable bit CRIE in register CRIC is set The organization of register CRIC is described below Refer to chapter 7 for more details on interrupts 8 2 2 3 4 Usingthe Capture and Reload Mode Since the reload and the capture mode of register CAPREL can be configured individually by bits 55 and T6SR one can set both bits to use the two modes of register CAPREL simultaneously This feature can be used to build a digital PLL configura tion which generates an output frequency that is a multiple of the input frequency as described in the following Figure below shows a block diagram of this configuration The operation in this mode will be explained with an example Consider the case where one has to detect con secutive external events which may occur aperiodi cally but need
124. 02200 0000000 8 49 A D Converter Interupt 2 8 49 SERIAL CHANNELS ss beet Re dene rte te cede edite Ded ete e Det 8 49 Modes of 8 51 ASYNCHRONOUS 22222 12 002 22500 000000000000 eene 8 52 SYNCHRONOUS OPERATION 8 56 Bald Rates 2332030008 een hn 8 58 ASYNCHRONOUS MODE BAUD RATES 2 55 8 58 SYNCHRONOUS MODE BAUD RATES 2 2 8 59 Serial Channels Interrupt Control 222 8 60 WATCHDOG TIMER WDT 2 2 2 2299 8 61 9 EXTERNAL BUS INTERFACE 9 1 9 2 9 3 9 4 9 5 9 6 EXTERNAL BUS CONFIGURATION DURING sss 9 2 SINGLE CHIP MODE RE SR ER Pe 9 4 16 18 BIT ADDRESS 8 BIT DATA NON MULTIPLEXED BUS 9 4 16 18 BIT ADDRESS 8 BIT DATA MULTIPLEXED BUS 9 5 16 18 BIT ADDRESS 16 BIT DATA MULTIPLEXED BUS 9 6 16 18 BIT ADDRESS 16 BIT DATA NON MULTIPLEXED 9 8 Ey SGS THOMSON MICROELECTRGNICS 9 7
125. 0F166BQ1 to 70 C ST10F166BQ6 32MHz e to 4010896 PQFP100 ST10F166BQ7 to 1 EET ST10F166CQ1 0 to 10 166 6 24MHz 40 to 85 PQFP100 ST10F166CQ7 40 to 105 C vg SGS THOMsON 0 0 0 YF MICROELECTRONICS ST10F166 NOTES S amp S THOMSON y SGS THOMSON o MICROELECTRONICS ST10166 ST10R166 16 BIT MCU WITH A D CONVERTER High Performance 16 bit CPU with 4 Stage Pipeline 100ns Instruction Cycle Time at 20MHz CPU Clock 500ns Multiplication 16x16 bits 1us Division 32 16 bits Enhanced Boolean Bit Manipulation Facilities Register Based Design with Multiple Variable Register Banks Single Cycle Context Switching Support 256 Kbyte Linear Address Space for Code and Data 1Kbyte On Chip RAM 32 KBYTE ON CHIP ROM ST10166 ONLY 512 byte On Chip Special Function Register Area 8 Channel Interrupt Driven Single Cycle Data Transfer Facilities via Peripheral Event Control ler PEC 16 Priority Level Interrupt System 10 Channel 10 bit A D Converter with 9 75us Conversion Time 16 Channel Capture Compare Unit 2 Multi Functional General Purpose Timer Units 2 Serial Channels USARTs Programmable Watchdog Timer 76 General Purpose I O Lines Temperature Range 0 to 70 40 to 85 40 to 125 1 2 micron multifunctional CMOS technology 100 Pin Metric Plastic Quad Flat Pack PQFP Rectangular Package April 1992 PRELI
126. 13 ADDRSEL1 ADDRESS SELECT REGISTER 5 13 PSW Processor Status Word 5 14 ALU STATUS E MULIPY 3 ioco ote nea 5 14 CPU INTERRUPT STATUS IEN ILVL 220222500001 5 16 HOLD HLDA BREQ BUS ARBITRATION 2 2 2 2 2 2 22 010200000222 5 16 SGS THOMSO 772 5 3 5 5 3 6 5 3 7 5 3 8 5 3 8 1 5 3 8 2 5 3 9 5 3 10 5 3 11 5 3 12 5 3 13 5 3 14 5 3 15 5 3 16 GENERAL INDEX IP Instruction Pointer 32s Sos le Col ces teat 5 16 CSP Code Segment Pointer 222 2 5 5 17 DPPO DPP1 DPP2 DPP3 Data Page Pointers 5 18 GPrContext Pointer ei oe eq e Ere pep im eiecit eret ep em 5 20 IMPLICIT CP USE WITH SHORT 4 BIT GPR ADDRESSES 5 20 IMPLICIT CP USE WITH SHORT 8 BIT REGISTER ADDRESSES 5 20 SP StackPointer ooa ed e Messe 5 22 STKUN Stack Underflow Pointer i ener 5 24 STKOV Stack Overflow Pointer 2 2 2 1 5 24 MDH Multiply Divide Register High
127. 166 the external bus This time miptexingreduces As shown in the figure 9 4 Port 0 is used as the overall possiblsandwidthof the bus word wide output for both the address and data This external bus configuration mode can also be which are time mltiplexedon the word wideex selected if the wat organied external memory is ternal bus Therefore an external word wide ad implemented by two separate 8 bit wide memo dress latch is required The least significant ries These two memories can be accessed both address bit 0 is normally not significant when ac wordwise coupled together as onsord wide cessing wordbrganized memories An Address indivdualy as twoindependenbyte Latch Enable ALE signal is generated by the on memories chip External Bus Controller EBC to signify For the case where the two byte wide memories valid address beingvailableon Port 0 Aslong aS are to be accessed only wordwise the addressing memory segmentation is not disabled Port4 isad Scheme is the same as if only one 16 bit wide ditionallyised as an output for the two most signifi memory is used For the case where the two cant bits of the required 18 bit addresses Port 1 memories are also to be accessed as inde can be used for general purpose I O functions pendentlysuitable byte wide memories the Exter Compared with the other external bus configura hal Bus Controller EBC must benabledto use tion modes the 16 18 bit Address 16 bit
128. 1b not When the interrupt enable bit CCxIE is set a both a positive and a negative transition will set the PEC request or an interrupt request for vector request flag When the interrupt enable bit CRIE is CCxINT will be generated For further details on set interruptrequest for vector CRINT or a PEC the CAPCOM unit see section 8 1 request will be generated See section 8 2 2 for fur Pins T2IN P3 7 or T4IN P3 5 be used asexter ther details on the GPT2 block nal interruptnput pins wherthe associated auxil The non maskable interrupt input NMI provides iary timer T2 or T4 in block GPT1 is configured for another possibility to obtain CPU reaction on an capture mode This mode is selected by program external input signal THdMI is a dedicated in ming the mode control fields T2M or TAM in control put pin which causes a hardware trap when a registers T2CON T4CON to 101b The active negative transition is detected on this pin Nid edge of the external input signal is determined by trap function is discussed in defaikhe following bit fields 21 or T4l When these fields are pro section 20 24 SGS THOMSON MOF 7 Interrupt And Trap Functions ren Ne MONS is selected for servicing according to table 7 2 in The ST10x166 provides two different kinds of trap Section 7 1 ping mechanisms These are software traps and Whenever a trap occurs the PSW the IP and in hardware traps Trap functions offer th
129. 2 from op1 Operand op1 may specify ONLY GPR registers Once the subtraction has complet vb bperandop1 is decremented by one Using the set flags a branch instruction can then be usednjuection with this in struction to form common high leke iguageFOR loops of any range FLAGS E 2 V E Setifthe value of op2 representsthe lowest possible negative number Cleared oth erwise Used to signal the end of a table 2 Set if the result equals zero Cleared otherwise V Set if an arithmetic underflow occurred i e the result can not be represented in the specified data type Cleared otherwise C Setifa borrow is generated Cleared otherwise Setif the most significant bit of the result is set Cleared otherwise INSTRUCTION FORMAT BXO Taoxtivy Onepav o Byteo CMPD1 CMPD1 Rw data n 2 CMPD1 CMPD1 Rwn datas A6 Fn 4 CMPD1 CMPD1 2 4 57 S6S THOMSON SE MICROELECTRGNICS A Ivotpux tiov Let XMIIA2 XMIIA2 Ivteyep XouTape avd Aeypeuevt 2 XMIIA2 onl 2 OPERATION op1 lt 0 2 1 opt 2 DATATYPES WORD This instruction is used to enhance the performance and flexibility of loops The source op erand specified by op1 is compared to the source operand specified by op2 by performing a 2 s complement binary subtraction of op2 from op1 Operand op1 may specify ONLY GPR registers Once the subtraction has complet
130. 2bytes Short STKUN registers see section 5 3 CPU Special and8 bit addressing modes initaboration with Function Registers the CP register support word or byte GPR ac sg SGS THOMSON 10 3 Memory Organization Figure 3 4 Word and Byte GPR Organization cessesregardles of the current DPP register con switching and an automatic saving of the previous tents Additionallyeach bit in the currently active context Any number of variously sized register register bank can be accessdddividually banks only limited by thavailableinternal RAM The ST10x166 supports fast register bank 5126 can be implemented simatteously text switching Based on that multiple register For more details about GPR addressing via the CP banks can physically exist in the internal RAM at register see the chapter 5 Advanced program the same time However only the register bank se ming methods for an optimum utilization of the lected by the CP register is active and the remain GPRs features such as Context Switching Con ing register banks are inactive at that time text Packing GrerlappingRegister Banks Local Selecting a new active register bank is simply done GPRs on the system stack and so on are de by updating the CP register A particular Switch scribed in chapter 13 System Programming Context SCXT instruction performs register bank 809 n SGS THOMSON MICROELECTRONICS 3 Memory O
131. 3x 2TCL n3 gt tar 50 0 7 gt 15 2TCL 1 ALE Cycle Time t 150 50 6TCL n x 2TCL Note TCL 1 fosc 25ns at 40MHz ALE Cycle Time Memory Cycle Time 6TCL 150ns at 40MHz for 0 wait state operation An address float time of 5ns must be permissible 14 t17 t19 See Device Specification Section Table C 2 Multiplexed Memory Read with Read Write Delay Quick Table SGS THoMson 75 YF MICROELECTRGNICS C Application Examples Table C 3 Multiplexed Memory Write With Read Write Delay Write Pulse Low Time wW lt t2 n1x50 tw 2TCL 10 n1x 2TCL n12 50 0 8 n12 twr 10 2TCL 1 Data Valid toWR taw lt 2 2 50 lt 2TCL 15 2 2TCL n22 taw 50 0 7 n22 taw 15 2TCL 1 Data Hold afteWR tan lt tah lt 2TCL 15 tah lt 35 Address Setup lt t6 6 z2TCL 15 tas lt 25 t ALE Cycle Time Time t2150 50 t 6TCL nx2TCL t 6TCL nx2TCL nx 2TCL Note TCL 1 fosc 25ns at 40MHz ALE Cycle Time Memory Cycle Time 6TCL 150ns at 40MHz for 0 wait state operation An address float time of 5ns must be permissible t6 ts t12 t22 t23 See Device Specification Section Take care of n and ts These times cannobe prolonged byvait states Table C 4 Multiplexed Memory Write With Read Write Delay Quick Table 8 10 Gr SGS THOMSON C App
132. 5 3 Cache Jump Instruction 2 222 5 3 Particular Pipeline Effects 2222 00 5 4 INSTRUCTION STATE TIMES oer orte bebe etse ed bec tete desee boten 5 5 Time Unit Definitions c da e E ete de tete tela tede Bed chet foedus 5 5 Minimum State Times 5 5 Additional State Times 22 22 5 6 CPU SPECIAL FUNCTION REGISTERS 5 8 SYSCON System Configuration Register 5 9 INTERNAL ROM OR FLASH MEMORY EXTERNAL MEMORY ACCESS MODE SELECTION 5 9 EXTERNAL BUS TIMING CONTROL VIA MCTC MTTC RWDO 5 9 BYTE HIGH ENABLE PIN CONTROL VIABYTDIS RH 5 9 READY PIN CONTROL VIA RDYEN 22 2 2 2 0 0 0 02202222000202200 5 10 CLOCK OUTPUT PIN CONTROL 2 2 2 2 2 0001 22 101011 00000000 5 11 NON SEGMENTED MEMORY MODE SELECTION VIA SGTDIS 5 11 MAXIMUM SYSTEM STACK SIZE SELECTION VIASTKSZ 5 11 BUSCON 1 Bus Configuration Register 5
133. 5 V 1096 Vss 0 V for Ports 0 1 and 4 ALE RD WR CLKOUT 100pF ALE cycle time 4TCL 100ns at 20MHz CPU clock CPU Clock Variable Timing Symbol 20MHz 1 TCL 2 to 40MHz 15 ns ALE High Time TCL 10 2 Address Setupto ALE TCL 15 ALE Falling Edge to RD WR 10 RD WR Low Time 3TCL 10 RD to Valid Data In ALE Low to Valid Data In Address to Valid Data In Data Hold after RD Rising Edge Data Float after RD Data Valid to WR 2TCL 15 Data Hold after WR TCL 10 ALE rising edge after RD WR 10 Address Hold after RD WR 0 This time may be longer if no external bus conflict can occur For example this requirement is always metif only code but no data are accessed externally n SGS CTHIMSON MICROELECTRONICS ST10F166 Figure 19 External Memory Read Cycle A17 A16 15 VROF1617 Figure 20 External Memory Write Cycle ts tog A17 A16 Ls xO BHE t28 t22 t24 VROG1617 16 17 S amp S THOMSON ST10F166 PACKAGE MECHANICAL DATA m max min typ al Dose oss o 2295 2320 2245 osos oss foo zo os Ee pex ze oo e os oo EN fiol VROA1500 ORDERING INFORMATION ST10F166AQ1 0 to 70 C ST10F166AQ6 40MHz E 08 to 85 C PQFP100 ST10F166AQ7 40 to ERT ST1
134. 6 24 565 50 ME WicRORuseTRONICS 7 Interrupt And Trap Functions Figure 7 2 Examples Of Possible Configurations In The Interrupt Control Registers Type of Service COUNT PEC Transfer Counter field Of Selected PEC Channel If COUNT z 0 PEC Service Channel 7 If COUNT z 0 CPU Interrupt Priority Level 15 Group Priority 3 If COUNT 0 PEC Service Channel 6 If COUNT z 0 CPU Interrupt Priority Level 15 Group Priority 2 If COUNT z 0 PEC Service Channel 3 If COUNT 0 CPU Interrupt Priority Level 14 Group Priority 3 If COUNT z 0 PEC Service Channel 0 If COUNT 0 CPU Interrupt Priority Level 14 Group Priority 0 CPU Interrupt Priority Level 13 Group Priority 3 CPU Interrupt Priority Level 13 Group Priority 2 CPU Interrupt Priority Level 13 Group Priority 1 CPU Interrupt Priority Level 13 Group Priority 0 CPU Interrupt Priority Level 1 Group Priority 0 No Service No Service No Service No Service gt oll a o jo n SGS CTHOMSON _ _ 7 24 o MICROELECTRGNICS 7 Interrupt And Trap Functions The Processor Status Word PSW is furiohally Because a PEC data transfer takes only one in divided into 2 parts the lower byte of the PSW ba struction cycle and is never interrupted the CPU sically represents the arithmetic status of the CPU priority field remains unaffected by a PEC service the upper byte of the PSW controls the interrupt For ha
135. 6 provides a vectored interrupt SyS The followingtable contains all sources that are tem In this system certain vector locations in the capable of requesting interrupt or PEC service in memory space reserved for the reset trap and the ST10x166 includingthe associated interrupt interrupt service functions Whenever a request vectors and trap numbers Also listed are the mne occurs the CPU branches to one of these locations monics of the affected Interrupt Request flags and which is predetermined by hardware This allows their corespondinglnterrupt Enable flags The request The only exceptions are the class B hard the respective source followed by a part that ware traps which all share the same vector ad specifies their function IR Interrupt Request fl dress The status flags in the Trap Flag Register iecintartlipt Enable cud e 2 24 S amp S THOMSON 7 Interrupt And Trap Functions Table 7 1 Interrupt Sources And Associated Interrupt Vectors PEC Service Request Flag Flag Vector Location Number ccm cca ww capcom Regist cone cow an cca come am vn capcom Registers come cn cum com m coan cose sm s cum cou cconr
136. 66 Registers Port 0 PotORegister ooon m erem we ep rre om Famosas _ omm s om ion oon recon PEC channsioconrolRegiter ooon recor rim om PEC Chamelt convolRegiser recon om ecco recon som PECChannela ConrotRogiter ooon recan en Pec crameta conti recs en PEC Cranners Conor Register econ oen PEC Channel oContalRegitr ooon _ rus com cpu programsiatus ors ooon _ Serial Channel 0 Baud Rate Generator 0000h Reload cael SOCON bi Serial Channel 0 Control Serial Channel 0 Control Register SOEIC FF70h PONI Serial Channel 0 Error Interrupt Control 0000h Register SORBUF Serial Channel 0 Receive Buffer Register XXXXh read only Serial Channel 0 Receive Interrupt Control 0000h SOTBUF Serial Channel 0 Transmit Buffer Register 0000h write only SOTIC b FF6Ch Serial Channel 0 Transmit Interrupt Control 0000h Register 14 16 Gr SGS THOMSON B ST10x166 Registers Name Physical 8 Bit Description Heset Address Address Value FEBCh Serial Channel 1 Baud Rate Generator 0000h Reload Ru SICON bi CON FFBsh Serial Channel 1 Control Serial Channel 1 Control Register Serial Channel
137. 7 In the following the branch target addressing modes are described in more detail 0 FFFEh 00h 7Fh 80h FFh 0 15 0 3 0 7Fh Specifies absolute 16 bit code ad Rw In this case the 16 bit branch target in dress within the current segment struction address is determined indi Branches MAY NOT be taken to odd rectly by the contents of a word GPR code addresses Therefore the least In contrast to indirect data addresses significant bit of caddr must always indirectly specified code addresses are contain a 0 otherwise a hardware trap NOT calculated via additional pointer will occur registers e g DPP registers Note that branches MAY NOT be taken to rel This mnemonic represents an 8 bit odd code addresses Therefore the signed word offset address relative to least significant bit of the address the current Instruction Pointer contents pointer GPR must always contain a 0 which represent the address of the in otherwise a hardware trap would occur struction after the branch instruction Depending on the offset address trap7 Specifies a particular interrupt or trap range either forward rel 00h to 7F number for branching to the corre or backward rel 80h to FFh sponding interrupt or trap service rou branches are possible According to an tine via a jump vector table According either word or doubleword sized to the maximum number of interrupt branc
138. 7 Table 9 2 Action Function Selected At BUSACT BTYP Reset Init After Init ROM enable ROM enable Segment 0 Segment 0 No ext Bus reserved ROM enable Segment 1 8 Bit Non Mux 8 Bit Non Mux 8 But Non Mux No ROM 8 Bit Mux 8 Bit Mux 8 Bit Mux No ROM 16 Bit Mux No ROM 16 Bit Non Mux 16 Bit Non Mux 16 Bit Non Mux No ROM sg SGS THOMSON 5 9 External Bus Interface 9 2 SINGLE CHIP MODE BUSACT bit in the SYSCON register see sec tion 5 3 1 1 In this case an external memory can The single chip mode must be selected whenever be accessed and the entire on chip memory re program execution shall start from the on chip pro mains accessible gram memory If this mode has been selected once during reset internal accesses s bally enabled Daring reset the Instruction laie IP 9 3 16 18 BIT ADDRESS 8 BIT DATA and the Code Segment Pointer CSP registersare NON MULTIPLEXED BUS both cleared and thus program execution begins i at the internal ROM o a This external bus mode must be selected if a byte external memory shall be connected to the As shown in figure 9 1 Port 0 Port 1 and Port 4 ST10x166 As shown in figure 9 2 Port 1 is used A17 and A16 can be usedas general purpose O as word address output while the lower half of registers Port0 is used as separated byte data output Since Note that any intended access to a location within two independent buses are used no time multi
139. 8 or 16 bits Thus short con The BSO Tasking software instruction set recog stants are always zero extended while long con nises all instructions of the hardware instruction Se amp tants are truncated if necessary to match the data mnemonics are added to allow easy and comfort able programming The assembler will determine by means of the combination of operands which opcode is entered in the instruction format This means that based on the combination of operands the appropriat hardware mnemonic is chosen Please refer to the BSO Tasking Documentation for further information Immediate constants are always signified by a leadingnumber sign Table 6 1 Data Type Adaptation of Immediate Constants data3 0000h data3 00h data3 date4 0000h data4 00h data4 data16 data16 data 16 OFFh data8 0000h data8 data8 mask 0000h mask mask sg SGS THOMSON 2565 6 Instruction Set Overview 6 2 2 Short Addressing Modes All of these addressing modes use an implicit basereg offset address to specify a physical 18 bit address cont d By these addressing modes data can be specified within the GPR SFR or bit addressable memory space Physical Add Base Add Ax Short Add In the bllowingthe shortaddressing modes which are shown in table 6 2 are described in more detail Rw Rb reg Specifies direct access to any GPR the currently active context register bank Bo
140. 9 7 1 9 7 1 1 9 7 1 2 9 7 2 9 7 2 1 9 7 2 2 9 8 9 8 1 9 8 2 9 8 3 9 8 4 9 8 5 9 9 GENERAL INDEX EXTERNAL BUS TRANSFER 9 9 Multiplexed Bus Transfer Characteristics 9 9 MULTIPLEXED BUS MEMORY 5 22 22 9 9 10 MULTIPLEXED BUS MEMORY WRITES 9 10 Non Multiplexed Bus Transfer Characteristics 9 10 NON MULTIPLEXED BUS MEMORY READS 2 0 720 22900 9 11 NON MULTIPLEXED BUS MEMORY WRITES eene eene 9 11 USER SELECTABLE BUS CHARACTERISTICS 9 12 Programmable Memory Cycle Time 2 222 2 9 12 Programmable Memory Tri State 9 14 Read Write Signal Delay eene 9 16 ALE signal delay sett eae tesi e twee e etus 9 17 Switching between the Bus Modes 9 18 EXTERNAL MEMORY ACCESS VIA THE DATA READY 9 19 10 PARALLEL PORT 10 1 10 1 1 10 1 2 10 1 3 10 1 3 1 10 1 3 2 10 1 3 3 10 1 3 4 10 1 4 10 2 PORTS
141. AND Rn 0h Clear Register CPLB Bit BMOVN Bit Bit Complement Bit DEC Rn SUB Rn 1h Decrement Register INC Rn ADD Rn 1h Increment Register SWAPB Rn ROR Rn 8h Swap Bytes in Word 1 8 13 System Programming 13 2 MULTIPLICATION AND DIVISION Note The above save sequence and the restore sequence after COPYL are only required if the cur Multiplicationand division of words andouble rent routine could have interrupted a previous rou words is provided through multiple cycle instructine which contained a MUL or DIV instruction The tions implementing a Booth algorithm Each in MDC register is also saved because it is possible struction implicitly uses the 32 bit MD registerthat a previous routine s Multiply or Divide instruc MDL low 16 bits MDH high 16 bits Whenever tion was interrupted while in progress In this case either half of this register is written into the MDRIU the information about how to restart the instruction flag Multiply or Divide Register In Use in the MDC is contained in this register The MDC register register is set It is cleared whenever the MDL reg must be cleared to be correciiyitialiad fora sub ister is read Because an interrupt can be acknow sequent multiplication or division ledged before the MD register contents are saved START MULU R1 R2 this flag is required to alert interrupt routines whichMuttiply 16x 16 unsigned Sets require the use of the multip ivide hardware of MDRIV state pr
142. ARBITRATION logical XORing of the two specified bits The HLDEN bit allows to enable the alternate func MULIP Flag The MULIP flag will be set to 1 tions at pins P2 15HMOLD P2 14 ALDA and by hardware upon the entrance into inter P2 13 BREQ If HLDEN bit is cleared after once rupt service routine when a multiply or divide being set this will disable the bus arbitration func ALU operation was interrupted before comple tion of this pins but WILL NOT turn them back to tion Depending on the state of the MULIP bit O or CAPCOM mode This feature is interesting the hardware decides whether a mipllication case of execution of critical real time routines or division must be continued or not at the end which must be interrupted or delayed by exter of an interrupt service The MULIP bit is over written with the contents of the stacked MULIP flag when the return from interrupt instruction RETI is executed This normally means that the MULIP flag is teared againafter that After reset all of the ALU status bits are cleared 5 3 4 2 CPU INTERRUPT STATUS IEN ILVL The Interrupt Hable bit allows togloballyenable IEN 1 or disable IEN 0 interrupts The four bit Interrupt Level field ILVL specifies the priority of the current CPU activity The interrupt level is 16 26 nal HOLD requests 5 3 5 IP Instruction Pointer This register determines the 16 bit intra segment address of the inst
143. Access Trap request flag Set when a word operand read or write access is made to an odd byte address Must be reset by software b1 Illegal Instruction Access Trap re quest flag Set when a branch is made to an odd byte ad dress Must be reset by software b0 ILLBUS Illegal External Bus Access Trap re quest flag Set when an external access is requested and no external bus is configured Must be reset by soft ware 22 24 tem stack depends on which operation caused the decrement of the SP When an implicit decrement of the SP is made through a Push or Call instruc tion or upon interrupt or trap entry the IP value pushed is the address of tHfellowingnstruction When the SP is decremented by a Subtract in struction the IP value pushed represents the ad dress of the instruction after the instruction followinghe Subtract instruction For recovery from stack overflow it must be en sured that there is enough excess space on the stack for twice saving the current system state PSW IP in segmented mode also CSP Other wise a system reset should be generated See chapter 13 for more details on stack usage SGS THOMSON MICROELECTRONICS 7 Interrupt And Trap Functions 7 3 2 3 STACK UNDERFLOW TRAP not repeated twice in the second word of the in Whenever the Stack Pointer is incremented to Struction and the bytefiowingthe opcode is not value which is greater than the value in the Stack the complement of
144. And an Auxiliary Timer Core Timer T3 Interrupt Request T3R Auxiliary Timer Tx TxUD x 2 4 Note Line only affected by over underflows of 3 but NOT by software modifications of T3OTL VROF1641 8 1 chap 1 8 2 1 chap 2 1 8 2 chap2 8 2 1 1 chap 2 1 1 Table 8 11 GPT1 Auxiliary Timers Reload Trigger Selection x 2 or 4 21 4 Reload on e oos C oe 9 21 17 eS os sg SGS THOMSON 2505 8 Peripherals 8 2 1 2 chap 2 1 2 8 2 1 2 1 chap 2 1 2 1 8 2 1 2 2 chap 2 1 2 2 8 2 1 2 3 Reload Mode Reload mode is selected by programming the mode control fields T2M or T4M to 100b In reload mode the core timer T3 is reloaded with the con tents of an auxiliary timer register Two different sources can be selected to cause a reload of the core timer The options are programmed by the in put selection bits of bit fields T2l and T4l in regis ters T2CON or T4CON as shown in table 8 11 When programmed for reload mode the respec tive auxiliary timer T2 or T4 stops independent of its run flag T2R or T4R When bit 21 2 0 or bit 41 2 0 the source which can cause a reload is the external input pin T2IN for timer register T2 or pin TAIN for timer reg ister
145. Asynchronous READY input will first insert the selected number of wait states SYSCON 3 0 Synchronous READY input 10 26 SGS THOMSON MICROELECTRONICS 5 Central Processing Unit In the asynchronous mode of operation the physical address generation This means also that READY input signal is internally synchronized tothe pins of Port 4 can be used as standard I O pins the microcontroller s operation In this case an ad in the case of the segmented memory mode ditional delay of up to two state times may be re SGTDIS 0 the CSP DPP registers are used quired in order t amp nternallysynchronizethe signal for the generation of physical 18 bit addresses as In the synchronous mode of operation it is the described in sections 5 3 6 and 5 3 7 The pins of user s regonsibilityo ensure that th READY in Port 4 are used as address pins A17 and A16 pro put signal meets the specified setup and hold vided that an external bus has been configured times In order to obtain the necessary timing infor Whenever the segmented memory mode is se mation and to perform external synchronization lected the CSP register is pushed onto the system the Clock Output function can be used stack in addition to the IP register before an interrupt After reset the Data Ready functiondssabled service routine is entered and it is repopped when the interrupt service routine is left again 5 3 1 5 CLOCK OUTPUT PIN CONTROL VIA CLKEN uod
146. Bus External RAM ROM Byte Organized Memories This configuration is shown in figure C 1 An external memory is implemented by a 32Kx8 EPROM and an 8Kx8 RAM The connected external bus is used for both 16 bit addresses and 8 bit data Because of time multiplexing an external address latch is required for the lower byte of the address 2 16 bit Addresses 8 bit Data Non Multi plexed Buses Extemal RAM ROM Byte Organized Memories This configuration is shown in figure C 2 The external memory is implemented by a 32Kx8 EPROM and an 8Kx8 RAM Because two separate 8 bit Data and 16 bit Address buses are used no external address latch is required APPENDIX C APPLICATION EXAMPLE 16 bit Addresses 16 bit Data Multiplexed Bus External RAM ROM Both Word and Byte Organized Memories This configuration is shown in figure C 3 The external memory is implemented by one 32Kx16 EPROM and by two 8Kx8 RAMs The connected external bus is used for both 16 bit addresses and 16 bit data Because of time multiplexing two external address latches are required The EPROM can only be accessed wordwise while the RAMs can also be ac cessed bytewise provided that the function of theBHE output pin is not disabled In this case the address signal 0 selects the lower byte memory and the active loBHE signal selects the upper byte memory 16 bit Addresses 16 bit Data Non Multi plexed Buses External RAM ROM Both Word and Byte
147. CAPREL and in terrupt request flag CRIR is set With the same de tected transition at CAPIN timer T5 can be cleared to 0000h This option is controlled by bit T5CLR in register 5 The timer T5 clear function can be selected regardless of the capture function To ensure that a transition of the clear trigger signal is correctly recognized its level should be held for at least 4state times Once timer T5 is cleared the in terrupt request flag CRIR in register CRIC is set Figure below shows a block diagram of register CAPREL in capture mode Figure 8 34 Register CAPREL In Reload Mode CAPREL Register Core Timer T6 157 SGS THOMSON Note that bit 55 only controls whether a capture is performed or not If 55 0 the input pin CAPIN can still be used as an external interrupt in put see also section 7 2 7 This interrupt is con trolled by the CAPREL interrupt control register CR IC described in section 8 2 2 3 3 8 2 2 3 2 Reload Mode CRIC FF6Ah B5h CAPREL Register Interrupt Control Register Reset Value 0000h 7 6 5 4 3 2 1 0 Interrupt Request To CAPCOM Timers TO 1 VROO1641 43 64 MIGRCELECTREMICS 8 Peripherals This mode is selected by setting bit T6SR 1 in register TECON The event causing a reload in this mode is an overflow or underflow of the core timer T6 If T6SR 1 when timer T6 overflows from FFFFh to 0000h when counting up or when itunderflows from 0
148. CTRGNICS A Ivotpux tiov Let Qop avd LoBpovtive ABooXvte 2 OPERATION DATA TYPES tmp 1 SP SP 2 5 tmp SP SP 2 SP IP IP op2 WORD Pushes the word specified by operand op1 and the value of the instruction pointer IP onto the system stack and branches to the absolute memory location specified by the second operand op2 Because the P always points to the instruc amp linWinghe branch instruc tion the value stored on the system stack represents the return address of the calling rou tine FLAGS E 2 V E Setif the value of the puted operandop1 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table 2 Set if the value of the pushed operand 1 equals zero Cleared otherwise V Not affected C Notaffected N Setif the most significant bit of the pushed operand op1 is set Cleared otherwise INSTRUCTION FORMAT BXO Taoxivy Mvenovux Onepav o Byteo PCALL PCALL reg caddr E2 RR MM MM 4 62 84 S amp S THOMSON A Ivotpuxuov orl OPERATION DATA TYPES FLAGS tmp SP SP SP 2 op1 tmp WORD Pops one word from the system stack specified by the Stack Pointer specified by op1 The Stack Pointer
149. CTRONICS A Ivotpux tiov Let XIIAB XIIAB Ivteyep Oveo Xoun euevt XIIAB oxi OPERATION 0 1 lt op1 DATATYPES BYTE Performs a 1 s complement of the source operand specified by op1 The result is stored back into op1 FLAGS E 2 V E Setifthe value of the source operand op1 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table 2 Setif result equals zero Cleared otherwise V Alwayscleared C Always cleared N Setif the most significant bit of the result is set Cleared otherwise INSTRUCTION FORMAT BXO Taokwy Mvepnovux Mveuovi Onepav o Byteo CPLB CPL Rh B1 2 34 84 SGS THOMSO 772 A Ivotpuxuov Let AIXQAT AIXQAT Avoa Ae Qatyndoy OPERATION Disable Watchdog Timer This instruction disables the Watchdog Timer The Watchdog Tineerabledby a reset DISWDT instruction allows the Watchdog Timer tadbgabledfor applications which do not require a watchdog functidtollowing reset this instruction can be executed at any time until either a Service Watchdog Timer instruction GRVWDT or an End of Initiali zation instruction EINIT are executed Once one of these instructions has been exe cuted the DISWDT instruction will have no effect To insure that this instruction is not accidentally executed it is implemented as a protected instruction FLAGS E Z V C N E Not affected Z Not affected V Not affected
150. Channel 1 Receive Interrupt Control 0000h Register Coone rem eon capcom Register connor neasi Cocas eren seh registers erup convoi noas reren omm CAPCOM Registra Cocas Freon em reir sitrupt convar Reise Fromm em Reiter sirupt contol mron cm carom reir sitrupt contol neit Freon om cacon Reiter itp onto Regis Cocas rr cm Registers imerupt ovr Rese uon Coone rmm em caconregsrimierupiconrimegsbr Tom Cosme Freon om caconregsursiwieriniConrsRegsr mron cm carom onl Rei Coro rrom can CAPCOM Register oon con capcom Register 15 interupt conta Reiser 8 16 Gr SGS THOMSON B ST10x166 Registers Name Physical 8 Bit Description Reset Address Address Value ADCIC CCh A D Converter End of Conversion Interrupt 0000h Control Register ADEIC CDh A D Converter Overrun Error Interrupt Contro 0000h Register TOIC FF9Ch CAPCOM Timer 0 Interrupt Control Register 0000h rh cr CAPCOM Timer 1 Interrupt Control Register 0000h ADCON FA Dh A D Converter Control Register 0000h em em es Faon oen Trap Flag Regie
151. Control ree oe qme 1 CC2IC FF7Ch Ea CAPCOM Register 2 Interrupt Control 0000h Register EMI PEEL D CAPCOM Register CC3IC FF7Eh Register 3 Interrupt Control 0000h Register FE88h ee Register 4 ooooh CAPCOM Register 4 Interrupt Control wg SGS THOMsON 1 5 YF MICROELECTRGNICS B ST10x166 Registers Name Physical 8 Bit Description Heset E E am rt CAPCOM CAPCOMRegisterS 000 5 oon CC5IC le CAPCOM Register 5 Interrupt Control 0000h Register FEBCh CAPCOM CAPCOM Register6 6 Register 6 Interrupt Control eo te ME CAPCOM Register CC7IC b rmm CAPCOM Register 7 Interrupt Control 0000h Register WEEK CAPCOM Register ccsic FF88h e e mM CAPCOM Register 8 Interrupt Control 0000h Register CAPCOM CAPCOM Register9 9 000h CC9IC Rr CAPCOM Register 9 Interrupt Control 0000h Register CC10IC b FF8Ch Register 10 Interrupt Control 0000h egister CC11IC nsn CAPCOM Register 11 Interrupt Control 0000h Register cca 2 CAPCOM CAPCOMRegisteriD O 12 CC12lC Register 12 Interrupt Control 0000h Register cci 3 CAPCOM CAPCOMRegister13 00 13 Register 13 Interrupt Control 12 16 Gr SGS THOMSON B ST10x166 Registers Name Physical 8 Bit Descrip
152. Control External To CAPCOM Capture Timers TO T1 Input Core Timer T6 VR0A1624 SGS THOMSON 2e YF MICROELECTRONICS 8 Peripherals 8 2 1 GPT1 Block The current contents of each timer can be read or All threetimers T2 3 T4 of block GPT1 can run Modified by the CPU by accessing the aespond 3 basic modes which are timer gated timer and ing timer registers T2 T3 or T4 which are located counter mode and all timers can either count up the non bit addressable SFR space When any down Each timer has an alternate input function 9f the timer registers is written by the CPU in the pin on port 3 associated with it which serves as the State immediately before atimer increment reload gate control in gated timer mode or as the count 9 Capture is to be performed the CPU write opera input in counter mode As a specific feature of the tion has priority in order to guarantee correct re core timer its count direction may be dynami SUlts cally altered by a signal at an external input pin From a programmer s point of view the GPT1 and each overflow underflow may be indicated on block is composed ofa set of SFRs as shownin fig an alternate output function pin Thaxiliay tim 8 16 Those portions of port and direction reg ers T2 and T4 may additionally be concatenated isters which are not used for alternate functions by with the core timer or used as capture or reload the GPT1 blockare not shaded r
153. D Rwa Rw 08 n 10ii 2 ADD ADD Rw Rw 08 n 11ii 2 ADD ADD Rwh data 08 0 2 ADD ADD reg dat s 06 RR 4 ADD ADD reg mem 02 RR MM MM 4 ADD ADD mem reg 04 RR MM MM 4 A Ivotpux tiov Let AAAB AAAB Ivteyep ASOLTLOV orl 2 OPERATION 1 1 2 DATATYPES BYTE Performs a 2 s complement binary addition of the source operand specified by op2 and the destination operand specified by op1 The sum is then stored in op1 FLAGS E 2 V EE E Setifthe value of op2 representsthe lowest possible negative number Cleared oth erwise Used to signal the end of a table 2 Set if result equals zero Cleared otherwise V Set if an arithmetic overflow occurred i e the result can not be represented in the specified data type Cleared otherwise C Setifa carry is generated from the most significant bit of the specified data type Cleared otherwise Setif the most significant bit of the result is set Cleared otherwise INSTRUCTION FORMAT BXO Taoxtivy Mvenoviy Mvenuovy Onepav o Byteo ADDB ADD Rw Rwm 01 nm 2 ADDB ADD Rw Rw 09 n 10ii 2 ADDB ADD Rw Rw 09 n 11ii 2 ADDB ADD Rw datas 09 n 0 2 ADDB ADD reg datac 07 RR 4 ADDB ADD reg mem 03 RR MM MM 4 ADDB ADD mem reg 05 RRMM MM 4 A Ivotpuxuov Let AAAX Ivteyep Xappw 2 OPERATION 1 1 0 2 TYPES WORD
154. DPP3 points to data page 3 EINIT Instruction Executed SGS THOMSON MICROELECTRONICS 11 System Reset 11 3 WATCHDOG TIMER OPERATION AFTER ter is initialized to the bus configuration that is de RESET termined by the state of pirBUSACT EBCO and EBC1 External Bus Configuration at the end of The Watchdog Timer starts running after the inter the internal system reset The Bus Active bit nal reset has completed Its default clock fre BUSACT will be cleared to 0 if single chip mode quency will be the internal system clock 2 10MHz has been selectedBUSACT 1 EBC1 0 00b at fosc 40MHz and its defaulteload value is otherwise it is set to 1 The other bits of the SY 00h such that a watchdog timer overflow will occurSCON register are forced to zero This default in 131072 states 6 55ms at dsc 40MHz after itialization of the SYSCON register has been completion of the internal reset When the system selected such that external memories are ac reset was caused by a Watchdog Timer overflow cessed with the slowest peible configuation for the WDTR Watchdog Timer Reset Indication flag the respective bus type The Ready function is dis in register WDTCON will be set to 1 This indi abled cates the cause ofthe internal reset to the software initialiation routine WDTR is resetto 0 by an ex ternal hardware reset or by servicing the watchdog High Byte Enable alternate function of P3 12 de timer pend
155. DTIN 1 145 44 13 12 11 10 9 8 b15 to b8 WDTREL Reload Value for the high byte of the Watchog Timer b7 tob2 Reserved b1 WDTR Watchdog Timer Reset Indication flag Read only bit this bit is set by watchdog overflow It is cleared by hardware reset or by the SRVWDT instruction 50 WDTIN Watchdog Timer Input Frequency Selection WDTIN 0 fosc 4 WDTIN 1 fosc 256 sg SGS THOMSON IGA 8 Peripherals NOTES 646A LL x 5S THOMSON e MIGROELECTRONICS SGS THOMSON JJ NicROELECTROMICS CHAPTER 9 EXTERNAL BUS INTERFACE 9 EXTERNAL BUS INTERFACE The ST10x166 has been architected tbe placed For this mode Port 0 is used as interface to the a number of different applications and systemmuliplexed exernal address data bus As long as designs In order to meet the needs of designs memory segmentation is not disabled Port 4 is ad where more memory is required than psovided ditionallyused as an output for the two most signifi on the chip a number of external bus configurationcant bits of the required 18 bit addresses modes are supported These are listed below 16 18 Bit Address 16 Bit Data Non Multi Single Chip Mode plexed Bus No external bus is configured in this mode Select This mode is also provided for accesses to a word ing this mode during reset implies that programorganizedexternal memory However two sepa execution starts from the internal program mem rat
156. ECTRONICS 5 Central Processing Unit Physical Stack Address SP FE 12h 09h FBFEh SP 1FEh Stack Pointer Register for 256 words stack size Reset Value FBFEh SP Heb for 128 words stack size 15 14 13 12 10 9 8 FBFEh SP 7Eh pepe for 64 words stack size 2 3 F 2 i FBFEh SP 3Eh for 32 words stack size The followingexample demonstrates the circular b15 to b11 1 tual stack napping First register R1 ipushed contents from F800h through FFFEh Note how onto the lowest physical stack location accordingeyer that the physical system stack is forced to in lowing instrction registr R2 will be pushed onto table 5 7 the highestphysical stack location although the SP is decremented by 2 as for the previous push op P10 to b1 sp Stack Pointer Register Modifiable portion of the SP register eration Assumed stack size is 64 b0 0 d SP content i Bit tied to 0 by hardware because only even SP ica contents areallowed 262286658 Physical stack address FB82h PUSH R1 SP ZFC80h Physical stack address FB80h PUSH R2 SP ZFC7Eh Physical stack address FBFEh Upon each stack access the SP register is com pared against two stack boundary registers This may cause a stack overflow or stack underflow hardware trap to occur For more details about the use of this feature see the description of the STKOV and STKUN staclbo
157. Eh Note however that it is the user s rgxonsibilityhat the physical GELUSEWIHTSHORTS BITGER GPR address specified via the CP register in addi tion withthe short GPR address mustalways be an When a short 4 bit GPR address mnemonic Rw internal RAM location If this condition is not 0 Rb is used the four bits specify an address unexpected results may occur relative to the memory location specified by the After reset the CP register isitializedo FCOOh contente or The CPragister Figure 5 10 shows how the CP register is used to select a register bank The CP register can be up dated via any instruction which is capable of modi fying SFR Due to the internal instruction pipelinea new CP value is not yet usable for GPR address calculations of the instruction immediately Depending on whether a relative word Rw or byte Rb GPR address is specified the short 4 bit GPR address is mltipliecbither by two by one before it is added to the contents of the CP register as shown in figure 5 8 Thus both byte and word GPR accesses are possible in this way followinghe instruction updating the CP register GPRs used as indirect address pointers are al ways accessed wordwise For some instructions only the first four GPRs can be used as indirect ad dress pointers These GPRs are specified via short 2 bit GPR addresses The respective physical ad dress calculation is identical to that for the short 4 bit
158. Exposure to absolute maximum rating conditions for extended periods may affect device reliability Note The ST10166 ST10R166 is also offered in the temperature range 40 to 125 C and 40 to 85 C All the following time specifications refer to a CPU clock of 20MHz which is identical to an oscillator frequency fosc of 40MHZ Test Condition Vout Output Low Voltage lott 1 6mA all other outputs Output High Voltage _ Ports 0 1 4 ALE RD WR BHE CLKOUT RSTOUT Vra lou 100A 2 4mA SOWA Output High Voltage 0 9 Vcc all other outputs 2 4 1 6 Input Leakage Current Ports 0 1 2 3 4 NMI EBCO EBC1 BUSACT 0217170 ind wr SGsTHomsen 5 YF MICROELECTRONICS ST10166 ST10R166 DC Characteristics Continued Limit Values C Pin Capacitance 10 pF 1MHz m digital inputs outputs 25 C Power Down Mode Supply 100 2 5 V Current A D CONVERTER CHARACTERISTICS TA 20 to 70 C Vcc 25V 10 Vss 0 V Varer Vcc 0 2 V Vss 0 2 V Limit Values Test Condition Test Condition Analog Input Voltage Analog Input Capacitance Sample Converstion Time Total Unadjusted Error Varer Supply Current Analog Input Current Notes 1 This parameter is tested including leakage currents Allinputs in cluding pins configured as inputs 10 V to 0 1 V or at VCC 0 1 Vto VCC VREF 0 V a
159. G or S1BG i e the timer registers always returns zero in bits 13 through 15 An auto reload of the timer with the contents of the reload register is performed each time SOBG or S1BG is written to However if SOR 0 or S1R 0 atthe time the write operation to SOBG or S1BG is performed the timer will not be reloaded until the first instruction cycle after SOR 1 or S1R 1 8 4 2 1 ASYNCHRONOUS MODE BAUD RATES In asynchronous operation the baud rate gener ators provide a clock with 16 times the rate of the established baud rate The reason for this is that on reception every bit frame is sampled 16 times Thus the baud rates and 1 for the serial channels ASCO and ASC1 in asynchronous operation are determined by the following formu las fosc 64 x SOBRL 1 1 fosc 64 x lt S1BRL 1 When SxBRS 1 these formulas are Basynco 2 _fosc 3 64x lt SOBRL gt 1 Basync1 2 fosc 3 64x lt S1BRD gt 1 lt SOBRL gt and lt S1BRL gt represent the contents of the reload registers taken as unsigned 13 bit inte gers Table 8 19 lists various commonly used baud rates together with the required reload value The maxi Table 8 19 Asynchronous Modes Baud Rates Baud Rate SxBRS 0 m SUS 157 SGS THOMSON 59 64 MIGRCELECTREMICS Peripherals Serial Channel Interrupt Control Registers
160. GPR addresses CP FE10h 08h Context Pointer Register Reset Value FCO0h 15 14 13 12 11 10 9 8 5 3 8 2 IMPLICIT CP USE WITH SHORT 8 BIT REGIS Pa fs Ps t ce TERADDRESSES 7 6 5 4 3 2 1 0 When a short 8 bit address mnemonic reg or bi c UI Mo toff is used and supposed that the respective value is within a range from FOh to FFh the four least significant bits are interpreted as short 4 bit GPR address while the four most significant bits are ignored As shownin figure 5 9 the respective physical GPR address alculationis identical to that for the short 4 bit GPR addresses For single bit accesses on a GPR the GPR s word address is calculated as just described but the position of the bit within the word is specified by a separate addi tional 4 bit value b15 to b11 z1 Bits tied to 1 by hardware This al lows possible contents from FAO0h to FDFEh Note however that valid GPR addresses must be situated within the internal RAM space b10 tob1 CP Context Pointer Register Modifiableportion of the CP register Note that bit 10 is always forced to the inverse state of bit 9 by hardware For software bit 10 can only be read but not directly be written 0 Bit tied to 0 by hardware since only even contents areallowed 20 26 n SGS THOMSON MICROELECTRONICS 5 Central Processing Unit Figure 5 8 Implicit CP Use by Short 4 Bit GPR addressing Modes Specified by R
161. Hardware Traps trap request flag by software causes the same af Hardware traps are used to identify faults or spe fects as if it had been set by hardware cific system states at runtime which cannot be After the reset functions which have hi it 2 4 ghest sys identified at assembly time Eight different hard tem priority trap priority Ill the traps of class A ware trap functions are supported by the Pete ST10x166 When a hardware ti condition has have the seend highes priority trap priority Il been detected the CPU branches to the trap vec o STR B trap but not an tor location for the respective trap condition De 05 DOCE the trap condition the instruction which tak Th NMI t has th ja hest caused the trap is either completed oancelled ihe the E at dress i e it has no effect on the system state before the a trap handlingroutine is entered The traps of class B all have the same trap priority trap priority 1 which is lower than the priority of class A traps Thus class B traps can never inter rupt class A traps byendingclass B traps will be executed after all class A traps are finished In the Pcase of simultaneously occurring class B traps the Hardware traps are non maskable and always have priority over every other CPU activity If sev eral hardware trap conditions are detected within the s
162. If the specified bit was clear the instruetitmwinghe JBC instruc tion is executed FLAGS E 2 V E Always cleared Z Contains the logical negation of the previous state of the specified bit V Always cleared C Always cleared Contains the previous state of the specified bit INSTRUCTION FORMAT BXO Taoxivy Mvenoviy Mvenuoviy Onepav o Byteo JBC JBC bitadd q rel AA QQ rr 10 4 vg SCS THOMSON 8B YF MICROELECTRGNICS A Ivotpux tiov Let ApooXvte SMITA 2 OPERATION IF 1 THEN IP op2 ELSE END IF If the condition specified by op1 is met a branch to the absolute address specified by op2 is taken If the condition is not met no action is taken and the instruction following the JMPA instruction is executed normally CONDITION CODES See Table A 2 next instruction FLAGS E 2 V Not affected 2 Not affected V Not affected C Notaffected N Not affected INSTRUCTION FORMAT BXO Taoxtvy Mvenoviy Mvenoviy Onepav o Byteo JMPA JMP cc caddr EA c0 MM MM 4 44 84 S6S THOMSO y cA eer Ivotpvuyuov 2 Bpavyn avd Ivotpuxtiovo XOVOLTLOV XOVOLTLOV Xode eo ee ue ha ee ee eee ia feee ece camry an O c 0 N
163. L Rwytdata 5C n 2 74 84 ka 565 0 50 A A Ivotpuxuov Let Entot orl 2 OPERATION count 0 2 0 0 DO WHILE count 0 V C v V C opo opin op1 1 nz 0 to 14 optis 0 count 1 END WHILE DATATYPES WORD Shifts the destination word operand op1 right by as many times as specified by the source operand op2 The most significant bits of the result are filled with zecosdiaglySince the bits shifted out effectively represent thea mier the Overflow flag is used instead as a Roundingflag This flag together with the Carry flag helps the user to determine whether the remainder bits lost were greater than less than or equal to one half an LSB Only shift values between 0 and 15 are allowed When using a GPR as the count control only the least significant 4 bits are used FLAGS E 2 V pots sis Always cleared Set if result equals zero Cleared otherwise V Setifinany cycle of the shift operation a 1 is shifted out of the Carry flag Cleared for a shift count of zero C The Carry flag is set according to the last LSB bit shifted out of op1 Cleared for a shift count of zero Setif the most significant bit of the result is set Cleared otherwise N m INSTRUCTION FORMAT BXO Taoxivy Mvenoviy Mvenoviy Onepav o Byteo SHR SHR Rwn Rwm 6C nm 2 SHR SHR Rw data 7C iin 2 57 S65 THOM
164. LAGS E 2 V 0 NORj OR AND E Always cleared Z Contains the logical NOR ofthe two specified bits V Containsthe logical OR of the two specified bits C the logical AND of the two specified bits N Containsthe logical XOR of the two specified bits INSTRUCTION FORMAT BXO Taokwy Onepav o Byteo BCMP CMP bitaddrzz bitaddag 2 QQ ZZ qz 4 14 84 SGS THOMSO A Ivotpuyuov Let But dieA Byte 1 0 2 3 OPERATION DATA TYPES FLAGS tmp op1 high byte tmp high byte tmp op2 v op3 op1 tmp WORD Replaces those bits in the high byte of the destination word operand op1 which are se lected by 1 in the AND mask op2 with the bits at theespondincpositions in the OR mask specified by op3 Note Bits which are masked off by a 0 in the AND mask op2 may be uninteatty al tered if the corresponding bit in the OR mask op3 contains 1 E 2 V Always cleared Set if the word result equals zero Cleared otherwise Always cleared Always cleared Set if the most significant bit of the word result is set Cleared otherwise lt INSTRUCTION FORMAT Mvenoviy BFLDH BXO Taoxtvy Mven ovi Onepav o Byteo BFLDH bitoff mask data 1 QQ 4 57 S6S THOMSON
165. M Registers Interrupt Control Registers CCOIC through CC151C Reset Value for all of the register 000h CCOIC FF78h BCh gl CCOIR 6 5 4 3 2 CC1IC FF7Ah BDh 7 6 5 4 3 2 CC2IC FF7Ch BEh 7 6 5 4 3 2 CC3IC FF7Eh BFh 7 6 5 4 3 2 CCAIC FF80h COh 7 6 5 4 3 2 CC5IC FF82h C1h 7 6 5 4 3 2 CC6IC FF84h C2h 7 6 5 4 3 2 CC7IC FF86h C3h 7 6 5 4 3 2 20 64 GLVL GLVL GLVL GLVL GLVL GLVL GLVL GLVL e e e e e e e e CC8IC FF88h C4h 7 6 5 4 3 2 CC9IC FF8Ah C5h 6 5 4 3 2 7 CC10IC FF8Ch C6h 7 5 4 3 2 FF8Eh C7h 7 6 5 4 3 2 CC121C FF90h C8h 7 6 5 4 3 2 FF92h C9h 7 5 4 3 2 ILVL CC14IC FF94h 7 6 5 4 3 2 FF96h CBh 7 6 5 4 3 2 o o SGS THOMSON MICROELECTRONICS GLVL GLVL GLVL GLVL GLVL GLVL GLVL e e e e e e e e GLVL 8 Peripherals Figure 8 14 Block Diagram of GPT1 Auxiliary Timer T2 System Clock Interrupt Requests External Interrupt Count and Core Timer T3 Capture Output Reload Control Control Inputs External Output External Up Down Control Auxili Timer T4 Input uxiliary VR001624 Figure 8 15 Block Diagram of GPT2 Timer T5 Auxiliary Interrupt Requests Mode Interrupt and External CAPREL Register Input Output Output Control
166. MDH reg After roset this register ipitializedo 0000h ister for programming multiply and divide algo A detailed description of how to use the MDL regis rithms can be found in section 13 2 ter for programming multiply and divide algorithms can be found in section 13 2 MDH FEOCh 06h MDL FEOEh 07h Multiply Divide Register High Portion Multiply Divide Register Low Portion Reset Value 0000h Reset Value 0000h 15 14 13 12 11 10 9 8 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 MDH continuation MDL continuation b15 b0 Multiply Divide Register High b15 to 60 Multiply Divide Register Low Portion Portion Specifies the high order 16 bits of the 32 bit Mul Specifies the low order 16 bits of the 32 bit Multi tiply and Divide Register MD ply and Divide Register MD 565 50 25 26 YZ 5 Central Processing Unit 5 3 14 MDC Multiply Divide Control Register MDC FEOEh 87h This bit addressable 16 bit register is implicitlyMultiply Divide Control Register used by the CPU when it performs a multiplication Reset cia or a division It is used to store the required control information for the corneendi multiply or divide 15 operation The MDC register is updated by hard ware during each single cycle ofa multiply or divide instruction Bo Le og 1 When a division or muplicationwas interrupted Rem EN HR 9 before its completi
167. MINARY DATA PQFP100 Ordering Information at the end of the datasheet A complete set of development tools is also avail able including C Compiler Assembler Linker Locater Librarian Emulator Starter Kit 1 6 This is advance information from SGS THOMSON Details are subjectto change without notice ST10166 ST10R166 Figure 1 ST10166 ST10R166 Pin Configuration VROO1549 Table 1 PINOUT Description ST10166 ST10R166 P0 3 P0 4 P0 5 P0 6 P0 7 VSS VCC P0 8 P0 9 P0 10 11 P0 12 P0 13 P0 14 P0 15 P4 0 P4 1 VCC XTAL2 XTAL1 VSS BUSACT EBC1 EBCO RSTOUT NMI P1 0 2 6 SGS THOMSON A3 v cRosuseTROMICS ABSOLUTE MAXIMUM RATINGS Ambient temperature under bias TA 0 to 70 C Storage temperature 6510 125 Supply Voltage Vcc 6 5V Input Voltage Vin min 3 0 V for pulse width less than 15ns 0 5 to VCC 0 5 V ee ATF Symbol Parameter Input Low Voltage 0 2 0 1 0 2 Vcc Ie ILE UT Input High Voltage all except and XTAL1 Output Low Voltage _ Ports 0 1 4 ALE RD WR BHE CLKOUT RSTOUT ST10166 ST10R166 Note Stresses above those listed under Absolute Maximum Rat ings may cause permanent damage to the device This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the op erational sections of this specification is not implied
168. N and the ters used for instruction fetches while executing inBUSCON1 register must select one of the multi structions from either internal ROM RAM or from plexed bus modes This is also true for the READY a different SYSCON or BUSCON1 address range function In order to use tREADY pin foigeneral For example if one wants to reprogram the purpose I O RDYEN in register SYSCON and BUSCONT1 register one should execute the in RDYEN1 in register BUSCON1 must be 0 structions to modify the register from an address space which is currently controlled by the SY SCON register Figure 9 16 Switching From Non Multiplexed Bus to Multiplexed Bus CLKOUT ADDRESS ADDRESS m Non Multiplexed Busk 1 State ultiplexed Bus Access Access Hold 2 18 20 Ey SGS THOMSON MICROELECTRONICS 9 9 EXTERNAL MEMORY ACCESS VIA THE DATA READY SIGNAL An optional Data Ready function can be used to al low an external device to determine the duration of an external memory access Note that tREADY input pin must be correctly activated for every ex ternal memory access if the Data Ready function has been enabled Otherwise the CPU would be halted until a reset occurs No time out protection other than a Watchdog Timer overflow is provided The Data Ready function can benabledby set ting the RDYEN bit in the SYSCON register to 1 see chapter 5 When the Data Ready function amp nabled the du ration of all external accesses iis det
169. NIT is placed at the internal memory decoders and al lows the user to specify any address directly or in directly and obtain the desired data without using temporary registers or special instructions All standard arithmetic and logical operations are performed in a 16 bit ALU In addition for byte op erations signals are provided from bits six and seven of the ALU result to correctly set the condi tion flags Miltiple arithmetic igrovided through a CARRY IN signal to the ALU from pre re AOE arr viously calculated portions of the desired opera For both code and data storage the ST10166 pro tion Booth multiplication and division areVides an internal ROM of 32 Kbytes and the supported by an e hded ALU and bit shifter 5110 166 provides an internal FLASH memory of placed on two coupled 16 bit registers MDL and 32Kbytes For both this memory area is connected MDH All targets for branch calculations are also 10 the CPU via a 32 bit bus Thus an entideuble computed in the central ALU word instruction can be fetched in one machine cy cle Program execution from the on chip ROM or FLASH memory is the fastest of all possible alter natives 4 6 yy 3GS THOMSON Figure 1 1 Functional Block Diagram Clock Generator ROM or FLASH 32KBytes Watchdog Timer 16 Bit CPU Interrupt amp PEC Control General Purpose Timer Unit GPT2 16 Bit Timer TO General Purpose Timer
170. NVERTER ud ea os ex et edet gr at tec el dede 2 5 SERIAE CHANNELS 2 2 6 WATCHDOG TIMER 22e dtt a 2 6 PARALLEL PORTS udis 2 6 Ey SGS THOMSON i MICROELECTRGNICS GENERAL INDEX 3 MEMORY ORGANIZATION 3 1 INTERNAL PROGRAM MEMORY 3 5 3 2 EXTERNAL MEMORY ttt e eee e setti it de cene cita 3 5 3 3 INTERNALRAM oue E dete ete ee 3 6 3 3 1 System Stack efe CU I endet 3 6 3 3 2 General Purpose 2 2 02 3 7 3 3 3 Pec Source and Destination Pointers 3 9 3 4 INTERNAL SPECIAL FUNCTION REGISTERS 3 10 4 ON CHIP FLASH MEMORY 4 1 5 CENTRAL PROCSSING UNIT 5 1 5 1 1 5 1 2 5 1 3 5 1 4 5 2 5 2 1 5 2 2 5 2 3 5 3 5 3 1 5 3 1 1 5 3 1 2 5 3 1 3 5 3 1 4 5 3 1 5 5 3 1 6 5 3 1 7 5 3 2 5 3 3 5 3 4 5 3 4 1 5 3 4 2 5 3 4 3 INSTRUCTION 5 2 Sequential Instruction Processing 2 22 5 2 Standard Branch Instruction Processing
171. O 5 8 ire PEE 13 System Programming Providing Local Registers for Subroutines For subroutines which require local storage the followingnethods are provided Alternate Bank of Registers Upon entry to a subroutine it is possible to specify a new set of local registers by executing a SCXT switch context instruction This mechanism does not provide a method to recursively call a subrou tine Saving and Restoring of Registers To provide local registers one can push the contents of the registers which are required for use by the subroutine and pop the previous values be fore returning to the calling routine This is the most common echnique used today it does provide a mechanism to support recur sive procedures This method however re quires two machine cycles per register stored on the system stack one cycle to PUSH the register and one to POP the register Figure 13 1 Local Registers Old Stack Newly Allocated Register Bank New Stack Area Use of the System Stack for Local Registers It is possible to use the SP and CP to set up local subroutine register frames This allows sub routines to dynamically allocate local variables as neededin two machine cycles To allocate a local frame one simply subtracts the number of required local registers from the SP and then moves the value of the new SP to the CP This operation is supported through the SCXT switch context instruc
172. O TNE 1V MAA 00001 me Paon tepva PAM iv tHe lvxXE the geuopy 16 OTLAA ueuopy Be pou o VVE TEX TES e amp ex v uov WLAA OX Xop pepopy It to xo evtep tne pode 16 000 ov THE artn THE EBX1 EBXO BYXAXT tied 1V Dy Mixpo avd AAE 0AA 0 niyn Sve xo tne payt THAT TE EAEXTPOVLYG LO vot AXXECOLBAE pou ovy AE qv t6 By a coptoape A NAPS LVTEPVOLA ESTEPVOLA uepopy wape ovPETIN WIAA THEV OTAPT TNE SEDLXE LV Tne Aoa ep opa MO ONEXLAA LOSE WIAA ev WITH A onopt avd THE TEXNVLOVE AXXEOG Tne PECET TO 000 THE PAcon PEXELWES HPOL 010 METNE wivdow tHE AXTIBATIOV NMI 1 16 anmpoemoatery luo xo 10 THE SEAXTLIBATLOV 1 4 Aoadep E 1 10 166 Mode Hardware reset ALE
173. OELECTRONICS E EgaunAe Aoadep tne 10 166 5 Mode INTPOAYXTION 116 Paon THE 10 166 16 10 166 cepi 1 tHE wtepvarA PAM avd me 1950 emye npototymivy PEXEIMIvy Sedived vouBEp oo Buceo quio ue vou GoXoue op penpoypouuaBAe PAM addpeco the oases npo ATTALYATLOVG Tnt VOTE ECAUTAE THE tu OTHEP TPOYPALL OVVYTLOVAALTY 16 TOGOLBAE TAEMEVTATLOV OV XNIT AOASEP EVTEPLVY te MAA Be op tme Paon ueuopy A 10 166 yovoryupesd oivyAe xn vo e amp TEPVOA WELOPY Qnev tne 10 166 16 xov vyopeg tv ynn THE 10 166 WIAA at Iv op ep e exvte me Aoadep tHE 0000n tHE ueuopw coraxe amiy The 10 166 to me ueuopy Tnepe ope tv THE YAGE a TOTAAAW EpacEdS HOSE THLG 16 dove A peototop xov iaon ueuopw OP xo e olde VEX1E tne ome a mE praon HELOPW
174. ORBUF store rec eived byte SORIR clear rec eive inte rrupt req uest bit 0 EndAddress all bytes rec eived CC_NE ReceiveL ifnotc ontin ue loop CC_UC RamRouti neSta rt yes jump to RAMrouti ne BTLCOIE ENDS 4 4 S amp S THOMSON GS SIE Sese APPENDIX F DATASHEET OVERVIEW This Appendix presents an overview of the ST10x166 product range ST10F166 16 BIT MCU WITH 256K FLASH MEMORY AND A D CONVERTER ST10166 16 BIT MCU WITH 32K INTERNAL ROM AND A D CONVERTER ST10R166 16 BIT MCU WITH A D CONVERTER ROMLESS Ey SGS THOMSON QGhh o MICROELECTRONICS ka SGS THOMSON wicresuerremcs SGS THOMSON JJ NicRoELECTROMIES ST10F166 16 BIT MCU WITH 256K FLASH MEMORY AND A D CONVERTER ADVANCE DATA High Performance 16 bit CPU with 4 Stage Pipeline 100ns Instruction Cycle Time at 20MHz CPU Clock 500ns Multiplication 16x16 bits 1us Division 32 16 bits Enhanced Boolean Bit Manipulation Facilities Register Based Design with Multiple Variable Register Banks Single Cycle Context Switching Support 256 Kbyte Linear Address Space for Code and Data 1Kbyte On Chip RAM 32 KBYTE ON CHIP FLASH MEMORY WITH BANK ERASE 512 byte On Chip Special Function Register Area 8 Channel Interrupt Driven Single Cycle Data Transfer Facilities via Peripheral Event Control PQFP100 Ordering Information at the end of the datasheet ler PEC A complet
175. PSW5oppedfrom the stack Restored from the the stack Restored from the PSVboppedfrom the stack ZzZO NwNI INSTRUCTION FORMAT Mvenoviy RETI 68 84 BXO Taoktvy Mvenoviy Onepav o Byteo RET FB 88 2 5 S amp S THOMSON A Ivotpuxuov Let oni OPERATION IP SP SP SP 2 tmp lt SP SP SP 2 1 tmp DATATYPES WORD Returns from a subroutine The IP is first popped from the system stack and then the next word is popped from the system stack into the operand specified by op1 Execution re sumes at the instructionltowinghe CALL instruction in the calling routine FLAGS E 2 V E Setif thevalue ofthe word popped into operand op1 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table 2 Setif the value of the womloppedinto operand equals zero Cleared otherwise V Not affected C Notaffected Setif the most significant bit of the into operand is se leared otherwise INSTRUCTION FORMAT BXO Taoxivy Onepav o Byteo RETP RETP reg EB RR 2 57 S65 THOMSON 2 0980 MICROELECTRGNICS A Ivotpux tiov Let PEPIX PETX OPERATION FLAGS PEIX Ivtep Leyuevt LoBpovtive IP
176. R unio ck ock wait 10 fcrv al y firsti nstru ction ond instr uctio ofunlock seq uenceto enterinthe write mode time out 10 us to set in terna sig nals FWEz1 these two i nstru ction s FEE 1 def ine the erasu re TLO 0 CKC TL1 1 defin ea 10mspulse WOWW 0 BEO 1 BE1 0 sel ect bank 1 SETz1con firm writ e mode load FCR set up SGS THOMSON MICROELECTRONICS TEST VPP mov fcrrd FCR read FCR jnb vp priv vpp fail test if VPP is high FLASHE erase add Ip cnt 01h inc rementtheal go loop counter cmp Ip cnt MAXLOOP2 compare to the limit jmpr cc_Z eras fail jump if limit has b een reach ed mov f sca n fl scan erasec rasur e start waiter mov fc rrd FCR read FCR jb busy waiter jumpif era sure is not ended TESTVPP jb vpp fail jump if FCVPP is set to know if fail occured because VPP did not havetheco rrect valued uring era sure ERASEV ERIFY MODE read f f cmp all1 fl scan first i nstru ction for EVM calla cc UC wait 4 time out 4 us cmp fl scan sec ond instr uctio n forEVM jmpr cc NZ erase jump if the word is not erased add fl _scan 02h inc rementthe bankp _ ointe r cmp fl scan FL SIZE com pare to the last bank address jmpr NZ read ff jump to ver ify the next address EXITOF WRITE MODE mov fcrval
177. S DURING IDLE AND POWER DOWN 12 2 13 SYSTEM PROGRAMMING 13 1 INSTRUCTIONS PROVIDED AS SUBSETS OF INSTRUCTIONS 13 1 13 1 1 Directly Substitutable Instructions 13 1 13 1 2 Modification of System Flags 13 1 13 1 3 External Memory Data Access I e rrr rrr rrna 13 1 13 2 MULTIPLICATION AND 2 2 2 222 13 2 13 3 BCD CALCULATIONS decere att eee tee c 13 3 13 4 STACK OPERATIONS i eroe m b ete ete oot oka ei E ER 13 3 13 4 1 Internal System 13 3 13 4 1 1 USE OF STACK UNDERFLOW OVERFLOW REGISTERS 13 4 13 4 2 User SIacks o Ub De rendent 13 5 13 5 REGISTER 22 2222222120220002 13 5 13 6 PROCEDURE CALL ENTRY AND EXIT 2 2 22 13 5 13 6 1 Passing Parameters on the System Stack 13 5 13 6 2 Cross Segment Subroutine Calls 13 5 13 6 3 Providing Local Registers for Subroutines 13 6 13
178. S6S THOMSON 8 MICROELECTRGNICS A Ivotpux tiov Let POP POP Potate POP onl 2 OPERATION count op2 0 0 DO WHILE count 0 V V opo opin op1 1 n2O to 14 opis count count 1 END WHILE DATATYPES WORD Rotates the destination word operand op1 right by as many times as specified by the source operand op2 Bit 0 is rotated into Bit 15 and into the Carry Only shift values be tween Oand 15 areallowed When using a GPR as the count control only the least signifi cant 4 bits are used FLAGS E 2 V Always cleared Set if result equals zero Cleared otherwise V Setifinany cycle of the shift operation a 1 is shifted out of the Carry flag Cleared for a rotate count of zero C The Carry flag is set according to the last LSB shifted out of op1 Cleared for a rotate count of zero Setif the most significant bit of the result is set Cleared otherwise N m INSTRUCTION FORMAT BXO Taoxtivy Mvenoviy Mvenoviy Onepav o Byteo ROR ROR Rwn Rwm 2C nm 2 ROR ROR Rwn data zn 2 72 84 SGS THOMSO A A Ivotpuxuov AXSI XOVTECT EXET 1 2 OPERATION 1 1 tmp2 2 SP lt SP 2 SP tmp1 1 tmp2 LAST Used to switch contexts for any register Switching contextis a push and loa
179. SGS THOMSON MICROELECTRGNICS 10 Parallel Ports 10 1 4 Port 4 The alternate functions on the two pins of Port 4 and theBHE signal the alternate function of Port P4 are the two segment address lines A16 and 4 might be required directly after reset Thus the 17 shown in table below As for Port 0 Port 1 alternate function of Port 4 will be switched auto matically Table 10 2 Port 4 Alternate Output Functions Figure 10 13 shows a block diagram ofa Port4 whichsupplieshe segment address Via a second which is the same as for a Port1 pin When an ex multiplexer the output buffer is enabled to drive ternal bus is selected AND segmentation is en the segment address abled through bit SGTDIS 0 in register segmentation is not required in an application SYSCON default after reset the inputto the port the can disable seginentation by patting bit output latch is switched via a multiplexer from theggTpjs to 1 The pins of Port 4 can then be used internal bus to the Alternate Data Output line tor general purpose I O Figure 10 13 Block Diagram of a Port 4 Pin Write DP4 y Direction Latch DP4 y Alternate Reod Direction Function Enable Read Buffer Alternate Function Enable Write Port P4 y Alternate Data Output Output Latch Read Port P4 y Read Buffer sGs THomson NB 10 Parallel Ports 10 2 Port 5 result when reading Port 5 Port 5 is actu
180. SON MICROELECTRONICS A Ivotpux tiov Let ZPL Yootoaope Pecet OPERATION Software Reset This instruction is used to perform a software reset A software reset has the same effect on the microcontroller as an externally applied hardware reset To insure that this instruc tion is not accidentally executed it is implemented as a protected instruction FLAGS E 2 V E Always cleared 2 Always cleared Always cleared Always cleared Always cleared INSTRUCTION FORMAT BXO Taoxtivy Mvepnovtux Byteo SRST SRST B7 48 B7 B7 4 76 84 565 0 50 A Ivotpuxuov Let lt Qatyndoy YPGOAT OPERATION Service Watchdog Timer This instruction services the Watchdog Timer It reloads the high order byte of the Watch dog Timer with a preset value and clearsthe low byte on every occurrence Once this in struction has been executed the watchdog timer cannot be disabled To insure that this instruction is not accidentally executed it is implemented as a protected instruction FLAGS E 2 V C N E Not affected Z Not affected V Not affected Not affected N Not affected INSTRUCTION FORMAT BXO Taoxtivy Mvenoviy Mvenoviy Byteo SRVWDT SRVWDT A7 58 A7 A7 4 565 0 77 84 are A Ivotpux tiov Let XYB XYB Ivteyep
181. ST10 FAMILY 16 BIT MCU USER MANUAL 1st EDITION APRIL 1992 USE IN LIFE SUPPORT DEVICES OR SYSTEMS MUST BE EXPRESSLY AUTHORIZED SGS THOMSON PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF SGS THOMSON Microelectronics As used herein 1 Life support devices or systems are those which a are intended for surgical implant into the body or b support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided with the product can be reasonably expected to result in significant in jury to the user 2 A critical component is any component of a life support device or system whose failure to perform can reasonably be expected to cause the failure of the life support device or system or to affect its safety or effectiveness GENERAL INDEX INTRODUCTION FEATURES 1 ARCHITECTURAL OVERVIEW 1 1 1 1 1 1 1 2 1 1 3 1 1 4 1 1 5 1 1 6 1 2 1 2 1 1 2 1 1 1 2 1 2 1 2 1 3 1 2 2 1 2 3 1 2 4 1 2 5 1 2 6 BASIC CPU CONCEPTS AND OPTIMIZATIONS 1 1 High Instruction Bandwidth Fast Execution 1 1 High Function 8 bit and 16 bit Arithmetic and Logic Unit 1 2 Extended Bit Processing and Peripheral Control
182. TEOTL may be outputon pin T6OUT This signal has 8 times more transitions than the signal which is applied to pin CAPIN The underflow signal of timer T6 can furthermore be used to clock the CAPCOM timers TO and or T1 which gives the user the possibility to set compare eventsbasedon a finer resolution than that of the ex ternal events 8 3 A D CONVERTER ADC ADST ADCH ADM ADBSY Conversion Control Analog Input Channels Converter Interrupt Requests 10 Bit Result Reg ADDAT VAREF VAGND SGS THOMSON VROP1641 45 64 MIGRCELECTREMICS 8 Peripherals The ST10x166 provides a 10 bit A D converter with 10 multiplexed analog input channels and a sample amp hold circuit on chip It supports 4 differ ent conversion modes including single channel single channel continuous auto scan and auto scan continuous conversion The external analog reference voltages Varer and are fixed Fig ure below shows a block diagram of the A D con verter In the following Figure 8 37 all SFRs and port pins are listed which are associated with the A D con verter 8 3 1 Conversion Modes and Operation The analog input channels ANO through AN9 are alternate functions of port 5 which is a 10 bit input only port The port 5 lines may either be used as analog or digital inputs No special action is re quired by the user software to configure the port 5 lines as analog inputs The functions of the A
183. U S A 6 6 S amp S THOMSON AE
184. UPT SOURCES Enablingand disabling of interrupt sources can be performed in several ways 1 Each interrupt source can Hedividuallyn abled or disabled by setting or clearing its In terrupt Enable flag in the interrupt control register that is associated with this source However as long as the global Interrupt En able control bit IEN in the PSW has not been set all interrupt sources remagioballydis abled and no interrupt requests will be ac knowledgedby the CPU 2 When the IEN bit in the PSW is set to 1 all in terrupt sources that have been individually en abled become globally enabled Interrupt requests which are generated by these sources can then participate in the prioritiza tion process The requests will be acknow ledged by the CPU according to their priority By programming the ILVL field of an Interrupt Control register to level 0 the associated source can never interrupt the CPU Programming the CPU priority in the PSW toa certain level prevents the CPU from being in terrupted by requests on the same or any lower level With this method all interrupts be low acertain level can be disabled with one in struction e g the Bit F ield BFLDH instruction 3 4 7 2 3 2 PRIORITY LEVEL STRUCTURE In the ST10x166 s interrupt system the priority ofa ferent sources on the same priority level is not fixed by the system but can be assigned via software In all cases the source on tHeighest
185. Which are switched to the higmpedancestate nition of data frames with missing stop bits An When configured as inputs During the internal re overrun error will be generated if the last character Set all port pins are configured as inputs received has not been read out of the receive buff Each port line has one programmable alternate in er register at the time reception of a new character put or output function associated with it Ports 0 is complete 1 may be used as address and data lines when accessing external memory while Port 4 outputs the additional segment address bits A16 and A17 2 9 WATCHDOG TIMER in systems where segmentation nabledto ac cess more than 64Kbytes of memory Port 2 is as The Watchdog Timer of the ST10x166 represents sociated with the capture inputs compare outputs one of the fail safe mechanissnwhich have been the CAPCOM unit and Port 3 includes alternate implemented to prevent the controller from mal functions of timers serial interfaces optional bus functioning for longer periods of time control signalf R BHE READY and the system The Watchdog Timer of the ST10x166 is always clock output CLKOUT Port 5 is used for the ana enabledafter a reset of the chip and can only be log input channels to the A D converter Whenany disabledin the time interval until the EINIT end of one of these alternate functions is not used the initialiation instruction has been executed Thus respective port line may be u
186. a block diagram of timer TO Figure 8 3 CAPCOM Timer TO Block Diagram Input Reload Reg TOREL Control System Clock GPT2 Timer T6 Interrupt Over Underflow Request P3 0 Edge Select TOI TOM TOI VROOT837 Interrupt Request GPT2 Timer T6 Over Underflow VROA1637 8 64 Gr SGS THOMSON TT 8 Peripherals 8 1 2 Capture Compare Registers CCMO FF52h A9h The sixteen 16 bit capture compare registers CAPCOM Mode Control Registers CCMO through CC15 are used as data registers for cap Reset Value 0000h ture or compare operations with respect to timer TO and T1 The capture compare 5 14 13 12 11 10 9 8 addressable Each of the registers through CC15 7 6 5 4 3 2 1 0 individuallyrogrammed for capture or one of 4 different compare modes and may be allocated in dividuallyto one of the timers TO or T1 A special b15 ACC3 Capture Compare Register Al combination of compare modes additionally allows bit the implemerdtion of a double regiet compare If set at 1 allocate to Timer 1 otherwise al mode When capture orampare operdbn is dis locate CC3 to Timer 0 abled for one of the registers it may be used for 3 b14 to b12 Capture Compare Regis general purpose variable storage ter CC3 Mode Selection The functions of the 16 capture compare registers See Table 8 3 are controlled by 4 b
187. a com ter to 110b pare register configured for compare mode 2 Note When a match is detected in compare mode 2 for that the port latch and pin remain unaffected in the first time within a timer period interrupt mode 2 Figure 8 10 shows a simple tim flag CCXIR is set to 1 The corspondingPort 2 9 example for this compare mode In this exam pin P2 x is not affected and can be used as a nor Ple the compare value in register CCx is modified mal I O pin However after the first match has from cv1 to cv2 after compare event 1 However been detected in this mode all further compare COMpare event 2 will not occur until the next pe events within the same timer period adisabled iod of timer Ty 14 64 SGS THOMSON 8 Peripherals Figure 8 9 Compare Mode 2 and3 Block Diagram Interrupt Compare Reg CCx Request Comparator Set Mode 3 CCMODx CAPCOM Timer Ty eques VROAI63B Figure 8 10 Timing Example for Compare Mode 2 Contents of Ty FFFFh Compare Value cv2 Compare Value cv1 Reload Value lt TyREL gt 0000h Interrupt Requests TyIR CCxIR CCxIR TyIR Event 1 Event 2 2 1 VROB1639 Ey SGS THOMSON 15 64 MICROELECTRONICS 8 Peripherals 8 1 2 2 4 Compare Mode 3 Figure 8 11 shows the timing example from the Compare mode 3 is selected for register CCx by Previo
188. a menupt Convoi easier Wm rrn aah GeriTmersConvmegsw omm e Freon sm m rem zm Ath e Freon s o rean om oon wor om watonsogTinernesisereesoniy _ me ow Samara mo ZEROS FF1Ch Constant Value 0 s Register read only 0000h 16 16 Gr SGS THOMSON SGS THOMSO C APPLICATION EXAMPLE This portion of theppendixis subdividednto two sections Section C 1 shows examples for the use of different types of memories connected to the ST10x166 in different external bus c g rations Section C 2 contains formulas tables and exam ples for programming the ST10x166 wait states described in detail in section 9 7 C 1 EXTERNAL BUS AND MEMORY CONFIGURATIONS A description of the possible ST10x166 external bus configuration modes which are determined by the state of the EBC1 EBCO andBUSACT input pins during reset can be found in chapter 9 Note that the dllowingexamples refer to the non seg mented memory model which supports only 64Kbytes of memory space Thus port pins P4 1 and P4 0 are not required as outpu s additional segment address bits A17 and A16 1 16 bit Addresses 8 bit Data Multiplexed
189. aal a ddrev secondin struc tion for PVM jmpr cc NZ prog jump if the word isnotc orrec tly progr ammedre start pro gramning cmp daah ddrod first ins truct ion for PVM odd call a cc UC wait4 4 us cmp daah ddrod secondin struc tion for PVM jmpr cc NZ prog jump if the word isnotc orrec tly progr ammedre start pro gramning 6 19 Gr SGS THOMSON MEMOP Y 25 For each new programming operation the variable must be incremented at this point it must be tested to verify whether the 25 limit has been reached or not If yes the word will never be programmed and the algorithm should be exited from In this case a possible solution is to change the address of the word to program add Ip cnt 011 incre ment the algo loopc ounter cmp Ipcnt compare to the limit jmpr cc Z p rg fa il jump if limit has been rea ched AAXT AAAPEXYY In case of consecutives words to program check the address variable to know if the last address has been reached If not increment the address variable and start another programming operation from the begin ning of the algorithm 0 All the words programmed exit the presto F program Write algorithm programming or program ver ify read operation are stopped by a reset of FCR register especially FWE bit cleared dfoeadingof the Flash memory can be performed only
190. able 8 12 GPT1 Auxiliary Timers Capture TriggerSelection x 2 or 4 21 4 Contents of T3 Captured into T2 T4 dl Positive and Negative External Transition on TxIN 34 64 SGS THOMSON MICROELECTRONICS 8 Peripherals T3CON so that it can be altered by software if re quired to modify the PWM signal 8 2 1 2 4 Capture Mode Capture mode is selected by programming the mode control fields T2M or T4M to 101b In cap ture mode the contents of the core timer are latched into an auxiliary timer register in response to a signal transition at the respective auxiliary timer s external input pin which is T2IN P3 7 for timer register T2 or T4IN P3 5 for timer register T4 The capture trigger signal can be a positive a negative or both a positive and a negative transi tion The two least significant bits of bit fields T2I or T4I are used to select the active transition see table below while the most significant bits 21 2 or 41 2 are irrelevant for the capture mode When programmed for capture mode the respective aux iliary timer T2 or T4 stops independent of its run flag T2R or If a selected transition at the corresponding input 2 T4INis detected then the contents of the core timer are loaded into the auxiliary timer Figure 8 27 GPT1 Auxiliary Timer in Capture Mode Capture Register Tx TxIN P3 7 P3 5 SGS THOMSON T2IC FF60h BOh
191. ach of the fourpipelinestages egardlessof whether all possible stage operations are really performed or not Since passing through onpipeline stage takes at least one machine cycle any single in struction takes at least four machine cycles to be completed Bpelining however allowgparallel this means snultaneou processing of up to four instructions Thus most of the instructions seem to be processed during one machine cycle as soon as thepipelinehas been filled once after reset see figure 5 1 Instructionpipeliningincreases the average in struction throughput considered over a certain pe riod of time In thedllowing any execution time specification of an instruction always refers to the average execution time due faipelited parallein struction processing FECH r k k u s e 2 26 Ey SGS THOMSON MICROELECTRGNICS 5 Central Processing Unit 5 1 2 Standard Branch Instruction Processing Instruction jpelininghelps to speed equential struction as shown in figure 5 2 program processing In the case that a branch is If a conditionabranch is not taken there is no de taken the instruction which has already been viation from theequentialrogram flow and thus fetched providently is mostly not the instructiorno extra tme is requiredin this case the instruc which must be decoded next Thus at least one tion after the branch instruction will enter the de additionalmachine cycle is normally required to code
192. ads from FBFEh while the tively Since locatio0000h is the first vector in the register bank selected by the CP grows upwards trap interrupt vector table it is the responsibility FCOOh the user to place a branch instruction at location Based on he appliation the user may wish to in zero which branches to the first instruction of thejtialize portions of the internal memory before nor initialiation routine Note that 8 bytes locations program operation Once the register bank reas e 22 In ir has been selected through programming of the CP e reset tunction single chip mode IS selected register can easily perform memory zeroing through pinBUSACT EBC1 and EBCO the inter through indirect addressing of the desired portions nal ROM for the ST10166 or the internal Flash of the internal memory memory for the ST10F166 is accessed when the RONDA initial branch is made to location zero Otherwise At the end of th nitializdbn the interrupt system an external fetch to location zero is made may be globallyenabled by moving the appropri ate constant to the PSW register One must be After reset the ROM access or the bus configura careful not to enable the interrupt system before in tion can be modified in the first instruction of theitialization is complete software initialization routine This is normally RUE quired whenever an eetnal memory is used be The sofware initializtion rouine should bedr
193. aitp r mov fc rrd FCR read FCR jb bu sy w aitpr jump if progr amming 1 not ended 0 To have a well programmed word it is important to check if VPP was at the correct value during program ming This is indicated by the status of the FCVPP bit of FCR If FCVPP 0 there was no problem continue with the algorithm If FCVPP 1 VPP was no noughhigh during programming jump to the user defined VPP fail routine An example of this routine could be a reset of FCR then a new test of the VPPRIV bit and if all is correct redo a programming operation otherwise exit the programming routine jb fc vpp vpp fai I jump if FCVPPisset To checkif the word is correctly programmed a comparison must be performed with the data expected Program Verify Read will check the cell margin of the word Perform twice the same reading instruction separated by a time sf 4 This sequence must be made to get a correct reading of the word This time corresponds to an internal switching of signals XOMIIAPE QITH EEIIEXTEA This step can be merged with the Program Verify Read step as the comparison instruction is a read instruc tion If the data programmed at the address given is different from the data expected an extra programming operation must be performed the next step cmp datal a ddrev first ins truct ion for PVM even call a cc UC wait4 4 us cmp d
194. allt ALL1 DATAL addrev ADDREV gramming of addre ss 0 000Ch with 08 642h reseta Igo reset FCR d ata value loadun lock data load10 usi oop data load4 us loop data resetw ait loop counter set R2 to FFFF load data loadad dress loop cou nter UNL OCK SEQUENCE FOR ENTERNG IN THEWR ITE MODE mov mov FCR unlo ck unlock ock calla cc UC wait 10 FCRSETUP FOR PROGRMMING bset belr belr belr bset mov fwe ck ctlO ck ctl1 wdww fw mset FCR fcrv al TEST VPP FCR vpp _ fail mov jnb fcrrd vp priv 16 19 firsti nstru ction sec ond instr uctio n ofunlock seq uenceto enterinto the w mode time out 10 sig nals rite us to set in terna FWE 1d efine pro gramning opera tion CKC TLO 0 TL1 0 defin 100 us pulse WDWWZO defin e 16 bit configura tion FWM SETz1ena ble progr am mode load FCR set up read FCR test if VPP is high SGS THOMSON MICROELECTRONICS FLASHP progw add Ip cnt 01h inc rementtheal 90 loop counter cmp Ipcnt 1 to the limit jmpr cc Z prg jump if limit has b een reach ed mov addrev d atal pro gramning commad waitpr FCR read FCR jb busy wait prw jump if pro gramning is note nded TESTVPP jb vpp jump if FCVPP is set to know if
195. ally a 10 bit port but the port register P5 is realized as a Port 5 P5 differs from Ports 0 through 4 since it is word register Positions P5 10 through P5 15 are a 10 bit input only port Besides being used as a reservedand will beead as zeros A write opera digital input port all lines of Port 5 may be used as tion to P5 has no effect The value written to it is the analog input to the A D converter lost The input buffers to P5 have Schmitt Trigger char acteristics in order to achieve logic levels from SP analog inputs Figure 10 14 illustrates the structurejinas being used as digital inputs A read operation of aPort 5 pin on Port 5 may be performed on any of the 10 bits Since Port 5is an input only port it has no port out The bits corresponding to lines being used as ana put latches and no direction register However an log inputs are don t care bits An A D conversion on address in the bit addressable register address a line being used as digital inputvill convert the space is provided in order to be able to read Port 5 logic leel applied b the pin Table 10 3 illustrates by software Register P5 shows the format of the the Port5 lines and the corrpsndinganalog input channels Figure 10 14 Block Diagram of a Port 5 Pin Channel Select Analog Switch To Sample Hold Circuit P5 Y ANy Read Buffer vROI1643 16 18 SGS THOMSON o MICROELECTRONICS 10
196. am a desired con propriate trap interrupt vector is made This figuration of a specifjseripheralione uses MOV sequence is described in detail in chapter 7 instructions of either constants or memory valuesA trap and interrupt routines require use of the to specific SFRs One can also alter specific con RETI return from interrupt instruction to exit from trol flags through bit instructions the called routine This instruction restores the sys Once in operation thperipheal operatesautono tem state from the system stack and then branches mously until an end condition is reached at whichto the location where the trap or interrupt occurred 57 S65 THOMSON 46 MICROELECTRONICS 13 System Programmin NOTES 8 8 3GS THOMSON TTT CROELECTRONIES SGS THOMSON JJ NicROELECTROMICS APPENDIX A INSTRUCTION SET A INZTPYXTION Section A 2 of thappendix of the ST10x166 User 1 3 Onepatiov Manual contains description of the This part presents a logical description of the op ST10x166 instructions ialphabeical order Basic eration portonned by an Instruction by means items of this descriptional part are defined thehigh jevellanguageconstruct A brief verbal de followingeection scription of the operation of the instruction is addi tionally provided 1 AeQtvitiovo The followingsymbols are used to represent data movement arithmetic or l
197. ame instruction cycle the highest priority tra 57 SGS THOMSON M MICROELECTRGNICS 7 Interrupt And Trap Functions correspondindlags in the register are set and the trap service routine is entered Since all class B traps have the same vector the priority of service of simultaneouly occurring class B traps is deter mined by software in the trap service routine TFR FFACh D6h Trap Flag Register TFR Reset Value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Rarer ioral b15 NMI External non Maskable Interrupt Trap request flag Set when a negatie transition is detected at the NMI pin Must be reset by software b14 STKOF Stack Overflow Trap request flag Set when the stack pointer value is less than the contents of the Stack Overflow STKOV register Must be reset by software b13 STKUF Stack Underflow Trap request flag Set when the stack pointer value is greater than the contents of the Stack Underflow STKUV register Must be reset by software b12 to b8 and b6 to b4 R Reserved b7 UNDOPC Undefined Opcode Trap request flag A class A trap occurring during the execution of a class B trap service routine will be serviced imme diately During the execution of a class A trap serv ice routine however any class B trap occurring will not be serviced until the class A trap service rou tine has finished Thus in this case the occur rence
198. an lowed by the high byte at the next odd byte ad even byte address and bit position 15 is the most dress Double words code only are stored in significant bit of the byte at the next odd byte ad ascending memory locations as twaubsequenly dress Figure 3 2 Word Byte And Bit Storage In a Byte Organised Memory Example xxxx6h xxxxbh xxxx4h Byte xxxx3h Byte xxxx2h Word High Byte xxxx1h Word Low Byte xxxxFh Table 3 1 shows how the different memory areas of memory segment 0 and into memory segments are mapped into the physical 256Kbyte address 1 through 3 Whenever the Program memory has space Basically all of the internal memory areas been disabledduring reset or remapped to seg ROM or FLASH memory RAM SFRs are 1 duringnitialiation the lowest 32Kbytes of mapped into memory segment 0 The ex segment 0 also specify an external memory area ternal memory is mapped into the raining parts 20 n SGS THOMSON MICROELECTRONICS 3 Memory Organization Table 3 1 Memory Address Space Mapping Address Space Memory Range Size Bytes 00000h O7FFFh Internal Program Memory Segment 0 or External Memory 08000h OF9FFh External Memory sks internal Memory 100008 17FFFh Internal Program Memory Segment 1 or External Memory The internal program memory the internal RAM RAM can basicallybe used for the system stack and the external m
199. and channel number may be specified While a conver sion isin progress modifications to the mode selec tion field ADM will not become effective until the next conversion Modifications to the channel se lection field ADCH will not become effective until Ey SGS THOMSON MICROELECTRONICS 8 Peripherals the next conversion in the single channel conver sion modes or the next conversion round in the auto scan modes 8 3 1 1 SINGLE CHANNEL CONVERSION MODE This mode is selected by programming the mode selection field ADM in register ADCON to 00b Af ter starting the converter through bit ADST the channel specified in bit field ADCH will be con verted After the conversion is complete interrupt request flag ADCIR will be set and the converter will automatically stop and reset bits ADBSY and ADST Resetting bit ADST while a conversion is in progress has no effect 8 3 1 2 SINGLE CHANNEL CONTINUOUS CONVERSION This mode is selected by bit combination 01b in bit field ADM After starting the converter the speci fied channel will be converted repeatedly until the converter is stopped by software Interrupt request flag ADCIRis set at the end of each single conver sion When bit ADST is reset by software the con verter will complete the current conversion and then stop and reset bit ADBSY 8 3 1 3 AUTO SCAN CONVERSION MODE With this mode a set of different analog input channels can be converted without requ
200. and divide algo rithms can be found in section 13 2 Reset Value FFFFh 15 14 13 12 11 10 9 8 5 3 15 ONES Constant Ones Register tt All bits of this bit addressable register are tied to 1 7 4 1 by hardware This register fead only The ONES ee register can be used as a register addressable aaa ee anos constant of all ones i e for bitanipulationor b15 to bO 1 2 mask generation It can be accessed via in All of the bits are tired to 1 by hardware en struction which is capable of addressingan SFR tire ONES register isead only 5 3 16 ZEROS Constant Zeros Register All bits of this bit addressable register are tied to ZEROS FFiCh 8Eh by hardware This register is read only The ZE Constant Zeros Register ROS register can be used as a register address Reset Value 0000h able constant of all zeros i e for lsitanipulation or mask generation It can be accessedviaanyin 15 14 13 12 11 10 9 8 struction which is capable of addressing SFR o o o o o o 7 6 5 4 3 2 1 0 b15 to b0 0 All of the bits are tired to 0 by hardware The en tire ZEROS register is read only 26 26 SGS THOMSON S71 SGS THOMSON e MICROELECTRONICS CHAPTER 6 INSTRUCTION SET OVERVIEW 6 INSTRUCTION SET OVERVIEW This chapter describes the ST10x166 s instruction 6 1 2 Logical Instructions set In the first section a short overv
201. any value This allows loop counters to cover any range This is particularly ad vantageous in table searching Saving of system state is automatically performed on theinternal system stagwoidinghe use of in 1 Architectural Overview 2 Avoid complexncodingschemes byplacing operands in consistent fields for each instruc tion Also avoid complex addressing modes which are not frequently used This decreases the instruction decode time while also simplify ing the development of compilers and assem blers Provide most frequently used instructions with one word instruction formats other instruc tions are placed into two word formats This al lows all instructions to be placed on word boundarieswhich alleviates the need for com plex alignment hardware It also has the bene fit of increasing the range for relatbranching instructions 3 1 1 6 Programmable Multiple Priority Interrupt Structure A number of enhancements have been included to structions to preserve state upon entry and exit ofallow processing of a large number of interrupt interrupt or trap routines Call instructions push th ources These are presented below value ofthe IP onthe system stack and require the same execution time as branch instructions Instructions have also been provided to support indi rect branch and call instructions This supports im plementation of multiple CASE statement branchingn assembler macros and high level lan gua
202. ash Pro ter banks and system stack When selectinginitiali gramming Board provided by SGS THOMSONMi zation values for the SP Stack Pointer and CP croelectronics Context Pointer registers one must ensure that pi i these registers ardnitialied before any GPR or during a hardware rese RS IN be pulledinigh stack operation is performed This includes inter n f rupt processing whichdssabledupon completion This feature is optional and if no program is stored of the internal reset and should remadisabled this area a software reset instruction SRST will until the SP isnitialigd select the address 0000h in the program memory 4 4 SGS THOMSO 772 SGS THOMSON JJ MICROELECTRONICS CHAPTER 12 POWER REDUCTION MODES 12 POWER REDUCTION MODES Two different power reduction modes with differ This feature can be used in conjunction with an ex ent levels of power reduction have been imple ternal power failure signal which pulls NMI pin mented in the ST10x166 which may be entered low when a power failure is imminent The micro under software control In Idle mode the CPU is controller will enter the NMI trap routine which can stopped while the peripherals continue their op perform saving of the internal state into RAM After eration In Power Down mode both the CPU and the internal state has been saved the trap routine the peripherals are stopped Idle mode can be may set or write a certa
203. ation described for thb and Rw addressing modes Specifies direct access to any word in the bit addressable memory space bit off requires eight bits in the in struction format Depending on the specified bitoff range different base addresses are used to generate physi cal addresses Short bitoff addresses from 00h to 7Fh use OFDOOh as a base address and thus they specify the 128 highest internal RAM word locations OFDOOh to OFDFEh Short bitoff ad dresses from 80h to EFh use 00 as a base address and thus they specify the highest internal SFR word locations 0 00 to OFFDEh Short bitoff addresses from 80h to EFh use OFFOOh as a base address and thus they specify the highest internal SFR word locations OFFOO0h to OFFDEh For short bitoff addresses from FOh to FFh only the lowest four bits and the contents of the CP register are used to generate the physical address of the selected word GPR Bit Word Offset Bit Word Offset Bit Word Offset 00h FFh Any Single Bit 0 15 bitaddr Any bit address is specified by a word address within the bit addressable memory space see bitoff and by a bit position bitpos within that word Thus bitaddr requires twelve bits in the instruction format 6 2 3 Long Addressing Mode This addressing mode uses one of the four DPP registers to specify a physical 18 bit address Any word or byte data within the entire memor
204. aud rate The 7th 8th and 9th sample are examined by the internal bit detectors The effective bit value is determined by a majority decision in order to avoid erroneous results that may be caused by noise If the detected value is not a 0 when the start bit is sampled the receive circuit is reset and waits for the next 1 to 0 transition at pin RXDO or RXD1 re spectively If the startbit proves valid the receive circuit continues sampling and shifts the incoming data frame into the receive shift register When the last stop bit has been received the con tents of the receive shift register are transferred to the receive data buffer register Simultaneously the receive interrupt request flag SORIR or S1RIR is set after the 9th sample in the first stop bit time slot when one stopbit has been programmed or in the second stop bittime slot when two stop bits are programmed regardless whether valid stop bits have beenreceived or not The receive circuit then waits for the next start bit 1 to O transition at its receive data input pin Note that in the 8 bit data wake up bit mode the data from receive shift register will only be transferred into SOR BUF S1RBUF and the receive interrupt request flag will only be set if the 9th data bit received was a l When the receiver enable bit SOREN or S1REN of a serial channel in asynchronous operation is reset to 0 while a reception is in progress the current reception will be completed in
205. aused by particular SFR operations as follows Readingan SFR immediately after an instruc tion which writes to the internal SFR space as shown in the following example MOV 1000h write to Timer 0 ADD R3 T1 read from Timer 1 1 x State Readingthe PSW register immediately after an In Ini instruction which implicitly updates the tion flags as shown in tHellowing eample ADD RO 1000h implicit modification of PSW flags BAND C Z read from PSW kad 2 x States In Ini external writes are normally performedparallel to other CPU operations Thusjalia could already have been considered in the standard processing time of another instruction Writing a via an 8 bit data bus requires twice as much time 2 ALE Cycle Times as the writing of a byte oper and JTesting Branch Conditions Tiada 0 or 1 x States Mostly NO extra time is required faonditional branch instructions to decide whether a branch condition is met or not However amiditional state time will be caused if the preceding instruc tion writesto the PSW register as shown in the fol lowing example BSET USRO write to PSW JMPR 2 label test condition flag in PSW Tiadaz 1 x State In this case the extra state time can simply be in tercepted by putting another suitable instruction before the onditionabranch instruction In Implicitly incrementing or decrementing the SP 7 J
206. auxiliary timers T2 and T4 has its own interrupt control reg ister T21C T4IC as shownin figure below Refer to chapter 7 for further details on interrupts 8 2 2 GPT2 Block Block GPT2 supports high precision event control with a maximum resolution of 200ns at 40MHz os cillator frequency It includes the two timers T5 and T6 and the 16 bit capture reload register CAPREL Timer is referred to as the core timer and T5 is referred to as the auxiliary timer of GPT2 Figure 8 28 SFRs And Port Pins Associated with the GPT2 Block Ports amp Direction Control Data Alternate Functions T6OUT P3 1 CAPIN P3 2 Port 3 Direction Control Register Port 3 Data Register GPT2 Timer 5 Register GPT2 Timer 6 Register GPT2 Capture Reload Register GPT2 Timer 5 Control Register GPT2 Timer 6 Control Register Registers Control Interrupt Registers Control VROB1640 GPT2 Timer 5 Interrupt Control Register GPT2 Timer 6 Interrupt Control Register GPT2 CAPREL Interrupt Control Register 36 64 SGS THOMSON o MICROELECTRONICS 8 Peripherals An overflow underflow of T6 which can only oper ate in timer mode is indicated by a toggle bit T6OTL whose state may be output on an alternate function port pin In addition T6 may be reloaded with the contents of CAPREL The toggle bit also supports concatenation of T6 with auxiliary timer T5 while concatenation of T6 with CAPCOM tim ers TO and 1 is provided
207. baud rate selection op tion can be selected through SOBRS or S1BRS The current baud rate will be multiplied by 2 3 All operating modes of the serial channels will be de scribed in detail in the following subsections 157 SGS THOMSON Clock Serial Port Control Shift Clock SxPE SxOE Receive Int Request Transmit Int Request Error Int Request Transmit Buffer Reg SxTBUF d TXDO P3 10 TXD4 P 3 8 VRDOO1B42 8 4 1 1 ASYNCHRONOUS OPERATION In asynchronous operation full duplex communi cation is supported The same operating mode and baud rate is used for both transmission and recep tion Each serial channel of the ST10x166 has two pins associated with it which are alternate functions of port pins RXDO P3 11 and TXDO P3 10 are used by ASCO in asynchronous operation as re 53 64 MIGRCELECTREMICS 8 Peripherals Figure 8 40 8 Bit Data Frame Start DO D7 Figure 8 41 9 Bit Data Frame D8 Start DO Bit LSB D1 D2 D3 D5 D7 parity wk up ceive data input and transmit data output pins re spectively while RXD1 P3 9 and TXD1 P3 8 are used by ASC1 Figure 8 39 shows a block diagram of a serial channel in the asynchronous mode of operation Information Frames in Asynchronous Opera tion Each information frame that can be transmitted or received by the serial channels in asynchronous operation consists of the following elements One startbit An 8
208. bined with the use of the Erase verify PRESTO F algorithm provides a tight erase threshold voltage distribution generating suffi cient margin to the faster erasing cell and the minimum threshold level required to read a one data value EPAXE amp XONTPOA To simplify control of the Flash operation modes the ST10F166 Flash memory includes a Flash Control Register FCR used for all programming or erase operations Mapped virtually into the Flash address space FCR is not accessible during normal memory access modes and must be unlocked by a special instruction sequence To avoid unpredictable programming or erase operation on the Flash memory the ST10F166 provides several levels of security Pipot user must perform a special sequence to enable the FCRand to enter into the writing mode Lexovd eoe to operate on the Flash memory two steps are necessary Firstthe user must set up the FCR in the desired configuration second the operation begins ONLY with the appropriate command Trips AeoeA during the writing mode two bits of FCR VPPRIV amp FCVPP indicate to the user the status of VPP the high voltage before and during an operation It is advisable for the user to test them in the erase or programming routine SGS THoMson 5 5 YF MICROELECTRONICS MEMOPY THE OPITE AAI OPITHM The followingection explains the Presto F Pro
209. bits SUBC SUBCB BCMP 16x16 bit signed or unsigned multiplication MUL MULU 16 16 bit Sgnedor unsigned division Same on DIV DIVU d xt rs CMP CMPB 32 16 bit sgnedor unsigned division a Comparison of two words with post increment DIVL DIVLU by either 1 or 2 15 complement of a word or byte CMPM CMPI2 CPL CPLB a Comparison of two words with post decrement a 2 s complement negation of a word or byte by either 1 or 2 NEG NEGB CMPD1 CMPD2 1 8 6 Instruction Set Overview 6 1 5 Shift and Rotate Instructions a Shifting right of a word SHR a Shifting left of a word SHL a Rotating right of a word ROR a Rotating left of a word ROL a Arithmetic shifting right of a word sign bit shifting ASHR 6 1 6 Prioritize Instruction a Determination of the number of shift cycles re quired to normalize a word operand floating point support PRIOR 6 1 7 Data Movement Instructions a Standard data movement of a word or byte MOV MOVB a Data movement of a byte to a word location With either sign or zero byte extension MOVBS MOVBZ 6 1 8 System Stack Instructions a Pushing of a word onto the system stack PUSH Poppirg of a word from the system stack POP a Saving of a word on the system stack and then updating the old word with a new value pro vided for register bank switching SCXT 6 1 9 Jump and Call Instructions with a post inversion of the tested bitin ca
210. byte high byte 16 bitimmediate constant data16 low byte high byte A 1 8 Noupep Byteo Specifies the size of an instruction in bytes All ST10x166 instructions consist of either 2 or 4 bytes Regardingthe instruction size all instruc tions can be classified as either single word or dou ble word instructions 2 XINT AEINZTPYXTION AEXXPIIITION The following section contains a detailled descrip tion of each single instruction of the ST10x166 in alphabetical order S amp S THOMSON A Ivotpuxuov Let Ivteyep AAA onl 2 OPERATION 1 1 op2 DATATYPES WORD Performs a 2 s complement binary addition of the source operand specified by op2 and the destination operand specified by op1 The sum is then stored in op1 FLAGS E 2 V E Setifthe value of op2 representsthe lowest possible negative number Cleared oth erwise Used to signal the end of a table 2 Set if result equals zero Cleared otherwise V Set if an arithmetic overflow occurred i e the result can not be represented in the specified data type Cleared otherwise C Setifa carry is generated from the most significant bit of the specified data type Cleared otherwise Setif the most significant bit of the result is set Cleared otherwise INSTRUCTION FORMAT BXO Taoxtivy Mvepnovur Mven ovi Onepav o Byteo ADD ADD Rw Rwm 00 nm 2 ADD AD
211. cessor communication and it is selected by programming the mode selection field SOM or S1M to 101b The data frame which will be transmitted includes the lower 9 bits of the transmit buffer reg ister 56 64 The operationin this mode is basically the same as in the 9 bit data mode However on reception if the 9th data bit received is a 0 the received data are not transferred into the receive buffer registers SORBUF S1RBUF and no receive interrupt re quest will be generated A way to use this feature in multiprocessor systems is as follows When the master processor wants to transmit a block of data to one of several slaves it first sends out an address byte which identifies the target slave An address byte differs from a data byte in that the additional 9th bit is a 1 for an address byte and a 0 fora data byte Operating in the 8 bit data wake up bit mode no slave will be interrupted by a data byte An address byte however will inter rupt all slaves so that each slave can examine the 8 LSBs of the received character and see if itis be ing addressed The addressed slave will switch its operating mode to the 9 bit data mode e g by clearing bit SxM 0 see table 8 18 and prepare to receive the data bytes that will be coming The slaves that were not being addressed remain in the 8 bit data wake up bit mode ignoring the incom ing data bytes 8 4 1 1 5 8 Bit Data Parity Bit Mode This mode i
212. cient addressing modes for high code density a Enhanced boolean bit manipulation with direct addressability of 4Kbits for peripheral control and user defined flags a Hardware traps to identify exception conditions during runtime Integrated On chip Memory Kbyte internal RAM a 32Kbytes internal ROM ST10166 a 32Kbytes internal FLASH memory ST10F166 External Memory Expansion Interface Supports 3 different bus configurations plus seg mentation capability 16 Priority Level Interrupt System 32 interrupt sources with separate interrupt vec tors 300 500ns typical maximum interrupt latency in case of internal program execution 8 Channel Peripheral Event Controller PEC Interrupt driven single cycle data transfer Transfer count option CPU interrupt generation after a programmable number of PEC transfers a Eliminates overhead of saving and restoring sys tem state for interrupt requests Intelligent Peripheral Subsystems 10 Channel 10 bit A D Converter 9 75us conversion time auto scan modes 16 Channel Capture Compare Unit with 2 pendent time basesvery flexible PWM unit event recording unit with 5 different operating modes includestwo 16 bit timers counters with 400ns maximum resolution 2 Multifunctional General Purpose Timer Units GPT1 three 16 bittimers counters 400ns maxi mum resolution GPT2 two 16 bit timers counters 200ns maxi mum resolution 2 Serial Channels USART wi
213. ck selection and status flags for error identifi cation Serial data transmission or reception is only possi ble when the Baud Rate Generator Run Bit SOR or S1R forthe respective channel is set to 1 The in dividual operating mode for each channel is deter mined by the mode control fields SOM and S1M in registers SOCON and S1CON as shown in Table 8 18 These fields may not be programmed to one of the reserved combinations otherwise unpre dictable results may occur A transmission will be performed by writing the data to be transmitted into the associated Transmit Buffer register SOTBUF or S1TBUF In general any instruction or PEC data transfer operation which uses these registers as destination will initi ate a transmission Note that SOTBUF and S1TBUF are non bit addressable WRITE ONLY registers and that only the number of data bits which is determined by the selected operating mode will actually be transmitted This means that the bits written to positions 9 through 15 of regis ters SOTBUF and S1TBUF are always insignifi 52 64 cant After a transmission has been completed the transmit buffer registers are cleared to 0000h Data reception is enabled by the Receiver Enable Bits SOREN and S1REN respectively After recep tion of a character has been completed the re ceived data and if provided by the selected operating mode the received parity bit can be read from the Receive Buffer registers SORBUF or S1RBUF of
214. cle Time wait states in increments of half a ma Note that internal memory access time are not ex chine cycle within a range from 0 to 15 default af tended by external waitstates ter reset The Memory Cycle Time wait states can Examples tables and formulas showing the calcu be configured via software by modifying the MCTC lation ofthe user selectable bus characteristicscanfield of the SYSCON register as shown in table be found in thappendixsection C 9 4 One Memory Cycle Time Wait State requires half a machine cycle 50ns ad c 40MHz By means of the Memory Cycle Time Wait States the Memory Cycle Time can be variedas follows The ST10x166 allows the user to adjust the con troller s Memory Access Cycle Time to the Memory MultiplexecBus Modes Cycle Time of the external memory being used 150ns 900ns at sc 40 2 The Memory Cycle Time is the totahte required Non Multiplexed Bus Mode to perform a memory access It represents the pe riod of time from the moment when the controller 100ns 850ns at sc 40MHz puts an address on the bus for the first time untilThese programmable Memory Cycle Time wait the nextexternal memory access can be started at states can be specified for all of the external bus the earliest As shown in figure 9 10 the Memory configuration modes Cycle Time determines how fast the memory can be accessedin general 9 8 1 Programmable Memory Cycle Time 9 8 2 Programmable Memory Tri State Time Tab
215. cluding generation of the receive interrupt request and in case of er rors generation of the error interrupt request and setting ofthe error status flags which are described 157 SGS THOMSON in the following Reception then stops for the af fected channel and further start bits at the receive data input pin will be ignored In order to use pin RXDO P3 11 or RXD1 P3 9 as receive data input the corresponding direction control bit DP3 11 or DP3 9 must be set to 0 Hardware Error Detection Capabilities To improve the safety of asynchronous data ex change the serial channels of the ST10x166 pro vide selectable hardware error detection capabilities For each channel three error status flags the channel s control register SOCON or S1CON indicate whether an error has been de tected during reception Upon completion of a re ception the error interrupt request flag SOEIR or S1EIR will be set simultaneously with the receive interrupt request flag SORIR or S1RIR if one or more of the following conditions are met If the framing error detection enable bit SOFEN or S1FEN is set and any of the expected stop bits is not high the framing error flag SOFE or S1FE is set indicating that the error interrupt request is due to a framing error If the parity error detection enable bit SOPEN or S1PEN is set in the modes where a parity bit is received and the parity check on the re ceived data bits proves false the parity err
216. controllepmripheralgo Check theREADY line and delay the memory ac determine the duration of an external memory ac C SS depending on the state of tlIEADY line cess Data Ready function ignabledby set Warning If the Data Ready function is enabled ting the RDYEN bit to 1 In this case port pin the READY input pin must be activated for every P3 14 takes on its alternate function as active low external memory access Otherwise the system READY input pin An active low signal on the would be halted until a reset occurs No time out READY input pin signifies that data sailable protection other than a Watchdog Timer overflow is and must be latched by the on chip External Bus provided for that case Controller Note that itis the user amp amp ponsibilt order to allow one to interface to a variety of pe cueing thie freto Duo pin to input be ripherals support for both asynchronous and syn chronous modes of operation is provided If the When the Data Ready function is enabled and bits Data Ready function is enabled bit 3 in the SY 0 to2 of SYSCON register are cleared the external SCON register the MSB of the MCTC bit field de bus timing is only determined by tHEADY pin termines whether thRREADY input pin is to be the MTTC bit the RWDC bit and by the selected used in asynchronous or sghronousnode external bus mode If 1 to 7 wait states are pro _ 4 DEADY grammed in bits 0 to 2 of the MCTC field the CPU f
217. cribed in detail in section 8 2 1 2 3 and 8 2 1 2 4 about theauxiliay timers Table 8 7 GPT1 Timer Input Frequencies Resolution and Periods Timer Input Selection 21 000b 001b 010b 011b 100b 101b 110b 111b fosc 40MHz sme eme mme zone 15 24 64 565 50 8 Peripherals If T3M 0 0 the timer isenabled when T3IN T3R The timer will only run if T3R 1 and the gate shows a low level A high level at this pin stops theis active it will stop if either T3Rz 0 or the gate is timer If T3M 0 1 pin TSIN must havea high level in active Note that a transition of the gate signal at in order to enable therher to run In addition the T3IN does not cause an interrupt request timer can be turned on or off by software using bit Figure 8 17 Block Diagram of Core Timer T3 in Timer Mode Interrupt Request vROO1641 Interrupt Request VROA1641 57 S6S THOMSON 20984 e MIGROELECTRONICS 8 Peripherals 8 2 1 1 3 Counter Mode For counter Rau pin Le must be E ing figured as input by setting direction control bit Counter mode is selected for T3 by programmin 222 bit field T3M in register to 1b counter DP3 6 to 0 The maximum input frequency which mode timer T3 is clocked by a transition at the ex 5 allowed incounter mode is fosc 16 1 25MHz at ternal input pin
218. cted N Alwayscleared INSTRUCTION FORMAT BXO Taoxtivy Mvenoviy Mvenoviy Onepav o Byteo MOVBZ MOVBZ Rom CO mn 2 MOVBZ MOVBZ reg mem C2 RR MM MM 4 MOVBZ MOVBZ mem reg C5 RR MM MM 4 54 84 S amp S THOMSON A Ivotpuxuov 1 onl 2 OPERATION MD lt op1 x op2 DATA TYPES WORD Performs a 16 bit by 16 bit signed multiplication using the two words specified by oper ands op1 and op2 respectively The signed 32 bit result is placed in the MD register FLAGS E 2 V E Always cleared Set if result equals zero Cleared otherwise This bit is set if the result cannot be represented in a word data type Cleared other wise C Always cleared Setif the most significant bit of the result is set Cleared otherwise N INSTRUCTION FORMAT BXO Taoxtvy Mvepnovtux Mvenuoviy Onepav o Byteo MUL MUL Ruh RWm 0B nm 2 57 S65 THOMSON gt MICROELECTRONICS A Ivotpux tiov Let MYAY MYAY Yvovyve MoXTUtAUX OctLOV MYAY 2 OPERATION MD lt op1 x op2 DATATYPES WORD Performs 16 bit by 16 b nsignedmultiplication using the two words specified by oper ands op1 and op2 respectively The ugsed32 bit result is placed in the MD register FLAGS E 2 V E Always cleared Set if result equals zero Cleared otherwise
219. cted timer resolution All further increments occurstops exactly after the time defined by the timer resolu wren is programmed to run in counter mode tion When both timers to be incremented orre TOM 417 pit field TOl is used to select the count loaded atthe same time TO is always servicedone source and transition which should cause a count state before T1 trigger for TO Table 8 2 shows the possible selec tions for the counter mode of timers TO and T1 8 1 1 2 COUNTER MODE In order to use pin P3 0 TOIN as external count in Counter mode is selected for timer TO or T1 by set Put pin for TO P3 0 must be configured as input ting theappropria mode selection bit TOM amp the corregondingdirection control bit DP3 0 T1M in register TO1CON to 1 Both timers can in register DP3 must be set to 0 If P3 0 TOIN is operate in counter mode by counting the over COnfigured as output timer may be clocked by flows underflows of timer 6 in block GPT2 see Modifying port data register bit P3 0 through soft section 8 2 2 for details on GPT2 In addition Ware e g fortesting purposes timer TO offers thecapabili of being clocked by maximum external input frequency to TO in external events Either a positive a negative or counter mode isdsc 16 1 25MHz at 40MHz both a positive and a negative transition at pin fosc To ensure that a signal transition is properly TOIN alternate input function of port
220. ction Peripheral Timing ality and programming of the peripherals incorpo rated in the ST10x166 Each of thgeripheralnits is discussed in a separate section the CAPCOM unit in section 8 1 the General Purpose Timers GPT in section 8 2 the A D Converter in section 8 3 the Serial Channelsin section 8 4 and the Watchdog Timer in section 8 5 Peripheral Interfaces The peripheralsjenerallyhave two different types of interfaces an interface to the CPU and an inter face to external hardware Communication between CPU anplripheals is performed through Special Function Registers SFRs and interrupts The SFRs serve as con trol status and data registers for tlperipherals Interrupt requests are generated by the peripher als based on specific events e g operation com plete error which occur during their operation For interfacing with external hardware specific pins of ports P2 P3 or P5 are used when an input or output function has been selected for a periph eral During this time the port pins are controlled by the peripheral when used as outputs or by the external hardware which controls tperipheral when used as inputs This ised the alternate input or output function of a port pin in contras to its function as a general purpose I O pin Each port consists of a port data register and a di rection control register except for port 5 which is an input only port The name Px x 0 5 of a port data regi
221. ctors to be programmed from exter FLASH memory can not be performed during an nal memory while retaining the common routineserase or programming operation on the FLASH and constants programmed into the FLASH mem memory Therefore thappropriad routines must ory be executed from internal RAM or external mem For erase or program updating the FLASH mem ory outside of the FLASH memory address range ory isorganisedinto 4 banks 12K 12K 6K and 2K each of which may bindependentlgrased Figure 4 1 Flash Memory Architecture HIGH VOLTAGE MANAGEMENT 32Bits ADDRESS BIDIRECTIONAL DECODER INTERFACE MATRIX READ WRITE FLASH CIRCUIT TIMER PROTECTION 1 8 4 Flash Memory FLASH MODES This section describes the differents modes used with the FLASH memory and is detailed in the fol lowing sections Normal mode This mode is the standard mode of the FLASH memory In this operation mode the FLASH mem ory works exactly as the 32K bytes ROM of the ST10166 with the same timing and functionality Write mode As it is not possible to fetch instructions from and write to the FLASH memory at the same time a Write mode has been defined In this mode FLASH memory accesses can be made only with indirect addressing modes and FCR register is accessed with direct access modes In Write mode all programming and erase opera tions on the FLASH memory are contledby soft ware with the Flash Control Register FCR
222. d Fetch Code 3rd Read Data the se EL quence of instructions processed by the CPU may must not be an instruction usinga GPR diverge from the sequence of the cesponding 2 MOV RO datax n write to GPR 0 in the new context external memory accesses performed by the EBC Int a Timing s already described instruction gliping re uces the average instruction processing time in a a Data Page Pointer Updating An instruction which calculates a physical operandy address via a particular DPPn n 0 to 3 registeris Wide scale from four to one machine cycles How mostly not capable of using a new DPPn register value which is to be updated by an immediately pre ever there are some rare cases where a particular ceding instruction Thus if one surely wants the be or by 7 DPPn register value to be used one must put at least one instruction between a DPPn changing in one machine cycle Although tadmonakime struction and a subsequent instruction which implickePresents only ofthe total program exe itl DPPn vi lona or indirect add t cution time it might be of interest to avoid these y uses Y Aog ect addressing pibeline caused time delays in time critical pro mode as shown in the following example gram modules In wise RR 56 4 via DPPO Besides a general execution time description sec tion 5 2 provides some hints how can optimize nei time critical pro
223. d as receive data input by setting DP3 1 1 0 or DP3 9 0 Once areceptionis in progress on a serial channel resetting its receiver enable bit SOREN or S1REN to 0 by software has no effect Writing to its trans mit buffer register while a reception is in progress has no effect on reception nor will it ever start a transmission 58 64 In synchronous operation the low byte of the re ceive buffer register represents the received data while the high byte is always zero after synchro nous reception If a previously received byte has not been read out of the receive buffer register at the time reception of the next byte is complete both the error interrupt request flag SOEIR or S1EIR and the overrun error status flag SOOE or S1OE will be set provided the overrun check has been enabled by bit SOOEN or S1OEN 8 4 1 2 3 Loop backMode For testing purposes a special loop back mode is provided which allows testing of each serial chan nel without using the alternate functions of the port pins associated with this channel While in loop back mode instead of receiving data from the RX DO or RXD1 pin the data which are transmitted are simultaneously clocked into the receive shift regis ter A transmission in loop back mode is initiated for channel ASCO by a write operation to SOTBUF when SOLB 1 SOREN 1 and SOR 1 and for ASC1 by writing to STTBUF with S1LB 1 S1REN 1 and S1R 1 This
224. d operation The contents of the register specified by the first operand op1 are pushed onto the stack That register is thetoadedwith the value specified by the second operand op2 FLAGS E 2 V C N E Not affected 2 Not affected V Not affected C Notaffected N Notaffected INSTRUCTION FORMAT BXO Taoxtivy Mvenoviux Onepav o SCXT SCXT reg dat s C6 RR SCXT SCXT reg mem D6 RR MM MM Ey SGS THOMSON o MICROELECTRGNICS Byteo 73 84 A Ivotpux tiov Let YHA XL HA YHA onl 2 OPERATION count op2 0 DO WHILE count 0 C opts 1 Optn 1 n 1 to 15 Opto 0 count 1 END WHILE DATATYPES WORD Shifts the deshation wod operand op1 left by as many times as specified by the source operand op2 The least significant bits of the result are filled with zeros accordingly The MSB is shifted into the Carry Only shift values between 0 and 15 areallowed When using a GPR as the count control only the least significant 4 bits are used FLAGS E 2 V E Always cleared Z Set if result equals zero Cleared otherwise V Always cleared C The Carry flag is set according to the last MSB shifted out of op1 Cleared for a shift count of zero N Setif the most significant bit of the result is set Cleared otherwise INSTRUCTION FORMAT BXO Taoxtivy Mveuovy Mveuovty Onepav o Byteo SHL SHL Rmh RWm 4C nm 2 SHL SH
225. d to cause an interruptor PEC tive external transition at pins T2IN P3 7 or service request The edge selection is performed T4IN P3 5 respectively When 21 or T4l are pro the control register of tlperipheraldevice as grammed to X10b then a negative external transi sociated with the respective port pin The periph tion will set the correendingrequest flag When eral must be programmed to a specific operating 21 or T4l are programmed to X11b both a positive mode to allow generation of an interrupt by the ex and anegative transition will set the request flag In ternal signal The priority of the interrupt request isall three cases the contents of the core timer T3 determined by the interrupt control register of thewill be captured into theuxiliaryiimer registers T2 respective peripheral interrupt source and the in or based on the transition at pins T2IN or TAIN terrupt vector of this source will be used in case anWhen the interrupt enable bits T2IE or T4IE interrupt is adkowledged set a PEC request or an interrupt request for vec In order to use any of the pins listed in Table 7 5 as tor T2INT or T4INT will be generated For further external interrupt inputs its direction control bifletails on the GPT1 block see section 8 2 DPx y in the comspondingport direction control Pin CAPIN P3 2 differs slightly from the other pins register DPx must be 0 described before in that it can be used as external When port pins CCxIO P2 x
226. data in the bot 7 6 5 4 3 2 1 0 tom of the stack may have been overwritten by the 2 srovcoiuto o status information stacked upon servicing the stack overflow trap b15 to b11 1 Bits tied to 1 by hardware This restricts contents The stack overflow trap could also be used for to values from F800h to FFFEh automatic system stack flushing when the system stack is used as a Stack Cache for an external b10 to b1 STKOV Stack Overflow Pointer Reg user stack In this case the STKOV register should ster be initialized to a value which represents the de Modifiableportion of the STKOV register sired lowest Top of Stack address plus 12 accord po 0 ing to the selected maximum stack size This Bit tied to 0 by hardware because only even considers the worst case that will occur when STKOV contents are compared against the SP stack overflow condition is detected just during en register 2426 n SGS THOMSON MICROELECTRONICS 5 Central Processing Unit 5 3 12 MDH Multiply Divide Register High 5 3 13 MDL Multiply Divide Register Low Portion Portion This register is implicitly used by the CPU when itThis register is implicitly used by the CPU when it performs a multiplication or a division After a mul performs a multiplication or a division After a mul tiplication this non bit addressable register repre tiplication this non bit addressable register repre sents the high order 16 bits of the 32
227. ding fwe R1 fee R1 ckctlO R1 FCRCKC TLO bit ckctl1 R1 FCRCKC TL1 bit wdww s FCR WDWW bit bed FCR BEO bit be1 FCR BE1 bit FCRFWE bit FCR FEE bit busy fcvpp vppriv FCR BUSY bit FCRFCVPP bit FCR VPP RIV bit SGS THOMSON MICROELECTRONICS 11 19 MEMOPY ERASEROUTINE sure of bank 1 t his routi nea ssumes that the bank was prev iousl y pr ogrammed to 0 000h beforee rasur e kkkkk kkkkk eek kkkkk f eras e ALL WORSIN BANK 1 kkk INITI AL CON DITIONS ekdekek kkkkk kkkkk kk kkk kkk HAVETOBE PROGRMMEBT ZERO WITHTHE PRE STO F PROGRAMRITE A LGORITHM dokekekeke kkkkk kkkkk REG ISTERS IN ITIAL IZATI ON mov mov mov mov mov mov mov mov Ipcnt fcrval unlock val10u val4u ALLO ALLO dokekekeke UNLOCK WAIT1 WAIT4 wat_cn t AL LO allt ALL1 0 fl scan BLK_ START kkkkk kkkkk kkkkk kkkkk kkkkk reseta 100 loop cou nter reset FCR d ata value loadun lock data load10 usi oop data load4 us loop data resetw ait loop counter set R2 to FFFF load fi rst bank address UNL OCK SEQUBCE FOR ENTERNG INTHE WRITE MODE mov mov FCR SET UP 12 19 bset bset belr bset belr bset belr bset mov FCR unlock cc UG FOR ERASE fwe fee ck ctlO ck ctl1 wdww be1 fw mset FC
228. disablinginterrupt sources see section COUNT PEC Transfer Counter Field 7 2 3 1 This 8 bit field is used to specify the number of data transfers to be performed by the respective PEC 7 2 2 2 SOURCE AND DESTINATION POINTERS channel Either an unlimited or a limited number of _ transfers 0 through 254 can be programmed The Fight pairs of word wide pointers are associated Transfer Counter field operates as an 8 bit down With the 8 PEC Service Channels Each pair is di counter Values from 0 through FFh can be speci rectly assigned to one specific PEC channel Each fied in this field where 0 and FFh have a special Of these pairs of pointers consists of a Source meaning Pointer which containshe source address of the PEC data transfer and a Destination Pointer If the COUNT value is between FEh and 2atthe which containsthe respective destination address time the PEC service request is generated the value is decremented after each PEC data trans These pointers share the top 16 word locations fer Also the Interrupt Request flag of the source byte addresses FDEOh through FDFFh in the in which generated the PEC service request is ternal RAM If no PEC service is required for a spe cleared cific PEC channel the locations of its pointers can be used for general data storage If the COUNT value equals 1 at the time the PEC Note If dd feri dt ifi service request is generated the value is decre Note If
229. displacement op2 The displacement is a two s complement number which is sign extended and counts the relative distance in words The value of the IP used in the target address calculation is the address of the instruction fol lowing the JNB instruction If the specified bit is set the in amp irufdllowing the JNB struction is executed next instruction FLAGS E 2 V Not affected Z Not affected V Not affected Not affected N Not affected INSTRUCTION FORMAT BXO Taoxivy Mvenoviy Mvenoviy Onepav o Byteo JNB JNB bitaddy g rel 9A QQrr q0 4 505 50 49 84 eee A Ivotpux tiov Let ONBX gt Peate VOUT 10 Bit XAEap avd Let But ONBX orl 2 OPERATION DATA TYPES IF op1 20 THEN 1 1 IP sign extend op2 ELSE 0p1 1 next instruction END IF BIT If the bit specified by op1 is clear program execution continues at the location of the in struction pointer IP plus the displaement op2 bit specified by is set allowing implementation of semaphore operations The displacement is a two s comple ment number which is sign extended and counts the relative distance in words The value of the IP used in the target address calculation is the address of the instrunilimuafg the JNBS instruction If the specified bit is set the instruailimwWinghe JNBS instruction is executed FLAGS E 2 V E Always cleared Z C
230. e request can be assigned to a specific priority Onceinstruction cycle only one source with the highest per instruction cycle all sources which requirepriority will be left with control of the interrupt sys PEC or interrupt processing will contend for servictem This source will then tsmabledfor servicing ing Every requesting source will try to exert its pri if the priority of the requestliggher than the cur ority on the interrupt system A special mechanismrent CPU priority in the PSW This arbitration called group priority has been implemented thatwhich occurs once every instruction cycle is called allows the specification of the order of service fora round of prioritization 4 24 S amp S THOMSON 7 Interrupt And Trap Functions 7 2 1 Interrupt System Register Description xxlC Interrupt processing is controllgbbballyby the Interrupt Control Register for Source xx PSW through a general interrupt enable bit IEN and the CPU priority field ILVL dlitionallythe 65 Value 0000h different interrupt sources are controlled individu 6 5 4 3 2 1 0 ally by their specific interrupt control registers xw xc wi Thus the acceptance of requests by the CPU is determined by both the individual interrupt XXIR Interrupt Request Flag registers and the PSW For PEC service addi 0 No interrupt request tional dedicated register and 2 pointers must 1
231. e IP and PSW and in segmentation mode also the CSP are pushed on the internal modal wore operanda Access Trap system stack and a jump is taken to the specified Instruction Access Trap vector location When segmentation sabled Illegal External Bus Access Trap and a trap is executed the CSP for the trap service ior routine is set to code segment 0 However the ende ion paren Share thersame trap prior CPU Priority field of the PSW is not modified and the trap service routine is executed on the priorityln order to allow trap service routine to identify level from which it was invoked Therefore the the kind of trap which caused the exception a bit service routine entered by the TRAP instruction addressable Special Function Register the Trap be interrupted by other traps or higher priorityFlag Register TFR is provided The c g ration interrupts No Interrupt Request flags are affected Of this register is shown next page by the TRAP instruction The interrupt service rou For each trap function a separate request flag is tine called by a TRAP instruction must be termi implemented When a hardware trap occurs the nated with a RETI return from interrupt instructioncorespondingequest flag in the TFR register is to ensure correct return set to 1 It must be reset by software in the trap service routine otherwise a new trap will be re quested after exiting the service routine Setting a 7 3 2
232. e are sepa ure 9 9 shows the timing sequence of a memory After the address has been stored externally and read and memory write access via a non multi removed fromlte bus again data are dven onto plexed bus 10 20 y SGS THOMSON MICROELECTRONICS 9 External Bus Interface Figure 9 9 Non Multiplexed External Bu Access Add SEGMENT P4 2 ALE gt 77 WR VROA 633 9 7 2 1 NON MULTIPLEXED BUS MEMORY READS 9 7 2 2 NON MULTIPLEXED BUS MEMORY WRITES A memory read access is initiated by the controllerA memory write access is initiated by the controller by placingan address on the address bus This ad by placing an address on the address bus This ad dress stays valid on the bus until the next memorydress stays valid on the bus until the next memory access cycle is started After a fixed period of time access cycle is started After a fixed period of time the active low memory read sign isapplied the controller drives its data onto the data bus and to the memory This enables the memory to drive applies the active low memory write sig MIR to data onto the data bus After a period of time which the memory This enables the memory to store the is determined by the access time of the memory data from the data bus onto the addressed loca data become valid on the data bus Then the con tion After a period of time which is determined by troller latches the valid data from the data bus and the access time of the memo
233. e buses are used for the sixteen least significant ory No external memory can be accessedas long address bits and the data word Thus addresses as the ST10x166 is in this mode However the sin and data do not have to be time multiplexed For gle chip mode can be left to enter any of tbdl w this mode Port 0 is used asan interface to the ex ing external bus configuration modes by simplyternal data bus and Port 1 is usedasan interface to reprogramming the System Configuration SY the external address bus As long as memory seg SCON register mentation is not disabled Port 4 is adeliially 16 18 Bit Address 8 Bit Data Multiplexed Bus used as an output for the two most significant bits i of the required 18 bit addresses This mode is provided for accesses to a byte or ganized external memory The eight least signifi 16 18 Address 8 Bit Data Non Multiplexed cant bits of the address and the data byte are US time muliplexed onthe lower portion of the word This mode is provided for accesses to a byte or wide external bus For this mode Port 0 is used as ganized exernal memory However two separate interface to the mltiplexedexternal address data buses are used for the eight least significant bits of bus As long as memory segmentation is not dis the address and the data byte For this mode Port abled Port 4 is additionally used as an output for 0 is used as an interface to the 8 bit external data the two most significant bits of t
234. e interrupt vector jump table The second and branch instructions in general and whichiyne the PEC interrupt processing steals just one hardware provisions have been made to speed the machine cycle from the current CPU activity to per execution of jump instructions in particular forma single data transfer via the on chip Periph With reference to instructiopipelinng most eral Event Controller PEC System errors ST10x166 instructions be regarded amp eing detected during program execution so called executed during one machine cycle 100ns at hardware traps or an external non maskable in 40MHz oscillator frequency Section 5 2 de terrupt are also processed as standard interrupts scribes the general instruction timimpluding with a very high priority For more information standard and exceptional timing about interrupts PEC data transfers ahdrdware While internal memory accesses are normally per see chapter 7 formed by the CPU itself all of the external mem In contrast to other on chjferipheals there is ory accesses are performed by a particular on chip closer conjunction between the Watchdog Timer External Bus Controller EBC which is automat and the CPU If enabled the Watchdog Timer ex ically invoked by the CPU whenever a code or data pects to be serviced by the CPU within a program addressbelongsto the external memory space If mable period of time otherwise it will reset the possible the CPU continues operati
235. e intervention 10 automatically store the conversion results into 5 table in memory for later evaluation without requir With its maximum resolution of 200ns ing the overhead of entering and exiting interrupt fosc 40MHz the GPT2 module provides pre for each data 9 cise event control and time measurement It in e MIGROELECTREMIGS 2 System Description 2 8 SERIAL CHANNELS When the software has beedesignedto service the Watchdog Timer before it overflows the Serial communication with other microcontrollersWatchdog Timer times out if the program does not processors terminals or external com progress properly due to hardware or software re ponents is provided by two serial interfaces withlated failures When the Watchdog Timer over identical functionality Seri amp lhannel 0 ASCO flows it generates an inteahhardware eset and and SerialChannel1 ASC1 pulls thdRSTOUT pin low in order to allow external Both channels suppoftull duplexasynchronous hardware components to reset communication up to 625Kbaud and half duplex The Watchdog Timer of the ST10x166 is a 16 bit synchronousommunication up to 2 5 Mbaud timer which can either be clocked witisd 4 or Two dedicated baud rate generators allow to set fosc 256 The high byte of the Watchdog Timer up all standard baud rates without oscillator tuning can be set toa prespecified reload value in For transmission reception and
236. e possibilitysegmentation mode also the CSP are pushed on to bypass the interrupt system s prioritization procthe system stack The CPU priority field of the ess in cases where immediate system reaction is PSW ofthe trap service routine is set to the highest required Trap functions are not maskable and al possible priority level i e level 15 thdisabling ways have priority over interrupt requests on anyall interrupts The CSP is set to code segment zero priority level if segmentation is enabled The trap service rou tine must be terminated with the RETI instruction 7 3 1 Software Traps The eight hardware trap functions of thetS X166 ME are divided into two classes class A and B The The TRAP instruction is used to cause a software traps of class A are the external Non Maskable In call to an interrupt service routine Associated withterrupt the Stack Overflow and the Stack the trap instruction is a trap number that can be Ungerflow trap All of these traps have the same specified in the operand field of the instruction trap priority but each of them has a separate vec This trap number determines which vector locationtor address in the memory space from Oh through 1FCh will be T branched to see also table 7 2 section 7 1 The traps of class B are thtollowing Executing a TRAP instruction causes a similar et Undefined Opcode Trap fect as if an interrupt at the same vector had oc Protection Fault Trap cured Th
237. e set of development tools is also avail ES able including a 16 Priority Level Interrupt System _ C Compiler d A D Converter with 9 75us _ Assembler a 16 Channel Capture Compare Unit a 2 Multi Functional General Purpose Timer Units 2 Serial Channels USARTs a Programmable Watchdog Timer a 76 General Purpose I O Lines a Temperature Range 0 to 70 C 40 to 85 C 40 to 110 m 1 2 micron multifunctional CMOS technology 100 Pin Metric Plastic Quad Flat Pack PQFP Rectangular Package a FLASH MEMORY PROTECTION OPTIONAL January 1992 1 17 This is advance information from SGS THOMSON Details subjectto change without notice ST10F166 Figure 1 ST10F166 Pin Configuration VROO1549 Table 1 PINOUT Description ST10F166 P0 3 P0 4 P0 5 P0 6 P0 7 VSS VCC P0 8 P0 9 P0 10 11 P0 12 P0 13 P0 14 P0 15 P4 0 P4 1 VCC XTAL2 XTAL1 VSS BUSACT EBC1 VPP EBCO RSTOUT NMI P1 0 2 17 S amp S THOMSON C ABSOLUTE MAXIMUM RATINGS Ambient temperature under bias TA 0 to 70 C Storage temperature 6510 125 C Supply Voltage Vcc 6 5V Input Voltage Vin 3 0 V for pulse width less than 15ns 0 5 to VCC 0 5 V Vpp Voltage 0 6 to 13 5V DC CHARACTERISTICS Ta 20 to 70 C 25V 10 Vss 20V ST10F166 Note Stresses above those listed under Absolute Maximum Rat ings may cause permanent damage to the dev
238. e single instruction processing times Tin of the considered instructions plus an offset value of 6 state times which considers the solitary filling of thpipelineas follows Tii Tio Tin 6x States This section is arranged in subsections of which theThe time Tn which a single instruction takes to be first one defines the subsequently used time units the second contains an overview about the mini mum standard state times of the ST10x166 in structions and the third describes the exceptionsr from that standard timing 5 2 1 Time Unit Definitions The followingiime units are used to describe the instruction processing times fosc Oscillator frequency may baariable from 2MHz to 40MHz State One state time is specified by two times an oscillator period Henceforth one State is used as the basic time unit be cause it represents the shortest period of time which has to beansideredfor in struction timing evaluations SGS THOMSON MICROELECTRONICS processed consists of a minimum numbefn plus an additionalnumber Tada of instruction state times and or ALE Cycle Times as follows Timin 5 2 2 Minimum State Times The followingable 5 1 shows the minimum num ber of state times required to process a k166 instruction fetched from the internal ROM The minimum number of state times for in structions fetched from the internal RAM or of ALE Cycle Times for inst
239. eared otherwise INSTRUCTION FORMAT BXO Taoxtivy Mvenoviy Mvenoviy Byteo DIVLU DIVLU Rw 7B nn 2 38 84 S amp S THOMSON A Ivotpuxuov AlcY AlcY 16 16 Amorov AlcY orl OPERATION DATA TYPES FLAGS MDL MDL op1 MDL mod op1 WORD Performs anunsignedi6 bit by 16 bit division of the low order word stored the MD reg ister by the source word operand op1 Timesignedquotient is then stored in the low order word ofthe MD register MDL and the remainder is stored in the high order word in the MD register MDH E 2 V EEE TERED E Always cleared Z Set if result equals zero Cleared otherwise Set if an arithmetic overflow occurred Overflow occurs when the result can not be represented in a word data type or if the divisor op1 was 0 Cleared otherwise C Always cleared Setif the most significant bit of the result is set Cleared otherwise lt INSTRUCTION FORMAT Mvenoviy DIVU BXO Taoxivy Mvenuovy Onepav o Byteo DIVU Rwn 5B nn 2 57 S65 THOMSON o MICROELECTRGNICS A Ivotpux tiov Let EINIT Evo IvvttoQaGoctov EINIT OPERATION END of INITIALIZATION This instrution is used to signdhe end of the initialization portion of a program After a reset the reset output pin RSTOUT is pulled low It remains low until the EINIT instruction has been ex
240. ecuted at which time it goes high This enables the program to signal the ex ternal circuitry that it has successfinltializedhe microcontroller After the EINIT instruc tion has been executed exertion of the Disabl amp Vatchdog Timer instruction DISWDT has no effect To insure that this instruction is not accidentally executed itis implemented as a protected instruction FLAGS E 2 V C N E Not affected 2 Not affected V Not affected C Notaffected N Notaffected INSTRUCTION FORMAT BXO Taoxtivy Mvenoviy Mvenoviy Onepav o Byteo EINIT EINIT B5 4A B5 B5 4 40 84 S amp S THOMSON A Ivotpuyuov Let IAAE IAAE 164 Mode IAAE OPERATION Enter Idle Mode This instruction causes the part to enter the idle mode In this mode the CPblsred down while theeripheralsemain unning It remains powered down untiberipherain terrupt or external interrupt occurs To insure that this instruction is not accidentally exe cuted itis implemented as a protected instruction FLAGS E Z V C N E Not affected Z Not affected V Not affected Not affected N Not affected INSTRUCTION FORMAT BXO Taoxtivy Mvenoviy Mvenoviy Onepav o Byteo IDLE IDLE 87 7887 87 4 565 0 41 84 are 27 70 77 77 A Ivotpux tiov Let DB OB Pe ate SOUT i Let OT 2 OPERATION DATA TYPES IF op1 1 THEN sign extend op2 ELSE END IF
241. ed SFR Note also that non implemented reserved SFR bits can not be modi fied and will always supply a read value of 0 8 26 SGS THOMSON MICROELECTRONICS 5 Central Processing Unit 5 3 1 SYSCON System Configuration 5 3 1 2 EXTERNAL BUS TIMING CONTROL VIA Register MCTC MTTC RWDC This bit addressable register provides general sys The MCTC bit field and the MTTC and RWDC bits tem configuration and control functions There arein the SYSCON register are provided for varying five different reset values for the SYSCON register external bus timing parameters as follows The because the BTYP bitfield and the BUSACT bit are Memory Cycle Time can be extended within a initialied during resetlependenton the state of range from 0 to 15 state times by means of the the BUSACT EBCO and EBC1 input pins MCTC bit field 1 state time 2 x By means of the MTTC bit the Memory Tri State time can be extended by either 1 or additionabtate time The 5 3 1 1 INTERNAL ROM OR FLASH MEMORY EX Memory Tri State Time iadditionallyxtended by TERNAL MEMORY ACCESS MODE SELECTION one state time whenever a multiplexed external A two bit field BTYP and BUSACT reflect the se bus configuration is selected The RWDC bit allows lected external bus configuration as shown ta programming a time delay of either 0 or 0 5 state ble 5 2 times between the falling edges of the ALE and the Read Write signals This read write delay does not BTYP bit
242. ed by the following instructions on the modularity loops and context switching In manyeT40x166 listed table 13 1 cases commonly used instruction sequences have been simplified whilgrovidinggreater flexi bility Thefollowingsections cover programming 13 1 2 Modification of System Flags features and implementations to fully utilize this inAll bit and word instructions can access the PSW struction set register Thus to set or clear PSW flags no CLEAR CARRY or ENABLE INTERRUPTS in 13 1 INSTRUCTIONS PROVIDED AS struction is required These functions are per SUBSETS OF INSTRUCTIONS formed using bit set or clear BSET BCLR instructions In many cases instructions found in other micro controllers are provided as subsets of more power ful Instructions In the ST10x166 This allows the Dal access same functionality to be providedtiledecreasing Byproviding Von Neumann memory architecture the hardware required and decreasimipcode and by providing hardware to detect access to in complexity In orderto aid assembly programming ternal RAM GPRs and SFRs special instructions these instructions familiar from other microcontrolare not required to load data pointers or explicitly lers can be built in macros Thelfowingsubsec load and store external data See chapter 6 for a tions describe methods of providing the function ofletailed description of data addressing modes these common instructions Table 13 1 Instruction Equivalents CLR Rn
243. egisters for the core timer Figure 8 16 SFRs and Port Pins Associated with the GPT1 Block Ports amp Direction Control Data Control Interrupt Alternate Functions Registers Registers Control lH i T21N P3 7 T3IN P3 6 T4IN P3 5 T3EUD P3 4 T3OUT P3 3 VROA1640 Port 3 Direction Control Register GPT1 Timer 3 Control Register S Data Reglster GPT1 Timer 4 Control Register GPT1 Timer 2 Register GPT1 Timer 3 Register GPT1 Timer 4 Register GPT1 Timer 2 Control Register GPT1 Timer 2 Interrupt control Register GPT1 Timer Interrupt Control Register GPT1 Timer 4 Interrupt Control Register In the following thindividuafeatures of each timer in block GPT1 will be discussed separately 22 64 SGS THOMSON 8 Peripherals 8 2 1 1 GPT1 CORE TIMER T3 Table 8 5 Core Timer T3 Mode Control The configuration of the core timer T3 is deter mined by its bit addressable control register T3CON which is showbelow Mode EARS GPT1 Core Timer T3 Control Register 1 o Gated Timer gate is active lov 15 14 13 12 11 10 9 8 Timer 3 Run Bit Rm tort oe rau 7 6 5 4 3 2 1 0 The timer can be started or stopped by software ruo rm m B through bit T3R Timer T3 Run Bit If T3R 0 the b15 tob11 b5 R Reserved timer stops Setting T3R to 1 will start the timer In gated timer mode the timer will only run if T3R 1 b10 T30TL Timer Output Toggle
244. eld and the BUSACT bit of the SYSCON register case accesses to addresses fromi08000h as follows through OF9FFh or in any segment other than E zero would be tried to be made externally Note SCONE EET however that external memory locations higher SYSCON 6 than OFFFFh cannot be accessed if the non seg SYSCON 10 BUSACT mented memory mode or the single chip mode is oH 22221 selected Thisalseppliesto the ST10F166 device CT pos and EBT input pin val S and its Flash memory For more details about the 5 coriespondingexternal bus configuration modes ST10x166 s memory organization see chapter 3 and the ports used as interface to the external ad dress and or data bus es Table 9 1 Initial External Bus Configuration During Reset Ports used for BUSACT EBC1 EBCO External Bus Configuration A17 A16 A15 A0 D15 DO Single Chip Mode No External Bus Reserved No External Bus Reserved No External Bus Reserved No External Bus 18 Bit Address 8 Bit Data Non Multiplexed PO low No Internal ROM 18 Bit Address 8 Bit Data Time Multiplexed PO low No Internal ROM 18 Bit Address 16 Bit Data Time multiplexed No Internal ROM 18 Bit Address 16 Bit Data Non Multiplexed No Internal ROM 2 20 SGS THOMSON MICROELECTRONICS 9 External Bus Interface As just mentioned the BUSACT bit and the BTYP SGTDIS bit in the SYSCON register is set to 1 I
245. electable by the user Processinga program from the internal RAM space is not as fast as execution from the internal ROM 1 State 22x1 fosc s forf osc variab le 50 ns for sc 40MHz ACT This ALE Address Latch Enable Cycle Time specifies the time required to per form one external memory access One ALE Cycle Time consists of either two for a non multiplexed external bus mode or three for a multiplexed external bus mode state times plus a number of state times which is determined by the number of wait states programmed in the MCTC Memory Cycle Time Control and MTTC Memory Tristate Time Control bit fields of the SYSCON register plus one state time if ALECTL1 bit of ADDRSEL1 register is set to 1 In the case of the non mitiplexedexter nal bus mode 1xACT 2 15 MCTC 1 MTTC ALECTL1 xStates 100ns 900ns for sc 40MHz In the case of the multiplexed external bus modes 1x ACT 23 15 MCTO 1 MTTC ALECTL1 x States 150ns 9501 40MHz The total time To whicha particular part of a pro area but it offers a lot of flexibility i e for end of linegram takes to be processed can be calculated by programming where a program could be loaded into the internal RAM via the chip s serial interface The following description allows evaluating the minimum and maximum program execution times This will be sufficient for most of the requirements the sum of th
246. elow holds the result of a conver sion The low order 10 bits ADDAT 9 0 contain the converted digital result while the upper four bits ADDAT 15 12 represent the number of the channel which was converted Register ADDAT is not bit addressable The data remains in ADDAT until itis overwritten by the data of the next conver sion 48 64 In all 4 conversion modes a conversion is started by setting bit ADST 1 This will also set the busy flag ADBSY The converter then selects and sam ples the input channel specified by the channel se lection field ADCH in register ADCON This will take 1 575us at 40MHz oscillator frequency The sampled level will then be held internally for the rest of the conversion which will require another 8 175us at 40 MHz When the conversion of this channel is complete the 10 bit result together with the number of the converted channel is transferred into the resultregister ADDAT and the interrupt re quest flag ADCIR will be set If a previous conver sion result was not read out of register ADDAT by the time a new conversion is complete then the A D overrun error interrupt request flag ADEIR will also be set The previous result in register ADDAT is lost because it is overwritten by the new value If bit ADST is reset and then set again while a con version is in progress this conversion will be aborted and the converter will start again When setting bit ADST a different conversion mode
247. emory paging and accesses be used for normal I O onto the General Brpose Registrs and the Sys BUSACT Bus Active Control Bit tom ove b9 BYTDIS Byte High EnableBHE pin control The accessmechanism for these SFRs inthe CPU core is identical to the access mechanism for BYTDIS BHE enabled other SFR Since all SFRs can simply be controlled BYTDIS 1 disabled can be used for by means of any instruction which is capable of ad normal I O dressing the SFR memory space a lot d xibili has been gained and the need to create a set of EPIS System Clock Output CLKOUT En system specific instructions was avoided Note oe XE however that there are user access restrictions for CLKEN 0 CLKOUT disabled pin can be used for normal l O tions SERS IO ensure properproc CLKEN 1 CLKOUT enabled pin used for sys The PSW SP and MDC registers can be modified n not only explicitly by the but also im 07 06 External Bus Configuration Control plicitly bythe CPU during mrmal instruction proc b5 MTTC Memory Tri state Time Control essing Note that any explicit programmer s write RWDC Read Write Delay Control request to an SFR supersedes a simamieous modification by hardware of the same register 03 02 01 00 MCTC Memory Cycle Time Con Note furthermore that any byte write operation to an SFR clears thenon addresed complementary byte within the specifi
248. emory space can be used for implementation The highest 32 bytes of the inter general code and data storage The internal SFR nal RAM addresses from OFDEOh to OFDFFh are space is provided for control data but not for codeprovided for the Peripheral EveQontrollexPEC storage source and destination pointers Three memory Spaces from to OFFDFh in the internal bad oe SFR area from OFDOOh to OFDFFh in the internal hvsical RAM area and the address space occupied by the organizational memory arsa currently selected register bank are basically pro vided for single bit accesses A particular use is provided for some memory ar _ eas asfollows Addresses fro 000hto000BFh Figure 3 3 gives an overview of the memory or in code segment zero are reserved for the hard 9anization of the ST10x166 For more details ware trap and interrupt vector jump table The ac about the different memory areas see the corre tive General Purpose Register Bank which is spondingsubsections in this chapter The princi selected by the Context Pointer CP Register Ples of the physical address generation are be situated anywhere in the internal RAMarea ad described in section 6 2 Addressing Modes dresses from to OFDFFh Word ad Chapter 9 is dedicated to the External Bus Control dresses from to OFBFEh the internal which is resonsiblefor all of the
249. enabled if SxLB 1 b13 SxBRS Baud Rate Selection Bit The current baud rate is multiplied by 2 3 if SxBRS 1 b12 tob11 R Reserved b10 SxOE Overrun Error Flag Set by hardware when an overrun error occurs and SxOEN 1 Must be reset by software b9 SxFE Framing Error Flag Set by hardware when a framing error occurs and SxFEN 1 Mustbe reset by software b8 SxPE Parity Error Flag Set by hardware when a parity error occurs and SxPEN 1 Must be reset by software b7 SxOEN Overrun Check Enable Bit SxOEN 0 Overrun Check Disabled SxOEN 1 Overrun Check Enabled b6 SxFEN Framing Check Enable Bit SxFEN 0 Framing Check Disabled SxFEN 1 Framing Check Enabled b5 SxPEN Parity Check Enable Bit SxPEN 0 Parity Check Disabled SxPEN 1 Parity Check Enabled b4 SxREN Receiver Enable Bit Used to Initiate Reception Reset by hardware af ter a byte in synchronous mode has been re ceived SxSTP Number of Stop Bits Selection SxSTP 0 One Stop Bit SxSTP 1 Two Stop Bits b2 tob0 SxM ASCx Mode Control see table 8 18 51 64 MIGRCELECTREMICS 8 Peripherals Table 8 18 Serial Channel Modes of Operation eee qp ow 8 bit data asynchronous operation 7 bit data parity bit asynchronous operation ELEC MEE Ad 9 bit data asynchronous operation OS do deem 7 che
250. er In other words by programming PEC block transfer Modifying the Interrupt Re 8 Source on priority level 15 ILVL 1111b PEC quest flag by software causes the same effects as channels through 4 can be selected By program if it had been set or cleared by hardware ming a source on priority level 14 ILVL 1110b sy SGS THOMSON 0 0 10 0 0 524 JI MICROELECTRGNICS 7 Interrupt And Trap Functions PEC channels 3 through 0 can be selected The These two bits are interpreted as the relative prior actual PEC channel number is then determined by of an interrupt service request within a group of the Group Priority field GLVL which is described insimultaneous requests from different sources on the followingparagraph Figure 7 1 shows the the same priority level For sources which are pro mapping of the ILVL and GLVL fields and their in grammed for PEC service in their ILVL fields the 2 terpretation during a round of prioritization bits of GLVL represent the 2 LSBs of the associ During the prioritization process the ILVL fields ofated PEC channel number See also figure 7 1 all interrupt requesting sources are compared to group priority field is particularly relevant for the current CPU priority level which is contained inresolving simultaneous interrupt requests from the ILVL field of the PSW An interrupt request of several sources on the same priority level Up to 4 higher priority than the current CPU priority can in sources can be
251. er value isadditionallyncremented by a data type dependent valued 1 for byte op erations 2 for word operations GPR Address GPR Address A optional step The table below gives an overview of the particular indirect addressing modes of the ST10x166 The specified indirect address pointer is automatically post incremented by either 1 for byte data operations or 2 for word data operations Rw The specified indirect address pointer is automatically predecremented by either 1 for byte data operations or 2 for word data operations ng Rw data 16 A 16 bit constant and the contents of the indirect address pointer are added before the 16 bit address is calculated 6 8 SGS THOMSON MICROELECTRONICS 6 Instruction Set Overview 6 2 5 Branch Target Addressing Modes Different addressing modes are provided to spec value A special mode is provided to address the ify the target address and segment of jump or call interrupt and trap jump vector table which is allo instructions Relative absolute and indirect modescated to the lowest portion of code segment 0 can be used to update the Instruction Pointer IP register while the Code Segment Pointer CSP register can be updated only with an absolute Table 6 5 Branch Target Addressing Modes Target Address Target Segment alid Address Range IP caddr I IP IP IP IP CP 2xrel 2x rel 1 2xRw IP 0000h 4xtrap
252. erefore Port 4 will always output 00b after reset ance state see chapter 10 for details about the When no memory accesses above 64K are to be internal port structure This ensures that the performed segmentation may Igdoballylisabled ST10x166 and external devices will not try to drive by setting bit SGTDIS to 1 the same pin to different levels Pin ALE floats to a Mise low state through a weakintermaldownandpin multiplexed or non multiplexed is Se 92 lected theBHE pin will be active after a reset It The BTYP Bus Type field of the SYSCONregis can be disabledby setting the BYTDIS bit in the SYSCON register to 1 When the internal reset has completed the con figuration of Ports 0 1 4 and of tH HE signal n SGS THOMSON 4 MICROELECTRGNICS 11 System Reset In addition the stack overflow STKOV and the 11 5 INITIALIZATION SOFTWARE ROUTINE stack underflow STKUN registers should be in itialized After reset the CP SP and STKUN regis To ensure proper entry into tlieitializdbn soft ters all contain the same reset value FCOOhhile ware routine a hardware branch to location the STKOV register contains With the de zero segment zero is made immediateligllowing fault rese nitializdbn 256 words of system stack completion of the internal system reset or deasser are available where the system stack selected by tion ofa correct reset signal on 6 respec the SP growsdownw
253. ermined as fol lows If 0 wait states are programmed in bits 0 to 2 of the MCTC field the duration is determined by the state of thdREADY input pin If between 1 and 7 wait states are programmed in bits O to 2 of the MCTC field the CPU will first insert the programmed wait states into the memory cycle and afterthe wait states has ex pired it will check thEADY line and delay the memory accesslependingon the state of the READY line This feature provides the fol lowing aduntages forthe user 1 Memory can be connected operating with or without wait states anperipheals operating with READY to the external bus of the ST10x166 and use wait states together with the READY function If the memory is ac cessed the chip select logic is used to bring the READY line to a LOW state The CPU will SGS THOMSON MICROELECTRONICS 9 External Bus Interface insert the programmed number of wait states if any into the memory cycle then check the READY line find that the external device is ready READY 0 and terminate the mem ory cycle If the peripheral device is accessed first the programmed wait states are inserted and then theREADY line is checked For READY 0 the bus cycle will be terminated For READY 1 the CPU will hold the bus cy cle untiREADY goes to 0 and then terminate the cycle Since normallperipheralsoperat ing with a READY function are much slower than memories even memories
254. erroneous recep order to allow further variation of the monitored time interval Each time it is seretbby the Sd EE TUM Merton aro Provided Tor cation software the high byte of the Watchdog Timer is reloaded Thus time intervals between In the synchronousnode one data byte is trans 25us and 420ms can be monitored c 40MHz mitted or received sychronouly to a shift clock The default Watchdog Timer interval after reset is which is generated by the ST10x166 In the asyn 6 55ms chronous mode an 8 or 9bit data frame is trans mitted or received preceded by a start bit and terminated by one or two stop bits For multiproc 2 10 PARALLEL PORTS essor communication a mechanism to digtiish address from data bytes has bedncluded 8 bit The ST10x166 provides 76 1 0 lines which are or data wake up bit mode and a loop back option is ganized into four 16 bit I O ports Porto through 3 availablefor testing purposes one 2 bit port Port 4 and one 10 bit input port A number of optional hardware error detection ca Port 5 All port lines are bit addressable and all pabilitiesas been included to increasetheliab of Port 0 through 4 are individually bit wise ity of data transfers A parity bit can automaticallyP ogrammable as inputs or outputs via direction be generated on transmission or be checked on re egisters The I O ports are true bidirectional ports ception Framing error detdon allowsthe recog
255. eserved in the MD register This register however must only be saved when an interrupt JNB V COPYL routhe requiresuse of the MD register and a pre Test for only 16 bit result vious task has not saved the current result This MOV R83 MDH flag is easily tested by the Jump on Bit instructions Move high portion of MD Multiplicatioris simply performed by specifying the COPYL MOV R4 MDL correct signed or unsigned version of the instruc Move low portion of MD Clears tion The result is then stored in the MD register MDRIV The overflow flag V is set if the result from a mul tiply or divide instruction is greater than 16 bita were caved DONE This flag can then be used to determine whether both word halves of the MD register must be trans _ POP MDL ferred from the MD register One must first move Restore registers the high portion of the MD register into the register POP file or memory to ensure that the MDRIU flag re flects the correct state The followinginstruction sequence performs an 6 by 16 bit mulplication SAVE JNB MDRIU START Test if MD was in use POP MDC DONE instruction To perform division the user must first move the dividendnto the MD register If a 16 16 bit division SCXT MDC 0 is specified only the low portion of the MD register Save and clear control register must be loaded The resultis also stored in the MD only required if multi
256. eused for SGs THoMson 1 5 5 Central Processing Unit Figure 5 4 Partitioning Example with BUSCON and SYSCON Segment 0 External Memory Accessed via SYSCON Parameters External Memory Accessed 16K Range via BUSCON1 Start Address Parameters e g 8Bit 8000h 32K Data Multiplexed Bus 2 Wait States READY enabled External Memory Accessed via SYSCON Parameters e g 16Bit Data Non Multiplexed Bus No Wait State BUSCON1 FF14h 8Ah Bus Configuration Register Reset Value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 b15 b14 b13 b11 b8 R Reserved b12 RDYEN1 READY Input Enable control bit RDYEN 0 READY function disabled for BUSCON1 accesses RDYEN 1 READY function enabled for BUSCON1 accesses b10 BUSACT1 Bus Active Control Bit b9 ALECTL1 ALELengtheningControl Bit b7 b6 BTYP External Bus Configuration Control b5 MTTC1 Memory Tri state Time Control b4 RWDC1 Read Write Delay Control b3 to b0 ZMCTC Memory Cycle Time Control ADDRSEL1 FE18h OCh Address Select Register Reset Value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 b15 to b10 zR Reserved b9 b3 ZRGSAD BUSCON1 Address Range Start Address Selection b2 b1 b0 ZRGSZ BUSCON1 Address Range Se lection 12 26 y SGS THOMSON o MICROELECTRONICS 5 Central Processing Unit 5 3 2 BUSCON1 Bus Configuration Register Warning The BUSCON1 regi
257. f field the SYSCON register are initialized during one of the two 16 bit Data Bus modes is selected reset This selected configuration can be modifiedduring reset the function of the Byte Highable during inializationbut after the EINIT instruction pin becomes alsoenabled and stays en only the external bus configuration can be modifiedabled until the BYTDIS bit in the SYSCON register at any time Any changes of the configuration is set to 1 This ensures that the External Bus which affect the on chip ROM or Flash Memory Controller can properly access the initialization can only bemade until the encbf theinitialiation code case Many ofthe external bus transfer instruction e g the mapping of the ROM to seg characteristicsare controlled via the SYSCON ment 1 the ROMdisabled ister in addition Software programming of the SY Table 9 2 shows all theossibilit of configuration SCON register allows the user to vary particular ap timing parameters in a wide range During reset all If the ST10x1 66 is initialized to an external bus of theexternal bus timing parameters areimized configuration mode other than the single chipjn a way that even very slow external memories mode Port 4 pins are used as an output for the can be accessed properly For more details on the most significant address pins A17 and A16 This programmable external bus timing parameters see alternate function of Port 4 stagnabled uni the section 9
258. f the most significant bit of the result is set Cleared otherwise INSTRUCTION FORMAT BXO Taoxtivy Mvenoviy Mvenoviy Onepav o Byteo AND AND Ruh RWm 60 nm 2 AND AND Rwa Rw 68 n 10ii 2 AND AND Rwa Rw 68 111 2 AND AND Rw datag 68 n 0 2 AND AND 66 RR 4 AND AND reg mem 62 RR MM MM 4 AND AND mem reg 64 RR 4 Ey SGS THOMSON 9 84 o MICROELECTRGNICS A Ivotpux tiov Let ANAB ANA ANAB 2 OPERATION 1 0 1 0 2 DATATYPES BYTE ANAB Performs a bitwise logical AND of the source operand specified by op2 and the destination operand specified by op1 The result is then stored in op1 FLAGS E 2 V Byteo E Setifthe value of op2 represents the lowest possible negative number Cleared oth erwise Used to signal the end of a table 2 Set if result equals zero Cleared otherwise V Alwayscleared C Always cleared N Setif the most significant bit of the result is set Cleared otherwise INSTRUCTION FORMAT BXO Taoxtvy Mvenoviy Mvenoviy Onepav o ANDB AND Rw RWm 61 nm ANDB AND Rw Rw 69 n 10ii ANDB AND Rw Rw 69 n 11ii ANDB AND Rw dat 69 n 0 ANDB AND reg datas 67 RR ANDB AND reg mem 63 RR MM MM ANDB AND mem reg 65 RRMMMM 1084 r SGS THOMSON MIGRCELECTREMICS A Ivotpuyuov Let AX HP AX HP APUTNMETLY Prynt AXHP ol 2 OPERATION c
259. f these interrupt requests can be pro maximum resolution of 400ns The CAPCOM grammed to be serviced by the Controller Unit is typically used to handle high speed I O tasks or by the RripheralEvent Controller such as pulse and waveform generation pulse In contrast to a standard interrupt service where width modulation PWM Digital to Analog D A the current program executionssspendedand conversion software timing or time recording rela branch to the interrupt vector table is performed tive to external events just one cycle is stolen from the current CPU ac Two 16 bit timers TO T1 with reload registers pro tivity to perform PEC service serviceim yide two independenttime bases for the cap plies a single byte or word data transfer between ture compare register array any two memory locations with an additional incre 4 ment of either the source or the destination The input clock for the timers is programmable to pointer AnindividuaPEC transfer counter is im Several prescaled values of the internal system plicitly decremented for each PEC service except Clock or may be derived from an overflow under when performing in the continuous transfer mode flow of timer 6 in module GPT2 When this counter reaches zero a standard inter This provides a wide range of variation for the timer rupt is performed to the corresponding source re period and resolution and allows precise adjust la
260. feature isavailable for all operating modes asynchronous and syn chronous of the serial channels 8 4 2 Baud Rates Each of the serial channels of the ST10x166 has its own dedicated 13 bit baud rate generator with 13 bit reload capability allowing independent baud rate selection for each channel Both baud rate generators are 13 bit timers clocked with the internal system clock divided by 2 10MHz at 40MHz oscillator frequency The tim ers are counting downwards and can be started or stopped through the Baud Rate Generator Run Bits SOR or S1R in register SOCON or S1CON Each underflow of a timer provides one clock pulse to a serial channel The timers are reloaded with the value stored in their 13 bit reload register each time they underflow The baud rate selection bits SOBRS and S1BRS allow the increase of the baud rate by a coefficient of 2 3 Ey SGS THOMSON MICROELECTRONICS 8 Peripherals Thus the baud rate of a serial channel is deter mined by the oscillator frequency the Baud Rate Selection Bit the reload value and the mode asynchronous or synchronous of the serial chan nel Registers SOBG and S1BG are the dual function Baud Rate Generator Reload registers Reading SOBG or S1BG returns the contents of the timer while writing to SOBG or S1BG always updates the reload register When writing to SOBG or S1BG i e to the reload registers the 3 upper bits 13 through 15are insignificant while reading SOB
261. fied word or byte data type has been generated during a subtraction which is perfoed internallyby the ALU as a 2 s complement addition and the C flag is cleared when this complement addition caused a carry The C flag is always cleared for logical multi ply and divide ALU operations because these Since logical ALU operations can not produce operations can not cause a carry anyhow an invalid result the V flag is cleared by these operations For the shift and rotate operations the C flag represents the value of the bit shifted out last If a shift count of zero is specified the C flag will be cleared The C flag is also cleared for a prioritize ALU operation because a 1 is never shifted out of the MSB during the normalization of an operand The V flag is also used as Sticky Bit for rotate right and shift right operations With only using the C flag a rounding error caused by a shift right operation can be estimated up to a quan tity of one half of the LSB of the result In con junction with the V flag the C flag allows evaluating the rounding error with a finer resolu tion as shown in table below For Boolean bit operations with only one oper and the C flag is always cleared ForoBlean bit operationswith two operands the C flag represents the logical ANDing of the two speci fied bits Table 5 6 Shift Right Rounding Error Evaluation C Flag V Flag Rounding Error Quantity No Rounding Error 0
262. floating gate 3 Meuopy Epace Meynaviou CONTROL GATE FLOATING GATE SOURCE VRDOT6B3 Unlike standard EEPROM memory wherimdividualbytes can be erased the Flash memory of the ST10F166 performs erase on blocks where the high voltagapipliedto all cells simltaneousy 2 19 Gr SGS THOMSON A difficulty with Flash memory concerns the requirement to set all the cells of a block to a minimum thresh old level suitable for programming and erase operations Applying a new erasing pulse to a block with a different storage level on each cell a different threshold level can bataemyerousfor the nctionalit of the Flash memory 4 Epaovpe CELL THRESHOLD CELL READ o Programming curve VERY SMALL DISPERSION Erasing curves TIME ms ERASING A CELL SET TO 1 PROBLEM ALL CELLS MUST BE SET TO 0 BEFORE ERASING VR001644 A fasterasing cell may have athreshold voltage too low or negative in this case the transistor is always on and is read at one This has the effect of leakage on other cells placed on the same array column Thus all cells of the column will be read at one instead of zero To avoid this the user mustjualizethe amount of charge on each cell by programming to 0 all cells of the bank before every erasure For increasedreliabilitythe SGS THOMSON Flash memorydchnology com
263. ger result e g 1 0 one has to per form a worst case evaluation of the selectappli cation signal delays etc to decide whether an additionalait state must be ansideredor not If wait state calculations supply different values for the same programmable parameter the worst case maximum value must always be consid ered Then the SYSCON register has to be pro grammed as follows 1 n3 MCTC 15 max n1 n2 Note For some memories the Chip Select Time typical values into the formulas represented the t s may be as long as the Address to Valid Data In correspondingable The required numbes of wait states are specified in all subsequent tables by symbols as follows For memory read accesses ni Number of wait states required to match Address to Valid Data In Time 0 lt nix 15 n1 integer 6 10 Time tcc Formulas within this document do not consider any signal delay caused by the chip se lecting logic All times are specified in nanoseconds ns unless noted otherwise SGS THOMSON MICROELECTRONICS C Application Example Table C 1 Multiplexed Memory Read With Read Write Delay t Address to Valid Data In i lt t7 n1x50 tacc lt 4 25 n1 x 2TCL 825 gt tcc 50 1 5 n1 gt 25 2TCL 2 RD to Valid Data In de t4 n2x50 te lt 2TCL 15 n2x 2TCL n2 toe 50 0 7 n2 gt toe 15 2TCL 1 Data Float AfterRD lt to n3x50 he lt 2TCL 15 n
264. ges 1 1 5 Consistent and Optimized Instruction Formats To obtain optimum performance drpipelinecde sign an instruction set has beelesignedwhich incorporates concepts from Reduced Instruction Set Computers RISC These concepts primarily allow fast decoding of the instructions and oper ands while reducing pipeline holds These con cepts however do not preclude the use of complex instructions which are required by micro controller users following goals werused to design the instruction set 1 Provide powerful instructions to perform op erations which currently require sequences of instructions and are frequently used Avoid transfer into and out of temporary registers such as accumulators and carry bits Perform tasks inparallelsuch as saving state upon en try to interrupt routines oulsroutines SGS THOMSON MICROELECTRONICS 1 PeripheralEvent Controller PEC This proc essor is used to off load many interrupt re quests from the CPU It avoids the overhead of entering and exiting interrupt or trap routines by performing single cycle interrupt driven byte or word data transfers Multiple Priority Interrupt Controller This con troller allows all interrupts to be placed at any specified priority Interrupts may also be grouped which provides the user with the abil ity to prevent similar priority tasks from inter rupting each other Multiple Register Banks This feature allows the user to spec
265. gether for word Note that the EBC places any byte value to be writ transfers ten to the external memory on both the upper byte portion and the lower byte portion of the 16 bit ex Only the high byte memory is ternal data bus However the byte will only be accessed for byte transfers stored inthat byte memory which is specified by AO To be correctly used as just described DIS output pin must be connected to the chip select im 31 1 Notused put CS of the memory at the high byte location Figure 9 5 16 18 Bit Address 16 Bit Data Bus Multiplexed Byte Wide Memories Segment Port 4 WR RD BHE ALE ST10x166 Port O ADDR CS OE WR ADDR CS OE WR 8 Bit 8 Bit External External Memory Memory INSTR DATA INSTR DATA 8001628 sg SGS THOMSON 7 9 External Bus Interface 9 6 16 18 BIT ADDRESS 16 BIT DATA twice in order to fetch a word wide value and it NON MULTIPLEXED BUS also savestheadditionatime delay caused by ad dress and data muiplexing _ As shown in figure 9 7 this external bus configura kd alb 59 bs ios used ircollabordbn with a tion mode can also be selected if the word organ Word WIde externatmemory ized external memory is implemented by two As shown in figure 9 6 Port 1 is used as a word separate 8 bit wide memory devices These two wide address output and Port 0 is used as sepa memories can be accessed both wordwise cou rated
266. given numbers of wait states and of the numbers of required wait states at given timing parameter val ues These tables consist of columns as follows Symbol Specifies commonly used symbols of the particular timing parameters Meaning Provides a short explanation of the symbolic timing parameters 40MHz Clock Specifies formulas to be used at a fixed oscillator frequency of 40MHz Variable Timing Specifies formulas to be used at a variable oscillator frequency Other so called Quick Tables signified by an ex tension b contain results caleted by insding n2 Number of wait states required to match RD to Valid Data In Time 0 lt 2 lt 15 n2 integer Number of wait states required to match Data Float AfteRD Time 0 lt n3 lt 1 n3 integer Total number of resulting wait states n max n1 n2 n3 For memory write accesses 1 Number of wait states required to match Write Pulse Low Time 0x nix 15 1 integer n2 Number of wait states required to match Data Valid tdVR Time 0x n2 lt 15 n2 integer Total number of resulting wait states required max n1 n2 Note The ST10x166 s wait states can be pro grammed in increments of one To get the number of required wait states to be programmed any value n1 n2 n3 calculated by means of the for mulas in tables a must be rounded upto the next integer value e g 1 252 If a calculation already suppliesan inte
267. gment FLAGS E 2 V C N C Notaffected N Notaffected V Not affected 2 Not affected E Not affected INSTRUCTION FORMAT BXO Taoxtivy Mvenoviy Mvenuoviy Onepav o Byteo CALLS CALL seg caddr DA 0 00ss MM MM 4 26 84 S amp S THOMSON A Ivotpuxuov Let XMII XMII XMII Ivteyep XOUTOPE onl 2 OPERATION op1 lt op2 DATA TYPES WORD The source operand specified by op1 is compared to the source operand specified by op2 by performing a 2 s complement binary subtraction of op2 from op1 The flags are set ac cording to the rules of subtraction T ygerandsremainunchanged FLAGS E 2 V E Setifthe value of op2 representsthe lowest possible negative number Cleared oth erwise Used to signal the end of a table 2 Setif the result equals zero Cleared otherwise V Setif an arithmetic underflow occurred i e the result can not be represented in the specified data type Cleared otherwise C Setifa borrow is generated Cleared otherwise Setifthe most significant bit of the result is set Cleared otherwise INSTRUCTION FORMAT BXO Taokwy Mvepnovux Onepav o Byteo CMP CMP Rwn RWm 40 nm 2 CMP CMP Rw Rw 48 n 10ii 2 CMP CMP Rw Rw 48 n 11ii 2 CMP CMP Rwn dat 48 n 0 2 CMP CMP reg zidatae 46 RR 4 CMP CMP reg mem 42 RR MM MM 4 A Ivotpux tiov Let XMIIB XMIIB OPERATION FLAGS XMIIB Ivteyep XOUTOPE onl
268. gram Write Algorithm shown in figure 5 for a better under standing of the user For higbliabilityit is necessary to follow this algorithm to program the Flash mem ory It is consideredhat the EBC1 VPP pin has been switched to the VPP supply after reset and the write mode has been unlocked GIIIIPIG After setting the program mode a delay ofrt must be inserted to allow the device to set its internal high voltage signals Then before starting the proper programming operation the VPP level must be checked VPPRIV is atthe one level if VPP is correct If itis not the programming algorithm must be held until VPP reaches its correct value or until the VPP supply is set correctly mov FCR read FCR jnb vppriv vpp test if VPP is high N 0 Initializatiorof vatableto zero The Presto F Program Write algorithm consist of applying severab100 pulses b each word until a coect verify occurs The maximum number of programming pulse is fixed to 25 ifthis limit is reached the word will never be programmed In case of several words to program an Address variable caimklialied mov ALLO reset algo l oop counter YOUMAVS First step for programming set FCR with the desired value Set FWE bit to enable programming mode Clear CKCTLO amp CKCTL1 bits to define a 108 programming time Choose the configuration Set WDWW bit for double word pr
269. gram parts with regard to such for iong ori u man ANS pipeline caused timing particularities to Ins2 MOV 0000h R1 move contents of GPR 1 to address location 0000h in data page 4 supposed that segmentation is not disabled 4206 n SGS THOMSON MICROELECTRONICS 5 Central Processing Unit 5 2 INSTRUCTION STATE TIMES Basically the time to execute an instruction de pends on where the instruction is fetched from and where possible operands are read from or written to The fastest processing mode of the ST10x166 is to executea program fetched from the internal pro gram memory In that case most of the instructions can be processed within just one machine cycle which also represents the general minimum execu tion time All of the external memory accesses are performed by the ST10x166 on chip External Bus Controller EBC which works in parallel with the CPU Mostly instructions from the external memory can not be processed as fast as instructions from the internal program memory because some data transfers which internally can be performed in parallel have to be performed sequentially via the external inter face In contrast to internal program memory pro gram execution the time required to process an external program additionally depends on the length of the instructions and operands on the se lected bus mode and on the duration of an external memory cycle which is partly s
270. h for reliableprogramming it will be at a logical 0 7 6 5 4 3 2 1 0 The reset value depends on the status of the exter nal Vpp on the EBC1 Vpp pin woww vera rover FSUSY pee ewe b3 FCVPP READ ONLYbit if set at alogical 1 will indicate to the user that VPP voltage has gone below the programming threshold during a pro b15 FWMSET will be set at a logical 1 once 9 mming or erase operation At 0 during reset the Write mode has been entered This bit mustbe b2 FBUSY READ ONLYbit is set at a logical 1 set to 1 at each writing of the FCR for an erase or during a program erase operation At 0 during re programming operation It will stay set at 1 whenset the operation has ended The user must reset po RPROT WRITE ONLY bit is used when the FWMSET to exit from the FLASH memory Write protected FLASH option is chosen This bit set at mode At 0 during reset a logical 1 and with the option selected will en b14 to b10 R reserved for future development able protection At 1 during reset must be written to 0 b1 FEE if set at a logical 1 will enable the b8 9 BEO 1 select the different Banks for Erase erase operation otherwise 0 for the program as shown in th ollowing able ming operation At 0 during reset In state 0 during reset bO FWE if set at a logical 1 will enable the writ ing operation the programming or
271. h instruction a rel value of 1 sources which are provided for the fu FFh or 2 leads to a repeated ture onlytrap numbers from 00h to 7Fh execution of the branch instruction it can be specified Any double word self code location in the address range from 00000h to 001FCh in code seg seg Specifies an absolute code segment ment 0 can be accessed by the trap number Currently the ST10x166 sup ports four different code segments and thus only the two least significant bits of the seg operand value are used for updating the CSP register S amp S THOMSON addressing mode The association be tween trap numbers and the corre sponding interrupt or trap sources is specified in table 7 1 7 8 6 Instruction Set Overview 6 3 CONDITION CODE SPECIFICATION monic abbreviations are ailablefor that It also describes which kinds of tests are performed due 16 possble conditiowodes can be used to deter the selected condition code and it shows the as mine whether aconditionabranch shall be taken sociation between the condition codes and their in or not Table 6 6 gives an overview of which mne ternal representation by a four bit number Table 6 6 Condition Codes Condition Code Test Description CC Mnemonics Number esee Dun ee Due pe om wem SERE 9 LN feo wem Leur fen
272. h the des tination bit specified by operand op1 The ANDed result then stored in op1 FLAGS E 2 V 0 NOR OR AND XOR E Always cleared 2 Contains the logical NOR ofthe two specified bits V Containsthe logical OR of the two specified bits C Contains the logical AND of the two specified bits N Containsthe logical XOR of the two specified bits INSTRUCTION FORMAT BXO Taoxtivy Mvenoviy Mvenoviy Onepav o Byteo BAND AND bitaddrz bitaddy q QQ 22 qz 4 12 84 565 0 50 BES THOMSON A Ivotpuxuov BXAP BXAP X eap BXAP oml OPERATION 1 0 DATATYPES BIT Clears the bit specified in operand op1 This instruction is primarily ugsstifjoneraand system control FLAGS E 2 V E Always cleared Z Contains the logical negation of the previous state of the specified bit V Always cleared C Always cleared Contains the previous state of the specified bit INSTRUCTION FORMAT BXO Taoxtivy Mvenuoviy Onepav o Byteo BCLR BCLR bitadd q qE QQ 2 57 S65 THOMSON E s MICROELECTRONICS A Ivotpux tiov Let BXMII BXMII XOUTAPE BXMII 2 OPERATION 1 lt gt 0 2 DATATYPES BIT Performs a single bit comparison of the source bit specified by operand op1 to the source bit specified by operand op2 No result is written by this instruction Ontynb ion codes are updated F
273. h timer overflow underflow The state input channels the remaining channels can be used ofthis latch may be output on a port pin e g for timeas digital input port pins out monitoring of external hardware components A D converter of the ST10x166 supports four may be used internally to clock timers T2 and T4 for different conversion modes In the standard Single measuring long time periods with high resolution Channel conversion mode the analog level on a In addition to their basic operating modes timers T2specified channel is once sampled and converted and T4 may be configured as reload or capture reg into a digital result In the Single Channel Continous isters for timer T3 When used as capture or reload mode the analog level is repeatedly sampled and registers timers T2 and T4 are stopped The con converted without software intervention tents of timer are captured into T2 or T4 re in the Auto Scan mode the analog levels on a pre sponse to a signal at their associated input pins Specified number of channels are sequentially sam Timer T3 is reloaded with the contents of T2 or T4 pled and converted In the Auto Scan Continuous either by an external signal or by a selectable state ifi S transition of its toggle latch When both T2 and T4 mode Ihe n mber et prespecineoenennsisris peatedly sampled and converted are configured to alternately reload T3 with the low _ constantly generated without softwar
274. hat VPP had the correct voltage ding programming After programming the FWE bit remains at a logical 1 The Program Verify Mode PVM is then entered automatically Anternallyjener ated margin voltage is applied to the FLASH and reading valid data indicates the word has been programmed successfully PVM needs a double read instruction with the same operand and time to stabilize the internal cir cuitry e g MOV R1 R2 Time out of 4us MOV R1 R2 To perform normal reading of the FLASH mem ory the FWE bit must be reset A programming operation of the FLASH memory can not be performed with a routine in the FLASH memory itself FLASH ERASE OPERATION As for the programming operation FLASH mem ory erase can be performed only inside the Write mode with indirect addressing mode instruction One of the four Banks is erased performing this op eration depending on the BEO 1 bits of FCR An erase operation is realized with thellowing sequence Program all the words of the relevant bank to 0000h Test VPPRIV bit of FCR to verify the correct voltage on VPP Load the desired value in FCR 5 8 MICROELECTRGNICS 4 Flash Memory 15 14 13 12 11 10 9 8 PRESTO F PROGRAM WRITE ALGORITHM Programming with Presto F algorithm consists of ij m _ 28 2258 ee oi ie ep we applying a equence of program pulses to each word until correct verify occurs A maximum of 7T 6 5 4 3 2 1 0 pr
275. he the TRAP instruction requires two cycles to push minimum interrupt response time may adttitlly the PSW generated by instruction Nand theIP and pe extended by 2 state times during internal ROM in segmentation mode the CSP of instruction program execution In case instruction N reads the N 1 PSW and instruction N 1 has an effect on the con The minimum interrupt response time is 5 states dition flags the interrupt response time may addi 250ns at 40MHz Thisappliesto program execu tionally be extended by 2 state times The worst tion fromthe internal ROM when no external oper case interrupt response time during internal ROM and read requests are performed and when the program execution is 12 state times 500 ns at interrupt request flag is set during the last state of40MHz See paragraph 5 for more details on in an instruction cycle When the interrupt request struction timing SGS THOMSON 1 1 77 YF MICROELECTRONICS 7 Interrupt And Trap Functions The absolute worst case interrupt response time location in the internal ROM the interrupt response will occur when instructions N through N 2 aretime is 1 word bus access plus 4 states executed out of an external memory instructionsN After an interrupt service routine has been termi and N 1 require operand read acesses nated through execution of the RETI instruction instructions N 3hrough write balc external op andit further interrupts are pending the nex
276. he core timer T6 or as both These functions are controlled separately by bits in the two timer control registers 5 and T6CON In the follow ing the use of register CAPREL in capture and re load mode is described in detail 8 2 2 3 1 Capture Mode This mode is selected by setting bit T5SC 1 in control register The source for a capture trigger is the external input pin CAPIN which is an Figure 8 33 Register CAPREL In Capture Mode Edge Select CAPREL Register 42 64 alternate input function of port pin P3 2 Either a positive a negative or both a positive and a nega tive transition at this pin can be selected to trigger the capture function The active edge is controlled by bit field Cl in register 5 according to ta ble below For triggering a capture operation on register CAPREL pin CAPIN P3 2 must be configured as input by setting its direction control bit DP3 2 to 0 The maximum input frequency for the capture trig ger signal at pin CAPIN is fosc 8 2 5MHz at fosc 40 2 To ensure that atransition of the capture trigger signal is correctly recognized its level should be held for at least 4 state times before it changes Interrupt Request Interrupt Request VROR1641 SGS THOMSON MICROELECTRONICS 8 Peripherals When a selected transition atthe external input pin CAPIN is detected the contents of the auxiliary timer T5 are latched into register
277. he required 18 bitbus and Port 1 is used as an interface to the 16 bit addresses external address bus No time miplexingand no 16 18 Bit A 16 Bit D Multipl additionaladdress latch is required in this bus B TO BIE MIB Id mode If segmentation is enabled Port 4 is addi tionally used to output the two most significant bits This mode is provided for accesses to a word or of the required 18 bit address anized external memory The sixteen least signifi x address bits and the data word UE Basically the ST10x166 supports an 18 bit ad time multiplexed on the word wide external bus dress space The 16 bit address mode refers to the case of segmentation being disabled 1 20 9 External Bus Interface Regardless of which external bus mode is se 9 1 EXTERNAL BUS CONFIGURATION lected accesses to addresses from 00 DURING RESET through OFFFFh are performed internally case of initializinghe 511016610 the nglechip mode of the initial external bus configuration modes internal ROM accesses become basicadiyabled is selected by means of three External Bus Con and thus accesses to addresses frota 0000h figuration pins EBCO EBC1 anBUSACT For through 07FFFh are performed internally too this the input values on these dedicated pins are Otherwise any accessto addresses within the first sampled during reset and copied into the BTYP bit 32Kbytes would be performed externally In any fi
278. higher CPU priority erglobaly dis and to the peripherals turned off In the abled interrupt system IEN 0 The CPU will ST10x166 the oscillator is completely switched ONLY go back into Idle mode when the interrupt Off Like in Idle mode all port pins which are config systemis globally enabledEN 41 ANDaPEC Ured as general purpose output pins output the last service on a priority level higher than the currentdata value which was written to their port output CPU level is requested and executed latches The Watchdog Timer may be used for monitoring When the alternate output function of a port pin is the Idle mode an internal reset will be generated if USed by a peripherathe state of this pin is deter no interrupt or NMI request occurs before the Mined by the last action of th ripheal before Watchdog Timer overflows To prevent the Watch the clocks were switched off In particular if dog Timer from overflowing during Idle mode it CLKOUT the alternate output function of P3 15 must be programmed to a reasabletime interval had been enabled it is not active during Power before the Idle mode is entered Down mode 2 4 Gr SGS THOMSON AN 12 Power Reduction Modes All external bus actions are completed before Idle Abbreviations used or Power Down mode is entered However Idle or ivi Power Down modes can NOT be entered if READY is enabled but has not been deasserted during the last bus acce
279. hip Mode and the egtnal bus configura of two byte organized memory chips which are tion modes see section 9 1 connected with the ST10x166 via a word wide ex ternal data bus After reset BYTDIS is initialized to zero For further information about the use of pin see chapter 10 Table 5 2 External Bus Configuration via BUSACT BTYP bit field 0 00 ROM enable Seg 0 No ext enable Seg 0 No Action Reserved ROM enable Seg 1 No Action Reserved Disable ROM No Action Reserved Disable ext Bus No Action 8 Bit Non Mux no ROM 8 Bit Non Mux 8 Bit Non Mux 8 Bit Mux no ROM 8 Bit Mux 8 Bit Mux 16 Bit Mux no ROM 16 Bit Mux 16 Bit Mux 16 Bit Non Mux no ROM 16 Bit Non Mux 16 Bit Non Mux sg SGS THOMSON 0 0 0 0 0 0 9 5 Central Processing Unit Table 5 3 SYSCON External Bus Timing Control Functions Control Value Number of Additional Affected Time Parameter State Times 15 Memory Cycle Time 9 8 7 6 5 4 3 2 1 0 Memory Tri State Time eo Read Write Signal Delay oo Memory Tri State Time implicit implicit for multiplexed implicit bus configurations 5 3 1 4 READY PIN CONTROL VIARDYEN into the memory cycle us ee The RDYEN bit provides an optional Data Ready egardlessf the state of th tEAD Y line Then af function via he cae loREADY input pin to id ter the wait state time has expired the CPU will low an external memory
280. ice This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the op erational sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability Note The ST10F166 is also offered inthe temperature range 40 to 105 C and 40 to 85 C All the following time specifications refer to a CPU clock of 20MHz which is identical to an oscillator frequency fosc of 40MHz Dm Symbol Parameter Test Condition Input Low Voltage 0 2 0 1 Input High Voltage 0 2 Vcc Output Low Voltage _ lo 2 4mA Ports 0 1 4 ALE RD W WR BHE CLKOUT RSTOUT Vout Output Low Voltage loti 1 6mA all other outputs Output High Voltage _ 0 9 Vcc G Ports 0 1 4 ALE RD WR 24 Pun p BHE CLKOUT RSTOUT VoHt Output High Voltage 0 9 Vcc SOWA all other outputs 2 4 1 6 Input Leakage Current Ports 0 0 V lt Vin lt Voc 1 2 3 4 NMI EBCO Vpp leakage Current 10 mA V V EBC1 Vpp iiia wg SGS THoMson 1L 5 YF MICROELECTRONICS ST10F166 DC Characteristics Continued Limit Values LLL 0 0 VeViseVco Test Condition Reset Resistor Input Current Current Pin Capacitance 10 f 1MHz digital inputs outputs Ta 25 C Power Down Mode Supply 150 Voc 2 5 V Current Vcc writing cu
281. ice routine is Setz 5 9 INTERRUPT PROCEDURE WITH SEGMEN TATION ENABLED Figure 7 5 Interrupt Procedure With Segmentation Disabled High High Addresses Addresses State of interrupted task saved on system stack Low Addresses Addresses a System Stack before b System Stack after Interrupt Entry Interrupt Entry The procedure that will be performed by the terrupt Request flag of the source that caused the ST10x166 s interrupt system when segmentation interrupt is cleared If a multiply or div geration is enabled igndepene nt of the code segment that was in progress when the interrupt was acknow the CPU is currently executing from ledged the MULIP bit in the PSW of the interrupt If segmentation is an request Service routine is set to 1 No data page pointer is is acknowledged the Code Segment Pointer affected CSP must also be pushed on the system stackto Upon execution of the RETI instruction Return ensure correctreturn to the previous segmentafter from Interrupt the information that was pushed on completion of the interrupt service routine Thethe stackispopped inreverse order to restore the contents of the PSW are pushed first then the con previous status Figure 7 6 shows how the system tents of the CSP and IP are pushed on the system stack is affected by an interrupt that is acknow stack The CSP for the interrupt service routine is ledged when segmentation enabled set to segment ze
282. ier ooon sm _ rem pem pm ewm Le rem carcomnesiwro Sm em rmm ain owcoumsee Les rem omm rum san Som Ceo reson am carcom negra oom Coos reus mom Tess cwcoumoswrs oom resem am carcom regi oom Ceo reson carcom magna oom eco son rem aan owcoumgswm mom capcom nesses wem rem ach Coers won wem cow roen oom cos rmm 4 16 Gr SGS THOMSON B ST10x166 Registers Name Physical 8 Bit Description Reset Address Address NUM ADDAT ADDAT FEAOh 5 A D Converter Result Register A D Converter Result Register qs reach seh reserve wot FEAEh Sh Watchdog Timer Register read oniy SOTBUF Serial Channel 0 Transmit Buffer Register 0000h write only SORBUF Serial Channel 0 Receive Buffer Register XXXXh read only Serial Channel 0 Baud Rate Generator 0000h Reload FEB8h EMI Channel 1 Transmit Buffer Register 0000h write only Serial Channel 1 Receive Buffer Register XXXXh read only FEBCh Serial Channel 1 Baud Rate Generato
283. iew of all avail a Bitwise ANDing of two words or bytes able instructions ordered by instruction classes is AND ANDB given The second section describes which thead Bitwise ORing of two words or bytes dressing modes ailable for each class Section 6 3 contains a description of the condition codes _ ORB availablefor conditional branch instructions a Bitwise XORing of two words or bytes A detailed description of each instructianjuding XOR XORB its operand data type condition flag settings ad dressing modes length number of bytes and ob 6 1 3 Boolean Bit Manipulation Instructions ject code format can be found appendixA 6 1 SUMMARY OF INSTRUCTION CLASSES This section contains a summary of the a Manipulation of a maskable bit field in either the high orthe low byte of a word BFLDH BFLDL a Setting of a bit BSET ST10x166 s instruction set subdivided instruc 4 Clearingof a bit tion classes Mnemonic instruction names refer to BCLR the corresponding descriptiorappendixA where He one can gain more detailed information adios a bit a Movement of a negated bit 6 1 1 Arithmetic Instructions BMOVN a Addition of two words or bytes a ANDing of two bits ADD ADDB BAND a Addition with Carry of two words or bytes ORing of two bits ADDC ADDCB BOR a Subtraction of two words or bytes XORing of two bits SUB SUBB BXOR a Subtraction with Carry of two words or bytes Comparison of two
284. if BHE functioenabled and fetch instruction or data when executing out ofREADY No change internal memory The CPU really stops execution if Figure 10 7 and 10 8 illustrate the timings for entry external data or instruction fetches are required The P2 14 used as hold acknowledge signal and exit from HOLD mode HLDA is active low This signal indicates to the 818 n SGS THOMSON MICROELECTRONICS 10 Parallel Ports Figure 10 7 Timing For Entry Into Hold Non Multiplexed Bus ARE HELD a m m m a a a a a m m a a a A QUT DAT Multiplexed Bus Non Figure 10 8 Timing For Exit From Hold 9 18 SGS THOMSON MICROELECTRONICS 10 Parallel Ports 10 1 3 Port 3 When the alternate input or output function of a Each of the 16 pins of Port 3 has an alternate Port 3 pin is not used this can be used as input or output function associated with it Sevengeneral purpose I O pin When an alternate func pins have an alternate input function seven pins tion is used ona Port3 pin the configuration of this have an alternate output function and two pins Pin dependson the type of the alternate function RXDO and RXD1 have an alternate input or output There are four different configurations described in functiondependingon the operating mode of the the fdlowingparagraphs serialchannel theyare a
285. ifies an immediate constant tion the selected addressing mode All yaiue an address or a pointer to an address as fol of the addressing modes ailable are summa 2 f lows rized at the end of single intruction descrip 26 tion In contrast to the syntax for the instructions Specities the immediate described thedllowing the ST10x166 assem constant value of opX bler provides much morelekibility in writing opX Specifies the contents of opX ST10x166 programs e g by generic instructions opXn Specifies the contents of and by automatically selecting appropriate ad bitn of opX dressing modes whenever possible and thus it A eases the use of the instruction set opX Specifies the contents of the contents of opX this means that opX is used as pointer to the actualperand 1 84 A Ivotpux tiov Let In addition to the formalperandsop1 op2 and 1 5 payo op3 which have already been introduced sub This part reflects the state of the V Zand E section A 1 2 Syntax following opemds will be used in the operational description flags in the PSW register which is the state after execution of the correggndingnstruction except if the PSW register itself was specified as the desti nation operand of that instruction see Note The resulting state of the flags is represented by symbols as follows The flag is set due to thellow
286. ify up to sixteen general pur pose registers located anywhere in the internal RAM A single one machine cycle instruction is used to switch register banks from one task to another Interruptable Multiple Cycle Instructions Re duced interrupt latency is providedalpwing multiple cycle instructions multiply divide to be interruptable 2 3 3 6 1 Architectural Overview 1 2 FUNCTIONAL BLOCKS 1 2 1 3 BARREL SHIFTER 16 bit barrel shifter provides multiple bit shifts in The ST10x166 family clearly separates peripher single cycle Rotates and arithmetic shifts are als from the core also supported This structure permits the maximum number of op erations to be performed iparalleland allows pe ripheralsto be added or deleted from family 1 2 2 Peripheral Event Controller and members without modifications to the core Each Interrupt Control functional block processes dattdependentlynd Each interrupt source is prioritized every machine communicates information over common buses cycle in the interrupt control block If PEC service is Functional blocks in the CPU core are controlled selected a PEC transfer is started If CPU interrupt by signals from the instruction decode logic Pe service is requested the current CPU priority level ripheralsare controlled by data written to the Spe stored in the PSW register is tested to determine cial Function Registers SFRs whether a higher priority interrupt is currdsd
287. igger a PEC service request timer will be set This flag can be used to generate b6 TOIE Timer 0 Interrupt Enable Bit an interruptor trigger PEC service request when If set at 1 will enable the timer 0 interrupt enabledby the interrupt enable bits TOIE or T1IE b5 to b2 IL VL Interrupt Priority Level Bits Each of the two timers TO or T1 has its own bit See chapter 7 for more details addressable interrupt control register TOIC or T1IC and its own interrupt vector TOINT or os alle S siu riority Bits T1INT The organization of the interrupt control i registers TOIC and T1IC is described hereafter Refer to chapter 7 for more details on the interrupt control registers T1IC FF9Eh CAPCOM Timer T1 Interrupt Control Registers Reset Value 0000h 7 6 5 4 3 2 1 0 b7 T1IR Timer 1 Interrupt Request Bit This flag can be used to generate an interrupt or trigger a PEC service request b6 T1IE Timer 1 Interrupt Enable Bit If set at 1 will enable the timer 1 interrupt b5 to b2 ILVL Interrupt Priority Level Bits See chapter 7 for more details b1 b0 GLVL Interrupt Group Priority Bits See chapter 7 for more details n SGS CTHIMSON 7064 o MICROELECTRGNICS 8 Peripherals 8 1 1 5 BLOCK DIAGRAM The followingolock diagrams illustrate the selec while Figure 8 4 shows a block diagram of timer tion ofthevailablefunctions for timer TO and timer T1 T1 Figure 8 3 shows
288. igure 5 4 shows an example of control of parti tions of the external address range by SYSCON and BUSCON1 Table 5 5 Address Range Selection Range Size Relevant Bits of RGSZ Selected Address Rarige Range Start Address 2 KByte RRRRRRR 16 KByte RRRRxxx 32 KByte RRRxxxx 64 KByte RRxxxxx 128 KByte RXXXXXX reserved reserved reserved SGS THOMSON 0 515 5 Central Processing Unit 5 3 4 PSW Processor Status Word PSW FF10h 88h This bit addressable register reflects the current Processor Status Word Register state of the microcontroller It is subdivided intotwopeset Value 9000h parts of which the first one contains bits which rep resent the current ALU status and the second bits 15 14 13 12 11 10 9 8 which determine the current CPU interruptstatus xw nr A separate bit USRO within the PSW register is provided for use as general purpose flag 7 6 5 4 3 2 1 0 5 3 4 1 ALU STATUS C V Z E MULIP r jumjwue E z v The condition flags of the PSW N C V Z E indicate b15 b14 b13 b12 ILVL This field represents the the ALU status due to the last recently performed ALU current interrupt level being serviced by the CPU operation They are set by most of the instructions due Upon entry into an interrupt routine the four bits to specific rules which depend on the ALU or data of the priority level of the snowledgednterrupt movement operation perfor
289. imer T6 and the auxiliary timer T5 to form a 32 bit or a 33 bit timer 16 bit timer T6 T6OTL 16 bit timer T5 see also section 8 2 1 2 3 The count di rections of the two timers are not required to be the same which offers a wide variety of different con figurations Figure 8 32 shows a block diagram for the concatenation of timers T5 and T6 8 2 2 2 3 Timer T5 Interrupt Control When timer T5 overflows from FFFFh to 0000h when counting up or when it underflows from 0000h to FFFFh when counting down the inter rupt request flag T5IR in register will be set This will cause an interrupt to the timer T5 interrupt vector T5INT or will trigger a PEC transfer if the interrupt enable bit T5IE in register T5IC is set The organization of interrupt control register T5IC is de scribed below Refer to Chapter 7 for more details on interrupts Table 8 15 Register CAPREL Capture Trigger Selection Contents of T5 Captured into CAPREL on RM NN Figure 8 32 Concatenation of Timers T5 and T6 Edge Select TSR TSUD TSI Interrupt Request Interrupt Request Note Line only affected by over underflows of but NOT by software modifications of TBOTL SGS THOMSON VRDN1841 41 64 MIGRCELECTREMICS 8 Peripherals 8 2 2 3 GPT2 CAPTURE RELOAD REGISTER CAPREL This 16 bit register can be used as a capture regis ter for the auxiliary timer T5 or as areload register for t
290. in wihin the internal RAM space does NOT struction sequences The ST10x166 simulator and Cause additional state times However reading an emulator offer many facilities which support theindirectly addressed internal RAM operand will ex user in optimizing the program whenever required tend the processing time by 1 state time if the pre 626 o n SGS THOMSON MICROELECTRONICS 5 Central Processing Unit ceding instruction auto increments or auto decre 5 External operand writes ments GPR as shown in th ollowingxample MOV RO auto increment RO MOV R3 R2 if R2 points into the internal RAM space 1 x State In this case the additional time can simply be In Int Tiadd 0 x State 1 x ACT Writing of an external operand via a 16 bit data bus takes one additional ALE Cycle Time For timing calculations of external program parts this extra time must always be considered The value which must be considered for timing evaluations of internal program parts may fluctuate between 0 avoided by putting another suitable instruction be state times and 1 ALE Cycle Time This is because fore the instruction indirectly reading the inter nal RAM 3 Internal SFR operand reads Tiadd 0 1 x State or 2 x States Mostly SFR read accesses do NOT require addi tional processing time In some rare cases how ever either one or two additional state times will be 6 c
291. in dog Timer continue to function normally only the tentionally entering the Power Down mode First CPU operation is halted the dE irat dies dd The Idle mode is entered after the IDLE instruction used to enter this mode has been implemented nas peen executed and the instruction before the as a protected instruction Second this instruc pi E instruction has completed To prevent unin tion is effective ONLY if thBMI Non Maskable tentional entry into Idle mode the IDLE instruction Interrupt pin is externally pulled low while the nas been implemented as a protected instruction PWRDN instruction is executed The microcon troller will then enter the Power Down mode after The Idle mode is terminated by interrupt requests the PWRDN instruction has completed from any enabled interrupt source whose individ ual Interrupt Enable flag was set before the Idle mode was entered 1 4 12 Power Reduction Modes For arequest which was selected for CPU interrupt 12 3 STATUS OF OUTPUT PINS DURING IDLE service the associated interrupt service routine isAND POWER DOWN MODE entered ifthe priority level of the requesting source is higher than the current CPU priority and the in Duringldle mode the CPU clocks are turned off terrupt system igloballyenabled After the RETI while all peripherals continue their operation in the Return from Interrupt instruction of the interruptnormal way Therefore all ports pins which are service routine
292. in bit pattern into spe terminated by any reset or interrupt request cific RAM locations and then execute the PWRDN while Power Down mode can only be terminated instruction If thBIMI pin is still low at this time the by a hardware reset Power Down mode will be entered otherwise pro gram execution continues During power down the voltage at the VCC pins can be lowered to 2 5V 12 1 POWER DOWN MODE and the contents of the internal RAM will be pre To save power in a system the microcontroller served ee us can be placed in Power Down mode All clocking Later when a reset occurs the italizatiorroutine of internal blocks is stopped but the contents check the identification flag or bit pattern in the internal RAM are preserved through the volt RAM to determine whether the controller was in age supplied by the VCC pins The Watchdog itially switched on or whether it was properly re Timer is stopped in Power Down mode One can Started from Power Down mode only exit this mode through an external hardware reset by asserting a low level on tiRSTIN pin 12 2 IDLEMODE for a specified period of time at least 2 state times This reset will initialize all SFRs and ports one can decrease the power consumption of the to their default state but will not change the con ST10x166 microcontroller by entering Idle mode If tents of the interna enabled allperipherals INCLUDING the Watch There are two levels of protection against un
293. in register T3IC is set Theorgani 7 6 5 4 3 2 1 0 zation of register T3IC is shown below Refer to chapter 7 for more details on interrupts T4CON FF44h A2h GPT1 Auxiliary Timers T4 Control Register Reset Value 0000h 15 14 13 FF62h B1h GPT1 Core Timer Interrupt Control Register Reset Value 0000h 7 6 5 4 3 2 1 0 12 11 7 6 5 4 3 2 1 0 8 2 1 2 GPT1 AUXILIARY TIMERS T2 AND T4 b15 to b8 R Reserved Both auxiliary timers T2 and T4 have exactly the 07 TXUD Timer x Up Down Control bit same functionality They can be configured for TXUD 0 Selectup counting timer gated timer or counter mode with the same TXUD 1 Select down counting options for the timerdquenciesand the count sig b6 TxR Timer x Run Bit nal as the core timer In addition to these 3 0 Timer x Stops counting modes the auxiliary timers can be con TxR 1 Timer x Runs catenated with the core timer or they may be used T as reload or capture registers in conjunction with S 10 Pee fines x Mode Control the core timer Unlike the core timer thaxiliay dn timers can not be controlled for up or down countb2 to b0 Timer x Input Selection by anexternal signal nor do they have a toggle bit See table 8 7 8 10 8 11 or 8 12 for more details or an alternate output function The individuatonfiguration for timers T2 and T4 is determined by their bit addressable control regis ters T2CON and T4CON which
294. in the PEC source and desti on priority level 15 or 14 whose COUNT field of the ation pointers are interpreted as direct 16 bit associated PEC channel contains 0 a CPU inter Memory addresses in segment 0 so that data rupt requestwith the vector of that source is gener tfansfers can be performed between two ated Note that no PEC data transfer operation can Memory locations within the first four data pages be performed while the CPU is executing a routine Pages 0 through 3 on CPU priority level 15 While the CPU is execut 7 2 3 Prioritization of Interrupt and PEC ing a routine on CPU priority level 14 only PEC Service Requests 10 24 SGS THOMSON 7 Interrupt And Trap Functions Figure 7 4 Mapping Of PEC Source And Destination Pointers into the Internal RAM PEC Source and Internal Destination Pointers RAM External Memory RAM Location PEC RAM Location Source Pointer Word Address Destination Pointer Word Address rom Cs rom rm Uem oem rom oem rm scm ome rw wen rem pow rh Ey SGS THOMSON 11 24 MICROELECTRONICS 7 Interrupt And Trap Functions Interrupt and PEC service requests from all sources that areenabled compete for service in the prioritization process The prioritization se quence is repeated every instruction cycle 7 2 3 1 ENABLING AND DISABLING OF INTERR
295. in the on chip area ontext Pointer CP register determines the modes which are as follows base address of the active register bank to be ac 16 bit 18 bit Addresses 16 bit Data Non Multi cessed by the CPU at the time The number of reg plexed ister banks is only restricted by tlavailable 16 bit 18 bit Addresses 16 bit Data Multi internal RAM space For easy parameter passing plexed register banks can also be organized to overlap 16 bit 18 bit Addresses 8 bit Data Multiplexed 16 bit 18 bit Addresses 8 bit data Non Multi plexed 2 6 SGS THOMSON TE micros ecrnenics 2 System Description Figure 2 2 CPU Block Diagram Instr Ptr Instr Reg 4 Stage Pipeline Mul Div HV 16 bit Barrel Shifter General Purpose Registers SYSCON ontext Ptr Code Seg Ptr A system stack of up to 512 bytes is provided asa storage for temporary data The system stack is al located in the on chip RAM area and itis accessed by the CPU via the stack pointer SP register Two separate SFRs STKOV and STKUN are implicitly compared against the stack pointer value upon each stackaccess for the detection ofa stack over flow orunderflow The high performance offered by the hardware im plementation of the CPU can efficiently be utilized _ by a programmer via the highly functional ST10x166 instruction set which includes the fol VR001614 Compare
296. incremented or written to by soft Figure 8 6 shows a functional diagram of a com ware After a reset compare events for register Pare register CCx configured for compare mode 0 CCx will only become enabled ifthe allocated timer Note that the port pin remaininaffected has been incremented or written to by software in compare mode 0 Figure 8 7 shows a simple tim and one of the compare modes described in the ing example for this mode In this example the followinghas been selected for this register compare value in register CCx is modified from cv1 to cv2 after compare events 1 and 3 and from The varii compare modes d pro cv1 after events 2 and 4 etc This results jected by SUE IE in periodic interrupt requests from timer Ty and in 1 interrupt requests from register CCx which occur at associated capture compare mode control register the time specified by the user through cv1 and cv2 see table 8 3 In the following each of the com pare modesjncludinghe specialdoulle register mode is discussed in detail Figure 8 6 Compare Mode 0 and 1 Block Diagram Interrupt Compare Reg CCx Request Toggle Mode 1 CAPCOM Timer Ty eques VROO1B38 12 64 565 50 C 8 Peripherals Figure 8 7 Timing Example for Compare Mode 0 Contents of Ty FFFFh Compare Value cv2 Compare Value cv1 Reload Value TyREL
297. ing Unit successor instruction are non aligned double words YSCON FFOCh 86h instructions as shownin thallowingexample System Configuration Register label 4 anynon alignecdoubleword instruction alues 0000h 0400h 0440h 0480h i e at location 12FAh 1 oe 15 14 13 12 11 10 9 8 anynon alignecdoubleword instruction roven BYTDIS CLKEN i e at location 12FEh JMPR UC label DL UN LIE CELLA E provided that a cache jump is taken 2 x States Tin 4 x States i If required these extra state times can beoided b15 R Reserved by allocating double word jump target instructions 14 b13 STKSZ Maximum System Stack Size to aligneddoubleword addresses xxx0h xxx4h Selectionof between 32 and 256 words xxx8h xxxCh b12 RDYEN READY Input Enable control bit RDYEN 0 READY disabled pin can be used for normal I O 5 3 CPU SPECIAL FUNCTION REGISTERS RDYEN 1 READY enabled pin used for READY input The core CPU requires a set of Special Function Registers SFRs to maintain the system state in b11 SGTDIS Segmentation Disable controle bit formation to supply the ALU with register address SGTDIS 0 A16 andA17 enabled Port 4 used able constants and to control system configuration for segment address and diide ALU operations code memory SGTDIS 1 A16 and A17 disabled Port 4 segmentation data m
298. ing table 6 10 Ey SGS THOMSON MICROELECTRONICS 3 Memory Organization Table 3 2 Maximum System Stack Size Selection Cm wum cau m m wem omm w rmo For all system stacloperationsthe on chip RAM 3 3 2 General Purpose Registers is accessed via the Stack Pointer SP register The sT10x166 s GPRs can basically be situated The stack growsdownwardfrom higher towards anywhere within the internal RAM address space lower RAM address locations Only word accesses addresses from to OFDFFh A particular are permitted to the system stack A stack overflow Context Pointer CP register determines the base STKOV and a stack underflow STKUN register address of the currently active register bank This are provided to control when the selected stack register bank may consist of up to 16 word GPRs area is left These two stack boundary registers RO R1 R15 and or of up to 16 byte GPRs can be used not only for protection against data RLO RHO RL7 RH7 The sixteen byte GPRs destruction but also to implement a circular stackare mapped onto the first eight word GPRs as with hardware supported system stadiashing shown in figure 3 4 and filling 9 In contrast to the system stack a register bank For further details about system stack addressing rows from lower towards hiaher address locations via the SP register and the use of the STKOV and and occupies a maximum space of 3
299. ingstandard rules for the corresponding flag CP Context Pointer register CSP Code Segment Pointer register IP Instruction Pointer MD Multiply Divide register 32 bits wide consists of MDH and MDL MDH Multiply Divide Low and High registers each 16 bit wide 0 PSW Program Status Word register 1 SP System Stack Pointer register 0 SYSCON System Configuration register V 21 Carry condition flag in the PSW register V 0 V Overflow condition flag in the PSW register 7 1 SGTDIS Segmentation Disable bit in the 2 0 SYSCON register E 1 count Temporary variable for an intermediate storage of the number of shift or rotate cycles which remain to complete the E 0 shift or rotate operation tmp Temporary variable for an intermediate result 0 1 2 Constant values due to the data format of the specified operation A 1 4 This specifies the particular data type accord ing to the instruction Basically tkedl winglata 0 types are possible BIT BYTE WORD DOUBLE WORD NOR Except for those instructions which extend byte data to word data all instructions have only one AND particular data type Note that the data types men tioned in this subsection do not consider accesses to indirect address pointers or to the system stack which are always performed with word data More OR over no data type is specified for System Control Instructions and for those of the b
300. ins which may be used for alternate input output and T1 each with its own reload register TOREL functions As can be seen from Figure 8 2 for each and T1REL and a bank of sixteen dual purpose pin e g P3 0 within a port there is a direction con 16 bit capture compare registers CChhrough trol bit e g DP3 0 within the associated port di CC15 rection control register e g DP3 In this figure The input clock for TO or T1 is programmable to those portions of port and direction registers which several presaled valuesof the system clock or it are not used by the CAPCOM unit for alternate can be derived from an overflow underflow of timerfUnctions are not shaded 2 64 Gr SGS THOMSON 8 Peripherals Figure 8 1 CAPCOM Unit Block Diagram System Clock TOIN P3 0 Input GPT2 Timer T6 Control Over Underflow CCOIO P2 0 Port 2 Alternate Mode Input Output Control Functions CC1510 P2 15 System Clock Input GPT2 Timer T6 Control Over Underflow Ks SGS THOMSON MICROELECTRONICS 16 Interrupt Request Capture Compare Interrupt Request Flags CC15IR Interrupt Request VR001616 3 64 8 Peripherals Figure 8 2 SFRs and Port Pins Associated with the CADCON Unit Ports amp Direction Control Data Control Interrupt Alternate Functions Registers Registers Control mum TOIN P3 0 P2 15 P2 0 VR001640 Port 3 Direction Contr
301. iption of the corre its high byte portion be accessed via these short 8 bit addressing modes Howevemovided 10300 n SGS THOMSON o MICROELECTRONICS SGS THOMSON JJ NicROELECTROMICS CHAPTER 4 ON CHIP FLASH MEMORY 4 ON CHIP FLASH MEMORY The ST10F166 provides in addition to the on chip Optionallythe FLASH Memory may be protected RAM 32K bytes of Electrically Erasable and Re against read and write accesses performed by programmable non volatile FLASH memory This fetch instructions from programs running in the in memory isorganisedas 8Kx32 bits allowinga ternal RAM or in external memory complete instruction to be read during one control of programming and erasing the FLASH tion fetch cycle Data values stored can be read aS memory is made from one Register the FLASH 16 bit operands usingll addresing modes ofthe Control Register FCR which is tially mapped ST10x166 instruction set into the FLASH memory space The FLASH memory is located in segment0 010 The presto F algorithm is used fosliability The O7FFFh during reset and thus contains the typical programming time is 109 and Stack time power on reset and interrupt vectors To provide ical en full flexibility in the use of the ST10F166 the CES presen FLASH memory may be remapped to segment 1 10000 to 17FFFh during irittlizationThis allows WARNING Access to or code execution from the the interrupt ve
302. iring soft ware to change the channel number The channels are converted consecutively starting with channel ANn which is specified in bit field ADCH down to and including channel ANO The auto scan conver sion mode is selected by 10b in bit field ADM Af ter conversion of channel ANn has been completed interrupt request flag ADCIR is set and the converter starts to convert channel ANn 1 This procedure is repeated until conversion of channel ANO is complete The A D converter then stops and resets bits ADST and ADBSY Resetting bit ADST while a conversion is in progress has no ef fect 8 3 1 4 AUTO SCAN CONTINUOUS CONVERSION This modeis selected by setting field ADM in regis ter ADCON to 11b The auto scan continuous mode differs from the auto scan mode described in the previous section only in that the converter does not stop after the conversion of channel ANO is completed The internal channel number counter is reloaded with the channel number which is speci fied in register ADCON and the conversion round is started again This procedure is repeated until 157 SGS THOMSON the converter is stopped by software When bit ADST is reset by software the converter will con tinue until the conversion of channel ANO is com plete It will then stop and reset bit ADBSY 8 3 2 A D Converter Interupt Control At the end of each conversion interrupt request flag ADCIR in interrupt control register ADCIC is set This e
303. is executed the CPU continues configured as general purpose output pins output normal program execution with the instruction folthe last data value which was written to their port lowing the IDLE instruction Otherwise if the inter output latches If the alternate output function of a rupt request can not be seined becaus of a too port is used by a peripheral the state of the low priority oa globallydisabled interrupt system is determined by the operation of the jipreral the CPU immediately resumes normal program Port2 Port 3 In particular if CLKOUT the alter execution with the instructia tlbwinghe IDLE in nate output function of P3 15 has been enabled it struction is also active during Idle mode For a request which was programmed for PEC Port pins which are used for bus control functions service a PEC data transfer is performed if the pri go into that state which represents the inactive ority level of this request is higher than the currentstate of the respective functioWR or to a de CPU priority and the interrupt systemgbobally fined state which is based on the last bus access enabled After the PEC data transfer has been BHE Pins which are dedicated for bus control completed the CPU returns into Idle mode Other functions are also held in the inactive state ALE wise if the PEC request can not be serviced be RD Port pins which are used as external ad cause of a too low priority orgloballydisabled dress data bus
304. is made to an odd byte ad pushed onto the system stack is the address of the the Illegal Instruction Access trap is entered The instruction that caused the trap This can be used IP value pushed onto the system stack is to emulate unimplemented instructions The trap 04d target address of the branch instruction service routine can examine the faulting instruction to decode operands opcodes based on the stacked IP In order to resume proc ILEGAL EXTERNAL BUS ACGESS TRAF essing the stacked IP value must be incremented Whenever the CPU requests an external instruc by the size of theindefinednstruction which isde tion or data fetch and no external bus configura termined by the user before a RETI instruction is tion has been specified in the BTYP field of the executed SYSCON register the ILLBUS flag in the TFR reg ister is set and the Illegal Bus Access trap is en 1 3 2 3 PROTECTION FAULT TRAP tered The IP value pushed onto the system stack Whenever one of the special protected instructionsis the address of the instructi ollowinghe one is executed where the opcode of that instruction iswhich caused the trap Ey SGS THOMSON 23 24 o MICROELECTRGNICS 7 Interrupt And Trap Functions NOTES 24 24 S amp S THOMSON SGS THOMSON MICROELECTRONICS 8 PERIPHERALS CHAPTER 8 PERIPHERALS This chapter provides a description of the fun
305. is then incremented by two E 2 V Set if the value of thpoppedword represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Set if the value of theoppedword equals zero Cleared otherwise Not affected Not affected Set if the most significant bit of theppedword is set Cleared otherwise m ZO lt N INSTRUCTION FORMAT Mvenoviy POP BXO Taoxtivy Mvenoviy Onepav o Byteo POP reg FC RR 2 57 S6S THOMSON 9M MICROELECTRONICS A Ivotpux tiov Let IIPIOP IIPIOP 2 OPERATION DATA TYPES tmp op2 count 0 DO WHILE tmps 1 AND count 15 AND 2 0 tmp tmpr 1 count 1 END WHILE 1 count WORD This instruction stores a count value in the wapdrand by op1 indicating the number of single bit shifts required to normalize the operand op2 so that its M amp amp db to one If the source operand op2 equals zero a zero is written to operand op1 and the zero flag is set Otherwise the zero flag is cleared FLAGS E 2 V E Always cleared Z Set if the source operand op2 equals zero Cleared otherwise V Always cleared C Always cleared Always cleared INSTRUCTION FORMAT BXO Taoxtivy Mvepnovuxr Mvenoviy Onepav o Byteo PRIOR PRIOR Run RWm 2B nm 2 64 84 S amp S THOMSON
306. ise Used to signal the end of a table 2 Set if result equals zero Cleared otherwise V Set if an arithmetic underflow occurred i e the result can not be represented in the specified data type Cleared otherwise C Setifa borrow is generated Cleared otherwise Setif the most significant bit of the result is set Cleared otherwise INSTRUCTION FORMAT BXO Taoxtvy Mvepnovur Mveuovty Onepav o Byteo SUBB SUB Ri Rbm 21 nm 2 SUBB SUB Rb data 29 n 0 2 SUBB SUB reg datac 27 RR 4 SUBB SUB Rh Rw 29 n 10ii 2 SUBB SUB Rb Rw 29 n 11ii 2 SUBB SUB reg mem 23 RR MM MM 4 SUBB SUB mem reg 25 RR MM MM 4 A Ivotpux tiov Let WITH Xappy onl 2 OPERATION op1 lt 1 op2 DATA TYPES WORD Performs a 2 s complement binary subtraction of the source operand specified by op2 and the previously generated carry bit fromthe destination operand specified by op1 The re sult is then stored in op1 This instruction can be used to perform multiple precision arith metic FLAGS 2 V PRES E Setifthe value of op2 represents the lowest possible negative number Cleared oth erwise Used to signal the end of a table 2 Set if result equals zero and previous Z flag was set Cleared otherwise V Set if an arithmetic underflow occurred i e the result can not be represented in the specified data type Cleared otherwise C Setifa borrow
307. ister with its name and address willThese four bits specify the priority level ofa service be shown the specific section tieripheralt request Values from through Fh can be speci is associated with see chapter 8 The function of fied in this field where Fh represents the highest each single or multiple bit field of an interrupt con Priority level trol registeris describedin more detail in Interrupt requests that are programmed to priority ing paragraphs levels 15 or 14 i e ILVL 111Xb will be serviced xxIR Interrupt Request Flag by the PEC unless the COUNT field of the associ PENES ated PEC channel contains zero In this case the This bit is set by hardware whenever a service re request will be serviced by normal interrupt proc quest from source xx occurs The Interrupt Re essing Interrupt requests that are programmed to quest flag is automatically cleared upon entry to priority levels 13 through filvalway be serviced the interrupt service routine or upon service of thepy normal interrupt processing request by the PEC In the case of PEC service the Interrupt Request flag remains set if the For interrupt requests which selected for COUNT field of the selected PEC channel goes to Service by the method described above the LSB of zero see section 7 2 2 1 for details This allows IL VL represents the MSB of the associated normal CPU interrupt to respond to a completed Channel numb
308. it addressable 16 bit mode control registers named CCMO CCM1 2 11 2 Capture Compare Register CC2 Al and which are all organized identically location Bit Each register contains bits for the mode selection f Set at 1 allocate CC2 to timer 1 otherwise allo and timer allocation of four capture compare regis Cate CC2 to timer 0 ters The organization of CAPCOM mode control b10 to b8 ZCCMOD2 Capture Compare Register register CCMO and the organization of CAPCOM 2 Mode Selection mode control registers CCM1 CCM2 and See 8 3 are decribed below As the selection of the individ 57 acct Capture Compare Register CC1 Allo ual operating mode is identical for each of the cap cation Bit ture compare registers only a detailed description t set at 1 allocate to timer 1 otherwise allo of register CCMO is given The description forreg cate CC1 to timer 0 isters CCM1 through is identical except for the indices of the respective capture compare reg 06 to 04 CCMOD1 Capture Compare Register isters CC1 Mode Selection Table 8 3 lists the possible capture and compare eee modes which can be programmed for each cap b3 ACCO Capture Compare Register CCO Allo ture compare register The different modes are Cation Bit discussed in detail in thellowingsubsections If set at1 allocate to timer 1 otherwise allo cate CCO to timer 0 b2
309. k diagram of a serial channel in synchronous mode In synchronous operation pin TXDO P3 10 is used by ASCO to output the shift clock while RXDO P3 11 either serves as transmit data input or receive data output Channel ASC1 uses pins RXD1 P3 9 and TXD1 P3 8 for these purposes 8 4 1 2 1 Synchronous Data Transmission Figure 8 42 Serial Channel Synchronous Mode Block Diagram Reload Register SxR System Clock SxM 000b SxREN SxOEN TXDO P3 10 SxLB TXD1 P 3 8 Shift Clock Receive Shift i RXDO P3 11 Register SxTBUF RXD1 P3 9 Transmit Receive Buffer Reg SxRBUF Receive 0 1 157 SGS THOMSON V Boud Rate Timer Clock Serial Port Control SxOE Receive Int Request Transmit Int Request Error Int Request Transmit Buffer Reg VRDA1642 57 64 MIGRCELECTREMICS 8 Peripherals For datatransmission the transmit data buffer reg ister SOTBUF S1TBUF is loaded with the byte to be transmitted If bit SOR 1 and SOREN 0 in register SOCON S1R 1 and S1REN 0 in S1CON atthat time the LSB ofthe transmit buffer register will appear at pin RXDO RXD1 within 4 state times afterthis write operation has been exe cuted Subsequently the contents of the transmit buffer register are shifted out synchronous with the clock at the corresponding shift clock output pin TXDO TXD1 After the bit time for the 8th bit both pins TXDO and
310. k diagram of timer T3 in TSOTL can also be set or reset by software Bit timer mode TSOE Alternate Output Function Enable in regis ter T3CON enables the state of T3OTL to be an al ternate function of the external output pin 8 2 1 1 2 Gated Timer Mode T3OUT P3 3 For that purpose a 1 must be writ In the gated timer mode the same options for the ten into port data latch P3 3 and T3OUT P3 3 input frequency as for the timer mode anailable must be configured as output by setting direction see table 8 7 However the input clock to the control bit DP3 3 to 1 If 1 pin T3OUT timer in this mode is gated by the external input pin then outputs the state of T3OTL If T30E 0 pin Timer External Input which is an alter T3OUT can be used as a general purpose I O pin nate function of P3 6 Figure 8 18 shows a block In addition T3OTL can be used in conjunction with diagram ofthe core timer in this mode the timer over underflows as a trigger source for The gated timer mode is selected by setting bit the counter or reload functions of thexiliarytim T3M 1 T3CON 4 to 1 Bit T3M 0 T3CON 3 se ers Forthis purpose the state of T3OTL does not lects the active level of the gate Pin T3IN P3 6 have to beavailableat pin because anin must be configured as input i e direction control ternal connection is provided for this option Thisbit DP3 6 must contain 0 feature is des
311. l bus There The process of transferring two bytes sequentially fore an external byte wide address latch is re Over the external bus for any word access causes quired for the eight least significant address bitS he operation of the processor to slow down In An Address Latch fable ALE signal is gener fact this mode is not as fast as the other external ated by the on chip External Bus Controller EBC memory access modes However there is a cost to signify a valid address beingailableon Port0 advantage since inexpensive byte wide memories As long as memory segmentation is not disabled can be used Port 4 isadditionallyised as an output for the two A most significant bits of the required 18 bit detailed application example forthis externalbus configuration mode is showndppendixC Figure 9 3 16 18 Bit Address 8 Bit Data Multiplexed Bus Segment Port 4 WR RD ALE ST10x166 Port ADDR OE WR 8 Bit External Memory INSTR DATA VRO81628 sg SGS THOMSON 1 1 0 1 0 570 9 External Bus Interface 9 5 16 18 BIT ADDRESS 16 BIT DATA performance It is faster than the 8 bit data bus MULTIPLEXED BUS mode because a memory does not need to be ac cessed twice in order to fetch a word wide value This external bus mode can be selected if a word This advantage however is not totally utilized wide external memory is connected to the since addresses and data are time multiplexed on ST10x
312. l the end of a table 2 Set if result equals zero Cleared otherwise V Alwayscleared C Always cleared Setif the most significant bit of the result is set Cleared otherwise B O T amp oxKxvy Mveuoviy Onepav o Byteo XOR Rbn Rbm 51 nm 2 XOR Rb data 59 n 0 2 XOR 57 RR 4 XOR Rb Rw 59 n 10ii 2 XOR Rw 59 n 11ii 2 XOR reg mem 53 RR MM MM 4 XOR mem reg 55 RRMM MM 4 none S71 SGS THOMSON e MICROELECTRONICS APPENDIX B ST10x166 REGISTERS B ST10x166 REGISTERS This part of the Appendx contains a summary of tion Registers are summarized and ordered by ad all registers incorpored in the ST10x166 Section dress while Section B 3 lists all Special Function B 1 lists all CPU General Purpose Registers In Registers iralphabetial order Section B 2 all ST10x166 Specific Special Func B 1 CPU GENERAL PURPOSE REGISTERS must be programmed such that the accessed GPRs GPRs are always located in the internal RAM space All GPRs are always located in the internal CPU General Purpose Registers are accessed via RAM space GPRs are bit addressable the Context Pointer CP The Context Pointer Word Registers Address Address Eu cP 0 Fon CPU General Purpose Register Ro CPU General Purpose Register mE CORONA Lm Fan ou Generarpurpose neister woon 69 5 Fan mo woon m m s rm CPU Gene
313. le 9 4 MCTC Encoding of the Memory Cycle Time Wait States Number of Additional Delay Wait States atfosc 40MHz ns 12 20 Ga SGS THOMSON MICROELECTRGNICS 9 External Bus Interface Figure 9 10 Memory Cycle Time Memory Cycle Time ALE Xo orem ate WR VROB1533 Figure 9 11 Memory Cycle Time Wait States Woit States SEGMENT Address ALE BUS PO Address An 1 l 1 sus Po 5cS THOMSON 0155 9 External Bus Interface The ST10x166 allows the user to adjust the time The ST10x166 allows the user to program 0 or 1 between twosubsequentmemory accessestoac default after reset Memory Tri State Time wait count for the Tri State Time of the external memory state by means of the MTTC bit in the SYSCON being used Tri State time is the timequired register as shown in table 9 5 One Memory Tri by the memory to release the bus once the mem State Time Wait State requires half a machine cy ory read RD signal has been deasserted As cle 50ns at sc 40MHz shown in figure 9 12 the Memory Tri State Time determines how quickly one memory access 9 5 Encoding of the Memory Tri State follow another Time Wait State If an external memory is too slow in releasing the bus after a memory read access the controller MTTC must wait for putting the next address on the bus Introduce One Wait State
314. le the interrupts when has to be performed the normal mode and from N write mode as they would not be served if the the FLASH memory ONLY program code is the FLASH memory MOV MEM Rn When the FLASH memory is apped in seg ment 1 some care must be taken for tlmanage where MEM is any even absolute address in the mentor merrupis cuting MR mode FLASH memory space The RPROT bit of FCR bit The unlock sequence and the 32 bit program 2 of Rn must be reset the other bits of FCR Ming sequence must not be interrupted protected in the normal mode and are not affected All erase or programming operations and verify se MOV Rn Rn When the protection is disabled reading of the quences can be interrupted if no FLASH reading is FLASH memory can be performed from all in performed from an external program internal RAM ternal or external memory Access to FCR reg or external memory during the interrupt ister and the FLASH programming or erase To exit from the Write mode to the normal mode operations is available only after having en the fdlowingnstruction has to be performed tered the Write mode MOV MEM Rn where bit 15 of Rn must be 0 to disable the Write mode FWMSET and MEM is any even absolute address in the FLASH memory space Note When the segmented memory mode is en abled the data page pointer must bemsidered for all FLASH memory accesses 4 8 yy 3GS THOMSON VicReRu
315. liableand cost effective memory A Flash memory cell consists of a single transistor with a floating gate for charge storage like EPROM the main that Flash memory uses a thinner gate oxide 1 Phaon cL Enpou XeAA CONTROL GATE FLOATING GATE OXIDE OXIDE NT N N SOURCE SOURCE DRAIN FLASH CELL EPROM CELL ROB EUR PROGRAMMATION HOT e INJECTION PROGRAMMATION HOT e INJECTION ERASURE THROUGH TUNNEL OXIDE ERASURE UV F N MECHANISM BULK ERASURE OF ENTIRE MEMORY IN 1SEC RANGE AN490 10 91 1 19 This isadvance information from SGS THOMSON Details are subject to change without notice MEMOPY The programming mechanism of a cell is based on hot electron injection This means that the cell control gate and drain are set to a high voltage and the cell sourcgriunded The high voltage on the drain generates hot electrons through the channel and the high voltage on the control gate traps the free elec trons into the floating gate 2 Paon Kear Mexnaviou Veo Vep CONTROL GATE FLOATING GATE VROO16E2 The cell erase mechanism is based ondler Nodheim tunneling This means that the cell control gate is grounded the cell drain is disconnected and the high voltagpigedto the cell source The high elec tric field between the floating gate and the source removes electrons from the
316. lication Example Table C 5 Non Multiplexed Memory Read With Read Write Delay Symbol 40MHz Clock Variable Timing Address to Valid Data In atc t7 n1 50 tacc lt 4TCL 25 n1 x 2TCL gt tw 50 1 5 n12 25 2TCL 2 RD to Valid Data In e lt 2 50 toe 2TCL 15 n2 x2TCL n2 gt taw 50 0 7 2 gt toe 15 2TCL 1 tar Data Float afterRD tar lt bo n3 x 50 lt 2 15 n3 x 2TCL n3 lt tar 50 0 7 n3 tat 15 2TCL 1 ALE Cycle Time t 2100 50 t ATCL n x 2TCL Note If the external memory is only used for code be longer than specified here In this case max n1 n2 because n3 0 ALE Cycle Time Memory Cycle Time 4TCL 100ns at 40MHz li4 7 020 See Device Specification Section Table C 6 Non Multiplexed Memory Read With Read Write Delay Quick Table Ey SGS THOMSON 9 10 MICROELECTRONICS C Application Examples Table C 7 Non Multiplexed Memory Write With Read Write Delay Symbol 40MHz Clock Variable Timing Write Pulse Low Time wW lt t2 n1x50 tw 2TCL 10 n1 x 2TCL 1 gt tw 50 0 8 gt tw 10 2TCL 1 Data Valid toWR laws 2 n2x 50 tiw lt 2TCL 15 2 2TCL n2 gt taw50 0 7 2 gt law 15 2TCL 1 Data Hold afteWR tan lt tea tah lt 2TCL 10 tdh lt 15 Address Setup lt t6 t 2TCL 25 tas lt 25 t ALECycdeTime ALE
317. lization This program memorydsableddur with internal program memoeyabled of external ing reset with the pirBUSACT high and the memory are really eailablein segment 0 external bus configuration pins EBC1 and EBCO the bus mode for external memory accessesis se low This mode is named the Single Chip Mode jected during reset by means of the external bus For further details about the external bus configU configuration pinsB SACT EBC1 and EBCO ration see chapter 9 According to there logic levels external memory The internal Program memory can be used for both accesses are eitheenabledor disabledduring re code and data storage The highest possible code set as shown in chapter 9 The selected external storage location in this memory is 07FFEh for 16 bus configuration is saved in the BTYP bit field in bit instructions or 07FFCh for 32 bit instructions Athe SYSCON register During thieitializa bn rou branch instruction reeededto cross the boundary tine however the user has the option bange between the internal Program memory to the ex any configuration which was selected during reset ternal memory otherwise this would cause errone After the EINIT instruction only the external bus ous results configuration can be changed at any time No short addressing mode and bit addressable For further details about the external bus configu mode are allowed for any accesses to the internal ration and control see chapter 9 External Bus In Program memo
318. ll outputs including pins configured as outputs disconnected 2 This parameter specifies the time during which the input capaci tance can be charged decharged by the external source It must be guaranteed that the input capacitance is fully loaded within these 63 TCLs AC CHARACTERISTICS Refer to the ST10F166 Data Sheet for AC charac teristics VCC 0 2 70 63 TCL 390 TCL 2 5 63 is 1 575us at20MHz CPU clock After the end of the sample time ts changes of the analog input voltage have no effect on the conversion result 3 This parameter includes the sample time ts 390 TCL is 9 75us at 20MHz CPU clock 4 IREF in Power Down Mode TBD 5 This parameter specifies the static input current for an analog in put channel e g when the channel is not selected for conversion 4 6 SGS THOMSON o AI nicotine PACKAGE MECHANICAL DATA ORDERING INFORMATION ST10166AQ1 ST10166AQ6 ST10R166AQ1 ST10R166AQ6 ST10166BQ1 ST10166BQ6 ST10R166BQ1 ST10R166BQ6 ST10166CQ1 ST10166CQ6 ST10R166CQ1 ST10R166CQ6 40MHz 40MHz 8041500 ST10166 ST10R166 inches 0120 2005 23201 2345 0904 ooro oes os zo 0 087 ossi osss e ess fos e os EN 0 to 70 PQFP100 40 to 85 0 to 70 C PQFP100 40 to 85 C to 70 C 40 to 85 C to 70 C PQFP100 40 to 85 C to
319. lyg The following sections describe the functional Serviced When an interrupt is amp nowledgedthe blocks of the ST10x166 and intertions between state of the machine is saved on the inter these blocks nal system stack and the CPU branches to the sys tem specific vector for the peripheral The PEC contains a set of SFRs which store the count value and control bits for eight data transfer channels In addition the PEC uses a dedicated area of RAM which contains the source and desti nation addesses is controlled similar to PLA outputs based on the selected opcode No mi qesired configuration of each channel crocode is used andach pipdine stage receigs control signals staged in control registers from the decode stage PLAsPipelineholds are primarily 1 2 3 Internal RAM caused by wait states for external memory qual port 512 by 16 bit internal RAM provides cesses and cause th oldingpf signals inthecon fast accessto General Purpose Registers trol registers Multiple cycle instructions data and system stack A uniqutecoding performed through instruction injection and simpl amp cheme provides flexible user register banks in the internal state machines which modify required con jjternal memory while optimizing themaining 1 2 1 16 Bit CPU trol signals RAM for user data Hardware detection of the selected memory space 1 2 1 2 ARITHMETIC AND LOGIC U
320. med by an instruction are copied into this field By modifying this field After execution of an instruction which explicitly up the Priority 25 of the current CPU task can be dates the PSW register the condition flags can not be Programmed interpreted as described in the following because anyb11 This bit globallgnablesor disables ac explicitwrite to the PSW register supersedesthe con ceptance of interrupts dition flag values which are implicitly generated by the IEN 0 CPU Interruptsdisabled CPU Explicitly reading the PSW register supplies 1 CPU Interruptsenabled read value which represents the state ofthe PSWreg b10 HI DEN Bus Arbitration Enable Bit ister after execution of the immediately preceding in DEN 0 HOLD HLDA BREQdisabled struction HLDEN 1 HOLD HLDA BREGenabled E Flag The E flag can be altered by instruc Pin P2 13 P2 15are used for these functions tions which perform ALU or data movement op b9 b8 b7 R Reserved erations The E flag is cleared by those gt 7 m n instructions which can not be reasonably used P86 USRO This bit is provided as the user s gen for table searchoperationsin all other cases purpose flag the is setlependingon the value of the b5 MULIP This bit specifies that a multiply divide source operand to signify whether the end ofa operation was interrupted before completion search table is reached or not If the value of MULIP 0
321. ments 1 2 3 For PEC data transfers the modes if the selected DPP register points to data external memory in segment 0 can be accessed in page 3 Any word data access is made on an even dependert of the contents of the DPP registers via byte address Provided that the PEC source and the PEC source and destination pointers destination pointers are not required the highest possible word datstorage location in the internal ee PI RAM is address OFDFEh For PEC data transfers the internal RAM can be accessdddependenbf Whenever a reset a hardware trap or an interrupt the contents of the DPP registers via the PEC occurs or whenever a software TRAP instruction source and destination pointers is executed and provided that internal program memory accesses are disabled program execu tion branches to an implicit external memory ad dress in pendent of the current CSP register contents expecting a jump vector being situate there For detailed information about the trap and interrupt jump vector table see section 7 1 Inter rupt System Structure All system stack operations are implicitly per formed by means of the Stack Pointer SP regis ter The GPRsare accessed via short 2 4 or 8 bit gaddressing modes irodlaboratiomith a particular Context Pointer CP register The channel num ber of a PEC data transferto be performed deter mines which PEC source or destination pointers will be implicitl
322. mer is derived from the internal sys easured or pulse multiplication to be performed tem clock divided by a programmable prescaler Without software overhead while Counter Mode allows a timer to be clocked in referenceto external events 27 A D CONVERTER Pulse width or duty cycle measurementis supported in Gated Timer Mode where the operation of atimer For analog signal measurement a 10 bit A D con is controlled by the gate level on an external inputverter with 10 multiplexed input channels and asam pin For these purposes each timer has one associ ple and hold circuit has been integrated on chip It ated port pin which servesas gate or clock input Theuses the method of successive approximation which maximum resolution of the timers in the GPT1 mod returns the conversion result for an analog channel ule is 400ns 6sc 40MHz within 9 795 fosc 40MHz The count direction up down for each timer is pro Overrun error detection capability is provided for the grammable by software For timer T3 the count di conversionresult register an interrupt request willbe rection may additionally be altered dynamically by angenerated when the result of a previous conversion external signal on a port pin to facilitate e g positionhas not been read from the result register at the time tracking the next conversion is complete Timer T3 has an output toggle latch which changes For applications which require less than 10 analog its state on eac
323. mi cause the SYSCON register isnitialied during nated with the EINIT instruction This instruction reset to the slowest possible memory configura has been implemented as a protected instruction tion To select the desired memory configuration Execution of the EINIT instruction disables the ac and the required access parameters one simply tion of the DISWDT instruction and causes the moves a constantto the SYSCON register thus en RSTOUT pin to go high see also figure 11 2 This suring that proper synchronization between the ex Signal can be used to indicate the end of the initiali ternal memory and the ST10x166 is achieved The zation routine and the proper operation of the mi external bus configuration options are described irf o controller to external hardware detail in section 9 1 To decrease the number of instructions required to11 6 THE BOOT STRAP MODE initialig the ST10x166 each peripheral is pro grammed to a default configuration upon reset butOn the ST10F166 256Bytes of ROM electrically is disabled from operation These default configu programmable are free to store the Boot Strap rations can be found in the descriptions of the indi Routine This routine defined by the user allows to vidualperipheralsn chapter 8 pass round the immediate branch at the address During the software design phase portions of the 0000h in single chip mode internal memory space must be agmedtoregis This program has to be loaded with the Fl
324. mponents being used The Address Latch En when ALECTL1 is set to 1 any access within the able signal is required to trigger an external latchaqqress range defined by the ADDRSEL1 register which captures the address Then after a period of is lengthened by one amp 25ns at 20MHz time during which the address has been latched cpy clock and the address hold time after ALE is the address is removed from the 0x166 sbus lengthenedby one If the external component need a longer address Figure 9 15 illustrates the bus cycle timing when setup and hold times the ST10x166 s ALE pulse is set Figure 9 15 Timing With ALE Lengthening Multiplexed Bus CLKOUT 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Normal Memory Cycle Lengthened Memory Cycle Multiplexed Bus Multiplexed Bus VRDA1520 sGs THomson 70 9 External Bus Interface 9 8 5 Switching between the Bus Modes As mentioned before it is possible to switch from With the features of the ST10x166 the different 8 bit data bus to a 16 bit data bus and vice bus modes and BUSCONI register it is possi Versa and to switch between anda ble to switch the bus characteristics on the fly 0n multiplexed bus There exists one condition One can change the number of wait states switch POWever which presents a special case When from a nultiplexecbus to a non multiplexed bus or SWitching from a
325. mum baud rate that can be achieved for the asyn Reset Value 0000h chronous modes when using a 40MHz oscillator is SOTIC FFGCh B6h WA 8 4 2 2 SYNCHRONOUS MODE BAUD RATES d 5 i 5 2 In the synchronous mode the baud rate ators provide 4 times the rate of the desired baud rate Therefore the underflow rate coming from the baud rate timers is additionally divided by four The maximum baud rate that can be achieved in SORIC FF6Eh B7h synchronous operation when using a 40MHz oscil 7 6 5 4 3 2 1 0 lator is 2 5 MBaud Generally the baud rates and Bsync1 for the serial channels in syn chronous operation are determined as follows BEDS LS SOEIC FF70h B8h 7 6 5 4 3 2 1 0 m mm 88801 E SOEIR SOEIE ILVL GLVL 16 x lt S1 BRL gt 1 When SxBRS 1 these formulas are S1TIC FF72h B9h 0 2 fosc fc Oa cR 222 0 3 16 lt 5 0 1 gt 1 S1RIC FF74h BAh 7 6 5 4 3 2 1 0 S1EIC FF76h BBh 7 6 5 4 3 2 1 0 60 64 SGS THOMSO lI 7572 SaS THOMSON 8 Peripherals 1 z2 fae 3 16x lt S1BRL gt 1 8 4 3 Serial Channels Interrupt Control Three bit addressable interrupt control registers are provided for each serial channel Registers SOTIC and S1TIC control the transmit interrupt registers SORIC and S1RIC control the receive in terrupt and registers SOEIC and S1EIC control the error inter
326. n Bit 16 TOL If set at 71 will enable counter mode otherwise Pro 16 12 STORER A E enable timer mode m osc F b10 to b8 T1I Timer Counter 1 input Selection 16x 2 TIREL x27 Bits fosc See table 8 1 and 8 2 for more information on the input The timer inputr amp quencies resolution and peri 2 ums ods which result from the selected prescaler option m 2108 ae deir i tees in TOI or when using a 40MHz oscillator are i listed in table 8 1 The numbers for the timer peri TOM Timer Counter 0 Mode Selection Bit ods are based on a reload value of 0000h Note If set at 1 will enable counter mode otherwise that some numbers may be rounded to 3 signifi enable timer mode cant digits b2 to 00 z TOI Timer Counter 0 input Selection Bits See table 8 1 and 8 2 for more information on the input n SGS THOMSON 56 MICROELECTRGNICS 8 Peripherals Table 8 1 CAPCOM Timers TO and T1 Input Frequencies Resolution and Periods Timer Input Selection T01 T1I 000b 001b 010b 011b 100b 101b 110b 111b sme nme some After a timer has been started by setting its run flagfor T1 This is the only option for T1 and it is se TOR or to 1 the first increment will occur lected by the ombinatiomT112X00b When bit field within the time interval which is defined by the se T1l is programmed to other combinations timer T1 le
327. n can then be used jue tion with this in struction to form common high leke iguageFOR loops of any range FLAGS E 2 V E Setifthe value of op2 representsthe lowest possible negative number Cleared oth erwise Used to signal the end of a table 2 Set if result equals zero Cleared otherwise V Set if an arithmetic underflow occurred i e the result can not be represented in the specified data type Cleared otherwise C Setifaborrow is generated Cleared otherwise Setif the most significant bit of the result is set Cleared otherwise INSTRUCTION FORMAT BXO Taoxtivy Mvepnovux Mvenovux Onepav o Byteo Rwn data 80 n 2 CMPI1 CMPI1 Rw dataig 86 Fn 4 CMPI1 CMPI1 Rwymem 82 MM MM 4 57 S65 THOMSON He o MICROELECTRGNICS A Ivotpux tiov Let XMIII2 XMIID Ivypeuevt By 2 XMIID 1 2 OPERATION 0 1 0 2 1 op1 2 DATATYPES WORD This instruction is used to enhance the performance and flexibility of loops The source op erand specified by op1 is compared to the source operand specified by op2 by performing a 2 s complement binary subtraction of op2 from op1 Operand op1 may specify ONLY GPR registers Once the subtraction has cpleted the 1 is incremented by two Using the set flags a branch instruction can then be used in conjunction with this in struction to f
328. n en abledif T6OE 1 b7 Timer 6 Up Down Control T6UD 0 Timer 6 is counting up T6UE 1 Timer 6 is counting down b6 T6R Timer 6 Run Bit Timer 6 runs if T6R 1 b2 tob0 T6I Timer 6 Input Selection See table 8 13 b2 tob0 T6I Timer 6 Input Selection See table 8 13 Table 8 13 GPT2 Timer Input Frequencies Resolution and Periods Timer Input Selection T2l T3l T4l see cob ow 100 wib 110b iib Prescaler for fosc e ge se w sz 10 Input Frequency 2 5MHz 1 25kHz 625kHz 312 5kHz 156 25kHz 78 125kHz 39 06kHz Resolution tion can be controlled by software through bit T6UD 8 2 2 1 1 Timer Mode Timer T6 is clocked with the internal system clock divided by a programmable prescaler Eight differ ent prescaler options can be selected by bit field T6l in control register 6 The input frequency fre to timer T6 is scaled linearly with slower oscilla 157 SGS THOMSON tor frequencies and is determined as follows The resulting inputfrequency resolution and timer period when using a 40MHz oscillator is illustrated in table 8 13 This table also applies to GPT2 aux iliary timer T5 Note that the numbers may be rounded to 3 significant digits 37 64 MIGRCELECTREMICS 8 Peripherals An overflow or underflow of timer T6 will clock the toggle bit T6OTL in control register T6CON T6OTL can also be set or reset by software
329. n op1 FLAGS E 2 V E Setifthe value of op1 represents the lowest possible negative number Cleared oth erwise Used to signal the end of a table Z Set if result equals zero Cleared otherwise V Set if an arithmetic underflow occurred i e the result can not be represented in the specified data type Cleared otherwise C Setifa borrow is generated Cleared otherwise Setif the most significant bit of the result is set Cleared otherwise INSTRUCTION FORMAT BXO Taoxtivy Mvenoviy Mvenoviy Onepav o Byteo NEGB NEG Rn A1 nO 2 58 84 SGS THOMSO A A Ivotpuxuov Let NOII NOII No Orepatiov NOII OPERATION No Operation This instruction causes a null operation to be performed A null operation causes no change in the status of the flags FLAGS E 2 V x pe pe apad Not affected Not affected Not affected Not affected Not affected ZoO lt Nm INSTRUCTION FORMAT BXO Taoxtivy Mvepnovuxr Mvenuoviy Onepav o Byteo NOP NOP CC 00 2 57 S65 THOMSON a a MICROELECTRONICS A Ivotpux tiov Let OP OP OP onl 2 OPERATION 1 lt 1 2 DATA TYPES WORD Performs a bit wise logical OR of the source operand specified by op2 and the destination operand specified by op1 The result is then stored in op1 FLAGS 2 V C N ERES SUE E Setifthe value of o
330. n stored in op1 This instruction can be used to perform multiple precision arithmetic FLAGS E 2 V Setifthe value of op2 representsthe lowest possible negative number Cleared oth erwise Used to signal the end of a table 2 Set if result equals zero and previous Z flag was set Cleared otherwise V Set if an arithmetic overflow occurred i e the result can not be represented in the specified data type Cleared otherwise C Setifa carry is generated from the most significant bit of the specified data type Cleared otherwise Setif the most significant bit of the result is set Cleared otherwise INSTRUCTION FORMAT BXO Taokwy Mveuovt Onepav o Byteo ADDCB ADDC Rw Rwm 11 nm 2 ADDCB ADDC Rw Rw 19 n 10ii 2 ADDCB ADDC Rw Rw 19 n 11ii 2 ADDCB ADDC Rw datag 19 n 0 2 ADDCB ADDC reg datas 17 RR THE 4 ADDCB ADDC reg mem 13 RR MM MM 4 ADDCB ADDC mem reg 15RR MMMM 4 M A Ivotpuxuov Let ANA ANA AOA ANA ANA onl 2 OPERATION 1 1 op2 DATATYPES WORD Performs a bitwise logical AND of the source operand specified by op2 and the destination operand specified by op1 The result is then stored in op1 FLAGS E 2 V E Setifthe value of op2 representsthe lowest possible negative number Cleared oth erwise Used to signal the end of a table 2 Set if result equals zero Cleared otherwise V Alwayscleared C Always cleared N Seti
331. nd of conversion interrupt request may cause an interrupt to vector ADCINT or it may trig ger a PEC data transfer which stores the conver sion result from register ADDAT e g into a table in the internal RAM for later evaluation Note that the number of the converted channel is contained in the four most significant bits in register ADDAT When the conversion result has not been read out of register ADDAT at the time the next conversion is complete the previous result will be overwritten and interrupt request flag ADEIR in register ADEIC will be set This overrun error interrupt request of the A D converter may be used to cause an inter rupt to vector ADEINT The interrupt control regis ters which are associated with the A D converter are described below For more details on interrupts refer to chapter 7 8 4 SERIAL CHANNELS For serial communication with other microcontrol lers microprocessors and external peripherals the ST10x166 has two identical serial interfaces ADCIC FF98h CCh Interrupt Control Registers Reset Value 0000h 7 6 5 4 3 2 1 0 ADCIR ADCIE GLVL ADEIC FF9Ah CDh Interrupt Control Registers Reset Value 0000h 7 6 5 4 3 2 1 0 ADEIR ADEIE ILVL GLVL 49 64 MIGRCELECTREMICS 8 Peripherals Figure 8 38 SFRs And Port Pins Associated With The Serial Channels Ports amp Direction Control Data Control Interrupt Alternate Functions Registers Registers Control Toss 5086
332. ng the implemented number of 16 priority levels to any smaller integer number This may be desirable to prevent a group of several different tasks with similar importance from interrupting each other It also reduces the stack depth For up request for interrupt or PEC service is completely programmable All enabled source requests must be programmed to different priorities which means that sources which are programmed to the same priority level must be programmed to different group priorities Otherwise undetermined results may occur for the interrupt vector Using the group priorities 0 through 3 up to 4 sources can be pro OCC grammed to the same priority level To prevent a group of more than 4 tasks with simi Y lar importance from interrupting each other the The advantage ofthis priority schemeis that the or first action within an interrupt service routine of der for servicing of simultaneous requests from dif each of these tasks could be to set the CPU Priority to 4tasks per group this can simply be done by as signing the associated interrupt sources to the same priority level in their ILVL field but to differ ent group priorities in their GLVL field 12 24 SGS THOMSON MIGRCELECTREMICS 7 Interrupt And Trap Functions field to the priority level ILVL of the source with For example an application may have 24 interrupt the highestpriority within this group In this way insources where these sources mus
333. ng and 16 bit programming routines are written as subroutines to allow easy inclusion in a user program The followingoutines are written in a way to clarify the operations as well as possible The initial conditions are described at the head of the routineeded 10 19 Gr SGS THOMSON TT MEMOP Y V ARIABLE DEFINI TIONSFOR THE FLASH M EMOR ROUTINES ALLO 0000 0h con stant 0 ALL1 OFFFFh con stant FFFF BLK START 0300 0h firsta ddres s of bank 1 FL_SIZ E 0300 0h size of bank 1 FCR 07FFEh dummy a ddres s ch osen for FCR ADDREV 0000 Ch add ress even le ast signi fican t bit ADDROD 0000 Eh add ress odd mostsi gnifi cant bit DATAH 09753h data to pro gram to odd addre ss DATAL 0864 2h data to pro gram to even address 1 0001 limitof the pr ogramming loop MAXLO 2 OOBB9h limit of the er ase loop UNLOCK 01000h data to unl ock the writi ng mode WAIT4 0000 Bh loop4 us WAIT10 0001 Fh loop10 us addrev RO evenad dress poi nter fcrval RT reg ister forFCRwri ting addrod R2 oddadd ress pointer datal reg ister with fi data datah RY reg ister withse cond data l pent R5 alg orith mloopc ounter allt R6 reg ister usedin EVM unlock R7 reg ister usedto unlock val10u Re cou nter 10us val4u RQ cou nter 4us wait c nt R10 reg ister to control wait loop fl scan R13 bankad dress poi nter f crrd R15 reg ister forFCRrea
334. ng while an ex chip Thus the Watchdog Timer is able to prevent ternal memory access is in progress If external the CPU from going totally astray when executing data are required but are not yewailable or if a erroneouscode After reset the Watchdog Timer new external memory access is requested by the starts counting automatically but it cardibsabled CPU before a previous access has been com via software if desired pleted the CPU will be held by the EBC until the re By any reset the CPU is forced intopredefined quest can be satisfied Chapter 9 is dedicated toa active state Further particular CPU states are The description of the external bus interfabeing IDLE state where the CPU clockis switched off and serviced by the EBC the peripheral clocks keep running and the The ST10x166 peripheals work nearly inde POWER DOWN state where all of the on chip pendent of the CPU with a separate clock gener clocks are switched off A transition into an active ator An interchange of data and control CPU state is forced by an interrupt if being IDLE or infornation between the CPU andhe peripherals reset if being in POWER DOWN mode re is done via Special Function Registers SFRs spectively The IDLE POWERDOWN and RESET Whenever peripherals non deterministically need states can be entered by particular ST10x166 sys a CPU action an on chip Interrupt Controller com tem control instructions For more information on pares all pending peripheral se
335. not be performed from another bank of the FLASH memory 6 8 3GS THOMSON C ACIE icReRuseTRONICS 4 Flash Memor Figure 4 3 Presto F Program Write Algorithm PROGRAM VERIFY READ COMPARE WITH DATA EXPECTED INCREMENT WRITE FWE 0 PT 100us VROO1632 SGS THOMSON 0 0 0 78 YF MICROELECTRONICS 4 Flash Memor Figure 4 4 Presto F Erase Algorithm ALL WORDS AT 0000H N D ADDRESS 0 WRITE ERASE COMMAND TO FCR WRITE ERASE DATA ERASE VERIFY READ COMPARE DATA FFFFH INCREMENT LAST ADDRESS ADDRESS S WRITE FWE O FEE 0 8 8 yy 3GS THOMSON ME icReluseTRONICS SGS THOMSON JJ MICROELECTRONICS CHAPTER 5 CENTRAL PROCESSING UNIT CPU 5 CENTRAL PROCESSING UNIT Basic tasks of the CPU are to fetch and decode in the priority of the current CPU operation is less structions to supply operands for the arithmeticthan the priority of the selected peripheral request and logic unit ALU to perform operations onan interrupt will occur these operands in the ALU and to store the pre Basically there are two types of interrupt process viously calculated results Since a four stage ing One type the standard interrupt processing line is implemented in the ST10x166 up to four forces the CPU to save the current program status instructions can be processedfarallel Section and the return address on the stack before branch 5 1 describes how thpipelineworks for sequential ino to th
336. nt is two s complement number which is sign extended and counts the relative distance in words The value of the IP used in the target address calculation is the address of the instruction fol lowing the JMPR instruction If the specified condition is not met program execution con tinues normally with the instructiohowinghe JMPR instruction CONDITION CODES See Table A 2 or A 1 next instruction FLAGS E 2 V Not affected 2 Not affected V Not affected Not affected N Not affected INSTRUCTION FORMAT BXO Taoxtivy Mvepnovtux Mven ovx Onepav o Byteo JMPR JMP cc rel cD rr 2 SGS THOMSO 47 84 7271 Paa ORGON l A Ivotpux tiov Let OMITX OMITX ABoodAvte SOUT SMIITX onl 2 OPERATION CSP lt 1 IP op2 Branches unconditionally to the absolute address specified by op2 within the segment specified by op1 FLAGS E 2 V C N E Not affected Z Not affected V Not affected Not affected N Not affected INSTRUCTION FORMAT BXO Taoxtivy Mvenoviy Mvenoviy Onepav o Byteo JMPS JMP seg caddr FA 0 00ss MM MM 4 48 84 Gr SGS THOMSON TTT A Ivotpuxuov Let ONB ONB Peate dvur 10 Bit XAEap ONB OT 2 OPERATION IF op1 0 THEN sign extend op2 ELSE END IF DATATYPES BIT If the bit specified by op1 is clear program execution continues at the location of the in struction pointer IP plus the specified
337. nt is then stored in the low or der word of the MD register MDL and the remainder is stored in the high order word of the MD register MDH E 2 V EEE TERED E Always cleared Z Set if result equals zero Cleared otherwise Set if an arithmetic overflow occurred Overflow occurs when the result can not be represented in a word data type or if the divisor op1 was 0 Cleared otherwise C Always cleared Setif the most significant bit of the result is set Cleared otherwise lt INSTRUCTION FORMAT Mvenoviy DIVL BXO Taoxtvy Mvenovux Onepav o Byteo DIVL RW 6B nn 2 57 S65 THOMSON M o MICROELECTRGNICS A Ivotpux tiov Let AIGAY AIGAY 32 16 Yvovyve Amorov AIGAY onl OPERATION DATA TYPES MDL MD op1 MD mod op1 WORD DOUBLE WORD Performs an extendednsigned32 bit by 16 bit division of the two words stored in the MD register by the source word operand op1 The unsigned quotient is then stored in the low order word of the MD register MDL and the remainder is stored in the high order word of the MD register MDH FLAGS E 2 V E Always cleared Z Set if result equals zero Cleared otherwise V Setif an arithmetic overflow occurred Overflow occurs when the result can not be represented in a word data type or if the divisor op1 was 0 Cleared otherwise C Always cleared N Setif the most significant bit of the result is set Cl
338. o Byteo SUBCB SUBC Rk Rbm 31 nm 2 SUBCB SUBC Rb data 39 n 0 2 SUBCB SUBC reg z datae 37 RR 4 SUBCB SUBC Rh Rw 39 n 10ii 2 SUBCB SUBC Rb Rw 39 n 11ii 2 SUBCB SUBC reg mem 33 RR MM MM 4 SUBCB SUBC mem reg 35 RR MM MM 4 57 S65 THOMSON MICROELECTRGNICS A Ivotpux tiov Let Yootoape ori OPERATION lt SP 2 SP PSW IF SYSCON SGTDIS 0 THEN SP SP 2 SP CSP CSP 0 END IF SP SP 2 SP lt IP IP zero extend 4 Invokes a trap or interrupt routine based on the specified operand op1 The invoked rou tine is detemined by branhing to the specified vector table entry point This routine has no indication of whether it was called by software or hardware System state is preserved identically to hardware interrupt entry except that the CPU priority level is not affected The RETI return from interrupt instruction is used to resume execution after the trap or inter rupt routine has completed The CSP is pushed if segmentatiam sbled This is indi cated by the SGTDIS bit in the SYSCON register FLAGS E 2 V C N E Not affected Z Not affected V Not affected Not affected N Not affected INSTRUCTION FORMAT BXO Taoxvy Mvenoviy Mvenoviy Onepav o Byteo TRAP TRAP 9B 1 110 2 82 84 SGS THOMSO AJ M A Ivotpuxuov Let EE
339. o which compare register CCx is allocated Figure 8 8 showsthe timing example from the pre has no effect on pin P2 x nor does it disable or en Vious section now for compare mode 1 The func able further compare events tional block diagram of a compare register in compare mode 1 is included in figure8 6 of the pre In order to use pin P2 x CCxlOas compare signal vious section Note that in compare mode 1 the output pin for compare register CCx in compare port latch is toggled upon each compare event For operation in thedouble regiter compare Ey SGS THOMSON 13 64 MICROELECTRONICS 8 Peripherals Figure 8 8 Timing Example for Compare Mode 1 Contents of Ty FFFFh Compare Value CCz Compare Value Reload Value TyREL gt 0000h Interrupt Requests CCxIR CCzIR TyIR CCxIR CCzIR State of CCxlO 1 Nb _ 0 VR001639 8 1 2 2 3 Compare Mode2 for compare register CCx until the allocated timer Compare mode 2 is an interrupt only mode similar This means that after the first match to compare mode 0 but only one interrupt request when the compare registerrieloadedwith per timer period will be generated Compare mode Value higher than the current timer value com 2 is selected for register CCx by setting bit field Pare event will occur until the next timer period CCMODx of the cotespondingnode control regis Figure 8 9 shows a functional diagram of
340. ocary tt ceur cs1 Unsignediessthan gh ceure 40 1 unsignediessthanauai Fh MI _ 20 0 greaterthan eh __ _ sgnedlesstham co ste jSignedlesstanoqua enh PICNNE z Nov eo greaterthan ah amp E 0 jNotequalANDnotendoftable in vg SCS THOMSON 5 YF MICROELECTRGNICS A Ivotpux tiov Let XOVOLTLOVAA BOUT onl 2 OPERATION IF op1 THEN IP lt 2 ELSE END IF If the condition specified by op1 is met a branch to the location specified indirectly by op2 is taken If the condition is not met no action is taken and the next instruction is executed normally CONDITION CODES See Table A 2 or A 1 next instruction FLAGS E 2 V Not affected 2 Not affected V Not affected C Notaffected N Not affected INSTRUCTION FORMAT BXO Taoxtvy Onepav o Byteo JMPI JMP cc Rw 9C cn 2 46 84 S6S THOMSO y cA eer A Ivotpuxuov Let OMIIP Peate SMIIP 2 OPERATION IF op1 THEN sign extend op2 ELSE END IF If the condition specified by op1 is met program execution continues at the location of the instruction pointer IP plus the specified displacement op displacere
341. ode for the auxiliary timersThe second count source is the toggle bit T3OTL of functions as described for the core timer In addi the core timer One can also select either a tion however timers T2 and T4 offer the possibility positive a negative or both a positive and a nega of selecting between two count sources The firsttive transition of TSOTL to cause an increment or source is an external input pin T2IN for timer T2 decrement Note that only state transitions of and T4IN for timer T4 One can selecteithera posi T3OTL which are caused by the overflows under tive a negative or both a positive and a negative flows of T3 will trigger the counter function of transition to cause an increment or decrement T2 T4 Modifications of T3OTL by software will The direction control bits DP3 7 for T2IN or DP3 5 NOT trigger the counter function of T2 T4 Ta for TAIN must be set to 0 and the input signal ble 8 10 summarizes the different counter modes should be heldat least8 states for correct edge de of the auxiliary timers A block diagram of an auxil tection which results in a maximuatiowedfre iary timer in counter mode is shown in figure 8 22 uc count input signal of 1 25MHz at Using the toggle bit T3OTL as a clock source for an osc 40MHz auxiliarytimer in counter mode offers the feature of 57 S65 THOMSON SE MICROELECTRGNICS 8 Peripherals Table 8 10 GPT1 Auxiliary Timers Counter Mode Input Selection x 2 or4
342. of injected in As mentioned in the introductional part of thisstructions too Although one will not notice these chapter a four stage instructiqripelineis imple mented in the ST10x166 This means that instruc internallynjected instructions in reality they are in troduced here to ease the explanation of the pipe tion processing is partitioned in four stages ofline thefollowing which each one has its individual task as follows 1st gt FETCH In this stage the instruction se lected by the Instruction Pointer and the Code Seg ment Pointer is fetched from either the internal ROM or FLASH memory internal RAM or external memory 2nd DECODE In this stage the instructions are decoded and if required the operand addresses are calculated and the resultingperands are fetched For all instructions which implicitly acces the system stack the SP register is either decre mented orincrementedas specified For branch in structions the Instruction Pointer and the Code Segment Pointer are updated with the desired branch target addresses provided that the branch is taken 3rd gt EXECUTE In this stage an operation is performed on the previously fetchegerandsin the ALU Additionally the condition flags in the PSW register are updated as specified by an in Figure 5 1 Sequential Instruction Pipelining 1 Machine lt 5 1 1 Sequential Instruction Processing Each single instruction has to pass through e
343. of the class B trap is stored in the TFR register but the IP value of the instruction which caused this trap is lost In the case where e gan UndefinedOpcode trap occurs simultaneously with an NMI trap both the NMI and the UNDOPC flag is set the IP of the in struction with the undefined opcode is pushed onto the system stack but the NMI trap is executed Af ter return from the NMI service routine the IP is popped from the stack and immediatq iyshed again be cause of the pending UNDOPC trap 7 3 2 1 EXTERNAL NMI TRAP Whenever a high to low transition on the dedicated externalNMI pin Non Maskable Interrupt is de tected the NMI flag in register TFR is set and the CPU will enter the External NMI trap routine The IP value pushed on the system stack is the address of the instructiofollowinghe one after which nor mal processing was interrupted by the NMI trap 7 3 2 2 STACK OVERFLOW TRAP Whenever the Stack Pointer value is decremented to a value which is less than the value in the Stack Overflow register STKOV the STKOF flag is set in Set when the opcode of the instruction currentlythe TFR register and the Stack Overflow trap is en in decode is nota valid ST10x166 opcode Must tered Which IP ulue willbe pushed onto the sys be reset by software PRTFLT Protection Fault Trap request flag Set when anillegalformat of a protected instruc tion is detected Must be reset by software b2 ILLOPA Illegal Word Operand
344. ogical operators This secton defines and explaingems which are Masy onepatiove mentioned in each single instruction description Instruction name syntax operational description data type condition flags addressing modes 10 lt is MOcEA into opX mats and number of bytes is AAAEA to opY opY is XYBTPAXTEA from opX E e Aun NOHE RS is MYATIIIAIEA by opY pecifies the mnemonic opcode of the instruction overszed bold lett ng for easy reference aa a ALAPA by opY mnemonics have been chosen with regard to the is logically NAed with opY particular operation which is performed by the is logicallyOPed with opY is OP ed with opY A 1 2 lt is XOMIIAPEA against opY Specifies the mnemonic opcode and thaquired mod is opY formal operands of the instruction as used in the followingsubsection Operation There are in structions with either none one two or three ands which must be separated from each other by omepatop on commas is logicall OMIIAEMENTEA MNEMONIC op2 0 e iae Md Missing or existing parentheses signify whether The syntax for the actual operands of an instruc the used operand spec
345. ogramming Clear WDWW bit for word programming Set FWMSET bit for write mode Take careat this point asthis step prepares the device for programming but does not activate the process mov fcrval ALLO reset FCR data value bset fwe FWE 1def ine progr ammingop erati on belr ckctlO CKCTIO 0 belr ckctl1 0 de fine 100 us pulse bset wdww fine 32 6 itc onfig on bset fw mset FWMSE 1 enabl e pr ogram mode mov FCR fcrva load FCR with the desired value DAL a 00peoo The followingcommand starts automatically the programming process For word programming mov addrev dat al progr amming co mmand For double word programming mov addrev dat al progr amming co mmandeven word mov addrev dat ah progr ammingco mmandodd word 4 19 3GS THOMSON IE YZ MICRGELECTRENIGS 5 IIPEXTO o Qpute AAyopitnu PROGRAM VERIFY READ COMPARE WITH DATA EXPECTED INCREMENT LAST ADDRESS ADDRESS ES WRITE FWE 0 VROO1632 n SGS THOMSON 5 19 e MIGROELECTRONICS MEMOPY OAITIIT The programming time PHependson the bits CKCTLO amp CKCTL1 of FCR see setting of FCR The end of programming can be detected by polling on the FBUSY bit of FCR FBUSY set to 1 indicates programming is in progress FBUSY cleared indicates programming has ended w
346. ogramming operations arellowed for each woww cKcTLO VPPRIV FCVPP FBUSY FEE FWE word Each program operation n of gram command the programming is then automat Si ically performed After a time out ofsla Program Verify is then performed which compares data out As FCR is a virtual register all bits previously writ put with data expected This sequengearantees ten must be confirmed in the same state at each that each is programmedliably FCR writing especially FWMSET Figure 4 3 illustrates the Presto F Program Write Perform the erase command Algorithm e g MOV RO RO Asthe program pulse varies in inverse ratio to the This special instruction for erase guarantees us frequency 400 TCL the number of operations ers against inadvertent operation allwed varies also FLASH erase will automatically start The ERES TEL WRIT Gbs S To SONS erase time depends on CKCTLO 1 bits of FCR End of erase is detected byollingon the PRESTO F ERASE ALGORITHM FBUSY bit of FCR Erasing with Presto F algorithm allows the electri Test FCVPP bit of FCR to verify that VPP had ally erasing of the selected Bank imeliableway the correct voltage during erase The algorithm starts by first programming all the Then all the FLASH memory must be read to words to 0000h in order to perform an uniform era verify the completely correct erasure After era Sure This step is performed by using the P
347. ol Register Port 3 Data Register Port 2 Direction Control Register Port 2 Data Register CAPCOM Timer 0 Register CAPCOM Timer 0 Reload Register CAPCOM Timer 1 Register CAPCOM Timer 1 Reload Register cco CC15 CAPCOM Registers 0 15 01 CAPCOM Timer 0 and Timer 1 Control Register CCM3 CAPCOM Mode Control Registers 0 3 TOIC CAPCOM Timer 0 Interrupt Control Register CAPCOM Timer 1 Interrupt Control Register CCOIC CC15IC CAPCOM Register 0 15 Interrupt Control Registers 4 64 SGS THOMSON O_O 8 Peripherals 8 1 1 Timers TO and T1 In all modes both timer TO and timer T1 are always The primary use of the timers TO and T1 is to pro Countng upwardThe current timer values are ac vide twdndependentime bases 400ns maximum cessible by the CPU in timer registers TO and T1 resolution for the capture compare registers but Which are both non bit addressable SFRs When they may also be usedndeperdent of the cap TO or T1 are written by the CPU in the state imme ture compare registers diately before a timer increment or reload is to be performed the CPU write operation has priority and the increment or reload isabledto guaran tee correct timer operation The functions of the timers TO and T1 are control led by the bit addressable 16 bit control register T01CON described below T1 is controlled by the upper byte and TO is controlled by the lower byte of TO1CON TOR and
348. on the MDC register must first p15 to b8 R Reserved be saved along with the MDH and MDL registers b7 to b5 b3 to b0 to be able to restart the interrupted operation later and then it must be cleared to peepared These bit portions are used by the machine for for the new calculation After completion ofthe new COntrollingmultiply and divide operations inter nally Thus they should never be modified by the division or multiplication the state of the inter userexceptatter having saved the previous MDC rupted multiply or divide operation must be re 4 Ply contents by restoring the MDC register stored i 64 MDRIU MD Register Use Flag The MDRIU flag is the only portion ofthe MDC re 222 ister which might be of Interest for the user The re Is setto 17 when the MDL or MDH register is writ maining portions of the MDC register are reserved ten by software or when a divide or multiply in for a dedicated use by the hardware and thus they Struction is executed This MD Register in should never be modified by the user other thanas Use Flag is cleared when the MDL register is described in thprecedingparagraph Otherwise ead by software a correct continuation of an interrupted multiply or divide operation can not kguaranteed After reset this register is initialized 600h ONES FE1Eh 8Fh A detailed description of how to use the MDC reg constant Ones Register ister for programming multiply
349. on is not metor that a cache jump is taken Instructions executed from the internal RAM re For 4 byte instructions quire the same minimum time as if being fetched Timin ext 2xACTs lmi ROM 2 x States from the internal ROM plus an instruction lengthFor instructions fetched from an external memory dependert number of state times as follows via an 8 bit data bus the minimum number of re For 2 byte instructions quired ALE Cycle Times is twice the number for a Timin ROM 4 x States 16 bit bus Table 5 1 Minimum Instruction State Times Timin ROM Timin ROM a Any except the following N CALLI CALLA CALLS CALLR PCALL JB JBC JNB JNBS JMPS JMPA JMPI JMPR MUL MULU DIV DIVL DIVU DIVLU MOV B Rn Rm data 16 RET RETI RETP RETS TRAP N a hPHRROOHAHAHA 5 2 3 Additional State Times 1 Internal ROM operand reads Tiada 2x States As described in theoflowing some operand ac Both byte and word operand reads always require cesses can extend the execution time of an in 2 additional state times struction h Since the additionaltime Tiada 2 Internal RAM operand reads via indirect ad mostly caused by internal instructidp iningit ressina m often will be possible to evade these timing effects essing modes Dor T XState in time critical program modules by means of a Readinga GPR or any other directly addressed suitable rearrangement of the corpendim
350. onditional jumping to a relatively addressed target instruction within the current code seg Resetting the ST10x166 by software SRST Entering the Idle mode IDLE Entering the Power Down mode PWRDN Servicing the Watchdog Timer SRVWDT Disablinghe Watchdog Timer DISWDT Signifying the end of thaitialiation routine pullsRSTOUT pin high and disables the effect of any later execution of a DISWDT instruction mentdependingon the state of a selectable bit EINIT 2 8 SGS THOMSO i THORSON 6 Instruction Set Overview 6 1 12 Miscellaneous 6 2 ADDRESSING MODES a Null operation which requires 2 bytes of storage and the minimum time for execution The ST10x166 provides many powerful address NOP ing modes for access on word byte and bit data or to specify the target address of a branch instruc tion The addressing modes areibdividedn dif 6 1 13 Software Instruction Set ferent categories as follows BSO Tasking provides softwaredeveloprent E Nee al 6 2 1 Constants wi e Assembler a166 This accepts all assem bly language instruction that have The ST10x166 instruction set supports the use of been described before and adds a software in wordwideor bytewide immediate constants For an struction set which is an extension of the previousOPtimum utilization of thevailablecode storage hardware instruction set these constants are represented in the instruction formats by either 3 4
351. onsistent soft TFR can then be used to determine the type of the ware design chniques each source of an inter trap see section 7 2 for more details For the spe rupt or PEC request isuppliedwith a separate cial software TRAP instruction the vector address interrupt control register and interrupt vector Theis specified by the operand field of the instruction control register contains the interrupt request which is a seven bit trap number the interrupt enable bit and the interrupt priority Offhe reserved vector locations of the ST10x166 s the associated source Each source request is aC memory space form a jump table Here one can tivated by one specific evenegendingonthese place the appropriat jump instructions to the lected operating mode of the respective device memory locations where the interrupt or trap serv The only exceptions are the two ser amp annelsof routines will actually start The entries to the the ST10x166 where an error interrupt request iump table are located at the lowest addresses in can be generated by a parity framing or overrun code segment zero of the memory space Jump ta error However specific status flags which identifypje entries have a distance of 4 bytes between the type of error are implemented in the serial consecutive entries except for the reset vector and channels corrbl registers see section 8 4 for de the hardware trap vectors where the distance is 8 tails or 16bytes The ST10x16
352. ontains the logical negation of the previous state of the specified bit V Always cleared C Always cleared Contains the previous state of the specified bit INSTRUCTION FORMAT BXO Taoxtvy Mvenoviy Mvenoviy Onepav o Byteo JNBS JNBS bitadd q rel QQ rr qO 4 50 84 S amp S THOMSON A Ivotpuxuov Let MOc Mode orl 2 OPERATION 1 2 DATATYPES WORD Moves the contents of the source operand specified by op2 to the location specified by the destinaipn operandop1 The contents of the moved data is examined and tbedition codes are updated accordingly FLAGS E 2 V E Setifthe value of op2 represents the lowest possible negative number Cleared oth erwise Used to signal the end of a table 2 Set if the value of the source operand 2 equals zero Cleared otherwise V Not affected C Notaffected Setif the most significant bit of the source operand op2 is set Cleared otherwise INSTRUCTION FORMAT BXO Taoxtivy Mvenoviy Mvenovy Onepav o Byteo MOV MOV Rwn Rwm FO nm 2 MOV MOV Rwn data EO zin 2 MOV MOV reg datac E6 RR 4 MOV MOV Rwn A8 nm 2 MOV MOV Rwn RWn 98 nm 2 MOV MOV 8 2 MOV MOV Rwy Rws 88 nm 2 MOV MOV Rw Rum C8 nm 2 MOV MOV Rwn Rwn D8 nm 2 MOV MOV Rwn Rwn E8 nm 2 MOV MOV Rwn Rwm di6 D4 nm 4 MOV MOV RWn di6 RWh C4 nm 4 MOV MOV 84
353. or flag SOPE or S1PE is setindicating that the er ror interrupt request is due to a parity error If the overrun error detection enable bit SOOEN or S1OEN is set and the last character re ceived was not read out of the receive buffer by software or PEC transfer at the time recep tion of a new frame is complete the overrun er ror flag SOOE or S1OE is set indicating that the error interrupt request is due to an overrun er ror In the following subsections specific charac teristics of the individual operating modes for the asynchronous communication are described in more detail 8 4 1 1 1 8 Bit DataMode This mode is selected by programming the mode selection field SOM or S1M in register SOCON or S1CON to 001b The data frame which will be transmitted and or received consists of 8 data bits After a reception the upper byte of the receive buffer register contains zero The parity checking function upon reception is disabled in this mode 55 64 MIGRCELECTREMICS 8 Peripherals independent of the state of SOPEN and S1PEN The overrun and framing checks however can be enabled 8 4 1 1 2 7 Bit Data Parity Bit Mode This mode is selected by programming the respec tive mode selection field SOM or S1M to 011b The data frame which will be transmitted and or re ceived consists of 7 data bits and a parity bit All er ror checks may be enabled in this mode On transmission the parity bit is automatically gen
354. orm common high leke iguageFOR loops of any range FLAGS E 2 V E Setifthe value of op2 representsthe lowest possible negative number Cleared oth erwise Used to signal the end of a table 2 Set if result equals zero Cleared otherwise V Set if an arithmetic underflow occurred i e the result can not be represented in the specified data type Cleared otherwise C Setifaborrow is generated Cleared otherwise Setif the most significant bit of the result is set Cleared otherwise INSTRUCTION FORMAT BXO Taoxivy Mvepnovtux Mvenovy Onepav o Byteo CMPI2 CMPI2 Rwn data 90 n 2 CMPI2 CMPI2 Rw dataig 96 Fn 4 CMPI2 CMPI2 Rwymem 92 MM MM 4 32 84 SGS THOMSO A A Ivotpuxuov Let XIIA XIIA Ivteyep Oveo Xoun euevt XIIA orl OPERATION 1 1 DATATYPES WORD Performs a 1 s complement of the source operand specified by op1 The result is stored back into op1 FLAGS E 2 V E Setifthe value of the source operand op1 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table 2 Setif result equals zero Cleared otherwise V Alwayscleared C Always cleared N Setif the most significant bit of the result is set Cleared otherwise INSTRUCTION FORMAT BXO Taokwy Mvepnovux Onepav o Byteo CPL CPL 91 nO 2 57 S65 THOMSON M MICROELE
355. ormed in a single machine cy cept for multiply and divide An advanced Booth al cle gorithm has been incorporated to allow four bits to addition bit field instructions have been pro be multiplied and two bits to be divided per ma vided which allow the modification of multiple bits chine cycle Thus theseperationsrequire four one operand a single instruction and nine machine cycles respectively to perform a 16 bit by 16 bit or 32 bit by 16 bit calculation plus one machine cycle to setup and adjust the op 1 1 4 High Performance Branch Call and erands and the result Even these longer multiply Loop Processing and divide instructions can be interrupted duringp to the high percentage of branching in control their execution to allow for very fast interrupt applications branch instructions have been op sponse Instructions have also been provided to al timized to require one extra machine cycle only low byte packing in memory whifeovidingsign when a branch is taken This is implemented by extension of bytes for word wide arithmetic opera precalculating the target address wh ecoding tions The internal bus structure also allows trans the instruction To decrease loop execution over fers of bytes or words to orfrqreripheralSiased head three enhancements have been provided on the peripheralequiremer amp The first solution provides single cycle branch exe A setof consistentflags is automatically upda
356. ot affected 2 Not affected V Not affected C Notaffected N Notaffected INSTRUCTION FORMAT BXO Taoxtivy Mvenoviy Mvenoviy Onepav o Byteo PWRDN PWRDN 97 6897 97 4 66 84 S amp S THOMSON A Ivotpuxuov PEI PEI LvBpovtive OPERATION SP SP SP 2 Returns from a subroutine The IPppppedfrom the system stack Execution resumes at the instructioroflowinghe CALL instruction in thalting routine FLAGS E 2 V C N E Not affected 2 Not affected V Not affected C Notaffected N Notaffected INSTRUCTION FORMAT BXO Taoxtvy Mvenuoviy Onepav o Byteo RET RET CB 00 2 57 S65 THOMSON MICROELECTRONICS A Ivotpux tiov Let PETI PETI OPERATION FLAGS PEII Ivceppuz Povtive IP SP SP SP 2 IF SYSCON SGTDIS 0 THEN CSP SP SP SP 2 END IF PSW SP SP SP 2 Returns from an interrupt routine The PSW IP and CSP are popped off the system stack Execution resumes at the instruction which had been interrupted The previous system state is restored after the PSW has beqropped The CSP is onlypoppedif segmentation is enabled This is indicated by the SGTDIS bit in the SYSCON register E 2 V 8 8 8 8 5 Restored from the PSW5oppedfrom the stack Restored from the PSW5oppedfrom the stack Restored from the
357. ount 2 0 0 DO WHILE count 0 V C v V C opo opin Op 1tns1 n 0 to 14 count count 1 END WHILE DATATYPES WORD Arithmetically shifts the destination word operand op1 right by as many times as specified in the source operand op2 To preserve the sign ofdhieginabperand the most sig nificant bits of the result are filled with zeros if thgimalMSB was 0 or with ones if the originaMSB was 1 The Overflow flag is used asRoundinglag The LSB is shifted into the Carry Only shift values between 0 and 15 areallowed When using a GPRas the count control only the least significant 4 bits are used FLAGS E 2 V isis E Always cleared Set if result equals zero Cleared otherwise V Setifin any cycle of the shift operation 1 is shifted out of the Carry flag Cleared for a shift count of zero C Carry flag is set according to the last LSB shifted out of op1 Cleared for a shift count of zero Setif the most significant bit of the result is set Cleared otherwise N INSTRUCTION FORMAT BXO Taoxtivy Mvenoviy Mvenoviy Onepav o Byteo ASHR ASHR Rw Rwm AC nm 2 ASHR ASHR Rw data BC n 2 57 S65 THOMSON Ie MICROELECTRGNICS A Ivotpux tiov Let BANA BANA Bit ANA BANA 2 OPERATION 1 0 1 0 2 DATA TYPES Performs a single bit logical AND of the source bit specified by operand op2 wit
358. p2 representsthe lowest possible negative number Cleared oth erwise Used to signal the end of a table 2 Set if result equals zero Cleared otherwise V Alwayscleared C Always cleared N Setif the most significant bit of the result is set Cleared otherwise INSTRUCTION FORMAT BXO Taoxtvy Mvenoviy Mvenoviy Onepav o Byteo OR OR Rwn Rwm 70 nm 2 OR OR Rwn datas 78 n 0 2 OR OR reg datag 76 RR 4 OR OR Rw 78 n 10ii 2 OR OR Rwn Rw 78 n 11ii 2 OR OR reg mem 72 RR MM MM 4 OR OR mem reg 74 RR MM MM 4 _ A Ivotpuxuov Let OPB OPB OP OPB onl 2 OPERATION 1 op1 v 2 DATATYPES BYTE Performs a bit wise logical OR of the source operand specified by op2 and the destination operand specified by op1 The result is then stored in op1 FLAGS E 2 V E Setifthe value of op2 representsthe lowest possible negative number Cleared oth erwise Used to signal the end of a table 2 Set if result equals zero Cleared otherwise V Alwayscleared C Always cleared N Setif the most significant bit of the result is set Cleared otherwise INSTRUCTION FORMAT BXO Taoxtivy Mvepnovuxr Mvenoviy Onepav o Byteo ORB OR Rb Rbm 71 nm 2 ORB OR Rb data 79 n 0 2 ORB OR reg dat s RR 4 ORB OR Rb Rw 79 n 10ii 2 ORB OR Rb Rw 79 n 11ii 2 ORB OR reg mem 73 RR MM MM 4 ORB OR mem reg 75 RRMMMM 4 57 S6S THOMSON SSS MICROELE
359. pe CODE In this stage the previously fetched instruction is decoded and therequiredperandsare fetched 1 6 1 Architectural Overview EXECUTE In this stage the specified operat 1 1 3 ExtendedBit Processing and Peripheral ion is performed on the previously Control fetchedoperands A large number of instructions has been dedicated WRITE BACK In this stage the resultis written to bit processing These instructions provide effi to the specified location cient control and testing peripheralswhile en hancing datamanipulation Unlike many current microcontrollers these instructions provide direct access to twooperandsin the bit addressable space withoutequiringnovement into temporary If this echniquewere not used each instruction would require four machine cycles This increased performance allows a greater number of tasks and interrupts to be processed flags The same logical instructiorasailablefor words 1 1 2 High Function 8 bit and 16 bit and bytes are also supported for bits This allows Arithmetic and Logic Unit the user to compare and modify a control bit for a Most internal execution blocks have been opti peripheralin one instruction Multiple bit shift in mized to perfornoperationson either 8 bit or 16 structions have beerncludedto avoid long in bit quantities Once theipelinehas been filled struction streams of single bit shift operations one instruction is completed per machine cycle ex These are also perf
360. pin P3 0 can recognized an external count input signal should be selected to cause an increment of TO be oe 8 state eee ge When T1 is programmed to run in counter mode ts level again The incremented count value ap 1 41 bit field T1lis used to enable the over Pears in SFR TO within 8 state times after the sig flows underflows of timer 6 as the count source transition at pin TOIN TABLE 8 2 Input Selection for TO and T1 in Counter Mode Counter TO is incremented Counter T1 is incremented on overiow runaeriow ararratiertd x o 91 ovortow or Undertow of GPT2 Timer PostveExerelTenaitonatPnTow x o _ Negative External TanstionatmTon weise Positive and Negative Transition at TOIN EVER Counter T1 stops 6 64 Gr SGS THOMSON TT 8 Peripherals 8 1 1 3 RELOAD TOIC FF9Ch CEh A reloadof a timer with the 16 bit value stored in its CAPCOM Timer TO Interrupt Control Registers associated reload register is performed in timer TOIC mode as well as in counter mode each time a timer overflows from FFFFh to 0000h The reload regis Peset Value 0000h ters TOREL and T1REL are not bit addressable 7 6 5 4 3 2 1 0 8 1 1 4 TIMER TO AND T1 INTERRUPTS b7 TOIR Timer 0 Interrupt Request Bit Upon timer overflow the corgesndingimerinter This flag can be used to generate an interrupt or rupt request flag TOIR or T1IR for the respective tr
361. ply or di register The low portion of the MD register MDL vide instruction was interrupted contains the integer result of the division while the BSET SAVED high portion of the MD register MDH contains the Save indication of stored state remainder PUSH MDH The overflow flag V is set if the result can not be Save previous MD contents represented in a word data type One must first copy the high portion of the MD register result into the register file or memory to ensure that the MDRIU flag is set correctly but one may write to either half ofthe MD register to set the MDRIU flag The followingnstruction sequence performs a 32 by 16 bit division PUSH MDL on system stack 2 8 yy 3GS THOMSON 13 System Programming MOV MDH HR1 Move dividendto MD register Sets MDRIV MOV MDL R2 Move low portion to MD DIV R3 Divide 32 16 signed holds divisor JB V ERROR Test for divide overflow MOV remainder to R3 MOV R4 MDL Move integer result to R4 Clears MDRIV R3 MDH Whenever a multiply or divide instruction is inter rupted while in progress the MULIP flag in the PSW of the interrupting routine is set When the in terrupt routine is exited with the RETI instruction this bit is implicitly tested before the old PSW is popped from the stack If MULIP 1 the inter Two types of stacks are provided in the ST10x166 The first type is used
362. povtive eGexvteo a ADOT 960 OTN THE avd vexecoupy Byteo Mia Trece otoped YOVOEXV pecovpyec THE wxepvo PAM onaye WoT pe Qe WTO THE LVTEPVAA 88 amp amp apea av Gapi 0 40 THAT THE ADOT to EELTES TO aeo addpeoo 40 16 Tne otope iv PAM 1 tev e exvted yose Tito npo TNE pode ebred Py ebs Seteputved By tHE LOY tne EPET wotpox tov SOMVAOASAVS TPOYPALLIVy xo g op OQAPNINT Id tne npotextiov NAG 1 t pepopy Beev evaAe THE Boop t 1 SLOUBAE THE VOLVY THE PIIPOT Bit XP w tHE oases npoypag Trio t TO TNHELVLTLOAA POVTLVEO LV THE PAM npo ypau avd epaoe tne pepopy 2 4 5 S amp S THOMSON Aoade 2 Aoadep BOOT STRAP LOADER ON CHIP SERIAL INTERNAL FLASH PO RAM MEMORY 960 Bytes VROO1647 Piyvpe E 3
363. priority level which also has the highest group priority wins the current round of prioritization Whether the request of this source will be accepted by the CPU or not depends on the current CPU priority If the priority of the requesting source is higher the request is acknowledgedand the CPU passes control to the source s interrupt vector The interrupt system supports 16 different priority levels Only 15 of those levels are actually effective priority levels because requests on level 0 are not capable of interrupting the CPU Therefore up to 15 interrupt service routines on different priority levels can be nested In the following section a method will be described which allows the limita tion of nested interrupt levels to a number less than 15 This may be desirable for reasons of stack effi ciency Normally the 2 highest priority levels level 15 and 14 are used by PEC requests Those levels can also be used to process high priorit PU inter rupt if the COUNT field of the selected PEC chan nel contains 0 at the time this channel is invoked see section 7 2 2 1 7 2 3 3 EXAMPLE FOR THE USE OF THE CPU PRI ORITY The priority level of the routine serviced by the CPU is indicated in the CPU Prior ity field ILVL of the PSW Modifying the CPU Pri ority field of the PSW by software addsiditional flexibility to the interrupt system of the ST10x166 For example it provides the user with a means of reduci
364. r 0000h Reload Register uem m em recor reon om mcos reom pec cramneiz container reca recon em Pec channaa container mcos em pec cramnoia container peoos recan em omon peoos recon ean pe ee me lem wy SGS THOMSON 5 5 YF MICROELECTRONICS B ST10x166 Registers Bit Addressable Special Function Registers Address Address Value m re oon Pon oDrecton mm feumeme Lom rre Ponts Dvecton ConroiRegiser rmm om 8h Port4Direction Control Register 2 Bits Port 4 Direction Control Register 2 Bits feron oon LN em CPU MutipDwideConrolRegiter Fron sm CPU Program siatuswors mm m 00021 musco rrn oan Bus Gontgwanonnegsier _ me pe ee consan vauc oe Reiter goodo Lows mm m mm m mme 22 6 16 Gr SGS THOMSON B ST10x166 Registers Address Address 2 T2CON Aoh GPT4 Timer2 Control Register GPT1 Timer 2 Control
365. r SFRs are to be accessed through indirect or direct addressing with 16 bit mem addresses it must bguaranteed that data page 3 is selected by one of the data page pointer registers DPPO through DPP3 This is not required for accessing SFRs via short 8 bit reg addressing or via the Periph eral Event Controller PEC because in these cases the data page pointers are not used Byte write operations to word wide SFRs via indirect or direct 16 bit mem addressing or byte transfers via the PEC force zeros in the non addressed byte Byte write operations via short 8 bit reg addressing can only access the low byte of an SFR and force zeros in the high byte It is therefore recommended to use the bitfield instructions BFLDL and BFLDH to write to any number of bits in either byte of an SFR without disturbing thaon addresed byte and the unselected bits t 2 1 64 8 Peripherals 3 Some of the bits which are contained in the T6 in block GPT2 TO may also operate in counter ST10x166 s SFRs are marked as reserved mode allowingit to be clocked by an external User software should never write 175 to re event served bits These bits are currently not imple Each capture compare register may be pro new functor im eap mmedindividualior capture or compare tun tion and each register may be allocated to either case the active state for these functions willbe timer To or T1 Each capt
366. r the Bit field T3M Timer 3 Mode Control selects the timer is running or not basic operating mode for timer Tlavailable When pin T3EUD P3 4 is used as external count options are listed in table 8 5 and will be discussed direction control input its copesdingdirection in detail in thedllowingsubsections control bit DP3 4 must be set to 0 wg SGS THOMSON __ 23 64 YF MICROELECTRONICS 8 Peripherals Table 8 6 GPT1 Core Timer T3 Count 8 2 1 1 1 Timer Mode Direction Control Timer mode is selected for the core timer T3 by setting bit field T3M in register T3CON to 00b In Pin Bit Bit Count Direction this mode T3 is clocked with the internal system TSEUD T3UDE clock divided by a programmable prescaler which is selected by bit field The input frequency f for timer T3 is saled linearlyvith slower oscillator frequencies as can be seen from the follow ing formula fr fosc 16x 2 lt gt The timer input frequencies resolution and periods which result from the selected prescaler option when using a 40MHz oscillator are listed in ta ble 8 7 This table alsapplies to the gated timer mode of T3 and to thauxiliarytimers T2 and TA in Timer 3 Output Toggle Latch timer and gated timer mode Note that some num An overflow or underflow of timer T3 will clock thebers may be rounded to 3 significant digits toggle bit T3OTL in control register T3CON Figure 8 17 shows a bloc
367. ra purpose Register ma woon emere Fan cru GenertPurpose Regier Cw om r ron cpu Generar Purpose Regier me om r ron cpu General purpose Regier me wm ron CPU General Purpose Regier mo Fan CPU Generar Purpose Regier mo XXX Len ome re opu GeneralpuposeRegitr emen ron cruGememaPuosemegser ron CPU Generar Purpose Regier ma ren cpu General Purpose Regier ms rm oru Generat runoso neose 1 16 B ST10x166 Registers Byte Registers Address Address Value ma creo ron cP Generat Purpose ma xm me imer m opu Generarpurpose XX ma emer rm cru GonvalPunoseregser Ra cpu Generar purpose Rogier Uma ran register me me mes ron Generat Purpose Regier me xm ron cpu Generar Purpose Regier X me emer rm Generat Purpose Regiser xm ma re opu Gereralpupose Register Ra Lm reo ron cpu Generar urnose negiser X ms i m ran Generar purpose Regier mis Cms omen re Generar purpose regier on _ omer ron cpu Generar purpose Regier are XX _ Fen cpu
368. ranch instructions which do not access any explicitly addressed data 2 84 SGS THOMSO 772 MSB ofthe result is set MSB of the result is not set Carry occured during operation No Carry occured duringperation Arithmetic Overflow occured during operation No Arithmetic Overflow occured during operation Result equals zero Result does not equal zero Source operand represents the lowest negative number either 8000h for word data or 80h for byte data Source operand does not represent the lowest negative number for the specified data type The flag is set due to rules which deviate from the just described standard For more details see section A2 or the description of the ALU status flags in section 6 3 2 1 The flag is not affected by the operation The flag is cleared by the operation The flag contains the logical NORing of the two specified bit operands The flag contains the logical ANDing ofthe two specified bit operands The flag contains the logical ORing of the two specified bilperands A Ivotpuxuov XOR The flag contains the logical selected as destination bits they stay tmaaged XORing of the two specified bit This means that they keep the state after execution operands of the previous instruction B The flag contains the original value any case if the PSW was the destation oper ofthe specified bit operand and ofan instruction the PSW flags do NOT repre
369. rd interrupt processing each register in response to an exter interrupt sources has a dedicated nal event at the port pin which is associated with this register In addition a specific interruptrequest Software interrupts are supported by means of thefor this capture compare register is generated TRAP instruction in combination witliramividual Either a positive a negative or both a positive and trap interrupt number a negative external signal transition at the pin can The ST10x166 also provides an excellent mecha be selected as the triggering event The contents nism to identify and to process exceptions or error f all registers which have been selected for of conditions that arise during run tiroalled Hard five compare modes cdntiouslycom ware Traps Hardware traps cause immediate Pared with the contents of the allocated timers non maskable system reaction which is similiar to When a match occurs between the timer value and a standard interrupt service branching to a dedi the value in a capture compare register specific cated vector table location The occurrence of a actions will be taken based on the selected com hardware trap is additionally signified by a individuaPare mode 4 6 7671 SGS THOMSON MIGRGELECTREMICS 2 System Description 2 6 GENERAL PURPOSE TIMER GPT UNIT cludes two timers T5 T6 and a capture reload register CAPREL Both time
370. rdware traps the CPU priority is set to the system of the ST10x166 This section specifically highest priority level i e 15 in the ILVL field of the refers only to those fields of the PSWtlglbbally PSW Therefore no interrupt or PEC request control interrupt and PEC service functions The pe servicedwhile an exception trap service routine organization of the PSW is shown in figure 7 3 is in progress The software TRAP instruction IL VL CPU Priority Field PSW 15 12 however does not change the CPU priority in the These four bits represent the priority level of the field of the PSW thus it can be interrupted by routine that is currently being executed by the higher level requests CPU During reset the CPU Priority field is initial IEN Interrupt Enable Control Bit PSW 11 ized to the lowest priority level i e level 0 Upon This bitjloballyenables or disables PEOperation entry to an interrupt service routine the four bitsang the acceptance of interrupts by the CPU from the interrupt source s Priority Level field ILVLiYhen IEN is cleared no interrupt requests are ac are copied into these four bits of the PSW after the cepted bythe CPU When IEN is set to 1 all inter previous contents of the PSW have begnished rupt sources which have been inilually onto the system stack enabledby the Interrupt Enable bits in their associ To determine which interrupt will be serviced the ated control registers aglobal enabled inter
371. re registers CCO The active transition is selected by the mode bits through CC15 can be programmed to any of the CCMODXx in the respective CAPCOM mode con availablecapture or compare modes these modes trol register In any case the event causing a cap will be described in detail in the following only foiture will also set the respective interrupt request one representative capture compare register flag CCxIR which can cause an interrupt or a PEC which is referred to as CCx The index x may be service request when enabled substituted by any ofthe indices 0 through 15 Figure 8 5 shows a block diagram for one cap Identically the Port 2 pin which is associated with ture compare register in capture mode register CCx will be referred to as CCxlO where i is the alternate function of P2 x The inter ui Pinter capture Cor bs rupt request flag which is associated with cap configured as input i e the corresponding direc ture compare register CCx is referred to as CCXIR tion control bit DP2 x in register DP2 must be set to and the allocation and mode control bits for CCx 0 To ensure that a signal transition is properly are referred to as ACCx and CCMODx respec recognized an external capture input signal tively should be held for at least 8 state times before it changes its level 8 1 2 1 CAPTURE MODE During these 8 states the capture input signals are The contents of the timer TO or T1 according
372. re the device with com tion is either xFFFEh for single word instructions or mon routines and constants programmed into the XFFFCh fordouble wordnstructions x 1 2 3 If Program memory to have a fast execution speed used for code storage the coryesndinglocation and with the interrupt vector programmed into Ex Must contain a branch instruction because seg ternal memory ment crossing for program execution is only possi ble by changing the CSP register contents by For the ST10F166 the special features of the means of the particular branch instructions JMPS FLASH memory are described in the FLASH mem and CALLS ory chapter 4 sg SGS THoMson 55 3 Memory Organization External word and byte data can only be accessed is either OFDFEh for single word instructions or via indirect or long 16 bit addressing modes in col OFDFCh for double word instructions If used for laboratiorwith the DPP registers There is no short code storage the coespondinglocation must addressing mode for external operands Any word contain a branch instruction to a memory location data access is made to an even byte address other than in the SFR space becausethis space is Thus the highest possible word data storage loca ot provided for code execution tions in the external memory are address OF9FEh Any word and byte data in the internal RAM can be in segment 0 and addresses xFFFEh in all other accessed via indirect or long 16 bit addressing seg
373. resto F sure bits FWE and FEE remain at a logical 1 Program Write Algorithm The Erase Verify Mode EVM is then entered The erase command see erase operation is writ automatically f ten and erase is performed An Erase Verify begins An internally generated margin voltage is ap at the first address and continues until the last ad plied to the FLASH memory If the memory lo dress isaccessedor until the comparison of data to cation is erased the Erase Verify is repeated FFFFh fails The address of the last word verified is for the next location This process continues forstored and a new erase operation is performed each word of the array until the last address is Then the Erase Verify restarts from the stored ad accessed or a word does not return FFFFh In dress Ins case where the nor Cased cans Figure 4 4 illustrates the Presto F Erase Algorithm other erase operation must be performed ASI Ise ET varies in i doi s the erasing pulse varies in inverse ratio to EVM needs a double reading instruction with the same operand time forabilizinghe internal the frequency the number of erasing operation eh varies also circuitry at 1MHz CPU clock 2ms N 15000 e g at 40 MHz CPU clock ET 10ms N 3000 MOV R1 R2 for otherfequenciesET 24 10 TCL Time out of 4ms N 75 10 TCL MOV R1 R2 To perform a normal FLASH reading the FWE FEE bits must be reset The erase of one bank can
374. rganization 3 3 3 Pec Source and Destination Pointers Whenever a PEC data transfer is performed the The upper 16 word locations in the internal RAM of source and destination pointers which is se addresses from OFDEOh to OFDFEh anerovided lected by the specified PEC channel number is ac as source and destination address pointers tor C SSed indeperdent of the current DPP register PEC data transfers contents PEC not used the corre spondingpointer locations can be used for word As shown in figure below a pair of source and des pyte or single bit data storage tination pointers is stored two subsequery fol lowing word memory locations with the more details about the use of the source and pointer SRCPx on the lower and with the destina destination pointers for PEC data transfers refer to tion pointer DSTPx on the higher word address Chapter 7 x20 to 7 Figure 3 5 PEC Source And Destination Pointer Word Organization Source n and Internal RAM Destination Pointers External Memory sg SGS THOMSON 595 3 Memory Organization 3 4 INTERNAL SPECIAL FUNCTION that the selected DPP register points to data page REGISTERS 3 any high byte low byte or any word in the SFR memory space can be accessedaan indirecor The ST10x166 provides 512bytes Spe long 16 bit addressing mode cial Function Register SFR space The SFR
375. rmance mi machine cycle was set for the core CPU Primarily crocontroller which is the right choice not only fotnis goal has been reached except for branch today s applications but also for futenginea multiplyor divide intructions These instructions ing however have also been optimized For example branch instructions only require additionama 1 1 BASIC CPU CONCEPTS AND chine cycle when a branch is taken and most OPTIMIZATIONS branches taken in loops require no additional ma chine cycles To meet the demand for greater performance and The instruction cycle time has been dramatically flexibility a number of areas has been optimized in reduced through the use of instructigipelining the processor core These are summarized below This echniqueallows the core CPU to process and described in detail in thellowingections portions of multiple sequential instruction stages in parallel The llowingour stagepipelineprovides a High Instruction Bandwidth Fast Execution the optimumbalancingfor the ST10x166 family s High Function 8 bit and 16 bit Arithmetic and CPU core Logic Unit a Extended Bit Processing andeBipheralContro FETCH In this stage an instruction is High Performance Branch Call and Loop fetched from the internal ROM or Processing e RAM or from the external memory a Consistent and Optimized Instruction Formats based on the current IP value Multiple Priority Interrupt Struc
376. rms Figure 8 Input Output Waveforms 2 0 9v 0 2 0 9 Vs POINTS lt 0 2Vcc 0 2V cee 0 VROO1629 AC Inputs during testing are driven at 2 4 V for a Timing measurements are made at min for a logic 1 and 0 4 V for a logic 0 logic 1 and max for a logic 0 Figure 9 Float Waveforms TIMING gt REFERENCE lt POINTS LOAD 0 1 Vo_tO 1 VROA1B29 For timing purposes a port pin is no longer floating but begins to float when a 100mV change from the when a 100mV change from load voltage occurs loaded Vou Vor level occurs loH loL 20mA Ey SGS THOMSON SEHE e MIGROELECTRGNICS ST10F166 AC CHARACTERISTICS Continued In the AC Characteristics waveforms the mid point of a signal transition is mostly used as the timing reference point Figure 10 Timing Reference Points If not specifically specified in the drawings the ex act timing reference points are given by the pa rameter description according to the following figures test voltage levels and float state refer ences shown on previous page Falling rising edge To signal After signal High time Low time Data Valid Setup Hold Time Time VROO153Q 6 17 5 S amp S THOMSON ST10F166 AC CHARACTERISTICS Continued External Clock Drive XTAL1 Ta 0 to 70 C 5 V 1096 Vss 0 V CPU Clock Variable Tlming Symbol Parameter 20MHz
377. ro As with segmentation dis 7 4 4 SWITCHING FORINTERRUPT abled the interrupt source s priority level is copiedsgnvicE ROUTINES into the CPU Priority field of the PSW and the In 14 24 S amp S THOMSON C 7 Interrupt And Trap Functions Figure 7 6 Interrupt Procedure With Segmentation Enabled High High Addresses Addresses State of interrupted task saved on system stack Low Addresses Addresses a System Stack before b System Stack after Interrupt Entry Interrupt Entry Context switching in conjunction with processing s an alternative to software oriented interrupt an interrupt service routine allows aisishinga processing the PEC provides a way to minimize new context within the interrupt service routine interrupt latency and software overhead in cases Thus a completely new set of General Purpose where only a single data transfer operation is re Registers GPRs can be provided for the interrupt quired to service eripheraldevice As all the service routine without the need of explicitly sav ST10x166 s peripheral functions aremtrolled by ing and restoring registers Special Function Registers SFRs it is sufficient Context switching can be performed by executing for many applications to simply transfer data to or the Switch Context instruction SCXT within the from the Special Function Registers and a data interrupt service routine before GPR is ac Memory location to handle
378. rocessed to obtain better table distri phores Instructions have also been provided to bution For sequentially searched tables the lock out tasks through software by setting or clear auto increment indirect addressing mode and the ing of user specific bits andmditionallipranching E end of table flag stored in the PSW decrease based on these specific bits the number of overhead instructions executed is recommended that fields of bits in control the loop Below two examples illustrate searching SFRs are updated using the BFLDH and BFLDL ordered tables and non ordered tables respec instructions to avoid undesired intermediate tively modes of operation which can occur when AND MOV OR instruction sequences are used Move table base into RO LOOP 1 RO 13 9 FLOATING POINT SUPPORT Compare targetto table entry SGT LOOP All floating poindperationsare performed using Test whethertarget has software Standard multiple precision instructions not been found are used to perform calculations on data types that exceed the size of the ALU Multiple bit rotate and Note The last entry in the table must be greater logic instructions allow easy masking and extract than the largest possible target ing of portions of floating point numbers MOV To decrease the time required to perform floating Move table base into RO pointoperationstwo hardware features have been LOOP R1 80
379. rrent 1 TCL 40MHz 240 mA 32 bit programming 8 We Vpp writing current 1 TCL 40MHz 50 mA 32 bit programming Vpp 12V A D CONVERTER CHARACTERISTICS TA 20 to 70 C Vcc 2 5 V 1096 Vss 0 V Varer 0 2 V Vss 0 2 V Limit Values Analog Input Voltage Analog Input Capacitance Sample Time Conversion Time Total Unadjusted Error Varer Supply Current Analog Input Current Notes 1 This parameter is tested including leakage currents All inputs in cluding pins configured as inputs at 0 V to 0 1 V orat VCC 0 1 Vto VCC VREF 0 V all outputs including pins configured as outputs disconnected 2 This parameter specifies the time during which the input capaci tance can be charged decharged by the external source It must be guaranteed that the input capacitance is fully loaded within these 63 TCLs Test Condition VCC 0 2 70 63 TCL 390 TCL 2 5 63 TCL is 1 575us at20MHz CPU clock After the end of the sample time ts changes of the analog input voltage have no effecton the conversion result 3 This parameter includes the sample time ts 390 TCL is 9 75us at 20MHz CPU clock 4 IREF in Power Down Mode TBD 5 This parameter specifies the static input current for an analog in put channel e g when the channel is not selected for conversion 4 17 S amp S THOMSON ST10F166 AC CHARACTERISTICS Testing Wavefo
380. rrupt enable bit T6IE in register T6IC is set The organization of interrupt control register T6lC is shown below Refer to chapter 7 for more details on interrupts 8 2 2 2 GPT2 AUXILIARY TIMER T5 The auxiliary timer T5 can operate in timer or counter mode These two modes are described below Unlike the core timer T6 the auxiliary timer T5 has no toggle bit and no alternate output func tion The operation of T5 is controlled by register T5CON which is shown in the following subsec tions In both timer and counter mode of operation the auxiliary timer T5 can count up or down depending on the control bit T5UD and it can be started or stopped through its run bit T5R Timer T5 Run Bit If 5 0 the timer stops Setting T5R 1 will start the timer Figure 8 30 Block Diagram of GPT2 Core Auxiliary Timer T5 in Timer Mode Auxiliary Timer 5 157 SGS THOMSON Interrupt Request VROL1641 39 64 MIGRCELECTREMICS 8 Peripherals 8 2 2 2 1 Timer Mode In this mode selected in register TSCON by setting bit 5 0 the auxiliary timer T5 operates exactly as described for the core timer T6 It has the same 8 prescaler options which are selected by bit field T5l in control register TECON The input frequency frs to timer T5 is determined as follows The resulting input frequency resolution and timer period when using a 40MHz oscillator is the same as for T6 see table 8 13 Figure 8 30 shows
381. rs c ndependently The GPT unit represents a very flexible multifunc count up or down clocked with an input clock tional timer counter structure which may be used forwhich is derived from a programmable prescaler many different time related tasks such as eventtim Concatenation of the timers is supported via the ing and counting pulse width and duty cycle meas output toggle latch of timer T6 which changes its urement pulse generation or pulse multiplication state on each timer overflow underflow The GPT unit incorporates five 16 bit timers which The state of this latch may be used to clock timer are organized in two separate modules GPT1 and T5 or it may be output on a port pin Overflows un GPT2 Each timer in each module may operateinde derflows of timer T6 can additionally be used to pendently in a number of different modes or may be clock the CAPCOM timers TO or T1 and to cause concatenated with another timer of the same mod a reload from the CAPREL register The CAPREL ule register may capture the contents of timer T5 Each of the three timers T2 T3 T4 of the GPT1 based on an external signal transition on the corre module be configured individually for one of Pondingport pin and timer T5 will be cleared by three basic modes of operation which are Timer this external transition if the clear function is en Gated Timer and Counter Mode In Timer Mode the 9bled This allows absolute time differences to be input clock for a ti
382. ruction which is currently fetched within the code segment selected by the CSP register The IP register is not mapped into the ST10x166 s address space and thus it can not be directly accessed by the programmer The IP can however be modified indirectly via the stack by means of a return instruction The IP register is implicitly updated by the CPU for branch instructions and after instruction fetch op erations SGS THOMSON o MICROELECTRONICS 5 Central Processing Unit 5 3 6 CSP Code Segment Pointer CSP FF08h 04h This non bit addressable register selects the code Code Segment Pointer Register segment being used at run time to access instruc Reset Value 0000h tions Currently only two bits of the CSP register dA 43 459 d 10 9 8 are implemented while bits 2 to 15 are reserved for future use The CSP registerallowsaccessingthe 40221 entire memory space in currently four segments of 7 6 5 4 3 2 1 0 64 Kbytes each Code memory addresses are generated by directly extendingthe 16 bit contents of the IP register b15 to b2 R Reserved contents otthe Com register b1 b0 SEGNR Code Segment Pointer Register In the case of the segmented memory mode bit1 Specifies the code segment number where the and bit 0 of the CSP register are output the seg current instruction is to be tetched Will be ig ment address pins A17 and A16 of Port 4 for allex nored in the case of segmentation being dis ternal
383. ructions fetched from the external ext can also be easily calculated by means of table 5 1 Most of the ST10x166 instructions except some of the branches the multiplication the division and a special move instruction require a minimum of two state times In the case of internal ROM pro 5 26 5 Central Processing Unit gram execution there is no execution tidpend For 4 byte instructions on the instruction length except some spe Timin RAM Timin ROM 6 x States cial branch situations The injected target In contrastto the internal ROM program execution instruction of a cache jump instruction can be minimum timeikir ext to process an external Mn ipe MdL instruction additionally depends on the instruction rom the internal of which mem length Tmifext is either 1 ALE Cycle Time for ory range the rest of the current program is really most of the 2 byte instructions or 2 ALE Cycle fetched from Times for most of the 4 byte instructions The fol For some ofthe branch instructions table 5 1 rep lowing formula represents the minimum execution resents both the standard number of state times time of instructions fetched from an external mem which means that the corrpendingbranch is ory via a 16 bit data bus taken and anadditionalimin value in parentheses x which refers to the case that either the branch con SER ACT DR ERO 2 x States diti
384. rupt of serial channel ASCO and ASC1 respectively Each interrupt source also has its own dedicated interrupt vector SOTINT is the Figure 8 43 Watchdog Timer Block Diagram WDT Control transmit interrupt vector SORINT is the receive in terrupt vector and SOEINT is the error interrupt vector for channel ASCO while S1TINT S1RINT and S1EINT are the corresponding interrupt vec tors for ASC1 The cause of an error interrupt request framing parity overrun error can be identified by the error status flags in control registers SOCON and S1CON Note that unlike the error interrupt re quest flags SOEIR or S1EIR the error status flags SOFE SOPE SOOE or S1FE S1PE S1OE are reset automatically upon entry into the error inter Figure 8 44 SFRs and Reset Indication Pin Associated with the Watchdog Timer Reset Indication Pin RSTOUT Timer Register read only SGS THOMSON Data Registers Watchdog Control Registers Watchdog Timer Control Register VROE1640 61 64 MIGRCELECTREMICS 8 Peripherals rupt service routine but must be cleared by soft ware The organization of the interrupt control registers associated with the serial channels is shown here For more details on interrupts refer to chapter 7 8 5 WATCHDOG TIMER WDT To allow recovery from software or hardware fail ure a Watchdog Timer has been provided in the ST10x166 If the software fails to service this timer
385. rupt system antinuouslycompares the cur E rent CPU priority to the priority levels opathding Mee bythe eos andare therefore interrupts Modifying the ILVL field of the PSW of fers the apabilityof programming the priority level below which the CPU can not be interrupted 7 2 2 PEC Service Channels Register Description Figure 7 3 Interrupt Control Functions In The PSW PSW FF10h 88h Processor Status Word Reset Value 0000h 7 6 5 4 3 2 1 0 m us mu j e z j v 8 24 SGS THOMSON MOE 7 Interrupt And Trap Functions The ST10x166 s Peripheral Event Controller PECCy PEC provides 8 PEC Servic hannels Upon an pec Channel Counter Control Registers Organi interrupt request a PEC channel is capable of per zation y 0 through 7 forming a single byte or word data transfer be tween any two memory locations in segment 0 Reset Value 0000h data pages 0 through 3 Each channel consists of 15 14 13 12 11 10 9 8 a dedicated PECChannelCounter Control register and a pair of pointers for source and destination of the data transfer 7 2 2 1 PEC CHANNEL COUNTER CONTROL REGIS 7 6 5 4 3 2 1 0 TERE Each of the 8 PEC servie channels impleranted in the ST10x166 issuppliedwith a separate PEC P15 to b11 R Reserved Channel CounteControl register Note thatthese b10 b9 Z INC Increment Control Field registers are NOT bit addressable They will be re INC 200b Increment no pointer ferred to a
386. rvice requests these states see chapter 12 against each other and prioritizes one of them If 1 26 5 Central Processing Unit Section5 3 describes the Special Function Regis struction All explicit writes to the SFR memory ters situated within the CPU core which are all space and all auto increment or auto decrement dedicated to particular uses as follows a General System Configuration SYSCON a Bus Configuration BUSCON1 a Address Select ADDRSEL1 a CPU Status Indication and Control PSW a Code Access Control IP CSP a Data Paging Control DPPO DPP1 DPP2 DPP3 a GPRs Access Control CP a System Stack Access Control SP STKUN STKOV a Multiply and Divide Support MDL MDH MDC a ALU Constant Support ZEROS ONES 5 1 INSTRUCTION PIPELINING writes to GPRs used as indirect address pointers are performed during the execute stage of an in struction too 4th gt WRITE BACK In this stage all external op erands and theemainingoperandswithin the in ternal RAM space are written back A particularity of the ST10x166 are the so called in jected instructions These injected instructions are internallyjenerated by the machine to provide the time neededto process instructions which cannot be processed within one machine cycle They are automatically injected into the decode stage of the pipeline and then they pass through tbenaining stages as every standard instruction Program in terrupts are performed by means
387. ry For PEC data transfers these terface accesses areindependentof the contents of the The external memory can be used for both code DPP registers via the PEC source and destination ang gata storage If the ST10x166 segmentation pointers mode is disabled SGTDIS bit in the SYSCON reg Whenever a reset hardware trap or interrupt oc ister contains a 1 all external memory accesses curs orwhenevera software TRAP instruction is are restricted to segment 0 only Code accesses executed and provided that the Program memory are always made on even byte addresses Thus accesses are enabled program execution the highest possible external code storage location branches to an implicit internal address inde in segment 0 is either OF9FEh for single word in pendent of the current Code Segment Pointer structions or OF9FCh for double word instructions CSP register contents expecting a jump vector If used for code storage the awspondingoca being situated there For detailed information tion mustcontain a branch instruction because se about the trap and interrupt jump vector table see quential boundary crossing from the external section 9 1 Interrupt System Structure memory to the internal RAM space is With the possibility to remap tirternal and would cause erroneous results In any seg memory t 1 during initialization how ment other than 0 the highest code storage loca ever the user can configu
388. ry the data become removes its memory read signal This causes the valid in the addressed memory location Then the memory toremove its data from the data bus which controller removes its memory write signal and is thentri stated again Simatteouslywith there puts the address for the next memory access moval of theRD signal the controller puts the ad the address bus if a subsequent external memory dress for the next memory access on the address access is required The data remain valid on the bus if a subsequent external memory access is re data bus until the next memory access cycle is quired started SGS THOMSON 0 120 9 External Bus Interface 9 8 USER SELECTABLE BUS If an external memory is too slow the controller CHARACTERISTICS must slow down in order to allow the memory to keep pace The ST10x166 can be slowed down for Important timing characteristics of the external busexternal memory accesses by introducing wait interface includingthe Memory Cycle Time the states during the access During these Memory Memory Tri State Time the Read Write Delay Cycle Time wait states the CPU is idle Figure 9 11 Time and the Address Latch Enable length have shows when Memory Cycle Time wait states are been made user programmable to allow adapting a introduced during the memory access wide range of different external bus and memory The sT10x166 allows the user to program Memory conigurationswith different types of memories Cy
389. s The upper portion of the SFR memory space ad mapped into the address space from to dresses from OFFOOh to OFFDFh contains SERS OFFFFh with many single flag control functions Thus this The SFRs are not provided for general code or memory area is directly bit addressable data storage but for data storage dedicated to very some bits in already existing SFRs and some word particular uses mainly for coollirg CPU Periph locations in the SFR address space have been re eral and I O functions served for a future implementation of additional on According to the just mentioned control functionschip peripherals Any intended write access to the SFRs are described in detail one of the chap such a reserved SFR memory spaosould be ig ters 5 CPU 8 Rripherals pr 10 Parallel Ports nored by the rachine andany intended read will A table ontaining short description symbolic ad SUPPly a read result of 0 dresses physical 18 bit and short8 bit addresses Note that any byte write to an existing SFR causes of the SFRs can be found iappendixB the non addresed complementary byte to be Most commonly an SFR can be accessed by word Cleared via an implicit base address plus a short 8 bit offsetSome SFRs or parts of them have a restricted ac addressindependentof the current DPP register cess type such as read only or write only For more contents The low byte portion of an SFR but not details see the functional descr
390. s PECCy where y represents the num 01b Increment destination pointer ber of the associated PEC channel yz rbugh INC 10b Increment source pointer Each register specifies the task which is tobe INC 211b Reserved performed by the associated spe BWT Byte Word Transfer Select bit cific PEC channel is selected by an interrupt BWT 0 Word Transfer source through the ILVL and GLVL field in the in pwr 4 Byte Transfer nee a PE hennel to b0 COUNT PEC Transfer Counter Field counter control registers while their organization COUNT FFh Couninuots transfer mode is shown besides In the liowing their function COUNT value not decremented Aoil gt COUNT gt 1 COUNT value decremented after each transfer COUNT z 0 CPU interrupt is generated INC Increment Control Field This 2 bit field specifies whether the Source Pointer or the Destination Pointer of the associated PEC channel shall be incremented after a PEC data transfer Only one of the 2 pointers either the Source or the Destination Pointer may be incre mented it is not possible to increment both point ers after a transfer When the function increment no pointer is selected INC 00b the transfer is always performed between the same two memory locations Note When software tries to program the INC field to 11b this value is modified by hardware to 10b Table 7 3 PEC Channel Co
391. s a finer resolution that means more ticks within the time between two external events For this purpose one measures the time between the external events using timer T5 and the CAPREL register Timer T5 runs in timer mode counting up T5UD 0 with a frequency of for example fosc 64 The external events are applied to pin CAPIN When Figure 8 35 Register CAPREL In Capture And Reload Mode 44 64 Interrupt Request Interrupt Request Interrupt Request To CAPCOM Timers TO T1 VROS1641 SGS THOMSON o MICROELECTRONICS 8 Peripherals an external event occurs the timer T5 contents are latched into register CAPREL and timer T5 is cleared T5CLR 1 Thus register CAPREL al ways contains the correct time between two events measured in timer T5 increments Timer T6 which runs in timer mode counting down T6UD 1 with a frequency of for example fosc 8 uses the value in register CAPREL to perform a re load on underflow This means the value in register CAPREL represents the time between two under flows of timer T6 now measured in timer T6 incre ments Since timer T6 runs 8 times fasterthan timer T5 it will underflow 8 times within the time between two external events Thus the underflow signal of timer generates 8 ticks Upon each underflow Figure 8 36 A D Converter Block Diagram interrupt request flag T6IR will be set and bit T6OTL will be toggled The state of
392. s and the BUSACT bit are always read the general memory access time Note fat tion selected during reset But after the EINIT additionabxternal wait states do not slow down in ternal memory accesses Table 5 3 summarizes instruction end of initialization only the external bus configuration can behangedat any time the SYSCON control functions for the external bus When the SYSCON parameters are modified dur ning ing initializ bn an instruction from a source ex After reset the MCTC MTTC and RWDC are all in ternal bus or internal ROM which is to be switched itialized to zero Thus even very slow memories must not be performed e glisablinghe external will be accessed correctly bus when executing from external memory Switching between the bus modes can also be per 5 3 1 3 BYTE HIGH ENABLE PIN CONTROL VIA BYT formed with the BUSCON register see section pis 5 3 1 5 for further information The BYTDIS bit is provided for controlling the ac Note that the selection of a multiplexed external tive low Byte High EnabI amp HE pin The function bus configuration automatically extends the Mem of the BHE pin isenabledif the BYTDIS bit con ory Tri State Time by one state time 1 state tains a 0 Otherwise it itisabledand the pin can timez2 x 1 bsc be used as standard I O pin ThBHE pin is implic For further information and for examples about theitly used by the External Bus Controller to select Single C
393. s configuration is selected The input direction is the default after reset If the CPU accessesexternal memory Port 0 first external device is connected to the pin however 9Utputs the 16 bit intra segment address informa one can also set the direction for this pin to output as an alternate output function Port 0 is then In this case the pin reflects the state of the port SWitched to the high impedance input mode to read output latch Thus the alternate input function the incoming instruction or data Inthe 16 18 bit Ad reads the value stored in the port output latch This dress 8 bit Data Bus mode two memory cycles are can be used for testing purposes to allow a soft required for word accesses the first for the low byte ware trigger of an alternate input function by writing d the second for the high byte of the word When to the port output latch datais written to an external memory Port 0 outputs the data byte or word after outputting the address On most of the port lines the user software is re y 9 sponsible for setting the proper direction when us the non multiplexed bus configuration Port 1 out ing an alternate input ar oulput function of a pin Puts the 16 bit intra segment address while Port 0 This is done by setting or clearing the direction adS the incoming instruction or data word or control bit DPx y dhe pin before enabling the al writes the data to the external memory Therefore ternate function
394. s on the bus type which was selected during After the internal reset has completed the opera reset via theBUSACT EBCO and EBC1 pins All tion of the Watchdog Timer laisabledbythe other pins remain in the higimpedancestate until DISWDT Disable Watchdog Timer instruction they are changed by software peripheralopera This instruction has been implemented as a pro tion tected instruction For further security its execu tion is only enabled in the time period aftera reset a rp high 1 either the SRVWDT Service Watchdog pedance state until modified by software or imer or the EINIT instruction has occurred Oth t E bus type reconfiquration in reaister SY erwise execution of the DISWDT instruction will 9 9 9 have no effect More details about Watchdog Timer operation can be found in section 8 5 When any of the external bus modes was selected during reset Port 0 and or Port 1 will operate inthe selected bus mode The two pins of Port 4 will out 11 4 PORTS AND EXTERNAL BUS put the segment address since bit SGTDIS in reg CONFIGURATION DURING RESET ister SYSCONis 0 default after reset The code segment pointer CSP is initialized to zero and all During the internal reset all of the ST10x166 s port bits of the data page pointers except for the two pins are configured as inputs through their direc4 SBs are also initialized to zero during reset tion registers and are switched to the high imped Th
395. s selected by programming the respec tive mode selection field SOM or S1M to 111b The data frame which will be transmitted and or re ceived consists of 8 data bits and a parity bit All er ror checks may be enabled in this mode On transmission the parity bit even parity is auto matically generated based on the 8 data bits and inserted at the MSB position of the data frame On reception the parity on the 8 data bits received is generated and the result is compared to the 9th bit received which is the parity bit If the compared bits are different both the parity error flag and the error interrupt request flag are set provided the parity check has been enabled The actual parity bit received is placed in the 9th bit of the receive data buffer register and the remaining 7 bits 9 through 15 of the receive buffer register are cleared to zero 8 4 1 2 SYNCHRONOUS OPERATION This operating mode of the serial channels ASCO and ASC1 allows half duplex communication and is mainly provided for simple I O expansion via shift registers 8 data bits are transmitted or received synchronous to a shift clock generated by the inter Ey SGS THOMSON MICROELECTRONICS 8 Peripherals nal baud rate generator The shift clock is only ac tive as long as data bits are transmitted or re ceived Synchronous operation is selected by programming the mode control field SOM or S1M of a serial channel to 0000 Figure 8 42 shows bloc
396. se lected DPP register are used for the physical ad DPP3 FE06h 03h dress generation just described Thus extreme care should be taken wherhanginga DPP regis Data Page Pointer Register ter contents if a non segmented memory model is Reset Value 0003h selected because otherwise unexpected results 15 14 13 12 11 10 9 8 could occur In the case of the segmented memory mode bits 3 soc acordes and 2 of the implicitly selected DPP register are 7 6 5 4 3 2 1 0 output on the segment address pins A17 and A16 of Port 4 for all external data accesses A DPP register can be updated via any instruction which is capable bmodifying an SFR Due to the b15 to b4 R Reserved internal instructiopipeline a new DPP value is to b0 DPPxPN x 0 to 3 Data Page Pointer not yet usable for the operand address calculation Specified the data page number selected by of the instruction immediatebJIbwinghe instruc DPPx In the case that segmentation is disabled tion updating the DPP register only the two least significant bits of DPPxPN are significant 18 26 S6S THOMSO Pe 7 7572 ORGON 5 Central Processing Unit Figure 5 6 Default Configuration of the Data PagePointers Sixteen 16 KByte Pages Note that all of the internal memory is accessible via 16 Bit addresses after reset 16 Bit Data Address DPP Registers specify 4 Bit Page Address 3 2 1 0 10 Intra
397. se of jump taken semaphore support JBC JNBS Conditionatalling of an either absolutly or indi rectly addressed subroutine within the current code segment CALLI Unconditionalallingof a relatively addressed subroutine within the current code segment CALLR a Unconditionaladlingof an absolutely ad dressed subroutine within any code segment CALLS a Unconditionaladlingof an absolutely ad dressed subroutine within the current code segment plus aradditionapushing of a select able register onto the system stack PCALL Unconditional branching to the interrupt or trap vector jump table in code segment 0 TRAP 6 1 10 Return Instruction Returning from a subroutine within the current code segment RET Returning from a subroutine within any code segment RETS Returning from a subroutine within the current code segment plus andditionabopphg ofa selectable register from the system stack RETP Returning from an interrupt service routine RETI 6 1 11 System Control Instructions a Conditional jumping to an either absolutely indi a rectly or relatively addressed target instruction within the current code segment a Unconditional jumping to an absolutely ad dressed target instruction within any code segment JMPS a Conditional jumping to a relatively addressed target instruction within the current code seg mentdependingon the state of a selectable bit JB JNB a C
398. seTRONICS 4 Flash Memory FLASH PROGRAMMING OPERATION After the Write mode has been entered the FLASH memory is accessed for programming with indirect addressing mode instructions One or two words word z 16 bits can be programmed at once de pendingon the WDWW bit value of FCR A programming operation is realized with the fol lowing sequence Test VPPRIV bit of FCR to verify the correct voltage on VPP Load thedesired value in FCR 15 14 13 12 11 10 9 8 Fuser seo pup sped 7 6 5 4 3 2 1 0 woww cker s cxeruo veemw rcvee reusv Fee iae qoe qos qos qo sco As FCR is a virtual register all bits previously writ ten must be confirmed in the same state at each FCR writing especially FWMSET Write the FLASH memory e g for one word MOV Rm R1 for two words MOV Rm R1 MOV Rm R2 The address used for a long word write 32 bits Rm must be aligned even address xxxOh xxx4h xxx8h xxxCh and is used as a base pointer for the FLASH memory writing The two words to write must be contiguoudignedat even address R1 contains the data to write at the first address and R2 contains the data to write at tliellowing even word address Ey SGS THOMSON FLASH programming will automatically start The programming time depends on CKCTLO 1 bits of FCR End of programming is detected by polling orthe FBUSY bit of FCR Test FCVPP bit of FCR to verify t
399. sed as general pur the chip s start up procedure is always monitored pose l O line 6 6 SGS THOMSON TE micros ecrnenies SGS THOMSON JJ NicROELECTROMICS CHAPTER 3 MEMORY ORGANIZATION 3 MEMORY ORGANIZATION The ST10x166 family s memory space is config The ST10x166 provides a total addressable mem ured in a von Neumann architecture This means ory space of 256Kbytes that code and data are accessed within the same This address space is arranged in four segments linear address space All of the physically sepa o 64Kbytes each and each segment is again sub rated memory areasjncludingthe internal ROM divided four pages of 16Kbytes each The total for the 510166 internalFLASH memory for the addressable space sea be pandedup ST10F1 66 internal RAM internal Special Func io 6 Mbytes for future members of the 0166 tion Registers SFRs and external memory are family mapped into a common address space Figure 3 1 Memory Segment And Page Arrangement Address 3FFFFh 30000h 2FFFFh 20000h 1FFFFh 10000h OFFFFh 00000h 256KByte Total Address Space 1 10 3 Memory Organization Bytes are stored at even or odd byte addresses followingwords Single bits are always stored in Words are stored in ascending memory locations the specified bit position at a word address Bit po with the low byte at an even byte address being fol sition 0 is the least significant bit of the byte at
400. service requests Ex cessed For example the instruction SCXT 2Mpleswouldbe storing of results from the A D New Bank is used to push the previous value of converter or data from a serial channel With the the Context Pointer CP on the system stack and 5110 16675 PEC data transfers between two set the CP to the value New Bank which is speci locations in segment 0 data page 0 fied as an immediate operand in the SCXT instruc through 3 are possible tion Note that GPRs in the new register bank The PEC data transfer itself does not affectthe IP should not be accessed by the instruction immedi or the flags in the PSW Therefore no program atelyfollowinghe SCXT instruction see also sec status information needs to be saved when the tion 5 1 4 PEC performs a data transfer This improves the Before executing the RETI instruction at the end of 9Verall systemtluughpu and speeds up the serv an interrupt service routine the previous ContextiCing ofperipheratequests Pointer must begpoppedfrom the system stack to priority level structure of the 80k 166 sinter ensure correct return to the previous context rupt system has beedesignedsuch that requests for service have priority over requests for p ge Peripheral CPU interrupt service Exceptions to this are when the CPU is executing a routine on CPU priority wg SCS THOMSON 80 0 0 397 YF MICROELECTRONICS 7 Interrupt And Trap Func
401. ses and instructions N 3 source s interrupt request flag is reset to 0 Notethrough N 1 write back external operands In this that when instruction N reads any of the con case the PEC response time is the time to perform trol registers PECCO through PECC7 while a 7 word bus accesses Note that this worst case request wins the current round of prioritization thi ituation is rather untypical and occurs only when round is repeated and the PEC data transfer is instructions and N 1 are indirect MOV instruc started one cycle later tions between two external memory locations es JR nuu n oris time is 3 states When instructions and N 1 are executed out of 150ns at 40MHz Thisappliesto program execu external memory but all operands for instruc tion fromthe internal ROM when no external oper tions N 3 through N 1 are in internal memory then and read requests are performed and when the the PEC response time is the time to perform 1 interrupt request flag is set during the last state of Word bus access plus 2 state times an instruction cycle When the request flag was set during the first state of an instruction cycle theOnce request for service has been acknow PEC response time 4 state times ledged by the CPU the execution of the next in struction is delayed by 2 state times plus the additionatime it might take to fetch the source op erand from internal ROM or external memory and to wri
402. sm coe sm ocon come coanr em w comm come commr sw w come commr sw wn come coomr vw comm coe cowmr m ven carcomRegiseris comm come commr ren LowcowTmeo wm me rwr oom Tm rw om m Femme vam aon zm Femmes ron re Foe mea rem Femmes Tm 2 Te A conversion complete ance Am ap overun rer ADEE or wm x son sormr ww 2M some aon serar cnarmeto Enor soem seme eon 2 sme smwr sw am Receive sim swr em zm sm see ech m Ey SGS THOMSON 3 24 MICROELECTRONICS 7 Interrupt And Trap Functions The vector locations for hardware traps and the est priority trap priority For more details on re correspondingstatus flags in register are setreferto chapter 1 listed in table 7 2 Also listed are the priorities of software traps may be
403. specified bits For the prioritize ALU opera tion the Z flag allows a differentiation of the represents the logical ORing of the two speci two cases which cause a result of zero fied bits V Flag For the addition subtraction and 2 s C Flag After an addition the C flag indicates complementation the V flag is always set to 1 that a carry from the most significant bit of the if the result overflows the maximum range of specified word or byte data type has been gen signed numbers which are representable by erated either 16 bits for word operations 8000h to 7FFFh or by 8 bits for byte operations 80h to 7Fh otherwise the V flag is cleared Note that the result of an integer addition inte ger subtraction or 2 s complement is not valid if the V flag signifies an arithmetic overflow For the multiplication and division the V flag is set to 1 if the result can not be represented ina word data type otherwise it is cleared Note that a division by zero will always cause an overflow In contrast to the result of a division the result of a multiplication is valid regardless of whether the V flag is set to 1 or not bit operations with two operands the V flag After a subtraction or a comparison the C flag indicates a borrow which represents the logical negation of a carry for the addition This means that the C flag is set to 1 ifo carry from the most significant bit of the speci
404. ss ADDR H Address High Byte The followingable 12 1 presents a summary ofthe DATA Data in Port Output Latch state of all ST10x166 output pins during Idle and 16 8 16 18 bit Address 8 bit Data Power Down modes MultiplexecBus 16 16 16 18 bit Address 16 bit Data Non Multiplexed Bus non segm SegmentatioBisabled Table 12 1 Output Pins Status during Idle and Power Down Mode bus enabled enabled bus enabled enabled L L L L H H H H FLOAT FLOAT last ADDR H 16 8 last ADDR H 16 8 FLOAT otherwise FLOAT otherwise DATA last ADDR 16 16 DATA last ADDR 16 16 DATA ee DATA DATA AF DATA DATA AF AF DATAlatAF AF DATA AF DATA AF DATA AF DATA last AF BHE P3 12 DATA L or H DATA L or H WR P3 13 DATA H DATA H CLKOUT P3 15 active active L L if enabled Port4 A16 A17 DATA DATA non segm DATA DATA non segm A last ADDR otherwise last ADDR otherwise 1 Low if IDLE or PWRDN executed before EINIT otherwise n SGS THOMSON _ 9 4 MICROELECTRGNICS 12 Power Reduction Modes NOTES 4 4 S amp S THOMSON C ACE SGS THOMSON AYA wicmowscimowCS CHAPTER 13 SYSTEM PROGRAMMING 13 SYSTEM PROGRAMMING To aid softwarelevelopnent a number of fea 13 1 1 Directly Substitutable Instructions tures has been incorporated into the instruction set ctructions known from other microcontrollers can of the ST10x166 These include constructs for pe replac
405. ssociated with The alter nate functions of Port 3 are listed in table 10 1 Table 10 1 Port3 Alternate Input Output Functions me mom ma GAEL Reiter apes ma 9 ma mem Down conoi ms 1 mera coumt Rood capuo mpa es mm oae neoa TXD1 Serial Channel 1 Data Output in Asynchronous Mode Clock Output in Syncrhonous Mode Serial Channel 1 Data Input in Asynchronous Mode Data Input Output in Synchronous Mode TXDO Serial Channel 0 Data Output in Asynchronous Mode Clock Output in Synchronous Mode RXDO Serial Channel 0 Data Input in Asynchronous Mode Data Input Output in Synchronous Mode S Byte High Enable Control Signal for External Memory 10 18 SGS THOMSON 10 Parallel Ports 10 1 3 1 PORT 3 PINS TOIN T2IN T3IN T4IN When the peripheal associated with such T3EUD CAPIN AND READY a pin is configured to use the alternate input func The basic structure of these seven Port 3 pins tion it reads the input latch which represents the which only an associated alternate input State of the pin via the linabeled Alternate Data function is identical as shown in figure 10 9 Note Input If an external device is driving the pin the di that theREADY pin hasan additionahlternate in rection ofthe pin must be set to input When no ex
406. stage of thepipelineat the beginningof the fetch the branch target instruction This extra ma next machine cycle after decode of thenditional chine cycle is provided by means of an injected in branch instruction Figure 5 2 Standard Branch Instruction Processing injection ITARGET ITARGET 1 ITARGET 2 ITARGET 3 1 Machine lt ITARGET ITARGET 1 ITARGET 2 ITARGET TARGET 1 5 1 3 Cache Jump Instruction Processing struction JMPR JB JBC JNB JNBS is ad A jump cache has been incorporated in the ditionallystored in a cache after having been ST10x166 as an optimization afonditional jums fetched which are processed repeatedly within a loop After eachrepeatedlyfollowingexecution of the Whenever a jump on cache is taken the extra time same cache jump instruction the jump target in to fetch the branch target instruction can be saved struction is not fetched but taken from the cache and thus the caespondingache jump instruction and immediatly injected into the decode stage of in most cases takes only one machine cycle to be the pipeline see figure 5 3 performed A time saving jump on cache is always taken after This performance is achieved by thellowing the second and any further occurence of the same mechanism Whenever a cache jump instruction cache jump instruction unless an instruction which passes through the decode stage of tpipeline has the fundamentabapabilityof changingthe for the first time and provided tha
407. ster controls only the This register used with the ADDRSEL1 register al possible controlthe on chip lows the automatic selection of a different bus POPE EON pad EDT figuration Itincludes all control bits of the MS canon y 9 SYSCON register relevant for configuring There are three different methods to lengthen an 5 3 3 ADDRSEL1 ADDRESS SELECT access to external memories or peripherals One is REGISTER using MCTC to lengthen the middle of a bus cycle This register specifies the address space in which another isusing MTTC to lengthen the end of abus the BUSCONT register will control the external bus Bit of BUSCON to lengthen thbeginnii of a This register is divided into three parts Bits 0 to 2 bus cycle b RGSZ Range Size Selection bit field specify the After reset the ALECTL1 bit is reset For periph address range according to tliellowingable 5 5 ALE pulse e longer address aha held nies The next bit field bits 3 to 9 Range Start Address 4 specified the start address of the address range within the address range specified by the AD The third field of register ADDRSEL1 bits 10 to 15 DRSEL1 register islengthenedby one machine S reserved for future expansion state 50ns 20MHz CPU clock The ALE signal There is a fixed relationship between the range is lengthened by one TCL TCL 1 2 machine size and the range start address
408. ster isjenerallyused to refer to thevhole port Px For reference to a port pin the notation Px y y 0 15 for the associated bit in the port data register is used as well as the symbol for the alter nate function of a port pin This chapter about thperipheralswill provide all information which is necessary to use the alternate functions of a port in conjunction with a peripheral A detailed description of the internal port structure will be given in chapter 10 Parallel Ports Internal operation of CPU anpbripheralsSs based on the oscillator frequencyp t divided by 2 The resulting frequency is referred to as system clock The basic time unit for internal operation of a chip is commonly called state time For the ST10x166 one state is defined as 2 periods of the oscillator frequency When a 40MHz oscillator is used the internal system clock is 20MHz and 1 state lasts for 50ns The clock which is gated to tlperipheralss inde pendent fromthe CPU clock During Idle mode the CPU clock is stopped while thgeripheralscon tinue their operation d ipheral S Rs may be ac cessed by the CPU on ceper state When an SFR is written to by software in the same state where it is also to be modified by thgeripheal the soft ware write operation has priority Further details on peripheraltiming are included in the specific sec tions about each peripheral Programming Hints 1 All SFRsreside in data page 3 ofhe memory space Wheneve
409. struction pointer plus the relative displacement op1 The displacement is a two s complement number which is sign ex tended and countsthe relative distance in words The value of the instruction pointer IP is placed onto the system stack Because the IP always points to the instr oliowing the branch instruction the value stored on the system stack represents the return address of the alling rouine The value of the IP used in the target address calculation is the ad dress of the instructioalflowinghe CALLR instruction E 2 V Not affected Not affected Not affected Not affected Not affected lt INSTRUCTION FORMAT CALLR BXO Taoxtvy Mvenoviy Onepav o Byteo CALL rel BBrr 2 57 S6S THOMSON o MICROELECTRGNICS A Ivotpux tiov Let XAAAX XAAAX XOAA Ivtep oeyevt LoBpovtive ol 2 OPERATION SP SP 2 SP CSP SP SP 2 SP IP CSP op1 IP op2 A branchis taken to the absolute location specified by op2 within the segment specified by op1 The value of the instruction pointer IP is placed onto the system stack Because the IP always points to the branch instruction the value stored on the system stack represents the return address to thing routine The previous value of the CSP is also placed on the system stack to insure correct return to the calling se
410. t 4 outputs through for Ports 0 through 3 the corre the additionabegment address bits A16 and 17 sponding Port Direction control registers DPO when segmenation is enabledThe pins of Port2 through are described below serve as capture inputs or compare outputs for the 2 CAPCOM unit or as bus arbitration signals for The 8 bit data register P4 for Port 4 is also de communication with external DMA functions PortSCribed Port 4 is actually a 2 bit port but the data 3 includes alternate input output functions of CAP and direction registers of Port 4 are realized as COM timer TO the general purpose timer blocks byte wide registers Bits 2 through 7 are reserved GPT1 2 and the serial channels ASCO 1 In addi bits while bits 8 through 15 axenimplemerdd tion Port 3 provides the bus interface control sig Writing to theunimplerented bits has no effect nals WR BHE READY and the system clock While reading always returns zero CLKOUT Port 5 is used for the analog input chan In the fllowingthe symbol Px x 0 through 4 for nels to the A D converter a port data register is also used to refer to the All ports have Schmitt Trigger input charac Whole Port x teristics except when used as external data bus and as analog inputs to the A D converter 10 1 THROUGH 4 1 18 10 Parallel Ports Ports 0 through 3 Data Registers PO FFOOh 80h Reset Value 0000h 15 14 13 12 11 10 9 8 rots
411. t beganized terrupt or PEC service requests of higher priorityin 3 priority classes with 8 10 and 6 sources per other thanin this group are still accepted class In the priority scheme of the ST10x166 the All interrupt requests of lower or equal priority be 24 Sources could be organized an mfigured as come pending Thus the interrupt system oper follows ates as if all tasks of the group were on the same In this example the 3 user defined priority levels priority level are called classes Each of the three classes A throughC includesnterrupt sources on 2 or 3 pri Table 7 4 Example of 24 Interrupt Organization In 3 Classes Organization PEC Service 8 Channels Class A 8 Interrupts ority levels of the interrupt system 2 highest Using this technique interrupts generated by the priority levels of the interrupt system are used bylowest class i e C can beinterrupted by a request the PEC service functions Priority level 0 does notfrom higher classes i e B or A However an inter provide interrupt service With the organization rupt service routine of a source th longsto the shown in table 7 4 any acknowledged interrupt highest class i e A can not be interrupted by re from the sources within a class e g A must set quests of the same or lower classes the CPU Priority field of the PSW to the highest pri 7 5 4 Interrupt Procedure ority level ontained inits class e g 8 for class B at thebeginningpf its in
412. t inter erands and the interrupt vector location is also inr service routine will not be entered until at least the external memory In this case the interrupt re two instruction cycles have been executed in the sponse is the ee a panom 9 wore program section returned to In most cases two in cesses because Instruction can not De fetched structions will be executed during this time Only over the external bus until all write fetch and read one instruction will typically be executed if the first requests of preceding instructions in pipeline instruction dilowing the RETI instruction is a are terminated Under the sameonditionsbut branch instruction without cache hit or if it reads with the interrupt vector location in the internalan operand in the internal ROM or if it is executed ROM the interrupt response time is 7 word bus ac gut of the internal RAM cesses plus 2 states because fetching of from the internal ROM can start earlier Note that these Similar to the interrupt response time the re worst case situations are rather untypical and oc SPonse time for data transfer request can cur only when instructions N and N 1 are indirectbe defined as the time required from the moment MOV instructions between two external memory interruptrequest flag has been setuntil the PEC locations When instructions N through N 2 are data transfer is started In general the PEC re executed out of an e
413. t the jump condi CSP register contents JMPS CALLS RETS tion is met the jump target instruction is fetchedTRAP RETI or any standard interrupt has been as usual causing a time delay ohe machine cy processed during the period of time between two cle In contrast to standard branch instructions followingoccurences of the same cache jump in however the target instruction of a cache jump in struction Figure 5 3 Cache Jump Instruction Pipelining Injection Injection of Cached 1 Machine lt Target Instruction Cycle FETCH har Hamer Imre DECODE 1st loop iteration Repeated loop iteration gt sg SGS THOMSON 0 0 0 0 0 0 3 5 Central Processing Unit 5 1 4 Particular Pipeline Effects a Explicit Stack Pointer Updating Since up to four different instructions are processedAny of the RET RETI RETS RETP or POP instruc simultaneously additional hardware has been spenttions is not capable of correctly using a new SP reg in the ST10x166to considerall causal dependencies ister value which is to be updated by an immediately which may exist on instructions in different pipelingosreceding instruction Thus if one wants the new SP stages without a loss of performance This extra register value to be used without erroneously per hardware i e for forwarding operand read and formed stack accesses one must put at least one in write values avoids that the pipeline becomes no struction between an explicitly
414. tart up time of the oscil set instruction lator about 50ms for a quartz crystal The internal 3 Byan overflow of the Watchdog Timer PME api may vary between 30land 150k 242 therefore the minimum power on reset time must Whenever one of these conditions occurs the mi determined by the lowest value of this pullup re crocontroller is reset into its predefined defaul 21 sistor One may also use aadditionakxternal re State throughan internal reset procedure Whena sistor In the reset circuit shown in figure 11 1b reset is initiatedpendinginternal hold states are cancelled and external memory access cycles are hee source 1 ed used e g for ipe aborted regardles of unreturnedREADY sig 214 reset source 2 for warm reset In the case of a nal Write operations to the internal RAM however warm reset where the oscillator 15 already stabi are completed before the internal reset procedure 229 the minimum low time of the reset signal at pin RSTIN is only 2 state times Noise pulses begins After this internal reset has been com dedos pleted in case of a software or watchdog timer trig longer than 2 state times will always initiate a com gered reset or after deassertion of the signal at pin Plete reset ofthe ST10x166 Shorter pulses will not be considered by the ST10x166 and must be RSTIN in case of a hardware reset the microcon 200 troller will start program execution from memory jo avoided
415. tate which is a high level 1 Figure 10 10 Block Diagram of a Port 3 Pin With an Alternate Output Function Write Direction Direction Latch DP S y Read DP3 y Alternate Read Write Port Data Output Buffer P3 1 T6QUT Buffer P3 3 T3OUT P3 B TXD1 P3 10 TXDO Read Port P3 y Erg CLKOUT Read Buffer y 1 3 8 10 13 15 12 18 Ey SGS THOMSON MICROELECTRONICS 10 Parallel Ports 10 1 3 3 PORT 3PIN BHE ANS a Ee 16 bit ME Figure 10 11 shows the block diagram of pin theBHE function isnabledthrough bit BYT P3 12 BHE which is the seventh Port 3 pin with DIS 9 in register SYSCON default after reset only an alternate output function Since the two multiplexers in the port data output line and signal might be required directly after reset when the port direction control line are switched The di an external 16 bit data bus mode multiplexed or ection is set to 1 output and the pin is colted non multiplexed is selected through pins EBC1 PY the Alternate Data Output line and EBCO there is no way the user can configure If theBHE pin is not required in application the the BHE pin Thus it will be switched automatically user can disable the function by setting bit BYTDIS to the alternate function to 1 The pin can then be used for general pur pose I O Figure 10 11 Block Diagram of Port 3 Pin Write DP3 12 Direction Latch DP35 12 Alternate Read DP3 12 F
416. te of the source bit INSTRUCTION FORMAT BXO Taoxtivy Mvenoviy Mvenoviy Onepav o Byteo BMOV MOV bitaddzz bitaddy g 4 00 22 42 4 57 S65 THOMSON ES MICROELECTRONICS A Ivotpux tiov Let BMOCN BMOCN But Bit avd Neyate 2 OPERATION 0 1 lt 0 2 DATATYPES Moves the complement of aiisglebit from the sourceperand by op2 into the destination operand specified by op1 The source bit is examined and the flags are up dated accodingy FLAGS E 2 V E Always cleared Z Contains the logical negation of the previous state of the source bit V Alwayscleared C Always cleared N Containsthe previous state of the source bit INSTRUCTION FORMAT BXO Taokivy Onepav o POPUAT Byteo BMOVN BMOVN bitaddzz bitaddag QQ 2242 4 18 84 565 0 50 A Ivotpuxuov Let BOP BOP But Aovuro OP BOP onl 2 OPERATION 1 op1 v op2 DATATYPES BIT Performs a single bit logical OR of the source bit specified by operand op2 with the desti nation bit specified by operand op1 The ORed result is then stored in op1 FLAGS E 2 V 0 NOR OR AND XOR Always cleared Contains the logical NOR ofthe two specified bits Contains the logical OR of the two specified bits Contains the logical AND of the two specified bits Contains the logical XOR of the two specified bi
417. te the destination operand over the external bus in an external program environment When internal holdanditiondetween ingruction pairs N 2 N 1 or N 1 N occur the minimum PE response time may be extended by 1 state time for each hold condition When instruction N reads an operand fromthe internal ROM or when N isa call return trap or MOV Rn Rm data16 instruction the minimum PEC response time may additally 7 2 7 External Interrupts be extended by 2 state times during internal ROM y ocun In case struction N reads the de sper pins may be used PSW and instruction N 1 has an effect on the con sa external interrupt input pins their al ternate function is noequired inconjunction with Bete tim a EE peripheral These pins are listed in table elow Table 7 5 Port Pins Configurable As External Interrupt Input Pins P20 CAPCOM Register 0 Capture Input Compare Output P215 CC1510 CAPCOM Register 15 Capture Input Compare Output 232 CAPIN CAPREL Register Capture Input 235 Timer 4 Count Gate Reload Capture Input T2IN Timer 2 Count Gate Reload Capture Input Ey SGS THOMSON 19 24 MICROELECTRONICS 7 Interrupt And Trap Functions For each of these pins either a positive a nega grammed to X01b interrupt request flags 2 or tive or both a positive and a negative external tran T4IR in registers 2 or will be set on a posi sition can be selecte
418. ted one PEC data transfer is performed the 2 pointers can optionally be incremented and an interrupt to an undetermined vector ad the channel s transfer counter COUNT can be de dress may occur cremented When the transfer counter reaches 0 7 2 6 Interruptand PEC Response Times a normal CPU interrupt request is generated and Figure 7 7 PEC Service Procedure ST10x166 Memory Space Seqment 0 PEC Service Control Destination Pointer DSTPy Increment i Source Pointer SRCPy Byte Word Decrement Zero Detect Data 8 bit Transfer Counter Transfer PEC Service Complete Service Generates Request CPU Interrupt Request VROO1623 16 24 565 50 icReRuseTRONICS 7 Interrupt And Trap Functions Interrupt response time is defined as the time re quired fromthe momentan interrupt request ofon the instructions through N 3 which are in the an enabled interrupt source is set until fetching ofpipelineat the time the request flag is set and on the first instruction atthe interrupt vector locatiortne followingwo instructions N 1 and 2 This is can begin In general the interrupt response time explainedby thepipelinediagram in figure 7 8 in the ST10x166 is 3 instruction cyclesdlipends Figure 7 8 Pipeline Diagram For Interrupt Response Dem e D Fuse m mem es psi ws we
419. ted for the data frame SOSTP 0 or S1STP 0 the correspond ing transmit interrupt request flag SOTIR or S1TIR will be setafter the last bit of the dataframe includ ing the parity or wake up bit has been sent out otherwise it will be set after the first stop bit has been sentout When a write operation to the transmit data buffer is performed while a transmission on the respec tive channel is in progress the current transmis sion will be aborted the associated output pin TXDO or TXD1 will go high and a new character frame will be sent with the data written to SOTBUF Ey SGS THOMSON MICROELECTRONICS 8 Peripherals or S1TBUF at the next overflow ofthe divide by 16 counter Continuous data transfer can be achieved by using the transmit interrupt request to reload the transmit data buffer in the interrupt service routine or by PEC datatransfer In order to use pin TXDO P3 10 or TXD1 P3 8 as transmit data output the corresponding port data output latch P3 10 or P3 8 must be setto 1 and the pin mustbe configured as output by setting its direction control bit DP3 10 or DP3 8 to 1 Asynchronous Reception Reception is initiated on channel ASCO by a de tected 1 to 0 transition on pin RXDO if bit SOR 1 and SOREN 4 and on ASC1 by a 1 to 0 transi tion RXD1 if S1R 1 and S1REN 1 The re ceive data input pins RXDO and RXD1 are sampled at 16 times the rate of the selected b
420. ted incution afterthe first iteration of a loop the PSW after each arithmetic logical shift Thus only one machine cycle is lost during the movement operation These flagsalldwanching execution of the entire loop In loops which fall on specific conditions Support for both signed andhrough upon completion no machine cycles are unsigned aithmetic is provided through user spe Jost when exiting the loop No special instructions cifiable branch tests n are also pre required to perform loops and loops are auto served automatically by the CPU upon entry to matically detected during execution of branch in interrupt or trap routine structions 2 6 ka SGS THOMSON WienesuseTRONICS The second loopenhancement allows the detec tion ofthe ends of tables and avoids the use of two compare instructionsmbedded in loops One simply places the lowest negative number at the end of the specific table and specifies branching if neither this value nor the compared value have been found Otherwise the loop is terminated if either condition has been met One can then test which condition has occurred This method is de scribed in detail in section 13 7 The thid loop enhanement provides a more flex ible solution than the Decrement and Skip on Zero instruction which is found in many other microcon trollers Through the use of Compare and Incre ment or Decrement instructions the user can make comparisons to
421. ted vector location PEC services are very well ment to the application specific requirements In suited for example for supporting the transmis addition an external count input for CAPCOM sion or reception of blocks of data or for transfer timer TO allows eventschedulingfor the cap ring A D converted results to a memory table The ture compare registers relative to external events ST10x166 has 8 PEC channels each of which of the capture compare register array contains 16 dd ever fast interrupt driven data transfer capa dual purpose capture compare registers each of which may bdndividuallgllocated to either CAP A separate control register which contains an inter COM timer TO or T1 and programmed for capture rupt request flag an interrupt enable flag and anin or compare function Each register has one port terrupt priority bitfield exists for each of thepin associated with it which serves as an input pin possible interrupt sources Via its related register for riggering the capire function or as an output each source can be programmed to one of sixteen pin to indicate the occurrence of a compare event interrupt priority levels Once having been ac When pture compare register has been se cepted by the CPU an interrupt service can only jected for capture mode the current contents ofthe be interrupted by a higher prioritized service re oc steq timer will be latched captured into the quest For the standa
422. ter CCx P2 x must be ang a bank 2 register form a register pair Both reg configured as output i e the cespondinglirec isters ofthe register pair operate on the pin associ tion control bit DP2 x in register DP2 must be set to ated with the bank 1 register pins CCOIO through 1 With this configuration the initial state of thecC716 which are the alternate functions of Port 2 output gnalcan be programmed or its state pins P2 0 through P2 7 Table 8 4 shows the rela be modified at any time by writing to bit latch P2 X tionship between the bank 1 and 2 register pairs and the affected pins for thdb ouble egister mode In order to use pin P2 x CCxlOas compare signal Figure 8 11 Timing Example for Compare Mode 3 Contents of Ty FFFFh Compare Value cv2 Compare Value cv1 Reload Value TyREL gt i 0000h Interrupt Requests TyIR CCxIR COxIR State of i Eventi Event 2 CCx cv2 CCx cv1 VROC1639 16 64 Gr SGS THOMSON TTT 8 Peripherals Table 8 4 Double Register Mode Compare Register Pairs Register Pair Associated Pin The double regiter mode can be programmed in dividually r each register pair In order to enable the double regiter mode a bank 1 register CCO through CC7 must be programmed for compare mode 1 and the cogspondingbank 2 register CC8 through CC15 must be programmed for compare mode 0 If the coespondindpank 1 com
423. terrupt service routine Once an interrupt has been selected for servicing the state of the task currently being executed by vg SGS THOMSON 88 28 YF MICROELECTRONICS 7 Interrupt And Trap Functions the CPU is saved on the system stack To ensure correct return to the location where the task had 1 The Interrupt Request Flag of the source that been interrupted the information stored on the caused the interrupt is cleared The CPU then stack also depends on whether segmentation is passes control to the source s interrupt vector The currentlyenabled as indicated by the SGTDIS bit pushed IP contains the address of the instruction in the SYSCON register to which execution will return after the interrupt service routine is completed 7 2 4 1 INTERRUPT PROCEDURE WITH SEGMEN Upon execution of the RETI instruction Return TATION DISABLED from Interrupt the information that was pushed on If segmentation islisabled the contents of the the stack ispoppedin reverse order In this way PSW and the contents of the IP are pushed on the the status of the interrupted routine is restored system stack The interrupt source s priority level isFigure 7 5 shows how the system stack is affected then copied into the CPU Priority field of the PSW When an interrupt is aciowledgedwhile segmen If a multiply or divide operation was in progresstation is disabled when the interrupt was aciowledgedthe MULIP bit in the PSW ofthe interrupt serv
424. th Rw and Rb require four bits in the instruction format The base address is determined by the contents of the CP register Rw specifies a 4 bit word GPR address relative to the base address CP while Rb specifies a 4 bit byte GPR address relative to the base address CP Specifies direct access to any SFR or GPR in the currently active context register bank regequires eighbits in the instruction format Short reg ad dresses from 00h to EFh always spec ify SFRs In that case the base address is and the facton equates 2 Dependingon the opcode of an instruction either the total word for word operations or the low byte for byte operations of an SFR can be ad dressed via reg Table 6 2 Short Addressing Modes Physical Address Short Address Range Allows Access On bitoff OFEO0h 2xreg CP 2x reg OFh CP 1 OFh OFDOOh 2xbitoff bitoff OFFOOh 2xbitoff OFFh bitoff CP 2x bitoff OFh bitoff bitaddr Word offset see bitoff bitoff Immediate Bit Position bitpos 4 8 SGS THOMSON MICROELECTRONICS Note that the high byte of an SFR can not be accessed via the reg address ing mode Short reg addresses from FOh to FFh always specify GPRs In that case only the lower four bits of reg aresignificant for physical address generationand thus it can beegarded as being identical to the address gen er
425. th a positive and a negative transition of T3OTL to cause a reload When a selected transition of T3OTL is detected the core timer T3 is reloaded with the contents of the auxiliary timer and the interrupt request flag T2IR or T4IR of the respective auxiliary timeris set Note thatthe interrupt request flag T3IR of the core timer T3 will also be set indicating the overflow un derflow of T3 Figure 8 25 shows a block diagram of this reload mode 157 SGS THOMSON VRDH1841 Note Although it is possible the user should not program both of the auxiliary timers to reload the core timer on the same trigger event since in this case both ofthe reload registers would try to reload the core timer at the same time In this case the contents of T4 are loaded into the core timer T3 The reload mode triggered by T3OTL can be used in a number of different configurations Depending on the selection of the active transition the follow ing functions can be performed If both a positive and a negative transition of is selected to trigger a reload the core timer will be reloaded with the contents of the aux iliary timer each time it overflows or underflows This is the normal reload mode reload on over flow underflow If either a positive or a negative transition of T3OTL is selected to trigger a reload the core timer will be reloaded with the contents of the auxiliary timer on every second overflow or underflow Using
426. th independent baud rate generators provide parity framing and overrun error detection Watchdog Timer with programmable time inter vals 76 Lines With Individual Bit Addressability Tri stated input mode Schmitt Trigger charac teristics Different Temperature Ranges 0 to 70 C 40 to 85 C 40 to 105 C Micron Multifunctional Cmos Process Low Power CMOS Technology including power saving Idle and Power Down modes 100 Pin Metric Plastic Quad Flat Pack PQFP Package standard 0 65mm lead spacing surface mount technology Complete Development Support C Compiler a Macro Assembler Linker Locater Library Man ager Object to Hex Converter Simulator forthe complete simulation of the CPU and the on chip peripherals Real Time In Circuit Emulator a Flash programming board for ST10F166 a Evaluation Board with monitor program Ey SGS THOMSON MICROELECTRONICS NOTES S amp S THOMSON SGS THOMSON JJ MICROELECTRONICS CHAPTER 1 ARCHITECTURAL OVERVIEW 1 ARCHITECTURAL OVERVIEW This chapter contains an overview of the 1 1 1 High Instruction Bandwidth Fast ST10x166 s architecture with combines advan Execution tages of both RISC and CISC processors in a very To achieve the desired performance a goal of ap well balanced way It introduces the features proximately one instruction executed during each which do in sum result in a high perfo
427. the internal stack will wrap around to the top ferred is determined by the average stack space Of the internal stack and continue to grow until the required by routines and the frequency of calls value of the stack overflow pointer is reached traps interrupts and returns In most cases this willbe approxirately one quarter to one tenth the size ofthe internal stack Once the transfer is com 4 8 yy 3GS THOMSON VicReRuseTRONICS 13 System Programming User stacks provide the ability to create task spe To support modular coding a procedure mecha cific data stacks and to off load data from the sys nism is provided to allow coding of frequently used tem stack The user may push both bytes and portions of code into subroutines The CALL and words onto a user stack but is responsible for us RET instructions store and restore the value of the ing theappropriad instructions whepoppingdata Instruction Pointer IP on the system stack before from the specific user stack No hardware detec and after a subroutine is executed One must also tion of overflow or underflow of a user stack is pro ensure that any data pushed onto the system stack vided The dllowing addressing modesallow during execution of the subroutinepisppedbe implementation of user stacks fore the RET instruction is executed Rb Rw or Rw Rw Post increment Indirect Addressing Used to 13 1 Passing P arameters on the System pop one b
428. the latter configuration for both auxiliary tim ers one can perform very flexible pulse width 33 64 MIGRCELECTREMICS 8 Peripherals Figure 8 26 GPT1 Timer Configuration For PWM Generation Reload Register T2 Interrupt Request Core Timer T3 ze Plum Reload R gister T4 T4l Note Line only affected by over underflows of T3 but modulation PWM One of the auxiliary timers is programmed to reload the core timer on a positive transition of T3OTL the other is programmed for a reload on anegative transition of T3OTL Thus the core timer is alternately reloaded by each of the auxiliary timers Figure 8 26 shows such a configuration of the GPT1 timers for flexible PWM T2 is programmed to reload T3 on a positive transition of T3OTL while T4 will reload T3 on a negative transition of T3OE Interrupt Request Interrupt Request NOT by software modificotions of T3OTL 011641 The alternate output function for T3OTL is enabled 1 and the PWM output signal will be available at pin T3OUT with the configura tion DP3 3 1 and P3 3 1 for port pin P3 3 as explained section 8 2 1 1 The auxiliary timer T2 holds the value of the high time of the output signal while T4 is used to reload T3 with the value ofthe low time With this method the low and high time of the PWM signal can be varied in a wide range Note that is implemented as a bit in SFR T
429. the register is allo this mode interrupt request flag CCxIR is set cated If the current timer contents match the com gach time a match is detected between the con pare value an appropriate output signal which tents of compare register CCx and the allocated based on the selected compare mode can be gen timer Several of these compare events are possi erated at the coresponding ort 2 and an in pie within a single tier period when the compare terrupt request is generated by setting the in register CCx is updated during the timer associated interrupt request flag CCxIR period The corresponding Port 2 pin P2 x is not af As forthe capture mode the compare registers are fected by compare events in this mode and can be also processed sequentially during compare used asa normal 1 0 pin mode When any two compare registers are pro If compare mode 0 is programmed for one of the grammed to the same compare value their corre registers CC8 to CC15 thelouble egister com spondinginterrupt request flags will be set to 1 pare mode becomesnabled for this register if the and the selected output signals will be generated 1 register is programmed to within 8 state times after the allocated timer is in compare mode 1 see section 8 1 2 2 5 for details cremented to the compare value Further compare thedoube register mode events on the same compare value anisabled until the timer is
430. theiggeringevent Block GPT1 contains 3 timers counterwhile occurred see also section 7 2 7 block GPT2 contains 2 timers counters and a 16 bit Capture Reload register CAPREL The GPT2 timers have a maximum resolution of 200ns at 40MHz oscillator frequency the resolution of the GPT1 timers is 400ns Each timer in each block may operateindependently in a number of differ ent modes such as gated timer or counter mode or may be concatenated with another timer of the same block The auxiliary timers of GPT1 may op tionally be configured as reload or capture regis ters for the core timer In the GPT2 block the additionalCAPREL register supports capture and reload operation with extended functionality and its core timer T6 may be concatenated with CAP COM timers TO and T1 Each block has alternate input output functions and specific interrupts asso ciated with it Figures 8 14 and 8 15 show block diagrams of and GPT2 In th ollowingthe GPT1 and GPT2 blocks will be described sepa rately Each of the 16 capture compare registers CCO through CC15 has its own bit addressable inter rupt control register CCOIC through CC151C and its own interrupt vector CCOINT hrbugh CC15INT The organization of the interrupt control registers CCOIC through CC151C is described on next page Refer to chapter 7 for more details on the interrupt control registers 57 S65 THOMSON MICROELECTRONICS Peripherals CAPCO
431. tion Reset a fe cc 4 FE9Ch CAPCOM CAPCOM Register14 14 000 5 5 CAPCOM CAPCOM Register15 15 000 CC15IC TI E CAPCOM Register 15 Interrupt Control 0000h Register e rrn ron capcommoze conrornogsiero omon _ oom ol rron capcom moas container omon ol rran nen cwcomweoscowmegser ol sen acn CAPCOM Node conroinegsiero ooon X i m e LE bi GPT2 CAPREL GPT2 CAPREL Interrupt Control Register Control Register mmm _ 2 Bits read only om From em ooon Com Fem eam Pons Drecton Reiser ome em Lom e From Pon specion Rogister Copa b rm on Pot4brectonconreRegserirs reon com Data Page Poimoro Regisier amns reom om cpu Data Page Pointer t Reiser eats oma reon om opu Data Page Poinor2 Regisier ians reon oon cpu Data Page Pointer a register apne ooon ol roe om cPUmuNipyOwaeontol Register ooon Fe0cn oon opu Mute Rogister Fgh Word _ rto om ceu MunpyoivdeRegster tow wora _ Lows o rren orm constant value Ye Register wg SGS THOMSON 156 YF MICROELECTRONICS B ST10x1
432. tion was irDetection of stack overflow underflow is supported progress in the interrupted routine MULIP 1 The MDC register holds state of the interrupted by two registers STKOV Stack Overflow Pointer and STKUN Stack Underflow Pointer Specific multiply divide instruction which is necessary in orsystem traps Stack Overflow trap Stack Under der to complete the instruction properly after theflow trap will be enteredheneverthe SP reaches RETI instruction The old MDC contents must be either boundaryspecified in these pointer regis popped from the stack before the RETI instruction ters is executed 13 3 BCD CALCULATIONS No direct support for BCD calculationgisvided in the ST10x166 BCD calculations are performed by converting between BCD data types and binary data types performing the desiredlculationsis ing standard data types Due to tlehanced per formance of division instructions one can quickl The contents of the Stack Pointer are always com pared to the contents of the Overflow register wheneverthe SP is DECREMENTED either by a Call Push or Subtract instruction An Overflow Trap will be entered when the SP value isless than the valuein the Stack Overflow register The Stack Pointer value is compared to the con tents of the Underflow register whenever the SP is INCREMENTED either by a Return Pop or Add An Underflow Trap will be entered convert from binary to BCD through di
433. tion with the addressing mode reg mem Using this instruction one can savethe old contents of the CP on the sys tem stack and move the value of the SP into CP see example in figure 13 1 Each local register is then accessedas if it was a normal register Note that the system stackjsowing downwardswhile the register bank tsgrowing upwards Upon exit from the subroutine one first re stores the old CP bpoppingt from the stack and then simply adds the number of local reg isters used to the SP to restore the allocated local space back to the system stack Example After subroutine entry SUB 10 5 Words SCXT CP SP Before exiting subroutine POP CP ADD SP 10 5 Words 6 8 3GS THOMSON Ts 13 System Programming 13 7 TABLE SEARCHING time it requests a PEC transfer or requests CPU servicing through an interrupt routine One can A number of features have beeimcludedto de also poll information from peripherals through read crease the execution time required to search ta accesses of SFRs or bit operationincluding bles First branch delays are eliminated after the branch tests on specific control bits in SFRs To first iteration of the loop Second in neguen ensure proper allocation qferipheralsamong tially searched tables thenhanced performance multiple tasks a portion of the internal memory has of the ALU allows more complicated hash algo been made bit addressable to allow user sema rithms to be p
434. tions level 15or 14 While the CPU is executinga routine the associated interrupt service routine can be on CPU priority level 14 only PEC data transfers used to reprogram the affected PEC channel A through servicechannels 4 through 7 can be proc functional diagram of the basic PEC service proce essed While the CPU is executing a routine on dure is shown in figure below CPU priority level 15 no PEC datatransfers can be Note All sources which are requesting PEC serv processed ice should be programmed to the same PEC serv When an interrupt request that has been pro ice channel ONLY if it is ensured that they do not grammed for PEC service is selected for servicing generate simultaneous requests while the COUNT by the prioritization circuit the PEC performs onefield of the respectivehannel contains 1 In the data transfer operation The data type byte or case of simu amp ineous requests where the COUNT word for this transfer is determined by bit BWT field contains a value greater than 1 at the time the the channel control register PECCy of the re PEC channel is invoked only one PEC data trans spective PEC channel The source and the desti fer will be performed for all of the simultaneous re nation ofthis data transfer are pointed to by sourcequests When the COUNT field contains 1 and pointer SRCPy and destination pointer DSTPy simultaneous PEC requests for this channel are After completion of the transfer operation one of Genera
435. to Input sg SGS THoMson 75 10 Parallel Ports As can be seen from the block diagram the user second master that the bus of the ST10x166 is software always has free access to the port pin now freefor use even when it is used as a compare output This is The pin P2 13 is used as second alternate function useful for setting up the initial level of the pin wheno pus request sign REQ This signal intends to using compare mode 1 or the double register give the ST10x166 chane to flag its own exter mode In these modes unlike in compare mode 3 nal bus request to the second master The second the pin is not set to a specific value when a master can then decide whether or not to grant the pare match occurs Instead it ieggled ST10x166 the external bus for one or more exter When the user wants to write to the port pin at the nal bus accesses same time a compare trigger tries to clock the out To enable these bus arbitration signals the bit put latch the write operation of the user software DEN of the PSW register must be set After re has priority Each time a CPU write access to the set once this bit has been set to 1 these three port output latch occurs the input multiplexerofthe ins of Port 2 can no longer be used fgeneral port output latch is switched to the line connecte urpose I O or for the CAPCOM unit even if this to the internal bus The port output latch will re Li DEN bit is cleared after once
436. to SCanned sequentially When a timer is modified or the state of the allocation control bit ACCx are incremented during this process the new timer latched into the allocated capture register CCx in Contents will already be captured for tieenaining response to an external event The external event registers within the scanning sequence causing a capture be programmed to be either If P2 x CCxlO is configured as output the capture a positive a negative or both a positive and a function may be performed by modifying port data negative transition at the respective external inputregister bit P2 x through software e g for testing pin CCxIO purposes Figure 8 5 Capture Mode Block Diagram Edge Select Copture Reg CCx Interrupt Request Semen Interrupt CAPCOM Timer Ty Request 0 15 0 1 VROB1637 57 S65 THOMSON SS MICROELECTRGNICS 8 Peripherals 8 1 2 2 COMPARE MODES 8 1 2 2 1 Compare mode 0 The compare modes allowitjgeringpf events with This is an interrupt only mode which be used minimum software overhead In all compare for software timing purposes Compare mode 0 is modes the 16 bit value stored in compare register selected for a given compare register CCx by set CCx in the following alsreferred to as compare ting bit field CCMODXx of the corgesndingmode value is continuously compared with the contentscontrol register to 100b of the timer TO or T1 to which
437. to allow the user the adaption of a wide made directly bit addressable range of different types of memories Access to The ST10166 contains 32Kbytes of mask pro very slow memories is supported via a particular grammable on chip ROM for code or constant Ready function data For applications which require less than 64Kbytes The ST10F166 contains 32Kbytes of reprogram of memory space a non segmented memory mable on chip FLASH memory for code or con model can be selected In this case all memory lo stant data cations can be addressed by 16 bits and thus Port 4 isnot needed as an otput for the two most sig A large dual port RAM of 1Kbyte is contained on all members of the ST10x166 family This internal ficant address bits A17 and A16 as is the case RAM is provided as a storage for user defined vari When using the segmented memory model ables for the system stack general purpose regis ter banks and even for code A register bank can 3 CENTRAL PROCESSING UNIT CPU consist of upto 1 amp ordwid RO to R15 and or by tewide RLO RHO RL7 RH7 called General The main core of the CPU consists of a 4 stage in Purpose Registers GPRs structiorpipelhe a 16 bit arithmetic and logic unit 512 bytes of the address space are reserved for ALU and dedicated SFRs dditionalhardware the Special Function Register SFR area SFRs has been spent for a separate multipiyd divide are wordwideregisters which are used
438. to b0 Z CCMODO Capture Compare register CCO Mode Selection See Table 8 3 Ey SGS THOMSON 9 64 o MICROELECTRGNICS 8 Peripherals 1 FF54h AAh FF58h ACh CAPCOM Mode Control Registers CCM1 CAPCOM Mode Control Registers CCM3 Reset Value 0000h Reset Value 0000h 15 14 13 12 11 10 9 8 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 See description CCMO See description CCMO 2 FF56h ABh CAPCOM Mode Control Registers CCM2 Reset Value 0000h 15 14 13 12 11 10 9 8 6 5 4 3 2 1 0 ACC9 CCMOD9 ACC8 CCMOD8 See description CCMO Table 8 3 Capture Compare Register Mode Selection CCMODx Function To o esate on Posie eterna e e evn on negao esate on Positive nd Era Tenor PROUD __ Compare Mode 0 Interrupt only several interrupts per timer period enables doub registers compare mode for registers CC8 through CC15 Compare Mode 1 Pin toggles on each match several compare events per timer period registers CCO through CC7 have to be in this mode for double register compare operate ie ie Compare Mode 2 Interrupt only only one interrupt per timer period Compare Mode 3 Pin set on match pin reset on timer overflow only one compare event per timer period Note x 0 15 10 64 Gr SGS THOMSON 8 Peripherals As each of the 16 capture compa
439. tput When an overflow of the cor responding timer occurs a 0 is written to the port set to output the state of the port output latch will latch In both h latch i be read since the pin represents the state of the OUtput latch In both cases the output latch is output latch This can be used to trigger a capture pas event through software by setting or clearing the ihe pih will be in the highpedance port latch Note that in the output configuration tate and will not reflect the state of the output latch Figure 10 4 Block Diagram of Port 2 Pin O to 12 Write DP2 y Read DP2 y Latch DP2 y Read Buffer Alternate gt Data Output Output Buffer Write Port P2 y Compare Trigger Read Port P2 y Read Buffer Alternate Latch Data Input Alternate Pin Data Input 1645 6 18 SGS THOMSON 10 Parallel Ports Figure 10 5 Block Diagram of Port 2 Pin 13 14 Write DP2 y Direction Read DP2 y Latch DP2 y Read Buffer Alternate Data Output Write Port 2 Compare Trigger Read Port P2 y Alternate Latch Data Input Alternate Pin Data Input 13 14 VROK1B43 Figure 10 6 Block Diagram of Port 2 Pin 15 Write DP2 y Direction Read DP2 y Latch DP2 y Alternate Output Data Output Buffer Write Port 2 Compare Trigger Read Port P2 y Alternate Latch Data Input Alternate Pin Da
440. ts ZzO NI INSTRUCTION FORMAT BXO Taoxtivy Mvenoviy Mvenoviy Onepav o Byteo BOR OR bitaddrz bitaddy g 0022 42 4 57 S65 THOMSON 9e MICROELECTRONICS A Ivotpux tiov Let BLET BLET onl OPERATION 0 1 lt 1 DATATYPES BIT Sets the bit specifieth operand op1 His instruction is primarily used foripberal ard system control FLAGS E 2 V E Always cleared Z Contains the logical negation of the previous state of the specified bit V Always cleared C Always cleared Contains the previous state of the specified bit INSTRUCTION FORMAT BXO Taoxtivy Mvenoviy Mvenoviy Onepav o Byteo BSET BSET bitaddg q qF QQ 2 20 84 565 0 50 A A Ivotpuxuov Let BEOP BEOP Bit 1 2 OPERATION 1 op1 op2 DATATYPES BIT Performs a single bit logical EXCLUSIVE OR of the source bit specified by operand op2 with the destination bit specified by operand op1 The XORed result is then stored in op1 FLAGS E 2 V 0 NOR OR AND xoR Always cleared Contains the logical NOR ofthe two specified bits Contains the logical OR of the two specified bits Contains the logical AND of the two specified bits Contains the logical XOR of the two specified bits ZzO NI INSTRUCTION FORMAT BXO Taoxtivy Mveuovy Mvenuoviy Onepav o Byteo BXOR XOR bitaddy
441. umps into the internal ROM space register immediately after an instruction which Tiaqa 0 or 2 x States explicitly writes to the SP register as shown in the followingexample MOV SP 40FBOOh explicitupdate of the stack pointer SCXT R1 10001 implicit decrement of the stack pointer lladaz 2 x States In these cases the extra state times can be In Ini avoided by putting other suitable instructions be fore the instruction In 1 reading the SFR 4 External operand reads Tiada 1 ACT Any external operand reading via a 16 bit data bus requires one additional ALE Cycle Tinf eading word operands via an 8 bit data bus takes twice as much time 2 ALE Cycle Times as the reading of byte operands SGS THOMSON MICROELECTRONICS As already described standard jumps into the in ternal ROM space require 4 state times to be exe cuted This minimum time will be extended by 2 additionalstate times if the branch target instruc tion is a double word instruction ahan aligned double word location xxx2h xxx6h xxxAh XxxEh as shown theflowingexample label anynon aligneddouble word instruction i e at location OFFEh cc ifa standard branch is taken Tiada 2 x States Tn 6 x States A cache jump which normally requires just 2 state times will be etended by 2 additionaltate times if both the cached jump target instruction and its Ini 7 26 5 Central Process
442. unction Enable Alternate Data Output Write Port P3 12 Ven P3 12 Buffer Read Port P3 12 Read Buffer 5cS THOMSON 0 0 0 6 10 Parallel Ports 10 1 3 4 PORT 3 PINS RXDO AND RXD1 nels read the state of pins RXDO and RXD1 via the The configuration of the two pins 0 and RXD1 line Alternate Data Input with both an alternate input and an alternate the half duplex synchronous mode pins RXDO function is shown in figure 10 12 The Alternate and RXD1 are used as either data inputs or out Data Outputline again is ANDed with the port out puts For transmission the user first must set the put latch line direction to output DP3 y 1 and must write 1 In the asynchronousmodes of the Serial Chan into the port output latch For reception the user nels pins RXDO and RXD1 are always used as must set the direction to input before starting the data inputs The direction of these pins must be When the alternate output function on these pins is not used the Alternate Data Output to Input by he User DPS y 0 The Seral Ghan line is in its inactive state whichis a high level 1 Figure 10 12 Block Diagram of Port 3 Pins RXDO and RXD1 Write DP3 y Direction Latch DPS y Read DP3 y Alternate Write Port P3 y Data Output P3 9 RXD1 P3 11 RXDO Read Port P3 y Read Buffer Alternate Dota Input 14 18 Gi
443. undaryegisters Table 5 7 Selectable Physical System Stack Ranges ao Physical Stack Spaces Size words Significant SP Bits SGs THoMson 255 5 Central Processing Unit 5 3 10 STKUN Stack Underflow Pointer This non bit addressable register is compared try into an interrupt service routine Then six addi against the SP register after each data pop opera tional stack word locations are requireddushing tion from the system stack i e for POP and RE the IP PSW and CSP registers for both the inter TURN instructions and after each addition to the rupt service and the hardware trap service For SP register If the contents of the SP register are more details about the implementation of a stack greater than the contents of the STKUN register a overflow trap service routine see chapter 13 stack overflow hardware trap will occur Stack Underflow Condition SP gt STKUN Since the least significant bit of the STKUN register is tied to 0 and bits 11 to 15 are tied to 1 by hard ware the STKUN register can only point to even STKUN FE16h 0 word addresses from OF800h through OFFFEh Stack Underflow Pointer Register Ee Mesi the STKUN register isnitialied to Reset Value FC00h A stackunderflow trap can be used foran automat UE des 10 1 8 ic filling of the system stack for example whenan external user stack is used as a storage extension 7 6 5 4 3
444. unter Control Registers Su Control Physical 8 Bit Control Physical 8 Bit Register Address Address Register Address Address PECCO FECOh mem peoos reom oom Cms em mes recon om fom SGS THOMSON 9 24 MICROELECTRGNICS 7 Interrupt And Trap Functions This will cause the Source Pointer to be incre data transfers through service channels 4 through mented after a PEC data transfer 7 can be processed BWT Byte Word Transfer Selection Bit If the Transfer Counter field has been set to FFh the continuous transfer mode is selected for the re This bit selects the data type to be transferred upon service request When the BWT bit is SPective PEC channel In this mode the COUNT set to 1 the BYTE data type is selected for a value isnot decremented which means that an un transfer limited number of transfers will be performed by this PEC channel The operation of a PEC Service When BWT is cleared the selected data type fora Channelprogrammed focontinuougransfer PEC transfer is WORD For byte transfers the op only be terminated either service tional increment value of the source or destinationor reprogramming its Channel pointer is 1 For word transfers the optional incre Counter Control register For the different possibili ment value of the source or destination pointeris2 ties of
445. ure compare register has 1 and the inactive state will be 0 In the one pin of port 2 associated with it which serves as ST10x166 the value read from reservedbitsis input pin for the capture function or as an output 0 pin forthe compare function The capture function causes the current timer con 8 1 CAPTURE COMPARE CAPCOM UNIT tents to be latched into the capture compare regis ter based on an external event on its associated The CAPCOM unit supports generation and con port 2 pin The compare function may cause an trol of timing sequences on up to 16 channels withoutput signal transition on that port 2 pin whose as a minimum of software intervention The CAPCOM sociated capture compare register matches the unit is typically used to handle high speed I O taskscurrent timer contents Specific interrupt requests such as pulse and waveform generation pulse are generated up on each capture compare event width modulation or recording of the time at whichor upon timer overflow Figure 8 1 shows a block specific events occur and it also allows the imple diagram of the CAPCOM unit mentation of up to 16 software timers The maxi resolution of the CAPCOM unit is 400ns at Pease VIVI 3 From the programmer s point of view the term TUM CAPCOM unit refers to a set of SFRs which are CAPCOM Block Diagram associated with thiperipheraljncludingthe port The CAPCOM unit consists of two 16 bittimers TO p
446. us section now for compare mode 3 The setting bit field CCMODx of the aesponding functional block diagram of a compare register in mode control register t611b In compare mode mode 3 is included in figure 8 9 of the pre 3 only one compare event will be generated per vious section Note that in compare mode 3 the timer period port latch is set by the compare event and reset by the next timer overflow When the first match within the timer period is de tected interrupt request flag CCxIR is set to 1 and pin CCxIO alternate function of Port 2 pin P2 x 8 1 2 2 5 DoubleRegister Compare Mode COM T The pin leds In the double egister compare mode two com allocated timer overtiows match was found pare registers work together to control one register CCx in this mode all further compare This mode is selected by a speciabmbinatiorof events during the current timer period disabled modes for the two registers for CCx until the corrgmndingimer overflows If after a match was detected the compare register For thedouble egister mode the 16 capture com is reloadedwith new value this value will notbe Pare registers are regarded as two banks of 8 reg come effective until the next timer period isters each Registers CCO through CC7 form bank 1 while registers CC8 through CC15 form bank 2 8 For the double register mode a bank 1 register output pin for compare regis
447. uses the value to be written into the port out grammed input or output via the respective Cl put latch while a read operation returns the rection control bit DPx y Figure 10 1 shows jatched state of the pin itself A read modify write general block diagram of port as is config gneration reads the value of the pin modifies it ured when used as a general purpose I O port and writes it back to the output latch Port pins selected as inputs DPx y 0 are Writing to a pin configured as an output placed into high ipedance state since the ppy y 1 causes the output latch and the pin to put buffer is disabled This is the default the written value ince the output buffer is tion after reset During reset all port pins enabled Readingthis pin returns the value of the configured for input When exiting reset while NOoutput latch A read modify write operation reads external bus function is selected all port pins re the value of the output latch modifies it and writes main in input mode unless configured otherwise by Hui the user When an external bus is selected the S SEI moditying ine Figure 10 1 Block Diagram of a Port 0 through 4 General Purpose Write DPx y Direction Latch DPx y Read DPx y Read Buffer Write Port Px y Output Buffer Read Port Px y Clock Read Buffer 0 4 0 15 for x 0 3 0 1
448. visions by 10when the SP value is greater than the value in the of binary data types Conversion from BCD to bi nary isenhaneed by multiple bit shift instructions Thus similar performance is achieved in compari son to instructionshich would apport BCD data types while nadditionahardware is required 13 4 STACK OPERATIONS Ey SGS THOMSON Stack Underflow register When a value is MOVED into the Stack Pointer NO check against the Overflow Underflow regis ters is performed 13 4 1 1 USE OF STACK UNDERFLOW OVERFLOW REGISTERS 3 8 MICROELECTRGNICS 13 System Programming In many cases he user will place 8ftware Re plete he boundarypointers are updated to reflect set SRST instruction in the stack underflow and the newly allocated space on the internal stack overflow trap service routines indicating a fatal er Thus the user is free to write code without concern ror However itis also possible to use the stack un for the internal stack limits Only the execution time derflow and stack overflow registers to cache required by the trap routines is seen by user pro portions of a larger external stack Th shnique grams places only the portion of the system stack cur Because of circular stacking data accessed at the rently being used in the internal memory thus al boundary limits of the internal stack is accessed as lowing a greater portion of the internal RAM to be no boundary existed When data is pushed be
449. w bperandop1 is decremented by two Using the set flags a branch instruction can then be used in conjunction with this in struction to form common high leke iguageFOR loops of any range FLAGS E 2 V E Setifthe value of op2 representsthe lowest possible negative number Cleared oth erwise Used to signal the end of a table 2 Set if the result equals zero Cleared otherwise V Set if an arithmetic underflow occurred i e the result can not be represented in the specified data type Cleared otherwise C Setifa borrow is generated Cleared otherwise Setif the most significant bit of the result is set Cleared otherwise INSTRUCTION FORMAT BXO Taoxtivy Mvenoviy Mvenoviy Onepav o Byteo CMPD2 CMPD2 Rw data BO Zn 2 CMPD2 CMPD2 Rwn datas B6 Fn 4 CMPD2 CMPD2 B2 Fn MM MM 4 30 84 SGS THOMSO A A Ivotpuxuov Let XMIIII XMIIII Ivypeuevt By 1 1 2 OPERATION 0 1 0 2 1 op1 1 DATATYPES WORD This instruction is used to enhance the performance and flexibility of loops The source op erand specified by op1 is compared to the source operand specified by op2 by performing a 2 s complement binary subtraction of op2 from op1 Operand op1 may specify ONLY GPR registers Once the subtraction has cpleted the 1 is incremented by one Using the set flags a branch instructio
450. w or Rb Context 4 Bit GPR Pointer Address Internal RAM Must be situated in the internal RAM area 1 for byte GPR accesses 2 for word GPR occesses VROO1635 Figure 5 9 Implicit CP Use by Short 8 Bit Addressing Specified by reg or bitoff 0 44 Context 4 Bit GPR Pointer Address Internal RAM Must be situated in the internal RAM area 1 for byte GPR accesses 2 for word GPR accesses VROA1635 SGS THOMSON 2 5 5 Central Processing Unit Figure 5 10 Register Bank Selection via the 5 3 9 SP Stack Pointer CP register This non bit addressable register is used to point to the top of the internal system stack TOS The SP Internal RAM register is pre decrementadheneverdata is to be pushed onto the stack and it is post incremented whenever data is to be popped from the stack Thus the system stack grows from higher toward lower memory locations Since the least significant bit of the SP register is tied to 0 and bits 11 to 15 are tied to 1 by hard ware the SP register can only point to even word addresses from OF800h to OFFFEh After reset the SP register is initialized to FCOOh The SP register can be updated via any instruction which is capable of modifying an SFR Based on the internal instruction pipeline a POP or RETURN instruction must not immediatly follow an instruc tion updating the SP register The maximum system stack size is programmable via the STKSZ
451. ware or not in the al The incoming data on Port0 is read on the line Al ternate function mode ternate Data Input While an external bus mode is s enabled the user software should not write to the The followingsections describe in detail each of port output latch otherwise unpredictable results the ports and its alternate input and output func may occur When the external bus modes are again tions disabled the contents of the direction register last written by the user become active While the 16 18 10 1 1 Port O and Port 1 Bit Address 8 Bit Data Non Multiplexed Bus mode is enabled the upper half of Port 0 can not be used Port 0 and Port 1 are two 16 bit I O ports They are for general purpose I O 418 Ey SGS THOMSON MICROELECTRONICS 10 Parallel Ports Figure 10 2 Block Diagram of a Port 0 Pin Alternate Write DPO y Direction Direction Latch DPO y Read DPO y Alternate Function Enable Alternate Function Enable write Port PO y Alternate Data Output Output Buffer Read Port PO y Clock Read Buffer Alternate Dato Input VROAT543 Figure 10 3 Block Diagram of a Port 1 Pin Write DP1 y Direction Latch DP1 y Read DP1 y Alternate Function Enable Read Buffer Alternate Function Enable Write Port Ply Alternate Data Output Read Port P1 y Read Buffer VHOB1643 sg SGS THoMson 55 10 Parallel Ports 10 1 2 Port2 external device ma
452. when accessing a sloweripheraldevice This example could be the case when accessing a which inthis case is slower than a normal bus cy memory which just requires three wait states and cle with three wait states where theREADY line is brought to low with the Chip Select signal for the memory In Figure 9 17 b after insertion of all three wait states the Figure 9 17 Using READY And Wait States Example c Example b READY Line is Checked 001619 20 20 SGS THOMSON o MICROELECTRONICS SGS THOMSON JJ MICROELECTRONICS CHAPTER 10 PARALLEL PORTS 10 PARALLEL PORTS The ST10x166 provides 7 arallel O lines organ followingsubsections first give a general de ized into four 16 bit I O ports Port 0 through 3 scription of Ports 0 through 4 then each of these one 2 bit I O port Port 4 and one 10 bitinput port ports is described in detail Port 5 will be discussed Port 5 All port lines are bit addressable and all separately in section 10 2 lines of Port 0 through 4 are individually bit wise programmable as inputs or outputs via direction registers Each port line has one programmable alternate in Each of the Ports 0 through 4 has its own port data put or output function associated with it PortO andregister PO through P4 and direction register Port 1 may be used as the address and data lines through The 16 bit data registers PO when accessing external memory Por
453. word wide data output The least significantpled together as one word wide memory and indi address bit AO is normally not used when access vidually as twondependenbyte memories ing word organized memories Since two inde Eor the case where the two memories are ac pendent buses are used no time miplexingand cessed coupled together as one word wide mem no additiona ddress latch is required in this case ory the addressing scheme is the same as if only As long as memory segmentation is not disabled 16 bit wide memory was used For the case Port 4 isadditionallyised as an output for the where the memories are also accessed as inde significant bits of the required 18 bit ad pendently suitable byte wide memories the Exter 5585 nal Bus Controller EBC must lemabledto use the Compared with the other external bus configura function of the Byte Highriable pin as de tion modes the 16 18 bit Address 16 bit Data scribed in the previous section 9 5 Non MultiplexedBus mode provides the highest Detailed applicationexamples for the just men Vel of Ja ais Lec enini tioned external bus and memory configuration are SKANS eos Y shown inappendixC This external bus mode can be selected if the Figure 9 6 16 18 Bit Address 16 Bit Data Non Multiplexed Bus Word Wide Memories Seqment Addr Port 4 WR RD Port ST10x166 ADDR WR 16 Bit External Memory INSTR DATA
454. x on the internal system stack A prioritization ceptions that arise during the execution of an scheme with 16 priority levels allows the user to instruction Hardware traps always have highest specify the order in which multiple interrupt re priority and cause immediate system reaction The quests are to be handled software trap function is invoked by the TRAP in Interrupt Processing via the Peripheral Event struction which generates a software interruptfor a Controller PEC specified interrupt vector For all types of traps the current program status is saved on the system As a faster alternative to normal software oriented stack interrupt processing any interrupt requesting source can also be serviced by the ST10x166 s in tegrated Peripheral EverfZontroller Upon an in terrupt request the PEC has theapability of pus on the Flash memory This condition can be avoid data pages 0 through 3 through one of eight pro ed with the Flash memory located in segment 1 grammable Servic hannels During aPEC and the program code in segment 0 external transfer the normal program execution of the CPU Memory Warning When program code is installed in the Flash memory ST10F166 and located in seg ment 0 the CPU can receive an interrupt but will not be able to service it during aiting operation 1 24 7 Interrupt And Trap Functions 7 1 INTERRUPT SYSTEM STRUCTURE In order to support modular and c
455. xAv01 e OP onl 2 OPERATION 1 1 op2 DATATYPES WORD Performs a bitwise logical EXCLUSIVE OR on each bit of the source operand specified by op2 and the destination operand specified by op1 The resultis then stored in op1 FLAGS E 2 V E Setifthe value of op2 represents the lowest possible negative number Cleared oth erwise Used to signal the end of a table 2 Set if result equals zero Cleared otherwise V Alwayscleared C Always cleared Setif the most significant bit of the result is set Cleared otherwise INSTRUCTION FORMAT B O T amp oxKxvy Mveuoviy Onepav o Byteo XOR XOR Rwn RWm 50 nm 2 XOR XOR Rwn datas 58 n 0 2 XOR XOR reg datag 56 RR 4 XOR XOR Rw 58 n 10ii 2 XOR XOR Rw Rw 58 n 11ii 2 XOR XOR reg mem 52 RR MM MM 4 XOR XOR mem reg 54 RR MM MM 4 Ey SGS THOMSON 83 84 o MICROELECTRGNICS A Ivotpux tiov Let EExAv01 e OP FLAGS Mvenoviy XORB XORB XORB XORB XORB XORB XORB 84 84 onl 2 OPERATION op1 op1 amp 0 2 DATATYPES BYTE Performs a bitwise logical EXCLUSIVE OR on each bit of the source operand specified by op2 and the destination operand specified by op1 The resultis then stored in op1 E 2 V E Setifthe value of op2 represents the lowest possible negative number Cleared oth erwise Used to signa
456. xternal memory and the inter 5 time in the ST10x166 is 2 instruction cy rupt vector location is also in external memory butCles k depends on the irtsuctions N 3 through all operands for instructions N 3 through N are inWhich arein theipelineat the momentthe request internal memory then the interrupt response time is set and on th ollowinginstruction 1 is the time to perform 3 word bus accesses Under This is explainedy thepipelinediagram in figure the same onditionsbut with the interrupt vector 7 9 Figure 7 9 Pipeline Diagram For PEC Response Time Ce e e a me iw ws re 1 IR Flag 0 PEC Response Time is equivalent to MOV B DSTPx SRCPx or MOV B DSTPx SRCPx or MOV B DSTPx SRCPx 0 18 24 SGS THOMSON 7 Interrupt And Trap Functions Once per instruction cycle adhabled interrupt response time during internal ROM program sources whose interrupt request flags have been execution is 9 state times 350ns at 40MHz set during the previous cycle compete for service The absolute worst case PEC response time will in a round of prioritization In the next cycle the occur when instructions N and N 1 are executed PEC data transfer is started when thwinning out of an external memory and both require exter source was programmed for PEC service and the nal operand read acces
457. y a new erasing pulse to the block and continue until the data is correctly checked or the maximum erase pulse count 3000 has been reached read ff cmp all1 fl sc an first ins truct ion for EVM call a cc UC wait4 4 us cmp all fl sc an secondin struc tion for EVM jmpr cc NZ erase jump if the word isnote rased e AAXT AAAPEXX Check the address variable to see if the last address of the block has been reached If not increment the address variable and start another Erase Verify Read add fl _scan 02h incre ment the bank poi nter cmp fl_scan FL_ SIZE compa to the last banka ddress jmpr cc_NZ re ad_ff jump to verif ythenextad dress e 0 All the block is erased exit the Presto F Erase algorithoppingall erasure or erase verify read operations with a reset of FCR register especially FWE FEE bits cleared Normal reading of Flash memory can be performed only after this step YXINI THE MEMOP P Follow the Presto F Algorithm and verify its correct implementation This will ensure that all the block has been programmed before erasure to minimize internal stresses on the memory cells and to perform writing operation ina fast anrbliableway Verify VPP status before and after every writing operation BAXIX EPAXYPE ANA This section describes basic routines which can be helpful for the user Erasure 32 bit programmi
458. y accessed All of the justttioned implicit internal RAM accesses are made inde 3 3 INTERNAL RAM pendent of the current DPP register contents The upper portion of the internal RAM addresses The ST10x166 contains 1Kbyte of on chip dual from to OFDFFh and the currently active port RAM which is organized 512x16 bytes In GPRs are provided for single bit storage and thus ternal RAM accesses are alwayenabled they are bit addressable The system stack the General Purpose Registers The followingsubsections describe in more detail GPRs and the PEC source and destination point the organization of the system stack of the GPRs ers are situated within the internal RAM space Ad and ofthe PEC source and destination pointers ditionallythe internal RAM be used for both code and data storage The ST10x166 assembler supports the reservation of the required internal3 3 1 System Stack RAM areas according to the just mentioned par The internal RAM address space from OFBFFh ticular uses downwardto OFAOO0h is basically provided for the Code accessesare always made on even byte ad ST10x166 ssystem stack implementation The de dresses Provided that the PEC source and desti fault maximum stack size of 256 words can easily nation pointers are not required the highest be reduced by bangingthe stack size STKSZ bit possible code storage location in the internal RAMfield in the SYSCON register as shown in the fol low
459. y drive the pin otherwise con All of the 16 pins of Port 2 P2 may be used for the f icts would occur alternate input output functions of the CAPCOM When a Port 2 line is used as a compare output unit They serve as an input line for the capture compare modes 1 and 3 refer to chapter 8 1 the function or as an output line for the compare func compare event or the timer overflow in compare tions The alternate symbols CCOlOhrbpugh mode 3 directly affects the port output latch In CC151O have been assigned to Port 2 mddition compare mode 1 when a valid compare match oc to the standard symbols P2 0 through P2 15 in or curs the state of the port output latch is read by the der to reflect its alternate functions Figures 10 4 CAPCOM control hardware via the line Alternate to 10 6 show block diagrams of Port2 pins Latch Data Input inverted and written back to the When a Port 2 line is used as a capture input the latch via the line Alternate Data Output The port state of the input latch which represents the state OUtput latch is clocked by the signal Compare Trig of the port is directed to the CAPCOM unit via 967 Which is generated by the CAPCOM unit In the line Alternate Pin Data Input The user software COMpare mode 3 when a match occurs the value must set the direction of the pin to input if an exter 1 S written to the port output latch via the line Al nal capture trigger signal is used If the direction isternate Data Ou
460. y space can be accessed in such a manner Word ac cesses may not be performed on odd byte ad dresses Otherwise a hardwaredp would ocur After reset the DPP registers are initialized in a way that all long addresses are directhapped onto the identical physical addresses Table 6 3 Long Addressing Mode 6 Instruction Set Overview Any long 16 bit address consists of two portions which are interpreted in different ways Bits 0 to 13 specify a 14 bit data page offset address while bits 14 to 15 specify that of the four Data Page Pointer registers which is to be used to generate the physi cal 18 bit address as described below At present the ST10x166 supports 256 Kbytes of address space and thus only the lowest four bits of the selected DPP register contents are added to the 14 bit data page offset address In case of seg mentation being disabled all data accesses are re stricted on segment 0 and thus only the lowest two bits of the selected DPP register are significant at all For more details about data paging see sec tion 5 3 7 The long addressing mode is represented by the mnemonic mem Table 6 3 shows the association between long 16 bit addresses and the corre spondinqData Page Pointer registers Physical Address Long Address Range Allows Access On mem 3FFFh mem 3FFFh mem 3FFFh mem 3FFFh DPPO DPP1 DPP2 DPP3 Long Address Bits 15 14 0000 3FFFh 4000 7FFFh 8000 BFFFh CO00
461. yte or word from a user stack This Stack mode is onlyavailablefor MOV instructions and can specify any GPR as the user stack Parameters may be passed on the system stack pointer through PUSHinstructions before the subroutine is called and POP instructions during execution of Rw Rb Rw the subroutine Base plus offset indirect address Indirect Addressing Used to 119 also permits access to parameters without pop ush one byte or word onto a user stack This ping parameters Tom Stack auring p 4 y oe execution of the subroutine Indirect addressing mode is onlyavailablefor MOV instructions provides a mechanism of accessing data refer and can specify any GPR as the user stack enced by data pointers which are passed to the pointer subroutine Rb IR Rw Rwal In addition two instructions have been imple Rw or Rw mented to allow one parameter to be passed on Post increment Index Register Indirect Ad the system stack withoatiditionaboftware over dressing Used to pop one byte or word from a head buon ERE The PCALL push and call instruction first pushes fied as the user stack pointer the reg operand and the IP contents on the sys tem stack and then passes control to the subrou tine specified by the caddr operand 13 5 REGISTER BANKING When exiting from the subroutine the RETP re turn and pop instruction first pops the and
462. z bitadd g QQ 2242 4 57 S6S THOMSON FUE MICROELECTRONICS A Ivotpux tiov Let XAAAA XAAAA LoBpovtive o7l 2 OPERATION IF 1 THEN SP SP 2 SP IP IP op2 ELSE END IF If the condition specified by op1 is met a branch to the absolute memory location specified by the second operand 2 is taken The value of the instruction pointer IP is placed onto the system stack Because the IP always points to the instructilbovting branch in struction the value stored onthe system stack represents the return addressoad time routine If the ondition isvot met no action is taken and the next instruction is executed normally CONDITION CODES See Table A 1 next instruction FLAGS E Z V C N E Not affected Z Not affected V Not affected Not affected N Not affected INSTRUCTION FORMAT BXO Taoxvy Onepav o Byteo CALLA CALL cc caddr CA c0 MM MM 4 22 84 SGS THOMSO AJ M Ivotpvuyuov A 1 Bpavyn avd Ivotpuxtiovo A OXpUULOV Xov vuov usd 4 Oo EN ewe Cay O Ema ae cene z 0 Norga cout ceure c 1 unsignediessthanaguai __ Fh C _

ST10166 16-BIT MCU USER MANUAL

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