FE100/200(-M) - ICwIC 中国IC世界 IC World In China
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1. CMOS Input 0 3 VDD 0 7 VDD Absolute Input Range 0 5 to VDD 0 5 Input Description Operating Operating Abs Max Abs Max Type V min V max V min V max Thermal Head Analog Input 0 2 VDD 0 8 VDD VDD 0 5 Video Analog In VADV 0 5 Video A D Vref 08 05 VADV 05 C H HU T TU OSC V y VADV 05 v NE CENE FRE VADV VADG v G HEC VDRAM X VBAT Battery Power for 0 5 RTC SRAM Output Signal Characteristics 1XC CMOS Output VDD 1 Output Description VOL IOL VOH IOH Type V max ma max V min ma max 5 1XP 2 High Capacitance Driver VDD 1 5 5 A A VR R XG DD ND XC CMOS Output VDD 1 XT XS XL XC XP XC T N Njo ojo 4 A 2 2 2 LED Driver VDD 1 5 CMOS Output Open Drain CMOS Output High Capacitance Driver 3X 4 CMOS Output 123XT 1 2 3X Tristate Output 1 6 4 6 24 1 6 4 6 2 2 3 3 TTL Output 2X 4 4 1X 2X 3X 4X wlio N aja a a oja ja ojojo 91 CL pF max MD219 FE100 200 M eXtended FAXENGINE Device Set 99 3 SWGAINO 96 1 RLSDn 88 1 DAOUT 85 7 EYECLK 84 EYECLKX 83 7 EYESYNC 100 1 GP02 5 ovb2 LI TxD ctsn 5 ovb2 GP17 GP16 SYNCIN2 G2XCLK D7 L3 DCLKI IRQ2n D6 5VD1 D5 D4 LI XCLK D3 LA XTLO D2 EA XTLI D1 LI PoRin DO L3 2 0 2 EN85n2. RTSn RAMPIN GP11 NC SEE NOTE 1 NC GP13 OVA RSO 5VD2 RS1 OVD1 RS2 SWGAINI 53 ECLKIN1 RS4 SYNCIN1 READn NC CSn NC WRITEn NC IRQn NC 99 cocoooocooooo O o o oo c Wmcosm aaa ROR DAIN C 34 ADOUT C 35 BYPASS C 36 RCVI C 37 TXLOSS3 C 38 NC 141 CJ 42 ova 43 TXOUT 744 RXIN 745 5VA C 46 ova 47 AGD 748 AOUT 749 1 150 TXLOSS2 139 TXLOSS1 C 40 MD125F3 MDMPA100F Notes 1 For R96DFXL connect pin 62 to 5VD1 or leave open nc For R144EFXL connect pin 62 to 5VD1 2 Names in parentheses apply to R144EFXL only Figure 3 R96DFXL and R144EFXL Facsimile Modem Pin Assignments MD219 15 FE100 200 M eXtended FAXENGINE Device Set 99 98 D7 D6 D5 D4 D3 D2 D1 WRITE DGND1 RXOUT RMODE TSTROBE TRESET DGNDA1 NC TMODE TXDAT AVDD TALK AGND1 TXA1 TXA2 DGNDA2 DCLK RLSD NC SR4OUT EYEXY SR1IO EYESYNC SR30UT 97 1 DGND5 96 95 94 93 92 91 38 39 40 90 89 88 87 86 85 84 83 41 42 43 44 45 46 47 48 49 82 1 SR4IN 4 x 81 denda 50 Figure 4 RFX96V24 S and RFX144V24 S Facsimile Modem Pin Assignments NC RXDAT RMODE RRESET RSTROBE TSTROBE TRESET 1 _ 35 SLEEP CJ 36 AGND2 C 37 TMODE 12 z z z z z z RIN TXDAT 13 VREF NC NC DGNDA3 SPKR VAA2 OH POR CLKIN
3. 0 4XC Indicates outputs OPO 7 0 are for LEDs AA cocs s 0 XC jtoDehipsee o General Purpose I O GPIOMJCPCIN 10 2xC_ Hysteresis In GPIO 4 or Calling Party ContolInput GPIOB SSCLK2 vO 2xC_ Hysteresis In GPIO S or SSCLK2 for SSIF2 GPIOUySSRXD2 se vO 2xC_ Hysteresis In GPIO 7 or SSRXD2 for SSIF2 GPIO 8 FWRn 85 2XC In GPIO 8 or flash write enable signal for NAND type flash memory GPIO 9 FRDn 84 H 2XC Hysteresis In GPIO 9 or flash read enable signal for NAND type flash memory GPIO 10 83 VO H 2XC__ Hysteresis In GPIO 10 or SSSTAT2 for SSIF2 SSSTAT2 GPIO 11 BE 82 H 1XC Hysteresis In GPIO 11 or bus enable or serial port data input for SERINP autobaud detection MD219 FE100 200 M eXtended FAXENGINE Device Set Table 5 FC100 200 Pin Assignments Cont d y o Input Output Pin Description Type Type General Purpose I O Cont d GPlolizuCS 2n 0 VO exc GPIO 14J CS 4 n 2 15J CS 5 n 77 2XC 16VIRQ 8 17 18 IRQ 9 n 19 RDY SEROUT GPIO 20 ALTTONE Q 2 Q V gg Q 39 5 DID 2 Oojo 103 106 115 118 Power Reference V R VR SM 3 0 GPO PM 3 0 GPO TONE 7 4 3 0 76 75 74 73 07 1 7 Vref CLREF ADXG lt gt c ADGA ADVA 0 ADGD 2 lt gt
4. 1297 Test clock 1 6 8 13 EE 15 20 22 27 141 144 wen 7 o 29XT write strobe RoMcsn Pd EJES ROMCSn o 123XT ROM chip select Beim pe EIES EIES Ww o O fe 3 3 e 5 A D gt N 2 123XT Address bus 24 bit Ni 123XT Data bus 8 bit 123XT Read strobe chip select 9 SRAM chip select Battery powered 123XT Modem chip select 123XT SYNC Indicates CPU op code fetch cycle active high 123XT Indicates REGSEL cycle and DMA cycle REGDMA 123XT Indicates current TSTCLK cycle is a wait state or a halt state WAIT 123XT_ DRAM row address select Battery powered CAS 1 0 n 111 112 fo 123XT_ DRAM column address select Battery powered owen 1 0 123 ORAM write Battery powered Prime Power Reset Logic and Test 5 0 DEBUGn o External non maskable input NMI RESETn FC100 200 Reset TEST 8 Pi coc Sets Test mode battery powered 9 2 1 5 Battery Power Control and Reset Logic sa 1 OSC jOysmlosilatorimputpin ____ O 6 Crystal oscillator output power Results in NMI Used by external system to indicate to FC100 200 oss of prime BATRSTn Battery power reset input WRPROTn 1 9 uo 98 Fosinvipomo 9 7 1 0 1XC Battery powered Write protect during los
5. R96FE200 v24 ReGFE200 Va4S R96FE200M 200 ROGFE200 MV24 R9GFE200 MV24S RI44FE200 RIM4FE200C 144 200 40 144 200 248 RIA4FE200M RI44FE200 MC 144 200 24 144 200 246 MD219 3 FE100 200 M eXtended FAXENGINE Device Set FAXENGINE Firmware The FAXENGINE firmware includes a complete software package core code and application code for the development of a customized facsimile machine The following features are supported by the firmware e A real time multitasking environment Modular software design e 30 protocol Call progress support for multiple countries 4 MH MR compression and decompression control T 6MMR Alternating compression decompression and Page Memory handling management M only 4 to A4 reduction Fax transmit receive and copy capabilities Polling Tx Rx Broadcast and Delayed Transmission functions M only Digital Answering Machine functions V or VS only Full duplex Digital Speakerphone function VS only Error diffusion FC200 and FC200 M only e 64 level Dither Table support NAND or NOR type Flash memory control and support e Programmable resolution conversion Voice Fax Discrimination Caller ID Core Code The Core Code provides the functions with close functional proximity to the FE100 200 M hardware The Core Code is provided in objec
6. cast delayed capabilities and receiving to memory e Resolution conversion e Multi level and bi level B4 to A4 reduction e Digital answering machine support e Full duplex digital speakerphone The supplied firmware allows conditional inclusion of the following items some of which automatically add other options as noted e FC100 200 type MMR and ACD option e Modem type e ECM RAM and size of Comm Buffer e Speakerphone e UART interface for debug e Scan image processing enabled disabled e Line ORing enabled disabled Call progress country e Language for operator interface e Fax mechanism Specifies parameter ranges for scanning and printing timing scanner and printer width shading correction and edge enhancement threshold value MD219 FE100 200 M eXtended FAXENGINE Device Set See detail A CHAM 4X TOP VIEW SIDE VIEW Millimeters Inches Min Max Min Max A 2 4 MAX 0 0945 MAX A1 0 05 0 35 0 0020 0 0138 A2 2 0 REF 0 0787 REF D 22 95 23 45 0 9035 0 9232 D1 20 0 REF 0 7874 REF D2 18 85 REF 0 7421 REF 1695 1745 06673 0 6870 1 14 0 REF 0 5512 REF E2 12 35 REF 0 4862 REF L 073 1 03 0 0287 0 0406 Li 1 6 REF 0 0630 REF e 0 65 BSC 0 0256 BSC b 025 045 0 0098 0 0177 013 019 0 0051 0 0075 Coplanarity 0 10 MAX 0 004 MAX Ref 100 PIN GP00 D234 DETAIL A Metric values millimeters should
7. 09 01 East Tower Singapore 237994 Phone 65 737 7355 Fax 65 737 9077 Australia Phone 61 2 9869 4088 Fax 61 2 9869 4077 China Phone 86 2 6361 2515 Fax 86 2 6361 2516 Hong Kong Phone 852 2827 0181 Fax 852 2827 6488 India Phone 91 11 692 4780 Fax 91 11 692 4712 Korea Phone 82 2 565 2880 Fax 82 2 565 1440 Europe Headquarters Conexant Systems France Les Taissounieres B1 1680 Route des Dolines BP 283 06905 Sophia Antipolis Cedex France Phone 33 4 93 00 33 35 Fax 33 4 93 00 33 03 Europe Central Phone 49 89 829 1320 Fax 49 89 834 2734 Europe Mediterranean Phone 39 02 9317 9911 Fax 39 02 9317 9913 Europe North Phone 44 1344 486 444 Fax 44 1344 486 555 Europe South Phone 33 1 41 44 36 50 Fax 33 1 41 44 36 90 Middle East Headquarters Conexant Systems Commercial Israel Ltd P O Box 12660 Herzlia 46733 Israel Phone 972 9 952 4064 Fax 972 9 951 3924 Japan Headquarters Conexant Systems Japan Co Ltd Shimomoto Building 1 46 3 Hatsudai Shibuya ku Tokyo 151 0061 Japan Phone 81 3 5371 1567 Fax 81 3 5371 1501 Taiwan Headquarters Conexant Systems Taiwan Co Ltd Room 2808 333 International Trade Building Keelung Road Section 1 Taipei 110 Taiwan ROC Phone 886 2 2720 0282 Fax 886 2 2757 6760
8. 2 R144FE100 MV24 R144FE100 MV24S R96FE200 R96FE200 C R96FE200 V24 96 200 245 96 200 R96FE200 MC R96FE200 MV24 R96FE200 MV24S RI44FE200 C R144FE200 V24 R144FE200 V24S R144FE200 M R144FE200 MC R144FE200 MV24 R144FE200 MV24S FC200 M RFX144V24 S Notes 1 MH MR compression and decompression 2 MH MR MMR and Alternating Compression Decompression for Page memory 2 lt o 2 o X o lt o 2 lt o lt 2 o eo eo lt gt gt lt 2 2 lt 2 2 lt lt o lt o 2 2 2 z lt o 2 L Wes 1 Yes Ye Yes Yes Yes 2 lt o lt o lt o 2 2 o Ke o 2 lt o 2 lt o zig o lt lt o 2 z o lt o 2 2 lt o o o o o X o 2 zs o lt o lt o 2 2 z lt lt o lt jojo o o o 2 lt o o lt o lt 96 1000 2 9 6 100 R96FE100 v24 R96FE100 v245 96 100 96 100 455 96 100 24 6 100 246 RI44FE100 0 2 Rise 14 4 00 40 144 100 248 144 100 RI44FETO0 MC 144 100 24 RI44FE100 MV24S ROGFE200 N ROGFE200 C
9. layered structure that allows for replacement of any of these subroutines by OEM written custom subroutines Core Code routines are organized in a library and the Core Code linkage routine optimizes ROM space code by preventing code duplication when Core Code routines are unused or replaced by Developer routines Application Code The Application Code provides source assembly code for a complete facsimile machine application The Application Code links to the Core Code functions to control the FAXENGINE peripheral functions The Application Code performs customized functions to provide flexibility to enable the following e Scanner and printer control e Operator panel control Keypad LED LCD Beeper Scan document handling pull in and eject e Printer paper handling eject and cut e page Setup controls for the facsimile machine date and time header transmit level e Call progress controls with parameter tables to allow modification for PTT requirements in different countries e T 30 control by generating frame content and sequence used during a T 30 negotiation e Fax Voice discrimination with external answering machine interface Conditional Assembly Other supported functions included in the final object code when the appropriate conditional assembly Switches are enabled are as follows e Error Correction Mode ECM e Flash memory Voice storage e Page Memory support that includes broad
10. 2 1 SSRXD 2 1 TATI2 1 General GPIO Purpose I O Sync Async Serial Port SASIF SASCLK A XD ASBXD FC100 200 M XOUT RTC Crystal SYSCLK A 4 0 DIZ 0 RDn WRn UO n External Bus Q 20 5 o S 5 0 n WRPROTn FRDn ERWn FCLE FCS 0 2 EBUGn VDD VDRAM Notes Telephone Line Speaker Microphone Circuit Line Interface SPKR RXDAT XDA RMODE IMO MONOFAX Facsimile Modem SLEEPS Q DRAM option GPIO 510 11 RASn DWR Flash Memory Alternative or GPIO lines Speakerphone only Voice or speakerphone Figure 1 FE100 200 Functional Interconnect Diagram MD219 FE100 200 M eXtended FAXENGINE Device Set DRAM Controller The DRAM controller supports memory devices of the sizes number of bits and access speeds tabulated below DRAM memory space is divided into three blocks thus if 4 MB chips are used a maximum of 8 MB of DRAM is supported Each block has a programmable size and starting address Addressing Size 4 MB 1MB 512K 256K Access Speed ns 60 to 150 DRAM controller provides battery backup refresh using DRAM battery power VDRAM Bi Level Resolution Conversion M only Bi level expansion to 200 and reduction down to 33 can be performed on either the scanner bi level data or the bi level data output by the T4 T6 decompression hardware Flash Memory Control
11. 4 2 n and CS5n Interrupt Signals Up to three external interrupts are provided IRQ8 GPIO16 is an active high level sensitive interrupt and IRQ9n GPIO18 is an active low level sensitive interrupt MIRQn is dedicated to the modem Scanner and Printer Motor Control Eight outputs are provided to external current drivers four to the scanner motor and four to the printer motor The printer and scanner motor outputs can be programmed as GPOs for applications using a single motor or plain paper printers 4 MD219 FE100 200 M eXtended FAXENGINE Device Set T 4 T 6 Compressor Decompressor The FC100 200 implements MH MR image data compression and decompression per ITU T Recommendation T 4 in hardware The FC100 200 M also provides MMR compression and decompression per ITU T Recommendation T 6 in dedicated hardware Compression and decompression can be alternated on a line by line basis in the FC100 200 M with the support of FE100 200 M Firmware MD219 5 FE100 200 M eXtended FAXENGINE Device Set Operator Panel Keypad LEDs amp LCD Printer Data Control amp Sensors Printer amp Scanner Motor Drivers Scanner Controls amp Sensors Scanner Video Preprocessing Sync Ports 2 SSIF OPO 7 0 OPI 3 0 LEDCTL TRB 3 0 TRBPO HAD PCLK PLAT PM 3 0 M 3 0 TART K2 eXtended VIDCTL 1 0 Facsimile Controller VIN VREF VREF SCLK 2 1 STXD
12. DGND3 5 IRQ2 VDD3 YCLK XCLK XTLO XTLI RESET GPOO GPO1 GPO2 IRQ1 CTS DGND2 GPO4 GPO5 GPO6 GPO7 GPI7 RINGD GPI6 VDD2 GPI5 4 GPI2 READ CS NC MD162F4 Pin Sigs 100F MD162F4 Pin Sigs 28L Figure 5 28 Pin XIA Pin Signals 16 FE100 200 M eXtended FAXENGINE Device Set Software Description Supplied Firmware FAXENGINE firmware supplied with the FE100 200 consists of Core Code and Application Code The Application Code in conjunction with Core Code and FC100 200 when connected to scanner and printer peripherals provides a complete facsimile machine The Core Code subdivided as Macro and Primitive functions is supplied as object code whereas the Application Code to complete a fax machine is supplied as assembly level source code Core Code The Core Code includes proprietary primitives and macros in object code form located in ROM at the top of the FAXENGINE processor address space These Core Code primitives and macros provide the following functions e Modem control e T 30 framing and control T 4 MH MR MMR control for FC100 200 and FC100 200 M compression decompression hardware Supports Line times of 5 ms per line e Send and receive a page e Real time multitasking executive for scheduling high priority interrupt driven tasks and servicing low priority background tasks The Core Code subroutines are organized in a modular
13. Requirements Environmental specifications are shown in Table 3 Power requirements are shown in Table 4 FC100 200 Interface Signals The FC100 200 hardware signal pin assignments are shown in Figure 2 These signals are described in Table 5and Table 6 Facsimile Modem Interface Signals R96DFXL CID and R144EFXL pin assignments are shown in Figure 3 RFX96V24 S and RFX144V24 S hardware interface signals are shown in Figure 4 Pin assignments for the 28 pin XIA used with the RFX96V12 S and RFX144V12 S modems are shown in Figure 5 The FE100 200 M device set package dimensions are shown in Figure 6 though Figure 8 For additional information on these devices refer to the specific product s Data Sheet or Designer s Guide MD219 FE100 200 M eXtended FAXENGINE Device Set Table 2 Documentation Order No R96DFXL MONOFAX Modem Data Sheet MD92 R144EFXL MONOFAX Modem Data Sheet RFX144V24 S and RFX96V24 8 MONOFAX Modems Data Sheet 600 bps MONOFAX Modem Designer s Guide 820 9600 bps MONOFAX Modem Designer s Guide 820A Addendum for R96DFXL R144EFXL MONOFAX Modem Designer s Guide 895 RFX144V24 S and RFX96V24 S MONOFAX 1070 Modems Designer s Guide MC24 Megacell CPU Programmer s Guide 415 eXtended Facsimile Controller FC100 200 1171 Hardware Description eXtended FAXENGINE Firmware Description 1139 FAXENGINE Evaluation System FEES X2 User s 1066 Manual MC24 FAXENGINE ROM Emulator System 1016 M
14. and interface functions The MC24 embedded micro processor provides an 8 bit data bus a 24 bit address bus and a direct external memory accessing capability to 16 MB Additionally it contains scanner printer keyboard stepper motor and modem interfaces These programmable functions and interfaces support a wide range of peripherals Integrated 8 bit pipeline ADC clamp sample hold and AGC allow minimum external scanner interface hardware Built in DLC and shading correction combined with two dimensional Error Diffusion and two dimensional edge enhancement provides state of the art image processing performance in half tone modes The eXtended FAXENGINE Controller enables product design flexibility by virtue of its built in peripheral and programmable hardware registers MONOFAX Modems Seven MONOFAX modem models are available with selection depending upon the desired applications The R144EFXL and R96DFXL R96DFXL CID support V 17 14400 bps and V 29 9600 bps fax transmission and reception The RFX96V24 and RFX144V24 add integrated fax and digital answering machine functionality by providing a low bit rate voice codec that provides 24 minutes of voice storage per 4 megabits of memory The RFX144V24 S and RFX96V24 S modems support the full range of features listed above and add full duplex speakerphone features for hands free applications An External Integrated Analog XIA front end is added for microphone and speaker interfaces to supp
15. and pulse width Two video control output signals VIDCTL 1 0 provide digital control for external signal pre processing cir cuitry These signals provide a per pixel period or per line period timing with programmable positive going and negative going transitions for each signal Scanner Pipeline A D Interface An internal 8 bit pipeline A D converter PADC and ADC clock are provided The A D reference inputs Vref and Vref are available for control by external circuits A programmable ADC sample position is provided Built in Automatic Gain Control AGC amplifier and Input Analog IA clamping circuits are provided External video circuits can be tailored by the developer Video Processing The FC100 200 supports DLC and two modes of shading correction for scanner data non uniformity s arising from uneven sensor output or uneven illumination Correction may be provided to an 8 pixel group at a time or separately to each pixel Less than 1 K of RAM is required to support shading correction A Digital Adaptive Halftone image processing is supported A 2 Dimensional error diffusion algorithm as well as a 2 D Edge Enhancement control are performed in the hardware Dynamic background and contrast control is provided for text images Multi level horizontal B4 to A4 reduction is also provided for the scanner data The FC100 200 includes an optional external image data processing port multiplexed with GPIO to allow the developer
16. be used for PCB layout English values inches are converted from metric values and may include round off errors PD PQFP 100 040695 Figure 6 100 Pin PQFP Dimensions 18 MD219 FE100 200 M eXtended FAXENGINE Device Set JI Millimeters Min May 1 6 MAY 0 0630 MAK 0 05 0 15 0 0020 0 0059 1 4 REF 0 0551 REF 21 75 22 25 0 8563 0 8760 20 0 REF 0 7874 REF 17 5 REF 0 6890 REF 05 075 1 0 REF 0 0394 REF 0 50 BSC 0 0197 BSC 0 17 0 27 0 0067 0 0106 0 11 0 17 0 0043 0 0067 Coplanarity 0 08 MAX 0 0031 MAX Ref 144 PIN TQFP GP00 D252 Metric values millimeters should be used for PCB layout English values inches are converted from metric values and may include round off errors DETAIL A PD TQFP 144 040395 Figure 7 144 Pin TQFP Dimensions MD219 19 FE100 200 M eXtended FAXENGINE Device Set SEATING PLANE 02 im E BH 1 REF TOP VIEW SIDE VIEW CHAM A hx45 DEG cH KE 3 PLCS mi D3 Millimeters Min Max 4 19 4 72 Inches Min Max 0 165 0 180 0 508 REF 0 432 0 533 12 32 12 57 11 48 REF 0 020 REF 0 017 0 021 0 485 0 495 0 452 REF 7 62 REF 0 300 REF 10 41 10 92 0 410 0 430 1 27 BSC 0 254 0 050 BSC 0 010 TYP 1 15 TYP
17. for request SSREQ and acknowledge SSACK are supported in slave mode Transmit and receive data shift direction and clock polarity is programmable Internal interrupt can be generated when the receive data register is full Synchronous Asynchronous Serial Interface SASIF The SASIF is configurable either as Synchronous or Asynchronous Serial Interface This interface consists of three lines SASTXD SASRXD and clock SASCLK The SASIF includes a programmable baud rate generator and produces an 8X driving clock for internal logic Receive data is double buffered to ease received timing restrictions SASIF status can be read anytime by the CPU Status includes IRQ source TXD or RXD and operation mode synchronous or asynchronous The CPU can also control and monitor TXD and SCLK RXD can be monitored at any time Autobaud The autobaud circuit with supporting firmware is used to analyze a serial data stream in order to determine the baud rate and data structure parity and character length to program an external UART A precision timer shift register and edge detector are included to determine the width of the start bit and to sample the serial data stream Serial data rates up to 115 2 kbps are supported The serial transmitted data is connected to the precision timer and shift register inputs via the SERINP pin The SEROUT pin is a gated version of the SERINP pin that can be enabled disabled Real Time Clock RTC T
18. 0 045 TYP 45 TYP 45 f L FOR EACH AXIS hh mp pm EXCEPT FOR BEVELED EDGE CHAM e J x45 DEG BOTTOM VIEW SECTION A A Figure 8 28 Pin PLCC Dimensions Coplanarity 0 10 MAX Ref 28 PIN PLCC GP00 D169 0 004 MAX PD PLCC 28 040695 20 MD219 amp CON EX AN T What s next in communications technologies gt Further Information literature conexant com 1 800 854 8099 North America 33 14 906 3980 International Web Site www conexant com World Headquarters Conexant Systems Inc 4311 Jamboree Road P O Box C Newport Beach CA 92658 8902 Phone 949 483 4600 Fax 949 483 6375 U S Florida South America Phone 813 799 8406 Fax 813 799 8306 U S Los Angeles Phone 805 376 0559 Fax 805 376 8180 U S Mid Atlantic Phone 215 244 6784 Fax 215 244 9292 U S North Central Phone 630 773 3454 Fax 630 773 3907 U S Northeast Phone 978 692 7660 Fax 978 692 8185 U S Northwest Pacific West Phone 408 249 9696 Fax 408 249 7113 U S South Central Phone 972 773 0723 Fax 972 407 0639 U S Southeast Phone 770 246 8283 Fax 770 246 0018 U S Southwest Phone 949 222 9119 Fax 949 222 0620 APAC Headquarters Conexant Systems Singapore Pte Ltd 1 Kim Seng Promenade Great World City
19. D141 MC24FERE User s Manual MC24 Megacell CPU Programming Manual Table 3 Environmental Specifications Specification Temperature Operating 0 to 70 C 32 F to 158 F 40 C to 80 C 40 F to 176 F 90 non condensing or a wet bulb temperature to 35 C whichever is less Storage Relative Humidity Table 4 Power Requirements Maximum Current 0 C Note 3 Voltage Note 1 Typical Current 25 C Note 3 FC100 200 Primary Power 5 VDC 5 10 70 ma FE100 200 M Primary Power 72 5 VDC 5 10 FC100 200 M Battery Power and RTC Note 2 20 pA 5 5 pA 5 VDC 17 pA 43 VDC 5yA MONOFAX Modems R96DFXL R144EFXL RFX96V24 RFX96V24 S RFX144V24 FX144V24 S 5 VDC 5 124 2 15 ma Note 4 R 5 VDC 5 5 VDC 5 5 VDC 5 100 2 ma 5 VDC 5 124 2 15 ma Note 4 5 VDC 5 100 2 ma 55 ma 60 ma 119 2 5 ma 149 2 8 ma 119 2 5 ma 149 2 8 ma Notes 1 Input voltage ripple lt 0 1 volts peak to peak The amplitude of any frequency between 20 and 150 kHz must be less than 500 microvolts peak Real Time Clock RTC battery power measurements made with a 32 768 kHz crystal oscillator Normal Standby current Modem and XIA combined MD219 FE100 200 M eXtended FAXENGINE Device Set STRBPOL oPO7 GPO15 LL 38 6 14 L_ 39 oPpo5 GP013 LJ 40 OP04 GP012 ssTxD1 LL 42 oPo3 cPo11 LJ 43 OPO2 GPO10 RING
20. ER LJ 44 133 SYSCLK 132 vsso 1314 RESETn 130 TSTCLK 129 DEBUGn 124 1 REGDMA 123 120 L2 Romcsn 119 L1 118 Pw0 cPo0 117 L PM1 GPO 115 PM3 GPO3 114 E 135 L2 MIRQn 134 vssi 126 sync 125 LJ WAITn 122 1 121 L5 mcsn 113 LL 112 E cason 111 E casin OPI3 GPIO24 49 OP1I2 GP1023 SSCLKIL 50 OPI1 GPIO22 SSTATI 51 BATRSTn 61 PWRDWNn 1 CY 65 66 OPIO GPIO21 SSRXD1L 52 1 6 1017 54 LEDCTL GPIO16 55 0201 GP09 PMPWRCTRL 0200 GPO8 SMPWRCTRL Figure 2 FC100 200 Pin Signals 144 Pin TQFP 110 C wRPROThn VSSo GPIO20 ALTTONE SM0 GPO4 SM1 GPO5 SM2 GPO6 SM3 GPO7 VDDi START CLK1n CLK2 FCS2n VIDCTL1 FCS1n VIDCTLO vssi GPIOO GPIO1 SASTXD GPIO2 SASRXD GPIO3 SASCLK GPIO4 CPCIN GPIO5 SSCLK2 VSSo GPIO6 SSTXD2 GPIO7 SSRXD2 GPIO8 FWRn GPIO9 FRDn GPIO10 SSSTAT2 GPIO11 BE SERINP VDDo GPIO12 CS2n GPIO13 CS3n GPIO14 CS4n GPIO15 CS5n GPIO16 IRQ8 GPIO17 GPIO18 IRQ9n GPIO19 RDY SEROUT MD162R1F2 10 MD219 FE100 200 M eXtended FAXENGINE Device Set Table 5 FC100 200 Pin Assignments Type Type Note Active low signals have an pin name ending CPU Control Interface mran 15 HU Modem interrupt active low Hysteresis In Internal Pullup svscuk 14 H JSytemdock Hysteressin __ rstouk 149 o
21. FE100 200 M gt e CON EX AN T eXtended FAXENGINE Device Set The Conexant FE100 200 M eXtended FAXENGINE adds error diffusion Dark Level Correction DLC and Flash Memory Support to the suite of facsimile functions already supported by the XFE family It is packaged in a two device set consisting of a Conexant eXtended Facsimile Controller FC100 200 M and a Conexant MONOFAX Modem This family of eXtended FAXENGINE devices provides upgrade capabilities via its hardware and software compatible controllers the FE100 200 is backward compatible with other XFE device sets Starting with the basic FE100 fax controller which includes a DRAM controller and flash memory controller voice support V can be added along with T 6 MMR with Alternating Compression Decompression ACD M and full duplex digital speakerphone support S The eXtended FAXENGINE Device Set combinations are shown in Table 1 The eXtended FAXENGINE Device set including supplied firmware comprises a complete facsimile machine controller needing only a power supply scanner printer and paper path components to complete the machine The FAXENGINE Development System including the FAXENGINE Evaluation System FEES X2 and the MC24 ROM Emulator McFERE provides a complete development environment eXtended FAXENGINE Controller FC100 FC100 M FC200 FC200 M The eXtended FAXENGINE Controller performs all common facsimile machine control monitor
22. c lt 9 7 7 7 6 6 TA GPIO GPIO GPIO GPIO Hysteresis In 12 or I O chip select 2 13 I O chip select 3 14 or I O chip select 4 15 or I O chip select 5 Hysteresis In Hysteresis In Hysteresis In Hysteresis In GPIO 19 or ready signal or Serial port data output or autobaud detection Miscellaneous Programmable scan motor control pins or GPO pins Programmable print motor control pins or GPO pins Tone output signal Voltages Ground Negative Reference Voltage for Video A D or Reference Voltage for the Clamp Circuit A D Internal GND NOTE This pin requires an external 0 22uF decoupling capacitor to ADGA A D Analog Ground A D Analog Power A D Digital Ground Positive Reference Voltage for Video A D Analog Video A D input Analog Thermal A D input Power and Ground lt n 7 21 28 45 53 56 64 88 95 108 132 134 14 32 41 48 81 102 123 140 lt lt lt JE Digital Ground Digital Power Battery Power DRAM Battery Power MD219 FE100 200 M eXtended FAXENGINE Device Set Table 6 FC100 200 Hardware Signal Characteristics Input Signal Characteristics Input Description VIL VIH Hysteresis Pullup Type V max V min V min Resistance K ohm CMOS input osvob orvoo 35 150 Lu 1 08 20 TUPuup os 20 35180
23. erwise under any patent rights of Conexant other than for circuitry embodied in Conexant products Conexant reserves the right to change circuitry at any time without notice This document is subject to change without notice Conexant and What s Next in Communications Technologies are trademarks of Conexant Systems Inc Product names or services listed in this publication are for identification purposes only and may be trademarks or registered trademarks of their respective companies All other marks mentioned herein are the property of their respective holders 1999 Conexant Systems Inc All Rights Reserved MD219 FE100 200 M eXtended FAXENGINE Device Set Table 1 FE100 200 M Family Characteristics eXtended FAXENGINE Fax MONOFAX MH MR M Full Duplex Digital Caller ID Error External Device Set Controller Fax Modem MR ACD Speakerphone Answering Diffusion DMA No Support Machine Channel R96FE100 R96FE100 C R96FE100 V24 R96FE100 V24S R96FE100 M R96FE100 MC R96FE100 MV24 R96FE100 MV24S z z e jo Ziz 2 2 2 2 lt z z o Yes Yes z 2 z o 2 lt n 2 2 2 2 lt o lt lt 2 R144FE100 R144FE100 C R144FE100 V24 R144FE100 V24S R144FE100 M R144FE100 MC 2 2 2 2 2 2 lt o z z o z o 2 olo 2 2 2 2 z z 6 6 5 5 6 5 6 5 5 5 6 5 615 lt
24. four for the printer motor Motor outputs can be programmed as General Purpose Outputs for application with a single motor or plain paper machines e Scanner and Video Control CCD and CIS scanners supported programmable control signals Four programmable scanner control signals Two video output control signals support external signal pre processing B4 A4 scanner support bmsminimum line time Line lengths to 2048 pixels Scanner pipeline A D Interface internal 8 bit pipeline A D converter clamp sample and hold and automatic gain circuits are provided internally A D reference inputs available for control by external circuits Video Processing single pixel and per eight pixel shading correction Dark Level Correction for 27 segments 2 imensional Error Diffusion Image processing FE200 and FE200 M only 2dimensional Edge enhancement Upto 8x8 programmable dither table Image data processing port allows access to scan data prior to video processing Multi level B4 to A4 size reduction e Programmable Resolution Conversion M only Programmable 2 dimensional bi level resolution conversion provides expansion to 20096 and reduction to 3396 Vertical line ORing Scanner output bit order reversal Thermal Printer Interface 1104 programmable strobe signals Traditional printers and latchless split mode printers Line lengths to 4096
25. he FC100 200 includes a battery backup real time clock The RTC life is 32 years its functions include leap year compensation A 32 768 kHz watch crystal is required by the RTC General Purpose Inputs Outputs The FC100 200 provides 20 GPIO and 8 GPO lines Programmable Tone Generator Two programmable tone generators each provide single tone digital output variable in frequency from 20 to 4000 Hz System Timing The FC100 200 derives its timing from the modem clock or from an external oscillator max frequency 20 MHz Two internal timer interrupts are provided e 1 timer derived from the RTC oscillator timebase exact period 1 00708 ms e Aprogrammable mechanical subsystem interrupt MSINT which serves as a source for motor stepping interrupts and or scanner and printer interrupts Independent programmable scan and print line times are supported Reset and Power Control The BATRSTn input initializes the FC100 200 at power on An externally generated power down input PWRDWNn controls switching between primary and battery power The open drain RESETn I O pin provides a reset output to external circuits or can accept an externally generated reset The external reset will not reset the RTC Separate DRAM and RTC battery power inputs are provided for battery backup functions Documentation Documentation for the FE100 200 family of devices and MONOFAX modems are listed in Table 2 Environmental and Power
26. ler The FC100 200 M includes a flash memory controller that supports the following types of flash memory and their equivalents Vendor Model Size K 29 040 28 400 TC58A040F Serial NAND KM29N040 080 150 NAND Thermal Printer Control The thermal printer interface consists of programmable data latch clock and up to four strobe signals Programmable timing supports traditional thermal printers as well as latchless and two clock split mode printers and line lengths to 4096 pixels From one to four strobes are generated with the length of the strobe cycle line time and strobe pulse width programmable Line times from 5 to 40 ms are supported A strap input to the FC 100 200 sets strobe polarity Three signals PDAT PCLK and PLAT control the transfer of data to the printer The FC100 200 includes a 6 bit A D converter conversion rate 80 ms full scale to monitor the head temperature of the thermal printer Two external terminating resistors are determined by the specific printhead selected Scanner and Video Control Six programmable control and timing signals support common CCD and CIS scanners The video control function provides signals for controlling the scanner and for processing its video output Four programmable control signals START CLK1 CLK1n and CLK2 provide timing related to line and pixel timing These are programmable with regard to start time relative delay
27. ort full duplex digital speakerphone operation S Distinguishing Features Microprocessor and Bus Interface Enhanced MC24 central processing unit CPU up to 10 MHz CPU clock speed Memory efficient input output bit manipulation 8 bit data 24 bit address bus External Bus Address data control status interrupt and decoded chip select signals support connection to external ROM external RAM and optional peripheral devices Chip selects ROMCSn for ROM support CSOn for SRAM CS1n for external peripherals MCSn for modem Optional general purpose CS2n CS3n CS4n and CS5n DRAM Controller Supports external page memory Battery backup refresh with separate battery power DMA Controller Six dedicated internal DMA channels for scanner printer and T 4 T 6 access of internal and or external memory Internal Video RAM 2K X 8 internal Video RAM is supported for 2 dimensional Error Diffusion image processing External RAM 11 MB External ROM 3 MB Interrupt controller Flash memory controller supports 2 MB NOR type flash memories Samsung NAND type flash memory and Toshiba NAND type flash memory with internal synchronous serial port T 4 T 6 Compression and Decompression in Hardware MH MR for FC100 200 MH MR MMR for FC100 200 M Data Sheet Order No MD219 April 23 1998 FE100 200 M eXtended FAXENGINE Device Set e Motor Control for Scanner and Printer Four outputs to external current drivers for the scanner motor and
28. pixels AID converter monitors printer head temperature e Programmable Tone Generator e Operator Interface The interface can directly drive a 32 key keypad 8x15 keyboard array is supportable with external circuitry Eight LEDs are driven directly Typical LCD display modules are supported Autobaud Interface Automatically detects baud rate of asynchronous serial data for external UART or built in SASIF support Synchronous Serial Interface SSIF 2 Synchronous Interface Master Slave configuration Clock Programmable clock rate Synchronous Asynchronous Serial Interface SASIF 1 Synchronous Asynchronous interface Programmable baud rate up to 14400 bps General Purpose Inputs and or Outputs Provides up to 20 GPIO and 8 GPO s Real Time Clock Battery backup 32 year range with leap year compensation Watchdog Timer Compact Packages FC100 200 144 pin TQFP MONOFAX Modem 100 pin PQFP XIA 28 pin PLCC FAXENGINE Development System FEES X2 and MC24 FERE Provides demonstration prototype development and evaluation capabilities to facsimile machine developers using the eXtended FAXENGINE Device Set Connects to a host PC for software development Information provided by Conexant Systems Inc is believed to be accurate and reliable However no responsibility is assumed by Conexant for its use nor any infringement of patents or other rights of third parties which may result from its use No license is granted by implication or oth
29. s of VDD power NOTE The functional logic is powered by battery power but the output drive is powered by DRAM battery power Scanner Interface Scanner shift gate control Scanner clock Scanner clock inverted 2 Flash memory chip select or Video Control signal XS XS XS XS Scanner reset gate control or clock for CIS scanner 2XT Flash memory chip select or Video Control signal MD219 11 FE100 200 M eXtended FAXENGINE Device Set Table 5 FC100 200 Pin Assignments Cont d L IPCLK DMAACK 29 o Head TPH clock or external DMAACK O xP SerialprintingdatatoTPH EA part 1 O axe aa ISTRE30 ssa 1XP Strobe signals for the 37 Sets strobe polarity active high low OPI 0 GPIO 21 SSRXD1 52 OPI 1 22 51 SSSTAT1 Scanner Interface 2XL LED strobe 5 or GPO 13 2XL LED strobe 6 or GPO 14 2XL LED strobe 7 or GPO 15 2XC Pullup Hysteresis In Keyboard return 0 or GPIO 21 or SSRXD1 for SSIF1 2XC Pullup Hysteresis In Keyboard return 1 or GPIO 22 or SSSTAT1 for SSIF1 2XC Pullup Hysteresis In Keyboard return 2 or GPIO 23 or HU HU HU 1 0 SSCLK1 SSCLK1 for SSIF1 Pullup Hysteresis In Keyboard return 3 or GPIO 24
30. ssion decompression and for facsimile machine control and monitoring Microprocessor The microprocessor is an enhanced MC24 central processing unit CPU This CPU provides fast instruction execution and memory efficient input output bit manipulation The CPU connects to other internal FC100 200 functions over internal address data and dedicated control buses These buses are routed outside the FC100 200 for external memory access External Bus Control Address data control status interrupt and decoded chip select signals support connection to external ROM external RAM and optional DRAM and peripheral devices Dedicated internal DMA logic is in cluded for scanner printer and T 4 access of internal and or external RAM Six internal DMA channels support scanner printer and T 4 access of the external shading and line buffer RAM A programmable DMA channel is available to support T 4 T 6 access to external page memory External RAM and ROM FC100 200 can use 3 MB of ROM and up to 1 MB of SRAM ROM stores all the FAXENGINE program ob ject code and SRAM is used by the FAXENGINE CPU shading RAM and line buffer RAM Independently programmable SRAM and ROM wait states from 0 to 3 are supported SRAM sizes may be 8 32 64K and 1 MB Chip Selects Various chip selects CS are provided by the FC100 200 such as ROMCSn CSOn for SRAM CS1n for external peripherals MCSn for modem and optional general purpose chip selects CS
31. t code form ready for linking to developer provided application program object code The Core Code is highly structured for maximum application flexibility with minimum overhead Application Code The Application Code builds an example fax machine using the FE100 200 M device set in the FEES X2 environment The Application Code is provided in source code form and serves as basis for the developer s application FE100 200 eXtended FAXENGINE Development System The Conexant FAXENGINE Evaluation System FEES X2 and MC24 FERE Fax Engine ROM Emulator provides demonstration prototype development and evaluation capabilities to facsimile machine developers using the FE100 200 eXtended FAXENGINE Device Set The FEES X2 offers flexibility for visibility and access It consists with the Modem Evaluation Board Data Access Arrangement DAA sockets for programmable parts and connectors for an emulator and all fax machine peripherals The ROM Emulator MC24 FERE is a PC based firmware development debugging environment with breakpoint and trace capability for developers Hardware Description The FE100 200 system level functional interface is shown in Figure 1 Note The suffix n indicates an active low signal eXtended Facsimile Controller FC100 200 The FC100 200 contains an internal 8 bit microprocessor with a 16MB external address space and dedicated circuitry optimized for facsimile image processing image data compre
32. to access scan data prior to video processing Operator Interface Operator interface functions are supported by the operator output bus OPO 7 0 the operator input bus OPI 3 0 and two control outputs LEDCTL and LCDCS The FC100 200 can directly drive a 32 key keypad External blocking diodes are required to isolate the keyboard strobe lines from the LEDs as the LEDs and keyboard strobe signals use the same lines Up to 8x15 keyboard array can be supportable with external circuitry Eight LEDs can be driven directly by the FC100 200 The keyboard strobes are shared with the LED drivers An LED control signal is provided to disable the LEDs during keyboard strobing The FC100 200 offsets LED turn on off times thereby preventing power supply overload when all indicators are activated simultaneously The LEDCTL signal can supply 12 ma Typical LCD display modules are driven by the FC100 200 The FC100 200 drives the 4 bit bus OPO 3 0 and two separate control lines OPO4 and LCDCS for LCD support For example the FAXENGINE Development System FEES X2 uses a 2 line 20 character per line display MD219 FE100 200 M eXtended FAXENGINE Device Set Synchronous Serial Interface SSIF FE100 200 provides two Synchronous Serial Interfaces The SSIF is configured to operate either as a Master or Slave interface bi directional Clock The interface consists of three lines SSTXD SSRXD and SSCLK Optional control signals
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