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CPU32 Reference Manual [330 pages!]

1. Instruction Head Tail Cycles ADD A Rn Rm 0 0 2 0 1 0 ADD A FEA Rn 0 0 2 0 1 0 ADD Dn FEA 0 3 5 0 1 x AND Dn Dm 0 0 2 0 1 0 AND FEA Dn 0 0 2 0 1 0 AND Dn FEA 0 3 5 0 1 x EOR Dn Dm 0 0 2 0 1 0 EOR Dn FEA 0 3 5 0 1 x OR Dn Dm 0 0 2 0 1 0 OR FEA Dn 0 0 2 0 1 0 OR Dn FEA 0 3 5 0 1 x SUB A Rn Rm 0 0 2 0 1 0 SUB A FEA Rn 0 0 2 0 1 0 SUB Dn FEA 0 3 5 0 1 x CMP A Rn Rm 0 0 2 0 1 0 CMP A FEA Rn 0 0 2 0 1 0 CMP2 Save FEA Rn 1 1 3 0 1 0 CMP2 Op FEA Rn 2 0 16 18 X 1 0 MUL S U W FEA Dn 0 0 26 0 1 0 MUL S U L Save FEA Dn 1 1 3 0 1 0 MUL S U L Op FEA DI 2 0 46 52 0 1 0 MUL S U L Op FEA Dn DI 2 0 46 0 1 0 DIVU W FEA Dn 0 0 32 0 1 0 DIVS W FEA Dn 0 0 42 0 1 0 DIVU L Save FEA Dn 1 1 3 0 1 0 DIVU L Op FEA Dn 2 0 lt 46 0 1 0 DIVS L Save FEA Dn 1 1 3 0 1 0 DIVS L Op FEA Dn 2 0 lt 62 0 1 0 TBL S U Dn Dm Dp 26 0 28 30 0 2 0 TBL S U Save CEA Dn 1 1 3 0 1 0 TBL S U Op CEA Dn 6 0 33 35 2X 1 0 TBLSN Dn Dm Dp 30 0 30 34 0 2 0 TBLSN Save CEA Dn 1 1 3 0 1 0 TBLSN Op CEA Dn 6 0 35 39 2X 1 0 TBLUN Dn Dm Dp 30 0 34 40 0 2 0 TBLUN Save CEA Dn 1 1 3 0 1 0 TBLUN Op CEA Dn 6 0 39 45 2X 1 0 X There is one bus cycle for byte and word operands and two bus cycles for long operands Fo
2. 7 24 7 2 8 15 No Operation a ahaa ea en aa ce 7 24 7 2 8 16 Future Commands cuoi ctae orate EH o Rb dE ecce 7 25 7 3 Deterministic Opcode Tracking atr ER rh Peers 7 25 7 3 1 Instruction Fetch IFE TCH we a pa ctn rper rnm ep nee 7 25 7 3 2 Instruction Pipe IPIPE sa iode tita e teta b 7 25 7 3 3 Opcode Tracking during Loop Mode 7 27 SECTION 8 INSTRUCTION EXECUTION TIMING 8 1 Resource Scheduling sseessssssssssssseeeeeeneneenen nnn 8 1 8 1 1 Microsequencer get rc 8 1 8 1 2 Instr ctiori PIDBII emer una e oA SR er Rie 8 2 8 1 3 Bus Controller RESOUICES 8 2 8 1 3 1 Prefetch Controller 8 3 8 1 3 2 Write Pending Buller Aka Gaal ee A aa As 8 3 8 1 3 3 Microbus Controller e i etc tta endis 8 3 8 1 4 Instruction Execution Overlap 53 9 9 21d ete BERI ae 8 4 8 1 5 Effects of Wait States po Lr 8 5 8 1 6 Instruction Execution Time Calculation 8 5 8 1 7 Effects of Negative Tails 8 6 8 2 Instruction Stream Timing Examples 8 7 8 2 1 Timing Example 1 Execution Overlap 8 7 8 2 2 Timing Example 2 Branch Inst
3. FC2 FC1 FCO Address Space 0 0 0 Undefined Reserved 0 0 1 User Data Space 0 1 0 User Program Space 0 1 1 Undefined Reserved 1 0 0 Undefined Reserved 1 0 1 Supervisor Data Space 1 1 0 Supervisor Program Space 1 1 1 CPU Space Address space 3 is reserved for user definition 0 and 4 are reserved for future use by Motorola Although an appropriate address space is selected memory locations of user program and data and of supervisor data within that address space are not predefined Dur ing reset two long words beginning at memory location zero in the supervisor program space are used for processor initialization No other memory locations are explicitly defined by the CPUS2 5 3 1 CPU Space Access Function code 7 FC2 FCO 111 selects CPU address space The processor com municates with external devices for special purposes by accessing this space All M68000 processors use CPU space for interrupt acknowledge cycles The CPU32 also uses CPU space for breakpoint acknowledge and the LPSTOP broadcast Supervisor programs can use the MOVES instruction to access all address spaces including user spaces and CPU address space Although the MOVES instruction can be used to generate CPU space cycles doing so may interfere with proper system op eration Exercise caution when using MOVES to access CPU space CPU32 PROCESSING STATES MOTOROLA REFERENCE MANUAL 5 3 Address bus encoding facilitate
4. The BERR stack frame is 12 words in length There are three variations of the frame each distinguished by different values in the SSW TP and MV fields An internal transfer count register appears at location SP 14 in all bus error stack frames The register contains an 8 bit microcode revision number and for type III faults an 8 bit transfer count Register format is shown in Figure 6 5 15 8 7 0 MICROCODE REVISION NUMBER TRANSFER COUNT Figure 6 5 Internal Transfer Count Register The microcode revision number is checked before a BERR stack frame is restored via RTE In a multiprocessor system this check insures that a processor using stacked information is at the same revision level as the processor that created it The transfer count is ignored unless the MV bit in the stacked SSW is set If the MV bit is set the least significant byte of the internal register is reloaded into the MOVEM transfer counter during RTE execution For faults occurring during normal instruction execution both prefetches and non MOVEM operand accesses SSW TP MV 00 Stack frame format is shown in Fig ure 6 6 Faults that occur during the operand portion of the MOVEM instruction are identified by SSW TP MV 01 Stack frame format is shown in Figure 6 7 When a bus error occurs during exception processing SSW TP MV 10 The frame shown in Figure 6 8 is written below the faulting frame Stacking begins at the a
5. 4 13 4 5 Instruction Format Summary uso eee ho DE Da E ERES A rM 4 170 4 6 Table Lookup and Interpolation Instructions 4 188 4 6 1 Table Example 1 Standard Usage 4 188 4 6 2 Table Example 2 Compressed 4 189 MOTOROLA CPU32 vi REFERENCE MANUAL TABLE OF CONTENTS Continued Paragraph Title Page 4 6 3 Table Example 3 8 Bit Independent Variable 4 191 4 6 4 Table Example 4 Maintaining Precision 4 192 4 6 5 Table Example 5 Surface Interpolations 4 194 4 7 Nested Subroutine Calls 0 4 194 4 8 Pipeline Synchronization with the NOP Instruction 4 194 SECTION 5PROCESSING STATES 5 1 State ae een ee 5 1 5 2 Privilege des ct pected olives diae D DE Mte En 5 1 5 2 1 Supervisor Privilege Level 2 4 00 5 2 5 2 2 User Privilege Level i ire tre oet bed 5 2 5 2 3 Changing Privilege Level odere a ana b 5 2 5 3 Types of Address Space uuu onde ia coca esc ee tror qp 5 3 5 3 1 CPU Space ACCESS 3o nde a eT ERU 5 3 5 3 1 1 Type 0000 Breakpoint 2 5 4 5 3 1 2 Type 0001 MMU
6. 3 4 3 4 2 3 Address Register Indirect With Predecrement 3 4 3 4 2 4 Address Register Indirect With Displacement 3 5 3 4 2 5 Address Register Indirect With Index 8 Bit Displacement 3 5 3 4 2 6 Address Register Indirect With Index Base Displacement 3 6 CPU32 MOTOROLA REFERENCE MANUAL TABLE OF CONTENTS Continued Paragraph Title Page 3 4 3 Special Addressing IMOUOS oie io oreet 3 7 3 4 3 1 Program Counter Indirect With Displacement 3 7 3 4 3 2 Program Counter Indirect with Index 8 Bit Displacement 3 7 3 4 3 3 Program Counter Indirect with Index Base Displacement 3 8 3 4 3 4 Absolute Short Address sssssee 3 8 3 4 3 5 Absol t Long 309666 ro etm o terreno cec 3 9 3 4 3 6 immediate Data 3 9 3 4 4 Effective Address Encoding Summary 3 9 3 5 Programming View of Addressing Modes 3 11 3 5 1 Addressing Capabilities 00 3 11 3 5 2 General Addressing Mode Summary 3 14 3 6 M68000 Family Addressing Capability 3 14 3 7 Other Data 9It ctliles t tue be eR en 3 15 3 7 1
7. 3 15 3 7 2 PLE 3 16 3 7 3 QUEUES sc ies v va pn dM arc und 3 17 SECTION 4 INSTRUCTION SET 4 1 M68000 Family Compatibility cade ciae te i eo eei eroe eo uate iecit 4 1 4 1 1 ehe d qe cte m terse newest 4 1 4 1 1 1 Low Power Stop LP STOP iie ed eet e E EIER 4 1 4 1 1 2 Table Lookup and Interpolation TBL 4 2 4 1 2 Unimplemented Instructions 444 42440 1 4 2 4 2 Instruction Format e bes 4 2 4 2 1 bo ER CT 4 3 4 3 Instr ction SUIMMANY tetera etiaai edle eme pn eoa ned 4 5 4 3 1 Condition Code Register 1 x cre eere epe RR CER Ec ace 4 5 4 3 2 Data Movement Instructions esses 4 6 4 3 3 Integer Arithmetic Operations 4444422042 4 7 4 3 4 LOGIC InstrellofiS 25 2 emp re qu Dee pda e trm co uad 4 8 4 3 5 Shift and Rotate Instructions 5 5 2 tto a 4 9 4 3 6 Bit Manipulation Instructions 4 9 4 3 7 Binary Coded Decimal BCD Instructions 4 10 4 3 8 Program Control Instructions ssseeeeeeene 4 10 4 3 9 System Control Instructions 2 4 11 4 3 10 Condition TOSS ees ds eter 4 12 4 4 Instr ctioni DetallS zc ters aet
8. 8 4 MOTOROLA REFERENCE MANUAL xi LIST OF ILLUSTRATIONS Continued Figure Title Page 8 3 Attributed Instruction Times ioo ea e e eds t od 8 4 8 4 Example 1 Instruction Stream 8 7 8 5 Example 2 Branch Taken 8 8 8 6 Example 2 Branch Not 44122 1111 8 8 8 7 Example 3 Branch Negative Tail 2 8 0000 8 9 MOTOROLA CPU32 i REFERENCE MANUAL XII LIST OF TABLES Table Title Page 1 4 Instruction Set SUImtalby to PL ees ie co e ap NE 1 5 3 1 Effective Addressing Mode 3 11 4 1 Condition Code 4 5 4 2 Data Movement 14024444404 nennen nnne 4 6 4 3 Integer Arithmetic nennen nnn 4 7 4 4 LOGIC Operations nea pi Er eb ce PO ele Me 4 8 4 5 Shift and Rotate 4 9 4 6 Bit Manipulation ODOralloris uei eet n ameta erae ti etaed 4 10 4 7 Binary Coded Decimal Operations 4 10 4 8 Program Control 4 10 4 9 Sys
9. 6 10 6 2 10 cm 6 11 6 2 11 juste ke t ER 6 12 6 2 12 Return from Exception 6 13 CPU32 MOTOROLA REFERENCE MANUAL vii TABLE OF CONTENTS Continued Paragraph Title Page 6 3 Paull Recovery a cu deed 6 14 6 3 1 Types or PSUIS ciu ve bcc dc pU eaters 6 16 6 3 1 1 Type 1 Released Write Faults 6 16 6 3 1 2 Type Prefetch Operand RMW and MOVEP Faults 6 17 6 3 1 3 Type 111 Faults During MOVEM Operand Transfer 6 17 6 3 1 4 Type IV Faults During Exception Processing 6 18 6 3 2 Correcting a ESbllo eem ous ete 6 18 6 3 2 1 Type 1 Completing Released Writes via Software 6 19 6 3 2 2 Type 1 Completing Released Writes via RTE 6 19 6 3 2 3 11 Correcting Faults via 6 19 6 3 2 4 Type III Correcting Faults via Software 6 20 6 3 2 5 III Correcting Faults By Conversion and Restart 6 20 6 3 2 6 Type Ill Correcting Faults via RTE 6 21 6 3 2 7 Type IV Correcting Faults via Software 6 21 6 4 CPU32 Stack Frames oe ed adn 6 21 6 4 1 Normal Four Word Stack Frame
10. CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4 193 4 6 5 Table Example 5 Surface Interpolations The various forms of table can be used to perform surface 3D TLIs However since the calculation must be split into a series of 2D TLIs the possibility of losing precision in the intermediate results is possible The following code sequence incorporating both TBLS and TBLSN eliminates this possibility LO MOVE W Dx DI Copy entry number and fraction number TBLSN B Dx TBLSN B 01 TBLS W Dx DI Dm Surface interpolation with round ASR L 8 Dm Read just the result BCC B L1 No round necessary ADDQ B 1 DI Half round up 22 Before execution of this code sequence Dx must contain fraction and entry numbers for the two TLI and Dm must contain the fraction for surface interpolation The ea fields in the TBLSN instructions point to consecutive columns in a 3D table The TBLS size parameter must be word if the TBLSN size parameter is byte and must be long word if TBLSN is word Increased size is necessary because a larger number of sig nificant digits is needed to accommodate the scaled fractional results of the 2D TLI 4 7 Nested Subroutine Calls The LINK instruction pushes an address onto the stack saves the stack address at which the address is stored and reserves an area of the stack for use Using this in struction in a series of subroutine calls will generate a linked list of stack frames T
11. sess 6 22 6 4 2 Normal Six Word Stack 6 22 6 4 3 BERR Stack eiie e ope ho fe n di 6 22 SECTION 7 DEVELOPMENT SUPPORT 7 1 CPU32 Integrated Development Support 7 1 7 1 1 Background Debug Mode Overview 7 1 7 1 2 Deterministic Opcode Tracking Overview 7 2 7 1 3 On Chip Hardware Breakpoint Overview 7 3 7 2 Background Debug Mode 7 3 7 2 1 Enabling oe esee ts 7 4 7 2 2 BOOMS OUICES DR a S ve queer Om ee UE 7 4 7 2 2 1 External BKPT Signal eterne nt poe emendo pene iens 7 4 7 2 2 2 cL eS t 7 4 7 2 2 3 et nacen iude 7 5 7 2 2 4 Peripheral Breakpoints ai 7 5 7 2 3 Entering BDM ss te e pete cM ee 7 5 7 2 4 Command Execution ordeo tib ead 7 5 7 2 5 Background Mode Registers 088 7 6 7 2 5 1 Fault Address Register 7 6 7 2 5 2 Return Program Counter 7 6 7 2 5 8 Current Instruction Program Counter PCC 7 7 7 2 6
12. gt Dx Where ENTRY n and ENTRY 1 are either 1 Consecutive entries in the table pointed to by the ea and indexed by Dx 15 8 size or 2 The registers Dym Dyn respectively Assembler Syntax TBLU sizeXea Dx Result rounded TBLUN lt size ea Dx Result not rounded TBLU size Dym Dyn Dx Result rounded TBLUN size Dym Dyn Dx Result not rounded Attributes Size Byte Word Long Description The signed table lookup and interpolate instruction TBLU allows the efficient use of compressed linear data tables to model complex functions The TBLU instruction has two modes of operation table lookup and interpolate mode and data register interpolate mode For table lookup and interpolate mode data register Dx 15 0 contains the indepen dent variable X The effective address points to the start of a signed byte word or long word table containing a linear representation of the dependent variable Y as a function of X In general the independent variable located in the low order word of Dx consists of an 8 bit integer part and an 8 bit fractional part An assumed radix point is located between bits 7 and 8 The integer part Dx 15 8 is scaled by the operand size and is used as an offset into the table The selected entry in the table is subtracted from the next consecutive entry A fractional portion of this difference is taken by mul tiplying by the interpolation fraction Dx 7 0 The adjusted difference is th
13. ASL XC lt lt 0 For ASR the operand is shifted right the number of positions shifted is the shift count Bits shifted out of the low order bit go to both the carry and the extend bits the sign bit MSB is shifted into the high order bit ASR gt gt gt XC MPH MOTOROLA INSTRUCTION SET CPU32 4 32 REFERENCE MANUAL ASL ASR Arithmetic Shift ASL ASR Condition Codes x N 7 V gt lt Set according to the last bit shifted out of the operand Unaffected for a shift count of zero Set if the most significant bit of the result is set Cleared otherwise Set if the result is zero Cleared otherwise Set if the most significant bit is changed during the shift operation Cleared otherwise Set according to the last bit shifted out of the operand Cleared for a shift count of zero Instruction Format Register Shifts lt NZ 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 0 COUNT REGISTER dr SIZE ilr 0 0 REGISTER Instruction Fields Register Shifts Count Register field Specifies shift count or register that contains shift count If i r 2 O this field contains the shift count The values one to seven represent counts of one to seven value of zero represents a count of eight If i r 2 1 this field specifies the data register that contains the shift count mod ulo 64 dr field Specifies the direction of the shift 0 Shift right 1
14. Destination Assembler Syntax MOVEA lt ea An Attributes Size Word Long Description Moves the contents of the source to the destination address register The size of the operation is specified as word or long Word size source operands are sign extended to 32 bit quantities Condition Codes Not affected Instruction Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EFFECTIVE ADDRESS 0 0 SIZE DST REG 0 0 1 MODE REGISTER Instruction Fields Size field Specifies the size of the operand to be moved 11 Word operation The source operand is sign extended to a long operand and all 32 bits are loaded into the address register 10 Long operation Destination Register Dst Reg field Specifies the destination address register Effective Address field Specifies the location of the source operand All addressing modes are allowed as shown Addressing Mode Mode Register Addressing Mode Mode Register Dn 000 Reg number Dn xxx W 111 000 An 001 Reg number An xxx L 111 001 An 010 Reg number An data 111 100 An 011 Reg number An An 100 Reg number An 416 101 Reg number dig PC 111 010 dg An Xn 110 Reg number An dg PC Xn 111 011 bd An Xn 110 Reg number An bd PC Xn 111 011 CPUS2 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4 91 MOVE Move from the MOVE from CCR
15. Dx 7 0 256 Dx Unrounded ENTRY n 256 ENTRY 1 7 ENTRY ny Dx 7 0 Dx Where ENTRY n and ENTRY 1 are either 1 Consecutive entries in the table pointed to by the ea and indexed by Dx 15 8 size or 2 The registers Dym Dyn respectively Assembler Syntax TBLS sizeXea Dx Result rounded TBLSN sizeX ea Dx Result not rounded TBLS size Dym Dyn Dx Result rounded TBLSN size Dym Dyn Dx Result not rounded Attributes Size Byte Word Long Description The signed table lookup and interpolate instruction TBLS allows the efficient use of compressed linear data tables to model complex functions The TBLS instruction has two modes of operation table lookup and interpolate mode and data register interpolate mode For table lookup and interpolate mode data register Dx 15 0 contains the indepen dent variable X The effective address points to the start of a signed byte word or long word table containing a linear representation of the dependent variable Y as a function of X In general the independent variable located in the low order word of Dx consists of an 8 bit integer part and an 8 bit fractional part An assumed radix point is located between bits 7 and 8 The integer part Dx 15 8 is scaled by the operand size and is used as an offset into the table The selected entry in the table is subtracted from the next consecutive entry A fractional portion of this difference is taken
16. Fully Upward Object Code Compatible with M68000 Family e Virtual Memory Implementation Loop Mode of Instruction Execution e Fast Multiply Divide and Shift Instructions Fast Bus Interface with Dynamic Bus Port Sizing Improved Exception Handling for Controller Applications Enhanced Addressing Modes Scaled Index Address Register Indirect with Base Displacement and Expanded PC Relative Modes 32 Bit Branch Displacements Instruction Set Enhancements CPU32 OVERVIEW MOTOROLA REFERENCE MANUAL 1 1 High Precision Multiply and Divide Trap On Condition Codes Upper and Lower Bounds Checking Enhanced Breakpoint Instruction Trace on Change of Flow Table Lookup and Interpolate Instruction Low Power Stop Instruction Hardware Breakpoint Signal Background Mode 16 77 MHz Operating Frequency 40 to 125 C Fully Static Implementation 1 1 1 Virtual Memory A system that supports virtual memory has a limited amount of high speed physical memory that can be accessed directly by the processor and maintains an image of a much larger virtual memory on a secondary storage device When the processor at tempts to access a location in the virtual memory map that is not resident in physical memory a page fault occurs The access to that location is temporarily suspended while the necessary data is fetched from secondary storage and placed in physical memory The suspended access is then restarted or continued
17. Instruction Field dr field Specifies the direction of the transfer 0 Register to memory 1 Memory to register Size field Specifies the size of the registers being transferred 0 Word transfer 1 Long transfer Effective Address field Specifies the memory address for the operation For regis ter to memory transfers only control alterable addressing modes or the pre decrement addressing mode are allowed as shown Addressing Mode Mode Register Addressing Mode Mode Register Dn xxx W 111 000 An xxx L 111 001 An 010 Reg number An data An An 100 Reg number An 416 101 Reg number An dig PC dg An Xn 110 Reg number An dg PC Xn bd An Xn 110 Reg number An bd PC Xn MOTOROLA INSTRUCTION SET CPU32 4 100 REFERENCE MANUAL MOVEM Move Multiple Registers MOVEM For memory to register transfers only control addressing modes or the postincre ment addressing mode are allowed as shown Addressing Mode Mode Register Addressing Mode Mode Register Dn xxx W 111 000 An xxx L 111 001 An 010 Reg number An data An 011 Reg number An An dis An 101 Reg number An dig PC 111 010 dg An Xn 110 Reg number An dg PC Xn 111 011 bd An Xn 110 Reg number
18. MOTOROLA OVERVIEW CPU32 1 4 REFERENCE MANUAL to store a sample of the full range and recover intermediate values quickly via linear interpolation A round to nearest algorithm can be applied to the results Table 1 1 Instruction Set Summary Mnemonic Description Mnemonic Description ABCD Add Decimal with Extend MOVE Move ADD Add MOVE CCR Move Condition Code Register ADDA Add Address MOVE SR Move Status Register ADDI Add Immediate MOVE USP Move User Stack Pointer ADDQ Add Quick MOVEA Move Address ADDX Add with Extend MOVEC Move Control Register AND Logical AND MOVEM Move Multiple Registers ANDI Logical AND Immediate MOVEP Move Peripheral ASL ASR Arithmetic Shift Left and Right MOVEQ Move Quick Bcc Branch Conditionally MOVES Move Alternate Address Space BCHG Test Bit and Change MULS MULS L Signed Multiply BCLR Test Bit and Clear MULU MULU L Unsigned Multiply BGND Background NBCD Negate Decimal with Extend BKPT Breakpoint NEG Negate BRA Branch NEGX Negate with Extend BSET Test Bit and Set NOP No Operation BSR Branch to Subroutine OR Logical Inclusive OR BTST Test Bit ORI Logical Inclusive OR Immediate CHK CHK2 Check Register Against Upper PEA Push Effective Address and Lower Bounds RESET Reset External Devices CLR Clear ROL ROR Rotate Left and Right CMP Compare ROXL ROXR Rotate with Extend Left and CMPA Compare Address Right CMPI Compare Immediate RTD Return and Deallocate
19. Shift left Size field Specifies the size of the operation 00 Byte operation 01 Word operation 10 Long operation i r field If i r O specifies immediate shift count If i r 1 specifies register shift count Register field Specifies a data register to be shifted CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4 33 ASL ASR Arithmetic Shift ASL ASR Instruction Format Memory Shifts 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EFFECTIVE ADDRESS MODE REGISTER Instruction Fields Memory Shifts dr field Specifies the direction of the shift 0 Shift right 1 Shift left Effective Address field Specifies the operand to be shifted Only memory alterable addressing modes are allowed as shown Addressing Mode Mode Register Addressing Mode Mode Register Dn xxx W 111 000 An xxx L 111 001 An 010 Reg number An data An 011 Reg number An An 100 Reg number An 416 101 Reg number dig PC dg An Xn 110 Reg number An dg PC Xn bd An Xn 110 Reg number An bd PC Xn MOTOROLA INSTRUCTION SET CPU32 4 34 REFERENCE MANUAL Bcc Branch Conditionally Bcc Operation If condition true then d PC Assembler Syntax Bcc labebAttributes Size Byte Word Long
20. cc Name Code Description cc Name Code Description CC Carry Clear 0100 LS Low or Same 0011 2 CS Carry Set 0101 C LT Less Than 1101 N eV N eV EQ Equal 0111 Z MI Minus 1011 N F Never equal 0001 0 Not Equal 0110 Z GE Greateror Equal 1100 NeVNeV PL Plus 1010 N GT Greater Than 1110 NeVeZ NeVeZ Always true 0000 HI High 0010 Overflow Clear 1000 V LE Less or Equal 1111 ZNeVNeV 5 Overflow Set 1001 V Condition Codes Not affected Instruction Format 15 14 13 12 11 10 9 8 7 6 5 4 2 1 0 0 1 0 1 CONDITION 1 1 1 1 OPMODE OPTIONAL WORD OR LONG WORD Instruction Fields Condition field The binary code for one of the conditions listed in the table Opmode field Selects the instruction form CPU32 010 Instruction is followed by word size operand 011 Instruction is followed by long word size operand 100 Instruction has no operand REFERENCE MANUAL INSTRUCTION SET MOTOROLA 4 165 TRA PV Trap on Overflow TRA PV Operation If V then TRAP Assembler Syntax TRAPV Attributes Unsized Description If the CCR overflow bit is set there is a TRAPV exception vector number 7 If the bit is not set the processor performs no operation and execution continues with the next instruction Condition Codes Not affected Instruction Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 0 0 1 1 1 0 0 1 1 1 0 1 1 0 MOTOROLA INSTRUCTI
21. normal exception background and halted Normal processing is associated with instruction execution The bus is used to fetch instructions and operands and to store results Exception processing is associated with interrupts trap instructions tracing and other exception conditions Background processing allows interactive debugging of the system Halted processing is an indication of catastrophic hardware failure See SECTION 5 PROCESSING STATES for complete information 1 1 8 Privilege States The processor can operate at either of two privilege levels Supervisor level is more privileged than user level all instructions are available at supervisor level but ac cess is restricted at user level Effective use of privilege level can protect system resources from uncontrolled access The state of the S bit in the status register determines access level and whether the stack pointer USP or the supervisor stack pointer SSP is used for stack operations See SECTION 5 PROCESSING STATES for a complete explanation of privilege lev els 1 2 Block Diagram A block diagram of the CPU32 is shown in Figure 1 2 The functional elements oper ate concurrently Essential synchronization of instruction execution and buss opera tion is maintained by the sequencer control unit The bus controller prefetches instructions and operands A three stage pipeline is used to hold and decode instruc tions prior to execution The execution uni
22. 0 Transfer the address register to the USP 1 Transfer the USP to the address register Register field Specifies the address register for the operation CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4 97 MOVEC Move Control Register MOV EC Privileged Instruction Operation If supervisor state then Rc Rn or Rn gt Rc else TRAP Assembler MOVEC Rc Rn Syntax MOVEC Rn Re Attributes Size Long Description Moves the contents of the specified control register Rc to the spec ified general register Rn or copies the contents of the specified general register to the specified control register MOVEC is always a 32 bit transfer even though the con trol register may be implemented with fewer bits Unimplemented bits are read as zeros Condition Codes Not affected Instruction Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 0 0 1 1 1 0 0 1 1 1 1 0 1 dr AID REGISTER CONTROL REGISTER Instruction Fields dr field Specifies the direction of the transfer 0 Control register to general register 1 General register to control register A D field Specifies the type of general register 0 Data register 1 Address register Register field Specifies the register number Control Register field Specifies the control register Hex Control Register 000 Source Function Code SFC 001 Destination Function Code DFC 800 Use
23. 100 Transfer word from memory to register 101 Transfer long from memory to register 110 Transfer word from register to memory 111 Transfer long from register to memory Address Register field Specifies the address register which is used in the address register indirect plus displacement addressing mode Displacement field Specifies the displacement used in the operand address CPU32 INSTRUCTION SET REFERENCE MANUAL MOTOROLA 4 103 MOVEQ Move Quick MOVEQ Operation Immediate Data Destination Assembler Syntax data Dn Attributes Size Long Description Moves a byte of immediate data to a 32 bit data register The data in an 8 bit field within the operation word is sign extended to a long operand in the data register as it is transferred Condition Codes X N Z V me 0 0 X Not affected N Set if the result is negative Cleared otherwise Z Set if the result is zero Cleared otherwise V Always cleared C Always cleared Instruction Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 1 1 REGISTER 0 DATA Instruction Fields Register field Specifies the data register to be loaded Data field Eight bits of data which are sign extended to a long operand MOTOROLA INSTRUCTION SET CPU32 4 104 REFERENCE MANUAL M OV ES Move Address Space M OV ES Privileged Instruction Operation If supervisor state
24. After the division this register contains the 32 bit remainder If Dr and Dq are the same register only the quotient is returned If Size is 1 this field also specifies the data register that contains the high order 32 bits of the dividend NOTE Overflow occurs if the quotient is larger than a 32 bit signed integer CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4 71 EOR Exclusive OR EOR Operation Source Destination Destination Assembler Syntax EOR Dn ea Attributes Size Byte Word Long Description Performs an exclusive OR operation on the destination operand using the source operand and stores the result in the destination location The source operand must be a data register The destination operand is specified in the effective address field Condition Codes X N 2 V 0 0 X Not affected N Set if the most significant bit of the result is set Cleared otherwise Z Set if the result is zero Cleared otherwise V Always cleared Always cleared Instruction Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EFFECTIVE ADDRESS 1 0 1 1 REGISTER OPMODE MODE REGISTER Instruction Fields Register field Specifies any of the eight data registers Opmode field Byte Word Long Operation 000 001 010 ea Dn 2 ea MOTOROLA INSTRUCTION SET CPU32 4 72 REFERENCE MANUAL EOR Exclusive OR EOR Effective Address field Sp
25. An M68000 Family processor makes two classes of memory references each of which has a complete separate logical address space References to opcodes and extension words are program space references Operand reads and writes are primarily data space references Operand reads are from data space in all but two cases immediate operands embedded in the instruc tion stream and operands addressed relative to the current program counter are pro gram space references All operand writes are to data space CPU32 DATA ORGANIZATION AND ADDRESSING CAPABILITIES MOTOROLA REFERENCE MANUAL 3 1 3 2 Notation Conventions EA Effective address An Address register n Example A3 is address register 3 Dn Data register n Example D5 is data register 5 Rn Any register data or address Xn SIZE SCALE Index register n data or address Index size W for word L for long word Scale factor 1 2 4 or 8 for byte word long word or quad word scaling PC Program counter SR Status register SP Stack pointer CCR Condition code register USP User stack pointer SSP Supervisor stack pointer dn Displacement value n bits wide bd Base displacement L Long word size W Word size B Byte size An Identifies an indirect address in a register 3 3 Implicit Reference Some instructions make implicit reference to the program counter the system stack pointer the user stack pointer the supervisor
26. Attributes Size Byte Word Long Description Performs an AND operation of the source operand with the destina tion operand and stores the result in the destination location The contents of an address register may not be used as an operand Condition Codes X N 2 V i 0 0 X Not affected N Set if the most significant bit of the result is set Cleared otherwise Z Set if the result is zero Cleared otherwise V Always cleared Always cleared Instruction Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EFFECTIVE ADDRESS 1 1 0 0 REGISTER OPMODE MODE REGISTER Instruction Fields Register field Specifies any of the eight data registers Opmode field Byte Word Long Operation 000 001 010 ea 2 Dn 100 101 110 Dn e ea gt ea MOTOROLA INSTRUCTION SET CPU32 4 26 REFERENCE MANUAL AND Logical AND AND Effective Address field Determines addressing mode If the location specified is a source operand only data addressing modes are allowed as shown Addressing Mode Mode Register Addressing Mode Mode Register Dn 000 Reg number Dn xxx W 111 000 An xxx L 111 001 An 010 Reg number An data 111 100 An 011 Reg number An An 100 Reg number An 416 101 Reg number dig PC 111 010 dg An Xn 110 Reg number An dg PC Xn 111 011 bd An Xn 110 Reg number An
27. Byte Word Long Operation 000 001 010 Dn gt Dn 199 101 110 Dn ea ADDA 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EFFECTIVE ADDRESS 1 1 0 1 REGISTER OPMODE MODE REGISTER Opmode Field Word Long Operation 011 111 ea An An ADDX 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 0 1 REGISTER Rx 1 SIZE 0 0 R M REGISTER Ry Size Field 00 Byte 01 Word 10 Long R M Field 0 Data Register to Data Register 1 Memory to Memory If R M 0 both registers must be data registers If R M 1 both registers must be address registers for Predecrement Addressing mode ASL ASR Register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 0 COUNT REGISTER dr SIZE ilr 0 0 REGISTER Count Register Field If I R Field 0 Specifies Shift Count If I R Field 1 Specifies Data Register that contains Shift Count dr Field 0 Right 1 Left Size Field 00 Byte 01 Word 10 Long I R Field 0 Immediate Shift Count 1 Register Shift Count CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4 185 LSL LSR Register 15 14 13 12 11 10 9 8 6 5 4 3 2 1 0 1 1 1 0 COUNT REGISTER dr SIZE ilr 0 1 REGISTER Count Register Field If I R Field 0 Specifies Shift Count If I R Field 1 Specifies Data Register that contains Shift Count dr Field 0 Right
28. CHK2 6 5 4 3 2 1 0 EFFECTIVE ADDRESS 0 0 0 0 SIZE 0 MODE REGISTER D A REGISTER 0 0 0 0 0 0 0 0 0 Instruction Fields Size field Specifies the size of the operation 00 Byte operation 01 Word operation 10 Long operation Effective Address field Specifies the location of the bounds operands Only control addressing modes are allowed as shown Addressing Mode Mode Register Addressing Mode Mode Register Dn xxx W 111 000 An xxx L 111 001 An 010 Reg number An data An An RES Ez 416 An 101 Reg number An dig PC 111 010 dg An Xn 110 Reg number An dg PC Xn 111 011 bd An Xn 110 Reg number An bd PC Xn 111 011 D A field Specifies whether an address register or data register is to be checked 0 Data register 1 Address register Register field Specifies the address or data register that contains the value to be checked MOTOROLA 4 52 INSTRUCTION SET CPU32 REFERENCE MANUAL CLR Clear an Operand CLR Operation 0 Destination Assembler Syntax CLR ea Attributes Size Byte Word Long Description Clears the destination operand to zero Condition Codes X N 2 V 0 1 0 0 Not affected Always cleared Always set Always cleared Always cleared Instructi
29. CPU32 REFERENCE MANUAL Motorola reserves the right to make changes without further notice to any products herein Motorola makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Motorola assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters can and do vary in different applications All operating parameters including Typicals must be validated for each customer application by customer s technical experts Motorola does not convey any license under its patent rights nor the rights of others Motorola products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur Should Buyer purchase or use Motorola products for any such unintended or unauthorized application Buyer shall indemnify and hold Motorola and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such uninten
30. O lt NZ amp 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EFFECTIVE ADDRESS 0 0 0 0 0 0 1 0 SIZE MODE REGISTER WORD DATA 16 BITS BYTE DATA 8 BITS LONG DATA 32 BITS Instruction Fields Size field Specifies the size of the operation 00 Byte operation 01 Word operation 10 Long operation MOTOROLA INSTRUCTION SET CPU32 4 28 REFERENCE MANUAL ANDI AND Immediate Effective Address field Specifies the destination operand Only data alterable addressing modes are allowed as shown ANDI Addressing Mode Mode Register Addressing Mode Mode Register Dn 000 Reg number Dn xxx W 111 000 An xxx L 111 001 An 010 Reg number An data An 011 Reg number An An 100 Reg number An 96 An 101 Reg number An 96 PC dg An Xn 110 Reg number An dg PC Xn bd An Xn 110 Reg number An bd PC Xn Immediate field Data immediately following the instruction If size 00 the data is the low order byte of the immediate word If size 01 the data is the entire immediate word If size 10 the data is the next two immediate words CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4 29 AN AND Immediate to Condition Code Register AN to CCR to CCR Operation Source CCR CCR Assembler Syntax ANDI data CCR Attributes Size B
31. isters An is the put pointer and Am is the get pointer To implement growth of the queue from low to high memory use An to put data into the queue Am to get data from the queue After a put operation the put register points to the next available queue space and the unchanged get register points to the next item to be removed from the queue After a get operation the get register points to the next item to be removed from the queue and the unchanged put register points to the next available queue space which is illustrated as follows LOW MEMORY LAST GET FREE GET Am NEXT GET LAST PUT PUT An FREE HIGH MEMORY To implement a queue as a circular buffer the relevant address register should be checked and if necessary adjusted before performing a put or get operation The address register is adjusted by subtracting the buffer length in bytes from the register contents To implement growth of the queue from high to low memory use An to put data into the queue Am to get data from the queue After a put operation the put register points to the last item placed in the queue and the unchanged get address register points to the last item removed from the queue After a get operation the get register points to the last item removed from the queue and the unchanged put register points to the last item placed in t
32. 96 An 101 Reg number An 96 PC dg An Xn 110 Reg number An dg PC Xn bd An Xn 110 Reg number An bd PC Xn MOTOROLA INSTRUCTION SET CPU32 4 118 REFERENCE MANUAL NOP No Operation NOP Operation None Assembler Syntax NOP Attributes Unsized Description Performs no operation The program counter is incremented but processor state is otherwise unaffected Execution continues with the instruction fol lowing the NOP instruction The NOP instruction does not begin execution until all pending bus cycles are completed This synchronizes the pipeline and prevents instruction overlap Condition Codes Not affected Instruction Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 0 0 1 1 1 0 0 1 1 1 0 0 0 1 CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4 119 NOT Logical Complement N OT Operation Destination Destination Assembler Syntax NOT ea Attributes Size Byte Word Long Description Calculates the ones complement of the destination operand and stores the result in the destination location Condition Codes X N Z V 0 0 Not affected Set if the result is negative Cleared otherwise Set if the result is zero Cleared otherwise Always cleared Always cleared Instruction Format lt 2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EFFECTIVE
33. ADDQ 2 V Sm 3 C SmeDm RmeDm SmeRm ADDX V SmeDmeRm SmeDme Rm C2SmeDm Rm e Dm Sm Hm Z Z e Rm e RO AND ANDI EOR EORI MOVEQ MOVE OR y 0 0 ORI CLR EXT TAS TST CHK D U U U CHK2 CMP2 Z R LB R UB U U C LB UB IR lt LB R gt UB UB lt LB R gt UB R lt LB SUB SUBI SUBQ 2 9 V SmeDmeRm SmeDmeRm C SmeDm RmeDm SmeRm SUBX V SmeDmeRm SmeDmeRm E C2SmeDm Rm e Dm Sm Rm Z ZeRm RO CMP CMPI CMPM __ f 2 9 V SmeDmeRm SmeDmeRm C SmeDm RmeDm SmeRm DIVS DIVU 0 V Division Overflow MULS MULU 0 Multiplication Overflow SBCD NBCD U 2 U Decimal Borrow Z Ze Rm e e RO NEG n A x 2 V DmeRm 1C Dm Rm NEGX V DmeRm ii C Dm Rm 0 Z ZeRm e RO CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4 5 Table 4 1 Condition Code Computations Continued Operations X N Z V C Special Definition ASL V Dme Dm 1 Dm r Dme i 2 2 Dm 1 4 Dm r C Dm r 1 ASL r 0 t 0 0 LSL ROXL i x 0 2 C Dm r 1 LSR r 0 Y 0 0 ROXL r 0 5 0 C X ROL 0 C Dm r 1 ROL r 0 0 0 ASR LSR ROXR 0 2 C Dr 1 ASR LSR r 0 0 0 ROXR r 0 i 0 C X ROR 3 i 0 C D
34. An 8 Destination Source X gt Destination 4 3 8 Program Control Instructions A set of subroutine call and return instructions and conditional and unconditional branch instructions perform program control operations Table 4 8 summarizes these instructions Table 4 8 Program Control Operations Instruction Syntax Operand Size Operation Conditional Bcc label 8 16 32 If condition true then PC d gt PC DBcc Dn label 16 If condition false then Dn 1 gt PC if Dn z 1 then PC d gt PC Scc ea 8 If condition true then destination bits are set to one else destination bits are cleared to zero Unconditional BRA label 8 16 32 PC d PC BSR label 8 16 32 SP 4 gt SP PC 5 SP PC d PC MOTOROLA INSTRUCTION SET CPU32 4 10 REFERENCE MANUAL Table 4 8 Program Control Operations Instruction Syntax Operand Size Operation JMP ea none Destination PC JSR ea none SP 4 gt SP PC 2 SP destination PC NOP none none PC 2 Returns RTD d 16 SP gt PC SP 4 d SP RTR none none SP CCR SP 2 gt SP SP 2 PC SP 4 SP RTS none none SP PC SP 4 SP To specify conditions for change in program control condition codes must be substi tuted for the letters cc in conditional program control opcodes Condition test mne monics are given below Refer to 4 3 10 C
35. An bd PC Xn 111 011 D A field Specifies whether an address register or data register is compared 0 Data register 1 Address register Register field Specifies the address or data register that contains the value to be checked CPU32 REFERENCE MANUAL INSTRUCTION SET MOTOROLA 4 63 DBcc Operation Assembler Syntax Attributes Description cc Name CC Carry Clear CS Carry Set EQ Equal F Never equal Test Condition Decrement and Branch DBcc If condition false then Dn 1 gt Dn If Dn z 1 then PC d PC DBcc Dn label Size Word Controls a loop of instructions The parameters are a condition code a data register counter and a displacement value The instruction first tests the con dition for termination if it is true no operation is performed If the termination condi tion is not true the low order 16 bits of the counter data register are decremented by one If the result is 1 execution continues with the next instruction If the result is equal to 1 execution continues at the location indicated by the current value of the PC plus the sign extended 16 bit displacement The value in the PC is the address of the instruction word of the DBcc instruction plus two The displacement is a twos complement integer that represents the relative distance in bytes from the current PC to the destination PC Condition code cc specifies one of the following
36. Bus Faults Double 7 5 Compatibility 68000 Addressing 3 14 Condition Code Computations 4 5 Register 2 3 4 5 Condition Tests 4 12 Control Registers 2 5 Conventions Notation 3 2 Correcting Faults 6 18 CPU Serial Logic 7 8 Space 5 3 D Data BDM Serial Format 7 7 Movement Instructions 4 6 Register Direct Addressing Mode 3 3 Registers 2 4 Structures Other Stacks and Queues 3 15 Types 2 3 Deterministic Opcode Tracking 7 2 7 25 Development Features Standard 7 1 Development Support 7 1 Development System Serial Logic 7 10 INDEX MOTOROLA 1 1 Double Bus Faults 6 5 7 5 Dynamic Bus Sizing 6 16 6 23 x 38 Effective Address 3 3 Calculation Timing Table CEA 8 13 Encoding Summary 3 9 Fetch Timing Table FEA 8 12 Enhanced Addressing Modes 1 4 Enhanced Instruction Set 1 4 Errors Bus 6 6 Exception Address Error 6 7 Breakpoint Instruction BKPT 6 8 Bus Error 6 6 Definition of Exception Processing 6 1 Format Error 6 9 Illegal Instruction 6 9 Instruction Traps 6 8 Interrupts 6 12 Multiple 6 4 Priority 6 4 Privilege Violation 6 10 Processing Sequence 6 3 Related Instructions and Operations 8 21 Reset 6 5 Return from 6 13 Stack Frame 6 3 Trace 6 11 Types 6 2 Unimplemented Instruction 6 9 Vectors 6 1 Execution Overlap 8 7 Execution Time Calculations 8 5 ps Faults Correcting 6 18 Type via RTE 6 19 Type via Software 6 19 Type II via RTE 6 19 Type III via Conversion and Restart 6 20 Type
37. Memory shift and rotate operations shift word length operands one bit position only The SWAP instruction exchanges the 16 bit halves of a register Performance of shift rotate instructions is enhanced so that use of the ROR and ROL instructions with a shift count of eight allows fast byte swapping Table 4 5 is a summary of the shift and rotate operations Table 4 5 Shift and Rotate Operations 4 3 6 Bit Manipulation Instructions Instruction Syntax Operand Size Operation ASL Dn Dn 8 16 32 data Dn 8 16 32 ACPE 125 a 3 ea 16 ASR Dn Dn 8 16 32 data Dn 8 16 32 an TON ea 16 LSL Dn Dn 8 16 32 data Dn 8 16 32 spe ae ea 16 LSR Dn Dn 8 16 32 data Dn 8 16 32 zi we ea 16 ROL Dn Dn 8 16 32 data Dn 8 16 32 C 1 lt 16 ROR Dn Dn 8 16 32 data Dn 8 16 32 i ME ea 16 ROXL Dn Dn 8 16 32 data Dn 8 16 32 ea 16 lt lt lt lt lt X lt ROXR Dn Dn 8 16 32 data Dn 8 16 32 ea 16 X gt gt gt SWAP Dn 16 MSW LSW A CPU32 Bit manipulation operations are accomplished using the following instructions bit test BTST bit test and set BSET bit test and clea
38. PC Xn 111 011 Long only all others are byte only Instruction Format Bit Number Dynamic specified in a register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EFFECTIVE ADDRESS 0 0 0 0 REGISTER 1 0 0 MODE REGISTER Instruction Fields Bit Number Dynamic Register field Specifies the data register that contains the bit number Effective Address field Specifies the destination location Only data addressing modes are allowed as shown Addressing Mode Mode Register Addressing Mode Mode Register Dn 000 Reg number Dn xxx W 111 000 An xxx L 111 001 An 010 Reg number An data 111 100 An 011 Reg number An An 100 Reg number An 416 101 Reg number dig PC 111 010 dg An Xn 110 Reg number An dg PC Xn 111 011 bd An Xn 110 Reg number An bd PC Xn 111 011 Long only all others are byte only MOTOROLA INSTRUCTION SET CPU32 4 48 REFERENCE MANUAL Check Register Against Bounds Operation If Dn 0 or Dn gt Source then TRAP Assembler Syntax CHK ea Dn Attributes Size Word Long Description Compares the value in the data register specified by the instruction to zero and to the upper bound effective address operand The upper bound is a twos complement integer If the register value is less than zero or greater than th
39. address of the next instruction to be executed 15 0 SP gt STATUS REGISTER 02 NEXT INSTRUCTION PROGRAM COUNTER HIGH NEXT INSTRUCTION PROGRAM COUNTER LOW 06 0 0 1 0 VECTOR OFFSET 08 FAULTED INSTRUCTION PROGRAM COUNTER HIGH FAULTED INSTRUCTION PROGRAM COUNTER LOW Figure 6 4 Format 2 Six Word Stack Frame Hardware breakpoints also utilize this format The faulted instruction program counter value is the address of the instruction executing when the breakpoint was sensed Usually this is the address of the instruction that caused the breakpoint but because released writes can overlap following instructions the faulted instruction program counter may point to an instruction following the instruction that caused the breakpoint The address to which RTE returns is the address of the next instruction to be executed 6 4 3 BERR Stack Frame This stack frame is created when a bus cycle fault is detected The CPU32 BERR stack frame differs significantly from the equivalent stack frames of other M68000 Family members The only internal machine state required in the CPU32 stack frame is the bus controller state at the time of the error and a single register MOTOROLA EXCEPTION PROCESSING CPU32 6 22 REFERENCE MANUAL Bus operation in progress at the time of a fault is conveyed by the SSW 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TP MV 0 TR B1 BO RR RM IN RW LG SIZ FUNC
40. bd Figure 3 4 Using Absolute Address with Indexes Scaling does not add to the EA calculation time However when combined with the appropriate derived modes scaling produces additional capabilities Arrayed struc tures can be addressed absolutely and then subscripted for example bd Rn SCALE Optionally an address register that contains a dynamic displacement can be MOTOROLA DATA ORGANIZATION AND ADDRESSING CAPABILITIES CPU32 3 12 REFERENCE MANUAL included in the address calculation od An Rn SCALE Another variation that can be derived is An Rn SCALE In the first case the array address is the sum of the contents of a register and a displacement see Figure 3 5 In the second example An contains the address of an array and Rn contains a subscript SYNTAX MOVE W A5 A6 L SCALE A7 WHERE A5 ADDRESS OF ARRAY STRUCTURE A6 INDEX NUMBER OF ARRAY ITEM A7 STACK POINTER SIMPLE ARRAY RECORD OF 1 WORD SCALE 1 SCALE 2 7 0 15 0 Abs A6 1 2 3 gt 2 4 RECORD OF 2 WORDS RECORD OF 4 WORDS SCALE 4 SCALE 8 15 0 15 0 A6 1 2 NOTE Regardless of array structure software increments index to point to next record Figure 3 5 Addressing Array Items CPU32 DATA ORGANIZATION AND ADDRESSING CAPABILITIES MOTOROLA REFERENCE MANUAL 3 13 3 5 2 General Addressing Mode Summary The addressing modes described in the previous paragraphs are derived from specific combination
41. bd PC Xn 111 011 If the location specified is a destination operand only memory alterable addressing modes are allowed as shown Addressing Mode Mode Register Addressing Mode Mode Register Dn xxx W 111 000 An xxx L 111 001 An 010 Reg number An data An 011 Reg number An An 100 Reg number An 96 An 101 Reg number An 96 PC dg An Xn 110 Reg number An dg PC Xn bd An Xn 110 Reg number An bd PC Xn NOTES 1 The Dn mode is used when the destination is a data register the destination ea mode is invalid for a data register 2 Most assemblers use ANDI when the source is immediate data CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4 27 AN AND Immediate AN Operation Immediate Data e Destination Destination Assembler Syntax ANDI 4 data ea Attributes Size Byte Word Long Description Performs an AND operation of the immediate data with the destina tion operand and stores the result in the destination location The size of the immedi ate data must match the operation size Condition Codes X N 7 V 0 0 Not affected Set if the most significant bit of the result is set Cleared otherwise Set if the result is zero Cleared otherwise Always cleared Always cleared Instruction Format
42. in a multiprocessor system 6 3 Fault Recovery There are four phases of recovery from a fault recognizing the fault saving the pro cessor state repairing the fault if possible and restoring the processor state Saving and restoring the processor state are described in the following paragraphs The stack contents are identified by the special status word SSW In addition to iden tifying the fault type represented by the stack frame the SSW contains the internal pro cessor state corresponding to the fault 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TP MV 0 TR B1 BO RR RM IN RW LG SIZ FUNC TP BERR frame type MV MOVEM in progress TR Trace pending 1 Breakpoint channel 1 pending BO Breakpoint channel 0 pending RR Rerun write cycle after RTE RM Faulted cycle was read modify write IN Instruction other RW Read write of faulted bus cycle LG Original operand size was long word SIZ Remaining size of faulted bus cycle FUNC Function code of faulted bus cycle MOTOROLA EXCEPTION PROCESSING CPU32 6 14 REFERENCE MANUAL The TP field defines the class of the faulted bus operation Two BERR exception frame types are defined One is for faults on prefetch and operand accesses and the other is for faults during exception frame stacking 0 Operand or prefetch bus fault 1 Exception processing bus fault MV is set when the operand transfer portion of the MOVEM instruction is in p
43. which are packed BCD num bers can be addressed in two different ways 1 Data register to data register Operands are contained in data registers spec ified by the instruction 2 Memory to memory Operands are addressed with the predecrement ad dressing mode using address registers specified by the instruction Condition Codes X N 2 V C z U U X Set the same as the carry bit N Undefined Z Cleared if the result is nonzero Unchanged otherwise V Undefined Set if a decimal carry was generated Cleared otherwise NOTE Normally the Z condition code bit is set via programming before the start of an operation This allows successful tests for zero results upon completion of multiple precision operations Instruction Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 0 0 REGISTER Rx 1 0 0 0 0 RM REGISTER Ry CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4 15 A BC D Add Decimal with Extend A BC D Instruction fields Register Rx field Specifies the destination register If R M 0 specifies a data register If R M 1 specifies an address register for predecrement addressing mode R M field Specifies the operand addressing mode 0 the operation is data register to data register 1 the operation is memory to memory Register Ry field Specifies the source register If R M 0 specifies a data register If R M 1 specifies an address
44. 0 SUBQ FEA 0 3 5 0 1 x ADDI Rn 0 0 2 0 1 0 ADDI FEA 0 3 5 0 1 x ANDI Rn 0 0 2 0 1 0 ANDI FEA 0 3 5 0 1 x EORI Rn 0 0 2 0 1 0 EORI FEA 0 3 5 0 1 x ORI Rn 0 0 2 0 1 0 ORI FEA 0 3 5 0 1 x SUBI Rn 0 0 2 0 1 0 SUBI FEA 0 3 5 0 1 x CMPI Rn 0 0 2 0 1 0 CMPI FEA 0 3 5 0 1 x X There is one bus cycle for byte and word operands and two bus cycles for long operands For long bus cycles add two clocks to the tail and to the number of cycles An fetch effective address time must be added for this instruction FEA FEA OPER CPU32 INSTRUCTION EXECUTION TIMING MOTOROLA REFERENCE MANUAL 8 17 8 3 7 Binary Coded Decimal and Extended Instructions The binary coded decimal and extended instruction table indicates the number of clock periods needed for the processor to perform the specified operation using the specified addressing mode No additional tables are needed to calculate total effective execution time for these instructions The total number of clock cycles is outside the parentheses The numbers inside parentheses r p w are included in the total clock cycle number All timing data assumes two clock reads and writes Instruction Head Tail Cycles ABCD Dn Dm 2 0 4 0 1 0 ABCD An 2 2 12 2 1 1 SBCD Dn Dm 2 0 4 0 1 0 SBCD An 2 2 12 2 1 1 ADDX Dn Dm 0 0 2 0 1 0 ADDX An 2 2 10 2 1
45. 1 Left Size Field 00 Byte 01 Word 10 Long I R Field 0 Immediate Shift Count 1 Register Shift Count ROXL ROXR Register 15 14 13 12 11 10 9 8 5 4 3 2 1 0 1 1 1 0 COUNT REGISTER dr SIZE ilr 1 0 REGISTER Count Register Field If I R Field 0 Specifies Shift Count If I R Field 1 Specifies Data Register that contains Shift Count dr Field 0 Right 1 Left Size Field 00 Byte 01 Word 10 Long I R Field 0 Immediate Shift Count 1 Register Shift Count ROL ROR 15 14 13 12 11 10 9 8 5 4 3 2 1 0 1 1 1 0 COUNT REGISTER dr SIZE ilr 1 1 REGISTER Count Register Field If I R Field 0 Specifies Shift Count If I R Field 1 Specifies Data Register that contains Shift Count dr Field 0 Right 1 Left Size Field 00 Byte 01 Word 10 Long I R Field 0 Immediate Shift Count 1 Register Shift Count ASL ASR Memory 15 14 13 12 11 10 9 8 7 5 4 3 2 1 0 EFFECTIVE ADDRESS 1 1 1 0 0 0 0 dr 1 MODE REGISTER dr Field 0 Right 1 Left LSL LSR Memory dr Field 0 Right 1 Left MOTOROLA INSTRUCTION SET 4 186 EFFECTIVE ADDRESS REGISTER CPU32 REFERENCE MANUAL ROXL ROXR Memory 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EFFECTIVE ADDRESS MODE REGISTER dr Field 0 Right 1 Left ROL ROR Memory EFFECTIVE ADDRESS REGISTER dr Field 0 Right 1 Left LPSTOP 15 142001010 9 8 7 6 5 4
46. 1 SUBX Dn Dm 0 0 2 0 1 0 SUBX An 2 2 10 2 1 1 CMPM An Am 1 0 8 2 1 0 8 3 8 Single Operand Instructions The single operand instruction table indicates the number of clock periods needed for the processor to perform the specified operation using the specified addressing mode The total number of clock cycles is outside the parentheses The numbers inside pa rentheses r p w are included in the total clock cycle number All timing data assumes two clock reads and writes Instruction Head Tail Cycles CLR Dn 0 0 2 0 1 0 CLR CEA 0 2 4 0 1 x NEG Dn 0 0 2 0 1 0 NEG FEA 0 3 5 0 1 x NEGX Dn 0 0 2 0 1 0 NEGX FEA 0 3 5 0 1 x NOT Dn 0 0 2 0 1 0 NOT FEA 0 3 5 0 1 x EXT Dn 0 0 2 0 1 0 NBCD Dn 2 0 4 0 1 0 NBCD FEA 0 2 6 0 1 1 Scc Dn 2 0 4 0 1 0 Scc CEA 2 2 6 0 1 1 TAS Dn 4 0 6 0 1 0 TAS CEA 1 0 10 0 1 1 TST FEA 0 0 2 0 1 0 X There is one bus cycle for byte and word operands and two bus cycles for long operands For long bus cycles add two clocks to the tail and to the number of cycles MOTOROLA INSTRUCTION EXECUTION TIMING CPU32 8 18 REFERENCE MANUAL 8 3 9 Shift Rotate Instructions The shift rotate instruction table indicates the number of clock periods needed for the processor to perform the specified operation on the given addressing mode Footnotes indicate when to account for the appropriate effective
47. 10 9 8 7 6 5 4 3 2 1 0 0 1 1 0 0 0 0 1 8 BIT DISPLACEMENT 16 BIT DISPLACEMENT IF 8 BIT DISPLACEMENT 00 32 BIT DISPLACEMENT IF 8 BIT DISPLACEMENT FF CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4 181 MOVEQ 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 1 1 REGISTER 0 DATA Data Field Data is sign extended to a long operand and all 32 bits are transferred to the data register OR 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EFFECTIVE ADDRESS 1 1 0 0 REGISTER OPMODE MODE REGISTER Opmode Field Byte Word Long Operation 000 001 010 Dn Dn 100 101 110 Dn ea ea DIVU 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EFFECTIVE ADDRESS 1 0 0 0 REGISTER 0 1 1 MODE REGISTER DIVS 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EFFECTIVE ADDRESS 1 0 0 0 REGISTER 1 1 1 MODE REGISTER SBCD 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 0 0 REGISTER Ry 1 0 0 0 0 R M REGISTER Rx R M Field 0 Data Register to Data Register 1 Memory to Memory If R M 0 both registers must be data registers If R M 1 both registers must be address registers for Predecrement Addressing mode SUB 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EFFECTIVE ADDRESS 1 1 1 REGISTER OPMODE a Opmode Field Byte Word Long Operation 000 001 010 Kea Dn Dn 100 10
48. 16 BITS BYTE DATA 8 BITS LONG DATA 32 BITS Size Field 00 Byte 01 Word 10 Long EORI to CCR 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 1 0 1 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 BYTE DATA 8 BITS EORI to SR 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 1 0 1 0 0 1 1 1 1 1 0 0 WORD DATA 16 BITS CMPI 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EFFECTIVE ADDRESS 0 0 0 0 1 1 0 0 SIZE MODE REGISTER WORD DATA 16 BITS BYTE DATA 8 BITS LONG DATA 32 BITS Size Field 00 Byte 01 Word 10 Long MOVES 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 B AID REGISTER dr 0 0 0 0 0 dr Field 0 EA to Register 1 Register to EA MOTOROLA INSTRUCTION SET CPU32 4 174 REFERENCE MANUAL MOVE 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DESTINATION EFFECTIVE ADDRESS 0 0 SIZE REGISTER MODE MODE REGISTER Size Field 00 Byte 01 Word 10 Long Note register and mode locations MOVEA 15 He 2 AT 10 9 8 7 6 5 4 3 2 1 0 DESTINATION EFFECTIVE ADDRESS 0 0 SIZE 0 0 1 REGISTER MODE REGISTER Size Field 00 Byte 01 Word 10 Long NEGX EFFECTIVE ADDRESS REGISTER Size Field 00 Byte 01 Word 10 Long MOVE from SR 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EFFECTIVE ADDRESS 0 1 0 0 0 0 0 0 1 1 MODE REGISTER CHK 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EFFECTIVE ADDRESS 0 1 0 0 REGISTER SIZE 0 M
49. 6 10 REFERENCE MANUAL 6 2 10 Tracing To aid in program development M68000 processors include a facility to allow tracing of instruction execution CPU32 tracing also has the ability to trap on changes in pro gram flow In trace mode a trace exception is generated after each instruction exe cutes allowing a debugging program to monitor the execution of a program under test The T1 and TO bits in the supervisor portion of the status register are used to control tracing When T 1 0 00 tracing is disabled and instruction execution proceeds normally see Table 6 3 Table 6 3 Tracing Control T1 TO Tracing Function 0 0 No tracing 0 1 Trace on change of flow 1 0 Trace on instruction execution 1 1 Undefined reserved When T 1 0 2 01 at the beginning of instruction execution a trace exception will be generated if the program counter changes sequence during execution All branches jumps subroutine calls returns and status register manipulations can be traced in this way No exception occurs if a branch is not taken When T 1 0 2 10 at the beginning of instruction execution a trace exception will be generated when execution is complete If the instruction is not executed either be cause an interrupt is taken or because the instruction is illegal unimplemented or priv ileged an exception is not generated At the present time T 1 0 11 is an undefined condition It is reserved by Motorola
50. 7 9 represents a sample circuit providing for both BKPT assertion methods As the name implies FORCE_BGND is used to force a transition into BDM by the asser tion of BKPT FORCE_BGND can be a short pulse or can remain asserted until FREEZE is asserted Once asserted the set reset latch holds BKPT low until the first SHIFT_CLK is applied BKPT_TAG SHIFT_CLK 94 KPT DSCLK RESET FORCE_BGND Figure 7 9 BKPT DSCLK Logic Diagram BKPT_TAG should be timed to the bus cycles since it is not latched If extended past the assertion of FREEZE the negation of BKPT_TAG appears to the CPU32 as the first DSCLK DSCLK is the gated serial clock Normally high it pulses low for each bit to be trans ferred At the end of the seventeenth clock period it remains high until the start of the next transmission Clock frequency is implementation dependent and may range from DC to the maximum specified frequency Although performance considerations might dictate a hardware implementation software solutions are not precluded provided se rial bus timing is maintained 7 2 8 Command Set Following is a description of the command set available in BDM 7 2 8 1 Command Format The following standard bit format is utilized by all BDM commands 15 10 9 8 7 6 5 4 3 2 0 OPERATION 0 RW OP SIZE 0 0 ND REGISTER EXTENSION WORD S Operation Field Commands are distinguished by the operation field This 6 bit f
51. 9 8 7 6 5 4 3 2 1 0 0 1 1 0 0 0 0 0 8 BIT DISPLACEMENT 16 BIT DISPLACEMENT IF 8 BIT DISPLACEMENT 00 32 BIT DISPLACEMENT IF 8 BIT DISPLACEMENT FF Instruction Fields 8 Bit Displacement field Twos complement integer specifying the number of bytes between the branch instruction and the next instruction to be executed 16 Bit Displacement field Used for a larger displacement when 8 bit displacement is 00 32 Bit Displacement field Used for a larger displacement when 8 bit displacement is FF NOTE A branch to the instruction immediately following automatically uses 16 bit displacement because the 8 bit displacement field contains 00 zero offset CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4 43 BS ET Test a Bit and Set BS ET Operation bit numberof Destination gt Z 1 bit number of Destination Assembler BSET Dn ea Syntax BSET lt data ea Attributes Size Byte Long Description Tests a bit in the destination operand sets the Z condition code appropriately then sets the specified bit in the destination operand When a data reg ister is the destination any of the 32 bits can be specified by a modulo 32 bit number When a memory location is the destination the operation is a byte operation and the bit number is modulo 8 In all cases bit zero refers to the least significant bit The bit number for this operation can be specified in tw
52. ADDRESS 0 0 0 0 REGISTER 1 0 1 MODE REGISTER BCLR Dynamic 15 14 13 12 11 10 9 8 7 6 4 3 2 1 0 EFFECTIVE ADDRESS 0 0 0 0 REGISTER 1 1 0 MODE REGISTER BSET Dynamic 15 14 13 12 11 10 9 8 7 6 4 3 2 1 0 EFFECTIVE ADDRESS 0 0 0 0 REGISTER 1 1 1 MODE REGISTER MOVEP 15 14 13 12 11 10 9 8 7 6 4 3 2 1 0 0 0 0 0 DATA REGISTER OPMODE 0 1 ADDR REGISTER DISPLACEMENT 16 BITS OPMODE FIELD 100 Transfer Word From Memory to Register 101 Transfer Long From Memory to Register 110 Transfer Word From Register to Memory 111 Transfer Word From Register to Memory ANDI 15 14 13 12 11 10 9 8 7 6 4 3 2 1 0 EFFECTIVE ADDRESS 0 0 0 0 0 0 1 0 SIZE MODE REGISTER WORD DATA 16 BITS LONG DATA 32 BITS BYTE DATA 8 BITS Size Field 00 Byte 01 Word 10 Long ANDI to CCR 15 13 102 10 9 8 7 6 4 3 2 1 0 0 0 0 0 0 0 1 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 BYTE DATA 8 BITS ANDI to SR 15 4 13 2 od 10 9 8 7 6 4 3 2 1 0 0 0 0 0 0 0 1 0 0 1 1 1 1 0 0 WORD DATA MOTOROLA INSTRUCTION SET CPU32 4 172 REFERENCE MANUAL SUBI 15 14 13 12 11 10 5 4 3 2 1 0 0 SIZE EFFECTIVE ADDRESS MODE REGISTER WORD DATA 16 BITS BYTE DATA 8 BITS LONG DATA 32 BITS Size Field 00 Byte 01 Word 10 Long ADDI 15 4 43 002001 1
53. ADDRESS 0 1 0 0 0 1 1 0 SIZE MODE REGISTER Instruction Fields Size field Specifies the size of the operation 00 Byte operation 01 Word operation 10 Long operation MOTOROLA INSTRUCTION SET CPU32 4 120 REFERENCE MANUAL NOT Logical Complement N OT Effective Address field Specifies the destination operand Only data alterable addressing modes are allowed as shown Addressing Mode Mode Register Addressing Mode Mode Register Dn 000 Reg number Dn xxx W 111 000 An xxx L 111 001 An 010 Reg number An data An 011 Reg number An An 100 Reg number An 96 An 101 Reg number An 96 PC dg An Xn 110 Reg number An dg PC Xn bd An Xn 110 Reg number An bd PC Xn CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4 121 OR Inclusive Logical OR OR Operation Source Destination Destination Assembler OR ea Dn Syntax OR Dn ea Attributes Size Byte Word Long Description Performs an inclusive OR operation on the source operand and the destination operand and stores the result in the destination location The contents of an address register may not be used as an operand Condition Codes X N 2 V i 0 0 X Not affected N Set if the most significant bit of the result is set Cleared otherwise Z Set if the result is zero Cleared otherwise
54. Access 5 4 5 3 1 3 Type 0010 Coprocessor Access 5 4 5 3 1 4 Type 0011 Internal Register Access 5 4 5 3 1 5 Type 1111 Interrupt Acknowledge 5 5 SECTION 6 EXCEPTION PROCESSING 6 1 Definition of Exception Processing 6 1 6 1 1 Exception Vectors rcm 6 1 6 1 2 Types of Exceptions 6 2 6 1 3 Exception Processing Sequence 4 4 24 1111 6 3 6 1 4 Exception Stack Frame 6 3 6 1 5 Multiple EXCODUOFIS bte ERE Oei 6 4 6 2 Processing of Specific Exceptions 6 5 6 2 1 AN 6 5 6 2 2 Bus OM iP mnnt 6 6 6 2 3 Address EITOE ioi eoe aer pdt 6 7 6 2 4 cde n En QR IE 6 8 6 2 5 Software Breakpolnls tea circle idonei es 6 8 6 2 6 Hardware 6 8 6 2 7 Format Errok 2025 tice on 6 9 6 2 8 Illegal or Unimplemented Instructions 6 9 6 2 9 Privilege Violation S
55. BDM the CPU32 ceases to fetch instructions via the parallel bus and communicates with the development system via a dedicated high speed SPlI type serial command interface CPU32 DEVELOPMENT SUPPORT MOTOROLA REFERENCE MANUAL 7 3 7 2 1 Enabling BDM Accidentally entering BDM in a non development environment could lock up the 32 since the serial command interface would probably not be available For this reason BDM is enabled during reset via the breakpoint BKPT signal BDM operation is enabled when BKPT is asserted low at the rising edge of RESET BDM remains enabled until the next system reset A high BKPT signal on the trailing edge of RESET disables BDM BKPT is relatched on each rising transition of RESET BKPT is synchronized internally and must be held low for at least two clock cycles pri or to negation of RESET BDM enable logic must be designed with special care If hold time on BKPT extends into the first bus cycle following reset the bus cycle could inadvertently be tagged with a breakpoint Refer to the system integration module user s manual for timing informa tion 7 2 2 BDM Sources When BDM is enabled any of several sources can cause the transition from normal mode to BDM These sources include external breakpoint hardware the BGND in struction a double bus fault and internal peripheral breakpoints If BDM is not enabled when an exception condition occurs the exception is processed norma
56. CAPABILITIES A summary of M68000 Family addressing modes is found in APPENDIX A M68000 FAMILY SUMMARY AO 0r ON 1 1 6 Instruction Set The instruction set of the CPU32 is very similar to that of the MC68020 see Table 1 1 Two new instructions have been added to facilitate controller applications low power stop LPSTOP and table lookup and interpolate TBL The following M68020 instructions are not implemented on the CPUS2 BFxxx Bit Field Instructions BFCHG BFCLR BFEXTS BFEXTU BFFFO BFINS BFSET BFTST CALLM RTM Call Module Return Module CAS CAS2 Compare and Set Read Modify Write Instructions cpxxx Coprocessor Instructions cpBcc cpDBcc cpGEN cp RESTORE CpSAVE cpScc PACK UNPK Pack Unpack BCD Instructions The CPU32 traps on unimplemented instructions and illegal effective addressing modes allowing the user to emulate instructions or to define special purpose func tions However Motorola reserves the right to use all currently uniplemented instruc tions operation codes for future M68000 core enhancements See SECTION 4 INSTRUCTION SET for comprehensive information 1 1 6 1 Table Lookup and Interpolation Instructions To speed up real time applications a range of discrete data points is often precalcu lated from a continuous control function then stored in memory A full range of data can require an inordinate amount of memory The table instructions make it possible
57. CMPM Compare Memory to Memory RTE Return from Exception CMP2 Compare Register Against RTR Return and Restore Codes Upper and Lower Bounds RTS Return from Subroutine DBcc Test Condition Decrement and SBCD Subtract Decimal with Extend Branch m Scc Set Conditionally DIVS DIVSL Signed Divide STOP Stop DIVU DIVUL Unsigned Divide SUB Subtract EOR Logical Exclusive OR SUBA Subtract Address EORI Logical Exclusive OR Immediate SUBI Subtract Immediate EXG Exchange Registers SUBQ Subtract Quick EXT EXTB Sign Extend SUBX Subtract with Extend LEA Load Effective Address SWAP Swap Register Words LINK Link and Allocate TBLS TBLSN Table Lookup and Interpolate LPSTOP Low Power Stop Signed LSL LSR Logical Shift Left and Right TBLU TBLUN Table Lookup and Interpolate ILLEGAL Take Illegal Instruction Trap Unsigned JMP Jump TAS Test Operand and Set JSR Jump to Subroutine TRAP Trap TRAPcc Trap Conditionally TRAPV Trap on Overflow TST Test Operand UNLK Unlink CPUS2 OVERVIEW MOTOROLA REFERENCE MANUAL 1 5 1 1 6 2 Low Power Stop Instruction The CPU32 is a fully static design Power consumption can be reduced to a minimum during periods of inactivity by stopping the system clock The CPUS2 instruction set includes a low power stop command LPSTOP that efficiently implements this capa bility The processor will remain in stop mode until a user specified interrupt or reset occurs 1 1 7 Processing States There are four processing states
58. Condition Code Register from CCR Operation CCR Destination Assembler Syntax MOVE CCR ea Attributes Size Word Description Moves the condition code bits zero extended to word size to the destination location Unimplemented bits are read as zeros Condition Codes Not affected Instruction Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EFFECTIVE ADDRESS MODE REGISTER Instruction Fields Effective Address field Specifies the destination location Only data alterable addressing modes are allowed as shown Addressing Mode Mode Register Addressing Mode Mode Register Dn 000 Reg number Dn xxx W 111 000 An xxx L 111 001 An 010 Reg number An data An 011 Reg number An An 100 Reg number An 416 101 Reg number dig PC dg An Xn 110 Reg number An dg PC Xn bd An Xn 110 Reg number An bd PC Xn NOTE MOVE from CCR is a word operation ANDI ORI and EORI to CCR are byte operations MOTOROLA INSTRUCTION SET CPU32 4 92 REFERENCE MANUAL MOVE Move to Condition Code Register MOVE to CCR to CCR Operation Source gt CCR Assembler Syntax MOVE ea CCR Attributes Size Word Description Moves the low order byte of the source operand to the condition code register The upper byte of the source operand is ignored the
59. Condition Codes X N U Set the same as the carry bit Undefined Cleared if the result is nonzero Un Undefined Set if a decimal carry was generat NOTE Normally the Z condition code bit is an operation This allows success of multiple precision operations O NZ X Instruction Format 15 14 13 12 10 1 110 0 REGISTER 1 Field 0 Data Register to Data Register 11 If R M 2 0 Rx and Ry are Data Registers If R M 1 Rx and Ry are Address Registers for t Instruction Fields Register Rx field Specifies the destin If R M 0 specifies a data register If R M 1 specifies an address regi R M field Specifies the operand addr 0 the operation is data register to 1 the operation is memory to me Register Ry field Specifies the sour If R M 0 specifies a data regis If R M 1 specifies an address Figure 4 2 Instruction Description Format MOTOROLA 4 14 INSTRUCTION SET CPU32 REFERENCE MANUAL A BC D Add Decimal with Extend A BC D Operation Source g Destination X Destination Assembler ABCD Dy Dx Syntax ABCD Ay Ax Attributes Size Byte Description Adds the source operand to the destination operand along with the extend bit and stores the result in the destination location The addition is performed using binary coded decimal arithmetic The operands
60. INSTRUCTION EXECUTION TIMING This section describes the instruction execution timing of the CPU32 External clock cycles are used to provide accurate execution and operation timing guidelines but not exact timing for every possible circumstance This approach is used because exact execution time for an instruction or operation depends on concurrency of independent ly scheduled resources on memory speeds and on other variables An assembly language programmer or compiler writer can use the information in this section to predict the performance of the CPU32 Additionally timing for exception processing is included so that designers of multitasking or real time systems can pre dict task switch overhead maximum interrupt latency and similar timing parameters Instruction timing is given in clock cycles to eliminate clock frequency dependency 8 1 Resource Scheduling The CPU32 contains several independently scheduled resources The organization of these resources within the CPU32 is shown in Figure 8 1 Some variation in instruc tion execution timing results from concurrent resource utilization Because resource scheduling is not directly related to instruction boundaries it is impossible to make an accurate prediction of the time required to complete an instruction without knowing the entire context within which the instruction is executing 8 1 1 Microsequencer The microsequencer either executes microinstructions or awaits completion o
61. MANUAL 8 5 The number of cycles for the instruction CN above can include one or two effective address calculations in addition to the raw number in the cycles column In these cas es calculate overall instruction time as if it were for multiple instructions using the fol lowing equation CEA min Hop Cop where CEA is the instruction s effective address time Cop is the instruction s operation time Hop is the instruction operation s head time TEA is the effective address s tail time min TN HM is the minimum of parameters TN and HM The overall head for the instruction is the head for the effective address and the over all tail for the instruction is the tail for the operation Therefore the actual equation for execution time becomes Cop1 min HEA2 Hopo Cop2 min Tope HEA3 Every instruction must prefetch to replace itself in the instruction pipe Usually these prefetches occur during or after an instruction A prefetch is permitted to begin in the first clock of any indexed effective addressing mode operation Additionally a prefetch for an instruction is permitted to begin two clocks before the end of an instruction provided the bus is not being used If the bus is being used then the prefetch occurs at the next available time when the bus would otherwise be idle 8 1 7 Effects of Negative Tails When the CPU32 changes instruction flow the
62. MOVEQ 1000 OR DIV SBCD 1001 SUB SUBX 1010 Unassigned Reserved 1011 CMP EOR 1100 AND MUL ABCD EXG 1101 ADD ADDX 1110 Shift Rotate Bit Field 1111 Table Lookup and Interpolation MOTOROLA INSTRUCTION SET CPU32 4 170 REFERENCE MANUAL ORI 15 14 13 12 11 10 9 8 7 4 3 2 1 0 EFFECTIVE ADDRESS 0 0 0 0 0 0 0 0 SIZE MODE REGISTER WORD DATA 16 BITS BYTE DATA 8 BITS LONG DATA 32 BITS Size Field 00 Byte 01 Word 10 Long ORI to CCR 15 14 13 12 11 10 9 8 7 4 3 2 1 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 BYTE DATA 8 BITS ORI to SR 15 14 13 12 11 10 9 8 7 4 3 2 1 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 WORD DATA Size Field 00 Byte 01 Word 10 Long CHK2 15 14 13 12 11 10 9 8 7 4 3 2 1 0 EFFECTIVE ADDRESS 0 0 0 0 0 SIZE 0 1 MODE REGISTER D A REGISTER 1 0 0 0 0 0 0 0 0 0 Size Field 00 Byte 01 Word 10 Long BTST Dynamic 15 14 13 12 11 10 9 8 7 4 3 2 1 0 EFFECTIVE ADDRESS 0 0 0 0 REGISTER 1 0 MODE REGISTER CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4 171 BCHG Dynamic 15 14 13 12 11 10 9 8 7 6 4 3 2 1 0 EFFECTIVE
63. Reg number dig PC 111 010 dg An Xn 110 Reg number An dg PC Xn 111 011 bd An Xn 110 Reg number An bd PC Xn 111 011 NOTE Overflow occurs if the quotient is larger than a 16 bit signed integer MOTOROLA INSTRUCTION SET CPU32 4 70 REFERENCE MANUAL DIVU Unsigned Divide DIVU DIVUL DIVUL Instruction Format long form 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EFFECTIVE ADDRESS 0 1 0 0 1 1 0 0 0 1 MODE REGISTER 0 REGISTER Dq 1 SIZE 0 0 0 0 0 0 0 REGISTER Dr Instruction Fields Effective Address field Specifies the source operand Only data addressing modes are allowed as shown Addressing Mode Mode Register Addressing Mode Mode Register Dn 000 Reg number Dn xxx W 111 000 An xxx L 111 001 An 010 Reg number An data 111 100 An 011 Reg number An An 100 Reg number An 416 101 Reg number dig PC 111 010 dg An Xn 110 Reg number An dg PC Xn 111 011 bd An Xn 110 Reg number An bd PC Xn 111 011 Register Dq field Specifies a data register for the destination operand The low order 32 bits of the dividend come from this register and the 32 bit quotient is loaded into this register Size field Selects a 32 or 64 bit division operation 0 32 bit dividend is in Register Dq 1 64 bit dividend is in Dr Dq Register Dr field
64. Set if a borrow is generated Cleared otherwise Instruction Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 1 1 REGISTER Ax 1 SIZE 0 0 1 REGISTER Ay Instruction Fields Register Ax field always the destination Specifies an address register in the postincrement addressing mode Size field Specifies the size of the operation 00 Byte operation 01 Word operation 10 Long operation Register Ay field always the source Specifies an address register in the postin crement addressing mode CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4 61 2 Compare Register Against Bounds 2 Operation Compare Rn lower bound or Rn gt upper bound and Set Condition Codes Assembler Syntax CMP2 ea Rn Attributes Size Byte Word Long Description Compares the value in Rn to each bound The effective address contains the bounds pair the lower bound followed by the upper bound For signed comparisons the arithmetically smaller value should be used as the lower bound For unsigned comparisons the logically smaller value should be the lower bound The size of the data and the bounds can be specified as byte word or long If Rn is a data register and the operation size is byte or word only the appropriate low order part of Rn is checked If Rn is an address register and the operation size is byte or word the bounds operands are sign extended to 32 bits
65. Size Byte Word Long Description Subtracts the destination operand from zero and stores the result in the destination location Condition Codes X N 7 V X Set the same as the carry bit N Set if the result is negative Cleared otherwise Z Set if the result is zero Cleared otherwise V Set if an overflow occurs Cleared otherwise Cleared if the result is zero Set otherwise Instruction Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EFFECTIVE ADDRESS 0 1 0 0 0 1 0 0 SIZE MODE REGISTER Instruction Fields Size field Specifies the size of the operation 00 Byte operation 01 Word operation 10 Long operation CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4 115 N EG Negate N EG Effective Address field Specifies the destination operand Only data alterable addressing modes are allowed as shown Addressing Mode Mode Register Addressing Mode Mode Register Dn 000 Reg number Dn xxx W 111 000 An xxx L 111 001 An 010 Reg number An data An 011 Reg number An An 100 Reg number An 96 An 101 Reg number An 96 PC dg An Xn 110 Reg number An dg PC Xn bd An Xn 110 Reg number An bd PC Xn MOTOROLA INSTRUCTION SET CPU32 4 116 REFERENCE MANUAL N EGX Negate with Extend N EGX Operation 0 Destination X Destination A
66. TIMING MOTOROLA REFERENCE MANUAL 8 11 8 3 1 Fetch Effective Address The fetch effective address table indicates the number of clock periods needed for the processor to calculate and fetch the specified effective address The total number of clock cycles is outside the parentheses The numbers inside parentheses r p w are included in the total clock cycle number All timing data assumes two clock reads and writes Instruction Head Tail Cycles Notes Dn 0 0 0 0 0 0 0 0 1 1 3 X 0 0 1 An 1 1 3 X 0 0 1 An 2 2 4 X 0 0 1 d16 An or 96 1 3 5 X 1 0 1 3 xxx W 1 3 5 X 1 0 1 xxx L 1 5 7 X 2 0 1 data B 1 1 3 0 1 0 1 data W 1 1 3 0 1 0 1 data L 1 3 5 0 2 0 1 dg An Xn Sz Sc or dg PC Xn Sz Sc 4 2 8 X 1 0 1 2 3 4 0 All Suppressed 2 2 6 X 1 0 1 4 d16 1 3 7 X 2 0 1 4 d32 1 5 9 X 3 0 1 4 An 1 1 5 X 1 0 1 2 4 Xm Sz Sc 4 2 8 X 1 0 1 2 4 An Xm Sz Sc 4 2 8 X 1 0 1 2 3 4 d16 An or 96 1 3 7 X 2 0 1 3 4 d32 An or d32 PC 1 5 9 X 3 0 1 3 4 d46 An Xm or d46 PC Xm 2 2 8 X 2 0 1 3 4 d32 An Xm or d32 PC Xm 1 3 9 X 3 0 1 3 4 dig An Xm Sz Sc or dig PC Xm Sz Sc 2 2 8 X 2 0 1 2 3 4 d32 An Xm Sz Sc or dao PC Xm Sz Sc 1 3 9 X 3 0 1 2 3 4 X There is one bus cycle for byte and word operands and two bus cycles for long operands For long bus cycles
67. The CPU32 uses in struction restart which requires that only a small portion of the internal machine state be saved After correcting the fault the machine state is restored and the instruction is refetched and restarted This process is completely transparent to the application program 1 1 2 Loop Mode Instruction Execution The CPU32 has several features that provide efficient execution of program loops One of these features is the DBcc looping primitive To increase the performance of the CPU32 a loop mode has been added to the processor The loop mode is used by any single word instruction that does not change the program flow Loop mode is im plemented in conjunction with the DBcc instruction Figure 1 1 shows the required form of an instruction loop for the processor to enter loop mode Loop mode is entered when DBcc is executed and loop displacement is 4 Once in loop mode the processor performs only data cycles associated with the instruction and suppresses instruction fetches Termination condition and count are checked after each execution of looped instruction data operations The CPU automatically exits loop mode for interrupts or other exceptions MOTOROLA OVERVIEW CPU32 1 2 REFERENCE MANUAL ONE WORD INSTRUCTION DBcc DBcc DISPLACEMENT FFFC 4 Figure 1 1 Loop Mode Instruction Sequence 1 1 3 Vector Base Register The vector base register VBR contains the base address of the 1024 byte excep
68. UNAFFECTED UNAFFECTED RESULT RESULT LONG RESULT RESULT RESULT RESULT If R 21 TBLSN the result is returned in register Dx without rounding If the size is byte the integer portion of the result is returned in Dx 15 8 The integer portion of a word result is stored in Dx 23 8 The least significant 24 bits of a long result are stored in Dx 31 8 Byte and word results are sign extended to fill the entire 32 bit register 31 24 23 16 15 8 7 0 BYTE SIGN EXTENDED SIGN EXTENDED RESULT FRACTION WORD SIGN EXTENDED RESULT RESULT FRACTION LONG RESULT RESULT RESULT FRACTION NOTE A long word result contains only the least significant 24 bits of integer precision CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4 155 TB LS Table Lookup and Interpolate Signed TB LS TBLSN TBLSN For all sizes the 8 bit fractional portion of the result is returned in the low byte of the data register Dx 7 0 User software can make use of the fractional data to reduce cumulative errors in lengthy calculations or implement rounding algorithms different from those provided by other forms of TBLS The assumed radix point described pre viously places two restrictions on the programmer 1 Tables are limited to 257 entries in length 2 Interpolation resolution is limited to 1 256 the distance between consecutive table entries The assumed radix point should not however be construed by the programmer as a requirement that the independent va
69. Vector CPU32 REFERENCE MANUAL Immediate data from an instruction Destination contents Source contents Location of exception vector Any address register A7 to 0 Address registers used in computation Any data register D7 to DO Control register VBR SFC DFC Any address or data register Data registers high and low order 32 bits of product Data registers division remainder division quotient Data registers used in computation Data registers table interpolation values Index register Address extension Condition code Displacement Example d16 is a 16 bit displacement Effective address Immediate data a literal integer Assembly program label List of registers Example D3 DO Bits of an operand Examples 7 is bit 7 31 24 are bits 31 to 24 Contents of a referenced location Example Rn refers to the contents of Rn MOTOROLA 4 8 INSTRUCTION SET CCR Condition code register lower byte of status register X extend bit N negative bit Z zero bit V overflow bit C carry bit PC Program counter SP Active stack pointer SR Status register SSP Supervisor stack pointer USP User stack pointer FC Function code DFC Destination function code register SFC Source function code register Addition or post increment Subtraction or predecrement Division or conjunction Multiplication Equal to Not equal to gt Greater than gt Greater than or equal to lt Less than lt L
70. W 111 000 An xxx L 111 001 An 010 Reg number An data 111 100 An 011 Reg number An An 100 Reg number An 416 101 Reg number dig PC 111 010 dg An Xn 110 Reg number An dg PC Xn 111 011 bd An Xn 110 Reg number An bd PC Xn 111 011 MOTOROLA INSTRUCTION SET CPU32 4 108 REFERENCE MANUAL M U LS Signed Multiply M U LS Instruction Format long form 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EFFECTIVE ADDRESS 0 1 0 0 1 1 0 0 0 0 MODE REGISTER 0 REGISTER DI 1 SIZE 0 0 0 0 0 0 0 REGISTER Dh Instruction Fields Effective Address field Specifies the source operand Only data addressing modes are allowed as shown Addressing Mode Mode Register Addressing Mode Mode Register Dn 000 Reg number Dn xxx W 111 000 An xxx L 111 001 An 010 Reg number An data 111 100 An 011 Reg number An An 100 Reg number An 416 101 Reg number dig PC 111 010 dg An Xn 110 Reg number An dg PC Xn 111 011 bd An Xn 110 Reg number An bd PC Xn 111 011 Register DI field Specifies a data register for the destination operand The 32 bit multiplicand comes from this register and the low order 32 bits of the product are loaded into this register Size field Selects a 32 or 64 bit product 0 32 bit product to be returned t
71. a long word operand A register operand is the low order word the upper word of the register is ignored All 32 bits of the product are saved in the destina tion data register In the long form the multiplier and multiplicand are both long word operands and the result is either a long word or a quad word The long word result is the low order 32 bits of the quad word result the high order 32 bits of the product are dis carded Condition Codes X N Z V C X Not affected N Set if the result is negative Cleared otherwise Z Set if the result is zero Cleared otherwise V Set if overflow Cleared otherwise C Always cleared NOTE Overflow V 1 can occur only when multiplying 32 bit operands to yield a 32 bit result Overflow occurs if the high order 32 bits of the quad word product are not the sign extension of the low order 32 bits CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4 107 M U LS Signed Multiply M U LS Instruction Format word form 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EFFECTIVE ADDRESS 1 1 0 0 REGISTER 1 1 1 MODE REGISTER Instruction Fields Register field Specifies a data register as the destination Effective Address field Specifies the source operand Only data addressing modes are allowed as shown Addressing Mode Mode Register Addressing Mode Mode Register Dn 000 Reg number Dn xxx
72. add two clocks to the tail and to the number of cycles NOTES 1 The read of the effective address and replacement fetches overlap the head of the operation by the amount specified in the tail 2 Size and scale of the index register do not affect execution time 3 The program counter may be substituted for the base address register An 4 When adjusting the prefetch time for slower buses extra clocks may be subtracted from the head until the head reaches zero at which time additional clocks must be added to both the tail and cycle counts MOTOROLA INSTRUCTION EXECUTION TIMING CPU32 8 12 REFERENCE MANUAL 8 3 2 Calculate Effective Address The calculate effective address table indicates the number of clock periods needed for the processor to calculate a specified effective address The timing is equivalent to fetch effective address except there is no read cycle The tail and cycle time are re duced by the amount of time the read would occupy The total number of clock cycles is outside the parentheses The numbers inside parentheses r p w are included in the total clock cycle number All timing data assumes two clock reads and writes Instruction Head Tail Cycles Notes Dn 0 0 0 0 T An 0 0 0 0 An 1 0 2 0 0 0 An 1 0 2 0 0 0 2 0 2 0 0 0 d16 An 046 1 1 3 0 1 0 1 3 xxx W 1 1 3 0 1 0 1 xxx L 1 3 5 0 2 0 1
73. an integrated debugger supports use of a bus state analyzer BSA for in circuit emulation The processor remains in the target system see Figure 7 2 and the CPU32 DEVELOPMENT SUPPORT MOTOROLA REFERENCE MANUAL 7 1 interface is simplified The BSA monitors target processor operation and the on chip debugger controls the operating environment Emulation is much closer to target hardware and many interfacing problems i e limitations on high frequency opera tion AC and DC parametric mismatches and restrictions on cable length are mini mized TARGET SYSTEM IN CIRCUIT EMULATOR lt TARGET MCU Figure 7 1 In Circuit Emulator Configuration TARGET SYSTEM nooo nooo BUS STATE ANALYZER TARGET MCU Figure 7 2 Bus State Analyzer Configuration 7 1 2 Deterministic Opcode Tracking Overview CPU32 function code outputs are augmented by two supplementary signals that mon itor the instruction pipeline The instruction fetch IFETCH output identifies bus cycles in which data is loaded into the pipeline and signals pipeline flushes The instruction pipe IPIPE output indicates when each mid instruction pipeline advance occurs and when instruction execution begins These signals allow a BSA
74. and the resultant operands are compared to the full 32 bits of An If the upper bound equals the lower bound the valid range is a single value NOTE This instruction is identical to CHK2 except that it sets condition codes rather than taking an exception when the value in Rn is out of bounds Condition Codes x N 7 V C U U X Not affected N Undefined Z Set if Rn is equal to either bound Cleared otherwise V Undefined C Set if Rn is out of bounds Cleared otherwise Instruction Format 15 14 18 12 11 10 9 8 6 5 4 3 2 1 0 EFFECTIVE ADDRESS 0 0 0 0 0 SIZE 0 1 1 MODE REGISTER D A REGISTER 0 0 0 0 0 0 0 0 0 0 0 0 MOTOROLA INSTRUCTION SET CPU32 4 62 REFERENCE MANUAL CMP2 Instruction Fields Compare Register Against Bounds Size field Specifies the size of the operation 00 Byte operation 01 Word operation 10 Long operation Effective Address field Specifies the location of the bounds pair Only control addressing modes are allowed as shown CMP2 Addressing Mode Mode Register Addressing Mode Mode Register Dn xxx W 111 000 An xxx L 111 001 An 010 Reg number An data An An 416 101 Reg number dig PC 111 010 dg An Xn 110 Reg number An dg PC Xn 111 011 bd An Xn 110 Reg number
75. and the sized scaled and sign extended index operand The val ue in the program counter is the address of the extension word This reference is a program space reference and is only allowed for reads The user must include the dis placement the program counter and the index register when specifying this address ing mode CPU32 DATA ORGANIZATION AND ADDRESSING CAPABILITIES MOTOROLA REFERENCE MANUAL 3 7 3 4 3 3 Program Counter Indirect with Index Base Displacement This mode is similar to the address register indirect with index base displacement mode described in 3 4 2 6 Address Register Indirect With Index Base Displace ment but the program counter is used as the base register It requires an index reg ister indicator and an optional 16 or 32 bit sign extended base displacement The operand is in memory The address of the operand is the sum of the contents of the program counter the scaled contents of the sign extended index register and the base displacement The value of the program counter is the address of the first exten sion word The reference is a program space reference and is only allowed for read accesses In this mode the program counter the index register and the displacement are all op tional However the user must supply the assembler notation ZPC zero value is tak en for the program counter to indicate that the program counter is not used This scheme allows the user to access the program space witho
76. appropriate table to cal culate that portion of the instruction time Destination effective addresses are divided by their formats refer to 3 4 4 Effective Address Encoding Summary The total number of clock cycles is outside the paren theses The numbers inside parentheses r p w are included in the total clock cycle number All timing data assumes two clock reads and writes When using this table begin at the top and move downward Use the first entry that matches both source and destination addressing modes Instruction Head Tail Cycles MOVE Rn Rn 0 0 2 0 1 0 MOVE FEA Rn 0 0 2 0 1 0 MOVE Rn Am 0 2 4 0 1 x MOVE Rn Am 1 1 5 0 1 x MOVE Rn Am 2 2 6 0 1 x MOVE Rn CEA 1 3 5 0 1 x MOVE FEA An 2 2 6 0 1 x MOVE FEA An 2 2 6 0 1 x MOVE FEA 2 2 6 0 1 x MOVE CEA 2 2 6 0 1 x MOVE CEA FEA 2 2 6 0 1 x X There is one bus cycle for byte and word operands and two bus cycles for long operands For long bus cycles add two clocks to the tail and to the number of cycles An fetch effective address time must be added for this instruction FEA CEA OPER NOTE For instructions not explicitly listed use the MOVE CEA FEA entry The source effective address is calculated by the calculate effective address table and the destination effective address is calculated by the fetch effective address table even though the bus cycle
77. by an operating system CPU32 EXCEPTION PROCESSING MOTOROLA REFERENCE MANUAL 6 1 Table 6 1 Exception Vector Assignments Vector Vector Offset Assignment Number Dec Hex Space 0 0 000 SP Reset Initial Stack Pointer 1 4 004 SP Reset Initial Program Counter 2 8 008 SD Bus Error 3 12 00C SD Address Error 4 16 010 SD Illegal Instruction 5 20 014 SD Zero Division 6 24 018 SD CHK Instructions 7 28 01C SD TRAPcc Instructions 8 32 020 SD Privilege Violation 9 36 024 SD Trace 10 40 028 SD Line 1010 Emulator 11 44 02C SD Line 1111 Emulator 12 48 030 SD Hardware Breakpoint 13 52 034 SD Reserved Coprocessor Protocol Violation 14 56 038 SD Format Error and Uninitialized Interrupt 15 60 03C SD Format Error and Uninitialized Interrupt 16 23 2 sp Unassigned Reserved 96 SD Spurious Interrupt SD Level 1 Interrupt Autovector SD Level 2 Interrupt Autovector SD Level 3 Interrupt Autovector Level 4 Interrupt Autovector Level 5 Interrupt Autovector Level 6 Interrupt Autovector Level 7 Interrupt Autovector Trap Instruction Vectors 0 15 Reserved Coprocessor Unassigned Reserved User Defined Vectors 192 Each vector is assigned an 8 bit number Vector numbers for some exceptions are ob tained from an external device others are supplied by the processor The processor multiplies the vector number by four to calculate vector offset then adds the offset to t
78. by mul tiplying by the interpolation fraction Dx 7 0 The adjusted difference is then added to the selected table entry The result is returned in the destination data register Dx For register interpolate mode the interpolation occurs using the Dym and Dyn regis ters in place of the two table entries For this mode only the fractional portion Dx 7 0 is used in the interpolation and the integer portion Dx 15 8 is ignored The register interpolation mode may be used with several table lookup and interpolations to model multidimensional functions MOTOROLA INSTRUCTION SET CPU32 4 154 REFERENCE MANUAL TBLS TBLSN Table Lookup and Interpolate Signed TBLS TBLSN Signed table entries range from 2 7 to 2 7 1 where nis 8 16 or 32 for byte word and long word tables respectively Rounding of the result is optionally selected via the R instruction field If R 0 TBLS the fractional portion is rounded according to the round to nearest algorithm The rounding procedure can be summarized by the following table Adjusted Difference Fraction Rounding Adjustment n lt 1 n j 0 gt 1 The adjusted difference is then added to the selected table entry The rounded result is returned in the destination data register Dx Only the portion of the register corre sponding to the selected size is affected 31 24 23 16 15 8 7 0 BYTE UNAFFECTED UNAFFECTED UNAFFECTED RESULT WORD
79. conditions Code 0100 0101 0111 0001 GE Greater or Equal 1100 GT Greater Than HI High LE Less or Equal Condition Codes Not affected MOTOROLA 4 64 1110 0010 1111 Description cc Name LS Low or Same LT Less Than Z MI Minus 0 Not Equal q N e V N eV PL Plus NeVeZiNeVeZ T Always true C eZ gt Overflow Clear 2 Z N eV N eV S Overflow Set INSTRUCTION SET Code 0011 1101 1011 0110 1010 0000 1000 1001 Description C Z N eV N eV N 7 lt l CPU32 REFERENCE MANUAL D Bcc Test Condition Decrement and Branch D Bcc Instruction Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 0 1 CONDITION 1 1 0 0 1 REGISTER DISPLACEMENT Instruction Fields Condition field The binary code for one of the conditions listed in the table Register field Specifies the data register used as the counter Displacement field Specifies the number of bytes to branch NOTES 1 Terminating condition is similar to UNTIL loop clauses of high level languages For example DBMI can be stated decrement and branch until minus 2 Most assemblers accept DBRA for DBF when a count terminates the loop no condition is tested 3 A program can enter a loop at the beginning or by branching to the trailing DBcc instruction Entering the loop at the beginning is useful for indexed ad dressing modes and dynamically specified bit operations In
80. cycle at the slower speed OLD TAIL OLD CYCLE is the value listed in the instruction timing tables NEW CLOCK is the number of clocks per cycle at the slower speed Note that many instructions listed as having negative tails are change of flow instruc tions and that the bus speed used in the calculation is that of the new instruction stream 8 2 Instruction Stream Timing Examples The following programming examples provide a detailed examination of timing effects In all examples memory access is either from internal two clock memory or from ex ternal synchronous memory the bus is idle and the instruction pipeline is full at start 8 2 1 Timing Example 1 Execution Overlap Figure 8 4 illustrates execution overlap caused by the bus controller s completion of bus cycles while the sequencer is calculating the next effective address One clock is saved between instructions as that is the minimum time of the individual head and tail numbers Instructions MOVE WA 0 ADDQ W 1 A0 CLR W 30 A1 BUS WRITE 1 PRE READ WRITE 2 PRE 3 PRE 3 PRE WRITE CONTROLLER FOR 1 FETCH FOR2 FOR2 FETCH FETCH FETCH FOR3 EA FETCH ADDQ EA Pres CLR MOVE W 1 ADDQ W 1 AO CLR W 30 A1 INSTRUCTION CONTROLLER EXECUTION TIME Figure 8 4 Example 1 Instruction Stream CPU32 INSTRUCTION EXECUTION TIMING MOTOROLA REFERENCE MANUAL 8 7 8 2 2 Timing Example 2 Branch Instructions Example 2 shows what happens w
81. data 111 100 An 011 Reg number An An 100 Reg number An 416 An 101 Reg number An dig PC 111 010 dg An Xn 110 Reg number An dg PC Xn 111 011 bd An Xn 110 Reg number An bd PC Xn 111 011 MOTOROLA INSTRUCTION SET CPU32 4 58 REFERENCE MANUAL CMPI Compare Immediate CMPI Operation Destination Immediate Data cc Assembler Syntax CMPI data ea Attributes Size Byte Word Long Description Subtracts the immediate data from the destination operand and sets condition codes according to the result The destination location is not changed The size of the immediate data must match the operation size Condition Codes X N 7 V X Not affected N Set if the result is negative Cleared otherwise Z Set if the result is zero Cleared otherwise V Set if an overflow occurs Cleared otherwise C Set if a borrow occurs Cleared otherwise Instruction Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EFFECTIVE ADDRESS 0 0 0 0 1 1 0 0 SIZE MODE REGISTER WORD DATA 16 BITS BYTE DATA 8 BITS LONG DATA 32 BITS Instruction Fields Size field Specifies the size of the operation 00 Byte operation 01 Word operation 10 Long operation CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4 59 CMPI Compare Immediate modes except immediate are allowed as shown CMPI Effective Address field Specif
82. fractional number in the range 0 lt X lt 255 On the contrary X should be con sidered to be an integer in the range 0 lt X lt 65535 realizing that the table is actually a compressed linear representation of a function in which only every 256th value is actually stored in memory See 4 6 Table Lookup and Interpolation Instructions for more information on the TBLU TBLUN instruction Condition Codes X N 2 V 0 X Not affected N Set if the most significant bit of the result is set Cleared otherwise Z Set if the result is zero Cleared otherwise V Set if the integer portion of an unrounded long result is not in the 0 lt Result lt 224 1 Cleared otherwise Always cleared Instruction Format Table Lookup and Interpolate 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EFFECTIVE ADDRESS 1 1 1 1 1 0 0 0 0 0 MODE REGISTER 0 REGISTER Dx 0 R 0 1 SIZE 0 0 0 0 0 0 MOTOROLA INSTRUCTION SET CPU32 4 160 REFERENCE MANUAL TB L U Table Lookup and Interpolate Unsigned TB L U TBLUN TBLUN Data Register Interpolate 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 0 0 0 0 0 0 0 0 REGISTER Dym 0 REGISTER Dx 0 R 0 0 SIZE 0 0 0 REGISTER Dyn Instruction Fields Effective address field table lookup and interpolate mode only Specifies the source location Only control addr
83. frame contains six words the program counter of the instruction that caused the initial exception is also stacked This data is placed on the stack in the format shown in Figure 6 4 The return address from the initial excep tion is stacked for RTE 6 3 2 Correcting a Fault Fault correction methods are discussed in the following paragraphs There are two ways to complete a faulted released write bus cycle The first is to use a software handler The second is to rerun the bus cycle via RTE Type II fault handlers must terminate with RTE but specific requirements must also be met before an instruction is restarted MOTOROLA EXCEPTION PROCESSING CPU32 6 18 REFERENCE MANUAL There are three varieties of Type operand fault recovery The first is completion of an instruction in software The second is conversion to Type II with restart via RTE The third is continuation from the fault via RTE 6 3 2 1 Type Completing Released Writes via Software To complete a bus cycle in software a handler must first read the SSW function code field to determine the appropriate address space then access the fault address point er on the stack and then transfer data from the stacked image of the output buffer to the fault address Because the CPU32 has a 16 bit internal data bus long operands require two bus ac cesses A fault during the second access of a long operand causes the LG bit in the SSW to be set The SIZ field indicates remaining
84. inhibit prefetch requests when a change in instruction flow e g a jump or branch instruction is anticipated In a typical program 10 to 25 percent of the instructions causes a change of flow Each time a change occurs the instruction pipeline must be flushed and refilled from the new instruction stream If instruction prefetches rather than operand accesses were given priority many instruction words would be flushed unused and necessary oper and cycles would be delayed To maximize available bus bandwidth the CPU32 will schedule a prefetch only when the next instruction is not a change of flow instruction and when there is room in the pipeline for the prefetch 8 1 3 2 Write Pending Buffer The CPU32 incorporates a single operand write pending buffer The buffer permits the microsequencer to continue execution after a request for a write cycle is queued in the bus controller The time needed for a write at the end of an instruction can overlap the head cycle time for the following instruction and thus reduce overall execution time Interlocks prevent the microsequencer from overwriting the buffer 8 1 3 3 Microbus Controller The microbus controller performs bus cycles issued by the microsequencer Operand accesses always have priority over instruction prefetches Word and byte operands are accessed in a single CPU initiated bus cycle although the external bus interface may be required to initiate a second cycle when a word operand is
85. instruction decode pipeline must begin refilling before instruction execution can resume Refilling forces a two clock idle peri od at the end of the change of flow instruction This idle period can be used to prefetch an additional word on the new instruction path Because of the stipulation that each instruction must prefetch to replace itself the con cept of negative tails has been introduced to account for these free clocks on the bus On a two clock bus it is not necessary to adjust instruction timing to account for the potential extra prefetch The cycle times of the microsequencer and bus are matched and no additional benefit or penalty is obtained In the instruction execution time equa tions a zero should be used instead of a negative number Negative tails are used to adjust for slower fetches on slower buses Normally in creasing the length of prefetch bus cycles directly affects the cycle count and tail val ues found in the tables MOTOROLA INSTRUCTION EXECUTION TIMING CPU32 8 6 REFERENCE MANUAL In the following equations negative tail values are used to negate the effects of a slow er bus The equations are generalized however so that they may be used on any speed bus with any tail value NEW_TAIL OLD_TAIL NEW CLOCK 2 IF NEW_CLOCK 4 gt 0 THEN NEW CYCLE OLD CYCLE NEW CLOCK 2 NEW CLOCK 4 ELSE NEW CYCLE OLD CYCLE NEW CLOCK 2 where NEW TAIL NEW CYCLE is the adjusted tail
86. is obtained For interrupts the number is fetched ROM CPU space F the bus cycle is an interrupt acknowledge For all other excep tions internal logic provides a vector number Next current processor status is saved An exception stack frame is created and placed on the supervisor stack All stack frames contain copies of the status regis ter and the program counter for use by RTE The type of exception and the context in which the exception occurs determine what other information is stored in the stack frame Finally the processor prepares to resume normal execution of instructions The ex ception vector offset is determined by multiplying the vector number by four and the offset is added to the contents of the VBR to determine displacement into the exception vector table The exception vector is loaded into the program counter If no other exception is pending the processor will resume normal execution at the new address in the PC 6 1 4 Exception Stack Frame During exception processing the most volatile portion of the current context is saved on the top of the supervisor stack This context is organized in a format called the ex ception stack frame The exception stack frame always includes the contents of status register and pro gram counter at the time the exception occurred To support generic handlers the pro cessor also places the vector offset in the exception stack frame and marks the frame with a format code The form
87. item is the address of the most significant byte of the high order word The address of the most significant byte of the low order word is N 2 and the address of the least significant byte of the long word is 3 The CPU32 requires data words and long words as well as instruction words to be aligned on word boundaries Data misalignment is not support ed Figure 2 6 shows how operands and instructions are organized in memory Note that N X is below N that is address value increases as one moves down the page MOTOROLA ARCHITECTURE SUMMARY CPU32 2 6 REFERENCE MANUAL BIT DATA 1 BYTE 8 BITS 7 6 5 4 3 2 1 0 BYTE DATA 8 BITS 15 8 7 0 MSB BYTEO LSB BYTE 1 BYTE2 BYTES WORD DATA INSTRUCTION 16 BITS LONG WORD DATA INSTRUCTION 82 BITS HIGH ORDER LOW ORDER ADDRESS 82 BITS HIGH ORDER LOW ORDER MSB Most Significant Bit LSB Least Significant Bit DECIMAL DATA 2 BCD DIGITS 1 BYTE 15 12 11 8 7 43 0 BCDO BCD1 150 BCD 3 MSD Most Significant Digit LSD Least Significant Digit Figure 2 6 Memory Operand Addressing CPU32 ARCHITECTURE SUMMARY MOTOROLA REFERENCE MANUAL 2 7 MOTOROLA ARCHITECTURE SUMMARY CPU32 2 8 REFERENCE MANUAL SECTION 3 DATA ORGANIZATION AND ADDRESSING CAPABILITIES The addressing mode of an instruction can specify the value of an operand an imme diate operand a register that contains the operand register direct addressing mode or how
88. loads the updated stack pointer into the address register Finally adds the dis placement value to the stack pointer For word size operation the displacement is the sign extended word following the operation word For long size operation the dis placement is the long word following the operation word The address register occu pies one long word on the stack The user should specify a negative displacement to allocate stack area Condition Codes Not affected Instruction Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 0 0 1 1 1 0 0 1 0 1 0 REGISTER WORD DISPLACEMENT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 0 0 1 0 0 0 0 0 0 0 1 REGISTER HIGH ORDER DISPLACEMENT LOW ORDER DISPLACEMENT Instruction Fields Register field Specifies the address register for the link Displacement field Specifies the twos complement integer to be added to the stack pointer NOTE LINK and UNLK can be used to maintain a linked list of local data and parameter areas on the stack for nested subroutine calls MOTOROLA INSTRUCTION SET CPU32 4 84 REFERENCE MANUAL L PSTO Low Power Stop L PSTO P Operation If supervisor state then Immediate Data gt SR Interrupt Mask External Bus Interface EBI STOP else TRAP Assembler Syntax LPSTOP data Attributes Size Word Privileged Description The immediate operand is moved into th
89. m X An with Predecrement Address Register Indirect 101 reg no X X X X d16 An with Displacement Address Register Indirect 110 reg no X X X X dg An Xn with Index 8 Bit Displacement Address Register Indirect 110 reg no X X X X bd An Xn with Index Base Displacement Absolute Short 111 000 X X X X xxx W Absolute Long 111 001 X X X X xxx L Program Counter Indirect 111 010 X X X dig PC with Displacement Program Counter Indirect 111 011 X X X dg PC Xn with Index 8 Bit Displacement Program Counter Indirect with Index Base Displacement Immediate 111 100 X X data 3 5 1 Addressing Capabilities In the CPU32 setting the base register suppress BS bit in the full format extension word see Figure 3 2 suppresses use of the base address register in calculating the EA allowing any index register to be used in place of the base register Because any data register can be an index register this provides a data register indirect form Dn This mode could also be called register indirect Rn because either a data register or an address register can be used to address memory an extension of M68000 Fam ily addressing capability The ability to specify the size and scale of an index register Xn SIZE SCALE in these modes provides additional addressing flexibility When using the SIZE parame ter either the entire contents of the index register can be used or the leas
90. operand size If operand coherency is important the complete operand must be rewritten After a long operand is rewritten the RR bit must be cleared Failure to clear the RR bit can cause RTE to rerun the bus cycle Following rewrite it is not necessary to adjust the program counter or other stack contents before executing RTE 6 3 2 2 Type 1 Completing Released Writes via RTE An exception handler can use the RTE instruction to complete a faulted bus cycle When RTE executes the fault address data output buffer program counter and sta tus register are restored from the stack Any pending breakpoint or trace exceptions as indicated by TR B1 and BO in the stacked SSW are requeued during SSW resto ration The RR bit in the SSW is checked during the unstacking operation if it is set the RW FUNC and SIZ fields are restored and the released write cycle is rerun To maintain long word operand coherence stack contents must be adjusted prior to RTE execution The fault address must be decremented by two if LG is set and SIZ indicates a remaining byte or word SIZ must be set to long All other fields should be left unchanged The bus controller uses the modified fault address and SIZ field to re run the complete released write cycle Manipulating the stacked SSW can cause unpredictable results because RTE checks only the RR bit to determine if a bus cycle must be rerun Inadvertent alteration of the control bits could cause the bus
91. operation is low because it is a high speed complementary metal oxide semiconductor HCMOS device Power consumption can be reduced to a minimum during periods of inactivity by executing the low power stop LPSTOP instruction which shuts down the CPU32 and other intermodule bus IMB submodules Ease of programming is an important consideration in using a microcontroller The CPU32 instruction format reflects a predominately register memory interaction philos ophy All data resources are available to all operations requiring those resources There are eight multifunction data registers and seven general purpose addressing registers The data registers readily support 8 bit byte 16 bit word and 32 bit long word operand lengths for all operations Address manipulation is supported by word and long word operations Although the program counter PC and stack pointers SP are special purpose registers they are also available for most data addressing activi ties Ease of program checking and diagnosis is enhanced by trace and trap capabil ities at the instruction level As controller applications become more complex and control programs become larger high level language HLL will become the system designer s choice in programming languages HLL aids rapid development of complex algorithms with less error and is readily portable The CPU32 instruction set will efficiently support HLL 1 1 Features Features of the CPU32 are as follows
92. overflow occurs Cleared otherwise C Set if a borrow occurs Cleared otherwise Instruction Format 15 14 18 12 11 10 9 8 7 6 5 4 3 2 1 0 EFFECTIVE ADDRESS 1 0 1 1 REGISTER OPMODE MODE REGISTER Instruction Fields Register field Specifies the destination data register Opmode field Byte Word Long Operation 000 001 010 ea CPUS2 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4 55 CMP Compare CMP Effective Address field Specifies the source operand All addressing modes are allowed as shown Addressing Mode Mode Register Addressing Mode Mode Register Dn 000 Reg number Dn 111 000 001 Reg number An xxx L 111 001 An 010 Reg number An data 111 100 An 011 Reg number An An 100 Reg number An 96 An 101 Reg number An dig PC 111 010 dg An Xn 110 Reg number An dg PC Xn 111 011 bd An Xn 110 Reg number An bd PC Xn 111 011 Word and long only NOTE CMPA is used when the destination is an address register CMPI is used when the source is immediate data CMPM is used for memory to memory compares Most assemblers automatically make the dis tinction MOTOROLA INSTRUCTION SET CPU32 4 56 REFERENCE MANUAL Compare Address Operation Destination Source cc Assembler Syntax CMPA ea An Attributes Size Word Long Descrip
93. sent to a byte sized external port Long operands are accessed in two bus cycles most significant word first The instruction pipeline is capable of recognizing instructions that cause a change of flow It informs the bus controller when a change of flow is imminent and the bus con troller refrains from starting prefetches that would be discarded due to the change of flow CPU32 INSTRUCTION EXECUTION TIMING MOTOROLA REFERENCE MANUAL 8 3 8 1 4 Instruction Execution Overlap Overlap is the time measured in clock cycles that an instruction executes concurrent ly with the previous instruction As shown in Figure 8 2 portions of instructions A and B execute simultaneously so that total execution time is reduced Because portions of instructions B and C also overlap overall execution time for all three instructions is also reduced Each instruction contributes to the total overlap time The portion of execution time at the end of instruction A that can overlap the beginning of instruction B is called the tail of instruction A The portion of execution time at the beginning of instruction B that can overlap the end of instruction A is called the head of instruction B The total overlap time between instructions A and B is the smaller tail of A and the head of B INSTRUCTION A INSTRUCTION B E INSTRUCTION C p si OVERLAP OVERLAP Figure 8 2 Simultaneous Instruction Execution The execution ti
94. stack pointer or the status register The following table shows the instructions and the registers involved Instruction Implicit Registers ANDI to CCR SR ANDI to SR SR BRA PC BSR PC SP CHK exception PC SP 2 exception SSP SR DBcc PC DIVS exception SSP SR DIVU exception SSP SR EORI to CCR SR EORI to SR SR JMP PC JSR PC SP LINK SP LPSTOP SR MOVE CCR SR MOVE SR SR MOVE USP USP MOTOROLA DATA ORGANIZATION AND ADDRESSING CAPABILITIES CPU32 3 2 REFERENCE MANUAL Instruction Implicit Registers ORI to CCR SR ORI to SR SR PEA SP RTD PC SP RTE PS SP SR RTR PC SP SR RTS PC SP STOP SR TRAP exception SSP SR exception SSP SR UNLK SP 3 4 Effective Address Most instructions specify the location of an operand by a field in the operation word called an effective address field or an effective address EA An EA is composed of two 3 bit subfields mode specification field and register specification field Each of the address modes is selected by a particular value in the mode specification subfield of the EA The EA field may require further information to fully specify the operand This information called the EA extension is in a following word or words and is considered part of the instruction see 3 1 Program and Data References 3 4 1 Register Direct Mode These EA modes specify that th
95. stores the result in the address register The entire destination address register is used regardless of the operation size Condition Codes Not affected Instruction Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EFFECTIVE ADDRESS 1 1 0 1 REGISTER OPMODE MODE REGISTER Instruction Fields Register field Specifies any of the eight address registers This is always the desti nation Opmode field Specifies the size of the operation 011 Word operation The source operand is sign extended to a long oper and and the operation is performed on the address register using all 32 bits 111 Long operation Effective Address field Specifies source operand All addressing modes are al lowed as shown Addressing Mode Mode Register Addressing Mode Mode Register Dn 000 Reg number Dn xxx W 111 000 An 001 Reg number An xxx L 111 001 An 010 Reg number An data 111 100 An 011 Reg number An An 100 Reg number An 96 An 101 Reg number An dig PC 111 010 dg An Xn 110 Reg number An dg PC Xn 111 011 bd An Xn 110 Reg number An bd PC Xn 111 011 CPUS2 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4 19 ADDI Add Immediate AD Operation Immediate Data Destination Destination Assembler Syntax ADDI data ea Attributes Size Byte Word Long Description Adds the immediate data
96. swapping in the low order word of a data register is best done with ROR ROR W 8 Dn A special hardware assist has been pro vided to minimize operation execution CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4 131 RO L RO R Rotate Without Extend Instruction Format Memory Rotate ROL ROR 3 EFFECTIVE ADDRESS MODE REGISTER Instruction Fields Memory Rotate dr field Specifies the direction of the rotate 0 Rotate right 1 Rotate left Effective Address field Specifies the operand to be rotated Only memory alterable addressing modes are allowed as shown Addressing Mode Mode Register Addressing Mode Mode Register Dn xxx W 111 000 An xxx L 111 001 An 010 Reg number An data An 011 Reg number An An 100 Reg number An 416 101 Reg number dig PC mE dg An Xn 110 Reg number An dg PC Xn bd An Xn 110 Reg number An bd PC Xn MOTOROLA INSTRUCTION SET CPU32 4 132 REFERENCE MANUAL ROXL ROXR Rotate with Extend Operation Assembler ROXd Dx Dy Syntax ROXd data Dy ROXd ea where d is direction L or R Attributes Size Byte Word Long ROXL ROXR Destination Rotated with X by count Destination Description Rotates the bits of the operand in the direction specified L or R T
97. the effective address of an operand in memory is derived An assembler syntax has been defined for each addressing mode Figure 3 1 shows the general format of the single effective address instruction oper ation word The effective address field specifies the addressing mode for an operand that can use one of the numerous defined modes The designation is composed of two 3 bit fields the mode field and the register field The value in the mode field selects a mode or a set of modes The register field specifies a register for the mode or a sub mode for modes that do not use registers EFFECTIVE ADDRESS REGISTER Figure 3 1 Single Effective Address Instruction Operation Word Many instructions imply the addressing mode for only one of the operands The for mats of these instructions include appropriate fields for operands that use only a single addressing mode Additional information may be needed to specify an operand address This information is contained in an additional word or words called the effective address extension and is considered part of an instruction Address extension formats are discussed in 3 4 4 Effective Address Encoding Summary When an addressing mode uses a register the register is specified by the register field of the operation word Other fields within the instruction specify whether the selected register is an address or data register and how the register is to be used 3 1 Program and Data References
98. the most significant bit of the result is set Cleared otherwise Z Set if the result is zero Cleared otherwise V Always cleared Set according to the last bit rotated out of the operand Set to the value of the extend bit when count is zero Instruction Format Register Rotate 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 0 COUNT REGISTER dr SIZE ilr 1 0 REGISTER Instruction Fields Register Rotate Count Register field If i r O this field contains the rotate count The values 1 7 represent counts of 1 7 and 0 specifies a count of 8 If i r 2 1 this field specifies a data register that contains the rotate count mod ulo 64 dr field Specifies the direction of the rotate 0 Rotate right 1 Rotate left Size field Specifies the size of the operation 00 Byte operation 01 Word operation 10 Long operation i r field Specifies the rotate count location If i r 0 immediate rotate count If i r 2 1 register rotate count Register field Specifies a data register to be rotated MOTOROLA INSTRUCTION SET CPU32 4 134 REFERENCE MANUAL ROXL ROXR Rotate with Extend ROXL ROXR Instruction Format Memory Rotate 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EFFECTIVE ADDRESS MODE REGISTER Instruction Fields Memory Rotate dr field Specifies the direction of the rotate 0 Rotate right 1
99. then Rn Destination DFC or Source SFC Rn else TRAP Assembler MOVES Rn ea Syntax MOVES ea Rn Attributes Size Byte Word Long Description Moves the byte word or long operand from the specified general register to a location within the address space specified by the destination function code DFC register or moves the byte word or long operand from a location within the address space specified by the source function code SFC register to the speci fied general register If the destination is a data register the source operand replaces the correspond ing low order bits of the data register depending on the size of the operation If the destination is an address register the source operand is sign extended to 32 bits and then loaded into the address register Condition Codes Not affected Instruction Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EFFECTIVE ADDRESS 0 0 0 0 1 1 1 0 SIZE MODE REGISTER AID REGISTER dr 0 0 0 0 0 0 0 0 0 0 0 Instruction Fields Size field Specifies the size of the operation 00 Byte operation 01 Word operation 10 Long operation CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4 105 M OV ES Move Address Space M OV ES Privileged Instruction Effective Address field Specifies the source or destination location within the alter nate address space Only memory alterable addressing modes are allo
100. total clock cycle number All timing data assumes two clock reads and writes Instruction Head Tail Cycles Bcc taken 2 2 8 0 2 0 Bcc B not taken 2 0 4 0 1 0 Bcc W not taken 0 0 4 0 2 0 Bcc L not taken 0 0 6 0 3 1 DBcc T not taken 1 1 4 0 2 0 DBcc F 1 not taken 2 0 6 0 2 0 DBcc F not 1 taken 6 2 10 0 2 0 DBcc T not taken 4 0 6 0 1 0 DBcc F 1 not taken 6 0 8 0 1 0 DBcc F not 1 taken 6 0 10 0 0 0 loop mode MOTOROLA INSTRUCTION EXECUTION TIMING CPU32 8 20 REFERENCE MANUAL 8 3 12 Control Instructions The control instruction table indicates the number of clock periods needed for the pro cessor to perform the specified operation on the given addressing mode Footnotes indicate when to account for the appropriate effective address times The total number of clock cycles is outside the parentheses The numbers inside parentheses r p w are included in the total clock cycle number All timing data assumes two clock reads and writes Instruction Head Tail Cycles ANDI SR 0 2 12 0 2 0 SR 0 2 12 0 2 0 ORI SR 0 2 12 0 2 0 ANDI CCR 2 0 6 0 2 0 EORI CCR 2 0 6 0 2 0 ORI CCR 2 0 6 0 2 0 BSR B 3 2 13 0 2 2 BSR W 3 2 13 0 2 2 BSR L 1 2 13 0 2 2 CHK FEA Dn no ex 2 0 8 0 1 0 CHK FEA Dn 2 2 42 2 2 6 CH
101. upper byte of the status register is not altered Condition Codes X N Z V C X Set to the value of bit 4 of the source operand N Set to the value of bit 3 of the source operand Z Set to the value of bit 2 of the source operand V Set to the value of bit 1 of the source operand C Set to the value of bit O of the source operand Instruction Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EFFECTIVE ADDRESS 0 1 0 0 0 1 0 0 1 1 MODE REGISTER CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4 93 MOVE Move to Condition Code Register MOVE to CCR to CCR Instruction Fields Effective Address field Specifies the destination location Only data addressing modes are allowed as shown Addressing Mode Mode Register Addressing Mode Mode Register Dn 000 Reg number Dn 111 000 xxx L 111 001 An 010 Reg number An data 111 100 An 011 Reg number An An 100 Reg number An 416 101 Reg number dig PC 111 010 dg An Xn 110 Reg number An dg PC Xn 111 011 bd An Xn 110 Reg number An bd PC Xn 111 011 NOTE MOVE to CCR is a word operation ANDI ORI and EORI to CCR are byte operations MOTOROLA INSTRUCTION SET CPU32 4 94 REFERENCE MANUAL MOVE Move from the Status Register MOVE from SR Privileged Instructio
102. zero a 16 bit displacement the word immediately following the instruction is used If the 8 bit displacement field in the instruction word is all ones FF the 32 bit displacement long word immediately fol lowing the instruction is used Condition Codes Not affected Instruction Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 1 0 0 0 0 1 8 BIT DISPLACEMENT 16 BIT DISPLACEMENT IF 8 BIT DISPLACEMENT 00 32 BIT DISPLACEMENT IF 8 BIT DISPLACEMENT FF Instruction Fields 8 Bit Displacement field Twos complement integer specifying the number of bytes between the branch instruction and the next instruction to be executed 16 Bit Displacement field Used for larger displacement when 8 bit displacement is 00 32 Bit Displacement field Used for larger displacement when 8 bit displacement is FF NOTE A branch to the instruction immediately following automatically uses 16 bit displacement because the 8 bit displacement field contains 00 zero offset MOTOROLA INSTRUCTION SET CPU32 4 46 REFERENCE MANUAL BIST Test a Bit BIST Operation bit number of Destination gt 2 Assembler BTST Dn ea Syntax BTST 4 data ea Attributes Size Byte Long Description Tests a bit in the destination operand and sets the Z condition code appropriately When a data register is the destination any of the 32 bits can be spec ified by a modulo 32 bit number W
103. 0 7 11 7 12 8 1 8 2 CPUS2 LIST OF ILLUSTRATIONS Title Page Loop Mode Instruction Sequence 24444000 1 3 CPUSZ Block Diagrami 1 7 User Programming Model 2 2 Supervisor Programming Model Supplement 2 2 Stat S o tatu 2 3 Data Organization in Data Begisters o i Ru EI appris 2 4 Address Organization in Address Registers 2 5 Memory Addressing ipe e e n euer rent tage 2 7 Single Effective Address Instruction Operation Word 3 1 Effective Address Specification Formats 3 10 Using SIZE in the Index Selection 04 2221 3 12 Using Absolute Address with Indexes 222011 3 12 Addressing Array NEMS uia C A URP 3 13 M68000 Family Address Extension Words 3 15 Instruction Word General 120 40 4 2 Instruction Description Format 4 14 Table Example d uu eb epe t pe M oes 4 188 Table Exatmple 2 oe e eise tente Ee rea eq iud 4 189 Table
104. 0 0 0 1 0 1 0 SIZE MODE REGISTER WORD DATA 16 BITS BYTE DATA 8 BITS LONG DATA 32 BITS Instruction Fields Size field Specifies the size of the operation 00 Byte operation 01 Word operation 10 Long operation MOTOROLA INSTRUCTION SET CPU32 4 74 REFERENCE MANUAL EORI Exclusive OR Immediate EORI Effective Address field Specifies the destination operand Only data alterable addressing modes are allowed as shown Addressing Mode Mode Register Addressing Mode Mode Register Dn 000 Reg number Dn xxx W 111 000 An xxx L 111 001 An 010 Reg number An data An 011 Reg number An An 100 Reg number An 96 An 101 Reg number An 96 PC dg An Xn 110 Reg number An dg PC Xn bd An Xn 110 Reg number An bd PC Xn Immediate field Data immediately following the instruction If size 00 the data is the low order byte of the immediate word If size 01 the data is the entire immediate word If size 10 the data is next two immediate words CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4 75 EORI Exclusive OR Immediate EORI to CCR to Condition Code Register to CCR Operation Source CCR CCR Assembler Syntax EORI data CCR Attributes Size Byte Description Performs an exclusive OR operation on the condition code register using the immediate op
105. 0 8 7 5 4 3 2 1 0 EFFECTIVE ADDRESS 0 0 0 0 0 1 0 SIZE MODE REGISTER WORD DATA 16 BITS LONG DATA 32 BITS BYTE DATA 8 BITS Size Field 00 Byte 01 Word 10 Long BTST Static 15 14 13 12 11 10 8 7 5 4 3 2 1 0 EFFECTIVE ADDRESS 0 0 0 0 1 0 0 0 MODE REGISTER 0 0 0 0 0 0 0 BIT NUMBER Bit Number Field Modulo 32 bit selection BCHG Static 15 14 13 12 11 10 8 7 5 4 3 2 1 0 EFFECTIVE ADDRESS 0 0 0 0 1 0 0 0 MODE REGISTER 0 0 0 0 0 0 0 BIT NUMBER Bit Number Field Modulo 32 bit selection BCLR Static 15 14 13 12 11 10 8 7 5 4 3 2 1 0 EFFECTIVE ADDRESS 0 0 0 0 1 0 0 1 MODE REGISTER 0 0 0 0 0 0 0 BIT NUMBER Bit Number Field Modulo 32 bit selection CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4 173 BSET Static 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EFFECTIVE ADDRESS 0 0 0 0 1 0 0 0 1 1 MODE REGISTER 0 0 0 0 0 0 0 0 BIT NUMBER Bit Number Field Modulo 32 bit selection EORI 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EFFECTIVE ADDRESS 0 0 0 0 1 0 1 0 SIZE MODE REGISTER WORD DATA
106. 00 Reg number An 416 An 101 Reg number An dig PC 111 010 dg An Xn 110 Reg number An dg PC Xn 111 011 bd An Xn 110 Reg number An bd PC Xn 111 011 NOTE Overflow occurs if the quotient is larger than a 16 bit signed integer CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4 67 D VS Signed Divide D VS DIVSL DIVSL Instruction Format long form 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EFFECTIVE ADDRESS 0 1 0 0 1 1 0 0 0 1 MODE REGISTER 0 REGISTER Dq 1 SIZE 0 0 0 0 0 0 0 REGISTER Dr Instruction Fields Effective Address field Specifies the source operand Only data addressing modes are allowed as shown Addressing Mode Mode Register Addressing Mode Mode Register Dn 000 Reg number Dn xxx W 111 000 An xxx L 111 001 An 010 Reg number An data 111 100 An 011 Reg number An An 100 Reg number An 416 101 Reg number dig PC 111 010 dg An Xn 110 Reg number An dg PC Xn 111 011 bd An Xn 110 Reg number An bd PC Xn 111 011 Register Dq field Specifies a data register for the destination operand The low order 32 bits of the dividend come from this register and the 32 bit quotient is loaded into this register Size field Selects a 32 or 64 bit division operation 0 32 bit dividend is in Register Dq 1 64 bit dividend i
107. 1 The first column is the value passed to the subroutine the second column is the value expected by the table instruction and the third column is the result returned by the subroutine The following value has been calculated for independent variable X 31 16 15 0 NOT USED 0000000010 111 1041 Since X is an 8 bit value the upper four bits are used as a table offset and the lower four bits are used as an interpolation fraction The following results are obtained from the subroutine Table Entry Offset Dx 4 7 B 11 Interpolation Fraction Dx 0 3 D 13 Thus Y is calculated as follows Y 80 13 64 80 16 67 If the 8 bit value for X were used directly by the table instruction interpolation would be incorrectly performed between entries 0 and 1 Data must be shifted to the left four places before use LSL W 4 Dx The new range for X is 0 lt X lt 4096 however since a left shift fills the least significant digits of the word with zeroes the interpolation fraction can only have one of 16 values After the shift operation Dx contains the following value 31 16 15 0 NOT USED 0000101 111010000 Execution of the table instruction using the new value in Dx yields Table Entry Offset Dx 8 15 0B 11 Interpolation Fraction Dx 0 7 DO 208 Thus Y is calculated as follows Y 80 208 64 80 256 67 4 6 4 Table Example 4 Maintaining Pr
108. 1 0 Assuming that no trailing write exists from the previous instruction effective address calculation requires six clocks Replacement fetch for the effective address occurs during these six clocks leaving a head of four If there is no time in the head to perform a prefetch due to a previous trailing write then additional time to do the prefetches must be allotted in the middle of the instruction or after the tail MOTOROLA INSTRUCTION EXECUTION TIMING CPU32 8 10 REFERENCE MANUAL 102 10 TOTAL NUMBER OF CLOCKS NUMBER OF READ CYCLES NUMBER OF INSTRUCTION ACCESS CYCLES NUMBER OF WRITE CYCLES The total number of bus activity clocks is 2 Reads x 2 Clocks Read 1 Instruction Access x 2 Clocks Access 0 Writes x 2 Clocks Write 6 Clocks of Bus Activity The number of internal clocks not overlapped by bus activity is 10 Clocks Total 6 Clocks Bus Activity 4 Internal Clocks Memory read requires two bus cycles at two clocks each This read time implied in the tail figure for the effective address cannot be overlapped with the instruction be cause the instruction has a head of zero An additional two clocks are required for the ADD instruction itself The total is 6 4 2 12 clocks If bus cycles take more time i e the memory is off chip add an appropriate number of clocks to each memory access The instruction sequence MOVE L DO A0 followed by LSL L 7 D2 provides an ex ample of o
109. 1 0 EFFECTIVE ADDRESS 0 1 0 1 DATA 0 SIZE MODE REGISTER Data Field Three bits of immediate data 000 111 represent values of 1 7 000 represents 8 Size Field 00 Byte 01 Word 10 Long MOTOROLA INSTRUCTION SET CPU32 4 180 REFERENCE MANUAL Scc 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EFFECTIVE ADDRESS 0 1 0 1 CONDITION 1 1 MODE REGISTER DBcc 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 0 1 CONDITION 1 1 0 0 1 REGISTER DISPLACEMENT TRAPcc 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 0 1 CONDITION 1 1 1 1 1 OPMODE OPTIONAL WORD OR LONG WORD Opmode Field 010 Word Operand 011 Long Operand 100 No Operand SUBQ 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EFFECTIVE ADDRESS 0 1 0 1 DATA 1 SIZE MODE REGISTER Data Field Three bits of immediate data 000 111 represent values of 1 7 000 represents 8 Size Field 00 Byte 01 Word 10 Long Bcc 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 1 0 CONDITION 8 BIT DISPLACEMENT 16 BIT DISPLACEMENT IF 8 BIT DISPLACEMENT 00 32 BIT DISPLACEMENT IF 8 BIT DISPLACEMENT FF BRA 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 1 0 0 0 0 0 8 BIT DISPLACEMENT 16 BIT DISPLACEMENT IF 8 BIT DISPLACEMENT 00 32 BIT DISPLACEMENT IF 8 BIT DISPLACEMENT FF BSR 15 14 13 12 11
110. 1 000 An 001 Reg number An xxx L 111 001 An 010 Reg number An data 111 100 An 011 Reg number An An 100 Reg number An 416 101 Reg number dig PC 111 010 dg An Xn 110 Reg number An dg PC Xn 111 011 bd An Xn 110 Reg number An bd PC Xn 111 011 Word and long word only If the location specified is a destination operand only memory alterable addressing modes are allowed as shown Addressing Mode Mode Register Addressing Mode Mode Register Dn xxx W 111 000 An xxx L 111 001 An 010 Reg number An data An 011 Reg number An An 100 Reg number An dig 101 Reg number An 916 PC x dg An Xn 110 Reg number An dg PC Xn bd An Xn 110 Reg number An bd PC Xn NOTES 1 Dn mode is used when destination is a data register Destination ea mode is invalid for a data register 2 ADDA is used when the destination is an address register ADDI and ADDQ are used when the source is immediate data Most assemblers automatically make this distinction MOTOROLA 4 18 INSTRUCTION SET CPU32 REFERENCE MANUAL A D DA Add Address A D DA Operation Source Destination Destination Assembler Syntax ADDA ea An Attributes Size Word Long Description Adds the source operand to the destination address register and
111. 1 1 0 0 MULU Long 15 14 13 12 11 10 9 8 7 6 4 3 2 1 0 EFFECTIVE ADDRESS 0 1 0 0 1 1 0 0 0 0 MODE REGISTER 0 REGISTER DI 0 SIZE 0 0 0 0 0 0 REGISTER Dh Size Field 0 Long Word Product 1 Quad Word Product MULS Long 15 14 13 12 11 10 9 8 7 6 4 3 2 1 0 EFFECTIVE ADDRESS 0 1 0 0 1 1 0 0 0 1 MODE REGISTER 0 REGISTER 1 SIZE 0 0 0 0 0 0 REGISTER Dr Size Field 0 Long Word Product 1 Quad Word Product TRAP 15 14 13 12 11 10 9 8 7 6 4 3 2 1 0 0 1 0 0 1 1 1 0 0 1 0 VECTOR MOTOROLA INSTRUCTION SET CPU32 4 178 REFERENCE MANUAL LINK Word 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 0 0 1 1 1 0 0 1 0 1 0 REGISTER WORD DISPLACEMENT UNLK 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 0 0 1 1 1 0 0 1 0 1 1 REGISTER MOVE USP 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 0 0 1 1 1 0 0 1 1 0 DR REGISTER DR Field 0 Move An to USP 1 Move USP to An RESET 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 0 0 1 1 1 0 0 1 1 1 0 0 0 0 NOP 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 0 0 1 1 1 0 0 1 1 1 0 0 0 1 STOP 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 0 0 1 1 1 0 0 1 1 1 0 0 1 0 IMMEDIATE DATA RTE 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 0 0 1 1 1 0 0 1 1 1 0 0 1 1 F
112. 1 110 ea ea MOTOROLA INSTRUCTION SET CPU32 4 182 REFERENCE MANUAL SUBA 15 14 13 12 11 10 8 T 6 5 4 3 2 1 0 EFFECTIVE ADDRESS 1 0 0 1 REGISTER OPMODE MODE REGISTER Opmode Field Word Long Operation 011 111 gt SUBX 15 14 13 12 11 10 8 7 6 5 4 3 2 1 0 1 1 0 1 REGISTER Rx 1 SIZE 0 0 R M REGISTER Ry Size Field 00 Byte 01 Word 10 Long R M Field 0 Data Register to Data Register 1 Memory to Memory If R M 0 both registers must be data registers If R M 1 both registers must be address registers for Predecrement Addressing mode CMP 15 14 13 12 11 10 8 7 6 5 4 3 2 1 0 EFFECTIVE ADDRESS 1 0 1 1 REGISTER OPMODE MODE REGISTER Opmode Field Byte Word Long Operation 000 001 010 Dn ea CCR CMPA 15 14 13 12 11 10 8 7 6 5 4 3 2 1 0 EFFECTIVE ADDRESS 1 0 1 1 REGISTER OPMODE MODE REGISTER Opmode Field Word Long Operation 011 11 KAn ea gt CCR EOR 15 14 13 12 11 10 8 7 6 5 4 3 2 1 0 EFFECTIVE ADDRESS 1 0 1 1 REGISTER OPMODE MODE REGISTER Opmode Field Byte Word Long Operation 100 101 110 ea Dn ea CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4 183 CMPM 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 1 1 REGISTER Ax 1 SIZE 0 0 1 REGISTER Ay Size Field 00 Byte 01 Word 10
113. 1 via RTE 6 21 Type via Software 6 20 Type IV via Software 6 21 Recovery 6 14 Types of 6 16 Type 1 Released Write 6 16 Type Il Prefetch Operand RMW MOVEP 6 17 Type Ill MOVEM Operand Transfer 6 17 Type IV Exception Processing 6 18 Fetch Effective Address Timing Table 8 12 Format Error 6 9 Four Word Stack Frame Normal 6 22 Function Code Registers 2 3 2 5 Future BDM Commands 7 25 MOTOROLA 1 2 INDEX G General Description 1 1 H Halt Operation 5 1 Illegal or Unimplemented Instruction 6 9 Immediate Arithmetic Logic Instruction Timing 8 17 Data Addressing 3 9 Implicit Reference 3 2 Indexed Addressing 3 5 3 7 Indirect Addressing 3 4 Instruction Details 4 13 Execution Overlap 8 4 Execution Time Calculation 8 5 Fetch Signal IFETCH 7 25 Format 4 2 Format Summary 4 170 M68000 Family Compatibility 4 1 New 4 1 Pipe 7 25 8 2 Pipe Signal IPIPE 7 25 Summary 4 5 Timing Tables 8 10 Traps 6 8 Instruction Set Extensions A 3 Instruction Stream Timing Examples 8 7 Instructions Binary Coded Decimal BCD 4 10 8 18 Bit Manipulation 4 10 8 20 Conditional Branch 4 10 8 20 Data Movement 4 6 8 14 Exception Related 4 11 8 21 Integer Arithmetic 4 7 8 15 Logic 4 8 8 15 Program Control Branch 4 10 8 20 Shift and Rotate 4 9 8 19 Single Operand 8 18 System Control 4 11 8 21 Table Lookup and Interpolation 4 188 Interrupts 6 12 a Logic Instructions 4 8 Low Power Stop LPSTOP 4 1 5 1 M M68000 F
114. 10 Reg number An dg PC Xn Lx bd An Xn 110 Reg number An bd PC Xn NOTES 1 If the destination is a data register it must be specified using the destination Dn mode not the destination ea mode 2 Most assemblers use ORI when the source is immediate data CPUS2 REFERENCE MANUAL INSTRUCTION SET MOTOROLA ORI Inclusive OR Immediate ORI Operation Immediate Data Destination Destination Assembler Syntax ORI ea Attributes Size Byte Word Long Description Performs an inclusive OR operation on the immediate data and the destination operand and stores the result in the destination location The size of the immediate data must match the operation size Condition Codes X N 7 V 0 0 Not affected Set if the most significant bit of the result is set Cleared otherwise Set if the result is zero Cleared otherwise Always cleared Always cleared Instruction Format O lt NZ amp 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EFFECTIVE ADDRESS 0 0 0 0 0 0 0 0 SIZE MODE REGISTER WORD DATA 16 BITS BYTE DATA 8 BITS LONG DATA 32 BITS Instruction Fields Size field Specifies the size of the operation 00 Byte operation 01 Word operation 10 Long operation MOTOROLA INSTRUCTION SET CPU32 4 124 REFERENCE MANUAL ORI Inclusive OR Immediate ORI Effectiv
115. 128 Three word cache for the loop mode Virtual Memory Machine MC68000 None MC68010 Bus Error Detection Instruction Continuation CPU32 Bus Error Detection Instruction Restart MC68020 Bus Error Detection Instruction Continuation Coprocessor Interface MC68000 Emulated in Software MC68010 Emulated in Software CPU32 Emulated in Software MC68020 In Microcode Word Long Word Data Alignment MC68000 Word Long Word Data Instructions and Stack Must Be Word Aligned MC68010 Word Long Word Data Instructions and Stack Must Be Word Aligned CPU32 Word Long Word Data Instructions and Stack Must Be Word Aligned MC68020 Only Instructions Must Be Word Aligned Data Alignment Im proves Performance Control Registers MC68000 None MC68010 SFC DFC VBR CPU32 SFC DFC VBR MC68020 SFC DFC VBR CACR CAAR Stack Pointers CPU32 M68000 FAMILY SUMMARY MOTOROLA REFERENCE MANUAL A 1 MC68000 MC68010 CPU32 MC68020 Status Register Bits MC68000 MC68010 CPU32 MC68020 USP SSP USP SSP USP SSP USP SSP MSP ISP S 10 11 12 X N Z V C S 10 11 12 X N Z V C T1 TO S 10 11 12 X N Z V C T1 TO S M 10 11 12 X N Z V C Function Code Address Space MC68000 MC68010 CPU32 MC68020 Indivisible Bus Cycles MC68000 MC68010 CPU32 MC68020 Stack Frames MC68000 MC68010 CPU32 MC68020 MOTOROLA A 2 FCO FC2 is Interrupt Acknowledge Only FCO FC2 7 is CPU Space FCO
116. 2 PC SP 4 SP restore state and de allocate stack according to SP else TRAP Assembler Syntax RTE Attributes Unsized Description Loads the processor state information stored in the exception stack frame located at the top of the stack into the processor The instruction examines the stack format field in the format offset word to determine how much information must be restored Condition Codes Set according to the condition code bits in the status register value restored from the stack Instruction Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 0 0 1 1 1 0 0 1 1 1 0 0 1 1 Format Offset word in stack frame 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FORMAT 0 0 VECTOR OFFSET Format Field of Format Offset Word Contains the format code which implies the stack frame size including the format off set word 0000 Short Format removes four words Loads the status register and the program counter from the stack frame 0001 Throwaway Format removes four words Loads the status register from the stack frame and switches to the active system stack Continues the instruction using the active system stack 0010 Instruction Error Format removes six words Loads the status register and the program counter from the stack frame and discards the other words 1000 MC68010 Long Format The MC68020 takes a format error exception 1001 Coprocessor Mid Instructi
117. 3 2 1 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 IMMEDIATE DATA TBLU TBLUN Data Register Interpolate 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 0 0 0 0 0 0 0 0 REGISTER Dym REGISTER Dx 0 R 0 0 SIZE 0 0 0 REGISTER Dyn R Field 0 Unrounded 1 Rounded TBLU TBLUN Lookup and Interpolate 0 REGISTER Dx 0 R 0 1 SIZE 0 0 0 0 0 0 R Field 0 Unrounded 1 Rounded TBLS TBLSN Data Register Interpolate 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 0 0 0 0 0 0 0 0 REGISTER Dym REGISTER Dx 1 R 0 0 SIZE 0 0 0 REGISTER Dyn R Field 0 Unrounded 1 Rounded TBLS TBLSN Lookup and Interpolate 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EFFECTIVE ADDRESS 1 1 1 1 1 0 0 0 0 0 MODE REGISTER 0 REGISTER Dx 1 R 0 1 SIZE 0 0 0 0 0 0 R Field 0 Unrounded 1 Rounded CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4 187 4 6 Table Lookup and Interpolation Instructions There are four table lookup and interpolate instructions TBLS returns a signed round ed byte word or long word result TBLSN returns a signed unrounded byte word or long word result TBLU returns an unsigned rounded byte word or long word result TBLUN returns an unsigned unrounded byte word or lon
118. 32 4 6 REFERENCE MANUAL Table 4 2 Data Movement Operations Instruction Syntax Operand Size Operation MOVEM list ea 16 32 Listed registers Destination ea list 16 32 32 Source Listed registers MOVEP Dn dig An 16 32 31 24 Dn 23 16 gt An d 2 Dn 15 8 2 An d 4 Dn 7 0 An d 6 9 6 An Dn An d gt Dn 81 24 An d 2 gt Dn 23 16 Tero An d 4 2Dn 15 8 An d 6 2 Dn 7 0 MOVEQ data Dn 8 gt 32 Immediate data Destination PEA ea 32 SP 4 SP ea gt SP UNLK An 32 An SP SP SP 4 5 SP 4 3 3 Integer Arithmetic Operations The arithmetic operations include the four basic operations of add ADD subtract SUB multiply MUL and divide DIV as well as arithmetic compare CMP CMPM CMP2 clear CLR and negate NEG The instruction set includes ADD CMP and SUB instructions for both address and data operations with all operand sizes valid for data operations Address operands consist of 16 or 32 bits The clear and negate in structions apply to all sizes of data operands Signed and unsigned MUL and DIV instructions include Word multiply to produce a long word product Long word multiply to produce a long word or quad word product Division of a long word dividend by a word divisor word quotient and word re mainder Division of a long word or quad word dividend by a
119. ATA CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4 127 P EA Push Effective Address P EA Operation Sp 4 gt SP ea gt SP Assembler Syntax PEA ea Attributes Size Long Description Computes the effective address and pushes it onto the stack The effective address must be a long word address Condition Codes Not affected Instruction Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EFFECTIVE ADDRESS MODE REGISTER Instruction Fields Effective Address field Specifies the address to be pushed onto the stack Only control addressing modes are allowed as shown Addressing Mode Mode Register Addressing Mode Mode Register Dn xxx W 111 000 An xxx L 111 001 An 010 Reg number An data An An 416 101 Reg number dig PC 111 010 dg An Xn 110 Reg number An dg PC Xn 111 011 bd An Xn 110 Reg number An bd PC Xn 111 011 MOTOROLA INSTRUCTION SET CPU32 4 128 REFERENCE MANUAL R ES ET Reset External Devices R ES ET Privileged Instruction Operation If supervisor state then Assert RESET Line else TRAP Assembler Syntax RESET Attributes Unsized Description Asserts the RESET signal for 512 clock periods resetting all exter nal devices The processor state other than the program counter is unaffected and execu
120. Addressing Mode Mode Register Addressing Mode Mode Register Dn 000 Reg number Dn xxx W 111 000 An xxx L 111 001 An 010 Reg number An data 111 100 An 011 Reg number An An 100 Reg number An 416 101 Reg number dig PC 111 010 dg An Xn 110 Reg number An dg PC Xn 111 011 bd An Xn 110 Reg number An bd PC Xn 111 011 Register DI field Specifies a data register for the destination operand The 32 bit multiplicand comes from this register and the low order 32 bits of the product are loaded into this register Size field Selects a 32 or 64 bit product 0 32 bit product to be returned to Register DI 1 64 bit product be returned to Dh DI Register Dh field If Size is 1 specifies the data register into which the high order 32 bits of the product are loaded If Dh DI and Size is 1 the results of the operation are undefined MOTOROLA INSTRUCTION SET CPU32 4 112 REFERENCE MANUAL N BC D Negate Decimal with Extend N BC D Operation 0 Destination 9 X Destination Assembler Syntax NBCD ea Attributes Size Byte Description Subtracts the destination operand and the extend bit from zero The operation is performed using binary coded decimal arithmetic The packed BCD result is saved in the destination location This instruction produces the tens comple ment of the destination if the extend bit is zero
121. An bd PC Xn 111 011 Register List Mask field Specifies the registers to be transferred corresponds to the first register to be transferred the high order bit corre sponds to the last register to be transferred Thus both for control modes and for the postincrement mode addresses the mask correspondence is 15 14 13 12 11 10 9 8 7 6 5 4 3 The low order bit 2 1 0 A7 A6 A5 A4 A3 A2 A1 AO D7 D6 D5 D4 D3 D2 D1 DO For predecrement mode addresses the mask correspondence is reversed 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DO D1 D2 D3 D4 D5 D6 D7 AO Al A2 A4 A5 A6 A7 CPU32 REFERENCE MANUAL NOTE An extra read bus cycle occurs for memory operands This accesses an operand at one address higher than the last register image re quired INSTRUCTION SET MOTOROLA 4 101 MOVEP Operation Assembler Syntax Attributes Description accesses alternate bytes on an 8 or 32 bit bus Move Peripheral Data Source Destination MOVEP Dx d Ay MOVEP d Ay Dx Size Word Long MOVEP Moves data between a data register and alternate bytes within the address space typically assigned to a peripheral starting at the location specified and incrementing by two This instr
122. CE MANUAL 4 139 5 BC D Subtract Decimal with Extend 5 BC D Operation Destination Source o X Destination Assembler SBCD Dx Dy Syntax SBCD Ax Ay Attributes Size Byte Description Subtracts the source operand and the extend bit from the destina tion operand and stores the result in the destination location The subtraction is per formed using binary coded decimal arithmetic the operands are packed BCD numbers The instruction has two modes 1 Data register to data register The data registers specified by the instruction contain the operands 2 Memory to memory The address registers specified by the instruction access the operands from memory using the predecrement addressing mode Condition Codes X N Z V n U U E X Set the same as the carry bit N Undefined Z Cleared if the result is nonzero Unchanged otherwise V Undefined C Set if a borrow decimal is generated Cleared otherwise NOTE Normally the Z condition code bit is set via programming before the start of an operation This allows successful tests for zero results upon completion of multiple precision operations Instruction Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 0 0 REGISTER Ry 1 0 0 0 0 R M REGISTER Rx Instruction Fields Register Dy Ay field Specifies the destination register If R M 0 specifies a data register If R M 1 specifies an address register for the predecrement
123. D BY CPU HIGH AND LOW ORDER RESULTS FROM PREVIOUS COMMAND 16 BITS OF RESULT RESPONSES FROM THE CPU Figure 7 10 Command Sequence Diagram Example CPU32 DEVELOPMENT SUPPORT MOTOROLA REFERENCE MANUAL 7 13 7 2 8 3 Command Set Summary The BDM command set is summarized in Table 7 4 Subsequent paragraphs contain detailed descriptions of each command Table 7 4 BDM Command Summary Mnemonic RAREG RDREG Command Read A D Register Description Read the selected address or data register and return the results via the serial interface Write A D Register WAREG WDREG The data operand is written to the specified address or data register Read System Register RSREG The specified system control register is read All registers that can be read in supervisor mode can be read in BDM Write System Register WSREG Read Memory Location The operand data is written into the specified system control register Read the sized data at the memory location specified by the long word address The source function code register SFC determines the address space accessed Write Memory Location Write the operand data to the memory location specified by the long word address The destination function code register DFC register determines the address space accessed Dump Memory Block Used in conjunction with the READ command to dump large blocks of memory An initial READ is executed to set up the sta
124. Description If the specified condition is true program execution continues at location PC displacement The PC contains the address of the instruction word of the Bcc instruction plus two The displacement is a twos complement integer that rep resents the relative distance in bytes from the current PC to the destination PC If the 8 bit displacement field in the instruction word is zero a 16 bit displacement the word immediately following the instruction is used If the 8 bit displacement field in the instruction word is all ones FF the 32 bit displacement long word immediately following the instruction is used Condition codes are specified as follows cc Name Code Description cc Name Code Description CC Carry Clear 0100 LS Low or Same 0011 2 CS Carry Set 0101 C LT Less Than 1101 N eV N eV EQ Equal 0111 Z MI Minus 1011 N GE Greateror Equal 1100 NeV N eV Not Equal 0110 2 GT Greater Than 1110 NeV eZiN eV eZ PL Plus 1010 N HI High 0010 TZ Overflow Clear 1000 V LE Less or Equal 1111 ZNeVNeV Overflow Set 1001 V Condition Codes Not affected Instruction Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 1 0 CONDITION 8 BIT DISPLACEMENT 16 BIT DISPLACEMENT IF 8 BIT DISPLACEMENT 00 32 BIT DISPLACEMENT IF 8 BIT DISPLACEMENT FF CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4 35 Bcc Branch Conditionally Bcc Instruction Fields Condition field The binary code for one of the conditions listed in
125. E REGISTERS Figure 2 2 Supervisor Programming Model Supplement 2 2 Registers Registers D7 to DO are used as data registers for bit byte 8 bit word 16 bit long word 32 bit and quad word 64 bit operations Registers A6 to AO and the user and supervisor stack pointers are address registers that may be used as software stack pointers or base address registers Register A7 shown as A7 A7 in Figure 2 1 is a register designation that applies to the user stack pointer in the user privilege level and to the supervisor stack pointer in the supervisor privilege level In addition ad dress registers may be used for word and long word operations All of the 16 general purpose registers D7 to DO A7 to 0 may be used as index registers MOTOROLA ARCHITECTURE SUMMARY CPU32 2 2 REFERENCE MANUAL The program counter PC contains the address of the next instruction to be executed by the CPU32 During instruction execution and exception processing the processor automatically increments the contents of the PC or places a new value in the PC as appropriate The status register SR see Figure 2 3 contains condition codes an interrupt prior ity mask three bits and three control bits Condition codes reflect the results of a pre vious operation The codes are contained in the low byte or condition code register of the SR The interrupt priority mask determines the level of priority an interrupt must have in order to be a
126. ENERATION EA GIVEN ASSEMBLER SYNTAX Qox L MODE 111 REGISTER 001 15 0 FIRST EXTENSION WORD ADDRESS HIGH 15 0 SECOND EXTENSION WORD gt ADDRESS LOW T DE CONCATENATION 31 0 MEMORY ADDRESS NUMBER OF EXTENSION WORDS 2 OPERAND 3 4 3 6 Immediate Data In this addressing mode the operand is in one or two extension words Byte Operation The operand is in the low order byte of the extension word Word Operation The operand is in the extension word Long Word Operation The high order 16 bits of the operand are in the first extension word the low order 16 bits are in the second extension word GENERATION OPERAND GIVEN ASSEMBLER SYNTAX XXX MODE 111 REGISTER 100 NUMBER OF EXTENSION WORDS 10R2 3 4 4 Effective Address Encoding Summary Most addressing modes use one of the three formats shown in Figure 3 2 The single EA instruction is in the format of the instruction word The mode field of this word se lects the addressing mode The register field contains the general register number or a value that selects the addressing mode when the mode field contains 111 Some indexed or indirect modes use the instruction word followed by the brief format extension word Other indexed or indirect modes consist of the instruction word and the full format of extension words The longest instruction for the CPU32 contains six extension words It is a MOVE instruction with full format exte
127. ER DISPLACEMENT LOW ORDER DISPLACEMENT SWAP 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 0 0 1 0 0 0 0 1 0 0 0 REGISTER BKPT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 0 0 1 0 0 0 0 1 0 0 1 VECTOR PEA 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EFFECTIVE ADDRESS 0 1 0 0 1 0 0 0 0 1 MODE REGISTER Size Field 00 Byte 01 Word 10 Long EXT EXTB 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 0 0 1 0 0 OPMODE 0 0 0 REGISTER Opmode Field 010 Extend Word 011 Extend Long 111 Extend Byte Long MOVEM 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EFFECTIVE ADDRESS 0 1 0 0 1 dr 0 0 1 SIZE MODE REGISTER REGISTER LIST MASK Size Field 00 Byte 01 Word 10 Long Register to EA Mask 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A7 A6 A5 A4 A3 A2 Al 0 D7 D6 D5 D4 D3 D2 D1 DO EA to Register Mask 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DO D1 D2 D3 D4 D5 D6 D7 0 Al A2 A4 5 A6 A7 CPUS2 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4 177 TST 15 14 13 12 11 10 9 8 7 6 4 3 2 1 0 EFFECTIVE ADDRESS 0 1 0 0 1 0 1 0 SIZE MODE REGISTER Size Field 00 Byte 01 Word 10 Long TAS 15 14 13 12 11 10 9 8 7 6 4 3 2 1 0 EFFECTIVE ADDRESS REGISTER BGND ILLEGAL 15 14 13 12 11 10 9 8 7 6 4 3 2 1 0 0 1 0 0 1 0 1 0 1 1 1
128. FC2 7 is CPU Space FCO FC2 7 is CPU Space Use AS Signal Use AS Signal Use RMC Signal Use RMC Signal Supports Original Set Supports Formats 0 8 Supports Formats 0 2 C Supports Formats 0 1 2 9 A B M68000 FAMILY SUMMARY CPU32 REFERENCE MANUAL Table A 1 M68000 instruction Set Extensions Mnemonic Description CPU32 M68020 Bcc Supports 32 Bit Displacement Bit Field Instructions BFCHG BFCLR BFEXTS BFEXTU BFFO BFINS BFSET BFTST BGND Background Operation BKPT New Instruction Function BRA Supports 32 Bit Displacement BSR Supports 32 Bit Displacement CALLM New Instruction CAS CAS2 New Instruction Supports 32 Bit Operands New Instruction Supports Program Counter Relative Addressing New Instruction Coprocessor Instructions DIVS DIVU Supports 32 Bit and 64 Bit Operations EXTB Supports 8 Bit Extend to 32 Bits LINK Supports 32 Bit Displacement New Instruction MOVEC Supports New Control Registers MULS MULU Supports 32 Bit Operands and 64 Bit Results PACK New Instruction RTM New Instruction TBLSN TBLUN TBLS TBLU New Instruction Supports Program Counter Relative Immediate and An Addressing UNPK New Instruction New Instruction j lt gt lt gt S S S o gt S o lt gt gt S o lt gt lt gt gt S o lt g
129. GAL READY WRITE MEMORY LOCATION LS DATA NOT READY XXX NOT READY NEXT CMD CMD COMPLETE BERR AERR NEXT CMD READY Operand Data Two operands are required for this instruction The first operand is a long word ab solute address that specifies a location to which the operand data is to be written The second operand is the data Byte data is transmitted as a 16 bit word justified in the least significant byte 16 and 32 bit operands are transmitted as 16 and 32 bits respectively Result Data Successful write operations return a status of 0FFFF Bus or address errors on the write cycle are indicated by the assertion of bit 16 in the status message and by a data pattern of 0001 7 2 8 10 Dump Memory Block DUMP DUMP is used in conjunction with the READ command to dump large blocks of mem ory An initial READ is executed to set up the starting address of the block and to re trieve the first result Subsequent operands are retrieved with the DUMP command The initial address is incremented by the operand size 1 2 or 4 and saved in a tem porary register Subsequent DUMP commands use this address increment it by the current operand size and store the updated address back in the temporary register CPU32 DEVELOPMENT SUPPORT MOTOROLA REFERENCE MANUAL 7 19 NOTE The DUMP command does not check for a valid address in the tem porary register DUMP
130. K Save FEA Dn no ex 1 1 3 0 1 0 CHK Op FEA Dn no 2 0 18 X 0 0 CHK Save FEA Dn 1 1 3 0 1 0 CHK Op FEA Dn 2 2 52 x 2 1 6 JMP CEA 0 2 6 0 2 0 JSR CEA 3 2 13 0 2 2 LEA CEA An 0 0 2 0 1 0 LINK W An 2 0 10 0 2 2 LINK L An 0 0 10 0 3 2 NOP 0 0 2 0 1 0 PEA CEA 0 0 8 0 1 2 RTD 1 2 12 2 2 0 RTR 1 2 14 3 2 0 RTS 1 2 12 2 2 0 UNLK An 1 0 9 2 1 0 X There is one bus cycle for byte and word operands and two bus cycles for long operands For long bus cycles add two clocks to the tail and to the number of cycles NOTE CHk2 instruction involves a save step which other instructions do not have To calculate total the instruction time calculate the Save the effective address and the Operation execution times and combine in the order listed using the equations given in 8 1 6 Instruction Execution Time Calculation 8 3 13 Exception Related Instructions and Operations The exception related instructions and operations table indicates the number of clock periods needed for the processor to perform the specified exception related actions No additional tables are needed to calculate total effective execution time for these in structions The total number of clock cycles is outside the parentheses The numbers inside parentheses r p w are included in the total clock cycle number All timing data assumes two clock reads and writes CPU32 INSTRUCTION EXECUTIO
131. Long AND 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EFFECTIVE ADDRESS 1 1 0 0 REGISTER OPMODE MODE REGISTER Opmode Field Byte Word Long Operation 000 001 010 ea Dn Dn 100 101 110 Dn ea ea MULU Word 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EFFECTIVE ADDRESS 1 1 0 0 REGISTER 0 1 1 MODE REGISTER MULS Word 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EFFECTIVE ADDRESS 1 1 0 0 REGISTER 1 1 1 MODE REGISTER ABCD 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 0 0 REGISTER Rx 1 0 0 0 0 R M REGISTER Ry R M Field 0 Data Register to Data Register 1 Memory to Memory If R M 0 both registers must be data registers If R M 1 both registers must be address registers for Predecrement Addressing mode EXG 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 0 0 REGISTER Rx 1 OPMODE REGISTER Ry Opmode Field Specifies type of exchange 01000 Data Register Exchange 01001 Address Register Exchange 10001 Data Register Address Register Rx specifies data register Ry specifies address register MOTOROLA INSTRUCTION SET CPU32 4 184 REFERENCE MANUAL ADD 15 14 13 12 11 10 9 8 T 6 5 4 3 2 1 0 EFFECTIVE ADDRESS 1 1 0 1 REGISTER OPMODE MODE REGISTER Opmode Field
132. MANUAL 4 163 TRAP Trap Operation SSP 2 gt SSP Format Offset SSP TRAP SSP 4 gt SSP PC 5 SSP SSP 2 gt SSP SR SSP Vector Address PC Assembler Syntax TRAP lt vector Attributes Unsized Description Causes a TRAP lt vector exception A vector number is generated by adding the immediate vector operand to 32 The range of vector operand values is 0 5 thus there are 16 possible vector numbers Condition Codes Not affected Instruction Format 15 14 13 12 11 10 9 8 7 6 3 2 1 0 0 1 0 0 1 1 1 0 0 1 VECTOR Instruction Fields Vector field Specifies the trap vector to be taken MOTOROLA INSTRUCTION SET CPU32 4 164 REFERENCE MANUAL TRAPcc Trap on Condition Operation If cc then TRAP Assembler TRAPcc Syntax TRAPcc W data TRAPcc L data Attributes Unsized or Size Word Long Description TRAPcc If the specified condition is true causes a TRAPcc exception vector number 7 The address of the next instruction word current PC is pushed onto the stack If the condition is not true the processor performs no operation and execution continues with the next instruction The immediate data operand must be placed in the word s immediately following the operation word It is available to the trap han dler Condition code cc specifies one of the following conditions
133. MOTOROLA REFERENCE MANUAL 4 141 Scc Set According to Condition Code Scc Instruction Fields Condition field The binary code for one of the conditions listed in the table Effective Address field Specifies the location in which the true false byte is to be stored Only data alterable addressing modes are allowed as shown Addressing Mode Mode Register Addressing Mode Mode Register Dn 000 Reg number Dn xxx W 111 000 An xxx L 111 001 An 010 Reg number An data An 011 Reg number An An 100 Reg number An 416 101 Reg number dig PC dg An Xn 110 Reg number An dg PC Xn bd An Xn 110 Reg number An bd PC Xn NOTE A subsequent NEG B instruction with the same effective address can be used to change the Scc result from TRUE or FALSE to the equiv alent arithmetic value TRUE 1 FALSE 0 MOTOROLA INSTRUCTION SET CPU32 4 142 REFERENCE MANUAL STO Load Status Register and Stop STO P Privileged Instruction Operation If supervisor state then Immediate Data gt SR STOP else TRAP Assembler Syntax STOP data Attributes Unsized Description Moves the immediate operand into the status register both user and supervisor portions advances the program counter to point to the next instruction and stops the fetching and executing of instructions A trace interrupt or reset exce
134. MOVEM Operand 15 0 SP gt STATUS REGISTER 02 NEXT INSTRUCTION PROGRAM COUNTER HIGH NEXT INSTRUCTION PROGRAM COUNTER LOW 06 1 1 0 0 VECTOR OFFSET 08 FAULTED ADDRESS HIGH FAULTED ADDRESS LOW 0C PRE EXCEPTION STATUS REGISTER FAULTED EXCEPTION FORMAT VECTOR WORD 10 FAULTED INSTRUCTION PROGRAM COUNTER HIGH SIX WORD FRAME ONLY FAULTED INSTRUCTION PROGRAM COUNTER LOW SIX WORD FRAME ONLY 14 INTERNAL TRANSFER COUNT REGISTER 16 0 1 SPECIAL STATUS WORD Figure 6 8 Format C Four and Six Word BERR Stack MOTOROLA EXCEPTION PROCESSING CPU32 6 24 REFERENCE MANUAL SECTION 7 DEVELOPMENT SUPPORT All M68000 Family members have the following special features that facilitate applica tions development Trace on Instruction Execution All M68000 processors include an instruction by instruction tracing facility to aid in program development The MC68020 MC68030 and CPU32 can also trace those instructions that change program flow In trace mode an exception is generated after each instruction is executed allow ing a debugger program to monitor execution of a program under test See 6 2 10 Tracing for more information Breakpoint Instruction An emulator can insert software breakpoints into target code to indicate when a breakpoint occurs On the MC68010 MC68020 MC68030 and CPU32 this function is provided via illegal instructions 4848 484F that ser
135. N TIMING MOTOROLA REFERENCE MANUAL 8 21 Instruction Head Tail Cycles BKPT Acknowledged 0 0 14 1 0 0 BKPT Bus Error 0 2 35 3 2 4 Breakpoint Acknowledged 0 0 10 1 0 0 Breakpoint Bus Error 0 2 42 3 2 6 Interrupt 0 2 30 3 2 4 RESET 0 0 518 0 1 0 STOP 2 0 12 0 1 0 LPSTOP 3 2 25 0 3 1 Divide by Zero 0 2 36 2 2 6 0 2 36 2 2 6 TRAP 4 2 29 2 2 4 ILLEGAL 0 2 25 2 2 4 A line 0 2 25 2 2 4 F line First word illegal 0 2 25 2 2 4 F line Second word illegal ea Rn 1 2 31 2 3 4 F line Second word illegal ea Rn Save 1 1 3 0 1 0 F line Second word illegal ea Rn Op 4 2 29 2 2 4 Privileged 0 2 25 2 2 4 TRAPcc trap 2 2 38 2 2 6 TRAPcc no trap 2 0 4 0 1 0 TRAPcc W trap 2 2 38 2 2 6 TRAPcc W trap 0 0 4 0 2 0 TRAPcc L trap 0 2 38 2 2 6 TRAPcc L no trap 0 0 6 0 3 0 trap 2 2 38 2 2 6 no trap 2 0 4 0 1 0 Minimum interrupt acknowledge cycle time is assumed to be three clocks NOTE The F line Second word illegal operation involves a save step which other operations do not have To calculate total the operation time calculate the Save then calculate effective address and the Operation execution times Combine in the order listed using the equations given in 8 1 6 Instruction Execution Time Calculation 8 3 14 Save and Restore Operations The save and r
136. ODE REGISTER Size Field 00 Byte 01 Word 10 Long LEA 15 14 13 12 11 10 9 8 7 6 EFFECTIVE ADDRESS 1 REGISTER 1 1 1 REGISTER CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4 175 CLR 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EFFECTIVE ADDRESS 0 1 0 0 0 0 1 0 SIZE MODE REGISTER Size Field 00 Byte 01 Word 10 Long MOVE from CCR EFFECTIVE ADDRESS REGISTER EFFECTIVE ADDRESS REGISTER Size Field 00 Byte 01 Word 10 Long MOVE to CCR 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EFFECTIVE ADDRESS 0 1 0 0 0 1 0 0 1 1 MODE REGISTER NOT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EFFECTIVE ADDRESS 0 1 0 0 0 1 1 0 SIZE MODE REGISTER Size Field 00 Byte 01 Word 10 Long MOVE to SR EFFECTIVE ADDRESS REGISTER EFFECTIVE ADDRESS REGISTER MOTOROLA INSTRUCTION SET CPU32 4 176 REFERENCE MANUAL LINK Long 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 0 0 1 0 0 0 0 0 0 0 1 REGISTER HIGH ORD
137. ON SET CPU32 4 166 REFERENCE MANUAL TST Test an Operand TST Operation Destination Tested Condition Codes Assembler Syntax TST ea Attributes Size Byte Word Long Description Compares the operand with zero and sets condition codes accord ing to the results of the test Condition Codes X N 2 d 0 0 X Not affected N Set if the operand is negative Cleared otherwise Z Set if the operand is zero Cleared otherwise V Always cleared Always cleared Instruction Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EFFECTIVE ADDRESS 0 1 0 0 1 0 1 0 SIZE MODE REGISTER Instruction Fields Size field Specifies the size of the operation 00 Byte operation 01 Word operation 10 Long operation CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4 167 TST Test an Operand TST Effective Address field Specifies the destination operand All addressing modes are allowed as shown Addressing Mode Mode Register Addressing Mode Mode Register Dn 000 Reg number Dn xxx W 111 000 An 001 Reg number An xxx L 111 001 An 010 Reg number An data 111 100 An 011 Reg number An An 100 Reg number An 416 An 101 Reg number An dig PC 111 010 dg An Xn 110 Reg number An dg PC Xn 111 011 bd An Xn 110 Reg number An bd PC Xn 111 011 Word or long word operation o
138. Only control addressing modes are allowed as shown Addressing Mode Mode Register Addressing Mode Mode Register Dn xxx W 111 000 An xxx L 111 001 An 010 Reg number An data An An Er m 416 101 Reg number dig PC 111 010 dg An Xn 110 Reg number An dg PC Xn 111 011 bd An Xn 110 Reg number An PC Xn 111 011 Size field Specifies the size of operation 00 byte operation 01 word operation 10 long operation Register field Specifies the destination data register Dx On entry the register contains the interpolation fraction and entry number Dyn field If the effective address mode field is nonzero this operand register is unused and should be zero If the effective address mode field is zero the surface interpolation variant of this instruction is implied and Dyn specifies one of the two source operands Rounding mode field The R bit controls rounding of the final result When R the result is rounded according to the round to nearest algorithm When R 1 the result is returned unrounded CPU32 REFERENCE MANUAL INSTRUCTION SET MOTOROLA 4 157 TB L U Table Lookup and Interpolate Unsigned TB L U TBLUN TBLUN Operation Rounded ENTRY n ENTRY i ENTRY n Dx 7 0 256 Dx Unrounded ENTRY n 256 ENTRY 1 7 ENTRY n 7 0
139. PU32 4 82 REFERENCE MANUAL L EA Load Effective Address L EA Operation ea An Assembler Syntax LEA ea An Attributes Size Long Description Loads the effective address into the specified address register All 32 bits of the address register are affected by this instruction Condition Codes Not affected Instruction Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EFFECTIVE ADDRESS 0 1 0 0 REGISTER 1 1 1 MODE REGISTER Instruction Fields Register field Specifies the address register to be updated with the effective address Effective Address field Specifies the address to be loaded into the address regis ter Only control addressing modes are allowed as shown Addressing Mode Mode Register Addressing Mode Mode Register Dn xxx W 111 000 An xxx L 111 001 An 010 Reg number An data E An An 416 101 Reg number dig PC 111 010 dg An Xn 110 Reg number An dg PC Xn 111 011 bd An Xn 110 Reg number An bd PC Xn 111 011 CPUS2 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4 83 LINK Link and Allocate LINK Operation Sp 4 gt Sp An 5 SP SP An SP SP Assembler Syntax LINK An displacement Attributes Size Word Long Description Pushes the contents of the specified address register onto the stack then
140. Power Stop Instruction 2 1 6 1 1 7 Processing States 10 5 au tech ou Re ete bte cus 1 6 1 1 8 Privilege States ea 1 6 1 2 Block e a E 1 6 SECTION 2ARCHITECTURE SUMMARY 2 1 Programming Model 2 1 2 2 lisez EE 2 2 2 9 Detar VOCS oca CHA LLLA A 2 3 2 3 1 Organization in 2 4 2 3 1 1 Data Registers UL let tU dde uU 2 4 2 3 1 2 Address Registers eese 2 5 2 3 1 3 Control Registers s 2 5 2 3 2 Organization in 2 6 SECTION 3 DATA ORGANIZATION AND ADDRESSING CAPABILITIES 3 1 Program Data References 3 1 3 2 Notation Conventions edt eoo ede dee DU RIDE PL babens 3 2 3 3 Irriplicit ope oie beet e dde ar eua ed ted Ei 3 2 3 4 Effective Address c te ceed 3 3 3 4 1 Register Direct 3 3 3 4 1 1 Data Register Direct o5 auctae 3 3 3 4 1 2 Address Register proba rax ape tu 3 3 3 4 2 Memory Addressing Modes Po etti 3 4 3 4 2 1 Address Register 2 0411 3 4 3 4 2 2 Address Register Indirect With Postincrement
141. R ADDRESS OTHERWISE BEGIN INSTRUCTION ERROR EXECUTION DOUBLE BUS FAULT ASSERT HALT EXIT Figure 6 2 Reset Operation Flowchart EXIT 6 2 2 Bus Error A bus error exception occurs when an assertion of the BERR signal is acknowledged The BERR signal can be asserted by one of three sources 1 External logic by assertion of the BERR input pin 2 Direct assertion of the internal BERR signal by an internal module 3 Direct assertion of the internal BERR signal by the on chip hardware watchdog after detecting a no response condition Bus error exception processing begins when the processor attempts to use informa tion from an aborted bus cycle MOTOROLA EXCEPTION PROCESSING CPU32 6 6 REFERENCE MANUAL When the aborted bus cycle is an instruction prefetch the processor will not initiate exception processing unless the prefetched information is used For example if a branch instruction flushes an aborted prefetch that word is not accessed and no ex ception occurs When the aborted bus cycle is a data access the processor initiates exception pro cessing immediately except in the case of released operand writes Released write bus errors are delayed until the next instruction boundary or until another operand ac cess is attempted Exception processing for bus error exceptions follows the regular sequence but con text preservation is more involved than for other exceptions because a bus exception can be initiat
142. REFERENCE MANUAL 2 Check Register Against Bounds 2 Operation If Rn lt lower bound or Rn gt upper bound then TRAP Assembler Syntax 2 ea Rn Attributes Size Byte Word Long Description Compares the value in Rn to each bound The effective address contains the bounds pair the lower bound followed by the upper bound For signed comparisons the arithmetically smaller value should be used as the lower bound For unsigned comparisons the logically smaller value should be the lower bound The size of both data and the bounds can be specified as byte word or long If Rn is a data register and the operation size is byte or word only the appropriate low order part of Rn is checked If Rn is an address register and the operation size is byte or word the bounds operands are sign extended to 32 bits and the resultant operands are compared to the full 32 bits of An If the upper bound equals the lower bound the valid range is a single value If the register value is less than the lower bound or greater than the upper bound a CHK instruction exception vector number 6 occurs Condition Codes x N 7 V e Tor U U X Not affected N Undefined Z Set if Rn is equal to either bound Cleared otherwise V Undefined C Set if Rn is out of bounds Cleared otherwise CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4 51 CHK2 Instruction Format Check Register Against Bounds
143. RENCE MANUAL 5 U BX Subtract with Extend 5 U BX Operation Destination Source X Destination Assembler SUBX Dx Dy Syntax SUBX Ax Ay Attributes Size Byte Word Long Description Subtracts the source operand and the extend bit from the destination operand and stores the result in the destination location The instruction has two modes 1 Register to register Data registers specified by the instruction contain the op erands 2 Memory to memory Address registers specified by the instruction access op erands from memory using predecrement addressing mode Condition Codes x N 7 V Set to the value of the carry bit Set if the result is negative Cleared otherwise Cleared if the result is nonzero Unchanged otherwise Set if an overflow occurs Cleared otherwise Set if a carry occurs Cleared otherwise O lt NZ amp NOTE Normally the Z condition code bit is set via programming before the start of an operation This allows successful tests for zero results upon completion of multiple precision operations CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4 151 5 U BX Subtract with Extend 5 U BX Instruction Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 0 1 REGISTER Rx 1 SIZE 0 0 R M REGISTER Ry Instruction Fields Register Dy Ay field Specifies the destination register R M 0 specifies a data register If R M 1 specifies an add
144. RESULT RESULT LONG RESULT RESULT RESULT RESULT If R 1 TABLUN the result is returned in register Dx without rounding If the size is byte the integer portion of the result is returned in Dx 15 8 The integer portion of a word result is stored in Dx 23 8 The least significant 24 bits of a long result are stored in Dx 31 8 Byte and word results are zero extended to fill the entire 32 bit register 31 24 23 16 15 87 0 BYTE ZERO EXTENDED ZERO EXTENDED RESULT FRACTION WORD ZERO EXTENDED RESULT RESULT FRACTION LONG RESULT RESULT RESULT FRACTION NOTE A long word result contains only the least significant 24 bits of integer precision INSTRUCTION SET MOTOROLA 4 159 TB L U Table Lookup and Interpolate Unsigned TB L U TBLUN TBLUN For all sizes the 8 bit fractional portion of the result is returned in the low byte of the data register Dx 7 0 User software can make use of the fractional data to re duce cumulative errors in lengthy calculations or implement rounding algorithms different from those provided by other forms of TBLU The assumed radix point de scribed previously places two restrictions on the programmer 1 Tables are limited to 257 entries in length 2 Interpolation resolution is limited to 1 256 the distance between consecutive ta ble entries The assumed radix point should not however be construed by the programmer as a requirement that the independent variable be calculated as a
145. RUCTION SET MOTOROLA REFERENCE MANUAL 4 147 SU Subtract Immediate SU Instruction Fields Size field Specifies the size of the operation 00 Byte operation 01 Word operation 10 Long operation Effective Address field Specifies the destination operand Only data alterable addressing modes are allowed as shown Addressing Mode Mode Register Addressing Mode Mode Register Dn 000 Reg number Dn xxx W 111 000 An xxx L 111 001 An 010 Reg number An data An 011 Reg number An An 100 Reg number An 416 101 Reg number dig PC dg An Xn 110 Reg number An dg PC Xn bd An Xn 110 Reg number An bd PC Xn I Immediate field Data immediately following the instruction If size 00 the data is the low order byte of the immediate word If size 01 the data is the entire immediate word If size 10 the data is the next two immediate words MOTOROLA INSTRUCTION SET CPU32 4 148 REFERENCE MANUAL SU BQ Subtract Quick SU BQ Operation Destination Immediate Data Destination Assembler Syntax SUBQ data ea Attributes Size Byte Word Long Description Subtracts the immediate data 1 8 from the destination operand Only word and long operations are allowed with address registers and the condition codes are not affected When subtracting from address registers
146. Ret rning from BDM oa PERLE 7 7 7 2 7 SerrabInmterfaoE oat ea eat 7 7 7 2 7 1 CPU Serial LOGI coe teh ds ee 7 8 7 2 7 2 Development System Serial Logic 7 10 MOTOROLA CPU32 viii REFERENCE MANUAL TABLE OF CONTENTS Continued Paragraph Title Page 7 2 8 COMMANG SOP er 7 11 7 2 8 1 Command Format o see cope eros 7 11 7 2 8 2 Command Sequence Diagram 7 12 7 2 8 3 Command Set Summary sss 7 14 7 2 8 4 Read A D Register RAREG RDREG 7 15 7 2 8 5 Write A D Register WAREG WDREG 7 15 7 2 8 6 Read System Register RSREG 7 16 7 2 8 7 Write System Register WSREG 7 16 7 2 8 8 Read Memory Location READ 7 17 7 2 8 9 Write Memory Location WRITE 7 18 7 2 8 10 Dump Memory Block DUMP 7 19 7 2 8 11 Fill Memory Block FILL 200 7 21 7 2 8 12 Resume Execution GO eo esrb ces ees des 7 22 7 2 8 13 Call User Code CALL 7 22 7 2 8 14 Reset Peripherals RST
147. Rotate left Effective Address field Specifies the operand to be rotated Only memory alterable addressing modes are allowed as shown Addressing Mode Mode Register Addressing Mode Mode Register Dn xxx W 111 000 An xxx L 111 001 An 010 Reg number An data An 011 Reg number An An 100 Reg number An 416 101 Reg number dig PC mE dg An Xn 110 Reg number An dg PC Xn bd An Xn 110 Reg number An bd PC Xn CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4 135 RTD Return and Deallocate RTD Operation SP gt PC SP 4 d SP Assembler Syntax RTD displacement Attributes Unsized Description Pulls the program counter value from the stack and adds the sign extended 16 bit displacement value to the stack pointer The previous program counter value is lost Condition Codes Not affected Instruction Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 0 0 1 1 1 0 0 1 1 1 0 1 0 0 DISPLACEMENT 16 BITS Instruction Field Displacement field Specifies the twos complement integer to be sign extended and added to the stack pointer MOTOROLA INSTRUCTION SET CPU32 4 136 REFERENCE MANUAL RTE Return from Exception RTE Privileged Instruction Operation If supervisor state then SP 2 SR SP 2 gt SP SP
148. SS 0 0 0 0 REGISTER 1 1 1 MODE REGISTER Instruction Fields Bit Number Dynamic Register field Specifies the data register that contains the bit number Effective Address field Specifies the destination location Only data alterable addressing modes are allowed as shown Addressing Mode Mode Register Addressing Mode Mode Register Dn 000 Reg number Dn xxx W 111 000 An xxx L 111 001 An 010 Reg number An data An 011 Reg number An An 100 Reg number An dig 101 Reg number An 916 PC dg An Xn 110 Reg number An dg PC Xn bd An Xn 110 Reg number An bd PC Xn Long only all others are byte only CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4 45 BSR Branch to Subroutine BSR Operation SP 4 gt SP PC gt SP PC d gt PC Assembler Syntax BSR label Attributes Size Byte Word Long Description Pushes the long word address of the instruction immediately follow ing the BSR instruction onto the system stack The PC contains the address of the instruction word plus two Program execution then continues at location PC dis placement The displacement is a twos complement integer that represents the rela tive distance in bytes from the current PC to the destination PC If the 8 bit displacement field in the instruction word is
149. Save Rn CEA 1 1 3 0 1 0 MOVES Op Rn CEA 9 2 12 0 1 X MOVE USP An 0 0 2 0 1 0 MOVE An USP 0 0 2 0 1 0 SWAP Dn 4 0 6 0 1 0 X There is one bus cycle for byte and word operands and two bus cycles for long operands For long bus cycles add two clocks to the tail and to the number of cycles 1 bus cycle may take up to four clocks without increasing total execution time Cr Control registers USP VBR SFC and DFC n Number of registers to transfer RL Register List lt Maximum time certain data or mode combinations may execute faster NOTE The MOVES instruction has an additional a save step which other instructions do not have To calculate total the instruction time calculate the Save the effective address and the Operation execution times and combine in the order listed using the equations given in 8 1 6 Instruction Execution Time Calculation 8 3 5 Arithmetic Logic Instructions The arithmetic logic instruction table indicates the number of clock periods needed to perform the specified arithmetic logical instruction using the specified addressing mode Footnotes indicate when to account for the appropriate effective address times The total number of clock cycles is outside the parentheses The numbers inside pa rentheses r p w are included in the total clock cycle number All timing data assumes two clock reads and writes CPU32 INSTRUCTION EXECUTION TIMING MOTOROLA REFERENCE MANUAL 8 15
150. TCH PARALLEL IN SERIAL OUT STATUS lt lt PARALLEL IN SERIAL OUT EXECUTION lt lt Y SYNCHRONIZE STATUS DATA MICROSEQUENCER CONTROL DSCLK CONTROL SERIAL LOGIC LOGIC CLOCK Figure 7 5 Debug Serial I O Block Diagram MOTOROLA DEVELOPMENT SUPPORT CPU32 7 8 RESULT LATCH SERIAL IN PARALLEL OUT REFERENCE MANUAL Both DSCLK and DSI are synchronized to on chip clocks thereby minimizing the chance of propagating metastable states into the serial state machine Data is sam pled during the high phase of CLKOUT At the falling edge of CLKOUT the sampled value is made available to internal logic If there is no synchronization between CPU32 and development system hardware the minimum hold time on DSI with respect to DSCLK is one full period of CLKOUT CLKOUT FREEZE DSCLK DSI SAMPLE WINDOW INTERNAL SYNCHRONIZED DSCLK INTERNAL SYNCHRONIZED DSI DSO Figure 7 6 Serial Interface Timing Diagram The serial state machine begins a sequence of events based on the rising edge of the synchronized DSCLK see Figure 7 6 Synchronized serial data is transferred to the input shift register and the received bit counter is decremented One half clock period later the output shift register is updated bringing the next output bit to the DSO signal DSO changes relative to the rising edge of DSCLK and does not necessarily remain sta
151. V Always cleared Always cleared Instruction Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EFFECTIVE ADDRESS 1 1 0 0 REGISTER OPMODE MODE REGISTER Instruction Fields Register field Specifies any of the eight data registers Opmode field Byte Word Long Operation 000 001 010 ea Dn 2 Dn 100 101 110 Dn 2 ea MOTOROLA INSTRUCTION SET CPU32 4 122 REFERENCE MANUAL OR Inclusive Logical OR addressing modes are allowed as shown OR Effective Address field If the location specified is a source operand only data Addressing Mode Mode Register Addressing Mode Mode Register Dn 000 Reg number Dn xxx W 111 000 An xxx L 111 001 An 010 Reg number An data 111 100 An 011 Reg number An An 100 Reg number An 416 An 101 Reg number An dig PC 111 010 dg An Xn 110 Reg number An dg PC Xn 111 011 bd An Xn 110 Reg number An bd PC Xn 111 011 If the location specified is a destination operand only memory alterable addressing modes are allowed as shown Addressing Mode Mode Register Addressing Mode Mode Register Dn xxx W 111 000 An xxx L 111 001 An 010 Reg number An data An 011 Reg number An An 100 Reg number An 416 101 Reg number dig PC dg An Xn 1
152. XXX NEXT CMD XXX NEXT CMD ILLEGAL NOT READY MS RESULT LS RESULT XXX NEXT CMD BERR AERR NOT READY Operand Data The single operand is the long word address of the requested memory location Result Data The requested data is returned as either a word or long word Byte data is returned in the least significant byte of a word result with the upper byte cleared Word re sults return 16 bits of significant data long word results return 32 bits A successful read operation returns data bit 16 cleared If a bus or address error is encountered the returned data is 10001 7 2 8 9 Write Memory Location WRITE Write the operand data to the memory location specified by the long word address The destination function code DFC register determines the address space accessed Only absolute addressing is supported Valid data sizes include byte word and long word Command Format 15 14 13 12 11 10 9 8 7 6 5 4 3 0 0 0 1 1 0 0 0 OP SIZE 0 0 0 0 0 Command Sequence MOTOROLA DEVELOPMENT SUPPORT CPU32 7 18 REFERENCE MANUAL WRITE BW MS ADDR LS ADDR DATA 777 READY gt READY gt N NOT READY VOCATION NOT READY XXX NEXT CMD NEXT CMD ILLEGAL NOT READY CMD COMPLETE BERR AERR NEXT CMD READY WRITE LONG MS ADDR LS ADDR MS DATA 22 NOT READY NOT READY NOT READY XXX NEXT CMD ILLE
153. Y Number Value Value 128 32768 1311 162 41472 1659 163 41728 1669 164 41984 1679 165 42240 1690 192 49152 1966 These values are the end points of the range All entries between these points fall on the line The table instruction is executed with the following bit pattern in Dx 31 NOT USED 16 15 10 1 00011 0 10000000 Table Entry Offset Dx 8 15 A3 163 Interpolation Fraction Dx 0 7 80 128 Using this information the table instruction calculates dependent variable Y Y 1669 128 1679 1669 256 1674 4 6 2 Table Example 2 Compressed Table DEPENDENT VARIABLE 256 512 X 786 INDEPENDENT VARIABLE Figure 4 4 Table Example 2 CPU32 REFERENCE MANUAL INSTRUCTION SET MOTOROLA 4 189 In Example 2 the data from Example 1 has been compressed by limiting the maximum value of the independent variable Instead of the range 0 lt X 65535 X is limited to 0 lt X x 1023 The table has been compressed to only 5 entries but up to 256 levels of interpolation are allowed between entries CAUTION Extreme table compression with many levels of interpolation is pos sible only with highly linear functions The table entries within the range of interest are as follows Entry X Y Number Value Value 1966 Since the table is reduced from 257 to 5 entries independent variable X must be scaled appropriately In this case the scaling
154. ack the active supervisor stack pointer is incremented by 12 and normal instruction execution resumes For a bus fault frame the format value on the stack is first checked for validity In ad dition the version number on the stack must match the version number of the proces sor that is attempting to read the stack frame The version number is located in the most significant byte bits 15 8 of the internal register word at location SP 14 in the stack frame The validity check insures that stack frame data will be properly inter preted in multiprocessor systems If a frame is invalid a format error exception is taken If it is inaccessible a bus error exception is taken Otherwise the processor reads the entire frame into the proper in ternal registers de allocates the stack 12 words and resumes normal processing Bus error frames for faults during exception processing require the RTE instruction to rewrite the faulted stack frame If an error occurs during any of the bus cycles required by rewrite the processor halts If a format error occurs during RTE execution the processor creates a normal four word fault stack frame below the frame that it was attempting to use If a bus error oc curs a bus error stack frame will be created The faulty stack frame remains intact so that it may be examined and repaired by an exception handler or used by a different type of processor e g an MC68010 MC68020 or a future M68000 processor
155. address field The instruction tests the current value of the operand and sets the N and Z con dition bits appropriately TAS also sets the high order bit of the operand The opera tion uses a read modify write memory cycle that completes the operation without interruption This instruction supports use of a flag to coordinate several processors Condition Codes X N 2 V __ 0 0 X Not affected N Set if the most significant bit of the operand is currently set Cleared otherwise Z Set if the operand was zero Cleared otherwise V Always cleared C Always cleared Instruction Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EFFECTIVE ADDRESS 0 1 0 0 1 0 1 0 1 1 MODE REGISTER MOTOROLA INSTRUCTION SET CPU32 4 162 REFERENCE MANUAL TAS Test and Set an Operand TAS Instruction Fields Effective Address field Specifies the location of the tested oper and Only data alterable addressing modes are allowed as shown Addressing Mode Mode Register Addressing Mode Mode Register Dn 000 Reg number Dn xxx W 111 000 An xxx L 111 001 An 010 Reg number An data An 011 Reg number An An 100 Reg number An 416 101 Reg number dig PC dg 110 Reg number An dg PC Xn bd An Xn 110 Reg number An bd PC Xn CPU32 INSTRUCTION SET MOTOROLA REFERENCE
156. address times The number of bits shifted does not affect the execution time unless noted The total number of clock cycles is outside the parentheses The numbers inside parentheses r p w are includ ed in the total clock cycle number All timing data assumes two clock reads and writes Instruction Head Tail Cycles Note LSd Dn Dm 2 0 0 1 0 1 LSd Dm 4 0 6 0 1 0 LSd FEA 0 2 6 0 1 1 ASd Dn Dm 2 0 0 1 0 1 Dm 4 0 6 0 1 0 ASd FEA 0 2 6 0 1 1 ROd Dn Dm 2 0 0 1 0 1 ROd Dm 4 0 6 0 1 0 ROd FEA 0 2 6 0 1 1 ROXd Dn Dm 2 0 0 1 0 2 ROXd Dm 2 0 0 1 0 3 ROXd FEA 0 2 6 0 1 1 NOTES 1 Head and cycle times can be calculated as follows Max 3 n 4 mod n 4 mod n 4 mod n 4 1 2 6 or derived from the following table 2 Head and cycle times are calculated as follows count x 63 max 3 n mod n 1 2 6 3 Head and cycle times are calculated as follows count x 8 max 2 n mod n 2 6 d Direction left or right Clocks Shift Counts 6 0 1 2 3 4 5 6 8 9 12 8 7 10 11 13 14 16 17 20 10 15 18 19 21 22 24 25 28 12 23 26 27 29 30 32 33 36 14 31 34 35 37 38 40 41 44 16 39 42 43 45 46 48 49 52 18 47 50 51 53 54 56 57 60 20 55 58 59 61 62 22 63 CPU32 INSTRUCTION EXECUTION TIMING MOTOROLA REFERENCE MANUAL 8 19 8 3 10 Bit Manip
157. addressing mode R M field Specifies the operand addressing mode 0 The operation is data register to data register 1 The operation is memory to memory Register Dx Ax field Specifies the source register If R M 0 specifies a data register If R M 1 specifies an address register for the predecrement addressing mode MOTOROLA INSTRUCTION SET CPU32 4 140 REFERENCE MANUAL Scc Set According to Condition Code Operation If Condition True then set Destination else clear Destination Scc Assembler Syntax Scc ea Attributes Size Byte Description Tests the specified condition code If the condition is true sets all bits in the byte specified to 1 TRUE Otherwise clears all bits to 0 FALSE Condi tion code cc specifies one of the following conditions cc Name Code Description cc Name Code Description CC Carry Clear 0100 LS Low or Same 0011 2 CS Carry Set 0101 C LT Less Than 1101 N eV N eV EQ Equal 0111 Z MI Minus 1011 N F Never equal 0001 0 E Not Equal 0110 Z GE Greater Equal 1100 NeV N eV PL Plus 1010 N GT Greater Than 1110 NeVeZNeVeZ T Always true 0000 HI High 0010 Caz Overflow Clear 1000 V LE Less or Equal 1111 ZNeVNeV E Overflow Set 1001 V Condition Codes Not affected Instruction Format 15 14 13 12 11 10 9 8 6 5 4 3 2 1 0 EFFECTIVE ADDRESS 0 1 0 1 CONDITION 1 MODE REGISTER CPU32 INSTRUCTION SET
158. akpoint instruction is executed the CPU32 performs a read from CPU space 0 at a location corresponding to the breakpoint number See 5 3 Types of Ad dress Space If this bus cycle is terminated by BERR the processor performs illegal instruction exception processing If the bus cycle is terminated by DSACK the proces sor uses the data returned to replace the breakpoint in the instruction pipeline and be gins execution of that instruction 6 2 6 Hardware Breakpoints The CPU32 recognizes hardware breakpoint requests Hardware breakpoint requests do not force immediate exception processing but are left pending An instruction MOTOROLA EXCEPTION PROCESSING CPU32 6 8 REFERENCE MANUAL breakpoint is not made pending until the instruction corresponding to the request is ex ecuted A pending breakpoint can be acknowledged between instructions or at the end of ex ception processing To acknowledge a breakpoint the CPU performs a read from CPU space 0 at location 1E See 5 3 Types of Address Space for a detailed description of CPU space operations If the bus cycle terminates normally instruction execution continues with the next in struction as if no breakpoint request occurred If the bus cycle is terminated by BERR the CPU begins exception processing Data returned during this bus cycle is ignored Exception processing follows the regular sequence Vector number 12 offset 30 is internally generated The program counter
159. amily Addressing Capability 3 14 M68000 Family Compatibility 4 1 Memory CPU32 REFERENCE MANUAL Addressing Modes 3 4 Indirect Addressing 3 4 Organization 2 6 Virtual 1 2 Microbus Controller 8 3 Microsequencer 8 1 Model Programming 2 1 Move Instruction Timing 8 14 Move Instruction Special Purpose Timing 8 14 Multiple Exceptions 6 4 N Negative Tails 8 6 Organization in Memory 2 6 Normal Processing State 5 1 Notation Conventions Addressing 3 2 Notation Instruction Set 4 3 Opcode Tracking during Loop Mode 7 27 Opcode Tracking in Background Mode 7 2 7 25 Organization Memory 2 6 Registers 2 4 Overlap 8 4 Pipeline Sync with the NOP Instruction 4 194 Prefetch Controller 8 3 Priority Exception 6 4 Interrupt 6 12 Privilege Levels 5 1 Changing 5 2 Supervisor 5 2 User 5 2 Privilege Violations 6 10 Processing of Specific Exceptions 6 5 Processing States 5 1 Program and Data References 3 1 5 3 Program Control Branch Instructions 4 10 Program Counter Indirect with Displacement Mode 3 7 Index 8 Bit Displacement 3 7 3 8 Index Base Displacement 3 8 Programming Model 2 1 Programming View of Addressing Modes 3 11 Queues 3 17 282 References Data 3 1 CPU32 REFERENCE MANUAL INDEX Implicit 3 2 Program 3 1 Register Direct Mode 3 3 Registers Address 2 5 Condition Code 2 3 4 5 Control 2 5 Data 2 4 Function Code 2 3 Organization 2 2 Status 2 3 Vector Base 2 3 6 1 Re
160. an be classified as follows Data A data addressing EA mode refers to data operands Memory A memory addressing EA mode refers to memory operands Alterable An alterable addressing EA mode refers to writable operands Control A control addressing EA mode refers to unsized memory operands Categories are sometimes combined forming new more restrictive categories Two examples are alterable memory or alterable data The former refers to addressing modes that are both alterable and memory addresses the latter refers to addressing modes that are both alterable and data addresses Table 3 1 shows categories to which each of the EA modes belong MOTOROLA DATA ORGANIZATION AND ADDRESSING CAPABILITIES CPU32 3 10 REFERENCE MANUAL 3 5 Programming View of Addressing Modes Extensions to indexed addressing modes indirection and full 32 bit displacements provide additional programming capabilities for the CPU32 The following paragraphs describe addressing techniques and summarize addressing modes from a program ming point of view Table 3 1 Effective Addressing Mode Categories Addressing Mode Code Register Data Memory Control Alterable Syntax Data Register Direct 000 reg no X X Dn Address Register Direct 001 reg no X An Address Register Indirect 010 reg no X X X X An Address Register Indirect 011 reg no X X X An with Postincrement Address Register Indirect 100 reg no X X
161. at field allows an RTE instruction to identify stack infor mation so that it can be properly restored The general form of the exception stack frame is illustrated in Figure 6 1 Although some formats are peculiar to a particular M68000 Family processor format 0000 is al ways legal and always indicates that only the first four words of a frame are present See 6 4 CPU32 Stack Frames for a complete discussion of exception stack frames CPU32 EXCEPTION PROCESSING MOTOROLA REFERENCE MANUAL 6 3 SP AFTER STACKING gt STATUS REGISTER PROGRAM COUNTER HIGH PROGRAM COUNTER LOW FORMAT VECTOR OFFSET OTHER PROCESSOR STATE INFORMATION DEPENDING ON EXCEPTION 0 2 OR 8 WORDS HIGHER ADDRESSES STACKING ORDER Figure 6 1 Exception Stack Frame 6 1 5 Multiple Exceptions Each exception has been assigned a priority based on its relative importance to sys tem operation Priority assignments are shown in Table 6 2 Group 0 exceptions have the highest priorities Group 4 exceptions have the lowest priorities Exception pro cessing for exceptions that occur simultaneously is done by priority from highest to lowest Table 6 2 Exception Priority Groups Group Exception and Characteristics Priority Relative Priority 0 Reset Aborts all processing instruction or exception does not save old context 1 1 Address Error Suspends processing instruction or 1 2 Bus Error exception saves internal
162. ax Size Operation RESET none none Assert RESET line RTE none none SP SR SP 2 gt SP SP 2 PC SP 4 SP restore stack according to format STOP 16 Data SR STOP LPSTOP data none Data SR interrupt mask EBI STOP Trap Generating BKPT data none If breakpoint cycle acknowledged then execute returned operation word else trap as illegal instruction BGND none none If background mode enabled then enter background mode else format vector offset gt SSP PC SSP SR 5 SSP vector gt PC CHK ea Dn 16 32 If Dn 0 or Dn ea then CHK exception CHK2 ea Rn 8 16 32 If Rn lower bound or Rn upper bound then CHK exception ILLEGAL none none SSP 2 gt SSP vector offset SSP SSP 4 2 SSP PC 2 SSP SSP 2 SSP SR 5 SSP Illegal instruction vector address PC TRAP SSP 2 2 SSP format vector offset SSP SSP 4 SSP PC 5 SSP SR 5 SSP vector address PC TRAPcc none none If cc true then TRAP exception data 16 32 TRAPV none none If V set then overflow TRAP exception Condition Code Register ANDI data CCR 8 Data e CCR gt CCR EORI data CCR 8 Data 6 CCR CCR MOVE ea CCR 16 Source gt CCR CCR ea 16 CCR o Destination ORI data CCR 8 Data CCR 5 CCR 4 3 10 Condition Tests Conditional program control instructions and the TRAPcc instruction execute on the basis of condition tes
163. ber of cycles available at the beginning of an instruction to com plete a previous instruction write or to perform a prefetch Tail The number of cycles an instruction uses to complete a write Cycles Four numbers per entry three contained in parentheses The outer number is the minimum number of cycles required for the in struction to complete Numbers within the parentheses represent the number of bus accesses performed by the instruction The first number is the number of operand read accesses performed by the instruction The second number is the number of instruction fetches performed by the instruction including all prefetches that keep the instruction and the instruction pipeline filled The third number is the number of write accesses performed by the in struction As an example consider an ADD L 12 A3 D7 W 4 D2 instruction Section 8 3 5 Arithmetic Logic Instructions shows that the instruction has a head 0 a tail 0 and cycles 2 0 1 0 However in indexed address register Indirect ad dressing mode additional time is required to fetch the effective address Section 8 3 1 Fetch Effective Address gives addressing mode data For dg An Xn Sz Scale head 4 tail 2 cycles 8 2 1 0 Because this example is for a long access and the FEA table lists data for word accesses add two clocks to the tail and to the number of cycles X table notation to obtain head 4 tail 4 cycles 10 2
164. ble until the falling edge of DSCLK One clock period after the synchronized DSCLK has been seen internally the updated counter value is checked If the counter has reached zero the receive data latch is up dated from the input shift register At this same time the output shift register is reload ed with the not ready come again response Once the receive data latch has been loaded the CPU is released to act on the new data Response data overwrites the not ready response when the CPU has completed the current operation Data written into the output shift register appears immediately on the DSO signal In general this action changes the state of the signal from a high not ready response status bit to a low valid data status bit logic level However this level change only occurs if the command completes successfully Error conditions overwrite the not ready response with the appropriate response that also has the status bit set CPU32 DEVELOPMENT SUPPORT MOTOROLA REFERENCE MANUAL 7 9 A user can use the state change on DSO to signal hardware that the next serial trans fer may begin A time out of sufficient length to trap error conditions that do not change the state of DSO should also be incorporated into the design Hardware interlocks in the CPU prevent result data from corrupting serial transfers in progress 7 2 7 2 Development System Serial Logic The development system as the master of the serial data link must suppl
165. bus cycle PCC will contain 00000001 if BDM is entered via a double bus fault immedi ately out of reset 7 2 6 Returning from BDM BDM is terminated when a resume execution GO or call user code CALL command is received Both GO and CALL flush the instruction pipeline and refetch instructions from the location pointed to by the RPC The return PC and the memory space referred to by the status register SUPV bit reflect any changes made during BDM FREEZE is negated prior to initiating the first prefetch Upon negation of FREEZE the serial subsystem is disabled and the signals revert to IPIPE IFETCH functionality 7 2 7 Serial Interface Communication with the CPU32 during BDM occurs via a dedicated serial interface which shares pins with other development features The BKPT signal becomes the se rial clock DSCLK serial input data DSI is received on IFETCH and serial output data DSO is transmitted on IPIPE The serial interface uses a full duplex synchronous protocol similar to the serial pe ripheral interface SPI protocol The development system serves as the master of the serial link since it is responsible for the generation of DSCLK If DSCLK is derived from the CPU32 system clock development system serial logic is unhindered by the oper ating frequency of the target processor Operable frequency range of the serial clock is from DC to one half the processor system clock frequency The serial interface o
166. by IFETCH Proper tracking of bus cycles via the IFETCH signal on a fast bus requires a simple state machine On a two clock bus IFETCH may signal a pipeline flush with associat ed prefetch followed immediately by a second prefetch That is IFETCH remains as serted for three clocks two clocks indicating the flush fetch and a third clock signaling the second fetch These two operations are easily discerned if the tracking logic sam ples IFETCH on the two rising edges of CLKOUT which follow the address strobe da ta strobe during show cycles falling edge Three clock and slower bus cycles allow time for negation of the signal between consecutive indications and do not experience this operation 7 3 2 Instruction Pipe IPIPE The internal instruction pipeline can be modeled as a three stage FIFO see Figure 7 11 Stage A is an input buffer data can be used out of the stages B and C IPIPE signals advances of instructions in the pipeline Instruction register A IRA holds incoming words as they are prefetched No decoding takes place in the buffer Instruction register B IRB provides initial decoding of the opcode and decoding of extension words it is a source of immediate data Instruc tion register C IRC supplies residual opcode decoding during instruction execution CPU32 DEVELOPMENT SUPPORT MOTOROLA REFERENCE MANUAL 7 25 DATA BUS EXTENSION OPCODES WORDS RESIDUAL Figure 7 11 Functional Model o
167. cept a new serial transfer with eight system clock periods In the third cycle the development system supplies the low order 16 bits of a memory address The CPU always returns the not ready response in this cycle At the com pletion of the third cycle the CPU initiates a memory read operation Any serial trans fers that begin while the memory access is in progress return the not ready response Results are returned in the two serial transfer cycles following the completion of mem ory access The data transmitted to the CPU during the final transfer is the opcode for the following command Should a memory access generate either a bus or address error an error status is returned in place of the result data COMMANDS TRANSMITTED TO THE CPU r COMMAND CODE TRANSMITTED DURING THIS CYCLE r HIGH ORDER 16 BITS OF MEMORY ADDRESS r LOW ORDER 16 BITS OF MEMORY ADDRESS NONSERIAL RELATED ACTIVITY SEQUENCE TAKEN IF OPERATION HAS NOT COMPLETED NEXT COMMAND Y XXX CODE NOT READY XXX NEXT CMD gt MS RESULT LS RESULT READ MEMORY LOCATION READ LONG 272 Ms ADDR LS ADDR READY NOT READY XXX NEXT CMD ILLEGAL READY XXX NEXT CMD BERR AERR NOT READY DATA UNUSED FROM THIS TRANSFER SEQUENCE TAKEN IF BUS ERROR L SEQUENCE TAKEN IF OR ADDRESS ERROR OCCURS ON ILLEGAL COMMAND MEMORY ACCESS IS RECEIVE
168. ch has a distinct fault address The stacked faulted excep tion format vector word identifies the type of faulted exception and the contents of the remainder of the frame A fault address corresponding to the vector specified in the stacked format vector word indicates that the processor could not obtain the address of the exception handler A BERR exception handler should execute RTE after correcting a fault RTE restores the internal machine state fetches the address of the original exception handler rec reates the original exception stack frame and resumes execution at the exception handler address If the fault is intractable the exception handler should rewrite the faulted exception stack frame at SP 14 06 and then jump directly to the original exception handler The stack frame can be generated from the information in the BERR frame the pre exception status register SP 0C the format vector word SP 0E and if the frame being written is a six word frame the program counter of the instruction causing the exception SP 10 The return program counter value is available at SP 02 A stacked fault address equal to the current stack pointer may indicate that although the first exception received a BERR while stacking the BERR exception stacking was successfully completed This is an extremely improbable occurrence but the CPU32 supports recovery from it Once the exception handler determines that the fault has been co
169. cifies the operand to be shifted Only memory alterable addressing modes are allowed as shown Addressing Mode Mode Register Addressing Mode Mode Register Dn xxx W 111 000 An xxx L 111 001 An 010 Reg number An data An 011 Reg number An An 100 Reg number An 416 101 Reg number dig PC dg An Xn 110 Reg number An dg PC Xn bd An Xn 110 Reg number An bd PC Xn MOTOROLA INSTRUCTION SET CPU32 4 88 REFERENCE MANUAL MOVE Move Data from Source to Destination MOVE Operation Source Destination Assembler Syntax MOVE ea ea Attributes Size Byte Word Long Description Moves the data at the source to the destination location and sets the condition codes according to the data Condition Codes X N Z V 0 0 Not affected Set if the result is negative Cleared otherwise Set if the result is zero Cleared otherwise Always cleared Always cleared Instruction Format lt 2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DESTINATION EFFECTIVE ADDRESS 0 0 SIZE REGISTER MODE MODE REGISTER Instruction Fields Size field Specifies the size of the operand to be moved 01 Byte operation 11 Word operation 10 Long operation CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4 89 MOVE Move Data from Source to Des
170. cknowledged The control bits determine trace mode and privilege level At user privilege level only the condition code register is available At supervisor privilege level software can access the full status register USER BYTE SYSTEM BYTE CONDITION CODE REGISTER 142 1 9 8 7 6 5 4 3 2 1 0 Ne TRACE INTERRUPT EXTEND ENABLE PRIORITY MASK NEGATIVE SUPERVISOR USER ZERO STATE OVERFLOW CARRY Figure 2 3 Status Register The vector base register VBR contains the base address of the exception vector ta ble in memory The displacement of an exception vector is added to the value in this register to access the vector table Alternate function code registers SFC and DFC contain 3 bit function codes The CPU32 generates a function code each time it accesses an address Specific codes are assigned to each type of access The codes can be used to select eight dedicated 4G byte address spaces The MOVE instructions can use registers SFC and DFC to specify the function code of a memory address 2 3 Data Types Six basic data types are supported Bits Binary Coded Decimal BCD Digits Byte Integers 8 bits Word Integers 16 bits Long Word Integers 32 bits Quad Word Integers 64 bits Ol BON CPU32 ARCHITECTURE SUMMARY MOTOROLA REFERENCE MANUAL 2 3 2 3 1 Organization in Registers The eight data registers can store
171. cle If the aborted cycle is a data space access exception processing begins when the pro cessor attempts to use the data except in the case of a released operand write Re leased write exceptions are delayed until the next instruction boundary or attempted operand access An address exception on a branch to an odd address is delayed until the program counter is changed No exception occurs if the branch is not taken In this case the fault address and return program counter value placed in the exception stack frame are the odd address and the current instruction program counter points to the instruc tion that caused the exception CPU32 EXCEPTION PROCESSING MOTOROLA REFERENCE MANUAL 6 7 If an address error occurs during exception processing for a bus error another ad dress error or a reset the processor halts 6 2 4 Instruction Traps Traps are exceptions caused by instructions They arise from either processor recog nition of abnormal conditions during instruction execution or from use of specific trap ping instructions Traps are generally used to handle abnormal conditions that arise in control routines The TRAP instruction which always forces an exception is useful for implementing system calls for user programs The TRAPcc TRAPV CHK and CHk2 instructions force exceptions when a program detects a run time error The DIVS and DIVU in structions force an exception if a division operation is attempted with a divisor of
172. complete status is returned when register write is complete Register Field The system control register is specified by the register field according to the follow ing table The FAR is a read only register any write to it is ignored System Register Select Code Return Program Counter RPC 0000 Current Instruction Program Counter PCC 0001 Status Register SR 1011 User Stack Pointer USP 1100 Supervisor Stack Pointer SSP 1101 Source Function Code Register SFC 1110 Destination Function Code Register DFC 1111 Temporary Register A ATEMP 1000 Fault Address Register FAR 1001 Vector Base Register VBR 1010 7 2 8 8 Read Memory Location READ Read the sized data at the memory location specified by the long word address Only absolute addressing is supported The SFC register determines the address space ac cessed Valid data sizes include byte word or long word Command Format 15 14 13 12 11 10 9 8 7 6 5 4 3 0 0 0 0 1 1 0 0 1 OP SIZE 0 0 0 0 0 0 Command Sequence CPU32 DEVELOPMENT SUPPORT MOTOROLA REFERENCE MANUAL 7 17 READ BW MS ADDR LS ADDR MEMORY Y 777 READY NOT READY LOCATION NOT READY XXX NEXT CMD NEXT CMD ILLEGAL NOT READY RESULT XXX BERR AERR NEXT CMD NOT READY READ LONG gt _MS ADDR LS ADDR MEMORY Y NOT READY NOT READY NOT READY
173. context 2 BKPT n CHK CHK2 Exception processing is a part of instruction Division by Zero RTE execution TRAP n TRAPcc TRAPV 3 Illegal Instruction Line A Exception processing begins before Unimplemented Line F instruction execution Privilege Violation 4 1 Trace Exception processing begins when current 4 2 Hardware Breakpoint instruction or previous exception processing 4 3 Interrupt is complete It is important to be aware of the difference between exception processing mode and execution of an exception handler Each exception has an assigned vector that points to an associated handler routine Exception processing includes steps described in 6 1 3 Exception Processing Sequence but does not include execution of handler routines which is done in normal mode When the CPU32 completes exception processing it is ready to begin either exception processing for a pending exception or execution of a handler routine Priority assign ment governs the order in which exception processing occurs not the order in which exception handlers are executed MOTOROLA EXCEPTION PROCESSING CPU32 6 4 REFERENCE MANUAL As a general rule when simultaneous exceptions occur the handler routines for lower priority exceptions are executed before the handler routines for higher priority excep tions For example consider the arrival of an interrupt during execution of a TRAP in struction while tracing is enabled Trap exception processing 2 is done firs
174. count deter mines the number of bit positions rotated Bits rotated out of the low order bit go to the carry bit and also back into the high order bit ROR MOTOROLA 4 130 INSTRUCTION SET CPU32 REFERENCE MANUAL RO L ROR Rotate Without Extend RO L ROR Condition Codes X N 2 n 0 gt X Not affected N Set if the most significant bit of the result is set Cleared otherwise Z Set if the result is zero Cleared otherwise V Always cleared Set according to the last bit rotated out of the operand Cleared when the rotate count is zero Instruction Format Register Rotate 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 0 COUNT REGISTER dr SIZE ilr 1 1 REGISTER Instruction Fields Register Rotate Count Register field If i r O this field contains the rotate count The values 1 7 represent counts of 1 7 and 0 specifies a count of 8 If i r 1 this field specifies a data register that contains the rotate count mod ulo 64 dr field Specifies the direction of the rotate 0 Rotate right 1 Rotate left Size field Specifies the size of the operation 00 Byte operation 01 Word operation 10 Long operation i r field Specifies the rotate count location If i r 0 immediate rotate count If i r 2 1 register rotate count Register field Specifies a data register to be rotated NOTE Byte
175. ctive address mode specified in the operation word branch displacements bit number special register specifications trap operands or argument counts 15 0 OPERATION WORD ONE WORD SPECIFIES OPERATION AND MODES SPECIAL OPERAND SPECIFIERS IF ANY ONE OR TWO WORDS IMMEDIATE OPERAND OR SOURCE ADDRESS EXTENSION IF ANY ONE TO THREE WORDS DESTINATION EFFECTIVE ADDRESS EXTENSION IF ANY ONE TO THREE WORDS Figure 4 1 Instruction Word General Format MOTOROLA INSTRUCTION SET CPU32 4 2 REFERENCE MANUAL Besides the operation code which specifies the function to be performed an instruc tion defines the location of every operand for the function Instructions specify an op erand location in one of three ways Register specification Effective address Implicit reference A register field of the instruction contains the number of the register An effective address field of the instruction con tains address mode information The definition of an instruction implies the use of specific registers The register field within an instruction specifies the register to be used Other fields within the instruction specify whether the register is an address or data register and how it is to be used SECTION 3 DATA ORGANIZATION AND ADDRESSING CA PABILITIES contains detailed register information 4 2 1 Notation Except where noted the following notation is used in this section Data Destination Source
176. cycle to be a read instead of a write or could cause access to a different address space than the original bus cycle If the rerun bus cycle is a read returned data will be ignored 6 3 2 3 Il Correcting Faults via RTE Instructions aborted because of a type II fault are restarted upon return from the ex ception handler A fault handler must establish safe restart conditions If a fault is caused by a nonresident page in a demand paged virtual memory configuration the fault address must be read from the stack and the appropriate page retrieved An RTE instruction terminates the exception handler After unstacking the machine state the instruction is refetched and restarted CPU32 EXCEPTION PROCESSING MOTOROLA REFERENCE MANUAL 6 19 6 3 2 4 Type III Correcting Faults via Software Sufficient information is contained in the stack frame to complete MOVEM in software After the cause of the fault is corrected the faulted bus cycle must be rerun Do the following to complete an instruction through software A Setup for Rerun Read the MOVEM opcode and extension from locations pointed to by stack frame PC and PC 2 The effective address need not be recalculated since the next operand address is saved in the stack frame However the opcode ef fective address field must be examined to determine how to update the address register and program counter when the instruction is complete Adjust the mask to account for operands alr
177. d Data immediately following the instruction If size 00 the data is the low order byte of the immediate word If size 01 the data is the entire immediate word If size 10 the data is the next two immediate words CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4 21 ADDQ Add Quick ADDQ Operation Immediate Data Destination Destination Assembler Syntax ADDQ data ea Attributes Size Byte Word Long Description Adds an immediate value in the range 1 8 to the operand at the destination location Word and long operations are allowed on the address registers When adding to address registers the condition codes are not altered and the entire destination address register is used regardless of the operation size Condition Codes X N Z V C Set the same as the carry bit Set if the result is negative Cleared otherwise Set if the result is zero Cleared otherwise Set if an overflow occurs Cleared otherwise Set if a carry occurs Cleared otherwise The condition codes are not affected when the destination is an address register lt 2 Instruction Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EFFECTIVE ADDRESS 0 1 0 1 DATA 0 SIZE MODE REGISTER MOTOROLA INSTRUCTION SET CPU32 4 22 REFERENCE MANUAL ADDQ Add Quick ADDQ Instruction Fields Data field Three bits of immediate data 9 11 with O repr
178. d Data Address Spaces Many Data Types Flexible Addressing Modes Full Interrupt Processing Expansion Capability 2 1 Programming Model The CPU32 programming model consists of two groups of registers that correspond to the user and supervisor privilege levels User programs can only use the registers of the user model The supervisor programming model which supplements the user programming model is used by CPU32 system programmers who wish to protect sen sitive operating system functions The supervisor model is identical to that of MC68010 and later processors The CPUS2 has eight 32 bit data registers seven 32 bit address registers a 32 bit program counter separate 32 bit supervisor and user stack pointers a 16 bit status register two alternate function code registers and a 32 bit vector base register see Figure 2 1 and Figure 2 2 CPU32 ARCHITECTURE SUMMARY MOTOROLA REFERENCE MANUAL 2 1 31 16 15 8 7 0 DO D1 D2 D3 DATA REGISTERS D4 D5 D6 D7 31 16 15 0 AO Al A2 ADDRESS REGISTERS A4 A5 A6 31 16 15 0 A7 USP USER STACK POINTER 31 0 PC PROGRAM COUNTER 15 8 7 0 0 CCR CONDITION CODE REGISTER Figure 2 1 User Programming Model 31 16 15 0 SSP SUPERVISOR STACK POINTER 15 8 7 0 CCR SR STATUS REGISTER 31 0 PC VECTOR BASE REGISTER 31 32 0 SFC ALTERNATE FUNCTION DFC COD
179. d exception is processed before the trace exception If an instruction is executed and a breakpoint is pending upon completion of the in struction the trace exception is processed before the breakpoint If an attempt is made to execute an illegal unimplemented or privileged instruction while tracing is enabled no trace exception will occur because the instruction is not executed This is particularly important to an emulation routine that performs an in struction function adjusts the stacked program counter to beyond the unimple mented instruction and then returns The status register on the stack must be checked to determine if tracing is on before the return is executed If tracing is on trace exception processing must be emulated so that the trace exception handler can account for the emulated instruction Tracing also affects normal operation of the STOP and LPSTOP instructions If either begins execution with T1 set a trace exception will be taken after the instruction loads the status register Upon return from the trace handler routine execution will continue with the instruction following STOP LPSTOP and the processor will not enter the stopped condition 6 2 11 Interrupts There are seven levels of interrupt priority and 192 assignable interrupt vectors within each exception vector table Judicious use of multiple vector tables and hardware chaining will permit a virtually unlimited number of peripherals to interrupt the pr
180. d in detail in 6 3 Fault Recovery A double bus fault during initial stack pointer program counter SP PC fetch sequence is distinguished by a value of FFFFFFFF in the current instruction PC At no other time will the processor write an odd value into this register 7 2 4 Command Execution Figure 7 4 summarizes BDM command execution Commands consist of one 16 bit operation word and can include one or more 16 bit extension words Each incoming word is read as it is assembled by the serial interface The microcode routine corre sponding to a command is executed as soon as the command is complete Result op erands are loaded into the output shift register to be shifted out as the next command is read This process is repeated for each command until the CPU returns to normal operating mode CPU32 DEVELOPMENT SUPPORT MOTOROLA REFERENCE MANUAL 7 5 7 2 5 Background Mode Registers BDM processing uses three special purpose registers to keep track of program context during development A description of each follows 7 2 5 1 Fault Address Register FAR The FAR contains the address of the faulting bus cycle immediately following a bus or address error This address remains available until overwritten by a subsequent bus cycle Following a double bus fault the FAR contains the address of the last bus cycle The address of the first fault if there was one is not visible to the user 7 2 5 2 Return Program Counter RPC The RPC points to t
181. d remainder Two special conditions may arise during the operation 1 Division by zero causes a trap 2 Overflow may be detected before instruction completion If an overflow is detected the overflow condition code is set and the operands are unaffected Condition Codes X N Z V 0 X Not affected N Set if quotient is negative Cleared otherwise Undefined if overflow or divide by zero occurs Z Set if quotient is zero Cleared otherwise Undefined if overflow or divide by Zero occurs V Set if division overflow occurs undefined if divide by zero occurs Cleared oth erwise C Always cleared CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4 69 DIVU Unsigned Divide DIVU DIVUL DIVUL Instruction Format word form 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EFFECTIVE ADDRESS 1 0 0 0 REGISTER 0 1 1 MODE REGISTER Instruction Fields Register field Specifies any of the eight data registers This field always specifies the destination operand Effective Address field Specifies the source operand Only data addressing modes are allowed as shown Addressing Mode Mode Register Addressing Mode Mode Register Dn 000 Reg number Dn 111 000 xxx L 111 001 An 010 Reg number An data 111 100 An 011 Reg number An An 100 Reg number An 416 101
182. data operands of 1 8 16 32 and 64 bits and ad dresses of 16 or 32 bits The seven address registers and the two stack pointers are used for address operands of 16 or 32 bits The PC is 32 bits wide 2 3 1 1 Data Registers Each data register is 32 bits wide Byte operands occupy the low order 8 bits word operands the low order 16 bits and long word operands the entire 32 bits When a data register is used as either a source or destination operand only the appropriate low order byte or word in byte or word operations respectively is used or changed the remaining high order portion is neither used nor changed The least significant bit LSB of a long word integer is addressed as bit zero and the most significant bit MSB is addressed as bit 31 Figure 2 4 shows the organization of various types of data in the data registers 31 30 1 0 MSB LSB 31 24 23 16 15 87 0 HIGH ORDER BYTE MIDDLE HIGH BYTE MIDDLE LOW BYTE LOW ORDER BYTE WORD 31 16 15 0 HIGH ORDER WORD LOW ORDER WORD LONG WORD 31 0 LONG WORD QUAD WORD 63 62 32 MSB HIGH ORDER LONG WORD 31 1 0 LOW ORDER LONG WORD LSB Figure 2 4 Data Organization Data Registers Quad word data consists of two long words for example the product of 32 bit multiply or the quotient of 32 bit divide operations signed and unsigned Quad words may be organized in any two data registers without restrictions on order or
183. ddress pointed to by SP 6 SP value is the value before initial stacking on the faulted frame The frame can have either four or six words depending on the type of error Four word stack frames do not include the faulted instruction program counter the internal trans fer count register is located at SP 10 and the SSW is located at SP 12 The fault address of a dynamically sized bus cycle is the address of the upper byte regardless of the byte that caused the error CPU32 EXCEPTION PROCESSING MOTOROLA REFERENCE MANUAL 6 23 15 0 SP gt STATUS REGISTER 02 RETURN PROGRAM COUNTER HIGH RETURN PROGRAM COUNTER LOW 06 1 1 0 0 VECTOR OFFSET 08 FAULTED ADDRESS HIGH FAULTED ADDRESS LOW 0C DBUF HIGH DBUF LOW 10 CURRENT INSTRUCTION PROGRAM COUNTER HIGH CURRENT INSTRUCTION PROGRAM COUNTER LOW 14 INTERNAL TRANSFER COUNT REGISTER 16 0 0 SPECIAL STATUS WORD Figure 6 6 Format C BERR Stack for Prefetches and Operands 15 0 SP gt STATUS REGISTER 02 RETURN PROGRAM COUNTER HIGH RETURN PROGRAM COUNTER LOW 06 1 1 0 0 VECTOR OFFSET 08 FAULTED ADDRESS HIGH FAULTED ADDRESS LOW 0C DBUF HIGH DBUF LOW 10 CURRENT INSTRUCTION PROGRAM COUNTER HIGH CURRENT INSTRUCTION PROGRAM COUNTER LOW 14 INTERNAL TRANSFER COUNT REGISTER 16 0 1 SPECIAL STATUS WORD Figure 6 7 Format C BERR Stack on
184. ded or unauthorized use even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part MOTOROLA and registered trademarks of Motorola Inc Motorola Inc is an Equal Opportunity Affirmative Action Employer MOTOROLA INC 1990 1996 PREFACE This reference manual describes programming and operation of the CPU32 in struction processing module found in the M68300 Family of embedded controllers It is part of a multivolume set of manuals each volume corresponds to a major module in the M68300 Family A user s manual for each device incorporating the CPU32 describes processor function and operation with reference to other modules within the device This manual consists of the following sections and appendix Section 1 Overview Section 2 Architecture Summary Section 3 Data Organization and Addressing Capabilities Section 4 Instruction Set Section 5 Processing States Section 6 Exception Processing Section 7 Development Support Section 8 Instruction Execution Timing Appendix A M68000 Family Summary Index NOTE In this manual the terms assertion and negation specifya particular logic state Assert and assertion refer to an active or true signal Negate and negation refer to an inactive or false signal These terms are used independently of the voltage level that they represent This manual is written for systems designers systems programmers and applica tions pro
185. dg An Xn Sz Sc or dg PC Xn Sz Sc 4 0 6 0 1 0 2 3 4 0 All Suppressed 2 0 4 0 1 0 4 d16 1 1 5 0 2 0 1 4 932 1 3 7 0 3 0 1 4 An 1 0 4 0 1 0 4 Xm Sz Sc 4 0 6 0 1 0 2 4 An Xm Sz Sc 4 0 6 0 1 0 2 4 d16 An or 046 1 1 5 0 2 0 1 3 4 d39 An or d32 PC 1 3 7 0 3 0 1 3 4 d16 An Xm or d165 PC Xm 2 0 6 0 2 0 3 4 or d32 PC Xm 1 1 7 0 3 0 1 3 4 d16 An Xm Sz Sc or d46 PC Xm Sz Sc 2 0 6 0 2 0 2 3 4 d32 An Xm Sz Sc or d32 PC Xm Sz Sc 1 1 7 0 3 0 1 2 3 4 X There is one bus cycle for byte and word operands and two bus cycles for long operands For long bus cycles add two clocks to the tail and to the number of cycles NOTES 1 Replacement fetches overlap the head of the operation by the amount specified in the tail 2 Size and scale of the index register do not affect execution time 3 The program counter may be substituted for the base address register An 4 When adjusting the prefetch time for slower buses extra clocks may be subtracted from the head until the head reaches zero at which time additional clocks must be added to both the tail and cycle counts CPU32 INSTRUCTION EXECUTION TIMING MOTOROLA REFERENCE MANUAL 8 13 8 3 3 MOVE Instruction The MOVE instruction table indicates the number of clock periods needed for the pro cessor to calculate the destination effective address and to perform a MOVE or MOVEA instruction For entries with CEA or FEA refer to the
186. direct With Displacement In the address register indirect with displacement mode the operand is in memory The address of the operand is the sum of the address in the address register plus the sign extended 16 bit displacement integer in the extension word Displacements are always sign extended to 32 bits before being used in EA calculations GENERATION An 016 ASSEMBLER SYNTAX 916 An MODE 101 REGISTER n 31 0 ADDRESS REGISTER An MEMORY ADDRESS 31 L DISPLACEMENT SIGN EXTENDED INTEGER 31 MEMORY ADDRESS NUMBER OF EXTENSION WORDS 1 OPERAND 3 4 2 5 Address Register Indirect With Index 8 Bit Displacement This mode requires one extension word that contains the index register indicator and an 8 bit displacement The index register indicator includes size and scale information In this mode the operand is in memory The address of the operand is the sum of the contents of the address register the sign extended displacement value in the low or der eight bits of the extension word and the sign extended contents of the index reg ister possibly scaled The user must specify displacement address register and index register This address mode can have either of two different formats of extension The brief for mat 8 bit displacement requires one word of extension and provides fast indexed ad dressing The full format 16 and 32 bit displacement provides optional dis
187. e upper bound a CHK instruction exception vector number 6 occurs Condition Codes X N 2 V C x U U U X Not affected N Set if Dn 0 cleared if Dn effective address operand Undefined otherwise Z Undefined V Undefined C Undefined Instruction Format 15 14 13 12 11 10 9 8 6 5 4 3 2 1 0 EFFECTIVE ADDRESS 0 1 0 0 REGISTER SIZE 0 MODE REGISTER Instruction Fields Register field Specifies the data register that contains the value to be checked Size field Specifies the size of the operation 11 Word operation 10 Long operation Effective Address field Specifies the upper bound operand Only data addressing modes areallowed as shown CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4 49 CHK Check Register Against Bounds CHK Effective Address field Specifies the destination location Only data addressing modes are allowed as shown Addressing Mode Mode Register Addressing Mode Mode Register Dn 000 Reg number Dn xxx W 111 000 An xxx L 111 001 An 010 Reg number An data An 011 Reg number An An 100 Reg number An 96 An 101 Reg number An dig PC 111 010 dg An Xn 110 Reg number An dg PC Xn 111 011 bd An Xn 110 Reg number An bd PC Xn 111 011 Long only all others are byte only MOTOROLA INSTRUCTION SET CPU32 4 50
188. e Address field Specifies the destination operand Only data alterable addressing modes are allowed as shown Addressing Mode Mode Register Addressing Mode Mode Register Dn 000 Reg number Dn xxx W 111 000 An xxx L 111 001 An 010 Reg number An data An 011 Reg number An An 100 Reg number An 96 An 101 Reg number An 96 PC dg An Xn 110 Reg number An dg PC Xn bd An Xn 110 Reg number An bd PC Xn x Immediate field Data immediately following the instruction If size 00 the data is the low order byte of the immediate word If size 01 the data is the entire immediate word If size 10 the data is the next two immediate words CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4 125 ORI Inclusive OR Immediate ORI to CCR to Condition Code Register to CCR Operation Source CCR gt CCR Assembler Syntax ORI data CCR Attributes Size Byte Description Performs an inclusive OR operation on the immediate operand and the condition codes and stores the result in the condition code register low order byte of the status register All implemented bits of the condition code register are affected Condition Codes X N Z V C X Set if bit 4 of immediate operand is zero Unchanged otherwise N Set if b
189. e encoded with information that allows the CPU32 to distinguish new additions to the basic M68000 Family architecture Earlier microprocessors have no knowledge of extension word formats implemented in later processors and while they do detect illegal instructions they do not decode invalid encodings of the extension words as exceptions Address extension words for the early MC68000 MC68008 MC68010 and MC68020 microprocessors are shown in Figure 3 6 MOTOROLA DATA ORGANIZATION AND ADDRESSING CAPABILITIES CPU32 3 14 REFERENCE MANUAL MC6800 MC68008 MC68010 ADDRESS EXTENSION WORD 15 14 12 11 10 9 8 7 0 D A REGISTER W L 0 0 0 DISPLACEMENT INTEGER D A 0 Data Register Select 1 Address Register Select W L 0 Word Sized Operation 1 Long Word Sized Operation CPU32 MC68020 EXTENSION WORD 15 14 12 11 10 9 8 7 0 D A REGISTER W L SCALE 0 DISPLACEMENT INTEGER D A 0 Data Register Select 1 Address Register Select W L 0 Word Sized Operation 1 Long Word Sized Operation SCALE 00 Scale Factor 1 Compatible with MC68000 01 Scale Factor 2 Extension to MC68000 10 Scale Factor 4 Extension to MC68000 11 Scale Factor 8 Extension to MC68000 Figure 3 6 M68000 Family Address Extension Words The encoding for SCALE used by the CPU32 and the MC68020 is a compatible ex tension of the M68000 architecture A value of zero for SCALE is the same encoding for both extensio
190. e entire status register the program counter is advanced to point to the next instruction and the processor stops fetching and executing instructions A CPU LPSTOP broadcast cycle is executed to CPU space 3 to copy the updated interrupt mask to the external bus interface EBI The internal clocks are stopped Execution of instructions resumes when a trace interrupt or reset exception occurs A trace exception occurs if the trace state is on when the LPSTOP instruc tion is executed If an interrupt request is asserted with a higher priority that the current priority level set by the new status register value an interrupt exception occurs otherwise the interrupt request is ignored If the bit of the immediate data corresponding to the S bit is off execution of the instruction causes a privilege vio lation An external reset always initiates reset exception processing Condition Codes Set according to the immediate operand Instruction Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 IMMEDIATE DATA Instruction Fields Immediate field Specifies the data to be loaded into the status register CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4 85 LSL LSR Logical Shift LS L LSR Operation Destination Shifted by count Destination Assembler LSd Dx Dy Syntax LSd data Dy LSd ea where d i
191. e operand address is used it is incremented by one two or four depending on the size of the operand byte word or long word If the address register is the stack pointer and the operand size is byte the address is incremented by two rather than one to keep the stack pointer aligned to a word boundary GENERATION EA An An An SIZE ASSEMBLER SYNTAX An MODE 011 REGISTER n 31 0 ADDRESS REGISTER An MEMORY ADDRESS OPERAND LENGTH 1 2 OR 4 31 Y 0 MEMORY ADDRESS NUMBER OF EXTENSION WORDS 0 OPERAND 3 4 2 3 Address Register Indirect With Predecrement In the address register indirect with predecrement mode the operand is in memory and the address of the operand is in the address register specified by the register field Before the operand address is used it is decremented by one two or four depending on the operand size byte word or long word If the address register is the stack point er and the operand size is byte the address is decremented by two rather than one to keep the stack pointer aligned to a word boundary MOTOROLA DATA ORGANIZATION AND ADDRESSING CAPABILITIES CPU32 3 4 REFERENCE MANUAL GENERATION An An SIZE EA An ASSEMBLER SYNTAX An MODE 100 REGISTER 31 0 ADDRESS REGISTER An MEMORY ADDRESS OPERAND LENGTH 1 2 OR 4 MEMORY ADDRESS 3 0 NUMBER OF EXTENSION WORDS 0 OPERAND 3 4 2 4 Address Register In
192. e operand is in one of the 16 multifunction registers 3 4 1 1 Data Register Direct In the data register direct mode the operand is in the data register specified by the EA register field GENERATION EA Dn ASSEMBLER SYNTAX Dn MODE 000 REGISTER n 31 0 DATA REGISTER gt OPERAND NUMBER OF EXTENSION WORDS 0 3 4 1 2 Address Register Direct In the address register direct mode the operand is in the address register specified by the EA register field GENERATION EA An ASSEMBLER SYNTAX An MODE 001 REGISTER n 31 0 DATA REGISTER An gt OPERAND NUMBER OF EXTENSION WORDS 0 CPU32 DATA ORGANIZATION AND ADDRESSING CAPABILITIES MOTOROLA REFERENCE MANUAL 3 3 3 4 2 Memory Addressing Modes These EA modes specify the address of the memory operand 3 4 2 1 Address Register Indirect In the address register indirect mode the operand is in memory and the address of the operand is in the address register specified by the register field GENERATION EA An ASSEMBLER SYNTAX An MODE 010 REGISTER n 31 0 ADDRESS REGISTER An ________ gt MEMORY ADDRESS 31 0 MEMORY ADDRESS NUMBER OF EXTENSION WORDS 0 OPERAND 3 4 2 2 Address Register Indirect With Postincrement In the address register indirect with postincrement mode the operand is in memory and the address of the operand is in the address register specified by the register field After th
193. e serial shifter after negation of RESET 7 2 8 15 No Operation NOP NOP performs no operation and may be used as a null command where required Command Format Command Sequence NEXT CMD NOP 797 CMD COMPLETE XXX NEXT CMD ILLEGAL READY Operand Data None Result Data The command complete response 0FFFF is returned during the next shift op eration MOTOROLA DEVELOPMENT SUPPORT CPU32 7 24 REFERENCE MANUAL 7 2 8 16 Future Commands Unassigned command opcodes are reserved by Motorola for future expansion All un used formats within any revision level will perform a NOP and return the ILLEGAL command response 7 3 Deterministic Opcode Tracking CPU32 utilizes deterministic opcode tracking to trace program execution Two signals IPIPE and IFETCH provide all the information required to analyze the opera tion of the instruction pipeline 7 3 1 Instruction Fetch IFETCH IFETCH indicates which bus cycles are accessing data to fill the instruction pipeline IFETCH is pulse width modulated to multiplex two indications on a single pin Asserted for a single clock cycle IFETCH indicates that the data from the current bus cycle is to be routed to the instruction pipeline IFETCH held low for two clock cycles indicates that the instruction pipeline has been flushed The data from the bus cycle is used to begin filling the empty pipeline Both user and supervisor mode fetches are signaled
194. e source operand All addressing modes are allowed as shown Addressing Mode Mode Register Addressing Mode Mode Register Dn 000 Reg number Dn xxx W 111 000 An 001 Reg number An xxx L 111 001 An 010 Reg number An data 111 100 An 011 Reg number An An 100 Reg number An 416 An 101 Reg number An dig PC 111 010 dg Xn 110 Reg number An dg PC Xn 111 011 bd An Xn 110 Reg number An bd PC Xn 111 011 MOTOROLA INSTRUCTION SET CPU32 4 146 REFERENCE MANUAL SU Subtract Immediate SU Operation Destination Immediate Data Destination Assembler Syntax SUBI data ea Attributes Size Byte Word Long Description Subtracts the immediate data from the destination operand and stores the result in the destination location The size of the immediate data must match the operation size Condition Codes X N Z V C Set to the value of the carry bit Set if the result is negative Cleared otherwise Set if the result is zero Cleared otherwise Set if an overflow occurs Cleared otherwise Set if a borrow occurs Cleared otherwise Instruction Format O lt NZ amp 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EFFECTIVE ADDRESS 0 0 0 0 0 1 0 0 SIZE MODE REGISTER WORD DATA 16 BITS BYTE DATA 8 BITS LONG DATA 32 BITS CPU32 INST
195. eady transferred Subtract the stacked operand transfer count from 16 to obtain the number of operands trans ferred Scan the mask using this count value Each time a set bit is found clear itand decrement the counter When the count is zero the mask is ready for use Adjust the operand address If the predecrement addressing mode is in effect subtract the operand size from the stacked value otherwise add the operand size to the stacked value B Rerun Instruction Scan the mask for set bits Read write the selected register from to the operand address as each bit is found As each operand is transferred clear the mask bit and increment decrement the operand address When all bits in the mask are cleared all operands have been transferred If the addressing mode is predecrement or postincrement update the register to complete the execution of the instruction If the TR bit is set in the stacked SSW create a six word stack frame and ex ecute the trace handler If either B1 or BO in the SSW is set create another six word stack frame and execute the hardware breakpoint handler De allocate the stack and return control to the faulted program 6 3 2 5 Type III Correcting Faults By Conversion and Restart In some situations it may be necessary to rerun all the operand transfers for a faulted instruction rather than continue from a faulted operand Clearing the MV bit in the stacked SSW converts a type 111 fault into a type II fa
196. ecifies the destination operand Only data alterable addressing modes are allowed as shown Addressing Mode Mode Register Addressing Mode Mode Register Dn 000 Reg number Dn xxx W 111 000 An xxx L 111 001 An 010 Reg number An data An 011 Reg number An An 100 Reg number An 96 An 101 Reg number An 96 PC dg An Xn 110 Reg number An dg PC Xn bd An Xn 110 Reg number An bd PC Xn NOTE Memory to data register operations are not allowed Most assem blers use EORI when the source is immediate data CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4 73 EORI Exclusive OR Immediate EORI Operation Immediate Data Destination Destination Assembler Syntax EORI data ea Attributes Size Byte Word Long Description Performs an exclusive OR operation on the destination operand using the immediate data and the destination operand and stores the result in the destination location The size of the immediate data must match the operation size Condition Codes X N 2 V i 0 0 X Not affected N Set if the most significant bit of the result is set Cleared otherwise Z Set if the result is zero Cleared otherwise V Always cleared Always cleared Instruction Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EFFECTIVE ADDRESS 0
197. ecision In this example three table lookup and interpolation TLI operations are performed and the results are summed The calculation is done once with the result of each TLI rounded before addition and once with only the final result rounded Assume that the result of the three interpolations as follows a indicates the binary radix point MOTOROLA INSTRUCTION SET CPU32 4 192 REFERENCE MANUAL TLI 1 0010 0000 0111 0000 TLI 2 0011 1111 0111 0000 TLI 3 0000 0001 0111 0000 First the results of each TLI are rounded with the TBLS round to nearest even algo rithm The following values would be returned by TBLS TLI 1 0010 0000 TLI 2 0011 1111 TLI 3 0000 0001 Summing the following result is obtained 0010 0000 0011 1111 0000 0001 0110 0000 Now using the same results the sum is first calculated and then rounded accord ing to the same algorithm 0010 0000 0111 0000 0011 1111 0111 0000 0000 0001 0111 0000 0110 0001 0101 0000 Rounding yields 0110 0001 The second result is preferred The following code sequence illustrates how addition of a series of table interpolations can be performed without loss of precision in the in termediate results LO TBLSN B Dx TBLSN B Dx TBLSN B DI ADD L Dx Dm Long addition avoids problems with carry ADD L Dm DI ASR L 8 Move radix point BCC B L1 Fraction MSB in carry ADDQ B 1 DI
198. ed while an instruction is executing Several bus error stack format orga nizations are utilized to provide additional information regarding the nature of the fault First any register altered by a faulted instruction effective address calculation is re stored to its initial value Then a special status word SSW is placed on the stack The SSW contains specific Information about the aborted access size type of access read or write bus cycle type and function code are saved Finally fault address bus error exception vector number program counter value and a copy of the status regis ter are saved If a bus error occurs during exception processing for a bus error an address error a reset or while the processor is loading stack information during RTE execution the processor halts This simplifies isolation of catastrophic system failure by preventing processor interaction with stacks and memory Only assertion of RESET can restart a halted processor 6 2 3 Address Error Address error exceptions occur when the processor attempts to access an instruction word operand or long word operand at an odd address The effect is much the same as an internally generated bus error The exception processing sequence is the same as that for bus error except that the vector number refers to the address error excep tion vector Address error exception processing begins when the processor attempts to use infor mation from the aborted bus cy
199. ed write 1 Faulted cycle was a released write Faulted RMW bus cycles set the RM bit RM is ignored during unstacking 0 Faulted cycle was non RMW cycle 1 Faulted cycle was either the read or write of an RMW cycle Instruction prefetch faults are distinguished from operand both read and write faults by the IN bit If IN is cleared the error was on an operand cycle if IN is set the error was on an instruction prefetch IN is ignored during unstacking 0 Operand 1 Prefetch Read and write bus cycles are distinguished by the RW bit Read bus cycles will set the bit and write bus cycles will clear it The bit is reloaded into the bus controller if the HR bit is set during unstacking 0 Faulted cycle was an operand write 1 Faulted cycle was a prefetch or operand read The LG bit indicates an original operand size of long word LG is cleared if the original operand was a byte or word SIZ will indicate original and remaining size LG is set if the original was a long word SIZ will indicate the remaining size at the time of fault CPU32 EXCEPTION PROCESSING MOTOROLA REFERENCE MANUAL 6 15 LG is ignored during unstacking 0 Original operand size was byte or word 1 Original operand size was long word The SSW SIZ field shows operand size remaining when a fault was detected This field does not indicate the initial size of the operand It also does not necessarily indicate the proper status of a dynamica
200. ege level and determines which stack pointer is used for stack operations The processor identifies each bus access supervisor or user mode via function codes to enforce supervisor and user access levels In a typical system most programs execute at the user level User programs can ac cess only their own code and data areas and are restricted from accessing other in formation The operating system executes at the supervisor privilege level has access CPU32 PROCESSING STATES MOTOROLA REFERENCE MANUAL 5 1 to all resources performs the overhead tasks for the user level programs and coordi nates their activities 5 2 1 Supervisor Privilege Level If the S bit in the status register is set supervisor privilege level applies and all instruc tions are executable The bus cycles generated for instructions executed in supervisor level are normally classified as supervisor references and the values of the function codes on FC 2 0 refer to supervisor address spaces All exception processing is performed at the supervisor level All bus cycles generated during exception processing are supervisor references and all stack accesses use the supervisor stack pointer Instructions that have important system effects can only be executed at supervisor lev el For instance user programs are not permitted to execute STOP LPSTOP or RE SET instructions To prevent a user program from gaining privileged access except in a controlled manner ins
201. egister that contains the bit number Effective Address field Specifies the destination location Only data alterable addressing modes are allowed as shown Addressing Mode Mode Register Addressing Mode Mode Register Dn 000 Reg number Dn xxx W 111 000 An xxx L 111 001 An 010 Reg number An data An 011 Reg number An An 100 Reg number An dig 101 Reg number An 916 PC dg An Xn 110 Reg number An dg PC Xn bd An Xn 110 Reg number An bd PC Xn Long only all others are byte only MOTOROLA INSTRUCTION SET CPU32 4 38 REFERENCE MANUAL BCLR Test a Bit and Clear BCLR Operation bit number of Destination Z 0 2 bit number of Destination Assembler BCLR Dn ea Syntax BCLR ea Attributes Size Byte Long Description Tests a specified bit in the destination operand sets the Z condition code appropriately then clears the bit When a data register is the destination any of the 32 bits can be specified by a modulo 32 bit number When a memory location is the destination the operation is a byte operation and the bit number is modulo 8 In all cases bit zero refers to the least significant bit The bit number for this operation can be specified in either of two ways 1 Immediate The bit number is specified by a second instruction word 2 Register The specif
202. en added to the selected table entry The result is returned in the destination data register Dx For register interpolate mode the interpolation occurs using the Dym and Dyn regis ters in place of the two table entries For this mode only the fractional portion Dx 7 0 is used in the interpolation and the integer portion Dx 15 8 is ignored The register interpolation mode may be used with several table lookup and interpolations to model multidimensional functions MOTOROLA INSTRUCTION SET CPU32 4 158 REFERENCE MANUAL TBLU TBLU TBLUN TBLUN Unsigned table entries range from 0 to 27 1 where n is 8 16 or 32 for byte word and long word tables respectively Unsigned and unrounded table results are zero extend ed Table Lookup and Interpolate Unsigned Rounding of the result is optionally selected via the R instruction field If R 0 TBLU the fractional portion is rounded according to the round to nearest algorithm The rounding procedure can be summarized by the following table Adjusted Difference Fraction n lt Rounding Adjustment 0 gt 1 CPU32 REFERENCE MANUAL The adjusted difference is then added to the selected table entry The rounded result is returned in the destination data register Dx Only the portion of the register corre sponding to the selected size is affected 31 24 23 16 15 8 7 0 BYTE UNAFFECTED UNAFFECTED UNAFFECTED RESULT WORD UNAFFECTED UNAFFECTED
203. er number while request level remains at seven Many M68000 peripherals provide for programmable interrupt vector numbers to be used in the system interrupt request acknowledge mechanism If the vector number is not initialized after reset and if the peripheral must acknowledge an interrupt request the peripheral should return the uninitialized interrupt vector number 15 See the system integration user s manual for detailed information on interrupt ac knowledge cycles 6 2 12 Return from Exception When exception stacking operations for all pending exceptions are complete the pro cessor begins execution of the handler for the last exception processed After the ex ception handler has executed the processor must restore the system context in existence prior to the exception The RTE instruction is designed to accomplish this task When RTE is executed the processor examines the stack frame on top of the super visor stack to determine if it is valid and determines what type of context restoration must be performed See 6 4 CPU32 Stack Frames for a description of stack frames For a normal four word frame the processor updates the status register and program counter with data pulled from the stack increments the supervisor stack pointer by eight and resumes normal instruction execution For a six word frame the status reg CPU32 EXCEPTION PROCESSING MOTOROLA REFERENCE MANUAL 6 13 ister and program counter are updated from the st
204. erand and stores the result in the condition code register low order byte of the status register All implemented bits of the condition code reg ister are affected Condition Codes X N Z V C X Changed if bit 4 of immediate operand is one Unchanged otherwise N Changed if bit 3 of immediate operand is one Unchanged otherwise Z Changed if bit 2 of immediate operand is one Unchanged otherwise V Changed if bit 1 of immediate operand is one Unchanged otherwise C Changed if bit O of immediate operand is one Unchanged otherwise Instruction Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 1 0 1 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 BYTE DATA 8 BITS MOTOROLA INSTRUCTION SET CPU32 4 76 REFERENCE MANUAL EO RI Exclusive OR Immediate to Status Register EO RI to SR Privileged Instruction to SR Operation If supervisor state then Source 6 SR gt SR else TRAP Assembler Syntax EORI data SR Attributes Size Word Description Performs an exclusive OR operation on the contents of the status register using the immediate operand and stores the result in the status register All implemented bits of the status register are affected Condition Codes x N 7 V Changed if bit 4 of immediate operand is one Unchanged otherwise Changed if bit 3 of immediate operand is one Unchanged otherwise Changed if bi
205. ers The CPU32 external bus interface interrupt mask register resides in CPU space This register is written to when LPSTOP is executed and masks off external interrupts while in stop mode A 3 1 indicate the encoded interrupt mask level 31 18 17 1 0 0 00000000000 001 1 11 11 115 1 1 1 1 1 BKPT T 0 DATA 0 00000 0 0 0111110 15 3 2 1 0 MOTOROLA PROCESSING STATES CPU32 5 4 REFERENCE MANUAL These control registers reserved for future expansion also reside in CPU space 3 and are only accessible through the MOVES command The general format of this CPU space type is defined as follows 31 18 17 16 15 12 11 8 7 5 4 2 1 0 0 0 00000000000 0 1 1 A A 15 12 are used as 1 of 16 external chip selects A 11 8 are used as 1 of 16 internal module selects A 7 0 are used as 1 of 256 module register addresses 5 3 1 5 Type 1111 Interrupt Acknowledge Interrupt acknowledge is a CPU space type used for interrupt acknowledge A 4 1 in dicate the encoded interrupt level being acknowledged Ti cde T1 d Te ABS 2151221 427b 1d 1d 1040 41 LEVEL 1 CPU32 PROCESSING STATES MOTOROLA REFERENCE MANUAL 5 5 MOTOROLA PROCESSING STATES CPU32 5 6 REFERENCE MANUAL SECTION 6 EXCEPTION PROCESSING This section discusses system resources related to exception handling exception pro cessing sequence and
206. erun upon return from the exception handler The remainder of the stack frame contains sufficient information to continue MOVEM with operand transfer following a faulted transfer The address of the next operand to be transferred incremented or decremented by operand size is stored in the faulted address location 08 The stacked transfer counter is set to 16 minus the number of transfers attempted including the faulted cycle Refer to Figure 6 3 for the stacking format 6 3 1 4 Type IV Faults During Exception Processing The fourth type of fault occurs during exception processing If this exception is a sec ond address or bus error the machine halts in the double bus fault condition How ever if the exception is one that causes a four or six word stack frame to be written a bus cycle fault frame is written below the faulted exception stack frame The SSW for a fault within an exception contains the following bit pattern 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0 1 0 0 TR B1 BO 0 0 0 1 LG SIZ FUNC 15 0 TR B1 and BO are set if a corresponding exception is pending when the BERR ex ception is taken The contents of the faulted exception stack frame are included in the bus fault stack frame The pre exception status register and the format vector word of the faulted frame are stacked The type of exception can be determined from the format vector word If the faulted exception stack
207. es the address register MOTOROLA INSTRUCTION SET CPU32 4 78 REFERENCE MANUAL EXT Sign Extend EXT EXTB EXTB Operation Destination Sign extended Destination Assembler Syntax EXT W Dnextend byte to word EXT L Dnextend word to long word EXTB L Dnextend byte to long word Attributes Size Word Long Description Extends a byte in a data register to a word or a long word or a word in a data register to a long word by replicating the sign bit to the left If the operation extends a byte to a word bit 7 of the designated data register is copied to bits 15 8 of that data register If the operation extends a word to a long word bit 15 of the des ignated data register is copied to bits 31 16 of the data register The EXTB form cop ies bit 7 of the designated register to bits 31 8 of the data register Condition Codes X N 2 V 0 0 X Not affected N Set if the result is negative Cleared otherwise Z Set if the result is zero Cleared otherwise V Always cleared Always cleared Instruction Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 0 0 1 0 0 OPMODE 0 0 0 REGISTER Instruction Fields Opmode field Specifies the size of the sign extension operation 010 Sign extend low order byte of data register to word 011 Sign extend low order word of data register to long 111 Sign extend low o
208. esenting a value of 8 Size field Specifies the size of the operation 00 Byte operation 01 Word operation 10 Long operation Effective Address field Specifies the destination location Only alterable addressing modes are allowed as shown Addressing Mode Mode Register Addressing Mode Mode Register Dn 000 Reg number Dn xxx W 111 000 An 001 Reg number An xxx L 111 001 An 010 Reg number An data 111 100 An 011 Reg number An An 100 Reg number An 416 101 Reg number dig PC 111 010 dg An Xn 110 Reg number An dg PC Xn 111 011 bd An Xn 110 Reg number An bd PC Xn 111 011 Word and long only CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4 23 A D DX Add Extended A D DX Operation Source Destination X Destination Assembler ADDX Dy Dx Syntax ADDX Ay Ax Attributes Size Byte Word Long Description Adds the source operand to the destination operand along with the extend bit and stores the result in the destination location The operands can be addressed in two ways 1 Data register to data register Data registers specified by the instruction contain the operands 2 Memory to memory Address registers specified by the instruction address the operands using the predecrement addressing mode Condition Codes x N 7 V Set the sa
209. ess than or equal to Boolean AND Boolean OR Boolean XOR exclusive OR not Boolean complement operand is inverted BCD Binary coded decimal indicated by subscript Example Source is a BCD source operand LSW Least significant word MSW Most significant word R W Read write indicator In description of an operation a destination operand is placed to the right of source operands and is indicated by an arrow MOTOROLA INSTRUCTION SET CPU32 4 4 REFERENCE MANUAL 4 3 Instruction Summary The instructions form a set of tools to perform the following operations Data movement Integer arithmetic Logic Shift and rotate Bit manipulation Binary coded decimal arithmetic Program control System control The complete range of instruction capabilities combined with the addressing modes described previously provide flexibility for program development 4 3 1 Condition Code Register The condition code register portion of the status register contains five bits that indicate the result of a processor operation Table 4 1 lists the effect of each instruction on these bits The carry bit and the multiprecision extend bit are separate in the M68000 Family to simplify programming techniques that use them Refer to Table 4 5 as an example Table 4 1 Condition Code Computations Operations X N Z V C Special Definition ABCD U 2 U 2 Decimal Carry 7 7 e e RO ADD ADDI
210. essing modes are allowed as shown Addressing Mode Mode Register Addressing Mode Mode Register Dn xxx W 111 000 An xxx L 111 001 An 010 Reg number An data An An 416 101 Reg number dig PC 111 010 dg An Xn 110 Reg number An dg PC Xn 111 011 bd An Xn 110 Reg number An bd PC Xn 111 011 Size field Specifies the size of operation 00 byte operation 01 word operation 10 long operation Register field Specifies the destination data register Dx On entry the register contains the interpolation fraction and entry number Dym Dyn field If the effective address mode field is nonzero this operand register is unused and should be zero If the effective address mode field is zero the surface interpolation variant of this instruction is implied and Dyn specifies one of the two source operands Rounding mode field The R bit controls rounding of the final result When R 0 the result is rounded according to the round to nearest algorithm When R 1 the result is returned unrounded CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4 161 TAS Test and Set an Operand TAS Operation Destination Tested Condition Codes 1 bit 7 of Destination Assembler Syntax TAS ea Attributes Size Byte Description Tests and sets the byte operand addressed by the effective
211. estination Source Destination signed or unsigned DIVSL DIVUL 64 32 gt 32 32 Destination Source Destination ea 32 32 gt 32 signed or unsigned Dr 32 32 gt 32 32 EXT Dn Dn 8 gt 16 Sign extended Destination Destination 16232 EXTB Dn 8 gt 32 Sign extended Destination Destination MULS MULU Dn ea DI 16 16 32 Source Destination Destination ea Dh DI 32 32 32 signed or unsigned 32 32 64 NEG ea 8 16 32 0 Destination Destination NEGX ea 8 16 32 0 Destination X Destination SUB ea Dn Dn ea 8 16 32 Destination Source Destination SUBA ea An 16 32 Destination Source Destination SUBI data ea 8 16 32 Destination Data Destination SUBQ data ea 8 16 32 Destination Data Destination SUBX Dn Dn 8 16 32 Destination Source X Destination An An 8 16 32 TBLS TBLU ea Dn 8 16 32 Dyn Dym gt Temp Dym Dyn Dn Temp Dn 7 0 gt Temp Dym 256 Temp Dn TBLSN TBLUN ea Dn 8 16 32 Dyn Dym gt Temp Dym Dyn Dn Temp Dn 7 0 256 5 Temp Dym Temp Dn 4 3 4 Logic Instructions The logical operation instructions AND OR EOR and NOT perform logical opera tions with all sizes of integer data operands A similar set of immediate instructions ANDI ORI and EORI provide these logical operations with all
212. estore operations table indicates the number of clock periods needed for the processor to perform the specified state save or return from exception Com plete execution times and stack length are given No additional tables are needed to calculate total effective execution time for these instructions The total number of clock cycles is outside the parentheses The numbers inside parentheses r p w are includ ed in the total clock cycle number All timing data assumes two clock reads and writes Instruction Head Tail Cycles BERR instruction O0 2 582212 BERR on exception 0 2 48 2 2 12 RTE four word frame 1 2 24 4 2 0 RTE six word frame 1 2 26 4 2 0 RTE BERR on instruction 1 2 50 12 12 Y RTE BERR on four word frame 1 2 66 10 2 4 RTE six word frame 1 2 7002260 Maximum time is indicated certain data or mode combinations execute faster Y If a bus error occurred during a write cycle the cycle is rerun by the RTE MOTOROLA INSTRUCTION EXECUTION TIMING CPU32 8 22 REFERENCE MANUAL APPENDIX AM68000 FAMILY SUMMARY Appendix A summarizes the characteristics of the microprocessors in the M68000 Family The M68000 user s manual includes more detailed information about the MC68000 and MC68010 differences MC68000 MC68010 CPU32 MC68020 Data Bus Size Bits 16 16 8 16 8 16 32 Address Bus Size Bits 24 24 24 32 Instruction Cache in Words 9 3
213. esult Overflow occurs if any of the high order 32 bits of the quad word product are not equal to zero MOTOROLA INSTRUCTION SET CPU32 4 110 REFERENCE MANUAL MULU Unsigned Multiply MULU Instruction Format word form 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EFFECTIVE ADDRESS 1 1 0 0 REGISTER 0 1 1 MODE REGISTER Instruction Fields Register field Specifies a data register as the destination Effective Address field Specifies the source operand Only data addressing modes are allowed as shown Addressing Mode Mode Register Addressing Mode Mode Register Dn 000 Reg number Dn xxx W 111 000 An xxx L 111 001 An 010 Reg number An data 111 100 An 011 Reg number An An 100 Reg number An 416 101 Reg number dig PC 111 010 dg An Xn 110 Reg number An dg PC Xn 111 011 bd An Xn 110 Reg number An bd PC Xn 111 011 CPUS2 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4 111 MULU Unsigned Multiply MULU Instruction Format long form 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EFFECTIVE ADDRESS 0 1 0 0 1 1 0 0 0 0 MODE REGISTER 0 REGISTER DI 0 SIZE 0 0 0 0 0 0 0 REGISTER Dh Instruction Fields Effective Address field Specifies the source operand Only data addressing modes are allowed as shown
214. f the register is less than 32 bits the result is returned zero extended Register Field The system control register is specified by the register field according to the follow ing table System Register Select Code Return Program Counter RPC 0000 Current Instruction Program Counter PCC 0001 Status Register SR 1011 User Stack Pointer USP 1100 Supervisor Stack Pointer SSP 1101 Source Function Code Register SFC 1110 Destination Function Code Register DFC 1111 Temporary Register A ATEMP 1000 Fault Address Register FAR 1001 Vector Base Register VBR 1010 7 2 8 7 Write System Register WSREG Operand data is written into the specified system control register All registers that can be written in supervisor mode can be written in BDM Several internal temporary reg isters are also accessible Command Format MOTOROLA DEVELOPMENT SUPPORT CPU32 7 16 REFERENCE MANUAL A A D A ar A o N o oa a 0 0 1 0 0 1 0 e e e REGISTER Command Sequence WSREG 22 MS DATA gt LS DATA NEXT CMD NOT READY NOT READY CMD COMPLETE ILLEGAL NOT READY Operand Data The data to be written into the register is always supplied as a 32 bit long word If the register is less than 32 bits the least significant word is used Result Data Command
215. f Instruction Pipeline Assertion of IPIPE for a single clock cycle indicates the use of data from IRB Regard less of the presence of valid data in IRA the contents of IRB are invalidated when IPIPE is asserted If IRA contains valid data the data is copied into IRB IRA IRB and the IRB stage is revalidated Assertion of IPIPE for two clock cycles indicates the start of a new instruction and sub sequent replacement of data in IRC This action causes a full advance of the pipeline IRB IRC and IRA gt IRB IRA is refilled during the next instruction fetch bus cycle Data loaded into IRA propagates automatically through subsequent empty pipeline stages Signals that show the progress of instructions through IRB and IRC are nec essary to accurately monitor pipeline operation These signals are provided by IRA and IRB validity bits When a pipeline advance occurs the validity bit of the stage be ing loaded is set and the validity bit of the stage supplying the data is negated Because instruction execution is not timed to bus activity IPIPE is synchronized with the system clock and not the bus Figure 7 12 illustrates the timing in relation to the system clock IRA gt IRA IRA IRA lt IRA IRA gt lt IRB gt IRC 3 9 IRA IRA gt lt IRB gt IRC CLKOUT M NEED in EE CENE EXTENSION INSTRUCTION EXTENSION INSTRUCTION WORD USED START WORD USED START Figure 7 12 Instruction Pipel
216. f ac cesses necessary to continue microcode execution The microsequencer supervises the bus controller instruction execution and internal processor operations such as calculation of effective address and setting of condition codes It also initiates instruc tion word prefetches after a change of flow and controls validation of instruction words in the instruction pipeline CPU32 INSTRUCTION EXECUTION TIMING MOTOROLA REFERENCE MANUAL 8 1 MICROSEQUENCER AND CONTROL INSTRUCTION PIPELINE STAGE Co STAGE STAGE CONTROL STORE 52 CONTROL LOGIC EXECUTION UNIT PROGRAM DATA DATA SECTION WRITE PEND PREFETCH BUFFER CONTROLLER ADDRESS BUS MICROBUS CONTROLLER BUS CONTROL SIGNALS Figure 8 1 Block Diagram of Independent Resources 8 1 2 Instruction Pipeline The CPU32 contains a two word instruction pipeline where instruction opcodes are decoded Each stage of the pipeline is initially filled under microsequencer control and subsequently refilled by the prefetch controller as it empties Stage A of the instruction pipeline is a buffer Prefetches completed on the bus before stage B empties are temporarily stored in this buffer Instruction words instruction op eration words and all extension words are decoded at stage B Residual decoding and e
217. factor is 64 and the scaling is done by a single instruction LSR W 6 Dx Thus Dx now contains the following bit pattern 31 16 15 0 NOT USED 0000001010001 11 90 Table Entry Offset Dx 8 15 02 2 Interpolation Fraction Dx 0 7 8E 142 Using this information the table instruction calculates dependent variable Y Y 1331 142 1966 1311 256 1674 The function chosen for Examples 1 and 2 is linear between data points If another function had been used interpolated values might not have been identical MOTOROLA INSTRUCTION SET CPU32 4 190 REFERENCE MANUAL 4 6 3 Table Example 3 8 Bit Independent Variable INDEPENDENT VARIABLE lt 1024 2048 3072 X INDEPENDENT VARIABLE Figure 4 5 Table Example 3 This example shows how to use a table instruction within an interpolation subroutine Independent variable X is calculated as an 8 bit value allowing 16 levels of interpola tion on a 17 entry table X is passed to the subroutine which returns an 8 bit result The subroutine uses the following data based on the function shown in Figure 4 5 X X Y Subroutine Instruction 0 0 0 1 256 16 2 512 32 3 768 48 4 1024 64 5 1280 80 6 1536 96 7 1792 112 8 2048 128 9 2304 112 10 2560 96 11 2816 80 12 3072 64 13 3328 48 14 3584 32 15 3840 16 16 4096 0 CPU32 INSTRUCTION SET REFERENCE MANUAL MOTOROLA 4 19
218. for future use Exception processing for trace starts at the end of normal processing for the traced instruction and before the start of the next instruction Exception processing follows the regular sequence tracing is disabled so that the trace exception itself is not traced A vector number is generated to reference the trace exception vector The ad dress of the instruction that caused the trace exception the trace exception vector off set the current program counter and a copy of the status register are saved on the supervisor stack The saved value of the program counter is the address of the next instruction to be executed A trace exception can be viewed as an extension to the function of any instruction If a trace exception is generated by an instruction the execution of that instruction is not complete until the trace exception processing associated with it is also complete If an instruction is aborted by a bus error or address error exception trace exception processing is deferred until the suspended instruction is restarted and completed nor mally An RTE from a bus error or address error will not be traced because of the pos sibility of continuing the instruction from the fault CPU32 EXCEPTION PROCESSING MOTOROLA REFERENCE MANUAL 6 11 If an instruction is executed and an interrupt is pending on completion the trace exception is processed before the interrupt exception If an instruction forces an exception the force
219. g word result All four in structions support two types of interpolation data an n element table stored in mem and a two element range stored in a pair of data registers The latter form provides a means of performing surface 3D interpolation between two previously calculated linear interpolations The following examples show how to compress tables and use fewer interpolation lev els between table entries Example 1 see Figure 4 3 demonstrates table lookup and interpolation for a 257 entry table allowing up to 256 interpolation levels between en tries Example 2 see Figure 4 4 reduces table length for the same data to four en tries Example 3 see Figure 4 5 demonstrates use of an 8 bit independent variable with an instruction Two additional examples show how TBLSN can reduce cumulative error when multi ple table lookup and interpolation operations are used in a calculation Example 4 demonstrates addition of the results of three table interpolations Example 5 illustrates use of TBLSN in surface interpolation 4 6 1 Table Example 1 Standard Usage DEPENDENT VARIABLE 16384 32768 49152 65536 X INDEPENDENT VARIABLE Figure 4 3 Table Example 1 The table consists of 257 word entries As shown in Figure 4 3 the function is linear within the range 32768 lt X lt 49152 Table entries within this range are as follows MOTOROLA INSTRUCTION SET CPU32 4 188 REFERENCE MANUAL Entry X
220. gister field Specifies the data register that contains the bit number Effective Address field Specifies the destination location Only data alterable addressing modes are allowed as shown Addressing Mode Mode Register Addressing Mode Mode Register Dn 000 Reg number Dn xxx W 111 000 An xxx L 111 001 An 010 Reg number An data An 011 Reg number An An 100 Reg number An 416 101 Reg number dig PC dg An Xn 110 Reg number An dg PC Xn bd An 110 Reg number An bd PC Xn mE Long only all others are byte only MOTOROLA INSTRUCTION SET CPU32 4 40 REFERENCE MANUAL BG N D Enter Background Mode BG N D Operation If background mode enabled then enter Background Mode else Format Vector offset SSP PC SSP SR SSP Vector PC Assembler Syntax BGND Attributes Size Unsized Description The processor suspends instruction execution and enters back ground mode if enabled The freeze output is asserted to acknowledge entrance into background mode Upon exiting background mode instruction execution contin ues with the instruction pointed to by the program counter If background mode is not enabled the processor initiates illegal instruction exception processing The vector number is generated to reference the illegal instruction exception vector Backgrou
221. grammers Systems designers need general knowledge of the entire vol ume with particular emphasis on Section 1 Section 7 and Appendix A they will also need to be familiar with electrical specifications and mechanical data con tained in the user s manual Systems programmers should become familiar with Sections 1 through 6 Section 8 and Appendix A Applications programmers can find most of the information they need in Sections 1 through 5 Section 8 and Ap pendix A This manual is also written for users of the M68000 Family that are not familiar with the CPU32 Although there are comparative references to other Motorola micro processors throughout the manual Section 1 Section 2 and Appendix A specifi cally identify the CPU32 within the M68000 Family and discuss the differences betweeen it and related devices CPUS32 REFERENCE MANUAL MOTOROLA iii MOTOROLA CPU32 REFERENCE MANUAL iv TABLE OF CONTENTS Paragraph Title Page SECTION 1 OVERVIEW 1 1 PCAN et ee cate disse eases 1 1 1 1 1 Virtual Memory costa MT 1 2 1 1 2 Loop Mode Instruction Execution 44844 1 2 1 1 3 Vector Base Register ae 1 3 1 1 4 Exception FIMO lyon 1 3 1 1 5 Enhanced Addressing Modes 5 S 1 4 1 1 6 Ol 24 AA ied oed ten te deo FEM ges 1 4 1 1 6 1 Table Lookup and Interpolation Instructions 1 4 1 1 6 2 Low
222. hanged the S bit is set establishing supervisor access level and bits T1 and TO are cleared disabling tracing Then priority level is set to the level of the inter rupt and the processor fetches a vector number from the interrupting device CPU space F The fetch bus cycle is classified as an interrupt acknowledge and the en coded level number of the interrupt is placed on the address bus If an interrupting device requests automatic vectoring the processor generates a vec tor number 25 to 31 determined by the interrupt level number If the response to the interrupt acknowledge bus cycle is a bus error the interrupt is taken to be spurious and the spurious interrupt vector number 24 is generated The exception vector number program counter and status register are saved on the supervisor stack The saved value of the program counter is the address of the instruc tion that would have executed if the interrupt had not occurred Priority level seven interrupt is a special case Level seven interrupts are nonmaskable interrupts NMI Level seven requests are transition sensitive to eliminate redundant servicing and concomitant stack overflow Transition sensitive means that the level seven input must change state before the CPU will detect an interrupt An NMI is generated each time the interrupt request level changes to level seven re gardless of priority mask value and each time the priority mask changes from seven to a low
223. he UNLK instruction removes a stack frame from the end of the list by loading an ad dress into the stack pointer and pulling the value at that address from the stack When the instruction operand is the address of the link address at the bottom of a stack frame the effect is to remove the stack frame from both the stack and the linked list 4 8 Pipeline Synchronization with the NOP Instruction Although the no operation NOP instruction performs no visible operation it does force synchronization of the instruction pipeline since all previous instructions must complete execution before the NOP begins MOTOROLA INSTRUCTION SET CPU32 4 194 REFERENCE MANUAL SECTION 5PROCESSING STATES This section describes the processing states of the CPUS2 It includes a functional de scription of the bits in the supervisor portion of the status register and an overview of actions taken by the processor in response to exception conditions 5 1 State Transitions The processor is in normal background or exception state unless halted When the processor fetches instructions and operands or executes instructions it is in the normal processing state The stopped condition which the processor enters when a STOP or LPSTOP instruction is executed is a variation of the normal state in which no further bus cycles are generated Background state is an alternate operational mode used for system debugging Refer to SECTION 7 DEVELOPMENT SUPPORT for more informatio
224. he contents of the VBR The sum is the memory address of the vector 6 1 2 Types of Exceptions An exception can be caused by internal or external events An internal exception can be generated by an instruction or by an error The TRAP TRAPcc TRAPV BKPT CHK CHK2 RTE and DIV instructions can cause excep tions during normal execution Illegal instructions instruction fetches from odd ad dresses word or long word operand accesses from odd addresses and privilege violations also cause internal exceptions MOTOROLA EXCEPTION PROCESSING CPU32 6 2 REFERENCE MANUAL Sources of external exception include interrupts breakpoints bus errors and reset re quests Interrupts are peripheral device requests for processor action Breakpoints are used to support development equipment Bus error and reset are used for access con trol and processor restart 6 1 3 Exception Processing Sequence For all exceptions other than a reset exception exception processing occurs in the fol lowing sequence Refer to 6 2 1 Reset for details of reset processing As exception processing begins the processor makes an internal copy of the sta tus register After the copy is made the processor state bits in the status register are changed the S bit is set establishing supervisor access level and bits T1 and are cleared disabling tracing For reset and interrupt exceptions the inter rupt priority mask is also updated Next the exception number
225. he ex tend bit is included in the rotation For register rotation the rotation count can be spec ified in either of two ways 1 Immediate The count 1 8 is specified by the instruction 2 Register The count is the value in the data register specified by the instruc tion modulo 64 The size of the operation for register destinations is specified as byte word or long The contents of memory ea can be rotated one bit only and operand size is restrict ed to a word The ROXL instruction rotates the bits of the operand to the left the rotate count deter mines the number of bit positions rotated Bits rotated out of the high order bit go to the carry bit and the extend bit the previous value of the extend bit rotates into the low order bit ROXL lt lt lt lt X lt The ROXR instruction rotates the bits of the operand to the right the rotate count de termines the number of bit positions rotated Bits rotated out of the low order bit go to the carry bit and the extend bit the previous value of the extend bit rotates into the high order bit ROXR CPU32 REFERENCE MANUAL INSTRUCTION SET MOTOROLA 4 133 ROXL ROXR Rotate with Extend ROXL ROXR Condition Codes X N 2 0 X Set to the value of the last bit rotated out of the operand Unaffected when count is zero N Set if
226. he index value is the long integer in the index register L The term scl refers to index scale selection and may be 1 2 4 or 8 The index value is scaled according to bits 10 9 Codes 00 01 10 or 11 select index scaling of 1 2 4 or 8 respectively 3 4 2 6 Address Register Indirect With Index Base Displacement The full format indexed addressing mode requires an index register indicator and an optional 16 or 32 bit sign extended base displacement The index register indicator includes size and scale information In this mode the operand is in memory The ad dress of the operand is the sum of the contents of the address register the scaled con tents of the sign extended index register and the base displacement GENERATION EA Xn SCALE bd ASSEMBLER SYNTAX bd An Xn SIZE SCALE MODE 110 REGISTER n 31 0 ADDRESS REGISTER An gt MEMORY ADDRESS 31 0 BASE DISPLACEMENT SIGN EXTENDED VALUE 5 31 0 INDEX REGISTER SIGN EXTENDED VALUE Y SCALE SCAEVAUE 9Q 9S Y 81 MEMORY ADDRESS NUMBER OF EXTENSION WORDS 1 2 OR3 OPERAND MOTOROLA DATA ORGANIZATION AND ADDRESSING CAPABILITIES CPU32 3 6 REFERENCE MANUAL 3 4 3 Special Addressing Modes These special addressing modes do not use the register field to specify a register num ber but rather to specify a submode 3 4 3 1 Program Counter Indirect With Displacement In this mode the
227. he location where fetching will commence after transition from background mode to normal mode This register should be accessed to change the flow of a program under development Changing the RPC to an odd value will cause an address error when normal mode prefetching begins CPU ACTIVITY DEVELOPMENT SYSTEM ACTIVITY ENTER BDM ASSERT FREEZE SIGNAL WAIT FOR COMMAND SEND INITIAL COMMAND LOAD COMMAND REGISTER ENABLE SHIFT CLOCK SHIFT OUT 17 BITS DISABLE SHIFT CLOCK EXECUTE COMMAND LOAD NOT READY RESPONSE PERFORM COMMAND STORE RESULTS READ RESULTS NEW COMMAND LOAD COMMAND REGISTER ENABLE SHIFT CLOCK SHIFT IN OUT 17 BITS DISABLE SHIFT CLOCK READ RESULT REGISTER IF RESULTS YES NOT READY NO CONTINUE Figure 7 4 BDM Command Execution Flowchart MOTOROLA DEVELOPMENT SUPPORT CPU32 7 6 REFERENCE MANUAL 7 2 5 3 Current Instruction Program Counter PCC The PCC holds a pointer to the first word of the last instruction executed prior to tran sition into background mode Due to instruction pipelining the instruction pointed to may not be the instruction which caused the transition An example is a breakpoint on a released write The bus cycle may overlap as many as two subsequent instructions before stalling the instruction sequencer A breakpoint asserted during this cycle will not be acknowledged until the end of the instruction executing at completion of the
228. he queue which is illustrated as follows CPU32 DATA ORGANIZATION AND ADDRESSING CAPABILITIES MOTOROLA REFERENCE MANUAL 3 17 LOW MEMORY FREE PUT An LAST PUT NEXT GET GET Am LAST GET FREE HIGH MEMORY To implement the queue as a circular buffer the get or put operation should be per formed first and then the relevant address register should be checked and if neces sary adjusted The address register is adjusted by adding the buffer length in bytes to the register contents MOTOROLA DATA ORGANIZATION AND ADDRESSING CAPABILITIES CPU32 3 18 REFERENCE MANUAL SECTION 4 INSTRUCTION SET This section describes the set of instructions provided in the CPU32 and demonstrates their use Descriptions of the instruction format and the operands used by instructions are included After a summary of the instructions by category a detailed description of each instruction is listed in alphabetical order Complete programming information is provided as well as a description of condition code computation and an instruction for mat summary The CPUS32 instructions include machine functions for all the following operations Data movement Arithmetic operations Logical operations e Shifts and rotates Bit manipulation Conditionals and branches System control The large instruction set encompasses a complete range of capabilities and com bined with the enhanced addressing modes provide
229. he third word BUS FETCH NEXT CONTROLLER INSTRUCTION EREDETOH INSTRUCTION OFFSET FAKEN PEN MOVE CONTROLLER CALC LE TO 00 EE MOVEQ 7 D1 BRA W FARAWAY MOVE L D1 D0 Figure 8 7 Example 3 Branch Negative Tail Example 3 illustrates three different aspects of instruction time calculation The branch instruction does not attempt to prefetch beyond the minimum number of words needed for itself The negative tail allows execution to begin sooner than would a three word pipeline There is a one clock delay due to late arrival of the displacement at the CPU Only changes of flow require negative tail calculation but the concept can be gener alized to any instruction only two words are required to be in the pipeline but up to three words may be present When there is an opportunity for an extra prefetch it is made A prefetch to replace an instruction can begin ahead of the instruction resulting in a faster processor CPU32 INSTRUCTION EXECUTION TIMING MOTOROLA REFERENCE MANUAL 8 9 8 3 Instruction Timing Tables The following assumptions apply to the times shown in the tables in this section A 16 bit data bus is used for all memory accesses Memory access times are based on two clock bus cycles with no wait states e The instruction pipeline is at the beginning of the instruction and is refilled by the end of the instruction Three values are listed for each instruction and addressing mode Head The num
230. hen a branch instruction is executed in both the taken and not taken cases Refer to Figures 8 5 and 8 6 The instruction stream is for a simple limit check with the variable already in a data register Instructions MOVEQ 7 D1 CMP LD1 DO BLE BNEXT MOVE LD1 A0 BUS 1 PRE 2 PRE PRE PRE PRE WRITE CONTROLLER FETCH FETCH FETCH FETCH FETCH FOR 3 INSTRUCTION CONTROLLER MOVEQ 7 D1 EXECUTION TIME CMP D1 D0 BLE B NOT TAKEN BUS 1 PRE 2 PRE 3 PRE 4 PRE WRITE WRITE CONTROLLER FETCH FETCH FETCH FETCH FOR 4 FOR 4 INSTRUCTION MOVE MP OFFSET NOT MOVE TO CONTROLLER p CALC TAKEN A0 EXECUTION MOVEQ CMP Time 701 0100 BLE B NOT TAKEN MOVE L D1 AO Figure 8 6 Example 2 Branch Not Taken MOTOROLA INSTRUCTION EXECUTION TIMING CPU32 8 8 REFERENCE MANUAL 8 2 3 Timing Example 3 Negative Tails This example Figure 8 7 shows how to use negative tail figures for branches and oth er change of flow instructions In this example bus speed is assumed to be four clocks per access Instruction three is at the branch destination Instructions MOVEQ 7 D1 BRA WFARAWAY MOVE LD1 DO Although the CPU32 has a two word instruction pipeline internal delay causes mini mum branch instruction time to be three bus cycles The negative tail is a reminder that an extra two clocks are available for prefetching a third word on a fast bus on a slow er bus there is no extra time for t
231. hen a memory location is the destination the oper ation is a byte operation and the bit number is modulo 8 In all cases bit zero refers to the least significant bit The bit number for this operation can be specified in either of two ways 1 Immediate The bit number is specified by a second word of the instruction 2 Register The specified data register contains the bit number Condition Codes X N 7 V C X Not affected N Not affected Z Set if the bit tested is zero Cleared otherwise V Not affected C Not affected Instruction Format Bit Number Static specified as immediate data 15 14 18 12 11 10 9 8 7 6 5 4 3 2 1 0 EFFECTIVE ADDRESS 0 0 0 0 1 0 0 0 0 0 MODE REGISTER 0 0 0 0 0 0 0 0 BIT NUMBER CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4 47 BIST Test a Bit BIST Instruction Fields Bit Number Static Bit Number field Specifies the bit number Effective Address field Specifies the destination location Only data addressing modes areallowed as shown Addressing Mode Mode Register Addressing Mode Mode Register Dn 000 Reg number Dn xxx W 111 000 An xxx L 111 001 An 010 Reg number An data An 011 Reg number An An 100 Reg number An 416 101 Reg number dig PC 111 010 dg An Xn 110 Reg number An dg PC Xn 111 011 bd An Xn 110 Reg number An bd
232. ied data register contains the bit number Condition Codes X N 7 V X Not affected N Not affected Z Set if the bit tested is zero Cleared otherwise V Not affected C Not affected Instruction Format Bit Number Static specified as immediate data 15 14 18 12 11 10 9 8 7 6 5 4 3 2 1 0 EFFECTIVE ADDRESS 0 0 0 0 1 0 0 0 1 0 MODE REGISTER 0 0 0 0 0 0 0 0 BIT NUMBER CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4 39 BCLR Test a Bit and Clear BCLR Instruction Fields Bit Number Static Bit Number field Specifies the bit number Effective Address field Specifies the destination location Only data alterable addressing modes are allowed as shown Addressing Mode Mode Register Addressing Mode Mode Register Dn 000 Reg number Dn xxx W 111 000 An xxx L 111 001 An 010 Reg number An data An 011 Reg number An An 100 Reg number An 416 101 Reg number dig PC dg An Xn 110 Reg number An dg PC Xn 110 Reg number bd PC Xn x Long only all others are byte only Instruction Format Bit Number Dynamic specified in a register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EFFECTIVE ADDRESS 0 0 0 0 REGISTER 1 1 0 MODE REGISTER Instruction Fields Bit Number Dynamic Re
233. ield provides for a maximum of 64 unique commands R W Field Direction of operand transfer is specified by this field When the bit is set the trans fer is from CPU to development system When the bit is clear data is written to the CPU or to memory from the development system CPU32 DEVELOPMENT SUPPORT MOTOROLA REFERENCE MANUAL 7 11 Operand Size For sized operations this field specifies the operand data size All addresses are expressed as 32 bit absolute values The size field is encoded as follows Encoding Operand Size 00 Byte 01 Word 10 Long 11 Reserved Address Data A D Field The A D field is used by commands that operate on address and data registers It determines whether the register field specifies a data or address register One in dicates an address register zero a data register For other commands this field may be interpreted differently Register Field In most commands this field specifies the register number when operating on an address or data register Extension Words as required At this time no command requires an extension word to specify fully the operation to be performed but some commands require extension words for addresses or immediate data Addresses require two extension words because only absolute long addressing is permitted Immediate data can be either one or two words in length byte and word data each require a single extension word long word data requ
234. ies the destination operand Only data addressing Addressing Mode Mode Register Addressing Mode Mode Register Dn 000 Reg number Dn xxx W 111 000 An xxx L 111 001 An 010 Reg number An data An 011 Reg number An An 100 Reg number An 416 An 101 Reg number An dig PC 111 010 dg An Xn 110 Reg number An dg PC Xn 111 011 bd An Xn 110 Reg number An bd PC Xn 111 011 Immediate field Data immediately following the instruction If size 00 the data is the low order byte of the immediate word If size 01 the data is the entire immediate word If size 10 the data is the next two immediate words MOTOROLA INSTRUCTION SET CPU32 4 60 REFERENCE MANUAL CMPM Compare Memory CMPM Operation Destination Source cc Assembler Syntax CMPM Ay Ax Attributes Size Byte Word Long Description Subtracts the source operand from the destination operand and sets the condition codes according to the results The destination location is not changed The operands are always addressed with the postincrement addressing mode using the address registers specified by the instruction Condition Codes X N 2 V X Not affected N Set if the result is negative Cleared otherwise Z Set if the result is zero Cleared otherwise V Set if an overflow is generated Cleared otherwise
235. ificant byte 16 and 32 bit oper ands are transmitted as 16 and 32 bits respectively XXX NEXT CMD ILLEGAL NOT READY Operand Data Result Data Status is returned as in the WRITE command 0FFFF for a successful operation and 10001 for a bus or address error during write CPU32 DEVELOPMENT SUPPORT MOTOROLA REFERENCE MANUAL 7 21 7 2 8 12 Resume Execution GO The pipeline is flushed and refilled before normal instruction execution is resumed Prefetching begins at the return PC and current privilege level If either the PC or SR is altered during BDM the updated value of these registers is used when prefetching commences NOTE The processor exits BDM when a bus error or address error occurs on the first instruction prefetch from the new PC the error is trapped as a normal mode exception The stacked value of the cur rent PC may not be valid in this case depending on the state of the machine prior to entering BDM For address error the PC does not reflect the true return PC Instead the stacked fault address is the odd return PC Command Format 0 0 0 0 1 1 e e e e e e e e e Command Sequence GO NORMAL 299 MODE XXX NEXT CMD ILLEGAL NOT READY Operand Data None Result Data None 7 2 8 13 Call User Code CALL This instruction provides a convenient way to patch user code The return PC is stacked at the l
236. ine Timing Diagram IPIPE should be sampled on the falling edge of the clock The assertion of IPIPE for a single cycle after one or more cycles of negation indicates use of the data in IRB advance of IRA into IRB Assertion for two clock cycles indi cates that a new instruction has started both IRA IRB and IRB gt gt IRC transfers MOTOROLA DEVELOPMENT SUPPORT CPU32 7 26 REFERENCE MANUAL have occurred Loading IRC always indicates that an instruction is beginning execu tion the opcode is loaded into IRC by the transfer In some cases instructions using immediate addressing begin executing and initiate a second pipeline advance at the same time IPIPE will not be negated between the two indications which implies the need for a state machine to track the state of IPIPE The state machine can be resynchronized during periods of inactivity on the signal 7 3 3 Opcode Tracking during Loop Mode IPIPE and IFETCH continue to work normally during loop mode IFETCH indicates all instruction fetches up through the point that data begins recirculating within the in struction pipeline IPIPE continues to signal the start of instructions and the use of ex tension words even though data is being recirculated internally IFETCH returns to normal operation with the first fetch after exiting loop mode CPU32 DEVELOPMENT SUPPORT MOTOROLA REFERENCE MANUAL 7 27 MOTOROLA DEVELOPMENT SUPPORT CPU32 7 28 REFERENCE MANUAL SECTION 8
237. inear interpolation to recover intermediate values from a sample of data points and thus conserves mem ory When the TBL instruction is executed the CPU32 looks up two table entries bounding the desired result and performs a linear interpolation between them Byte word and long word operand sizes are supported The result can be rounded according to a round to nearest algorithm or returned unrounded along with the fractional portion of the calculated result byte and word results only This extra precision can be used to reduce cumulative error in complex calculations See 4 6 Table Lookup and Inter polation Instructions for examples 4 1 2 Unimplemented Instructions The ability to trap on unimplemented instructions allows user supplied code to emulate unimplemented capabilities or to define special purpose functions However Motorola reserves the right to use all currently unimplemented instruction operation codes for future M68000 enhancements See 6 2 8 Illegal or Unimplemented Instructions for more details 4 2 Instruction Format All instructions consist of at least one word Some instructions can have as many as seven words as shown in Figure 4 1 The first word of the instruction called the op eration word specifies instruction length and the operation to be performed The re maining words called extension words further specify the instruction and operands These words may be immediate operands extensions to the effe
238. ires two words Both operands and addresses are transferred most significant word first 7 2 8 2 Command Sequence Diagram A command sequence diagram illustrates the serial bus traffic for each command Each bubble in the diagram represents a single 17 bit transfer across the bus The top half in each diagram corresponds to the data transmitted by the development system to the CPU the bottom half corresponds to the data returned by the CPU in response to the development system commands Command and result transactions are over lapped to minimize latency Figure 7 10 demonstrates the use of command sequence diagrams The cycle in which the command is issued contains the development system com mand mnemonic in this example read memory location During the same cycle the CPU responds with either the lowest order results of the previous command or with a command complete status if no results were required During the second cycle the development system supplies the high order 16 bits of the memory address The CPU returns a not ready response unless the received command was decoded as unimplemented in which case the response data is the il legal command encoding If an illegal command response occurs the development system should retransmit the command MOTOROLA DEVELOPMENT SUPPORT CPU32 7 12 REFERENCE MANUAL NOTE The not ready response can be ignored unless a memory bus cycle is in progress Otherwise the CPU can ac
239. is a long word quo tient and a long word remainder Two special conditions may arise during the operation 1 Division by zero causes a trap 2 Overflow may be detected before instruction completion If an overflow is detected the overflow condition code is set and the operands are unaffect ed MOTOROLA INSTRUCTION SET CPU32 4 66 REFERENCE MANUAL D VS Signed Divide D VS DIVSL DIVSL Condition Codes x N 7 V o 0 X Not affected N Set if quotient is negative Cleared otherwise Undefined if overflow or divide by zero occurs Z Set if quotient is zero Cleared otherwise Undefined if overflow or divide by zero occurs V Set if division overflow occurs undefined if divide by zero occurs Cleared oth erwise C Always cleared Instruction Format word form 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EFFECTIVE ADDRESS 1 0 0 0 REGISTER 1 1 1 MODE REGISTER Instruction Fields Register field Specifies any of the eight data registers This field always specifies the destination operand Effective Address field Specifies the source operand Only data addressing modes are allowed as shown Addressing Mode Mode Register Addressing Mode Mode Register Dn 000 Reg number Dn xxx W 111 000 An xxx L 111 001 An 010 Reg number An data 111 100 An 011 Reg number An An 1
240. is a valid command only when preceded by another DUMP or by a READ command Otherwise the results are undefined The NOP command can be used for inter command pad ding without corrupting the address pointer The size field is examined each time a DUMP command is given allowing the operand size to be altered dynamically Command Format 0 0 0 1 1 1 0 1 OP SIZE 0 0 0 0 0 0 Command Sequence DUMP BAT READ ird mewory Y OTHE di LOCATION NEXT CMD RESULT XXX NEXT CMD BERR AERR NOT READY XXX NEXT CMD ILLEGAL READY READ MEMORY LOCATION 22 DUMP LONG EN Y XXX J NOT READY XXX NEXT CMD MS RESULT LS RESULT XXX NEXT CMD BERR AERR NOT READY XXX NEXT CMD ILLEGAL NOT READY Operand Data None Result Data Requested data is returned as either a word or long word Byte data is returned in the least significant byte of a word result Word results return 16 bits of significant data long word results return 32 bits Status of the read operation is returned as in the READ command 0xxxx for success 10001 for bus or address errors MOTOROLA DEVELOPMENT SUPPORT CPU32 7 20 REFERENCE MANUAL 7 2 8 11 Fill Memory Block FILL FILL is used in conjunction with the WRITE command to fill large blocks of memory An initial WRITE is executed to set up the starting address of the block and to sup
241. is for the source effective address 8 3 4 Special Purpose MOVE Instruction The special purpose MOVE instruction table indicates the number of clock periods needed for the processor to fetch calculate and perform the special purpose MOVE operation on control registers or a specified effective address Footnotes indicate when to account for the appropriate effective address times The total number of clock cycles is outside the parentheses The numbers inside parenthe ses r p w are included in the total clock cycle number All timing data assumes two clock reads and writes MOTOROLA INSTRUCTION EXECUTION TIMING CPU32 8 14 REFERENCE MANUAL Head Tail Cycles EXG Rn Rm 2 0 4 0 1 0 MOVEC Cr Rn 10 0 14 0 2 0 MOVEC Rn Cr 12 0 14 16 0 1 0 MOVE CCR Dn 2 0 4 0 1 0 MOVE CCR CEA 0 2 4 0 1 1 MOVE Dn CCR 2 0 4 0 1 0 MOVE FEA CCR 0 0 4 0 1 0 MOVE SR Dn 2 0 4 0 1 0 MOVE SR CEA 0 2 4 0 1 1 MOVE Dn SR 4 2 10 0 3 0 FEA SR 0 2 10 0 3 0 MOVEM W CEA RL 1 0 84 n 4 n 1 2 0 1 MOVEM W RL CEA 1 0 8 n 4 0 2 1 MOVEM L CEA RL 1 0 12 n 4 2n 2 2 0 MOVEM L RL CEA 1 2 10 n 4 0 2 2n MOVEP W Dn d46 An 2 0 10 0 2 2 MOVEP W d16 An Dn 1 2 11 2 2 0 MOVEP L Dn 016 2 0 14 0 2 4 MOVEP L dig An Dn 1 2 19 4 2 0 MOVES Save CEA Rn 1 1 3 0 1 0 MOVES Op CEA Rn 7 1 11 X 1 0 MOVES
242. isable tracing Sets the S bit in the status register to establish supervisor privilege Sets the interrupt priority mask to the highest priority level 96111 Initializes the vector base register to zero 00000000 Generates a vector number to reference the reset exception vector Loads the first long word of the vector into the interrupt stack pointer Loads the second long word of the vector into the program counter Fetches and initiates decode of the first instruction to be executed Figure 6 2 is a flowchart of the reset exception Qo OT ON After initial instruction prefetches normal program execution begins at the address in the program counter The reset exception does not save the value of either the pro gram counter or the status register If a bus error or address error occurs during reset exception processing sequence a double bus fault occurs The processor halts and the HALT signal is asserted to indi cate the halted condition Execution of the RESET instruction does not cause a reset exception nor does it affect any internal CPU register but it does cause the CPU32 to assert the RESET signal resetting all internal and external peripherals CPU32 EXCEPTION PROCESSING MOTOROLA REFERENCE MANUAL 6 5 ENTRY t 1 gt 5 0 gt TO T1 7 gt 12 10 0 gt VBR FETCH VECTOR 0 il OTHERWISE BUS ERROR SP VECTOR 0 FETCH VECTOR 4 1 OTHERWISE BUS ERROR PC VECTOR 1 PREFETCH FIRST WORD BUS ERRO
243. it 3 of immediate operand is zero Unchanged otherwise Z Set if bit 2 of immediate operand is zero Unchanged otherwise V Set if bit 1 of immediate operand is zero Unchanged otherwise C Set if bit 0 of immediate operand is zero Unchanged otherwise Instruction Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 BYTE DATA 8 BITS MOTOROLA INSTRUCTION SET CPU32 4 126 REFERENCE MANUAL ORI to SR Operation Assembler Syntax Attributes Description Inclusive OR Immediate to Status Register ORI Privileged Instruction to 5 R If supervisor state then Source SR SR else TRAP ORI data SR Size Word Performs an inclusive OR operation of the immediate operand and the contents of the status register and stores the result in the status register All implemented bits of the status register are affected Condition Codes X N Z V C lt 2 Set if bit 4 of immediate operand is zero Unchanged otherwise Set if bit 3 of immediate operand is zero Unchanged otherwise Set if bit 2 of immediate operand is zero Unchanged otherwise Set if bit 1 of immediate operand is zero Unchanged otherwise Set if bit 0 of immediate operand is zero Unchanged otherwise Instruction Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 WORD D
244. leased Writes 6 16 6 19 Reset 6 5 Resource Scheduling 8 1 Return from Exception 6 13 Rotate Instructions 4 9 S Save and Restore Operation Timing 8 22 Serial Interface BDM 7 7 Shift and Rotate Instruction Timing 8 19 Shift and Rotate Instructions 4 9 Single Operand Instruction Timing 8 18 Six Word Stack Frame Normal 6 22 Sizing Dynamic Bus 6 16 6 23 Software Breakpoints 6 8 Software Fault Recovery 6 19 Space Formats 5 4 Type 0000 Breakpoint 5 4 Type 0001 MMU Access 5 4 Type 0010 Coprocessor Access 5 4 Type 0011 Internal Register Access 5 4 Type 1111 Interrupt Acknowledge 5 5 Special Addressing Modes 3 7 Special Purpose MOVE Instruction Timing 8 14 Stack Frames 6 3 6 21 Supervisor 2 2 3 15 System 3 16 User 2 2 3 15 State Transition 5 1 Status Register 2 3 Subroutine Calls Nested 4 194 Supervisor Privilege Level 5 2 Surface Interpolation 4 188 4 194 Synchronization Pipeline with NOP 4 194 System Control Instructions 4 11 Stack 3 16 Te Table Lookup and Interpolation 4 187 Examples 8 Bit Independent Variable 4 191 Compressed Table 4 190 Maintaining Precision 4 192 MOTOROLA l 3 Standard Usage 4 188 Surface Interpolations 4 194 Instruction Using the 4 188 Tests Condition 4 12 Timing Examples Branch Instructions 8 8 Execution Overlap 8 7 Negative Tails 8 9 Timing Tables 8 10 Arihmetic Logic Instructions 8 15 Binary Coded Decimal Extended Instructions 8 18 Bit Manipulation Inst
245. lly Table 7 1 summarizes the processing of each source for both enabled and disabled cases As shown in Table 7 1 the BKPT instruction never causes a transition into BDM Table 7 1 BDM Source Summary Source BDM Enabled BDM Disabled BKPT Background Breakpoint Exception Double Bus Fault Background Halted BGND Instruction Background Illegal Instruction BKPT Instruction Opcode Substitution Opcode Substitution Illegal Instruction Illegal Instruction 7 2 2 1 External BKPT Signal Once enabled BDM is initiated whenever assertion of BKPT is acknowledged If BDM is disabled a breakpoint exception vector 0C is acknowledged The BKPT input has the same timing relationship to the data strobe trailing edge as does read cycle data There is no breakpoint acknowledge bus cycle when BDM is entered 7 2 2 2 BGND Instruction An illegal instruction 4AFA is reserved for use by development tools The CPU32 defines 4AFA BGND to be a BDM entry point when BDM is enabled If BDM is dis abled an illegal instruction trap is acknowledged lllegal instruction traps are dis cussed in 6 2 8 Illegal or Unimplemented Instructions MOTOROLA DEVELOPMENT SUPPORT CPU32 REFERENCE MANUAL 7 2 2 3 Double Bus Fault The CPU32 normally treats a double bus fault or two bus faults in succession as a catastrophic system error and halts When this condition occurs during initial system debug a fault in the reset logic fu
246. lly sized bus cycle Dynamic sizing occurs on the ex ternal bus and is transparent to the CPU Byte size is shown only when the original operand was a byte The field is reloaded into the bus controller if the RR bit is set dur ing unstacking The SIZ field is encoded as follows 00 Long word 01 Byte 10 Word 11 Unused reserved The function code for the faulted cycle is stacked in the FUNC field of the SSW which is a copy of FC2 FCO for the faulted bus cycle This field is reloaded into the bus con troller if the RR bit is set during unstacking All unused bits are stacked as zeros and are ignored during unstacking Further discussion of the SSW is included in 6 3 1 Types of Faults 6 3 1 Types of Faults An efficient implementation of instruction restart dictates that faults on some bus cy cles be treated differently than faults on other bus cycles The CPU32 defines four fault types released write faults faults during exception processing faults during MOVEM operand transfer and faults on any other bus cycle 6 3 1 1 Type I Released Write Faults CPUS32 instruction pipelining can cause a final instruction write to overlap the execu tion of a following instruction A write that is overlapped is called a released write Since the machine context for the instruction that queued the write is lost as soon as the following instruction starts it is impossible to restart the faulted instruction Released write fault
247. long word divisor long word quotient and long word remainder A set of extended instructions provides multiprecision and mixed size arithmetic These instructions are add extended ADDX subtract extended SUBX sign extend EXT and negate binary with extend NEGX Refer to Table 4 3 for a summary of the integer arithmetic operations Table 4 3 Integer Arithmetic Operations Instruction Syntax Operand Size Operation ADD Dn ea 8 16 32 Source Destination Destination ea Dn 8 16 32 ADDA ea An 16 32 Source Destination Destination ADDI data ea 8 16 32 Immediate data Destination Destination ADDQ data ea 8 16 32 Immediate data Destination Destination ADDX Dn Dn 8 16 32 Source Destination X Destination An An 8 16 32 CLR ea 8 16 32 0 Destination CMP ea Dn 8 16 32 Destination Source CCR shows results CMPA ea An 16 32 Destination Source CCR shows results CMPI data ea 8 16 32 Destination Data CCR shows results CMPM An An 8 16 32 Destination Source CCR shows results CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4 7 Table 4 3 Integer Arithmetic Operations Instruction Syntax Operand Size Operation CMP2 ea Rn 8 16 32 Lower bound Rn Upper bound CCR shows result DIVS DIVU ea Dn 32 16 16 16 D
248. me as the carry bit Set if the result is negative Cleared otherwise Cleared if the result is nonzero Unchanged otherwise Set if an overflow occurs Cleared otherwise Set if a carry is generated Cleared otherwise O cNZ JX NOTE Normally the Z condition code bit is set via programming before the start of an operation This allows successful tests for zero results upon completion of multiple precision operations Instruction Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 0 1 REGISTER Rx 1 SIZE 0 0 R M REGISTER Ry MOTOROLA INSTRUCTION SET CPU32 4 24 REFERENCE MANUAL A D DX Add Extended A D DX Instruction Fields Register Rx field Specifies the destination register If R M 0 specifies a data register If R M 1 specifies an address register for predecrement addressing mode Size field Specifies the size of the operation 00 Byte operation 01 Word operation 10 Long operation R M field Specifies the operand address mode 0 The operation is data register to data register 1 The operation is memory to memory Register Ry field Specifies the source register If R M 0 specifies a data register If R M 1 specifies an address register for predecrement addressing mode CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4 25 AND Logical AND AND Operation Source e Destination Destination Assembler AND ea Dn Syntax AND Dn ea
249. me attributed to instructions A B and C after considering the overlap is illustrated in Figure 8 3 The overlap time is attributed to the execution time of the completing instruction The following equation shows the method for calculating the overlap time Overlap min Heady 1 INSTRUCTION A INSTRUCTION B INSTRUCTION C OVERLAP OVERLAP PERIOD PERIOD ABSORBED BY ABSORBED BY INSTRUCTION A INSTRUCTION B Figure 8 3 Attributed Instruction Times MOTOROLA INSTRUCTION EXECUTION TIMING CPU32 8 4 REFERENCE MANUAL 8 1 5 Effects of Wait States The CPU32 access time for on chip memory and peripherals is two clocks While two clock external accesses are possible when the bus is operated in a synchronous mode a typical external memory speed is three or more clocks All instruction times listed in this section are for word access only unless an explicit exception is given and are based on the assumption that both instruction fetches and operand cycles are to a two clock memory Any time a long access is made time for the additional bus cycle s must be added to the overall execution time Wait states due to slow external memory must be added to the access time for each bus cycle A typical application has a mixture of bus speeds program execution from an off chip ROM accesses to on chip peripherals storage of variables in slow off chip RAM and accesses to external peripherals with speeds ranging from
250. moderate to very slow To arrive at an accurate instruction time calculation each bus access must be individually considered Many instructions have a head cycle count which can overlap the cycles of an operand fetch to slower memory started by a previous instruction In these cases an increase in access time has no effect on the total execution time of the pair of in structions To trace instruction execution time by monitoring the external bus note that the order of operand accesses for a particular instruction sequence is always the same pro vided bus speed is unchanged the interleaving of instruction prefetches with operands within each sequence is identical 8 1 6 Instruction Execution Time Calculation The overall execution time for an instruction depends on the amount of overlap with previous and following instructions In order to calculate an instruction time estimate the entire code sequence must be analyzed To derive the actual instruction execution times for an instruction sequence the instruction times listed in the tables must be ad justed to account for overlap The formula for this calculation is min T4 H2 Co min To min where CN is the number of cycles listed for instruction N Hy is the head time for instruction N TN is the tail time for instruction N min TN HM is the minimum of parameters TN and HM CPU32 INSTRUCTION EXECUTION TIMING MOTOROLA REFERENCE
251. n Exception processing refers specifically to the transition from normal processing of a program to normal processing of system routines interrupt routines and other excep tion handlers Exception processing includes the stack operations the exception vec tor fetch and the filling of the instruction pipeline caused by an exception Exception processing ends when execution of an exception handler routine begins Refer to SECTION 6 EXCEPTION PROCESSING for comprehensive information A catastrophic system failure occurs if the processor detects a bus error or generates an address error while in the exception processing state This type of failure halts the processor For example if a bus error occurs during exception processing caused by a bus error the CPU32 assumes that the system is not operational and halts The halted condition should not be confused with the stopped condition After the pro cessor executes a STOP or LPSTOP instruction execution of instructions can resume when a trace interrupt or reset exception occurs 5 2 Privilege Levels To protect system resources the processor can operate with either of two levels of ac cess user or supervisor Supervisor level is more privileged than user level All in structions are available at the supervisor level but execution of some instructions is not permitted at the user level There are separate stack pointers for each level The S bit in the status register indicates privil
252. n from SR Operation If supervisor state then SR Destination else TRAP Assembler Syntax MOVE SR ea Attributes Size Word Description Moves the data in the status register to the destination location The destination must be of word length Unimplemented bits are read as zeros Condition Codes Not affected Instruction Format 15 14 18 12 11 10 9 8 7 6 5 4 3 2 1 0 EFFECTIVE ADDRESS MODE REGISTER Instruction Fields Effective Address field Specifies the destination location Only data alterable addressing modes are allowed as shown Addressing Mode Mode Register Addressing Mode Mode Register Dn 000 Reg number Dn xxx W 111 000 An xxx L 111 001 An 010 Reg number An data An 011 Reg number An An 100 Reg number An 416 An 101 Reg number An 916 PC dg An Xn 110 Reg number An dg PC Xn bd An Xn 110 Reg number An bd PC Xn NOTE Use the MOVE from CCR instruction to access only the condition codes CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4 95 MOVE Move to the Status Register MOVE to SR Privileged Instruction to SR Operation If supervisor state then Source 5 SR else TRAP Assembler Syntax MOVE ea SR Attributes Size Word Description Moves the data in the source operand to the status register The source operand i
253. n use operands of more than one size a suffix is used with the mnemonic of the instruction W Word L Long word B In instruction set descriptions changes in CCR bits are shown as follows Set according to result of operation Not affected by operation 0 Cleared 1 Set U Undefined after operation CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4 13 INSTRUCTION NAME OPERATION DESCRIPTION ABCD Add Deci Operation Destination ASSEMBLER SYNTAX FOR THIS INSTRUCTION Assembler Syntax ABCD Dy Dx ABCD Ay Ax SIZE ATTRIBUTE Attributes Size Byte TEXT DESCRIPTION OF INSTRUCTION OPERATION CONDITION CODE EFFECTS Description Adds the source operatio and stores the result in the destinati decimal arithmetic The operands different ways 1 Data register to data register specified in the instruction 2 Memory to memory The addressing mode using the ad INSTRUCTION FORMAT THIS SPECIFIES THE BIT PATTERN AND FIELDS OF THE OPERATION AND COMMAND WORDS AND ANY OTHER WORDS THAT ARE ALWAYS PART OF THE INSTRUCTION THE EFFECTIVE ADDRESS EXTENSIONS ARE NOT EXPLICITLY ILLUSTRATED THE EXTENSION WORDS IF ANY FOLLOW IMMEDIATELY AFTER THE ILLUSTRATED PORTIONS OF THE INSTRUCTIONS MEANINGS AND ALLOWED VALUES FOR THE VARIOUS FIELDS REQUIRED BY THE INSTRUCTION FORMAT
254. n words thus software that uses this encoding is both upward and downward compatible across all processors in the product line However the other values of SCALE are not found in both extension formats therefore while software can be easily migrated in an upward compatible direction only nonscaled addressing is supported in a downward fashion If the MC68000 were to execute an instruction that encoded a scaling factor the scaling factor would be ignored and would not ac cess the desired memory address 3 7 Other Data Structures In addition to supporting the array data structure with the index addressing mode M68000 processors also support stack and queue data structures with the address register indirect postincrement and predecrement addressing modes A stack is a last in first out LIFO list a queue is a first in first out FIFO list When data is added to a stack or queue it is pushed onto the structure when it is removed it is popped or pulled from the structure The system stack is used implicitly by many instructions user stacks and queues may be created and maintained through use of addressing modes 3 7 1 System Stack Address register 7 A7 is the system stack pointer SP The SP is either the supervi sor stack pointer SSP or the user stack pointer USP depending on the state of the S bit in the status register If the S bit indicates the supervisor state the SSP is the SP and the USP cannot be referenced a
255. nd mode is covered in SECTION 7 DEVEL OPMENT SUPPORT Condition Codes x N 7 V C X Not affected N Not affected Z Not affected V Not affected C Not affected Instruction Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 14 0 0 1 0 0 1 0 1 0 1 1 1 1 1 0 1 0 CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4 41 B KPT Breakpoint B KPT Operation Run breakpoint acknowledge cycle If acknowledged then execute returned operation word else TRAP as illegal instruction Assembler Syntax BKPT lt data Attributes Unsized Description Executes a breakpoint acknowledge bus cycle Bits 2 4 of the address bus are set to the value of the immediate data 0 to 7 and bits 0 and 1 of the address bus are set to 0 The breakpoint acknowledge cycle accesses the CPU space addressing type 0 and provides the breakpoint number specified by the instruction on address lines A4 to A2 If external hardware terminates the cycle with DSACKx the data on the bus an in struction word is inserted into the instruction pipe and is executed after the breakpoint instruction The breakpoint instruction requires a word transfer if the first bus cycle accesses an 8 bit port a second cycle is required If external logic terminates the breakpoint acknowledge cycle with BERR i e no instruction word available the pro cessor takes an illegal instruction exception Refer to 6 2 5 Software Breakpoints for details of breakpoint ope
256. nly MOTOROLA INSTRUCTION SET CPU32 4 168 REFERENCE MANUAL UNLK Unlink UNLK Operation An gt SP SP An SP 4 gt SP Assembler Syntax UNLK An Attributes Unsized Description Loads the stack pointer from the specified address register then loads the address register with a long word pulled from the top of the stack Condition Codes Not affected Instruction Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 0 0 1 1 1 0 0 1 1 1 1 REGISTER Instruction Fields Register field Specifies the address register for the instruction CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4 169 4 5 Instruction Format Summary A summary of the primary words in each instruction of the instruction set follows The complete instruction definition consists of the primary words followed by the address ing mode operands such as immediate data fields displacements and index oper ands The four most significant bits of the first or only primary word provide a means of categorizing the instructions Table 4 11 is an operation code opcode map that lists an instruction category for each combination of these bits Table 4 11 Operation Code Map Bits 15 12 Operation 0000 Bit Manipulation MOVEP Immediate 0001 Move Byte 0010 Move Long 0011 Move Word 0100 Miscellaneous 0101 ADDQ SUBQ Scc DBcc TRAPcc 0110 Bcc BSR BRA 0111
257. nsion words for both source and destination EA and a 32 bit base displacement for both addresses CPU32 DATA ORGANIZATION AND ADDRESSING CAPABILITIES MOTOROLA REFERENCE MANUAL 3 9 SINGLE EA INSTRUCTION FORMAT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EFFECTIVE ADDRESS X X X X X X X X X X MODE REGISTER BRIEF FORMAT EXTENSION WORD 15 14 12 11 10 9 8 7 0 D A REGISTER W L SCALE 0 DISPLACEMENT FULL FORMAT EXTENSION WORD S 15 14 12 11 10 9 8 7 6 5 4 3 2 0 D A REGISTER W L SCALE 1 BS IS BD SIZE 0 ns BASE DISPLACEMENT 0 1 OR 2 WORDS Field Definition Field Definition Instruction BS Base Register Suppress Register General Register Number 0 Base Register Added Extension 1 Base Register Suppressed Register Index Register Number IS Index Suppress D A Index Register Type 0 Evaluate and Add Index Operand 0 Dn 1 Suppress Index Operand 1 An BD SIZE Base Displacement Size W L Word Long Word Index Size 00 Reserved 0 Sign Extended Word 01 Null Displacement 1 Long Word 10 Word Displacement Scale Scale Factor 11 Long Word Displacement 00 1 IIS Index Indirect Selection 01 2 Indirect and Indexing Operand 10 4 Determined in Conjunction with Bit 6 11 8 Index Suppress Memory indirect addressing will cause illegal instruction trap must be 000 if IS 1 Figure 3 2 Effective Address Specification Formats EA modes c
258. nstructions ac count for all operand writes not considered released All type II faults cause an immediate exception that aborts the current instruction Any registers that were altered as the result of an effective address calculation i e postin crement or predecrement are restored prior to processing the bus cycle fault The SSW for faults in this category contains the following bit pattern 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0 0 0 0 0 B1 BO 0 RM IN RW LG SIZ FUNC The trace pending bit is always cleared since the instruction will be restarted upon re turn from the handler Saving a pending exception on the stack would result in a trace exception being taken prior to restarting the instruction If the exception handler does not alter the stacked SR trace bits the trace is requeued when the instruction is start ed The breakpoint pending bits are stacked in the SSW even though the instruction is restarted upon return from the handler This avoids problems with bus state analyzer equipment that has been programmed to breakpoint only the first access to a specific location or to count accesses to that location If this response is not desired the ex ception handler can clear the bits before return The RM IN RW LG FUNC and SIZ fields all reflect the type of bus cycle that caused the fault If the bus cycle was an RMW the RM bit will be set and the RW bit will show whether the fault wa
259. o register DI 1 64 bit product to be returned to Dh DI Register Dh field If Size is 1 specifies the data register into which the high order 32 bits of the product are loaded If Dh DI and Size is 1 the results of the operation are undefined This field is unused otherwise CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4 109 MULU Unsigned Multiply MULU Operation Source Destination Destination Assembler Syntax MULU W Dn16x16 32 MULU L ea DI32x32 32 MULU L ea Dh DI32x32 64 Attributes Size Word Long Description Multiplies two unsigned operands yielding an unsigned result In the word form the multiplier and multiplicand are both word operands and the result is a long word operand A register operand is the low order word the upper word of the register is ignored All 32 bits of the product are saved in the destina tion data register In the long form the multiplier and multiplicand are both long word operands and the result is either a long word or a quad word The long word result is the low order 32 bits of the quad word result the high order 32 bits of the product are dis carded Condition Codes X N 7 V C X Not affected N Set if the result is negative Cleared otherwise Z Set if the result is zero Cleared otherwise V Set if overflow Cleared otherwise C Always cleared NOTE Overflow V21 can occur only when multiplying 32 bit operands to yield a 32 bit r
260. o ways 1 Immediate The bit number is specified by the second word of the instruc tion 2 Register The specified data register contains the bit number Condition Codes x N Z V X Not affected N Not affected Z Set if the bit tested is zero Cleared otherwise V Not affected C Not affected Instruction Format Bit Number Static specified as immediate data 15 14 18 12 11 10 9 8 7 6 5 4 3 2 1 0 EFFECTIVE ADDRESS 0 0 0 0 1 0 0 0 1 1 MODE REGISTER 0 0 0 0 0 0 0 0 BIT NUMBER MOTOROLA INSTRUCTION SET CPU32 4 44 REFERENCE MANUAL BS ET Test a Bit and Set BS ET Instruction Fields Bit Number Static Bit Number field Specifies the bit number Effective Address field Specifies the destination location Only data alterable addressing modes are allowed as shown Addressing Mode Mode Register Addressing Mode Mode Register Dn 000 Reg number Dn xxx W 111 000 An xxx L 111 001 An 010 Reg number An data An 011 Reg number An An 100 Reg number An 416 101 Reg number dig PC dg An Xn 110 Reg number An dg PC Xn bd An Xn 110 Reg number An bd PC Xn Long only all others are byte only Instruction Format Bit Number Dynamic specified in a register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EFFECTIVE ADDRE
261. ocation pointed to by the current SP The stacked PC serves as a return address to be restored by the RTS command that terminates the patch routine After stacking is complete the 32 bit operand data is loaded into the PC The pipeline is flushed and refilled from the location pointed to by the new PC BDM is exited and nor mal mode instruction execution begins NOTE If a bus error or address error occurs during return address stacking the CPU returns an error status via the serial interface and remains in BDM MOTOROLA DEVELOPMENT SUPPORT CPU32 7 22 REFERENCE MANUAL If a bus error or address error occurs on the first instruction prefetch from the new PC the processor exits BDM and the error is trapped as a normal mode exception The stacked value of the current PC may not be valid in this case depending on the state of the machine prior to entering BDM For address error the PC does not reflect the true return PC Instead the stacked fault address is the odd return PC Command Format 15 A 95 EN A o p A 0 0 0 0 1 0 0 0 0 0 e e e e e Command Sequence CALL MS ADDR LS ADDR 222 N NOT READY NOT READY STACK RETURN PC UN XXX NEXT CMD ILLEGAL NOT READY FREEZE NEGATED PREFETCH STARTED Operand Data XXX NEXT CMD BERR AERR READY The 32 bit operand data i
262. oces sor Interrupt recognition and subsequent processing are based on internal interrupt re quest signals IRQ7 IRQ1 and the current priority set in status register priority mask I 2 0 Interrupt request level zero IRQ7 IRQ1 negated indicates that no service is re quested When an interrupt of level one through six is requested via IRQ6 IRQ1 the processor compares the request level with the interrupt mask to determine whether the interrupt should be processed Interrupt requests are inhibited for all priority levels less than or equal to the current priority Level seven interrupts are nonmaskable IRQ7 IRQ1 are synchronized and debounced by input circuitry on consecutive rising edges of the processor clock To be valid an interrupt request must be held constant for at least two consecutive clock periods Interrupt requests do not force immediate exception processing but are left pending A pending interrupt is detected between instructions or at the end of exception pro cessing all interrupt requests must be held asserted until they are acknowledged by the CPU If the priority of the interrupt is greater than the current priority level excep tion processing begins MOTOROLA EXCEPTION PROCESSING CPU32 6 12 REFERENCE MANUAL Exception processing occurs as follows First the processor makes an internal copy of the status register After the copy is made the processor state bits in the status reg ister are c
263. ode Mode Register Dn xxx W 111 000 An xxx L 111 001 An 010 Reg number An data An An Nem see 416 An 101 Reg number An dig PC 111 010 dg An Xn 110 Reg number An dg PC Xn 111 011 bd An Xn 110 Reg number An bd PC Xn 111 011 CPUS2 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4 81 JSR Jump to Subroutine JSR Operation SP 4 gt Sp PC gt SP Destination Address Assembler Syntax JSR ea Attributes Unsized Description Pushes the long word address of the instruction immediately follow ing the JSR instruction onto the system stack Program execution then continues at the address specified by the instruction Condition Codes Not affected Instruction Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EFFECTIVE ADDRESS MODE REGISTER Instruction Fields Effective Address field Specifies the address of the next instruction Only control addressing modes are allowed as shown Addressing Mode Mode Register Addressing Mode Mode Register Dn xxx W 111 000 An xxx L 111 001 An 010 Reg number An data E An An 416 101 Reg number dig PC 111 010 dg An Xn 110 Reg number An dg PC Xn 111 011 bd An Xn 110 Reg number An bd PC Xn 111 011 MOTOROLA INSTRUCTION SET C
264. ode only a register to memory operation is allowed The registers are stored starting at the specified address minus the operand length 2 or 4 and the address is decremented by the operand length following each transfer The order of storing is from address register 7 to address register 0 then from data register 7 to data register 0 When the instruction has completed the decremented address register contains the address of the last operand stored In the CPU 32 if the addressing register is also moved to memory the value written is the decremented value If the effective address is specified by the postincrement mode only a memory to register operation is allowed The registers are loaded starting at the specified address the address is incremented by the operand length 2 or 4 following each transfer The order of loading is the same as that of control mode addressing When the instruction has completed the incremented address register contains the address of the last operand loaded plus the operand length In the CPUS2 if the addressing register is also loaded from memory the value loaded is the value fetched plus the operand length INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4 99 MOVEM Move Multiple Registers MOVEM Condition Codes Not affected Instruction Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EFFECTIVE ADDRESS 0 1 0 0 1 dr 0 0 1 SIZE MODE REGISTER REGISTER LIST MASK
265. of the currently executing instruction the program counter of the next instruction to execute and a copy of the status register are saved on the supervisor stack 6 2 7 Format Error The processor checks certain data values for control operations The validity of the stack format code and in the case of a bus cycle fault format the version number of the processor that generated the frame are checked during execution of the RTE in struction This check ensures that the program does not make erroneous assumptions about information in the stack frame If the format of the control data is improper the processor generates a format error ex ception This exception saves a four word format exception frame and then vectors through vector table entry number 14 The stacked program counter is the address of the RTE instruction that discovered the format error 6 2 8 Illegal or Unimplemented Instructions An instruction is illegal if it contains a word bit pattern that does not correspond to the bit pattern of the first word of a legal CPU32 instruction if it is a MOVEC instruction that contains an undefined register specification field in the first extension word or if it contains an indexed addressing mode extension word with bits 5 4 00 or bits 3 0 0000 If an illegal instruction is fetched during instruction execution an illegal instruction ex ception occurs This facility allows the operating system to detect program errors or to em
266. on Format lt 2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 EFFECTIVE ADDRESS 0 1 0 0 0 0 1 0 SIZE MODE REGISTER Instruction Fields Size field Specifies the size of the operation 00 Byte operation 01 Word operation 10 Long operation CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4 53 CLR Clear an Operand CLR Effective Address field Specifies the destination location Only data alterable addressing modes are allowed as shown Addressing Mode Mode Register Addressing Mode Mode Register Dn 000 Reg Number Dn xxx W 111 000 An xxx L 111 001 An 010 Reg number An data An 011 Reg number An An 100 Reg number An 416 An 101 Reg number An 96 PC dg An Xn 110 Reg number An dg PC Xn bd An Xn 110 Reg number An bd PC Xn MOTOROLA INSTRUCTION SET CPU32 4 54 REFERENCE MANUAL CMP Compare CMP Operation Destination Source cc Assembler Syntax CMP ea Dn Attributes Size Byte Word Long Description Subtracts the source operand from the destination data register and sets condition codes according to the result The data register is not changed Condition Codes X N 7 V X Not affected N Set if the result is negative Cleared otherwise Z Set if the result is zero Cleared otherwise V Set if an
267. on Format removes 10 words Resumes execution of coprocessor instruction 1010 MC68020 Short Format removes 16 words and resumes instruction execution 1011 MC68020 Long Format removes 46 words and resumes instruction execution Any other value in this field causes the processor to take a format error exception CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4 137 RTR Return and Restore Condition Codes RTR Operation SP CCR SP 2 gt SP SP gt PC SP 4 gt SP Assembler Syntax RTR Attributes Unsized Description Pulls the condition code and program counter values from the stack The previous condition codes and program counter values are lost The supervisor portion of the status register is unaffected Condition Codes Set to the condition codes from the stack Instruction Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 0 0 1 1 1 0 0 1 1 1 0 1 1 1 MOTOROLA INSTRUCTION SET CPU32 4 138 REFERENCE MANUAL RTS Return from Subroutine RTS Operation SP gt PC SP 4 SP Assembler Syntax RTS Attributes Unsized Description Pulls the program counter value from the stack The previous value is lost Condition Codes Not affected Instruction Format 15 14 13 12 11 10 9 8 7 6 5 1 0 0 1 0 0 1 1 1 0 0 1 1 0 1 CPU32 INSTRUCTION SET MOTOROLA REFEREN
268. ondition Codes X N 7 V X Not affected N Not affected Z Set if the bit tested is zero Cleared otherwise V Not affected C Not affected Instruction Format Bit Number Static specified as immediate data 15 14 18 12 11 10 9 8 7 6 5 4 3 2 1 0 EFFECTIVE ADDRESS 0 0 0 0 1 0 0 0 0 1 MODE REGISTER 0 0 0 0 0 0 0 0 BIT NUMBER CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4 37 BCHG Test a Bit and Change BCHG Instruction Fields Bit Number Static Bit Number field Specifies the bit number Effective Address field Specifies the destination location Only data alterable addressing modes are allowed as shown Addressing Mode Mode Register Addressing Mode Mode Register Dn 000 Reg number Dn xxx W 111 000 An xxx L 111 001 An 010 Reg number An data An 011 Reg number An An 100 Reg number An 416 101 Reg number dig PC dg An Xn 110 Reg number An dg PC Xn bd An Xn 110 Reg number An bd PC Xn Long only all others byte only Instruction Format Bit Number Dynamic specified in a register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EFFECTIVE ADDRESS 0 0 0 0 REGISTER 1 0 1 MODE REGISTER Instruction Fields Bit Number Dynamic Register field Specifies the data r
269. ondition Tests for detailed information on condition codes CC Carry clear CS Carry set EQ Equal F False GE Greater or equal GT Greater than HI High LE Less or equal Not applicable to the Bcc instruction 4 3 9 System Control Instructions Privileged instructions trapping instructions and instructions that use or modify the condition code register provide system control operations All of these instructions cause the processor to flush the instruction pipeline Table 4 9 summarizes the in structions The preceding list of condition tests also applies to the TRAPcc instruction Refer to 4 3 10 Condition Tests for detailed information on condition codes LS Low or same LT Less than MI Minus NE Not equal PL Plus T True VC Overflow clear VS Overflow set Table 4 9 System Control Operations Instruction Syntax Size Operation Privileged ANDI data SR 16 Data SR SR EORI data SR 16 Data 6 SR SR MOVE ea SR 16 Source gt SR SR ea 16 SR 5 Destination MOVEA USP An 32 USP An An gt USP An USP 32 MOVEC Rc Rn 32 Rc Rn Rn Re 32 Rn gt Rc MOVES Rn ea 8 16 32 Rn Destination using DFC ea Rn Source using SFC Rn ORI data SR 16 Data SR SR CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4 11 Table 4 9 System Control Operations Continued Instruction Synt
270. operand is in memory The address of the operand is the sum of the address in the program counter and the sign extended 16 bit displacement integer in the extension word The value in the program counter is the address of the extension word The reference is a program space reference and is only allowed for read access es GENERATION EA PC 016 ASSEMBLER SYNTAX d16 PC MODE 111 REGISTER 010 31 0 PROGRAM COUNTER _ ADDRESS OF EXTENSION WORD 400020 15 0 DISPLACEMENT SIGN EXTENDED INTEGER 31 0 MEMORY ADDRESS NUMBER OF EXTENSION WORDS 1 OPERAND 3 4 3 2 Program Counter Indirect with Index 8 Bit Displacement This mode is similar to the address register indirect with index 8 bit displacement mode described in 3 4 2 5 Address Register Indirect With Index 8 Bit Displace ment but the program counter is used as the base register GENERATION EA PC Xn dg ASSEMBLER SYNTAX dg PC Xn SIZE SCALE MODE 111 REGISTER 011 31 0 PROGRAM COUNTER ADDRESS OF EXTENSION WORD 81 7 0 DISPLACEMENT SIGN EXTENDED INTEGER 81 0 INDEX REGISTER SIGN EXTENDED VALUE SCALE SCALE VALUE Y 81 Y 0 MEMORY ADDRESS NUMBER OF EXTENSION WORDS 1 OPERAND The operand is in memory The address of the operand is the sum of the address in the program counter the sign extended displacement integer in the lower eight bits of the extension word
271. or the nines complement if the extend bit is one Condition Codes X N 2 V U U n X Set the same as the carry bit N Undefined Z Cleared if the result is non zero Unchanged otherwise V Undefined C Set if a decimal borrow occurs Cleared otherwise NOTE Normally the Z condition code bit is set via programming before the start of the operation This allows successful tests for zero results upon completion of multiple precision operations Instruction Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EFFECTIVE ADDRESS 0 1 0 0 1 0 0 0 0 0 MODE REGISTER CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4 113 N BC D Negate Decimal with Extend N BC D Instruction Fields Effective Address field Specifies the destination operand Only data alterable addressing modes are allowed as shown Addressing Mode Mode Register Addressing Mode Mode Register Dn 000 Reg number Dn xxx W 111 000 An xxx L 111 001 An 010 Reg number An data An 011 Reg number An An 100 Reg number An 96 An 101 Reg number An 96 PC dg An Xn 110 Reg number An dg PC Xn bd An Xn 110 Reg number An bd PC Xn MOTOROLA INSTRUCTION SET CPU32 4 114 REFERENCE MANUAL N EG Negate N EG Operation 0 Destination Destination Assembler Syntax NEG ea Attributes
272. ormat Offset Word in stack frame 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FORMAT 0 0 VECTOR OFFSET Format Field Four bits imply frame size only values 000 0010 and 1000 1011 are used RTD 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 0 0 1 1 1 0 0 1 1 1 0 1 0 0 DISPLACEMENT 16 BITS CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4 179 RTS 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 0 0 1 1 1 0 0 1 1 1 0 1 0 1 TRAPV 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 0 0 1 1 1 0 0 1 1 1 0 1 1 0 RTR 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 0 0 1 1 1 0 0 1 1 1 0 1 1 1 MOVEC 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 0 0 1 1 1 0 0 1 1 1 1 0 1 dr AID REGISTER CONTROL REGISTER dr Field 0 Control Register to General Register 1 General Register to Control Register Control Register Field 000 SFC 801 VBR 001 DFC 802 CAAR 002 CACR 803 MSP 800 USP 804 ISP JSR 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EFFECTIVE ADDRESS 0 1 0 0 1 1 1 0 1 0 MODE REGISTER JMP 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EFFECTIVE ADDRESS 0 1 0 0 1 1 1 0 1 1 MODE REGISTER ADDQ 15 14 13 12 11 10 9 8 7 6 5 4 3 2
273. p tion causes the processor to resume instruction execution A trace exception occurs if instruction tracing is enabled TO 1 T120 when the STOP instruction begins execu tion If an interrupt request is asserted with a priority higher than the priority level set by the new status register value an interrupt exception occurs otherwise the inter rupt request is ignored External reset always initiates reset exception processing Condition Codes Set according to the immediate operand Instruction Format 15 14 18 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 0 0 1 1 1 0 0 1 1 1 0 0 1 0 IMMEDIATE DATA Instruction Fields Immediate field Specifies the data to be loaded into the status register CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4 143 S U B Subtract 5 U B Operation Destination Source Destination Assembler SUB ea Dn Syntax SUB Dn ea Attributes Size Byte Word Long Description Subtracts the source operand from the destination operand and stores the result in the destination The mode of the instruction indicates which oper and is the source which is the destination and which is the operand size Condition Codes X N Z V Set to the value of the carry bit Set if the result is negative Cleared otherwise Set if the result is zero Cleared otherwise Set if an overflow is generated Cleared o
274. pairing There are no explicit instructions for the management of this data type however the MOVEM instruction can be used to move a quad word into or out of the registers MOTOROLA ARCHITECTURE SUMMARY CPU32 2 4 REFERENCE MANUAL BCD data represents decimal numbers in binary form CPU32 BCD instructions use a format in which a byte contains two digits the four LSB contain the low digit and the four MSB contain the high digit The ABCD SBCD and NBCD instructions operate on two BCD digits packed into a single byte 2 3 1 2 Address Registers Each address register and stack pointer holds a 32 bit address Address registers can not be used for byte sized operands When an address register is used as a source operand either the low order word or the entire long word operand is used depending upon the operation size When an address register is used as a destination operand the entire register is affected regardless of operation size If the source operand is a word it is first sign extended to 32 bits and then used in the operation Address reg isters can be used to support address computation The instruction set includes in structions that add to subtract from compare and move the contents of address registers Figure 2 5 shows the organization of addresses in address registers 31 16 15 0 SIGN EXTENDED 16 BIT ADDRESS OPERAND 31 0 FULL 32 BIT ADDRESS OPERAND Figure 2 5 Address Organization in Add
275. perates in full duplex mode data is transmitted and received simultaneously by both master and slave devices In general data transitions occur on the falling edge of DSCLK and are stable by the following rising edge of DSCLK Data is transmitted MSB first and is latched on the rising edge of DSCLK The serial data word is 17 bits wide 16 data bits and a status control bit 16 15 0 SIC DATA FIELD T STATUS CONTROL BIT Bit 16 indicates status of CPU generated messages as shown in Table 7 3 CPU32 DEVELOPMENT SUPPORT MOTOROLA REFERENCE MANUAL 7 7 Table 7 3 CPU Generated Message Encoding Bit 16 Data Message Type 0 XXXX Valid Data Transfer FFFF Command Complete Status OK 0 1 0000 Not Ready with Response Come Again 1 0001 BERR Terminated Bus Cycle Data Invalid 1 FFFF Illegal Command Command and data transfers initiated by the development system should clear bit 16 The current implementation ignores this bit however Motorola reserves the right to use this bit for future enhancements 7 2 7 1 CPU Serial Logic CPU serial logic shown in the left hand portion of Figure 7 5 consists of transmit and receive shift registers and of control logic that includes synchronization serial clock generation circuitry and a received bit counter CPU INSTRUCTION REGISTER BUS RCV DATA LATCH SERIAL IN PARALLEL OUT DEVELOPMENT SYSTEM DATA COMMAND LA
276. placement size Both forms use an index operand For brief format addressing the address of the operand is the sum of the address in the address register the sign extended displacement integer in the low order eight bits of the extension word and the index operand The reference is classed as a data reference except for the JMP and JSR instructions The index operand is specified Ri sz scl CPU32 DATA ORGANIZATION AND ADDRESSING CAPABILITIES MOTOROLA REFERENCE MANUAL 3 5 GENERATION EA An Xn SCALE dg ASSEMBLER SYNTAX dg An SIZE SCALE MODE 110 REGISTER n 31 0 ADDRESS REGISTER gt MEMORY ADDRESS 31 7 0 DISPLACEMENT SIGN EXTENDED INTEGER 31 0 INDEX REGISTER SIGN EXTENDED VALUE um Y SCALE SCALEVALUE Q O S Y 31 MEMORY ADDRESS NUMBER OF EXTENSION WORDS 1 OPERAND Ri specifies a general data or address register used as an index register The index operand is derived from the index register The index register is a data register if bit 15 the first extension word and an address register if bit 15 1 The index register number is given by extension word bits 14 12 Index size is referred to as sz It may be either W or L Index size is given by bit 11 of the extension word If bit 11 2 O the index value is the sign extended low order word integer of the index register W If bit 11 2 1 t
277. ply the first operand Subsequent operands are written with the FILL command The initial address is incremented by the operand size 1 2 or 4 and is saved in a temporary register Subsequent FILL commands use this address increment it by the current op erand size and store the updated address back in the temporary register NOTE The FILL command does not check for a valid address in the tempo rary register FILL is a valid command only when preceded by an other FILL or by a WRITE command Otherwise the results are undefined The NOP command can be used for inter command pad ding without corrupting the address pointer The size field is examined each time a FILL command is given allowing the operand size to be altered dynamically Command Format 15 14 13 12 11 1 0 0 0 1 1 A i e e OP SIZE 0 0 0 e e e Command Sequence FILL BW DATA MEMORY Y XXX 777 NOT READY NOT READY __NEXTCMD XXX NEXT CMD EOM ILLEGAL READY CMD COMPLETE XXX BERR AERR NEXT CMD READY FILL LONG MS DATA LS DATA SCE Y XXX 77 NOT READY NOT READY LOCATION NOT READY NEXT CMD CMD COMPLETE XXX NEXT CMD BERR AERR NOT READY A single operand is data to be written to the memory location Byte data is trans mitted as a 16 bit word justified in the least sign
278. priate address space The RTE instruction causes a return to a program that was executing when an excep tion occurred When RTE is executed the exception stack frame saved on the super visor stack can be restored in either of two ways MOTOROLA PROCESSING STATES CPU32 5 2 REFERENCE MANUAL If the frame was generated by an interrupt breakpoint trap or instruction exception the status register and program counter are restored to the values saved on the su pervisor stack and execution resumes at the restored program counter address with access level determined by the S bit of the restored status register If the frame was generated by a bus error or an address error exception the entire pro cessor state is restored from the stack 5 3 Types of Address Space During each bus cycle the processor generates function code signals that permit se lection of eight distinct 4 Gigabyte address spaces Not all devices that incorporate the CPU32 support a full complement of memory Refer to the appropriate user s manual for details Selection varies according to the access required Automatic selection of supervisor and user space and of program and data space is provided In addition certain special processor cycles such as the interrupt acknowledge cycle or the LP STOP broadcast cycle are recognized and appropriate codes are generated Table 5 1 shows function code values and the corresponding address space Table 5 1 Address Spaces
279. r BCLR and bit test and change BCHG All bit manipulation operations can be performed on either registers or mem INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4 9 ory The bit number is specified as immediate data or in a data register Register op erands are 32 bits long and memory operands are 8 bits long Table 4 6 is a summary of bit manipulation instructions Table 4 6 Bit Manipulation Operations Instruction Syntax Operand Size Operation BCHG Dn ea 8 32 bit number of destination gt Z 2 lt data ea 8 32 bit of destination BCLR Dn ea 8 32 bit number of destination Z data ea 8 32 0 bit of destination BSET Dn ea 8 32 bit number of destination Z data ea 8 32 1 5 bit of destination BTST Dn ea 8 32 bit number of destination gt Z data ea 8 32 4 3 7 Binary Coded Decimal BCD Instructions Five instructions support operations on BCD numbers The arithmetic operations on packed BCD numbers are add decimal with extend ABCD subtract decimal with ex tend SBCD and negate decimal with extend NBCD Table 4 7 is a summary of the BCD operations Table 4 7 Binary Coded Decimal Operations Instruction Syntax Operand Size Operation Dn Dn 8 en ABCD An An 8 Source Destination o4 X Destination NBCD ea 0 Destination X Destination Dn Dn 8 S n SBCD An
280. r 1 ROR r 0 i 0 0 Note The following notation applies to this table only affected U Undefined See special definition General case X C 4 3 2 Data Movement Instructions The MOVE instruction is the basic means of transferring and storing address and data MOVE instructions transfer byte word and long word operands from memory to memory memory to register register to memory and register to register Address movement instructions MOVE or MOVEA transfer word and long word operands and ensure that only valid address manipulations are executed Sm Source operand MSB Dm Destination operand MSB Rm Result operand MSB R Register tested r Shift count LB Lower bound UB Upper bound In addition to the general MOVE instructions there are several special data movement instructions move multiple registers MOVEM move peripheral data MOVEP move quick MOVEQ exchange registers EXG load effective address LEA push effective address PEA link stack LINK and unlink stack UNLK Table 4 2 is a summary of the data movement operations Table 4 2 Data Movement Operations Instruction Syntax Operand Size Operation EXG Rn Rn 32 Rn 5 Rn LEA ea An 32 gt An LINK An 16 32 SP 4 SP An gt SP SP d 5 SP MOVE ea ea 8 16 32 Source Destination MOVEA ea An 16 32 32 Source Destination MOTOROLA INSTRUCTION SET CPU
281. r Stack Pointer USP 801 Vector Base Register VBR Any other code causes an illegal instruction exception MOTOROLA INSTRUCTION SET CPU32 4 98 REFERENCE MANUAL MOVEM Move Multiple Registers MOVEM Operation Registers Destination Source Registers Assembler MOVEM register list ea Syntax MOVEM register list Attributes Size Word Long Description Moves the contents of selected registers to or from consecutive memory locations starting at the location specified by the effective address A register is selected if the bit in the mask field corresponding to that register is set The instruc tion size determines whether 16 or 32 bits of each register are transferred In the case of a word transfer to either address or data registers each word is sign extended to 32 bits and the resulting long word is loaded into the associated register CPUS2 Selecting the addressing mode also selects the mode of operation of the MOVEM instruction and only the control modes the predecrement mode and the postin crement mode are valid If the effective address is specified by one of the control modes the registers are transferred starting at the specified address and the address is incremented by the operand length 2 or 4 following each transfer The order of the registers is from data register 0 to data register 7 then from address register O to address register 7 If the effective address is specified by the predecrement m
282. r are returned as a long word value The data is returned most significant word first 7 2 8 5 Write A D Register WAREG WDREG The operand long word data is written to the specified address or data register All 32 bits of the register are altered by the write Command Format A A 4A A A a A o o a qp 0 0 1 0 0 0 0 0 1 e e 5 REGISTER Command Sequence WDREG WAREG MS DATA LS DATA NEXT CMD 22 NOT READY NOT READY COMPLETE XXX NEXT CMD ILLEGAL READY Operand Data Long word data is written into the specified address or data register The data is supplied most significant word first Result Data Command complete status SOFFFF is returned when register write is complete CPU32 DEVELOPMENT SUPPORT MOTOROLA REFERENCE MANUAL 7 15 7 2 8 6 Read System Register RSREG The specified system control register is read All registers that can be read in supervi sor mode can be read in BDM Several internal temporary registers are also accessi ble Command Format 0 0 1 0 0 1 0 0 1 0 0 0 REGISTER Command Sequence RSREG XXX NEXT CMD 22 MS RESULT LS RESULT XXX NEXT CMD ILLEGAL READY Operand Data None Result Data Always returns 32 bits of data regardless of the size of the register being read I
283. r long bus cycles add two clocks to the tail and to the number of cycles Maximum time certain data or mode combinations may execute faster su The execution time is identical for signed or unsigned operands These instructions have an additional save operation that other instructions do not have To calculate total instruction time calculate save ea and operation execution times then combine in the order shown using equations in 8 1 6 Instruction Execution Time Calculation A save operation is not run for long word divide and multiply instructions when FEA Dn MOTOROLA INSTRUCTION EXECUTION TIMING CPU32 8 16 REFERENCE MANUAL 8 3 6 Immediate Arithmetic Logic Instructions The immediate arithmetic logic instruction table indicates the number of clock periods needed for the processor to fetch the source immediate data value and to perform the specified arithmetical logical instruction using the specified addressing mode Foot notes indicate when to account for the appropriate fetch effective or fetch immediate effective address times The total number of clock cycles is outside the parentheses The numbers inside parentheses r p w are included in the total clock cycle number All timing data assumes two clock reads and writes Instruction Head Tail Cycles MOVEQ Dn 0 0 2 0 1 0 ADDQ Rn 0 0 2 0 1 0 ADDQ FEA 0 3 5 0 1 x SUBQ Rn 0 0 2 0 1
284. ration This instruction supports breakpoints for debug monitors and real time hardware em ulators The exact operation performed by the instruction is implementation depen dent Typically this instruction replaces an instruction in a program and the replaced instruction is returned by the breakpoint acknowledge cycle Condition Codes Not affected Instruction Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 0 0 1 0 0 0 0 1 0 0 1 VECTOR Instruction Fields Vector field Contains immediate data in the range 0 7 This is the breakpoint number MOTOROLA INSTRUCTION SET CPU32 4 42 REFERENCE MANUAL B RA Branch Always B RA Operation PC d PC Assembler Syntax BRA label Attributes Size Byte Word Long Description Program execution continues at location PC displacement The PC contains the address of the instruction word of the BRA instruction plus two The displacement is a twos complement integer that represents the relative distance in bytes from the current PC to the destination PC If the 8 bit displacement field in the instruction word is zero a 16 bit displacement the word immediately following the instruction is used If the 8 bit displacement field in the instruction word is all ones FF the 32 bit displacement long word immediately following the instruction is used Condition Codes Not affected Instruction Format 15 14 18 12 11 10
285. rder byte of data register to long Register field Specifies the data register is to be sign extended CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4 79 L L EGAL Take Illegal Instruction Trap L L EGAL Operation SSP 2 SSP Vector Offset SSP SSP 4 gt SSP PC 5 SSP SSP 2 SSP SR SSP Illegal Instruction Vector Address PC Assembler Syntax ILLEGAL Attributes Unsized Description Forces an illegal instruction exception vector number 4 All other illegal instruction bit patterns are reserved for future extension of the instruction set and should not be used to force an exception Condition Codes Not affected Instruction Format MOTOROLA INSTRUCTION SET CPU32 4 80 REFERENCE MANUAL JMP Jump JMP Operation Destination Address PC Assembler Syntax JMP ea Attributes Unsized Description Program execution continues at the effective address specified by the instruction The addressing mode for the effective address must be a control addressing mode Condition Codes Not affected Instruction Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EFFECTIVE ADDRESS MODE REGISTER Instruction Fields Effective Address field Specifies the address of the next instruction Only control addressing modes are allowed as shown Addressing Mode Mode Register Addressing M
286. recte d qo qu qq pef 4 191 Exception Stack Plame e ot top ro ERE LU dE DUE 6 4 Reset Operation Flowchart eeu cette dede backen ended 6 6 Format 0 Four Word Stack Frame 6 22 Format 2 Six Word Stack Frame 2 6 22 Internal Transfer Count Register 6 23 Format C BERR Stack for Prefetches and Operands 6 24 Format C BERR Stack on MOVEM Operand 6 24 Format C Four and Six Word BERR Stack 6 24 Iri Circuit Emulator Configuration 7 2 Bus State Analyzer Configuration 7 2 BOM Block Diagram i oot Eel cade ER in bb ER d eru 7 3 BDM Command Execution Flowchart 2 2 7 6 Debug Serial I O Block Diagram 2 8 7 8 Serial Interface Timing 7 9 BKPT Timing for Single Bus 7 10 BKPT Timing ftor Forcing BDM s o e Rex rhe EH MEE RUE 7 10 BRPTI DSGEREbogiG Diagrami oe ES ERE aro 7 11 Command Sequence Diagram Example 2 7 13 Functional Model of Instruction Pipeline 7 26 Instruction Pipeline Timing Diagram eese 7 26 Block Diagram of Independent Resources 8 2 Simultaneous Instruction Execution
287. register for predecrement addressing mode MOTOROLA INSTRUCTION SET CPU32 4 16 REFERENCE MANUAL ADD Add ADD Operation Source Destination Destination Assembler ADD ea Dn Syntax ADD Dn ea Attributes Size Byte Word Long Description Adds the source operand to the destination operand using binary addition and stores the result in the destination location The mode of the instruction indicates which operand is the source and which is the destination as well as the operand size Condition Codes X N 2 V e X Set the same as the carry bit N Set if the result is negative Cleared otherwise Z Set if the result is zero Cleared otherwise V Set if an overflow is generated Cleared otherwise Set if a carry is generated Cleared otherwise Instruction Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EFFECTIVE ADDRESS 1 1 0 1 REGISTER OPMODE MODE REGISTER Instruction Fields Register field Specifies any of the eight data registers Opmode field Byte Word Long Operation 000 001 010 ea Dn 2 Dn 100 101 110 ea gt ea CPUS2 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4 17 ADD Effective Address Field Determines addressing mode If the location specified is a source operand all addressing modes are allowed as ADD shown Addressing Mode Mode Register Addressing Mode Mode Register Dn 000 Reg number Dn xxx W 11
288. rement mode to decrement the register before its contents are used as the pointer to the stack Use the postincrement mode to increment the register after its contents are used as the pointer to the stack Maintain the SP correctly when byte word and long word items are mixed in these stacks To implement stack growth from high to low memory use An to push data on the stack An to pull data from the stack For this type of stack after either a push or a pull operation register An points to the top item on the stack This scheme is illustrated as follows LOW MEMORY FREE An TOP OF STACK HIGH MEMORY BOTTOM OF STACK To implement stack growth from low to high memory use An to push data on the stack to pull data from the stack In this case after either a push or pull operation register An points to the next avail able space on the stack This scheme is illustrated as follows MOTOROLA DATA ORGANIZATION AND ADDRESSING CAPABILITIES CPU32 3 16 REFERENCE MANUAL LOW MEMORY BOTTOM OF STACK TOP OF STACK An FREE HIGH MEMORY 3 7 3 Queues Queues can be implemented using the address register indirect with postincrement or predecrement addressing modes Queues are pushed from one end and pulled from the other and use two registers A queue filled either from high to low memory or from low to high memory can be implemented with a pair two of AO to A6 of address reg
289. ress Registers 2 3 1 3 Control Registers The control registers contain control information for supervisor functions The registers vary in size With the exception of the user portion of the SR CCR they are accessed only by instructions at the supervisor privilege level The SR shown in Figure 2 3 is 16 bits wide Only 11 bits of the SR are defined and all undefined values are reserved by Motorola for future definition The undefined bits are read as zeros and should be written as zeros for future compatibility The lower byte of the SR is the CCR Operations to the CCR can be performed at the supervisor or user privilege level All operations to the SR and CCR are word size operations For all CCR operations the upper byte is read as all zeros and is ignored when written regardless of privilege level The alternate function code registers SFC and DFC are 32 bit registers with only bits 2 0 implemented These bits contain address space values FC2 to FCO for the read or write operand of the MOVES instruction The MOVEC instruction is used to transfer values to and from the alternate function code registers These are long word transfers the upper 29 bits are read as zeros and are ignored when written CPU32 ARCHITECTURE SUMMARY MOTOROLA REFERENCE MANUAL 2 5 2 3 2 Organization in Memory Memory is organized on a byte addressable basis An address corresponds to a high order byte For example the address N of a long word data
290. ress register for the predecrement addressing mode Size field Specifies the size of the operation 00 Byte operation 01 Word operation 10 Long operation R M field Specifies the operand addressing mode 0 The operation is data register to data register 1 The operation is memory to memory Register Dx Ax field Specifies the source register R M 0 specifies a data register If R M 1 specifies an address register for the predecrement addressing mode MOTOROLA INSTRUCTION SET CPU32 4 152 REFERENCE MANUAL SWA P Swap Register Halves SWA P Operation Register 31 16 lt gt Register 15 0 Assembler Syntax SWAP Dn Attributes Size Word Description Exchange the 16 bit words halves of a data register Condition Codes X N Z 0 0 X Not affected N Set if the most significant bit of the 32 bit result is set Cleared otherwise Z Set if the 32 bit result is zero Cleared otherwise V Always cleared Always cleared Instruction Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 0 0 1 0 0 0 0 1 0 0 0 REGISTER Instruction Fields Register field Specifies the data register to swap CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4 153 TB LS Table Lookup and Interpolate Signed TB LS TBLSN TBLSN Operation Rounded ENTRY n ENTRY n 1 7 ENTRY n
291. riable be calcu lated as a fractional number in the range 0 x X lt 255 On the contrary X should be considered an integer in the range 0 lt X lt 65535 realizing that the table is actually a compressed linear representation of a function in which only every 256th value is actually stored in memory See 4 6 Table Lookup and Interpolation Instructions for more information on the TBLS TBLSN instruction Condition Codes X N 2 n 0 X Not affected N Set if the most significant bit of the result is set Cleared otherwise Z Set if the result is zero Cleared otherwise V Set if the integer portion of an unrounded long result is not in the range 223 lt Result lt 223 1 Cleared otherwise Always cleared Instruction Format Table lookup and interpolate 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EFFECTIVE ADDRESS 1 1 1 1 1 0 0 0 0 0 MODE REGISTER 0 REGISTER Dx 1 R 0 1 SIZE 0 0 0 0 0 0 MOTOROLA INSTRUCTION SET CPU32 4 156 REFERENCE MANUAL TBLS TBLSN Table Lookup and Interpolate Signed Data Register Interpolate TBLS TBLSN 15 14 13 12 11 10 9 7 6 5 4 3 2 1 0 1 1 1 1 1 0 0 0 0 0 0 0 REGISTER Dym 0 REGISTER Dx 1 R 0 SIZE 0 0 0 REGISTER Dyn Instruction Fields Effective address field table lookup and interpolate mode only Specifies the source location
292. rogress at the time of a bus fault If a prefetch bus fault occurs while refetching the MOVEM opcode and extension word both the MV and IN bits will be set 0 MOVEM was not in progress when fault occurred 1 MOVEM in progress when fault occurred TR indicates that a trace exception was pending when a bus error exception was pro cessed The instruction that generated the trace will not be restarted upon return from the exception handler This includes MOVEM and released write bus errors indicated by the assertion of either MV or RR in the SSW 0 Trace not pending 1 Trace pending B1 indicates that a breakpoint exception was pending on channel 1 external break point source when a bus error exception was processed Pending breakpoint status is stacked regardless of the type of bus error exception 0 Breakpoint not pending 1 Breakpoint pending BO indicates that a breakpoint exception was pending on channel 0 internal break point source when the bus error exception was processed Pending breakpoint status is stacked regardless of the type of bus error exception 0 Breakpoint not pending 1 Breakpoint pending RR will be set if the faulted bus cycle was a released write If the write is completed rerun in the exception handler the RR bit should be cleared before executing RTE The bus cycle will be rerun if the RR bit is set upon return from the exception handler 0 Faulted cycle was read RMW or unreleas
293. ror Exception 6 7 Address Register Direct Addressing Mode 3 3 Indirect Addressing Mode 3 4 Indirect Displacement Mode 3 5 Indirect Index 8 Bit Displacement Mode 3 5 Indirect Index Base Displacement Mode 3 6 Indirect Postincrement Addressing Mode 3 4 Indirect Predecrement Addressing Mode 3 4 Address Registers 2 5 Address Space Types 5 3 Addressing Capabilities 3 11 Compatibility M68000 3 14 A 4 Indexed 3 5 3 6 3 7 Indirect 3 4 Mode Enhancements 1 4 Mode Summary 3 14 Addressing Modes Memory 3 4 Programming View 3 11 Register Direct 3 3 Special 3 7 Architectural Comparisons M68000 A 1 Arithmetic Logic Instructions 4 7 Assignments Exception Vector 6 2 Asynchronous Bus Operation See appropriate user s manual B Background Debug Mode 7 3 Commands Execution 7 5 Format 7 11 Sequence Diagrams 7 12 Sequence Example 7 13 Set 7 11 Summary 7 14 Enabling 7 4 Entering 7 5 Returning from 7 7 CPU32 REFERENCE MANUAL INDEX Sources 7 4 Registers 7 6 Serial Interface 7 7 BGND Instruction 7 4 Binary Coded Decimal Operations 4 10 Bit Manipulation Operations 4 10 Block Diagram 1 6 Branch Instructions 4 10 Condition Tests 4 12 Breakpoint Exception Processing 6 8 Breakpoint Instruction 4 12 7 4 Breakpoint Signal External 7 4 Breakpoints Hardware 6 9 7 4 On Data Accesses 7 4 On Instructions 7 4 Peripheral 7 5 Software 6 8 Bus Controller Resources 8 2 Bus Error 6 6 6 22 Bus Error Fault Stack Frame 6 22
294. rrected recovery can proceed as described previously If the fault cannot be corrected move the supervisor stack to another area of memory copy all valid stack frames to the new stack create a faulted exception frame on top of the stack and re sume execution at the exception handler address 6 4 CPU32 Stack Frames The CPU32 generates three different stack frames the normal four and six word frames and the twelve word BERR stack frame CPU32 EXCEPTION PROCESSING MOTOROLA REFERENCE MANUAL 6 21 6 4 1 Normal Four Word Stack Frame This stack frame is created by interrupt format error TRAP Zn illegal instruction A line and F line emulator trap and privilege violation exceptions Depending on the ex ception type the program counter value is either the address of the next instruction to be executed or the address of the instruction that caused the exception see Figure 6 3 15 0 SP gt STATUS REGISTER 02 PROGRAM COUNTER HIGH PROGRAM COUNTER LOW 06 0 0 0 0 VECTOR OFFSET Figure 6 3 Format 0 Four Word Stack Frame 6 4 2 Normal Six Word Stack Frame This stack frame see Figure 6 4 is created by instruction related traps which include CHK CHK2 TRAPcc TRAPV and divide by zero and by trace exceptions The fault ed instruction program counter value is the address of the instruction that caused the exception The next program counter value the address to which RTE returns is the
295. rther debugging is impossible until the problem is corrected In BDM the fault can be temporarily bypassed so that its origin can be iso lated and eliminated 7 2 2 4 Peripheral Breakpoints CPU32 peripheral breakpoints are implemented in the same way as external break points peripherals request breakpoints by asserting the BKPT signal Consult the appropriate peripheral user s manual for additional details on the generation of periph eral breakpoints 7 2 3 Entering BDM When the processor detects a breakpoint or a double bus fault or decodes a BGND instruction it suspends instruction execution and asserts the FREEZE output This is the first indication that the processor has entered BDM Once FREEZE has been as serted the CPU enables the serial communication hardware and awaits a command The CPU writes a unique value indicating the source of BDM transition into temporary register A ATEMP as part of the process of entering BDM A user can poll ATEMP and determine the source see Table 7 2 by issuing a read system register command RSREG ATEMP is used in most debugger commands for temporary storage it is imperative that the RSREG command be the first command issued after transition into BDM Table 7 2 Polling the BDM Entry Source Source ATEMP 31 16 ATEMP 15 0 Double Bus Fault SSW FFFF BGND Instruction 0000 0001 Hardware Breakpoint 0000 0000 Special status word SSW is describe
296. rting address of the block and to retrieve the first result Subsequent operands are retrieved with the DUMP command Fill Memory Block Resume Execution Used in conjunction with the WRITE command to fill large blocks of memory An initial WRITE is executed to set up the starting address of the block and to supply the first operand Subsequent operands are written with the FILL command The pipeline is flushed and refilled before resuming instruction execution at the return PC Call User Code Current PC is stacked at the location of the current SP Instruction execution begins at user patch code Reset Peripherals Asserts RESET for 512 clock cycles The CPU is not reset by this command Synonymous with the CPU RESET instruction No Operation MOTOROLA 7 14 DEVELOPMENT SUPPORT NOP performs no operation and may be used as a null command CPU32 REFERENCE MANUAL 7 2 8 4 Read A D Register RAREG RDREG Read the selected address or data register and return the results via the serial inter face Command Format A A DA A A a A o o oa qe 0 0 1 0 0 0 e e e e 5 REGISTER Command Sequence RDREG RAREG 22 XXX NEXT CMD MS RESULT LS RESULT XXX ILLEGAL NEXT CMD NOT READY Operand Data None Result Data The contents of the selected registe
297. ruction vector or in the case of an unimplemented instruction to the corresponding emulation vector The illegal instruction vector number current program counter and a copy of the status register are saved on the supervisor stack with the saved value of the program counter being the address of the illegal or unim plemented instruction 6 2 9 Privilege Violations To provide system security certain instructions can be executed only at the supervisor access level An attempt to execute one of these instructions at the user level will cause an exception The privileged exceptions are as follows AND Immediate to SR EOR Immediate to SR e LPSTOP MOVE from SR MOVE to SR MOVE USP MOVES OR Immediate to SR RESET STOP Exception processing for privilege violations is nearly identical to that for illegal instruc tions The instruction is fetched and decoded If the processor determines that a priv ilege violation has occurred exception processing begins before instruction execution Exception processing follows the regular sequence The vector number 8 is gener ated to reference the privilege violation vector Privilege violation vector offset current program counter and status register are saved on the supervisor stack The saved program counter value is the address of the first word of the instruction causing the privilege violation MOTOROLA EXCEPTION PROCESSING CPU32
298. ructions 8 8 8 2 3 Timing Example 3 Negative 8 9 8 3 Instruction Timing Tables do Eo eeu 8 10 8 3 1 Fetch Effective Address oes fiios ies 8 12 8 3 2 Calculate Effective Address esee 8 13 CPU32 MOTOROLA REFERENCE MANUAL ix Paragraph 8 3 3 8 3 4 8 3 5 8 3 6 8 3 7 8 3 8 8 3 9 8 3 10 8 3 11 8 3 12 8 3 13 8 3 14 MOTOROLA TABLE OF CONTENTS Continued Title MONE Instruction ar oi eic oi EE ER a Special Purpose MOVE Instruction Arithmetic Logic Instructions o ot doce ee et adeo Immediate Arithmetic Logic Instructions Binary Coded Decimal and Extended Instructions Single Operand Instr CcllollS cuui occi ae o ertet Shift Rotate Instructions ss qusc uera Cc RE ER rro a qe Ern rct Ont Bit Manipulation Iristr ctloris rar Conditional Branch Instructions 2 tr auct Sue oe AEN Exception Related Instructions and Operations Save and Restore Operations APPENDIX AM68000 FAMILY SUMMARY INDEX REFERENCE CPU32 MANUAL 7 1
299. ructions 8 20 Calculate Effective Address CEA 8 13 Conditional Branch Instructions 8 20 Control Instructions 8 21 Exception Related Instructions 8 21 Fetch Effective Address FEA 8 10 Immediate Arithmetic Logic Instructions 8 17 MOVE Instruction 8 14 Save and Restore Operations 8 22 Shift Rotate instructions 8 19 Single Operand instructions 8 18 Special Purpose MOVE Instruction 8 14 Trace on Instruction Execution 6 11 7 1 U Unimplemented instruction Emulation 6 9 7 1 Unimplemented Instructions 4 2 6 9 User Privilege Level 5 2 User Stacks 3 16 N Vector Base Register 1 3 2 3 6 1 Vectors Exception 6 1 Virtual Memory 1 2 W Write Pending Buffer 8 3 MOTOROLA 4 INDEX CPU32 REFERENCE MANUAL
300. s CPU space transactions Bits A 19 16 the CPU space type field show which transaction is being performed Currently only five of the 16 possible encodings are defined 0000 0001 0010 0011 and 1111 Of these only 0000 0011 and 1111 are supported by the CPUS2 Address bits A 31 20 are not present on all M68000 processors and thus cannot be essential to CPU space transaction decoding The function of other address bus bit fields depends on the transaction being performed A description of each defined CPU space types follows 5 3 1 1 Type 0000 Breakpoint This CPU space type is used for breakpoint acknowledge 31 5 4 2 1 0 o 0 00000000000000000000 0 0 0 BKPT T 0 BKPT field A 4 2 indicates the breakpoint number Software breakpoints set this val ue to the number of the executing breakpoint instruction Hardware breakpoints al ways set BKPT to 7 111 T bit A1 designates the type of breakpoint T 0 indicates a software breakpoint T 1 indicates a hardware breakpoint 5 3 1 2 Type 0001 MMU Access This type of access is not supported by the CPU32 processor This space is reserved for future use 5 3 1 3 Type 0010 Coprocessor Access This type of access is not supported by the CPU32 processor This space is reserved for future use 5 3 1 4 Type 0011 Internal Register Access Type 0011 space is used to access certain critical system configuration or control reg ist
301. s a flexible base for program de velopment 4 1 M68000 Family Compatibility It is the philosophy of the M68000 Family that all user mode programs can execute unchanged on a more advanced processor and that supervisor mode programs and exception handlers should require only minimal alteration The CPU32 can be thought of as an intermediate member of the M68000 Family Ob ject code from an MC68000 or MC68010 may be executed on the CPU32 and many of the instruction and addressing mode extensions of the MC68020 are also support ed 4 1 1 New Instructions Two instructions have been added to the M68000 instruction set for use in controller applications These are the low power stop LPSTOP and the table lookup and inter polation TBL commands 4 1 1 1 Low Power Stop LPSTOP In applications where power consumption is a consideration the CPU32 can force the device into a low power standby mode when immediate processing is not required The low power mode is entered by executing the LPSTOP instruction The processor remains in this mode until a user specified or higher level interrupt or a reset occurs CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4 1 4 1 1 2 Table Lookup and Interpolation TBL To maximize throughput for real time applications reference data is often precalculat ed and stored in memory for quick access The storage of sufficient data points can require an inordinate amount of memory The TBL instruction uses l
302. s a word and all implemented bits of the status register are affected Condition Codes Set according to the source operand Instruction Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EFFECTIVE ADDRESS MODE REGISTER Instruction Fields Effective Address field Specifies the destination location Only data addressing modes are allowed as shown Addressing Mode Mode Register Addressing Mode Mode Register Dn 000 Reg number Dn xxx W 111 000 An xxx L 111 001 An 010 Reg number An data 111 100 An 011 Reg number An An 100 Reg number An 416 An 101 Reg number An dig PC 111 010 dg An Xn 110 Reg number An dg PC Xn 111 011 bd An 110 Reg number An bd PC Xn 111 011 MOTOROLA INSTRUCTION SET CPU32 4 96 REFERENCE MANUAL MOVE Move User Stack Pointer MOVE US P Privileged Instruction US P Operation If supervisor state then USP An or An gt USP else TRAP Assembler MOVE USP An Syntax MOVE An USP Attributes Size Long Description Moves the contents of the user stack pointer to or from the specified address register Condition Codes Not affected Instruction Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 0 0 1 1 1 0 0 1 1 0 dr REGISTER Instruction Fields dr field Specifies the direction of transfer
303. s an address register If the S bit indicates the user state the USP is the active SP and the SSP cannot be referenced Each system CPU32 DATA ORGANIZATION AND ADDRESSING CAPABILITIES MOTOROLA REFERENCE MANUAL 3 15 stack fills from high memory to low memory The address mode SP creates a new item on the active system stack and the address mode SP deletes an item from the active system stack The program counter is saved on the active system stack on subroutine calls and is restored from the active system stack on returns On the other hand both the program counter and the status register are saved on the supervisor stack during the process ing of traps and interrupts Thus the correct execution of the supervisor state code is not dependent on the behavior of user code and user programs may use the USP ar bitrarily To keep data on the system stack aligned properly data entry on the stack is restricted so that data is always put in the stack on a word boundary Thus byte data is pushed on or pulled from the system stack in the high order half of the word the low order half is unchanged 3 7 2 User Stacks The user can implement stacks with the address register indirect with postincrement and predecrement addressing modes With address register An n 0 to 6 the user can implement a stack that is filled either from high to low memory or from low to high memory Important considerations are as follows Use the predec
304. s are taken at the next instruction boundary The stacked program counter is that of the next unexecuted instruction If a subsequent instruction attempts an operand access while a released write fault is pending the instruction is aborted and the write fault is acknowledged This action prevents stale data from being used by the instruction The SSW for a released write fault contains the following bit pattern 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0 0 0 0 TR B1 BO 1 0 0 0 LG SIZ FUNC TR B1 and BO are set if the corresponding exception is pending when the BERR ex ception is taken Status regarding the faulted bus cycle is reflected in the SSW LG SIZ and FUNC fields MOTOROLA EXCEPTION PROCESSING CPU32 6 16 REFERENCE MANUAL The remainder of the stack contains the program counter of the next unexecuted in struction the current status register the address of the faulted memory location and the contents of the data buffer which was to be written to memory This data is written on the stack in the format depicted in Figure 6 3 6 3 1 2 Type Prefetch Operand RMW and MOVEP Faults The majority of BERR exceptions are included in this category all instruction prefetches all operand reads all RMW cycles and all operand accesses resulting from execution of MOVEP except the last write of a MOVEP Rn ea or the last write of MOVEM which are type faults The TAS MOVEP and MOVEM i
305. s direction L or R Attributes Size Byte Word Long Description Shifts the bits of the operand in the direction specified L or R The carry bit receives the last bit shifted out of the operand Shift count can be specified in one of two ways 1 Immediate The shift count 1 8 is specified by the instruction 2 Register The shift count is the value in the data register specified by the instruction modulo 64 The size of the operation for register destinations may be specified as byte word or long The contents of memory ea can be shifted one bit only and the operand size is restricted to a word The LSL instruction shifts the operand to the left the number of positions specified as the shift count Bits shifted out of the high order bit go to both the carry and the extend bits zeros are shifted into the low order bits LSL XC 1 lt x lt 9 The LSR instruction shifts the operand to the right the number of positions specified as the shift count Bits shifted out of the low order bit go to both the carry and the ex tend bits zeros are shifted into the high order bits MOTOROLA INSTRUCTION SET CPU32 4 86 REFERENCE MANUAL LSL LSR Logical Shift LS L LSR Condition Codes X N 2 V gt 7 0 gt X Set according to the last bit shifted out of the operand Unaffected for a shift count of zero Set if the result is negative Cleared otherwise Set if the re
306. s in Dr Dq Register Dr field After the division this register contains the 32 bit remainder If Dr and Dq are the same register only the quotient is returned If Size is 1 the Dr field also specifies the data register that contains the high order 32 bits of the dividend NOTE Overflow occurs if the quotient is larger than a 32 bit signed integer MOTOROLA INSTRUCTION SET CPU32 4 68 REFERENCE MANUAL DIVU Unsigned Divide DIVU DIVUL DIVUL Operation Destination Source Destination Assembler Syntax DIVS W Dn32 16 16r 16q DIVS L 0432 32 32q DIVS L Dr Dq64 32 gt 32r 32q DIVSL L Dr Dq32 32 32r 32q Attributes Size Word Long Description Divides the unsigned destination operand by the unsigned source operand and stores the unsigned result in the destination The instruction uses one of four forms The word form of the instruction divides a long word by a word The result is a quotient in the lower word least significant 16 bits and a remainder in the upper word most significant 16 bits of the destination The first long form divides a long word by a long word The result is a long quo tient the remainder is discarded The second long form divides a quad word in any two data registers by a long word The result is a long word quotient and a long word remainder The third long form divides a long word by a long word The result is a long word quotient and a long wor
307. s of options in the indexing mode or a selection of two alternate address ing modes For example the addressing mode called register indirect Rn assembles as address register indirect if the register is an address register If Rn is a data register the assembler uses address register indirect with index mode with a data register as the indirect register and suppresses the address register by setting the base suppress bit in the EA specification Assigning an address register as Rn provides higher performance than using a data register as Rn Another case is bd An which selects an addressing mode based on the size of the displacement If the displacement is 16 bits or less the address register indirect with displacement mode 016 An is used When a 32 bit displacement is re quired the address register indirect with index bd An Xn is used with the index reg ister suppressed It is useful to examine the derived addressing modes available to a programmer with out regard to the CPU32 EA mode actually encoded because the programmer need not be concerned about these decisions The assembler can choose the more efficient addressing mode to encode 3 6 M68000 Family Addressing Capability Programs can be easily transported from one member of the M68000 Family to anoth er The user object code of earlier members of the family is upwardly compatible with later members and can be executed without change The address extension word s ar
308. s on a read or write 6 3 1 3 Type Faults During MOVEM Operand Transfer Bus faults that occur as a result of MOVEM operand transfer are classified as type III faults MOVEM Instruction prefetch faults are type II faults Type III faults cause an immediate exception that aborts the current instruction None of the registers altered during execution of the faulted instruction are restored prior to execution of the fault handler This includes any register predecremented as a result of the effective address calculation or any register overwritten during instruction exe cution Since postincremented registers are not updated until the end of an instruction the register retains its preinstruction value unless overwritten by operand movement The SSW for faults in this category contains the following bit pattern CPU32 EXCEPTION PROCESSING MOTOROLA REFERENCE MANUAL 6 17 0 1 0 TR B1 BO RR 0 IN RW LG SIZ FUNC MV is set indicating that MOVEM should be continued from the point where the fault occurred upon return from the exception handler TR B1 and BO are set if a corre sponding exception is pending when the BERR exception is taken IN is set if a bus fault occurs while refetching an opcode or an extension word during instruction restart RW LG SIZ and FUNC all reflect the type of bus cycle that caused the fault All write faults have the RR bit set to indicate that the write should be r
309. s the starting location of the patch routine which is the initial PC upon exiting BDM Result Data None As an example consider the following code segment It is supposed to output a char acter to an asynchronous communications interface adaptor note that the routine fails to check the transmit data register empty TDRE flag CHKSTAT MOVE B ACIAS DO Move ACIA status to DO BEQ B CHKSTAT Loop till condition true MOVE B DATA ACIAD Output data e e e MISSING ANDI B 2 D0 Check for TDRE RTS Return to in line code BDM and the CALL command can be used to patch the code as follows CPU32 REFERENCE MANUAL 9 OB mcr Breakpoint user program at CHKSTAT Enter BDM Execute CALL command to MISSING Exit BDM Execute MISSING code Return to user program DEVELOPMENT SUPPORT MOTOROLA 7 23 7 2 8 14 Reset Peripherals RST RST asserts RESET for 512 clock cycles The CPU is not reset by this command This command is synonymous with the CPU RESET instruction Command Format A a an D A A a D 2 e e e e e e e e e e e 0 0 0 0 0 1 Command Sequence RESET 22 ASSERT XXX RESET NOT READY NEXT CMD CMD COMPLETE NEXT CMD NOT READY XXX ILLEGAL Operand Data None Result Data The command complete response 0FFFF is loaded into th
310. se Cleared if bit 2 of immediate operand is zero Unchanged otherwise Cleared if bit 1 of immediate operand is zero Unchanged otherwise Cleared if bit 0 of immediate operand is zero Unchanged otherwise Instruction Format lt 2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 1 0 0 1 1 1 1 1 0 0 WORD DATA CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4 31 ASL ASR Arithmetic Shift ASL ASR Operation Destination Shifted by count Destination Assembler ASd Dx Dy Syntax ASd data Dy ASd ea where d is direction L or R Attributes Size Byte Word Long Description Arithmetically shifts the bits of the operand in the direction L or R specified The carry bit receives the last bit shifted out of the operand The shift count for shifting a register may be specified in two ways 1 Immediate Shift count is specified by the instruction shift range 8 1 2 Register The shift count is the value in the data register specified by the in struction modulo 64 An operand in memory can be shifted one bit only and the operand size is restricted to a word For ASL the operand is shifted left the number of positions shifted is the shift count Bits shifted out of the high order bit go to both the carry and the extend bits zeros are shifted into the low order bit The overflow bit indicates if any sign changes occur dur ing the shift
311. sizes of immediate da ta The TST instruction arithmetically compares the operand with zero placing the re sult in the condition code register Table 4 4 summarizes the logical operations Table 4 4 Logic Operations Instruction Syntax Operand Size Operation ea Dn 8 16 32 PRUAN A AND Dn 8 16 32 Source e Destination Destination ANDI data ea 8 16 32 Data e Destination Destination EOR Dn ea 8 16 32 Source Destination Destination EORI data ea 8 16 32 Data Destination Destination NOT ea 8 16 32 Destination Destination ea Dn 8 16 32 MAE T OR ea 8 16 32 Source Destination Destination ORI ea 8 16 32 Data Destination Destination TST ea 8 16 32 Source 0 to set condition codes MOTOROLA INSTRUCTION SET CPU32 4 8 REFERENCE MANUAL 4 3 5 Shift and Rotate Instructions The arithmetic shift instructions ASR and ASL and logical shift instructions LSR and LSL provide shift operations in both directions The ROR ROL ROXR and ROXL in structions perform rotate circular shift operations with and without the extend bit All shift and rotate operations can be performed on either registers or memory Register shift and rotate operations shift all operand sizes The shift count may be specified in the instruction operation word to shift from 1 to 8 places or in a register modulo 64 shift count
312. specific features of individual exception processing routines 6 1 Definition of Exception Processing An exception is a special condition that preempts normal processing Exception pro cessing is the transition from normal mode program execution to execution of a routine that deals with an exception 6 1 1 Exception Vectors An exception vector is the address of a routine that handles an exception The vector base register VBR contains the base address of a 1024 byte exception vector table which consists of 256 exception vectors Sixty four vectors are defined by the proces sor and 192 vectors are reserved for user definition as interrupt vectors Except for the reset vector each vector in the table is one long word in length The reset vector is two long words in length Refer to Table 6 1 for information on vector assignment CAUTION Because there is no protection on the 64 processor defined vectors external devices can access vectors reserved for internal purposes this practice is strongly discouraged All exception vectors except the reset vector are located in supervisor data space The reset vector is located in supervisor program space Only the initial reset vector is fixed in the processor memory map When initialization is complete there are no fixed assignments Since the VBR stores the vector table base address the table can be located anywhere in memory It can also be dynamically relocated for each task exe cuted
313. ssembler Syntax NEGX ea Attributes Size Byte Word Long Description Subtracts the destination operand and the extend bit from zero Stores the result in the destination location Condition Codes X N 7 V Set the same as the carry bit Set if the result is negative Cleared otherwise Set if the result is zero Cleared otherwise Set if an overflow occurs Cleared otherwise Cleared if the result is zero Set otherwise lt 2 NOTE Normally the Z condition bit is set via programming before the start of the operation This allows successful tests for zero results upon completion of multiple precision operations Instruction Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EFFECTIVE ADDRESS 0 1 0 0 0 0 0 0 SIZE MODE REGISTER Instruction Fields Size field Specifies the size of the operation 00 Byte operation 01 Word operation 10 Long operation CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4 117 NEGX Effective Address field Specifies the destination operand Only data alterable addressing modes are allowed as shown Negate with Extend NEGX Addressing Mode Mode Register Addressing Mode Mode Register Dn 000 Reg number Dn xxx W 111 000 An xxx L 111 001 An 010 Reg number An data An 011 Reg number An An 100 Reg number An
314. sult is zero Cleared otherwise Always cleared Set according to the last bit shifted out of the operand Cleared for a shift count of zero Instruction Format Register Shifts O lt NZ 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 0 COUNT REGISTER dr SIZE i r 0 1 REGISTER Instruction Fields Register Shifts Count Register field Specifies shift count or register that contains shift count If i r 0 this field contains the shift count The values one to seven represent counts of one to seven value of zero represents a count of eight If i r 1 this field specifies the data register that contains the shift count mod ulo 64 dr field Specifies the direction of the shift 0 Shift right 1 Shift left Size field Specifies the size of the operation 00 Byte operation 01 Word operation 10 Long operation i r field If i r O specifies immediate shift count If i r 1 specifies register shift count Register field Specifies a data register to be shifted CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4 87 LSL LSR Logical Shift LS L LSR Instruction Format Memory Shifts 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EFFECTIVE ADDRESS MODE REGISTER Instruction Fields Memory Shifts dr field Specifies the direction of the shift 0 Shift right 1 Shift left Effective Address field Spe
315. t o lt gt S o o S S o S Sj CPU32 REFERENCE MANUAL M68000 FAMILY SUMMARY MOTOROLA A 3 Table A 2 M68000 Addressing Modes Mode Mnemonic MC68010 CPU32 MC68020 MC68000 Register Direct Rn 9 9 9 Address Register Indirect An 9 9 9 Address Register Indirect with An 9 9 9 Postincrement Address Register Indirect with An 00 9 9 9 Predecrement Address Register Indirect with Displacement 16 An 9 9 9 Address Register Indirect with Index d8 An Xn 9 9 9 8 Bit Displacement Address Register Indirect with Index Base Displacement bd An Xn SCALE 9 9 Memory Indirect with Postincrement bd An Xn Od 9 Memory Indirect with Predecrement bd An Xn Od 9 Absolute Short xxx W 9 9 9 Absolute Long xxx L 9 9 9 Program Counter Indirect with d16 PC 9 9 9 Displacement Program Counter Indirect with Index d8 PC Xn 9 9 9 8 Bit Displacement Program Counter Indirect with Index Base Displacement bd PC Xn SCALE 9 9 Immediate data 9 9 9 Program Counter Memory Indirect with Postincrement bd PC Xn od 9 Program Counter Memory Indirect with Predecrement bd PC od 9 MOTOROLA M68000 FAMILY SUMMARY CPU32 A 4 REFERENCE MANUAL Absolute Long Address Mode 3 9 Absolute Short Address Mode 3 8 AC Electrical Specifications See appropriate user s manual Address bus See appropriate user s manual Address Er
316. t followed immediately by exception processing for the trace 4 1 and then by exception pro cessing for the interrupt 4 3 Each exception places a new context on the stack When the processor resumes normal instruction execution it is vectored to the inter rupt handler which returns to the trace handler that returns to the trap handler There are special cases to which the general rule does not apply The reset exception will always be the first exception handled since reset clears all other exceptions It is also possible for high priority exception processing to begin before low priority excep tion processing is complete For example if a bus error occurs during trace exception processing the bus error will be processed and handled before trace exception pro cessing is completed 6 2 Processing of Specific Exceptions The following paragraphs provide details concerning sources of specific exceptions how each arises and how each is processed 6 2 1 Reset Assertion of RESET by external hardware or assertion of the internal RESET signal by an internal module causes a reset exception The reset exception has the highest priority of any exception Reset is used for system initialization and for recovery from catastrophic failure The reset exception aborts any processing in progress when it is recognized and that processing cannot be recovered Reset performs the following operations Clears TO and T1 in the status register to d
317. t 2 of immediate operand is one Unchanged otherwise Changed if bit 1 of immediate operand is one Unchanged otherwise Changed if bit O of immediate operand is one Unchanged otherwise Instruction Format lt 2 0 0 0 0 1 0 1 0 0 1 1 1 1 1 0 0 WORD DATA 16 BITS CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4 77 EXG Exchange Registers EXG Operation Rx e Assembler EXG Dx Dy Syntax EXG Ax Ay EXG Dx Ay EXG Ay Dx Attributes Size Long Description Exchanges the contents of two 32 bit registers The instruction per forms three types of exchanges 1 Exchange data registers 2 Exchange address registers 3 Exchange a data register and an address register Condition Codes Not affected Instruction Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 0 0 REGISTER Rx 1 OPMODE REGISTER Ry Instruction Fields Register Rx field Specifies either a data register or an address register depending on the mode If the exchange is between data and address registers this field always specifies the data register Opmode field Specifies the type of exchange 01000 Data registers 01001 Address registers 10001 Data register and address register Register Ry field Specifies either a data register or an address register depending on the mode If the exchange is between data and address registers this field always specifi
318. t maintains the program counter under se quencer control The bus control contains a write pending buffer that allows the sequencer to continue execution of instructions after a request for a write cycle is queued See SECTION 8 INSTRUCTION EXECUTION TIMING for a detailed expla nation of instruction execution MOTOROLA OVERVIEW CPU32 1 6 REFERENCE MANUAL SEQUENCER CONTROL INSTRUCTION UNIT PIPELINE AND S DECODE DATA BUS e 16 gt Bis EXECUTION CONTROL BUS CONTROL UNIT Oo ADDRESS BUS 32 K Figure 1 2 CPU32 Block Diagram CPU32 OVERVIEW MOTOROLA REFERENCE MANUAL 1 7 MOTOROLA OVERVIEW CPU32 1 8 REFERENCE MANUAL SECTION 2ARCHITECTURE SUMMARY The CPU32 is upward source and object code compatible with the MC68000 and MC68010 It is downward source and object code compatible with the MC68020 With in the M68000 Family architectural differences are limited to the supervisory operating state User state programs can be executed unchanged on upward compatible devic es The major CPU32 features are as follows e 32 Bit Internal Data Path and Arithmetic Hardware 32 Bit Address Bus Supported by 32 Bit Calculations Rich Instruction Set Eight 32 Bit General Purpose Data Registers Seven 32 Bit General Purpose Address Registers Separate User and Supervisor Stack Pointers Separate User and Supervisor State Address Spaces Separate Program an
319. t significant word can be sign extended to provide a 32 bit index value refer to Figure 3 3 CPU32 DATA ORGANIZATION AND ADDRESSING CAPABILITIES MOTOROLA REFERENCE MANUAL 3 11 31 16 15 0 USED IN ADDRESS CALCULATION Figure 3 3 Using SIZE in the Index Selection For the CPU32 the register indirect modes can be extended further Because dis placements can be 32 bits wide they can represent absolute addresses or the results of expressions that contain absolute addresses This scheme allows the general reg ister indirect form to be bd Rn or bd An Rn when the base register is not sup pressed Thus an absolute address can be directly indexed by one or two registers refer to Figure 3 4 Setting the index register suppress bit IS in the full format extension word suppresses the index operand The indirect suppressed index register mode uses the contents of register An as an index to the pointer located at the address specified by the displace ment The actual data item is at the address in the selected pointer An optional scaling function supports direct array subscripting An index register can be left shifted by zero one two or three bits before use in an EA calculation to scale for an array of elements of corresponding size This is much more efficient than using an arithmetic value in one of the general purpose registers to multiply the index regis ter by one two four or eight SYNTAX bd An Rin
320. ta An 011 Reg number An An 100 Reg number An dig An 101 Reg number An 916 PC _ dg An 110 Reg number An dg PC Xn bd An Xn 110 Reg number An bd PC Xn mE NOTES 1 If the destination is a data register it must be specified as a destination Dn address not as a destination ea address 2 Most assemblers use SUBA when the destination is an address register and SUBI or SUBQ when the source is immediate data CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4 145 S U BA Subtract Address 5 U BA Operation Destination Source Destination Assembler Syntax SUBA ea An Attributes Size Word Long Description Subtracts the source operand from the destination address register and stores the result in the address register Word size source operands are sign extended to 32 bit quantities prior to the subtraction Condition Codes Not affected Instruction Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EFFECTIVE ADDRESS 1 0 0 1 REGISTER OPMODE MODE REGISTER Instruction Fields Register field Specifies the destination any of the eight address registers Opmode field Specifies the size of the operation 011 Word operation The source operand is sign extended to a long oper and and theoperation is performed on the address register using all 32 bits 111 Long operation Effective Address field Specifies th
321. tem Control 4 11 4 10 Condition LOSES C 4 12 4 11 4 170 5 1 Address it eae oft 5 3 6 1 Exception Vector AsSighimernts tege eene etes nuege 6 2 6 2 Exception Priority Groups 2 6 4 6 3 Tracing 6 11 7 1 BDM Source SUITImiBly 7 4 7 2 Polling the BDM Entry Source acer rro p dp E 7 5 7 3 CPU Generated Message 7 8 7 4 BDM Command SUM MANY sso reote ees 7 14 A 1 M68000 instruction Set A 3 A 2 M68000 Addressing eret emet Pc ee t A 4 CPU32 MOTOROLA REFERENCE MANUAL xiii LIST OF TABLES Continued Table Title Page MOTOROLA CPU32 xiv REFERENCE MANUAL SECTION 1 OVERVIEW The CPU32 the first generation instruction processing module of the M68300 Family is based on the industry standard MC68000 processor It has many features of the MC68010 and MC68020 as well as unique features suited for high performance con troller applications The CPU32 is source code and binary code compatible with the M68000 Family CPU32 power consumption during normal
322. the entire destina tion address register is used regardless of the operation size Condition Codes X N 7 V X Set to the value of the carry bit N Set if the result is negative Cleared otherwise Z Set if the result is zero Cleared otherwise V Set if an overflow occurs Cleared otherwise Set if a borrow occurs Cleared otherwise Instruction Format 15 14 13 12 11 10 9 8 6 5 4 3 2 1 0 EFFECTIVE ADDRESS 0 1 0 1 DATA 1 SIZE MODE REGISTER CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4 149 SU BQ Subtract Quick SU BQ Instruction Fields Data field Three bits of immediate data 1 7 represent immediate values of 1 7 and 0 represents 8 Size field Specifies the size of the operation 00 Byte operation 01 Word operation 10 Long operation Effective Address field Specifies the destination location Only alterable address ing modes are allowed as shown Addressing Mode Mode Register Addressing Mode Mode Register Dn 000 Reg number Dn xxx W 111 000 An xxx L 111 001 An 010 Reg number An data An 011 Reg number An An 100 Reg number An 96 An 101 Reg number An 96 PC dg An Xn 110 Reg number An dg PC Xn e bd An Xn 110 Reg number An bd PC Xn Word and long only MOTOROLA INSTRUCTION SET CPU32 4 150 REFE
323. the table 8 Bit Displacement field Twos complement integer specifying the number of bytes between the branch instruction and the next instruction to be executed if the condition is met 16 Bit Displacement field Used for displacement when 8 bit displacement field contains 00 32 Bit Displacement field Used for displacement when 8 bit displacement field contains FF NOTE A branch to the instruction immediately following automatically uses 16 bit displacement because the 8 bit displacement field contains 00 zero offset MOTOROLA INSTRUCTION SET CPU32 4 36 REFERENCE MANUAL BCHG Test a Bit and Change BCHG Operation number of Destination Z number of Destination bit number of Destination Assembler BCHG Dn ea Syntax BCHG lt data ea Attributes Size Byte Long Description Tests a specified bit in the destination operand sets the Z condition code appropriately then inverts the specified bit When the destination is a data regis ter any of the 32 bits can be specified by the modulo 32 bit number When the desti nation is a memory location the operation is a byte operation and the bit number is modulo 8 In all cases bit zero refers to the least significant bit The bit number for this operation may be specified in either of two ways 1 Immediate The bit number is specified by a second instruction word 2 Register The specified data register contains the bit number C
324. therwise Set if a borrow is generated Cleared otherwise O lt NZ amp 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EFFECTIVE ADDRESS 1 1 0 1 REGISTER OPMODE MODE REGISTER Instruction Fields Register field Specifies any of the eight data registers Opmode field Byte Word Long Operation 000 001 010 ea Dn gt Dn 100 101 110 Dn ea 2 ea MOTOROLA INSTRUCTION SET CPU32 4 144 REFERENCE MANUAL 5 U B Subtract 5 U B Effective Address field Determines the addressing mode If the location specified is a source operand all addressing modes are allowed as shown Addressing Mode Mode Register Addressing Mode Mode Register Dn 000 Reg number Dn xxx W 111 000 An 001 Reg number An xxx L 111 001 An 010 Reg number An data 111 100 An 011 Reg number An An 100 Reg number An 96 An 101 Reg number An dig PC 111 010 dg An Xn 110 Reg number An dg PC Xn 111 011 bd An Xn 110 Reg number An bd PC Xn 111 011 For byte size operation address register direct is not allowed If the location specified is a destination operand only memory alterable addressing modes are allowed as shown Addressing Mode Mode Register Addressing Mode Mode Register Dn xxx W 111 000 An xxx L 111 001 An 010 Reg number An da
325. this case the con trol index count must be one less than the desired number of loop executions However when entering a loop by branching to the trailing DBcc instruction the control count should equal the loop execution count so that the DBcc instruction will not branch and the main loop will not execute if a zero count occurs CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4 65 D VS Signed Divide D VS DIVSL DIVSL Operation Destination Source Destination Assembler Syntax DIVS W ea Dn32 16 16r 16q DIVS L 0432 32 32q DIVS L Dr Dq64 32 gt 32r 32q DIVSL L Dr Dq32 32 32r 32q Attributes Size Word Long Description Divides the signed destination operand by the signed source oper and and stores the signed result in the destination The instruction uses one of four forms The word form of the instruction divides a long word by a word The result is a quotient in the lower word least significant 16 bits and a remainder in the upper word most significant 16 bits of the destination The sign of the remainder is the same as the sign of the dividend The first long form divides a long word by a long word The result is a long quotient the remainder is discarded The second long form divides a quad word in any two data registers by a long word The result is a long word quotient and a long word remainder The third long form divides a long word by a long word The result
326. tination MOVE Destination Effective Address field Specifies the destination location Only data alterable addressing modes are allowed as shown Addressing Mode Mode Register Addressing Mode Mode Register Dn 000 Reg number Dn xxx W 111 000 An xxx L 111 001 An 010 Reg number An data An 011 Reg number An An 100 Reg number An 96 An 101 Reg number An 96 PC dg An Xn 110 Reg number An dg PC Xn bd An Xn 110 Reg number An bd PC Xn Source Effective Address field Specifies the source operand All addressing modes are allowed as shown Addressing Mode Mode Register Addressing Mode Mode Register Dn 000 Reg number Dn xxx W 111 000 An 001 Reg number An xxx L 111 001 An 010 Reg number An data 111 100 An 011 Reg number An An 100 Reg number An 416 101 Reg number dig PC 111 010 dg An Xn 110 Reg number An dg PC Xn 111 011 bd An Xn 110 Reg number An bd PC Xn 111 011 For byte size operation address register direct is not allowed NOTES 1 Most assemblers use MOVEA when the destination is an address register 2 MOVEQ can be used to move an immediate 8 bit value to a data register MOTOROLA INSTRUCTION SET CPU32 4 90 REFERENCE MANUAL MOVEA Move Address MOV EA Operation Source
327. tion Subtracts the source operand from the destination address register and sets the condition codes according to the result The address register is not changed The size of the operation can be specified as word or long Word length source operands are sign extended to 32 bits for comparison Condition Codes X N 2 V X Not affected N Set if the result is negative Cleared otherwise Z Set if the result is zero Cleared otherwise V Set if an overflow is generated Cleared otherwise Set if a borrow is generated Cleared otherwise Instruction Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EFFECTIVE ADDRESS 1 0 1 1 REGISTER OPMODE MODE REGISTER Instruction Fields Register field Specifies the destination address register Opmode field Specifies the size of the operation 011 Word operation The source operand is sign extended to a long oper and and the operation is performed on the address register using all 32 bits 111 Long operation CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4 57 CMPA Effective Address field Specifies source operand All addressing modes allowed as shown Compare Address CMPA Addressing Mode Mode Register Addressing Mode Mode Register Dn 000 Reg number Dn 111 000 001 Reg number An xxx L 111 001 An 010 Reg number An
328. tion vector table The table contains 256 exception vectors Exception vectors are the memory addresses of routines that begin execution at the completion of exception pro cessing Each routine performs operations appropriate to the corresponding excep tion Because exception vectors are memory addresses each table entry is a single long word Each vector is assigned an 8 bit number Vector numbers for some exceptions are ob tained from an external device others are supplied automatically by the processor The processor multiplies the vector number by four to calculate vector offset then adds the offset to the VBR base address The sum is the memory address of the vec tor Because the VBR stores the vector table base address the table can be located any where in memory It can also be dynamically relocated for each task executed by an operating system Details of exception processing are provided in SECTION 6 EX CEPTION PROCESSING 1 1 4 Exception Handling The processing of an exception occurs in four steps with variations for different ex ception causes During the first step a temporary internal copy of the status register is made and the status register is set for exception processing During the second step the exception vector is determined During the third step the current processor context is saved During the fourth step a new context is obtained and the processor then proceeds with normal instruction execution Excep
329. tion continues with the next instruction Condition Codes Not affected Instruction Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 0 0 1 1 1 0 0 1 1 1 0 0 0 0 CPU32 INSTRUCTION SET MOTOROLA REFERENCE MANUAL 4 129 ROL ROR Rotate Without Extend ROL ROR Operation Destination Rotated by count Destination Assembler ROd Dx Dy Syntax ROd data Dy ROd ea where d is direction L or R Attributes Size Byte Word Long Description Rotates the bits of the operand in the direction specified L or R The extend bit is not included in the rotation For register rotation the rotation count can be specified in either of two ways 1 Immediate The count 1 8 is specified by the instruction 2 Register The count is the value in the data register specified by the instruc tion modulo 64 The size of the operation for register destinations is specified as byte word or long The contents of memory ea can be rotated one bit only and operand size is restrict ed to a word The ROL instruction rotates the bits of the operand to the left the rotate count deter mines the number of bit positions rotated Bits rotated out of the high order bit go to the carry bit and also back into the low order bit ROL lt lt lt r The ROR instruction rotates the bits of the operand to the right the rotate
330. tion processing saves the most volatile portion of the current context by pushing it on the supervisor stack This context is organized in a format called an exception stack frame The stack frame always includes the status register and program counter at the time an exception occurs To support generic handlers the processor also plac es the vector offset in the exception stack frame and marks the frame with a format code The return from exception RTE instruction uses the format code to determine what information is on the stack so that context can be properly restored CPU32 OVERVIEW MOTOROLA REFERENCE MANUAL 1 3 1 1 5 Enhanced Addressing Modes Addressing in the CPUS2 is register oriented Most instructions allow the results of the specified operation to be placed either in a register or in memory There is no need for extra instructions to store register contents in memory There are seven basic addressing modes Register Direct Register Indirect Register Indirect with Index Program Counter Indirect with Displacement Program Counter Indirect with Index Absolute Immediate The register indirect addressing modes include postincrement predecrement and off set capability The PC relative mode also has index and offset capabilities In addition to the addressing modes many instructions implicitly specify the use of a status reg ister SP and or PC Addressing is explained fully in SECTION 3 DATA ORGANIZA TION AND ADDRESSING
331. to synchronize with in struction stream activity Refer to 7 3 Deterministic Opcode Tracking for complete information MOTOROLA DEVELOPMENT SUPPORT CPU32 REFERENCE MANUAL 7 1 3 On Chip Hardware Breakpoint Overview An external breakpoint input and an on chip hardware breakpoint capability permit breakpoint trap on any memory access Off chip address comparators preclude break points on internal accesses unless show cycles are enabled Breakpoints on prefetched instructions which are flushed from the pipeline before execution are not acknowledged but operand breakpoints are always acknowledged Acknowledged breakpoints can initiate either exception processing or background debug mode BDM See 6 2 6 Hardware Breakpoints for more information 7 2 Background Debug Mode BDM BDM is an alternate CPU32 operating mode During BDM normal instruction execu tion is suspended and special microcode performs debugging functions under exter nal control Figure 7 3 is a BDM block diagram SERIAL INTERFACE SEQUENCER MICROCODE gt IFETCH DSI B NI PT DSCLK BUS CONTROL DATA BUS BERR FREEZE EXECUTION UNIT ADDRESS BUS Figure 7 3 BDM Block Diagram BDM can be initiated in several ways by externally generated breakpoints by inter nal peripheral breakpoints by the background BGND instruction or by catastrophic exception conditions While in
332. to the destination operand and stores the result in the destination location The size of the immediate data must match the oper ation size Condition Codes x N Z V C Set the same as the carry bit Set if the result is negative Cleared otherwise Set if the result is zero Cleared otherwise Set if an overflow is generated Cleared otherwise Set if a carry is generated Cleared otherwise Instruction Format O lt NZ amp 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EFFECTIVE ADDRESS 0 0 0 0 0 1 1 0 SIZE MODE REGISTER WORD DATA 16 BITS BYTE DATA 8 BITS LONG DATA 32 BITS Instruction Fields Size field Specifies the size of the operation 00 Byte operation 01 Word operation 10 Long operation MOTOROLA INSTRUCTION SET CPU32 4 20 REFERENCE MANUAL ADDI Only data alterable addressing modes are allowed as shown Add Immediate Effective Address field Specifies the destination operand ADDI Addressing Mode Mode Register Addressing Mode Mode Register Dn 000 Reg number Dn xxx W 111 000 An xxx L 111 001 An 010 Reg number An data An 011 Reg number An An 100 Reg number An 96 An 101 Reg number An 96 PC dg An Xn 110 Reg number An dg PC Xn bd An Xn 110 Reg number An bd PC Xn Immediate fiel
333. tructions that can alter the S bit in the status register are priv ileged The TRAP instruction provides controlled user access to operating system services 5 2 2 User Privilege Level If the S bit in the status register is cleared the processor executes instructions at the user privilege level The bus cycles for an instruction executed at the user privilege lev el are classified as user references and the values of the function codes on FC 2 0 specify user address spaces While the processor is at the user level implicit referenc es to the system stack pointer and explicit references to address register seven A7 refer to the user stack pointer USP 5 2 3 Changing Privilege Level To change from user privilege level to supervisor privilege level a condition that caus es exception processing must occur When exception processing begins the current values in the status register including the S bit are saved on the supervisor stack and then the S bit is set enabling supervisory access Execution continues at supervisor level until exception processing is complete To return to user access level a system routine must execute one of the following in structions MOVE to SR ANDI to SR EORI to SR ORI to SR or RTE These instruc tions execute only at supervisor privilege level and can modify the S bit of the status register After these instructions execute the instruction pipeline is flushed then re filled from the appro
334. ts A condition test is the evaluation of a logical expression relat ed to the state of the CCR bits If the result is one the condition is true If the result is zero the condition is false For example the T condition is always true and the EQ condition is true only if the Z bit condition code is true Table 4 10 lists each condition test Table 4 10 Condition Tests Mnemonic Condition Encoding Test T True 0000 1 F False 0001 0 HI High 0010 Cez LS Low or Same 0011 C Z CC Carry Clear 0100 CS Carry Set 0101 MOTOROLA INSTRUCTION SET CPU32 4 12 REFERENCE MANUAL Table 4 10 Condition Tests Continued Mnemonic Condition Encoding Test NE Not Equal 0110 2 EQ Equal 0111 Z VC Overflow Clear 1000 V VS Overflow Set 1001 V PL Plus 1010 N MI Minus 1011 N GE Greater or Equal 1100 NeV NeV LT Less Than 1101 NeV NeVv GT Greater Than 1110 NeVeZ NeVeZ LE Less or Equal 1111 ZNeV NeV Not available for the Bcc instruction 4 4 Instruction Details The following paragraphs contain detailed information about each instruction in the CPUS32 instruction set The instruction descriptions are arranged alphabetically by in struction mnemonic Figure 4 2 shows the format of the instruction descriptions 4 2 1 Notation applies with the following additions A The attributes line specifies the size of the operands of an instruction When an instruction ca
335. uction is designed for 8 bit peripherals on a 16 bit data bus The high order byte of the data register is transferred first and the low order byte is transferred last The memory address is specified by the address register indi rect plus 16 bit displacement addressing mode If the address is even all the trans fers are to or from the high order half of the data bus if the address is odd all the transfers are to or from the low order half of the data bus The instruction also Example Long transfer to from an even address Byte Organization in Register 31 24 23 16 15 7 0 HIGH ORDER MID UPPER MID LOWER LOW ORDER Byte Organization in Memory Low Address at Top 158 7 0 HIGH ORDER MID UPPER MID LOWER LOW ORDER MOTOROLA INSTRUCTION SET CPU32 4 102 REFERENCE MANUAL MOVE P Move Peripheral Data Example Word transfer to from an odd address Byte Organization in Register MOVEP 31 24 23 16 15 8 T 0 HIGH ORDER LOW ORDER Byte Organization in Memory Low Address at Top 158 7 0 HIGH ORDER LOW ORDER Condition Codes Not affected Instruction Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 DATA REGISTER OPMODE 0 0 1 ADDR REGISTER DISPLACEMENT 16 BITS Instruction Fields Data Register field Specifies the data register for the instruction Opmode field Specifies the direction and size of the operation
336. ulate instructions in software Word patterns with bits 15 12 1010 referred to as A line opcodes are unimple mented instructions A separate exception vector vector 10 offset 28 is given to un implemented instructions to permit efficient emulation Word patterns with bits 15 12 1111 referred to as F line opcodes are used for M68000 Family instruction set extensions They can generate an unimplemented in struction exception caused by the first extension word of the instruction or by the ad dressing mode extension word A separate F line emulation vector vector 11 offset 2C is used for the exception vector CPU32 EXCEPTION PROCESSING MOTOROLA REFERENCE MANUAL 6 9 All unimplemented instructions are reserved for use by Motorola for enhancements and extensions to the basic M68000 architecture Opcode pattern 4AFC is defined to be illegal on all M68000 Family members Those customers requiring the use of an unimplemented opcode for synthesis of custom instructions operating system calls etc should use this opcode Exception processing for illegal and unimplemented instructions is similar to that for traps The instruction is fetched and decoding is attempted When the processor de termines that execution of an illegal instruction is being attempted exception process ing begins No registers are altered Exception processing follows the regular sequence The vector number is generated to refer to the illegal inst
337. ulation Instructions The bit manipulation instruction table indicates the number of clock periods needed for the processor to perform the specified operation on the given addressing mode The total number of clock cycles is outside the parentheses The numbers inside parenthe ses r p w are included in the total clock cycle number All timing data assumes two clock reads and writes Instruction Head Tail Cycles BCHG Dn 2 0 6 0 2 0 BCHG Dn Dm 4 0 6 0 1 0 BCHG FEA 1 2 8 0 2 1 BCHG Dn FEA 2 2 8 0 1 1 BCLR Dn 2 0 6 0 2 0 BCLR Dn Dm 4 0 6 0 1 0 BCLR FEA 1 2 8 0 2 1 BCLR Dn FEA 2 2 8 0 1 1 BSET Dn 2 0 6 0 2 0 BSET Dn Dm 4 0 6 0 1 0 BSET FEA 1 2 8 0 2 1 BSET Dn FEA 2 2 8 0 1 1 BTST Dn 2 0 4 0 2 0 BTST Dn Dm 2 0 4 0 1 0 BTST FEA 1 0 4 0 2 0 BTST Dn FEA 2 0 8 0 1 0 An fetch effective address time must be added for this instruction FEA FEA OPER 8 3 11 Conditional Branch Instructions The conditional branch instruction table indicates the number of clock periods needed for the processor to perform the specified branch on the given branch size with com plete execution times given No additional tables are needed to calculate total effective execution time for these instructions The total number of clock cycles is outside the parentheses The numbers inside parentheses r p w are included in the
338. ult Consequently MOVEM like all other type Il exceptions will be restarted upon return from the exception handler When a fault occurs after an operand has transferred that transfer is not undone However these memory locations are accessed a second time when the instruction is restarted If a register used in an effective address calculation is overwritten before a fault occurs an incorrect effective address is calculated upon instruction restart MOTOROLA EXCEPTION PROCESSING CPU32 6 20 REFERENCE MANUAL 6 3 2 6 Type Correcting Faults via RTE The preferred method of MOVEM bus fault recovery is to correct the cause of the fault and then execute an RTE instruction without altering the stack contents The RTE recognizes that MOVEM was in progress when a fault occurred restores the appropriate machine state refetches the instruction repeats the faulted transfer and continues the instruction MOVEM is the only instruction continued upon return from an exception handler Al though the instruction is refetched the effective address is not recalculated and the mask is rescanned the same number of times as before the fault modifying the code prior to RTE can cause unexpected results 6 3 2 7 Type IV Correcting Faults via Software BERR exceptions can occur during exception processing while the processor is fetch ing an exception vector or while it is stacking The same stack frame and SSW are used in both cases but ea
339. ut using the program counter in calculating the EA The user can access the program space with a data reg ister indirect access by placing ZPC in the instruction and specifying a data register Dn as the index register GENERATION EA PC Xn bd ASSEMBLER SYNTAX bd PC Xn SIZE SCALE MODE 111 REGISTER 011 31 0 PROGRAM COUNTER E ADDRESS OF EXTENSION WORD 81 0 BASE DISPLACEMENT SIGN EXTENDED VALUE 81 0 INDEX REGISTER SIGN EXTENDED VALUE SCALE SCALE VALUE Ww 81 Y 0 MEMORY ADDRESS NUMBER OF EXTENSION WORDS 1 2 OR3 OPERAND 3 4 3 4 Absolute Short Address In this addressing mode the operand is in memory and the address of the operand is in the extension word The 16 bit address is sign extended to 32 bits before it is used GENERATION EA GIVEN ASSEMBLER SYNTAX MODE 111 REGISTER 000 31 15 0 EXTENSION WORD SIGN EXTENDED MEMORY ADDRESS 31 Y 0 MEMORY ADDRESS NUMBER OF EXTENSION WORDS 1 OPERAND MOTOROLA DATA ORGANIZATION AND ADDRESSING CAPABILITIES CPU32 3 8 REFERENCE MANUAL 3 4 3 5 Absolute Long Address In this mode the operand is in memory and the address of the operand occupies the two extension words following the instruction word in memory The first extension word contains the high order part of the address the low order part of the address is the second extension word G
340. ve as breakpoint instructions See 6 2 5 Software Breakpoints for more information Unimplemented Instruction Emulation When an attempt is made to execute an illegal instruction an illegal instruction exception occurs Unimplemented instruc tions F line A line utilize separate exception vectors to permit efficient emulation of unimplemented instructions in software See 6 2 8 Illegal or Unimplemented Instructions for more information 7 1 CPU32 Integrated Development Support In addition to standard MC68000 family capabilities the CPU32 has features to sup port advanced integrated system development These features include background debug mode deterministic opcode tracking hardware breakpoints and internal visi bility in a single chip environment 7 1 1 Background Debug Mode BDM Overview Microprocessor systems generally provide a debugger implemented in software for system analysis at the lowest level The BDM on the CPU32 is unique because the debugger is implemented in CPU microcode BDM incorporates a full set of debug options registers can be viewed and or altered memory can be read or written and test features can be invoked A resident debugger simplifies implementation of an in circuit emulator In a common setup see Figure 7 1 emulator hardware replaces the target system processor A complex expensive pod and cable interface provides a communication path between target system and emulator By contrast
341. verlapped execution The MOVE instruction has a head of zero and a tail of four because it is a long write The LSL instruction has a head of four The trailing write from the MOVE overlaps the LSL head completely Thus the two instruction se quence has a head of zero and a tail of zero and a total execution of eight rather than 12 clocks General observations regarding calculation of execution time are as follows Any time the number of bus cycles is listed as X substitute a value of one for byte and word cycles and a value of two for long cycles For long bus cycles usually add a value of two to the tail The time calculated for an instruction on a three clock or longer bus is usually longer than the actual execution time All times shown are for two clock bus cycles If the previous instruction has a negative tail then a prefetch for the current instruc tion can begin during the execution of that previous instruction Certain instructions requiring an immediate extension word immediate word effec tive address absolute word effective address address register indirect with dis placement effective address conditional branches with word offsets bit operations LPSTOP TBL MOVEM MOVEC MOVES MOVEP MUL L DIV L CHK2 CMP2 and DBco are not permitted to begin until the extension word has been in the instruction pipeline for at least one cycle This does not apply to long offsets or displacements CPU32 INSTRUCTION EXECUTION
342. wed as shown Addressing Mode Mode Register Addressing Mode Mode Register Dn xxx W 111 000 An xxx L 111 001 An 010 Reg number An data An 011 Reg number An An 100 Reg number An dig 101 Reg number An dig PC dg An Xn 110 Reg number An dg PC Xn bd An Xn 110 Reg number An bd PC Xn m A D field Specifies the type of general register 0 Data register 1 Address register Register field Specifies the register number dr field Specifies the direction of the transfer 0 From ea to general register 1 From general register to ea NOTE For either of the two following examples which use the same ad dress register as both source and destination the value stored is un defined The current implementations of the MC68010 CPU32 and MC68020 store the incremented or decremented value of An MOVES x An An MOVES x An An MOTOROLA INSTRUCTION SET CPU32 4 106 REFERENCE MANUAL M U LS Signed Multiply M U LS Operation Source Destination Destination Assembler Syntax MULS W ea Dn16x16 32 MULS L ea DI 32x32 32 MULS L Dh DI32 x 32 64 Attributes Size Word Long Description Multiplies two signed operands yielding a signed result In the word form the multiplier and multiplicand are both word operands and the result is
343. xecution take place in stage C Each pipeline stage has an associated status bit that shows whether the word in that stage was loaded with data from a bus cycle that terminated abnormally 8 1 3 Bus Controller Resources The bus controller consists of the instruction prefetch controller the write pending buffer and the microbus controller These three resources transact all reads writes and instruction prefetches required for instruction execution MOTOROLA INSTRUCTION EXECUTION TIMING CPU32 8 2 REFERENCE MANUAL The bus controller and microsequencer operate concurrently The bus controller can perform a read or write or schedule a prefetch while the microsequencer controls ef fective address calculation or sets condition codes The microsequencer can also request a bus cycle that the bus controller cannot per form immediately When this happens the bus cycle is queued and the bus controller runs the cycle when the current cycle is complete 8 1 3 1 Prefetch Controller The instruction prefetch controller receives an initial request from the microsequencer to initiate prefetching at a given address Subsequent prefetches are initiated by the prefetch controller whenever a pipeline stage is invalidated either through instruction completion or through use of extension words Prefetch occurs as soon as the bus is free of operand accesses previously requested by the microsequencer Additional state information permits the controller to
344. y the serial clock However normal and BDM operations could interact if the clock generator is not properly designed Breakpoint requests are made by asserting BKPT to the low state in either of two ways The primary method is to assert BKPT during a single bus cycle for which an exception is desired Another method is to assert BKPT then continue to assert it until the CPU32 responds by asserting FREEZE This method is useful for forcing a transi tion into BDM when the bus is not being monitored Each of these methods requires a slightly different serial logic design to avoid spurious serial clocks Figure 7 7 represents the timing required for asserting BKPT during a single bus cy cle SHIFT CLK l l l FORCE_BGND BKPT_TAG N O Lo T UWUUUUUUUUUUUUUUUUUU FREEZE Figure 7 7 BKPT Timing for Single Bus Cycle Figure 7 8 depicts the timing of the BKP T FREEZE method In both cases the serial clock is left high after the final shift of each transfer This technique eliminates the pos sibility of accidentally tagging the prefetch initiated at the conclusion of a BDM session As mentioned previously all timing within the CPU is derived from the rising edge of the clock the falling edge is effectively ignored SHIFT_CLK FORCE_BGND _ BKPT_TAG 25 STUUUUUUUUUUUUUU FREEZE ff Le Figure 7 8 BKPT Timing for Forcing BDM MOTOROLA DEVELOPMENT SUPPORT CPU32 7 10 REFERENCE MANUAL Figure
345. yte Description Performs an AND operation of the immediate operand with the con dition codes and stores the result in the low order byte of the status register Condition Codes X N Z V C O lt NZX Cleared if bit 4 of immediate operand is zero Unchanged otherwise Cleared if bit 3 of immediate operand is zero Unchanged otherwise Cleared if bit 2 of immediate operand is zero Unchanged otherwise Cleared if bit 1 of immediate operand is zero Unchanged otherwise Cleared if bit 0 of immediate operand is zero Unchanged otherwise Instruction Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0 0 0 0 0 0 0 1 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 BYTE DATA 8 BITS MOTOROLA INSTRUCTION SET CPU32 4 30 REFERENCE MANUAL AN DI AND Immediate to the Status Register AN DI to SR Privileged Instruction to SR Operation If supervisor state then Source SR S5 SR else TRAP Assembler Syntax ANDI data SR Attributes Size Word Description Performs an AND operation of the immediate operand with the con tents of the status register and stores the result in the status register All implemented bits of the status register are affected Condition Codes x N 7 V Cleared if bit 4 of immediate operand is zero Unchanged otherwise Cleared if bit 3 of immediate operand is zero Unchanged otherwi
346. zero Exception processing for traps follows the regular sequence If tracing is enabled when an instruction that causes a trap begins execution a trace exception will be gen erated by the instruction but the trap handler routine will not be traced the trap excep tion will be processed first then the trace exception The vector number for the TRAP instruction is internally generated part of the num ber comes from the instruction itself The trap vector number program counter value and a copy of the status register are saved on the supervisor stack The saved pro gram counter value is the address of the instruction that follows the instruction which generated the trap For all instruction traps other than TRAP a pointer to the instruc tion causing the trap is also saved in the fifth and sixth words of the exception stack frame 6 2 5 Software Breakpoints To support hardware emulation the CPU32 must provide a means of inserting break points into target code and of announcing when a breakpoint is reached The MC68000 and MC68008 can detect an illegal instruction inserted at a breakpoint when the processor fetches from the illegal instruction exception vector location Since the VBR on the CPU32 allows relocation of exception vectors the exception vector ad dress is not a reliable indication of a breakpoint CPU32 breakpoint support is provided by extending the function of a set of illegal instructions 4848 484F When a bre

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