Evaluation Board User Guide
Contents
1. o r eSTesvs larg oo ga osta v CIEN 2 Bs c Bs EA a Bs or T sy 0 Zd W 8 E c E a ER ore Te zd T 69T699 lOTU EST eds OI jou 0050522021 ai ie Pe c pe Sy aso 5 Bs 8537215515 D gs B go X e ES re Td Figure 22 Capture Board Connector Rev 0 Page 18 of 28 UG 074 IT Ier 2A MAX O O O Oo o o au DIG AMP INPUT de p18 INPUT EXT_NEG_AMP_V 2 E S BI oS S 8 ANALOG 4 Pu al DEVICES CoS g J3TP604 T o d ay e SYNC_INPUT o NA am j 52 pac A e E gier P59 FMON M Low i CUSTOMER Po ei O oo EVALUATION weer P603 Bog TATUS 2 Ei BOARD 5 de PECL_OUT L J603 XTAL_INT 9265CEO1A CLK IN 7 g265CEO1A J602 R6 di CHARGE PUMP Ne FILTER 08699 023 Figure 23 Top Side Rev 0 Page 19 of 28 Evaluation Board User Guide 08699 024 Figure 24 Ground Plane Layer 2 Rev 0 Page 20 of 28 Evaluation Board User Guide UG 074 08699 025 Rev 0 Page 21 of 28 Evaluation Board User Guide HUA 08699 026 o O9 QQ 0ooooo C nooooo o o o O ooo o eoo o o o 006 ooo oo 00 oo o O oo E o o 00 O oo 95 SS c E ez 000 0 00 O O o o o e o o 9 08000 o o oo Bren Bie Me 8 O O O2. Analog Devices ADP1706ARDZ 3 3 R7 SO8NB PAD3_1X2_41 50 3 U5 U7 U603 IC TinyLogic UHS dual buffer Fairchild NC7WZ16P6X SC70 Rev 0 Page 25 of 28 UG 074 Item No Qty Reference Designator Description Manufacturer Part No 51 1 U6 IC compact 600 mA 3 MHz Analog Devices ADP2108AUJZ 1 8 R7 step down dc to dc converter 5 lead TSOT 52 1 U601 IC 12 output clock gen Analog Devices AD9517 4BCPZ with int 1 6 GHz VCO QFNA8 7X7 PAD5 1X5 1 53 1 U8 IC low dropout CMOS lin reg Analog Devices ADP1708ARDZ R7 SO8NB PAD3 1X2 41 54 2 U9 U10 IC low dropout CMOS lin reg Analog Devices ADP1706ARDZ 1 8 R7 SO8NB PAD3 1X2 41 55 C1 Capacitor chip mono Murata GJM1555C1H2R2WBO1 ceramic COG 0402 2 2 pF 56 C13 Capacitor chip mono Murata GRM1555C1H101JD01D ceramic COG 0402 100 pF 57 C49 C50 Ceramic capacitor 1000 pF Panasonic ECU E1E102KBQ 58 C6 C25 C30 C51 C52 C70 Ceramic capacitor 0402 0 1 uF Panasonic ECJ OEX1C104K C97 C603 C604 C620 C623 C624 C660 59 C77 C79 C80 C81 Capacitor 0603 X5R 10 uF Panasonic ECJ 1VB0J106M 60 E2 E3 E11 Inductor ferrite bead Panasonic EXC ML20A390U 100 MHz L0805 61 J2 J7 J602 J603 Conn PCB SMA ST edge Samtec SMA J P X ST EM1 mount CNSAMTECSMA JPX ST EM1 MKT 62 L1 L5 L6 Chip inductor 15 nH L7144 Coilcraft 0603CS 15NXGLU 63 L2 L3 Inductor SMT power 2 2 uH Coilcraft EPL2014 222MLB LSMSQ79H57 64 L8 L9 Chip inductor 36 nH L7144 Co
3. dl Tea eH m k Sonat za AS ig ato ert LONE TU DNE h Ei Eu e a aro ar 6Na ec S OPT Ez ve CTA ST Oem Fz st STI GE Ce GNY O ETH VID PII Tra 92 ero err t Houf zz 9 Bla eue LN ora ow STD elie zz SNY TTO TII ST CUT Sr TE Houut zz gt a ero e ST Er aa REH Gala erip zz Sen go er D Du gt Ld Gg EH Ja he Satna zz oT er 2 a Lv ze TNS i E o a v6 Sr Dou zz Se omg Ee zz Sat da aga E So Bug zz ja vom E ako qe zz Ayn La en SpNyE za E La ze 9 UNS gt 2 YAT ore anta rel rel are TED 62 TT E 28 HOT Seu 3448 LAdLNO STd Figure 21 Output Buffer Circuits Rev 0 Page 17 of 28 UG 074 220 66980 I e8Tesvg 9 H3093H nd Toa 1 691699 D I 920920 911d TOU Ire H3UU3H DI Toe I 68T68e THO Y3003H 911d TOE T 59T69 va SadesH 9ma ae asp ar eral sisi olal al l Al A Al Al al T 69T69t9 920930 OC z S D A D uj S aj al El ala alal al al al al al l a T 69Te6SvS H3de3H 5rrad T BSTESvS ata TOS esa TT ES massaro ES 2a ES XDS 0313 5E TO F mmen ES ER Ta H3UU3H 90d Td T 6STesvs H3ug3H amd laT ow B5 Bo TFT 4 7 QET Bea iso oor Pp o 9r je a 19 ES Tear M5 oar ER m D E g i y 0 H3 e3H Sfr dS a 3e eer as OO ol olol DOO ols
4. AN 878 Application Note High Speed ADC SPI Control Software and the AN 877 Application Note Interfacing to High Speed ADCs via SPI for additional information on the 1 available settings H Ca Cycle See 19 BST rg Bee See Sack S ADC mung d F CM tare hna st Par De bete rese TESTIOND Dag Test Moca A DIA NC a T pec bana onse mm H 08699 011 Figure 11 SPIController Example ADCBase 0 Page 5 Click the Run button in the VisualAnalog toolbar see Figure 12 2 08699 012 Figure 12 Run Button Encircled in Red in VisualAnalog Toolbar Collapsed Display Rev 0 Page 9 of 28 UG 074 Adjusting the Amplitude of the Input Signal The next step is to adjust the amplitude of the input signal as follows Adjust the amplitude of the input signal so that the fundamental is at the desired level Examine the Fund Power reading in the left panel of the Graph AD9265 Average FFT window see Figure 13 gt Graph A09268 Average FFT 6 15 2009 1 49 25 PM Fe aal rile sl EN 12M 16M 24M 30M 36M 42M 48M 54M 60M Time 14925 PM Sample Frequency 125 MHz Samples 16364 SNA 77 205 di SNAPS 78 25 d amp SINAD 76 981 Ble DC Power 54538 BFS Ham 3 Power 37 304 Be Harm 4 Power 100 46 Bo Ham 5 Power 112728 dic Harm 6 Power 113553 dic Worst Other Frequency 54 817 Mhir Wani Othes Power 57 535 BFS Noise Hz 156 209 BPS Ha Average Bri No
5. default and optional settings are described CONFIGURING THE BOARD Before using the software for testing configure the evaluation board as follows 1 Connect the evaluation board to the data capture board as shown in Figure 1 and Figure 2 Connect one 6 V 2 5 A switching power supply such as the CUI Inc EPS060250UH PHP SZ supplied to the AD9265 or AD9255 board Connect one 6 V 2 5 A switching power supply such as the CUI EPS060250UH PHP SZ supplied to the HSC ADC EVALCZ board Connect the HSC ADC EVALCZ board at J6 to the PC with a USB cable On the ADC evaluation board confirm that three jumpers are installed on P4 one between Pin 1 and Pin 2 one between Pin 4 and Pin 5 and one between Pin 8 and Pin 9 to connect the SPI bus to the DUT Make sure a low jitter sample clock is applied at J6 On the ADC evaluation board use a clean signal generator with low phase noise to provide an input signal Use a 1 m shielded RG 58 50 Q coaxial cable to connect the signal generator For best results use a narrow band band pass filter with 50 O terminations and an appropriate center frequency Analog Devices uses TTE Allen Avionics and K amp L Microwave band pass filters USING THE SOFTWARE FOR TESTING Setting Up the ADC Data Capture After configuring the board set up the ADC data capture using the following steps 1 Open VisualAnalog on the connected PC The appropriate part type should be listed in th
6. exports GOVERNING LAW This Agreement shall be governed by and construed in accordance with the substantive laws of the Commonwealth of Massachusetts excluding conflict of law rules Any legal action regarding this Agreement will be heard in the state or federal courts having jurisdiction in Suffolk County Massachusetts and Customer hereby submits to the personal jurisdiction and venue of such courts The United Nations Convention on Contracts for the International Sale of Goods shall not apply to this Agreement and is expressly disclaimed 02011 Analog Devices Inc All rights reserved Trademarks and ANALOG registered trademarks are the property of their respective owners UG08699 0 1 11 0 DEVICES www analo g com Rev 0 Page 28 of 28
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8. 09 C610 C611 C612 C613 C614 C615 C616 C617 C618 C619 C621 4 3 C39 C41 C74 Ceramic capacitor mono Murata GRM155R60J105KE19D 0402 1 uF 5 8 C53 C54 C62 C64 C65 Capacitor 0603 X5R 4 7 uF Panasonic ECJ 1VB0J475M C67 C68 C69 6 1 C605 Ceramic capacitor multilayer Panasonic ECJ OEB1E182K X7R 0402 1800 pF 7 1 C606 Ceramic capacitor 0 033 uF Panasonic 0402YD333KAT2A C0402 8 1 C607 Ceramic capacitor 0402 Panasonic ECJ 0EB1H152K 1500 pF 9 1 C622 Ceramic capacitor 0 22 uF Panasonic ECJ 0EBOJ224K C0402 10 9 C7 C9 C55 C56 C57 Ceramic capacitor Murata GRM21BR61C106KE15L C58 C59 C63 C84 monolithic 10 uF C0805 11 C72 C73 Capacitor 0603 X5R 10 uF Panasonic ECJ 1VB0J106M 12 C75 C82 C83 Ceramic capacitor multilayer Panasonic ECJ OEB1E103K X7R 0402 0 01 uF 13 1 CR1 Diode Schottky dual series Avago HSMS 2812BLK SOT23 14 2 CR2 CR601 LED red surface mount Lumex SML LXTO805IW TR 15 4 CR3 CR4 CR5 CR6 Diode recovery rectifier Micro Commercial Components Corp S2A TP DO214AA3 16 1 CR7 LED green surface mount Panasonic LNJ308G8TRA LEDO0603 17 1 DUT Analog to digital converter Analog Devices AD9265BCPZ 80 AD9265BCPZ 105 AD9265BCPZ 125 AD9255BCPZ 80 AD9255BCPZ 105 or AD9255BCPZ 125 per build instructions 18 9 E1 E4 E5 E6 E7 E8 E9 Inductor ferrite bead Panasonic EXC ML20A390U E10 E12 100 MHz L0805 19 1 F1 Fuse polyswitch PTC device Tyco Electronics MINISMDC1 10F 2 1812 1 1 A FTYCOMINI
9. ALYZER l OR VISUAL ANALOG 1 SIGNAL USER SOFTWARE l SYNTHESIZER 1 mg OPTIONAL CLOCK SOURCE Figure 2 Evaluation Board Connection Rev 0 Page 4 of 28 08699 002 DEFAULT OPERATION AND JUMPER SELECTION SETTINGS This section explains the default and optional settings or modes allowed on the AD9265 AD9255 Rev A evaluation board Power Circuitry Connect the switching power supply that is supplied in the evaluation kit between P26 and a rated 100 V ac to 240 V ac wall outlet at 47 Hz to 63 Hz Analog Input The inputs on the evaluation board are set up for a double balun coupled analog input with a 50 2 impedance For the AD9265 AD9255 the default analog input configuration supports analog input frequencies of up to 250 MHz see Figure 3 This input network is optimized to support a wide frequency band See the AD9265 and AD9255 data sheets for additional information on the recommended networks for different input frequency ranges Optionally the analog input on the board can be configured to use the ADL5562 which is a 3 3 GHz ultralow distortion RF IF differential amplifier The ADL5562 component is included on the evaluation board at U1 However the path into and out of the ADLS5562 can be configured in many different ways depending on the application therefore the parts in the input and output path are left unpopulated Users should see the ADL5562 data sheet for additional information on this part and for confi
10. ANALOG DEVICES Evaluation Board User Guide UG 074 One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 Fax 781 461 3113 www analog com Evaluating the AD9265 AD9255 Analog to Digital Converters FEATURES Full featured evaluation board for the AD9265 AD9255 SPI interface for setup and control External on board oscillator or AD9517 clocking options Balun transformer or amplifier input drive options LDO regulator or switching power supply options VisualAnalog and SPI controller software interfaces EQUIPMENT NEEDED Analog signal source and antialiasing filter Sample clock source if not using the on board oscillator 2 switching power supplies 6 0 V 2 5 A provided CUI Inc EPS060250UH PHP SZ PC running Windows XP or Windows Vista USB 2 0 port recommended USB 1 1 compatible AD9265 or AD9255 evaluation board HSC ADC EVALCZ FPGA based data capture kit SOFTWARE NEEDED VisualAnalog SPI controller DOCUMENTS NEEDED AD9265 or AD9255 data sheet HSC ADC EVALCZ data sheet AN 905 Application Note VisualAnalog Converter Evaluation Tool Version 1 0 User Manual AN 878 Application Note High Speed ADC SPI Control Software AN 877 Application Note Interfacing to High Speed ADCs via SPI AN 835 Application Note Understanding High Speed ADC Testing and Evaluation GENERAL DESCRIPTION This user guide describes the AD9265 and AD9255 evaluation board which provides all o
11. GA has been programmed by verifying that the DONE LED is illuminated on the HSC ADC EVALCZ board If this LED is not illuminated make sure the U4 switch on the board is in the correct position for USB CONFIG e Make sure the correct FPGA program was installed by selecting the Settings button in the ADC Data Capture block in VisualAnalog see Figure 7 Then select the FPGA tab and verify that the proper FPGA bin file is selected for the part If VisualAnalog indicates that the FIFO Capture timed out via a pop up window do the following 1 Make sure all power and USB connections are secure 2 Probe the DCO signal at P25 Pin 2 on the evaluation board and confirm that a clock signal is present at the ADC sampling rate Rev 0 Page 10 of 28 UG 074 EVALUATION BOARD SCHEMATICS AND ARTWORK S10 66980 ml 699 oe E Dale lex eso F 95 Aer S 9 99 20T MSL E ZH aa Tay 189 ZHMWOaT EN m EEUU 3 ch MS e B ING 223 8 T ZInegareddg anar us WA em O une S l Nal L zs E ZHWaaT me INT En YET Nin Zed en x me JdaeaaT EISEM ma ma TTS 99 LI eg Ana e xxi Vamos m TORE qz ne G anar Lamar uge Lee M i Ac H3MOd 9NIHOLIMS TWNOTLdO E23 T 229 E mo
12. ORY 1 11 Revision 0 Initial Version Rev 0 Page 2 of 28 UG 074 EVALUATION BOARD HARDWARE The AD9265 and AD9255 evaluation board provides all of the support circuitry required to operate these parts in their various modes and configurations Figure 2 shows the typical bench characterization setup used to evaluate the ac performance of the AD9265 or AD9255 It is critical that the signal sources used for the analog input and clock have very low phase noise 1 ps rms jitter to realize the optimum performance of the signal chain Proper filtering of the analog input signal to remove harmonics and lower the integrated or broadband noise at the input is necessary to achieve the specified noise performance See the Evaluation Board Software Quick Start Procedures section to get started and see Figure 15 to Figure 28 for the complete schematics and layout diagrams These diagrams demonstrate the routing and grounding techniques that should be applied at the system level when designing application boards using these converters POWER SUPPLIES This evaluation board comes with a wall mountable switching power supply that provides a 6 V 2 A maximum output Connect the supply to the rated 100 V ac to the 240 V ac wall outlet at 47 Hz to 63 Hz The output from the supply is provided through a 2 1 mm inner diameter jack that connects to the printed circuit board PCB at P26 The 6 V supply is fused and conditioned on the PCB before con
13. SMDC 1 10F 20 1 FL1 Filter noise suppression LC Murata BNX016 01 combined type 21 4 J1 J3 J6 J9 Conn PCB SMA ST edge Samtec SMA J P X ST EM1 mount CNSAMTECSMA JPX ST EM1 MKT 22 2 JP5 JP8 3 pin solder jumper JPRSLDO3 Not applicable 23 2 P1 P2 Conn PCB 60 pin RA connector Tyco 6469169 1 CNTYCO1469169 1 Rev 0 Page 24 of 28 UG 074 Item No Qty Reference Designator Description Manufacturer Part No 24 1 P26 Conn PCB power jack surface CUI PJ 002AH SMT mount CN 2MM PWR JACK 25 13 P3 P6 P7 P11 P12 P14 P18 Conn PCB header 2 position Samtec TSW 102 08 G S P19 P27 P28 P29 P31 P32 CNSAMTEC1X2H330LD36 26 1 P4 Conn PCB header Samtec TSW 103 08 G T ST male 9 position CNSAMTEC3X3H338LD36 27 3 P5 P10 P30 Conn PCB Berg header Samtec TSW 103 08 G S ST male 3 position CNBERG1X3H205LD36 28 2 P8 P9 Conn PCB header 6 position Wieland Z5 531 3625 0 CNWIELAND5313625 29 22 R1 R6 R10 R11 R30 R31 Resistor film SMD 0402 0 Q Panasonic ERJ 2GEOROOX R46 R47 R48 R52 R53 R77 R79 R81 R83 R85 R86 R608 R623 R627 R629 JP4 30 4 R13 R14 R15 R16 Resistor film SMD 0402 33 Q Panasonic ERJ 2GEJ330X 31 15 R26 R27 R35 R36 R37 R38 Resistor precision thick film Panasonic ERJ 2RKF 1002X R39 R40 R43 R57 R58 R59 chip R0402 10 kQ R68 R69 R70 32 4 R3 R8 R22 R23 Resistor precision thick film Panasonic ERJ 2RKF 1 OROX chip R0402 100 33 2 R25 R33 Resis
14. anta s CAAA ant e S E zas Tad TWA EH 228 2 o o TH T mae L 969 Tuad a mr Sac aL 2 aaocanoOa 551200 oH Ul bey Gus oot e Figure 18 Analog Input Circuits Rev 0 Page 14 of 28 UG 074 2 S S T A o o ING E Eb IND ery anta 1 d T BED ac ING n oe An o ES 2n seu ET DE e s a D Na d 7 D gol d a5 eor OB z y C HALA podra By a gt za 2932 E Kei ZC om t HUNE g T mum i Y ACA AU e THO INT ING m i 3300 gt WerBe susH eeng E EECH E y s a a een a e zm EM acu AULINOYTO 90719 ous HIE A d ous Yog T LH z UNS REE ino at ALLI 3 23 d S 9 89 Z0T MEL 3d Figure 19 Default Clock Path Input Circuits Rev 0 Page 15 of 28 020 66980 UG 074 UNS ant a A mu A era a4nzz p anre 2299 T A A DOT Sa DCH ji anta A DER 2139 fs alo DLD t c 2 Sa ant o ag e STS T szo Dia Ri vTS2 GER 4nr a d 33 s n sn E sa a T N an D 8235 3 by w ano nas INT m ano 931113 dWfid 3O8UHo EE EECH INg Se Tees
15. d con ola N vir G 5 Ge 226 E OH IUS OJIdJ 393 pale en S X9dLOZMLON GO ans QNS uns Figure 17 SPI Interface Circuit Rev 0 Page 13 of 28 UG 074 810 66980 ano ma kua 270 ME S 2 B0 20T MSL 2ovaudr z SE M H3 Y HE E L va LL EN3 NM d Tat std ano ING ma ar I Set Ant ia HNSE HNST 6 ve a eru 66 el gi BvD TR g 222 EI ING veal z 3 z 3878 97 8 a INC ANT e a DO vun IS 3 EM EM 1 ABAT don INIA M i TS ya BL ETI TT NOR tarn E S a ING SEI cava 25 zer E EE L ata Ina Nd I ING SE 9 u S FR ze DEED y HINGE HNST JET ee an ASI oq uf E E gt FINO ane VERAT na eta e 23s Tad Su 67 EN DCH Tee o o D 219 TAA 8 2 n eu vi ES N ov ING e S a ri i d NIdE stoo i Sal sar TOS NIdE 2722578 as Cea usas 3 al GO T GER Sdr adun NAT TOS M AE MANI 9O ONO IUNOLLdAO f Qe vam zOvQudf ms ES t ST rn T TO NIG UNO Bar E Tal HM ane BIL ano Jder os nes v2 ENEE 28278 ING z mt 9 oke qe ur ar 100 dug T IL a No BH ezi 25 Sou ONE ING TS LMT T108 INg 6 6v a ow x ING z FE D A El mg sou ala Y a sta 3842 ING ING 7 4 UNO ECH bk ddoT EE E 3 z lt a ef gic 223F m 12 WORT NIS 9 A T a S me wo D EE ju 9 aL va ata 3 i 3 lt eer E y la di o zwa7sdr
16. d goa mem ed la Oar ors gg 52070105 SOWO E ana ant a ae 57 Tq 82071108 Wi em E 199 895 e woe aen ZA i sl SSES qaos Z ad ECT anu am gt xar ET ee E ero E oe e TEEN sg HE 5 s S SEI S g Boch f Ber issP2c dao E ma 27742830365 ATE Cu ana ERRE REE RSS d TO INNI DNAS E m P Tas Qro Er mmm s gt Slo 2 ETE 28 lt s amp T8 T ux re fee es 4 eem mea d i 9 98 Z0T MSL An T ano Ka a6 3 waa an E 2d T 1 K Geen Am o mo me n anro Lao or er ee pin seu eu a 5 5 80 ZaT nSL a us san 71 D I val E sre zovom me ano Qe e osu co ING ING aT at eeu Sca dab H LR ad Gel S0 00 221 msi a i 2 soc me 1 N3 7s n1 ata Figure 16 DUT and Related Circuits Rev 0 Page 12 of 28 UG 074 4410 66980 1 9 80 E0T MSL vd ING o Z EST dT OJIJ an9 o DNB Teu 880 0113 ADT XS9d9TZML2N Aen Z UNO ING yA cut D Qi 125059310319 EI TRI T 320 H S sn YAT 2H X198 0313 zn INT 0 EE ING 2 A 84 2 UNO deen 005453310313 Gans HOOT ssa dh E 021 Wo ne ERR ADD T T9 of A 8 qc UND UNS UND 2 9 S Se z HOT ING E me EES E 1 105953370314 Z ORIS 09 T IGL Gul vay T L
17. e shorting jumpers on P4 This disconnects the CSB SCLK DFS and SDIO DCS pins from the SPI control bus and connects CSB to SVDD allowing the DUT to operate in non SPI mode In this mode the SCLK DFS and SDIO DCS pins take on their alternate functions to select the data format and enable disable the DCS With the SDIO DCS jumper removed DCS is disabled to enable DCS add a shorting jumper on P4 between Pin 2 and Pin 3 With the SCLK DFS jumper removed the data format is set to offset binary To set the data format to twos complement a jumper should be added on P4 between Pin 5 and Pin 6 Switching Power Supply Optionally the ADC on the board can be configured to use the ADP2108 dual switching power supply to provide power to the DRVDD and AVDD rails of the ADC To configure the board to operate from the ADP2108 the following changes must be incorporated see the Evaluation Board Schematics and Artwork and Bill of Materials sections for specific recommendations for part values 1 Install L2 and L3 2 Install C77 C79 C80 and C81 3 Install E2 E3 and E11 4 Remove P31 and E5 Making these changes enables the switching converter to power the ADC Using the switching converter as the ADC power source is more efficient than using the default LDOs Rev 0 Page 6 of 28 EVALUATION BOARD SOFTWARE QUICK START PROCEDURES This section provides quick start procedures for using the AD9265 and AD9255 evaluation board Both the
18. e status bar of the VisualAnalog New Canvas window Select the template that corresponds to the type of testing to be performed see Figure 4 where the AD9265 is shown as an example VisualAnalog New Canvas New lara Recent Categories C AD9211 CJ AD9214 Samples Logic AD9244 C AD9245 C3 AD9246 ADIsimADC ADIsi mADC ADISmADC ADisimADC ADS255 Two Tone Average Samples Logic C3 AD9261 C AD9237 gj gj by LF Check for Updates Open AD9265 16 Bit 80 105 125 MSPS device found 08699 004 Figure 4 VisualAnalog New Canvas Window After the template is selected a message appears asking if the default configuration can be used to program the FPGA see Figure 5 Click Yes and the window closes VisualAnalog i VisualAnalog will now attempt to program the on board FPGA with a default file for the AD9265 Please click Yes to program the FPGA If you prefer to use the current FPGA configuration click No Before clicking Yes please make sure the HSC ADC EVALC is powered with the correct supply and that 15 con to the computer Also make sure the dipswitch U4 on the HSC ADC EVALC is set to the following configuration MO ON M1 OFF M2 OFF If the configuration is successful you will see the DONE light T Do not show this message again 08699 005 Figure 5 VisualAnalog Default Configuration Message To cha
19. e the performance of the ADC when powered by a more efficient regulator INPUT SIGNALS When connecting the clock and analog source use clean signal generators with low phase noise such as the Rohde amp Schwarz SMA100A HP 8644B signal generators or an equivalent Use a 1 m shielded RG 58 50 coaxial cable for connecting to the evaluation board Enter the desired frequency and amplitude see the Specifications section in the data sheet of the respective part When connecting the analog input source use of a multipole narrow band band pass filter with 50 O terminations is recommended Analog Devices Inc uses TTE and K amp L Microwave Inc band pass filters The filters should be connected directly to the evaluation board If an external clock source is used it should also be supplied with a clean signal generator as previously specified Typically most Analog Devices evaluation boards can accept 2 8 V p p or 13 dBm sine wave input for the clock OUTPUT SIGNALS The default setup uses the Analog Devices high speed converter evaluation platform HSC ADC EVALCZ for data capture The CMOS output signals are buffered through U2 and are routed through P2 to the FPGA on the data capture board Rev 0 Page 3 of 28 UG 074 WALL OUTLET 100V ACTO 240V AC 47Hz TO 63Hz SWITCHING POWER SUPPLY SWITCHING POWER SUPPLY SIGNAL SYNTHESIZER ECH i ANALOG INPUT ve L PC RUNNING ADC AN
20. ey Fisher with a low phase noise oscillator installed The oscillator frequency is set to match the rated speed of the part 125 MHz 105 MHz or 80 MHz for the AD9265 AD9255 To enable the oscillator install P6 and to connect it into the clock path add a 0 O resistor at C70 R25 should also be removed to remove the 50 2 termination from the output of the oscillator A differential LVPECL clock driver output can also be used to clock the ADC input using the AD9517 4 U601 To place the AD9517 4 into the clock path populate R28 and R29 with 0 Q resistors and remove R30 and R31 to disconnect the default clock path inputs In addition populate R85A and R86A with 0 Q resistors and remove R85 and R86 to disconnect the default clock path outputs and insert the AD9517 4 OUTO LVPECL The AD9517 4 must be configured through the SPI controller software to set up the PLL and other operation modes Consult the AD9517 4 data sheet for more information about these and other options PDWN To enable the power down feature add a shorting jumper across P7 at Pin 1 and Pin 2 to connect the PDWN pin to DRVDD OEB To disable the outputs using the OEB pin add a shorting jumper across P3 at Pin 1 and Pin 2 to connect the OEB pin to DRVDD 08699 003 Figure 3 Default Analog Input Configuration of the AD9265 AD9255 Rev 0 Page 5 of 28 UG 074 Non SPI Mode For users who want to operate the device under test DUT without using SPI remove th
21. f the support circuitry required to operate the AD9265 or AD9255 in its various modes and configurations The application software used to interface with the devices is also described The AD9265 and AD9255 data sheets provide additional information and should be consulted when using the evaluation board All documents and software tools are available at www analog com fifo For additional information or questions send an email to highspeed converters analog com EVALUATION BOARDS x 0 VIRTEOCA 08699 001 Figure 1 AD9265 and AD9255 Evaluation Board and HSC ADC EVALCZ Data Capture Board Please see the last page for an important warning and disclaimers Rev 0 Page 1 of 28 UG 074 TABLE OF CONTENTS Pd wawa 1 Input Sign lee 3 Equipment Needed eese sunm ee eer 1 Output Signals tinas naa cian 3 Software Needed ii id 1 Default Operation and Jumper Selection Settings 5 Documents Needed ne RUNG 1 Evaluation Board Software Quick Start Procedures 7 General Description ia 1 Configuring the Board sse 7 Evaluation Boards eto pi eire 1 Using the Software for Testing seen 7 Revision History see 2 Evaluation Board Schematics and Artwork 11 Evaluation Board Hardware seen 3 Ordering Information eene 24 Power Supplies eerte heec lette e 3 Bill of Materials cde tee ee ded 24 REVISION HIST
22. guring the inputs and outputs The ADL5562 is normally held in power down mode and can be enabled by adding a jumper on P19 The ADL5562 can also be substituted with the ADA4937 1 or the ADA4938 1 to allow evaluation of these parts with the ADC VREF VREF is set by default to 1 0 V with SENSE connected to AGND through a jumper connecting Pin 2 and Pin 3 on Header P5 This causes the ADC to operate with the internal reference in the 2 0 V p p differential full scale range The reference voltage can be changed to 0 5 V for a 1 0 V p p full scale range by moving the SENSE pin jumper connection on P5 from Pin 2 and Pin 3 to Pin 1 and Pin 2 this connects the SENSE pin to the VREF pin 0 1uF 2V p p Pa eoe o v 330 Y UG 074 To use the programmable reference mode a resistor divider can be set up by installing R50 and R51 The jumper on P5 should be removed for this mode of operation See the data sheet of the part for additional information on using the programmable reference mode RBIAS RBIAS has a default setting of 10 kQ R68 to ground and is used to set the ADC core bias current Note that using a resistor value other than a 10 KQ 1 resistor for RBIAS may degrade the performance of the device Clock Circuitry The AD9265 AD9255 board is set by default to use an external clock generator An external clock source capable of driving a 50 Q terminated input should be connected to J6 This board is shipped from Valp
23. ilcraft 0603CS 36NXGLU 65 P15 P16 P17 P25 Conn PCB header 2 position Samtec TSW 102 08 G S CNSAMTEC1X2H330LD36 66 R4 R12 R94 R95 Resistor precision thick film Panasonic ERJ 3EKF49R9V chip R0603 49 9 Q 67 R17 R18 R19 R93 Resistor precision thick film Panasonic ERJ 2RKF24R9X chip R0402 24 9 Q 68 R20 R21 Resistor precision thick film Panasonic ERJ 2RKF 1001 X chip R0402 1 00 kQ 69 R28 R29 R32 R34 R41 R42 Resistor film SMD 0402 0 Q Panasonic ERJ 2GEOROOX R78 R80 R82 R84 R85A R86A R96 JP1 JP25 70 R44 R45 R638 R639 Resistor precision thick film Panasonic ERJ 2RKF2000X chip R0402 200 O 71 R5 R72 R73 Resistor film SMD 0402 100 Q Venkel CR0402 16W 1000FT 72 R50 R51 Do not install TBD R0402 73 R54 R56 Resistor film SMD 0603 0 Q Multicomp MC0603WG00000T5F TC 74 R633 R651 Resistor precision thick film Panasonic ERJ 2RKF57R6X chip R0402 57 6 Q 75 R76 Resistor precision thick film Panasonic ERJ 2RKF1003X chip R0402 100 kO Rev 0 Page 26 of 28 UG 074 Item No Qty Reference Designator Description Manufacturer Part No 76 T1 XFMR RF MINICD542 Mini Circuits ADT1 1WT 77 T4 T5 T601 XFMR RF 1 1 ETC1 M A COM MABA 007159 000000 78 T6 XFMR RF MINICD542 Mini Circuits ADT1 1WT 79 TP1 TP2 TP3 TP6 TP7 Conn PCB test point black Components Corp TP 104 01 00 TP10 TP11 CNLOOPTP 80 TP4 TP5 TP9 TP19 TP601 Conn PCB test point white Comp
24. necting to the low dropout linear regulators default configuration that supply the proper bias to each of the various sections on the board The evaluation board can be powered in a nondefault condition using external bench power supplies To do this the P27 P28 P31 P30 P32 and P29 jumpers can be removed to disconnect the outputs from the on board LDOs This enables the user to bias each section of the board individually Use P8 and P9 to connect a different supply for each section A 1 8 V supply is needed with a 1 A current capability for AVDD SVDD and DRVDD however it is recommended that separate supplies be used for both analog and digital domains An additional supply is also required to supply 1 8 V for digital support circuitry on the board 3V DIG This should also have a 1 A current capability and can be combined with DRVDD with little or no degradation in performance Two additional supplies V AVDD and 3V AVDD are used to bias the optional input path amplifiers If used these supplies should each have a 1 A current capability P18 is also necessary if an amp that requires a negative supply voltage is being used A second optional power supply configuration allows the replacement of the LDOs that supply the AVDD and DRVDD rails ofthe ADC with the ADP2108 step down dc to dc converter Using this switching controller in place of the LDO regulators to power the AVDD and DRVDD supplies of the ADC allows customers to evaluat
25. nge features to settings other than the default settings click the Expand Display button located on the bottom right corner of the window to see what is shown in Figure 7 Detailed instructions for changing the features and capture settings can be found in the AN 905 Application Note VisualAnalog Converter Evaluation Tool Version 1 0 User Manual After the changes are made to the capture settings click Collapse Display see Figure 7 gt gt VisualAnalog File Edit View Canvas Tools Window Help as Hir e msr Figure 6 VisualAnalog Window Toolbar Collapsed Display 08699 006 Rev 0 Page 7 of 28 UG 074 gt gt VisualAnalog Canvas AD9265 FFT DER Ge File Edit View Canvas Tools Window az W e rose Components x t Board Interfaces a ADC Data Capture DAC Pattem Generator Interface Ze Data Pattem Generator 2 Interface FIFO4x Interface Blackman Hanis DEBUG ONLY 9 Debug Graphics Process sd Filter Process rehin Graph AD9265 FFT EZ Comment B E els E eben gale CIR ejm else el ADC Model J ik Complex Waveform Merger Ti Complex Waveform Splitter E Data Router Z DNL INL Analysis A FFT wee Peak Hold d Power Phase eee 08699 007 Figure 7 VisualAnalog Main Window Setting Up the SPI Controller Software EINE After the ADC data capture board setup is complete set up the pm SPIController software
26. onents Corp TP 104 01 09 TP602 TP603 TP604 TP605 CNLOOPTP 81 Y1 IC clock OSC ACMOS LSTTL Valpey Fisher VFAC3HL 125MHZ compatible 125 MHz XTALCB3LV_H90 1 Do not insert Rev 0 Page 27 of 28 U6 074 NOTES A ESD Caution ESD electrostatic discharge sensitive device Charged devices and circuit boards can discharge without detection Although this product features patented or proprietary protection Alas circuitry damage may occur on devices subjected to high energy ESD Therefore proper ESD precautions should be taken to avoid performance degradation or loss of functionality Legal Terms and Conditions By using the evaluation board discussed herein together with any tools components documentation or support materials the Evaluation Board you are agreeing to be bound by the terms and conditions set forth below Agreement unless you have purchased the Evaluation Board in which case the Analog Devices Standard Terms and Conditions of Sale shall govern Do not use the Evaluation Board until you have read and agreed to the Agreement Your use of the Evaluation Board shall signify your acceptance of the Agreement This Agreement is made by and between you Customer and Analog Devices Inc ADI with its principal place of business at One Technology Way Norwood MA 02062 USA Subject to the terms and conditions of the Agreement ADI hereby grants to Customer a free limited personal temp
27. orary non exclusive non sublicensable non transferable license to use the Evaluation Board FOR EVALUATION PURPOSES ONLY Customer understands and agrees that the Evaluation Board is provided for the sole and exclusive purpose referenced above and agrees not to use the Evaluation Board for any other purpose Furthermore the license granted is expressly made subject to the following additional limitations Customer shall not i rent lease display sell transfer assign sublicense or distribute the Evaluation Board and ii permit any Third Party to access the Evaluation Board As used herein the term Third Party includes any entity other than ADI Customer their employees affiliates and in house consultants The Evaluation Board is NOT sold to Customer all rights not expressly granted herein including ownership of the Evaluation Board are reserved by ADI CONFIDENTIALITY This Agreement and the Evaluation Board shall all be considered the confidential and proprietary information of ADI Customer may not disclose or transfer any portion of the Evaluation Board to any other party for any reason Upon discontinuation of use of the Evaluation Board or termination of this Agreement Customer agrees to promptly return the Evaluation Board to ADI ADDITIONAL RESTRICTIONS Customer may not disassemble decompile or reverse engineer chips on the Evaluation Board Customer shall inform ADI of any occurred damages or any modifications or alterations it makes to
28. se 117 394 BFS 08699 013 AMPLITUDE dBFS Figure 13 Graph Window of VisualAnalog Click the disk icon within the Graph window to save the performance plot data as a csv formatted file See Figure 14 for an example 125MSPS 70 1MHz 1dBFS SNR 76 5dB 77 5dBFS SFDR 88 0dBc THIRD HARMONIC SECOND HARMONIC 08699 014 FREQUENCY MHz Figure 14 Typical FFT AD9265 AD9255 UG 074 Troubleshooting Tips If the FFT plot appears abnormal do the following If you see a normal noise floor when you disconnect the signal generator from the analog input be sure you are not overdriving the ADC Reduce the input level if necessary In VisualAnalog see Figure 7 click the Settings button in the Input Formatter block Check that Number Format is set to the correct encoding offset binary by default Repeat for the other channel If the FFT appears normal but the performance is poor check the following Make sure an appropriate filter is used on the analog input Make sure the signal generators for the clock and the analog input are clean low phase noise Change the analog input frequency slightly if noncoherent sampling is being used Make sure the SPI config file matches the product being evaluated If the FFT window remains blank after clicking Run do the following e Make sure the evaluation board is securely connected to the HSC ADC EVALCZ board e Make sure the FP
29. ssos y o oo 2 a o 2 0 o a O eo oo o oe O oo 53 O a o 0000 O 020 S O 0000 o 990 00 O oo o o o Q 0 Oo OO L E s 0 0 E o 9 9 o o o E 000000 a e o d 000000 j Oo o 888 O o 60 g x o o 000000 A Dee e a 20 g 0000 o o 000000 Oe n 999 oee 2000 LEES 000000 oo 9 oo o9 38000 d oa 000000 o af e 9 Os T x og o 000000 o O o o 0 Bat T 000000 ofo o 9 H 000000 Qe ef o o 000000 Ze Se ooo 0 o o0 O 9 o o o o 000 o O ai P a 5 5 99 000 O ofo o P O O o o 020 p ELO o 9 o e TO S a ESCH o o o K re 7 E Se 0 o 000000 9 0 e a O ca acie Ni 000000 o re OOo id 000000 e 9 M E 000000 020 D SS 000000 De 000000 o o o o 9 000000 ae OG YA g o 000000 o 90 o o 00 000000 8 9 2 g 87 O D 000000 S o o oO Oo 0 0 Oo 8 Figure 27 Ground Plane Layer 5 Rev 0 Page 22 of 28 UG 074 si AR 08699 028 Figure 28 Bottom Side Rev 0 Page 23 of 28 UG 074 ORDERING INFORMATION BILL OF MATERIALS Table 1 AD9265 AD9255 BOM Item No Qty Reference Designator Description Manufacturer Part No 1 1 Not applicable Printed circuit board 2 3 C2 C4 C15 Ceramic capacitor multilayer Phycomp Yageo CC0402J RNPO9BN100 NPO 0402 10 pF 3 46 C3 C5 C8 C10 C11 C12 Ceramic capacitor 0402 0 1 uF Panasonic ECJ OEX1C104K C14 C16 C18 C22 C23 C27 C29 C31 C32 C33 C34 C38 C40 C42 C43 C45 C46 C47 C48 C60 C61 C66 C71 C78 C96 C601 C602 C608 C6
30. the Evaluation Board including but not limited to soldering or any other activity that affects the material content of the Evaluation Board Modifications to the Evaluation Board must comply with applicable law including but not limited to the RoHS Directive TERMINATION ADI may terminate this Agreement at any time upon giving written notice to Customer Customer agrees to return to ADI the Evaluation Board at that time LIMITATION OF LIABILITY THE EVALUATION BOARD PROVIDED HEREUNDER IS PROVIDED AS IS AND ADI MAKES NO WARRANTIES OR REPRESENTATIONS OF ANY KIND WITH RESPECT TO IT ADI SPECIFICALLY DISCLAIMS ANY REPRESENTATIONS ENDORSEMENTS GUARANTEES OR WARRANTIES EXPRESS OR IMPLIED RELATED TO THE EVALUATION BOARD INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTY OF MERCHANTABILITY TITLE FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT OF INTELLECTUAL PROPERTY RIGHTS IN NO EVENT WILL ADI AND ITS LICENSORS BE LIABLE FOR ANY INCIDENTAL SPECIAL INDIRECT OR CONSEQUENTIAL DAMAGES RESULTING FROM CUSTOMER S POSSESSION OR USE OF THE EVALUATION BOARD INCLUDING BUT NOT LIMITED TO LOST PROFITS DELAY COSTS LABOR COSTS OR LOSS OF GOODWILL ADI S TOTAL LIABILITY FROM ANY AND ALL CAUSES SHALL BE LIMITED TO THE AMOUNT OF ONE HUNDRED US DOLLARS 100 00 EXPORT Customer agrees that it will not directly or indirectly export the Evaluation Board to another country and that it will comply with all applicable United States federal laws and regulations relating to
31. tor precision thick film Panasonic ERJ 3EKF49R9V chip R0603 49 9 Q 34 2 R49 R71 Resistor precision thick film Panasonic ERJ 2RKF22ROX chip R0402 22 Q 35 2 R55 R67 Resistor precision thick film Panasonic ERJ 3EKF2490V chip R0603 249 O 36 1 R610 Resistor precision thick film Panasonic ERJ 2RKF4121X chip R0402 4 12 KQ 37 1 R611 Resistor precision thick film Panasonic ERJ 2RKF5111X chip R0402 5 11 kO 38 4 R614 R616 R625 R630 Resistor precision thick film Panasonic ERJ 2RKF2000X chip R0402 200 Q 39 2 R626 R640 Resistor film SMD 0402 100 O Venkel CR0402 16W 1000FPT 40 3 R64 R65 R66 Resistor precision thick film Panasonic ERJ 2RKF 1003X chip R0402 100 kO 41 9 R7 R61 R62 R63 R604 Resistor precision thick film Panasonic ERJ 2RKF 1001X R605 R606 R607 R609 chip R0402 1 00 kO 42 1 R74 Resistor precision thick film Panasonic ERJ 2RKF 1473X chip R0402 147 kO 43 1 R75 Resistor precision thick film Panasonic ERJ 2RKF2802X chip RO402 28 kO 44 4 RN4 RN5 RN9 RN10 Resistor network 8 pin 4 CTS 742C083220JCT resistor surface mount RESNET742 4 22 Q 45 3 T2 T3 T9 XFMR RF 1 1 ETC1 M A COM MABA 007159 000000 46 1 U1 IC 2 6 GHz ultralow distortion Analog Devices ADL5562 PRELIM differential IF RF amplifier QFN16 3X3 PAD 5X1 5 47 1 U2 IC TTL low volt 20 bit buffer Fairchild 74VCX162827MTDX TSSOP56 48 1 U3 IC TinyLogic UHS dual buffer Fairchild NC7WZ07P6X SC70 49 1 U4 IC low dropout CMOS lin reg
32. using the following procedure e 1 Open the SPIController software by going to the Start menu meen or by double clicking the SPIController software desktop GE icon If prompted for a configuration file select the appropriate Si L en E one If not check the title bar of the window to determine 8 which configuration is loaded If necessary choose Cfg Figure 9 SPIController New DUT Button Open from the File menu and select the appropriate file 3 Inthe ADCBase 0 tab of the SPIController window find the based on your part type Note that the CHIP ID 1 field CLOCK DIVIDE B box see Figure 10 If using the clock should be filled to indicate whether the correct divider use the drop down box to select the correct clock SPIController configuration file is loaded see Figure 8 divide ratio if necessary See the appropriate part data sheet the AN 878 Application Note High Speed ADC SPI Control Software and the AN 877 Application Note Interfacing to High Speed ADCS via SPI for additional information Pe Cr meo RL gus ata ic CHRON CCI ASB re 08699 008 Figure 8 SPIController CHIP ID 1 Box 2 Click the New DUT button in the SPIController window see Figure 9 08699 010 S 120749 ru Figure 10 SPIController CLOCK DIVIDE B Box Rev 0 Page 8 of 28 4 Note that other settings can be changed on the ADCBase 0 tab see Figure 10 See the appropriate part data sheet the
33. w Sie ment re P acd sa je 4 emer en HS 5 E SSC t du 3b n t ION I Ged di ves W ER A a el A gee g us eso zinaa 4 ner aK 525 d nY xw ft one r xE CS gam ale Ed Eat roi D I a SEE pe eine NE pene E En 4 Lae Emma tan en SLAM OL 350712 394978 pe VW A PK aves ano BA a 9 80 20T MSL E 4 2 LE ESTE EEN En Bod 123NMO3 a E Jr serene were EECH E seat ager ues ves er E EE s SCH 2j CE 3 mme ei Ze mea 1 C varr que pl 6d 469 bnza EN T 23 esa TES SZ BE S en LH ZUeIBSU Ten anar L A SYHOLYTNDSY ATddNs lt NOILdO SN digo UND HO NS SSn dWg von t d ng ns T 2 dig NE E Omg ne 1 E 44NZ SOLD IdS ne RT OL tt DION a dvoga jo 1S3 D vin ech ae A S20 TES SZ TO 2TBXNE Be cle LE 1 AO En m EE NE E OL tt aans NG3HO UHLGOGGEINT I Suo n ew Z 8 T Oe z e SE Z 8 T dog ru Sea SO9coug lfldNI Adans sod Figure 15 Board Power Input and Supply Circuits Rev 0 Page 11 of 28 UG 074 910 66980 S 5 88 EDI MSL D i S 5 80 201 m5L 180 ata ano s n e H Ehe S s s G D Tu ur T en THO AON ka a mg SUIZOS k P BB fo fs ao la fs o n Luya wos s ier dic OL HS 0919 ow se ar any d EE EE RAA DSK PITTI F GHESseavaase 5 9 80 ZaT MSL ano 8 8 ENR H CO anra L Su ss E Ev us za wo a Sd ow ea le e ET oo
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