XSA Board V1.0 XSA Board V1.0 User Manual User Manual
Contents
1. lt O e gt x 2 9 Ld 2 6 4 5 6 7 8 9 10 e 5V A 90 YW S2 1 5g 83 S4 O O O O 55 s 1552 DP 9 62 CNCcOST 10 z233 E ED Eb EL OOOO XSA BOARD V1 0 USER MANUAL 23 Seven Segment LED The XSA Board has a 7 segment LED digit for use by the FPGA or the CPLD The segments of this LED are active high meaning that a segment will glow when a logic high is applied to it The LED shares the same pins as the eight bits of the Flash RAM data bus Four Position DIP Switch The XSV Board has a bank of four DIP switches accessible from the CPLD and FPGA When closed or ON each switch pulls the connected pin of the FPGA and CPLD to ground Otherwise the pin is pulled high through a resistor when the switch is open or OFF When not being used the DIP switches should be left in the open or OFF configuration so the pins of the FPGA and CPLD are not tied to ground and can freely move between logic low and high levels The DIP switches also share the same pins as the uppermost four bits of the Flash RAM address bus If the Flash RAM is programmed with several FPGA bitstreams then the DIP switches can be used to select a particular bitstreams which will be loaded in2. HEX 41 14 Storing Non Volatile Designs in Your XSA Board The Spartan II FPGA on the XSA Board stores its configuration in an on chip SRAM which is erased whenever power is removed Once your design is finished you may want to store the bitstream in the 256 KByte Flash device on the XSA Board which configures the FPGA for operation as soon as power is applied Before downloading to the Flash the FPGA BIT file must be converted into a EXO or MCS format using one of the following commands promgen u 0 file bit s 256 promgen u 0 file bit mcs s 256 In the commands shown above the bitstream in the file bit file is transformed into an EXO or MCS file format starting at address zero and proceeding upward until an upper limit of 256 KBytes is reached Before attempting to program the Flash you must place all four DIP switches into the OFF position After the EXO or MCS file is generated it is loaded into the Flash device by dragging it into the area and clicking on the Load button This activates the following sequence of steps 1 The entire Flash device is erased 2 The CPLD on the XSA Board is reprogrammed to create an interface between the Flash device and the PC parallel port This interface is stored in the fintf100 svf bitstream file located within the XSTOOLS XSA folder 3 The contents of the EXO or MCS file are downloaded into the Flash t
3. VGA SYCC 3 VO jPushbutonRESET 62 FLASHA3 50 2 RRLED SA 0 63 2 51 JRLED S2 64 FLASHA 56 RLED SS 350 19 469 PPSZDATA 8 15 5 68 2 15 SPARTANTD 15 Xchecker TDI 4 1 SPARTANTDO 250 2237 16 773 20038 18 SPARTANDOUTBSY 5 39 2 FLASH DODIND0LED SI 71 JXcheckerDIN 1 0 57 9 51 41 11 FLASH CE 6 JRAMCE 42 57 FLASH A10 5 _ RLED SS 43 12 5 6 RMO 4 4 FLASH DILEDDP 40 BARLED2 46 5 FLASH D2 LED S4 39 RAMD2 BARLEDG 477 43 7 59 8 RRLED SO 48 44 9 1 460 14 56 49 6 FLASH D3 LED S6 5 4 50 45 FLASH A8 78 51 46 FLASHAIS 7 79 4 LED S4 54 47 82 5 5 5 48 FLASH AI7DIPSWID 83 6 LLED S 57 7 FLASH D amp 4LED S5 35 04 5 58 49 FLASHWE 7 _ 62 RAMWE 59 50 FLASH RESET 66
4. CS and WR of the FPGA that control the loading of a bitstream CPLD uses the input of the FPGA to select either the slave serial or master select configuration mode M1 and M2 are already hard wired to VCC and GND respectively The CPLD can monitor the status of the bitstream download through the INIT DONE and BSY DOUT pins of the FPGA The CPLD also has access to the FPGA JTAG pins TCK TMS TDI TDO The TMS TDI and pins share the connections with the BSY DOUT CS WR pins With these connections the CPLD can be programmed with an interface that allows configuration of the Spartan Il FPGA through the Xilinx JTAG Programmer software utility Jumper J9 allows the connection of status pin S7 to the general purpose CPLD pin that also drives status pin S5 This is needed to implement the parallel port interface required by the JTAG Programmer software FLASH RAM EO XC9572XL Spartan ll FPGA Parallel Port D7 DO 2 PPDO 3 PPD1 gt o gt 4 PPD2 5 IPROGRAM 6 PPD4 INIT 7 PPD5 M0 8 PPD6 M1 9 PPD7 M2 17 PPC3 TDI zs 16 2 TMS 14 gt BSY DOUT 11 PPS7 lt o lt IDO DONE 12 5 4 5 13 54 4 TMS 15 PPS3 4 w TDI Kas TDO nre pepe 10 PPS6 4 XSA BOARD V1 0 USER MANUAL
5. After setting the board type and parallel port you can download SVF files to the Spartan II FPGA or XC9572XL CPLD on your XSA Board simply by dragging them to the FPGA CPLD area of the GXSLOAD window as shown below XSA BOARD V1 0 USER MANUAL 12 X gxsload Once you release the left mouse button and drop the file the highlighted file name appears in the FPGA CPLD area and the Load button in the GXSLOAD window is enabled Clicking on the Load button will begin sending the highlighted file to the XSA Board through the parallel port connection BIT files contain configuration bitstreams that are loaded into the FPGA while SVF files will go to the CPLD GXSLOAD will reject any non downloadable files ones with a suffix other than BIT During the downloading process GXSLOAD will display the name of the file and the progress of the current download gxsload 100 bit You can drag amp drop multiple files into the FPGA CPLD area Clicking your mouse filename will highlight the name and select it for downloading Only one file at a time can be selected for downloading XSA BOARD V1 0 USER MANUAL 13 gxsload ram100 bit dwnld ar lt Double clicking the highlighted file will deselect it so file will downloaded Doing this disables the Load button XSA BOARD V1 0 USER MANUAL gxsload 5 100 21
6. 00 Port eri Exit Next you select the parallel port that your XS Board is connected to from the Port pulldown list GXSTEST starts with parallel port LPT1 as the default but you can also select LPT2 or LPT3 depending upon the configuration of your PC After selecting the parallel port you select the type of XS Board you are testing from the associated pulldown list Then click on the TEST button to start the testing procedure GXSTEST will configure the FPGA to perform a test procedure on your XSA Board After several seconds you will see a O displayed on the LED digit if the test completes successfully Otherwise an E will be displayed if the test fails A status window will also appear on your PC screen informing you of the success or failure of the test If your XS Board fails the test you will be shown a checklist of common causes for failure If none of these causes applies to your situation then test the board using another In our experience 99 9 of all problems are due to the parallel port If you cannot get your board to pass the test even after taking these steps then contact XESS Corp for further assistance As a result of testing the XSA Board the CPLD is programmed with the standard parallel port interface found in the dwnldpar svf bitstream file located within the XSTOOLS XSA folder This is the standard interface that should be loaded into the CPLD when you want to use it with the GXSLOAD utility
7. 4 BUS056 56 112 xcBusi2 4 1 CBUS088 88 CCLKO XCR 4 50 BUSOIR VREF6_1 T6 Lg Paves B 39 120 XxCBUS12n 4 B 44 DIN DO i21 XCBUS121 4 B 46 0 122 XCRUSI22 4 48 02 VREF6 3 355 Y CBUSI23 B 57 03 124 XxCBUS124 B 80 24 126 xCBUS126 4 RBF 4 7K B 62 129 12 4 6 57 06 130 1 0 A B 38 151 xcrusi3i 4 B Ta DOUT 132 xCBuS132 4 ST WRITE VREF7 1 33 Xcausisi 5068 68 105 34 xcBusis4 R8G 47 B XCRUSO 72 DONE 136 XCRUS136 4 37 PROGRAM VREF7_2 Hyg CCLK VREF7 199 XCBUS139 4 7 10 XCRUS109 109 uo M40 4 B XCBUS111 LE i141 xcBusi4t 4 RSH 4 7 BUS106 XCRUS106 106 M2 XCBUSOO 2 XCBUS142 142 XCBUSD 92 TDI nco 403 TDO 2222222222222222 WRITE C C C O CO CO CO CO C C ba os ae EX a Rcx 55 BUSY DOUT 3 5 2 5 COMPANY XESS Corporation TITLE XSA Board Spartan FPGA RELEASED XCBUS 001 144 0 01uF xsal_0 sch 2 Tue Sep 11 15 53 21 2001 N D5 XCBUSO60 8 5 K xcRus043 12 o TCK Kk xcRuson2 06 06 D7 XCBUS06 CE XCBUS04 CS TDI BUSO BSY BUSO CC
8. The XSA Board contains the following components 25100 Spartan II FPGA This is the main repository of programmable logic on the XSA Board XC9572XL CPLD This CPLD manages the interfaces between the PC parallel port and the rest of the XSA Board Osc A programmable oscillator generates the master clock for the XSA Board Flash A 256 KByte Flash device provides non volatile storage for data and configuration bitstreams SDRAM A 16 MByte SDRAM provides volatile storage for data accessible by the FPGA LED A seven segment LED allows visible feedback as the XSA Board operates DIP switch A four position DIP switch passes settings to the XSA Board or controls the upper address bits of the Flash device Pushbutton A single pushbutton sends momentary contact information to the FPGA Parallel Port This is the main interface for passing configuration bitstreams and data to and from the XSA Board PS 2 Port A keyboard or mouse can interface to the XSA Board through this port VGA Port The XSA Board can send signals to display graphics on a VGA monitor through this port Prototyping Header Many of the FPGA I O pins are connected to the 84 pins on the bottom of the XSA Board that are meant to mate with solderless breadboards XSA BOARD V1 0 USER MANUAL 19 Parallel Port XC9572XL XC2S100 015 00 D7 D0 BA1
9. 2608 Sweetgum Drive Apex NC 27502 Toll free 800 549 9377 International 919 387 0076 orporation FAX 919 387 1302 XSA Board V1 0 User Manual How to install test and use your new XSA Board RELEASE DATE 9 14 2001 Copyright 2001 by X Engineering Software Systems Corporation All XS prefix product designations are trademarks of XESS Corp All XC prefix product designations are trademarks Xilinx All rights reserved No part of this publication may be reproduced stored in a retrieval system or transmitted in any form or by any means electronic mechanical photocopying recording or otherwise without the prior written permission of the publisher Printed in the United States of America XSA BOARD V1 0 USER MANUAL 1 Table of Contents Table of Contents Preliminaries XSA BOARD V1 0 USER MANUAL 2 XSA BOARD V1 0 USER MANUAL Preliminaries Getting Help Here are some places to get help if you encounter problems If you can t get the XSA Board hardware to work send an e mail message describing our problem to help xess com or submit a problem report at http www xess com reqhelp html Our web site also has m answers to frequently asked questions m example designs for the XS Boards m to sign up for our email forum Where you can post questions to other XS Board users If you can t get your Xilinx WebPACK software tools installed properly send an e mail
10. 4A4AAA 9 4 XCBUSO93 PS2 DATA 680 D2 S4 XCBUS046 6 SW PUSH NO Sw2 43 13 03 56 XCBUS049 5AA 2 D4 S5 XCBUS057 PA D5 S3 XCBUS060 3 14 D6 S2 XCBUS062 07 50 XCBUS067 10 00 51 XCBUS039 BAAAS D1 DP XCBUSO44 7 10 XCBUS 001 1441 COMPANY XESS Corporation mE XSA Board PS 2 Port VGA Port LED DRAWN DATED REV V1 0 RELEASED DATED SHEET OF xsal_0 sch 6 Tue Sep 11 15 53 22 2001 PP CO 41 64 PROG OSC 0 01uF 0 01uF ls 14 XSA Board Programmable Oscillator xsal_0 sch 7 Tue Sep 11 15 53 22 2001 PWRPLUG 95 5 SWITCH 1N4148 1N4148 COMPANY XESS Corporation XSA Board Regulated Power Supplies xsal_0 sch 8 Tue 11 15 53 23 2001 U9C U9D 5 o6 9 0 741514 741514 w U9B 5 gt gt PP C1 gp 741514 48 2 gt gt PP D0 98 15 gt 53 U9A U9E 1 1 p gt gt PP D1 J8 16 D gt 741514 741514 48 4 D PP C2 48 17 gt PP D2 J8 5 D gt PP C3 J8 18 D gt mi gt PP D3 48 6 gt PP D4 48 7 D gt PP D5 EB J8 8 D gt PP D6 48 9 D PP D7 PETS J8 10 5 Hx XCBUSO78 98 23 gt U9F NO 12 13 48 11 5 O 57 48 24 9 EN 74LS14 ii d O PP S4 48 15 gt 48 27
11. XSA BOARD V1 0 USER MANUAL 20 control of the parallel port The divisor is stored in EEPROM in the DS1075 so it will be restored whenever power is applied to the XSA Board The shunt on jumper J6 must be across pins 2 and 3 to make the oscillator output a clock signal upon power up The clock signal enters a dedicated clock input of the CPLD Then the CPLD can output a clock signal to a dedicated clock input of the FPGA To get a precise frequency value or to sync the XSA circuitry with an external system you can insert an external clock signal through pin 64 of the prototyping header This external clock replaces the internal 100 MHz clock source in the DS1075 oscillator You must use the GXSSETCLK software utility to enable the external clock input of the DS1075 Clock signals can also be directly applied to two of the dedicated clock inputs of the FPGA through the pins of the prototyping header 5V PP CO J6 47 22 1 51075 lt Pin 64 42 17 3 Spartan ll XC9572XL 100 MHz FPGA CPLD red OS XSA BOARD V1 0 USER MANUAL 21 16 MByte Synchronous DRAM A ith 16 MBytes of storage 8M x 16 is connected to the FPGA as shown below Note that the clock signal to the SDRAM is also re routed back to a dedicated clock input of the FPGA This makes it easy to synchronize the internal operations of the FPGA with the SDRAM operations ss ss ss s
12. gt 2 I R13 2 J8 26 D C30 COMPANY XESS Corporation XSA Board Parallel Port Interface RELEASED DATED SHEET xsal_0 sch 9 Tue 11 15 53 23 2001 XCBUS002 XCBUS063 XCBUS012 i s16 XCBUS064 21 41 84 5013 L J 41 27 5065 L 1 3 XCBUSO15 1 41 28 5066 0 4 XCBUSO18 H 1 5 XCBUS067 1 4 5 XCBUSO19 s 5068 21 41 10 5020 H J1 29 XCBUS069 H si XCBUS021 1 41 32 XCBUSO72 H 41 55 5022 XCBUS074 H 53 XCBUS023 1 41 34 XCBUSO75 L J 4 79 XCBUS026 XCBUS076 1 41 77 XCBUS027 L J 1 37 XCBUS077 1 41 6 XCBUS028 L J 1 50 XCBUS078 O s 9 XCBUS029 1 01 51 XCBUSO79 1 41 67 5030 1 41 56 XCBUS080 L 7 XCBUSO31 1 21 69 XCBUSOB3 O XCBUS032 L J 1 68 XCBUS084 XCBUS034 1 01 15 XCBUS085 L 01 19 XCBUS037 E 41 59 5086 XCBUS038 H eds 5087 1 41 25 5039 E i45 XCBUSO88 1 41 24 XCBUS040 HO s 71 XCBUS093 L J 41 38 XCBUS041 1 41 57 5094 L J 41 25 5042 1 41 65 XCBUS106 1 41 26 XCBUS043 L J J1 58 XCBUS109 1 J 7 XCBUS044 1 01 61 XCBUS111 XCBUS046 1 Ji 40 XCBUS142 1 J 21 XEBUS047 91 39 91 17 XCBUS048 E 4599 05049 91 60 i XCBUS050 O 11 38 Ji 42 XCB SSET 41 78 4 01 43 XCBUSGER 01 79 i 44 NEBUSUSE O 11 82 i 1 46 XCHISUET O 1 83 5 47 XEHUSHER O 11 35 il 21 48 91 62 Ji 49 SEEUSORO J1 66 A Ji 63 XCBUSD62 41 80 OO 72 Ji 8
13. 26 XSA Pin Connections The following tables list the pin numbers of the Spartan Il FPGA the XC9572XL CPLD along with the pins of the other chips that they connect to on the XSA Board The columns of the table are arranged as follows Column 1 lists the Spartan Il FPGA pin It is left blank if there is no connection to the FPGA for this function Column 2 lists the XC9572XL CPLD pin It is left blank if there is no connection to the CPLD for this function Column 3 lists the pins of other devices on the XSA Board that are connected to the associated FPGA and or CPLD port Column 4 lists the pin of the XSA prototyping header that is connected to the associated FPGA and or CPLD pin Columns 5 7 list the pins of devices on the Xstend Board that will connect to the FPGA and or CPLD when the XSA Board is inserted into an Xstend Board XSA BOARD V1 0 USER MANUAL 27 FPGA CPLD XSA Function Proto Pin XSTendFuncions 221 54 14 2 2 18 12 SDRAMAT SDRAMERT L JSDRAMAG 6 SDBRAMA2 8 EM 22010 5 11 J SDRAMAA 4 aan n BERNER 3 ee VGAGRENO 29 jJVGAGREEN 32 __ VGABLUO J 33 J 34 96
14. XSA BOARD V1 0 USER MANUAL 10 Programming the XSA Board Clock Oscillator The XSA Board has 100 MHz programmable oscillator a Dallas Semiconductor DS1075Z 100 100 MHz master frequency can be divided by factors of 1 2 up to 2052 to get clock frequencies of 100 MHz 50 MHz down to 48 7 KHz respectively The divided frequency is sent to the FPGA as a clock signal The divisor is stored in non volatile memory in the oscillator chip so it will resume operation at its programmed frequency whenever power is applied to the XS Board You can store a particular divisor into the oscillator chip by using the GUl based GXSSETCLK as follows You start GXSSETCLK by clicking on the icon placed on the desktop during the XSTOOLS installation This brings up the screen shown below Board Type SET Port 21 Exit Divisor External Clock E Your next step is to select the parallel port that your XSA Board is connected to from the Port pulldown list GXSSETCLK starts with parallel port LPT1 as the default but you can also select LPT2 or LPT3 depending upon the configuration of your PC After selecting the parallel port you select from the pulldown list the type of XS Board you have connected to the PC parallel port Next you must enter a divisor between 1 and 2052 into the Divisor text box Once it is programmed the oscillator will output a clock signal generated by dividing its 100 MHz master frequency
15. by the divisor The divisor is stored in non volatile storage in the oscillator chip so you only need to use GXSSETCLK when you want to change the frequency An external clock signal can be substituted for the internal master frequency of the programmable oscillator Checking the external clock checkbox will enable this feature in the programmable oscillator chip If the external clock option is selected you are then responsible for providing the external clock to the XSA Board through pin 64 XSA BOARD V1 0 USER MANUAL 11 Programming This section will show you how to download a logic designs into the FPGA and CPLD of your XSA Board and how to download and upload data to and from the SDRAM and Flash devices on the board Downloading Designs into the FPGA and CPLD of Your XSA Board During the development and testing phases you will usually connect the XSA Board to the parallel port of a PC and download your circuit each time you make changes to it You can download Spartan II FPGA design into your XSA Board using the GXSLOAD utility as follows You start GXSLOAD by clicking on the icon placed on the desktop during the XSTOOLS installation Then select the type of XS Board you are using and the parallel port to which it is connected as shown below gxsload x Board Type 5 00 Load Port FPGA CPLD Flash EEPROM 11 High Address Low Address Upload Format
16. the FPGA with the contents of the Flash device upon power up XSTOOLS XSA dwnidpar svf Drag amp drop this file into the FPGA CPLD area and click on the Load button to put the XSA in a mode where it will configure the FPGA through the parallel port Downloading and Uploading Data to the SDRAM in Your XSA Board The XSA Board contains a 16 MByte synchronous DRAM SDRAM whose contents can be downloaded and uploaded by GXSLOAD This is useful for initializing the SDRAM with data for use by the FPGA and then reading the SDRAM contents after the FPGA has operated upon it The SDRAM is loaded with data by dragging amp dropping one or more EXO MCS HEX and or XES files into the RAM area of the GXSLOAD window and then clicking on the Load button This activates the following sequence of steps 1 The FPGA on the XSA Board is reprogrammed to create an interface between the RAM device and the PC parallel port This interface is stored in the ram100 bit bitstream file located within the XSTOOLS XSA folder CPLD must have previously been loaded with the dwnldpar svf file found in the same folder 2 The contents of the EXO MCS HEX or XES files are downloaded into the SDRAM through the parallel port The data in the files will overwrite each other if their address ranges overlap 3 If any file is highlighted in the FPGA CPLD area then this bitstream is loaded into the FPGA or CPLD on the XSA Board Otherwise t
17. three ways distinguished by the method you use to apply power to the board Using wall mount power supply You can use your XSA Board all by itself to experiment with logic designs Just place the XSA Board on a non conducting surface as shown in Figure 1 apply power to jack J5 of the XSA Board from a 9V DC wall mount power supply with a 2 1 mm female center positive plug See Figure 2 for the location of jack J5 on your XSA Board The on board voltage regulation circuitry will create the voltages required by the rest of the XSA Board circuitry Be careful The voltage regulators on the XSA Board will become hot Attach a heat sink to them if necessary Powering Through the PS 2 Connector You can use your XSA Board with a laptop PC by connecting a PS 2 male to male cable from the PS 2 port of the laptop to the J4 connector You must also have a shunt across pins 1 and 2 of jumper J7 The on board voltage regulation circuitry will create the voltages required by the rest of the XSA Board circuitry Many PS 2 ports cannot supply more than 0 5A so large fast FPGA designs may not work when using this power source Solderless Protoboard Installation The two rows of pins from your XSA Board can be plugged into a solderless protoboard with holes spaced at 0 1 intervals One of the A C E protoboards from 3M is a good XSA BOARD V1 0 USER MANUAL 6 choice Once plugged in many of the pins of the FPGA are accessible to ot
18. 1 i Ji 74 i Ji 75 i Ji 76 XCBUS 001 144 COMPANY XESS Corporation XSA Board Prototyping Header RELEASED
19. 6 12 20 5 5 x 9 SDRAMOIB T T soana SDRAMQa 12 SDRAMOB T 7 19 omamo T 06 SPARTANM2 12 yo x 10 36 SPARTANMO 14 1 ai SPARTANM T m onno SDRAMQM T 14 SRAMQH j T 115 SDRAMQ T T O o yO SDRAMQg T sonno 12 SDRAMQML 1 123 SDRAMWE 1 SyS iM SDRAMQMH 1200 SDRAWOCAS T SDRAMCGK O 1 yO SDRAWRAS 181 SDRAMCKE 1 132 SDRAWOS 1 7183 SDRAMAi2 1 194 SDRAMBAQ0 1 x 186 SDRAMAM T 137 SDRAMBAI 1 188 SDRAMAS T 5 x 10 SDRAMAB 1 14 _ T 777142777 18 SPARTANTMS O 17 Xehecker TMS 80 PARPORFGLCPLD ICK _ T x 29 PARPORTOZCPLDMS I 28 PARPORTOSCPLD IDI T PARORTDO T PARPORTD T PAR
20. BA0 A12 A0 RAS CAS CS WE nse PROGRAM INIT 2 ICS WR BSY DOUT 1 DONE TCK RED1 RED0 25 REENT GREENI us TDO BLUE BLUE0 GCLK VSYNC 10 PPS6 4 e Figure 3 XSA Board programmer s model VGA Connector Programmable logic XC2S100 Spartan II FPGA and XC9572XL CPLD The XSA Board contains two programmable logic chips m 100 Kgate Xilinx 25100 a 144 pin QFP package The FPGA is the main repository of programmable logic on the XSA Board m AX ilinx 9572 CPLDIthat is used to manage the configuration of the FPGA via the parallel port The CPLD also controls the programming of the Flash RAM on the XSA Board 100 MHz Programmable Oscillator A Dallas 051075 programmable oscillator provides a clock signal to both the FPGA and the CPLD The DS1075 has a maximum frequency of 100 MHz that is divided to provide frequencies of 100 MHz 50 MHz 33 3 MHz 25 MHz 48 7 KHz The clock signal is connected to a dedicated clock input of the CPLD The CPLD passes the clock signal on to the FPGA This allows the CPLD to control the clock source for the FPGA To set the divisor value the DS1075 must be placed in its programming mode This is done by pulling the clock output to 5V on power up with a shunt across pins 1 and 2 of jumper J6 Then programming commands to set the divisor can be sent to the DS1075
21. DIPSW7 60 8 FLASH D5 LED S3 80 06 BARLD7 602 9 FLASH D6 LED S2 81 05 BARLD6 63 51 FLASH A16 DIPSWIC 84 644 52 FLASH A15 DIPSW1B_ 3 LLED S0 65 56 J FLASRAI2 4 RAMAI 6 58 FLASRA7 7 5 62 67 10 FLASH D7 LED SO 10 RAMD7 BARLEDG8 0 2 68 38 41 jRAMDO 69 39 55 Pushbutton PROGRAM Xchecker PROG 72 40 5 74 61 FLASH A4 70 CODECSDNN 75 60 FLASH A5 77 CODECSCLK 2 TASA 6 2217 9 78 56 6 7 9 ZJ 7 DIPSW1 19 FPGA CPLD XSA Function Proto Pin XSTend Functions a DISW2 XcheckerRST 18 011010 1 0 5 2 pe amp RE 2 8 is MASTER CLK XcheckerCLK 000 j PS2 DATAPUSHBUTTON 25 VGABLUEO J 2
22. L BUSO WRITE TDO XCB 19 U2 As raison s XC9572XL vQ64 M A7 XCBUSORS A6 Kk xcRus076 A4 Kk xcRus074 A3 Kk xcRus027 A2 Kk xcRusn2R A1 xcausn20 0 Kk xcRusn4n DO Kk xcRusnig j 01 Kk xcRus044 D2 03 K xcRusn4o D4 xcRus057 C17 C18 C19 0 01uF 0 01uF 0 01uF COMPANY XESS Corporation XSA Board CPLD Interface RELEASED DATED SHEET OF PROGRAM DONE XCBUS 001 144 C20 0 01uF xsal_0 sch 3 11 15 53 21 2001 AT49F002 01 4O 01 4 C42 XCBUS054 XCB 4 XCBUS063 Kk O XCBUS056 Kk xcausns amp 6 XCBUS 001 144 XESS Corporation XSA Board Flash RAM RELEASED DATED SHEET xsal_0 sch 4 Tue Sep 11 15 53 21 2001 U4 SDRAM 256MB XCBUS 001 1441 pe C22 C25 0 01uF 0 01uF COMPANY XESS Corporation XSA Board Sync DRAM DRAWN DATED REV V RELEASED DATED SHEET xsal_0 sch 5 Tue Sep 11 15 53 22 2001 R2C RED1 XCBUSO13 3 ANN 6 330 REDO XCBUSO12 A Ad 680 R2B GREENI XCBUS020 2AAACL 330 RIB GREENO XCBUSO19 z 680 R2A BLUE1 XCBUS022 330 BLUEO XCBUSO21 8 AAA 680 HSYNC XCBUS023 VSYNC XCBUS026 R3E 4 7K R3D AAA 4 7K 12 R2D 330 XCBUS094 4 ps2 CLK RID
23. ORTD2 T T T 5 PARORTFDA PARPORTFD T PARPORTD7 PARPORTSS 80888 T PARPORTSA 1 o 5 PARPORTSS 1 88 PARPORTSZOPLDDO 2 T L jj sm 2 2 XSA Schematics The following pages show the detailed schematics for the XSA Board XSA BOARD V1 0 USER MANUAL 28 xsal_0 sch 1 Tue Sep 11 15 53 20 2001 3 3V 2 5V CN rO u O P 00 O O cN cN r Fu CO P 0 0 0 05 055855 466555 28888888888888888668 gt gt n 8 1 Aniston Lk mU WERT B T VREFO_1 VREF3_2 XCB RUSO07 7 VREF0_2 65 XCBIISOB5 4 R 010 10 VREF3_3 X B 066 RUSO 1 74 XCBUS074 RUSO 12 3 75 xcausnz5 7 25 77 B 0 29 4 1178 6078 1 79 23 0815018 1 SUSE 2 VREF1_1 VREF4 2 80805079 BUSO 23 83 RUSO 25 84 XCRUSORA 2 28 REEL 2 VREF 4_3 88 XCRUSORR 1 BUS029 29 VREFI_S 87 xCBuS087 RUSD40 40 93 XCRUSQ937 RUSD4 VREF2 1 VREF5_1 95 Ycnusnas 4 RUSO4 47 2_2 99 1 usns VREF5_2 01 4 BUSO 51 102 xCBUS102 4 RUSO 54 XC2S TQFP144 VREF5_3 193
24. bed previously and status line S6 connects directly to the FPGA for use as a communication line from the FPGA back to the PC The CPLD handles the fifteen remaining active lines of the interface to the parallel port Fifteen of the active lines of the parallel port connect to general purpose pins on the CPLD Three of the parallel port control lines 1 connect to the JTAG pins through which the CPLD is programmed The C1 control line clocks configuration data presented on the C3 line into the CPLD while the C2 signal steers the actions of the CPLD programming state machine Meanwhile information from the CPLD returns to the PC through status line S7 The eight data lines 00 07 and the remaining three status lines 53 55 connect to general purpose pins of the CPLD The CPLD can be programmed to act as an interface between the FPGA and the parallel port the dwnldpar svf file is an example of such an interface Schmitt trigger inverters are inserted into the D 1 line so it can carry a clean clock edge for use by any state machine programmed into the CPLD The CPLD connects to the configuration pins of the Spartan Il FPGA so it can pass configuration bitstreams from the parallel port to the FPGA The actual configuration data is presented on the to the FPGA on the same 8 bit bus that connects the CPLD Flash seven segment XSA BOARD V1 0 USER MANUAL 25 LED The CPLD also drives the configuration pins CCLK
25. e removed if the 2 5V supply voltage is applied from an external source through pin 22 of the XSA Board 46 1 2 set The shunt should be installed on pins 1 2 set when setting the frequency of the programmable oscillator 2 3 osc shunt should be installed on pins 2 and osc during normal operations when the programmable default oscillator is generating a clock signal J7 1 2 The shunt should be installed on pins 1 and 2 if the 3 3V supply voltage is derived from the 5V default supply 2 3 The shunt should be installed on pins 2 and 3 if the 3 3V supply voltage is derived from the 9VDC supply applied through jack J5 49 1 2 xi The shunt should be installed on pins 1 2 if the 5 Board is to be downloaded using the Xilinx JTAG Programmer software utility 2 3 xs The shunt should be installed on pins 2 3 if the XSA Board is to be downloaded using the XESS default GXSLOAD software utility J10 N A This is a header that provides access to the 5V and GND references on the board No shunt should be placed on this header XSA BOARD V1 0 USER MANUAL 9 Testing Your XSA Board Once your XSA Board is installed and the jumpers are in their default configuration you can test the board using the GUI based GXSTEST utility as follows You start GXSTEST by clicking on the icon placed on the desktop during the XSTOOLS installation This brings up the screen shown below gxstest OR x Board Type
26. he FPGA remains configured as an interface to the SDRAM You can also examine the contents of the SDRAM device by uploading it to the PC To upload data from an address range in the SDRAM type the upper and lower bounds of the range into the High Address and Low Address fields below the RAM area and select the format in which you would like to store the data using the drop down list Then click on the file icon and drag amp drop it into any folder This activates the following sequence of steps 1 The FPGA on the XSA Board is reprogrammed to create an interface between the RAM device and the PC parallel port This interface is stored in the ram100 bit bitstream file located within the XSTOOLS XSA folder 2 The SDRAM data between the high and low addresses inclusive is uploaded through the parallel port 3 The uploaded data is stored in a file named RAMUPLD with an extension that reflects the file format XSA BOARD V1 0 USER MANUAL 17 XSA BOARD V1 0 USER MANUAL gxsload LPT bam 82 x 44 602 scu 18 Programmer s Models This section describes the various sections of the XSA Board and shows how the of the FPGA and CPLD are connected to the rest of the circuitry The schematics which follow are less detailed so as to simplify the descriptions Please refer to the complete schematics at the end of this document if you need more details XSA Board Organization
27. her circuits on the protoboard The numbers printed next to the rows of pins on your XSA Board correspond to the pin numbers of the FPGA Power can still be supplied to your XSA Board though jack J9 or power can be applied directly through several pins on the underside of the board Just connect 5V 3 3V 2 5V and ground to the pins of your XSA Board listed in e Table 1 Power supply pins for the XSA Board Voltage Pin Note 5V 2 3 3V 22 Remove the shunt from jumper J7 if you wish to use your own 3 3V supply Leave the shunt on jumper J7 to generate the 3 3V supply from the 5V supply 2 5V 54 Remove the shunt from jumper J2 if you wish to use your own 2 5V supply Leave the shunt on jumper J2 to generate the 2 5V supply from the 3 3V supply GND 52 PS 2 mouse or keyboard center positive power supply VGA monitor e Figure 1 External connections to the XSA Board Actually this is an 540 Board but the connections are the same XSA BOARD V1 0 USER MANUAL PC Parallel Port External Clock Input 100 MHz Osc 9VDC Power Supply 3 3V Pushbutton GND CPLD Flash RAM 5V Spartan II FPGA SDRAM Pushbutton 2 5V PS 2 Mouse VGA Monitor or Keyboard e Figure 2 Arrangement of components on the XSA Board Connecting a PC to Your XSA Board The 6 DB25 male to male cable included w
28. hrough the parallel port 4 The CPLD is reprogrammed to create a circuit that configures the FPGA with the contents of the Flash when power is applied to the XSA Board This configuration loader is stored in the fcnfg100 svf bitstream file located within the XSTOOLS XSA folder Multiple files can be stored in the Flash device just by dragging them into the Flash EEPROM area highlighting the files to be downloaded and clicking the Load button Note that anything previously stored in the Flash will be erased by each new download This is useful if you need to store information in the Flash in addition to the FPGA bitstream Files are selected and de selected for downloading just by clicking on their names in the Flash EEPROM area The address ranges of the data in each file should not overlap or this will corrupt the data stored in the Flash device XSA BOARD V1 0 USER MANUAL 15 You can also examine the contents of the Flash device by uploading it to the To upload data from an address range in the Flash type the upper and lower bounds of the range into the High Address and Low Address fields below the Flash EEPROM area and select the format in which you would like to store the data using the drop down list Then click on the file icon and drag amp drop it into any folder This activates the following sequence of steps 1 The CPLD on the XSA Board is reprogrammed to create an interface between the Flash device and the PC parallel p
29. ith your XSA Board connects it to a PC One end of the cable attaches to the parallel port on the PC and the other connects to the female DB 25 connector J8 at the top of the XSA Board as shown in Connecting a VGA Monitor to Your XSA Board You can display images on a VGA monitor by connecting it to the 15 pin J3 connector at the bottom of your XSA Board see You will have to download a VGA driver circuit to your XSA Board to actually display an image You can find an example VGA driver at http www xess com ho03000 html XSA BOARD V1 0 USER MANUAL 8 Connecting a Mouse or Keyboard to Your XSA Board You can accept inputs from a keyboard or mouse by connecting it to the J4 PS 2 connector at the bottom of your XSA Board see Figure 1 You can find an example keyboard driver at http www xess com ho03000 html Setting the Jumpers on Your XSA Board The default jumper settings shown in 2 configure your XSA Board for use in a logic design environment You will need to change the jumper settings only if you are m downloading FPGA bitstreams to your XSA Board using the Xilinx JTAG Programmer software m reprogramming the clock frequency on your XSA Board see page 11 m changing the power sources for the XSA supply voltages e Table 2 Jumper settings for XSA Boards Jumper Setting Purpose J2 On A shunt should be installed if the 2 5V supply voltage is derived from the 3 3V supply default Off The shunt should b
30. message describing your problem to hotline xilinx com or check their web site at http www xilinx com support support htm The XSA Board requires an external power supply to operate It does not draw power through the downloading cable from the PC parallel port If you are connecting a 9VDC power supply to your XSA Board please make sure the center terminal of the plug is positive and the outer sleeve is negative XSA BOARD V1 0 USER MANUAL 4 Packing List Here is what you should have received in your package m 5 Board m with 25 pin male connector on each end m anXSTOOLS CDROM with software utilities and documentation for using the XSA Board XSA BOARD V1 0 USER MANUAL 5 Installation Installing the XSTOOLS Utilities and Documentation Xilinx currently provides the WebPACK tools for programming their CPLDs and Spartan ll FPGAs Any recent version of WebPACK software should generate bitstream configuration files that are compatible with your XSA Board You can download the most current version of the WebPACK tools from http www xilinx com xlnx xil prodcat landingpage jsp title ISE WebPack Follow the directions Xilinx provides for installing their software XESS Corp provides the additional XSTOOLS utilities for interfacing a PC to your XSA Board Run the SETUP EXE program on the XSTOOLS CDROM to install these utilities Applying Power to Your XSA Board You can use your XSA Board in
31. ort 2 The Flash data between the high and low addresses inclusive is uploaded through the parallel port 3 The uploaded data is stored in a file named FLSHUPLD with an extension that reflects the file format X gxsload Board Type 5 00 Load Port FPGA CPLD Flash EEPROM E 00 High Address 0x3FFFF Low Address Upload Format EXO The uploaded data can be stored in the following formats MCS Intel hexadecimal file format This is the same format generated by the promgen utility with the p mcs option HEX Identical to MCS format EXO 16 Motorola S record format with 16 bit addresses suitable for 64 KByte uploads only EXO 24 Motorola S record format with 24 bit addresses This is the same format generated by the promgen utility with the p exo option EXO 32 Motorola S record format with 32 bit addresses XES 16 XESS hexadecimal format with 16 bit addresses This is a simplified file format that does not use checksums XES 24 XESS hexadecimal format with 24 bit addresses XSA BOARD V1 0 USER MANUAL 16 XES 32 XESS hexadecimal format with 32 bit addresses After the data is uploaded from the Flash you must reprogram the CPLD on the XSA Board with one of the following files XSTOOLS XSA fintf100 svf Drag amp drop this file into the FPGA CPLD area and click on the Load button to put the XSA in a mode where it will configure
32. s ss ss ss ss ss ss O SN IO I 000 000 OC IJIN OO 3 E 00 ONCU lt O A Li 0 0 42 8 X 16 SDRAM A 256 KByte Flash Atmel AT49F002 Flash RAM with 256 KBytes of storage 256K x 8 is connected to both the FPGA and CPLD as shown below The CPLD and FPGA both have access to the Flash RAM Typically the CPLD will program the Flash with data passed through the parallel port If the data is FPGA configuration bitstream then the CPLD can be configured to program the FPGA with the bitstream from Flash whenever the XSA Board is powered up After power up the FPGA XSA BOARD V1 0 USER MANUAL 22 can read and or write the Flash Of course the CPLD and FPGA have to be programmed such that they do not conflict if both are trying to access the Flash The Flash be disabled by raising the CE pin to in which case the I O lines connected to the Flash can be used for general purpose communication between the FPGA and the CPLD 256 KByte Flash RAM O NOTWSOMm LLI c OO oor lt lt lt C C T T lt lt lt lt lt C t t t t t x wx oo
33. to the FPGA by the CPLD on power up PS 2 Port The XSA Board provides a PS 2 style interface mini DIN connector J4 to either a keyboard or a mouse The FPGA receives two signals from the PS 2 interface a clock signal and a serial data stream that is synchronized with the falling edges on the clock signal 5V ck PS 2 data Connector FPGA 44 o Pushbutton N SW2 XSA BOARD V1 0 USER MANUAL 24 The XSA Board has a single pushbutton that shares the FPGA pin connected to the data line of the PS 2 port The pushbutton applies a low level to the FPGA pin when pressed and a resistor pulls the pin to a high level when the pushbutton is not pressed VGA Monitor Interface The FPGA can generate a video signal for display on a VGA monitor When the FPGA is generating VGA signals the FPGA outputs two bits of red green and blue color information to a simple resistor ladder DAC The outputs of the DAC are sent to the RGB inputs of a VGA monitor along with the horizontal and vertical sync pulses HSYNC from the FPGA gt vsync gt hsync REDO AAA Spartan ll 25550 AA l red AWW onnector GREEN AAA TT 43 BLUE0 AN BLUET AAA Parallel Port Interface The parallel port is the main interface for communicating with the XSA Board Control line goes directly to the DS1075 oscillator and is used for setting the divisor as descri
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