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uPD780053, 780054, 780055, 780056, 780058, 780058B, 780053Y

1. NOTE ITEM MILLIMETERS Each lead centerline is located vvithin 0 13 mm of A 17 20 0 20 its true position T P at maximum material condition 14 00 0 20 14 00 0 20 17 20 0 20 0 825 0 825 0 32 0 06 0 13 0 65 T P 1 60 0 20 0 80 0 20 01788 0 10 1 40 0 10 0 125 0 075 o 7 39739 1 70 MAX P80GC 65 8BT 1 o D ooluz Z rixicl T O TO OJU Data Sheet U12182EJ4VODS 71 NEC PD780053 780054 780055 780056 780058 7900568 780053Y 780054Y 780055Y 780056Y 780058BY 80 PIN PLASTIC TQFP FINE PITCH 12x12 detail of lead end NOTE ITEM MILLIMETERS Each lead centerline is located within 0 08 mm of A 14 0 0 2 its true position T P at maximum material condition 12 0 0 2 12 0 0 2 14 0 0 2 1 25 1 25 0 22 0 05 0 08 0 5 T P 1 0 0 2 0 5 0 145 0 05 0 08 1 0 0 1 0 05 ot 4 39739 1 1 0 1 0 25 0 640 15 P80GK 50 9EU 1 ci l l x olulz zjm xjl TO Tjoo wW 72 Data Sheet U12182EJAVODS NEC 15 RECOMMENDED SOLDERING CONDITIONS 0780053 780054 780055 780056 780058 780058B 780053Y 780054Y 780055Y 780056Y 780058BY The uPD78005x and 78005xY should be soldered and mounted under the following recommended con
2. Directly connect to Vsso or Vss Data Sheet U12182EJ4VODS NEC PD780053 780054 780055 780056 780058 7900568 780053Y 780054Y 780055Y 780056Y 780058BY Figure 3 1 Pin I O Circuits 1 2 Von enable LG cr Von Output Luc Schmitt triggered input with hysteresis characteristics disable Vsso vd O IN OUT Von Type 10 B e z z Defers S Deere enable Vppo e Das 1 Ty II P n Dep t AH Hren IN OUT Output Open drain disable Output disable ua Vsso y Input lt Q enable IN OUT Type 5 N Type 11 D Von Pull up Do P ch Pull up Do F Ph enable Vos enable Vom bate feh e Deier P E Output IN OUT disable P ch__ 7Vsso Comparator J 1 1 Output disable I T N ch ER Vsso Vner threshold voltage Input y enable Data Sheet U12182EJ4VODS HO IN OUT 17 uPD780053 780054 780055 780056 780058 7900588 780053Y 780054Y 780055Y 780056Y 780058BY Figure 3 1 Pin Input Output Circuits 2 2 NEC Type 12 C Vboo z Pull enable Do ra Type 16 Feed back cut off aL gt NN T IN OUT Output N ch disable V F SS0 m Input ch enable Analog output XT1 XT2 voltage bibi 7 Vsso Type 13 J
3. Mask 1 E IN OUT Data Output disable E N ch Vsso Von RD P ch cA T Middle voltage input buffer Data Sheet U12182EJ4VODS NEC PD780053 780054 780055 780056 780058 7900588 780053Y 780054Y 780055Y 780056Y 780058BY 4 MEMORY SPACE Figure 4 1 shows the memory map of the uPD78005x and 78005xY Figure 4 1 Memory Map Special function registers SFRs 256 x 8 bits General purpose registers 32 x 8 bits Reserved Internal expanded RAM 1 024 x 8 bits Internal high speed Note 1 RAM FBOOH Note 2 FAFFH Reserved Reserved J FAEOH Data memory FADFH nnnnH space Internal buffer RAM Program area 32 x 8 bits FACOH 1000H FABFH xall Reserved CALLF entry area FASOH A FA7FH 0800H 07 Program area External memory Program memory 0080H space 007FH nnnnH 1 nnnnH CALLT table area 0040H OO3FH Internal ROMNete 3 Vector table area Y Y 0000H 0000H Notes 1 uPD780058 780058B 780058BY only 2 If external device expansion functions are to be employed for the 780058 780058B or 780058BY setthe size ofthe internal ROM to 56 KB or less using internal the memory size switching register IMS 3 The internal ROM capacity depends on the product see the table below Part Number Last Address of Internal ROM nnnnH uPD780053 780053Y HPD780054 780054Y LPD780055 780055Y
4. E Software interrupt d Internal bus y Interrupt Priority Xo le request generator controller IF Interrupt request flag IE Interrupt enable flag ISP In service priority flag MK Interrupt mask flag PR Priority specification flag Data Sheet U12182EJAVODS 33 NEC PD780053 780054 780055 780056 780058 7900588 780053Y 780054Y 780055Y 780056Y 780058BY 6 2 Test Functions The test function includes the two test input sources shown in Table 6 2 below Table 6 2 Test Input Source List Test Input Source Internal External Trigger INTWT Watch timer overflow Internal INTPT4 Port 4 falling edge detection External Figure 6 2 Basic Configuration of Test Function nternal bus Standby release Test input signal flag F Test input flag MK Test mask flag 34 Data Sheet U12182EJAVODS NEC PD780053 780054 780055 780056 780058 7900568 780053Y 780054Y 780055Y 780056Y 780058BY 7 EXTERNAL DEVICE EXPANSION FUNCTION The external device expansion function connects external devices to areas other than the internal ROM RAM and SFR areas Ports 4 to 6 are used for external device connection 8 STANDBY FUNCTION The following two standby functions are available for further reduction of system current consumption HALT mode In this mode the CPU operating clock is stopped The average current consumption can be reduced by intermittent operation b
5. 780056 780056Y HPD780058B 780058BY 780058 Data Sheet U12182EJAVODS 19 NEC PD780053 780054 780055 780056 780058 7900588 780053Y 780054Y 780055Y 780056Y 780058BY 5 PERIPHERAL HARDWARE FUNCTION FEATURES 5 1 Ports The following three types of I O ports are available e CMOS input POO P07 2 CMOS VO P01 to P05 port 1 to port 5 P64 to P67 port 7 port 12 port 13 62 N ch open drain I O P60 to P63 4 Total 68 Table 5 1 Port Functions Port Name Pin Name Function POO P07 Input only 1 to PO5 port Input output can be specified in 1 bit units When used as an input port an on chip pull up resistor can be specified by software P10 to P17 1 O port Input output can be specified in 1 bit units When used as an input port an on chip pull up resistor can be specified by software P20 to P27 port Input output can be specified in 1 bit units When used as an input port an on chip pull up resistor can be specified by software P30 to P37 port Input output can be specified in 1 bit units When used as an input port an on chip pull up resistor can be specified by software P40 to P47 port Input output can be specified in 8 bit units When used as an input port an on chip pull up resistor can be specified by software The test flag KRIF is set to 1 by falling edge detection P50 to P57 UO port Input output can be specified in 1 bit units
6. Capture trigger signal input to the capture register CR00 PO1 INTP1 External count clock input to the 8 bit timer TM1 P33 External count clock input to the 8 bit timer TM2 P34 TO0 TO1 TO2 16 bit timer TMO output also used for 14 bit PWM output P30 8 bit timer TM1 output P31 8 bit timer TM2 output P32 PCL Output Clock output for trimming of main system clock and subsystem clock P35 BUZ Output Buzzer output P36 RTPO to RTP7 Output Real time output port from which data is output in synchronization with a trigger P120 to P127 ADO to AD7 Remark 1 0 Lower address data bus for expanding memory externally uPD78005xY only Data Sheet U12182EJ4VODS P40 to P47 13 NEC uPD780053 780054 780055 780056 780058 780058B 780053Y 780054Y 780055Y 780056Y 780058BY 3 2 Non Port Pins 2 2 Pin Name Output Function Higher address bus for expanding memory externally Alternate Function P50 to P57 Output Strobe signal output for reading from external memory Strobe signal output for writing to external memory P64 P65 WAIT Input Wait insertion at external memory access P66 ASTB Output Strobe output that externally latches address information output to ports 4 and 5 to access external memory P67 ANIO to ANI7 Input A D converter analog input P10
7. 50 Time from VVRT to address hold twRADH 0 85tcy 1 15tcy 40 Delay time from WAIT to RD VVTRD 1 15tcy 40 3 15tcy 40 Delay time from WAITT to WRT twrwR 1 15tcv 30 Remarks 1 MCS Bit 0 of the oscillation mode selection register OSMS 2 PCC2 to PCCO Bits 2 to of the processor clock control register PCC 3 tcv 4 4 nindicates the number of waits Data Sheet U12182EJ4VODS 3 15tcy 30 47 NEC 0780053 780054 780055 780056 780058 780058B 780053Y 780054Y 780055Y 780056Y 780058BY b When MCS 0 or PCC2 to PCCO 000B Ta 40 to 85 C Von 2 7 to 5 5 V Parameter Conditions ASTB high level width ASTH tcy 80 Address setup time ADS tcy 80 Address hold time ADH 0 4tcy 10 Time from address to data input Lupp 3 2n 160 ADD2 4 2n tcv 200 Time from RD to data input trop 1 4 2n tcv 70 RDD2 2 4 2n tcy 70 Read data hold time RDH 0 RD low level width RDL1 1 4 2n tcv 20 RDL2 2 4 2n tcy 20 Time from RD to WAIT Input tour tcv 100 RDVVT2 2tcy 100 Time from WR to WAIT input twawr 2tcy 100 WAIT low level width twrL 1 2n tcv 2 2n tcv Write data setup time twos 2 4 2n tcy 60 Write data hold time twoH 20 WR low level width twaL 2 4 2n tcv 20 Delay time from ASTB
8. Watch timer Serial interface 0 Serial interface 1 Serial Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 interface 2 A D converter D A converter Interrupt control Buzzer output Clock output control 78K 0 ROM CPU core RAM Vasen IC Von Vssi Port 12 Port 13 Real time output port External access System control The internal ROM and RAM capacity varies depending on the product 4PD78005xY only Data Sheet U12182EJ4VODS 0780053 780054 780055 780056 780058 780058B 780053Y 780054Y 780055Y 780056Y 780058BY POO P01 to POS P07 P10 to P17 P20 to P27 P30 to P37 P40 to P47 P50 to P57 P60 to P67 P70 to P72 P120 to P127 P130 P131 RTPO P120 to RTP7 P127 ADO P40 to AD7 P47 AB P50 to A15 P57 RD P64 VVR P65 VVA T P66 ASTB P67 RESET X1 X2 XT1 P07 XT2 NEC PD780053 780054 780055 780056 780058 7900568 780053Y 780054Y 780055Y 780056Y 780058BY 3 PIN FUNCTIONS 3 1 Port Pins 1 2 Pin Name Function Alternate Function POO Port 0 Input only INTPO TIOO Pot 7 bit 1 O p
9. 300 400 0 4 5 V lt Voo lt 5 5 V 2 0 V lt Voo lt 4 5 V Von 2 0 to 5 5 V viii 12 bus mode SCL External clock input uPD78005xY only Parameter SCL cycle time Conditions SCL high low level width Von 2 0 to 5 5 V SDAO SDA1 setup time to SCLT Von 2 0 to 5 5 V SDAO SDA1 hold time from 514 Delay time from SCLJ to SDAO SDA1 output 1 kO 4 5 V lt Voo lt 5 5 V C 100 pFNote 2 0 V lt Voo lt 4 5 V SDAO SDA1J from SCLT or SDAO SDA11 from SCLT SCL from SDAO SDA1L Von 2 0 to 5 5 V SDAO SDA1 high level width Von 2 0 to 5 5 V SCL rise fall time Note R and C are the load resistance and load capacitance of the SDAO and SDA1 output lines When using external device expansion function When not using external device expansion function Data Sheet U12182EJAVODS 53 NEC b Serial interface channel 1 i 3 wire serial I O mode SCK1 Internal clock output Parameter SCK1 cycle time Conditions 4 5 V lt Voo lt 5 5 V uPD780053 780054 780055 780056 780058 780058B 780053Y 780054Y 780055Y 780056Y 780058BY 800 2 7 V lt Voo lt 4 5 V 1 600 2 0 V lt Voo lt 2 7 V 3 200 4 800 SCK1 high low level width tkHo tkLo Voo 4 5 to 5 5 V tkcvo 2 50 tkcvo 2
10. 780054 780055 780056 780058 780058B 780053Y 780054Y 780055Y 780056Y 780058BY 3 wire serial UO mode with automatic transmit receive function SO1 X D7 SI1 X D7 tsik11 12 16 M 8 E14 12 kHi1 12 SCK1 tsew KCY11 12 STB 3 wire serial l O mode with automatic transmit receive function busy processing Note The signal is not actually driven low here it is shown as such to indicate the timing UART mode external clock input KCY15 ASCK 64 Data Sheet U12182EJAVODS NEC 0780053 780054 780055 780056 780058 780058B 780053Y 780054Y 780055Y 780056Y 780058BY A D Converter Characteristics uPD780053 780054 780055 780056 780058B 780053Y 780054Y 780055Y 780056Y 780058BY Ta 40 to 85 C Voo 1 8 to 5 5 V AVss Vss 0 V Parameter Conditions Resolution 8 Overall errorNote 1 1 8 V x AVrero lt 2 7 V 1 4 2 7 V x AVrero lt 5 5 V 0 6 Conversion time Tcowvi 1 8 V x AVRero lt 2 7 V 100 Tconve 2 7 V x AVrero lt 5 5 V 100 Analog input voltage Vian AVREFo Reference voltage AVnero Von AVnero current ReFo When A D converter is operatingNote 2 1 500 When A D converter is not operatingNote 3 3 Notes 1 Excludes quantization error 1 2 LSB This value is indicated as a ratio to the full scale value FSR 2 The current flowing to the AVrero pin when bit 7 CS of the
11. 780058 7900558 780053Y 780054Y 780055Y 780056Y 780058BY Notes 1 High speed mode operation when the processor clock control register PCC is set to OOH 2 Low speed mode operation when the PCC is set to 04H 3 Operation with main system clock fxx fx 2 when the oscillation mode select register OSMS is set to 00H 4 Operation with main system clock fxx fx when OSMS is set to 01H 5 Refer to the current flowing to the Vppo and pins The current flowing to the A D converter D A converter and on chip pull up resistor is not included 6 When the main system clock operation is stopped AC Characteristics 1 Basic operation Ta 40 to 85 C 1 8 to 5 5 V Parameter Conditions Cycle time Operating with main system Von 2 7 to 5 5 V 0 8 Minimum clock fxx 2 5 MHz Note 1 2 0 instruction execution time Operating with main system 3 5 V lt Voo lt 5 5 V 0 4 clock fxx 5 0 MHz Note 2 2 7 V lt Voo lt 3 5 V 0 8 Operating on subsystem clock 40Note 3 TIOO input high trmoo 3 5 V lt Von lt 5 5 V 2 fsam 0 1Note 4 low level width triLoo 2 7 V lt Voo lt 3 5 V 2ifsam 0 2Note 4 2 fsam 0 5Note 4 T101 input high Drun Voo 2 7 to 5 5 V 10 lovv level vvidth triLot 20 TH TI2 input fm Voo 4 5 to 5 5 V 0 frequency 0 TH TI2 input Voo 4 5 to 5 5 V 100 high low level 1 8 width Interrupt request 3 5 V lt Voo lt 5 5 V 2 fsam 0 1N
12. Automatic data transmit receive address pointer ADTP Automatic data transmit receive interval specification register ADTI 51 20 O 501 21 Handshake controller STB TxD1 P23 BUSY RxD1 P24 SCK1 P22 O Serial clock counter Serial clock controller 28 Data Sheet U12182EJ4V0DS fxx 2 to fxx 2 TO2 NEC 0780053 780054 780055 780056 780058 7900568 780053Y 780054Y 780055Y 780056Y 780058BY Figure 5 12 Block Diagram of Serial Interface Channel 2 Internal bus Receive buffer register RXB SIO2 Direction controller IF Transmit shift register TXS SIO2 Direction controller RxDO SI2 P70 O Transmit controller INTST Receive shift register RXS Receive controller Near I INTSR INTCSI2 t RxD1 BUSY P24 O TxD0 SO2 P71 TxD1 STB P23 O Y SCK output controller Baud rate generator fxx to fxx 210 5 9 Real Time Output Ports Data set previously in the real time output buffer register is transferred to the output latch by hardware concurrently with timer interrupt request and external interrupt request generation in order to output off chip This is the real time output function Pins used to output off chip are called real time output ports By using a real time output port a signal with no jitter can be output This is mo
13. Capacity Subseries Name Bytes 16 Bit Watch A D Control uPD78075B 32 K to 40 K 3 ch UART 1 ch 4PD78078 48 K to 60 K uPD78070A UPD780058 24 K to 60 K 3 ch time division UART 1 ch LPD78058F 48 K to 60 K 3 ch UART 1 ch 4PD78054 16 K to 60 K 80065 40 K to 48 K 4 ch UART 1 ch 80078 48 K to 60 K 3 ch UART 2 ch uPD780034A 8 K to 32 K 3 ch UART 1 ch 4PD78018F 8 K to 60 K uPD78083 8Kto 16K 1 ch UART Inverter uPD780988 16 K to 60 K 3 ch UART control VED uPD780208 32 K to 60K 2 ch drive 1 780232 16 K to 24 K uPD78044H 32 K to 48 K 1 ch 8044 16 K to 40 K 2 ch uPD780338 48 K to 60 K 2 ch UART uPD780328 uPD780318 uPD780308 48 K to 60 K 3 ch time division UART 1 ch 1PD78064B 32 K 2 ch UART 1 ch 8064 16K to 32K Bus uPD780948 60 K 3 ch UART 1 ch interface 78098 40 K to 60 K supported pD780816 32 K to 60 K 2 ch UART 1 ch Meter 1PD780958 48 K to 60 K 2 ch UART 1 ch control Dash uPD780852 32 K to 40 K 3 ch UART 1 ch board control 4PD780828B 32 K to 60 K Note 16 bit timer 2 channels 10 bit timer 1 channel 4 Data Sheet U12182EJ4VODS NEC The major functional differences among the subseries are l
14. Default priority is the priority order when several maskable interrupt requests are generated simultaneously 0 is the highest order and 17 is the lowest Basic configuration types A to E correspond to A to E in Figure 6 1 Data Sheet U12182EJAVODS 31 NEC PD780053 780054 780055 780056 780058 7900588 780053Y 780054Y 780055Y 780056Y 780058BY Figure 6 1 Basic Configuration of Interrupt Function 1 2 A Internal non maskable interrupt Internal bus Interrupt Priority request controller generator Standby release signal B Internal maskable interrupt Internal bus Vector table address generator nterrupt request gt Standby release signal C External maskable interrupt INTPO Internal bus y Sampling clock select SCS Sampling clock External interrupt mode register INTMO Vector table address generator Interrupt request Standby release signal 32 Data Sheet U12182EJAVODS NEC 0780053 780054 780055 780056 780058 7900568 780053Y 780054Y 780055Y 780056Y 780058BY Figure 6 1 Basic Configuration of Interrupt Function 2 2 D External maskable interrupt except INTPO Y Internal bus External interrupt mode register INTMO ae Vector table Interrupt 2 address request controller generator Standby release signal
15. Time 3 seconds max per pin row Caution Do not use different soldering methods together except for partial heating Data Sheet U12182EJ4VODS 73 NEC PD780053 780054 780055 780056 780058 7900568 780053Y 780054Y 780055Y 780056Y 780058BY Table 15 1 Surface Mounting Type Soldering Conditions 2 2 uPD780053GK xxx 9EU 80 pin plastic TQFP 12 x 12 1PD780054GK xxx 9EU 80 pin plastic TQFP 12 x 12 uPD780055GK xxx 9EU 80 pin plastic TQFP 12 x 12 uPD7800566GK xxx 9EU 80 pin plastic TQFP 12 x 12 uPD780058GK xxx 9EU 80 pin plastic TQFP 12 x 12 uUPD780058BGK xxx 9EU 80 pin plastic TQFP 12 x 12 UPD780053YGK xxx 9EU 80 pin plastic TQFP 12 x 12 uUPD780054YGK xxx 9EU 80 pin plastic TQFP 12 x 12 uPD780055YGK xxx 9EU 80 pin plastic TQFP 12 x 12 UPD780056YGK xxx 9EU 80 pin plastic TQFP 12 x 12 uPD780058BYGK xxx 9EU 80 pin plastic TQFP 12 x 12 Soldering Soldering Conditions Recommended Method Condition Symbol Infrared reflow Package peak temperature 235 C Time 30 seconds max at 210 C or higher IR35 107 2 Count Twice or less Exposure limit 7 days ee after that prebake at 125 C for 10 hours VPS Package peak temperature 215 C Time 40 seconds max at 200 C or higher VP15 107 2 after that prebake at 125 C for 10 hours Note Count Twice or less Exposure limit 7 days Wave soldering Partial heating Pin temperature 300 C or less Time 3 seconds ma
16. Voo lt 4 5 V 2 0 V lt Voo lt 2 7 V SCK2 high low level width 4 5 V lt Voo lt 5 5 V 2 7 V lt Voo lt 4 5 V 2 0 V lt Voo lt 2 7 V SI2 setup time to SCK21 tski4 Voo 2 0 to 5 5 V SI2 hold time from SCK21 ksit4 Delay time from SCK2J to SO2 tksow C 100 pFNete Vpp 2 0 to 5 5 V output SCK rise fall time Other than below Von 4 5 to 5 5 V When not using external device expansion function Note C is the load capacitance of the SO2 output line Data Sheet U12182EJAVODS 57 NEC PD780053 780054 780055 780056 780058 7800568 780053Y 780054Y 780055Y 780056Y 780058BY iii UART mode Dedicated baud rate generator output Parameter Transfer rate Conditions 4 5 V lt Voio lt 5 5 V 78 125 2 7 V lt Voo lt 4 5 V 39 063 2 0 V lt Voo lt 2 7 V 19 531 iv UART mode External clock input Parameter ASCK cycle time KCY15 Conditions 4 5 V lt Voo lt 5 5 V 9 766 2 7 V lt Voo lt 4 5 V 2 0 V lt Voo lt 2 7 V ASCK high low level width 4 5 V lt Voo lt 5 5 V 2 7 V lt Voo lt 4 5 V 2 0 V lt Voo lt 2 7 V Transfer rate 4 5 V lt Voo lt 5 5 V 39 063 2 7 V lt Voo lt 4 5 V 19 531 2 0 V lt Voo lt 2 7 V 9 766 6 510 ASCK rise fall time 58 Voo 4 5 to 5 5 V when
17. lovv level vvidth xH xL Notes 1 Indicates only oscillator characteristics Refer to AC Characteristics for instruction execution time 2 Time required to stabilize oscillation after reset or STOP mode release Cautions 1 Whenusing the main system clock oscillator wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance Keep the wiring length as short as possible Do not cross the wiring with the other signal lines Do not route the wiring near a signal line through which a high fluctuating current flows Always make the ground point of the oscillator capacitor the same potential as Vss Do not ground the capacitor to a ground pattern through which a high current flows Do not fetch signals from the oscillator 2 When the main system clock is stopped and the system is operating on the subsystem clock vvait until the oscillation stabilization time has been secured by the program before svvitching back to the main system clock Remark For the resonator selection and oscillator constant customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation 40 Data Sheet U12182EJAVODS NEC PD780053 780054 780055 780056 780058 7900558 780053Y 780054Y 780055Y 780056Y 780058BY Subsystem Clock Oscillator Characteristics TA 40 to 85 C 1 8
18. lt Voo lt 2 7 V 3 200 4 800 SCK1 high low level width Tett koi Von 4 5 to 5 5 V tkcy11 2 50 tkcy11 2 100 SI1 setup time to SCK11 tsik11 4 5 V lt Voo lt 5 5 V 100 2 7 V lt Voo lt 4 5 V 150 2 0 V lt Voo lt 2 7 V 300 400 91 hold time from SCK11 ksi11 400 Delay time from 9 14 to SO1 output kso11 C 100 pFNote 300 STB from SCK1T SBD tkcv11 2 100 tkcvi 2 100 Strobe signal high level width tsBw 2 7 V lt Voo lt 5 5 V bei 30 tkcy11 30 2 0 V lt Voo lt 2 7 V bei 60 feu 60 tkov1i1 90 tkcy11 90 Busy signal setup time to busy signal detection timing 100 Busy signal hold time from busy signal detection timing 4 5 V lt Voo lt 5 5 V 100 2 7 V lt Voo lt 4 5 V 150 2 0 V lt Voo lt 2 7 V 200 300 SCK1J from busy inactive Note C is the load capacitance of the SCK1 and SO1 output lines Data Sheet U12182EJ4VODS 2tkov11 55 NEC PD780053 780054 780055 780056 780056 7800568 780053Y 780054Y 780055Y 780056Y 780058BY iv 3 wire serial 1 O mode with automatic transmit receive function SCK1 External clock input Parameter Conditions SCK1 cycle time kcyiz 45 V lt Voo lt 5 5 V 2 7 V lt Voo lt 4 5 V 2 0 V lt Voo lt 2 7 V SCK1 hig
19. to RD tasrap 0 4tcy 30 Delay time from ASTBJ to WRJ tastwa 1 4tcy 30 Delay time from RD to RDAST tcv 10 tcv 20 ASTBT at external fetch Time from RDT to address RDADH tcv 50 tov 50 hold at external fetch Time from RDT to write data trowo 0 4tcy 20 output Time from VVR to write data twrwb 60 output Time from WRT to address hold VVRADH toy tcy 60 Delay time from WAIT to RDT twrrp 0 6tcy 180 2 6tcv 180 Delay time from WAITT to WRT twrwa 0 6tcy 120 2 6tev 120 Remarks 1 MCS Bit 0 of the oscillation mode selection register OSMS 2 PCC2 to PCCO Bits 2 to of the processor clock control register PCC 3 tcv Tcv 4 4 n indicates the number of waits 48 Data Sheet U12182EJ4VODS NEC c When MCS or 2 to PCCO 000B Ta 40 to 85 C Von 1 8 to 2 7 V Parameter ASTB high level width ASTH Conditions tcy 150 0780053 780054 780055 780056 780058 780058B 780053Y 780054Y 780055Y 780056Y 780058BY Address setup time taps tcv 150 Address hold time ADH 0 37tcy 40 Time from address to data input ADD1 3 2n tcv 320 ADD 4 2n tcy 300 Time from RD to data input RDD1 1 37 2n tev 120 RDD 2 37 2n tcv 120 Read data hold time RDH 0 RD low level width trou 1 37 2n t
20. 100 SI1 setup time to SCK11 4 5 V lt Voo lt 5 5 V 100 2 7 V lt Voo lt 4 5 V 150 2 0 V lt Voo lt 2 7 V 300 400 91 hold time from SCK11 400 Delay time from SCK1J to SO1 output C 100 pFNote Note C is the load capacitance of the SCK1 and SO1 output lines 3 wire serial UO mode SCK1 External clock input Parameter SCK1 cycle time Conditions 45V lt Vo0 lt 5 5V 2 7 V lt Voo lt 4 5 V 2 0 V lt Voo lt 2 7 V SCK1 high low level width KH10 KL10 45V lt Voo lt 5 5 V 2 7 V lt Voo lt 4 5 V 2 0 V lt Voo 2 7 V SI1 setup time to SCK11 SIK10 Voo 2 0 to 5 5 V 911 hold time from SCK11 tkisto Delay time from SCK1J to SO1 output KSO10 C 100 pFNote V55 2 0 to 5 5 V SCKT rise fall time Note Cis the load capacitance of the SO1 54 trio tF10 When using external device expansion function When not using external device expansion function output line Data Sheet U12182EJAVODS NEC PD780053 780054 780055 780056 780058 7600588 780053Y 780054Y 780055Y 780056Y 780058BY iii 3 wire serial UO mode with automatic transmit receive function SCK1 Internal clock output Parameter SCK1 cycle time KCY11 Conditions 4 5 V lt Voo lt 5 5 V 800 2 7 V lt Voo lt 4 5 V 1 600 2 0 V
21. 12C bus mode Y MSB first 2 wire serial UO mode Y MSB first Asynchronous serial interface V On chip dedicated baud UART mode on chip time rate generator division transfer function Figure 5 10 Block Diagram of Serial Interface Channel 0 1 2 a uPD78005x Internal bus Serial 1 O shift register 0 SIOO Selector 500 5 1 26 D Busy acknowledge output circuit Selector 1 nterrupt request INTCSIO SCKO P27 D e signal generator he 221 Serial clock lt controller fxx 2 to fxx 28 TO2 Data Sheet U12182EJAVODS 27 NEC PD780053 780054 780055 780056 780058 7900588 780053Y 780054Y 780055Y 780056Y 780058BY Figure 5 10 Block Diagram of Serial Interface Channel 0 2 2 b uPD78005xY nternal bus Y SIO SBO SDAO P25 Output SO0 SB1 SDA1 P26 C gt j 4 q Serial I O shift register 0 SIOO Selector Acknowledge output circuit Selector Start condition stop condition acknovvledge detector nterrupt 75 INTCSIO ial laa signal SCKO SCL P27 o D e Serial clock counter generator fxx 2 to 2 TO2 Serial clock lt controller Figure 5 11 Block Diagram of Serial Interface Channel 1 Internal bus Buffer RAM Serial I O shift register 1 SIO1
22. 12C components conveys a license under the Philips I2C Patent Rights to use these components in an 12C system provided that the system conforms to the 12C Standard Specification as defined by Philips FIP and IEBus are trademarks of NEC Corporation Windows is either a registered trademark or trademark of Microsoft Corporation in the United States and or other countries PC AT is a trademark of IBM Corporation HP9000 series 700 and HP UX are trademarks of Hewlett Packard Company SPARCstation is a trademark of SPARC International Inc Solaris and SunOS are trademarks of Sun Microsystems Inc 80 Data Sheet U12182EJAVODS NEC PD780053 780054 780055 780056 780058 700538 780053Y 780054Y 780055Y 780056Y 780058BY Regional Information Some information contained in this document may vary from country to country Before using any NEC product in your application please contact the NEC office in your country to obtain a list of authorized representatives and distributors They will verify Device availability Ordering information Product release schedule Availability of related technical literature Development environment specifications for example specifications for third party tools and components host computers power plugs AC supply voltages and so forth e Network requirements In addition trademarks registered trademarks export restrictions and other legal issues may also vary from co
23. A D converter mode register ADM is 1 3 The current flowing to the AVrero pin when bit 7 CS of the A D converter mode register ADM is 0 A D Converter Characteristics PD780058 TA 40 to 85 C 2 7 to 5 5 V AVss Vss 0 V Parameter Conditions Resolution Overall errorNote 1 Conversion time Tconv Analog input voltage Vian Reference voltage AVRero AVnero current Inero When A D converter is operatingNote 2 When A D converter is not operatingNote 3 Notes 1 Excludes quantization error 1 2 LSB This value is indicated as a ratio to the full scale value FSR 2 The current flowing to the AVRero pin when bit 7 CS of the A D converter mode register ADM is 1 3 The current flowing to the AVrero pin when bit 7 CS of the A D converter mode register ADM is Caution The operating voltage range of the A D converter and D A converter of the uPD780058 is Von 2 7 to 5 5 V Data Sheet U12182EJ4VODS 65 NEC 0780053 780054 780055 780056 780058 780058B 780053Y 780054Y 780055Y 780056Y 780058BY D A Converter Characteristics uPD780053 780054 780055 780056 780058B 780053Y 780054Y 780055Y 780056Y 780058BY Ta 40 to 85 C Voo 1 8 to 5 5 V AVss Vss 0 V Parameter Conditions Resolution Overall error R 2 MQNote 1 R 4 MONote1 R 10 MONote1 Settling time C 30 pFNOfe 1 Aver 1 8 to 2 7 V Outp
24. ANI7 Input Independently connect to Vppo or Vsso via a resistor P20 SI1 Output Leave open P21 SO1 P22 SCK1 P23 STB TxD1 P24 BUSY RxD1 P25 Sl0 SBO SDAO P26 SO0 SB1 SDA1 P27 SCKO SCL P30 TOO P31 TO1 P32 TO2 P33 T11 P34 TI2 P35 PCL P36 BUZ P37 P40 ADO to P47 AD7 Input Independently connect to Vooo via a resistor Output Leave open 50 8 to P57 A15 Input Independently connect to Vono or Vsso via a resistor Output Leave open P60 to P63 Input Independently connect to Vooo via a resistor Output Leave open Pe4 RD Input Independently connect to Vooo or Vsso via a resistor P65 WR Output Leave open P66 WAIT P67 ASTB Remark uPD78005xY only Data Sheet U12182EJ4VODS 15 NEC Pin Name P70 SI2 RxDO 0780053 780054 780055 780056 780058 7900588 780053Y 780054Y 780055 Y 780056 Y 780058BY Table 3 1 Pin VO Circuit Type 2 2 VO Circuit Type P71 SO2 TxDO P72 SCK2 ASCK P120 RTPO to P127 RTP7 Recommended Connection Input Independently connect to Vooo or Vsso via a resistor Output Leave open P130 ANOO P131 ANO1 Input Independently connect to Vsso via a resistor Output Leave open RESET XT2 AVREFO AVRer AVss IC 16 Leave open Connect to Vsso Connect to Connect to Vsso
25. P121 RTP1 P71 SO2 TxDO 9 O P120 RTPO P72 SCK2 ASCK O O P37 20 9 O O P36 BUZ 21 801 O O P35 PCL P22 SCK1 O O 34 2 P23 STB TxD1 O P33 TH P24 BUSY RxD1 O O P32 TO2 P25 SIO SBO VSDA 0 O O P31 TO1 P26 SO0 SB1 VSDA 11 O O P30 TO0 P27 SCKO SCL O O P67 ASTB P40 ADO O O P66 WAIT P41 AD1 O O P65 WR 0 0 E 070 00 00 E E O 00 OOO 0 SSSSSHSLLLELLZZLZESE x 32 x SS SS 2 a e 3 d a a ZS d OG GC 5 E A 9 FO dO KLOD D Q OO o x Yo d d d x D D D 030 aD D LO o e D a a a a a D m mx aa Cautions 1 Connect the IC Internally Connected pin directly to Vsso or Vss 2 Connect the AVss pin to Vsso Remarks 1 1 uPD78005xY only 2 Whenthe microcontroller is used in applications where the noise generated inside the microcontroller needs to be reduced the implementation of noise reduction measures such as supplying voltage to Vppo and individually and connecting Vsso and Vss to different ground lines is recommended 8 Data Sheet U12182EJAVODS NEC PIN IDENTIFICATION A8 to A15 ADO to AD7 ANIO to ANI7 ANOO ANO1 ASCK ASTB AVnero AVREF1 AVss BUSY BUZ IC NTPO to INTP5 POO to P05 P07 P10 to P17 P20 to P27 P30 to P37 P40 to P47 P50 to P57 P60 to P67 P70 to P72 P120 to P127 P130 P131 Address bus Address data bus Analog input Analog output Asynchronous serial clock Address strobe Analog reference voltage Analog gr
26. SERIES LINEUP The products in the 78K 0 Series are listed below The names enclosed in boxes are subseries name dl Products in mass production E Products under development Y subseries products are compatible with 1 C bus Control 100 pin uPD78075B EMI noise reduced version of the uPD78078 100 pin 1PD78054 with timer and enhanced external interface 100 pin ROMless version of the 78078 100 pin 1 PD78078Y with enhanced serial I O and limited function 80 pin HPD78054 with enhanced serial 1 O 80 pin EMI noise reduced version of the uPD78054 80 pin PD78018F with UART and D A converter and enhanced I O 80 pin uPD780024A with expanded 64 pin uPD780034A with timer and enhanced serial 64 pin u PD780024A with enhanced A D converter 64 pin 780024 uPD780024AY LA PD78018F with enhanced serial I O 64 pin uPD78014H EMI noise reduced version of the PD78018F 64 pin uPD78018F uPD78018FY Basic subseries for control 42 44 pin uPD78083 On chip UART capable of operating at lovv voltage 1 8 V nverter control 64 pin uPD780988 On chip inverter control circuit and UART EMl noise reduced VFD drive 100 pin uPD78044F with enhanced I O and VED C D Display output total 53 25 80 pin For panel control On chip VFD C D Display output total 53 80 pin Lu PD78044F with N ch open drain I O Display output total 34 E 80 pin Basic subseries for driving
27. U12182EJ4VODS NEC 3 2 Non Port Pins 1 2 Pin Name INTPO INTP1 INTP2 INTP3 INTP4 INTP5 Function External interrupt request input for which the valid edge rising edge falling edge or both rising edge and falling edges can be specified 0780053 780054 780055 780056 780058 7900588 780053Y 780054Y 780055 Y 780056 Y 780058BY Alternate Function POO TIOO P01 TIO1 P02 P03 P04 P05 SIO SH s z Serial interface serial data input P25 SB0 SDAO P20 P70 RxD 500 501 502 Output Serial interface serial data output P26 SB1 SDA1 P21 P71 TxD SBO SB1 SDAO SDA1 Serial interface serial data input output P25 Sl0 SDAO P26 S00 SDA1 uPD78005XY only P25 SI0 SBO P26 SO0 SB1 SCKO SCK1 SCK2 SCL Serial interface serial clock input output P27 SCL P22 P72 ASCK HPD78005xY only P27 SCKO STB Output Serial interface automatic transmit receive strobe output P23 TxD1 BUSY Input Serial interface automatic transmit receive busy input P24 RxD1 RxDO RxD1 Input Asynchronous serial interface serial data input P70 SI2 P24 BUSY TxDO TxD1 Output Asynchronous serial interface serial data output P71 SO2 P23 STB ASCK Input Asynchronous serial interface serial clock input P72 SCK2 TIOO TIO1 TH TI2 Input External count clock input to the 16 bit timer TMO POO INTPO
28. When used as an input port an on chip pull up resistor can be specified by software LEDs can be driven directly P60 to P63 N ch open drain UO port Input output can be specified in 1 bit units On chip pull up resistor can be used by mask option LEDs can be driven directly P64 to P67 VO port Input output can be specified in 1 bit units When used as an input port an on chip pull up resistor can be specified by software Port 7 P70 to P72 port Input output can be specified in 1 bit units VVhen used as an input port an on chip pull up resistor can be specified by softvvare Port 12 P120 to P127 VO port Input output can be specified in 1 bit units VVhen used as an input port an on chip pull up resistor can be specified by softvvare Port 13 P130 P131 VO port Input output can be specified in 1 bit units VVhen used as an input port an on chip pull up resistor can be specified by softvvare 20 Data Sheet U12182EJAVODS NEC PD780053 780054 780055 780056 780058 7900568 780053Y 780054Y 780055Y 780056Y 780058BY 5 2 Clock Generator Two types of generators a main system clock generator and a subsystem clock generator are available The minimum instruction execution time can be changed 0 4 us 0 8 us 1 6 us 3 2 us 6 4 us 12 8 us 5 0 MHz operation with main system clock 122 us 32 768 kHz operation with subsystem clock Figure 5 1 Clock Generator Block Diagram XT1 P07 Subsy
29. channel 16 bit timer event counter 8 bit timer event counter Watch timer Watchdog timer Timer outputs 3 14 bit PWM output x 1 Clock output 19 5 kHz 39 1 kHz 78 1 kHz 156 kHz 313 kHz 625 kHz 1 25 MHz 2 5 MHz 5 0 MHz 5 0 MHz operation with main system clock 32 768 kHz 32 768 kHz operation with subsystem clock Buzzer output 1 2 kHz 2 4 kHz 4 9 kHz 9 8 kHz 5 0 MHz operation with main system clock Vectored Maskable Internal 13 External 6 interrupt Non maskable Internal 1 Sources Software 1 Test inputs Internal 1 external 1 Supply voltage Voo 1 8 to 5 5 V Operating ambient temperature TA 40 to 85 C Package e 80 pin plastic QFP 14 x 14 80 pin plastic TQFP fine pitch 12 x 12 Notes 1 uPD78005x only 2 uPD78005xY only Data Sheet U12182EJ4VODS NEC uPD780053 780054 780055 780056 780058 780058B 780053Y 780054Y 780055Y 780056Y 780058BY CONTENTS 1 PIN CONFIGURATION TOP 55555 2 suas sanas nsn rra 8 2 DIAGRAM U cla AR re o EE BALA diana s d as 10 33 PIN FUNCTION O 00 TTH42ontUUULUU dios 11 3 1 Port Pins A ai 11 3 2 NeomcRort RIAS et ee EEN ENEE ENEE ee ere Ee Ge 13 3 3 Pin VO Circuits and Recommended Connection of Unused Pins 15 4 ME
30. lt S lt lt lt lt lt lt lt 0 2 lt POO to P05 P20 P22 P24 to P27 P33 P34 P70 P72 RESET Von 2 7 to 5 5 V 0 2Vpp 0 15Vpp P60 to P63 4 5 V lt Voo lt 5 5 V 0 3Vpp 2 7 V lt Voo lt 4 5 V 0 2Vpp 0 1 1 X2 Von 2 7 to 5 5 V 0 4 0 2 XT1 P07 2 4 5 V lt Voo lt 5 5 V 0 2Vpp 2 7 V lt Voo lt 4 5 V 0 1 Note olciololdolololololo 0 1Vpp Output voltage high Voo 4 5 to 5 5 V lou 1 mA lou 100 uA Output voltage low P50 to P57 P60 to P63 Voo 4 5 to 5 5 V lo 15 mA e le lee le le leie le lee le Ise P01 to P05 P10 to P17 P20 to P27 P30 to P37 P40 to P47 P64 to P67 P70 to P72 P120 to P127 P130 P131 Voo 4 5 to 5 5 V lo 1 6 mA 580 SB1 SCKO Voo 4 5 to 5 5 V open drain pulled up R 1 kQ lo 400 uA Note When PO7 XT1 pin is used as P07 the inverse phase of P07 should be input to XT2 pin using an inverter Remark Unless specified otherwise the characteristics of alternate function pins are the same as those of port pins 42 Data Sheet U12182EJ4VODS NEC PD780053 780054 780055 780056 780058 7900558 780053Y 780054Y 780055Y 780056Y 780058BY DC Characteristics TA 40 to 85 C 1 8 to 5 5 V Parameter Conditions Input leakage Vin Von POO to P05 P10 to P17 P20 t
31. not using external device expansion function 1 000 Data Sheet U12182EJ4VODS NEC PD780053 780054 780055 780056 780058 7800588 780053Y 780054Y 780055Y 780056Y 780058BY AC Timing Measurement Points Excluding X1 XT1 Inputs 0 8Vpp Point of 0 8 0 2Voo a ur 0 2Voo Clock Timing Vru MIN Vins MAX XT input Vins MIN Vis MAX TI Timing Fr troo trito1 troo rIHo1 T100 TIO1 1 m TH TI2 Data Sheet U12182EJAVODS 59 NIE PD780053 780054 780055 780056 780058 7800588 780053Y 780054Y 780055Y 780056Y 780058BY Read Write Operation External fetch no wait A8 to A15 Higher 8 bit address ADO to AD7 tRDADH ASTH Le tRDAST ASTB RD Le ASTRD 9 4 RDL1 gt e RDH External fetch wait insertion A8 to A15 Higher 8 bit address ADO to AD7 8 bit address taps La RDD1 gt lt a tRDADH gt ADH ASTH ii lRDAST h ASTB RD Lei ASTRD 4 RDL1 gt gt RDH WAIT twrRD RDVVT1 gt twit E gt 60 Data Sheet U12182EJAVODS NEC 0780053 780054 780055 780056 780058 7600588 780053Y 780054Y 780055Y 780056Y 780058BY External data access no wait A8 to A15 Higher 8 bit addr
32. the clock output 19 5 kHz 39 1 kHz 78 1 kHz 156 kHz 313 kHz 625 kHz 1 25 MHz 2 5 MHz 5 0 MHz 5 0 MHz operation with main system clock 32 768 kHz 32 768 kHz operation with subsystem clock Figure 5 6 Block Diagram of Clock Output Controller fxx 2 fxx 2 fxx 23 bou2 Selector Synchronization Output controller O PCL P35 fxx 25 fxx 2 fxx 27 XT 5 5 Buzzer Output Controller Clocks with the following frequencies can be output as the buzzer output 1 2 kHz 2 4 kHz 4 9 kHz 9 8 kHz 5 0 MHz operation with main system clock Figure 5 7 Block Diagram of Buzzer Output Controller fxx 2 fxx 2 Selector Output controller O BUZ P36 fxx 2 24 Data Sheet U12182EJ4VODS NEC PD780053 780054 780055 780056 780058 7900588 780053Y 780054Y 780055Y 780056Y 780058BY 5 6 A D Converter An A D converter consists of eight 8 bit resolution channels is incorporated The following two types of the A D conversion operation startup methods are available Hardware start Software start Figure 5 8 Block Diagram of A D Converter Series resistor string ANIO P10 C Sample amp hold circuit e AVREFO r ANI1 P11 O Voltage comparator functions alternately ANI2 P12 O O I 1 as analog power supply ANI3 P13 O Tap AVss selector ANI4 P14 ANI5 P15 O ANI6 P16 0 ei Successive approximation i O ss ANI7 P
33. this product from Japan is regulated by the Japanese government To export this product may be prohibited without governmental license the need for which must be judged by the customer The export or re export of this product from a country other than Japan may also be prohibited without a license from that country Please call an NEC sales representative The information in this document is current as of August 2001 The information is subject to change vvithout notice For actual design in refer to the latest publications of NEC s data sheets or data books etc for the most up to date specifications of NEC semiconductor products Not all products and or types are available in every country Please check with an NEC sales representative for availability and additional information No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC NEC assumes no responsibility for any errors that may appear in this document NEC does not assume any liability for infringement of patents copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products No license express implied or otherwise is granted under any patents copyrights or other intellectual property rights of NEC or others Descriptions of circuits software and other related informatio
34. to 5 5 V Resonator Recommended Circuit Parameter Conditions Crystal IC XT2 XT1 Oscillation resonator frequency fxr Note 1 Oscillation Voo 4 5 to 5 5 V stabilization timeNote 2 External XT1 input clock frequency fxr Note 1 XT1 input uPD74HCU04 high lovv level vvidth fer Notes 1 Indicates only oscillator characteristics Refer to AC Characteristics for instruction execution time 2 Time required to stabilize oscillation after Von reaches oscillation voltage MIN Cautions 1 When using the subsystem clock oscillator wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance Keep the wiring length as short as possible Do not cross the wiring with the other signal lines Do not route the wiring near a signal line through which a high fluctuating current flows Always make the ground point of the oscillator capacitor the same potential as Vss Do not ground the capacitor to a ground pattern through which a high current flows Do not fetch signals from the oscillator 2 The subsystem clock oscillator is designed as a low amplitude circuit for reducing current consumption and is more prone to malfunction due to noise than the main system clock oscillator Particular care is therefore required with the wiring method when the subsystem clock is used Remark For the resonator selection and
35. to P17 ANOO ANO1 Output D A converter analog output P130 P131 AVREFo Input A D converter reference voltage input also used for analog power supply AVner nput D A converter reference voltage input AVss A D converter and D A converter ground potential Use at the same potential as Vsso System reset input Connecting crystal resonator for main system clock oscillation Connecting crystal resonator for subsystem clock oscillation Port block positive power supply Port block ground potential Positive power supply except for port and analog blocks Ground potential except for port and analog blocks 14 Internally connected Connect directly to Vsso or Vss1 Data Sheet U12182EJ4VODS NEC PD780053 780054 780055 780056 780058 7900588 780053Y 780054Y 780055Y 780056Y 780058BY 3 3 Pin I O Circuits and Recommended Connection of Unused Pins The I O circuit type of each pin and recommended connection of unused pins are shown in Table 3 1 For the I O circuit configuration of each type see Figure 3 1 Table 3 1 Pin I O Circuit Type 1 2 Pin Name 1 O Circuit Recommended Connection Type POO INTPO TIOO Connect to Vsso P01 INTP1 TIO1 Input Independently connect to Vsso via a resistor PO2 INTP2 Output Leave open P03 INTP3 P04 INTP4 P05 INTP5 7 1 Connect to P10 ANIO to P17
36. 0B Ta 40 to 85 C Vo 3 5 to 5 5 V Parameter ASTB high level width ASTH Conditions 0 85tcy 50 0780053 780054 780055 780056 780058 780058B 780053Y 780054Y 780055Y 780056Y 780058BY Address setup time taps 0 85tcy 50 Address hold time ADH 50 Time from address to data input 1 01 2 85 2n 80 tapp2 4 2n tcv 100 Time from RD to data input RDD1 2 2n tcv 100 RDD 2 85 2n 1 100 Read data hold time RDH 0 RD lovv level vvidth RDL1 2 2n 60 RDL 2 85 2n tcv 60 Time from RD to WAIT input RDVVT1 0 85tcy 50 RDVVT2 2tcv 60 Time from WR to WAIT input VVRVVT 2tcv 60 VVA T lovv level vvidth VVTL 1 15 2n tev 2 2n tcy Write data setup time twos 2 85 2n tcv 100 Write data hold time twDH 20 WR low level width twRL 2 85 2n tcy 60 Delay time from ASTB to RDJ ASTRD 25 Delay time from ASTB to WRU tasrwR 0 85tcy 20 Delay time from RD to ASTBT at external fetch tRDAST 0 85tcy 10 1 15tcy 20 Time from RDT to address hold at external fetch RDADH 0 85tcy 50 1 15tcy 50 Time from RDT to write data output RDVVD 40 Time from VVR to write data output VVRVVD 0
37. 17 register SAR 7 Edge INTAD INTP3 P03 O detector Controller INTP3 A D conversion result register ADCR Internal bus Data Sheet U12182EJ4VODS 25 NEC PD780053 780054 780055 780056 780058 7900588 780053Y 780054Y 780055Y 780056Y 780058BY 5 7 D A Converter A D A converter consisting of two 8 bit resolution channels is incorporated The conversion method is the R 2R resistor ladder method Figure 5 9 D A Converter Block Diagram ANOn Selector A CEG write E INTTMx D A conversion value set register n 1 DAMm DACSn D A converter mode register nternal bus 26 Data Sheet U12182EJAVODS NEC 0780053 780054 780055 780056 780058 7900588 780053Y 780054Y 780055Y 780056Y 780058BY 5 8 Serial Interfaces Three clocked serial interface channels are incorporated Serial interface channel 0 Serial interface channel 1 Serial interface channel 2 Table 5 3 Types and Functions of Serial Interface Function Serial Interface Channel 0 Serial Interface Channel 1 Serial Interface Channel 2 HPD78005x uPD78005xY 3 wire serial UO mode Y MSB LSB first switching V MSB LSB first switching V MSB LSB first switching possible possible possible 3 wire serial UO mode with Y MSB LSB first switching automatic transmit receive possible function SBI serial bus interface mode 4 MSB first
38. 2 Osaka Electronics Department TEL 81 6 6 244 6672 e For third party development tools see the Single Chip Microcontroller Development Tool Selection Guide U11069E The host machine and OS suitable for each software are as follows Host Machine OS PC EVVS PC 9800 series Japanese Windows HP9000 series 700 IHP UXTMI IBM PC AT compatibles SPARCstation SunOS Japanese English Windows SP78KO RA78K0 CC78K0 1D78K0 NS 1D78K0 SM78K0 RX78K0 Note DOS based software 76 Data Sheet U12182EJAVODS NEC PD780053 780054 780055 780056 780058 7800538 780053Y 780054Y 780055Y 780056Y 780058BY APPENDIX B RELATED DOCUMENTS The related documents indicated in this publication may include preliminary versions However preliminary versions are not marked as such Documents Related to Devices Document Name Document No 1PD780058 780058Y Subseries User s Manual U12013E uPD780053 780054 780055 780056 780058 780058B 780053Y 780054Y 780055Y 780056Y This document 780058BY Data Sheet 780053 780054 A 780055 A 780056 A 780058B A 780053Y A 780054Y A 780055Y A U15443E 780056Y A 780058BY A Data Sheet uPD78F0058 78F0058Y Data Sheet U12092E 78K 0 Series User s Manual Instruction U12326E 78K 0 Series Application Note Basic 11 U10182E Documents Related to Development Tools Software User s Manuals Document Name Document N
39. 5 780056 780058 780058B 780053Y 780054Y 780055Y 780056Y 780058BY 13 CHARACTERISTICS CURVES REFERENCE VALUES Supply current loo mA vs loo fx 5 0 MHz fxx 2 5 MHz 25 C PCC 00H 01H PCC 02H PCC 03H PCC 04H PCC 30H 1 HALT X1 oscillating XT1 oscillating 0 1 PCC BOH HALT X1 stopped XT1 oscillating 0 2 3 4 5 6 7 Supply voltage Voo V Data Sheet U12182EJAVODS 69 NEC 0780053 780054 780055 780056 780058 780058B 780053Y 780054Y 780055Y 780056Y 780058BY Voo vs loo fx fxx 5 0 MHz Ta 25 C 00H 01 02 03 04 30H HALT 1 oscillating Approximately the same curve XT1 oscillating 0 1 Supply current loo mA Tace E HALT X1 stopped XT1 oscillating 0 01 0 001 0 2 3 4 5 6 7 Supply voltage Von V 70 Data Sheet U12182EJAVODS NEC 0780053 780054 780055 780056 780058 7600538 780053Y 780054Y 780055Y 780056Y 780058BY 14 PACKAGE DRAWINGS 80 PIN PLASTIC QFP 14x14 detail of lead end rS
40. 5Y 780056Y 780058BY iii 2 wire serial UO mode SCKO Internal clock output Parameter Conditions SCKO cycle time 1 kO 2 7 V lt WVoo lt 5 5 V 1 600 C 100 pFNote 5 0 y lt Von lt 2 7V 3 200 4 800 SCKO high level width Voo 2 7 t0 5 5 V 1 2 160 1 2 190 SCKO low level width Voo 4 5 to 5 5 V tkcvs 2 50 1 2 100 580 SB1 setup time 4 5 V lt Voo lt 5 5 V 300 to SCKO1 2 7 V Voo lt 4 5 V 350 2 0 V lt Voo lt 2 7 V 400 500 SBO SB1 hold time 600 from SCKOT Delay time from SCKOL to SBO SB1 output Note R and C are the load resistance and load capacitance of the SCKO SBO and SB1 output lines iv 2 wire serial UO mode SCKO Internal clock input Symbol Conditions SCKO cycle time 2 7V lt Vo0 lt s5 5V 1 600 2 0 V lt Voo lt 2 7 V 3 200 4 800 SCKO high level width 2 7 V lt Voo lt 5 5 V 650 2 0 V lt Voo lt 2 7 V 1 300 2 100 SCKO low level width 2 7 V lt Voo lt 5 5 V 800 2 0 V lt Voo lt 2 7 V 1 600 2 400 SBO SB1 setup time Voo 2 0 to 5 5 V 100 to SCKOT 150 SBO SB1 hold time tkcv4 2 from SCKOT Delay time from SCKOJ R 1k0 4 5 V lt Voo lt 5 5 V to SBO SB1 output C 100 pFNote 2 0 V lt Von lt 4 5 V SCKO rise fall time tra tra When using external device expa
41. 78K 0 Series IE 70000 98 IF C Adapter used when PC 9800 series PC except notebook type is used as host machine C bus supported IE 70000 PC IF C Interface adapter when using IBM PC AT or compatible as host machine ISA bus supported 1E 780308 R EM Emulation board common to the uPD780308 Subseries EP 78230GC R Emulation probe for 80 pin plastic QFP GC 8BT type EP 78054GK R Emulation probe for 80 pin plastic TQFP GK 9EU type TGK 080SDVV Conversion adapter to connect the EP 78054GK R and a target system on which an 80 pin plastic TQFP GK 9EU type can be mounted EV 9200GC 80 Socket to be mounted on a target system board made for 80 pin plastic QFP GC 8BT ype 1D78K0 Integrated debugger for IE 78001 R A SM78KO 78K 0 Series common system simulator DF780058 5 Real time OS Device file for the uPD780058 780058Y Subseries RX78K0 Real time OS for the 78K 0 Series 6 Cautions on using development tools The ID78K0 NS ID78K0 and 5 78 are used in combination with the DF780058 The CC78K0 and RX78KO0 are used in combination with the RA78KO and DF780058 The FL PR3 FA 80GC 8BT FA80GK 9EU NP 80GC and NP 80GK are products of Naito Densei Machida Mfg Co Ltd TEL 81 45 475 4191 TGK 080SDW is a product made by TOKYO ELETECH CORPORATION For further information contact Daimaru Kogyo Ltd Tokyo Electronics Department TEL 81 3 3820 711
42. 85 C Voo 1 8 to 5 5 V a Serial interface channel 0 i 3 wire serial I O mode SCKO Internal clock output Parameter Conditions SCKO cycle time 4 5 V lt Voo lt 5 5 V 800 2 7 V lt Voo lt 4 5 V 1 600 2 0 V lt Voo lt 2 7 V 3 200 4 800 SCKO high low level tkH1 KL1 Von 4 5 to 5 5 V tkcy1 2 50 width tkcvi 2 100 SIO setup time 4 5 V lt Mons 5 5 V 100 to SCKOT 2 7 V Noe 4 5 V 150 2 0 V lt Voo 2 7 V 300 400 SIO hold time 400 from SCKOT Delay time from SCKOL C 100 pFNote to SOO output Note Cis the load capacitance of the SCKO and SOO output lines ii 3 wire serial I O mode SCKO External clock input Parameter Conditions SCKO cycle time 45V lt Vp lt 5 5V 2 7 V lt Voo lt 4 5 V 2 0 V lt Voo lt 2 7 V SCKO high low level tkH2 4 5 V lt Vppx 5 5 V width 2 7 V lt Voo lt 4 5 V 2 0 V lt Voo lt 2 7 V SIO setup time 2 0 V lt Voo lt 5 5 V to SCKOT SIO hold time from SCKOT Delay time from SCKOL C 100 pFNote Vpp 2 0 to 5 5V to SOO output SCKO rise fall time tre tte When using external device expansion function When not using external device expansion function Note C is the load capacitance of the SOO output line 50 Data Sheet U12182EJ4VODS NEC PD780053 780054 780055 780056 780058 7800588 780053Y 780054Y 79005
43. D converter analog input pins set port 1 to the input mode At this time on chip pull up resistors are automatically disconnected Remark 1 uPD78005xY only Data Sheet U12182EJ4VODS 11 NEC PD780053 780054 780055 780056 780058 7600538 780053Y 780054Y 780055Y 780056Y 780058BY 3 1 Port Pins 2 2 Pin Name Function Alternate Function P50 to P57 Port 5 A8 to A15 8 bit I O port LEDs can be driven directly Input output can be specified in 1 bit units When used as an input port an on chip pull up resistor can be specified by software Port 6 N ch open drain input 8 bit I O port Input output can be specifiedin output port An on chip pull 1 bit units up resistor can be specified by the mask option LEDs can be driven directly When used as an input port an on chip pull up resistor can be specified by software ASTB Port 7 SI2 RxDO 2 OT 602 00 nput output can be specified in 1 bit units VVhen used as an input port an on chip pull up resistor can be specified by SCK2 ASCK software P120 to P127 Port 12 RTPO to RTP7 8 bit I O port Input output can be specified in 1 bit units When used as an input port on chip pull up resistor can be specified by software P130 P131 Port 13 ANOO ANO1 2 bit I O port Input output can be specified in 1 bit units When used as an input port an on chip pull up resistor can be specified by software 12 Data Sheet
44. D780056Y uPD780058B uPD780058BY uPD780058 24 KB memory 1 High speed RAM 1 024 bytes Buffer RAM 32 bytes Expanded RAM None 1 024 bytes Memory space 64 KB General purpose registers 8 bits x 32 registers 8 bits x 8 registers x 4 banks Minimum instruction On chip minimum instruction execution time variable function execution VVhen main system time clock is selected 0 4 us 0 8 us 1 6 us 3 2 us 6 4 us 12 8 us 5 0 MHz operation When subsystem clock is selected 122 us 032 768 kHz operation Instruction set 16 bit operation Multiply divide 8 bits x 8 bits 16 bits 8 bits Bit manipulation set reset test Boolean operation BCD adjust etc ports Total 68 CMOS input 2 CMOS VO 62 N ch open drain UO 4 A D converter 8 bit resolution x 8 channels Operating voltage range Voo 1 8 to 5 5 V Voo 2 7 to 5 5 D A converter 8 bit resolution x 2 channels Operating voltage range Voo 1 8 to 5 5 V Vip 2 7 to 5 5 Serial interface e 3 wire serial l O 2 wire serial 1 5 1 2 C bus mode selectable 1 channel e 3 wire serial I O mode automatic data transmit receive function for up to 32 bytes provided on chip 1 channel 3 wire serial mode time division transfer function provided on chip selectable 1 channel Timers 1 channel 2 channels 1 channel 1
45. DATA SHEET MOS INTEGRATED CIRCUIT NEC 11PD780053 780054 780055 780056 780058 780058B 780053Y 780054Y 780055Y 780056Y 780058BY 8 BIT SINGLE CHIP MICROCONTROLLERS DESCRIPTION The uPD780053 780054 780055 780056 780058 and 780058B hereafter referred to as uPD78005x are products of the wPD780058 Subseries in the 78K 0 Series The uPD780053Y 780054Y 780055Y 780056Y and 780058BY hereafter referred to as uPD78005xY are products of the uPD780058Y Subseries in the 78K 0 Series These microcontrollers show a reduction in the EMI Electro Magnetic Interference noise generated internally compared to the conventional type the uPD78054 Subseries Also they have provided is an 8 bit resolution A D converter 8 bit resolution D A converter timers serial interfaces real time output ports interrupt functions and various other peripheral hardware The uPD780058Y Subseries is based on the uPD780058 Subseries but with the addition of an IC bus interface function supporting multi master Flash memory versions the uPD78F0058 and 78F0058Y and various development tools are also available Detailed function descriptions are provided in the following user s manuals Be sure to read them before designing uPD780058 780058Y Subseries User s Manual U12013E 78K 0 Series User s Manual Instruction U12326E FEATURES Program Memory Data Memory Part Number ROM Internal High Speed RAM Internal Buffer RAM Internal Ex
46. ECTION GUIDE Products 8 Packages X13769E Semiconductor Device Mounting Technology Manual C10535E Quality Grades on NEC Semiconductor Devices C11531E NEC Semiconductor Device Reliability Quality Control System C10983E Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge ESD C11892E Caution The related documents listed above are subject to change without notice Be sure to use the latest version of each document for designing 78 Data Sheet U12182EJAVODS NEC X PD780053 780054 780055 780056 780058 7600538 780053Y 780054Y 780055Y 780056Y 780058BY MEMO Data Sheet U12182EJ4VODS 79 NEC 0780053 780054 780055 780056 780058 7900588 780053Y 780054Y 780055Y 780056Y 780058BY NOTES FOR CMOS DEVICES PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note Strong electric field when exposed to a MOS device can cause destruction of the gate oxide and ultimately degrade the device operation Steps must be taken to stop generation of static electricity as much as possible and quickly dissipate it once when it has occurred Environmental control must be adequate When it is dry humidifier should be used It is recommended to avoid using insulators that easily build static electricity Semiconductor devices must be stored and transported in an anti static container static shielding bag or conductive material All test and measurement tools including work bench and floor should
47. MORY SPACE Uu us Goa eaa aaa a adsteeeteatascdacucsadsuadedeaddsuenteade adveavacccadacnveasceudebead cdeecs 19 5 PERIPHERAL HARDWARE FUNCTION FEATURES V 20 DM POS A EE 20 5 2 Glock Generator oii hcscputnsndnsnseposcsstnccundadessaccnetceetarsiupacestandurssadesasansedancdsuncubecccesstdassecesasdusvdasedvens 21 b Timer Eve nt Counter iii idad ada d 21 5 4 Clock Output Controller comision ii ei 24 5 5 Buzzer Output Controller oi idad 24 5 6 A D CONVOrEN ansia 25 LEY MIB SN CT EE 26 5 8 Serial Interfaces unio 27 5 9 Real Time Output dea 29 6 INTERRUPT AND TEST FUNCTIONS 522 as aaa 4444 a a 30 6 1 Interrupt FUNCTIONS 30 6 2 Test Functions a ainda 34 7 EXTERNAL DEVICE EXPANSION FUNCTION aa daa nan 35 8 STANDBY FUNCTION acidos 35 9 RESET FUNCTION EE 35 10 MASK OPTHON a A a s nd 36 t1 INSTRUCTION E WEE 37 12 ELECTRICAL SPECIFICATI O NG a a lla B n 39 13 CHARACTERISTICS CURVES REFERENCE VALUES 69 14 PACKAGE DRAWINGS a oro y Aaaa Aaaa aaz asa DOr REN 71 15 RECOMMENDED SOLDERING CONDITIONS occcnccccconononoononocononononon
48. Number Package HPD780053GC xxx 8BT HPD780053GK xxx 9EU HPD780054GC xxx 8BT HPD780054GK xxx 9EU HPD780055GC xxx 8BT HPD780055GK xxx 9EU HPD780056GC xxx 8BT HPD780056GK xxx 9EU HPD780058GC xxx 8BT HPD780058GK xxx 9EU HPD780058BGC xxx 8BT uPD780058BGK xxx 9EU HPD780053YGC xxx 8BT HPD780053YGK xxx 9EU uPD780054YGC xxx 8BT uPD780054YGK xxx 9EU HPD780055YGC xxx 8BT HPD780055YGK xxx 9EU HPD780056YGC xxx 8BT HPD780056YGK xxx 9EU uPD780058BYGC xxx 8BT uPD780058BYGK xxx 9EU 80 pin plastic QFP 14 x 14 80 pin plastic TQFP fine pitch 12 x 12 80 pin plastic QFP 14 x 14 80 pin plastic TQFP fine pitch 12 x 12 80 pin plastic QFP 14 x 14 80 pin plastic TQFP fine pitch 12 x 12 80 pin plastic QFP 14 x 14 80 pin plastic TQFP fine pitch 12 x 12 80 pin plastic QFP 14 x 14 80 pin plastic TQFP fine pitch 12 x 12 80 pin plastic QFP 14 x 14 80 pin plastic TQFP fine pitch 12 x 12 80 pin plastic QFP 14 x 14 80 pin plastic TQFP fine pitch 12 x 12 80 pin plastic QFP 14 x 14 80 pin plastic TQFP fine pitch 12 x 12 80 pin plastic QFP 14 x 14 80 pin plastic TQFP fine pitch 12 x 12 80 pin plastic QFP 14 x 14 80 pin plastic TQFP fine pitch 12 x 12 80 pin plastic QFP 14 x 14 80 pin plastic TQFP fine pitch 12 x 12 Remark xxx indicates ROM code suffix Data Sheet U12182EJ4VODS NEC PD780053 780054 780055 780056 780058 7900568 780053Y 780054Y 780055Y 780056Y 780058BY 78K 0
49. P57 P60 to P63 Peak value rms value 70 Total for P10 to P17 P20 to P27 Peak value 50 P40 to P47 P70 to P72 P130 P131 rms value 20 Total for PO1 to PO5 P30 to P37 Peak value 50 P64 to P67 P120 to P127 rms value 20 Operating ambient 40 to 85 temperature Storage 65 to 150 temperature Note rms value should be calculated as follows rms value Peak value x NDuty Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter That is the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded Data Sheet U12182EJAVODS 39 NEC PD780053 780054 780055 780056 780058 7900588 780053Y 780054Y 780055Y 780056Y 780058BY Main System Clock Oscillator Characteristics Ta 40 to 85 C 1 8 to 5 5 V Resonator Recommended Circuit Parameter Conditions Ceramic Oscillation Voo Oscillation resonator frequency fx Note 1 voltage range Oscillation After Von reaches stabilization timeNote 2 oscillation voltage range MIN Crystal Oscillation resonator frequency fx Note 1 Oscillation 4 5 to 5 5 V stabilization timeNote 2 External X1 input clock frequency fx Note 1 X1 input LPD74HCUO4 high
50. VFD Display output total 34 LCD drive 120 pin PD780308 with enhanced display function and timer Segment signal output 40 pins max 120 pin PD780308 with enhanced display function and timer Segment signal output 32 pins max 120 pin PD780308 with enhanced display function and timer Segment signal output 24 pins max 100 pin uPD78064 with enhanced SIO and expanded ROM and RAM 100 pin EMI noise reduced version of the uPD78064 100 pin Basic subseries for driving LCDs on chip UART Bus interface supported 100 pin uPD780948 On chip CAN controller 80 pin uPD78098B uPD78054 with IEBus controller 80 pin HPD780702Y _ On chip IEBus controller D 80 pin HPD780703Y On chip CAN controller 80 pin On chip controller compliant with J1850 Class 2 64 pin 4uPD780816 Specialized for CAN controller function 8 Meier control 100 pin uPD780958 For industrial meter control 80 pin uPD780852 On chip automobile meter controller driver 80 pin uPD780828B For automobile meter driver On chip DCAN controller Remark VFD Vacuum Fluorescent Display is referred to as FIPTM Fluorescent Indicator Panel in some documents but the functions of the two are the same Data Sheet U12182EJ4VODS 3 NEC 0780053 780054 780055 780056 780058 7600538 780053Y 780054Y 780055Y 780056Y 780058BY The major functional differences among the subseries are listed below Non Y subseries ROM Timer 10 Bit Serial Interface
51. ata retention supply current 1 8 V disconnected Subsystem clock stop and feed back resistor Release signal set time Oscillation stabilization vvait time Release by RESET Release by interrupt request Note Selection of 2 fxx and 21 fxx to 277 fxx is possible with bits O to 2 OSTSO to OSTS2 of the oscillation stabilization time selection register OSTS Remark fxx Main system cloc fx Main system cloc k frequency fx or fx 2 k oscillation frequency Data Retention Timing STOP Mode Release by RESET STOP instruction execution STOP mode Internal reset operation 1 Data retention mode Ser 4 tsREL HALT mode gt gt a Operating mode RESET La twait gt Data Retention Timing Standby Release Signal STOP Mode Release by Interrupt Request Signal Von A STOP instruction execution STOP mode HALT mode 1 Operating mode Data retention mode Ser 4 SREL gt Standby release signal Interrupt request Data Sheet U12182EJ4VODS lt lt twat 67 NEC 0780053 780054 780055 780056 780058 780058B 780053Y 780054Y 780055Y 780056Y 780058BY Interrupt Request Input Timing INTL c tINTH INTPO to INTP5 RESET Input Timing RSL RESET 68 Data Sheet U12182EJ4VODS NEC 0780053 780054 78005
52. be grounded The operator should be grounded using wrist strap Semiconductor devices must not be touched with bare hands Similar precautions need to be taken for PW boards with semiconductor devices on it HANDLING OF UNUSED INPUT PINS FOR CMOS Note No connection for CMOS device inputs can be cause of malfunction If no connection is provided to the input pins itis possible that an internal input level may be generated due to noise etc hence causing malfunction CMOS devices behave differently than Bipolar or NMOS devices Input levels of CMOS devices must be fixed high or low by using a pull up or pull down circuitry Each unused pin should be connected to Vop or GND with a resistor if it is considered to have a possibility of being an output pin All handling related to the unused pins must be judged device by device and related specifications governing the devices STATUS BEFORE INITIALIZATION OF MOS DEVICES Note Power on does not necessarily define initial status of MOS device Production process of MOS does not define the initial operation status of the device Immediately after the power source is turned ON the devices with reset function have not yet been initialized Hence power on does not guarantee out pin levels I O settings or contents of registers Device is not initialized until the reset signal is received Reset operation must be executed immediately after power on for devices having reset function Purchase of NEC
53. cuit emulator that combines IE 78K0 NS and IE 78K0 NS PA 12 70000 5 Power supply unit for IE 78KO NS and IE 78K0 NS A IE 70000 98 IF C Interface adapter used when a PC 9800 series PC except notebook types is used as the host machine C bus supported IE 70000 CD IF A PC card and interface cable used when a PC 9800 series notebook types PC is used as the host machine PCMCIA socket supported IE 70000 PC IF C Adapter necessary when an IBM PC AT or compatible is used as the host machine ISA bus supported IE 70000 PCI IF A Interface adapter necessary when using a PC with PCI bus as the host machine 12 780308 5 1 Emulation board common to the uPD780308 Subseries NP 80GC Emulation probe for 80 pin plastic QFP GC 8BT type NP 80GK Emulation probe for 80 pin plastic TQFP GK 9EU type TGK 080SDVV Conversion adapter to connect the NP 80GK and a target system board 80 pin plastic TQFP GK 9EU type can be mounted EV 9200GC 80 Socket to be mounted on a target system board made for 80 pin plastic QFP GC 8BT type 1D78K0 NS Integrated debugger for IE 78K0 NS SM78K0 System simulator common to the 78K 0 Series Data Sheet U12182EJ4VODS 75 NEC 0780053 780054 780055 780056 780058 7900568 780053Y 780054Y 780055Y 780056Y 780058BY When using the IE 78001 R A in circuit emulator IE 78001 R A In circuit emulator common to the
54. ditions For details of the recommended soldering conditions refer to the document Semiconductor Device Mounting Technology Manual C10535E For soldering methods and conditions other than those recommended below contact an NEC sales representative Table 15 1 Surface Mounting Type Soldering Conditions 1 2 uPD780053GC xxx 8BT uPD780054GC xxx 8BT uPD780055GC xxx 8BT uPD780056GC xxx 8BT uPD780058GC xxx 8BT HPD780058BGC xxx 8BT HPD780053YGC xxx 8BT HPD780054YGC xxx 8BT HPD780056YGC xxx 8BT 80 pin plastic QFP 14 x 14 80 pin plastic QFP 14 x 14 80 pin plastic QFP 14 x 14 80 pin plastic QFP 14 x 14 80 pin plastic QFP 14 x 14 80 pin plastic QFP 14 x 14 80 pin plastic QFP 14 x 14 80 pin plastic QFP 14 x 14 80 pin plastic QFP 14 x 14 uPD780055YGC xxx 8BT 80 pin plastic QFP 14 x 14 P Hu PD780058BYGC xxx 8BT 80 pin plastic QFP 14 x 14 Soldering Soldering Conditions Recommended Method Condition Symbol Infrared reflow Package peak temperature 235 C Time 30 seconds max IR35 00 2 at 210 C or higher Count Twice or less VPS Package peak temperature 215 C Time 40 seconds max VP15 00 2 at 200 C or higher Count Twice or less Wave soldering Soldering bath temperature 260 C or less Time 10 seconds max WS60 00 1 Count Once Preheating temperature 120 C max package surface temperature Partial heating Pin temperature 300 C or less
55. erating mode fxx 2 5 MHz Note 3 Vip 5 0 V 10 Note 1 Voo 3 0 V 10 Note 2 Voo 2 0 V 10 Note 2 5 0 MHz crystal oscillation operating mode fxx 5 0 MHz Note 4 Voo 5 0 V 10 Note 1 Voo 3 0 V 10 Note 2 5 0 MHz crystal oscillation HALT mode fxx 2 5 MHz Nete 3 Von 5 0 V 10 Peripheral functions operating Peripheral functions not operating pp 3 0 V 10 Peripheral functions operating Peripheral functions not operating pp 2 0 V 10 Peripheral functions operating Peripheral functions not operating 5 0 MHz crystal oscillation HALT mode fxx 5 0 MHz Note 4 pp 5 0 V 10 Peripheral functions operating Peripheral functions not operating pp 3 0 V 10 Peripheral functions operating Peripheral functions not operating 32 768 kHz crystal oscillation operating modeNote 6 Voo 5 0 V 10 Voo 3 0 V 10 Von 2 0 V 10 32 768 kHz erystal oscillation HALT modeNote 6 Voo 5 0 V 10 Von 3 0 V 10 Von 2 0 V 10 XT1 Voo STOP mode When feedback resistor is used Voo 5 0 V 10 Von 3 0 V 10 Von 2 0 V 10 XT1 STOP mode When feedback resistor is not used Von 5 0 V 10 Von 3 0 V 10 Von 2 0 V 10 Data Sheet U12182EJ4VODS NEC PD780053 780054 780055 780056
56. ess ADO to AD7 ASTH ASTB RD ASTRD a iRDWD WR tasrwR External data access wait insertion A8 to A15 Higher 8 bit address La Lower Hi Z ADO to AD7 8 bit m address taps m ADH ASTH ASTB a ASTRD RD a RDL gt iRDWD gt twos VVDVVR VVR a ASTVVR gt a VVRL W VVRADH gt VVAIT RDVVT2 ti twr VVRVVT twrL twrwR Data Sheet U12182EJAVODS 61 NEC 0780053 780054 780055 780056 780058 780058B 780053Y 780054Y 780055Y 780056Y 780058BY Serial Transfer Timing 3 wire serial I O mode KCYm KLm tkHm SCKO to SCK2 tsikm tksim tksom m 1 2 9 10 13 14 n 2 10 14 2 wire serial UO mode KCY3 4 SCKO tsiks 4 tksi3 4 Li tksos 4 gi 580 SB1 62 Data Sheet U12182EJAVODS NEC 0780053 780054 780055 780056 780058 780058B 780053Y 780054Y 780055Y 780056Y 780058BY SBI mode bus release signal transfer KCY5 6 KL5 6 kH5 6 ine jo SCKO 580 SB1 SBI mode command signal transfer KCY5 6 ES IAS tro SCKO SBO SB1 PC bus mode SCL tsiks SDAO SDA1 sBH SiKm m 7 8 Data Sheet U12182EJ4VODS sBk tsiks 6 ee 6 6 ksB 63 NEC uPD780053
57. et U12182EJAVODS 35 NEC PD780053 780054 780055 780056 780058 7900588 780053Y 780054Y 780055Y 780056Y 780058BY 10 MASK OPTION The uPD78005x and 78005xY have the following mask options Pull up resistor An on chip pull up resistor for P60 to P63 I O port can be specified in 1 bit units lt 1 gt Specifies on chip pull up resistor lt 2 gt Does not specify on chip pull up resistor 36 Data Sheet U12182EJAVODS NEC 0780053 780054 780055 780056 780058 7900588 780053Y 780054Y 780055Y 780056Y 780058BY 11 INSTRUCTION SET 1 8 bit instructions MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MULU DIVUW INC DEC ROR ROL RORC ROLC ROR4 ROL4 PUSH POP DBNZ Second laddr16 HL Byte addr16 Operand HL B HL C laddr16 PSVV DE HL HL Byte HL B HL C X C Note Except A Data Sheet U12182EJ4VODS 37 NEC PD780053 780054 780055 780056 780058 7900588 780053Y 780054Y 780055Y 780056Y 780058BY 2 16 bit instructions MOV XCHW ADDW SUBW CMPW PUSH POP INCW DECW Second Operand laddr16 First Operand MOVWNote sfrp saddrp laddr16 SP Note Only when rp BC DE or HL 3 Bit manipulation instructions MOV1 AND1 OR1 XOR1 SET1 CLR1 NOT1 BT BF BTCLR Second Operand saddr bit PSW bit HL bit CY addr16 No
58. ev 20 RDL 2 37 2n tor 20 Time from RD to WAIT input RDVVT1 tcy 200 RDVVT2 2tcy 200 Time from WR to WAIT input VVRVVT 2tcv 200 WAIT low level width twr 1 2n tcv 2 2n tcv Write data setup time twos 2 37 2n tev 100 Write data hold time twDH 20 WR low level width VVRL 2 37 2n tor 20 Delay time from ASTB to RD ASTRD 0 37tcy 50 Delay time from ASTB to WR tasrwR 1 37tcv 50 Delay time from RDT to ASTB at external fetch RDAST tcv 10 Time from RDT to address hold at external fetch RDADH tcv 50 Time from RDT to write data output RDVVD 0 37tcy 40 Time from VVR to write data output VVRVVD 0 120 Time from VVRT to address hold VVRADH tcy tcv 120 Delay time from WAIT to RD VVTRD 0 63tcy 350 2 63tcy 350 Delay time from WAITT to WRT Remarks 1 twrwR 0 63tcv 240 MCS Bit 0 of the oscillation mode selection register OSMS 2 63tcv 240 2 PCC2 to PCCO Bits 2 to 0 of the processor clock control register PCC 3 tcv 4 4 nindicates the number of waits Data Sheet U12182EJ4VODS 49 NEC 0780053 780054 780055 780056 780058 780058B 780053Y 780054Y 780055Y 780056Y 780058BY 3 Serial interface Ta 40 to
59. from SCKOT Delay time from SCKOJ 1 kO Voo 4 5 to 5 5 V to SBO SB1 output C 100 pFNote 580 SB1W from SCKOT txss SCKO from SBO 5814 tsek 980 SB1 high level width tse SBO SB1 low level width SBL SCKO rise fall time tre tre When using external device expansion function When not using external device expansion function Note R and C are the load resistance and load capacitance of the SBO and SB1 output lines 52 Data Sheet U12182EJAVODS NEC vii I4C bus mode SCL Internal clock output uPD78005xY only Parameter SCL cycle time SCL high level width SCL low level width SDAO SDA1 setup time to SCLT SDAO SDA1 hold time from 5814 Delay time from SCLJ to SDAO SDA1 output SDAO SDA1J from SCLT or SDAO SDA11 from SCL SCL from SDAO SDA1L SDAO SDA1 high level width Note R and C are the load resistance and load capacitance of the SCL SDAO and SDA1 output lines Conditions R 1 KO 2 7 V lt Voo lt 5 5 V 10 uPD780053 780054 780055 780056 780058 780058B 780053Y 780054Y 780055Y 780056Y 780058BY C 100 pFNote 2 0 V lt Voo lt 2 7 V 20 30 Voo 2 7 to 5 5 V tkcy7 160 tkcy7 190 Von 4 5 to 5 5 V tkcv 50 tkcy7 100 2 7 V lt Voo x 5 5 V 200 2 0 V lt Voo lt 2 7 V
60. h low level width 4 5 V lt Voo lt 5 5 V 2 7 V lt Voo lt 4 5 V 2 0 V lt Voo lt 2 7 V 91 setup time to SCK11 tski2 2 0 to 5 5 V 91 hold time from SCK11 tksi12 Delay time from 9 14 to SO1 tksoiz C 100 pFNete Vpp 2 0 to 5 5 V output SCK1 rise fall time tri2 triz When using external device expansion function When not using external device expansion function Note C is the load capacitance of the SO1 output line 56 Data Sheet U12182EJAVODS NEC PD780053 780054 780055 780056 780058 7800588 780053Y 780054Y 780055Y 780056Y 780058BY c Serial interface channel 2 i 3 wire serial I O mode SCK2 Internal clock output Parameter Conditions SCK2 cycle time tkcyis 4 5 V lt Voo lt 5 5 V 800 2 7 V lt Voo lt 4 5 V 1 600 2 0 V lt Voo lt 2 7 V 3 200 4 800 SCK2 high lovv level width 1 4 5 to 5 5 V txov18 2 50 us tkov13 2 100 SI2 setup time to SCK21 Io 4 5 V lt Voo lt 5 5 V 100 2 7 Vx V 4 5 V 150 2 0 V lt Voo lt 2 7 V 300 400 SI2 hold time from SCK21 tksi13 400 Delay time from SCK2J to SO2 tksos C 100 pFNete output Note C is the load capacitance of the SO2 output line 3 wire serial I O mode SCK2 External clock input Parameter Conditions SCK2 cycle time tkovia 4 5 V lt Voo lt 5 5 V 2 7 V lt
61. isted below Y subseries Function Subseries Nam Control uPD78078Y ROM Capacity 48 K to 60 K Timer 10 Bit uPD78070AY uPD780018AY 48 K to 60 K 780058 24 K to 60 K uPD78058FY 48 K to 60 K HPD78054Y 16 K to 60 K 16 BitWatch A D uPD780078Y 48 K to 60 K uPD780034AY uPD780024AY 8Kto 32K uPD78018FY 8 K to 60 K Serial Interface 3 ch UART 1 ch 12C 1 ch 3 ch 2 1ch 3 ch time division UART 1 ch FC 1 ch 3 ch UART 1 ch BC 1 ch 4 ch UART 2 ch 12C 1 ch 3 ch UART 1 ch 12C 1 ch 2 ch 12 1 ch 0780053 780054 780055 780056 780058 7900588 780053Y 780054Y 780055Y 780056 780058BY External Expansion LCD HPD780308Y 48 K to 60 K drive uPD78064Y 16 K to 32 K 3 ch time division UART 1 ch 20 1 ch 2 ch UART 1 ch 12C 1 ch Bus uPD780701Y interface uPD780703Y supported uPD780833Y Remark Functions other than the serial interface are common to both the Y and non Y subseries 60 K Data Sheet U12182EJ4VODS 4 ch UART 1 ch 12C 1 ch NEC 0780053 780054 780055 780056 780058 780058B 780053Y 780054Y 780055Y 780056Y 780058BY OVERVIEW OF FUNCTIONS Product Name Internal ROM 4PD780053 uPD780054 uPD780055 uPD780056 uPD780053Y uPD780054Y uPD780055Y uP
62. n _ 16 bit timer counter fxx 2 TMO fxx 2 Edge detector 100 O Match s INTTMO1 gt INTPO 16 bit capture compare register CRO1 Internal bus Figure 5 3 Block Diagram of 8 Timer Event Counter Internal bus Y m R INTTM1 8 bit compare register CR10 8 bit compare register CR20 Match i G TO2 P32 Match fxx 2 to fxx 29 INTTM2 8 bit timer fx 2 counter 1 TM1 8 bit timer TI1 P33 counter 2 TM2 Clear fxx 2 to fxx 29 fy2 Selector TI2 P34 O Output TO1 P31 9 Y Internal bus 22 Data Sheet 12182 4 NEC 0780053 780054 780055 780056 780058 7900588 780053Y 780054Y 780055Y 780056Y 780058BY Figure 5 4 Block Diagram of Watch Timer xx 27 Selector I Prescaler fxr Selector gt INTTM3 gt To 16 bit timer event counter Figure 5 5 Block Diagram of Watchdog Timer INTWDT maskable interrupt request RESET 8 bit counter INTWDT non maskable interrupt request Data Sheet U12182EJAVODS 23 NEC PD780053 780054 780055 780056 780058 7900588 780053Y 780054Y 780055Y 780056Y 780058BY 5 4 Clock Output Controller Clocks with the following frequencies can be output as
63. n in this document are provided for illustrative purposes in semiconductor product operation and application examples The incorporation of these circuits software and information in the design of customer s equipment shall be done under the full responsibility of customer NEC assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits software and information While NEC endeavours to enhance the quality reliability and safety of NEC semiconductor products customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely To minimize risks of damage to property or injury including death to persons arising from defects in NEC semiconductor products customers must incorporate sufficient safety measures in their design such as redundancy fire containment and anti failure features NEC semiconductor products are classified into the following three quality grades Standard Special and Specific The Specific quality grade applies only to semiconductor products developed based on a customer designated quality assurance program for a specific application The recommended applications of a semiconductor product depend on its quality grade as indicated below Customers must check the quality grade of each semiconductor product before using it in a particular application Standard Computers office equipment communications equipment test a
64. nd measurement equipment audio and visual equipment home electronic appliances machine tools personal electronic equipment and industrial robots Special Transportation equipment automobiles trains ships etc traffic control systems anti disaster systems anti crime systems safety equipment and medical equipment not specifically designed for life support Specific Aircraft aerospace equipment submersible repeaters nuclear reactor control systems life support systems and medical equipment for life support etc The quality grade of NEC semiconductor products is Standard unless otherwise expressly specified in NEC s data sheets or data books etc If customers wish to use NEC semiconductor products in applications not intended by NEC they must contact an NEC sales representative in advance to determine NEC s willingness to support a given application Note 1 NEC as used in this statement means NEC Corporation and also includes its majority owned subsidiaries 2 NEC semiconductor products means any semiconductor product developed or manufactured by or for NEC as defined above M8E 00 4
65. ne First Operand sfr bit saddr bit 4 Call instruction branch instructions CALL CALLF CALLT BR BC BNC BZ BNZ BT BF BTCLR DBNZ Second Operand laddr16 laddr11 addr5 addr16 First Operand Basic instruction Compound instruction 5 Other instructions ADJBA ADJBS BRK RET RETI RETB SEL NOP El DI HALT STOP 38 Data Sheet U12182EJAVODS NEC PD780053 780054 780055 780056 780058 7900598 780053Y 780054Y 780055Y 780056Y 780058BY 12 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings Ta 25 C Parameter Conditions Ratings Supply voltage 0 3 to 46 5 AVRero 0 3 to Voo 0 3 Aner 0 3 to Voo 0 3 AVss 0 3 to 0 3 nput voltage Vit POO to P05 P07 P10 to P17 P20 to P27 P30 to P37 0 3 to Voo 0 3 P40 to P47 P50 to P57 P64 to P67 P70 to P72 P120 to P127 P130 P131 X1 X2 XT2 RESET P60 to P63 N ch open drain 0 3 to 16 Output voltage 0 3 to Voo 0 3 Analog input voltage P10 to P17 Analog input pin AVss 0 3 to AVrero 0 3 Output Per pin 10 current nign Total for P01 to P05 P30 to P37 P56 P57 P60 to P67 15 P120 to P127 Total for P10 to P17 P20 to P27 P40 to P47 15 P50 to P55 P70 to P72 P130 P131 Output Per pin Peak value 30 current low rms value 15 Total for P50 to P55 Peak value rms value Total for P56
66. nsion function When not using external device expansion function Note R and C are the load resistance and load capacitance of the SBO and SB1 output lines Data Sheet U12182EJ4VODS 51 NEC 0780053 780054 780055 780056 780058 780058B 780053Y 780054Y 780055Y 780056Y 780058BY v SBI mode SCKO Internal clock output uPD78005x only Parameter Conditions SCKO cycle time 4 5 V Von 5 5 V 800 2 0 V lt Voo lt 4 5 V 3 200 4 800 SCKO high low level tkus 4 5 V lt Voo lt 5 5 V tkcys 2 50 width tkcvs 2 150 SBO SB1 setup time 4 5 V lt Voo lt 5 5 V 100 to SCKOT 2 0 V Voo lt 4 5 V 300 400 SBO SB1 hold time tkcvs 2 from SCKOT Delay time from SCKOJ R 1 kO Voo 4 5 to 5 5 V to SBO SB1 output C 100 pFNote SBO SB1 from SCKOT SCKOJ from 580 8811 580 581 high level width SBO 581 low level width Note Rand C are the load resistance and load capacitance of the SCKO SBO and SB1 output lines vi SBI mode SCKO External clock input uPD78005x only Parameter Conditions SCKO cycle time 4 5 V lt Voo lt 5 5 V 800 2 0 V lt Voo lt 4 5 V 3 200 4 800 SCKO high low level tkue tis 4 5 V lt Voo lt 5 5 V 400 width 2 0 V lt Voo lt 4 5 V 1 600 2 400 580 SB1 setup time 4 5 V lt Voo lt 5 5 V 100 to SCKOT 2 0 V lt Voo lt 4 5 V 300 400 SBO SB1 hold time tkcve 2
67. o RA78KO Assembler Package Operation U14445E Assembly Language U14446E Structured Assembly Language U11789E 78 0 C Compiler Operation U14297E Language U14298E SM78KOS SM78KO System Simulator Ver 2 10 or Later Operation U14611E VVindovvs Based SM78K Series System Simulator Ver 2 10 or Later External Part User Open U15006E nterface Specifications 1D78K0 NS Integrated Debugger Ver 2 00 or Later Operation U14379E Windows Based ID78KO Integrated Debugger Windows Based Reference U11539E Guide U11649E RX78KO Real Time OS Fundamental U11537E Installation U11536E Project Manager Ver 3 12 or Later Windows Based U14610E Caution The related documents listed above are subject to change without notice Be sure to use the latest version of each document for designing Data Sheet U12182EJ4VODS 77 NEC PD780053 780054 780055 780056 780058 7900568 780053Y 780054Y 780055Y 780056Y 780058BY Documents Related to Development Tools Hardware User s Manuals Document Name Document No IE 78K0 NS In Circuit Emulator U13731E IE 78K0 NS A In Circuit Emulator U14889E IE 780308 NS EM1 Emulation Board U13304E IE 78001 R A In Circuit Emulator U14142E IE 780308 R EM Emulation Board U11362E Documents Related to Flash ROM Writing PG FP3 Flash Memory Programmer User s Manual U13502E Other Related Documents Document Name Document No SEMICONDUCTOR SEL
68. o P27 current high P30 to P37 P40 to P47 P50 to P57 P60 to P67 P70 to P72 P120 to P127 P130 P131 RESET X1 X2 1 07 2 P60 to P63 Input leakage POO to P05 P10 to P17 P20 to P27 current low P30 to P37 P40 to P47 P50 to P57 P64 to P67 P70 to P72 P120 to P127 P130 P131 RESET X1 X2 1 07 XT2 P60 to P63 Output leakage Vout Von current high Output leakage Vout 0 V current low Mask option pull up Vin 0 V P60 to P63 resistor Software pull up Vin OV PO1 to P05 P10 to P17 P20 to P27 resistor P30 to P37 P40 to P47 P50 to P57 P64 to P67 P70 to P72 P120 to P127 P130 P131 Note When pull up resistors are not connected to P60 to P63 specified by the mask option a low level input leakage current of 200 uA MAX flows only for 1 5 clocks without wait after a read instruction has been executed to port 6 P6 or port mode register 6 PM6 At times other than this 1 5 clock interval a 3 uA MAX current flows Remark Unless specified otherwise the characteristics of alternate function pins are the same as those of port pins Data Sheet U12182EJAVODS 43 NEC 0780053 780054 780055 780056 780058 780058B 780053Y 780054Y 780055Y 780056Y 780058BY DC Characteristics TA 40 to 85 C 1 8 to 5 5 V Parameter Power supply currentNote 5 44 Conditions 5 0 MHz crystal oscillation op
69. ononannananonnanaaananonananaaaanrnnanana 73 APPENDIX A DEVELOPMENT TOOLS ooccccccnconcocccnncononanonononananononnnonnanarnncnnannana cr nnn nana nnaman nnana 75 APPENDIX B RELATED 522 7 sa aa aa RR R44 a a sasa a a nan TT Data Sheet U12182EJ4VODS 7 NEC 0780053 780054 780055 780056 780058 7600538 780053Y 780054Y 780055Y 780056Y 780058BY 1 PIN CONFIGURATION TOP VIEW 80 pin plastic QFP 14 x 14 uPD780053GC xxx 8BT 780054GC xxx 8BT 780055GC xxx 8BT 780056GC xxx 8BT 780058GC xxx 8BT 780058BGC xxx 8BT 780053YGC xxx 8BT 780054YGC xxx 8BT 780055YGC xxx 8BT 780056YGC xxx 8BT 780058BYGC xxx 8BT 80 pin plastic TQFP fine pitch 12 x 12 uPD780053GK xxx 9EU 780054GK xxx 9EU 780055GK xxx 9EU 780056GK xxx 9EU 780058GK xxx 9EU 780058BGK xxx 9EU 780053Y GK xxx 9EU 780054 YGK xxx 9EU 780055Y GK xxx 9EU 780056 YGK xxx 9EU 780058BYGK xxx 9EU s aa oo EE Hz E e gt SZ S S 5 B ee ENE SS SS Sr 2 222222 a D e SS E Yo dq erz gran E FO rrr rs 6 QN Oo oo o DD DD D e x x gt aa E UO 9 Q QOO O6 O 769 D OO H O P05 H O P02 O P01 P00 80 79 78 P15 ANI5 O 1 O RESET P16 ANI6 O 2 O O P127 RTP7 P17 ANI7 O 3 O P126 RTP6 AVss O 4 O P125 RTP5 P130 ANO0 5 O P124 RTP4 P131 ANO1 O 6 O P123 RTP3 AVaer O 7 O P122 RTP2 P70 SI2 RxDO 8 O
70. ort When used as an input port an on chip pull up P02 resistor can be specified by software INTP3 Input output can be specified in 1 bit units INTP1 TIO1 INTP2 P04 INTP4 Po5 INTP5 PO7Note 1 Input only XT1 P10 to P17 Port 1 ANIO to ANI7 8 bit I O port Input output can be specified in 1 bit units When used as an input port an on chip pull up resistor can be specified by softwareNote 2 P20 Port 2 Si P21 8 bit 1 O port nput output can be specified in 1 bit units VVhen used as an input port an on chip pull up resistor can be SCK1 P23 specified by software STB TxD1 SO1 P22 P24 BUSY RxD1 P25 SIO SBO SDAO P26 S00 SB1 SDA1 P27 SCKO SCL P30 Port 3 TOO P31 8 bit I O port Input output can be specified in 1 bit units When used as an input port an on chip pull up resistor can be specified TO2 P33 by software TI P34 TI2 TO1 P32 P35 PCL P36 BUZ P37 P40 to P47 Port 4 ADO to AD7 8 bit I O port Input output can be specified in 8 bit units VVhen used as an input port an on chip pull up resistor can be specified by software The test input flag KRIF is set to 1 by falling edge detection Notes 1 When using the P07 XT1 pins as an input port set bit 6 FRC of the processor clock control register PCC to 1 Do not use the on chip feedback resistor of the subsystem clock oscillator 2 When using the P10 ANIO to P17 ANI7 pins as the A
71. oscillator constant customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation Capacitance TA 25 C Voo Vss 0 V Parameter Conditions Input f 1 MHz capacitance Unmeasured pins returned to 0 V VO f 1 MHz P01 to PO5 P10 to P17 capacitance Unmeasured pins returned P20 to P27 P30 to P37 to 0 V P40 to P47 P50 to P57 P64 to P67 P70 to P72 P120 to P127 P130 P131 P60 to P63 Remark Unless specified otherwise the characteristics of alternate function pins are the same as those of port pins Data Sheet U12182EJAVODS 41 NEC DC Characteristics TA 40 to 85 C Voo 1 8 to 5 5 V Parameter Input voltage high Conditions P10 to P17 P21 P23 P30 to P32 P35 to P37 P40 to P47 P50 to P57 P64 to P67 P71 P120 to P127 P130 P131 Von 2 7 to 5 5 V 0780053 780054 780055 780056 780058 780058B 780053Y 780054Y 780055Y 780056Y 780058BY POO to P05 P20 P22 P24 to P27 P33 P34 P70 P72 RESET Von 2 7 to 5 5 V P60 to P63 N ch open drain Von 2 7 to 5 5 V X1 X2 Von 2 7 to 5 5 V XT1 P07 XT2 4 5 V lt Voo lt 5 5 V 2 7 V lt Voo lt 4 5 V Note Input voltage low P10 to P17 P21 P23 P30 to P32 P35 to P37 P40 to P47 P50 to P57 P64 to P67 P71 P120 to P127 P130 P131 2 7 to 5 5 V 0 3Vpp lt E
72. ote 4 input high 2 7 V Von lt 3 5 V 2 fsam 0 2Note 4 low level width 2ffsam 0 5Note 4 INTP1 to INTP5 P40 to P47 2 7 to 5 5 V 10 20 RESET low 2 7 to 5 5 V 10 level width 20 Notes 1 Operation with main system clock fxx fx 2 when the oscillation mode select register OSMS is set to 00H 2 Operation with main system clock fxx 2 fx when OSMS is set to 01H 3 Value when external clock is used When a crystal resonator is used it is 114 us MIN 4 Selection of fsam fxx 2 fxx 32 fxx 64 and fxx 128 is possible with bits 0 and 1 SCS0 SCS1 ofthe sampling clock selection register SCS when N 0 to 4 Data Sheet U12182EJAVODS 45 NEC PD780053 780054 780055 780056 780058 7900588 780053Y 780054Y 780055Y 780056Y 780058BY Tcv vs Von fxx fx 2 main system clock operation Tcv vs Voo fxx fx main system clock operation 60 60 10 Y Operation guaranteed Y Operation m range guaranteed 2 2 range o o E 20 o gt gt 40 0 5 0 4 gl a PUE MNA LN ee 1 2 3 4 5 6 Supply voltage Von V Supply voltage Von V 46 Data Sheet U12182EJAVODS NEC 2 Read write operation a When MCS 1 2 to PCCO 00
73. ound Busy Buzzer clock nternally connected nterrupt from peripherals Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 12 Port 13 PCL RD RESET RTPO to RTP7 RxDO RxD1 SBO SB1 SCKO to SCK2 SCL SDAO SDA1 SIO to SI2 SO0 to S02 STB TIOO TIO1 TH TI2 TOO to TO2 TxDO TxD1 Vono 1 Vsso Vss1 WAIT WR X1 X2 XT1 XT2 Data Sheet U12182EJ4VODS 0780053 780054 780055 780056 780058 7900588 780053Y 780054Y 780055 Y 780056 Y 780058BY Programmable clock Read strobe Reset Real time output port Receive data Serial bus Serial clock Serial clock Serial data Serial input Serial output Strobe Timer input Timer input Timer output Transmit data Power supply Ground Wait Write strobe Crystal main system clock Crystal subsystem clock NEC 2 BLOCK DIAGRAM TO0 P30 TIOO INTPO POO TIO1 INTP1 PO1 TO1 P31 TI1 P33 TO2 P32 TI2 P34 SIO SBO SDAO P25 SOO SB1 SDA1 P26 SCKO SCL P27 911 20 SO1 P21 SCK1 P22 STB TxD1 P23 BUSY RxD1 P24 BUSY RxD1 P24 STB TxD1 P23 SI2 RxDO P70 SO2 TxDO P71 SCK2 ASCK P72 ANIO P10 to ANI7 P17 AVss AVRero ANOO P130 ANO1 P131 AVss AV REF1 INTPO POO to INTP5 P05 BUZ P36 PCL P35 Remarks 1 2 10 16 bit timer event counter 8 bit timer event counter 1 8 bit timer event counter 2 Watchdog timer
74. pansion RAM uPD780053 780053Y 1 024 bytes 32 bytes uPD780054 780054Y uPD780055 780055Y uPD780056 780056Y uPD780058B 780058BY 1 024 bytes 780058 Internal high capacity ROM amp RAM External memory expansion space 64 KB e Minimum instruction execution time can be changed from high speed 0 4 us to ultra low speed 122 us O ports 68 N ch open drain 4 e 8 bit resolution A D converter 8 channels Voo 1 8 to 5 5 VNete e 8 bit resolution D A converter 2 channels 1 8 to 5 5 V ete Serial interface 3 channels Timer 5 channels Supply voltage Voo 1 8 to 5 5 V Note The operation voltage of the A D converter and D A converter of the uPD780058 is Vop 2 7 to 5 5 V The information in this document is subject to change without notice Before using this document please confirm that this is the latest version Not all devices types available in every country Please check with local NEC representative for availability and additional information Document No U12182EJ4VODSOO0 4th edition The mark shows major revised points Date Published October 2001 N CP K Printed in Japan NEC Corporation 1997 2001 NEC PD780053 780054 780055 780056 780058 7600538 780053Y 780054Y 780055Y 780056Y 780058BY APPLICATIONS Car audio systems cellular phones pagers printers AV equipment cameras PPCs vending machines etc ORDERING INFORMATION Part
75. ption INTCSI2 End of serial interface channel 2 3 wire transfer INTST End of serial interface channel 2 UART transmission Notes 1 Defaultpriority isthe priority order when several maskable interrupt requests are generated simultaneously 0 is the highest order and 17 is the lowest 2 Basic configuration types A to E correspond to A to E in Figure 6 1 Remark There are two types of interrupt source for the watchdog timer Non maskable interrupts and maskable interrupts internal Only one of these interrupts can be selected 30 Data Sheet U12182EJAVODS NEC 0780053 780054 780055 780056 780058 7900588 780053Y 780054Y 780055Y 780056Y 780058BY Interrupt Type Maskable Note 1 Default Priority Table 6 1 Interrupt Source List 2 2 Interrupt Source INTTMS Trigger Reference time interval signalfrom watch timer INTTMOO Generation of match signal of 16 bit timer counter and capture compare register CROO INTTMO1 Generation of match signal of 16 bit timer counter and capture compare register CRO1 INTTM1 Generation of match signal of 8 bit timer event counter 1 INTTM2 Generation of match signal of 8 bittimer event counter 2 End of conversion by A D converter Internal External Internal Vector Table Address Basic Configuration TypeNete 2 Software Notes 1 Execution of BRK instruction
76. st applicable to control of stepper motors etc ASCK SCK2 P72 O 1 VES Figure 5 13 Block Diagram of Real Time Output Port Internal bus Real time output Real time output Output trigger buffer register buffer register controller higher 4 bits lower 4 bits RTBH Real time output port mode register RTPM Output latch Data Sheet U12182EJAVODS 29 NEC PD780053 780054 780055 780056 780058 7900588 780053Y 780054Y 780055Y 780056Y 780058BY 6 INTERRUPT AND TEST FUNCTIONS 6 1 Interrupt Functions The interrupt function includes three different kinds of interrupts from 21 sources as shown below Non maskable 1 Maskable 19 Software 1 Table 6 1 Interrupt Source List 1 2 Note 1 Default Interrupt Source nternal 1 Vector Table Basic TS External Address Configuration Priority Trigger TypeNote 2 nterrupt Type Non maskable INTWDT Watchdog timer overflow Internal with watchdog timer mode 1 selected Maskable INTWDT Watchdog timer overflow with interval timer mode selected INTPO Pin input edge detection External INTP1 INTP2 INTP3 INTP4 INTP5 INTCSIO End of serial interface channel 0 Internal transfer INTCSI1 End of serial interface channel 1 transfer INTSER Occurrence of serial interface channel 2 UART reception error INTSR End of serial interface channel 2 UART rece
77. stem clock XT2 oscillator XT gt Watch timer clock output function Prescaler X1 O Main system clock Clock to peripheral x2 oscillator hardvvare Prescaler te Scaler STOP 5 Standby Wait CPU clock controller controller fcru To INTPO sampling clock 5 3 Timer Event Counter Five timer event counter channels are incorporated 16 bit timer event counter 1 channel 8 bit timer event counter 2 channels Watch timer 1 channel Watchdog timer 1 channel Table 5 2 Operations of Timer Event Counter 16 Bit Timer 8 Bit Timer Watch Timer Watchdog Timer Event Counter Event Counter Operation Interval timer 1 channel 2 channels mode 1 channel 1 channel External event counter 1 channel 2 channels Function Timer output 1 output 2 outputs PWM output 1 output Pulse width measurement 1 input Square wave output 1 output 2 outputs One shot pulse output 1 output Interrupt request 2 2 Data Sheet U12182EJAVODS 21 NEC PD780053 780054 780055 780056 780058 7900588 780053Y 780054Y 780055Y 780056Y 780058BY Figure 5 2 Block Diagram of 16 Bit Timer Event Counter Internal bus INTP1 TI01 P01 INTP1 16 bit capture compare register M CROO INTTMOO PWM pulse Watch timer output O Too P30 output controller 2fxx Ta
78. untry to country NEC Electronics Inc U S Santa Clara California Tel 408 588 6000 800 366 9782 Fax 408 588 6130 800 729 9288 NEC Electronics Germany GmbH Duesseldorf Germany Tel 0211 65 03 02 Fax 0211 65 03 490 NEC Electronics UK Ltd Milton Keynes UK Tel 01908 691 133 Fax 01908 670 290 NEC Electronics Italiana s r l Milano Italy Tel 02 66 75 41 Fax 02 66 75 42 99 NEC Electronics Germany GmbH Benelux Office Eindhoven The Netherlands Tel 040 2445845 Fax 040 2444580 NEC Electronics France S A Velizy Villacoublay France Tel 01 3067 5800 Fax 01 3067 5899 NEC Electronics France S A Madrid Office Madrid Spain Tel 091 504 2787 Fax 091 504 2860 NEC Electronics Germany GmbH Scandinavia Office Taeby Sweden Tel 08 63 80 820 Fax 08 63 80 388 Data Sheet U12182EJ4VODS NEC Electronics Hong Kong Ltd Hong Kong Tel 2886 9318 Fax 2886 9022 9044 NEC Electronics Hong Kong Ltd Seoul Branch Seoul Korea Tel 02 528 0303 Fax 02 528 4411 NEC Electronics Singapore Pte Ltd Novena Square Singapore Tel 253 8311 Fax 250 3583 NEC Electronics Taiwan Ltd Taipei Taiwan Tel 02 2719 2377 Fax 02 2719 5951 NEC do Brasil S A Electron Devices Division Guarulhos SP Brasil Tel 11 6462 6810 Fax 11 6462 6829 J01 2 81 NEC 0780053 780054 700055 780056 780058 7000568 780053Y 780054Y 780055Y 780056Y 780058BY The export of
79. ut resistance Ro Note 2 Analog reference voltage AVREF1 AVrer current Joer Note 2 Resistance between AVner and AVss Range DACSO DACS1 55HNote 2 Notes 1 R and C are the D A converter output pin load resistance and load capacitance respectively 2 Value for one D A converter channel Remark DACSO and DACS1 D A conversion value setting registers 0 1 D A Converter Characteristics uPD780058 Ta 40 to 85 C Voo 2 7 to 5 5 V AVss Vss 0 V Parameter Conditions Resolution Overall error R 2 MQNote 1 R 4 MQNote 1 R 10 MQNote 1 Settling time C 30 prete 1 Output resistance Ro Note 2 Analog reference voltage AVnRer AVner current Joer Note 2 Resistance between AVner and AVss Ranger DACSO DACS1 55HNote 2 Notes 1 R and C are the D A converter output pin load resistance and load capacitance respectively 2 Value for one D A converter channel Remark DACSO and DACS1 D A conversion value setting registers 1 Caution The operating voltage range of the A D converter and D A converter of the uPD780058 is 2 7 to 5 5 V 66 Data Sheet U12182EJAVODS NEC 0780053 780054 780055 780056 780058 780058B 780053Y 780054Y 780055Y 780056Y 780058BY Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics Ta 40 to 85 C Parameter Data retention supply voltage Conditions D
80. x per pin row Note After opening the dry pack store it below 25 C and 65 RH for the allowable storage period Caution Do not use different soldering methods together except for partial heating 74 Data Sheet U12182EJAVODS NEC 0780053 780054 780055 780056 780058 780058B 780053Y 780054Y 780055Y 780056Y 780058BY APPENDIX A DEVELOPMENT TOOLS The following development tools are available for system development using the uPD780058 and 780058Y Subseries Also refer to 6 Cautions on using development tools 1 Software package SP78K0 CD ROM that integrates the development tools software common to the 78K 0 Series n one package 2 Language processing softvvare RA78K0 Assembler package common to the 78K 0 Series CC78K0 C compiler package common to the 78K 0 Series DF780058 Device file for the uPD780058 780058Y Subseries CC78K0 L C compiler library source file common to the 78K 0 Series 3 Flash memory writing tools Flashpro Il Part number FL PR3 PG FL3 Dedicated flash programmer for microcontrollers incorporating flash memory FA 80GC 8BT FA 80GK 9EU Adapter for flash memory writing 4 Debugging tools When using the IE 78K0 NS IE 78K0 NS A in circuit emulator IE 78K0 NS In circuit emulator common to the 78K 0 Series IE 78K0 NS PA Performance board to enhance and expand the functions of the IE 78K0 NS IE 78K0 NS A In cir
81. y combining this mode with the normal operation mode STOP mode n this mode oscillation of the main system clock is stopped All the operations performed on the main system clock are suspended and only the subsystem clock is used resulting in extremely small power consumption Figure 8 1 Standby Function Main system 5 Subsystem clock clock operation Ces 0 operationNote STOP HALT HALT 7 instruction instruction instruction Interrupt Interrupt request request HALT mode Clock supply to CPU is stopped oscillation continues HALT modeNote Clock supply to CPU is stopped oscillation continues STOP mode Main system clock oscillation stopped Note The current consumption can be reduced by stopping the main system clock When the CPU is operating on the subsystem clock set the MCC bit 7 of the processor clock control register PCC to stop the main system clock The STOP instruction cannot be used Caution When the main system clock is stopped and the system is operating on the subsystem clock wait until the oscillation stabilization time has been secured by the program before switching back to the main system clock Remark CSS Bit 4 of the processor clock control register PCC 9 RESET FUNCTION The following two reset methods are available External reset by RESET signal input Internal reset by watchdog timer program loop time detection Data She

uPD780053, 780054, 780055, 780056, 780058, 780058B, 780053Y

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