Technical Data Sheet
Contents
1. 13 Changes to Equation 1 and Equation 2 sse 13 Changes to Table 6 and Table 7 sse 13 Test oerte erant einst ve iet 12 Theory of Operation 13 Programming the Variable Resistor sss 13 Programming the Potentiometer 14 ESD Protection eec E E 14 Terminal Voltage Operating Range sse 14 Power Up Sequence seen 14 Layout and Power Supply Bypassing sss 14 Constant Bias to Retain Resistance Setting 15 Evaluation Board eene 15 IC Interface eco e ee ER 16 PC Compatible 2 Wire Serial Bus sss 16 O tline Dimensions nitent ertt rre e Rite 19 Ordering Guide 19 Added Figure 37 Changes to Equation 4 Deleted Readback Value Section 14 Deleted Level Shifting for Bidirectional Interface Section 14 Moved ESD Protection Section to Page 14 Changes to Figure 38 and Figure 39 sss 14 Moved Terminal Voltage Operating Range Section to Page 14 Changes to Figure 14 Moved Power Up Sequence Section to 14 Moved Layout and Power Supply Bypassing Section to Page 15 Added Constant Bias to Retai2. 32 64 96 128 160 192 CODE Decimal 224 256 03436 009 Figure 10 R INL vs Code vs Temperature Vpp 5 V 32 64 96 128 160 192 CODE Decimal 03436 010 Figure 11 R DNL vs Code vs Temperature Voo 5 V 2 5 o EN a e a 0 40 80 TEMPERATURE C Figure 12 Full Scale Error vs Temperature 03436 011 Rev B Page 9 of 20 ZSE ZERO SCALE ERROR pA 10 0 40 80 120 TEMPERATURE C 03436 012 Figure 13 Zero Scale Error vs Temperature 5 5V SUPPLY CURRENT uA M 27V 0 1 40 0 40 80 120 TEMPERATURE C 03436 013 Figure 14 Supply Current vs Temperature lA SHUTDOWN CURRENT nA 03436 014 TEMPERATURE Figure 15 Shutdown Current vs Temperature RHEOSTAT MODE TEMPCO ppm C 0 32 64 96 128 160 192 224 256 CODE Decimal 03436 015 Figure 16 Rheostat Mode Tempco ARws AT vs Code 160 140 120 100 80 60 40 20 POTENTIOMETER MODE TEMPCO ppm C 0 32 64 96 128 160 192 224 256 CODE Decimal 03436 016 Figure 17 Potentiometer Mode Tempco AVws AT vs Code REF LEVEL IDIV MARKER 1 000 000 000Hz 0 000dB 6 000dB MAG 8 918dB 0 80 42 0x40 0x20 0x10 0x08 0
3. Versions eer 4 Timing Characteristics eene edited en uen 5 5 10 50 100 Versions enn 5 Absolute Maximum Ratings seen 6 ESD Ca tion z citer HH HR EH OI eR 6 Pin Configuration and Function Descriptions s 7 Typical Performance Characteristics sees 8 REVISION HISTORY 1 06 Rev A to Rev B Changes to Table 3 Changes to Ordering Guide 3 04 Rev 0 to Rev A Updated Pormat tme rte er ete Universal Changes to Features aeree ate Re eee ete dta 1 Changes to Applications seen 1 Changes to Figure 1 Changes to Electrical Characteristics 5 Version 3 Changes to Electrical Characteristics 10 50 and i100 kO Versions none neue nee een de 4 Changes to Timing Characteristics sse 5 Changes to Absolute Maximum Ratings eee 6 Moved ESD Caution to Page eerte 6 Changes to Pin Configuration and Function Descriptions 7 Changes to Figures 22 and 23 sss Moved Figure 25 to Figure 26 Moved Figure 26 to Figure 27 Moved Figure 27 to Figure 25 sse Deleted Figures 31 and 2 Changes to Figure 32 Figure 33 and Figure 34 12 Changes to Rheostat Operation 13 Added
4. resistance 2 Package power dissipation Tmax Ta Qua ESD CAUTION ESD electrostatic discharge sensitive device Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection Although this product features Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability WARNING lt proprietary ESD protection circuitry permanent damage may occur on devices subjected to high energy Sprit Ate electrostatic discharges Therefore proper ESD precautions are recommended to avoid performance degradation or loss of functionality ESD SENSITIVE DEVICE Rev B Page 6 of 20 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 03436 002 Figure 3 Pin Configuration Table 5 Pin Function Descriptions Pin No Mnemonic Description 1 W Terminal GND lt Vw lt 2 Voo Positive Power Supply 3 GND Digital Ground 4 SCL Serial Clock Input Positive edge triggered Pull up resistor required 5 SDA Serial Data Input Output Pull up resistor required 6 ADO Programmable Address Bit 0 for Two Device Decoding 7 B B Termina
5. no connect 45 ppm C Wiper Resistance Rw Vpp 5V 50 120 Q DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE Specifications Apply to All VRs Differential Nonlinearity DNL 1 0 1 1 LSB Integral Nonlinearity INL 1 0 3 1 LSB Voltage Divider Temperature Coefficient AVw Vw AT x 10 Code 0x80 15 Full Scale Error Vwese Code OxFF 3 1 0 LSB Zero Scale Error VwzsE Code 0x00 0 1 3 LSB RESISTOR TERMINALS Voltage Range Va Ve Vw GND Vop V Capacitance A B Ca f 1 MHz measured to GND 90 pF code 0x80 Capacitance W Cw f 1 MHz measured to GND 95 pF code 0x80 Shutdown Supply Current la sp Voo 5 5 V 0 01 1 Common Mode Leakage Va Vs Vop 2 1 nA DIGITAL INPUTS AND OUTPUTS Input Logic High Vin Von 5V 2 4 V Input Logic Low Vit Voo 5V 0 8 V Input Logic High Vin Von 3V 2 1 V Input Logic Low Vit Vpp 3V 0 6 V Input Current li Vin OVor5V 1 Input Capacitance Ci 5 pF POWER SUPPLIES Power Supply Range VDD RANGE 2 7 5 5 V Supply Current 5 0 3 8 Power Dissipation Poiss 5 V or Vi O V Voo 5 V 44 uW Power Supply Sensitivity PSS Voo 5 V 10 0 02 0 05 code midscale DYNAMIC CHARACTERISTICS 8 Bandwidth 3 dB BW Ras 10 50 kO 100 600 100 40 kHz code 0x80 Total Harmonic Distortion THDw Va 1 V rms OV f 1 kHz 0 1 96 Ras 10 Vw Settling Time 10 kO 50 kO 100 ts Va 5 0 2 us 1 LSB err
6. 10 5 10k 100k 1M START 1 000 000Hz 60 BR PSRR dB HA N F LEVEL IDIV 000dB 0 500dB 5 1 026MHz 10 511kHz 50kO 101kHz 100 54kHz 50kO 5 100kQ 10kO Figure 22 3 dB Bandwidth Code 0x80 STOP 1 000 000 000Hz 10M 03436 021 CODE 0x80 Va Vg 0V PSRR Vpp DC 10 AC PSRR Vpp 5V DC 10 AC 100 1k 10k 100k 900 800 700 600 500 400 300 200 100 FREQUENCY Hz Figure 23 PSRR vs Frequency 1M 03436 022 0k 100k 1M FREQUENCY Hz Figure 24 lpp vs Frequency 03436 023 Rev B Page 11 of 20 Ch1 200mV By Ch2 5 00 M 100ns CH27 3 00 V Figure 25 Large Signal Settling Time Code OxFF 2 0x00 Ch1 100mV By Ch2 5 00 V Bw 200ns A CH1 152mV Figure 26 Digital Feedthrough Chi 5 00 By Ch2 5 00 V Bw 200 5 A CH1 3 00V Figure 27 Midscale Glitch Code 0x80 gt Ox7F SCL 03436 024 03436 025 03436 026 TEST CIRCUITS Figure 28 to Figure 34 illustrate the test circuits that define the test conditions used in the product specification tables Table 1 through Table 3 V
7. Vpp 1LSB V 2N Vus 03436 027 03436 031 Figure 28 Test Circuit for Potentiometer Divider Nonlinearity Error Figure 32 Test Circuit for Gain vs Frequency INL DNL NO CONNECT Rsw a DUT SW CODE 0x00 03436 028 03436 032 Figure 29 Test Circuit for Resistor Position Nonlinearity Error Figure 33 Test Circuit for Incremental On Resistance Rheostat Operation R INL R DNL 03436 029 03436 033 NC CONNECT Figure 34 Test Circuit for Common Mode Leakage Current V Vpp 10 PSRR dB 20 log AVpp AVus AVpp PSS 03436 030 Figure 31 Test Circuit for Power Supply Sensitivity PSS PSSR Rev B Page 12 of 20 THEORY OF OPERATION The AD5245 is a 256 position digitally controlled variable resistor VR device An internal power on preset places the wiper at midscale during power on which simplifies the fault condition recovery at power up PROGRAMMING THE VARIABLE RESISTOR Rheostat Operation The nominal resistance of the RDAC between Terminals A and B is available in 5 10 50 and 100 The nominal resistance Ras of the VR has 256 contact points accessed by the wiper terminal plus the B terminal contact The 8 bit data in the RDAC latch is decoded to select one of the 256 possible settings Figure 35 Rheostat Mode Configuration 03436 034 Assuming that a 10 part is used the wiper s firs
8. Hold Time Repeated START t2 After this period the first clock 0 6 us pulse is generated Low Period of SCL Clock ts 1 3 us High Period of SCL Clock t4 0 6 Us tsu sta Setup Time for Repeated START Condition ts 0 6 us Data Hold Time te 0 9 us tsupar Data Setup Time t 100 ns tr Fall Time of Both SDA and SCL Signals ts 300 ns tr Rise Time of Both SDA and SCL Signals to 300 ns tsusro Setup Time for STOP Condition tio 0 6 us 1 Typical specifications represent average readings at 25 C Voo 5 V Guaranteed by design and not subject to production test 3 See timing diagram Figure 44 for locations of measured values 4 Standard mode operation guaranteed by design Rev B Page 5 of 20 ABSOLUTE MAXIMUM RATINGS Ta 25 C unless otherwise noted Table 4 Parameter Value Voo to GND 0 3Vto 7V Va Ve Vw to GND Terminal Current A to B A to W to W Pulsed 20 mA Continuous 5 mA Digital Inputs and Output Voltage to GND OVto7V Operating Temperature Range 40 to 125 C Maximum Junction Temperature Timax 150 Storage Temperature Range 65 C to 150 C Lead Temperature Soldering 10 sec 245 Thermal Resistance Oja SOT 23 8 230 C W Maximum terminal current is bound by the maximum current handling of the switches maximum power dissipation of the package and maximum applied voltage across any two of the A B and W terminals at a given
9. input voltage at to B Unlike the polarity of Von to GND which must be positive voltage across A to B W to A and W to B can be at either polarity 03436 036 Figure 37 Potentiometer Mode Configuration If ignoring the effect of the wiper resistance for approximation then connecting the A terminal to 5 V and the B terminal to ground produces an output voltage at the wiper to B starting at 0 V up to 1 LSB less than 5 V Each LSB of voltage is equal to the voltage applied across Terminal A and B divided by the 256 positions of the potentiometer divider The general equation defining the output voltage at Vw with respect to ground for any valid input voltage applied to Terminals A and B is D 256 D V 3 256 1 8 more accurate calculation which includes the effect of wiper resistance Vw is Ryg D TOM A T AB R AB Rwa D y Vw D B 4 Operation of the digital potentiometer in the divider mode results in a more accurate operation over temperature Unlike the rheostat mode the output voltage is dependent mainly on the ratio of the internal resistors Rwa and Rws not the absolute values Therefore the temperature drift reduces to 15 ppm C ESD PROTECTION digital inputs are protected with a series of input resistors and parallel Zener ESD structures shown in Figure 38 and Figure 39 This applies to the digital input pins SDA SCL and ADO 03436 037 Figure 38 ESD Protec
10. of reset mode the RDAC remains at midscale The third MSB SD is a shutdown bit A logic high causes an open circuit at Terminal A while shorting the wiper to Terminal B This operation yields almost 0 in rheostat mode or 0 V in potentiometer mode It is important to note that the shutdown operation does not disturb the contents of the register When brought out of shutdown the previous setting is applied to the RDAC Also during shutdown new settings can be programmed When the part is returned from shutdown the corresponding VR setting is applied to the RDAC The remainder of the bits in the instruction byte are dont cares see Table 8 After acknowledging the instruction byte the last byte in write mode is the data byte Data is transmitted over the serial bus in sequences of nine clock pulses eight data bits followed by an acknowledge bit The transitions on the SDA line must occur during the low period of SCL and remain stable during the high period of SCL see Figure 45 In read mode the data byte follows immediately after the acknowledgment of the slave address byte Data is transmitted over the serial bus in sequences of nine clock pulses a slight difference with write mode in which eight data bits are followed by an acknowledge bit Similarly the transitions on the SDA line must occur during the low period of SCL and remain stable during the high period of SCL see Figure 46 After all data bits have been read
11. ANALOG 256 Position I2C Compatible DEVICES Digital Potentiometer FEATURES FUNCTIONAL BLOCK DIAGRAM 256 position Vpp End to end resistance 5 10 50 100 Compact SOT 23 8 2 9 mm x 3 mm package Fast settling time ts 5 us typ on power up Full read write of wiper register Power on preset to midscale Extra package address decode pin ADO Computer software replaces pC in factory programming applications Single supply 2 7 V to 5 5 V Low temperature coefficient 45 ppm C 03436 001 Low power loo 8 pA Wide operating temperature 40 C to 125 Evaluation board available PIN CONFIGURATION APPLICATIONS Mechanical potentiometer replacement in new designs LCD panel Vcom adjustment LCD panel brightness and contrast control Transducer adjustment of pressure temperature position Figure 2 chemical and optical sensors RF amplifier biasing Automotive electronics adjustment Gain control and offset adjustment 03436 002 GENERAL DESCRIPTION The AD5245 provides a compact 2 9 mm x 3 mm packaged Operating from a 2 7 V to 5 5 V power supply and consuming solution for 256 position adjustment applications These less than 8 allows usage in portable battery operated devices perform the same electronic adjustment function as applications mechanical potentiometers or variable resistors with enhanced Note that the terms digital potentiometer VR and RDAC are resolution sol
12. Differential Nonlinearity DNL 1 5 0 1 1 5 LSB Integral Nonlinearity INL 1 5 06 15 LSB Voltage Divider Temperature Coefficient AVw Vw AT x 10 Code 0x80 15 ppm C Full Scale Error Vwese Code OxFF 6 2 5 0 LSB Zero Scale Error Vwzse Code 0x00 0 2 6 LSB RESISTOR TERMINALS Voltage Range Va Vg Vw GND Voo V 1 MHz measured to GND Capacitance A B Ca code 0x80 90 pF f 1 MHz measured to GND Capacitance W Cw code 0x80 95 pF Shutdown Supply Current la sp Voo 5 5 V 0 01 1 Common Mode Leakage Icm Va Vs Vop 2 1 nA DIGITAL INPUTS AND OUTPUTS Input Logic High Vin Von 5V 2 4 V Input Logic Low Vit Vpp 5V 0 8 V Input Logic High Vin Von 3V 2 1 V Input Logic Low Vit Vpp 3V 0 6 V Input Current li Vin OVor5V 1 Input Capacitance Ci 5 pF POWER SUPPLIES Power Supply Range VDD RANGE 2 7 5 5 V Supply Current Ipp Vu 25VorVi 0 3 8 Power Dissipation Poiss Viu 5V or Va OV Vo 5 V 44 uW Power Supply Sensitivity PSS Voo 5 V 10 code midscale 0 02 0 05 DYNAMIC CHARACTERISTICS Bandwidth 3 dB BW 5K Ras 5 code 0x80 1 2 MHz Total Harmonic Distortion THDw Va 1 V rms Vs O V f 1 kHz 0 1 Vw Settling Time ts Va 5 V Vs OV 1 LSB error band 1 us Resistor Noise Voltage Density Rwe 2 5 Rs 0 6 nV 4Hz 1 Typical specifications represent average readings at 25 C and Voo 5 V Resistor position nonlinearity error R INL
13. JZ100 R2 40 to 125 C 8 Lead SOT 23 RJ 8 DOK 100 k 250 AD5245BRJZ100 RL7 40 C to 125 C 8 Lead SOT 23 RJ 8 DOK 100k 3 000 AD5245EVAL Evaluation Board 17 Pb free part 2 The evaluation board is shipped with the 10 Ras resistor option however the board is compatible with all available resistor value options Rev B Page 19 of 20 NOTES Purchase of licensed PC components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips Patent Rights to use these components in an system provided that the system conforms to the Standard Specification as defined by Philips 2006 Analog Devices Inc All rights reserved Trademarks and ANALOG registered trademarks are the property of their respective owners C03436 0 1 06 B DEVICES www analog com Rev B Page 20 of 20
14. ONS INDICATOR 1 30 0005 015 2 038 e 0 22 E 2 90 BSC z 2 80 BSC 0 65 BSC 1 95 BSC 1 45 0 22 008 0 60 A m e 0 45 SEATING s 0 30 PLANE 0 COMPLIANT TO JEDEC STANDARDS MO 178 BA Figure 48 8 Lead Small Outline Transistor Package SOT 23 RJ 8 Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option Branding Ordering Quantity AD5245BRJ5 R2 40 to 125 C 8 Lead SOT 23 RJ 8 DOG 5k 250 AD5245BRJ5 RL7 40 to 125 C 8 Lead SOT 23 RJ 8 DOG 5k 3 000 AD5245BRJZ5 R2 40 C to 125 8 Lead SOT 23 RJ 8 DOG 5k 250 AD5245BRJZ5 RL7 40 to 125 C 8 Lead SOT 23 RJ 8 DOG 5k 3 000 AD5245BRJ10 R2 40 C to 125 C 8 Lead SOT 23 RJ 8 DOH 10k 250 AD5245BRJ10 RL7 40 C to 125 C 8 Lead SOT 23 RJ 8 DOH 10k 3 000 AD5245BRJZ10 R2 40 C to 125 8 Lead SOT 23 RJ 8 DOH 10k 250 AD5245BRJZ10 RL7 40 C to 125 C 8 Lead SOT 23 RJ 8 DOH 10k 3 000 AD5245BRJ50 R2 40 to 125 C 8 Lead SOT 23 RJ 8 DOJ 50k 250 AD5245BRJ50 RL7 40 to 125 C 8 Lead SOT 23 RJ 8 DOJ 50k 3 000 AD5245BRJZ50 R2 40 C to 125 8 Lead SOT 23 RJ 8 DOJ 50k 250 AD5245BRJZ50 RL7 40 C to 125 C 8 Lead SOT 23 RJ 8 DOJ 50k 3 000 AD5245BRJ100 R2 40 to 125 C 8 Lead SOT 23 RJ 8 DOK 100 k 250 AD5245BRJ100 RL7 40 to 125 C 8 Lead SOT 23 RJ 8 DOK 100 k 3 000 AD5245BR
15. ce of 100 Q is present Care should be taken to limit the current flow between W and B in this state to a maximum pulse current of no more than 20 mA Otherwise degradation or possible destruction of the internal switch contact can occur Similar to the mechanical potentiometer the resistance of the RDAC between the Wiper W and Terminal A also produces a digitally controlled complementary resistance Rwa When these terminals are used the B terminal can be opened Setting the resistance value for Rwa starts at a maximum value of resistance and decreases as the data loaded in the latch increases in value The general equation for this operation is 256 2 2 For Ras 10 the terminal open circuited the following output resistance Rwa is set for the indicated RDAC latch codes Table 7 Codes and Corresponding Rwa Resistance D Dec Rwa Q Output State 255 139 Full Scale 128 5 060 Midscale 1 9 961 1 LSB 0 10 060 Zero Scale Typical device to device matching is process lot dependent and can vary by up to 30 Because the resistance element is processed in thin film technology the change in Ras with temperature has a very low 45 ppm C temperature coefficient Rev B Page 13 of 20 05245 PROGRAMMING THE POTENTIOMETER DIVIDER Voltage Output Operation The digital potentiometer easily generates a voltage divider at wiper to B and wiper to A proportional to the
16. e S START condition Read P STOP condition RS Reset wiper to midscale 0x80 Acknowledge SD Shutdown connects wiper to B terminal and open circuits X Don t care A terminal but does not change contents of wiper register W Write D7 D6 D5 D4 D3 D2 D1 DO Data Bits 1 9 1 9 1 9 SCL 0 1 0 1 1 KRSXSDX XX XXXXXKX P7 ADE X 05 D3 02 ACK BY ACK BY ACK BY AD5245 AD5245 AD5245 START BY FRAME 1 FRAME 2 FRAME 3 STOP BY MASTER SLAVE ADDRESS BYTE INSTRUCTION BYTE DATA BYTE MASTER Figure 45 Writing to the RDAC Register 03436 044 SCL sA for s X 95 X X 02 X02 pori ACK BY NO ACK AD5245 BY MASTER 3 START BY pe FRAME 1 FRAME 2 STOPBY MASTER SLAVE ADDRESS BYTE RDAC REGISTER MASTER Figure 46 Reading Data from a Previously Selected RDAC Register in Write Mode Rev B Page 17 of 20 03436 043 Multiple Devices on One Bus Figure 47 shows two AD5245 devices on the same serial bus Each has a different slave address because the states of their ADO pins are different This allows the RDAC within each device to be written to or read from independently The master devices output bus line drivers are open drain pull downs a fully PC compatible interface Rev B Page 18 of 20 SDA SCL SDA SCL ADO ADO AD5245 Figure 47 Multiple AD5245 Devices on One Bus SDA SCL 03436 046 OUTLINE DIMENSI
17. evice the user can simply click the Read button The format of the read bits is shown in Table 9 Rev B Page 15 of 20 05245 26 INTERFACE 2 WIRE SERIAL BUS The 2 wire serial bus protocol operates as follows 1 The master initiates data transfer by establishing a START condition which is when a high to low transition on the SDA line occurs while SCL is high see Figure 45 The next byte is the slave address byte which consists of the 7 bit slave address followed by an R W bit this bit determines whether data is read from or written to the slave device The AD5245 has one configurable address bit ADO see Table 8 The slave whose address corresponds to the transmitted address responds by pulling the SDA line low during the ninth clock pulse this is termed the acknowledge bit At this stage all other devices on the bus remain idle while the selected device waits for data to be written to or read from its serial register If the R W bit is high the master reads from the slave device On the other hand if the R W bit is low the master writes to the slave device 2 In write mode the second byte is the instruction byte The first bit MSB of the instruction byte is a don t care The second MSB RS is the midscale reset A logic high on this bit moves the wiper to the center tap where Rwa Rws This feature effectively overwrites the contents of the register therefore when taken out
18. id state reliability and superior low temperature used interchangeably coefficient performance The wiper settings are controllable through an PC compatible digital interface which can also be used to read back the wiper register content ADO can be used to place up to two devices on the same bus Command bits are available to reset the wiper position to midscale or to shut down the device into a state of zero power consumption Rev B Information fumished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties that may result from its use Specifications subject to change without notice No One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A license is granted by implication or otherwise under any patent or patent rights of Analog Devices Tel 781 329 4700 www analog com Trademarks and registered trademarks are the property of their respective owners Fax 781 461 3113 2006 Analog Devices Inc All rights reserved 05245 TABLE OF CONTENTS F at tes ce tov 1 Applications R E 1 Functional Block Diagram serene 1 Pin Configuration tenentes 1 General Description seen 1 Revision History eene 2 Electrical Characteristics essen 3 SKO deinem ne dite ires 3 10 50 100
19. is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions R DNL measures the relative step change from ideal between successive tap positions Parts are guaranteed monotonic 3 Vas Von wiper Vw no connect 51 and DNL are measured at Vw with the RDAC configured as a potentiometer divider similar to a voltage output D A converter Va Von and Vs OV DNL specification limits of 1 LSB maximum are guaranteed monotonic operating conditions 5 Resistor Terminals A B and W have no limitations on polarity with respect to each other 6 Guaranteed by design and not subject to production test 7 Measured at the A terminal The A terminal is open circuited in shutdown mode 8 Poss is calculated from lbo CMOS logic level inputs result in minimum power dissipation All dynamic characteristics use Vpp 5 V Rev B Page 3 of 20 10 50 100 VERSIONS Vpp 5 V 10 or 3 1096 Va Vpp Vs 0 V 40 C lt lt 125 C unless otherwise noted Table 2 Parameter Symbol Conditions Min Typ Max Unit DC CHARACTERISTICS RHEOSTAT MODE Resistor Differential Nonlinearity R DNL Rwe VA no connect 1 0 1 1 LSB Resistor Integral Nonlinearity R INL Va no connect 2 0 25 2 LSB Nominal Resistor Tolerance ARas Ta 25 C 30 30 Resistance Temperature Coefficient ARas Rag AT x 10 Vas Wiper
20. l GND lt Vs lt 8 A A Terminal GND x Va lt Rev B Page 7 of 20 TYPICAL PERFORMANCE CHARACTERISTICS RHEOSTAT MODE INL LSB RHEOSTAT MODE DNL LSB POTENTIOMETER MODE INL LSB 0 32 64 96 128 160 192 224 256 CODE Decimal 03436 003 Figure 4 R INL vs Code vs Supply Voltages CODE Decimal 03436 004 Figure 5 R DNL vs Code vs Supply Voltages 40 C 25 85 C 125 0 32 64 96 128 160 192 224 256 CODE Decimal 03436 005 Figure 6 INL vs Code vs Temperature Voo 5 V Rev B Page 8 of 20 POTENTIOMETER MODE INL LSB POTENTIOMETER MODE DNL LSB POTENTIOMETER MODE DNL LSB 32 64 96 128 160 192 224 256 CODE Decimal Figure 7 DNL vs Code vs Temperature Voo 5 V CODE Decimal Figure 8 INL vs Code vs Supply Voltages CODE Decimal Figure 9 DNL vs Code vs Supply Voltages 03436 006 03436 007 03436 008 RHEOSTAT MODE INL LSB 5 b a N RHEOSTAT MODE DNL LSB FSE FULL SCALE ERROR LSB 1 0 0 8 0 6 0 4 40 C 25 85 C 125 0 2
21. n Resistance Setting Section 15 Added Eig re 42 eeepc ee b tt PREIS Added Evaluation Board Section sss Added A Moved Interface Section to Page Changes to I2C Compatible 2 Wire Serial Bus Section Moved Table 5 and Table 6 to Renumbered as Table 8 and Table 9 Moved Figure 36 Figure 37 and Figure 38 to Page 17 Renumbered as Figure 44 Figure 45 and Figure 46 Moved Multiply Devices on One Bus Section to Page 18 Updated Ordering Guide see 19 Updated Outline Dimensions seen 19 Moved Disclaimer to Page ees 20 5 03 Revision 0 Initial Version Rev B Page 2 of 20 ELECTRICAL CHARACTERISTICS 5 VERSION Vpp 5 V 1096 or 3 1096 Va Vpp Vs 0 V 40 C lt Ta lt 125 unless otherwise noted Table 1 Parameter Symbol Conditions Min Unit DC CHARACTERISTICS RHEOSTAT MODE Resistor Differential Nonlinearity R DNL Rwe VA no connect 1 5 01 1 5 LSB Resistor Integral Nonlinearity R INL Va no connect 4 0 75 4 LSB Nominal Resistor Tolerance ARas Ta 25 C 30 30 Resistance Temperature Coefficient ARag Rag AT x 10 Vas Voo wiper no connect 45 ppm C Wiper Resistance Rw 50 120 Q DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE Specifications Apply to All VRs
22. ntly biasing the potentiometer can be a practical approach Most portable devices do not require the removal of batteries for charging Although the resistance setting of the AD5245 is lost when the battery needs replacement such events occur rather infrequently so that this inconvenience is justified by the lower cost and smaller size offered by the AD5245 If total power is lost then the user should be provided with a means to adjust the setting accordingly EVALUATION BOARD An evaluation board along with all necessary software is available to program the AD5245 from any PC running Windows 98 2000 XP The graphical user interface as shown in Figure 43 is straightforward and easy to use More detailed information is available in the user manual which is provided with the board ADSMS Rev Fun SDA Write zi 327 soe Run EE ida jb 5 sle Iove Byte SDA Road Bit indicator Hit Read rm am Figure 43 AD5245 Evaluation Board Software Read 03436 042 The AD5245 starts at midscale upon power up To increment or decrement the resistance the user can simply move the scroll bars on the left To write a specific value the user should use the bit pattern in the upper screen and click the Run button The format of writing data to the device is shown in Table 8 To read the data from the d
23. or band Resistor Noise Voltage Density Rwe 5 Rs 0 9 nV 4Hz 1 Typical specifications represent average readings at 25 C and Voo 5 V Resistor position nonlinearity error R INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions R DNL measures the relative step change from ideal between successive tap positions Parts are guaranteed monotonic 3 Vas Wiper Vw no connect 51 and DNL are measured at Vw with the RDAC configured as a potentiometer divider similar to a voltage output D A converter Va Voo and Vs 0 V DNL specification limits of 1 LSB maximum are guaranteed monotonic operating conditions 5 Resistor Terminals B W have no limitations on polarity with respect to each other Guaranteed by design and not subject to production test 7 Poss is calculated from lbo x CMOS logic level inputs result in minimum power dissipation 8 All dynamic characteristics use Vpp 5 V Rev B Page 4 of 20 TIMING CHARACTERISTICS 5 10 KO 50 KO 100 KO VERSIONS Vpp 5 V 1096 or 3 1096 Va Vpp Vs 0 V 40 C lt lt 125 unless otherwise noted Table 3 Parameter Symbol Conditions Min Typ Max Unit INTERFACE TIMING CHARACTERISTICS 3 4 Specifications Apply to All Parts SCL Clock Frequency 400 kHz Bus Free Time Between STOP and START t 1 3 us tupsra
24. or written a STOP condition is established by the master A STOP condition is defined as a low to high transition on the SDA line while SCL is high In write mode the master pulls the SDA line high during the 10 clock pulse to establish a STOP condition see Figure 45 In read mode the master issues a no acknowledge for the ninth clock pulse that is the SDA line remains high The master then brings the SDA line low before the 10 clock pulse which goes high to establish a STOP condition see Figure 46 A repeated write function gives the user flexibility to update the RDAC output a number of times after addressing and instructing the part only once For example after the RDAC has acknowledged its slave address and instruction bytes in the write mode the RDAC output updates on each successive byte If different instructions are needed then the write read mode has to start again with a new slave address instruction and data byte Similarly a repeated read function of the RDAC is also allowed Rev B Page 16 of 20 Table 8 Write Mode S 0 1 O 1 1 0 W RS SD IX X X X X A 107 D6 05 02 Slave Address Byte Instruction Byte Data Byte Table 9 Read Mode S 0 1 0 31 1 0 R JA D7 D6 D5 D4 D3 D2 D1 00 Slave Address Byte Data Byt
25. t connection starts at the B terminal for Data 0x00 Because there is a 50 wiper contact resistance such a connection yields a minimum of 100 Q 2 x 50 resistance between Terminals W and B The second connection is the first tap point which corresponds to 139 Rws 256 2 x Rw 39 2 x 50 for Data 0x01 The third connection is the next tap point representing 178 Q 2 x 39 Q 2 x 50 for Data 0x02 and so on Each LSB data value increase moves the wiper up the resistor ladder until the last tap point is reached at 10 100 Q Ras 2 x Rw RDAC LATCH AND DECODER 03436 035 Figure 36 AD5245 Equivalent RDAC Circuit The general equation determining the digitally programmed output resistance between W and B is D Ry4 GD xR 2xXR 1 WB 256 AB Ww where D is the decimal equivalent of the binary code loaded in the 8 bit RDAC register is the end to end resistance Rwis the wiper resistance contributed by the on resistance of the internal switch In summary if Ras 10 and the A terminal is open circuited then the following output resistance Rws is set for the indicated RDAC latch codes Table 6 Codes and Corresponding Rws Resistance D Dec Rws Q Output State 255 9 961 Full Scale Ras 1 LSB Rw 128 5 060 Midscale 1 139 1 LSB 0 100 Zero Scale Wiper Contact Resistance Note that in the zero scale condition a finite wiper resistan
26. tion of Digital Pins A B W 03436 038 GND Figure 39 ESD Protection of Resistor Terminals TERMINAL VOLTAGE OPERATING RANGE The AD5245 Vp and GND power supply defines the boundary conditions for proper 3 terminal digital potentiometer operation Supply signals present on Terminals A B and W that exceed Vpp or GND are clamped by the internal forward biased diodes see Figure 40 Vpp OA OW OB 03436 039 GND Figure 40 Maximum Terminal Voltages Set by Voo and GND POWER UP SEQUENCE Because the ESD protection diodes limit the voltage compliance at Terminals A B and W see Figure 40 it is important to power Vpp and GND before applying any voltage to Terminals A B and W otherwise the diode is forward biased such that is powered unintentionally and can affect the rest of the users circuit The ideal power up sequence is the following order GND Vpn digital inputs and then Va Vs and Vw The relative order of powering Va Vs Vw and the digital inputs is not important as long as they are powered after and GND LAYOUT AND POWER SUPPLY BYPASSING Itis good practice to employ compact minimum lead length layout design The leads to the inputs should be as direct as possible with a minimum conductor length Ground paths should have low resistance and low inductance Similarly it is also good practice to bypass the power supplies with quality capacitors for optimum stability Supply leads
27. to the device should be bypassed with disk or chip ceramic capacitors of 0 01 uF to 0 1 uF Low ESR 1 uF to 10 pF tantalum or electrolytic capacitors should also be applied at the supplies to minimize any transient disturbance and low frequency ripple see Figure 41 Note that the digital ground should also be joined remotely to the analog ground at one point to minimize the ground bounce 03436 040 Figure 41 Power Supply Bypassing Rev B Page 14 of 20 CONSTANT BIAS RETAIN RESISTANCE SETTING For users who desire nonvolatility but cannot justify the additional cost for the EEMEM the AD5245 can be considered a low cost alternative by maintaining a constant bias to retain the wiper setting The AD5245 is designed specifically with low power in mind which allows low power consumption even in battery operated systems Figure 42 demonstrates the power consumption from a 3 4 V 450 mA hr Li Ion cell phone battery that is connected to the AD5245 The measurement over time shows that the device draws approximately 1 3 uA and consumes negligible power Over a course of 30 days the battery is depleted by less than 296 the majority of which is due to the intrinsic leakage current of the battery itself 110 108 106 104 102 100 98 96 BATTERY LIFE DEPLETED 94 92 90 03436 041 DAYS Figure 42 Battery Operating Life Depletion This demonstrates that consta
28. x04 0x02 0x01 1k 10k 100k 1M START 1 000 000Hz STOP 1 000 000 000Hz 03436 017 Figure 18 Gain vs Frequency vs Code Ras 5 Rev B Page 10 of 20 REF LEVEL IDIV MARKER 510 634 725Hz 0 000dB 6 000dB 9 049dB 0 0x80 6 2 0x40 0x20 0x10 24 0x08 30 0x04 36 0x02 42 0x01 48 54 60 1k 10k 100k 1M START 1 000 000Hz STOP 1 000 000 000Hz Figure 19 Gain vs Frequency vs Code Ras 10 REF LEVEL MARKER 100 885 289Hz 0 000dB 6 000dB 9 014dB 0 0 80 6 42 0x40 0x20 18 24 0x10 0x08 30 36 0x04 0x02 42 0 01 48 54 60 1k 10k 100k 1M START 1 000 000Hz STOP 1 000 000 000Hz Figure 20 Gain vs Frequency vs Code Ras 50 REF LEVEL IDIV MARKER 54 089 173Hz 0 000dB 6 000dB A R 9 052dB 0x80 0x40 0x20 0x10 0x08 36 0x04 42 0x02 0x01 48 54 60 1k 10k 100k 1M START 1 000 000Hz STOP 1 000 000 000Hz Figure 21 Gain vs Frequency vs Code Ras 100 03436 018 03436 019 03436 020 5 5 5 6 0 6 5 10 0
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