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78K/0S Series 8-Bit Single-Chip Microcontroller Instructions

1. User s Manual U11047EJ3VOUMOO 19 CHAPTER 1 MEMORY SPACE 1 4 CALLT Instruction Table Area In a 64 byte address area 0040H to 007FH the subroutine entry address of a 1 byte call instruction CALLT can be stored 1 5 Internal Data Memory Space The 78K 0S Series products incorporate the following data memory 1 Internal high speed RAM The 78K 0S Series products incorporate internal high speed RAM in the address space shown in Table 1 12 The internal high speed RAM is also used as a stack memory 2 LCD display RAM uPD789407A and uPD789417A Subseries LCD display RAM is allocated in the area between and FA1BH The LCD display RAM can also be used as ordinary RAM 3 EEPROM uPD789146 789156 789197AY 789217AY Subseries Electrically erasable PROM EEPROM is allocated in the address space shown in Table 1 12 Unlike ordinary RAM EEPROM retains the data it contains even when the power is turned off Also unlike EPROM the contents of EEPROM can be erased electrically without the need to expose the chip to ultraviolet light Table 1 12 Internal Data Memory Space of 78K 0S Series Products 1 2 Product Name High Speed RAM LCD Display RAM EEPROM uPD789014 FE80H to FEFFH Subseries uPD789042 128 bytes uPD78P9014 FEO0H to FEFFH 256 bytes uPD789026 607902 2 10 Subseries 0789024 2 0789025 FDOOH to FEFFH LPD789026 512 bytes uPD78F9026 078904
2. 0789841 789842 Preliminary Product Information U13790E 13790 uPD78F9842 Preliminary Product Information U13901E U13901J 789842 Subseries User s Manual U13776E U13776J Caution The above documents are subject to change without prior notice Be sure to use the latest version document when starting design 10 User s Manual U11047EJ3VOUMOO CONTENTS CHAPTER 1 MEMORY SPAGCE J J J 9 9 EYE nome J J J 15 1 1 Memory Space certare eine enne 15 1 2 Internal Program Memory Internal ROM Space U U u 15 1 3 Vector Table E 17 14 CALLT Instruction Table Area 555955 95555955565935 895 6985 89 20 1 5 Internal Data Memory u u u u 20 1 6 Special Function Register SFR Area 22 CHAPTER 2 REGISTERS nee ER ELI daos deo n eoe eo a Eo deo 23 2 1 Control R gislers 1 crei 23 2 1 1 Program counter PG Acie ele
3. User s Manual 78 05 Series 8 Bit Single Chip Microcontroller Instructions Common to 78K 0S Series Document U11047EJ3VOUMUJ1 8rd edition Date Published November 2000 N CP K NEC Corporation 1996 Printed in Japan 2 User s Manual U11047EJ3VOUMOO NOTES FOR CMOS DEVICES D PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note Strong electric field when exposed to a MOS device can cause destruction of the gate oxide and ultimately degrade the device operation Steps must be taken to stop generation of static electricity as much as possible and quickly dissipate it once when it has occurred Environmental control must be adequate When it is dry humidifier should be used It is recommended to avoid using insulators that easily build static electricity Semiconductor devices must be stored and transported in an anti static container static shielding bag or conductive material All test and measurement tools including work bench and floor should be grounded The operator should be grounded using wrist strap Semiconductor devices must not be touched with bare hands Similar precautions need to be taken for PW boards with semiconductor devices on it HANDLING OF UNUSED INPUT PINS FOR CMOS Note No connection for CMOS device inputs can be cause of malfunction If no connection is provided to the input pins itis possible that an internal input level may be generated due to noise etc hence causin
4. sd how x Notes 1 Exceptr 2 Exceptr A X 3 Only when rp BC DE or HL gt gt gt gt gt gt gt 5 Ee S gt 52 User s Manual U11047EJ3VOUMOO CHAPTER 4 INSTRUCTION SET Mnemonic ADDC SUBC a kmw om 9999 91 _____ hum rassoroi Sema 9 99 1 hm 9 1 1 hoooron Jo hmw To sana 9199 9 JO Awa vor soos SS hm or 9 1 1 hororo 1 hme om 1 9919 991 _____ hum 969991 Seem TOO raoiraoi hm 9 1 1 9 91 om hmw porron 1 0119 9 91 sama ar ssessaro rorrmmm _ hum Awan rors soos eee hm 1 19 44 Joo 191199 991 ar eeessare iro mmm hus 419969 9 1 sa Awan 9119199 uem hm
5. Operand Description 9 When Z 0 program branches to the address specified with the operand When Z 1 no processing is carried out and the subsequent instruction is executed Description example CMP A 55 BNZ 0A39H the A register is not 0055H program branches to 0A39H with the start of this instruction set in the range of addresses 09B8H to 0AB7H User s Manual U11047EJ3VOUMOO 107 CHAPTER 5 EXPLANATION OF INSTRUCTIONS Branch if True Conditional Branch by Bit Test Byte Data Bit 1 Instruction format BT bit addr16 Operation PC b jdisp8 if bit 1 Operand Description e If the 151 operand bit contents have been set 1 program branches to the address specified with the 2nd operand addr16 If the 1st operand bit contents have not been set 1 no processing is carried out and the subsequent instruction is executed Description example BT OFE47H 3 55CH When bit 3 at address FE47H is 1 program branches to 055CH with the start of this instruction set in the range of addresses 04DAH to 05D9H 108 User s Manual U11047EJ3VOUMOO CHAPTER 5 EXPLANATION OF INSTRUCTIONS Branch if False Conditional Branch by Bit Test Byte Data Bit 0 Instruction format BF bit addr16 Operation PC b jdisp8 if bit 0 Operand Description e If the 1st operand bit contents have been cleared 0 program branches to the a
6. 113 01 114 HALT 115 STOP 116 User s Manual U11047EJ3VOUMOO 111 CHAPTER 5 EXPLANATION OF INSTRUCTIONS No Operation No Operation Instruction format NOP Operation no operation Operand None Description No processing is performed and only time is consumed 112 Users Manual U11047EJ3VOUMOO CHAPTER 5 EXPLANATION OF INSTRUCTIONS Enable Interrupt Interrupt Enabled Instruction format EI Operation IE 1 Operand None Description The maskable interrupt acknowledge enable status is set by setting the interrupt enable flag IE 1 e Interrupts are acknowledged immediately after this instruction is executed e If this instruction is executed vectored interrupt acknowledgment with another source can be disabled For details refer to Interrupt Functions in the User s Manual of each product User s Manual U11047EJ3VOUMOO 113 CHAPTER 5 EXPLANATION OF INSTRUCTIONS Disable Interrupt Interrupt Disabled Instruction format DI Operation IE 0 Description e Maskable interrupt acknowledgment with vectored interrupt is disabled with the interrupt enable flag IE cleared 0 e No interrupts are acknowledged between this instruction and the subsequent instruction e For details of interrupt servicing refer to Interrupt Functions in the User s Manual of each product 114 User s Manual U11047EJ3VOUMOO
7. Jeep 9 1 orror 1 User s Manual U11047EJ3VOUMOO 53 CHAPTER 4 INSTRUCTION SET kmw foroo o S bem 91119 99 1 9 ena J hus sa 1 911 91 hw C 90 1 e om 1 bem 999 1 J ar sssssaro ssoommm O hmm foroooros aros Bm peent hme _foooroors om 1 199919 99 1 1 1 ____ fooovoves __ ez L meme 667 mms 9899 1 ewe woes 999 1 1 oorsee ai_fooovoooe je 998999 ar ooreo _ 54 User s Manual U11047EJ3VOUMOO CHAPTER 4 INSTRUCTION SET ___ seme ha T 10999191919685 919 9 901 bum foooororofo sseni
8. 465 250 3583 Fax 1 800 729 9288 1 408 588 6130 Europe Korea Japan NEC Electronics Europe GmbH NEC Electronics Hong Kong Ltd NEC Semiconductor Technical Hotline Seoul Branch Fax 044 435 9608 Technical Documentation Dept Fax 02 528 4411 Fax 49 211 6503 274 South America Taiwan NEC do Brasil S A NEC Electronics Taiwan Ltd Fax 55 11 6465 6829 Fax 02 2719 5951 would like to report the following error make the following suggestion Document title Document number Page number If possible please fax the referenced page or drawing Document Rating Excellent Clarity Technical Accuracy Organization
9. B R3 E R4 D R5 L R6 H R7 AX RPO DE RP2 HL sfr Special function register symbol saddr FE20H to FF1FH Immediate data or labels saddrp FE20H to FF1FH Immediate data or labels even addresses only addr16 0000H to FFFFH Immediate data or labels only even addresses for 16 bit data transfer instructions addr5 0040H to 007FH Immediate data or labels even addresses only word 16 bit immediate data or label byte 8 bit immediate data or label bit 3 bit immediate data or label Remark Refer to the User s Manual of each product for symbols of special function registers 40 User s Manual U11047EJ3VOUMOO CHAPTER 4 INSTRUCTION SET 4 1 2 Description of operation column rrmoomxre z E eds S Or m 3 x PSW XH XL A v addr16 jdisp8 A register 8 bit accumulator X register B register C register D register E register H register L register AX register pair 16 bit accumulator BC register pair DE register pair HL register pair Program counter Stack pointer Program status word Carry flag Auxiliary carry flag Zero flag Interrupt request enable flag Non maskable interrupt servicing flag Memory contents indicated by address or register contents in parentheses Higher 8 bits and lower 8 bits of 16 bit register Logical product AND Logical sum OR Exclusive logical sum exclusive OR Inverted data 16 bit immediate data or label Signed
10. CHAPTER 5 EXPLANATION OF INSTRUCTIONS Halt HALT Mode Set Instruction format HALT Operation Set HALT Mode Operand None Description This instruction is used to set the HALT mode to stop the CPU operation clock Total power consumption of the system can be reduced with intermittent operations through combination with the normal operation mode User s Manual U11047EJ3VOUMOO 115 CHAPTER 5 EXPLANATION OF INSTRUCTIONS Stop Stop Mode Set Instruction format STOP Operation Set STOP Mode Operand None Description e This instruction is used to set the STOP mode to stop the main system clock oscillator and to stop the whole system Power dissipation can be minimized to an ultra low leakage current level only 116 User s Manual U11047EJ3VOUMOO APPENDIX A INSTRUCTION INDEX MNEMONIC BY FUNCTION 8 bit data transfer instructions MOV 60 XCH 61 16 bit data transfer instructions MOVW 63 XCHW 64 8 bit operation instructions ADD 66 ADDC 67 SUB 68 SUBC 69 AND 70 OR 71 XOR 72 73 16 bit operation instructions ADDW 75 SUBW 76 CMPW 77 Increment decrement instructions INC 79 DEC 80 INCW 81 DECW 82 Rotate instructions ROR 84 ROL 85 RORC 86 ROLC 87 Bit manipulation instructions 89 CLR1 90 NOTI 91 Call return instructions C
11. Space 07 OFFFH 1FFFH 2FFFH 3FFFH 5FFFH 7FFFH Subseries Name 0789014 uPD789011 0789012 78 9014 Subseries 0789022 0789024 0789025 uPD789026 uPD78F9026 789046 uPD78F9046 LP D789111 0789112 0789114 SS EBENEN LP D789131 0789132 0789134 D 789154 uPD789156 uPD78F9156 Subseries Subseries Subseries Subseries 0789124 Subseries Subseries Subseries Subseries Subseries 0789176 0789177 uPD78F9177 LPD789196AY uPD789197AY uPD78F9197AY Subseries LPD789197AY Subseries E E 8 E pu E B ni User s Manual U11047EJ3VOUMOO 15 CHAPTER 1 MEMORY SPACE Table 1 1 Internal ROM Space of 78K 0S Series Products 2 2 Capacity 2 2 Kbytes 4 Kbytes 8 Kbytes 12 Kbytes 16 Kbytes 24 24Kbytes 32 32Kbytes Address 0000 to 0000H to 0000H to 0000H to 0000H to 0000H to 0000H to Space 07 OFFFH 1FFFH 2FFFH 3FFFH 5FFFH 7FFFH Subseries Name LPD789217AY LPD789216AY uPD789217AY Subseries uPD78F9217AY Subseries HPD789417A HPD789415A uPD789416A uPD789417A uPD78F9418A Subseries Subseries LPD789842 uPD789841 LPD789842 uUPD78F9842 Subseries 16 User s Manual U11047EJ3VOUMOO CHAPTER 1 MEMORY SPACE 1 3 Vector Table Area The vector table area stores program start addresses to which execution branches when the RESET signal is input or when an interrupt
12. Ss 0999 919 6559 esssraro remesova rw 0999 9191 666 9 9 99 bum ___ To je um lev je C ems 3 9 9 _______ bur mem T Er siessss mm boe mw 99 96 poeet as 1919 1 19 9 9 1 To ham 9 9611994991 aw 4 m _ _ poreo SSS feme oorrrooo mc 9 4 1 mee mz 9 9 sfr bit addr16 0000 10 1 0 1 BeBiBoO0 100 Sfr offset 100001010 01 PSW bit addr16 00001010 1 5 25 801 0 0 010001 1110 User s Manual U11047EJ3VOUMOO 55 CHAPTER 4 INSTRUCTION SET gt jew oooo emus foorroroo foori ooro saa E 10909191 989 1 9 99 a 199949491 9 9 99 9 9 T 1 s oss 1 SSCS 56 User s Manual U11047EJ3VOUMOO CHAPTER 5 EXPLANATION OF INSTRUCTIONS This chapter expla
13. addressing iren gh a divine HEC He eines 38 32 7 i Stack addressings uie pnt io ei 38 CHAPTER 4 INSTRUCTION SET edi Ran Dc E 58 39 4 1 OPS eatin mE 40 4 1 1 Operand representation and description formats a 40 4 1 2 Description of operation column u nennen nenne 41 4 1 5 Description or flag scu et tette era n xe Pe pe ie Bee ees Deos ag 41 44 4 Description of clock col rn iiec Leite cec Reged Lote as 42 41 5 Operationlist ite Modo rdi 43 4 1 6 Instruction list py addreSsIng_ neri eere ete ete etr ntt tern 48 4 2 nstr ction Codes iiie dann sa aD 51 4 2 1 Description of instruction Code table nennen 51 42 2 jnstruction code list o ree PR e HERE ERE 52 User s Manual U11047EJ3VOUMOO 11 CHAPTER 5 EXPLANATION OF INSTRUCTIONS esee u u uuu uu u 57 5 1 8 Bit Data Transfer InstructiOns oerte 59 5 2 16 Bit Data Transfer Ins
14. e If the logical product shows that all bits 0 the Z flag is set 1 In all other cases the Z flag is cleared 0 Description example AND OFEBAH 110111008 FEBAH contents and 11011100B are ANDed bit wise and the result is stored at FEBAH 70 User s Manual U11047EJ3VOUMOO CHAPTER 5 EXPLANATION OF INSTRUCTIONS Or Logical Sum of Byte Data Instruction format OR dst src Operation dst dst v src Operand A e byte Description e The destination operand dst specified with the 1st operand and the source operand src specified with the 2nd operand are ORed bit wise and the result is stored in the destination operand dst e If the logical sum shows that all bits are 0 the Z flag is set 1 In all other cases the Z flag is cleared 0 Description example OR A OFE98H The A register and FE98H are ORed bit wise and the result is stored in the A register User s Manual U11047EJ3VOUMOO 71 CHAPTER 5 EXPLANATION OF INSTRUCTIONS Exclusive Or Exclusive Logical Sum of Byte Data Instruction format XOR dst src Operation dst lt dst src Operand A e byte Description e The destination operand dst specified with the 1st operand and the source operand src specified with the 2nd operand are XORed bit wise and the result is stored in the destination operand dst Logical negation of all bits of the destination operand dst is possible with this instruc
15. ee ai hea Bee 23 2 1 2 Program status word PSW w u denied pe c ee eda eee 23 2 1 3 Stack pointer 5 cer oh e o ie ee oe ee eee 24 22 1 111 1 1 1 1 11 uuu uuu uuu u 25 2 3 Special Function Registers SFRs U u u u uuu uu u uu uu u 27 CHAPTER 3 ADDRESSING uuu u SG kuah ak haqa ua au 29 3 1 Addressing of Instruction U 29 3 1 1 Relative addressing irre a 29 3 1 2 Immediate addressing ie nie De nt eae redi abe bo ob 30 3 1 3 Table indirect addressing uuu ullu aee ul tnnt 31 3 1 4 Register addresSIng ee cnet id 32 3 2 Addressing of Operand Address keit oret 33 3 2 1 Direct addressirig a ee ente et EP etre e Laetus 33 3 22 Short direct addressihg ater a etae eet 34 3 2 8 Special function register SFR addressing 44 35 3 24 Register addressirig inte ot de Poe viele oper 36 3 25 Register indirect addr ssirig taceant e ese nte t die fer 37 3 2 6 Based
16. general Read this manual in the order of the CONTENTS User s Manual U11047EJ3VOUMOO 7 To learn the hardware functions of the 78K 0S Series products Refer to the user s manual for each product see Related documents Conventions Data significance Higher digits on the left and lower digits on the right Note Footnote for item marked with Note in the text Caution Information requiring particular attention Remark Supplementary information Numeral representation Binary xxxxB Decimal Hexadecimal xxxxH x Related Documents The related documents indicated in this publication may include preliminary versions However preliminary versions are not marked as such o Document common to 78K 0S Series Document Name Document Number English Japanese User s Manual Instructions U11047J o Individual documents 9 uPD789014 Subseries Document Name Document Number English Japanese 0789011 789012 Data Sheet U11095E U11095J uPD78P9014 Data Sheet U10912bE U10912J 0789014 Subseries User s Manual U11187E U11187J 9 uPD789026 Subseries Document Name Document Number English Japanese HP D789022 789024 789025 789026 Data Sheet U11715E U11715J HPD78F9026 Data Sheet U11858E U11858J 769026 Subseries User s Manual U11919E U11919J 9 uPD789046 Subseries Document Name Document Number English Japanese 789046 Preliminary Prod
17. table 0 Low addr Effective address 1 High addr 15 8 7 0 PC User s Manual U11047EJ3VOUMOO 31 CHAPTER 3 ADDRESSING 3 1 4 Register addressing Function Register pair AX contents specified with an instruction word are transferred to the program counter PC and program branches This function is carried out when the BR AX instruction is executed Illustration 32 User s Manual U11047EJ3VOUMOO CHAPTER 3 ADDRESSING 3 2 Addressing of Operand Address The following methods are available to specify the register and memory addressing which undergo manipulation during instruction execution 3 2 1 Direct addressing Function This addressing directly addresses a memory to be manipulated with immediate data in an instruction word Operand format addr16 Label or 16 bit immediate data Description example FE00H When setting addr16 to FE00H Instruction code 0 01 0 1 0 0 1 OPcode 0000000 0 1 1 1 1 1 1 1 Illustration OP code addr16 lower addr16 higher Memory User s Manual U11047EJ3VOUMOO 33 CHAPTER 3 ADDRESSING 3 2 2 Short direct addressing Function This addressing directly addresses memory to be manipulated in the fixed space with the 8 bit data in an instruction word This addressing is applied to the 256 byte fixed space of FE20H to FF1FH An internal high speed RAM and special function registers SF
18. CALL and CALLT instructions e The word data saved in the stack returns to the PC and the program returns from the subroutine User s Manual U11047EJ3VOUMOO 95 CHAPTER 5 EXPLANATION OF INSTRUCTIONS Return from Interrupt Return from Hardware Vectored Interrupt Instruction format RETI Operation lt SP PCH SP 1 PSW SP 2 Operand None Description e This is a return instruction from the vectored interrupt e The data saved in the stack returns to the PC and PSW and the program returns from the interrupt service routine e None of interrupts are acknowledged between this instruction and the next instruction to be executed The NMIS flag is set to 1 by acknowledgment of a non maskable interrupt and cleared to 0 by the RETI instruction Caution When the return from non maskable interrupt servicing is performed by an instruction other than the RETI instruction the NMIS flag is not cleared to 0 and therefore no interrupts including non maskable interrupts can be acknowledged 96 User s Manual U11047EJ3VOUMOO CHAPTER 5 EXPLANATION OF INSTRUCTIONS 5 9 Stack Manipulation Instructions The following are stack manipulation instructions PUSH 98 POP 99 MOVW SP AX 100 MOVW AX SP 100 User s Manual U11047EJ3VOUMOO 97 CHAPTER 5 EXPLANATION OF INSTRUCTIONS Instruction format PUSH src Operation When src rp When src PSW SP 1 srcu S
19. Rotate Instructions The following are rotate instructions ROR 84 ROL 85 RORC 86 ROLC 87 User s Manual U11047EJ3VOUMOO 83 CHAPTER 5 EXPLANATION OF INSTRUCTIONS Rotate Right Byte Data Rotation to the Right Instruction format ROR dst cnt Operation CY dstz dsto dstm 1 dstm x one time Operand Description e The destination operand dst contents specified with the 1st operand are rotated to the right just once e The LSB bit 0 contents are simultaneously rotated to MSB bit 7 and transferred to the CY flag CY 7 0 pub Description example 1 The A register contents are rotated one bit to the right 84 User s Manual U11047EJ3V0UM00 CHAPTER 5 EXPLANATION OF INSTRUCTIONS Rotate Left Byte Data Rotation to the Left Instruction format ROL dst cnt Operation CY dsto lt 00517 dstm 1 dstm x one time Operand Description e The destination operand dst contents specified with the 1st operand are rotated to the left just once 9 The MSB bit 7 contents are simultaneously rotated to LSB bit 0 and transferred to the CY flag CY 7 0 jar s e Description example ROL A 1 The A register contents are rotated to the left by one bit User s Manual U11047EJ3V0UM00 85 CHAPTER 5 EXPLANATION OF INSTRUCTIONS Rotate Right with Carry Byte Data Rotation to the Right with Carry Instruction fo
20. also be specified with an address 16 bit manipulation Describes a symbol reserved by the assembler for the 16 bit manipulation instruction operand When addressing an address describe an even address For details of the special function registers refer to the User s Manual of each product User s Manual U11047EJ3VOUMOO 27 28 User s Manual U11047EJ3VOUMOO CHAPTER 3 ADDRESSING 3 1 Addressing of Instruction Address An instruction address is determined by the program counter PC contents The PC contents are normally incremented 1 per byte automatically according to the number of bytes of an instruction to be fetched each time another instruction is executed When a branch instruction is executed the branch destination information is set in the PC and branched by the following addressing For details of each instruction see CHAPTER 5 EXPLANATION OF INSTRUCTIONS 3 1 1 Relative addressing Function The value obtained by adding the 8 bit immediate data displacement value jdisp8 of an instruction code to the first address of the following instruction is transferred to the program counter PC and program branches The displacement value is treated as signed two s complement data 128 to 127 and bit 7 becomes a sign bit Thus relative addressing causes a branch to an address within the range of 128 to 127 relative to the first address of the next instruction This function is carried out when the B
21. application please contact the NEC office in your country to obtain a list of authorized representatives and distributors They will verify Device availability Ordering information Product release schedule Availability of related technical literature Development environment specifications for example specifications for third party tools and components host computers power plugs AC supply voltages and so forth Network requirements In addition trademarks registered trademarks export restrictions and other legal issues may also vary from country to country NEC Electronics Inc U S Santa Clara California Tel 408 588 6000 800 366 9782 Fax 408 588 6130 800 729 9288 NEC Electronics Germany GmbH Duesseldorf Germany Tel 0211 65 03 02 Fax 0211 65 03 490 NEC Electronics UK Ltd Milton Keynes UK Tel 01908 691 133 Fax 01908 670 290 NEC Electronics Italiana s r l Milano Italy Tel 02 66 75 41 Fax 02 66 75 42 99 NEC Electronics Germany GmbH Benelux Office Eindhoven The Netherlands Tel 040 2445845 Fax 040 2444580 NEC Electronics France S A Velizy Villacoublay France Tel 01 30 67 58 00 Fax 01 30 67 58 99 NEC Electronics France S A Madrid Office Madrid Spain Tel 91 504 2787 Fax 91 504 2860 NEC Electronics Germany GmbH Scandinavia Office Taeby Sweden Tel 08 63 80 820 Fax 08 63 80 388 User s Manual U11047EJ3VOUMOO NEC E
22. e The destination operand dst specified with the 1st operand is added to the source operand src specified with the 2nd operand and the result is stored in the CY flag and the destination operand dst e If the addition result shows that dst is 0 the Z flag is set 1 In all other cases the Z flag is cleared 0 e If the addition generates a carry from bit 7 the CY flag is set 1 In all other cases the CY flag is cleared 0 e f the addition generates carry from bit to bit 4 the AC flag is set 1 In all other cases the AC flag is cleared 0 Description example ADD CR10 56H 56H is added to the CR10 register and the result is stored in the CR10 register 66 User s Manual U11047EJ3VOUMOO CHAPTER 5 EXPLANATION OF INSTRUCTIONS Add with Carry Addition of Byte Data with Carry Instruction format ADDC dst src Operation dst CY dst src CY Operand Description The destination operand dst specified with the 1st operand the source operand src specified with the 2nd operand and the CY flag are added and the result is stored in the destination operand dst and the CY flag The CY flag is added to the least significant bit This instruction is mainly used to add two or more bytes If the addition result shows that dst is 0 the Z flag is set 1 In all other cases the Z flag is cleared 0 If the addition generates a carry from bit 7 the CY flag is set 1 In all other cases the CY fl
23. is granted under any patents copyrights or other intellectual property rights of NEC or others Descriptions of circuits software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples The incorporation of these circuits software and information in the design of customer s equipment shall be done under the full responsibility of customer NEC assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits software and information While NEC endeavours to enhance the quality reliability and safety of NEC semiconductor products customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely To minimize risks of damage to property or injury including death to persons arising from defects in NEC semiconductor products customers must incorporate sufficient safety measures in their design such as redundancy fire containment and anti failure features NEC semiconductor products are classified into the following three quality grades Standard Special and Specific The Specific quality grade applies only to semiconductor products developed based on a customer designated quality assurance program for a specific application The recommended applications of a semiconductor product depend on its quality grade as indicated below Customers must check the qual
24. memory Only the internal high speed RAM area can be set as the stack area Figure 2 3 Format of Stack Pointer 15 0 esee er ses ses ser sre rs ors ses see 5 Po SP The SP is decremented ahead of write save to the stack memory and is incremented after read reset from the stack memory The data saved restored as a result of each stack operation are as shown in Figures 2 4 and 2 5 Caution Since RESET input makes the SP contents undefined be sure to initialize the SP before executing an instruction 24 User s Manual U11047EJ3VOUMOO CHAPTER 2 REGISTERS Figure 2 4 Data to Be Saved to Stack Memory PUSH rp CALL CALLT Interrupt instruction instructions SP SP 3 A SP lt SP 2 SP lt SP 2 SPI PC7 to PCO Lower byte in 4 2 register pair in 2 PC7 to PCO zd 2 PC15 to PC8 _ Upper byte in E _ 1 pall 1 PC15 to PC8 spon PSW SP SP gt gt Figure 2 5 Data to Be Restored from Stack Memory POP rp RET instruction RETI instruction instruction Lower byte in register pair SP PC7 to PCO SP PC7 to PCO Upper byte in SP 1 register pair SP 1 PC15 to PC8 i 1 PC15 to PC8 SP lt SP 2 SP lt SP 2 SP 2 PSW SP SP 3 2 2 General Purpose Registers The general purpose register consists of eight 8 bit registers X A C B E D L and H Each register can be used as an 8 bit register or two 8 b
25. request is generated Of the 16 bit address the lower 8 bits are stored in an even address and the higher 8 bits are stored in an odd address Table 1 2 Vector Table 0000H to 0013H uPD789014 Subseries bmw Table 1 3 Vector Table 0000H to 002BH uPD789026 Subseries Table 1 4 Vector Table 0000H to 0019H uPD789046 Subseries Table 1 5 Vector Table 0000H to 0015H uPD789104 789114 789124 789134 Subseries Vector Table Address Interrupt Request Vector Table Address Interrupt Request 0000H RESET input 000CH INTSR20 INTCSI20 0004H INTWDT 000 INTST20 0006H INTPO 0010H INTTM80 0008H INTP1 0012H INTTM20 000AH INTP2 0014H INTADO User s Manual U11047EJ3VOUMOO 17 CHAPTER 1 MEMORY SPACE Table 1 6 Vector Table 0000H to 0019H uPD789146 789156 Subseries Vector Table Address Interrupt Request Vector Table Address Interrupt Request 0000H RESET input 000 INTST20 0004H INTWDT 0010H INTTM80 Table 1 7 Vector Table 0000H to 0023H wPD789167 789177 Subseries Table 1 8 Vector Table 0000 to 0027 uPD789197AY 789217 Subseries 18 User s Manual U11047EJ3VOUMOO CHAPTER 1 MEMORY SPACE Table 1 9 Vector Table 0000H to 0023H uPD789407A and 789417 Subseries a m Table 1 10 Vector Table 0000H to 0019H uPD789800 Subseries Table 1 11 Vector Table 0000H to 0023H uPD789842 Subseries
26. when an interrupt request is generated or when the PUSH PSW instruction is executed and are automatically reset when the RETI and POP PSW instruction are executed RESET input sets PSW to 02H Figure 2 2 Format of Program Status Word 7 0 2 of ols User s Manual U11047EJ3VOUMOO 23 CHAPTER 2 REGISTERS 1 Interrupt enable flag IE This flag controls interrupt request acknowledge operations of the CPU When IE 0 all interrupts except non maskable interrupts are disabled DI status When IE 1 interrupts are enabled El status At this time acknowledgment of interrupt requests is controlled by the interrupt mask flag for each interrupt source The IE flag is reset 0 when the DI instruction execution is executed or when an interrupt is acknowledged and set 1 when the El instruction is executed 2 Zero flag Z When the operation result is zero this flag is set 1 otherwise it is reset 0 3 Auxiliary carry flag AC If the operation result has a carry from bit 3 or a borrow to bit 3 this flag is set 1 otherwise it is reset 0 4 Carry flag CY This flag records an overflow or underflow upon add subtract instruction execution also records the shift out value upon rotate instruction execution and functions as a bit accumulator during bit operation instruction execution 2 1 3 Stack pointer SP This is a 16 bit register that holds the first address of the stack area in the
27. 00000000 addr5 SP SP 2 Remark One instruction clock cycle is equal to one CPU clock fceu cycle selected by the processor clock control register PCC lt lt gt gt o o 46 User s Manual U11047EJ3VOUMOO CHAPTER 4 INSTRUCTION SET iui 6 SP 1 PC SP SP SP 2 SP 2 SP SP 3 NMIS 0 PUSH 2 1 lt PSW SP lt SP 1 se r so lt SP 1 rp lt SP SP SP 2 vow fesa id a fe forme LL we lepe ocre A fi epean Bo mee s 6 59 6 3 1 be s 6 6 gt ene e 6 1 41 5 85 4 10 Amsa 5 6 2 5 8 4 sadar bit adarte 4 oo PC 4 jdisp8 if saddr bit oe 5 8 6 6 4 8 gt 2 sasare 4 10 6 76 5 65 9 8 0 86 9 8 8 8 2 6 8 9 5151 EXC WEE UJ mi C addr16 C C 1 then PC PC 2 jdisp8 if C 0 saddr addr16 saddr lt saddr 1 then PC lt PC 3 jdisp8 if 0 Remark One instruction clock cycle
28. 2 User s Manual U11047EJ3VOUMOO LIST OF FIGURES Figure No Title Page 2 1 Format of Program Gounter RU e ERREUR 23 2 2 Format of Program Stat s Word a u a nennen nennen entree rnit 23 2 9 Format of Stack Pointer tact ain 24 2 4 Data to Be Saved to Stack 25 2 5 Data to Be Restored from Stack Memory eene nennen trennen e nnn enne 25 2 6 General Purpose Register 26 LIST TABLES Table No Title Page 1 1 Internal ROM Space of 78K 0S Series Products eene nennen nennen 15 1 2 Vector Table 0000H to 0013H uPD789014 5 17 1 3 Vector Table 0000H to 002BH uPD789026 17 1 4 Vector Table 0000H to 0019H uPD789046 17 1 5 Vector Table 0000H to 0015H uPD789104 789114 789124 789134 17 1 6 Vector Table 0000H to 0019H uPD789146 789156 18 1 7 Vector Table 0000H to 0023H uPD789167 789177 Subseries sse 18 1 8 Vector Tabl
29. 3 SP lt SP 2 PC target Operand CALL laddr16 Description e This is a subroutine call with a 16 bit absolute address or a register indirect address The next instruction s start address PC 3 is saved in the stack and is branched to the address specified with the target operand target Description example CALL 3059H Subroutine call to 3059H User s Manual U11047EJ3VOUMOO 93 CHAPTER 5 EXPLANATION OF INSTRUCTIONS Call Table CALLT Subroutine Call Call Table Reference Instruction format CALLT addr5 Operation SP 1 1 SP 2 lt 1 SP lt SP 2 lt 00000000 addr5 1 PCL 00000000 addr5 Operand CALLT addr5 Description This is a subroutine call for call table reference e The next instruction s start address 1 is saved in the stack and is branched to the address indicated with the word data of a call table the higher 8 bits of address are fixed to 00000000B and the following 5 bits are specified with addr5 Description example CALLT 40H Subroutine call to the addresses indicated by word data of 0040H and 0041H 94 User s Manual U11047EJ3VOUMOO CHAPTER 5 EXPLANATION OF INSTRUCTIONS Return Return from Subroutine Instruction format RET Operation lt SP PCH lt SP 1 SP lt SP 2 Operand None Description e This is a return instruction from the subroutine call made with the
30. 6 789046 FD00H to FEFFH Subseries LPD78F9046 512 bytes uPD789104 0789101 to FEFFH Subseries LPD789102 256 bytes uPD789104 0789114 uPD789111 to FEFFH Subseries LPD789112 256 bytes LPD789114 HPD78F9116 20 User s Manual U11047EJ3VOUMOO CHAPTER 1 MEMORY SPACE Table 1 12 Internal Data Memory Space of 78K 0S Series Products 2 2 Product Name High Speed RAM LCD Display RAM EEPROM uPD789124 uPD789121 FEOOH to FEFFH Subseries 0789122 256 bytes 0789124 0789134 HPD789131 FEO0H to FEFFH Subseries LPD789132 256 bytes uPD789134 uPD78F9136 0789146 uPD789144 FEO0H to FEFFH F800H to F8FFH Subseries LPD789146 256 bytes 256 bytes 0789156 0789154 to FEFFH F800H to F8FFH Subseries LPD789156 256 bytes 256 bytes uPD78F9156 0789167 0789166 FDOOH to FEFFH Subseries 0789167 512 bytes 0789177 0789176 FD00H to FEFFH Subseries LPD789177 512 bytes LPD78F9177 LPD789197AY HPD789196AY FD00H to FEFFH Subseries LPD789197AY 512 bytes LPD78F9197AY 0789217 LPD789216AY FD00H to FEFFH F800H to F87FH Subseries LPD789217AY 512 bytes 128 bytes LPD78F9217AY 789407 0789405 FD00H to FEFFH Subseries LPD789406A 512 bytes 789407 789417 LPD789415A FD00H to FEFFH to FA1BH Subseries LPD789416A 512 bytes 28 bytes LPD789417A LPD78F9418A uPD789800 uPD789800 FE00H to FEFFH Subseries uPD7
31. 789124 e uPD789134 Subseries PD789131 789132 789134 78F9136 e uPD789146 Subseries PD789144 789146 e uPD789156 Subseries 789154 789156 78F9156 e uPD789167 Subseries PD789166 789167 e uPD789177 Subseries PD789176 789177 78F9177 e uPD789197AY Subseries uPD789196AY 789197AY 78F9197AY e uPD789217AY Subseries uPD789216AY 789217AY 78F9217AY e uPD789407A Subseries 789405 789406A 789407A e uPD789417A Subseries 789415 789416A 789417A 78F9418A e uPD789800 Subseries uPD789800 78F9801 e uPD789842 Subseries PD789841 789842 78F9842 Note Under development This manual is intended for users to understand the instruction functions of 78K 0S Series products The contents of this manual are broadly divided into the following CPU functions Instruction set Explanation of instructions It is assumed that the reader of this manual has general knowledge in the fields of electrical engineering logic circuits and microcontrollers To check the details of the functions of an instruction whose mnemonic is known See APPENDICES A and B INSTRUCTION INDEX To check an instruction whose mnemonic is not known but whose general function is known Check the mnemonic in CHAPTER 4 INSTRUCTION SET then the functions in CHAPTER 5 EXPLANATION OF INSTRUCTIONS To understand the overall functions of the 78K 0S Series products instructions in
32. 8 bit data displacement value 4 1 3 Description of flag column Blank X Not affected Cleared to 0 Setto 1 Set cleared according to the result Previously saved value is restored User s Manual U11047EJ3V0UM00 41 CHAPTER 4 INSTRUCTION SET 4 1 4 Description of clock column The number of clock cycles during instruction execution is outlined as follows One instruction clock cycle is equal to one CPU clock cycle selected by the processor clock control register PCO The operation list is shown below 42 User s Manual U11047EJ3VOUMOO CHAPTER 4 INSTRUCTION SET 4 1 5 Operation list Mnemonic Operand Byte Clock Operation Flag Z AC CY x o eleke s s T mm elebe o xr mp he E Asa e epeen e ejem xm s hes E a e ee O Aw fele sana Jele e Am 9 4 hm seem hw id fe fey 6 e Sa ENEN Ca awe A HU A HL byte A lt gt HL byte Notes 1 Exceptr 2 Exceptr A X Remark One instruction clock cycle is equal to one CPU clock fceu cycle selected by the processor cl
33. 8F9801 256 bytes 789842 0789841 to FEFFH Subseries LPD789842 256 bytes uUPD78F9842 User s Manual U11047EJ3VOUMOO 21 CHAPTER 1 MEMORY SPACE 1 6 Special Function Register SFR Area Special function registers SFRs of on chip peripheral hardware are allocated to the area FFOOH to FFFFH refer to the User s Manual of each product 22 User s Manual U11047EJ3VOUMOO CHAPTER 2 REGISTERS 2 1 Control Registers The control registers have dedicated functions such as controlling the program sequence statuses and stack memory The control registers include a program counter program status word and stack pointer 2 1 4 Program counter PC The program counter is a 16 bit register that holds the address information of the next program to be executed In normal operation the PC is automatically incremented according to the number of bytes of the instruction to be fetched When a branch instruction is executed immediate data and register contents are set When the RESET signal is input the program counter is set to the value of the reset vector table which are located at addresses 0000H and 0001H Figure 2 1 Format of Program Counter PC 15 0 Feu poaren Pcs Po or ren res ren res o veo 2 1 2 Program status word PSW Program status word is an 8 bit register consisting of various flags to be set reset by instruction execution The contents of program status word are automatically stacked
34. ALL 93 CALLT 94 RET 95 RETI 96 Stack manipulation instructions PUSH 98 POP 99 MOVW SP AX 100 MOVW AX SP 100 Unconditional branch instruction BR 102 Conditional branch instructions BC 104 BNC 105 BZ 106 BNZ 107 BT 108 BF 109 DBNZ 110 CPU control instructions NOP 112 113 DI 114 HALT 115 STOP 116 User s Manual U11047EJ3VOUMOO 117 118 User s Manual U11047EJ3VOUMOO APPENDIX B INSTRUCTION INDEX MNEMONIC IN ALPHABETICAL ORDER A ADD 66 ADDC 67 ADDW 75 AND 70 B BC 104 109 BNC 105 BNZ 107 BR 102 BT 108 82 106 CALL 93 CALLT 94 CLR1 90 CMP 73 CMPW 77 D DBNZ 110 DEC 80 DECW 82 DI 114 E El 113 HALT 115 INC 79 INCW 81 M MOV 60 MOVW 63 MOVW AX SP 100 MOVW SP AX 100 NOP 112 NOT1 91 71 POP 99 PUSH 98 R RET 95 RETI 96 ROL 85 ROLC 87 ROR 84 RORC 86 S SET1 89 STOP 116 SUB 68 SUBC 69 SUBW 76 X XCH 61 XCHW 64 72 User s Manual U11047EJ3VOUMOO 119 120 User s Manual U11047EJ3VOUMOO APPENDIX C REVISION HISTORY A history of the revisions up to this edition is shown below Applied to indicates t
35. EOH to FFFFH However the SFRs mapped at FFOOH to FF1FH can also be accessed by means of short direct addressing Operand format Special function register name Description example A When selecting PMO for sfr Instruction code 1 1 1 0 0 1 1 1 1 0 0 Illustration OP code sfr offset Effective address User s Manual U11047EJ3VOUMOO 35 CHAPTER 3 ADDRESSING 3 2 4 Register addressing Function This addressing is to access a general purpose register by specifying it as an operand The general purpose register to be accessed is specified with a register specification code in an instruction code or function name Register addressing is carried out when an instruction with the following operand format is executed When an 8 bit register is specified one of the eight registers is specified with 3 bits register specification code in the instruction code Operand format r JXAGREDLH AX BO DE HL and rp can be described with absolute names RO to R7 and RPO to RP3 as well as functional names X A C B E D L H AX BC DE and HL Description example MOV A C When selecting the C register for r Instruction code 0 000 Register specification code INCW DE When selecting the DE register pair for rp Instruction code 1 0 0 1 0 0 0 Register specification code 36 User s Manual U11047EJ3VOUMOO CHAPTER 3 ADDRESSI
36. HAPTER 5 EXPLANATION OF INSTRUCTIONS 5 1 8 Bit Data Transfer Instructions The following instructions are 8 bit data transfer instructions MOV 60 XCH 61 User s Manual U11047EJ3VOUMOO 59 CHAPTER 5 EXPLANATION OF INSTRUCTIONS Move Byte Data Transfer Instruction format dst src Operation dst src Operand Note Exceptr A Flag PSW byte and PSW A All other operand operands combinations Description e The contents of the source operand src specified by the 2nd operand are transferred to the destination operand dst specified by the 1st operand e No interrupts are acknowledged between the MOV PSW byte instruction or the MOV PSW instruction and the subsequent instruction Description example MOV A 4DH 4DH is transferred to A register 60 User s Manual U11047EJ3VOUMOO CHAPTER 5 EXPLANATION OF INSTRUCTIONS Exchange Byte Data Exchange Instruction format XCH dst src Operation dst src Operand Note Exceptr A X Description e The ist and 2nd operand contents are exchanged Description example XCH A OFEBCH The A register contents and address FEBCH contents are exchanged User s Manual U11047EJ3VOUMOO 61 CHAPTER 5 EXPLANATION OF INSTRUCTIONS 5 2 16 Bit Data Transfer Instructions The following instructions are 16 bit data transfer instructions MOVW 63 XCHW 64 62 User s Manual U11047EJ3VOU
37. MOO CHAPTER 5 EXPLANATION OF INSTRUCTIONS Move Word Word Data Transfer Instruction format MOVW dst src Operation dst src Operand Note Only when rp BC DE or HL Description The contents of the source operand src specified by the 2nd operand are transferred to the destination operand dst specified by the 1st operand Description example MOVW AX HL The HL register contents are transferred to the AX register Caution Only an even address can be specified to saddrp An odd address cannot be specified User s Manual U11047EJ3VOUMOO 63 CHAPTER 5 EXPLANATION OF INSTRUCTIONS Exchange Word Word Data Exchange Instruction format XCHW dst src Operation dst src Operand Note Only when rp BC DE or HL Description e The ist and 2nd operand contents are exchanged Description example XCHW AX BC The memory contents of AX register are exchanged with those of the BC register 64 User s Manual U11047EJ3VOUMOO CHAPTER 5 EXPLANATION OF INSTRUCTIONS 5 3 8 Bit Operation Instructions The following are 8 bit operation instructions ADD 66 ADDC 67 SUB 68 SUBC 69 AND 70 OR 71 XOR 72 73 User s Manual U11047EJ3VOUMOO 65 CHAPTER 5 EXPLANATION OF INSTRUCTIONS Add Byte Data Addition Instruction format ADD dst src Operation dst CY lt dst src Operand A e byte Description
38. MOO 77 CHAPTER 5 EXPLANATION OF INSTRUCTIONS 5 5 Increment Decrement Instructions The following are increment decrement instructions INC 79 DEC 80 INCW 81 DECW 82 78 User s Manual U11047EJ3VOUMOO CHAPTER 5 EXPLANATION OF INSTRUCTIONS Increment Byte Data Increment Instruction format INC dst Operation dst dst 1 Operand Description e The destination operand dst contents are incremented by only one e If the increment result is 0 the Z flag is set 1 In all other cases the Z flag is cleared 0 e the increment generates carry from bit to bit 4 the AC flag is set 1 In all other cases the AC flag is cleared 0 e Because this instruction is frequently used for a counter for repeated operations the CY flag contents are not changed to hold the CY flag contents in multiple byte operation Description example INC B The B register is incremented User s Manual U11047EJ3VOUMOO 79 CHAPTER 5 EXPLANATION OF INSTRUCTIONS Decrement Byte Data Decrement Instruction format DEC dst Operation dst lt dst 1 Operand Description The destination operand dst contents are decremented by only one If the decrement result is 0 the Z flag is set 1 In all other cases the Z flag is cleared 0 If the decrement generates a carry from bit 4 to bit 3 the AC flag is set 1 In all other cases the AC flag is cleared 0 Because this instr
39. NG 3 2 5 Register indirect addressing Function This addressing is to address memory using the contents of the special register pair as an operand The register pair to be accessed is specified with the register pair specification code in an instruction code This addressing can be carried out for the entire memory space Operand format Description example MOV A DE When selecting register pair DE Instruction code 0 0 1 0 1 O 1 1 Illustration Memory address specified with register pair DE The contents of the specified memory address are transferred 7 User s Manual U11047EJ3VOUMOO 37 CHAPTER 3 ADDRESSING 3 2 6 Based addressing Function This addressing is to address the memory by using the result of adding 8 bit immediate data to the contents of the base register i e the HL register pair The addition is performed by expanding the offset data as a positive number to 16 bits A carry from the 16th bit is ignored This addressing can be carried out for the entire memory space Operand format Description example MOV HL 10H When setting byte to 10H Instruction code 0 0 1 0 1 1 0 1 3 2 7 Stack addressing Function This addressing is to indirectly address the stack area with the stack pointer SP contents This addressing method is automatically employed when the PUSH POP subroutine call or RETURN instructions is executed or when
40. Operation Instructions The following are 16 bit operation instructions ADDW 75 SUBW 76 CMPW 77 74 User s Manual U11047EJ3VOUMOO CHAPTER 5 EXPLANATION OF INSTRUCTIONS Add Word Word Data Addition Instruction format ADDW dst src Operation dst CY lt dst src Operand ADDW AX word Description The destination operand dst specified with the 1st operand is added to the source operand src specified with the 2nd operand and the result is stored in the destination operand dst e If the addition result shows that dst is 0 the Z flag is set 1 In all other cases the Z flag is cleared 0 e If the addition generates a carry from bit 15 the CY flag is set 1 In all other cases the CY flag is cleared 0 e Asaresult of addition the AC flag becomes undefined Description example ADDW AX 0 ABCDH is added to the AX register and the result is stored in the AX register User s Manual U11047EJ3VOUMOO 75 CHAPTER 5 EXPLANATION OF INSTRUCTIONS Subtract Word Word Data Subtraction Instruction format SUBW dst src Operation dst CY lt dst src Operand SUBW AX word Description e The source operand src specified with the 2nd operand is subtracted from the destination operand dst specified with the 1st operand and the result is stored in the destination operand dst and the CY flag The destination operand can be cleared to 0 by equalizing
41. P 1 src SP 2 lt src SP lt SP 1 SP c SP 2 Operand rp Description e The data of the register specified with the source operand src is saved in the stack Description example PUSH AX AX register contents are saved in the stack 98 User s Manual U11047EJ3VOUMOO CHAPTER 5 EXPLANATION OF INSTRUCTIONS Pop POP Pop Instruction format POP dst Operation When dst rp When dst PSW dst SP dst lt SP dst lt SP 1 SP SP 1 SP lt SP 2 Operand Description e Data is returned from the stack to the register specified with the destination operand dst e When the operand is PSW each flag is replaced with stack data 9 No interrupts are acknowledged between the POP PSW instruction and the subsequent instruction Description example POP AX The stack data is returned to the AX register User s Manual U11047EJ3VOUMOO 99 CHAPTER 5 EXPLANATION OF INSTRUCTIONS MOVW SP AX Move Word MOVW AX SP Word Data Transfer with Stack Pointer 3 Instruction format MOVW dst src Operation dst src Operand MOVW SP AX AX SP Description e This is an instruction to manipulate the stack pointer contents e The source operand src specified with the 2nd operand is stored in the destination operand dst specified with the 1st operand Description example MOVW SP AX AX register contents are stored in the stack pointer 100 User s Manual U11047EJ3
42. R addr16 instruction or a conditional branch instruction is executed Illustration 15 0 of instruction next to BR instruction 15 8 7 6 0 x tc S 1 jdisp8 15 0 4 When S 0 all bits are 0 When 5 1 all bits of are 1 User s Manual U11047EJ3VOUMOO 29 CHAPTER 3 ADDRESSING 3 1 2 Immediate addressing Function Immediate data in the instruction word is transferred to the program counter PC and program branches This function is carried out when the CALL laddr16 or BR laddr16 instruction is executed The CALL 16 and BR 16 instructions can be used to branch to any address within the memory Spaces Illustration In case of CALL addr16 or BR addr16 instruction 7 0 CALL or BR Low addr High addr 15 87 0 PC 30 User s Manual U11047EJ3VOUMOO CHAPTER 3 ADDRESSING 3 1 3 Table indirect addressing Function Table contents branch destination address of a particular location addressed by the immediate data of bits 1 to 5 of an instruction code are transferred to the program counter PC and program branches Table indirect addressing is performed when the CALLT addr5 instruction is executed This instruction references the address stored in the memory table from 40H to 7FH and allows branching to the entire memory Space Illustration 7 6 5 1 0 15 8 7 6 5 1 0 Effective address 000000000 s mes 7 Memory
43. Rs are mapped at FE20H to FEFFH and FF00H to FF1FH respectively The SFR area FFOOH FF1FH to which short direct addressing is applied constitutes only part of the overall SFR area In this area ports that are frequently accessed in a program and a compare register of the timer event counter are mapped and these SFRs can be manipulated with a small number of bytes and clocks When 8 bit immediate data is 20H to FFH bit 8 of an effective address is set to 0 When it is 00H to 1FH bit 8 is setto 1 See Illustration below Operand format Label or FE20H to FF1FH immediate data Label or FE20H to FF1FH immediate data even address only Description example MOV 50H When setting saddr to FE30H and the immediate data to 50H Instruction code 1 0 1 OP code n mk a a 1 1 0 0 0 0 30H saddr offset 1 0 0 0 0 50H immediate data Illustration saddr offset Short direct memory Effective address When 8 bit immediate data is 20H to When 8 bit immediate data is OOH to 1FH a 0 1 34 User s Manual U11047EJ3VOUMOO CHAPTER 3 ADDRESSING 3 2 3 Special function register SFR addressing Function This addressing is to address special function registers SFRs mapped to the memory with the 8 bit immediate data in an instruction word This addressing is applied to the 240 byte spaces of FFOOH to FFCFH and FF
44. S A HL byte A saddr byte A CY HL byte A A byte saddr lt saddr byte Ax sadi A Ax edi A lt 4 A HL byte wie lt Av HL byte lt A HL byte A Avbyte saddr saddr vbyte Avr lt Av saddr lt Av addr16 lt Avbyte saddr byte Te saddr byte saddr lt saddr byte lt Avr lt Ax saddr lt 16 Av HL byte byte saddr byte r saddr A laddr16 A HL A HL byte addr16 HL HL byte User s Manual U11047EJ3VOUMOO Remark One instruction clock cycle is equal to one CPU clock fceu cycle selected by the processor clock control register PCC 45 CHAPTER 4 INSTRUCTION SET Mnemonic Operand Byte Clock Operation Flag Z AC CY how 2 Do Em 515 pm INC CY Az Ao Am 1 x CY Ao lt Az Ama lt Am x CY Ao Az CY Ami Am x 1 gt gt saddr bit sfr bit PSW bit HL bit saddr bit sfr bit PSW bit HL bit C C CALL laddr16 SP 1 lt 3 SP 2 lt PC 3 PC addr16 SP SP 2 CALLT addr5 SP 1 lt PC 1 SP 2 lt PC 1 lt 00000000 addr5 1 PC lt
45. VOUMOO CHAPTER 5 EXPLANATION OF INSTRUCTIONS 5 10 Unconditional Branch Instruction The following is an unconditional branch instruction BR 102 User s Manual U11047EJ3VOUMOO 101 CHAPTER 5 EXPLANATION OF INSTRUCTIONS Branch Unconditional Branch Instruction format BR target Operation PC lt target Operand B Description e This is an instruction to branch unconditionally e The word data of the target address operand target is transferred to PC and program branches Description example BR AX The AX register contents are regarded as an address to which the program branches 102 Users Manual U11047EJ3VOUMOO CHAPTER 5 EXPLANATION OF INSTRUCTIONS 5 11 Conditional Branch Instructions The following are conditional branch instructions BC 104 BNC 105 BZ 106 BNZ 107 BT 108 BF 109 DBNZ 110 User s Manual U11047EJ3VOUMOO 103 CHAPTER 5 EXPLANATION OF INSTRUCTIONS Branch if Carry Conditional Branch with Carry Flag CY 1 Instruction format BC addr16 Operation PC 2 jdisp8 if CY 1 Operand Operand addr16 Description e When CY 1 program branches to the address specified with the operand When CY 0 no processing is carried out and the subsequent instruction is executed Description example BC 300H When CY 1 program branches to 0300H with the start of this instruction set in the range of a
46. ag is cleared 0 If the addition generates a carry from bit 3 to bit 4 the AC flag is set 1 In all other cases the AC flag is cleared 0 Description example ADDC A HL The A register contents the contents at address HL register and the CY flag are added and the result is stored in the A register User s Manual U11047EJ3VOUMOO 67 CHAPTER 5 EXPLANATION OF INSTRUCTIONS Subtract Byte Data Subtraction Instruction format SUB dst src Operation dst CY lt dst src Operand A e byte Description e The source operand src specified with the 2nd operand is subtracted from the destination operand dst specified with the 1st operand and the result is stored in the destination operand dst and the CY flag The destination operand be cleared to 0 by equalizing the source operand src and the destination operand dst e If the subtraction shows that dst is 0 the Z flag is set 1 In all other cases the Z flag is cleared 0 9 If the subtraction generates a borrow at bit 7 the CY flag is set 1 In all other cases the CY flag is cleared 0 e If the subtraction generates a borrow from bit 4 to bit 3 the AC flag is set 1 In all other cases the AC flag is cleared 0 Description example SUB A D The D register is subtracted from the A register and the result is stored in the A register 68 User s Manual U11047EJ3VOUMOO CHAPTER 5 EXPLANATION OF INSTRUCTIONS Subtrac
47. ber English Japanese HPD789166 789167 789176 789177 Preliminary Product Information To be prepared U14017J uPD78F9177 Preliminary Product Information To be prepared U14022J 789177 Subseries User s Manual To be prepared be prepared User s Manual U11047EJ3VOUMOO 9 e uPD789197AY Subseries Document Name Document Number English Japanese uPD789196AY 789197AY Preliminary Product Information U13853E U13853J HPD78F9197Y Preliminary Product Information U13224E U13224J HPD789217Y Subseries User s Manual U13186E U13186J 9 789217 Subseries Document Name Document Number English Japanese 789216 789217Y Preliminary Product Information U13196E U13196J HPD78F9217Y Preliminary Product Information U13205E U13205J HPD789217Y Subseries User s Manual U13186E U13186J 9 uPD789407A 789417A Subseries Document Name Document Number English Japanese LPD789405A 789406A 789407A 789415A 789416A 789417A Data Sheet be prepared U14024J LPD78F9418A Data Sheet To be prepared To be prepared 789407 789417A Subseries User s Manual To be prepared U13952J uPD789800 Subseries Document Name Document Number English Japanese uPD789800 Data Sheet U12627E U12627J HPD78F9801 Preliminary Product Information U12626E U12626J 789800 Subseries User s Manual U12978E U12978J e uPD789842 Subseries Document Name Document Number English Japanese
48. ddress specified with the 2nd operand addr16 If the 1st operand bit contents have not been cleared 0 no processing is carried out and the subsequent instruction is executed Description example BF P2 2 1549H When bit 2 of port 2 is 0 program branches to address 1549H with the start of this instruction set in the range of addresses 14C6H to 15C5H User s Manual U11047EJ3VOUMOO 109 CHAPTER 5 EXPLANATION OF INSTRUCTIONS Decrement and Branch if Not Zero Conditional Loop R1 z 0 Instruction format DBNZ dst addr16 Operation dst lt dst 1 then PC b jdisp16 if dst R1 0 Operand Description e One is subtracted from the destination operand dst contents specified with the 1st operand and the subtraction result is stored in the destination operand dst e f the subtraction result is not 0 program branches to the address indicated with the 2nd operand addr16 When the subtraction result is 0 no processing is carried out and the subsequent instruction is executed e The flag remains unchanged Description example DBNZ B 1215H The B register contents are decremented If the result is not 0 program branches to 1215H with the start of this instruction set in the range of addresses 1194H to 1293H 110 User s Manual U11047EJ3VOUMOO CHAPTER 5 EXPLANATION OF INSTRUCTIONS 5 12 CPU Control Instructions The following are CPU control instructions NOP 112
49. ddresses 027FH to 037EH 104 User s Manual U11047EJ3VOUMOO CHAPTER 5 EXPLANATION OF INSTRUCTIONS Branch if Not Carry Conditional Branch with Carry Flag CY 0 Instruction format BNC addr16 Operation PC PC 2 jdisp8 if CY 0 Operand Operand addr16 Description e When CY 0 program branches to the address specified with the operand When CY 1 no processing is carried out and the subsequent instruction is executed Description example BNC 300H When CY 0 program branches to 0300H with the start of this instruction set in the range of addresses 027FH to 037EH User s Manual U11047EJ3VOUMOO 105 CHAPTER 5 EXPLANATION OF INSTRUCTIONS Branch if Zero Conditional Branch with Zero Flag 2 1 Instruction format BZ addr16 Operation PC PC 2 jdisp8 if Z 1 Operand Operand addr16 Description e When Z 1 program branches to the address specified with the operand When Z 0 no processing is carried out and the subsequent instruction is executed Description example DEC B BZ 3C5H When the B register is 0 program branches to 03C5H with the start of this instruction set in the range of addresses 0344H to 0443H 106 User s Manual U11047EJ3VOUMOO CHAPTER 5 EXPLANATION OF INSTRUCTIONS Branch if Not Zero Conditional Branch with Zero Flag 2 0 Instruction format BNZ addr16 Operation PC PC 2 jdisp8 if Z 0 Operand
50. e 0000H to 0027H uPD789197AY 789217 18 1 9 Vector Table 0000H to 0023H uPD789407A uPD7894174A 19 1 10 Vector Table 0000H to 0019H uPD789800 Subseries renes 19 1 11 Vector Table 0000H to 0023H uPD789842 5 19 1 12 Internal Data Memory Space of 78 05 Series 20 4 1 Representation and Description Formats u 40 User s Manual U11047EJ3VOUMOO 13 14 User s Manual U11047EJ3VOUMOO CHAPTER 1 MEMORY SPACE 1 4 Memory Space The 78K 0S Series product program memory map varies depending on the internal memory capacity For details of the memory mapped address area refer to the User s Manual of each product 1 2 Internal Program Memory Internal ROM Space The 78K 0S Series product has internal ROM in the address space shown below Program and table data etc are stored in ROM This memory space is usually addressed by the program counter PC Table 1 1 Internal ROM Space of 78K 0S Series Products 1 2 X Capacity 2 Kbytes 4 Kbytes 8 Kbytes 12 Kbytes 16 Kbytes 24 Kbytes 32 Kbytes Address 0000H to 0000H to 0000H to 0000H to 0000H to 0000H to 0000H to
51. es Description e The destination operand dst is set 1 9 When the destination operand dst is CY or PSW bit only the corresponding flag is set 1 Description example OFE55H 1 Bit 1 of FE55H is set 1 User s Manual U11047EJ3VOUMOO 89 CHAPTER 5 EXPLANATION OF INSTRUCTIONS Clear Single Bit Carry Flag 1 Bit Data Clear Instruction format CLR1 dst Operation dst 0 Operand Flag dst PSW bit dst CY In all other cases Description The destination operand dst is cleared 0 9 When the destination operand dst is CY or PSW bit only the corresponding flag is cleared 0 Description example CLR1 P3 7 Bit 7 of port 3 is cleared 0 90 User s Manual U11047EJ3VOUMOO CHAPTER 5 EXPLANATION OF INSTRUCTIONS Not Single Bit Carry Flag 1 Bit Data Logical Negation Instruction format NOT1 dst Operation dst dst Operand Description The CY flag is inverted Description example NOT1 CY The CY flag is inverted User s Manual U11047EJ3VOUMOO 91 CHAPTER 5 EXPLANATION OF INSTRUCTIONS 5 8 CALL RETURN Instructions The following are call return instructions CALL 93 CALLT 94 RET 95 RETI 96 92 User s Manual U11047EJ3VOUMOO CHAPTER 5 EXPLANATION OF INSTRUCTIONS Call Subroutine Call 16 Bit Direct Instruction format CALL target Operation SP 1 PC SP 2 lt
52. es 4 2 1 Description of instruction code table Bn Data Low High byte Saddr offset Sfr offset Low High adar jdisp 184 Immediate data corresponding to bit 8 bit immediate data corresponding to byte 16 bit immediate data corresponding to word 16 bit address lower 8 bit offset data corresponding to saddr sfr 16 bit address lower 8 bit offset data 16 bit immediate data corresponding to addr16 Signed two s complement data 8 bits of relative address distance between the start and branch addresses of the next instruction 5 bits of immediate data corresponding to addr5 User s Manual U11047EJ3VOUMOO 51 CHAPTER 4 INSTRUCTION SET 4 2 2 Instruction code list Mnemonic Operand Instruction Code _ 111911 1 Sema Ar foooosvoro riio mmm hem fooroores bens 9 1109 6 s Si hw 9 1 sma j erroris 1 SS foororooi tows mnan ees rrrooos om _ mw ____ T ____ T j he us 1 he snn ML m poen amema m f Bea 1 11011901 0m po p s
53. g malfunction CMOS devices behave differently than Bipolar or NMOS devices Inputlevels of CMOS devices must be fixed high or low by using a pull up or pull down circuitry Each unused pin should be connected to or GND with a resistor if it is considered to have a possibility of being an output pin All handling related to the unused pins must be judged device by device and related specifications governing the devices STATUS BEFORE INITIALIZATION OF MOS DEVICES Note Power on does not necessarily define initial status of MOS device Production process of MOS does not define the initial operation status of the device Immediately after the power source is turned ON the devices with reset function have not yet been initialized Hence power on does not guarantee out pin levels I O settings or contents of registers Device is not initialized until the reset signal is received Reset operation must be executed immediately after power on for devices having reset function EEPROM is a trademark of NEC Corporation The export of these products from Japan is regulated by the Japanese government The export of some or all of these products may be prohibited without governmental license To export or re export some or all of these products from a country other than Japan may also be prohibited without a license from that country Please call an NEC sales representative The following products are manufactured and sold based on a license cont
54. he chapters to which the revision was applied 2nd Addition of the following target products Throughout LP D789026 789407 789417 789800 and 789806Y Subseries Modification of the format of the table of the internal data memory space of the CHAPTER 1 MEMORY 78K 0S Series products SPACE Throughout Addition of the following target products 0789046 789104 789114 789124 789134 789146 769156 789167 789177 789197AY 789217AY 789407A 789417A and 789842 Subseries CDU gt 789417 and 789806Y Subseries Modification of MOV PSW Modification of PSW byte instruction code 0 instruction code CHAPTER 4 INSTRUCTION User s Manual U11047EJ3VOUMOO 121 122 Users Manual U11047EJ3VOUMOO Although NEC has taken all possible steps essage to ensure thatthe documentation supplied to our customers is complete bug free and up to date we readily accept that From errors may occur Despite all the care and precautions we ve taken you may Name encounter problems in the documentation Please complete this form whenever Company you d like to report errors or suggest improvements to us Tel FAX Address Thank you for your kind support North America Hong Kong Philippines Oceania Asian Nations except Philippines NEC Electronics Inc NEC Electronics Hong Kong Ltd NEC Electronics Singapore Pte Ltd Corporate Communications Dept Fax 852 2886 9022 9044 Fax
55. ins the instructions of 78K 0S Series Each instruction is described in the unit of mnemonic including description of multiple operands The basic configuration of instruction descriptions is shown on the next page For the number of instruction bytes and operation codes refer to CHAPTER 4 INSTRUCTION SET All the instructions are common to 78K 0S Series products User s Manual U11047EJ3VOUMOO 57 CHAPTER 5 EXPLANATION OF INSTRUCTIONS DESCRIPTION EXAMPLE Mnemonic Full name Move Byte Data Transfer Meaning of instruction Instruction format MOV dst src Indicates the basic description format of the instruction Operation dst src Indicates instruction operation using symbols Operand Indicates operands that can be specified with this instruction Refer to 4 1 Operation for a description of each operand symbol A HL byte Flag Indicates the operation of the flag that changes by instruction execution Each flag operation symbol is shown in the legend Legend Unchanged Cleared to 0 Set to 1 Set or cleared according to the result Previously saved value is restored Description Describes the instruction operation in detail The contents of the source operand src specified by the 2nd operand are transferred to the destination operand dst specified by the 1st operand Description example MOV A 4DH 4DH is transferred to A register 58 User s Manual U11047EJ3VOUMOO C
56. is equal to one CPU clock fceu cycle selected by the processor clock control register PCC UJ User s Manual U11047EJ3VOUMOO 47 CHAPTER 4 INSTRUCTION SET 4 1 6 Instruction list by addressing 1 8 bit instructions MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP INC DEC ROR ROL RORC ROLC PUSH POP DBNZ 2nd operand byte saddr laddri6 PSW DE HL byte addr16 1 None 1st operand CMP Ll pee LL MOV DBNZ INC DEC Note Exceptr 48 User s Manual U11047EJ3VOUMOO CHAPTER 4 INSTRUCTION SET 2 16 bit instructions MOVW XCHW ADDW SUBW CMPW PUSH POP INCW DECW 2nd operand word AX SP None 1st operand ADDW MOVW MOVW MOVW SUBW XCHW CMPW u Note Only when BC DE HL 3 Bit manipulation instructions SET1 CLR1 NOT1 BT BF 2nd operand saddr None 1st operand A bit BT SET1 CLR1 sfr bit SET1 CLR1 saddr bit SET1 CLR1 PSW bit CLR1 HL bit CLR1 CY CLR1 NOT1 User s Manual U11047EJ3VOUMOO 49 CHAPTER 4 INSTRUCTION SET 4 Call instructions branch instructions CALL CALLT BR BC BNC BZ BNZ BT BF DBNZ 2nd operand laddr16 5 addr16 1st operand Basic instructions CALL CALLT 5 Other instructions RET RETI NOP El DI HALT STOP 50 User s Manual U11047EJ3VOUMOO CHAPTER 4 INSTRUCTION SET 4 2 Instruction Cod
57. it registers in pairs can be used as a 16 bit register AX BC DE and HL Registers can be described in terms of functional names X A C B E D L H AX BC DE and HL and absolute names RO to R7 and RPO to RP3 User s Manual U11047EJ3VOUMOO 25 CHAPTER 2 REGISTERS 26 Figure 2 6 General Purpose Register Configuration a Absolute name 16 bit processing 8 bit processing 2 1 b Functional name 16 bit processing 8 bit processing HL BC AX User s Manual U11047EJ3VOUMOO CHAPTER 2 REGISTERS 2 3 Special Function Registers SFRs Unlike general purpose registers special function registers have their own functions and are allocated to the 256 byte area FFOOH to FFFFH A special function register can be manipulated like a general purpose register by using operation transfer and bit manipulation instructions The bit units in which one register is to be manipulated 1 8 and 16 differ depending on the special function register type The bit unit for manipulation is specified as follows e 1 bit manipulation Describes a symbol reserved by the assembler for the 1 bit manipulation instruction operand sfr bit This manipulation can also be specified with an address e 8 bit manipulation Describes a symbol reserved by the assembler for the 8 bit manipulation instruction operand sfr This manipulation can
58. ity grade of each semiconductor product before using it in a particular application Standard Computers office equipment communications equipment test and measurement equipment audio and visual equipment home electronic appliances machine tools personal electronic equipment and industrial robots Special Transportation equipment automobiles trains ships etc traffic control systems anti disaster Systems anti crime systems safety equipment and medical equipment not specifically designed for life support Specific Aircraft aerospace equipment submersible repeaters nuclear reactor control systems life support systems and medical equipment for life support etc The quality grade of NEC semiconductor products is Standard unless otherwise expressly specified in NEC s data sheets or data books etc If customers wish to use NEC semiconductor products in applications not intended by NEC they must contact an NEC sales representative in advance to determine NEC s willingness to support a given application Note 1 NEC as used in this statement means NEC Corporation and also includes its majority owned subsidiaries 2 NEC semiconductor products means any semiconductor product developed or manufactured by or for NEC as defined above M8E 00 4 User s Manual U11047EJ3VOUMOO Regional Information Some information contained in this document may vary from country to country Before using any NEC product in your
59. lectronics Hong Kong Ltd Hong Kong Tel 2886 9318 Fax 2886 9022 9044 NEC Electronics Hong Kong Ltd Seoul Branch Seoul Korea Tel 02 528 0303 Fax 02 528 4411 NEC Electronics Singapore Pte Ltd United Square Singapore Tel 65 253 8311 Fax 65 250 3583 NEC Electronics Taiwan Ltd Taipei Taiwan Tel 02 2719 2377 Fax 02 2719 5951 NEC do Brasil S A Electron Devices Division Guarulhos SP Brasil Tel 55 11 6462 6810 Fax 55 11 6462 6829 J00 7 MAJOR REVISIONS IN THIS EDITION Throughout Addition of the following target products LPD789046 789104 789114 789124 789134 789146 789156 789167 789177 789197AY 789217AY 789407A 789417A and 789842 Subseries Deletion of the following target products 0789407 789417 and 789806Y Subseries The mark x shows major revised points 6 User s Manual U11047EJ3VOUMOO Readers Purpose Organization How to read this manual INTRODUCTION This manual is intended for users who wish to understand the functions of 768 05 Series products and to design and develop its application systems and programs 78K 0S Series products e uPD789014 Subseries 789011 789012 78P9014 e uPD789026 Subseries uPD789022 789024 789025 789026 78F9026 e uPD789046 Subseries 789046 78F9046 e uPD789104 Subseries uPD789101 789102 789104 e uPD789114 Subseries 789111 789112 789114 78F9116 e uPD789124 Subseries PD789121 789122
60. ock control register PCC User s Manual U11047EJ3VOUMOO 43 CHAPTER 4 INSTRUCTION SET Mnemonic Operand Byte Clock Operation Flag Z AC CY mee 399m mam bun mom e i ajeo MOVW rp AX ADD A saddr A laddr16 saddr byte A HL byte A byte saddr byte A saddr A laddr16 A HL byte A byte saddr byte A r A laddr16 A HL byte Note Only when rp BC DE or HL azar 515 10 saddr saddr byte paps ss j amp weaewem i s gt 2 4 a CY saddr ESES r 1 2 218 21277 5150 E NECS e A CY A HL byte A lt byte CY lt saddr byte A CY eA A CY lt A saddr A CY addr16 A CY A A CY lt HL byte Remark One instruction clock cycle is equal to one CPU clock fceu cycle selected by the processor clock control 44 register PCC User s Manual U11047EJ3VOUMOO CHAPTER 4 INSTRUCTION SET Operation Flag Z AC CY saddr byte ERES saddr CY saddr byte CY e 4 o aw PX s 6 aore eai NT oc ERE
61. ract with CP8 Transac regarding the EEPROM microcontroller patent These products cannot be used for an IC card SMART CARD Applicable products uPD789146 789156 789197 789217AY Subseries User s Manual U11047EJ3VOUMOO 3 Purchase of NEC components conveys a license under the Philips C Patent Rights to use these components in an system provided that the system conforms to the 2 Standard Specification as defined by Philips Applicable products uPD789197AY 789217AY Subseries The information in this document is current as of March 1999 The information is subject to change without notice For actual design in refer to the latest publications of NEC s data sheets or data books etc for the most up to date specifications of NEC semiconductor products Not all products and or types are available in every country Please check with an NEC sales representative for availability and additional information No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC NEC assumes no responsibility for any errors that may appear in this document NEC does not assume any liability for infringement of patents copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products No license express implied or otherwise
62. rmat RORC dst cnt Operation CY lt dsto 08 CY dstm 1 dstm x one time Operand Description The destination operand dst contents specified with the 1st operand are rotated just once to the right including the CY flag CY 7 0 Description example RORC A 1 The A register contents are rotated to the right by one bit including the CY flag 86 User s Manual U11047EJ3VOUMOO CHAPTER 5 EXPLANATION OF INSTRUCTIONS Rotate Left with Carry Byte Data Rotation to the Left with Carry Instruction format ROLC dst cnt Operation CY lt dst7 dsto CY dstm lt dstm x one time Operand Description e The destination operand dst contents specified with the 1st operand are rotated just once to the left including the CY flag CY 7 0 Description example ROLC A 1 The A register contents are rotated to the left by one bit including the CY flag User s Manual U11047EJ3VOUMOO 87 CHAPTER 5 EXPLANATION OF INSTRUCTIONS 5 7 Bit Manipulation Instructions The following are bit manipulation instructions 89 CLR1 90 NOTI 91 88 User s Manual U11047EJ3VOUMOO CHAPTER 5 EXPLANATION OF INSTRUCTIONS Set Single Bit Carry Flag 1 Bit Data Set Instruction format SET1 dst Operation dst lt 1 Operand sfr bit A bit PSW bit HL bit Flag dst PSW bit dst CY In all other cas
63. t with Carry Subtraction of Byte Data with Carry Instruction format SUBC dst src Operation dst CY dst src CY Operand Description The source operand src specified with the 2nd operand and the CY flag are subtracted from the destination operand dst specified with the 1st operand and the result is stored in the destination operand dst The CY flag is subtracted from the least significant bit This instruction is mainly used for subtraction of two or more bytes If the subtraction shows that dst is 0 the Z flag is set 1 In all other cases the Z flag is cleared 0 If the subtraction generates a borrow at bit 7 the CY flag is set 1 In all other cases the CY flag is cleared 0 If the subtraction generates a borrow from bit 4 to bit 3 the AC flag is set 1 In all other cases the AC flag is cleared 0 Description example SUBC A HL HL register address contents and the CY flag are subtracted from the A register and the result is stored in the A register User s Manual U11047EJ3VOUMOO 69 CHAPTER 5 EXPLANATION OF INSTRUCTIONS And Logical Product of Byte Data Instruction format AND dst src Operation dst lt dst src Operand A e byte Description e The destination operand dst specified with the 1st operand and the source operand src specified with the 2nd operand are ANDed bit wise and the result is stored in the destination operand dst
64. the register is saved restored upon generation of an interrupt request Stack addressing can address the internal high speed RAM area only Description example In the case of PUSH DE Instruction code 1 1 0 1 0 1 0 38 User s Manual U11047EJ3VOUMOO CHAPTER 4 INSTRUCTION SET This chapter lists the instruction set of the 78K 0S Series The instructions are common to all 78K 0S Series products User s Manual U11047EJ3VOUMOO 39 CHAPTER 4 INSTRUCTION SET 4 1 Operation 4 1 1 Operand representation and description formats In the operand column of each instruction an operand is described according to the description format for operand representation of that instruction for details refer to the assembler specifications When there are two or more description methods select one of them Uppercase characters are keywords and must be described as is Each symbol has the following meaning 9 Immediate data 9 5 Relative address e Absolute address Indirect address In the case of immediate data describe an appropriate numeric value or a label When using a label be sure to describe or For operand register description formats r and rp either functional names X A C etc or absolute names names in parentheses in the table below RO R1 R2 etc can be described Table 4 1 Operand Representation and Description Formats Description Format r X 80 A R1 R2
65. the source operand src and the destination operand dst e If the subtraction shows that dst is 0 the Z flag is set 1 In all other cases the Z flag is cleared 0 e If the subtraction generates a borrow at bit 15 the CY flag is set 1 In all other cases the CY flag is cleared 0 e As a result of subtraction the AC flag becomes undefined Description example SUBW AX 0ABCDH is subtracted from the AX register contents and the result is stored in the register 76 User s Manual U11047EJ3VOUMOO CHAPTER 5 EXPLANATION OF INSTRUCTIONS Compare Word Word Data Comparison Instruction format CMPW dst src Operation dst src Operand CMPW AX word Description e The source operand src specified with the 2nd operand is subtracted from the destination operand dst specified with the 1st operand The subtraction result is not stored anywhere and only the Z AC and CY flags are changed e If the subtraction result is 0 the Z flag is set 1 In all other cases the Z flag is cleared 0 e the subtraction generates a borrow at bit 15 the CY flag is set 1 In all other cases the CY flag is cleared 0 e As a result of subtraction the AC flag becomes undefined Description example CMPW AX 0 ABCDH is subtracted from the AX register and only the Z AC and CY flags changed comparison of the AX register and the immediate data User s Manual U11047EJ3VOU
66. tion by selecting 0FFH for the source operand src e the exclusive logical sum shows that all bits are 0 the Z flag is set 1 In all other cases the Z flag is cleared 0 Description example XOR A L The A and L registers are XORed bit wise and the result is stored in the A register 72 User s Manual U11047EJ3VOUMOO CHAPTER 5 EXPLANATION OF INSTRUCTIONS Compare Byte Data Comparison Instruction format CMP dst src Operation dst src Operand saddr byte A AC CMP A byte A 6 HL byte byte Description The source operand src specified with the 2nd operand is subtracted from the destination operand dst specified with the 1st operand The subtraction result is not stored anywhere and only the Z AC and CY flags are changed If the subtraction result is 0 the 2 flag is set 1 In all other cases the 2 flag is cleared 0 If the subtraction generates a borrow at bit 7 the CY flag is set 1 In all other cases the CY flag is cleared 0 If the subtraction generates a borrow from bit 4 to bit 3 the AC flag is set 1 In all other cases the AC flag is cleared 0 Description example CMP OFE38H 38H 38H is subtracted from the contents at address FE38H and only Z AC and CY flags are changed comparison of contents at address FE38H and the immediate data User s Manual U11047EJ3VOUMOO 73 CHAPTER 5 EXPLANATION OF INSTRUCTIONS 5 4 16 Bit
67. tructions 62 5 3 8 Bit Operation Instructions eese 65 5 4 16 Bit Operation Instructions coeur eterne cnet retinent eser 74 5 5 I ncrement Decrement Instructions U u u u 78 5 6 Rotate INStructins u u uu 83 57 Manipulation Instructions 88 5 8 CALL RETURN Instructions u UU UU S sa h uq Sasha 92 5 9 Stack Manipulation IRStructi ng III A I u kadaa panie iat 97 5 10 Unconditional Branch 101 5 11 Conditional Branch Instructions U u uu u u u u u 103 5 12 Control ASFC ONS uu 111 APPENDIX INSTRUCTION INDEX MNEMONIC BY FUNCTION rennen nnn 117 APPENDIX B INSTRUCTION INDEX MNEMONIC IN ALPHABETICAL ORDER 119 APPENDIX REVISION HISTORY s DIE SR 121 1
68. uct Information U13380E U13380J HPD78F9046 Preliminary Product Information U13546E U13546J 769046 Subseries User s Manual U13600E U13600J 8 User s Manual U11047EJ3VOUMOO e 789104 Subseries Document Document Number English Japanese 0789101 789102 789104 Data Sheet To be prepared 12815 789134 Subseries User s Manual U13045E U13045J e uPD789114 Subseries Document Name Document Number English Japanese HPD789111 789112 789114 Preliminary Product Information U13013E U13013J uPD78F9116 Preliminary Product Information U13037E U13037J HPD789134 Subseries User s Manual U13045E U13045J e uPD789124 Subseries Document Name Document Number English Japanese HPD789121 789122 789124 Preliminary Product Information U13025E U13025J uPD789134 Subseries User s Manual U13045E U13045J e uPD789134 Subseries Document Name Document Number English Japanese HPD789131 789132 789134 Preliminary Product Information U13015E U13015J 78 9136 Preliminary Product Information U13036E U13036J HPD789134 Subseries Users Manual U13045E U13045J e uPD789146 789156 Subseries Document Name Document Number English Japanese 789144 789146 789154 789156 Preliminary Product Information U13478E U13478J HPD78F9156 Preliminary Product Information To be prepared 13756 789146 789156 Subseries User s Manual U13651E U13651J e uPD789167 789177 Subseries Document Name Document Num
69. uction is frequently used for a counter for repeated operations the CY flag contents are not changed to hold the CY flag contents in multiple byte operation If dst is the B or C register or saddr and it is not desired to change the AC and CY flag contents the DBNZ instruction can be used Description example DEC OFE92H The contents at address FE92H are decremented 80 User s Manual U11047EJ3VOUMOO CHAPTER 5 EXPLANATION OF INSTRUCTIONS Increment Word Word Data Increment Instruction format INCW dst Operation dst dst 1 Operand Description The destination operand dst contents are incremented by only one Because this instruction is frequently used for increment of a register pointer used for addressing the Z AC and CY flag contents are not changed Description example INCW HL TheHL register is incremented User s Manual U11047EJ3VOUMOO 81 CHAPTER 5 EXPLANATION OF INSTRUCTIONS Decrement Word Word Data Decrement Instruction format DECW dst Operation dst dst 1 Operand Description The destination operand dst contents are decremented by only one e Because this instruction is frequently used for decrement of a register pointer used for addressing the Z AC and CY flag contents are not changed Description example DECW DE The DE register is decremented 82 User s Manual U11047EJ3VOUMOO CHAPTER 5 EXPLANATION OF INSTRUCTIONS 5 6

78K/0S Series 8-Bit Single-Chip Microcontroller Instructions

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