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PMC-CPU/440 - esd electronics, Inc.

1. FPGA PPC440 UIC Int FPGA Interrupt Mask Register bit Status Register bit Interrupt Source IRQO 1 28 FIFO Module HOSTCTRL FIFO_IE_FLAG STATUS FIFO_ISF Host Interrupt HOSTCTRL HOST_IE_FLAG STATUS HOST_ISF IRQ1 1 30 Custom Module HOSTCTRL CSTMOIE_FLAG STATUS CSTMO_ISF nIRQO IRQ2 2 3 CAN IP Cores HOSTCTRL CANIPIE_FLAG STATUS CANIP_ISF Custom Module HOSTCTRL CSTM1IE_FLAG STATUS CSTM1_ISF nIRQ1 nIRQ2 12 5 Using the FIFO module The PMC440 provides four hardware FIFOs that are implemented in the on board FPGA Each FIFO provides a 32 bit data port and has a capacity of 256 entries The FIFOs share a common external interrupt to the PPC440 CPU Each FIFO is represented by a set of two 32 bit registers The registers are accessible from the PPC440 and from the PCI bus This allows other PCI devices to write data into the FIFOs data ports The following sample code demonstrates the FIFO module usage The extract is taken from the PMC405V2 U Boot sourcecode define define define define u32 u32 L TRE OITS define define define define define define u32 us u32 u32 us u32 us us u32 BIEGEN FPGA_CLRBI FIFO EMP FIFO FUI FIFO LEVEL MASK 0x000000 FPGA interface BPGAVOULES Ee RTE TZ Gin pe in32 int HE CAMS ELE EES Pr OU sa eine Ep nz IS Dp QUES 32 p Simmer mmer Firo S i data CEEI
2. 4 Copy the new bootloader into flash gt cp b 100000 00000 80000 This command copies 0x80000 bytes starting at RAM location 0x100000 into flash memory starting at Oxfff00000 5 Enable protection of the flash area gt protect on f00000 LL7LLLL 6 Add the booting command to the bootcmd or preboot variable and save the environment Typically you will need to add some more commands to the bootcmd variable e g to start your operating system gt setenv fpga fpga loadb 0 fff00000 gt setenv bootcmd run fpga gt saveenv gt User Manual V 2027 21 Revision 1 1 All rights reserved Confidential Page Filename pmc440 me odt 2008 07 14 Copyright esd gmbh 2008 27 of 49 PMC CPU 440 g 11 Bootloader Status preliminary SD 7 Reset the board gt reset 11 5 7 painit Command The painit command does all the setup in order to use the PClAccess driver with a PMC440 painit requires a correctly setup pram variable see later chapter painit is typically called by the preboot command gt setenv preboot painit EE EE EI The painit command presets the reserved memory see pram variable in the following way 1 The reserved memory is zero d 2 The bootloader s representation of the bootloader environment is copied at the beginning of the reserved memory 3 The environment size e g 0x00000800 is written to the l
3. User Manual V 2027 21 Revision 1 1 All rights reserved Confidential Page Filename pmc440 me odt 2008 07 14 Copyright esd gmbh 2008 25 of 49 PMC CPU 440 T 11 Bootloader Status preliminary OG fifo level status 0 0 EMPTY iL 0 EMPTY 2 OS EMeP iy 3 0 EMPTY The command fifo read will dump all FIFOs content until the FIFOs are empty The command fifo wait will do the same but using an interrupt The fifo wait will dump FIFO data forever until it is interrupted by pressing CTRL C Finally the fifo write command can be used to write data to a FIFO s data port The FIFO data port can be addressed through giving its physical address or its number The first way can be used to access a FIFO data port over the PCI bus while the 2 method only works for a local FIFO access gt fifo write 84000080 12345678 3 writing 3 x 12345678 to fifo port at address 84000080 gt fifo write 2 aa5555aa 2 veiting 2 x BASIS EO ite 2 gt fifo fifo level status 0 0 EMPTY il O EMeP iy 2 2 NOT EMPTY 3 0 EMPTY gt 11 5 5 loadpci Start PCI firmware loading The loadpci command can be used on a pci target adapter platform to boot software images that are copied to RAM from a PCI master e g system CPU via the PCI bus firmware download It also provides a simple mechanism to remote execute bootloader commands on the pci target that are issued by a PCI master In most se
4. TE prarty prime Content OH Lro VEY void dump fifo pmc405v2 fpga fpga int f int n ECH neo walle etel PRGA W32 Gipga Stir T CTL amp FO BMWA i Peiner Scene 23d 308 n f ctrl amp FIFO LEVEL MASK FIFO FULL FPGA_IN32 amp fpga gt fifo f data age etol 8 FIFO OVERFLOW printf OVERFLOW n IGA CIMRIE INS LEESCH eet FIFO OVERFLOW else Same N 2 fifo command from PMC405V2 U Boot sourcecode iwe CO H tol E ime fleecy inte arge char elects pmc405v2_fpga_t fpga pmc405v2 foga t EPGA BA En int n 0 WS2 Wiel data i ierg Stef TYN init alocwic Of int count 0 int count2 0 switch argc case 1 User Manual V 2027 21 Revision 1 1 All rights reserved Confidential Page Filename pmc440 me odt 2008 07 14 Copyright esd gmbh 2008 40 of 49 PMC CPU 440 12 FPGA Status preliminary print all fifos status information primen Wieito leyel Statuen 5 Same Y pl foe 2 07 Zenn COUNT Li ENEE EE E ER printe Qa 3d s s s s n ap HET FIFO LEVEL MASK FIFO FULL Ciel SE RIT ROUTE o MITE a an CS amp PLIO BOIS TTT nen CEL amp PLRO SU REUZ Bid 2 VI sz SNOR T ctr iiei ETE OTOVERE KONE ROVERE KONE 79010 break case 2 7 completely read out fifo in ar leben VieSexcl A Palme UN 2 EE breet kruet lit E
5. 63 GND no REQ64 64 7 2 PMC P2 Connector Pin Signal Signal Pin 1 12V n c 2 A ne TDO bridged to TDI 4 5 TDI bridged to TDO GND 6 7 GND n c reserved 8 9 nc reserved n c reserved 10 11 MODE2 3 3V 12 13 PCI RST MODE3 14 15 3 3V MODE4 16 17 ne PME GND 18 19 AD 30 AD 29 20 21 GND AD 26 22 23 AD 24 3 3V 24 25 IDSEL AD 23 26 27 3 3V AD 20 28 29 AD 18 GND 30 31 AD 16 C BE2 32 33 GND IDSELB 34 35 TRDY 3 3V 36 37 GND STOP 38 39 PERR GND 40 41 3 3V SERR 42 43 C BE1 GND 44 45 AD 14 AD 13 46 47 M66EN AD 10 48 49 AD 08 3 3V 50 51 AD 07 n c REQB 52 53 3 3V GNTB 54 55 nc reserved GND 56 57 nc reserved EREADY 58 59 GND RESETOUT 60 61 n c ACK64 3 3V 62 63 GND MONARCH 64 User Manual V 2027 21 Filename pmc440 me odt Revision 1 1 2008 07 14 All rights reserved Confidential Copyright esd gmbh 2008 Page 16 of 49 PMC CPU 440 T 7 PMC Connectors Status preliminary OG 7 3 PMC PA I O Connector P4 is used to interface many PMC CPU 440 specific interfaces like the CAN buses I2C and FPGA I Os esd offers a PMC PIM module with two isolated CAN physical circuits 7 3 1 Pinout Pin Signal Name Notes Signal Name Notes Pin 1 FPGA lO lt 0 gt 3 3V IO FPGA IO lt 1 gt 3 3V IO 2 3 FPGA lO lt 2 gt 3 3V IO FPGA IO
6. JTAG Interface nn 3 ee err sees RRR TRAN mmmm a MAMA u 7 20 1202 A OFPINd gt Wd e 3 3 V Only Coding Hole G GE of cz a GND Pad Serial Number MAC IDs Fig 4 Bottomview of the PMC module User Manual V 2027 21 Revision 1 1 All rights reserved Confidential Page Filename pmc440 me odt 2008 07 14 Copyright esd gmbh 2008 12 of 49 PMC CPU 440 T Status preliminary OG 5 PPC440EPx GPIO Functions This chapter will be added later 6 JTAG Debug Interface The debug port is used during manufacturing tests and to flash an initial firmware 5 PPC440EPx GPIO Functions 6 1 JTAG Chain Description All JTAG capable circuits on the PMC440 module are connected to a common JTAG chain in the order as follows TDI gt CPU gt FPGA gt CPLD gt Phy0 gt Phy1 gt TDO Device position Function Device part number JTAG IR length in chain 1 CPU PPC440EPx AMCC 8 2 FPGA XC2S1200E FT256 Xilinx 6 3 CPLD XCI536XL VQAA Xilinx 8 4 5 Ethernet Phy VCS8601 Vitesse 2x4 6 2 JTAG Connector X5 The JTAG interface can be accessed through a 8 pin single in line 1 27mm plug It is possible to connect to the JTAG interface even when the PMC440 module is assembled on a carrier system Drillings in the PCB allow interfacing the JTAG port from the solder side of the module It can be connected via a contact strip connector It is recommended to build a
7. MSB 31 30 2 unused 29 20 10 Day 2 5 bed digits 0 366 19 14 6 Hour 1 5 bed digits 0 23 13 7 7 Minute 2 5 bcd digits 0 59 6 0 LSB 7 Second 2 5 bed digits 0 59 IRIG_TOD 0x0044 R IRIG B time that is used by transmitter The SBS field is calculated from the content of the IRIG_TIME register This register is read only Bits N Function MSB 31 17 15 unused 16 0 17 SBS straight binary seconds 0 86399 IRIG_CF 0x0048 R IRIG B control function flags that are inserted into the transmitted frame User Manual V 2027 21 Filename pmc440 me odt Revision 1 1 All rights reserved Confidential Page 2008 07 14 Copyright esd gmbh 2008 31 of 49 PMC CPU 440 T 12 FPGA Status preliminary OG Register Offset Mode Function Bits N Function MSB 31 27 5 unused 26 0 LSB 27 CFE control functions LSB bit0 corresponds to CFO CFO ist the first bit of the control functions filed in the IRIG B frame IRIG_CTRL 0x004c R W IRIG B modul configuration BU 1 receive framing error IRIG_RX_TIME 0x0050 R Received IRIG B time Bitfields in this register are identical to IRIG_TIME register IRIG_RX_TOD 0x0054 R Received IRIG B time Bitfields in this register are identical to IRIG_TOD register IRIG_RX_CF 0x0058 R Received IRIG B time
8. PMC CPU 440 Status preliminary OG PMC CPU 440 PowerPC 440EPx PrPMC module PMC CPU440 User Manual Product Order No V 2027 02 Vertraulich Weitergabe sowie Vervielf ltigung dieser Unterlage Verwertung und Confidential Copying of this document and giving it to others and the use or Mitteilung ihres Inhalts nicht gestattet soweit nicht ausdr cklich zugestanden communication of the contents thereof are forbidden without express authority Zuwiederhandlungen verpflichten zu Schadenersatz Alle Rechte vorbehalten Offenders are liable to payment of damages All rights are reserved User Manual V 2027 21 Revision 1 1 All rights reserved Confidential Page Filename pmc440 me odt 2008 07 14 Copyright esd gmbh 2008 1 of 49 PMC CPU 440 T Status preliminary OG Der Inhalt dieses Handbuches wurde mit gr ter Sorgfalt erarbeitet und gepr ft esd bernimmt jedoch keine Verantwortung f r Sch den die aus Fehlern in der Dokumentation resultieren k nnten Insbesondere Beschreibungen und technische Daten sind keine zugesicherten Eigenschaften im rechtlichen Sinne esd hat das Recht nderungen am beschriebenen Produkt oder an der Dokumentation ohne vorherige Ank ndigung vorzunehmen wenn sie aus Gr nden der Zuverl ssigkeit oder Qualit tssicherung vorgenommen werden oder dem technischen Fortschritt dienen S mtliche Rechte an der Dokumentation liegen bei esd Die Weitergabe an Dritte und Ve
9. V 2027 21 Revision 1 1 All rights reserved Confidential Page Filename pmc440 me odt 2008 07 14 Copyright esd gmbh 2008 28 of 49 PMC CPU 440 T 11 Bootloader Status preliminary CSD Example gt setenv pcidelay 2000 gt BEVEN 11 6 2 ptm1la ptmims ptm2la and ptm2ms Variables This set of bootloader environment variables can be used to overwrite the default PCI memory resources that are requested by the PMC module Each PCI address space of the PPC440EPx s PCI bridge is configured by a set of variable ptmXla and pciXms X stands for the two address spaces 1 and 2 e The ptmXla determine the 440EPx local base address for the corresponding PCI address translation e PtmXms setup the address window size through a size mask size 1 The LSB enables the address space When the variables are not set these are the defaults e ptmiia 0 ptmims installed_mem_size 1 1 e This setup enables BAR1 to map the complete SDRAM e ptm2la 0xef000000 ptm2ms Oxff000001 e This setup enabled BAR2 to map the 440EPx s internal peripherals e g GPIO registers and the FPGA internal registers See the 440EPx usermanual for more details 11 6 3 pram Variable The pram variable is used to reserve RAM that is not used by the bootloader When pram is set the variable mem is automatically set to the amount of available RAM total RAM pram The reserved RAM is used by the esd PClAccess driver Pram must
10. L FIFO_COUNT 4 struct pmc405v2 foga s T E E STEET E v p ae fei Rz Him iLO Criel regester 24 FIFO IE FIFO OVERFLOW 1 lt lt L lt lt l lt 1 lt lt Deich Ox silizeo usA 212 irig time Jg agl Jg Gie pad2 irig rx time pad3 3 Ws derer oftsert int p int p amp 0x0040 0x0050 User Manual V 2027 21 Filename pmc440 me odt Revision 1 1 2008 07 14 All rights reserved Confidential Copyright esd gmbh 2008 Page 39 of 49 PMC CPU 440 12 FPGA Status preliminary us2 hostcerl offset 0x0060 32 pach Lem A Bier MSZ 113 SERVICE mmm Fito s Eent COUN FE 77 00060 00097 typedef struct pmc405v2 roga s pmc405v2 fpga t status register define SEO HS FILO ILS Ie L g TR Inosiceiciel register define HOSTCTRL FTEOTI SIE een Ho SICHERTE GA ee 21 Frac il lt lt 2 FPGA to PPC interrupt define FPGA IRQ 31 HiME Goe EE EE FIFO module interrupt handler int fpga_interrupt pmc405v2 fpga_t fpga iim ze p mot ior ms 24 WS2 status WIC INOZ Mitre SSiceeuls check for interrupt from fifo module ii etatus amp STATUS PITO ISE disable mask this int source FPGA OUT32 amp fpga gt hostctrl HOSTCTRL FIFOIE GATE ze Op got _fifoirg 1 trigger backend RED E E
11. plus any associated interface definition files plus the scripts used to control compilation and installation of the executable However as a special exception the source code distributed need not include anything that is normally distributed in either source or binary form with the major components compiler kernel and so on of the operating system on which the executable runs unless that component itself accompanies the executable If distribution of executable or object code is made by offering access to copy from a designated place then offering equivalent access to copy the source code from the same place counts as distribution of the source code even though third parties are not User Manual V 2027 21 Revision 1 1 All rights reserved Confidential Filename pmc440 me odt 2008 07 14 Copyright esd gmbh 2008 Page 47 of 49 PMC CPU 440 14 Appendix Status preliminary compelled to copy the source along with the object code 4 You may not copy modify sublicense or distribute the Program except as expressly provided under this License Any attempt otherwise to copy modify sublicense or distribute the Program is void and will automatically terminate your rights under this License However parties who have received copies or rights from you under this License will not have their licenses terminated so long as such parties remain in full compliance 5 You are not required to accept this License since y
12. 49 User Manual V 2027 21 Filename pmc440 me odt PMC CPU 440 T Status preliminary OG 12 FPGA Bits Name Function 8 LEDA_MODE When set to 1 LEDA frontpanel is controlled by CTRLB LEDA When set to 0 LEDA is pulsed by an interrupt coming from an even 0 2 CAN IP core or by nIRQ1 from the FPGA s custom module Default after reset 1 7 2 reserved unused reads always 0 1 LEDB Controls the state of LEDB on the PMC s frontpanel when CTRLB LEDB_MODE bit is set to 1 Default after reset 0 0 LEDA Controls the state of LEDA on the PMC s frontpanel when CTRLB LEDA_MODE bit is set to 1 Default after reset 0 12 3 4 TSCTRL Timestamp unit control register 0x0018 Bits Name Function MSB reserved unused 31 5 reads always 0 5 TS_CFRSTEN Enable timestamp counter reset via IRIG B control flags 4 TS_MRST Timestamp manual reset write 1 to reset timestamp counter reads always 0 3 TS_XRSTEN Timestamp reset enable 1 enable reset of timestamp counter via external RESET signal on Pn4 2 0 TS_SRC 2 0 Timestampcounter clock source select 000 FPGA internal 100kHz clock 010 external CLOCK signal on Pn4 other combinations of the TS_SRC bits are reserved for future use Note Write 0x0000 0000 to TSCTRL for testing and read the current 64 bit counter value from offset 0x0010 and 0x0014 This uses the FPGA internal 100kHz timest
13. Bitfields in this register are identical to IRIG_CF register reserved HOSTCTRL 0x0060 R W Host control register This register can be used to request an interrupt service by the PPC440 This is an alternative way than a write access to the PCI_COMMAND register for an other PCI device e g host CPU to trigger an interrupt The implementation of PCI configuration cycles as needed for access to the PCI COMMAND register is very slow and time consuming on some operating systems e g MS Windows with RTX extension The HOSTCTRL register also provides interrupt masking capabilities for the FIFO module and the optional FPGA custom module reserved DDFSCTRL 0x0070 R W DDFS control register ADPLL phase error see detailed description below DDFSINC 0x0074 R DDFS increment value see detailed description below reserved FIFOO_DATA 0x0080 R W FIFO 0 data port FIFOO_CTRL 0x0084 R W FIFO 0 control status register FIFO1_DATA 0x0088 R W FIFO 1 data port FIFO1_CTRL 10x008c R W FIFO 1 control status register FIFO2_DATA 0x0090 R W FIFO 2 data port FIFO2_CTRL 10x0094 R W FIFO 2 control status register FIFO3_DATA 0x0098 R W FIFO 3 data port FIFO3_CTRL 0x009c RW FIFO 3 control status register User Manual V 2027 21 Revision 1 1 All rights reserved Confidential Page Filename pmc440 me odt 2008 07 14 Copyright esd gmbh 2008 32 of 49 PMC CPU 44
14. FPGA Status preliminary OG 12 2 FPGA Registers See chapter 8 for local FPGA base addresses All registers are 32bit wide Bit 31 is MSB bit 0 is LSB Register Offset Mode Function CTRL A 0x0000 R W Mode Control register Pn4 IO configuration GPIO alternative functions see description below STATUS 0x0004 Status register see description below CTRLB 0x0008 R W Secondary mode control register front panel LED control LED behavior see description below 0x000c reserved TSH 0x0010 TSL 0x0014 64 bit local timestamp counter The clock source and frequency can be setup by the TSCTRL register TSCTRL 0x0018 Timestamp unit control register reserved TSLOH 0x0020 TSLOL 0x0024 64 bit local timestamp latch for CANO TSH TSL is latched into these registers when a hardware interrupt from the CAN controller 0 occurs The register stays unchanged until the next falling edge of the interrupt line TSL1H 0x0028 TSL1IL 0x002c 64 bit local timestamp latch for CANT TSH TSL is latched into these register when a hardware interrupt from the CAN controller 1 occurs The register stays unchanged until the next falling edge of the interrupt line reserved IRIG_TIME 0x0040 R W IRIG B time that is used by transmitter The time can be set by a write to this register Bits N Function
15. Gnomovision comes with ABSOLUTELY NO WARRANTY for details type show w This is free software and you are welcome to redistribute it under certain conditions type show c for details The hypothetical commands show wi and show ci should show the appropriate parts of the General Public License Of course the commands you use may be called something other tha mouse clicks or menu items w You should also get your empl school if any to sign a co necessary Here is a sample Yoyodyne Inc hereby disc Gnomovision which makes lt signature of Ty Coon gt 1 A Ty Coon President of Vice This General Public License d proprietary programs If you consider it more useful to pe library If this is what you Public License instead of thi n show wi and show c they could even be atever suits your program oyer if you work as a programmer or your pyright disclaimer for the program if alter the names laims all copyright interest in the program passes at compilers written by James Hacker pril 1989 oes not permit incorporating your program into r program is a subroutine library you may rmit linking proprietary applications with the want to do use the GNU Lesser General s License User Manual V 2027 21 Filename pmc440 me odt Revision 1 1 2008 07 14 All rights reserved Confidential Copyright esd gmbh 2008 Page 49 of 49
16. OUT RS232 request to send 2 port User Manual V 2027 21 Revision 1 1 All rights reserved Confidential Page Filename pmc440 me odt 2008 07 14 Copyright esd gmbh 2008 18 of 49 PMC CPU 440 7 PMC Connectors Status preliminary SD Signal Name Direction Description CTSS1 IN RS232 clear to send 2 port SDA R VO I2C bus pulled up against 3 3V SCL_R UO GND GND Ground Note All output signals except the CAN signals are using 3 3V signalling All inputs but the I2C signals are 5V tolerant 8 Local Memory Map The PPC440EPx CPU uses more than 32 bits for physical addresses The U Boot bootloader configures the MMU in a way that physical addesses above 4GB will be mapped below the 4 GB border The address translation just masks all high bits Example GPIO controller 0 has physical address Ox1ef600b00 It is mapped to Oxef600b00 by U Boot Please note that this may be handled differently depending on the used operating system Start Address End Address Function 0x0 0000 0000 0x0 0fff ffff SDRAM 256MB 0x1 8000 0000 Oxl bfff ffff 1GB PCI memory address space 0x8000 0000 Oxbfff ffff Note This is the default setup as initialized by the U Boot bo
17. PMC Box clock reset distribution logic PIM CPU 440 PBOX PIM module with Beckhoff ET1100 V 2028 02 ESC EtherCAT slave interface PMC CPU 440 VxW VxWorks BSP V 2027 30 PMC CPU 440 Linux Linux BSP V 2027 32 PMC CPU 440 QNX QNX BSP V 2027 33 PMC CPU 440 OS9 OS 9 BSP V 2027 34 User Manual V 2027 21 Revision 1 1 All rights reserved Confidential Page Filename pmc440 me odt 2008 07 14 Copyright esd gmbh 2008 45 0f 49 PMC CPU 440 14 Appendix Status preliminary 14 Appendix 14 1 GNU General Public License GNU GENERAL PUBLIC LICENSE Version 2 June 1991 Copyright C 1989 1991 Free Software Foundation Inc 51 Franklin Street Fifth Floor Boston MA 02110 1301 USA Everyone is permitted to copy and distribute verbatim copies of this license document but changing it is not allowed Preamble The licenses for most software are designed to take away your freedom to share and change it By contrast the GNU General Public License is intended to guarantee your freedom to share and change free software to make sure the software is free for all its users This General Public License applies to most of the Free Software Foundation s software and to any other program whose authors commit to using it Some other Free Software Foundation software is covered by the GNU Lesser General Public License instead You can apply it to your programs too When we speak of free software we are referring to freedom not price Our Gene
18. be set to the amount of reserved RAM in KiB gt setenv pram 4096 gt SUE Or User Manual V 2027 21 Revision 1 1 All rights reserved Confidential Page Filename pmc440 me odt 2008 07 14 Copyright esd gmbh 2008 29 of 49 PMC CPU 440 T 12 FPGA Status preliminary OG 12 FPGA The PMC CPU 440 comes with a Xilinx Spartan 3E FPGA part XC3S1200E 4FTG256C installed The FPGA provides several functions that are described in this chapter 12 1 Functional Blocks e IRIG B decoding of B100 timecode format input source selection P4 rear differential input default HA rear TTL input local time code generation e Multiple CAN IP cores default 2 max 8 e CAN timestamping unit local time 64 bit counter with 10us resolution timestamp latching for CAN free running counter sync ed to IRIG B signal digital PLL or external clock e default external clock from Pn4 resetable via register access or IRIG B control function flag 100kHz CLOCK_OUT RESET_OUT generation on Pn4 for simple syncronisation of external peripherals e Pn4 frontpanel GPIO configuration usage as GPIO alternative functions IRIG B timestamp syncing signals Hardware FIFOs e Custom module for customized extensions of the PMC CPU 440 User Manual V 2027 21 Revision 1 1 All rights reserved Confidential Page Filename pmc440 me odt 2008 07 14 Copyright esd gmbh 2008 30 of 49 PMC CPU 440 12
19. esd gmbh 2008 Page 48 of 49 PMC CPU 440 14 Appendix Status preliminary 11 BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE THERE IS NO WARRANTY FOR THE PROGRAM TO THE EXTENT PERMITTED BY APPLICABLE LAW EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND OR OTHER PARTIES PROVIDE THE PROGRAM AS IS WITHOUT WARRANTY OF ANY KIND EITHER EXPRESSED OR IMPLIED INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF ERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU SHOULD THE PROGRAM PROVE DEFECTIVE YOU ASSUME THE COST OF ALL NECESSARY SERVICING REPAIR OR CORRECTION 12 IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING WILL ANY COPYRIGHT HOLDER OR ANY OTHER PARTY WHO MAY MODIFY AND OR REDISTRIBUTE THE PROGRAM AS PERMITTED ABOVE BE LIABLE TO YOU FOR DAMAGES INCLUDING ANY GENERAL SPECIAL INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE USE OR INABILITY TO USE THE PROGRAM INCLUDING BUT NOT LIMITED TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES END OF TERMS AND CONDITIONS How to Apply These Terms to Your New Programs If you develop a new program and you want it to be of the greatest possibl
20. 0 12 FPGA Status preliminary OG 12 3 Register Description 12 3 1 CTRL Register 0x0000 Bits Name Function 31 RESET_EN When set to 1 the RS485 RESET signal driver is enabled The RS485 driver circuit is located on the PMC405 PIM module When enabled the PMC440 is the source of the RESET signal When the PMC440 is not used with the PMC405 PIM this flag can be used to control the state ofthe TTL signal RESET_R_EN on Pn4 pin 62 Default after reset 0 30 CLOCK_EN When set to 1 the RS485 CLOCK signal driver is enabled The RS485 driver circuit is located on the PMC405 PIM module When enabled the PMC440 is the source of the CLOCK signal When the PMC440 is not used with the PMC405 PIM this flag can be used to control the state of the TTL signal CLOCK_R_EN on Pn4 pin 60 Default after reset 0 29 CLKRST_EN_CSTM When set to 1 the RESET EN and CLOCK EN signals on Pn4 see above are connected to the FPGA s custom module Default after reset 0 28 IRIGB_R_EN When set to 1 the RS485 output driver for IRIG B transmission on Pn4 on the PMC440 is enabled and IRIG_B_R_OUT_P _M become a differential output Default after reset 0 27 IRIGB_R_EN_CSTM When set to 1 the IRIGB_R_EN signal driver enable for RS485 transceiver is connected to the FPGA s custom module Default after reset 0 26 reserved Default after reset 0 25
21. 10 in the 32 bit custom address space 12 6 2 Sample Custom Module simple_io The PMC CPU 440 is shipped with a default FPGA image that includes the simple_io custom module This module implements a simple GPIO controller for 48 usable FPGA I Os that are available on the PMC s P4 connector The module is controlled by a couple of 32 bit registers The base address for these registers is ADDR_CSTM32_BASE 0xef08 0000 see chap 8 Registername Offset Function CSTM32_ID 0x0000 simple_io module identification 0x0000 0001 CSTM32_VER 0x0010 simple_io module version starting with 0x0000 0001 CSTM32_ORO 0x0020 Output register 0 each bit in this register controls the output level of a corresponding signal on the PMCs P4 FPGA IO lt 31 gt FPGA IO lt 0 gt In order to control the output state the pin must be User Manual V 2027 21 Revision 1 1 All rights reserved Confidential Page Filename pmc440 me odt 2008 07 14 Copyright esd gmbh 2008 43 of 49 PMC CPU 440 12 FPGA Status preliminary CSD enabled as output via the TCRO register see below Default 0x0000 0000 CSTM32_TCRO 0x0024 Tristate control register O each bit in this register controls the direction of a corresponding signal on the PMCs P4 FPGA IO lt 31 gt FPGA IO lt O gt A set bit enables the signal as output Default 0x0000 0000 CSTM32_IRO 0x0028 Input register 0 each bit mirrows t
22. 256 Bytes connected via I2C used for CPU strapping Watchdog CPU internal 4 selectable intervals 4ms 64ms 1s 16s 533 MHZ CPU clock 1 2 3 Realtime Clock RTC Type RX 8025 Epson NVRAM None Backup energy source Double layer capacitor Backup time Up to 1 week 1 2 4 PCI Interface Specification PCI 2 2 compatible Features host or target bus master 2 target address spaces BARs PCI clock 33 66 MHz Bus width 32 bit IO voltage 3 3V only the PCI interface is NOT 5V tolerant Interrupt non monarch INTA monarch INTA INTD User Manual V 2027 21 Filename pmc440 me odt Revision 1 1 2008 07 14 All rights reserved Confidential Copyright esd gmbh 2008 Page 8 of 49 PMC CPU 440 1 Overview Status preliminary SD 1 2 5 Serial Interfaces Number 2 Controller CPU internal 16550 compatible Physical Layer Port0 USB 1 1 device via FT232RQ USB to serial converter Port1 RS232 Lines RxD TxD CTS RTS Connector Port USB Mini B Port1 PMC P4 Baudrate Max 115200 baud Default baudrate on USB console is 115200 baud 8N1 1 2 6 CAN Interfaces Number 2 CAN controller esd CAN IP core in FPGA CAN protocol CAN 2 0A 2 0B Physical interface TTL no transceiver on board Bitrate 10 kbit s 1 Mbit s Bus t
23. 28 0 FPGA IRQO active low level sensitive 1 30 1 FPGA IRQ1 active low level sensitive 2 3 2 FPGA IRQ2 active low level sensitive 2 4 3 Ethernet PHY 0 active low level sensitive 0 27 4 Ethernet PHY 1 active low level sensitive 2 0 5 RTC active low level sensitive 2 1 6 PCI INTA active low level sensitive 1 18 7 PCI INTB active low level sensitive 1 19 8 PCI INTC active low level sensitive 1 20 9 PCI INTD active low level sensitive 9 2 PCI Interrupt Handling 9 2 1 Monarch Mode In monarch mode the PPC440EPx s external interrupts 6 to 9 see table above are used as PCI INTA PCI INTD inputs 9 2 2 Asserting PCI Interrupts In Non monarch Mode e Method I set API flag in PCICO_ICS register see PPC440EPx usermanual e Method Il an alternative way to assert the PCI INTA line as on the PMC CPU 405 is not supported 9 2 3 Asserting Local Interrupts From PCI Bus e Method I PCI master writes to PCI COMMAND register e Method Il PCI master writes to the FPGA s HOSTCTRL reigster see chap 12 2 10 PCI Configuration The PMC CPU 405 uses the following PCI identification Monarch PrPMC Class Subclasscode 0x0600 hostbridge Non Monarch Class Subclasscode 0x0b20 processor PPC Vendor ID Vendor ID 0x1014 0x1014 Device ID Device ID User Manual V 2027 21 Revision 1 1 All rights reserved Confidential Page Filename pmc440 me odt 2008 07 14 Copyright e
24. Intertace sees eee 9 1 2 8 USB Interface Host or Device eee 9 2 Installation INStrUCtiONS sees eee eee 10 eae TT ee Sees ee re Nee Tree 10 4 Top and Bottom Gide T 11 5 PPC440ERX GPIO gue te EE 13 SC JTAG Debug Ihlerffate ne ae a ee 13 6 1 JTAG Chain Descrpton nn sn nnnnnn 13 6 2 JTAG Connector 6 2 EE 13 7 PMCG Connechors sn ss snnennnennennennnnnnnnn 15 7 1 PMC P1 CGonnechor sese eee eee eee 15 7 2 PMC P2 CGonnechot essen sn ss sn aiaiai 16 7 3 PMC P4 UO CGonnechor nn EE EAEE EE E E E EEEE ERNE EEEE 17 Le DND Gill ae een eng 17 7 3 2 Signal Description 18 Ea Ee e gt PRRRNDERPANDEDEREEERDERPNPA DERITDELFIECREFHRENELTEHERRCHEBRLNEERDPEOEERREUPELEREDEREEEITOERPELERERENELEIREEPBELTEFTE 19 Gluten 20 9 1 External Interrupt Assignment eee eee eee eee eek 20 9 2 PCI Interrupt Ent ln GE 20 9 2 1 Monarch Mode E 20 9 2 2 Asserting PCI Interrupts In Non monarch Mode 20 9 2 3 Asserting Local Interrupts From PCI Bus eee 20 10 PCI CGonfguration nenn nnnnnnnnnennennnnnnnnnnnnnnnnnnnnnnnnnnnennnenn 20 11 Bootloader nn nn nnnnnennennnnnnnnnnnnnnnnnnnnnnnnnnenenenneennennnnenn 21 r Bs WIG lt T 21 11 2 Configuration and Console E 21 11 3 Default Bootloader Environment 22 11 4 Flash Update anne een 23 11 5 BSP Commande tens ak een en 24 11 5 1 irigb Get Set IRIGPBume nn ennennnennennnnnnnnnnnnne 24 11 5 2 inta Assert Deassert PCI interrupt line on PDMCAAU ee ceeecesceseceeeeeeeeeeeeeeeeeeees 24 11 5 3 sbe configu
25. Reset Init R LED 0 green Link Trafic ETH Port 0 o ETHO USB 2 0 Interface Host or Device Port Ethernet Port O as Fig 2 PMC CPU 440 Frontpanel 4 Top and Bottom Side The top side of the PMC CPU 440 PCB is covered by a an aluminium heatsink on most areas There are two 0 1 contacts near the frontpanel These can be used to install a strapping jumper By default the jumper is not installed when the boards are shipped In this case the CPU clocking and some other parameters are configured through the content of a serial EEPROM With the jumper installed a default configuration is active Jumper designator Function JP2 Installed Default configuration CPU runs at 533 Mhz and serial bootloader console is on serial port 1 on PMC P4 connector Not installed Configuration is read from I2C EEPROM The EEPROM content can be configured by the sbe bootloader command User Manual V 2027 21 Revision 1 1 All rights reserved Confidential Page Filename pmc440 me odt 2008 07 14 Copyright esd gmbh 2008 11 of 49 PMC CPU 440 4 Top and Bottom Side Status preliminary JP2 Strapping Jumper P4 P1 P2 Fig 3 Topview of the PMC module The PMC CPU 440 has one additional LED on the bottom side of the PCB This LEDs is visible when the PMC module is installed on a carrier board LED designator Color Function LED6 green Data indicator for USB console CON
26. U 440 T 11 Bootloader Status preliminary OG 11 5 3 sbe configure CPU strapping The sbe command is used to write CPU strapping configuration into an on board EEPROM This configuration is automatically read by the CPU on reset when the JP2 jumper see chapter 4 is not installed When the JP2 jumper is installed the PMC CPU 440 modules is configured from compiled in defaults So installing the JP2 jumper might be useful to bring up the module after incorrect data has been written to the strapping EEPROM Use the help or command to get a short command reference gt sbe sbe lt cpufreq 400 533 667 gt lt console uart 0 1 gt lt bringup delay 0 20s gt sbe takes up to 3 arguments The first argument is the desired CPU clock frequency Values of 400 533 and 667MHz are supported Attention Do not configure the module for 667MHz CPU frequncy when no 667MHz CPU type is installed The second argument configured the bootloader console port A value of 0 uses the CPU s first serial port for the U Boot console This port is available as the USB CON port on the frontpanel A value of 1 configures the CPU s seconds serial port as bootloader console This port is available on the PMC P4 connector The latter is also the default configuration with jumper JP2 installed The last argument is used to setup a bringup delay in units of seconds Following a board reset the first bootloader message on the serial co
27. amp clock source 12 3 5 HOSTCTRL Host control register 0x0060 Bits Name Function 31 6 RESERVED Always read 0 17 PMCRSTOUT_GATE see PMCRSTOUT_FLAG 16 PMCRSTOUT_FLAG This bit represents the state of PMC RESETOUT signal After reset this bit is set Clearing this bit can be used to assert the PMC RESETOUT signal The PMCRSTOUT_FLAG can only be modified when the PMCRSTOUT_GATE bit is set during the same write access to the HOSTCTRL register This makes modification of the PMCRSTOUT_FLAG possible without read modify write operations and without taking care of the other bits of the HOSTCTRL register 15 8 RESERVED Always read 0 User Manual V 2027 21 Revision 1 1 All rights reserved Confidential Page Filename pmc440 me odt 2008 07 14 Copyright esd gmbh 2008 36 of 49 PMC CPU 440 12 FPGA Bits Name Status preliminary SD Function 7 CSTM1IE_GATE see CSTM1IE_FLAG 6 CSTM1IE_FLAG 1 unmask interrupts from the FPGA custom module 0 mask interrupts from the FIFO module The CSTM1IE_FLAG can only be modified when the CSTM1IE_GATE bit is set during the same write access to the HOSTCTRL register This makes modification of the CSTM1IE_FLAG possible without read modify write operations and without taking care of the other bits of the HOSTCTRL register CSTMOIE_GATE see CSTMOIE_ FLAG CSTMOIE_FLAG 1 unmask interrupts from the FPGA
28. ary commands These variables can be executed using the run command 1 Load binary image from a TFTP server User Manual V 2027 21 Revision 1 1 All rights reserved Confidential Page Filename pmc440 me odt 2008 07 14 Copyright esd gmbh 2008 23 of 49 PMC CPU 440 T 11 Bootloader Status preliminary OG gt run load 2 When the previous command succeeded unprotect erase flash and reset gt run update Attention Please doublecheck the content of the oad and update variable before using them This will prevent you from running into trouble 11 5 BSP Commands The following U Boot BSP commands have been specially added to support the PMC CPU 440 functions Type help lt commana gt at the bootloader prompt to get a short command reference 11 5 1 irigb Get Set IRIG B time The irigb command will display the current IRIG B time IRIG B receiver local IRIG B generators time This command will change in the future because there will only be a single IRIG B time This command requires a booted FPGA with IRIG B core 11 5 2 inta Assert Deassert PCI interrupt line on PMC440 This command is only supported in non monarch configuration It can be used to manually assert the PCI INTA interrupt line for testing purposes User Manual V 2027 21 Revision 1 1 All rights reserved Confidential Page Filename pmc440 me odt 2008 07 14 Copyright esd gmbh 2008 24 of 49 PMC CP
29. ast 32bit memory location e g Ox3fffffc 4 The reserved memory size see pram in units of bytes is written before the previous value e g Oxffffff8 5 A CRC32 checksum is calculated over the two 32bit value and written at the third last memory location e g Oxffffff4 6 A 32bit zero 0x00000000 is written to the fourth last memory location e g Oxffffff0 Attention The behavior of painit will change with the next bootloader version because of an CPU errata 11 5 8 USB This chapter will be added later 11 5 9 resetout Command The PMC440 never asserts PMC RESETOUT automatically because this would lead to race conditions during power up or reset cycles But it is possible to assert RESETOUT manually using the resetout command Assert RESETOUT gt resetout 0 Attention Never add this command to any bootloader variable that is automatically executed after power on e g preboot or bootcmd This would lead to an uninteruptible reset loop 11 6 Special Environment Variables 11 6 1 pcidelay Variable The booloader variable pcidelay can be used to delay PCI enumeration through the bootloader When pcidelay is not set the bootloader on a PMC440 in monarch mode starts PCI enumeration as soon as possible EREADY is still checked When pcidelay is set to an amount of time in milliseconds of seconds the bootloader waits for this period checks EREADY and finally starts PCI enumeration User Manual
30. ck testing only 16 ETHO_LED1 Ethernet phy 0 LED1 output readback testing only 15 11 reserved unused read 0 12 CANIP_ISF CAN IP core interrupt status flag This bit indicates a pending interrupt from any CAN controller 11 CSTM1_ISF Custom module interrupt status flag This bit indicates a pending interrupt from the FPGA s custom module nIRQ1 nIRQ2 10 CSTMO_ISF Custom module interrupt status flag This bit indicates a pending interrupt from the FPGA s custom module nIRQO 9 FIFO_ISF FIFO module interrupt status flag This bit indicates a pending interrupt from the FIFO module 8 HOST_ISF Host interrupt status flag This bit indicates a pending host interrupt 7 6 reserved unused read 0 5 IRIGB_R_IN logic state of Pn4 TTL input signal 4 IRIGB_R_IN_PM logic state of Pn4 RS485 input signal 3 reserved unused read 0 2 reserved unused read 0 1 CLOCK_IN logic state of Pn4 CLOCK input signal 0 RESET_IN logic state of Pn4 RESET input signal 12 3 3 CTRLB Register 0x0008 Bits Name Function MSB reserved unused 31 10 reads always 0 9 LEDB_MODE When set to 1 LEDB frontpanel is controlled by CTRLB LEDB When set to 0 LEDB is pulsed by an interrupt coming from an odd 1 3 CAN IP core or by nIRQ2 from the FPGA s custom module Default after reset 1 Revision 1 1 2008 07 14 All rights reserved Confidential Page Copyright esd gmbh 2008 35 of
31. custom module 0 mask interrupts from the FIFO module The CSTMOIE_FLAG can only be modified when the CSTMOIE_GATE bit is set during the same write access to the HOSTCTRL register This makes modification of the CSTMOIE_FLAG possible without read modify write operations and without taking care of the other bits of the HOSTCTRL register FIFOIE_GATE see FIFOIE_FLAG FIFOIE_FLAG 1 unmask interrupts from the FIFO module FIFO interrupts must also be enabled for each FIFO in the corresponding FIFOx_CTRL register 0 mask interrupts from the FIFO module The FIFOIE_FLAG can only be modified when the FIFOIE_GATE bit is set during the same write access to the HOSTCTRL register This makes modification of the FIFOIE_FLAG possible without read modify write operations HCINT_GATE see HCINT_FLAG HCINT_FLAG 1 assert host interrupt host interrupts must be enabled via HOST_IE bit in the CTRL register 0 deassert host interrupt The HCINT_FLAG can only be modified when the HCINT_GATE bit is set during the same write access to the HOSTCTRL register This makes modification of the HCINT_FLAG possible without read modify write operations 12 3 6 DDFSCTRL DDFSINC Clock generator registers 0x0070 0x0074 The FPGA uses a DDFS direct frequency synthesis clock generator to synthesize a 100kHz reference clock This clock can be output on Pn4 and or directly passed to the timestamp unit The refer
32. d functionality to tne PMC440 onboard FPGA For extending the PMC440 FPGA esd provides the following files shipped in a zip archive that have to be added to an Xilinx ISE design project e pmc440_cstm_fpga_r7 pmc440 vhd top level VHDL source for PMC440 FPGA design e pmc440_cstm_fpga_r7 custom_module_pmc440 vhd example VHDL sourcecode to custom extension wrapper for custom modules e pmc440_cstm_fpga_r7 simple_io_custom_module_pmc440 vhd example VHDL sourcecode to custom extension simple GPIO controller e pmc440_cstm_fpga_r7 pmc440_custom_module_pimesc vhd example VHDL sourcecode to custom extension EtherCAT PIM module e pmc440_cstm_fpga_r7 pmc440_r7 ucf constraints file e pmc440_cstm_fpga_r7 pmc440_common ngc esd IP of fixed design parts as described in previous chapter of this document e pmc440_cstm_fpga r7 README_CustomDesign txt information text file After implementing the FPGA design the genererated bit file can directly be loaded into the PMC440 FPGA by using the bootloader s fpga command see above 12 6 1 Custom Module Conventions Some rules should be followed when implementing customized modules for the PMC440 FPGA e Each module must provide a 32 bit module ID at offset 0 in the 32 bit custom address space e IDs from 0x0000 0000 to Ox fff ffff are reservedfor esd So non esd custom modules must have the MSB of the ID field set to 1 e Each module must provide a 32 bit module version at offset 0x
33. dix ern a een 46 14 1 GNU General Public License nme ennennennnnnnnnnnnnnnnnnnnnnnnennnnnn 46 User Manual V 2027 21 Revision 1 1 All rights reserved Confidential Page Filename pmc440 me odt 2008 07 14 Copyright esd gmbh 2008 6 of 49 PMC CPU 440 T 1 Overview Status preliminary SD 1 Overview 1 1 Description Of The PMC CPU 440 Module The PMC CPU 440 is a PMC module in single PCI Mezzanine Card form factor It can act as PMC monarch PrPMC or as non monarch adapter target board Apart from a powerful CPU core the PowerPC 440EPx embedded processor integrates a DDR2 RAM controller a PCI bus interface a controller for serial interfaces and two gigabit ethernet MACs The module comes with DDR2 RAM and flash memories a double layer capacitor buffered realtime clock RTC and a FPGA A serial console is provided through an USB device port that integrates a USB to serial converter This is in accordance to modern PC technologies abandoning serial ports A second serial interface is accessible via the PMC I O connector with RS232 signal levels The module provides two 1000 BaseT gigabit ethernet port on the front panel Their link status and several other status information are indicated by 5 LEDs The on board FPGA provides extended flexibilities for specialized applications The default FPGA functionality includes two high speed CAN interfaces IRIG B timecode decoding and generation and much more Many FPGA pins are di
34. e Default after reset 00 13 12 IRIGB_R_OUTPM_MO configuration of IRIG B differential output on Pn4 DE 1 0 00 signal is driven low 01 signal is driven high 10 IRIG B output 11 signal is connected to the FPGA s custom module Default after reset 1 00 11 9 reserved Default after reset 000 8 HOST_IE Host control interrupt enable See HOSTCTRL register 7 4 reserved Default after FPGA reset 0000 3 2 reserved Default after FPGA reset 00 1 reserved Default after FPGA reset 0 0 reserved Default after FPGA reset 0 User Manual V 2027 21 Revision 1 1 All rights reserved Confidential Page Filename pmc440 me odt 2008 07 14 Copyright esd gmbh 2008 34 of 49 PMC CPU 440 12 FPGA Status preliminary OG 12 3 2 STATUS Register 0x0004 The logic state readback functionality is independant from any alternative function Bits Name Function MSB 31 24 VERSION FPGA version current version is 0x07 23 20 HW_REV PMC440 hardware revision 1 x 0 lt x lt 15 This bit field is updated by the bootloader after FPGA booting see chapter 5 on how to query the hardware revision 19 ETH1_LED2 Ethernet phy 1 LED2 output readback testing only 18 ETH1_LED1 Ethernet phy 1 LED1 output readback testing only 17 ETHO_LED2 Ethernet phy 0 LED2 output readba
35. e dedicated signal directions 4 All FPGA IO signals have 22 Ohm series resistors 5 Above notes have the folloing meaning e 3 3V 3 3V only digital signal These signals are not 5V tolerant User Manual V 2027 21 Revision 1 1 All rights reserved Confidential Page Filename pmc440 me odt 2008 07 14 Copyright esd gmbh 2008 17 of 49 PMC CPU 440 T 7 PMC Connectors Status preliminary OG e 5V 5V tolerant input or 5V driving output e input only O output only IO bidirectional signal e PWR power supply signal 5V GND e n c these signals are not connected on the PMC module Special configurations may exists where these signals are used Do not connect to these signals e RS232 RS232 signals logic 1 9V logic 0 9V e RS485 RS485 differential signals 7 3 2 Signal Description Signal Name Direction Description CLOCK_IN IN 3 3V 5V tolerant general purpose input This signal is logically connected to a FPGA pin CLOCK_IN can optionally be configured as a timestamp reference clock source CLOCK_OUT OUT LVTTL general purpose output This signal is logically connected to a FPGA pin CLOCK OUT can optionally be configured as a timestamp reference clock output CLOCK_EN OUT LVTTL general purpose output This signal is logically connected to a FPGA pin CLOCK_EN can be used to enable an RS485 driver on a PMC PIM module applicatio
36. e use to the public the best way to achieve this is to make it free software which everyone can redistribute and change under these terms To do so attach the following notices to the program It is safest to attach them to the start of each source file to most effectively convey the exclusion of warranty and each file should have at least the copyright line and a pointer to where the full notice is found lt one line to give the program s name and a brief idea of what it does gt Copyright C lt year gt lt name of author gt This program is free software you can redistribute it and or modify it under the terms of the GNU General Public License as published by the Free Software Foundation either version 2 of the License or at your option any later version This program is distributed in the hope that it will be useful but WITHOUT ANY WARRANTY without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE See the GNU General Public License for more details You should have received a copy of the GNU General Public License along with this program if not write to the Free Software Foundation Inc 51 Franklin Street Fifth Floor Boston MA 02110 1301 USA Also add information on how to contact you by electronic and paper mail If the program is interactive make it output a short notice like this when it starts in an interactive mode Gnomovision version 69 Copyright C year name of author
37. ence clock can optionally be synchronized through an IRIG B timecode signal and the frequency is controlled by an FPGA internal ADPLL The current reference clock frequency is calculated as Lon 66 6668 MHz DDFSINC 2 Base value with IRIG B sync regulator disabled is 0x00624e00 When the IRIG B sync regulator is active the DDFSINC register is updated every IRIG B bit time The DDFS unit is can be controlled through the DDFSCTRL register User Manual V 2027 21 Filename pmc440 me odt Revision 1 1 2008 07 14 All rights reserved Confidential Page Copyright esd gmbh 2008 37 of 49 PMC CPU 440 T 12 FPGA Status preliminary OG Bits Name Function dl A RESERVED Always read 0 2 RESTART 1 reference clock is stopped an regulator parameter are reset 0 reference clock is enabled When REGULATE flag is set the oscillator starts with the next IRIG B bit Default after FPGA reset is 0 1 REGULATE 1 reference clock is synchronized to IRIG B input source 0 reference clock is free running Default after FPGA reset is 0 0 STOP 1 reference clock is stopped and regulator parameter a left untouched 0 reference clock is enabled When REGULATE flag is set the oscillator starts with the next IRIG B bit Default after FPGA reset is 0 12 3 7 FIFO lt 0 3 gt _DATA 32 bit wide FIFO data port Data producers write to this register Consumers read from this re
38. ermination None Connectors PMC P4 1 2 7 Ethernet Interface Number 2 Standard IEEE 802 3 10 100 1000BaseT Bitrate 10 100 1000Mbit s Controller CPU internal Isolation transformer Connector RJ45 socket in frontpanel MAC address Port0 00 02 27 83 40 00 serial 1 2 Port1 00 02 27 83 40 00 serial 1 2 1 1 2 8 USB Interface Host or Device Number 1 Standard USB 2 0 Bitrate 480 Mbit s Controller CPU internal host OHCI EHCI alt device Role Host or device configurable via software Connector Mini AB in frontpanel 1 esd provides a suitable software driver for Linux or MS Windows PCs User Manual V 2027 21 Filename pmc440 me odt Revision 1 1 2008 07 14 All rights reserved Confidential Page Copyright esd gmbh 2008 9 of 49 PMC CPU 440 2 Installation Instructions Status preliminary OG 2 Installation Instructions e The PMC CPU 440 comes with a separate frontpanel sealing rubber band and four M2 5 x 5mm mounting screws Use only these M2 5 x 5 screws e Attention Do not use longer screws because they might damage the PMC CPU 440 mounting threads e The PMC CPU 440 may only be used on PMC sites with 3 3V PCI signalling Typically this is ensured by the correct IO voltage coding holes in the PMC module and pins on the carrier system 3 Frontpanel The PMC CPU 440 frontpanel provides access to the Ethernet interface
39. gister Only 32 bit access to this register is supported 12 3 8 FIFO lt 0 3 gt _CTRL FIFO control register Each register controls the behavior of a single FIFO Bits Name Access Function 15 IE R W Enable interrupts from this FIFO An interrupt is asserted when the FIFO contains at least one entry EMPTY 0 The interrupt is reset when all data is read from the FIFO Clearing the IE bit only masks the interrupt 11 14 RESERVED Always read 0 10 OVERFLOW R W This flag is set when a write access to a full FIFO occured which means that data got lost Writing a 0 resets the OVERFLOW flag EMPTY FIFO empty The FIFO does not contain any valid data FULL FIFO full The FIFO contains exactly 256 valid entries that are ready to be read LEVEL Filling level of FIFO O empty Each write access to the data port increases LEVEL while a read access decreases LEVEL LEVEL 0 means the FIFO is empty EMPTY 1 A full fifo is indicated by LEVEL 0x00 and the fifo full flag set to 1 This means bits 8 0 can be interpreted as the total fifo level from User Manual V 2027 21 Filename pmc440 me odt Revision 1 1 All rights reserved Confidential Page 2008 07 14 Copyright esd gmbh 2008 38 of 49 PMC CPU 440 g 12 FPGA Status preliminary SD Bits Name Access Function 0x000 to 0x100 12 4 FPGA Interrupts
40. gram by all those who receive copies directly or indirectly through you then the only way you could satisfy both it and this License would be to refrain entirely from distribution of the Program If any portion of this section is held invalid or unenforceable under any particular circumstance the balance of the section is intended to apply and the section as a whole is intended to apply in other circumstances It is not the purpose of this section to induce you to infringe any patents or other property right claims or to contest validity of any such claims this section has the sole purpose of protecting the integrity of the free software distribution system which is implemented by public license practices Many people have made generous contributions to the wide range of software distributed through that system in reliance on consistent application of that system it is up to the author donor to decide if he or she is willing to distribute software through any other system and a licensee cannot impose that choice This section is intended to make thoroughly clear what is believed to be a consequence of the rest of this License 8 If the distribution and or use of the Program is restricted in certain countries either by patents or by copyrighted interfaces the original copyright holder who places the Program under this License may add an explicit geographical distribution limitation excluding those countries so that distribution is permit
41. h 2008 26 of 49 PMC CPU 440 T 11 Bootloader Status preliminary OG e Command 2 run command The command string at the address pointed by the address parameter is executed as if it was entered at the bootloader prompt The command string must be terminated by a 0 See PClAccess Driver manual for more details about the Ioadpci command 11 5 6 fpga command The fpga command is used to boot the on board Xilinx Spartan 3E FPGA XC3S1200E gt tftp 100000 tftpboot pmc440 pmc440 fpga bit ENET Speed is 1000 Mbps FULL duplex connection EMACO Using ppc Ass eth0 device TELERO Genee 1020702190 oume he address 1755 Kor Filename tftpboot pmc440 pmc440 fpga bit Load address 0x100000 Loading Litti EEE EE EEE EE EH EH HEH HH HH done gt fpga loadb 0 100000 Bytes transferred 480225 753el hex design tilenen e smei4l cS mec part number 3s1200eft256 date 2007 11 20 Eime ae eA bytes in bitstream 480148 gt Step by step instructions to write an alternative bitstream into flash memory and load it into the FPGA after reset 1 Upload the bitstream into RAM e g at RAM address 0x100000 The easiest way is to load the images from a TFTP server gt tftp 100000 tftpboot pmc440 pmc440_fpga bit 2 Remove flash write protection gt PKOKSCE OLE EE EI E TE E TE 3 Erase the current flash content gt erase fff00000 EEE EET EE
42. he actual state of a corresponding signal on the PMCs P4 FPGA IO lt 31 gt FPGA IO lt 0 gt CSTM32_OR1 0x0030 Output register 1 each bit in this register controls the output level of a corresponding signal on the PMCs P4 FPGA IO lt 47 gt FPGA IO lt 32 gt In order to control the output state the pin must be enabled as output via the TCRO register see below Default 0x0000 0000 CSTM32_TCR1 0x0034 Tristate control register O each bit in this register controls the direction of a corresponding signal on the PMCs P4 FPGA lIO0 lt 47 gt FPGA IO lt 32 gt A set bit enables the signal as output Default 0x0000 0000 CSTM32_IR1 0x0038 Input register 0 each bit mirrows the actual state of a corresponding signal on the PMCs P4 FPGA IO lt 47 gt FPGA IO lt 32 gt User Manual V 2027 21 Filename pmc440 me odt Revision 1 1 All rights reserved Confidential Page 2008 07 14 Copyright esd gmbh 2008 44 of 49 PMC CPU 440 13 Ordering information Status preliminary OG 13 Ordering information Type Description Order no PMC CPU 440 PowerPC PrPMC module V 2027 02 PMC CPU 440 667 PowerPC PrPMC module V 2027 03 667 MHz version PMC CPU 440 ME Usermanual in english V 2027 21 PIM CPU 405 2xCAN PIM module with 2 CAN physical layers V 2025 02 PIM CPU 405 PBOX PIM module with 2 CAN physical layers V 2025 04 2xCAN and
43. lt 3 gt 3 3V IO 4 5 FPGA IO lt 4 gt 3 3V IO FPGA IO lt 5 gt 3 3V IO 6 7 27 FPGA IO lt 6 26 gt 3 3V IO FPGA IO lt 7 27 gt 3 3V IO 8 28 29 FPGA IO lt 28 gt 3 3V IO FPGA IO lt 29 gt 3 3V 10 30 31 FPGA IO lt 30 gt 3 3V IO FPGA IO lt 31 gt 3 3V IO 32 33 5V FPGA IO lt 32 gt PWR 5V CANO_TX FPGA IO lt 33 gt DM 34 35 n c FPGA IO lt 34 gt 3 3V IO CANO_RX FPGA IO lt 35 gt 15V 36 37 n c FPGA IO lt 36 gt 3 3V 10 CAN1_TX FPGA IO lt 37 gt DV O 38 39 n c FPGA IO lt 38 gt 3 3V IO CAN1_RX FPGA IO lt 39 gt 5V 1 40 41 n c FPGA IO lt 40 gt 3 3V IO GND FPGA IO lt 41 gt PWR GND 42 43 GND FPGA IO lt 42 gt PWR n c FPGA IO lt 43 gt 3 3V IO 44 GND 45 n c FPGA IO lt 44 gt 3 3V IO RxS1 RS232 46 47 RTSS1 RS232 O TxS1 RS232 O 48 49 CTSS1 RS232 n c FPGA IO lt 45 gt 3 3V IO 50 51 n c FPGA IO lt 46 gt 3 3V 10 GND FPGA IO lt 47 gt PWR GND 52 53 CLOCK_IN 5V CLOCK_OUT 3 3V O 54 55 RESET IN 5V RESET_OUT 3 3V O 56 57 IRIG B_R_IN 5V IRIG B_R_OUT 3 3V O 58 59 IRIG B_R_P RS485 CLOCK_EN 3 3V O 60 61 IRIG B_R_M RS485 RESET_EN 3 3V O 62 63 IIC1 SDA 3 3V IO IIC1 SCL 3 3V IO 64 Notes 1 Signal names and corresponding notes in braces are optional and only available in non standard configurations 2 The PMC440 NGCC variant uses the optional FPGA IO signals FPGA IO lt 32 47 gt 3 FPGA IO lt 33 35 37 39 gt hav
44. m does 1 You may copy and distribute verbatim copies of the Program s User Manual V 2027 21 Revision 1 1 All rights reserved Confidential Filename pmc440 me odt 2008 07 14 Copyright esd gmbh 2008 Page 46 of 49 PMC CPU 440 14 Appendix Status preliminary source code as you receive it in any medium provided that you conspicuously and appropriately publish on each copy an appropriate copyright notice and disclaimer of warranty keep intact all the notices that refer to this License and to the absence of any warranty and give any other recipients of the Program a copy of this License along with the Program You may charge a fee for the physical act of transferring a copy and you may at your option offer warranty protection in exchange for a fee 2 You may modify your copy or copies of the Program or any portion of it thus forming a work based on the Program and copy and distribute such modifications or work under the terms of Section 1 above provided that you also meet all of these conditions a You must cause the modified files to carry prominent notices stating that you changed the files and the date of any change b You must cause any work that you distribute or publish that in whole or in part contains or is derived from the Program or any part thereof to be licensed as a whole at no charge to all third parties under the terms of this License c If the modified program normally reads commands inte
45. n zo N ner ONE ala A cumo Ze tee ip in p else if stremp argv 1 wait gor Eike D ieam eaan JEE 2710 interrupt handler rem Eer FOGE F printer E Fire lewel cletee im 5 Primer n enable all fifo interrupts FPGA OUT32 amp fpga gt hostctrl HOSTCTRL FIFOIE GATE HOSTCTRL FIFOIE FLAG for 2 07 Zenn COUNT itt q enable interrupts from all fifos FPGA SETBITS SEpga gt ELEo 1 cri BUS 20 5al while 1 wait loop Rae leegen i Count i N one 3 pn A CLONE Zar Pe putc 0x08 backspace SUES Site lCoume2 SS 2117 Abort if ctrl c was pressed i alocice Serle 4 puts nAbort n break udelay 1000 if abort break simple fifo backend Lif erer TERiE uLice for i 0 i lt FIFO COUNT i cumo isi See A Gin P GjOrE_AETMEGalice Oe unmask global fifo irq FPGA OUT32 amp fpga gt hostctrl User Manual V 2027 21 Revision 1 1 All rights reserved Confidential Page Filename pmc440 me odt 2008 07 14 Copyright esd gmbh 2008 41 of 49 PMC CPU 440 T 12 FPGA Status preliminary SD BOSCO PILI E TEH G REER O AGE disable all fifo interrupts IGA DE eeleren IOC TEET O TECATE for 2 07 eenig COUNTE itt d IGN CRISIS EES Ee Een rer IIo IL 9 irg free nerder BEGA TAO i else printf Usage nfifo s
46. n cmdtp gt help return 1 break case 4 case 5 aif lettres aio Il rieet get fifo number or fifo address i simple tzo azew 2 NUL 16 5 data paramter cete simole steti Segre 2 Nuti 116 2 get optional count parameter n 1 iit eee S 5 4 a Gime Salmi STER Re axow 4 Mol 110 p ie GE lt IPO COUNTE peiner H H eer cl as GOK te Fire Sen me date Eie Eos 0p at aa Hf FPGA OUT32 amp fpga gt fifo f data data else printf writing d x 08x to fifo port at address 08x n in Cleneei SE Eon ei On ee ENEE lie ler erch else printf Usage nfifo s n cmdtp gt help return 1 break default printf Usage nfifo s n cmdtp gt help return 1 return 0 U_BOOT CMD LEO Dp aly Clo ito WNP aL ECO Fifo module operations n wait nfifo read n ice weits Ciro Carta TT a I TTT IT T m without arguments print all fifo s status n with wait argument interrupt driven read from all fifos n with read argument read current contents from all fifos n with write argument write data cnt times to fifo or address n DE User Manual V 2027 21 Revision 1 1 All rights reserved Confidential Page Filename pmc440 me odt 2008 07 14 Copyright esd gmbh 2008 42 of 49 PMC CPU 440 T 12 FPGA Status preliminary OG 12 6 FPGA Custom Module The FPGA custom module allows users to add customize
47. n specific RESET_IN IN 3 3V 5V tolerant general purpose input This signal is logically connected to a FPGA pin This pin can optionally be enabled to reset the FPGA internal timestamp counter RESET OUT OUT LVTTL general purpose output This signal is logically connected to a FPGA pin This pin can be used to generate a defined reset pulse to other CLOCK RESET sinks RESET_EN OUT LVTTL general purpose output This signal is logically connected to a FPGA pin RESET_EN can be used to enable an RS485 driver on a PMC PIM module application specific IRIG B_R_IN IN 3 3V 5V tolerant general purpose input This signal is logically connected to a FPGA pin This signal is used as IRIG B time signal input when a TTL time signal is provided This signal is logically connected to a FPGA pin IRIG B_R_OUT OUT LVTTL general purpose output This signal is reserved for future implementation of an IRIG B time code generator IRIG B_R_P diff O Half duplex RS485 differential IRIG B input output This signal pair IRIG B R M diff ue S used to supply the PMC440 with an external IRIG B time signal me source This signal pair can also be configured as an output that is controlled by FPGA internal functionality e g IRIG B timecode generation TX0 CO OUT TTL CANO transmit RX0 CO IN TTL CANO receive TX0 C1 OUT TTL CAN1 transmit RX0 C1 IN TTL CAN1 receive RxS1 IN RS232 receive data 2 port TxS1 OUT RS232 transmit data 2 port RTSS1
48. nsole is delayed by this value This is especially helpful when using the USB CON console on most PC operating systems the serial port device of the PMC CPU 440 will appear a short time after the device is powered on This means that a terminal program on the PC cannot open the port before the PMC CPU 440 module is powered on With a suitable bringup delay the user has enough time to open the serial port from the terminal program without losing any startup messages Example setup 533MHz cpu frequency U Boot console is available via USB CON connector 5s bringup delay gt sbe 533 0 5 Bootstrapping for 533MHz Writing boot EEPROM done dump via i2c md 52 0 1 14 gt Attention Do not use this command until you know what you are doing 11 5 4 fifo Control Hardware FIFO Module The fifo command is used to demonstrate and debug the FPGA internal hardware FIFOs The full functionality of the FIFO module is described in a separate chapter gt fifo fifo wait fifo read fifo write fifo 0 3 data cnt 1 fifo write address gt 4 data cnt 1 Waldlaatie argumentas Oriat all FLOS STewus with wait argument interrupt driven read from all fifos with read argument read current contents from all fifos with write argument write data cnt times to fifo or Tale Without any arguments the fifo command will output a short summary about the four FIFOs state gt fifo
49. otloader using the PMMO register set It can be changed during runtime by the operating system 0x1 d000 0000 0x1 d00f ffff EBC bank 2 PerCS2 NAND flash Oxl ef00 0000 Oxl ef0f ffff EBC bank 4 PerCS4 FPGA 32 bit bank size 1MB Oxl ef00 0000 0x1 ef00 00ff FPGA internal registers 32bit bank Oxl ef01 n000 Oxl ef01 nfff esd s CAN IP cores default 2 IP cores n 0 1 0x1 ef08 0000 Oxl ef0f ffff FPGA internal registers reserved for custom extensions Oxl ef10 0000 Oxl eflf ffff EBC bank 5 PerCS5 FPGA 16 bit bank size 1MB Oxl ef18 0000 Oxl eflf ffff FPGA internal registers 16 bit address space reserved for custom extensions Oxl ef60 0b00 Oxl ef60 0b1f GPIO controller 0 Oxl ef60 0c00 Oxl ef60 0c1f GPIO controller 1 EBC bank 0 PerCS0 4MB NOR flash Oxl ffc0O 0000 Oxl ffef ffff unused Oxl fff0 0000 Oxl fff7 ffff default FPGA bit file image 512KB Oxl fff8 0000 0x1 fff9 ffff reserved 128KB 0x1 fffa 0000 0x1 ffff ffff U Boot bootloader 384KB 3 EBC external bus controller User Manual V 2027 21 Filename pmc440 me odt Revision 1 1 All rights reserved Confidential Page 2008 07 14 Copyright esd gmbh 2008 19 of 49 PMC CPU 440 9 Interrupts Status preliminary OG 9 Interrupts 9 1 External Interrupt Assignment UIC IRQ Ext Interrupt Pin Device Configurations 1
50. ou have not signed it However nothing else grants you permission to modify or distribute the Program or its derivative works These actions are prohibited by law if you do not accept this License Therefore by modifying or distributing the Program or any work based on the Program you indicate your acceptance of this License to do so and all its terms and conditions for copying distributing or modifying the Program or works based on it 6 Each time you redistribute the Program or any work based on the Program the recipient automatically receives a license from the original licensor to copy distribute or modify the Program subject to these terms and conditions You may not impose any further restrictions on the recipients exercise of the rights granted herein You are not responsible for enforcing compliance by third parties to this License 7 If as a consequence of a court judgment or allegation of patent infringement or for any other reason not limited to patent issues conditions are imposed on you whether by court order agreement or otherwise that contradict the conditions of this License they do not excuse you from the conditions of this License If you cannot distribute so as to satisfy simultaneously your obligations under this License and any other pertinent obligations then as a consequence you may not distribute the Program at all For example if a patent license would not permit royalty free redistribution of the Pro
51. r work not based on the Program with the Program or with a work based on the Program on a volume of a storage or distribution medium does not bring the other work under the scope of this License 3 You may copy and distribute the Program or a work based on it under Section 2 in object code or executable form under the terms of Sections 1 and 2 above provided that you also do one of the following a Accompany it with the complete corresponding machine readable source code which must be distributed under the terms of Sections 1 and 2 above on a medium customarily used for software interchange or b Accompany it with a written offer valid for at least three years to give any third party for a charge no more than your cost of physically performing source distribution a complete machine readable copy of the corresponding source code to be distributed under the terms of Sections 1 and 2 above on a medium customarily used for software interchange or c Accompany it with the information you received as to the offer to distribute corresponding source code This alternative is allowed only for noncommercial distribution and only if you received the program in object code or executable form with such an offer in accord with Subsection b above The source code for a work means the preferred form of the work for making modifications to it For an executable work complete source code means all the source code for all modules it contains
52. ractively when run you must cause it when started running for such interactive use in the most ordinary way to print or display an announcement including an appropriate copyright notice and a notice that there is no warranty or else saying that you provide a warranty and that users may redistribute the program under these conditions and telling the user how to view a copy of this License Exception if the Program itself is interactive but does not normally print such an announcement your work based on the Program is not required to print an announcement These requirements apply to the modified work as a whole If identifiable sections of that work are not derived from the Program and can be reasonably considered independent and separate works in themselves then this License and its terms do not apply to those sections when you distribute them as separate works But when you distribute the same sections as part of a whole which is a work based on the Program the distribution of the whole must be on the terms of this License whose permissions for other licensees extend to the entire whole and thus to each and every part regardless of who wrote it Thus it is not the intent of this section to claim rights or contest your rights to work written entirely by you rather the intent is to exercise the right to control the distribution of derivative or collective works based on the Program In addition mere aggregation of anothe
53. ral Public Licenses are designed to make sure that you have the freedom to distribute copies of free software and charge for this service if you wish that you receive source code or can get it if you want it that you can change the software or use pieces of it in new free programs and that you know you can do these things To protect your rights we need to make restrictions that forbid anyone to deny you these rights or to ask you to surrender the rights These restrictions translate to certain responsibilities for you if you distribute copies of the software or if you modify it For example if you distribute copies of such a program whether gratis or for a fee you must give the recipients all the rights that you have You must make sure that they too receive or can get the source code And you must show them these terms so they know their rights We protect your rights with two steps 1 copyright the software and 2 offer you this license which gives you legal permission to copy distribute and or modify the software Also for each author s protection and ours we want to make certain that everyone understands that there is no warranty for this free software If the software is modified by someone else and passed on we want its recipients to know that what they have is not the original so that any problems introduced by others will not reflect on the original authors reputations Finally any free program is threatened con
54. re GE E e UL DEE 25 11 5 4 fifo Control Hardware FIFO Module 25 11 5 5 loadpci Start PCI firmware loading sees 26 K Reese e ennl EE 27 11 5 7 painit Command essen nn nsn an 28 let Eegeregie 28 11 5 9 resetout Commande 28 11 6 Special Environment Variables ccccceccecccecceceeceeceeeceseeaaeeaaanaaeaaecaaecaeceeeceeeeeeeeseeeeeeeeeeess 28 11 6 1 pcidelay Variable see ee 28 User Manual V 2027 21 Revision 1 1 All rights reserved Confidential Page Filename pmc440 me odt 2008 07 14 Copyright esd gmbh 2008 5 of 49 PMC CPU 440 T Status preliminary OG 11 6 2 ptmila ptmims ptm2la and ptm2ms Vartables nenn nennen 29 11 6 3 Pram Variable sense sank ee 29 12 e E 30 12 1 Functional Blocks nn nanasan rnaner ereen 30 12 2 PPGA EE 31 12 3 Register Deseriplon ee een sb 33 12341 CTRL Register OD ae 33 12 3 2 STATUS Register Ox0004 joo un ae 35 12 3 3 CTRLB Register II EE 35 12 3 4 TSCTRL Timestamp unit control register OsOO 19 sss eee 36 12 3 5 HOSTCTRL Host control register DXxD060 4 04 44000402444440000000nB HE een 36 12 3 6 DDFSCTRL DDFSINC Clock generator registers 0x0070 OsO0 4 2 gt 37 12 3 7 ElFOU 2 DA TR een ee een 38 12 385 FIFO lt 0 3 gt e E 38 12 4 FPGA Interrupts nn 39 12 5 Using the FIFO Ban E 39 12 6 FPGA Custom Module 43 12 6 1 Custom Module Conventions ees esse re 43 12 6 2 Sample Custom Module simple Io 43 E dee ln eege en DEE 45 14 Appen
55. rectly connected the PMC P4 IO connector 2 4 x CAN dar LEDs IP Module gt CAN TTL p FPGA VO USR2 USB max 48 USB console gt om FPGA gt Ricaa E Se SS gt Special l O RUN dk RS232 USB 2 0 a Fk f i N 12C SPI host device ETHO v ee UART d NOR NAND i Flash Flash BE 2 x Ethernet PPC440EPx 1000 Base T gt 533 667 MHz Pn1 PCI2 2 9 l I N Pn2 32bit I 33 66MHz Vv _ 4 l EEPROM Sc Fig 1 PMC CPU 440 Block Diagram 3 3V only User Manual V 2027 21 Revision 1 1 All rights reserved Confidential Page Filename pmc440 me odt 2008 07 14 Copyright esd gmbh 2008 70f49 PMC CPU 440 1 Overview Status preliminary 1 2 Technical Data 1 2 1 General Operating temperature 0 50 C Humidity max 90 non condensing Power supply 5V and 3 3V DC 5 Power consumption 6 W since hardware revision 1 2 main powerrail is 3 3V before main powerrail is 5 0V PCB formfactor 148mm x 74mm weight 140g including heatsink 1 2 2 CPU Core CPU PPC440EPx AMCC CPU clock 533MHz optional 667MHz RAM 256MB DDR2 RAM Flash memory NOR 4MB Spansion S29AL032D90TFI04 NAND flash 256 MB 2KB page size EEPROM a 4KB connected via I2C used for bootloader configuration b
56. reserved Default after reset 0 24 22 CLOCK_MODEI2 0 000 CLOCK_OUT signal is driven low 001 CLOCK OUT signal is driven high 010 100kHz 50 duty cycle clock with IRIG B sync option 111 CLOCK_OUT is connected to the FPGA s custom module Default after reset 000 User Manual V 2027 21 Filename pmc440 me odt Revision 1 1 All rights reserved Confidential Page 2008 07 14 Copyright esd gmbh 2008 33 of 49 PMC CPU 440 T 12 FPGA Status preliminary SD Bits Name Function 21 19 RESET_MODE 2 0 000 RESET OUT signal is driven low 001 RESET_OUT signal is driven high 010 RESET_OUT pulse is triggered by manual timestampcounter reset see timestamp unit 011 RESET OUT pulse is triggered by IRIG B receiver unit CF 100 esd internal test mode do not use 111 RESET_OUT is connected to the FPGA s custom module Default after reset 000 The automatically timed reset pulse has about 6 us pulse width 18 16 IRIGB_SRC 2 0 IRIG B input select for IRIG B module 000 IRIG_B_R_P M Pn4 diff input 001 IRIG_B_R_IN Pn4 TTL input 010 reserved 011 reserved xx reserved for future use Default after reset 000 15 14 IRIGB_R_OUT_MODEL configuration of IRIG B TTL output on Pn4 1 0 00 signal is driven low 01 signal is driven high 10 IRIG B output 11 signal is connected to the FPGA s custom modul
57. rvielf ltigung jeder Art auch auszugsweise sind nur mit schriftlicher Genehmigung durch esd gestattet The information in this document has been carefully checked and is believed to be entirely reliable esd makes no warranty of any kind with regard to the material in this document and assumes no responsibility for any errors that may appear in this document esd reserves the right to make changes without notice to this or any of its products to improve reliability performance or design esd assumes no responsibility for the use of any circuitry other than circuitry which is part of a product ofesd gmbh esd does not convey to the purchaser of the product described herein any license under the patent rights of esd gmbh nor the rights of others esd electronic system design gmbh Vahrenwalder Str 207 D 30165 Hannover GERMANY Tel 49 511 372 98 0 FAX 49 511 372 98 68 E Mail info esd eu www esd eu User Manual V 2027 21 Revision 1 1 All rights reserved Confidential Page Filename pmc440 me odt 2008 07 14 Copyright esd gmbh 2008 2 of 49 PMC CPU 440 Status preliminary OG Dokumenten Information document no V 2027 21 document type DOCO8xx document status preliminary document revision 1 1 date of creation 2008 07 14 document path I Prj esd PMC pmc440 Doku document filename pmc440 me odt number of pages annex 49 0 Responsible for con
58. s USB console CON and USB 2 0 host device port Five LEDs indicate several status information LED designator Color Function LED 0 green Ethernet port 0 link traffic indicator This LED is lit when the ethernet port has established a link Flickering of this LED indicates network dataflow LED 1 green Ethernet port 1 link traffic indicator This LED is lit when the ethernet port has established a link Flickering of this LED indicates network dataflow LEDA green User LED A This LED can be controlled by software When using the FPGA internal CAN IP cores this LED can be configured to indicate CAN data traffic LED B green User LED RB This LED can be controlled by software When using the FPGA internal CAN IP cores this LED can be configured to indicate CAN data traffic LEDR red green This LED will lit red after power on until the bootloader has finished hardware intialisation It can be turned on in green under software control User Manual V 2027 21 Filename pmc440 me odt Revision 1 1 All rights reserved Confidential Page 2008 07 14 Copyright esd gmbh 2008 10 of 49 PMC CPU 440 T 3 Frontpanel Status preliminary SD PMC CPU440 Ethernet Port 1 ETH LED 1 green Link Trafic ETH Port 1 1 CON BON LED B green CAN Traffic or User LED B 8 USB Console LED A green CAN Traffic or User LED A A LED R dual color
59. s reserved Confidential Page Filename pmc440 me odt 2008 07 14 Copyright esd gmbh 2008 14 of 49 PMC CPU 440 7 PMC Connectors Status preliminary OG 7 PMC Connectors The PMC CPU 440 module uses the PMC connectors P1 P2 and P4 P1 and P2 provide the PCI interface and power supply connection P4 has a complete module specific pinout 7 1 PMC P1 Connector User Manual V 2027 21 Filename pmc440 me odt Pin Signal Signal Pin 1 n c TCK 12V 2 3 GND INTA 4 5 INTB INTC 6 7 GND PRESENT 5V 8 9 INTD n c reserved 10 11 GND n c reserved 12 13 PCI CLK GND 14 15 GND GNT 16 17 REQ 5V 18 19 VIO AD 31 20 21 AD 28 AD 27 22 23 AD 25 GND 24 25 GND C BE3 26 27 AD 22 AD 21 28 29 AD 19 5V 30 31 VIO AD 17 32 33 FRAME GND 34 35 GND IRDY 36 37 DEVSEL 5V 38 39 GND n c LOCK 40 41 n c SDONE n c SBO 42 43 IPAR GND 44 45 VIO AD 15 46 47 AD 12 AD 11 48 49 AD 09 5V 50 51 GND C BEO 52 53 AD 06 AD 05 54 55 AD 04 GND 56 57 VIO AD 03 58 59 AD 02 AD 01 60 61 AD 00 5V 62 Revision 1 1 All rights reserved Confidential 2008 07 14 Copyright esd gmbh 2008 Page 15 of 49 PMC CPU 440 7 PMC Connectors Status preliminary SD
60. sd gmbh 2008 20 of 49 PMC CPU 440 10 PCI Configuration Status preliminary SD Monarch PrPMC Non Monarch 0x027f Subsystem Vendor ID 0x12fe esd gmbh Subsystem ID 0x0440 0x027f Subsystem Vendor ID 0x12fe esd gmbh Subsystem ID 0x0441 PCI base address register mapping PCI BAR1 default 64MB top of local SDRAM 0x0c00 0000 0x0fff ffff mapping can be modified through bootloader environment variables A minimum size of 4MB is recommended to allow firmware download to non monarch boards via PCI The local base can be reconfigured during runtime BAR1 configuration must not be changed when any esd drivers PciAccess backplane network driver are used PCI BAR2 size 16MB mapping of local address space 0x1 ef00 0000 0x1 efff ffff This means that the FPGA internal register e g IRIG B time start at the beginning of BAR2 offset Ox600b00 0x600c00 440 s GPIO controller used for remote self reset and adapter interrupt control functions offset 0Ox000000 FPGA internal registers IRIG B time FIFOs etc This can be used to access any FPGA internal function from the PCI bus BAR2 configuration must not be changed when any esd drivers PciAccess backplane network driver are used Please read the bootloader chapter of this manual to get detailed information on how to modify the PCI BARx configuration 11 Bootloader 11 1 License The PMC CPU 440 module uses
61. simple adapter from the contact strip connector to a 16 pin connector to connect to the port This 16 pin connector is used by a wide range of third party hardware debugger vendors Attention Be careful when plugging the contact strip connector into the drillings Do not plug it in to deep The pins must not come into contact with the module s heatsink Pin Number X5 Function Direction 1 TDO output TDI input TRST pulled down via input 1kOhm 4 Vref 3 3V via 33 Ohm _ output resistor TCK input 6 TMS input 2 The JTAG connector is oriented with pin 1 close to the center of the PCB The pin 1 drilling is marked by a tiny 1 on the PCB s solder side User Manual V 2027 21 Filename pmc440 me odt All rights reserved Confidential Page Copyright esd gmbh 2008 13 of 49 Revision 1 1 2008 07 14 PMC CPU 440 g 6 JTAG Debug Interface Status preliminary CSpD Pin Number X5 Function Direction 7 PPC440 HALT input 8 GND reference JTAG Connector 16 pole Post Connector ixample of an Adapter Uncasred Connectors to build adapter SMD pin coulact slip Fa Satz modified pm contact sirip order uo MIMS 108 55 T 5 435 2 54 mm post conmectar Le Fa Harting 16 pole straight order no OSTRST67524 Fig 5 self build JTAG adapter inserted into PMC module from botton side of PCB User Manual V 2027 21 Revision 1 1 All right
62. stantly by software patents We wish to avoid the danger that redistributors of a free program will individually obtain patent licenses in effect making the program proprietary To prevent this we have made it clear that any patent must be licensed for everyone s free use or not licensed at all The precise terms and conditions for copying distribution and modification follow GNU GENERAL PUBLIC LICENSE TERMS AND CONDITIONS FOR COPYING DISTRIBUTION AND MODIFICATION 0 This License applies to any program or other work which contains a notice placed by the copyright holder saying it may be distributed under the terms of this General Public License The Program below refers to any such program or work and a work based on the Program means either the Program or any derivative work under copyright law that is to say a work containing the Program or a portion of it either verbatim or with modifications and or translated into another language Hereinafter translation is included without limitation in the term modification Each licensee is addressed as you Activities other than copying distribution and modification are not covered by this License they are outside its scope The act of running the Program is not restricted and the output from the Program is covered only if its contents constitute a work based on the Program independent of having been made by running the Program Whether that is true depends on what the Progra
63. t communication parameters are 115200 baud 8N1 8 databits no parity 1 stopbit no hardware handshake After the next power on you will see the bootloader startup messages being output on the serial console When you see the message Press SPACE hit the space key to stop booting and to access the interactive bootloader console At the prompt you can use an extensive command set to do configuration debugging or testing tasks Enter help followed by hitting the RETURN key to get a full list of all supported commands DA enert 1 3 1 dam 21 2008 111341350 CPU AMCC PowerPC 440EPx Rev A at 533 334 MHz PLB 133 OPB 66 EBC 66 MHz No Security Kasumi support Bootstrap Option C Boot ROM Location EBC 16 bits Internal PCI arbiter disabled PCI async ext clock used 32 kB I Cache 32 kB D Cache Board esd GmbH PMC440 Rev 1 1 non monarch PCI 33 MHz TAE ready DOC L is 33 G Dres 2 ae A DRAM 256 MB FLASH 4 MB AND 256 MiB a serial out serial mare 8 serial USB esis SE ppc 4xx eth0 ppc 4xx ethl POST cache PASSED POST i2c PASSED POST cpu PASSED POST fpu PASSED POST ethernet PASSED POST spr PASSED PARAM 0f c00000 Press SPACE to abort autoboot in 3 seconds gt 11 3 Default Bootloader Environment U Boot uses so called environment variables to store any configuration The full set of variables can be printed to the console by executing the printen
64. ted only in or among countries not thus excluded In such case this License incorporates the limitation as if written in the body of this License 9 The Free Software Foundation may publish revised and or new versions of the General Public License from time to time Such new versions will be similar in spirit to the present version but may differ in detail to address new problems or concerns Each version is given a distinguishing version number If the Program specifies a version number of this License which applies to it and any later version you have the option of following the terms and conditions either of that version or of any later version published by the Free Software Foundation If the Program does not specify a version number of this License you may choose any version ever published by the Free Software Foundation 10 If you wish to incorporate parts of the Program into other free programs whose distribution conditions are different write to the author to ask for permission For software which is copyrighted by the Free Software Foundation write to the Free Software Foundation we sometimes make exceptions for this Our decision will be guided by the two goals of preserving the free status of all derivatives of our free software and of promoting the sharing and reuse of software generally NO WARRANTY User Manual V 2027 21 Revision 1 1 All rights reserved Confidential Filename pmc440 me odt 2008 07 14 Copyright
65. tent author Name Company Phone Email Department M Fuchs esd gmbh SD 49 511 37298 0 support esd electronics com Distribution Review Name Firma Abteilung Telefon Email User Manual V 2027 21 Revision 1 1 All rights reserved Confidential Page Filename pmc440 me odt 2008 07 14 Copyright esd gmbh 2008 30f49 PMC CPU 440 Status preliminary OG Modification history Technical modifications in this overview are marked by an additional The following overview is handled from revision 1 0 Revision Chapter Page Changelog Date Sign 0 9 all al Document created 2008 03 18 MF 1 0 all all Initial release 2008 03 28 MF 11 5 3 25 Added ebe command describtion 2008 04 01 MF 9 2 20 Added chapter 2008 04 09 MF 11 5 5 26 Chapter rewritten 14 46 Added Appendix GPL License 2008 05 09 MF ke 31 Chapters added 2008 07 04 MF User Manual V 2027 21 Revision 1 1 All rights reserved Confidential Page Filename pmc440 me odt 2008 07 14 Copyright esd gmbh 2008 4 of 49 PMC CPU 440 Status preliminary Contents RE ee EE 7 1 1 Description Of The PMC CPU 440 Module 7 1 2 Technical Data sense nee 8 1 2 1 e IT 8 12 2 CRU EE nee Eege ege beer 8 1 2 3 Realtime Clock te E 8 R E e te le 8 1 2 5 Serial Interfaces a een E ERRET 9 1 2 6 CAN Interfaces esse eee eee 9 1 2 7 Ethernet
66. that suits to your board The bootloader update process is very delicate Any mistake may result in a board that is not usable anymore and which must be shipped back to be reprogrammed by esd using a JTAG debugger Here are step by step instructions for bootloader update at the serial console The tftp command requires a correct U Boot network configuration That means the the bootloader environment variables ipaddr netmask gatewayip and serverip must be setup according to you network When any of the following step fail do not proceed 1 Upload the new bootloader binary image into RAM e g at RAM address 0x100000 The easiest way is to load the images from a TFTP server gt tftp 100000 tftpboot pmc440 u boot bin 2 Remove flash write protection SS PROESCIE OIE IEA 121E 3 Erase the current bootloader Attention do not switch of the board from now on until a new bootloader has been written into the flash gt erase fffa0000 ffffffff 4 Copy the new bootloader into flash gt cp b 100000 fffa0000 60000 This command copies 0x60000 bytes starting at RAM location 0x100000 into flash memory starting at Oxfffa0000 5 Enable flash write protection for bootloader address range gt protect on fffa0000 ffLELLE 6 When all the above commands succeeded reset the board gt reset To simplify the bootloader update process two environment variables already contain the necess
67. the opensource bootloader Das U Boot The U Boot sourcecode is published in terms of the GNU public license GPL Please see the appendix of this document for the full license text You can contact esd for a copy of the full bootloader sourcecode for the PMC CPU 440 Esd electronics will take every effort to upload all PMC CPU 440 board specific changes on the U Boot sourcecode back to the official repository The U Boot project homepage is at http www denx de wiki UBoot 11 2 Configuration and Console Access Use an USB cable with mini B connector PMC440 side and type A connector PC side to connect the PMC CPU 440 to a PCs USB port The U Boot console is accessable via the frontpanel s USB All rights reserved Confidential Page Copyright esd gmbh 2008 21 of 49 User Manual V 2027 21 Revision 1 1 Filename pmc440 me odt 2008 07 14 PMC CPU 440 T 11 Bootloader Status preliminary OG CON device port mini B socket After the first power on of the PMC module you will be prompted for a driver You should have received a suitable driver from esd for MS Windows operating systems Windows 2000 and above Most Linux distributions bring their own driver for the used on board FTDI USB serial converter When driver installation has been down you have a new virtual serial port COMx on Windows and typically dev ttyUSBx on Linux Now open a terminal program and point to the virtual COM port of the PMC CPU 440 The defaul
68. tups the loadpci command is appended to the bootcmd variable gt printenv bootcmd bootcmd run vxworksargs loadpci This is how loadpci works 1 The command cleared the first 0x20 bytes beginning at the target s local PCI BAR1 base address PTM1LA 2 Oxffffffff is written at PTM1LA 3 The loadpci command start to check the data at PTM1LA until it differs from Oxffffffff or CTRL C is pressed This check is done every millisecond During this polling state you will see the rolling bar in the bootloader console 4 When the content at PTM1LA changes the lower 12 bits are taken as a command token while the complete value with masked lower 12 bits is added to PTM1LA address and finally taken as address argument for further processing so the address parameter is always 4k aligned For PMC405 boards PTM1LA is typically 0x00000000 For PMC440 boards PTM1LA is typically 0x0c000000 192MB 5 The 12 bit command token decides what U Boot does next and how the address parameter is used Unsupported commands lead to termination of the loadpci command with no action e Command 0 bootm The U Boot loadaddr variable is set to the address parameter value Then the bootm command is issued e Command 1 autoscr The autoscr command is executed with the address parameter passed as script address User Manual V 2027 21 Revision 1 1 All rights reserved Confidential Page Filename pmc440 me odt 2008 07 14 Copyright esd gmb
69. v command Variables can be modified through the setenv lt name gt lt value gt command and finally modifications can be stored in a non volatile memory through saveenv This is the factory default environment setup for the PMC CPU 440 only the most important variables are printed here gt printenv baudrate 115200 ocd Eeeh update protect off FFFA0000 FFFFFFFF era FFFA0000 FFFFFFFF cp b 200000 FFFA0000 60000 serial PMC440 GA0013 hostname pmc440 GA0013 ethaddr 00 02 27 83 40 18 ethladdr 00 02 27 83 40 19 bd_type pmc4 40 bootdelay 3 User Manual V 2027 21 Revision 1 1 All rights reserved Confidential Page Filename pmc440 me odt 2008 07 14 Copyright esd gmbh 2008 22 of 49 PMC CPU 440 T 11 Bootloader Status preliminary OG preboot painit pram 4096 load tftp 200000 tftpboot pmc440 u boot bin ethrotate no ethact ppc_4xx eth0 fpga tftp 100000 tftpboot pmc440 pmc440 fpga bit fpga loadb 0 100000 bootcmd run fpga mem 258048k eler 1 9 1 vain 2i 2008 att Sur gatewayip 10 0 0 79 netmask 255 255 0 0 ipaddr 10 0 18 113 serverip 10 0 0 190 gt Environment size 1507 4092 bytes 11 4 Flash Update The bootloader resides at the top of the PMC440 onboard NOR flash memory Assuming a binary size of 384kByte 0x60000 the bootloader image must be programmed into the flash memory starting at Oxfffa0000 Please check that you are using the correct bootloader image

PMC-CPU/440 - esd electronics, Inc.

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