Home

LC870G00 SERIES USER`S MANUAL

1. Note 1 TIL serves as an event counter when INT4 is specified as the timer 1 count clock input in the external interrupt 4 5 pin select register I45SL It serves as a timer that runs using 2Tcyc as its count clock if INT4 is not specified as the timer count clock input Note 2 TIL will not run normally if INT4 is specified as the timer count clock input when TIPWM 1 When TI PWM 1 do not specify INT4 as the timer 1 count clock input 3 Prescaler count Determined by the TIPRR value The count clock for T1L is generated at the intervals determined by the prescaler count TILPRE TILPRC2 TILPRC1 TILPRCO TIL Prescaler Count 0 1 1 0 0 0 2 1 0 0 1 4 1 0 1 0 8 1 0 1 1 16 1 1 0 0 32 1 1 0 1 64 1 1 1 0 128 1 1 1 1 256 4 Reset When the timer stops operation or a TIL reset signal is generated 3 34 LC870G00 Chapter 3 3 5 3 4 Timer 1 prescaler high byte 8 bit counter 1 Start stop The start stop of timer 1 prescaler high byte is controlled by the 0 1 value of TIHRUN timer 1 control register bit 7 2 Count clock Varies with the operating mode Mode T1LONG TIPWM T1H Prescaler Count Clock 0 0 0 2 Tcyc 1 0 1 1 Tcyc 2 1 0 TIL match signal 3 1 1 256 x TILPRC count x Tcyc 3 Prescaler count Determined by the TIPRR value The count clock for TIH is generated at the i
2. Reserved for system R63 7EH L L R1 02H RO 00H Fig 2 10 1 Allocation of Indirect Registers Addressing Modes The LC870000 series microcontrollers support the following seven addressing modes lt l gt Immediate immediate data refers to data whose value has been established at program preparation assembly time lt 2 gt lt 3 gt lt 4 gt lt 5 gt lt 6 gt lt 7 gt Indirect register Rn indirect 0 8 nS 63 Indirect register Rn Indirect register RO Direct ROM table look up External data memory access C register indirect 0 lt nS 63 Offset value indirect The rest of this section describes these addressing modes 2 11 1 Immediate Addressing The immediate addressing mode allows 8 bite 1 byte or 16 bit 1 word immediate data to be handled Examples are given below Examples LD LI LDW PUSH ADD BE 12H 1234H 34H 56H 78H LI Loads the accumulator with byte data 12H Loads the BA register pair with word data 1234H Loads the stack with byte data 34H Adds byte data 56H to the accumulator Compares byte data 78H with the accumulator for a branch 2 6 LC870G00 Chapter 2 2 11 2 Indirect Register Indirect Addressing Rn In the indirect register indirect addressing mode it is possible to select one of the indirect registers RO to R63 and use its contents to designate an address in RAM or SFR When the selected regist
3. This bit is read only No instruction can rewrite the value of this bit directly Bits 3 2 These bits do not exist They are always read as 1 XCNT1 bit 1 0000BH Interrupt level control flag e A 1 in this bit sets all interrupts to vector address 0000BH to the L level e AO in this bit sets all interrupts to vector address 0000BH to the X level XCNTO bit 0 00003H Interrupt level control flag e A 1 in this bit sets all interrupts to vector address 00003H to the L level e AO in this bit sets all interrupts to vector address 00003H to the X level 4 3 Interrupt 4 1 4 2 Interrupt priority control register IP 1 The interrupt priority control register is an 8 bit register that selects the interrupt level H L of interrupts to vector addresses 00013H to 0004BH Address Initial value R W Name BIT7 BIT6 BIT5 BIT4 BITS BIT2 BIT1 BITO FE09 0000 0000 R W IP IP4B IP43 IP3B IP33 IP2B IP23 IPIB IP13 Interrupt Vector Address 0004BH L EI 00043H IP43 0003BH IP3B Interrupt Level Be 00033H IP33 0002BH IP2B 00023H IP23 0001BH IP1B B 00013H IP13 4 4 LC870G00 Chapter 4 4 2 System Clock Generator Function 4 2 1 Overview This series of microcontrollers incorporates five systems of oscillator circuits i e the main clock oscillator subclock oscillator low medium and high speed RC oscillators as system clock generator circuits The low medium and high speed R
4. INTOIE bit 0 INTO interrupt request enable When this bit and INTOIF are set to 1 a HOLD mode release signal and an interrupt request to vector address 0003H are generated 3 2 3 7 External interrupt 2 3 control register 123CR 1 The external interrupt 2 3 control register is an 8 bit register for controlling external interrupts 2 and 3 Address Initial value R W Name Br Bite Bits era ers Br2 sm erro FESE 0000 0000 R W I23CR INT3HEG INT3LEG INT3IF INT3IE INT2HEG INT2LEG INT2IF INT2IE INT3HEG bit 7 INT3 rising edge detection control INT3LEG bit 6 INT3 falling edge detection control INT3HEG INT3LEG INT3 Interrupt Conditions P15 Pin Data No edge detected Falling edge detected 0 0 gt ai rispa O i O INT3IF bit 5 INT3 interrupt source flag This bit is set when the conditions specified by INT3HEG and INT3LEG are satisfied When this bit and the INT3 interrupt request enable bit INT3IE are set to 1 an interrupt request to vector address 001BH are generated This bit must be cleared with an instruction as it is not cleared automatically INT3IE bit 4 INT3 interrupt request enable When this bit and INT3IF are set to 1 an interrupt request to vector address 001BH is generated INT2HEG bit 3 INT2 rising edge detection control INT2LEG bit 2 INT2 falling edge detection control INT2HEG INT2LEG INT2 Interrupt Conditions P16 Pin Data No edge detected
5. Notes on this addressing mode gt The internal data memory space is divided into three closed functional areas as explained in Section 2 1 namely 1 system reserved area FFOOH to FFFFH 2 SFR area FEOOH to FEFFH and 3 RAM stack area 0000H to FDFFH Consequently it is disallowed to point to a different area using the value of the C register from the basic area designated by the contents of Rn For example if the instruction LD R5 C is executed when RS contains OFDFFH and the C register contains 1 since the basic area is 3 RAM stack area 0000H to FDFFH the intended address OFDFFH 1 OFEOOH lies outside the basic area and OFFH is consequently placed in the ACC If the instruction LD R5 C is executed when RS contains FEFFH and the C register contains 2 since the basic area is 2 SFR area FEOOH to FEFFH the intended address OFEFFH 2 OFFO1H lies outside the basic area In this case since SFR is confined in an 8 bit address space the part of the address data addressing outside the 8 bit address space is ignored and the contents of OFEO1H B register are placed in the ACC as the result of the computation OFFO1H amp 0FFH OFE00H OFEO1 2 7 2 11 4 Indirect Register RO Offset Value indirect Addressing off In this addressing mode the results of adding the 7 bit signed offset data off 64 to 63 to the contents of the indirect register RO designate an address in RAM or SFR If RO contains
6. 3 8 5 3 8 5 1 2 3 4 5 6 ADC Conversion Example 12 bit AD conversion mode Setting up the 12 bit AD conversion mode Set the ADMD3 bit bit 6 of the AD mode register ADMRC to 0 Setting up the conversion time To set the conversion time to 1 32 set the AD conversion results low byte register ADRLC bit 0 ADTM2 to 1 and the AD mode register ADMRC bit 1 ADTM1 to 0 and bit 0 ADTMO to 1 Setting up the input channel When using AD channel input ANS set AD control register ADCRC bit 7 ADCHSEL3 to 0 bit 6 ADCHSEL2 to 1 bit 5 ADCHSEL1 to 0 and bit 4 ADCHSELO to 1 Starting AD conversion Set bit 2 ADSTART of the AD control register ADCRC to 1 The conversion time is doubled after a system reset and when the AD conversion is carried out for the first time after the AD conversion mode is switched from 8 bit to 12 bit AD conversion mode The conversion time determined by the formula is taken in the second and subsequent conversions Testing the end of AD conversion flag Monitor bit 1 ADENDF of the AD control register ADCRC until it is set to 1 Clear the end of conversion flag ADENDF to 0 after confirming that the ADENDF flag bit 1 is set to 1 Reading in the AD conversion results Read the AD conversion results high byte register ADRHC and AD conversion results low byte register ADRLC Since the conversion results data contains some errors quantization error c
7. 4 15 Standby 4 3 3 Related Registers 4 3 81 Power Control Register PCON 3 bit register 1 The power control register is a 3 bit register that specifies the operating mode normal HALT HOLD X tal HOLD Address Initial value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE07 HHHH H000 R W PCON XTIDLE PDN IDLE See 4 2 4 1 Power control register PCON 4 16 LC870G00 Chapter 4 Table 4 3 1 Standby Mode Operations Item mode Reset State HALT Mode HOLD Mode X tal HOLD Mode Entry conditions e RES applied PCON register PCON register e PCON register e Reset by POR LVD Bit 1 0 Bit 2 0 Bit 2 1 BitO 1 Bit 1 1 Bit121 e Reset from watchdog timer Data changed on entry e Initialized as shown in e WDTCNT bit 5 is e WDTCNT register bit 5 e WDTCNT register bit 5 separate table cleared if WDTCNT is cleared if WDTCNT is cleared if WDTCNT When watchdog timer register bit 4 0 and bit register bit 420 and bit register bit 420 and bit reset WDTCNT 3 1 3 1 3 1 register bit 7 is set e PCON register bit Ois e PCON register bit 0 is set set e OCR 3 register bit 6 is cleared e OCR register bits 5 4 and 1 are cleared if OCR3 register bit 1 0 e OCR3 register bit O is set and OCR register bits 5 and 4 are cleared if OCR3 register bit 1 1 Main clock oscillation e Stopped e State established at entry e Stopped e Stopped time Subclock oscillatio
8. BTPRRT BTPRRA STOHCP 3 45 BT 3 6 3 3 6 3 1 1 2 3 6 3 2 2 3 6 3 3 2 3 6 3 4 1 Circuit Configuration 8 bit programmable prescaler This prescaler is an 8 bit programmable prescaler that uses the signal selected by the input signal select register ISL as its clock source A match signal is generated when a match occurs between its output value and the value of the programmable prescaler match register BTPRR This match signal serves as the clock input to the binary up counter in the following stage This counter is reset under the conditions BTON BTCR bit 6 is set to 0 stop base timer operation a match signal is generated data is loaded into the BTPRR and the microcontroller is in HOLD mode 8 bit binary up counter This counter is an 8 bit binary up counter that uses as its clock source the match signal from the programmable prescaler Its output is used as the buzzer output signal or used to set the base timer interrupt 1 flag The overflow output of this counter serves as the clock input to the 6 bit binary up counter This counter is reset under the conditions BTON BTCR bit 6 is set to 0 stop base timer operation data is loaded into the BTPRR and the microcontroller is in HOLD mode 6 bit binary up counter This counter is a 6 bit binary up counter that uses as its clock source the match signal from the programmable prescaler or overflow output from the 8 bit binary up counter
9. L L a PUSHW PICREGHS Pl lt bitl when PSW is REG8 RAMS P1 lt RAM8 popped REGH8 lt RAMHB8 REGL8 lt RAML8 Pl lt RAMHS P1 bitl when higher order address of PSW is popped BITS ignored D DW ST STW MOV Popp EA NU POP BA P1 lt RAMH8 XCH REG8COPI Same as left I XCHW REGH8 lt P1 REGL8 lt Pl P1 lt REGH8 Same as left INC 9 bits P1 REGS after computation INCW INC 17 bits REGLS lt lower byte of CY P1 lt REGH8 after computation INC 9 bits INC 17 bits C NC DE DEC 9 bits B DEC 9 bits P1 lt REG8 after computation DECW DEC 17 bits REGL8 lt lower byte of CY P1 lt REGH8 after inverted computation DBNZ DEC 9 bits P1 lt REG8 D DEC 9 bits P1 lt REG8 SETI DEC 17 bits DEC 9 bits check lower order 8 bits DEC 9 bits check lower order 8 bits C Z CLRI BPC PN MUL24 RAM8 lt 1 Bit 8 of RAM address DIV24 for storing results is set to 1 GEES Note A 1 is read if the processing target is an 8 bit register no bit 8 Legends REGS Bit 8 of a RAM or SFR location REGHS REGLS Bit of the higher order byte of a RAM location or SFR bit 8 of the lower order byte RAMS Bit 6 of a RAM location RAMHS8 RAMLS Bit 8 of the higher order byte of a RAM location bit 8 of the lower order byte 2 11 2 12 3 3 1 LC870G00 Chapter 3 Peripheral System Configuration This chapter describes the built in functional blocks peripheral system of this series of micr
10. RUE A E l1 1 d d 1 1 1 The division ratios of S A and are allowed 1 2 4 8 16 32 64 128 4 7 FRCSEL I Main clock CF Main clock oscillator circuit ECFOSC High speed clock High speed FRCSTART RC oscillator circuit SRCSEL CLKCB5 4 CLKSGL CLKDV2 0 Medium speed RCSTOP RC oscillator eee 1 2 SRCSTART RC oscillator circuit Oscillation control To watchdog timer from watchdog timer and base timer fSCLK System clock frequency Subclock Subclock fCYC Cycle clock frequency EXTOSC X tal oscillator minimum instruction cycle circuit To base timer fCYC fSCLK 3 Figure 4 2 1 System Clock Generator Block Diagram 4 8 System Clock System clock SCLK LC870G00 Chapter 4 4 2 4 Related Registers 4 2 4 1 Power Control Register PCON 3 bit register 1 The power control register is a 3 bit register used to specify the operating mode normal HALT HOLD X tal HOLD See 4 3 Standby Function for the procedures to enter and exit the microcontroller operating modes Address Initial value R W Name BIT7 BIT6 BITS BIT4 BIT3 BIT2 BIT1 BITO FE07 HHHH H000 R W PCON XTIDLE PDN IDLE bits 7to3 These bits do not exist They are always read as 1 XTIDLE bit 2 X tal HOLD mode setting flag PDN bit 1 HOLD mode setting flag XTIDLE PDN Operating mode Normal or HALT mode HOLD mode 0 EE cr X tal HOLD mode 1 These bits must be set with
11. When P13 is placed in the output mode P13DDR 1 and P13FCR is set to 1 the value of port data latch is placed at pin P13 P12FCR bit 2 P12 function control SIO1 clock output control This bit controls the output data at pin P12 When P12 is placed in the output mode P12DDR 1 and P12FCR is set to 1 the OR of the SIO1 clock output data and the port data latch is placed at pin P12 P11FCR bit 1 P11 function control SIO1 data output control This bit controls the output data at pin P11 3 9 PORTS When P11 is placed in the output mode PI 1IDDR 1 and P11FCR is set to 1 the OR of the SIO1 output data and the port data latch is placed at pin P11 When the SIO1 is active SIO1 input data is read from P11 regardless of the I O state of P11 P10FCR bit 0 P10 function control SIOO data output control This bit controls the output data at pin P10 When P10 is placed in the output mode PIODDR 1 and P10FCR is set to 1 the OR of the SIO1 output data and the port data latch is placed at pin P10 LC870G00 Chapter 3 3 2 8 4 External interrupt 4 5 control register 145CR 1 Theexternal interrupt 4 5 control register is an 8 bit register for controlling external interrupts 4 and 5 Address Initial value R W Name BIT7 BIT6 BITS BIT4 BIT3 BIT2 BIT1 BITO FE4A 0000 0000 R W I45CR INTSHEG INTSLEG INTSIF INTSIE INT4HEG INT4LEG INT4IF INTHE INT5HEG bit 7 to INTSIE bit 4 Must always be set
12. of multiplex interrupt control Any interrupt requests of the level equal to or lower than the current interrupt are not accepted 2 When interrupt requests to two or more vector addresses occur at the same time the interrupt of the highest level takes precedence over the other interrupts For interrupts of the same level the interrupt into the smallest vector address is given priority No Vector Address Level Interrupt Source 1 00003H XorL INTO 2 0000BH XorL INT1 3 00013H HorL INT2 TOL INT4 4 0001BH HorL INT3 BT 5 00023H HorL TOH 6 0002BH HorL TIL T1H 7 00033H HorL HPWM2 8 0003BH HorL SIO1 9 00043H HorL ADC 10 0004BH HorL PO VCPWM e Priority levels X gt H gt L e Of interrupts of the same level the one with the smallest vector address takes precedence m Subroutine Stack Levels Up to 128levels the stack is allocated in RAM Ml High speed Multiplication Division Instructions e 16 bits x 8 bits 5 tCYC execution time e 24 bits x 16 bits 12 tCYC execution time e 16 bits 8 bits 8 tCYC execution time e 24 bits 16 bits 12 tCYC execution time E Oscillation Circuits e nternal oscillation circuits 1 Low speed RC oscillation circuit For system clock approx 30kHz 2 Medium speed RC oscillation circuit For system clock 1MHz 3 Hi speed RC oscillation circuit For system clock 83MHz 4 Hi speed RC oscillation circuit2 For High speed PWM 40MHz E System
13. 2 Duet 100 0012 ww PIR PUR PCR PISER nam PIC POOR PRIOR pas mee 0100 0000 ww PER PUFG PR PISFCR PR PISFCR Fe PLIFCR pen Crear wore ww prs o me t f 1 8o mee roo 0000 NW Cacces imibted FO AO AO AM m AO FEG Ho0 0000 RW CAces inhibited Foo 56 mo 50 mo ag ma 0000 0000 ww TR O INSHEG TNIIEG INSI INISIE TNZFEG TNIALEG TNIAIF NME 0000 0000 yw 593 1582 i581 1550 1433 1482 1981 1480 AAA EST NE DRE EMI RETIRER RT IT EES MI T re fT IEA ISO p pq p p p EIERE EE DE DEES DE DEE Py r reo pg o NES PEO pq p gp E E ME EE EC CE BN PO E a eh as A E PEE ueterum cp xe ME EE En FE 90900 WW ASOC ix tzocwtro IL AXH amp EG LD ADOSELI ADCHSELO waere sel or FES 0000 0000 NW AMC im tz ome AMD AMB AMP AMI AMD AMO AXM AO FEM 00000000 RW ARC imbtzocmesereutl DATALS BA DALI VAG ARG AR ARI ANNO FE 00000000 RW ARE ibt aD comersionresut H DNA DNA6 DATAS DATA DAS DX DWTAL DSAO rc HD HO AW P7 mtroum omm rr LE Feb oxo0xo NW A E INILV TNIIF INHIE TNOEH TNRLV OF TOE AI 3 Address Initial Value R W LG870 0 Remarks B T8 BT7 B T6 Bi T5 B TA B T3 B T2 BTI B TO FE5E 000
14. Enable Use Disable Disuse 2 LVD Reset Level Option 3 POR Release Level Option Typical Value of Min Operating Selected Option VDD Value Selected Option VDD Value E L to L91V 201v 231v 251v 2 81V EN 4 28V The minimum operating VDD value specifies the approximate lower limit value of the VDD value beyond which the selected POR release level or LVD reset level can be effected without generating a reset 1 LVD reset function option When Enable is selected a reset is generated at the voltage that is selected by the LVD reset level option Note 1 In this configuration operating current of several uA always flows in all modes No LVD reset is generated when Disable is selected Note 2 In this configuration no operating current will flow in all modes See the sample operating waveforms of the reset circuit shown in Subsection 4 6 5 for details 2 LVD reset level option The LVD reset level can be selected from 7 level values only when the LVD reset function is enabled Select the optimal detection level based on the actual operating conditions 3 POR release level option The POR release level can be selected only when the LVD reset function is disabled When not using the internal reset circuit set the POR release level to the lowest level 1 67V that will not affect the minimum guaranteed operating voltage Note 3 No operating current flows when the POR reset state is relea
15. Frequency tunable 12 bit PWM x2ch il High speed PWM HPWM2 8 10 bits PWM x1ch 1 The PWM clock is selectable from system clock and Hi speed RC2 40MHz 2 The PWM type is selectable from 8 bits Normal mode and 10 bits additive puls mode i Temperature sensor Senseor voltage can be comapred by the AD converter E On chip Debugger Function e Supports software debugging with the IC mounted on the target board e Provides 1 channel of on chip debugger pin OWPO li Data Security Function e Protects the program data stored in flash memory from unauthorized read or copy Note This data security function does not necessarily provide absolute data security LC870G00 Chapter 1 m Package Form e SSOP24 225mil Lead free and halogen free type MH Development Tools e On chip debugger TCB87 Type C 1 wire interface cable LC87F0G08A m Programming Board Package Programming board SSOP24 225mil W87F0GQ 1 5 1 3 Pin Assignment P7O INTO TOLCP ANO9 C 1 24 3 OWPO RES 2 23 3 POS T1PWMH vssi C3 22 3 PO5 T1PWML CKO cFi XT1 Ha LC87F0G08A 24 7 Pod ANANCPWMI CF2 XT2 C5 20 4 POS ANS VCPWMO vpp C6 19 Po2 AN2 CPIM P10 SO C417 18 C PO1 APIP P11 SH SB1 C18 17 L POO APIM P12 SCK1 Ca 16 4 VREF P13 INT4 T1IN AN7 C 10 15 3 VSS2 PAA INTA TAIN ANG 11 14 EA P17 BUZ INT1 TOHCP HPWM2 P15 INT3 TOIN ANS 12 13 4 P16 INT2 TOIN CPOUT HPWM2 SS
16. Synchronous 8 bit SIO UART 1 stop bit no parity SIT RUN bit 5 SIO1 operation flag 1 A 1 in this bit indicates that SIO1 is running 2 See Table 3 10 1 for the conditions for setting and clearing this bit SI1REC bit 4 SIO1 receive send control 1 Setting this bit to 1 places SIOI into the receive mode 2 Setting this bit to O places SIOI into the send mode SI DIR bit 3 MSB LSB first select 1 Setting this bit to 1 places SIOI into the MSB first mode 2 Setting this bit to 0 places SIOI into the LSB first mode SI OVR bit 2 SIO1 overrun flag 1 In mode 0 1 3 this bit is set when a falling edge of the input clock is detected with SILRUN 0 2 This bit is set if the conditions for setting SITEND are established when SIIEND 1 3 In modes 3 this bit is set when the start condition is detected 4 This bit must be cleared with an instruction SIT END bit 1 End of serial transmission flag 1 This bit is set when serial transmission terminates see Table 3 10 1 2 This bit must be cleared with an instruction SI1IE bit 0 SIO1 interrupt request enable control When this bit and SILEND are set to 1 an interrupt request to vector address 003BH is generated 3 60 LC870G00 Chapter 3 3 7 5 2 Serial buffer 1 SBUF1 1 Serial buffer 1 is a 9 bit register used to store data to be handled during SIO1 serial transmission 2 The lower order 8 bits of SBUFI are transferred to the data shift regist
17. VCPWMO compare VCPWM 1 compare register H VCPWM1H register L VCPWMOL VCPWMO output M VCPWM output control circuit atch control circuit VCPWMO VCPWM1 output output Overflow VCPWMO 1 CPWMOOV set signal additional pulses lt q Occurs in every overall period generation counter VCPWM1 compare register L VCPWM1L Figure 3 10 1 VCPWMO and VCPWM1 Block Diagram 3 77 VCPWM 3 10 4 Related Registers 3 10 4 1 VCPWMO VCPWM1 control register VCPWMOC 1 The VCPWMO VCPWMI control register controls the operation and interrupts of VCPWMO and VCPWMI Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE84 00000000 R W veewmoc CPWMOC7 CPWMOC6 CPWMOC5 CPWMOC4 ENCPWM ENCPWMO CPWMOOV CPWMOIE CPWMOC7 to CPWMOCA bits 7 to 4 VCPWMO VCPWM1 period control e Fundamental wave period Value represented by CPWMOC7 to CPWMOC4 1 x SS Tcyc Overall period Fundamental wave period x 16 ENCPWM bit 3 VCPWM1 operation control e When this bit is set to 1 VCPWMI is active e When this bit is set to 0 the VCPWMI output ternary can be controlled using bits 7 to 4 of VCPWMIL ENCPWMO bit 2 VCPWMO operation control When this bit is set to 1 VCPWMO is active When this bit is set to 0 the VCPWMO output ternary can be controlled using bits 7 to 4 of VCPWMOL CPWMOOV bit 1 VCPWM0 VCPWM1 overflow flag This bit is set at the interval equal to the overall p
18. analog input 1 channel with 10x 20x operational amplifier analog input 1 channel for VREF1 2V analog input 1 channel for temperature sensor 5 Conversion time select 6 Reference voltage automatic generation 7 AD conversion reference voltage source select 3 8 2 Functions 1 Successive approximation The ADC has a resolution of 12 bits e trequires some conversion time after starting conversion processing The conversion results are placed in the AD conversion results register ADRLC ADRHC 2 AD conversion select resolution switching The AD converter supports two AD conversion modes 12 and 8 bit conversion modes so that the appropriate conversion resolution can be selected according to the operating conditions of the application Mode switching is accomplished through the AD mode register ADMRC 3 Analog input The signal to be converted is selected using the AD control register ADCRC out of 10 types of analog signals that are supplied from ports P02 toP04 P13 to P15 and P70 the 10x 20x amplifier VREF1 2V temperature sensor See 3 9 Reference Voltage Generator Circuit VREF for the control of the 10x 20x amplifier 4 Conversion time select The AD conversion time can be set to 1 1 to 1 128 frequency division ratio The AD mode register ADMRC and AD conversion result low byte register ADRLC are used to select the conversion time for appropriate AD conversion 5 Automatic reference voltage generation con
19. port 1 retains the state that is established when the HALT or HOLD mode is entered LC870G00 Chapter 3 3 3 3 3 1 Port 7 Overview Port 7 is a 1 bit I O port equipped with a programmable pull up resistor It is made up of a data control latch and a control circuit The input output direction of port data can be controlled on a bit basis Port 7 can also serve as an input port for external interrupts It can also be used as an input port for the capture signal input and HOLD mode release signal input There is no user option for this port 3 3 2 D 2 3 4 Functions Input output port 1 bit P70 Thebit 0 of the port 7 control register P7 FESC is used to control the port output data and the bit 4 to control the I O direction of port data e P70 is of the N channel open drain output type Each port bit is provided with a programmable pull up resistor Interrupt input pin function e P70 is assigned to INTO and used to detect a low or high level or a low or high edge and set the interrupt flag Timer OL capture input function A timer OL capture signal is generated each time a signal change such that the interrupt flag is set is supplied to the port selected from P70 and P16 When a selected level of signal is input to P70 that is specified for level triggered interrupts a timer OL capture signal is generated at 1 cycle interval This continues while the input is present HOLD mode release function Wh
20. the usable instructions vary depending on the address of RAM The efficiency improvement of use ROM and execution speed can be attempted by using these instructions properly 2 2 LC870G00 Chapter 2 FFFFH Reserved for system FFOOH E FEFFH SFR space BR Note Some registers are 9 bit FEOOH Vv FDFFH 2000H A A AA HIM 1FFFH Stack space EN A A Bit instruction direct long Bit instruction direct short Non bit instruction direct long indirect 16 bit operation instruction direct indirect Non bit instruction direct short 9 bit 0200H 01FFH 0100H 00FFH 0000H Fig 2 4 1 RAM Addressing Map When the value of the PC is stored in RAM during the execution of a subroutine call instruction or interrupt assuming that SP represents the current value of the stack pointer the value of BNK and the lower order 8 bits of the 17 bit PC are stored in RAM address SP 1 and the higher order 9 bits in SP 2 after which SP is set to SP 2 2 5 Accumulator A Register ACC A The accumulator ACC also called the A register is an 8 bit register that is used for data computation transfer and I O processing It is allocated to address FEOOH in the internal data memory space and initialized to 00H on a reset Address Initial value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE00 0000 0000 R W AREG AREG7 AREG6 AREGS AREG4 AREG3 AREG2 AREGI AREGO 2 6 B Register B The B register
21. x rocas recat rocaro cars rocana Tocats roca rocca caua 3 4 4 8 Timer counter 0 capture register high byte TOCAH 1 This register is a read only 8 bit register used to capture the contents of timer counter O high byte TOH on an external input detection signal Address Initial value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FEI7 XXXX XXXX R TOCAH TOCAH7 TOCAH6 TOCAHS TOCAH4 TOCAH3 TOCAH2 TOCAHI TOCAHO 3 29 3 30 3 31 3 5 3 5 1 Timer Counter 1 T1 Overview The timer counter 1 T1 incorporated in this series of microcontrollers is a 16 bit timer counter with a prescaler that provides the following four functions D 2 3 4 3 5 2 2 3 Mode 0 8 bit programmable timer with an 8 bit prescaler with toggle output 8 bit programmable timer counter with toggle output Mode 1 Two channels of 8 bit PWM with an 8 bit prescaler Mode 2 16 bit programmable timer counter with an 8 bit prescaler with toggle output the lower order 8 bits may be used as a timer counter with toggle output Mode 3 16 bit programmable timer with an 8 bit prescaler with toggle output the lower order 8 bits may be used as a PWM Functions Mode 0 8 bit programmable timer with an 8 bit prescaler with toggle output 8 bit programmable timer counter with toggle output TIL functions as an 8 bit programmable timer counter that counts the number of signals obtained by d
22. 0 data direction register PODDR 1 The portO data direction register is an 8 bit register that controls the I O direction of port 0 data in 1 bit units A 1 in bit POnDDR places port POn into the output mode and a 0 places into the input mode Bit7 must always set to 0 2 When bit POnDDR is set to 0 and bit POn of port 0 data latch is set to 1 the port POn is an input with a pull up resistor 3 PO4DDR must be set to O for VCPWMI output In this case pin P04 can output a VCPWMI output even if PO4DDR is O 4 PO3DDR must be set to 0 for VCPWMO output In this case pin P03 can output a VCPWMO output even if PO3DDR is 0 Address Initial value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE41 0000 0000 R W PODDR FIXO PO6DDR POSDDR PO4DDR PO3DDR PO2DDR POIDDR POODDR Port POn State Internal Pull up de Input Output esistor Enabled OFF 3 1 3 3 Port 0 Function Control Register POFCR 1 The port 0 function control register is a 6 bit register that controls the shared output of port 0 Address Initial value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE42 0000 0000 R W POFCR TiHPWMEN TILPWMEN POFLG POIE CLKOEN CKODV2 CKODVI CKODVO T1HPWMEN bit 7 timer 1 PWMH output control When P06 is placed in the output mode POGDDR 1 the EOR of AND of this bit and timer 1 PWMH output and the port data latch is placed at pin PO6 T1HPWMEN P06 P06 Pin Data in Output Mode PO
23. 2 VCPWMIL is assigned bits 7 to 4 and all of its lower order 4 bits are apparently set to 1 when it is read 3 When the VCPWMI control bit VCPWMOC FE84 bit 3 is set to 0 the output of VCPWMI ternary can be controlled using bits 7 to 4 of VCPWMIL Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE82 0000 HHHH R W VCPWMiL CPWM1L3 CPWM1L2 CPWM1L1 CPWM1LO z ENCPWM1 CPWM1L3 CPWM1L2 CPWM1L1 0 FE84 bit3 FE82 bit7 FE82 bit6 FE82 bit5 4 VCPWM1 Output 3 10 4 5 VCPWM1 compare register H VCPWM1H 1 The VCPWMI compare register H controls the fundamental pulse width of VCPWMI Fundamental pulse width Value represented by CPWMIH7 to CPWMIHO x iTcyc 2 When bits 7 to 4 of VCPWMIL are all fixed at 0 VCPWMI can serve as period programmable 8 bit PWM that is controlled by VCPWMIH Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE53 0000 0000 R W vcPWM1H CPWM1H7 CPWM1H6 CPWM1H5 CPWM1H4 CPWM1H3 CPWM1H2 CPWM1H1 CPWM1HO Additional pulse D o D counter Additional pulses J l PWM2H PWM3H setting value Fundamental pulse counter Fundamental PVM waveform T PWM output i waveform r r 1 i 3 79 VCPWM e The 12 bit PWM has the following waveform structure Theoverall period consists of 16 fundamental wave p
24. 3 5 HALT and HOLD Mode Operation o 3 19 Timer Counter 0 TO o ca 3 21 3 4 1 Overview o eee eee eee ee eee eee eee ee 3 21 3 4 2 Functions o 3 21 3 4 3 Circuit Configuration o Tee eee ee ee eee 3 23 3 4 4 Related Registers ruuansassusuusaussusunsubSSsssunsusassunsusussupunusmuausussnuussauusensunsuuos 3 27 Timer Counter 1 T1 o 3 32 3 5 1 Overview o Tee eee ee ree eee ee ee ee ee 3 32 3 5 2 Functions wuuasassuuuuuansunsususausunssuuusussusuaAsussusuusisssausunsnususunsnsuasesensuusuases 3 32 3 5 3 Circuit Configuration Furusassuusuuamsausunssssassasunsuhumsassuuuusussususunuaususunsunsuuss 3 34 3 5 4 Related Registers Sn ee 3 39 Base Timer BT RT 3 45 3 6 1 Overview o 3 45 3 6 2 Eunctions o o ree eee ee eee eee ee 3 45 3 6 3 Circuit Configuration o 3 46 3 6 4 Related Registers o Tere ree eee eee ee eee ee ee 3 48 Serial Interface 1 SIO1 ssanasussansuasasunaansunsassaAusaAnauaAuaaunuunanuausanuansaunuansuuuaa 3 51 3 7 1 Overview muamassssuuuassussuunmsussunssuuusssensusuUscussussEHPSHsuseinssssseusensumsausunsuuuamues 3 51 3 7 2 Functions wuansassansuussssunsnsunnssasunsssuasassussanussuuuuumz usseussussusunsnsuasussnsuuuaues 3 51 3 7 3 Circuit Coufiguration A O 3 52 3 7 4 SIO1 Transmission Examples rursuasssussuuuanssssunsmmeseusensussusunsensuasusensuunuases 3 56 3 7 5 Related Registers Fuuusassssuusuusssuanusuausussunsussssununsunsussssssausussnsuuassensunusses 3 60 AD Converter ADC 12 ssanasassnunuauuuusussanssusssnauAnaunsuansauanansuausunsuan
25. Clock Divider Function e Can run on low consumption current e Minimum instruction cycle selectable from 375ns 750ns 1 5us 3 0ps 6 0us 12 0us 24 0us 48 0us and 96 0us at SM main clock lilnternal Reset Circuit ePower on reset POR function 1 POR reset is generated only at power on time 2 The POR release level is 1 67V e Low voltage detection reset LVD function 1 LVD and POR functions are combined to generate resets when power is turned on and when power voltage falls below a certain level 2 The use disuse of the LVD function and the low voltage threshold level can be selected from 7 levels 1 91V 2 01V 2 31V 2 51V 2 81V 3 79V and 4 28V through option configuration ll Standby Function HALT mode Halts instruction execution while allowing the peripheral circuits to continue operation 1 Oscillation is not halted automatically 2 There are three ways of resetting the HALT mode 1 Setting the reset pin to the low level 2 Having the watchdog timer or LVD function generate a reset 3 Having an interrupt generated e HOLD mode Suspends instruction execution and the operation of the peripheral circuits 1 The CF RC and crystal oscillators automatically stop operation Note The low speed RC oscillator is controlled directly by the watchdog timer its oscillation in the standby mode is also controlled by the watchdog timer 2 There are four ways of resetting the HOLD mode 1 Setting the reset pin to the lower le
26. FE5Fh need setting up TOLCMP TOHCMP flag set flag set 8 bit programmable timer with 8 bit programmable timer with programmable prescaler programmable prescaler Figure 3 4 1 Mode 0 TOLONG 0 TOLEXT 0 Block Diagram Capture trigger Registers l01 CR FE5Dh I23CR FE5Eh and ISL FESFh need setting up TOCAL Capture External Glock input TOL Set in ISL FE5Fh dE Match buffer register d emt TOHCMP flag set 8 bit programmable counter 8 bit programmable timer with programmable prescaler Figure 3 4 2 Mode 1 TOLONG 0 TOLEXT 1 Block Diagram 3 25 Clock Clear Tcyc gt Prescaler Match Comparator Capture trigger TOCAH TOCAL Registers 101CR FE5Dh Capture 123CR FE5Eh and ISL FESFh need setting up TOLCMP TOHCMP flags set S 6 bit programmable timer programmable prescaler Figure 3 4 3 Mode 2 TOLONG 1 TOLEXT 0 Block Diagram Capture trigger Registers 101CR FE5Dh Capture I23CR FE5Eh and ISL FESFh need setting up External clock input Set in ISL FEBFh TOLCMP Match buffer register TOHCMP flags set eload R TOHR TOLR lt 16 bit programmable counter gt Figure 3 4 4 Mode 3 TOLONG 1 TOLEXT 1 Block Diagram 3 26 LC870G00 Chapter 3 3 4 4 Related Registers 3 4 4 1 Timer counter 0 control register TOCNT 1 This register is an 8 bit register that controls the operation and interrupts of TOL a
27. Falling edge detected 0 0 eae 1 o ring eg desd SSS PORTS INT2IF bit 1 INT2 interrupt source flag This bit is set when the conditions specified by INT2HEG and INT2LEG are satisfied When this bit and the INT2 interrupt request enable bit INT2IE are set to 1 a HOLD mode release signal and an interrupt request to vector address 0013H are generated The interrupt flag cannot be set however by a rising edge occurring when P16 data which is established when the HOLD mode is entered is in the high state or by a falling edge occurring when P16 data which is established when the HOLD mode is entered is in the low state Consequently to release the HOLD mode with P16 it is recommended that P16 be used in the double edge interrupt mode This bit must be cleared with an instruction as it is not cleared automatically INT2IE bit 0 INT2 interrupt request enable When this bit and INT2IF are set to 1 a HOLD mode release signal and an interrupt request to vector address 0013H are generated 3 2 3 8 Input signal select register ISL 1 The input signal select register is an 8 bit register that controls the timer 0 input noise filter time constant buzzer output and base timer clock Address Initial value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FESF 0000 0000 R W ISL STOHCP STOLCP BTIMCI BTIMCO BUZON NFSEL NFON STOIN STOHCP bit 7 Timer OH capture signal input port select This bit selects the t
28. HPWM2AH must be written finally in the data update process of the program because writing to HPWM2AH is the trigger of reload operation H2ACKSL H2ACKDV GER the system clock Internal high speed RC 40M Hz H2ABWSL oscillation control H2A40MO set signal for H2AOVF fundamental gt counter 8bit additional P puls counter P17H2ASL set H2ABWSL TIPWMH or BUZ output decorder P17 function output PWM wave HPWM 2 outpu generate circuit oo000000 P16 function output TIPWML output comparator output reload signal generate circuit Figure 3 11 1 HPWM2 Block Diagram H2ARLBSY jinhibit writing to HPWM2AH HPWM2AL bits 7 to 6 0 3 85 HPWM2 fundamental period i fundamental period HPWM2AH value 91h HPWM2AH value 00 fundamental period 256 x period set by HPVM2AC bits 6 to 5 high puls width value of HPWM2AH 1 x period set by HPWM2AC bits 6 to 5 Figure 3 11 2 Examples of waveform of the 8 bit PWM mode H2ABWSL 0 i overall period i overall period fundamental fundamental fundamental fundamental fundamental fundamental fundamental fundamental period i period B period i period period period i period period HPWV2AH HPWN2AL bits 7 value 001h HPWV2AH HPWN2AL bits 7 value 002h HPWV2AH HPWN2AL bits 7 value 003h HPWV2AH HPWM2AL bits 7 to 6 value 004h HPWM
29. INTIIE INTOLH INTOLV INTOIF INTOIE INT1LH bit 7 INT1 detection polarity select INT1LV bit 6 INT1 detection level edge select INT1LH INT1LV INT1 Interrupt Conditions P17 Pin Data 0 Falling edge detected Low level detected 0 a sa MNT Tis INT1IF bit 5 INT1 interrupt source flag This bit is set when the conditions specified by INTILH and INTILV are satisfied When this bit and the INT interrupt request enable bit INTIIE are set to 1 a HOLD mode release signal and an interrupt request to vector address OOOBH are generated This bit must be cleared with an instruction as it is not cleared automatically INT1IE bit 4 INT1 interrupt request enable When this bit and INTIIF are set to 1 a HOLD mode release signal and an interrupt request to vector address 000BH are generated 3 12 LC870G00 Chapter 3 INTOLH bit 3 INTO detection polarity select INTOLV bit 2 INTO detection level edge select INTOLH INTOLV INTO Interrupt Conditions P70 Pin Data 0 Falling edge detected Low level detected 0 E a rige data INTOIF bit 1 INTO interrupt source flag This bit is set when the conditions specified by INTOLH and INTOLV are satisfied When this bit and the INTO interrupt request enable bit INTOIE are set to 1 a HOLD mode release signal and an interrupt request to vector address 0003H are generated This bit must be cleared with an instruction as it is not cleared automatically
30. In mode 1 transmission is automatically started when a falling edge of receive data is detected While mode 1 is on the falling edge of data is always detected at the data I O port P11 Consequently if the transmit port is assigned to the data output port P10 it is likely that data transmissions are started unexpectedly according to the changes in the state of P11 5 Starting receive operation Set SIIREC to 1 Once SIIREC is set to 1 do not attempt to write data to the SCONI register until the SIIEND flag is set Detect the falling edge of receive data 6 Reading data after an interrupt Read SBUFI SBUFI has been loaded with serial data read from the data I O port even in the transmission mode When SBUFI is read in the data about the position of the stop bit is read into bit 1 of the PSW e Clear SIIEND and exit interrupt processing Return to step 4 when repeating processing Note Make sure that the following conditions are met when performing continuous mode reception processing with SIOI in mode UART The number of stop bits is set to 2 or greater e Clearing of SIIEND during interrupt processing terminates before the next start bit arrives 3 7 4 8 Bus master mode mode 2 1 Setting the clock e Setup SBRI Setting the mode N Set as follows SIIMO 0 SIMI 1 SIIDIR SNTE 1 SILREC 0 3 Setting up the ports Designate the clock and data ports as N channel open drain
31. P16DDR PISDDR PI4DDR PI3DDR P12DDR P11DDR P10DDR Register Data Port Pin State Built in Pull up P1nDDR Output Resistor Enabled Open OFF 0 0 p o Enabled Built in pull up resister Enabled High open CMOS N channel open drain 3 2 3 3 Port 1 function control register P1FCR 1 The port 1 function control register is an 8 bit register that controls the shared output of port 1 Address Initial value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE46 0000 0000 R W PIFCR P17FCR PI6FCR PISFCR P14FCR P13FCR P12FCR P11FCR PIOFCR P1n Pin Data in Output Mode P1nDDR 1 Value of port data latch P17 HPWM2 data or base timer buzzer data i The high data output pins P10 to P17 that are selected as N channel open drain outputs by user option is represented by an open circuit 1 1 1 1 1 1 1 o1 ES FE uM a a DEER GN Lor IL EA pto po o1 poro EEE ME MEE A Ree pu ume HE ee Eo E A MEN UNS WE ESE pro 0 ee NM E SS ET RESUME EE a re EEE UE n A i R 3 8 LC870G00 Chapter 3 P17FCR bit 7 P17 function control HPWM 2 or base timer buzzer output control This bit controls the output data at pin P17 When P17 is placed in the output mode P17DDR 1 and P17FCR is set to 1 the EOR of HPWM2 output or buzzer output from the base timer and the port data latch is placed at pin 17 The selection between HPWMQ and base timer b
32. TmMSXN FDO OX nm EA AE A quos uus c rop ME AE AA AMA A AI 7 Address Initial Value R W LG870 0 Remarks B T8 BT7 B TO B T5 B TA B T3 B T2 BTI B TO FEDC aes Wl ate AAA A A A ub pa E A A A E ME NA a TEA E O DA A da EA A E FEO XoXxex WW Em 2 mode GCdxal cme coms ona as om oni ono FEEL Teaser WW LET 20 ode eoc ota n am cams ons Ue ons one am ano FE Iesel WW DHL a ode ees om7 ome oms oma oms om2 omi omo F3 Iesel NW DIH HedeeX dan omr ome ome oma pms ome at DEO EE or Re Wee ee EE LC870G00 APPENDIX I AI 9 W POFCR R POFCR W PO R PO W PODDR R PODDR LC870G00_APPENDIX Il Bus T1HPWM POFCR FE49 bits BO PU ae IR 4 PO FE40 bit6 D E CMOS Pin or Nch OD P06 Special input CLKOUT Ee Contra aen circuit Ee POFCR FE42 bit5 d P i PO FE40 bit5 c D Q or Pin P05 T PODDR FE41 bit5 Table of Port 0 Shared Function et Special input FUNCTONOupt timer H PWM output Clock output systeny subclock selectable timer1L PWM output Port 0 Block Diagram P06 P05 Option Output type CMOS or N channel OD selectable on a bit basis AII 1 Port Block Diagrams o PU 2 a E PO FE40 bit4 CMOS W PO Nch OD quu Lf m R PO UN FE41 bit4 IE Special input IR een E W PODDR C R PODDR CD
33. Vssl VssS2 VppD Reference voltage outputs 1 VREF Dedicated debugger port 1 OWPO 1 1 MTimers e Timer 0 16 bit timer counter with 2 capture registers Mode 0 8 bit timer with an 8 bit programmable prescaler with two 8 bit capture registers x 2 channels Mode 1 8 bit timer with an 8 bit programmable prescaler with two 8 bit capture registers 8 bit counter with two 8 bit capture registers Mode 2 16 bit timer with an 8 bit programmable prescaler with two 16 bit capture registers Mode 3 16 bit counter with two 16 bit capture registers e Timer 1 16 bit timer counter that supports PWM toggle outputs Mode 0 8 bit timer with an 8 bit prescaler with toggle outputs 8 bit timer counter with an 8 bit prescaler with toggle outputs Mode 1 8 bit PWM with an 8 bit prescaler x 2 channels Mode 2 16 bit timer counter with an 8 bit prescaler with toggle outputs toggle outputs also possible from lower order 8 bits Mode 3 16 bit timer with an 8 bit prescaler with toggle outputs lower order 8 bits may be used as a PWM output e Base timer 1 The clock is selectable from the subclock 32 768kHz crystal oscillation the low speed RC system clock and timer 0 prescaler output 2 with an 8 bit programmable prescaler 3 Interrupts programmable in 5 different time schemes HESIO e SIO1 8 bit asynchronous synchronous serial interface Mode 0 Synchronous 8 bit serial I O 2 or 3 wire configuration 2 to 512
34. and SILOVR then exit interrupt processing Return to step 4 to repeat processing Bus slave mode mode 3 Setting the clock Set up SBRI to set the acknowledge data setup time Setting the transmission mode Set as follows SIIMO 1 SIIMI 1 SIIDIR SIIIE 1 SILREC 0 Setting up ports Designate the clock and data ports as N channel open drain output ports 3 58 4 5 6 7 LC870G00 Chapter 3 Starting communication waiting for an address o KD o Set SILREC SIIRUN is automatically set on detection of a start bit Perform receive processing 8 bits and set the clock output to 0 on the falling edge of the 8th clock which generates an interrupt Checking address data after an interrupt Detecting a start condition sets SILOVR Check SIIRUN 1 and SILOVR 1 to determine if the address has been received SILOVR is not automatically cleared Clear it by instruction Read SBUF1 and check the address If no address match occurs clear SILRUN and SIIEND and exit interrupt processing then wait for a stop condition detection at of step 8 Receiving data x o Clear SILEND and exit interrupt processing If a receive sequence has been performed send an acknowledge and release the clock port after the lapse of SBR1 value 1 x Tcyc When a stop condition is detected SITRUN is automatically cleared and an interrupt is generated Then clear SILEND to exit interrupt processing an
35. be released only when it is set for level detection Address Initial value R W Name BIT7 BIT6 BIT5 BIT4 BITS BIT2 BIT1 BITO FE44 0000 0000 R W Pil P10 Crear momo Pew virst exo mo ro Bit 7 bit 5 and bit O of PITST FE47 must always be set to 0 3 2 3 Related Registers 3 2 8 4 Port 1 data latch P1 1 The port 1 data latch is an 8 bit register for controlling port 1 output data and pull up resistors 2 When this register is read with an instruction data at pins P10 to P17 is read in If P1 FE44 is manipulated with an instruction NOTI CLR1 SETI DBZ DBNZ INC or DEC the contents of the register are referenced instead of the data at port pins 3 Port 1 data can always be read regardless of the I O state of the port Address Initial value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE44 0000 0000 R W P1 P17 P16 P15 P14 P13 P12 P11 P10 3 2 3 2 Port 1 data direction register P1DDR 1 The port 1 data direction register is an 8 bit register that controls the I O direction of port 1 data on a bit basis Port P1n are placed in the output mode when bit PInDDR is set to 1 and in the input mode when bit PInDDR is set to 0 3 7 PORTS 2 When bit PInDDR is set to O and the bit P1n of the port 1 data latch is set to 1 port PIn becomes an input with a pull up resistor Address Initial value R W Name BIT7 BIT6 BITS BIT4 BIT3 BIT2 BIT1 BITO FE45 0000 0000 R W PIDDR P17DDR
36. bits 5 to 3 General purpose flags These bits can be used as general purpose flag bits Any manipulations of these bits exert no influence on the operation of this function block SRCSEL bit 1 RC clock select 1 When this bit is set to 0 the medium speed RC oscillator clock is selected as the RC clock source 2 When this bit is set to 1 the low speed RC oscillator clock is selected as the RC clock source See Figure 4 2 1 for details SRCSTART bit 0 Low speed RC oscillator circuit control 1 A Oin this bit stops the low speed RC oscillator circuit 2 A 1 in this bit starts the low speed RC oscillator circuit 3 When a reset occurs this bit is cleared and the oscillator circuit is disabled for oscillation 4 When the microcontroller enters the HOLD mode this bit is set as described below according to the value of SRCSEL If SRCSEL is set to 0 the state of this bit remains unchanged If SRCSEL is set to 1 this bit is set and the oscillator starts oscillation and the low speed RC oscillator is designated as the system clock source when the microcontroller returns from the HOLD mode 4 13 System Clock 4 2 4 5 System clock divider control register CLKDIV 3 bit register 1 The system clock divider control register controls the frequency division processing of the system clock Address Initial value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FEOC HHHH H000 R W CLKDIV CLKDV2 CLKDV1
37. circuit oscillates according to the internal resistor and capacitor 2 Theinternal high speed RC oscillator serves as the system clock that is used for high speed operation 4 2 3 6 Power control register PCON 3 bit register 1 The power control register specifies the operating mode normal HALT HOLD X tal HOLD 4 2 3 7 Oscillation control register OCR 8 bit register 1 Theoscillation control register controls the start stop operations of the main clock subclock and medium speed RC oscillator circuits 2 This register selects the system clock 3 The register sets the division ratio of the oscillation clock to be used as the system clock to or 5 4 The data at the CF1 XT1 and CF2 XT2 pins can be read as bits 2 and 3 of this register 4 2 8 8 Oscillation control register 2 XT2PC 6 bit register 1 Theoscillation control register 2 controls the main clock oscillator circuit 2 This register controls the general purpose inputs outputs at the CF1 XT1 and CF2 XT2 pins 4 2 8 9 Oscillation control register 3 OCR3 8 bit register 1 Theoscillation control register 3 controls the start stop operations of the low speed high speed RC oscillator circuits 2 This register controls the RC clock selector and the high speed clock selector 4 2 3 10 System clock division control register CLKDIV 3 bit register 1 The system clock division control register controls the operation of the system clock divider circuit
38. circuits retain their state that is established when the microcontroller enters the HALT or HOLD mode 3 74 LC870G00 Chapter 3 3 10 Voltage control PWM VCPWMO VCPWM1 3 10 1 Overview This series of microcontrollers incorporates two 12 bit PWMs named VCPWMO and VCPWM1 Each PWM is made up of a PWM generator circuit that generates multifrequency 8 bit fundamental PWM waves and a 4 bit additional pulse generator 3 10 2 Functions 1 VCPWMO Fundamental PWM mode register VCPWMOL 0 Fundamental wave period mene Tcyc programmable in EI Tcyc increments common to VCPWM1 e High level pulse width 0 to Fundamental wave period 3 Teyc programmable in 3 Tcyc increments 2 VCPWMO Fundamental wave Additional pulse PWM mode Fundamental wave period gene Tcyc programmable in 18 Tcyc increments common to VCPWM1 Overall period Fundamental wave period x 16 e High level pulse width 0 to Overall period 3 Teyc programmable in 3 Teyc increments 3 VCPWMI Fundamental wave PWM mode register VCPWM1L 0 Fundamental wave period Leza Tcyc programmable in KEN Tcyc increments common to VCPWMO e High level pulse width 0 to Fundamental wave period y Teyc programmable in y Teyc increments 4 VCPWMI Fundamental Additional pulse PWM mode Fundamental wave period enam Tcyc programmable in 18 Tcyc increments common to VCPWMO Overall period Fundamental wave period x 16 e High level pulse width 0
39. clock 0 Internal high speed RC 40MHz In System clock fSCLK H2ABWSL bit 4 HPWM2 resolution select H2ABWSL HPWM2 resolution 0 8 bit fundamental nu 10 bit fundamental additional pulse H2ARUN bit 3 HPWM2 operation control Setting this bit to 0 stops the operation of HPWM2 Setting this bit to 1 starts the operation of HPWM2 H2ARLBSY bit 2 HPWM2 reload wait flag When HPWM2 is operatingf H2ARUN 1 when HPWM2AH is written reload wait flag H2ARLBSY is set and writing to HPWM2AL bits 7 to 6 and HPWMO2AH is inhibited The conditions required to clear H2ARLBSY are 1 When HPWN2 is not operationg H2ARUN 0 2 When an overflow signal of the next PWM period fundamenta period at 8 bit PWM mode overall period at 10 bit mode is generated H2AOVF bit 1 HPWM2 period overflow flag When HPWM2 is operating H2ARUN 1 this bit is set whenever an overflow signal of the PWM period fundamenta period at 8 bit PWM mode overall period at 10 bit mode is generated This bit must be cleared with an instruction H2AIE bit 0 HPWM2 interrupt request enable When this bit and H2AOVF are set to 1 an interrupt request to vector address 0033H are generated 3 87 HPWM2 Note When the internal high speed RC 40MHz is used for HPWM2 operation an oscillation stabilization time of about 10 uS after an oscillation start H2A40MON 0 oscillation stop gt 1 oscillation start is required b
40. generated when the value of this match buffer register coincides with that of timer 1 low byte TIL The match buffer register is updated as follows TILR and the match register has the same value when in inactive state TI LRUN 0 If active TILRUN 1 the match buffer register is loaded with the contents of TILR when the value of TIL reaches 0 Timer 1 match data register high byte T1HR 8 bit register with a match buffer register This register is used to store the match data for T1H It has an 8 bit match buffer register A match signal is generated when the value of this match buffer register coincides with that of timer 1 high byte T1H The match buffer register is updated as follows T1HR and the match register have the same value when in inactive state TIHRUN 0 If active TI HRUN 1 the match buffer register is loaded with the contents of TIHR when the value of T1H reaches 0 Timer 1 low byte output TTPWML The TIPWML output is fixed at the high level when TIL is inactive If TIL is active the TIPWML output is fixed at the low level when TILR FFH Timer 1 low byte output is a toggle output whose state changes on a TIL match signal when TIPWM timer 1 control register bit 4 is set to 0 When TIPWM timer 1 control register bit 4 is set to 1 this PWM output is cleared on an TIL overflow and set on a TIL match signal Timer 1 high byte output TTPWMH The TIPWMH output is fixed at the high level when T1
41. is combined with the ACC to form a 16 bit arithmetic register during the execution of a 16 bit arithmetic instruction During a multiplication or division instruction the B register is used with the ACC and C register to store the results of computation In addition during an external memory access instruction LDX or STX the B register designates the higher order 8 bits of the 24 bit address The B register is allocated to address FEO1H of the internal data memory space and initialized to 00H on a reset Address Initial value R W Name BIT7 BIT6 BITS BIT4 BIT3 BIT2 BIT1 BITO FE01 0000 0000 R W BREG BREG7 BREG6 BREGS BREG4 BREG3 BREG2 BREGI BREGO 2 7 C Register C The C register is used with the ACC and B register to store the results of computation during the execution of a multiplication or division instruction In addition during a C register offset indirect instruction the C register stores the offset data 128 to 127 to the contents of an indirect register The C register is allocated to address FEO2H of the internal data memory space and initialized to 00H on a reset Address Initial value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE02 0000 0000 R W CREG CREG7 CREG6 CREGS CREG4 CREG3 CREG2 CREGI CREGO 2 8 Program Status Word PSW The program status word PSW is made up of flags that indicate the status of computation results a flag to access the 9th bit of RAM and a
42. is free of noise interferences as the ground for the capacitors rough standard values are R less than 5 kQ C 1000 pF to 0 1uF Do not lay analog signal lines close to in parallel with or in a crossed arrangement with digital pulse signal lines or signal lines in which large current changes can occur Shield both ends of analog signal lines with noise free ground shields Make sure that no digital pulses are applied to or generated out of pins adjacent to the analog input pin that 1s being subject to conversion Correct conversion results may not be obtained because of noise interferences 1f the state of port outputs is changing To minimize the adverse influences of noise interferences it is necessary to keep the line resistance across the power supply and the VDD pins of the microcontroller at minimum This should be kept in mind when designing an application circuit 3 69 ADC12 Adjust the amplitudes of the voltage at the oscillator pin and the I O voltages at the other pins so that they fall within the voltage range between VDD and VSS 10 To obtain valid conversion data perform conversion operations on the input several times discard the maximum and minimum values of the conversion results and take an average of the remaining data 3 70 LC870G00 Chapter 3 3 9 Reference Voltage Generator Circuit 3 9 1 Overview The reference voltage generator circuit controls the operation on off of the reference voltage VR
43. mode 4 12 LC870G00 Chapter 4 Register Data CF2 XT2 State XT2DT XT2DR XT2CMOS Input Output O Enabled Open o When general purpose input output mode is selected See Figure 4 2 4 2 Oscillation Control Register for details 4 2 4 4 Oscillation Control Register 3 OCR3 8 bit register 1 The oscillation control register 3 is an 8 bit register that controls the operation of the low speed RCoscillator circuit and the high speed RC oscillator circuit and selects the high speed clock source and the RC clock source Address Initial value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE7C 0000 0000 R W OCR3 FRCSEL FRCSTART OCR3B5 OCR3B4 OCR3B3 FIXO SRCSEL SRCSTART FRCSEL bit 7 High speed clock select 1 When this bit is set to O the main clock is selected as the high speed clock source 2 When this bit is set to 1 the high speed RC oscillator clock is selected as the high speed clock source See Figure 4 2 1 for details FRCSTART bit 6 High speed RC oscillator circuit control 1 Setting this bit to O stops the oscillation of the high speed RC oscillator circuit 2 Setting this bit to 1 starts the oscillation of the high speed RC oscillator circuit 3 When a reset occurs this bit is cleared and the oscillator circuit is disabled for oscillation 4 When the microcontroller enters the HOLD mode this bit is cleared and the oscillator circuit is disabled for oscillation OCR3BS5 to 3
44. nun 2 1 0 2 1 2 2 What is a Wait Sequence eee eee eee eee rere eee eee ere eee ere ee re re 2 1 0 Chapter 3 Peripheral System Configuration kr Rad Deis deci EEN 3 1 3 1 Port 0 Mursanhhursuruesesuenenusaenensenensusaepenssuensessenensussesessenenessenenussenessenesssaes 3 1 3 1 1 Overview ere rer eee ere rece e rere errr errr OTTOTTOTOTTOTTOTOTTOTOOEE 3 1 3 1 2 Functions a 3 1 3 1 3 Related Registers AAA 3 2 3 2 3 3 3 4 3 5 3 6 3 7 3 8 Contents 3 1 4 Options muuyusassssuuuusausunsunusseussnsuuuzquassunuassssusunusbu essunsensussunensuausa sensunumsune 3 4 3 1 5 HALT and HOLD Mode Operation o 3 4 Port 1 AAA 3 6 3 2 1 Overview o a 3 6 322 Eunctions o eee ee ree ree eee ee eee ee eee 3 6 3 2 3 Related Registers Fuuusassusauuyuanssusununsessunsusasssusensususu5esssssaususununuuasussunsususe 3 7 3 2 4 Options o 3 16 325 HALT and HOLD Mode Operation o Tee eee ee eee ee eee 3 16 Port 7 MRRRruuuurrrtuuuuuuuerreuuuuuuuuerreuusususssusssseuuansessessuensusumsssssesensussssseseeessusueee 3 1 7 3 3 1 Overview wuruasassusuusaumsusnumssususnsusssusussnssuaussc ossssREARASSERRERRESERSERERRRRGRRR RR RRR uut 3 1 7 3 3 2 Functions wuuaassuuuuuansunsussususseunsusuusussussuasusunsuuuassusumnsusuausensnsuasusesssuauses 3 17 3 3 3 Related Registers Fuuusassssuuuanssusunumsussunuussssunsusansu5susussasseusensuususunsunumues 3 1 8 3 3 4 Options muruunmasssusunuansusunsusnisssunsnuususaHseunsususmssusuzssuuuunascussnunsausunsnsuasusensuuususes 3 19 3
45. of an arithmetic operation and cleared to 0 otherwise An overflow occurs in the following cases lt l gt When MSB is used as the sign bit and when the result of negative number negative number or negative number positive number is a positive 2 When MSB is used as the sign bit and when the result of positive number positive number or positive number negative number is a negative number LC870G00 Chapter 2 3 When the higher order 8 bits of a 16 bits x 8 bits multiplication is nonzero 4 When the higher order 16 bits of a 24 bits x 16 bits multiplication is nonzero 5 When the divisor of a division is 0 There are some instructions that do not affect this flag at all P1 bit 1 RAM bit 8 data flag P1 is used to manipulate bit 8 of 9 bit internal data RAM 0000H to FDFFH Its behavior varies depending on the instruction executed See Table 2 4 2 for details PARITY bit 0 Parity flag This bit shows the parity of the accumulator A register The parity flag is set to 1 when there are an odd number of 1s in the A register It is cleared to 0 when there are an even number of 1s in the A register 2 9 Stack Pointer SP The LC870000 series microcontrollers can use RAM addresses 0000H to FDFFH as a stack area The size of RAM however varies depending on the model of the microcontroller The SP is 16 bits long and made up of two registers SPL at address FEOAH and SPH at address FEOBH It is initial
46. of the master mode is in the system do the timeout processing using the timer module and detect the case of the arbitration lost Return to step 6 when continuing data transmission Go to step 10 to terminate communication Receiving data Set SHREC to 1 Clear SIIEND and exit interrupt processing receive 8bits SBUFI bit 8 acknowledge output Reading received data after an interrupt Read SBUFI Return to step 8 to continue reception of data Go to in step 10 to terminate processing At this moment SBUFI bit 8 data has already been presented as acknowledge data and the clock for the master side has been released 10 Terminating communication 3 7 4 4 2 3 Manipulate the clock output port PI2FCR 0 PI2DDR 1 P12 0 and set the clock output to 0 Manipulate the data output port PI1FCR 0 PIIDDR 1 P11 0 and set the data output to 0 Restore the clock output port into the original state PI2FCR 1 PI2DDR 1 P12 2 0 and release the clock output Wait for all slaves to release the clock and the clock to be set to 1 Allow for a data setup time then manipulate the data output port PI 1FCR 0 PIIDDR 1 Pll 1 and set the data output to 1 In this case the SIO1 overrun flag SHLOVR FE34 bit 2 is set but this will exert no influence on the operation of SIO1 Restore the data output port into the original state set P11FCR to 1 then P11DDR to 1 and P11 to 0 Clear SITEND
47. output ports 4 Starting communication sending an address Load SBUFI with address data Set SIIRUN transfer a start bit SBUFI 8 bits stop bit H 5 Checking for address data after an interrupt Read SBUFI SBUFI has been loaded with serial data from the data I O port even in the transmission mode When SBUFI is read in the data about the position of the stop bit is read into bit 1 of the PSW Check for an acknowledge by reading bit 1 of the PSW e An interrupt does not occur when arbitration lost because SIIRUN is cleared Refer to the note of the table 3 10 1 When possibility of the arbitration lost exists for example other device of the master mode is in the system do the timeout processing using the timer module and detect the case of the arbitration lost 6 Sending data Load SBUFI with output data e Clear SIIEND and exit interrupt processing transfer SBUFI 8 bits stop bit H 3 57 SIO1 7 8 9 Checking sent data after an interrupt Read SBUF1 SBUFI has been loaded with serial data from the data I O port even in the transmission mode When SBUFI is read in the data about the position of the stop bit is read into bit 1 of the PSW Check for an acknowledge by reading bit 1 of the PSW An interrupt does not occur when arbitration lost because SI1RUN is cleared Refer to the note of the table 3 10 1 When possibility of the arbitration lost exists for example other device
48. peripheral module it determines the level priority and interrupt enable status of the interrupt If the interrupt request is legitimate for processing the microcontroller saves the value of PC in the stack and causes a branch to the predetermined vector address The return from the interrupt routine is accomplished by the RETI instruction which restores the old state of the PC and interrupt level 2 Multilevel interrupt control The interrupt function supports three levels of interrupts that is the low level L high level H and highest level X The interrupt function will not accept any interrupt requests of the same level or lower than that of the interrupt that is currently being processed 3 Interrupt priority e When interrupt requests to two or more vector addresses occur at the same time the interrupt request of the highest level takes precedence over the other interrupt requests Among the interrupt requests of the same level the one whose vector address is the smallest is prioritary 4 Interrupt request enable control e The master interrupt enable register can be used to control the enabling disabling of H and L level interrupt requests Interrupt requests of the X level cannot be disabled 5 Interrupt disable period Interrupts are held disabled for a period of 2Tcyc after a write operation is performed to the IE FE08H or IP FEO9H register or the HOLD mode is released Nointerrupt can occur dur
49. port P17 When this bit is set to 1 the timer 1 PWMH output is always set high and port P17 is provided as buzzer output with the signal that is generated by dividing the base timer clock 3 14 LC870G00 Chapter 3 When this bit is set to 0 the buzzer output is always set high in which case port 7 is provided with the timer 1 PWMH output data NFSEL bit 2 Noise filter time constant select NFON bit 1 Noise filter time constant select A noise filter is connected to INT3 INTO INT1 and INT4 do not have a noise filter Noise Filter Time Constant 1 Tcyc i STOIN bit 0 Timer 0 counter clock input port select This bit selects the timer 0 counter clock signal input port When set to 1 a timer 0 count clock is generated when an input that satisfies the INT3 interrupt detection conditions is supplied to P15 When this bit is set to 0 a timer 0 count clock is generated when an input that satisfies the INT2 interrupt detection conditions is supplied to P16 Note If timer OL capture signal input or timer OH capture signal input is specified to both P70 and P14 at the same time as an INT4 any signals from port 7and port 1 are ignored PORTS 3 2 4 Options The following two user options are available for P10 to P17 1 CMOS output with a programmable pull up resistor 2 N channel open drain output with a programmable pull up resistor 3 2 5 HALT and HOLD Mode Operation When in the HALT or HOLD mode
50. program counter is initialized to OOOOH on a reset See Appendix AI 87 Register Map for the initial values of the special function registers SFR lt Notes and precautions gt The stack pointer is initialized to OOOOH Data RAM is never initialized by a reset Consequently the contents of RAM are unpredictable at power on time When using the internal reset function it is necessary to implement and connect an external circuit to the reset pin according to the user s operating environment Be sure to review and observe the operating specifications circuit configuration precautions and considerations discussed in section 4 7 Internal Reset Function 4 22 4 5 4 5 4 5 LC870G00 Chapter 4 Watchdog Timer WDT 1 Overview This series of microcontrollers is provided with a watchdog timer WDT that has the following features 1 Can generate an internal reset signal on an overflow occurring on a timer which runs on either an internal low speed RC oscillator clock or subclock 2 Three standby mode time operating modes continue count operation suspend operation suspend count operation while retaining the count value The primary function of the watchdog timer is to detect program runaway conditions The use of the watchdog timer is highly recommended to enhance system reliability 2 Functions 1 Watchdog timer A 17 bit up counter WDTCT runs on the WDT clock the clock source is
51. register 3 OCR3 bit 1 when the HOLD mode is entered Note 3 If the X tal HOLD mode is entered with the low speed RC oscillator selected as the base timer input clock source and the base timer has been started the low speed RC oscillator circuit retains the state that is established when the X tal HOLD mode is entered 6 Tocontrol the system clock it is necessary to manipulate the following special function registers PCON CLKDIV OCR XT2PC OCR3 Address Initial value RAW Name BIT7 BIT6 BITS BIT4 BIT3 BIT2 BIT1 BITO FE07 HHHH H000 R W PCON XTIDLE PDN IDLE roc nnnm nooo Rw fero _ _lexpvalexpvil cuve es moowe uw xrmc crib KID ea FE7C 0000 0000 OCR3 FRCSEL FRCSTART OCR3B5 OCR3B4 OCR3B3 FIXO SRCSEL SRCSTART 4 2 3 Circuit Configuration 4 2 3 1 Main clock oscillator circuit 1 The main clock oscillator circuit gets ready for oscillation by connecting a ceramic oscillator and a capacitor to the CF1 XT1 and CF2 XT2 pins and controlling the OCR and XT2PC registers 2 The data at the CF1 XT1 and CF2 XT2 pins can be read as bits 2 and 3 of the OCR register 3 The general purpose input configuration must be selected and the CF1 XT1 and CF2 XT2 pins must be held high or low level when neither main nor subclock is to be used or they are not to be used as general purpose input ports 4 6 LC870G00 Chapter 4 4 2 3 2 Subclock oscillator circuit 1 Thesubclock os
52. selected from either internal low speed RC oscillation clock or subclock A WDT reset internal reset signal is generated when the overflow time selected out of 8 time values that is selected by the watchdog timer control register WDTCNT expires At this moment the WDT reset detection flag WDTRSTF is set Since the WDTCT can be cleared by a program it is necessary to code the program so that the WDTCT be cleared at regular intervals Ifthe WDT operation is started with the internal low speed RC oscillator clock selected as the WDT clock source the internal low speed RC oscillation circuit is controlled by both of the oscillation control register 3 OCR3 and WDT Since they control the oscillation independently of each other even if the system clock happens to be suspended by a program runaway condition the WDT continues operation so that it 1s possible to detect the runaway condition Ifthe WDT operation is started when the subclock is selected as the WDT clock a WDT reset is generated on detection of subclock oscillation suspended by the XT function control bit EXTOSC of oscillation control register OCR or entry into the HOLD mode In this case WDTRSTF is set 2 Standby mode time operations The action that the WDT takes in the standby mode can be selected from three operating modes i e continue count operation suspend operation and suspend count operation while retaining the count value If the internal low sp
53. serial transmission mode 0 1 Setting the clock Setup SBRI when using an internal clock 2 Setting the transmission mode Setas follows STIMO 0 SI1M1 0 SIIDIR STIIE 1 3 Setting up the ports and SIIREC BIT4 Clock Port P12 Internal clock Output External clock Data Output Port Data UO Port SI1REC P10 Data transmission only Output Data transmission reception i Output 3 wire Data transmission reception N channel open drain 2 wire output 4 Setting up output data e Write output data into SBUFI in the data transmission mode SII REC 0 5 Starting operation Set SIIRUN 6 Reading data after an interrupt e Read SBUFI SBUFI has been loaded with serial data from the data I O port even in the transmission mode e Clear SIIEND and exit interrupt processing Return to step 4 when repeating processing 3 7 4 2 Asynchronous serial transmission Mode 1 1 Setting the baudrate Setup SBRI 2 Setting the transmission mode e Set as follows SIIMO 1 SIIMI 0 SIIDIR SITE 1 3 Setting up the ports Data Output Port Data UO Port P10 P11 Data transmission reception 2 wire Output Input Data transmission reception 1 wire N channel open drain output 3 56 LC870G00 Chapter 3 4 Starting transmission Set SIIREC to 0 and write output data into SBUFI e Set SIIRUN Note Use the SIO1 data I O port P11 when using the SIO1 transmission only in mode 1
54. signal for the prescaler When this bit is set to 1 the count clock for TOL is an external input signal TOHCMP bit 3 TOH match flag This bit is set when the value of TOH matches the value of the match buffer register for TOH while TOH is running TOHRUN 1 and a match signal is generated Its state does not change if no match signal is generated Consequently this flag must be cleared with an instruction In the 16 bit mode TOLONG 1 a match needs to occur in all 16 bits of data for a match signal to generate TOHIE bit 2 TOH interrupt request enable control When this bit and TOHCMP are set to 1 an interrupt request to vector address 0023H is generated 3 27 E TOLCMP bit 1 TOL match flag This bit is set when the value of TOL matches the value of the match buffer register for TOL while TOL is running TOLRUN 1 and a match signal is generated Its state does not change if no match signal is generated Consequently this flag must be cleared with an instruction In the 16 bit mode TOLONG 1 a match needs to occur in all 16 bits of data for a match signal to generate TOLIE bit 0 TOL interrupt request enable control When this bit and TOLCMP are set to 1 an interrupt request to vector address 0013H is generated Notes TOHCMP and TOLCMP must be cleared to O with an instruction When the 16 bit mode is to be used TOLRUN and TOHRUN must be set to the same value to control operation TOLCMP and TO
55. tCYC transfer clocks Mode 1 Asynchronous serial I O half duplex 8 data bits 1 stop bit 8 to 2048 tCYC baudrates Mode 2 Bus mode 1 start bit 8 data bits 2 to 512 tCYC transfer clocks Mode 3 Bus mode 2 start detect 8 data bits stop detect MAD Converter e AD converter input port with 10x 20x amplifier 1channel e AD converter input port 7channel 12 8 bit resolution selectable AD converter eSelectable reference voltage source for an AD converter Selectable from VDD Internal Reference Voltage Generator Circuit V REF Mi internal Reference Voltage Generator Circuit VREF Generates 2 0V 4 0V for AD converter mm Comparator Comparator input pin 1 channel Comparator output pin 1 channel Comparator output set high when comparator input level lt 1 22V Comparator output set low when comparator input level gt 1 22V MH Clock Output Function e Generates clocks with a clock rate of 1 1 1 2 1 4 1 8 1 16 1 32 or 1 64 of the source oscillation clock that is selected as the system clock il Watchdog Timer e Generates an internal reset on an overflow occurring in the timer running on the low speed RC oscillator clock approx 30kHz or subclock Operating mode at standby is selectable from 3 modes continue counting suspend operation suspend counting with the count value retained 1 2 LC870G00 Chapter 1 Minterrupts e 15 sources 10 vectors 1 Provides three levels low L high H and highest X
56. the port 0 data latch PO FE40 is set to 1 In this case if POIE POFCR FE42 bit 4 is 1 the HOLD mode is released and an interrupt request to vector address 004BH is generated 3 Multiplexed pin Pin P06 also serves as the Timer PWMH output pin pin POS also serves as the system clock output pin Timerl PWML output pin pin P04 also serves as the VCPWM1 output pin pin P03 also serves as the VCPWMO output pin pins P02 to P04 as the AD input channel pins AN2 to AN4 pin P02 also serves as the comparator output pin and pins POO and DOT as AD input pin with a 10x 20x operational amplifier Address Initial value R W Name BIT7 BIT6 BIT5 BIT4 BITS BIT2 BIT1 BITO FE40 0000 0000 R W FIXO P06 P05 P04 P03 P02 PO1 P00 3 1 PORTS 3 1 3 Related Registers 3 1 3 1 Port 0 data latch PO 1 The port 0 data latch is an 8 bit register for controlling port 0 output data and port 0 interrupts Bit7 must always set to 0 2 When this register is read with an instruction data at pins POO to P06 is read in If PO FE40 is manipulated with an instruction NOT1 CLR1 SET1 DBZ DBNZ INC or DEC the contents of the register are referenced instead of the data at port pins The value of bit7 should be ignored 3 Port 0 data can always be read regardless of the I O state of the port Address Initial value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE40 0000 0000 R W PO FIXO P06 P05 P04 P03 P02 PO1 POO 3 1 3 2 Port
57. the value of the stack pointer SP Standard instructions NOP MOV ADD PC PC nb Unchanged nb Number of instruction bytes 2 3 Program Memory ROM This series of microcontrollers has a program memory space of 256K bytes but the size of the ROM that is actually incorporated in the microcontroller varies with the series of the microcontroller The ROM table lookup instruction LDC can be used to refer all ROM data within the bank Of the ROM space the 256 bytes in ROM bank 0 LC870A00 series 1F00H to 1FFFH are reserved as the option area Consequently this area is not available as a program area 2 4 Internal Data Memory RAM The LC870000 series microcontrollers has an internal data memory space of 64K bytes but the size of the RAM that is actually incorporated in the microcontroller varies with the series of the microcontroller 9 bits are used to access addresses 0000H to FDFFH of the 128K ROM space and 8 or 9 bits are used to access addresses FE00H to FFFFH The 9th bit of RAM is implemented by bit 1 of the PSW and can be read and written The 128 bytes of RAM from 0000H to 007FH are paired to form 64 2 byte and can also be used as 64 indirect address registers The bit length of these indirect registers is normally 16 bits 8 bits x 2 When they are used by the ROM table lookup instruction LDCW however their bit length is set to 17 bits 9 higher order bits 8 lower order bits As shown in Figure 2 4 1
58. to 1 Make sure that ADSTART is set to O before putting the microprocessor in the HALT or HOLD mode 3 8 4 2 AD mode register ADMRC 1 The AD mode selector register is an 8 bit register that controls AD converter operation mode Address Initial value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FES9 0000 0000 R W ADMRC ADMD4 ADMD3 ADMD2 ADMDI ADMDO ADMR2 ADTMI ADTMO ADMDA bit 7 Fixed bit Must always be set to 0 ADMDS bit 6 AD conversion mode control resolution switching This bit selects the AD converter s conversion mode between 12 bit AD conversion mode 0 and 8 bit AD conversion mode 1 If this bit is set to 1 the AD converter serves as an 8 bit AD converter The conversion results are placed only in the AD conversion results high byte register ADRHC the contents of the AD conversion results low byte register ADRLC remain unchanged If this bit is set to 0 the AD converter serves as a 12 bit AD converter The conversion results are placed in the AD conversion results high byte register ADRHC and the higher order 4 bits of AD conversion results low byte register ADRLC ADMD2 bit 5 Fixed bit Must always be set to 0 ADMD1 bit 4 Fixed bit Must always be set to 0 ADMDO bit 3 Fixed bit Must always be set to 0 3 65 ADC12 ADMR2 bit 2 Fixed bit Must always be set to 0 ADTM1 bit 1 AD conversion time control ADTMO bit 0 These bits and ADTM2 b
59. up resistor option RESET Figure 4 6 7 Sample Reset Circuit Configuration Using a CMOS Type Reset IC 4 37 Internal reset 2 When configuring the external POR circuit without using the internal reset circuit The internal POR is active at power on time even if the internal reset circuit is not used as in the case 1 in Subsection 4 6 7 When configuring an external POR circuit with a Cres value of 0 1uF or larger to obtain a longer reset period than with the internal POR however be sure to connect an external diode Dres as shown in Figure 4 6 8 Microcontroller Internal pull up resistor option RESET From POR Connect an external diode Figure 4 6 8 Sample External POR Circuit Configuration 4 38 LC870A00 Chapter 4 4 39 Appendixes Table of Contents Appendix l Special Functions Register SFR Map Appendix ll Port 0 Block Diagram Port 1 Block Diagram Port 7 Block Diagram LC870G00 APPENDIX I Address Initial Value R W LG870 0 Remarks B T8 BT7 B T6 B T5 B TA B T3 B T2 BTI B TO og OOFF XOX XXX R W RAMP56B 9 bits long FE00 0000 0000 RW AEG A La AS ARECb AREGi AEG AER AREGL FEOL 0000 0000 NW EEG BRE BES BRES BREGI BREG BRE BREGI BRED FE coco 0000 WW MG GEG GEC GEC MG GREG GREG aa MA OA A xcu ecce x ECKEN NEN GENE CENE RR E
60. voltage level of 1 67V only with the internal POR function When selecting an internal POR release level of 1 67V connect the external capacitor Cres furthermore when the disuse of the internal pull up resistor function is selected by option connect the pull up resistor Regs of the values that match the power supply s rise time to the RESET pin and make necessary adjustments so that the reset state is released after the release voltage exceeds the minimum guaranteed operating voltage Or set and hold the voltage level of the RESET pin at the low level until the release voltage exceeds the minimum guaranteed operating voltage When POR release level is 1 67V Min guaranteed operating voltage Reset VIH level Unknown state Figure 4 6 3 Sample Release Level Waveform in Internal POR Only Configuration 4 35 Internal reset 3 When temporary power interruption or voltage fluctuations shorter than several hundreds us are anticipated The response time measured from the time the LVD senses a power voltage drop at the option selected level till it generates a reset signal is defined as the minimum low voltage detection width TLVDW shown in Figure 4 6 4 see SANYO Semiconductor Data Sheet If temporary power interruption or power voltage fluctuations shorter than this minimum low voltage detection width are anticipated be sure to take preventive measures shown in Figure 4 6 5 or other necessary measures LVD r
61. 0 0000 RW 23CR S I NI3FEG INTILEG INI3F INISIE INI2FEG INT2LEG INT2IF INT2IE FESF 00000000 WW ISL STOP STOP BTML BMD BON NSE NON STON eeo MOREM AAA PAN RR RCM INGENII HERI fl MA PS ES EA i ee E AAA AA A EE on vs n v MAA lo A A HE AREAS A AE AA AA AA AA LESS e ruo ono punc AA AM to ts ERES o oo o qoo qo o o o po o po o o IO MES S D E EE EE RE EE E A p zu AA AE EE EE E E a a A E E FT O A ER AA E oup ceca EA dq cuo AAA E e re 5 TI og p p p p p RE EE STE a I Me e reo pg d 0 qq p p p END EA AAA EE A NAE DE UNE eee MENU a A AAA ARA AA AREA EECH e MEM HESS HEN AAA a E E E all A o le o Al A ERES II qo o qo o o po po IESO ISO E MES S ESI E E MAA ES MEA EP UA A AS Ms ll ET EISE RE ERR EC Se FE79 0000 0000 R W wO Tiner type watchdog tiner RSTFLG WIOGL VORN 10 P1 IDLCPO VOTSL2 VOTSLI wn LEA TOT gp og j pq p p p p EFEPAE ERE ESOO OEA SE A A A A S FE C 000000 WW ORs gt FRGEL FRCSTART omaes oe OCRGE3 ol SRCSEL SRCSTART ALA LC870G00 APPENDIX I Address Initial Value R W LC870G 0 Rerrarks B T8 BI T7 BI T6 B T4 B T3 B T2 BI Tl BI TO FE7D FE7E 0000 0000 FSRO FLASH control bit 4is R O FSROB7 FSROB6 FSWOK INH GH FSLDAT FSPG FSVRE Fix ETA 0 Fix oo 0 FEF 0000 0000 AW BTR Bsetime cotrd Sen EE as EE FEBI 00000000 R W V
62. 0000 0000 RW mar TBHU TIAN LOS TIMM HOP HE a ms 0000 0000 ww nmR E APR TIR HHRO TIR HE mua ms n 1 um nre n n um n ns mue FA 0000 0000 R nm mr Hb mw eis 0000 0000 R nu HW HH n5 mc 0000 0000 ww mn HUN HU TIAM rb 0000 0000 ww n e ne HHe nM AI 1 Address Initial Value R W LG870 0 Remarks B T8 BT7 B TO B T5 B TA B T3 B T2 BTI B TO FEIE EEE AE A AH E m ee I e eo I Hee AAA A AMA MESA enm p IE IESO p p P AAA NEN ASAS MAA FSE e AE ASAS RARAS A AR A o A ES HON AE ESOO ALO OO AAA AA AM OE res IESO IES IESO SO VERO IESO IESO IESO MO EOS FER esa ucc oo A O MES ASAS zx AE EA AS AE gt A A FA ST EA O E SS ISS ss SE sm so Sora mao iul STE P plug MES NN ee Lo p pn ERREUR ERR zin LC870G00 APPENDIX I Address Initial Value R W LG870 0 B T8 B 17 B T6 B T5 B TA B T3 B T2 BTI B TO EA lt ll AE A E A EEN 0000 000 WW PO Fm me pos Po Po Po POL RO 0000 0000 WW PR FIXO POSER POSER POMER POIIR POZLER POIDDR POOLE 000000 Rw PCR STP ruren POFLG POE AKEN ake aka TO eng FDO 0000 0000 0001 0100 0011 ras o mr ig pmo me o FEM Lmw m p
63. 1 0 0 32 1 1 0 1 64 1 1 1 0 128 1 1 1 1 256 3 40 LC870G00 Chapter 3 TILPRE bit 3 Controls the timer 1 prescaler low byte T1LPRC2 bit 2 Controls the timer 1 prescaler low byte TILPRCI1 bit 1 Controls the timer 1 prescaler low byte TILPRCO bit 0 Controls the timer 1 prescaler low byte TILPRE TILPRC2 TILPRC1 TILPRCO TIL Prescaler Count 0 z 1 1 0 0 0 2 1 0 0 1 4 1 0 1 0 8 1 0 1 1 16 1 1 0 0 32 1 1 0 1 64 1 1 1 0 128 1 1 1 1 256 3 5 4 3 Timer 1 low byte T1L 1 This is a read only 8 bit timer It counts up on every TIL prescaler output clock Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FEIA 0000 0000 R TIL TIL7 TIL6 TILS TIL4 TIL3 TIL2 TIL1 TILO 3 5 4 4 Timer 1 high byte T1H 1 This is a read only 8 bit timer It counts up on every T1H prescaler output clock Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FEIB 0000 0000 R TIH T1H7 T1H6 T1H5 T1H4 T1H3 T1H2 TIHI TIHO 3 5 4 5 Timer 1 match data register low byte T1LR 1 This register is used to store the match data for TIL It has an 8 bit match buffer register A match signal is generated when the value of this match buffer register coincides with the value of timer 1 low byte 2 Match buffer register is updated as fo
64. 1 XT1 output data when OCR register sets CF1 XT1 and CF2 XT2 to the general purpose input output mode Register Data CF1 XT1 State XT1DT XT1DR Input Output O Enabled Open er RR When general purpose input output mode is selected See Figure 4 2 4 2 Oscillation Control Register for details XTCFSEL bit 3 CF1 XT1 and CF2 XT2 input control This bit and EXTOSC OCR register bit 6 and CFSTOP OCR register bit 0 are used to select the function of the CF1 XT1 and CF2 XT2 pins between main clock subclock and general purpose input output port pins See 4 2 4 2 Oscillation control register for details XT2CMOS bit 2 CF2 XT2 output mode This bit controls the CF2 XT2 output mode when OCR register sets CF1 XT1 and CF2 XT2 to the general purpose input output mode and CF2 XT2 is set to the output mode XT2DR 1 1 When this bit is set to 0 CF2 XT2 output mode is set to N channel open drain 2 When this bit is set to 1 CF2 XT2 output mode is set to CMOS XT2DR bit 1 CF2 XT2 data direction This bit controls the CF2 XT2 input output direction when OCR register sets CF1 XT1 and CF2 XT2 to the general purpose input output mode 1 When this bit is set to 0 CF2 XT2 is set to the input mode 2 When this bit is set to 1 CF2 XT2 is set to the output mode XT2DT bit 0 CF2 XT2 data latch This bit controls the CF2 XT2 output data when OCR register sets CF1 XT1 and CF2 XT2 to the general purpose input output
65. 17 is assigned to INT1 and used to detect the low level high level low edge or high edge of the interrupt signal and sets the corresponding interrupt flag Pl and P15 are assigned to INT2 and INT3 respectively and used to detect the low edge high edge or both edges of the interrupt signal and set the corresponding interrupt flag A port INT4 selected out of P13 and P14 are used to detect the low edge high edge or both edges of the interrupt signal and sets the corresponding interrupt flag Timer 0 count input function A count signal is sent to timer 0 each time a signal change such that the interrupt flag is set is supplied to the port selected from P16 and P15 Timer OL capture input function A timer OL capture signal is generated each time a signal change such that the interrupt flag is set is supplied to the port selected from P70 P16 P14 and P13 When a selected level of signal is input to P70 that is specified for level triggered interrupts a timer OL capture signal is generated at cycle interval Timer OH capture input function A timer OH capture signal is generated each time a signal change such that the interrupt flag is set is supplied to the port selected from P17 P15 P14 and P13 When a selected level of signal is input to P17 that is specified for level triggered interrupts a timer OH capture signal is generated at 1 cycle interval This continues while the input is present Timer count input fu
66. 2 0V 4 0V or External input No OWPO 1 0 On chip debugger pin No Port 0 1 0 O 7 bit UO port Yes P00 to POS O I O specifiable in 1 bit units Pull up resistors can be turned on and off in 1 bit units e Pin functions POO ANO PO1 AN1 AD converter input port with 10x 20x operational amplifier PO2 AD converter input port AN2 Comparator input CPIM P03 AD converter input port AN3 VOPWMO output P04 AD converter input port AN4 VCPWM1 output P05 Timer 1 PWML output System clock output PO6 Timer 1 PWMH output P07 On chip debugger pin OWPO Port 1 1 0 8 bit I O port Yes P10 to P15 VO specifiable in 1 bit units l SCH Pull up resistors can be turned on and off in 1 bit units e Pin functions P10 SIO1 data output P11 SIO1 data input bus input output P12 SIO1 clock input output P13 INT4 input HOLD release input timer 1 event input timer OL capture input timer OH capture input AD converter input port AN7 P14 INT4 input HOLD release input timer 1 event input timer OL capture input timer OH capture input AD converter input port AN6 P15 INT3 input with noise filter timer O event input timer OH capture input AD converter input port AN5 P16 INT2 input HOLD release input timer O event input timer OL capture input HPWM2 output P17 beeper output INT1 input HOLD release input timer OH capture input HPWM2 output Interrupt acknowledge type Rising amp Rising
67. 2 Reference Voltage 2 0V Adjustment Register VR2AJ The reference voltage 2 0V adjustment register is used to adjust the VREF2 0V level Address Initial value R W Name BIT7 BIT6 BIT5 BIT4 BITS BIT2 BIT1 BITO FECI XXXX XXXX R W VR2AJ VR2AJ7 VR2AJ6 VR2AJ5 VR2AJ4 VR2AJ3 VR2AJ2 VR2AJ1 VR2AJO No access must be made to this register 3 9 3 3 Analog Input Port Control Register ANIEZ The ANIEZ register is used to disable the digital input function of AD converter input ports The leak current through the transistor of the digital input circuit of ports can be surpressed and AD conversion can be done on less noise condition Address Initial value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FEC2 0000 0000 R W ANIEZ ANIGIEZ ANI2IEZ ANI1IEZ ANIOIEZ AN9IEZ AN7IEZ ANGIEZ ANSIEZ AN13IEZ bit 7 Test bit Must always be set to 0 AN12IEZ bit 6 Test bit Must always be set to 0 AN11IEZ bit 5 Test bit Must always be set to 0 AN10IEZ bit 4 Test bit Must always be set to 0 AN9IEZ bit 3 Analog input P70 ANO9 port digital input function disable control When P70 ANO is used as an analog input this bit should be set to 1 When P70 ANO is not used as an analog input this bit must be set to 0 ANTIEZ bit 2 Analog input P13 AN7 port digital input function disable control When P13 AN7 is used as an analog input this bit should be set to 1 When P13 AN7 is not used as an analog i
68. 22 3 4 3 3 4 3 1 D 3 4 3 2 D 3 4 3 3 1 2 3 4 3 4 3 4 1 2 3 4 3 4 3 5 1 2 3 4 3 4 3 6 LC870G00 Chapter 3 Circuit Configuration Timer counter 0 control register TOCNT 8 bit register This register controls the operation and interrupts of TOL and TOH Programmable prescaler match register TOPRR 8 bit register This register stores the match data for the programmable prescaler Programmable prescaler 8 bit counter Start stop This register runs in modes other than the HOLD mode Count clock Cycle clock period 1 Tcyc Match signal A match signal is generated when the count value matches the value of register TOPRR period 1 to 256 Tcyc Reset The counter starts counting from 0 when a match signal occurs or when data is written into TOPRR Timer counter 0 low byte TOL 8 bit counter Start stop This counter is started and stopped by the 0 1 value of TOLRUN timer 0 control register bit 6 Count clock Either prescaler s match signal or external signal must be selected through the 0 1 value of TOLEXT timer 0 control register bit 4 Match signal A match signal is generated when the count value matches the value of the match buffer register 16 bits of data need to match in the 16 bit mode Reset This counter is reset when it stops operation or a match signal is generated Timer counter 0 high byte TOH 8 bit counter Start stop This counter is start
69. 2AH HPWM2AL bits 7 to 6 value 005h HPWV2AH HPWM2AL bits 7 to 6 value 006h HPWV2AH HPWNM2AL bits7 to 6 value 007h HPvW2AH HPWM2AL bits 7 to 6 value 3FFh fundamental period 256 x period set by HPWV2AC bits 6 to 5 overall period fundamental period x 4 high puls width HPWM2AH HPWV2AL bits 7 to 6 x period set by HPWV2AC bits 6to 5 Figure 3 11 3 Examples of waveform of the 10 bit PWM mode H2ABWSL 1 3 86 LC870G00 Chapter 3 3 11 4 Related Registers 3 11 4 1 HPWM2 control register HPWM2AC 1 The HPWM2 control register controls the operation of the internal high speed RC and the operation and interrupts of HPWM2 2 H2ARLBSY HPWM2AC bit2 is read only bit Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE8D 0000 0000 R W HPWM2AC H2A40MON H2ACKDV H2ACKSL H2ABWSL H2ARUN H2ARLBSY H2AOVF H2AIE H2A40MON bit 7 Internal high sped RC 40MHz oscillation control e Setting this bit to 0 stops the oscillation of the internal high speed RC 40MHz oscillator circuit e Setting this bit to 1 starts the oscillation of the internal high speed RC 40MHz oscillator circuit H2ACKDV bit 6 HPWM 2 clock divider control When this bit is set to 1 the 1 1 division of the clock selected by H2ACKSL is used When this bit is set to O the 1 2 division of the clock selected by H2ACKSL is used H2ACKSL bit 5 HPWM2 clock select H2ACKSL HPWN
70. 3 ADCR3 bit 3 Fixed bit Must always be set to 0 ADSTART bit 2 AD conversion control Starts 1 or stops 0 AD conversion processing Setting this bit to 1 starts AD conversion The bit is reset automatically when the AD conversion ends The time specified by the conversion time control register 1s required to complete the conversion The conversion time is defined using three bits i e the ADTM2 bit bit 0 of the AD conversion result register low byte ADRLC and the ADTM1 bit 1 and ADTMO bit 0 of the AD mode register ADMRC Setting this bit to 0 stops the AD conversion No correct conversion results can be obtained if this bit is cleared when AD conversion is in progress Never clear this bit while the AD conversion processing is in progress ADENDF bit 1 End of AD conversion flag This bit identifies the end of an AD conversion operation It is set when the AD conversion is finished Then an interrupt request to vector address 0043H is generated if ADIE is set to 1 If ADENDF is set to 0 it indicates that no AD conversion operation is in progress This flag must be cleared with an instruction ADIE bit 0 AD conversion interrupt request enable control An interrupt request to vector address 0043H is generated when this bit and ADENDF are set to 1 Notes e It is inhibited to set ADCHSEL3 to ADCHSELO to a value 1000 and from 1010 to 1110 Do not place the microprocessor in the HALT or HOLD mode with ADSTART set
71. 3 D4TH2 D4TH1 D4THO 3 12 5 Example of Using Temperature sensor 1 Setting of the temperature sensor e Write 80h to TEMPS2CNT and the operation of temperature sensor starts If the automatic turning on off function of the temperature sensor is used this writing is not necessary 2 Setting of the AD converter Write to ADMRC and ADRLC setup the appropriate AD conversion time Write FAh F5h Interrupt request enable disable to ADCRC connect the output of the temperature sensor to the input of AD conveter start AD conversion 3 Detection of the temperaturer After the end of AD conversion calculate the temperature value using the AD conversion data in ADRLC ADRHC and the reference temperature sensor data at 60 C stored in D2TL D2TH D4TL D4TH 3 03 LC870G00 Chapter 4 4 Control Functions 4 1 Interrupt Function 4 1 1 Overview This series of microcontrollers has the capabilities to control three levels of multiple interrupts i e low level L high level H and highest level X The master interrupt enable resister and interrupt priority control register are used and enable or disable interrupts and determine the priority of interrupts 4 1 2 Functions 1 Interrupt processing e Peripheral modules generate an interrupt request to the predetermined vector address when the interrupt request and interrupt request enable flags are set to 1 e When the microcontroller receives an interrupt request from a
72. 7 to 4 of VCPWMOL VCPWMO compare register H VCPWMOH 8 bit register The VCPWMO compare register H controls the fundamental pulse width of VCPWMO When bits 7 to 4 of VCPWMOL are all fixed at 0 VCPWMO can serve as period programmable 8 bit PWM that is controlled by VCPWMOH VCPWM1 compare register L VCPWM1L 4 bit register The VCPWM1 compare register L controls the additional pulses of VCPWMI VCPWMIL is assigned bits 7 to 4 and all of its lower order 4 bits are apparently set to 1 when it is read When the VCPWMI control bit VCPWMOC FE84 bit 3 is set to 0 the output of VCPWMI ternary can be controlled using bits 7 to 4 of VCPWMIL VCPWM compare register H VCPWM1H 8 bit register The VCPWMI I compare register H controls the fundamental pulse width of VCPWMI When bits 7 to 4 of VCPWMIL are all fixed at 0 VCPWMI can serve as period programmable 8 bit PWM that is controlled by VCPWMIH VCPWM01 port input register VCPWMO1P 2 bit register This register controls the waveform and the output buffer of VCPWMO This register controls the waveform and the output buffer of VCPWMI 3 76 System clock Match Comparator Match buffer register Reload VCPWMO compare register H VCPWMOH LC870G00 Chapter 3 VCPWMO 1 R fundamental wave Clock Clear period generation counter Match Comparator Fundamental period Match buffer match data register VCPWMOC7 4
73. C oscillator circuits have built in resistors and capacitors so that no external circuits are required The system clock can be selected from these five types of clock sources under program control 4 2 2 Functions 1 System clock select Allows the system clock to be selected under program control from five types of clocks generated by the main clock oscillator subclock oscillator low medium and high speed RC oscillators 2 System clock frequency division Divides frequency of the oscillator clock selected as the system clock and supplies the resultant clock to the system as the system clock The frequency divider circuit is made up of two stages S ech 1 The first stage allows the selection of division ratios of A and 1 1l The second stage allows the selection of division ratios of GA uu Lo and 3 Oscillator circuit control Allows the start stop control of the five systems of oscillators to be executed independently through microcontroller instructions The main clock and subclock oscillator circuits share pins CF1 XT1 and CF2 XT2 and cannot be used at the same time 4 Multiplexed input output pin function The CF oscillation crystal oscillation pins CF1 XT1 and CF2 XT2 can also be used as general purpose input output ports 5 Oscillator circuit states and operating modes Low speed Mode Clock Main Clock Sub clock RC Oscillator Note 1 Medium speed High speed RC RC Oscillat
74. CLKDVO Bits 7 to 3 These bits do not exist They are always read as 1 CLKDV2 bit 2 CLKDVI bit 1 Define the division ratio of the system clock CLKDVO bit 0 CLKDV2 CLKDV1 CLKDVO Division Ratio 0 0 0 0 0 1 5 0 1 0 1 0 1 1 1 0 0 1 0 1 gt 1 1 0 1 1 1 4 14 LC870G00 Chapter 4 4 3 Standby Function 4 3 1 Overview This series of microcontrollers supports three standby modes called the HALT HOLD and X tal HOLD modes that are used to reduce current consumption at power failure time or in program standby mode In a standby mode the execution of all instructions is suspended 4 3 2 Functions 1 HALT mode The microcontroller suspends the execution of instructions but its peripheral circuits continue processing certain serial transfer functions are stopped Note 1 The HALT mode is entered by setting bit 0 of the PCON register to 1 e Bit 0 of the PCON register is cleared and the microcontroller returns to the normal operating mode when a reset occurs or an interrupt request is accepted 2 HOLD mode e All oscillations are suspended The microcontroller suspends the execution of instructions and its peripheral circuits stop processing Notes 1 2 The HOLD mode is entered by setting bit 1 of the PCON register to 1 when bit 2 is set to O In this case bit O of the PCON register HALT mode flag is automatically set When areset occurs or a HO
75. CMOS 8 BIT MICROCONTROLLER LC870G00 SERIES USER S MANUAL ECH REV 1 00 ON Semiconductor Digital Solution Division Microcontroller amp Flash Business Unit ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries LLC SCILLC or its subsidiaries in the United States and or other countries SCILLC owns the rights to a number of patents trademarks copyrights trade secrets and other intellectual property A listing of SCILLC s product patent coverage may be accessed at www onsemi com site pdf Patent Marking pdf SCILLC reserves the right to make changes without further notice to any products herein SCILLC makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does SCILLC assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation special consequential or incidental damages Typical parameters which may be provided in SCILLC data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts SCILLC does not convey any license under its patent rights nor the rights of others SCILLC products are not designed intended or authorized for use as components i
76. CP24 225nhl Lead Hal ogen f ree Type SSOP24 NAME SSOP24 NAME 1 P70 INTO TOLCP ANO9 13 P16 INT2 TOIN CPOUT HPWM2 2 RES 14 P17 BUZ INT1 TOHCP HPWM2 3 Vss1 15 Vss2 4 CF1 XT1 16 VREF 5 CF2 XT2 17 POO APIM 6 Von 18 PO1 APIP 7 P10 SO1 19 P02 AN2 CPIM 8 P11 SH SB1 20 P03 AN3 VCPW MO 9 P12 SCK1 21 P04 AN4 VCPWM1 10 P13 INT4 T1IN AN7 22 P05 T1PWML CKO 11 P14 INT4 T1IN ANG 23 P06 T1PWMH 12 P15 INT3 TOIN AN5 24 OWPO LC870G00 Chapter 1 1 4 System Block Diagram Interrupt control IR PLA Standby control Flash ROM a 5 low speed RC S 9 medium speed RC S PC O High speed RC ACC WDT low speed RC B register Reset control lii Reset circuit O0 LVD POR C register SIO1 i gt Bus interface ALU Timer1 wh e Port1 PSW Base timer D RAR RAM HPWM2 gt VCPWM 11 High speed RC2 Port7 Stack pointer Ju ji INTO 4 INT3 with Noise filter On chip debugger ADC 10x 20x amplifier f t 1 channel Vref gt Comparator 1 7 1 5 Pin Description Pin Name 1 0 Description Option Vss1 power supply pin No Vpp1 D power supply pin No Vss2 e power supply pin No VREF 1 0 Reference voltage output
77. EF2 0V 4 0V generator adjusts the voltage level and controls the operation of the operational amplifier with a gain of 10x 20x operation the comparator and disable the digital input function of AD converter input ports 3 9 2 Functions 1 The VRCNT register is used to control the operation of the reference voltage VREF2 0V 4 0V generator and the comparator 2 The VR2AJ register is used to adjust the VREF2 0V level 3 The ANIEZ register is used to disable the digital input function of AD converter input ports 4 The APCNT register is used to control the operation of the operational amplifier with a gain of 10x 20x 5 The VR4AJ register is used to adjust the VREF4 0V level co eornm mw vrenr veros venon cron East recs vona mooo ww arent aron cama L arvin aru arbo 3 9 3 Related Registers 3 9 3 1 Reference voltage control register VRCNT 1 Thereference voltage control register is an 8 bit register that controls the generation of the reference voltage VREF and the operation of the 10x 20x operational amplifier Address Initial value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FECO 000H HH00 R W VRCNT VRI2ON VR240N CPON VRADSEL VR2SELZ VR120N bit 7 VREF12 operation control Setting VR12ON to 0 stops operation of VREFI2V circuit block Setting VR12ON to 1 starts operation of VREF12V circuit block See Fig 3 9 2 for VREF12V circuit block
78. FE02H and off has a value of 7EH 2 for example the A register FE02H 2 FEOOH is designated Examples When RO contains 123H RAM address 0 23H RAM address 1 01H LD 10H Transfers the contents of RAM address 133H to the accumulator L1 STW 10H Transfers the contents of the BA register pair to RAM address 133H PUSH 10H Saves the contents of RAM address 133H in the stack SUB 10H Subtracts the contents of RAM address 133H from the accumulator DBZ 10H L1 Decrements the contents of RAM address 133H by and causes a branch if Zero Notes on this addressing mode The internal data memory space is divided into three closed functional areas as explained in Section 2 1 namely 1 system reserved area FFOOH to FFFFH 2 SFR area FEOOH to FEFFH and 3 RAM stack area 0000H to FDFFH Consequently it is disallowed to point to a different area using an offset value from the basic area designated by the contents of RO For example if the instruction LD 1 is executed when RO contains OFDFFH since the basic area is 3 RAM stack area 0000H to FDFFH the intended address OFDFFH 1 OFEOOH lies outside the basic area and OFFH is placed in the ACC as the results of LD If the instruction LD 2 is executed when RO contains OFEFFH since the basic area is 2 SFR FEOOH to FEFFH the intended address FEFFH 2 OFFO1H lies outside the basic area In this case since SFR is confined in an 8 bit addres
79. Falling H level L level Falling INT1 enable enable disable enable enable INT2 enable enable enable disable disable INT3 enable enable enable disable disable INT4 enable enable enable disable disable Continued on next page 1 8 LC870G00 Chapter 1 Continued from preceding page Port 7 1 0 O 1 bit I O port No P70 O I O specifiable O Pull up resistors can be turned on and off e Pin functions P70 INTO input HOLD release input timer OL capture input AD converter input port AN9 Interrupt acknowledge type a Rising amp Rising Falling H level L level Falling INTO enable enable disable enable enable RES l External reset input internal reset output pin Yes Internal pullup ON OFF CF1 XT1 1 0 e Ceramic oscillator 32 768kHz crystal oscillator input pin No e Pin functions O 1 bit UO port O UO specifiable only Nch open drain CF2 XT2 1 0 e Ceramic oscillator 32 768kHz crystal oscillator output pin No e Pin functions 1 bit UO port O UO specifiable OWPO 1 0 On chip debugger pin No 1 9 1 6 On chip Debugger Pin Connection Requirements For the treatment of the on chip debugger pins refer to the separately available documents entitled Rd87 On chip Debugger Installation Manual 1 7 Recommended Unused Pin Connections Recommended Unused Pin Connections Port Name Board Software POO to P07 O
80. GDDR 1 Value of port data latch P06 0 Timer 1 PWMH data Inversion of the above 0 3 2 LC870G00 Chapter 3 T1LPWMEN bit 6 timer 1 PWML output control When POS is placed in the output mode POSDDR 1 the EOR of OR of AND of this bit and timer 1 PWML output and the system clock and port data latch is placed at pin POS TILPWMEN CLKOEN P05 POS Pin Data in Output Mode POSDDR 1 Value of port data latch POS The system clock Inversion of the above POFLG bit 5 PO interrupt source flag This flag is set when a low level is applied to a port O pin specified as input and the corresponding PO FE40 bit is set A HOLD mode release signal and an interrupt request to vector address 004BH are generated when both this bit and the interrupt request enable bit POIE are set to 1 This bit must be cleared with an instruction as it is not cleared automatically POIE bit 4 PO interrupt request enable Setting this bit and POFLG to 1 generates a HOLD mode release signal and an interrupt request to vector address 004BH CLKOEN bit 3 This bit controls the output data of pin PO5 This bit is disabled when POS is in the input mode When POS is in the output mode POS outputs data as summarized in the above table CKODV2 bit 2 CKODV1 bit 1 CKODVO bit 0 These bits define the frequency of the system clock to be placed at POS 000 Frequency of source oscillator selected as sy
81. H EE dil e Ma Reset period E nm icc AE 1 D 1 WI ts E PET SE Reset period D Reset period xy p A R 1 p i Unknown state LVUKS There also exists an unknown state LVUKS before the POR transistor starts functioning normally when both POR and LVD functions are used Resets are generated both when power is turned on and when the power level lowers The reset release voltage and entry voltage in this case may have some range Refer to the latest SANYO Semiconductor Data Sheet for details A hysteresis width LVHYS is provided to prevent the repetitions of reset release and entry cycles near the detection level 4 34 LC870A00 Chapter 4 4 6 6 Notes on the Use of the Internal Reset Circuit 1 When generating resets only with the POR function When generating resets using only the POR function do not short the RESET pin directly to VDD as when using it with the LVD function Be sure to use an external capacitor Crgs of an appropriate capacitance When the disuse of the internal pull up resistor function is selected by option be sure to use a pull up resistor Rggs Test the circuit intensively under the anticipated power supply conditions to verify that resets are reliably generated Microcontroller Internal pull up resistor option Rres RESET From POR Figure 4 6 2 Reset Circuit Configuration Using Only the Internal POR Function 2 When selecting a release
82. H is inactive If T1H is active the TIPWMH output is fixed at the low level when TIHR FFH The timer 1 high byte output is a toggle output whose state changes on a TIH match signal when TIPWM 0 or TILONG 1 When TIPWM 1 and TILONG 0 this PWM output is cleared on a T1H overflow and set on a TIH match signal 3 36 LC870G00 Chapter 3 Clock 2Tcyc gt T1H prescaler T1PWML output Clock 2Tcyc gt or external events Set in 145CR FE4Ah 145SL FE4Bh registers T1L prescaler Invert TIPWMH output Match buffer register Match buffer register Reload Reload e NN TILR TILCMP T1HR T1HCMP flag set flag set a 8 bit programmable timer gt 4 8 bit programmable timer gt Figure 3 5 1 Mode 0 T1LONG 0 T1PWM 0 Block Diagram Clock 1Tcyc gt T1L prescaler Clock 1Tcyc gt T1H prescaler Overflow Reset Overflow T1PWML output Set Reset T1PWMH output Set Match buffer register Match buffer register Reload Y e Reload TILCMP TIHCMP e 8 bit PWM d 8 bit PWM Figure 3 5 2 Mode 1 T1LONG 0 T1PWM 1 Block Diagram Clock 2Tcyc TiL prescaler or external events Set in 1450R FE4Ah 145SL FE4Bh registers Clear TIL Match buffer register Invert T1PWMH output Invert T1PWML output Match buffer register e Reload e Reload T4LR LE LCMP TIHR T1HCMP ag
83. HCMP are set at the same time in the 16 bit mode 3 4 4 2 Timer 0 programmable prescaler match register TOPRR 1 Timer 0 programmable prescaler match register is an 8 bit register that is used to define the clock period Tpr of timer counter 0 2 The count value of the prescaler starts at 0 when TOPRR is loaded with data 3 Tpr TOPRR 1 x Tcyc Tcyc Period of cycle clock Address Initial value R W Name BIT7 BIT6 BIT5 BIT4 BITS BIT2 BIT1 BITO FE11 0000 0000 R W TOPRR TOPRR7 TOPRR6 TOPRRS TOPRR4 TOPRR3 TOPRR2 TOPRRI TOPRRO 3 4 88 Timer counter 0 low byte TOL 1 This is a read only 8 bit timer counter It counts the number of match signals from the prescaler or external signals Address Initial value R W Name BIT7 BIT6 BITS BIT4 BITS BIT2 BIT1 BITO FE12 0000 0000 R TOL TOL7 TOL6 TOLS TOL4 TOL3 TOL2 TOL1 TOLO 3 4 4 4 Timer counter 0 high byte TOH 1 This is a read only 8 bit timer counter It counts the number of match signals from the prescaler or overflows occurring TOL Address Initial value R W Name BIT7 BIT6 BIT5 BIT4 BITS BIT2 BIT1 BITO FE13 0000 0000 R TOH TOH7 TOH6 TOHS TOH4 TOH3 TOH2 TOHI TOHO 3 4 4 5 Timer counter 0 match data register low byte TOLR 1 This register is used to store the match data for TOL It has an 8 bit match buffer register A match signal is generated when the value of this match buffer register coincides with the lower order byte of t
84. IT1 BITO FESF 0000 0000 R W ISL STOHCP STOLCP BTIMCI BTIMCO BUZON NFSEL NFON STOIN STOHCP bit 7 Timer OH capture signal input port select STOLCP bit 6 Timer OL capture signal input port select These 2 bits have nothing to do with the control function on the base timer BTIMC1 bit 5 Base timer clock select BTIMCO bit 4 Base timer clock select BTIMC1 BTIMCO Base Timer Input Clock 0 Subclock Cycle clock 0 a a a 1 0 JLowspeedRCoscilaionclok 3 49 BT BUZON bit 3 Buzzer output enable This bit enables data buzzer output to be transferred to port P17 when P17FCR P1FCR bit7 is set to 1 and PI7H2ASL HPWMAAL bit 1 is set to O When this bit is set to 1 a signal that is obtained by dividing the base timer clock is sent to port P17 as buzzer output When this bit is set to 0 the buzzer output is held low and it is sent to port P17 NFSEL bit 2 Noise filter time constant select NFON bit 1 Noise filter time constant select STOIN bit 0 Timer 0 counter clock input port select These 3 bits have nothing to do with the control function on the base timer 3 50 LC870G00 Chapter 3 3 7 Serial Interface 1 SIO1 3 7 1 Overview The serial interface SIO1 incorporated in this series of microcontrollers provides the following four functions 1 Mode 0 Synchronous 8 bit serial I O 2 or 3 wire system clock rates of 2 to 512 Tcyc 2 Mode 1 Asynchronous serial I O Half d
85. LD mode release signal INTO INT1 INT2 INT4 and port 0 interrupt occurs bit 1 of the PCON register is cleared and the microcontroller switches into the HALT mode 3 X tal HOLD mode e All clock oscillations except that of the subclock are stopped If however the base timer has been started with low speed RC oscillation selected as the base timer input clock source the low speed RC oscillation circuit retains the state that is established when the X tal HOLD mode is entered The execution of instructions and the operation of the peripheral circuits except the base timer are suspended Notes 1 and 2 The X tal HOLD mode is entered by setting bit 1 of the PCON register to 1 when bit 2 is set to 1 In this case bit O of the PCON register HALT mode flag is automatically set When areset occurs or a HOLD mode release signal INTO INT1 INT2 INT4 and port 0 interrupt occurs bit 1 of the PCON register is cleared and the microcontroller switches into the HALT mode Note 1 The oscillation of the low speed RC oscillation circuit is controlled directly by the watchdog timer Its oscillation is also controlled in the standby mode See Section 4 6 Watchdog Timer for details Note 2 Do not allow the microcontroller to enter into the HOLD or X tal HOLD mode while AD conversion is in progress Make sure that ADSTART ADCRC register bit 2 is set to O before placing the microcontroller into one of the above mentioned standby modes
86. MEME M5 A a mar pen A RU RE PEPA o e ee FEOS 0000 0000 RW Pw C AC PS5 PSVPA LOK o Pl PARTY FEO7 HH ooo NW PON 0 DE PN IDE FEOS 0000 oo WW IE IE LG HG EG XT xam F9 0000 0000 WW IP S PB PAB IPB IP23 IP2B IP23 IPIB IPIS FEOA 00000000 WW see S7 SP S5 spa sa Se SP SO FEB 0000 0000 RW SH SP5 SP SPD P SPM sio S9 SP FEC Hoo WW ol 8 j AK a aw FEOE 00000900 Ww OR omrenixrexiat tits2ad3 aksa EXEC GKCE5 OKA ONT XUN ROTO FSE EM AN EE Gem EA RERUMS CENE TE O O FEA EIER mu 0000 0000 ww TEN OA TAN TOL TQEX TG THE 7109 TUE re coon ooo wW Tem rae os ng mcer Torey OPA rors Tona Toma Torta TER TOPR LE exo Rara ar as Tus mua Tus to Tii Too res wa 78 88 ee ms 796 m amp ms me mt 00 tid 0000 0000 yw TUR OLA TOS TOS TOUR TOLRS oe 70 eis 0000 0000 ww TUR o TO TOH6 10 84 TOE TOR TO ms WOK WOK R TOOL timer O capture register L TOONT TOCALS TOONS TOCALA TOONS TOCAL2 TOOL Le wem R TOW Tm o capture register H WORT Toons Taos Toon Toote Tuc ris
87. MP TILIE FEIA 0000 0000 R TIL TIL7 TIL6 TILS TIL4 TIL3 TIL2 TILI TILO FEIB 0000 0000 R TIH T1H7 T1H6 T1H5 T1H4 T1H3 T1H2 TIH1 T1HO FEIC 0000 0000 R W TILR TILR7 TILR6 TILRS TILR4 TILR3 TILR2 TILRI TILRO FEID 00000000 R W TIHR TIHR7 TIHR6 TIHR5 TIHR4 TIHR3 TIHR2 TIHRI TIHRO FE19 0000 0000 R W TIPRR TIHPRE TIHPRC2 TIHPRCI TIHPRCO TILPRE TILPRC2 TILPRCI TILPRCO Note 1 The output of the TIPWML is fixed at the high level if the TIL is stopped If the TIL is running the output of the TIPWML is fixed at the low level when TILR FFH The output of TIPWMH is fixed at the high level if the T1H is stopped If the T1H is running the output of the TIPWMH is fixed at the low level when TIHR FFH 3 33 Circuit Configuration Timer 1 control register T1CNT 8 bit register 1 The timer 1 control register controls the operation and interrupts of the TIL and T1H Timer 1 prescaler control register T1PRR 8 bit counter 1 This register sets the clocks for TIL and T1H Timer 1 prescaler low byte 8 bit counter 1 Start stop The start stop of timer 1 prescaler low byte is controlled by the 0 1 value of TILRUN timer 1 control register bit 6 2 Count clock Varies with the operating mode Mode T1LONG T1PWM T1L Prescaler Count Clock 0 0 0 2 Tcyc events Note 1 1 0 1 1 Tcyc Note 2 2 1 0 2 Tcyc events Note 1 3 1 1 1 Teyc Note 2
88. OWWH voltage control m CPNORT CIO ower VIA CANOES CNO own eweg FE 0000 HHH AW VOPWAL voltage contro pum FE amp 00000000 WW VOPWIH voltage control pwa CWMIHT CAES AS OMA OVAS OVER COMMIT CANAD Fee 00000000 AW VOPWOC voltage control m CPWBOCT PWG owes VIGA ENCPV ENPO CPVW00V owes FES HED 0000 wW vwo voltage control pum omo ome osx mx roo EE H gh speed PWM H gh speed PVM H gh speed PWM Address Initial Value R W LC870G 00 B T2 B T1 goce NUR FEAT 00000990 HW RST Freeney couter cor REFGSI REFOGD SELFROL SELFRED FROFSTI FRELIST FREED crensmo Ee ET EE EE ES IN HS E EE E EE FEAA EX OE AA ARA fs ea ERES EH FEBS OK WOK NW FRAO ArT E enen NW irem H gh spend RE trima register 1 FSO po ale I on EIER E RE O SL AI 6 LC870G00 APPENDIX I Address Initial Value R W LG870 0 Remarks B T8 BT7 B TO B T5 B TA B T3 B T2 BTI B TO AAA DERE EE M S E REEL VN VREF control o i VO wer2avajust E APO ss PWR PWM RC tri ming register o FG RHO WW ca Pwa trino NL FE Xexxex WT Wa wervsut r FEED FEE EZ AE Es MEN pa E FEDA OOH HDO woe Temperature sensor control
89. PWM 1DPO CDPWM1CPO PU PO FE40 bit3 CMOS Nch OD C POS z Special input FE41 bit3 Q Ww Wa E CDPWMODPO CDPWMOCPO O Y We H PO FE40 bit2 O si s or Pin E P02 to POO FE41 bit2 O Special inp t EI I C d Table of Port 0 Shared Function ENU SUIT NN Po4 AN4 vcew Oupt Output P03 AN3 VERMO Output P02 AN2 comparator inp E WE 10x 20x amplifier side Ge POO APIM 10x 20x amplifier side inp Port 0 Block Diagram P04 to POO Option Output type CMOS or N channel OD selectable on a bit basis AII 2 PO FE40 bit 7 PODDR FE41 bit 7 P07 pin input data PO FE40 bit 6 PODDR FE41 bit 6 P06 pin input data PO FE40 bit 5 PODDR FE41 bit 5 P05 pin input data PO FE40 bit 4 PODDR FE41 bit 4 P04 pin input data PO FE40 bit 3 PODDR FE41 bit 3 P03 pin input data PO FE40 bit 2 PODDR FE41 bit 2 PO FE40 bit 1 PODDR FE41 bit 1 P01 pin input data PO FE40 bit 0 PODDR FE41 bit 0 POO pin input data POFCR FE42 LC870G00 APPENDIX II PO interrupt detect PO interrupt detect Port O nterrupt Block Diagram AII 3 Port Block Diagrams P17HPWSEL HPWM2 output BUZON E BUZ output P1FCR FE46 bit7 Bus 5 c d R P1FCR bit7 eus D Q or Pin NP c EOR P17 R P1 ech C P1DDR FE45 bit7 pecial input ME W P1DDR C R P1DDR iiil comparator output P16HPWSEL HPWM2 outpu
90. RRRARRRSERRARRRARRRSRARRRRRRRRRRARRRRRRRGRRARRRRARRRRRARRRRRRRGuR AR una 3 90 3 1 2 3 Circuit Configuration ssausnsuansauuauuaunanupiaausuHuunanuunausuauanauunauuaunsauuuasuuanauunuanuu 3 90 3 1 24 Related Registers snsassuauansauanauunsanauuanusausyuassuauanssaunnauuauuuanuuauaAsessnnsasuuasauansunuas 3 92 3 12 5 Example of Using Temperature Sensor rr 3 93 Chapter A ControlFunctions 00000000 terete renee cence eee eeeeeeeeeeeneeeeeenes 4 1 4 1 Interrupt Function mH HH 4 1 4 1 1 Overview o 4 1 4 1 2 Functions o o 4 1 4 1 3 Circuit Configuration o 4 2 4 1 4 Related Registers FuuussssssuusussesansusussunsuuansusunssssusunsshuaRsusussuyusussssunumsune 4 3 4 2 System Clock Generator Function HM rere ee tnnt 4 5 4 2 1 Overview sssasuuansauanauanasanuauanassuanasuuaAus uauuanauanusuunusauusuuasuuuasuuanuaunausuauansuunanuua 4 5 4 2 2 Functions BRRARRRARARSESARRRARRRRRRARRRARRRGSRARRRRRARRGRSERARRRARRRGRRARRRARRRGRARRRRRARRRRRAR RR Rn 4 5 4 2 3 Circuit Configuration o 4 6 4 2 4 Related Registers o 4 9 4 8 Standby Function meme 4 15 4 3 1 Overview NENNIR NNT 4 1 5 4 3 2 Functions sssasunuansassansuupuaunuuansaunnumasasuanasuunsanuAuuaunuunsuuauuuaunuaseuanauansusasansunuauu 4 1 5 4 3 3 Related Registers sssasuuansasansuunuasauansunuausuaunasunsusaunsanuasusaunsauuassauuansunuas 4 1 6 44 Reset Function rne nnn eren nenne nnne nenne nnn ss 4 21 4 4 1 Overview o NNT 4 21 4 4 2 Functions sssasuuansasansuunanusuauussunnasauanuauunnauua
91. T1 BITO FE4B 0000 0000 R W I45SL I5SL3 I5SL2 ISSLI I5SLO I4SL3 I4SL2 I4SL1 I4SLO I5SL3 bit 7 to I5SLO bit4 Must always be set to 0 PORTS 14SL3 bit 3 INT4 pin select 14SL2 bit 2 INT4 pin select Pin Assigned to INT4 Port P13 14SL1 bit 1 INT4 pin function select 14SLO bit 0 INT4 pin function select When the data change specified by the external interrupt 4 5 control register I45CR is given to the pin that is assigned to INT4 timer 1 count clock input and timer 0 capture signal are generated 14SL1 14SLO Function other than INT4 Interrupt 0 None 0 363 Timer 1 count clock input o1 0 Timer OL capture signal input Timer 0H capture signal input 1 Ifthe timer OL or OH capture signal input is specified together with port 7 for INT4 any signal from port 7 is ignored 2 IfINTA is specified for timer 1 count clock input and timer OL or OH capture signal input at the same time both inputs are accepted 3 If timer I count clock input is specified for INT4 timer IL serves as an event counter If the timer 1 count clock input is not specified timer 1L counts every 2Tcyc 3 2 3 6 External interrupt 0 1 control register 101CR 1 The external interrupt 0 1 control register is an 8 bit register for controlling external interrupts 0 and l Address Initial value R W Name BIT7 BIT6 BIT5 BIT4 BITS BIT2 BIT1 BITO FESD 0000 0000 R W IOICR INTILH INTILV INTIIF
92. T1LONG bit 5 Timer 1 bit length select When this bit is set to O timer 1 s higher and lower order bytes serve as independent 8 bit timers When this bit is set to 1 timer 1 serves as a 16 bit timer since the timer 1 high byte T1H counts up at the interval of the timer 1 low byte T1L Independent match signals are generated from T1H and TIL when their count value matches the contents of the corresponding match buffer register regardless of the value of this bit T1PWM bit 4 T1 output mode select This bit and TILONG bit 5 determine the output mode of T1 TIPWMH and TIPWML as summarized in Table 3 7 1 Table 3 7 1 Timer 1 Output TTPWMH TIPWML T1PWMH T1PWML Toggle output Period T1HR 1 x TIHPRC count x Toggle output Period TILR 1 x TILPRC 4 x Tcyc count x 4 x Tcyc Period 2 T1LR 1 x TILPRC count x events PWM output Period 256 x TIHPRC count x Tcyc PWM output Period 256 x TILPRC count x Tcyc Toggle output Period T1HR 1 x TIHPRC count x Toggle output Period TILR 1 x TILPRC 2 1 0 TIPWML period count x 4 x Tcyc or Period 2 T1HR 1 x TIHPRC count x or Period 2 TILR 1 x TILPRC TILR 1 x TILPRC count x events count x events 3 1 1 Toggle output Period T1HR 1 x TIHPRC count x PWM output Period 256 x TILPRC count TIPWML period x 2 x Tcyc T1HCMP bit 3 T1H match flag This flag is set if TIH reaches 0 when T1H is active TIHRUN 1 This flag must be cleared
93. T5 BIT4 BIT3 BIT2 BIT1 BITO FEDA 00HH HHOO R W rewPs2cNr TEMPS20N FIXO DIO2X FIXO TEMPS2ON bit 7 Temperature sensor operation control manual Setting this bit to 0 stops the operation of the temperature sensor Setting this bit to 1 starts the operation of the temperature sensor Note When ANIS is selected as AD converter input and AD conversion starts the operation of the temperature sensor is turned on automatically And when AD conversion ends the operation of the temperature sensor is turned off automatically bit 6 Test bit Must always be set to 0 DIO2X bit 1 Temperature sensor diode number of row select When this bit is set to 0 the temperature sensor is configured to 4 diodes mode When this bit is set to 1 the temperature sensor is configured to 2 diodes mode bit 0 Test bit Must always be set to 0 Note When the temperature sensor is operating TEMPS20N 1 about an operating current of several hundreds uA is always flowing in the IC In this state when standby mode is entered the temperature sensor keeps its operation If it is required to reduce a current at the stanby mode the operation of the temperature sensor must be stopped TEMPS20N 0 before standby mode is entered 3 12 4 Temperature sensor 60 C 2 diodes reference register L D2TL 8 bit register The lower 8 bit of the result of 12 bit AD conversion VREF2 0V of the reference output voltage level of the senso
94. TALI DATALO ADRL3 ADRL2 ADRLI ADTM2 DATAL3 bit 7 DATAL2 bit 6 AD conversion results lower order 4 bits DATAL1 bit 5 DATALO bit 4 ADRL3 bit 3 Fixed bit Must always be set to 0 ADRL2 bit 2 Fixed bit Must always be set to 0 ADRL1 bit 1 Fixed bit Must always be set to 0 ADTM2 bit 0 AD conversion time control This bit and AD mode register ADMRC bits ADTMI bit 1 and ADTMO bit 0 are used to control the conversion time See the subsection on the AD mode register for the procedure to set the conversion time Note The conversion results data contains some errors quantization error combination error Be sure to use only valid conversion results while referring to the latest SANYO Semiconductors Data Sheet 3 8 4 4 AD conversion results high byte register ADRHC 1 The AD conversion results high byte register is used to hold the higher order 8 bits of the results of an AD conversion that is carried out in the 12 bit AD conversion mode The register stores the whole 8 bits of an AD conversion that is carried out in the 8 bit AD conversion mode 2 Since the data in this register is not established during an AD conversion the conversion results must be read out only after the AD conversion is completed Address Initial value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FESB 0000 0000 R W ADRHC DATA7 DATA6 DATAS DATA4 DATA3 DATA2 DATAI DATAO 3 67 ADC12
95. Timer OL capture signal gt Er EE m INT1 _ __ L level E Int request to address 00003 I01CR FE5D E Int request to address 0000B INTO Ports 1 and Port 7 Interrupt Block Diagram AII 7 Important Note This document is designed to provide the reader with accurate information in easily understandable form regarding the device features and the correct device implementation procedures The sample configurations included in the various descriptions are intended for reference only and should not be directly incorporated in user product configurations ON Semiconductor shall bear no responsibility for obligations concerning patent infringements safety or other legal disputes arising from prototypes or actual products created using the information contained herein LC870G00 SERIES USER S MANUAL Rev 1 00 June 14 2013 ON Semiconductor Digital Solution Division Microcontroller amp Flash Business Unit
96. V REF2 0V of the reference output voltage level of the sensor 2 diodes at about 60 C is stored in this register 3 12 3 3 Temperature sensor 60 C 2 diodes reference register H D2TH 8 bit register The upper 4 bit of the result of 12 bit AD conversion VREF2 0V of the reference output voltage level of the sensor 2 diodes at about 60 C is stored in this register 3 90 LC870G00 Chapter 3 3 12 3 4 Temperature sensor 60 C 4 diodes reference register L DATL 8 bit register The lower 8 bit of the result of 12 bit AD conversion VREF4 0V of the reference output voltage level of the sensor 4 diodes at about 60 C is stored in this register 3 12 3 5 Temperature sensor 60 C 4 diodes reference register H DATH 8 bit register The upper 4 bit of the result of 12 bit AD conversion VREF4 0V of the reference output voltage level of the sensor 4 diodes at about 60 C is stored in this register 3 12 3 6 Temperature sensor This is a temperature sensor whose output voltage level varies according to temperature ADC start AN15 selected Temperature TEMPS2CNT Sensor AD Converter 60 C 2 diodes reference lower 60 C4 diodes reference upper Figure 3 12 1 Temperature Sensor Block Diagram 3 91 HPWM2 3 12 4 Related Registers 3 12 4 1 Temperature sensor control register TEMPS2CNT The temperature sensor control register controls the operation of the temperature sensor Address Initial Value R W Name BIT7 BIT6 BI
97. VR24ON bit 6 10x 20x operational amplifier operation control Setting VR24ON to 0 stops operation of VREF24V circuit block Setting VR24ON to 1 starts operation of VREF24V circuit block See Fig 3 9 2 for VREF24V circuit block CPON bit 5 Comparator operation control Setting CPON to 1 and VR12ON to 1 starts the operation of the comparator When voltage level at PO2 1 22V comparator output High level When voltage level at PO2 gt 1 22V comparator output Low level 3 71 Reference Voltage Generator Circuit P02 To P16 pin function Comparator VREF12V output TYP1 22V Fig 3 9 1 Comparator VRADSEL bit 1 AD converter reference voltage select VR2SELZ bit 0 VREF24 output voltage select These bits control the AD converter reference voltage as the bellow table VREF24 VREF pin output AD converter reference VR120N VR240N VRADSEL VR2SELZ Circuit block voltage ON 2 0V 2 0V ON 4 0V 4 0V Open VDD Open VDD Opem VREF pin external voltage source VREF pin VREF12 VREF24 1 22V output AD converter 2 0V 4 0V output VR120N reference voltage input VR2SELZ 2 0V 4 0V select VR240N ON OFF control VRADSEL eference voltage select ANO 10x 20x amplifier amplifier output ON OFF control to P16 function comparator output Comparator ON OFF control Fig 3 9 2 VREF related circuit 3 72 LC870G00 Chapter 3 3 9 3
98. alized however when a WDT triggered reset occurs Note The WDTCNT is disabled for write once the WDT starts operation WDTRUN set to I If the instruction MOV 55H WDTCNT is executed in this case the WDTCT is cleared and count operation is restarted at a count value of 0 the WDTCT is not cleared when it is loaded with 55H with any other instruction Note The internal low speed RC oscillator circuit is started by setting WDTCKSL to 0 and WDTRUN to I Once the oscillator starts oscillation operating current of several uA flows For details refer to the latest SANYO Semiconductor Data Sheet It is noted that the oscillation is also started by setting SRCSTART OCR3 bit 0 to 1 4 27 WDT 4 5 5 Using the Watchdog Timer Code a program so that instructions for clearing the watchdog timer periodically are executed 1 2 3 Starting the watchdog timer 1 Set the time for a WDT reset to occur to WDTCKSL WDTCNT bit 6 and WDTSL 2 to 0 WDTCNT bits 2 to 0 2 Set the WDT standby mode operation HALT HOLD X tal HOLD to IDLOP 1 to 0 WDTCNT bits 4 to 3 3 After 1 and 2 set WDTRUN WDTCNT bit 5 to 1 The watchdog timer starts functioning when WDTRUN is set to 1 Once the watchdog timer starts operation WDTCNT is disabled for write it 1s allowed only to clear WDTCT and read WDTCNT Consequently the watchdog timer can never be stopped with an instruction The function of the watchdog timer is stopped onl
99. amental pulse width of HPWM2 Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BITS BIT2 BIT1 BITO FE8F 0000 0000 R W HPWM2AH HPWM2AH7 HPWM2AH6 HPWM2AH5 HPWM2AH4 HPWM2AH3 HPWM2AH2 HPWM2AH1 HPWM2AHO The PWM period and high level pulse witdth are set by HPWM2AH and HPWM2AL bits 7 to 6 as following lt 8 bit PWM mode H2ABWSL 0 gt e Fundamental wave period 256 x period set by HPWM2AC bits 6 to 5 e High level pulse width data of HPWM2AH 1 x period set by HPWM2AC bit6 to 5 lt 10 bit PWM mode H2ABWSL 1 gt Fundamental wave period 256 x period set by HPWM2AC bits 6 to 5 Overall period Fundamental wave period x 4 e High level pulse width HPWM2AH HPWM2AL bits 7 to 6 x period set by HPWM2AC bit6 to 5 3 88 LC870G00 Chapter 3 Note When HPWM2 is operating in 8 bit PWM mode setting of HPWM2AL bits 7 to 6 doesn t affect HPWM2 operation See 3 11 3 4 HPWM2 compare data buffer register for the detail reload operation of the compare data HPWM2AH HPWM2AL bits 7 to 6 3 89 HPWM2 3 12 Temperature sensor TEMPS 3 12 1 Overview This series of microcontrollers incorporates a simplified temperature sensor and microcontrollers can detect temperature changes using this sensor 1 The output voltage level of the sensor varies according to temperature 2 The output voltage level of the senser can be monitored by the AD converter 3 The result of AD conversion of a referenc
100. an instruction When the microcontroller enters the HOLD mode all oscillations main clock subclock low medium high speed RC are suspended and the related registers are placed in the states described below If OCR3 register bit 1 is set to 1 OCR3 register bit 0 is set and OCR register bits 4 and 5 and OCR3 register bit 6 are cleared If OCR3 register bit 1 is set to 0 OCR register bits 1 4 and 5 and OCR3 register bit 6 are cleared When the microcontroller returns from the HOLD mode according to the values of OCR and OCR3 registers the low or medium speed RC oscillator starts operation and is designated as the system clock source The main clock and subclock return to the states that were established before the microcontroller entered the HOLD mode The high speed RC oscillator is suspended When the microcontroller enters the X tal HOLD mode all oscillations except subclock 1 e main clock and low medium high speed RC are suspended but the states of the OCR and OCR3 registers remain unchanged If however the X tal HOLD mode is entered with the low speed RC oscillator selected as the base timer input clock source and the base timer has been started the low speed RC oscillator circuit retains the state that is established when the X tal HOLD mode is entered When the microcontroller returns from the X tal HOLD mode the system clock to be used when the X tal HOLD mode is entered needs to be set to either
101. and generates set signals for base timer interrupts 0 and 1 The switching of the input clock is accomplished by the base timer control register BTCR This counter is reset under the conditions BTON BTCR bit 6 is set to 0 stop base timer operation data is loaded into the BTPRR and the microcontroller is in HOLD mode Base timer input clock source The clock input to the base timer can be selected via the input signal select register ISL from 4 clock sources i e cycle clock timer counter 0 prescaler output subclock and low speed RC oscillator clock wow 3 46 LC870G00 Chapter 3 BTON HOLD mode Load BTPRR BTIMC1 0 ISL bits 5 4 Reset 6 bit 16384 64tBST Subclock BTIFO set counter Teyc Programmable Low speed RC OSC clock prescaler Timer O prescaler BTC11 0 amp bit 2048 8tBS BTIF1 set f 32tBST 128tBS To P17 BUZ Timer 1PWMH BUZON ISL bit 3 tBST Base timer input clock period selected by BTPRR set value 1 x BTIMC1 0 ISL bits 5 4 Figure 3 6 1 Base Timer Block Diagram 3 47 BT 3 6 4 Related Registers 3 6 4 1 Base timer control register BTCR 1 The base timer control register is an 8 bit register that controls the operation of the base timer Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE7F 0000 0000 R W BTCR BTFST BTON BTCI1 BTCIO BTIF1 BTIEI BTIFO BTIEO BTFST bit 7 Base timer interrupt 0 period co
102. asunsanuuan 3 62 3 8 1 Overview o 3 62 3 8 2 Eunctions o Tee ee ree ree eee ee eee eee ee 3 62 3 8 3 Circuit Configuration Furuusassusuuumsasuuununmsuasununsuusausussusuususuusununusausunsussuauss 3 64 3 8 4 Related Registers Furuusassusuusussueuuumsuassununsaneunsuuusausunsusauseussnsuasuusensunumses 3 64 3 8 5 ADC Conversion Example rurussssssuuuunssssunsnsunsasussussuusumsseeunanssseusuansunuuuuas 3 68 3 8 6 Hints on the Use of the ADC o 3 69 11 Contents 3 9 Reference Voltage Generator Circuit mm 3 71 3 9 1 Overview o RR 3 71 3 9 2 Functions sssasuuansasanasuansuuasuuauuuaucuanauansanuuuuauunsuanuap yzaunuasauenauansanauansuuunauu 3 71 3 9 3 Related Registers sasasuuansasanasuunusasuuanasuansanussananuunsusuumsmauunmassaeunnasuuasauansunuas 3 71 3 9 4 HALT and HOLD Time Operation o 3 74 310 VOPWM 0 ro 3 75 3 1 0 1 Overview o una 3 75 3 1 0 2 Eunctions o o AR Rua 3 75 3 1 0 3 Circuit Configuration A AO 3 76 3 1 0 4 Related Registers o a 3 78 ARMIZUUPVIM 3 84 3 1 1 1 Overview sssasuuanssuanssuanasuuasunaunuasasssauASsuasssauanasuaunasuuasunassussausnauansanauansunnansu 3 84 3 1 1 2 Functions NENNIR NNT 3 84 3 1 1 3 Circuit Configuration o o o RR RR 3 85 3 1 1 4 Related Registers AA 3 87 3 12 Temperature sensor mH HH 3 90 3 1 2 1 Overview BRRRRRRARARASRARRRARRRSRRARRRARRRGRARRRRRRRGRRARRRRRRRSRRARRRARRRSRARRRRGARRGRRAR RR a n 3 90 3 1 2 2 Functions BRRARRRARARSSESA
103. bits as the highest order byte of the address and the contents 16 bits of Rn Rn C or RO off either one as the lower order bytes of the address Examples LDW 3456H Sets up the lower order 16 bits STW R5 Loads the indirect register R5 with the lower order 16 bits of the address MOV 12H B Sets up the higher order 8 bits of the address LDX 1 Transfers the contents of external data memory address 123456H to the accumulator 2 9 2 12 Wait Sequence 2 12 1 Wait Sequence Occurrence The LC870A00 series of microcontrollers does not have wait sequences that automatically suspends execution of instructions 2 12 2 What Is a Wait Sequence 1 When a wait request occurs out of a factor explained in Subsection 2 12 1 the CPU suspends the execution of the instruction for one cycle during which transfers the required data This is called a wait sequence 2 The peripheral circuits such as timers and PWM continue processing during the wait sequence 3 A wait sequence extends over no more than two cycles 4 The microprocessor performs no wait sequence when it is in the HALT or HOLD mode 5 Note that one cycle of discrepancy is introduced between the progresses of the program counter and time once a wait sequence occurs 2 10 LC870G00 Chapter 2 Table 2 4 2 Chart of State Transitions of Bit 8 RAM SFR and P1 Instruction BIT8 RAM SFR P1 PSW BIT 1 Remarks LD LDW 5 P1 lt REG8 P1 lt REGH8
104. cillator circuit gets ready for oscillation by connecting a crystal oscillator 32 768 kHz standard a capacitor and a damping resistor to the CF1 XT1 and CF2 XT2 pins and controlling the OCR and XT2PC registers 2 The data at the CF2 XT2 pin can be read as bit 3 of the oscillation control register OCR The data at the CF1 XT1 pin is not read as bit 2 of the OCR register 3 The general purpose input configuration must be selected and the CF1 XT1 and CF2 XT2 pins must be kept high or low level when neither main nor subclock is to be used or they are not to be used as general purpose input ports 4 2 8 3 Internal low speed RC oscillator 1 Thelow speed RC oscillator oscillates according to the internal resistor and capacitor at 30 kHz standard 2 Theinternal low speed RC oscillator serves as the system clock that is to be used for low power low speed operation 4 2 8 4 Internal medium speed RC oscillator 1 The medium speed RC oscillator oscillates according to the internal resistor and capacitor at MHz standard 2 Theclock from the medium speed RC oscillator is designated as the system clock after the reset state is released After the HOLD mode is exited the clock from the medium or low speed RC oscillator is designated as the system clock according to the value of oscillation control register 3 OCR3 bit 1 when HOLD mode is entered 4 2 8 5 Internal high speed RC oscillator circuit 1 Thehigh speed RC oscillator
105. d return to 2 in step 4 Perform a receive operation 8 bits then set the clock output to 0 on the falling edge of the 8th clock after which an interrupt occurs The clock counter will be cleared if a start condition is detected in the middle of receive processing In such a case another 8 clocks are required to generate an interrupt Read SBUF1 and store the read data Note Bit 8 of SBUF is not yet updated because the rising edge of 9th clock has not yet occurred Return to in step 6 to continue receive processing Sending data o KD 3e x4 o Clear STIREC Load SBUFI with output data Clear SIIEND and exit interrupt processing Send an acknowledge for the preceding reception operation and release the clock port after the lapse of SBR1 value 1 x Tcyc Perform a send operation 8 bits and set the clock output to 0 on the falling edge of the 8th clock after which an interrupt occurs Go to 3 in step 7 if SITRUN is set to 1 If SILRUN is set to 0 implying an interrupt from 4 in step 7 clear SILEND and SILOVR and return to 1 in step 4 Read SBUFI and check send data as required Note Bit 8 of SBUF is not yet updated because the rising edge of 9th clock has not yet occurred Load SBUFI with the next output data Clear SIITEND and exit interrupt processing Release the clock port after the lapse of SBR1 value 1 x Tcyc Return to 1 in step7 if an acknowledge from the master is pres
106. ditions PCON register FEO7H bit 2 set to 1 and bit 1 to 1 X tal HOLD Note 1 Main clock low medium high speed RC oscillators stopped Subclock retains the state established when X tal HOLD mode is entered Note 2 Contents of OCR and OCR3 registers remain unchanged CPU enters this mode after selecting subclock low speed RC oscillator medium speed RC oscillator or high speed RC oscillator as system clock source CPU and all peripheral modules except base timer stop operation Base timer retains the state established when X tal HOLD mode is entered When X tal HOLD mode is exited the oscillators return to the state established when the mode is entered E X tal HOLD mode release conditions Interrupt request by base timer generated INTO or INT1 level interrupt request generated Request for INT2 INT4 or port O interrupt generated Resetting condition established Note 3 The oscillation of the low speed RC oscillation circuit is controlled directly by the watchdog timer Its oscillation is also controlled in the standby mode See Section 4 6 Watchdog Timer for details If the X tal HOLD mode is entered with the low speed RC oscillation selected as the base timer input clock source and the base timer has been started the low speed RC oscillation circuit retains the state that is established when the X tal HOLD mode is entered The CPU enters the reset state when the resetting conditio
107. e falling edge of the eighth clock for recognition by a program 5 Interrupt generation An interrupt request is generated at the end of communication if the interrupt request enable flag is set 6 Tocontrol serial interface 1 SIO1 it is necessary to control the following special function registers SCONI SBUFI SBR1 PI PIDDR PIFCR Address Initial Value R W Name BIT8 BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE34 0000 0000 R W SCONI SIIMI SIIMO SIIRUN SII REC SIIDIR SHOVR SILEND SIE rex 00000000 rw seri ssmcr7 ssgie ssgois sect seRais seRG12 seRG 1 sBRG10 3 51 3 7 3 4 2 Circuit Configuration SIO1 control register SCON1 8 bit register The SIO1 control register controls the operation and interrupts of SIO1 SIO1 shift register SIOSF1 8 bit shift register This register is a shift register used to transfer and receive SIO1 data This register cannot be accessed with an instruction It is accessed via SBUFI SIO1 data register SBUF1 9 bit register The lower order 8 bits of SBUF1 are transferred to SIOSFI at the beginning of data transfer At the end of data transfer the contents of SIOSFI are placed in the lower order 8 bits of SBUFI In modes 1 2 and 3 since the 9th input data is placed in bit 8 of SBUFI it is possible to check for a stop bit SIO1 baudrate generator register SBR1 8 bit reload counter This is a reload counter to generate an inte
108. e generation of the clock immediately Data input 8 bit shift register SIOSF1 EE At time transfer At time operation l SIO1 output cort E P10 fepe pepe ri 0 P10 output contro SBUF1 FE35h lt SIO1 output control Z P11 P11 port latch gt Le E Clock P11 output contro lt Clock generation NC E circuit SIO1 output contro E ES P12 P12 port latch MSB LSB first control P12 tput t Baud rate pur generator Serial transfer end flag SBR1 FE36h Overrun flag Er efTe eT SCON1 FE34h Interrupt request Figure 3 7 1 SIO1 Mode 0 Synchronous 8 bit Serial I O Block Diagram SI1M1 0 SI1M0 0 3 54 LC870G00 Chapter 3 Start bit additional circuit Shift input Shift input Start stop bit additional circuit operation starts LSB MSB first control Stop bit data input zs ose eo o SBUF1 FE35h Stop bit input clock 8 bit shift register SIOSF1 Shift clock transfer ends SIO1 output control P10 port latch P10 output control Clock generation circuit SIO1 output control gt P11 P11 port latch Lo WW Baud rate SET SHEND when P11 output control generator stop bit data ends SBR1 FE36h Overrun flag DOE SCON1 FE34h Interrupt request Figure 3 7 2 SIO1 Mode 1 Asynchronous Serial UART Block Diagram SI1M1 0 SI1M0 1 3 55 3 7 4 SIO1 Transmission Examples 3 7 4 1 Synchronous
109. e output voltage level of the sensor has been stored in SFR before shipment sorting of ICs 3 12 2 Functions 1 Temperature sensor function The output voltage level of the sensor varies linearly according to temperature The lower tenperature is the higher the output voltage level of the sensor is low temperaturez room temperaturez low temperature The output of the sensor is connected to the AD converter input so a temperature can be monitored by the AD conversion of the output voltage level of the sensor 2 Reference to reference voltage level of the temperature sensor The result of AD conversion of the reference output voltage level of the sensor at about 60 C has been stored in SFR before shipment sorting of this series of microcontrollers and it can be referred by program 3 To control temperature sensor it is necessary to manipulate the following special function registers TEMPS2CNT ADCRC ADMRC ADRLC ADRHC D2TL D2TH DATL DATH Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FEDA ooHH HH00 R W tempsecnt TEMPS2ON FIXO DIO2X FIXO 3 12 3 Circuit Configuration 3 12 3 1 Temperature sensor control register TEMPS2CNT 8 bit register The temperature sensor control register controls the operation of the temperature sensor 3 12 3 2 Temperature sensor 60 C 2 diodes reference register L D2TL 8 bit register The lower 8 bit of the result of 12 bit AD conversion
110. e provided between release from a standby mode and entry into the next standby mode Note that the oscillation frequency of the low speed RC oscillator may fluctuate For details refer to the latest SANYO Semiconductor Data Sheet 2 When the subclock is selected as WDT clock WDTCKSL 1 When the watchdog timer is used with WDTCKSL set to 1 set EXTOSC OCR bit 6 to 1 and start the watchdog timer operation with a program control allowing the subclock oscillator to get stabilized On the detection of subclock oscillation suspended by EXTOSC OCR bit 6 being set to 0 or the HOLD mode being entered when the watchdog timer is running the watchdog timer considers that a program hangup has occurred and triggers a WDT reset In this case WDTRSTF is set This mode is primarily used for real time clock applications to realize low power operation 4 29 WDT 4 30 LC870A00 Chapter 4 4 6 Internal Reset Function 4 6 1 Overview This series of microcontroller incorporates internal reset functions called the power on reset POR and low voltage detection reset LVD The use of these functions will contribute to the reduction in the number of externally required reset circuit components reset IC etc 4 6 2 Functions 1 Power on reset POR function POR is a hardware feature that generates a reset to the microcontroller at power on time This function allows the user to select the POR release level by optio
111. e sure to read the CLKOEN value in advance and make sure that it is 0 3 1 4 Options Two user options are available 1 CMOS output with a programmable pull up resistor 2 N channel open drain output with a programmable pull up resistor 3 1 5 HALT and HOLD Mode Operation When in the HALT or HOLD mode port 0 retains the state that is established when the HALT or HOLD mode is entered 3 4 LC870G00 Chapter 3 3 5 PORTS 3 2 3 2 1 Port 1 Overview Port 1 is an 8 bit I O port equipped with programmable pull up resistors It is made up of a data latch a data direction register a function control register and a control circuit Control of the input output signal direction is accomplished by the data direction register on a bit basis Port 1 can also be used as a serial interface I O port a HPWM2 output port or a comparator output port by manipulating its function control register As a user option either CMOS output with a programmable pull up resistor or N channel open drain output with a programmable pull up resistor can be selected as the output type on a bit basis 3 2 2 D 2 4 5 6 7 Functions I O port 8 bits P10 to P17 The port output data is controlled by the port 1 data latch P1 FE44 and the I O direction is controlled by the port 1 data direction register PIDDR FE45 Each port bit is provided with a programmable pull up resistor Interrupt input pin function e P
112. e timer interrupt 1 request enable control Setting this bit and BTIFI to 1 generates X tal HOLD release reset signal and interrupt request to vector address 001 BH conditions BTIFO bit 1 Base timer interrupt 0 flag This flag is set at the interval equal to the base timer interrupt O period that is defined by BTFST This flag must be cleared with an instruction 3 48 LC870G00 Chapter 3 BTIEO bit 0 Base timer interrupt 0 request enable control Setting this bit and BTIFO to 1 generates the X tal HOLD mode release signal and interrupt request to vector address 001BH e The base timer interrupt period must be set up as the conditions for setting the flags BTIF 1 and BTIFO at every base timer interrupt interval so that the cycle clock period Tcyc and the base timer interrupt period satisfy the following relationship Cycle clock period Tcyc 7 Base timer interrupt period 2 Since program processing e g interrupt processing routine is involved in practice the time that is required to execute such processing should be taken into consideration when setting up the optimum interrupt period e There are cases in which BTIFI is set to if an attempt is made to rewrite BTC11 or BTC10 while the base timer is running M Base timer oscillation may be suspended if the CPU is placed in the standby mode while the base timer is running when the main clock or subclock is selected as the base timer clock source Although the osc
113. ection signal from P17 INT1 TOHCP P15 INT3 TOIN P13 and P14 timer OH capture input pins TOL period TOLR 1 x TOPRR 1 x Tcyc TOH period TOHR 1 x TOPRR 1 x Tcyc Tcyc Period of cycle clock Mode 1 8 bit programmable timer with a programmable prescaler equipped with an 8 bit capture register 8 bit programmable counter equipped with an 8 bit capture register TOL serves as an 8 bit programmable counter that counts the number of external input detection signal from pins P16 INT2 TOIN and P15 INT3 TOIN TOH serves as an 8 bit programmable timer that runs on the clock with a period of 1 to 256 Tcyc from an 8 bit programmable prescaler The contents of TOL are captured into the capture register TOCAL on an external input detection signal from P70 INTO TOLCP P16 INT2 TOIN P13 and P14 timer OL capture input pins The contents of TOH are captured into the capture register TOCAH on an external input detection signal from P17 INT1 TOHCP P15 INT3 TOIN and P13 and P14 timer OH capture input pins TOL period TOLR 1 TOH period TOHR 1 x TOPRR 1 x Tcyc 3 2 3 Mode2 16 bit programmable timer with a programmable prescaler equipped with a 16 bit capture register nthis mode timer counter 0 serves as a 16 bit programmable timer that runs on the clock with a period of 1 to 256 Tcyc from an 8 bit programmable prescaler The contents of TOL and TOH are captured into the capture regist
114. ed and stopped by the 0 1 value of TOHRUN timer 0 control register bit 7 Count clock Either prescaler s match signal or TOL match signal must be selected through the 0 1 value of TOLONG timer 0 control register bit 5 Match signal A match signal is generated when the count value matches the value of the match buffer register 16 bits of data need to match in the 16 bit mode Reset This counter is reset when it stops operation or a match signal is generated Timer counter 0 match data register low byte TOLR 8 bit register with a match buffer register 1 2 This register is used to store the match data for TOL It has an 8 bit match buffer register A match signal is generated when the value of this match buffer register coincides with the lower order byte of timer counter 0 16 bits of data need to match in the 16 bit mode The match buffer register is updated as follows The match register matches TOLR when it is inactive TOLRUN 0 When the match register is running TOLRUN 1 it is loaded with the contents of TOLR when a match signal is generated 3 23 3 4 8 7 Timer counter 0 match data register high byte TOHR 8 bit register with a match buffer register 1 This register is used to store the match data for TOH It has an 8 bit match buffer register A match signal is generated when the value of this match buffer register coincides with the higher order byte of timer counter 0 16 bits of data
115. ed directly by the watchdog timer Its oscillation is also controlled in the standby mode See Section 4 6 Watchdog Timer for details Note 2 If the X tal HOLD mode is entered with the low speed RC oscillation selected as the base timer input clock source and the base timer has been started the low speed RC oscillation circuit retains the state that is established when the X tal HOLD mode is entered Note 3 Certain serial transmission functions are stopped Note4 The microcontroller switches into the reset state if it exits the current mode on the establishment of reset entry conditions 4 17 Standby Table 4 3 2 Pin States and Operating Modes This Series On Exit from Reset Time Normal Mode HALT Mode HOLD Mode HOLD e T O pin CFI e Input pin CF oscillation inverter CF oscillation inverter e State established e Oscillation not input general purpose input general purpose input on entry into started input output selected by is in the state established on HOLD mode bit 3 of register XT2PC entry into HOLD mode FE43H Oscillation enabled or disabled by register OCR FEOEH Feedback resistors e Feedback resistor e Feedback resistor between for CF and XT are between CF1 and CF2 CFI and CF2 is in the state turned off controlled by a program established on entry into HOLD mode ASTI KT2 turned off controlled by a program established on entry into HOLD mode CF2 e Input pin e CF oscil
116. ee ee eee ee eee eee eee eee eee eee ee ee ee eee eee 1 1 0 1 9 User Option Table ss 1 11 1 10 Power Pin Treatment Recommendations VDD1 VSS1 m 1 11 Chapter 2 Internal Configuration E 2 1 2 1 Memory Space Mururshruesasuesenuenenanauenensenensusuenensenensussenenssuenensenensssesensenes 2 1 2 2 Program Counter PC n0 GL 2 1 2 3 Program Memory ROM 0 LM 2 2 24 Internal Data Memory RAM a ere 2 2 2 5 Accumulator A Register ACC A ee ee eee eee eee eee eee eee ee eee eee eee ee 2 3 2 6 B Register B eee eee eee ee eee eee ee eee ee eee eee eee ee eee eee eee ree eee eee ee 2 3 2 7 C Register C a 2 4 2 8 Program Status Word PSW a 2 4 2 9 Stack Pointer SP o 2 5 2 10 Indirect Addressing Registers AAA 2 5 2 11 Addressing Modes M MH MM 2 6 2 11 1 Immediate Addressing eee eee eee eee eee eee eee eee eee eee ee ee eee ee 2 6 2 11 2 Indirect Register Indirect Addressing Rn etre eener 2 7 2 11 3 Indirect Register C Register Indirect Addressing Pn CH 2 7 2 11 4 Indirect Register RO Offset Value indirect Addressing off 2 8 2 11 5 Direct Addressing dst Frkursusrsuysseassesusessneseseensseesssenssessssssyusessseessesssee 2 8 2 11 6 ROM Table Look up Addressing eee ee eee eee eee eee eee eee 2 9 2 11 7 External Data Memory Addressing eee eee eee eee eee eee eee eee eee eee ee 2 9 2 1 2 Wait Sequence eee eee eee eee ee ee ee eee eee ee eee eee ee eee eee ee ee ee reer 2 1 0 2 1 2 1 Wait Sequence Occurrence eee eee eee eee eee
117. eed RC oscillator clock is selected as the WDT clock source when the continue count operation is selected an operating current of several yA is always flowing in the IC because the internal low speed RC oscillation circuit is continuing oscillation For details refer to the latest SANYO Semiconductor Data Sheet 3 To control the watchdog timer WDT it is necessary to manipulate the following special function register WDTCNT Address Initial value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE79 00000000 R W WDTCNT WDTRSTF WDTCKSL WDTRUN IDLOP1 IDLOPO WDTSL2 WDTSLI WDTSLO 4 23 WDT 4 5 3 4 5 3 1 Circuit Configuration WDT control register WDTCNT 8 bit register 1 The WDT control register is used to manipulate the WDT reset detection flag to select operations in the standby time mode to select the overflow time and to control the operation of WDT Note Note Note 4 5 3 2 The WDTCNT is initialized with 00H when a low level signal is applied to the external RES pin or a reset is triggered by the internal reset POR LVD function Bit 6 and bits 4 to 0 of the WDTCNT are not initialized however when a WDT triggered reset occurs The WDTCNT is disabled for writes once the WDT is started WDTRUN set to 1 If the instruction MOV 55H WDTCNT is executed in this case the WDTCT is cleared and count operation is restarted at a count value of 0 the WDTCT is not cleared when i
118. efore HPWM2 starts operation When the internal high speed RC 40MHz is operating about an Operating current of several mA is always flowing in the IC If it is required to reduce a current at the stanby mode the oscillation must be stopped H2A40MON O before standby mode is entered 3 11 4 2 HPWM 2 compare register L HPWM2AL 1 The HPWM2 compare register L controls the additional pulses of HPWM2 and the function outputs of P17 and P16 FE8E 00HH HHOO R W HPWM2AL HPWM2AL1 HPWM2ALO P17H2ASL P16H2ASL P17H2ASL bit 1 P17 function output control This bit and BUZON ISL bit3 select the data transferred to P17 from the buzzer timer 1 PWMH and HPWM2 output Note It is also required for the function output from P17 to setup P17 P1 bit P17DDR P1IDDR bit7 and P17FCR PIFCR bit7 P17H2ASL BUZON function output HPWM2AL bit1 ISL bit3 O00 5 0 0 Timer1 PWMH output P16H2ASL bit 0 P16 function output control When this bit is set to 0 AND of timer 1 PWML and the comparator output is transferred to P16 e When this bit is set to 1 AND of HPWM2 and the comparator output is transferred to P16 Note The comparator output is fixed to high level when CPON VRCNT bit5 is set to 0 t is also required for the function output from P16 to setup P16 P1 bit6 PIGDDR PIDDR bit6 and P16FCR P1FCR bit6 3 11 4 3 HPWM 2 compare register H HPWM2AH 1 The HPWM2 compare register H controls the fund
119. elease voltage AC LVD reset voltage LVDET LVDET 0 5V Figure 4 6 4 Example of Power Interruption or Voltage Fluctuation Waveform Microcontroller VDD1 VSS1 Figure 4 6 5 Example of Power Interruption Voltage Fluctuation Countermeasures 4 36 4 6 7 1 LC870A00 Chapter 4 Notes to be Taken When Not Using the Internal Reset Circuit When configuring an external reset IC without using the internal reset circuit The POR function is activated and the capacitor Cres discharging N channel transistor connected to the RESET pin turns on when power is turned on even if the internal reset circuit is not used For this reason when connecting an external reset IC adopt the reset IC of a type whose detection level is not lower than the minimum guaranteed operating voltage level and select the lowest POR release level 1 67V that does not affect the minimum guaranteed operating voltage The figures given below show sample reset circuit configurations that use reset ICs of N channel open drain and CMOS types respectively Reset IC Microcontroller Several hundreds kO Internal pull up resistor option N channel open drain type RESET From POR Figure 4 6 6 Sample Reset Circuit Configuration Using an N channel Open Drain Type Reset IC Insert a protective resistor of several to scores of kO to prevent through current Reset IC Microcontroller CMOS type Internal pull
120. en the interrupt flag and interrupt enable flag are set by INTO a HOLD mode release signal is generated releasing the HOLD mode The CPU then enters the HALT mode main oscillation by CR When the interrupt is accepted the CPU switches from the HALT mode to normal operating mode When a signal change such that the interrupt flag is set is input to P70 that is specified for level triggered interrupt in the HOLD mode the interrupt flag is set In this case the HOLD mode is released if the corresponding interrupt enable flag is set 5 Multiplexed pins Pin P70 also serves as the AD input channel pin AN9 3 17 PORTS Interrupt Input Signal Timer 0 Count Hold Mode Input Output Capture Input P P Detection Input P P Release With N channel open L level H level Timer OL Enabled programmable drain L edge H edge pull up resistor Address Initial value R W Name BIT7 BIT6 BITS BIT4 BIT3 BIT2 BIT1 BITO FESC HHH0 HHHO R W P70DDR P70DT 3 3 8 Related Registers 3 3 3 1 Port 7 control register P7 1 The port 7 control register is a 2 bit register for controlling the I O of port 7 data and pull up resistors 2 When this register is read with an instruction data at pin P70 is read into bit 0 Bit 4 is loaded with bit 4 of register P7 If P7 FESC is manipulated with an instruction NOTI CLR1 SETI DBZ DBNZ INC or DEC the contents of the register are referenced as bit O instead of the data at
121. ent L If there is no acknowledge presented from the master H SIO1 recognizing the end of data transmission automatically clears SIIRUN and release the data port However in a case that restart condition comes just after the event SITREC must be set to 1 before exiting the interrupt SII REC is for detecting a start condition and is not set automatically It may disturb the transmission of address from the master if there is an unexpected restart just after slave s transmission when SII REC is not set 1 by instruction When a stop condition is detected an interrupt is generated and processing returns to 2 in step 7 3 59 8 Terminating communication Set SILREC Return to in step 6 to cause communication to automatically terminate To force communication to termination clear SITRUN and SIIEND release the clock port e An interrupt occurs when a stop condition is detected Then clear SILEND and SILOVR and return to 2 in step 4 3 7 5 Related Registers 3 7 5 1 SIO1 control register SCON1 1 The SIO1 control register is an 8 bit register that controls the operation and interrupts of SIO1 Address Initial Value R W Name BIT8 BIT7 BIT6 BITS BIT4 BIT3 BIT2 BIT1 BITO FE34 0000 0000 R W SCONI SIIMI SIIMO SIIRUN SIIREC SIIDIR SIIOVR SIIEND SITE SI1M1 bit 7 SIO1 mode control SI1MO bit 6 SIO1 mode control Table 3 7 2 SIO1 Operation Modes Mode SH M1 SI MO Operating Mode
122. er contains for example FE02H it designates the C register Examples When R3 contains 123H RAM address 6 23H RAM address 7 01H LD R3 Transfers the contents of RAM address 123H to the accumulator LI STW R3 Transfers the contents of BA register pair to RAM address 123H PUSH R3 Saves the contents of RAM address123H in the stack SUB R3 Subtracts the contents of RAM address 123H from the accumulator DBZ R3 L1 Decrements the contents of RAM address 123H by 1 and causes a branch if Zero 2 11 3 Indirect Register C Register Indirect Addressing Rn C In the indirect register C register indirect addressing mode the result of adding the contents of one of the indirect registers RO to R63 to the contents of the C register 128 to 127 with MSB being the sign bit designates an address in RAM or SFR For example if the selected indirect register contains FE02H and the C register contains FFH 1 the address B register FE02H 1 FEO1H is designated Examples When R3 contains 123H and the C register contains 02H LD R3 C Transfers the contents of RAM address 125H to the accumulator LI STW R3 C Transfers the contents of the BA register pair to RAM address 125H PUSH R3 C Saves the contents of 125H in the stack SUB R3 C Subtracts the contents of RAM address 125H from the accumulator DBZ R3 C Ll Decrements the contents of RAM address 125H by 1 and causes a branch if Zero
123. er for data transmission reception at the beginning of transmission processing and the contents of the shift register are placed in the lower order 8 bits of SBUFI when 8 bit data is transferred 3 In modes 1 2 and 3 bit 8 of SBUFI is loaded with the 9th data bit that is received data about the position of the stop bit FE35 00000 0000 R W SBUFI SBUFIS8 SBUF17 SBUF16 SBUFI5 SBUF14 SBUFI3 SBUF12 SBUF11 SBUFIO 3 7 5 3 Baudrate generator register SBR1 1 The baudrate generator register is an 8 bit register that defines the baudrate of SIO1 2 Loading this register with data causes the baudrate generating counter to be initialized immediately 3 The baudrate varies from mode to mode the baudrate generator is disabled in mode 3 Modes O and 2 TSBRI SBRI value 1 x 2 Tcyc Value range 2 to 512 Tcyc Mode 1 TSBRI z SBRI value 1 x 8Tcyc Value range 8 to 2048Tcyc Address Initial Value R W Name BIT8 BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE36 0000 0000 R W SBRI SBRGI7 SBRGI6 SBRGI5 SBRG14 SBRG13 SBRG12 SBRG11 SBRG10 3 61 ADC12 3 8 AD Converter ADC12 3 8 1 Overview This series of microcontrollers incorporates a 12 bit resolution AD converter that has the features listed below It allows the microcontroller to take in analog signals easily 1 12 bit resolution 2 Successive approximation 3 AD conversion mode select resolution switching 4 Analog input 7 channel
124. erating Modes cont Synchronous Mode 0 UART Mode 1 Bus Master Mode 2 Bus Slave Mode 3 Transmit Receive Transmit Receive Transmit Receive Transmit Receive SHREC 0 SHREC 1 SHREC 0 SI1REC 1 SMREC 0 SHREC 1 SMREC 0 SHREC 1 SILOVR Set 1 Falling lt 1 Falling lt 1 SHEND lt 1 Falling lt bit 2 edge of edge of set edge of clock clock conditions clock detected detected met when detected when when SIIEND 1 when ShRUN 0 SIIRUN 0 SIIRUN 20 2 SIIEND 2 SIITEND 2 SIIEND set set set conditions conditions conditions met when met when met when SHEND 1 SIIEND 1 SIIEND 1 3 Start bit detected Clear Instruction lt Instruction lt Instruction lt Instruction lt Shift data SBUFI gt SBUFI gt SBUFI gt SBUFI gt update Shifter at Shifter at Shifter at Shifter at beginning beginning beginning of beginning of of of operation operation operation operation Shift SBUFI Rising edge When 8 bit When 8 bit Rising edge Rising edge lt bits O to 7 of 8th clock data data of 8th clock of 8th clock transferred received Input data Input data Input data update of read in on read in on read in on SBUFI bit 8 stop bit rising edge rising edge of 9th clock of 9th clock Note 1 If internal data output state H and data port state L conditions are detected at the rising edges of the first to 8th clocks the microcontroller recognizes a bus arbitration lost and clears SIIRUN and also stops th
125. eriod of PWM This flag must be cleared with an instruction CPWMOIE bit 0 VCPWMO VCPWM1 interrupt request enable control An interrupt to vector addresses 004BH is generated when this bit and CPWMOOV are both set to 1 3 10 4 2 VCPWMO compare register L VCPWMOL 1 The VCPWMO compare register L controls the additional pulses of VCPWMO 2 VCPWMOL is assigned bits 7 to 4 and all of its lower order 4 bits are apparently set to 1 when it is read 3 When the VCPWMO control bit VCPWMOC FE84 bit 2 is set to 0 the output of VCPWMO ternary can be controlled using bits 7 to 4 of VCPWMOL Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE80 0000 HHHH R W VCPWMOL CPWMOL3 CPWMOL2 CPWMOL1 CPWMOLO 7 ENCPWMO CPWMOL3 CPWMOL2 CPWMOL1 0 FE84 bit2 FE80 bit7 FE80 bit6 FE80 bit5 4 VCPWMO Output HI Z 3 78 LC870G00 Chapter 3 3 10 4 3 VCPWMO compare register H VCPWMOH 1 The VCPWMO compare register H controls the fundamental pulse width of VCPWMO Fundamental pulse width Value represented by CPWMOH7 to CPWMOH 0 x iTcyc 2 When bits 7 to 4 of VCPWMOL are all fixed at 0 VCPWMO can serve as period programmable 8 bit PWM that is controlled by VCPWMOH FE81 0000 0000 R W VCPWMOH CPWMOH7 CPWMOH6 CPWMOHS5 CPWMOH4ICPWMOH3 CPWMOH2 CPWMOH 1 CPWMOHO 3 10 4 4 VCPWM1 compare register L VCPWM1L 1 The VCPWMI compare register L controls the additional pulses of VCPWMI
126. eriods A fundamental wave period is represented by an 8 bit PWM PWM compare register H PNMH 4bits are used to designate the fundamental wave period to which additional pulses are to be added PWM compare register L PWML 12 bit register structure gt PWMH PWML XXXX XXXX XXXX 12BIT e How pulses are added to the fundamental wave periods Example 1 e PWM compare register H PWMH 00 H PWM compare register L PWML 0 to F H lt i st Overall period E M X Fundamental Fundamental Fundamental E Fundamental Fundamental Fundamental wave period O wave period 1 wave period 2 wave period 13 wave period 14 wave period 15 Fundamental period cor qu 909 3 E 553 56 2 9 f08 539 9 EN i1 i14 1s signal PWMH PWML 000 PWMH PWML 001 PWMH PWML 002 PWMH PWML 003 PWMH PWML 004 PWMH PWML 005 PWMH PWML 006 PWMH PWML 007 PWMH PWML 008 PWMH PWML 009 PWMH g PWML 00A PWMH g PWML 00B PWMH g PWML 00C PWMH g PWML 00D uh Arr M js ls PWMH PWML 00E PWMH I r r r r PWML 00F l JJLJL JL JL IL IL JL IL ILS 3 80 LC870G00 Chapter 3 e How pulses are added to fundamental wave periods e PWM compare register H PWMH OI H e PWM compare register L PWML OtoF H AA Overall period Fundamental Fundamental Fundamental Fundamental F
127. ers TOCAL and TOCAH at the same time on an external input detection signal from P17 INTI TOHCP P15 INT3 TOIN and P13 and P14 timer 0H capture input pins TO period TOHR TOLR 1 x TOPRR 1 x Tcyc 16 bits 4 Mode3 16 bit programmable counter equipped with a 16 bit capture register e In this mode timer counter 0 serves as a 16 bit programmable counter that counts the number of external input detection signal from pins P16 INT2 TOIN and P15 INT3 TOIN The contents of TOL and TOH are captured into the capture registers TOCAL and TOCAH at the same time on an external input detection signal from P17 INT1 TOHCP P15 INT3 TOIN P13 and P14 timer 0H capture input pins TO period TOHR TOLR 1 16 bits 5 Interrupt generation TOL or TOH interrupt requests are generated at the counter interval for timer counter TOL or TOH if the interrupt request enable bit is set 6 To control timer counter 0 TO it is necessary to manipulate the following special function registers TOCNT TOPRR TOL TOH TOLR TOHR PI PIDDR PIFCR P7 TSL ISL IO1CR I23CR I45CR I45SL Address Initial value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE10 0000 0000 R W TOCNT TOHRUN TOLRUN TOLONG TOLEXT TOHCMP TOHIE TOLCMP TOLIE re pooocoox m rocan roca rocas rocats tocara Tocats caua rocari rocauo rer exxx xxx r rocan rocas rocane rocans rocana rocans rocana roca rocano 3
128. ersion is carried out in the 12 bit AD conversion mode for the first time after a system reset The AD conversion is carried out for the first time after the AD conversion mode is switched from 8 bit to 12 bit AD conversion mode The conversion time determined using the conversion time calculation formula is adopted in the second and subsequent conversions or in the AD conversions that are carried out in the 8 bit AD conversion mode The conversion results data contains some errors quantization error combination error Be sure to use only valid conversion results while referring to the latest SANYO Semiconductors Data Sheet Make sure that only input voltages that fall within the specified range are supplied to pins P00 APIM PO1 APIP PO2 AN2 to P04 AN4 P15 ANS to P13 AN7 and P70 ANO Application of a voltage greater than VDD or lower than VSS to an input pin may exert adverse influences on the converted value of the channel in question or other channels Take the following preventive actions as countermeasures to keep the reduction in conversion accuracy due to noise interferences as low as possible Be sure to add external bypass capacitors several uF and thousands pF near the VDD1 and VSS1 pins as close as possible desirably 5 mm or less Add external low pass RC filters or capacitors most suitable for noise reduction immediately close to the analog input pins To avert the adverse coupling influences use a ground that
129. essing modes Rn Rn C and off are available for this purpose In this case only Rn are configured as 17 bit registers 128K byte space For models with banked ROM it is possible to reference the ROM data in the ROM bank 128K bytes identified by the LDCBNK flag bit 3 in the PSW Consequently when looking into the ROM table on a series model with banked ROM execute the LDCW instruction after switching the bank using the SETI or CLRI instruction so that the LDCBNK flag designates the ROM bank where the ROM table resides Examples TBL DB 34H DB 12H DW 5678H LDW TBL Loads the BA register pair with the TBL address CHGP3 TBL gt gt 17 amp 1 Loads LDCBN in PSW with bit 17 of the TBL address Note 1 CHGP1 TBL gt gt 16 amp 1 Loads Pl in PSW with bit 16 of the TBL address STW RO Load indirect register RO with the TBL address bits 16 to 0 LDCW l Reads the ROM table B 78H ACC 12H MOV 1 C Loads the C register with 01H LDCW R0 C Reads the ROM table B 78H ACC 12H INC C Increments the C register by 1 LDCW RO C Reads the ROM table B 56H ACC 78H Note 1 LDCBNK bit 3 of PSW need to be set up only for models with banked ROM 2 11 7 External Data Memory Addressing The LC870000 series microcontrollers can access external data memory spaces of up to 16M bytes 24 bits using the LDX and STX instructions To designate a 24 bit space specify the contents of the B register 8
130. et occurs this bit and XT2PC register bit 6 are cleared and the CF1 and CF2 pins serve as the input pins 3 XT2PC OCR register register CF1 XT1 OCR register EXTOsC CFSTOP XTCFSEL CF2 XT2 state XT2IN XTIIN Main clock oscillator CF2 XT2 CF1 XT1 active pin data pin data 1 1 1 Main clock oscillator CF2 XT2 CF1 XT1 stopped pin data pin data 1 X Subclock oscillator CF2 XT2 Read 0 active pin data X Inhibited Se Read pin data 0 General purpose input Ce CEIXTI purp P pin data pin data 0 General purpose CF2 XT2 CF1 XT1 input output pin data pin data 4 2 4 3 Oscillation Control Register 2 XT2PC 6 bit register 1 Theoscillation control register 2 is an 6 bit register that controls the operation of the oscillator circuits controls the general purpose outputs of CF1 XT1 N channel open drain CF2 XT2 pins and reads data from the CF1 and CF2 pins Address Initial value R W Name BIT7 BIT6 BITS BIT4 BIT3 BIT2 BIT1 BITO FE43 HH00 0000 R W XT2PC XTIDR XTIDT XTCFSEL XT2CMOS XT2DR XT2DT System Clock XTIDR bit 5 CFI XTI data direction This bit controls the CF1 XT1 input output direction when OCR register sets CF1 XT1 and CF2 XT2 to the general purpose input output mode 1 When this bit is set to 0 CFI XTI is set to the input mode 2 When this bit is set to 1 CFI XTI is set to the output mode N channel open drain XTIDT bit 4 CFI XTI data latch This bit controls the CF
131. flag to designate the bank during the LDCW instruction The PSW is allocated to address FEO6H of the internal data memory space and initialized to 00H on a reset Address Initial value R W Name BIT7 BIT6 BITS BIT4 BIT3 BIT2 BIT1 BITO FE06 0000 0000 R W PSW CY AC PSWBS PSWB4 LDCBNK OV PI PARITY CY bit 7 Carry flag CY is set to 1 when a carry occurs as the result of a computation and cleared to 0 when no carry occurs There are the following types of carries lt l gt Carry resulting from an addition lt 2 gt Borrow resulting from a subtraction 3 Borrow resulting from a comparison lt 4 gt Carry resulting from a rotation There are some instructions that do not affect this flag at all AC bit 6 Auxiliary carry flag AC is set to 1 when a carry or borrow occurs in bit 3 bit 3 of the higher order byte during a 16 bit computation as the result of an addition or subtraction and cleared to 0 otherwise There are some instructions that do not affect this flag at all PSWB5 PSWBA bits 5 and 4 User bits These bits can be read and written through instructions They can be used by the user freely LDCBNK bit 3 Bank flag for the table lookup instruction LDCW This bit designates the ROM bank to be specified when reading the program ROM with a table lookup instruction 0 ROM ADR 0 to IFFFF 1 ROM ADR 20000 to 3FFFF OV bit 2 Overflow flag OV is set to 1 when an overflow occurs as the result
132. g l I 00000H 0000H 000000H Note SFR is the area in which special registers such as the accumulator are allocated see Appendix 1 Fig 2 1 1 Types of Memory Space 2 2 Program Counter PC The program counter PC is made up of 17 bits and a bank flag BNK The value of BNK determines the bank The lower order 17 bits of the PC allows linear access to the 128K ROM space in the current bank Normally the PC advances automatically in the current bank on each execution of an instruction Bank switching is accomplished by executing a Return instruction after pushing necessary addresses onto the stack When executing a branch or subroutine instruction when accepting an interrupt or when a reset is generated the value corresponding to each operation is loaded into the PC Table 2 2 1 lists the values that are loaded into the PC when the respective operations are performed 2 1 Table 2 2 1 Values Loaded in the PC Operation PC value BNK value 00000H mm wm E mn leen 9 Im 3 wna 9 NTSBT CUA ma wm 9 mung wm 9 www men 9 so o wm 9 Dc fons 9 mw eem o SS M one instructions BZW BNZW BP BN BPC nb Number of instruction bytes Return instructions RET RETI PC16 to 08 SP BNK is set PC07 to 00 SP 1 to bit 8 of SP denotes the contents of RAM SP 1 address designated by
133. illation is resumed when the standby mode is exited erroneous counting will occur in the base timer because no oscillation stabilization time can be reserved in this case It is therefore recommended that measures be taken to stop the base timer before placing the CPU in the standby mode See Section 4 2 System Clock Generator Function for the state of the oscillation circuits in the standby mode e Counting errors can occur in the base timer if the base timer clock source is changed resetting ISL bits 5 and 4 while the base timer is running Be sure to stop the base timer in advance when changing the base timer clock source 3 6 4 2 Base timer programmable prescaler match register BTPRR 1 This register is an 8 bit register that sets the clock period tBST of 8 bit 6 bit binary up counter 2 When BTPRR is loaded with data the prescaler and the binary up counter are reset to the count value 0 3 tBST BTPRR set value 1 x Base timer input clock period Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE3D 0000 0000 R W BTPRR BTPRR7 BTPRR6 BTPRR5 BTPRR4 BTPRR3 BTPRR2 BTPRRI BTPRRO 3 6 4 3 Input signal select register ISL 1 This register is an 8 bit register that controls the timer 0 input noise filter sampling clock selection buzzer output timer PWMH output selection and base timer clock selection Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 B
134. imer OH capture signal input port When set to 1 a timer OH capture signal is generated when an input that satisfies the INT 1 interrupt detection conditions is supplied to P17 If the INTI interrupt detection mode is set to level detection capture signals are generated at an interval of 1 Tcyc as long as the detection level is present at P17 When this bit is set to 0 a timer OH capture signal is generated when an input that satisfies the INT3 interrupt detection conditions is supplied to P15 STOLCP bit 6 Timer OL capture signal input port select This bit selects the timer OL capture signal input port When this bit is set to 1 a timer OL capture signal is generated when an input that satisfies the INTO interrupt detection conditions is supplied to P70 If the INTO interrupt detection mode is set to level detection capture signals are generated at an interval of 1 Tcyc as long as the detection level is present at P70 When this bit is set to 0 a timer OL capture signal is generated when an input that satisfies the INT2 interrupt detection conditions is supplied to P16 BTIMC1 bit 5 Base timer clock select BTIMCO bit 4 Base timer clock select BTIMC1 BTIMCO Base Timer Input Clock 0 Subclock Cycle clock 0 EE Timer counter 0 prescaler output BUZON bit 3 Buzzer output timer 1 PWMH output select When P17FCR PIFCR bit7 is set to 1 this bit selects the data buzzer output or timer 1 PWMH to be sent to
135. imer counter 0 16 bits of data need match in the 16 bit mode 2 The match buffer register is updated as follows The match register matches TOLR when it is inactive TOLRUN 0 When the match register is running TOLRUN 1 it is loaded with the contents of TOLR when a match signal is generated Address Initial value R W Name BIT7 BIT6 BIT5 BIT4 BITS BIT2 BIT1 BITO FE14 0000 0000 R W TOLR TOLR7 TOLR6 TOLRS TOLR4 TOLR3 TOLR2 TOLR1 TOLRO 3 28 LC870G00 Chapter 3 3 4 46 Timer counter 0 match data register high byte TOHR 1 This register is used to store the match data for TOH It has an 8 bit match buffer register A match signal is generated when the value of this match buffer register coincides with the higher order byte of timer counter 0 16 bits of data need match in the 16 bit mode 2 The match buffer register is updated as follows The match register matches TOHR when it is inactive TOHRUN 0 When the match register is running TOHRUN 1 it is loaded with the contents of TOHR when a match signal is generated Address Initial value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE15 0000 0000 R W TOHR TOHR7 TOHR6 TOHR5 TOHR4 TOHR3 TOHR2 TOHRI TOHRO 3 4 4 7 Timer counter 0 capture register low byte TOCAL 1 This register is a read only 8 bit register used to capture the contents of timer counter 0 low byte TOL on an external input detection signal res Pexxx xxx
136. ing the interval between the execution of an instruction that loads the PCON FE07H register and the execution of the next instruction Nointerrupt can occur during the interval between the execution of a RETI instruction and the execution of the next instruction 4 1 Interrupt 6 Interrupt level control Interrupt levels can be selected on a vector address basis Table of Interrupts No Vector Address Selectable Level Interrupt Sources 1 00003H XorL INTO 00013H INT2 TOL INT4 0001BH INT3 Base timer TIL TIH 10 0004BH HorL Port0 VCPWM e Priority levels X gt H gt L e Of interrupts of the same level the one with the smallest vector address takes precedence 7 To enable interrupts and to specify their priority it is necessary to manipulate the following special function registers JE IP Address Initial value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE08 0000 HHOO R W IE IE7 XFLG HFLG LFLG XCNTI XCNTO 4 1 3 Circuit Configuration 4 1 3 1 Master interrupt enable control register IE 6 bit register 1 The master interrupt enable control registers enables and disables H and L level interrupts 2 The interrupt level flag of the register can be read 3 The register selects the level L or X of interrupts to vector addresses 00003H and 0000BH 4 1 3 2 Interrupt priority control register IP 8 bit register 1 The interrupt priority control register selects the
137. is activated and designated as system clock when the HOLD mode is released If OCR3 register bit 1 is set to 0 since OCR register bits 1 4 and 5 are cleared the medium speed RC oscillator is activated and designated as system clock when the HOLD mode is released Since OCRS register bit 6 is cleared the high speed RC oscillator is stopped when the HOLD mode is released CPU and peripheral modules are stopped W HOLD mode release conditions INTO or INT1 level interrupt request generated Request for INT2 INT4 or port 0 interrupt generated Resetting condition established Note 3 W HALT mode entry conditions PCON register FEO7H bit 1 set to 0 and bit 0 to 1 All modes Reset Main clock stopped Subclock stopped Low speed RC oscillator stopped Medium speed RC oscillator started High speed RC oscillator stopped All registers initialized Normal operating mode Note 1 Start stop of oscillators programmable CPU and peripheral modules run in normal mode HALT mode Note 1 All oscillators retain the state established when the HALT mode is entered CPU stopped Peripheral modules keep running W HALT mode release conditions Interrupt request accepted Note 4 Resetting condition established Note 3 LC870G00 Chapter 4 W Reset state release conditions Lapse of predetermined time after resetting conditions are terminated W X tal HOLD mode entry con
138. isticated 16 bit timer counter may be divided into 8 bit timers a 16 bit timer counter may be divided into 8 bit timers or 8 bit PWM modules a 16 bit timer with a prescaler a base timer serving as a time of day clock an asynchronous synchronous SIO interface an 7 channel A D converter with a 12 8 bit resolution selector a 10x 20x amplifier a reference voltage generator circuit 2V 4V for an AD converter a comparator a 8 10 bit High speed PWM 150kHz a 12 bit PWM x 2ch a temperature sensor a system clock frequency divider an internal reset circuit and 15 source 10 vector interrupt feature 1 2 Features mFlash ROM TT Capable of on board programming with a wide range of supply voltages 2 2 to 5 5 V Block erasable in 128 byte units Writes data in 2 byte units 8192 x 8 bits ERAM 256x9 bits E Bus Cycle Time 83 3ns 12MHz VDD 2 7V to 5 5V Ta 40 C to 85 C 125ns MHz VDD 2 0V to 5 5V Ta 40 C to 85 C 250ns 4MHz VDD 1 8V to 5 5V Ta 40 C to 85 C Note The bus cycle time here refers to the ROM read speed Ml Minimum Instruction Cycle Time tCYC 250ns 12MHz VDD 2 7V to 5 5V Ta 40 C to 85 C O 375ns 8MHz VDD 2 0V to 5 5V Ta 40 C to 85 C TT 750ns 4MHz VDD 1 8V to 5 5V Ta 40 C to 85 C MPotrs ll Normal withstand voltage I O ports whose I O direction can be designated in 1 bit units 18 POn P1n P70 CF1 CF2 Reset pins 1 RES Power supply pins 3
139. it bit 0 of the AD conversion results low byte register ADRLC define the conversion time ADRLC ADMRC Register Register AD Frequency Division Ratio Conversion time calculation formulas 12 bit AD conversion mode Conversion time 52 AD division ratio 2 x 1 3 x Tcyc 8 bit AD conversion mode Conversion time 32 AD division ratio 2 x 1 3 x Tcyc Notes The conversion time is doubled in the following cases 1 The AD conversion is carried out in the 12 bit AD conversion mode for the first time after a system reset 2 The AD conversion is carried out for the first time after the AD conversion mode is switched from 6 bit to 12 bit AD conversion mode The conversion time determined by the above formula is taken in the second and subsequent conversions or in the AD conversions that are carried out in the 8 bit AD conversion mode 3 66 LC870G00 Chapter 3 3 8 4 3 AD conversion results low byte register ADRLC 1 The AD conversion results low byte register is used to hold the lower order 4 bits of the results of an AD conversion carried out in the 12 bit AD conversion mode and to control the conversion time 2 Since the data in this register is not established during an AD conversion the conversion results must be read out only after the AD conversion is completed Address Initial value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FESA 0000 0000 R W ADRLC DATAL3 DATAL2 DA
140. ium speed RC oscillator is activated and designated as system clock when the HOLD mode is released Since OCR3 register bit 6 is cleared the high speed RC oscillator is stopped when the HOLD mode is released e Reset Main clock stopped JSubclock stopped Low speed RC oscillator stopped Medium speed RC oscillator started High speed RC oscillator stopped e Normal operating mode Note 1 Start stop of oscillators programmable e HALT mode Note 1 DAI oscillators retain the state established when HALT mode is entered System Clock e X tal HOLD Note 1 Main clock low medium and high speed RC oscillators are stopped Subclock retains the state established when X tal HOLD mode is entered Note 3 Contents of OCR and OCR3 registers remain unchanged CPU enters this mode after selecting subclock low medium or high speed RC oscillator as system clock source When X tal HOLD mode is released the oscillators return to the state established when the X tal HOLD mode is entered Note 1 The oscillation of the low speed RC oscillator circuit is controlled directly by the watchdog timer Its oscillation is also controlled in the standby mode See Section 4 6 Watchdog Timer for details Note 2 When the Hold mode is released low sped RC oscillator or medium speed RC oscillator automatically resumes oscillation and is set to be the system clock according to the value of oscillation control
141. ividing the cycle clock by 2 or external events while T1H functions as an 8 bit programmable timer that counts the number of signals obtained by dividing the cycle clock by 2 Two independent 8 bit programmable timers T1L and T1H run on a clock that is obtained by dividing the cycle clock by 2 TIPWML and TIPWMH generate a signal that toggles at the interval of TIL and T1H period respectively Note 1 TIL period TILR 1 x TILPRC count x 2Tcyc or T1LR 1 x TILPRC count events detected TIPWML period TIL period x 2 T1H period T1HR 1 x TIHPRC count x 2Tcyc TIPWMH period T1H period x 2 Mode 1 Two channels of 8 bit PWM with an 8 bit prescaler Two independent 8 bit PWMs TIPWML and TIPWMH run on the cycle clock TIPWML period 2256 x TILPRC count x Tcyc TIPWML low period T1LR 1 x TILPRC count x Tcyc TIPWMH period 256 x TIHPRC count x Tcyc TIPWMH low period T1HR 1 x TIHPRC count x Tcyc Mode 2 16 bit programmable timer counter with an 8 bit prescaler with toggle output the lower order 8 bits may be used as a timer counter with toggle output A 16 bit programmable timer counter runs that counts the number of signals whose frequency is equal to that of the cycle clock divided by 2 or the number of external events Since interrupts can occur from the lower order 8 bit timer T1L at the interval of TIL period the lower order 8 bits of this 16 bit programmable timer counter can be used as the refere
142. ixed to low level 3 84 LC870G00 Chapter 3 3 11 3 Circuit Configuration 3 11 3 1 HPWM 2 control register HPWM2AC 8 bit register 1 The HPWM2 control register controls the operation of the internal high speed RC and the operation and interrupts of HPWM2 2 H2ARLBSY HPWM2AC bit2 is read only bit 3 11 3 2 HPWM2 compare register L HPWM2AL 4 bit register The HPWM2 compare register L controls the additional pulses of HPWM2 and the function outputs of P17 and P16 3 11 3 3 HPWM2 compare register H HPWM2AH 8 bit register The HPWM2 compare register H controls the fundamental pulse width of HPWM2 3 11 3 4 HPWM2 compare data buffer register HPWM2BR 10 bit buffer register The HPWM2 compare data buffer register is used to store the setting data of the puls width of HPWM2 The data of HPWM2AH HPWM2AL bits 7 to 6 is stored to this register The update of the buffer register is carried out as follows e When HPWM2 is not operating H2ARUN 0 the data of HPWM2BR will be equal to the data of IHPWM2AH HPWM2AL bits 7 to 6 When HPWM2 is operating H2ARUN 1 when HPWM2AH is written reload wait flag H2ARLBSY is set and writing to HPWM2AL bits 7 to 6 and HPWM2AH is inhibited In this state when an overflow signal of the next PWM period fundamenta period at 8 bit PWM mode overall period at 10 bit mode is generated the data of HPWM2AH HPWM2AL bits 7 to 6 is reloaded to HPWM2BR and H2ARLBSY is cleared Note 2 Note2
143. ized to 0000H on a reset The SP is incremented by 1 before data is saved in stack memory and decremented by 1 after the data is restored from stack memory Address Initial value R W Name BIT7 BIT6 BITS BIT4 BIT3 BIT2 BIT1 BITO FEOA 0000 0000 R W SPL SP7 SP6 SP5 SP4 SP3 SP2 SP1 SPO The value of the SP changes as follows When the PUSH instruction is executed SP SP 1 RAM SP DATA lt 2 gt When the CALL instruction is executed SP SP 1 RAM SP ROMBANK ADL SP SP 1 RAM SP ADH lt 3 gt When the POP instruction is executed DATA RAM SP SP SP 1 lt 4 gt When the RET instruction is executed ADH RAM SP SP SP 1 ROM BANK ADL RAM SP SP SP 1 2 10 Indirect Addressing Registers The LC870000 series microcontrollers are provided with three addressing schemes Rn Rn C off that use the contents of indirect registers indirect addressing modes See Section 2 11 for the addressing modes Used for these addressing modes are 64 2 byte indirect registers RO to R63 allocated to RAM addresses 0 to 7EH The indirect registers can also be used as general purpose registers e g for saving 2 byte data Naturally these addresses can be used as ordinary RAM on a 1 byte 9 bits basis if they are not used as indirect registers RO to R63 are system reserved words to the assembler and need not be defined by the user 2 5 2 11 Address 7FH 7EH RO lower
144. k 4 26 LC870G00 Chapter 4 WDTRUN bit 5 WDT operation control Setting this bit to 0 stops the WDT operation Setting this bit to 1 starts the WDT operation IDLOP 1 bit 4 WDT standby mode operation selection IDLOPO bit 3 IDLOP1 IDLOPO WDT sem Mode oe pud en ee di Suspend count operation while retaining the count value See Figure 4 6 2 for details of the WDT operating modes WDTSL2 bit 2 WDTSL1 bit 1 Overflow time select WDTSLO bit 0 WDTCT set count number and overflow WDTSL2 WDTSL1 WDTSLO generation time example Count Low speed RC number clock pubelock 1024 34 13ms 31 25ms 2048 68 26ms 62 50ms 4096 136 5ms 125 0ms 8192 273 0ms 250 0ms 16384 546 1ms 500 0ms 32768 1 092ms 1 000s 65536 2 184ms 2 000s 131072 4 368s 4 000s Time values in the Low speed RC clock column of the table refer to the time for a WDTCT overflow to occur when the low speed RC oscillation frequency is 30 kHz typical The low speed RC oscillation frequency varies from IC to IC For details refer to the latest SANYO Semiconductor Data Sheet Time values in the Subclock column of the table refer to the time a WDTCT overflow to occur when the 32 768 kHz X tal oscillator is used Note The WDTCNT is initialized with 00H when a low level signal is applied to the external RES pin Or a reset is triggered by the internal reset POR LVD function Bit 6 and bits 4 to 0 of the WDTCNT are not initi
145. k The bit length of the base timer can be specified using the base timer control register BTCR 4 Buzzer output function The signal generated by frequency dividing the output of a programmable prescaler by 8 can be used as the buzzer signal The control mode of the buzzer output can be specified using the input signal select register ISL The buzzer output HPWM2 shares an output pin and can be transmitted via pin 17 5 Interrupt generation An interrupt request to vector address 001BH is generated if an interrupt request is generated by the base timer when the interrupt request enable bit is set The base timer can generate two types of interrupt requests base timer interrupt 0 and base timer interrupt 1 6 X tal HOLD mode operation and X tal HOLD mode releasing The base timer is enabled for operation in the X tal HOLD mode by selecting the subclock or low speed RC oscillator clock as the base timer count clock source and setting bit 2 of the power control register PCON The X tal HOLD mode can be released by an interrupt from the base timer This function allows the microcontroller to perform low current intermittent operations 7 To control the base timer it is necessary to manipulate the following special function registers BTCR BTPRR ISL P1 PIDDR PIFCR HPWM2AL Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE7F 0000 0000 R W BTCR BTFST BTON BTC11 BTCIO BTIF1 BTIEI BTIFO BTIEO
146. l register The conversion results are placed in the AD conversion results register ADRHC ADRLC 3 8 8 3 Multiplexer 1 MPX1 1 Multiplexer 1 is used to select the analog signal to be subject to AD conversion from 8 channels of analog signals 3 8 8 4 Automatic reference voltage generator circuit 1 The reference voltage generator circuit consists of a network of ladder resistors and a multiplexer MPX2 and generates the reference voltage that is supplied to the comparator circuit Generation of the reference voltage 1s automatically started when an AD conversion starts and stopped when the conversion ends The reference voltage output ranges from reference voltage to VSS AD conversion reference voltage source can be selected from VDD internal VREF external voltage source See 3 9 Reference Voltage Generator Circuit VREF for the internal VREF 3 8 4 Related Registers 3 8 4 1 AD converter control register ADCRC 1 The AD converter control register is an 8 bit register that controls the operation of the AD converter Initial value BIT7 BIT5 BIT4 AD AD AD CHSEL3 CHSEL1 CHSELO 0000 0000 ADCHSEL3 bit 7 ADCHSEL2 bit 6 ADCHSEL1 bit 5 ADCHSELO bit 4 AD conversion input signal select These 4 bits are used to select the signal to be subject to AD conversion Signal Input Pin 10x 20x amplifier PO2 AN2 PO3 AN3 P04 ANA P15 AN5 P14 AN6 P13 AN7 P70 AN9 LC870G00 Chapter
147. lation inverter e CF oscillation inverter e State established e Oscillation not output general purpose output general purpose on entry into started input output selected by input is in the state HOLD mode bit 3 of register XT2PC established on entry into FE43H HOLD mode Oscillation enabled or disabled by register OCR FEOEH e Feedback resistors e Feedback resistor e Feedback resistor between for CF and XT are between CF1 and CF2 CFI and CF2 is in the state POO P06 e Input mode e Input output pull up e Pull up resistor off resistor controlled by a program P10 P17 e Input mode e Input output pull up e Pull up resistor off resistor constant current mode controlled by a program P20 P27 eInput mode Input output pull up resistor constant current e Pull up resistor off mode controlled by a program P70 Input mode e Input output pull up Input mode Normal operating resistor controlled by a mode e Pull up resistor off e Pull up resistor off program 4 18 W Reset state entry conditions Low level applied to RES pin Reset signal generated by internal reset function POR LVD Reset signal generated by watchdog timer W HOLD mode entry conditions PCON register FEO7H bit 2 set to O and bit 1 to 1 HOLD mode Note 1 All oscillators stopped If OCRG register bit 1 is set to 1 since OCRG register bit 0 is set and OCR register bits 4 and 5 are cleared the low speed RC oscillator
148. level H or L of interrupts to vector addresses 00013H to 0004BH 4 2 LC870G00 Chapter 4 4 1 4 Related Registers 4 1 4 1 Master interrupt enable control register IE 1 The master interrupt enable control register is a 6 bit register for controlling the interrupts Bits 6 to 4 of this register are read only Address Initial value R W Name BIT7 BIT6 BIT5 BIT4 BITS BIT2 BIT1 BITO FE08 0000 HH00 R W IE IE7 XFLG HFLG LFLG XCNT1 XCNTO IE7 bit 7 H L level interrupt enables disables control e A 1 in this bit enables H and L level interrupt requests to be accepted e Ain this bit disables H and L level interrupt requests to be accepted e X level interrupt requests are always enabled regardless of the state of this bit XFLG bit 6 X level interrupt flag R O This bit is set when an X level interrupt is accepted and reset when execution returns from the processing of the X level interrupt This bit is read only No instruction can rewrite the value of this bit directly HFLG bit 5 H level interrupt flag R O This bit is set when an H level interrupt is accepted and reset when execution returns from the processing of the H level interrupt This bit is read only No instruction can rewrite the value of this bit directly LFLG bit 4 L level interrupt flag R O This bit is set when an L level interrupt is accepted and reset when execution returns from the processing of the L level interrupt
149. llows TILR and the match register has the same value when in inactive TILRUN 0 If active TILRUN 1 the match buffer register is loaded with the contents of TILR when the value of TIL reaches 0 Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FEIC 00000000 R W TILR TILR7 TILR6 TILRS TILR4 TILR3 TILR2 TILRI TILRO 3 5 4 6 Timer 1 match data register high byte T1HR 1 Thisregister is used to store the match data for T1H It has an 8 bit match buffer register A match signal is generated when the value of this match buffer register coincides with the value of timer 1 high byte 2 The match buffer register is updated as follows T1HR and the match register has the same value when in inactive TIHRUN 0 If active TI HRUN 1 the match buffer register is loaded with the contents of TIHR when the value of T1H reaches 0 Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FEID 00000000 R W TIHR TIHR7 TIHR6 TIHRS TIHR4 TIHR3 TIHR2 TIHRI TIHRO 3 41 Match buffer register value Mode 0 2 I p E ER Match signal Interrupt flag set T1PWML T1PWMH FFH Counter value E z LL n D z o o a T D us c S amp o pm d I o o o S t g o E TT Ka 2 o a t o E E O E Mode 1 3 42 LC870G00 Chapter 3 FFH Ma
150. n 0 OOU000 Q Oscillation Internal Stop oscillation internal RC s low speed RC oscillation oscillator circuit control circuit Write WDTCNT Low speed RC oscillation clock MOV 55H WDTCNT write instruction detector circuit Clock WDT counter Reset b gt oom E O 0 00000 Stop clock 00000 0 000000 WDT t i Set rese n 000000 n WDTRUN clear signal generator WDT reset circuit WDTRSTF set signal 0000 00 O G Standby mode o 000000 op 00 00 O WDTRUN clear signal Enter standby mode DU nana WDTRUN clear signal WDT reset ne WDTRSTF set signal 0000 00 M00 Dana Enter HOLD mode Figure 4 5 1 Watchdog Timer Block Diagram 4 25 WDT Operation performed when IDLOP1 0 are set to 0 or 3 continue count operation Overflow V WDTSL2 0 set count value e WDTCT Count value 0 Time set in WDTSL2 0 A A A WDT operation start MOV 55H WDTCNT WDT reset signal generated WDTRUN 1 instruction executed WDTRUN cleared to 0 Low speed RC WDTCT cleared to 0 WDTRSTF set to 1 oscillator start Note Low speed RC oscillator stopped Operation performed when IDLOP1 0 are set to 1 suspend operation Standby mode entered V WDTSL2 0 set count value WDTCT Count value 0 WDT operation start WDTRUN cleared to 0 WDTRUN 1 Low speed RC Low speed RC oscillator stopped oscillator start Note Note Operation performed when IDLOP1 0 are set to 2 s
151. n e Stopped e State established at entry e Stopped e State established at entry time time Low speed RC e Stopped e State established at entry e Stopped Note 1 e Stopped Notes 1 2 oscillation time Note 1 Medium speed RC e Running e State established at entry e Stopped e Stopped oscillation time High speed RC e Stopped e State established at entry e Stopped e Stopped oscillation time e Initialized e Stopped e Stopped e Stopped a e See Table 4 42 RAM e RES Unpredictable e Data preserved e Data preserved e Data preserved e LVD Unpredictable or data preserved depends on supply voltage e When watchdog timer reset Data preserved Base timer e Stopped e State established at entry e Stopped e State established at entry time time Peripheral modules e Stopped e State established at entry e Stopped e Stopped except base timer time Note 3 Exit conditions e Entry conditions e Interrupt request e Interrupt request from e Interrupt request from canceled accepted INTO INT1 INT2 INT4 INTO INT1 INT2 INT4 e Reset entry conditions and port 0 port O and base timer established e Reset entry conditions e Reset entry conditions established established e Normal mode Note 4 e HALT Note 4 e HALT Note 4 Data changed on exit e None PCON register bit 0 is e PCON register bit 1 is e PCON register bit 1 is cleared cleared cleared Note 1 The oscillation of the low speed RC oscillation circuit is controll
152. n only when the disuse of the low voltage detection reset function is selected It is necessary to use the undermentioned low voltage detection reset function together with this function or configure an external reset circuit if there are possibilities that chatter can occur or a momentary power loss occur at power on time 2 Low voltage detection reset LVD function This function when used together with the POR function can generate a reset when power is turned on and when the power level lowers As a user option the use or disuse and the detection level of this function can be specified 4 6 3 Circuit Configuration The internal reset circuit consists of POR LVD pulse stretcher circuit capacitor Cres discharging transistor external capacitor Cres pull up resistor Regs or pull up resistor Rggs alone The circuit diagram of the internal reset circuit is given in Figure 4 6 1 Pulse stretcher circuit The pulse stretcher circuit stretches the POR and LVD reset signals It is used to stretch the internal reset period and discharge the external capacitor Cggs connected to the RESET pin The stretching time is from 30 us to 100 us e Capacitor Cres discharging transistor This is an N channel transistor used to discharge the external capacitor Core connected to the RESET pin If the capacitor Core is not to be connected to the RESET pin it is possible to monitor the internal reset signal by connecting only the external pull up resisto
153. n systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application Buyer shall indemnify and hold SCILLC and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part SCILLC is an Equal Opportunity Affirmative Action Employer This literature is subject to all applicable copyright laws and is not for resale in any manner Contents Chapter MESI QV BRL LDAP 1 1 1 1 Overview a B9 1 1 1 2 Features eee eee eee eee eee eee eee eee eee eee eee eee eee ee ere eee eee ee ee ee ee ree 1 1 1 3 Pin Assignment eee eee eee ee eee eee ee eee ee eee eee eee eee eee ree eee eee eee ee 1 6 1 4 System Block Diagram X ee 1 7 1 5 Pin Description eee eee ere reer eee eee eee eee eee eee eee eee eee eee eee eee eee 1 8 1 6 On chip Debugger Pin Connection Requirements ees 1 10 1 7 Recommended Unused Pin Connections its 1 10 1 8 Port Output Types eee eee eee eee eee e
154. nce timer TIPWML and TIPWMH generate a signal that toggles at the interval of TIL and T1 periods respectively Note 1 3 32 LC870G00 Chapter 3 TIL period T1LR 1 x TILPRC count x 2Tcyc or TILR 1 x TILPRC count events detected TIPWML period TIL period x 2 T1 period TIHR 1 x TIHPRC count x TIL period or TIHR 1 x TIHPRC count x TILR 1 x TILPRC count events detected TIPWMH period T1 period x 2 4 Mode3 16 bit programmable timer with an 8 bit prescaler with toggle output the lower order 8 bits may be used as a PWM A 16 bit programmable timer runs on the cycle clock The lower order 8 bits run as a PWM TIPWML having a period of 256 Tcyc TIPWMH generates a signal that toggles at the interval of T1 period Note 1 TIPWML period 2256 x TILPRC count x Tcyc TIPWML low period T1LR 1 x TILPRC count x Tcyc T1 period T1HR 1 x TIHPRC count x TIPWML period TIPWMH period T1 period x 2 5 Interrupt generation TIL or T1H interrupt request is generated at the counter period of the TIL or T1H timer if the interrupt request enable bit is set 6 To control timer 1 T1 it is necessary to manipulate the following special function registers TICNT TIL TIH TILR TIHR TIPRR PI PIDDR PIFCR I45CR I45SL Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BITS BIT2 BIT1 BITO FE18 0000 0000 R W TICNT TIHRUN TILRUN TILONG TIPWM TIHCMP TIHIE TILC
155. nction A count signal is sent to timer 1 each time a signal change such that the interrupt flag is set is supplied to the port selected from P14 and P13 3 6 LC870G00 Chapter 3 8 HOLD mode release function When the interrupt flag and interrupt enable flag are set by INTO P70 INT1 P17 INT2 P16 or INT4 P14 or P13 a HOLD mode release signal is generated releasing the HOLD mode The CPU then enters the HALT mode main oscillation by CR When the interrupt is accepted the CPU switches from the HALT mode to normal operating mode The interrupt flag cannot be set however by a rising edge occurring when INT2 P16 data which is established when the HOLD mode is entered is in the high state or by a falling edge occurring when P16 data which is established when the HOLD mode is entered is in the low state Consequently to release the HOLD mode with P16 it is recommended that P16 be used in the double edge interrupt mode 9 Multiplexed pin function P17 is also used as the HPWM2 or base timer buzzer output P16 as the timer HPWM2 output or comparator output pins P13 to P15 as AD input channel AN7 to ANS and P12 to P10 for SIO1 I O Interrupt Input Signal Timer Count Hold Mode Prine 9 Capture Input Output P Detection Input Release CMOS N channel L level H level Timer OH Enabled programmable pen drain L edge H edge Note Timer 1 Timer OL H Enabled Timer OI H Enabled Note HOLD mode of P17 can
156. nd 2 all bits of this register can be read or written Address Initial value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FEOE 0000 XX00 R W OCR CLKSGL EXTOSC CLKCB5 CLKCB4 XT2IN XTIIN RCSTOP CFSTOP CLKSGL bit 7 System clock division ratio select 1 When this bit is set to 1 the clock selected by bits 4 and 5 is used as the system clock as is 1 2 When this bit is set to 0 the clock having a clock rate of 5 ofthe clock selected by bits 4 and 5 is used as the system clock EXTOSC bit 6 CF1 XT1 and CF2 XT2 function control 1 When this bit and CFSTOP bit 0 are set to 1 the CF1 XT1 and CF2 XT2 pins serve as the pins for subclock oscillation and get ready for oscillation when a crystal oscillator 32 768 kHz standard capacitors and damping resistors are connected When the OCR register is read in this case bit 3 reads the data at the CF2 XT2 pin and bit 2 reads 0 2 When this bit is set to O and XTCFSEL XT2PC register bit 3 is set to 1 the CFI XTI and CF2 XT2 pins serve as the pins for main clock oscillation and get ready for oscillation when a ceramic oscillator capacitors feedback resistors and damping resistors are connected When the OCR register is read in this case bit 3 reads the data at the CF2 XT2 pin and bit 2 reads the data at the CFI XTI pin CLKCBS bit 5 System clock select CLKCBA bit 4 System clock select 1 CLKCBS and CLKCB4 are used to select the system clock 2 CLKCBS a
157. nd CLKCBA are cleared at reset time or when the HOLD mode is entered CLKCB5 CLKCBA System clock RC clock High speed clock 0 0 AA 1 9 tae See Figure 4 2 1 for details 4 10 LC870G00 Chapter 4 XT2IN bit 3 CF2 XT2 data read only XTIIN bit 2 CFI XTI data read only 1 Data that can be read via XT2IN and XTIIN varies as shown in the table below according to the value of EXTOSC bit 6 EXTOSC XT2IN XT1IN 0 CF2 XT2 pin data CFI XTI pin data RCSTOP bit 1 Medium speed RC oscillator circuit control 1 Setting this bit to 1 stops the oscillation of the medium speed RC oscillator circuit 2 Setting this bit to O starts the oscillation of the medium speed RC oscillator circuit 3 When a reset occurs this bit is cleared and the RC oscillator circuit is enabled for oscillation 4 When the microcontroller enters the HOLD mode this bit is set as described below according to the value of bit 1 of the OCR3 register f OCR3 register bit 1 is set to 0 this bit is cleared and the oscillator starts oscillation and the medium speed RC oscillator is designated as the system clock source when the microcontroller exits the HOLD mode If OCR3 register bit 1 is set to 1 the state of this bit remains unchanged CFSTOP bit 0 CF oscillator circuit control 1 Setting this bit to 1 stops the CF oscillator circuit 2 Setting this bit to O starts the CF oscillator circuit 3 When a res
158. nd TOH Address Initial value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE10 0000 0000 R W TOCNT TOHRUN TOLRUN TOLONG TOLEXT TOHCMP TOHIE TOLCMP TOLIE TOHRUN bit 7 TOH count control When this bit is set to 0 timer counter 0 high byte TOH stops on a count value of 0 The match buffer register of TOH has the same value as TOHR When this bit is set to 1 timer counter 0 high byte TOH performs the required counting operation The match buffer register of TOH is loaded with the contents of TOHR when a match signal is generated TOLRUN bit 6 TOL count control When this bit is set to 0 timer counter 0 low byte TOL stops on a count value of 0 The match buffer register of TOL has the same value as TOLR When this bit is set to 1 timer counter 0 low byte TOL performs the required counting operation The match buffer register of TOL is loaded with the contents of TOLR when a match signal is generated TOLONG bit 5 Timer counter 0 bit length select When this bit is set to 0 timer counter 0 s higher and lower order bytes serve as independent 8 bit timers counters When this bit is set to 1 timer counter 0 functions as a 16 bit timer counter A match signal is generated when the count value of the 16 bit counter comprising TOH and TOL matches the contents of the match buffer register of TOH and TOL TOLEXT bit 4 TOL input clock select When this bit is set to 0 the count clock for TOL is the match
159. need to match in the 16 bit mode 2 The match buffer register is updated as follows The match register matches TOHR when it is inactive TOHRUN 0 When the match register is running TOHRUN 1 it is loaded with the contents of TOHR when a match signal is generated 3 4 8 8 Timer counter 0 capture register low byte TOCAL 8 bit register 1 Capture clock External input detection signal from the P70 INTO TOLCP P16 INT2 TOIN P13 and P14 timer OL capture input pins when TOLONG timer 0 control register bit 5 is set to 0 External input detection signal from the P17 INTI TOHCP P15 INT3 TOIN P13 and P14 timer OH capture input pins when TOLONG timer 0 control register bit 5 is set to 1 2 Capture data Contents of timer counter 0 low byte TOL 3 4 3 9 Timer counter 0 capture register high byte TOCAH 8 bit register 1 Capture clock External input detection signals from the P17 INT1 TOHCP P15 INT3 TOIN P13 and P14 timer OH capture input pins 2 Capture data Contents of timer counter 0 high byte TOH Table 3 4 1 Timer 0 TOH TOL Count Clocks Mode TOLONG TOLEXT TOH Count Clock TOL Count Clock TOH TOL Count Clock 0 0 0 TOPRR match signal TOPRR match signal GE le AA TOPRR match signal External signal EA AAA TPR cg EO T d O Bemmisgmb 3 24 LC870G00 Chapter 3 Clock Clear To SD Fee Capture trigger Comparar gt Registers I01CR FE5Dh 123CR FE5Eh and ISL
160. nput this bit must be set to 0 ANGIEZ bit 1 Analog input P14 AN6 port digital input function disable control When P14 AN6 is used as an analog input this bit should be set to 1 When P14 AN6 is not used as an analog input this bit must be set to 0 ANBIEZ bit 0 Analog input P15 AN5 port digital input function disable control When P15 AN5 is used as an analog input this bit should be set to 1 When P15 ANS is not used as an analog input this bit must be set to 0 3 9 3 4 10x 20x Amplifier Control Register APCNT The APCNT register is used to control the operation of the operational amplifier with a gain of 10x 20x Address Initial value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FEC3 00H0_H000 R W APCNT APON GAIN20 FIXO APDIR APMDI APMDO APON bit 7 10x 20x operational amplifier operation control Setting APON to 1 and VR12ON to starts the operation of the 10x 20x operational amplifier The output voltage of the amplifier can be measured by performing AD conversion on AD converter s analog channel 0 ANO when the amplifier is running Provided that When APDIR bit2 is set to 0 Voltage level at POO S Voltage level at PO1 When APDIR bit2 is set to 1 Voltage level at PO0 z Voltage level at P0O1 3 73 Reference Voltage Generator Circuit GAIN20 bit 6 10x 20x operational amplifier gain control Setting this bit to O set the gain of operational amplifier 10x Setting this bit t
161. ns are established The CPU cannot return from the HALT mode since no interrupt request can be accepted unless its interrupt level is higher than the interrupt level that placed the CPU into the HALT HOLD or X tal HOLD mode Figure 4 3 1 Interrupt request level that can release HALT HOLD or X tal HOLD mode HALT mode Standby Mode State Transition Diagram 4 19 Watchdog timer 4 20 LC870G00 Chapter 4 4 4 Reset Function 4 4 1 Overview The reset function initializes the microcontroller when it is powered on or while it is running 4 4 2 Functions This series of microcontrollers provides the following three types of resetting function 1 External reset via the RES pin e The microcontroller is reset without fail by applying and holding a low level to the RES pin for 200us or longer Note however that a low level of a small duration less than 200us is likely to trigger a reset The RES pin pin can serve as a power on reset pin when it is provided with an external time constant element 2 Internal reset The internal reset function is available in two types the power on reset POR that triggers a reset when power is turned on and the low voltage detection reset LVD that triggers a reset when the power voltage falls below a certain level Options are available to set the power on reset release level to Enable use and Disable disuse the low voltage detection reset function and its threshold level 3 I
162. nternal pull up resistor Options are available to Enable use and Disable disuse the internal pull up resistor for the RES pin 4 Reset function using a watchdog timer The watchdog timer of this series of microcontroller can be used to generate reset by the internal low speed RC oscillator or the subclock at a predetermined time intervals An example of a resetting circuit is shown in Figure 4 4 1 The external circuit connected to the reset pin shows an example that the internal reset function is disabled and an external power on reset circuit is configured Interior of microcontroller Exterior of microcontroller Watchdog timer WDT Internal Sync circuit reset signal Internal pull up resistor 1 Internal reset option circuit POR LVD Figure 4 5 1 Sample Reset Circuit Block Diagram 4 21 Reset 4 4 3 Reset State When a reset is generated by the RES pin internal reset circuit or watchdog timer the hardware functional blocks of the microcontroller are initialized by a reset signal that is in synchronization with the system clock Since the system clock is switched to the internal medium speed RC oscillator when a reset occurs hardware initialization is also carried out immediately even at power on time After the hardware reset if the main clock is to be used enable the oscillation of the main clock and switch the system clock to the main clock after the oscillation gets stabilized The
163. ntervals determined by the prescaler count T1HPRE TIHPRC2 T1HPRC1 T1HPRCO T1H Prescaler Count 0 m Ei 1 1 0 0 0 2 1 0 0 1 4 1 0 1 0 8 1 0 1 1 16 1 1 0 0 32 1 1 0 1 64 1 1 1 0 128 1 1 1 1 256 4 Reset When the timer 1 stops operation or a T1H reset signal is generated 3 5 3 5 Timer 1 low byte T1L 8 bit counter 1 Start stop The start stop of the timer 1 low byte is controlled by the 0 1 value of TILRUN timer 1 control register bit 6 2 Countclock TIL prescaler output clock 3 Match signal A match signal is generated when the count value matches the value of the match buffer register 4 Reset The timer 1 low byte is reset when it stops operation or a match signal occurs on the mode 0 or 2 condition 3 5 3 6 Timer 1 high byte T1H 8 bit counter 1 Start stop The start stop of the timer 1 high byte is controlled by the 0 1 value of TIHRUN timer 1 control register bit 7 2 Countclock T1H prescaler output clock 3 Matchsignal A match signal is generated when the count value matches the value of the match buffer register 4 Reset The timer 1 high byte is reset when it stops operation or a match signal occurs on the mode 0 2 or 3 condition 3 35 3 5 3 8 2 3 5 3 9 2 3 3 5 3 10 2 3 Timer 1 match data register low byte T1LR 8 bit register with a match buffer register This register is used to store the match data for TIL It has an 8 bit match buffer register A match signal is
164. ntrol This bit is used to select the interval at which base timer interrupt 0 is to occur If this bit is set to 1 the base timer interrupt 0 flag is set when an overflow occurs in the 6 bit counter The interval at which overflows occur is 64tBST If this bit is set to 0 the base timer interrupt 0 flag is set when an overflow occurs in the 14 bit counter The interval at which overflows occur is 16384tBST This bit must be set to 1 when the high speed mode is to be used ES Is the period of the input clock to the base timer that is selected by BTPRR set value 1 x BTIMCI 0 ISL bits 5 4 BTON bit 6 Base timer operation control When this bit is set to 0 the base timer stops operation when a count value of 0 is reached When this bit is set to 1 the base timer continues operation BTC11 bit 5 Base timer interrupt 1 period control BTC10 bit 4 Base timer interrupt 1 period control Base Timer Interrupt 0 Base Timer Interrupt 1 Period Period 16384tBST 32BST o ee E 16384tBST 1281BST Ss pe gp EA 16384tBST 512tBST po 1 1 AJl S8BST 2048BST pp mel ro e AONBSTS X A oi 1 T emo O poto 1 0 6uBST 2BST BTIF1 bit 3 Base timer interrupt 1 flag This flag is set at the interval equal to the base timer interrupt 1 period that is defined by BTFST BTC11 and BTC10 This flag must be cleared with an instruction BTIE1 bit 2 Bas
165. o 1 set the gain of operational amplifier 20x bit 4 Test bit Must always be set to 0 APDIR APMD1 APMDO bit 2 1 0 10x 20x operational amplifier input switch control These bits are used to control the switches for the amplifier inputs so that the AD converter can be used to measure the 10x 20x amplified voltage between pins POO and DOT and the offset voltage of the amplifier itself Register Data Amplifier Input Switch Amplifier Output APDIR APMD1 APMDO SW1 SW2 SW3 SW4 OFF OFF OFF OFF OFF X 0 0 1 ON OFF O OFF 10x 20X voltage between POO and DOT including offset FE OSS TN 1 OFF ON O 10x 20 X voltage between POO and DOT including offset UI UE EI eo Ct O OFF ON EE x 3 o ew or ON ON ON Amplifier s offset voltage when POO is set to GND FF N FF FF ON OFF ON ON OFF Amplifier s offset voltage when PO1 is set to GND POO side input 1 pA SWS 10x 20X amplifier To AD converter PO side input 3 9 3 5 Reference Voltage 4 0V Adjustment Register VR4AJ The reference voltage 4 0V adjustment register is used to adjust the VREF4 0V level Address Initial value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FEC6 XXXX XXXX R W VR4AJ VR4AJ7 VR4AJ6 VR4AJS VR4AJ4 VR4AJ3 VR4AJ2 VR4AJ1 VR4AJO No access must be made to this register 3 9 4 HALT and HOLD Time Operation In the HALT or HOLD mode the VREF and AMP
166. ocontrollers except the CPU core RAM and ROM Port block diagrams are provided in Appendix II for reference Port 0 3 1 1 Overview Port 0 is an 7 bit I O port equipped with programmable pull up resistors It is made up of a data latch a data direction register and a control circuit Control of the input output signal direction is accomplished through the data direction register in 1 bit units This port can also serve as a pin for external interrupts and can release the HOLD mode As a user option either CMOS output with a programmable pull up resistor or N channel open drain output with a programmable pull up resistor can be selected as the output type on a bit basis Notes on the flash ROM version Do not apply a clock or low vololtage level or any medium voltage level signal to the port OWPO For the treatment of the on chip debugger pins refer to the separately available documents entitled RD87 On chip Debugger Installation Manual and LC870000 Series On chip Debugger Pin Processing 3 1 2 Functions 1 Input output port 7 bits POO PO6 The port output data is controlled by port 0 data latch PO FE40 and the I O direction is controlled by the port 0 direction register PODDR FE41 Each port bit is provided with a programmable pull up resistor 2 Interrupt pin function POFLG POFCR FE42 bit 5 is set when an input port is specified and O level data is input to one of port bits whose corresponding bit in
167. ombination error use only the valid part of the conversion data selected according to the specifications given in the latest SANYO Semiconductors Data Sheet Pass the above read data to the application software processing Return to step 4 to repeat the conversion processing 3 68 3 8 6 1 2 3 4 5 6 7 8 9 LC870G00 Chapter 3 Hints on the Use of the ADC The conversion time that the user can select varies depending on the frequency of the cycle clock When preparing a program refer to the latest SANYO Semiconductors Data Sheet to select an appropriate conversion time Setting ADSTART to 0 while conversion is in progress will stop the conversion function Do not place the microcontroller in the HALT or HOLD mode while AD conversion processing is in progress Make sure that ADSTART is set to O before putting the microcontroller in the HALT or HOLD mode ADSTART is automatically reset and the AD converter stops operation if a reset is triggered while AD conversion processing is in progress When conversion is finished the end of AD conversion flag ADENDF is set and at the same time the AD conversion operation control bit ADSTART is reset The end of conversion condition can be identified by monitoring ADENDF Setting ADIE causes an interrupt request to vector address 0043H to be generated at the end of conversion The conversion time 1s doubled in the following cases The AD conv
168. or Oscillator System Clock Medium speed RC oscillator Normal mode Programmable Programmable Programmable Programmable Programmable Programmable HALT State established State established State established State established State established State established at entry time at entry time at entry time at entry time at entry time at entry time Reset Stopped Stopped Stopped Running Stopped HOLD Stopped Stopped Stopped Stopped Stopped Stopped Immediately Low or after exit from siu ME RAE Running Note 2 Running Note 2 Stopped medium speed HOLD mode ac ey ume SET une RC oscillator X tal HOLD Stopped State established Stopped Note 3 Stopped Stopped Stopped pp at entry time pp pp pp pp Immediately after exit from State established State established State established State established State established State established X tal HOLD at entry time at entry time at entry time at entry time at entry time at entry time mode Note See Section 4 3 Standby Function for the procedures to enter and exit the microcontroller operating modes 4 5 e HOLD mode Note 1 JAII oscillators stopped If OCR3 register bit 1 is set to 1 since OCR3 register bit O is set and OCR register bits 4 and 5 are cleared the low speed RC oscillator is activated and designated as system clock when the HOLD mode is released If OCR3 register bit 1 is set to 0 since OCR register bits 1 4 and 5 are cleared the med
169. pen Output low P10 to P17 Open Output low P70 Open Output low CF1 XT1 Open General I O port output low CF2 XT2 Open General UO port output low OWPO Pulled low with a 100k resistor 1 8 Port Output Types The table below lists the types of port outputs and the presence absence of a pull up resistor Data can be read into any input port even if it is in the output mode Port Name reo K Option type Output type Pull up resistor POO to P06 1 bit 1 CMOS Programmable 2 Nch open drain Programmable P10 to P17 1 bit 1 CMOS Programmable 2 Nch open drain Programmable CF1 XT1 No Nch open drain No when general I O port is selected CF2 XT2 No CMOS Nch open drain No when general 1 0 port is selected programmable P70 No Nch open drain Programmable 1 10 LC870G00 Chapter 1 1 9 User Option Table Option Name Option Type Flash Version Option Selected in Units of Option Selection Port output form CMOS POO to PO6 enable 1 bit Nch open drain CMOS P10 to P17 enable 1 bit Nch open drain Program start 00000h or 01E00h address When protected area 1 is Weg selected 00000h When either of protected area 2 3 or 4 is selected Protected area 1 1800h 1FFFh 2 0000h 1DFFh 1F00h 1FFFh Note1 Sg 3 0000h 1CFFh 1FOOh 1FFFh 4 0000h 1AFFh 1F00h 1FFFh Reset pin Internal pullup ON g ON OFF enable OFF Low voltage Enable Use de
170. port pin 3 Port 7 data can always be read regardless of the I O state of the port Address Initial value R W Name BIT7 BIT6 BITS BIT4 BITS BIT2 BIT1 BITO FESC HHHO HHHO R W P7 P70DDR P70DT Register Data Port P70 State P70DDR Input Output Enabled OFF Built in Pull up Resistor ies O page RN o 1 Embed tow or Bits 7 to 5 These bits do not exist They are always read as 1 P7ODDR bit 4 P70 I O control A 1 or 0 in this bit controls the output N channel open drain or input of pin P70 Bit s3 to 1 These bits do not exist They are always read as 1 P70 bit 0 P70 data The value of this bit is output from pin P70 when P70DDR is set to 1 Since this bit is of N channel open drain output type then is placed in the high impedance state when P70 is set to 1 A value of 1 or 0 in this bit turns on and off the internal pull up resistor for pin P70 LC870G00 Chapter 3 3 3 8 2 External interrupt 0 1 control register I01CR See 3 2 3 6 External interrupt 0 1 control register 101CR 3 3 8 3 External interrupt 2 3 control register I23CR See 3 2 3 7 External interrupt 2 3 control register 123CR 3 3 8 4 Input signal select register ISL See 3 2 3 8 Input signal select register ISL The input transistor for the port 7 pin is always on Consequently current will flow into the input transistor when the voltage level at the input pin reaches an inte
171. r 2 diodes at about 60 C is stored in this register Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FEEO XXXX XXXX R W D2TL D2TL7 D2TL6 D2TL5 D2TL4 D2TL3 D2TL2 D2TL1 D2TLO 3 12 4 3 Temperature sensor 60 C 2 diodes reference register H D2TH 8 bit register The upper 4 bit of the result of 12 bit AD conversion VREF2 0V of the reference output voltage level of the sensor 2 diodes at about 60 C is stored in this register Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FEE1 0000 xxxx RW D2TH D2TH7 D2TH6 D2TH5 D2TH4 D2TH3 D2TH2 D2TH1 D2THO 3 12 4 4 Temperature sensor 60 C 4 diodes reference register L D4TL 8 bit register The lower 8 bit of the result of 12 bit AD conversion VREF4 0V of the reference output voltage level of the sensor 4 diodes at about 60 C is stored in this register Address Initial Value R W Name BIT7 BIT6 BITS BIT4 BITS BIT2 BIT1 BITO FEE2 XXXX XXXX R W D4TL D4TL7 D4TL6 D4TL5 D4TL4 D4TL3 D4TL2 D4TL1 D4TLO 3 92 LC870G00 Chapter 3 3 12 4 5 Temperature sensor 60 C 4 diodes reference register H DATH 8 bit register The upper 4 bit of the result of 12 bit AD conversion VREF4 0V of the reference output voltage level of the sensor 4 diodes at about 60 C is stored in this register Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FEE3 0000 xxxx R W D4TH D4TH7 D4TH6 D4TH5 D4TH4 D4TH
172. r Rggs Option selector circuit The option selector circuit is used to configure the LVD options This circuit selects the enable or disable of LVD and its detection level See Subsection 4 6 4 External capacitor Core Pull up resistor Regs After the reset signal from the internal reset circuit is released the reset period is further stretched according to the external CR time constant This enables the microcontroller to avoid the repetitive entries and releases of the reset state from occurring when the power on chatter occurs The circuit configuration shown in Figure 4 6 1 in which the capacitor Crrs and pull up resistor Bar are externally connected is recommended when both POR and LVD functions are to be used The recommended constant values are Cres 0 022 uF and Rres 510 KQ When the disuse of the internal pull up resistor function is selected by option the external pull up resistor Bar must always be installed even when the set s specifications inhibit the installation of the external capacitor Cres 4 31 Internal reset Interior of microcontroller Internal pull up resistor option Rres 51 OkQ Reset Cres 0 022uF Power on reset POR Options Pulse stretcher Low voltage detection reset LVD Figure 4 6 1 Internal Reset Circuit Configuration 4 6 4 Options The POR and LVD options are available for the reset circuit 1 LVD Reset Function Options
173. rmediate level 3 3 4 Options There is no user option for this port 3 3 5 HALT and HOLD Mode Operation The pull up resistor to P70 is turned off PORTS 3 20 3 4 3 4 1 LC870G00 Chapter 3 Timer Counter 0 TO Overview The timer counter 0 TO incorporated in this series of microcontrollers is a 16 bit timer counter that provides the following four functions D 2 3 4 3 4 2 D 2 Mode 0 Two channels of 8 bit programmable timers with a programmable prescaler equipped with an 8 bit capture register Mode 8 bit programmable timer with a programmable prescaler equipped with an 8 bit capture register 8 bit programmable counter equipped with an 8 bit capture register Mode 2 16 bit programmable timer with a programmable prescaler equipped with a 16 bit capture register Mode 3 16 bit programmable counter equipped with a 16 bit capture register Functions Mode 0 Two channels of 8 bit programmable timers with a programmable prescaler equipped with an 8 bit capture register Two independent 8 bit programmable timers TOL and TOH run on the clock with a period of 1 to 256 Tcyc from an 8 bit programmable prescaler The contents of TOL are captured into the capture register TOCAL on an external input detection signal from P70 INTO TOLCP P16 INT2 TOIN P13 and P14 timer OL capture input pins The contents of TOH are captured into the capture register TOCAH on an external input det
174. rnal clock The generator can generate clocks of 2 to 512 Tcyc in modes 0 and 2 and clocks of 8 to 2048 Tcyc in mode 1 3 52 LC870G00 Chapter 3 Table 3 7 1 SIO1 Operations and Operating Modes Bus Master Mode 2 Bus Slave Mode 3 Transmit Receive Transmit Receive Transmit Receive Transmit Receive SI1REC 0 SHREC 1 SHREC 0 SI1REC 1 SMREC 0 SHREC 1 SI1REC 0 SHREC 1 None None Output Input See 1 and 2 Not required Not required See 2 below Low below 8 8 8 All 1s Shift data All 1s c 8 c Input pin Output Input SBUF1 H L bit8 Clock c 9 c c Low output Internal on falling edge of 8th clock Operation start SIIRUNT lt 1 On left 1 On right l Clock side released on falling edge of SIIEND when TIRUN 1 SIIRUN 1 NN bit i d Wah start detected it on rising Shen SIIRUN 0 and SILEND 0 Period 2 to 512 c 8 to 2048 2 to 512Tcyc 2 to 512Tcyc lt Tcyc Tcyc SILRUN Set Instruction Instruction Already set Already set Start bit bit 5 Instruction detected Clear End of lt End of stop 1 Stop c processing bit condition condition detected detected 2 When 2 Ack 1 arbitration detected lost Note 1 SILEND Set End of End of stop lt 1 Rising 1 Falling bit 1 processing bit edge of 9th edge of 8th clock clock 2 Stop 2 Stop condition condition detected detected Continued on next page 3 53 Table 3 7 1 SIO1 Operations and Op
175. s 6 to 5 e High level pulse width data of HPWM2AH 1 x period set by HPWM2AC bit6 to 5 High speed 10 bit fundamental Additional pulse PWM mode HPWM2 operates as a 10 bit PWM by a PWM generator circuit that generates multifrequency 8 bit fundamental PWM waves and a 2 bit additional pulse generator Note 1 Fundamental wave period 256 x period set by HPWM2AC bits 6 to 5 Overall period Fundamental wave period x 4 e High level pulse width HPWM2AH HPWM2AL bits 7 to 6 x period set by HPWM2AC bit6 to 5 Interrupt generation nterrupt request to vector address 0033H is generated at the intervals equal to the fundamental PWM period 8 bit mode or the overall PWM period 10 bit mode if the interrupt request enable bit is set To control high speed PWM2 HPWM2 it is necessary to manipulate the following special function registers e HPWM2AC HPWM2AL HPWM2AH P1 PIDDR PIFCR Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE8D 0000 0000 R W HPWM2AC H2A40MON H2ACKDV H2ACKSL H2ABWSL H2ARUN H2ARLBSY H2AOVF H2AIE Lese Lamae aow remen farne ewen Laser Notel When HPWM2 is not operating HPWM2 output is fixed to high level When HPWM2 is operating as the 8 bit PWM mode and the data of HPWM2AH is FFH HPWM2 output is fixed to high level When HPWM2 is operating as the 10 bit PWM mode and the data of HPWM2AH HPWM2AL bits 7 to 6 is OOOH HPWM2 output is f
176. s set tol the internal low speed RC oscillator circuit continues oscillation in the HALT mode even though the watchdog timer is running with IDLOP 1 and 0 set to 1 or 2 To realize ultra low power operation using the HOLD mode it is necessary to disable the watchdog timer from running in the HOLD mode by setting IDLOP 1 and 0 to 1 or 2 When setting IDLOP 1 and 0 to 1 or 3 several LA of operating current flows at all times because the low speed RC oscillator circuit continues oscillating even in the HOLD mode If the standby mode is entered when the watchdog timer is running with IDLOP 1 and 0 set to 2 the internal low speed RC oscillator circuit stops oscillation and the watchdog timer stops count operation and retains the count value When the CPU subsequently exits the standby mode the low speed RC oscillator circuit resumes oscillation and the watchdog timer starts count operation If the period between the release of the standby mode to the next entry into a standby mode is less than low speed RC oscillation clock x 4 however the low speed RC oscillator circuit may not stop oscillation when the CPU enters the standby mode In such a case the standby mode is on several A of operating current flows because the low speed RC oscillator circuit is active though the watchdog timer is inactive To minimize the standby power requirement of the set code the program so that an interval of low speed RC oscillator clock x 4 or longer b
177. s space the part of the address data addressing outside the 8 bit address space is ignored and the contents of OFE01H B register are placed in the ACC as the result of computation OFF01 H amp OFFH OFEOOH OFEOI 2 11 5 Direct Addressing dst The direct addressing mode allows a RAM or SFR address to be specified directly in an operand In this addressing mode the assembler automatically generates optimum instruction code from the address specified in the operand the number of instruction bytes varies according to the address specified in the operand Long middle range instructions identified by an L M at the end of the mnemonic are available to make the byte count of instructions constant align instructions with the longest one Examples LD 123H Transfers the contents of RAM address 123H to the accumulator 2 byte instruction LDL 123H Transfers the contents of RAM address 123H to the accumulator 3 byte instruction L1 STW 123H Transfers the contents of the BA register pair to RAM address 123H PUSH 123H Saves the contents of RAM address 123H in the stack SUB 123H Subtracts the contents of RAM address 123H from the accumulator DBZ 123H L1 Decrements the contents of RAM address 123H by 1 and causes a branch if Zero 2 8 LC870G00 Chapter 2 2 11 6 ROM Table Look up Addressing The LC870000 series microcontrollers can read 2 byte data into the BA register pair at once using the LDCW instruction Three addr
178. se added system as seen from the figure below the pulse added system is considered better for motor controlling uses lt Overall period Se PWMH PWML 237 Ripple 3 10 4 6 VCPWMO 1 port input register VCPWMO01P 1 This register controls the waveform and the output buffer of VCPWMO 2 This register controls the waveform and the output buffer of VCPWMI Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE85 HHHO 0000 R W VCPWMO1P CPWMOIP2 CPWM1ECK CPWMOECK FIXO FIXO 3 82 LC870G00 Chapter 3 bits 7 to 5 Does not exist always read as 1 CPWM01P2 bit 4 Test bit Must always be set to 0 CPWM1ECK bit 3 When this bit is set to 1 VCPWMI generates waveform of the PWM waves and the system clock CPWMOECK bit 2 When this bit is set to 1 VCPWMO generates waveform of the PWM waves and the system clock bits 1 to 0 Test bit Must always be set to 0 3 83 HPWM2 3 11 High speed PWM2 HPWM2 3 11 1 Overview This series of microcontrollers incorporates high speed 8 12 bit PWM named HPWM2 HPWM2 is made up of a PWM generator circuit that generates multifrequency 8 bit fundamental PWM waves and a 2 bit additional pulse generator 3 11 2 Functions High speed 8 bit fundamental PWM mode HPWM2 operates as an 8 bit PWM by a PWM generator circuit that generates multifrequency 8 bit fundamental PWM waves e Fundamental wave period 256 x period set by HPWM2AC bit
179. sed Note 4 See the notes in paragraph 2 of Subsection 4 6 6 when selecting a POR release level that is lower than the minimum guaranteed operating voltage 1 67V 4 32 LC870A00 Chapter 4 e Selection example 1 Selecting the optimum LVD reset level to keep the microcontroller running without resetting it until VDD falls below 2 7V according to the set s requirements Set the LVD reset function option to Enable and select 2 51V as the LVD reset level Set operating range VDD 2 7V LVD release voltage LVDET LVHYS IA Sek tte pee SS tee LVD reset voltage LVDET Typ 2 51V e Selection example 2 Selecting the optimum LVD reset level that meets the guaranteed operating conditions of VDD 2 7VACYC 250 ns Set the LVD reset function option to Enable and select 2 81V as the LVD reset level option Microcontroller guaranteed operating range LVD release voltage LVDET LVHYS a al a A LVD reset voltage LVDET Typ 2 81V Operation guarantee voltage e Selection example 3 Disabling the internal reset circuit and using an external reset IC that can detect and react at 3 0V see also paragraph 1 of Subsection 4 6 7 Set the LVD reset function option to Disable and select 1 67V as the POR release level option Set operating range VDD 3 1V External 3 0V detection circuit POR release voltage PORRL Typ 1 67V Note 5 The operation guarantee values voltage operating frequency shown in the examples var
180. set flag set 16 bit programmable timer gt Figure 3 5 3 Mode 2 T1LONG 1 T1PWM 0 Block Diagram Clock Clock 1Teyc gt T1L prescaler T1H prescaler Overflow Clear T1H T1PWML output Set Invert T1PWMH output Match buffer register Reload Reload SI e TILCMP TIHCMP T1LR flag set MAR flag set 16 bit programmable timer gt Figure 3 5 4 Mode 3 T1LONG 1 T1PWM 1 Block Diagram Match buffer register 3 38 LC870G00 Chapter 3 3 5 4 Related Registers 3 5 41 Timer 1 control register T1CNT 1 Timer 1 control register is an 8 bit register that controls the operation and interrupts of TIL and T1H Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE18 0000 0000 R W TICNT TIHRUN TILRUN TILONG TIPWM TIHCMP TIHIE TILCMP TILIE T1HRUN bit 7 T1H count control When this bit is set to 0 timer 1 high byte T1H stops on a count value of 0 The match buffer register of T1H has the same value as TIHR When this bit is set to 1 timer 1 high byte T1H performs the required counting operation T1LRUN bit 6 TIL count control When this bit is set to 0 timer 1 low byte TIL stops on a count value of 0 The match buffer register of TIL has the same value as TILR When this bit is set to 1 timer 1 low byte T1L performs the required counting operation
181. stem clock 001 1 2 of frequency of source oscillator selected as system clock 010 1 4 of frequency of source oscillator selected as system clock O11 1 8 of frequency of source oscillator selected as system clock 100 1 16 of frequency of source oscillator selected as system clock 101 1 32 of frequency of source oscillator selected as system clock 110 1 64 of frequency of source oscillator selected as system clock 111 Frequency of source oscillator selected as subclock lt Notes on the use of the clock output feature gt Take notes 1 to 3 given below when using the clock output feature Anomalies may be observed in the waveform of the port clock output if these notes are violated lt 1 gt Do not change the frequency of the clock output when CLKOEN bit 3 is set to 1 gt Do not change the settings of CKODV2 to CKODVO bits 2 0 lt 2 gt Do not change the system clock selection when CLKOEN bit 3 is set to 1 gt Do not change the settings of CLKCB5 and CLKCBA bits 5 and 4 of the OCR register 3 3 PORTS 3 CLKOEN will not go to 0 immediately even when the user executes an instruction that loads the POFCR register with such data that sets the state of CLKOEN from 1 to 0 CLKOEN is set to 0 at the end of the clock that is being output on detection of a falling edge of the clock Accordingly when changing the clock divider setting or changing the system clock selection after setting CLKOEN to 0 with an instruction b
182. subclock or low medium high speed RC because required oscillation stabilization time cannot be secured for the main clock Since the X tal HOLD mode is used usually for low current clock counting less current will be consumed if the system clock is switched to the subclock or low speed RC and the main clock and medium high speed RC oscillators are suspended before the X tal HOLD mode is entered 2 XTIDLE must be cleared with an instruction 3 PDN is cleared when a HOLD mode releasing signal INTO INT1 INT2 INT4 Port 0 interrupt base timer interrupt or CVD interrupt or a reset occurs 4 BitO is automatically set when PDN is set 4 9 System Clock IDLE bit 0 HALT mode setting flag 1 Setting this bit places the microcontroller into the HALT mode 2 This bit is automatically set whenever bit 1 is set 3 This bit is cleared on acceptance of an interrupt request or on receipt of a reset signal Note The oscillation of the low speed RC oscillator circuit is controlled directly by the watchdog timer Its oscillation is also controlled in the standby mode See Section 4 6 Watchdog Timer for details 4 2 4 2 Oscillation Control Register OCR 8 bit register 1 Theoscillation control register is an 8 bit register that selects the system clock division ratio controls the operation of the oscillator circuits selects the system clock and reads data from the CF1 XT1 and CF2 XT2 pins Except for read only bits 3 a
183. t P1FCR FE46 bit6 semp d gt i a P1 FE44 bit6 CMOS D Q i re PME x C EOR P16 LA P1DDR FE45 bit6 pecial inp t FUNCTION bits 5 to 0 P1FCR FEA6 bits 5 to 0 1 ums D P1 FE44 bits 5 to 0 D Q R s Pin Nch OD P15 to P10 FE45 bits 5 to 0 Special input Table of Port 1 Shared Function Special input FUNCTION output P17 INT1 TOHCP HPWM2 output BUZ P16 INT2 TOIN HPWM2 amp comparator output P15 INT3O TOIN ANS P14 INT4 TUN ANG P13 INT4 T1IN AN7 P12 SIO1 clock input SIO1 clock output P11 SIO1 data input SIO1 data output P10 SIO1 data output Port 1 Block Diagram Option Output type CMOS or N channel OD selectable on a bit basis AII 4 LC870G00 APPENDIX I Int request to address 00013 145SL FE4B Lian Timer 1 count clock Timer OL capture signal P14 i i Timer OH capture signal Ports 1 Interrupt Block Diagram AII 5 Port Block Diagrams Bus PU HALT HOLD D P7 FE5C bit 0 Pin D Q q P70 W P7 R P7 DES m C Special inp t Table of Port 7 Shared Function Pon FUNCTION Output P70 INTO TOLCP AN9 pam A Port 7 Block Diagram Option None AII 6 LC870G00 APPENDIX I ISL FE5F INTS dos Noisefiter filter EH Timer 0 clock input Ki 7 Timer OH capture signal gt Int request to address 00013 I23CR FEBE CELLS Int request to address 0001B L INT2 i REI A
184. t is loaded with 55H by any other instruction The internal low speed RC oscillator circuit is started by setting WDTCKSL WDTCNT bit 6 to 0 and WDTRUN WDTCNT bit 5 to 1 Once the oscillator starts oscillation operating current of several uA flows For details refer to the latest SANYO Semiconductor Data Sheet It is noted that the oscillation is also started by setting SRCSTART OCR3 bit 0 to 1 WDT counter WDTCT 17 bit counter 1 Operation start stop Places the CPU into the standby mode when WDTRUN is set to 1 and WDTRUN is set to 0 or when WDTRUN is set to 1 and IDLOP1 and IDLOPO WDTCNT bits 4 and 3 are set to 2 2 Count clock WDT clock selected from the internal low speed RC oscillation clock or subclock 3 Overflow Generated when the WDTCT count value matches the count value designated by WDTSL2 through WDTSLO WDTCNT bits 2 to 0 Generates the WDT reset signal the WDTRUN clear signal and WDTRSTF WDTCNT bit 7 set signal 4 Resetting Setting WDTRUN to 0 or WDTRUN to 1 and executing MOV 55H See WDTCNT instruction Figure 4 6 2 for details on the WDT operation 4 24 LC870G00 Chapter 4 00000000 000 ama 000 mooo omo mo00 como O 0000 0000 Omm 00m 00 000 amo Om 00 000000 Enable To system clock and base timer UUUUU E oscillatio
185. tch buffer register value Counter value I Tm D 1 D 5 S g E g S GS D bes E D gt T G S o i a gt lt 2 z 5 c g z I 2 D a 4 2 5 D ES D o ES E E E E E Mode 3 3 43 3 44 LC870G00 Chapter 3 3 6 Base Timer BT 3 6 1 Overview The base timer BT incorporated in this series of microcontrollers is a 14 bit binary up counter that provides the following five functions 1 Clock timer 2 14 bit binary up counter with a programmable prescaler 3 High speed mode when used as a 6 bit base timer 4 Buzzer output 5 X tal Hold mode release 3 6 2 Functions 1 Clock timer The base timer can count clocks at 0 5 second intervals when a 32 768 kHz subclock is used as the count clock for the base timer One of the four clocks namely cycle clock timer counter 0 prescaler output subclock and low speed RC oscillator clock must be loaded in the input signal select register ISL as the base timer count clock 2 14 bit binary up counter with a programmable prescaler A 14 bit binary up counter can be constructed using an 8 bit binary up counter which runs on the clock output from an 8 bit programmable prescaler and a 6 bit binary up counter These counters can be cleared under program control 3 High speed mode when used as a 6 bit base timer When the base timer is used as a 6 bit timer it can clock at intervals of approximately 2 ms if the 32 768 kHz subclock is used as the count cloc
186. tection reset Detect function enable Disable Not Used SEN Detect level enable 7 level erer Power On reset level enable 1 level function Notel onboard programming inhbited address 1 10 Power Pin Treatment Recommendations VDD1 VSS1 Connect bypass capacitors that meet the following conditions between the Vpp1 and Vss1 pins e Connect among the Vpp and Vss1 pins and bypass capacitors C1 and C2 with the shortest possible heavy lead wires making sure that the impedances between the both pins and the bypass capacitors are as equal as possible L1 L1 L2 L2 e Connect a large capacity capacitor C1 and a small capacity capacitor C2 in parallel The capacitance of C2 should be approximately 0 1 HF L2 L1 C2 L1 L2 VSS1 VDD1 LC870G00 Chapter 2 2 Internal Configuration 2 1 Memory Space This series of microcontrollers has the following three types of memory space 1 Program memory space 256K bytes 128K bytes x 2 banks 2 Internal data memory space 64K bytes 0000H to FDFFH out of 0000H to FFFFH is shared with the stack area 3 External data memory space 16M bytes Address External data memory cle db Ae FFFFFFH 3FFFFH Intermal data Address memory space ROM bank 1 L I I LI I LI I FFFFH i Reserved for 16MB 1 system FF00H i FEFFH SFR 8 bit 1FFFFH bi FEOOH some 9 bit ROM bank 0 CORA TER D ac I 128KB 64 KB 9 bit confi
187. to 0 INT4HEG bit 3 INT4 rising edge detection control INT4LEG bit 2 INTA falling edge detection control INTAHEG INTALEG INT4 Interrupt Conditions Pin Data No edge detected Falling edge detected 0 0 at 1 o Rising eae detected INT4IF bit 1 INT4 interrupt source flag This bit is set when the conditions specified by INT4HEG and INT4LEG are satisfied When this bit and the INT4 interrupt request enable bit INTAIE are set to 1 a HOLD mode reset signal and an interrupt request to vector address 0013H are generated The interrupt flag however cannot be set by a rising edge occurring when INT4 data which is established when the HOLD mode is entered is in the high state or by a falling edge occurring when INT4 data which is established when the HOLD mode is entered is in the low state Consequently to release the HOLD mode with INT4 it is recommended that INT4 be used in the double edge interrupt mode This bit must be cleared with an instruction as it is not cleared automatically INTAIE bit 0 INT4 interrupt request enable When this bit and INT4IF are set to 1 a HOLD mode release signal and an interrupt request to vector address 0013H are generated 3 2 8 5 External interrupt 4 5 pin select register 145SL 1 Theexternal interrupt 4 5 pin select register is an 8 bit register used to select pins for the external interrupts 4 and 5 Address Initial value R W Name BIT7 BIT6 BITS BIT4 BIT3 BIT2 BI
188. to Overall period 3 Teyc programmable in 3 Tome increments 5 Interrupt generation nterrupt requests are generated at the intervals equal to the overall PWM period if the interrupt request enable bit is set 6 Waveform selection VCPWMO VCPWMI can also generate waveform of the PWM waves and the system clock 7 To control VCPWMO and VCPWMI it is necessary to manipulate the following special function registers VCPWMOL VCPWMOH VCPWMIL VCPWMIH VCPWMOC VCPWMOIP Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE80 0000 HHHH R W vcrwmoL CPWMOL3 CPWMOL2 CPWMOL1 CPWMOLO BREET ve 000 mun rw venen orinar ome mmm ommo res bann rw homo formnerJormucerformncoc Fro Fo 3 75 VCPWM 3 10 3 3 10 3 1 D 3 10 3 2 D 2 3 3 10 3 3 1 2 3 10 3 4 1 2 3 3 10 3 5 1 2 3 10 3 6 1 2 Circuit Configuration VCPWMO VCPWM control register VCPWMOC 8 bit register The VCPWMO VCPWMI control register controls the operation and interrupts of VCPWMO and VCPWMI VCPWMO compare register L VCPWMOL 4 bit register The VCPWMO compare register L controls the additional pulses of VCPWMO VCPWMOL is assigned bits 7 to 4 and all of its lower order 4 bits are apparently set to 1 when it is read When the VCPWMO control bit VCPWMOC FE84 bit 2 is set to 0 the output of VCPWMO ternary can be controlled using bits
189. trol The ADC incorporates a reference voltage generator that automatically generates the reference voltage when an AD conversion starts and stops the generation when the conversion ends Accordingly set reset control of reference voltage generation is not necessary Also there is no need to supply reference voltage externally 6 AD conversion reference voltage source select AD conversion reference voltage source can be selected from VDD internal VREF external voltage source See 3 9 Reference Voltage Generator Circuit VREF for the internal VREF 7 Itis necessary to manipulate the following special control registers to control the AD converter ADCRC ADMRC ADRLC ADRHC Initial value BIT7 BIT6 BIT5 BIT4 AD AD AD AD CHSEL3 CHSEL2 CHSELI CHSELO 3 62 0000 0000 LC870G00 Chapter 3 ADRLI 3 63 ADC12 3 8 3 Circuit Configuration 3 8 3 1 AD conversion control circuit 1 The AD conversion control circuit runs in two modes 12 and 8 bit AD conversion modes 3 8 8 Comparator circuit 1 The comparator circuit consists of a comparator that compares the analog input with the reference voltage and a control circuit that controls the reference voltage generator circuit and the conversion result The end of conversion flag ADENDF of the AD control register ADCRC is set when an analog input channel is selected and the AD conversion terminates in the conversion time designated by the conversion time contro
190. uenassaEAusuauuunuanunuascuanasuansanausansuunnauu 4 21 4 4 3 Reset State ssnassnsanusuannsanunuassuansansassusunsauauuauaunanuuasusaunuauuuanuaunauauasanssuuuauu 4 22 iii Contents 45 Watchdog Timer WDT m HH HH Hee 4 23 4 5 1 OVEFVIEW RE 4 23 4 5 2 Functions eee eee eee rere eee ee eee eee eee ee eee eee eee eee ee eee eee ee ee eee eee eee eee ee a 4 23 4 5 3 Circuit Configuration mme 4 24 4 5 4 Related Registers HH 4 26 4 5 5 Using the Watchdog Timer mmmmmmmmmmmmmmHHHeHeee HH 4 28 4 5 6 Notes on the Use of the Watchdog Timer mmm Hmm 4 29 46 Internal Reset Function tetta rann 4 31 4 6 1 OVEFVIEW REEL 4 31 4 6 2 Functions MaaaaaRaauraaranararueseasararuesesanasuenenenssansensuenenusannensenenesuseenens 4 31 4 6 3 Circuit Configuration HH 4 31 4 6 4 Options RA 4 32 4 6 5 Sample Operating Waveforms of the Internal Reset Circuit n 4 34 4 6 6 Notes on the Use of the Internal Reset Circuit 8 4 35 4 6 7 Notes to be Taken When Not Using the Internal Reset Circuit ee 4 37 iv Contents Appendix Special Functions Register SFR Map een Al 1 8 Appendix ll Port Block Diagrams Se EE Ee sese All 1 7 LC870G00 Chapter 1 1 Overview 1 1 Overview The LC870G00 series is an 8 bit microcontroller that centered around a CPU running at a minimum bus cycle time of 83 3 ns integrate on a single chip a number of hardware features such as 8K bytes of flash ROM onboard programmable 256 bytes of RAM a soph
191. undamental Fundamental wave period O wave period 1 wave period 2 wave period 13 wave period 14 wave period 15 Fundamental period 0 signal PWMH PWML 010 PWMH PWML 011 PWMH PWML 012 PWMH lL M 2 PE EE At EE Ir PWML 013 L_JL_JL_IL_ Lo KE y pS PWMH n m M n n8 M n nl M IE 8 f PWML 014 PWMH PWML 015 PWMH PWML 016 PWMH PWML 017 PWMH PWML 018 PWMH PWML 019 PWMH g PWML 01A PWMH PWML 01B PWMH PWML 01C PWMH O PWML 01D PWML 01E d d d J i d A J d PWMH H H H H H 1 H H H z H A e The fundamental wave period is variable within the range of Qon Tcyc Fundamental wave period Value represented by CPWMOC7 to CPWMOCA 1 x 16 Tcyc The overall period can be changed by changing the fundamental wave period The overall period is made up of 16 fundamental wave periods 3 81 VCPWM Examples e Wave comparison when the 12 bit PWM contains 237 H 12 bit register configuration PWMH PWML 237 H 1 Pulse added system this series A Overall period Fundamental A l period signal 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 PWML 237 i 2 Ordinary system Since the ripple component of the integral output in this system is greater than that of the pul
192. uplex 8 data bits 1 stop bit baud rates of 8 to 2048 Tcyc 3 Mode 2 Bus master start bit 8 data bits transfer clock of 2 to 512 Tcyc 4 Mode 3 Bus slave start detection 8 data bits stop detection 3 7 2 Functions I Mode 0 Synchronous 8 bit serial I O Performs 2 or 3 wire synchronous serial communication The clock may be an internal or external clock The clock rate of the internal clock is programmable within the range of 2 to 512 Tcyc 2 Mode 1 Asynchronous serial UART Performs half duplex 8 data bits 1 stop bit asynchronous serial communication The baudrate is programmable within the range of 8 to 2048 Tcyc 3 Mode 2 Bus master e SIOI is used as a bus master controller The start conditions are automatically generated but the stop conditions must be generated by manipulating ports Clock synchronization is used Since it is possible to verify the transfer time bus data at the end of transfer this mode can be combined with mode 3 to provide support for multi master configurations The period of the output clock is programmable within the range of 2 to 512 Tcyc 4 Mode 3 Bus slave e SIOI is used as a slave device of the bus Start stop condition detection processing is performed but the detection of an address match condition and the generation of an acknowledge require program intervention SIOI can generate an interrupt after automatically placing the clock line at the low level on th
193. uspend count operation while retaining the count Standby mode entered Standby mode exited Overflow Low speed RC oscillator Low speed RC oscillator y stopped Note started Note WDTSL2 0 set count value WDTCT Count value 0 Time set in WDTSL2 0 Standby mode time i A WDT operation start WDT reset signal generated WDTRUN 1 WDTRUN cleared to 0 Low speed RC WDTRSTF set to 1 oscillator start Note Low speed RC oscillator stopped Note Oscillation start stop control for low speed RC oscillator circuit is performed when WDTCKSL is set to 0 Note Figure 4 5 2 Sample Watchdog Timer Operation Waveforms 4 5 4 Related Registers 4 5 4 1 WDT control register WDTCNT 1 The WDT control register is used to manipulate the reset detection flag to select the standby mode operation to select the overflow time and to control the operation of the WDT Address Initial value RAW Name BIT7 BIT6 BIT5 BIT4 BITS BIT2 BIT1 BITO FE79 00000000 R W WDTCNT WDTRSTF WDTCKSL WDTRUN IDLOP1 IDLOPO WDTSL2 WDTSLI WDTSLO WDTRSTF bit 7 WDT reset detection flag This bit is cleared when a reset is effected by applying a low level to the external RES pin or using the internal reset POR LVD function This bit is set when a WDT triggered reset occurs This flag can be rewritten with an instruction WDTCKSL bit 6 WDTCT input clock select WDTCKSL WDTCT input clock 0 Internal low speed RC oscillation cloc
194. uzzer output is accomplished by the P17H2ASL HPWM2AL FESE bit1 and the BUZSEL ISL FESF bit 3 P17H2ASL BUZON P17 Pin Data in Output Mode P17DDR 1 HPWM2AL bit1 ISL bit3 0 0 Value of port data latch P17 P16FCR bit 6 P16 function control HPWM2 output control This bit controls the output data at pin P16 When P16 is placed in the output mode PI6DDR 1 and P16FCR is set to 1 the EOR of AND of HPWN2 output data and comparator output and the port data latch data is placed at pin 16 The comparator output is set to 0 when CPON VRCNT bit 5 is set to 1 Consequently when P16 is placed in the output mode P16DDR 1 and P16FCR is set to 1 the EOR of the HPWM2 output and port data latch is placed at pin P16 P16H2ASL CPON P16 Pin Data in Output Mode P16DDR 1 HPWM2AL bito VRCNT bis 0 X Value of port data latch P16 o a Inversion of the above PAN oF PWIND data and comparapor oupa P15FCR bit 5 P15 function control This bit controls the output data at pin P15 When P15 is placed in the output mode P15DDR 1 and P15FCR is set to 1 the value of port data latch is placed at pin 15 P14FCR bit 4 P14 function control This bit controls the output data at pin P14 When P14 is placed in the output mode P14DDR 1 and P14FCR is set to 1 the value of port data latch is placed at pin P14 P13FCR bit 3 P13 function control This bit controls the output data at pin P13
195. vel 2 Having the watchdog timer or LVD function generate a reset 3 Having an interrupt source established at one of the INTO INT1 INT2 and INT4 pins INTO and INTI can be used in the level sense mode only 4 Having an interrupt source established at port 0 e X tal HOLD mode Suspends instruction execution and the operation of the peripheral circuits except the base timer when X tal oscillation or low speed RC oscillation is selected 1 The CF low speed and medium speed RC oscillators automatically stop operation Note The low speed RC oscillator is controlled directly by the watchdog timer its oscillation in the standby mode is also controlled by the watchdog timer Note If the base timer is run with low speed RC oscillation selected as the base timer input clock source and the X tal HOLD mode is entered the low speed RC oscillator retains the state that is established when the X tal HOLD mode is entered 2 The state of crystal oscillation established when the X tal HOLD mode is entered is retained 3 There are five ways of resetting the X tal HOLD mode 1 Setting the reset pin to the low level 2 Having the watchdog timer or LVD function generate a reset 3 Having an interrupt source established at one of the INTO INT1 INT2 and INT4 pins INTO and INTI can be used in the level sense mode only 4 Having an interrupt source established at port 0 5 Having an interrupt source established in the base timer circuit il VCPWM
196. with an instruction 3 39 Ti T1HIE bit 2 T1H interrupt request enable control An interrupt request is generated to vector address 002BH when this bit and TIHCMP are set to 1 T1LCMP bit 1 TIL match flag This flag is set if TIL reaches 0 when TIL is active TILRUN 1 This flag must be cleared with an instruction T1LIE bit 0 TIL interrupt request enable control An interrupt request is generated to vector address 002BH when this bit and TILCMP are set to 1 Note TIHCMP and TILCMP must be cleared to 0 with an instruction 3 5 4 2 Timer 1 prescaler control register T1PRR 1 This register sets up the count values for the timer 1 prescaler 2 When the register value is changed while the timer is running the change is reflected in the prescaler operation at the same timing when the match buffer register for the timer TIL T1H is updated Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BITS BIT2 BIT1 BITO FE19 0000 0000 R W TIPRR TIHPRE TIHPRC2 TIHPRCI TIHPRCO TILPRE TILPRC2 TILPRCI TILPRCO T1HPRE bit 7 Controls the timer 1 prescaler high byte T1HPRC2 bit 6 Controls the timer 1 prescaler high byte T1HPRC1 bit 5 Controls the timer 1 prescaler high byte T1HPRCO bit 4 Controls the timer 1 prescaler high byte TIHPRE TIHPRC2 TIHPRC1 TIHPRCO T1H Prescaler Count 0 zi 1 1 0 0 0 2 1 0 0 1 4 1 0 1 0 8 1 0 1 1 16 1
197. y with the microcontroller type Be sure to see the latest SANYO Semiconductor Data Sheet for details 4 33 Internal reset 4 6 5 Sample Operating Waveforms of the Internal Reset Circuit 1 Waveform observed when only POR is used LVD not used RESET pin Pull up resistor Regs only POR release voltage PORRL E Reset period En Reset period 100ys or longer A Unknown state POUKS RES There exists an unknown state POUKS before the POR transistor starts functioning normally The POR function generates a reset only when power is turned on starting at the VSS level The reset release voltage in this case may have some range Refer to the latest SANYO Semiconductor Data Sheet for details No stable reset will be generated if power is turned on again when the power level does not go down to the VSS level as shown in a If such a case is anticipated use the LVD function together with the POR function as explained in 2 or implement an external reset circuit A reset is generated only when the power level goes down to the VSS level as shown in b and power is turned on again after this condition continues for 100 us or longer 2 Waveform observed when both POR and LVD functions are used RESET pin Pull up resistor Rggs only LVD hysteresis width LVD release voltage LVHYS LVDET LVHYS 1 LVD reset voltage N LVDET 1 1 li o A ns be r
198. y when a low level is applied to the external reset pin a reset by the internal reset function POD LVD occurs or the standby mode is entered when IDLOP 1 to 0 are set to 1 In this case WDTRUN is cleared Clearing the watchdog timer When the watchdog timer starts operation WDTCT counts up When this WDTCT overflows a WDT reset occurs To run the program in the normal mode it is necessary to periodically clear WDTCT before WDTCT overflows Execute the following instruction to clear WDTCT while it is running MOV 55H WDTCNT Detecting a runaway condition Unless the above mentioned instruction is executed WDTCT overflows because the watchdog timer is not cleared If an overflow occurs the watchdog timer considers that a program hangup has occurred and triggers a WDT reset In this case WDTRSTF WDTCNT bit 7 is set After a WDT reset occurs the program execution restarts at address 0000H In the case of flash ROM version the program execution restarts at address selected as an option 4 28 LC870G00 Chapter 4 4 5 6 Notes on the Use of the Watchdog Timer 1 When the internal low speed RC oscillation clock is selected as the WDT clock WDTCKSL 0 O O If the internal low speed RC oscillation clock is not to be used as the system clock set SRCSTART OCR3 bit 0 to 0 the start stop of the internal low speed RC oscillator circuit is also controlled from the watchdog timer side If SRCSTART OCR3 bit 0 i

LC870G00 SERIES USER`S MANUAL

Contents

Download Pdf Manuals

Related Search

Related Contents