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1. Intended Linearity Specifications e 1 SFOR KE ve vat 2 T vour Target SFOR Range 60 569 7 T wu A 1 d Maximum Expected Signal Frequency 40 kHz T L r1 cv equired Vipp 0 2V I ed Peak Vopp 2V mum required slew rate 2 534V us 1 fi Feedback GBP BW Slew Rate Nominal Nominal bos EE Vec Min VecMax 1k MSRP PartNumber Type MHz v us En nV Vec V Is mA V v v Price Description EEE Select 12 42 147 3 6 2 30 2 2 1 4 5 EE Select 13125221 F 18 4 5 s pe Ei Select 13 281212 F 3 s Prec EH Select 15 28190 8 s s 8 3 0 02 3 s s 1 58 Prec ERE Select L8302 s s s 1 09 LowPv EE Select 48103 9 5 5 s s 1 35 Med gt EE Select L8108 F 12 13 Dua EEE Seiect 45103 F 65 VFA 2 si 5 10 ai 12 6 i s d e ae 21 Intersil Proprietary Information April 2010 B nte FS H jas heEWOLUTIONOtANALOG The 2 most important thing is that the Constraints can only be changed if you sitting on the final stage as the active stage This is mainly related to the final output Vpp target That can be updated for the last stage but is then calculated for all previous stages and hence cannot be updated if you are sitting on those earlier stages for amplifier selection purposes While sitting on each stage tab the tool is computing and reporting the implied requirements for that stage These include Bandwidth if the stage is non inverting Since this ca
2. Adjustments Available on the Setup stage Several of these constraints are feeding into the Estimated minimum slew rate required reported on each stage Slew rate is estimated to achieve either an SFDR target or step response without slew limiting The SFDR constraint is a necessary but not sufficient condition to achieve a certain distortion level you might still not get the SFDR with a device offering the reported slew rate but you reduce your chances if the device does not have at least the reported slew rate for that stage Fora step response the tool is looking at the pole locations of that stage and the desired nominal Vopp or Vstep at the output It then computes the peak dV dT to produce that output from an ideal input step and takes 2X that number for a design target Possible op amps to use in each stage use this Slew Rate calculation to constrain the list to op amps that offer at least 9096 of this calculated value e e 24 Intersil Proprietary Information April 2010 B nte FS H lt Picking Suitable Oo Amp Solutions The goal of this Setup page is to pick a suitable op amp that will work in each stage in the design f possible the tool will automatically pick the closest fit as you come into this step but that can be overridden by picking one of the parts listed at the bottom of the screen These are often different devices auto filled in each stage but these can often b
3. Closed loop bandwidth and frequency response peaking under different external conditions Loading effects on closed loop frequency response Input noise terms including 1 f effects Slew rate Input and Output Headroom limits to I O voltage swing Supply current at nominal specified supply voltages Nominal input DC error terms 1 3 of specified data sheet test or specified limits intended to give 10 error term on one polarity Load current reflected into the power supply current 4 Intersil Proprietary Information April 2010 B nte FS i Features not supported by the Macromodels Harmonic distortion effects Composite video differential gain and phase errors Output current limiting if any Disable operation if any Thermal effects and or over temperature parameter variation Limited performance variation vs supply voltage modeled Part to part performance variation due to normal process parameter spread Any performance difference arising from different packaging Multichannel device crosstalk effects e e 8 Intersil Proprietary Information April 2010 B nte FS H lt Enhanced Capability Provi ded by the Tool Semi automatic design flow for multi stage filters Spreads the gain from 1 to 10V V total between the stages and sequences the poles order gt 2 in a way that reduces non linear effects Significantly improved circuit
4. 24 order stages are only complex poles in this tool Q gt 0 5 2 d through 6 order filters supported by the tool built up as a combination of 15t and 2 order stages no 3 order stages Filter Shape describes the pole locations Infinite number of possible combinations of multiple pole locations some standard ones include Butterworth Chebyshev etc Filter Topology describes the op amp implementation to achieve a particular 15 or 2 order set of filter poles Sallen Key is one popular one E y p Proprietary Information April 2010 B nte si i Low Pass Active Hiter Design Range The design tool supports a very wide range of requirements Cuttoff frequencies from 5Hz to 50Mhz 7 decade range Total filter gain from 1 to 10V V in semi automatic design flow but up to 125V V 3 stage design in the manual design flow Filter order from 2 to 6 The filter order from 2 to 6 implies from 1 to 3 amplifier stages Higher order filters tend to require extreme element precision to hit the higher Q targets that come along with orders 6 e e 5 Intersil Proprietary Information April 2010 B nte FS a lt Part ist with New MacroModels Present Feb 2010 table of op amps in the Active Filter Designer sorted by ascending GBP or BW for CFA Part Topology GBP BVVm Nominal Typ Is Min vcc Max vcc Single Dual Quad VFA CFA MHz Total Vcc mA fat vcc With Versions Vers
5. the Design Resources and Tools is the iSim Online Design Simulation Clicking that takes you to gt intersil Available Design Tools under the iSimoption 3 2010 intersil ASim Interactive web design simulation too Currently the isim application tools are broken into Power Management Operational Amplifiers Intersil s iSim is an interactive web based tool for selecting and simulating devices from Switching Raeulstio Active Filter D Me Intersil s broad portfolio Based on input and output specifications provided by the user iSim will Switching Reguladon Active Fiter Designer NEW find all suitable Intersil d s for your application In many cases a simulatio j vailable for immediate feedback on circuit performance Currently iSim is available for Intersil s T a Integrated FET power management devices and operational amplifiers Power Modules NEW Non Inverting Gain aiaiai amps The top Multi Phase Transimpedance Intersil s iSim simulator for power is an applications based Intersil Power Management Solution Selector with dynamic input fields to match your input and output requirements All applicable Isolated DC DC Differential Amplifier Intersil devices vill be listed and those vith a design button are available for online simulation selection n the op When available for simulation a reference schematic will be generated for simulation based on Linear Regulators Instrumentation
6. Amplifier your specifications MOSFET Drivers Single Stage Low Pass Filter Operational Amplifiers am S IS th IS new Intersil s iSim simulator for Operational Amplifiers provides application oriented solution tools Power Supply Support Single Stage High Pass Filter using the broad range of Intersil precision and high speed amplifiers Tools include an Active Filter Designer Inverting gain configuration Non inverting gain configuration Transimpedance t A C tern f eg C lec c Hot Swap Controllers Differential Amplifier Instrumentation Amplifier Single Stage Low Pass Filter and Single Stage High Pass Filter Each tool includes Intersil devices suited to that application along with simulation 1 sequencers models in most cases Taking designer inputs each tool will help you pick the best Intersil amplifier and deliver designs to hit the red performance targets Battery Management LED D i iSim vill filter out only the inputs required for the application group you are interested in Please river i A wists adn select an application from the links on the left to get started Offline LED Driver mv n s n See AN1243 Getting Started with iSim and iSim PE Clicking the Active Filter Designer takes you to iSim is a Trademark of Intersil Americas Inc 2003 2010 Intersil Americas Inc All rights reserved intersil 12 Intersil Proprietary Information April 2010 iSim Active Filter Designer
7. User Log In Compatibility Checks Email Address Login Sf Javascript o SP Pop ups Windows W adobe Flash Player 8 or higher W cookies iSim PE iSim Active Filter Designer Design Verification by Remote Simulation Summary Download Design amp More iSim generates a design report including design summary schematic bill of material and simulation results You may also share your design with other users and or dowmload your schematic to iSim PE Enter your filter design iSim selects and sorts op requirements such as amps suitable to each type order cutoff stage After you have frequency gain etc selected the op amps it Your design is displayed on an online schematic This virtual evaluation platform allows you to test Preview the design with then designs for the R s ideal plots of the gain and C s considering phase and group delay of numerous 2nd order the filter effects the design with simulations for AC Noise and Step Transient analysis e e 13 Intersil Proprietary Information April 2010 f nte FS lt Arst Step in Getting to a Alter Implementation Coming into the tool fresh will give you the first Requirements screen set up to a default condition intersil SOU TUE MEME Requirements MEET NEMPE NEC UE LM M Michael Steffes Logout Give Feedback Filter Designer Design Requirements Select Filter Type Low Pass Select Filter Orde
8. an be saved and then easily emailed around to colleagues customers Download to iSim PE This ports the schematic into a more general purpose simulator where added operations can be performed These include MonteCarlo simulations re ordering the stages converting it to a single supply design etc e e 34 Intersil Proprietary Information April 2010 B nte FS a lt heEWOLUTIONOtANALOG Full User s manual added March 2010 Designer s Manual for the iSim Active Filter Designer AN1548 Additional parts will be easily added to the tool as they become available new parts or as needed older parts not currently included Op Amps in the tool have totally updated upgraded Spice Macromodels Next addition will be the High Pass Filter flow followed by the BandPass Filter flow during 2010 If you use the tool and find an issue please try to re create it keeping track of exactly how you got to that point and report it using the Feedback option It is also helpful to save the design and share it Intersil Proprietary Information April 2010 nte rsi D o
9. andaQ x 2 E E n amp Q and gain for each stage E FO Hz Q gt P ah Stage sooo fi 3 Ge gt Stage2 scoco Es E X N Wl Update Preview L3 Continue i N 0000 100000 06 0 Frequency intersi 19 Intersil Proprietary Information April 2010 B m e Si I jee _ heEWOLUTIONOIANALOG Hitting Continue from the Requirements page will go the Setup page where numerous implementation parameters are considered and available for modification This step starts out with some default assumptions This is where the real work begins in matching op amps to the desired filter implementations For multi stage filters the most important thing to notice on this next screen is which stage is active in the setup screen This is the red color on the Stage tab It comes into this step with the last stage as the default active stage This is where the design constraints can be updated Those also default to the values shown on the next slide but can be modified amp Intersil Proprietary Information April 2010 H nte rsi Setting up the Design The main goal for this step is to pick the right op amps for eac stage given the topology filter targets and constraints Antersil Michael Steffes Logout Give Feedback Filter Designer Staget Stage FO 50 kHz Q Topology Sallen Ke Staget Stage Total Supply Voltage F Max Vopp at Last Stage Output E
10. e made the same device with a little effort Changing the supply voltage will typically show a completely different set of op amps Forinstance going to 10V total supply with 6Vpp output will show the following screen hit the Apply key after you update the supply voltage and output swing fields e e 25 Intersil Proprietary Information April 2010 B nte FS a lt Modifying the Constraints gives new part choices More CFA parts show up here as the prior setting of 5V supply and 2Vpp output violated the 1 6V headroom on those parts intersil 26 intersil 27 N The part choices are sorted by minimally acceptable to increasing design margin to the requirements The top device in the table generated for each stage is deemed minimally suitable and is the default part filled into the top boxes Going down the list gives more design margin This step requires a device selection for each stage before the next step hitting Design At any time you can change a stage to inverting which then constrains the solution op amps to be VFA since CFA devices cannot easily be applied to the those topologies The Setup and design process works in gain magnitudes but it does report if the overall filter is inverting or non inverting amp Intersil Proprietary Information April 2010 H nte rsi Picking Suitable Oo Amp Solutions To summarize the computed minimum requirements fo
11. he pole locations from here or the shape description to use in the iSim Active Filter Designer Filter Wiz PRO http www schematica com filter wiz files FWPRO htm Exact pole locations and advanced features may require you to purchase the full version e e 16 Intersil Proprietary Information April 2010 B nte rsi lt AC Response Preview From whatever settings are used in the upper section of the Requirements screen hitting Update Preview will generate the ideal Gain Phase and Group delay These are used later to compare to the actual circuit level implementation Here is the screen after hitting Update Preview intersil Cum Requirements Setup Design DesignSummary MyDesigns Michael Steffes Logout Give Feedback Filter Designer esign ements Select Filter Type Low Pass z z Select Filter Order 4 x o Enter Poles Manuaily yz Cyes o Filter Cutoff Frequency sc kHz Phase deg GroupDelay us e e 17 Intersil Proprietary Information April 2010 B nte rsi lt heEWOLUTIONOtANALOG 1 Semi Automatic flow is where you want to use some of the pre loaded filter shapes and let the tool do most of the work for you This is the default mode and is what is shown on first entering the tool This flow also decides for you the sequence of poles order gt 2 and how to imp
12. iSim Active Filter Designer Design Design Verification Summary Requirements by Remote Download Design Interview Simulation amp More intersil theEMOLUTIONotANALOG Intersil Propreitary Information Introduction to the New Active Filter Designer Scope and Intent Getting into the tool Two Primary Design Flows Semi automatic design User specified poles and gains for each stage From design targets pick op amps simulate and save share features Example Designs Future plans for the tool e e Intersil Proprietary Information April 2010 B nte FS H lt Scope and Intent of the Active Alter Designer Intent is to deliver working designs using Intersil s Precision and High Speed Op amps Basic filter types that will be supported Low Pass High Pass Bandpass Notch filters are not anticipated have seen those occasionally but the required external component precision precludes widespread application The list above will be the rollout sequence Low pass filter designs are available at this initial Feb 2010 e e 3 re lease Intersil Proprietary Information April 2010 R nte FS H il Important Termi nology Filter Type is the highest level classification Low Pass High Pass Notch Bandpass Allpass etc Filter Order is the number of poles in the transfer function fstorder is just a single energy storage element like an RC filter
13. implementations Noise effects considered and reduced if possible 2 order issues in the feedback and gain setting elements considered loading noise BW phase margin Resistor solutions adjusted to account for amplifier bandwidth effects to hit the desired pole locations more precisely This also allows reduced amplifier bandwidth vs target Fo design margin than any currently available design tools e 9 Intersil Proprietary Information April 2010 B nte FS a lt Some Connon Misconceptions about Active Filters The Active Filter Designer includes numerous features that might appear to violate some widespread myths Current feedback amplifiers CFA s cannot be used in active filters They are in fact very suitable as wideband gain blocks if that is what is needed in the filter stage Cannot be used easily with reactive feedback type topologies such as the MFB or infinite gain circuit Gain of 1 is required for the active filters or low gain The gain is a design variable and can be accounted for in setting the R s and C s Butit does interact strongly with the amplifier bandwidth if VFA devices are used and this is also accounted for in the design algorithms provided in the tool Equal R or Equal C designs are required or desirable This comes from simplified academic developments or where the text is headed towards integrated solutions close cap ratio s desirable for
14. integrated filters Not really a required constraint for discrete E T J Intersil aa a ae April 2010 B nte FS imolementations SSE 11 lt ac intersil Hon Produc Design Assi English BAR Japanese MAPX Chinese amp Korean Application Order The Evolution of Analog Product Families Amplfiers Buffers ATE ICs Automolive ICs Communications ICs D2Audio Audio ICs Data Converters Digital Potentiometers DCPs Digital ICs Display ICs Interface ICs Optoelectronics Power Management Power Modules Precision Analog Quellan Signal Integrity Products Space Defense Design Resources and Tirels iSim Online Design Simulation Application Support Ask Our Staff Application Notes Technical Briefs FAQ Knowledge Base Review My Questions Application Block Diagrams Design Models Technical Documentation Engineering Resources Packaging Information Parametric Search Product Cross Reference Product Trees Quality and Reliability He omp Sales and Ordering Buy Direct from Intersil Distributor Stock Check Order Samples Pricing Leadtime Status Product Cross Reference Product Selection Guide Product Status RoHS Pb Free Green Sales Support Intersil Proprietary Information April 2010 Intersil at a Glance Investor Relations Locations and Operations Press Room Stock Chart Stock Quote Subscribe View Cart ch y Currently the top listing under
15. ions Disable ISL28194 VFA 0 0035 5 0 00033 1 8 5 5 SL28194 ISL28195 VFA 0 01 5 0 001 1 6 5 5 SL28195 IsL28158 YFA 0 2 5 0 034 2 4 5 5 1S5L26158 ISL28258 ISL28156 VFA 0 25 5 0 039 2 4 5 5 SL28156 ISL28256 ISL28133 WFA 0 4 5 0 016 2 5 5 ISL28233 ISL26433 EL8176 WFA 0 4 5 0 055 2 4 5 5 EL8176 ISL28275 ISL26476 ISL26107 WFA 1 3 0 21 4 5 40 ISL28207 ISL28117 VFA 1 5 30 0 44 4 5 40 ISL28217 ISL28113 vFA 2 5 0 09 1 6 5 5 ISL26213 ISL28413 ISL28136 VFA 5 1 5 0 9 2 4 5 5 SL28136 ISL28235 ISL28114 VFA 7 7 5 0 4 1 8 55 ISL28214 ISL28414 ISL26127 VFA 10 30 2 2 4 5 40 ISL26227 ISL24021 VFA 15 10 2 4 5 18 ISL26191 VFA 61 5 2 6 3 5 5 SL28181 ISL28291 ISL55001 FA 58 3 9 8 30 ISL55002 ISL28190 VFA 83 3 5 8 5 3 5 5 SL28180 ISL28290 EL8101 WFA 106 5 2 3 5 5 EL8100 EL8201 EL8401 EL5103 WFA 155 10 5 5 12 6 EL5102 EL5203 EL5101 WFA 170 10 2 5 5 12 6 EL5100 ELB103 WFA 198 5 5 6 4 5 5 EL8102 EL5105 VFA 264 10 5 5 12 6 EL5104 EL5205 EL5161 CFA 95 10 0 75 5 12 6 EL5160 EL5261 EL5163 CFA 140 10 1 5 5 12 5 EL5162 EL5263 EL5108 CFA 190 12 14 3 4 5 13 EL8108 EL5165 CFA 370 10 5 5 12 6 EL5164 EL5167 CFA 620 10 8 5 5 12 6 EL5166 gt e 6 Intersil Proprietary Information April 2010 nte FS H lt Feature set for the New Upgraded Macromodels Typical room temp nominal power supply voltages used to produce the following characteristics Open and closed loop I O impedances Open loop gain and phase
16. lement the total target gain It is essentially sequencing from high to low Q stages in low to higher gains in those stages in going from input to output 2 Manual Pole selection is where you have some specific pole locations you wish to implement and want to enter those directly This also allows you to select the Frequencies Gains and Q s over a wider range than the semi automatic path This is all selected in the row that asks Enter Poles Manually This defaults to No but clicking Yes changes this screen to accept user entry for each stage The order setting still sets the number of stages and an odd order 3 or 5 forces the real pole to be the last stage amp 18 Intersil Proprietary Information April 2010 H nte FSI Manual Pole Entry Option Here the entry screen has been changed by clicking Yes on the Enter Poles Manually line and we have changed the gain in each stage to 10 giving an overall filter gain of 100 10 in each stage is the maximum for 2 stage designs and manually set the Q s to get a 4 order Butterworth shape then hit Update Preview again Hitting the Continue key from here gt intersil D TEMME MEE Requirements EESTI NEM T NEM C EESTI III Filter Designer ts Low Pass Select Filter Order sz Enter Poles Manually y G ves C tio E mug co be foe m E Pass Band Gain v v z Entar f Fo
17. n be either a VFA or CFA op amp gain bandwidth is not used in this line So taking the required BW number times the stage gain will give you the required GainBandwidth Product if you want to use a VFA op amp in this stage f you change the stage to be inverting only VFA devices can be used and this computation reports the required Gain Bandwidth Product GBP amp Intersil Proprietary Information April 2010 H nte FS Adjustments Available on the Setup stage On any given stage you can change the topology from non inverting default to inverting and that immediately updates the recommended amplifier list at the bottom this is the only thing that can be changed when you are sitting on earlier stages Sitting on the last stage you can change the following global constraints Desired total supply voltage range here is 1 8V to 40V This supply voltage is assumed to be the same for all stages Maximum final stage Output Swing Vpp limited to be from 10 to 90 of Vs Linearity Target either SFDR if frequency domain or Step if step response f SFDR also asks for maximum expected frequency and desired distortion range Resistor tolerance exact 0 596 196 or 296 This effects the filter accuracy in that exact R solutions might be snapped to available values probably shifting the achieved filter shape off somewhat e e 23 Intersil Proprietary Information April 2010 B nte FS a lt
18. ons at the top Hitting the AC tab will run an AC simulation Antersil Filter Analysis schematic Configure L3 noise L3Ac D transient R1 52 R2 S2 3 4 20 0k Q Devices Selected and Alternate Versions Stagei Stage2 Device Sel Stege S 2 s 30 Intersil Proprietary Information April 2010 S y ON BY J simetrix intersil Qutput of the ACsimul ation key Clicking on the Filter AC Output opens a waveform viewer where we can add the Ideal Gain Phase and Group Delay Doing that intersil Me Design MESI ET me Ie Michael Steffes Logout Give Feedback Filter Analysis waveforms Current Design not saved rn E AC Results AC Output S1 Filter AC Output Ej Cu 30 004 GroupOx Phase 204 sin Si 004 8 7 104 i 1 004 gt gt J amp 0 X 3 o 3 s5 z a o 5 a a a i 1 3 9 4 1 5004 amp S di rc o 1 204 24 4 140 304 T 1 17 10000 100000 1e 06 1e 07 Frequency Hz All AC Outputs 1 12 10 gt amp 20 e a 50 N 4 S 00 80 N 600 110 x om ee 0 00 40 F 2 800 170 r 10000 100000 1e 06 Te 07 31 Intersil Proprietary Information April 2010 nte FS H CEN Comparison of Actual to Ideal AC Response This viewer also has two cursors that can be moved and a zoom in feature Here we see very good overall fit for the simulated filter response v
19. r 4 Enter Poles Manually C yes 9 No Filter Cutoff Frequency s kHz Pass Band Gain V V E _ Filter Shape Butterworth This filter shape offers the flattest passband gain response at Wl Update Preview 3 Continue the expense of relatively slow rolloff in the transition region There are no gain ripples in either the passband or stopband region The step response does show some overshoot that increases with filter order Fade Feutoff e e 14 Intersil Proprietary Information April 2010 B nte rsi lt T heEWOLUTIONOtANALOG Many vendor tools provide some filter shape help as an early step in their tools This is used to arrive at a desired filter order and pole locations to hit a particular skirt shape how fast the cutoff band rolls off Usually this is specified in terms of stop band attenuation at a certain frequency above the desired passband The Active Filter Designer assumes you already know the target shape and or the approximate order or filter poles you want to implement The tool mainly works on getting the right op amp selected and design implemented in a way the will yield a successful board level implementation amp Intersil Proprietary Information April 2010 H nte rsi The Tool is Mainly an Implementation Aid If you need help deciding on the filter shape try this web site free download that has a lot of filter shape design tools just need to get t
20. r each stage shown on this screen include Bandwidth if the stage in non inverting Gain Bandwidth Product if inverting Slew rate Maximum Vopp including any step overshoot or frequency response peaking Maximum input Vipp These terms are used to constrain and sort the table of op amp selections to parts that Can operate at the specified total supply voltage Will not clip given that supply voltage and output swing including any peaking or step overshoot effects considering the output headroom of each device Provides at least 9096 of the computed BW and slew rate Will not limit on the input given the supply voltage and input headroom limits of each device considered e e 28 Intersil Proprietary Information April 2010 B nte FS H lt Executing the Design Once we have design targets for each stage and an op amp selected hitting the Design key will go off and compute the R s and C s for each stage and come back with a completed design At that point the total specified supply is split into Vs 2 halves and the design is shown as a DC coupled ground centered signal swing implementation Hitting Design from the previous screen 10V supply 6V output swing gives the following active filter design e e 29 Intersil Proprietary Information April 2010 B nte FS a lt Example Design Output Page Note the related parts at the bottom and the simulation opti
21. s ideal Note the 40dB gain at low frequencies WebScope 0 G amp iE AC Output S1 Filter AC Output All AC Outputs 32 Intersil Proprietary Information April 2010 Design Summary and Saving Sharing Options Going back to the Filter tool from the waveform viewer and clicking Design Summary will give the following screen intersil mum E 08Q a esis Stage Stage2 0000 Steget Stege so ain Q polo ect t2 ema C151 c1 s2 in F 40p F i RIS R2 51 15128127 R152 R2 s2 1 124021 pO a ti i vin a lt 4a 3 lt m dm vo II r5 c2 S81 al c2 s2 T t L tr Jv mv ot c RF RF S2 RG S1 5762 RG_S2 348k Q e 340 33 Q e Intersil Proprietary Information April 2010 B nte FS H lt 33 Design Summary and Saving Sharing Options This summarizes the overall targets the constraints and the final circuit design Down below on this screen are the BOM the AC Transient and or noise sims that have been done Mostimportantly in the upper right are 3 paths to go on from here Save the design the little floppy icon This saves the design locally in your filter tool folder so you open it up and work on it later Once saved you can also share the design by emailing it from the Saved Designs tab Download to PDF This takes the design summary and creates a pdf version that c

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